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1.05M
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`timescale 1ns/100ps
module Combiner(
input clk,
input signed [15:0] din,
//input mode,
input integ,
input bypass,
//input [9:0] gateEnd,
//(* equivalent_register_removal = "no" *) output reg signed [15:0] dout = 16'h0000
output signed [15:0] dout
);
`include "bits_to_fit.v"
//parameter real CLK_FREQ = 192e6; // SiS digitisers - 192 MHz
parameter real CLK_FREQ = 357e6; // FONT5A board - 357 MHz
parameter real SUB_PULSE_LENGTH = 280e-9; // Factor 4 - 280 ns sub-pulse length
//localparam integer COMB_FACT = 4; // Factor 4 combination
localparam integer SUB_PULSE_CNT_SIZE = bits_to_fit(CLK_FREQ * SUB_PULSE_LENGTH);
//localparam SUB_PULSE_CNT_SIZE = $clog2(CLK_FREQ * SUB_PULSE_LENGTH + 1); //NB: Icarus verilog understand the clog2 system CUF but not user functions!!!
//localparam [SUB_PULSE_CNT_SIZE-1:0] SUB_PULSE_CNT = CLK_FREQ * SUB_PULSE_LENGTH;
//reg [SUB_PULSE_CNT_SIZE-1:0] subPulseCtr = {SUB_PULSE_CNT_SIZE{1'b0}};
//parameter SRL_SIZE = 64;
localparam [SUB_PULSE_CNT_SIZE-1:0] SRL_SIZE = (CLK_FREQ * SUB_PULSE_LENGTH);
reg signed [17:0] dsh [0:SRL_SIZE-1]; // 18-bits necessary for Factor 4 combination //
integer i, n;
initial for (i=0; i < SRL_SIZE; i=i+1) dsh[i] = 18'h00000;
//MUXY for uncombined beam
wire signed [17:0] din_mux = (bypass) ? {din, 2'b00} : {{2{din[15]}}, din} + dsh[SRL_SIZE-1];
always @(posedge clk) begin
/* if (intergrating) begin //ACC/CLR !!
dsh[0] <= din + dsh[SRL_SIZE-1];
for (n=SRL_SIZE-1; n > 0; n=n-1) dsh[n] <= dsh[n-1];
end else begin
for (n=SRL_SIZE-1; n > 0; n=n-1) dsh[n] <= 20'h0; // not synthesisible, must shift-in the zero
dout <= dsh[SRL_SIZE-1]; */
//Begin combiner unit
/*
dout <= (bypass) ? din : dsh[SRL_SIZE-1];
dsh[0] <= (integ) ? din + dsh[SRL_SIZE-1] : 20'h0; //control (integ) must be set to correct sample range
for (n=SRL_SIZE-1; n > 0; n=n-1) dsh[n] <= dsh[n-1]; */
//End combiner
//NO THIS iS WRONG, output needs to be din + dsh
//dout <= (bypass) ? din : din + dsh[SRL_SIZE-1];
dsh[0] <= (integ) ? din_mux : 18'h00000; // MUXY to clear SR when not interleaving
//dsh[0] <= (bypass) ? {din, 2'b00} : {{2{din[15]}}, din} + dsh[SRL_SIZE-1]; //MUXY for uncombined beam
for (n=SRL_SIZE-1; n > 0; n=n-1) dsh[n] <= dsh[n-1]; // Implement Shift Rgegister
//dout <= dsh[0][17:2]; // Bit-select top 16 bits and present on output
end
assign dout = dsh[1][17:2];
endmodule
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
//include "registers.v"
module router_op_lut_regs_cntr
#(
parameter UDP_REG_SRC_WIDTH = 2
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
// --- interface to op_lut_process_sm
input pkt_sent_from_cpu, // pulsed: we've sent a pkt from the CPU
input pkt_sent_to_cpu_options_ver, // pulsed: we've sent a pkt to the CPU coz it has options/bad version
input pkt_sent_to_cpu_bad_ttl, // pulsed: sent a pkt to the CPU coz the TTL is 1 or 0
input pkt_sent_to_cpu_dest_ip_hit, // pulsed: sent a pkt to the CPU coz it has hit in the destination ip filter list
input pkt_forwarded, // pulsed: forwarded pkt to the destination port
input pkt_dropped_checksum, // pulsed: dropped pkt coz bad checksum
input pkt_sent_to_cpu_non_ip, // pulsed: sent pkt to cpu coz it's not IP
input pkt_sent_to_cpu_arp_miss, // pulsed: sent pkt to cpu coz we didn't find arp entry for next hop ip
input pkt_sent_to_cpu_lpm_miss, // pulsed: sent pkt to cpu coz we didn't find lpm entry for destination ip
input pkt_dropped_wrong_dst_mac, // pulsed: dropped pkt not destined to us
input clk,
input reset
);
// ------------- Internal parameters --------------
localparam NUM_REGS_USED = 10;
// ------------- Wires/reg ------------------
wire [NUM_REGS_USED-1:0] updates;
// -------------- Logic --------------------
generic_cntr_regs
#(
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.TAG (`ROUTER_OP_LUT_BLOCK_ADDR), // Tag to match against
.REG_ADDR_WIDTH (`ROUTER_OP_LUT_REG_ADDR_WIDTH),// Width of block addresses
.NUM_REGS_USED (NUM_REGS_USED), // How many registers
.INPUT_WIDTH (1), // Width of each update request
.MIN_UPDATE_INTERVAL (8), // Clocks between successive inputs
.REG_WIDTH (`CPCI_NF2_DATA_WIDTH), // How wide should each counter be?
.RESET_ON_READ (0)
) generic_cntr_regs (
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
.reg_req_out (reg_req_out),
.reg_ack_out (reg_ack_out),
.reg_rd_wr_L_out (reg_rd_wr_L_out),
.reg_addr_out (reg_addr_out),
.reg_data_out (reg_data_out),
.reg_src_out (reg_src_out),
// --- update interface
.updates (updates),
.decrement ('h0),
.clk (clk),
.reset (reset)
);
assign updates[`ROUTER_OP_LUT_ARP_NUM_MISSES] = pkt_sent_to_cpu_arp_miss;
assign updates[`ROUTER_OP_LUT_LPM_NUM_MISSES] = pkt_sent_to_cpu_lpm_miss;
assign updates[`ROUTER_OP_LUT_NUM_CPU_PKTS_SENT] = pkt_sent_from_cpu;
assign updates[`ROUTER_OP_LUT_NUM_BAD_OPTS_VER] = pkt_sent_to_cpu_options_ver;
assign updates[`ROUTER_OP_LUT_NUM_BAD_CHKSUMS] = pkt_dropped_checksum;
assign updates[`ROUTER_OP_LUT_NUM_BAD_TTLS] = pkt_sent_to_cpu_bad_ttl;
assign updates[`ROUTER_OP_LUT_NUM_NON_IP_RCVD] = pkt_sent_to_cpu_non_ip;
assign updates[`ROUTER_OP_LUT_NUM_PKTS_FORWARDED] = pkt_forwarded;
assign updates[`ROUTER_OP_LUT_NUM_WRONG_DEST] = pkt_dropped_wrong_dst_mac;
assign updates[`ROUTER_OP_LUT_NUM_FILTERED_PKTS] = pkt_sent_to_cpu_dest_ip_hit;
endmodule
|
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ([email protected])
//
// Copyright (c) 2004 Guy Hutchison ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// Negative-edge based wrapper allows memory wait_n signal to work
// correctly without resorting to asynchronous logic.
module tv80a (/*AUTOARG*/
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
// Inputs
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
);
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter T2Write = 1; // 1 => wr_n active in T3, 0 => wr_n active in T2
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
input reset_n;
input clk;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] di;
output [7:0] dout;
reg mreq_n;
reg iorq_n;
reg rd_n;
reg wr_n;
wire cen;
wire intcycle_n;
wire no_read;
wire write;
wire iorq;
reg [7:0] di_reg;
wire [6:0] mcycle;
wire [6:0] tstate;
assign cen = 1;
tv80_core #(Mode, IOWait) i_tv80_core
(
.cen (cen),
.m1_n (m1_n),
.iorq (iorq),
.no_read (no_read),
.write (write),
.rfsh_n (rfsh_n),
.halt_n (halt_n),
.wait_n (wait_n),
.int_n (int_n),
.nmi_n (nmi_n),
.reset_n (reset_n),
.busrq_n (busrq_n),
.busak_n (busak_n),
.clk (clk),
.IntE (),
.stop (),
.A (A),
.dinst (di),
.di (di_reg),
.dout (dout),
.mc (mcycle),
.ts (tstate),
.intcycle_n (intcycle_n)
);
reg [6:0] tstate_r = 7'h00;
reg [6:0] tstate_rr = 7'h00;
always @(negedge clk) begin
tstate_r <= tstate;
end
always @(posedge clk) begin
tstate_rr <= tstate;
end
wire mreq_read = ~iorq & ~no_read & ~write;
wire mreq_write = ~iorq & ~no_read & write;
wire iorq_read = iorq & ~no_read & ~write;
wire iorq_write = iorq & ~no_read & write;
always @* begin
mreq_n = 1;
rd_n = 1;
iorq_n = 1;
wr_n = 1;
if (mcycle[0]) begin
if (intcycle_n == 1'b1) begin
if (tstate_r[1] || tstate[2]) begin
mreq_n = 1'b0;
rd_n = 1'b0;
end
else if (rfsh_n == 1'b0 && tstate_r[3]) begin
mreq_n = 1'b0;
end
end
else begin
if (tstate[2]) begin
iorq_n = 1'b0;
end
end
end
else begin
if (mreq_read == 1'b1) begin
if (tstate_r[1] || tstate_r[2]) begin
mreq_n = 1'b0;
rd_n = 1'b0;
end
end
else if (mreq_write == 1'b1) begin
if (tstate_r[1] || tstate_r[2]) begin
mreq_n = 1'b0;
if (tstate_r[2]) begin
wr_n = 1'b0;
end
end
end
else if (iorq_read == 1'b1) begin
if (tstate_rr[1] || tstate_r[2]) begin
iorq_n = 1'b0;
rd_n = 1'b0;
end
end
else if (iorq_write == 1'b1) begin
if (tstate_rr[1] || tstate_r[2]) begin
iorq_n = 1'b0;
wr_n = 1'b0;
end
end
end
end
always @(posedge clk) begin
if (!reset_n) begin
di_reg <= #1 0;
end
else begin
if (tstate[2] && wait_n == 1'b1)
di_reg <= #1 di;
end // else: !if(!reset_n)
end // always @ (posedge clk)
endmodule // t80n
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
// Date : Tue Oct 18 17:47:49 2016
// Host : chinook.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.2 (Maipo)
// Command : write_verilog -force -mode synth_stub
// /afs/ece.cmu.edu/usr/jacobwei/Public/FPGA/FPGA.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.v
// Design : blk_mem_gen_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2015.2" *)
module blk_mem_gen_0(clka, wea, addra, dina, clkb, addrb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[18:0],dina[3:0],clkb,addrb[18:0],doutb[3:0]" */;
input clka;
input [0:0]wea;
input [18:0]addra;
input [3:0]dina;
input clkb;
input [18:0]addrb;
output [3:0]doutb;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_jbi_sc1_1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ff_jbi_sc1_1(/*AUTOARG*/
// Outputs
jbi_sctag_req_d1, scbuf_jbi_data_d1, jbi_scbuf_ecc_d1,
jbi_sctag_req_vld_d1, scbuf_jbi_ctag_vld_d1, scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1, sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1, so,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req, rclk, si, se
);
output [31:0] jbi_sctag_req_d1;
output [31:0] scbuf_jbi_data_d1;
output [6:0] jbi_scbuf_ecc_d1;
output jbi_sctag_req_vld_d1;
output scbuf_jbi_ctag_vld_d1;
output scbuf_jbi_ue_err_d1;
output sctag_jbi_iq_dequeue_d1;
output sctag_jbi_wib_dequeue_d1;
output sctag_jbi_por_req_d1;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
input rclk;
input si, se;
output so;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
dff_s #(32) ff_flop_row0 (.q(jbi_sctag_req_d1[31:0]),
.din(jbi_sctag_req[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_flop_row1 (.q(scbuf_jbi_data_d1[31:0]),
.din(scbuf_jbi_data[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(13) ff_flop_row2 (.q({ jbi_scbuf_ecc_d1[6:0],
jbi_sctag_req_vld_d1,
scbuf_jbi_ctag_vld_d1,
scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1,
sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1}),
.din({ jbi_scbuf_ecc[6:0],
jbi_sctag_req_vld,
scbuf_jbi_ctag_vld,
scbuf_jbi_ue_err,
sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue,
sctag_jbi_por_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Flag synchronizer from clock domain 0 to 1
* See http://www.fpga4fun.com/CrossClockDomain.html
*/
module aceusb_sync(
input clk0,
input flagi,
input clk1,
output flago
);
/* Turn the flag into a level change */
reg toggle;
initial toggle = 1'b0;
always @(posedge clk0)
if(flagi) toggle <= ~toggle;
/* Synchronize the level change to clk1.
* We add a third flip-flop to be able to detect level changes. */
reg [2:0] sync;
initial sync = 3'b000;
always @(posedge clk1)
sync <= {sync[1:0], toggle};
/* Recreate the flag from the level change into the clk1 domain */
assign flago = sync[2] ^ sync[1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FILL_1_V
`define SKY130_FD_SC_LP__FILL_1_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fill_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fill_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__FILL_1_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module video_scaler_mul_jbC_MulnS_0(clk, ce, a, b, p);
input clk;
input ce;
input[32 - 1 : 0] a;
input[16 - 1 : 0] b;
output[32 - 1 : 0] p;
reg signed [32 - 1 : 0] a_reg0;
reg signed [16 - 1 : 0] b_reg0;
wire signed [32 - 1 : 0] tmp_product;
reg signed [32 - 1 : 0] buff0;
assign p = buff0;
assign tmp_product = a_reg0 * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module video_scaler_mul_jbC(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
video_scaler_mul_jbC_MulnS_0 video_scaler_mul_jbC_MulnS_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* VC allocator
* Allocates new virtual-channels for newly arrived packets.
*
* "unrestricted" VC allocation (Peh/Dally style)
*
* Takes place in two stages:
*
* stage 1. ** VC Selection **
* Each waiting packet determines which VC it will request.
* (v:1 arbitration). Can support VC alloc. mask here (from
* packet header or static or dynamic..)
*
*
* stage 2. ** VC Allocation **
* Access to each output VC is arbitrated (PV x PV:1 arbiters)
*
*/
//
// ** THIS IS NOT USED ** only for hacking at present.... (*:
//
`include "types.v"
function automatic logic[15:0] NW_vc_sel_mask (input flit_t f);
begin
case (f.control.output_port)
`port5id_tile:
begin
NW_vc_sel_mask='1;
end
`port5id_north:
begin
// north next too
if (f.control.y_disp+1<0) begin
NW_vc_sel_mask=4'b0011;
end else begin
NW_vc_sel_mask=4'b1100;
end
end
`port5id_east:
begin
// east next too
if (f.control.x_disp-1>0) begin
NW_vc_sel_mask=4'b0011;
end else begin
NW_vc_sel_mask=4'b1100;
end
end
`port5id_south:
begin
// south next too
if (f.control.y_disp-1>0) begin
NW_vc_sel_mask=4'b0011;
end else begin
NW_vc_sel_mask=4'b1100;
end
end
`port5id_west:
begin
// west next too
if (f.control.x_disp+1<0) begin
NW_vc_sel_mask=4'b0011;
end else begin
NW_vc_sel_mask=4'b1100;
end
end
endcase
end
endfunction // NW_vc_sel_mask
module NW_vc_unrestricted_allocator (req, // VC request
output_port, // for which port?
//vc_mask, // which VC's are we permitted to request
req_priority, // prioritized requests? (between VC requests)
vc_status, // which VCs are free
vc_new, // newly allocated VC id.
vc_new_valid, // has new VC been allocated?
vc_allocated, // change VC status from free to allocated?
vc_requested, // which VCs were requested at each input VC?
flit, // head of each input VC buffer
vc_credits, // credits for each VC at each output port
clk, rst_n);
// `include "NW_functions.v";
//parameter type flit_priority_t = flit_pri_t;
parameter buf_len = 4;
parameter xs=4;
parameter ys=4;
parameter np=5;
parameter nv=4;
// some packets can make higher priority requests for VCs
// ** NOT YET IMPLEMENTED **
parameter dynamic_priority_vc_alloc = 0;
//
// selection policies
//
parameter vcselect_bydestinationnode = 0;
parameter vcselect_leastfullbuffer = 0;
parameter vcselect_arbstateupdate = 0; // always/never update state of VC select matrix arbiter
parameter vcselect_usepacketmask = 0; // packet determines which VCs may be requested (not with bydestinationnode!)
typedef logic unsigned [clogb2(buf_len+1)-1:0] pri_t;
//-----
input [np-1:0][nv-1:0] req;
input output_port_t output_port [np-1:0][nv-1:0];
//input [np-1:0][nv-1:0][nv-1:0] vc_mask;
input flit_priority_t req_priority [np-1:0][nv-1:0];
input [np-1:0][nv-1:0] vc_status;
output [np-1:0][nv-1:0][nv-1:0] vc_new;
output [np-1:0][nv-1:0] vc_new_valid;
output [np-1:0][nv-1:0] vc_allocated;
output [np-1:0][nv-1:0][nv-1:0] vc_requested;
input flit_t flit [np-1:0][nv-1:0];
input [np-1:0][nv-1:0][clogb2(buf_len+1)-1:0] vc_credits;
input clk, rst_n;
genvar i,j,k,l;
logic [np-1:0][nv-1:0][nv-1:0] stage1_request, stage1_grant;
logic [np-1:0][nv-1:0][nv-1:0] selected_status;
logic [np-1:0][nv-1:0][np-1:0][nv-1:0] stage2_requests, stage2_grants;
logic [np-1:0][nv-1:0][nv-1:0][np-1:0] vc_new_;
logic [np-1:0][nv-1:0][nv-1:0] vc_mask;
pri_t pri [np-1:0][nv-1:0][nv-1:0];
assign vc_requested=stage1_grant;
generate
for (i=0; i<np; i++) begin:foriports
for (j=0; j<nv; j++) begin:forvcs
//
// Determine value of 'vc_mask'
//
// What VCs may be requested?
//
// (a) all
// (b) use mask set in packet's control field
// (c) or select VC solely by destination node
//
if (vcselect_bydestinationnode || vcselect_usepacketmask) begin
if (vcselect_bydestinationnode) begin
//
// unless exiting network! - should be set as vcalloc_mask at source!!!!! TO-DO
// OR just set second stage request directly?
/*assign vc_mask[i][j] = (output_port[i][j]==`port5id_tile) ? '1 :
1'b1<<(flit[i][j].debug.xdest+xs*flit[i][j].debug.ydest);
// 1'b1<<(flit[i][j].debug.xsrc+xs*flit[i][j].debug.ysrc);
*/
end else begin
end
end else begin
// packet may request any free VC
assign vc_mask[i][j] = '1;
end
//
// Select VC status bits at output port of interest (determine which VCs are free to be allocated)
//
assign selected_status[i][j] = vc_status[oh2bin(output_port[i][j])];
//
// Requests for VC selection arbiter
//
// Narrows requests from all possible VCs that could be requested to 1
//
for (k=0; k<nv; k++) begin:forvcs2
// Request is made if
// (1) Packet requires VC
// (2) VC Mask bit is set
// (3) VC is currently free, so it can be allocated
//
assign stage1_request[i][j][k] = req[i][j] && vc_mask[i][j][k] && selected_status[i][j][k];
// VC selection priority = number of credits
if (vcselect_leastfullbuffer) begin
assign pri[i][j][k] = vc_credits[oh2bin(output_port[i][j])][k];
end
end
//
// first-stage of arbitration
//
// Arbiter state doesn't mean much here as requests on different clock cycles may be associated
// with different output ports. vcselect_arbstateupdate determines if state is always or never
// updated.
//
matrix_arb #(.size(nv), .multistage(1),
.priority_support(vcselect_leastfullbuffer)
//,
//.priority_type(pri_t)
)
stage1arb
(.request(stage1_request[i][j]),
.req_priority(pri[i][j]),
.grant(stage1_grant[i][j]),
// .success(vc_new_valid[i][j]),
.success((vcselect_arbstateupdate==1)),
.clk, .rst_n);
//
// second-stage of arbitration, determines who gets VC
//
for (k=0; k<np; k++) begin:fo
for (l=0; l<nv; l++) begin:fv
assign stage2_requests[k][l][i][j] = stage1_grant[i][j][l] && output_port[i][j][k];
end
end
//
// np*nv np*nv:1 tree arbiters
//
NW_tree_arbiter #(.multistage(0),
.size(np*nv),
.groupsize(nv),
.priority_support(dynamic_priority_vc_alloc)
//,
//.priority_type(flit_priority_t)
) vcarb
(.request(stage2_requests[i][j]),
.req_priority(req_priority),
.grant(stage2_grants[i][j]),
.clk, .rst_n);
assign vc_allocated[i][j]=|(stage2_requests[i][j]);
//
// new VC IDs
//
for (k=0; k<np; k++) begin:fo2
for (l=0; l<nv; l++) begin:fv2
// could get vc x from any one of the output ports
assign vc_new_[i][j][l][k]=stage2_grants[k][l][i][j];
end
end
for (l=0; l<nv; l++) begin:fv3
assign vc_new[i][j][l]=|vc_new_[i][j][l];
end
assign vc_new_valid[i][j]=|vc_new[i][j];
end
end
endgenerate
endmodule // NW_vc_unrestricted_allocator
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_4_V
`define SKY130_FD_SC_LP__O311A_4_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311a_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_4_V
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sample_iterator_get_offset (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
indices_stride_req_din,
indices_stride_req_full_n,
indices_stride_req_write,
indices_stride_rsp_empty_n,
indices_stride_rsp_read,
indices_stride_address,
indices_stride_datain,
indices_stride_dataout,
indices_stride_size,
indices_begin_req_din,
indices_begin_req_full_n,
indices_begin_req_write,
indices_begin_rsp_empty_n,
indices_begin_rsp_read,
indices_begin_address,
indices_begin_datain,
indices_begin_dataout,
indices_begin_size,
ap_ce,
i_index,
i_sample,
indices_samples_req_din,
indices_samples_req_full_n,
indices_samples_req_write,
indices_samples_rsp_empty_n,
indices_samples_rsp_read,
indices_samples_address,
indices_samples_datain,
indices_samples_dataout,
indices_samples_size,
sample_buffer_size,
sample_length,
ap_return
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output indices_stride_req_din;
input indices_stride_req_full_n;
output indices_stride_req_write;
input indices_stride_rsp_empty_n;
output indices_stride_rsp_read;
output [31:0] indices_stride_address;
input [7:0] indices_stride_datain;
output [7:0] indices_stride_dataout;
output [31:0] indices_stride_size;
output indices_begin_req_din;
input indices_begin_req_full_n;
output indices_begin_req_write;
input indices_begin_rsp_empty_n;
output indices_begin_rsp_read;
output [31:0] indices_begin_address;
input [31:0] indices_begin_datain;
output [31:0] indices_begin_dataout;
output [31:0] indices_begin_size;
input ap_ce;
input [15:0] i_index;
input [15:0] i_sample;
output indices_samples_req_din;
input indices_samples_req_full_n;
output indices_samples_req_write;
input indices_samples_rsp_empty_n;
output indices_samples_rsp_read;
output [31:0] indices_samples_address;
input [15:0] indices_samples_datain;
output [15:0] indices_samples_dataout;
output [31:0] indices_samples_size;
input [31:0] sample_buffer_size;
input [15:0] sample_length;
output [31:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg indices_stride_req_write;
reg indices_stride_rsp_read;
reg indices_begin_req_write;
reg indices_begin_rsp_read;
reg [0:0] ap_CS_fsm = 1'b0;
wire ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
reg ap_reg_ppiten_pp0_it2 = 1'b0;
reg ap_reg_ppiten_pp0_it3 = 1'b0;
reg ap_reg_ppiten_pp0_it4 = 1'b0;
reg ap_reg_ppiten_pp0_it5 = 1'b0;
reg ap_reg_ppiten_pp0_it6 = 1'b0;
reg ap_reg_ppiten_pp0_it7 = 1'b0;
reg ap_reg_ppiten_pp0_it8 = 1'b0;
reg ap_reg_ppiten_pp0_it9 = 1'b0;
reg ap_reg_ppiten_pp0_it10 = 1'b0;
reg ap_reg_ppiten_pp0_it11 = 1'b0;
reg ap_reg_ppiten_pp0_it12 = 1'b0;
reg ap_reg_ppiten_pp0_it13 = 1'b0;
reg [15:0] i_sample_read_reg_130;
reg [15:0] ap_reg_ppstg_i_sample_read_reg_130_pp0_it1;
wire [31:0] tmp_fu_93_p1;
reg [31:0] tmp_reg_135;
reg [31:0] ap_reg_ppstg_tmp_reg_135_pp0_it1;
reg [31:0] ap_reg_ppstg_tmp_reg_135_pp0_it2;
reg [31:0] ap_reg_ppstg_tmp_reg_135_pp0_it3;
reg [7:0] indices_stride_addr_read_reg_145;
reg [31:0] indices_begin_addr_read_reg_165;
wire [23:0] grp_fu_110_p2;
reg [23:0] tmp_7_reg_170;
wire [15:0] grp_fu_110_p0;
wire [7:0] grp_fu_110_p1;
wire [31:0] grp_fu_125_p0;
wire [31:0] grp_fu_125_p1;
reg grp_fu_110_ce;
wire [31:0] grp_fu_125_p2;
reg grp_fu_125_ce;
reg [0:0] ap_NS_fsm;
reg ap_sig_pprstidle_pp0;
wire [23:0] grp_fu_110_p00;
wire [23:0] grp_fu_110_p10;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_pp0_stg0_fsm_0 = 1'b0;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv16_0 = 16'b0000000000000000;
parameter ap_true = 1'b1;
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 #(
.ID( 0 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 16 ),
.din1_WIDTH( 8 ),
.dout_WIDTH( 24 ))
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_U0(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_110_p0 ),
.din1( grp_fu_110_p1 ),
.ce( grp_fu_110_ce ),
.dout( grp_fu_110_p2 )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U1(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_125_p0 ),
.din1( grp_fu_125_p1 ),
.ce( grp_fu_125_ce ),
.dout( grp_fu_125_p2 )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end
end
end
/// ap_reg_ppiten_pp0_it10 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end
end
end
/// ap_reg_ppiten_pp0_it11 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end
end
end
/// ap_reg_ppiten_pp0_it12 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it12
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end
end
end
/// ap_reg_ppiten_pp0_it13 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it13
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end
end
end
/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end
end
end
/// ap_reg_ppiten_pp0_it7 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end
end
end
/// ap_reg_ppiten_pp0_it8 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end
end
end
/// ap_reg_ppiten_pp0_it9 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 <= i_sample_read_reg_130;
ap_reg_ppstg_tmp_reg_135_pp0_it1[0] <= tmp_reg_135[0];
ap_reg_ppstg_tmp_reg_135_pp0_it1[1] <= tmp_reg_135[1];
ap_reg_ppstg_tmp_reg_135_pp0_it1[2] <= tmp_reg_135[2];
ap_reg_ppstg_tmp_reg_135_pp0_it1[3] <= tmp_reg_135[3];
ap_reg_ppstg_tmp_reg_135_pp0_it1[4] <= tmp_reg_135[4];
ap_reg_ppstg_tmp_reg_135_pp0_it1[5] <= tmp_reg_135[5];
ap_reg_ppstg_tmp_reg_135_pp0_it1[6] <= tmp_reg_135[6];
ap_reg_ppstg_tmp_reg_135_pp0_it1[7] <= tmp_reg_135[7];
ap_reg_ppstg_tmp_reg_135_pp0_it1[8] <= tmp_reg_135[8];
ap_reg_ppstg_tmp_reg_135_pp0_it1[9] <= tmp_reg_135[9];
ap_reg_ppstg_tmp_reg_135_pp0_it1[10] <= tmp_reg_135[10];
ap_reg_ppstg_tmp_reg_135_pp0_it1[11] <= tmp_reg_135[11];
ap_reg_ppstg_tmp_reg_135_pp0_it1[12] <= tmp_reg_135[12];
ap_reg_ppstg_tmp_reg_135_pp0_it1[13] <= tmp_reg_135[13];
ap_reg_ppstg_tmp_reg_135_pp0_it1[14] <= tmp_reg_135[14];
ap_reg_ppstg_tmp_reg_135_pp0_it1[15] <= tmp_reg_135[15];
ap_reg_ppstg_tmp_reg_135_pp0_it2[0] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[0];
ap_reg_ppstg_tmp_reg_135_pp0_it2[1] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[1];
ap_reg_ppstg_tmp_reg_135_pp0_it2[2] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[2];
ap_reg_ppstg_tmp_reg_135_pp0_it2[3] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[3];
ap_reg_ppstg_tmp_reg_135_pp0_it2[4] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[4];
ap_reg_ppstg_tmp_reg_135_pp0_it2[5] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[5];
ap_reg_ppstg_tmp_reg_135_pp0_it2[6] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[6];
ap_reg_ppstg_tmp_reg_135_pp0_it2[7] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[7];
ap_reg_ppstg_tmp_reg_135_pp0_it2[8] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[8];
ap_reg_ppstg_tmp_reg_135_pp0_it2[9] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[9];
ap_reg_ppstg_tmp_reg_135_pp0_it2[10] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[10];
ap_reg_ppstg_tmp_reg_135_pp0_it2[11] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[11];
ap_reg_ppstg_tmp_reg_135_pp0_it2[12] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[12];
ap_reg_ppstg_tmp_reg_135_pp0_it2[13] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[13];
ap_reg_ppstg_tmp_reg_135_pp0_it2[14] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[14];
ap_reg_ppstg_tmp_reg_135_pp0_it2[15] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[15];
ap_reg_ppstg_tmp_reg_135_pp0_it3[0] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[0];
ap_reg_ppstg_tmp_reg_135_pp0_it3[1] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[1];
ap_reg_ppstg_tmp_reg_135_pp0_it3[2] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[2];
ap_reg_ppstg_tmp_reg_135_pp0_it3[3] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[3];
ap_reg_ppstg_tmp_reg_135_pp0_it3[4] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[4];
ap_reg_ppstg_tmp_reg_135_pp0_it3[5] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[5];
ap_reg_ppstg_tmp_reg_135_pp0_it3[6] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[6];
ap_reg_ppstg_tmp_reg_135_pp0_it3[7] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[7];
ap_reg_ppstg_tmp_reg_135_pp0_it3[8] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[8];
ap_reg_ppstg_tmp_reg_135_pp0_it3[9] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[9];
ap_reg_ppstg_tmp_reg_135_pp0_it3[10] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[10];
ap_reg_ppstg_tmp_reg_135_pp0_it3[11] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[11];
ap_reg_ppstg_tmp_reg_135_pp0_it3[12] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[12];
ap_reg_ppstg_tmp_reg_135_pp0_it3[13] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[13];
ap_reg_ppstg_tmp_reg_135_pp0_it3[14] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[14];
ap_reg_ppstg_tmp_reg_135_pp0_it3[15] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[15];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
i_sample_read_reg_130 <= i_sample;
tmp_reg_135[0] <= tmp_fu_93_p1[0];
tmp_reg_135[1] <= tmp_fu_93_p1[1];
tmp_reg_135[2] <= tmp_fu_93_p1[2];
tmp_reg_135[3] <= tmp_fu_93_p1[3];
tmp_reg_135[4] <= tmp_fu_93_p1[4];
tmp_reg_135[5] <= tmp_fu_93_p1[5];
tmp_reg_135[6] <= tmp_fu_93_p1[6];
tmp_reg_135[7] <= tmp_fu_93_p1[7];
tmp_reg_135[8] <= tmp_fu_93_p1[8];
tmp_reg_135[9] <= tmp_fu_93_p1[9];
tmp_reg_135[10] <= tmp_fu_93_p1[10];
tmp_reg_135[11] <= tmp_fu_93_p1[11];
tmp_reg_135[12] <= tmp_fu_93_p1[12];
tmp_reg_135[13] <= tmp_fu_93_p1[13];
tmp_reg_135[14] <= tmp_fu_93_p1[14];
tmp_reg_135[15] <= tmp_fu_93_p1[15];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_begin_addr_read_reg_165 <= indices_begin_datain;
tmp_7_reg_170 <= grp_fu_110_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_stride_addr_read_reg_145 <= indices_stride_datain;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it13 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((~(ap_const_logic_1 == ap_start) & (ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) | ((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it13) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it4 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp0_it8 or ap_reg_ppiten_pp0_it9 or ap_reg_ppiten_pp0_it10 or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp0_it12 or ap_reg_ppiten_pp0_it13)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it3) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it4) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it5) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it6) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it7) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it8) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it9) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it10) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it11) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it12) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it13))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_pprstidle_pp0 assign process. ///
always @ (ap_start or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it4 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp0_it8 or ap_reg_ppiten_pp0_it9 or ap_reg_ppiten_pp0_it10 or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it3) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it4) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it5) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it6) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it7) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it8) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it9) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it10) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it11) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it12) & (ap_const_logic_0 == ap_start))) begin
ap_sig_pprstidle_pp0 = ap_const_logic_1;
end else begin
ap_sig_pprstidle_pp0 = ap_const_logic_0;
end
end
/// grp_fu_110_ce assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
grp_fu_110_ce = ap_const_logic_1;
end else begin
grp_fu_110_ce = ap_const_logic_0;
end
end
/// grp_fu_125_ce assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
grp_fu_125_ce = ap_const_logic_1;
end else begin
grp_fu_125_ce = ap_const_logic_0;
end
end
/// indices_begin_req_write assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it4 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_begin_req_write = ap_const_logic_1;
end else begin
indices_begin_req_write = ap_const_logic_0;
end
end
/// indices_begin_rsp_read assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_begin_rsp_read = ap_const_logic_1;
end else begin
indices_begin_rsp_read = ap_const_logic_0;
end
end
/// indices_stride_req_write assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_stride_req_write = ap_const_logic_1;
end else begin
indices_stride_req_write = ap_const_logic_0;
end
end
/// indices_stride_rsp_read assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_stride_rsp_read = ap_const_logic_1;
end else begin
indices_stride_rsp_read = ap_const_logic_0;
end
end
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce or ap_sig_pprstidle_pp0)
begin
case (ap_CS_fsm)
ap_ST_pp0_stg0_fsm_0 :
ap_NS_fsm = ap_ST_pp0_stg0_fsm_0;
default :
ap_NS_fsm = 'bx;
endcase
end
assign ap_reg_ppiten_pp0_it0 = ap_start;
assign ap_return = grp_fu_125_p2;
assign grp_fu_110_p0 = grp_fu_110_p00;
assign grp_fu_110_p00 = $unsigned(ap_reg_ppstg_i_sample_read_reg_130_pp0_it1);
assign grp_fu_110_p1 = grp_fu_110_p10;
assign grp_fu_110_p10 = $unsigned(indices_stride_addr_read_reg_145);
assign grp_fu_125_p0 = $unsigned(tmp_7_reg_170);
assign grp_fu_125_p1 = indices_begin_addr_read_reg_165;
assign indices_begin_address = ap_reg_ppstg_tmp_reg_135_pp0_it3;
assign indices_begin_dataout = ap_const_lv32_0;
assign indices_begin_req_din = ap_const_logic_0;
assign indices_begin_size = ap_const_lv32_1;
assign indices_samples_address = ap_const_lv32_0;
assign indices_samples_dataout = ap_const_lv16_0;
assign indices_samples_req_din = ap_const_logic_0;
assign indices_samples_req_write = ap_const_logic_0;
assign indices_samples_rsp_read = ap_const_logic_0;
assign indices_samples_size = ap_const_lv32_0;
assign indices_stride_address = tmp_fu_93_p1;
assign indices_stride_dataout = ap_const_lv8_0;
assign indices_stride_req_din = ap_const_logic_0;
assign indices_stride_size = ap_const_lv32_1;
assign tmp_fu_93_p1 = $unsigned(i_index);
always @ (posedge ap_clk)
begin
tmp_reg_135[31:16] <= 16'b0000000000000000;
ap_reg_ppstg_tmp_reg_135_pp0_it1[31:16] <= 16'b0000000000000000;
ap_reg_ppstg_tmp_reg_135_pp0_it2[31:16] <= 16'b0000000000000000;
ap_reg_ppstg_tmp_reg_135_pp0_it3[31:16] <= 16'b0000000000000000;
end
endmodule //sample_iterator_get_offset
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : bus_arbiter.v
//Project Name : azpr_soc
//Description : the bus arbiter.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/bus_arbiter.v
//License : CPL
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 01-07-2016 17:00(1th Fri,July,2016)
//First Author : lichangbeiju
//Modify Date : 02-09-2016 14:20(1th Sun,July,2016)
//Last Author : lichangbeiju
//Version Number : 002
//Last Commit : 03-09-2016 14:30(1th Sun,July,2016)
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.21 - lichangbeiju - Add grant and master owner logic.
//****************************************************************************************************
`include "../sys_include.h"
`include "bus.h"
module bus_arbiter(
input wire clk ,//01 the system clock
input wire reset ,//01
input wire m0_req_n ,//01
output reg m0_grant_n ,//01
input wire m1_req_n ,//01
output reg m1_grant_n ,//01
input wire m2_req_n ,//01
output reg m2_grant_n ,//01
input wire m3_req_n ,//01
output reg m3_grant_n //01
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
// `define UDP
// `define CLK_TEST_EN
//************************************************************************************************
// 2.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 2.1 the output reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.2 the internal reg
//------------------------------------------------------------------------------------------------
reg [01:00] owner ;//aux data input and output
//------------------------------------------------------------------------------------------------
// 2.x the test logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 3.Main code
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the master grant logic
//------------------------------------------------------------------------------------------------
always @(*) begin : MASTER_GRANT
m0_grant_n = `DISABLE_N;
m1_grant_n = `DISABLE_N;
m2_grant_n = `DISABLE_N;
m3_grant_n = `DISABLE_N;
case(owner)
`BUS_OWNER_MASTER_0 : begin
m0_grant_n = `ENABLE_N;
end
`BUS_OWNER_MASTER_1 : begin
m1_grant_n = `ENABLE_N;
end
`BUS_OWNER_MASTER_2 : begin
m2_grant_n = `ENABLE_N;
end
`BUS_OWNER_MASTER_3 : begin
m3_grant_n = `ENABLE_N;
end
endcase
end
//------------------------------------------------------------------------------------------------
// 4.1 the master owner control logic
//------------------------------------------------------------------------------------------------
always @(posedge clk or `RESET_EDGE reset) begin : OWNER_CTRL
if(reset == `RESET_ENABLE)
begin
owner <= `BUS_OWNER_MASTER_0;
end
else begin
case(owner)
`BUS_OWNER_MASTER_0 : begin
if(m0_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_0;
end
else if(m1_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_1;
end
else if(m2_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_2;
end
else if(m3_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_3;
end
else
begin
owner <= owner;
end
end
`BUS_OWNER_MASTER_1 : begin
if(m1_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_1;
end
else if(m2_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_2;
end
else if(m3_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_3;
end
else if(m0_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_0;
end
else
begin
owner <= owner;
end
end
`BUS_OWNER_MASTER_2 : begin
if(m2_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_2;
end
else if(m3_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_3;
end
else if(m0_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_0;
end
else if(m1_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_1;
end
else
begin
owner <= owner;
end
end
`BUS_OWNER_MASTER_3 : begin
if(m3_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_3;
end
else if(m0_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_0;
end
else if(m1_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_1;
end
else if(m2_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_2;
end
else
begin
owner <= owner;
end
end
endcase
end
end
//************************************************************************************************
// 4.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 4.1 the clk generate module
//------------------------------------------------------------------------------------------------
endmodule
//****************************************************************************************************
//End of Module
//****************************************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22O_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A22O_FUNCTIONAL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a22o (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22O_FUNCTIONAL_V |
`timescale 1ns / 1ps
module ControlUnit (clk,OPCODE,BOpCode,Zero,BSelector,MemRD,MemWD,RegWrite,RegSelector,PCSelect,Enable1,Enable2,Enable3,Enable4);
input wire clk;
input [4:0] OPCODE;
input [0:0] Zero;
input [4:0] BOpCode;
output reg[0:0] BSelector;
output reg[0:0] MemRD;
output reg[0:0] MemWD;
output reg[0:0] RegWrite;
output reg[1:0] RegSelector;
output reg[0:0] PCSelect;
output reg[0:0] Enable1;
output reg[0:0] Enable2;
output reg[0:0] Enable3;
output reg[0:0] Enable4;
parameter ADD = 5'd0;
parameter SUB = 5'd1;
parameter ADDI = 5'd2;
parameter SUBI = 5'd3;
parameter MLT = 5'd4;
parameter MLTI = 5'd5;
parameter AND = 5'd6;
parameter OR = 5'd7;
parameter ANDI = 5'd8;
parameter ORI = 5'd9;
parameter SLR = 5'd10;
parameter SLL = 5'd11;
parameter LDR = 5'd12;
parameter STR = 5'd13;
parameter BNE = 5'd14;
parameter BEQ = 5'd15;
parameter J = 5'd16;
parameter CMP = 5'd17;
parameter NOP = 5'b11111;
initial begin
BSelector = 1'd0;
PCSelect= 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
Enable1 = 1'd1;
Enable2 = 1'd1;
Enable3 = 1'd1;
Enable4 = 1'd1;
end
always @ (posedge clk) begin
case(OPCODE)
ADD:
begin
BSelector = 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
SUB:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector =2'd0 ;
end
ADDI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
SUBI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
MLT:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
MLTI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
AND:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
OR:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
ANDI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
ORI:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
SLR:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector =2'd1;
end
SLL:
begin
BSelector = 1'd1;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd1;
end
LDR:
begin
BSelector =1'd1;
MemRD = 1'd1;
MemWD = 1'd0;
RegWrite = 1'd1;
RegSelector = 2'd2;
end
STR:
begin
BSelector =1'd1;
MemRD = 1'd0;
MemWD = 1'd1;
RegWrite = 1'd1;
RegSelector = 2'd2;
end
BNE:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd1;
end
BEQ:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd1;
end
J:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
end
CMP:
begin
BSelector =1'd0;
MemRD = 1'd0;
MemWD =1'd0 ;
RegWrite = 1'd1;
RegSelector = 2'd0;
end
NOP:
begin
BSelector = 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
end
default:
begin
BSelector = 1'd0;
MemRD = 1'd0;
MemWD = 1'd0;
RegWrite = 1'd0;
RegSelector = 2'd0;
end
endcase
end
always @ (Zero,BOpCode) begin
if (BOpCode==BNE && !Zero) PCSelect=1'd1;
else if (BOpCode==BEQ && Zero) PCSelect=1'd1;
else PCSelect=1'd0;
end
endmodule |
/*
Copyright (c) 2015-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* si5341_i2c_init
*/
module si5341_i2c_init (
input wire clk,
input wire rst,
/*
* I2C master interface
*/
output wire [6:0] m_axis_cmd_address,
output wire m_axis_cmd_start,
output wire m_axis_cmd_read,
output wire m_axis_cmd_write,
output wire m_axis_cmd_write_multiple,
output wire m_axis_cmd_stop,
output wire m_axis_cmd_valid,
input wire m_axis_cmd_ready,
output wire [7:0] m_axis_data_tdata,
output wire m_axis_data_tvalid,
input wire m_axis_data_tready,
output wire m_axis_data_tlast,
/*
* Status
*/
output wire busy,
/*
* Configuration
*/
input wire start
);
/*
Generic module for I2C bus initialization. Good for use when multiple devices
on an I2C bus must be initialized on system start without intervention of a
general-purpose processor.
Copy this file and change init_data and INIT_DATA_LEN as needed.
This module can be used in two modes: simple device initialization, or multiple
device initialization. In multiple device mode, the same initialization sequence
can be performed on multiple different device addresses.
To use single device mode, only use the start write to address and write data commands.
The module will generate the I2C commands in sequential order. Terminate the list
with a 0 entry.
To use the multiple device mode, use the start data and start address block commands
to set up lists of initialization data and device addresses. The module enters
multiple device mode upon seeing a start data block command. The module stores the
offset of the start of the data block and then skips ahead until it reaches a start
address block command. The module will store the offset to the address block and
read the first address in the block. Then it will jump back to the data block
and execute it, substituting the stored address for each current address write
command. Upon reaching the start address block command, the module will read out the
next address and start again at the top of the data block. If the module encounters
a start data block command while looking for an address, then it will store a new data
offset and then look for a start address block command. Terminate the list with a 0
entry. Normal address commands will operate normally inside a data block.
Commands:
00 0000000 : stop
00 0000001 : exit multiple device mode
00 0000011 : start write to current address
00 0001000 : start address block
00 0001001 : start data block
00 001dddd : delay 2**(16+d) cycles
00 1000001 : send I2C stop
01 aaaaaaa : start write to address
1 dddddddd : write 8-bit data
Examples
write 0x11223344 to register 0x0004 on device at 0x50
01 1010000 start write to 0x50
1 00000000 write address 0x0004
1 00000100
1 00010001 write data 0x11223344
1 00100010
1 00110011
1 01000100
0 00000000 stop
write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53
00 0001001 start data block
00 0000011 start write to current address
1 00000000 write address 0x0004
1 00000100
1 00010001 write data 0x11223344
1 00100010
1 00110011
1 01000100
00 0001000 start address block
01 1010000 address 0x50
01 1010001 address 0x51
01 1010010 address 0x52
01 1010011 address 0x53
00 0000000 stop
*/
// init_data ROM
localparam INIT_DATA_LEN = 536;
reg [8:0] init_data [INIT_DATA_LEN-1:0];
initial begin
// Initial delay
init_data[0] = 9'b000010110; // delay 30 ms
// Set muxes to select Si5341
init_data[1] = {2'b01, 7'h70};
init_data[2] = {1'b1, 8'h00};
init_data[3] = 9'b001000001; // I2C stop
init_data[4] = {2'b01, 7'h71};
init_data[5] = {1'b1, 8'h04};
init_data[6] = 9'b001000001; // I2C stop
// Si534x/7x/8x/9x Registers Script
//
// Part: Si5341
// Project File: C:\Users\Alex\Documents\Si5341-RevD-fpga-161-osc-Project.slabtimeproj
// Design ID: fpga
// Includes Pre/Post Download Control Register Writes: Yes
// Die Revision: B1
// Creator: ClockBuilder Pro v3.1 [2021-01-18]
// Created On: 2021-03-14 17:21:45 GMT-07:00
//
// Start configuration preamble
init_data[7] = {2'b01, 7'h77};
init_data[8] = {1'b1, 8'h01};
init_data[9] = {1'b1, 8'h0b}; // set page 0x0b
init_data[10] = {2'b01, 7'h77};
init_data[11] = {1'b1, 8'h24};
init_data[12] = {1'b1, 8'hc0}; // write 0xc0 to 0x0b24
init_data[13] = {1'b1, 8'h00}; // write 0x00 to 0x0b25
// Rev D stuck divider fix
init_data[14] = {2'b01, 7'h77};
init_data[15] = {1'b1, 8'h01};
init_data[16] = {1'b1, 8'h05}; // set page 0x05
init_data[17] = {2'b01, 7'h77};
init_data[18] = {1'b1, 8'h02};
init_data[19] = {1'b1, 8'h01}; // write 0x01 to 0x0502
init_data[20] = {2'b01, 7'h77};
init_data[21] = {1'b1, 8'h05};
init_data[22] = {1'b1, 8'h03}; // write 0x03 to 0x0505
init_data[23] = {2'b01, 7'h77};
init_data[24] = {1'b1, 8'h01};
init_data[25] = {1'b1, 8'h09}; // set page 0x09
init_data[26] = {2'b01, 7'h77};
init_data[27] = {1'b1, 8'h57};
init_data[28] = {1'b1, 8'h17}; // write 0x17 to 0x0957
init_data[29] = {2'b01, 7'h77};
init_data[30] = {1'b1, 8'h01};
init_data[31] = {1'b1, 8'h0b}; // set page 0x0b
init_data[32] = {2'b01, 7'h77};
init_data[33] = {1'b1, 8'h4e};
init_data[34] = {1'b1, 8'h1a}; // write 0x1a to 0x0b4e
// End configuration preamble
//
// Delay 300 msec
init_data[35] = 9'b000011010; // delay 300 ms
// Delay is worst case time for device to complete any calibration
// that is running due to device state change previous to this script
// being processed.
//
// Start configuration registers
init_data[36] = {2'b01, 7'h77};
init_data[37] = {1'b1, 8'h01};
init_data[38] = {1'b1, 8'h00}; // set page 0x00
init_data[39] = {2'b01, 7'h77};
init_data[40] = {1'b1, 8'h06};
init_data[41] = {1'b1, 8'h00}; // write 0x00 to 0x0006
init_data[42] = {1'b1, 8'h00}; // write 0x00 to 0x0007
init_data[43] = {1'b1, 8'h00}; // write 0x00 to 0x0008
init_data[44] = {2'b01, 7'h77};
init_data[45] = {1'b1, 8'h0b};
init_data[46] = {1'b1, 8'h74}; // write 0x74 to 0x000b
init_data[47] = {2'b01, 7'h77};
init_data[48] = {1'b1, 8'h17};
init_data[49] = {1'b1, 8'hd0}; // write 0xd0 to 0x0017
init_data[50] = {1'b1, 8'hfc}; // write 0xfc to 0x0018
init_data[51] = {2'b01, 7'h77};
init_data[52] = {1'b1, 8'h21};
init_data[53] = {1'b1, 8'h0b}; // write 0x0b to 0x0021
init_data[54] = {1'b1, 8'h00}; // write 0x00 to 0x0022
init_data[55] = {2'b01, 7'h77};
init_data[56] = {1'b1, 8'h2b};
init_data[57] = {1'b1, 8'h02}; // write 0x02 to 0x002b
init_data[58] = {1'b1, 8'h33}; // write 0x33 to 0x002c
init_data[59] = {1'b1, 8'h05}; // write 0x05 to 0x002d
init_data[60] = {1'b1, 8'hae}; // write 0xae to 0x002e
init_data[61] = {1'b1, 8'h00}; // write 0x00 to 0x002f
init_data[62] = {1'b1, 8'hae}; // write 0xae to 0x0030
init_data[63] = {1'b1, 8'h00}; // write 0x00 to 0x0031
init_data[64] = {1'b1, 8'h00}; // write 0x00 to 0x0032
init_data[65] = {1'b1, 8'h00}; // write 0x00 to 0x0033
init_data[66] = {1'b1, 8'h00}; // write 0x00 to 0x0034
init_data[67] = {1'b1, 8'h00}; // write 0x00 to 0x0035
init_data[68] = {1'b1, 8'hae}; // write 0xae to 0x0036
init_data[69] = {1'b1, 8'h00}; // write 0x00 to 0x0037
init_data[70] = {1'b1, 8'hae}; // write 0xae to 0x0038
init_data[71] = {1'b1, 8'h00}; // write 0x00 to 0x0039
init_data[72] = {1'b1, 8'h00}; // write 0x00 to 0x003a
init_data[73] = {1'b1, 8'h00}; // write 0x00 to 0x003b
init_data[74] = {1'b1, 8'h00}; // write 0x00 to 0x003c
init_data[75] = {1'b1, 8'h00}; // write 0x00 to 0x003d
init_data[76] = {2'b01, 7'h77};
init_data[77] = {1'b1, 8'h41};
init_data[78] = {1'b1, 8'h07}; // write 0x07 to 0x0041
init_data[79] = {1'b1, 8'h07}; // write 0x07 to 0x0042
init_data[80] = {1'b1, 8'h00}; // write 0x00 to 0x0043
init_data[81] = {1'b1, 8'h00}; // write 0x00 to 0x0044
init_data[82] = {2'b01, 7'h77};
init_data[83] = {1'b1, 8'h9e};
init_data[84] = {1'b1, 8'h00}; // write 0x00 to 0x009e
init_data[85] = {2'b01, 7'h77};
init_data[86] = {1'b1, 8'h01};
init_data[87] = {1'b1, 8'h01}; // set page 0x01
init_data[88] = {2'b01, 7'h77};
init_data[89] = {1'b1, 8'h02};
init_data[90] = {1'b1, 8'h01}; // write 0x01 to 0x0102
init_data[91] = {2'b01, 7'h77};
init_data[92] = {1'b1, 8'h08};
init_data[93] = {1'b1, 8'h06}; // write 0x06 to 0x0108
init_data[94] = {1'b1, 8'h09}; // write 0x09 to 0x0109
init_data[95] = {1'b1, 8'h3b}; // write 0x3b to 0x010a
init_data[96] = {1'b1, 8'h28}; // write 0x28 to 0x010b
init_data[97] = {2'b01, 7'h77};
init_data[98] = {1'b1, 8'h0d};
init_data[99] = {1'b1, 8'h06}; // write 0x06 to 0x010d
init_data[100] = {1'b1, 8'h09}; // write 0x09 to 0x010e
init_data[101] = {1'b1, 8'h3b}; // write 0x3b to 0x010f
init_data[102] = {1'b1, 8'h28}; // write 0x28 to 0x0110
init_data[103] = {2'b01, 7'h77};
init_data[104] = {1'b1, 8'h12};
init_data[105] = {1'b1, 8'h02}; // write 0x02 to 0x0112
init_data[106] = {1'b1, 8'h09}; // write 0x09 to 0x0113
init_data[107] = {1'b1, 8'h3b}; // write 0x3b to 0x0114
init_data[108] = {1'b1, 8'h2c}; // write 0x2c to 0x0115
init_data[109] = {2'b01, 7'h77};
init_data[110] = {1'b1, 8'h17};
init_data[111] = {1'b1, 8'h06}; // write 0x06 to 0x0117
init_data[112] = {1'b1, 8'h09}; // write 0x09 to 0x0118
init_data[113] = {1'b1, 8'h3b}; // write 0x3b to 0x0119
init_data[114] = {1'b1, 8'h29}; // write 0x29 to 0x011a
init_data[115] = {2'b01, 7'h77};
init_data[116] = {1'b1, 8'h1c};
init_data[117] = {1'b1, 8'h06}; // write 0x06 to 0x011c
init_data[118] = {1'b1, 8'h09}; // write 0x09 to 0x011d
init_data[119] = {1'b1, 8'h3b}; // write 0x3b to 0x011e
init_data[120] = {1'b1, 8'h29}; // write 0x29 to 0x011f
init_data[121] = {2'b01, 7'h77};
init_data[122] = {1'b1, 8'h21};
init_data[123] = {1'b1, 8'h06}; // write 0x06 to 0x0121
init_data[124] = {1'b1, 8'h09}; // write 0x09 to 0x0122
init_data[125] = {1'b1, 8'h3b}; // write 0x3b to 0x0123
init_data[126] = {1'b1, 8'h2a}; // write 0x2a to 0x0124
init_data[127] = {2'b01, 7'h77};
init_data[128] = {1'b1, 8'h26};
init_data[129] = {1'b1, 8'h06}; // write 0x06 to 0x0126
init_data[130] = {1'b1, 8'h09}; // write 0x09 to 0x0127
init_data[131] = {1'b1, 8'h3b}; // write 0x3b to 0x0128
init_data[132] = {1'b1, 8'h2a}; // write 0x2a to 0x0129
init_data[133] = {2'b01, 7'h77};
init_data[134] = {1'b1, 8'h2b};
init_data[135] = {1'b1, 8'h06}; // write 0x06 to 0x012b
init_data[136] = {1'b1, 8'h09}; // write 0x09 to 0x012c
init_data[137] = {1'b1, 8'h3b}; // write 0x3b to 0x012d
init_data[138] = {1'b1, 8'h2b}; // write 0x2b to 0x012e
init_data[139] = {2'b01, 7'h77};
init_data[140] = {1'b1, 8'h30};
init_data[141] = {1'b1, 8'h06}; // write 0x06 to 0x0130
init_data[142] = {1'b1, 8'h09}; // write 0x09 to 0x0131
init_data[143] = {1'b1, 8'h3b}; // write 0x3b to 0x0132
init_data[144] = {1'b1, 8'h2b}; // write 0x2b to 0x0133
init_data[145] = {2'b01, 7'h77};
init_data[146] = {1'b1, 8'h3a};
init_data[147] = {1'b1, 8'h06}; // write 0x06 to 0x013a
init_data[148] = {1'b1, 8'h09}; // write 0x09 to 0x013b
init_data[149] = {1'b1, 8'h3b}; // write 0x3b to 0x013c
init_data[150] = {1'b1, 8'h2b}; // write 0x2b to 0x013d
init_data[151] = {2'b01, 7'h77};
init_data[152] = {1'b1, 8'h3f};
init_data[153] = {1'b1, 8'h00}; // write 0x00 to 0x013f
init_data[154] = {1'b1, 8'h00}; // write 0x00 to 0x0140
init_data[155] = {1'b1, 8'h40}; // write 0x40 to 0x0141
init_data[156] = {2'b01, 7'h77};
init_data[157] = {1'b1, 8'h01};
init_data[158] = {1'b1, 8'h02}; // set page 0x02
init_data[159] = {2'b01, 7'h77};
init_data[160] = {1'b1, 8'h06};
init_data[161] = {1'b1, 8'h00}; // write 0x00 to 0x0206
init_data[162] = {2'b01, 7'h77};
init_data[163] = {1'b1, 8'h08};
init_data[164] = {1'b1, 8'h02}; // write 0x02 to 0x0208
init_data[165] = {1'b1, 8'h00}; // write 0x00 to 0x0209
init_data[166] = {1'b1, 8'h00}; // write 0x00 to 0x020a
init_data[167] = {1'b1, 8'h00}; // write 0x00 to 0x020b
init_data[168] = {1'b1, 8'h00}; // write 0x00 to 0x020c
init_data[169] = {1'b1, 8'h00}; // write 0x00 to 0x020d
init_data[170] = {1'b1, 8'h01}; // write 0x01 to 0x020e
init_data[171] = {1'b1, 8'h00}; // write 0x00 to 0x020f
init_data[172] = {1'b1, 8'h00}; // write 0x00 to 0x0210
init_data[173] = {1'b1, 8'h00}; // write 0x00 to 0x0211
init_data[174] = {1'b1, 8'h02}; // write 0x02 to 0x0212
init_data[175] = {1'b1, 8'h00}; // write 0x00 to 0x0213
init_data[176] = {1'b1, 8'h00}; // write 0x00 to 0x0214
init_data[177] = {1'b1, 8'h00}; // write 0x00 to 0x0215
init_data[178] = {1'b1, 8'h00}; // write 0x00 to 0x0216
init_data[179] = {1'b1, 8'h00}; // write 0x00 to 0x0217
init_data[180] = {1'b1, 8'h01}; // write 0x01 to 0x0218
init_data[181] = {1'b1, 8'h00}; // write 0x00 to 0x0219
init_data[182] = {1'b1, 8'h00}; // write 0x00 to 0x021a
init_data[183] = {1'b1, 8'h00}; // write 0x00 to 0x021b
init_data[184] = {1'b1, 8'h00}; // write 0x00 to 0x021c
init_data[185] = {1'b1, 8'h00}; // write 0x00 to 0x021d
init_data[186] = {1'b1, 8'h00}; // write 0x00 to 0x021e
init_data[187] = {1'b1, 8'h00}; // write 0x00 to 0x021f
init_data[188] = {1'b1, 8'h00}; // write 0x00 to 0x0220
init_data[189] = {1'b1, 8'h00}; // write 0x00 to 0x0221
init_data[190] = {1'b1, 8'h00}; // write 0x00 to 0x0222
init_data[191] = {1'b1, 8'h00}; // write 0x00 to 0x0223
init_data[192] = {1'b1, 8'h00}; // write 0x00 to 0x0224
init_data[193] = {1'b1, 8'h00}; // write 0x00 to 0x0225
init_data[194] = {1'b1, 8'h00}; // write 0x00 to 0x0226
init_data[195] = {1'b1, 8'h00}; // write 0x00 to 0x0227
init_data[196] = {1'b1, 8'h00}; // write 0x00 to 0x0228
init_data[197] = {1'b1, 8'h00}; // write 0x00 to 0x0229
init_data[198] = {1'b1, 8'h00}; // write 0x00 to 0x022a
init_data[199] = {1'b1, 8'h00}; // write 0x00 to 0x022b
init_data[200] = {1'b1, 8'h00}; // write 0x00 to 0x022c
init_data[201] = {1'b1, 8'h00}; // write 0x00 to 0x022d
init_data[202] = {1'b1, 8'h00}; // write 0x00 to 0x022e
init_data[203] = {1'b1, 8'h00}; // write 0x00 to 0x022f
init_data[204] = {2'b01, 7'h77};
init_data[205] = {1'b1, 8'h35};
init_data[206] = {1'b1, 8'h00}; // write 0x00 to 0x0235
init_data[207] = {1'b1, 8'h00}; // write 0x00 to 0x0236
init_data[208] = {1'b1, 8'h00}; // write 0x00 to 0x0237
init_data[209] = {1'b1, 8'h90}; // write 0x90 to 0x0238
init_data[210] = {1'b1, 8'h54}; // write 0x54 to 0x0239
init_data[211] = {1'b1, 8'h00}; // write 0x00 to 0x023a
init_data[212] = {1'b1, 8'h00}; // write 0x00 to 0x023b
init_data[213] = {1'b1, 8'h00}; // write 0x00 to 0x023c
init_data[214] = {1'b1, 8'h00}; // write 0x00 to 0x023d
init_data[215] = {1'b1, 8'h80}; // write 0x80 to 0x023e
init_data[216] = {2'b01, 7'h77};
init_data[217] = {1'b1, 8'h4a};
init_data[218] = {1'b1, 8'h00}; // write 0x00 to 0x024a
init_data[219] = {1'b1, 8'h00}; // write 0x00 to 0x024b
init_data[220] = {1'b1, 8'h00}; // write 0x00 to 0x024c
init_data[221] = {1'b1, 8'h00}; // write 0x00 to 0x024d
init_data[222] = {1'b1, 8'h00}; // write 0x00 to 0x024e
init_data[223] = {1'b1, 8'h00}; // write 0x00 to 0x024f
init_data[224] = {1'b1, 8'h03}; // write 0x03 to 0x0250
init_data[225] = {1'b1, 8'h00}; // write 0x00 to 0x0251
init_data[226] = {1'b1, 8'h00}; // write 0x00 to 0x0252
init_data[227] = {1'b1, 8'h00}; // write 0x00 to 0x0253
init_data[228] = {1'b1, 8'h00}; // write 0x00 to 0x0254
init_data[229] = {1'b1, 8'h00}; // write 0x00 to 0x0255
init_data[230] = {1'b1, 8'h00}; // write 0x00 to 0x0256
init_data[231] = {1'b1, 8'h00}; // write 0x00 to 0x0257
init_data[232] = {1'b1, 8'h00}; // write 0x00 to 0x0258
init_data[233] = {1'b1, 8'h00}; // write 0x00 to 0x0259
init_data[234] = {1'b1, 8'h00}; // write 0x00 to 0x025a
init_data[235] = {1'b1, 8'h00}; // write 0x00 to 0x025b
init_data[236] = {1'b1, 8'h00}; // write 0x00 to 0x025c
init_data[237] = {1'b1, 8'h00}; // write 0x00 to 0x025d
init_data[238] = {1'b1, 8'h00}; // write 0x00 to 0x025e
init_data[239] = {1'b1, 8'h00}; // write 0x00 to 0x025f
init_data[240] = {1'b1, 8'h00}; // write 0x00 to 0x0260
init_data[241] = {1'b1, 8'h00}; // write 0x00 to 0x0261
init_data[242] = {1'b1, 8'h00}; // write 0x00 to 0x0262
init_data[243] = {1'b1, 8'h00}; // write 0x00 to 0x0263
init_data[244] = {1'b1, 8'h00}; // write 0x00 to 0x0264
init_data[245] = {2'b01, 7'h77};
init_data[246] = {1'b1, 8'h68};
init_data[247] = {1'b1, 8'h00}; // write 0x00 to 0x0268
init_data[248] = {1'b1, 8'h00}; // write 0x00 to 0x0269
init_data[249] = {1'b1, 8'h00}; // write 0x00 to 0x026a
init_data[250] = {1'b1, 8'h66}; // write 0x66 to 0x026b
init_data[251] = {1'b1, 8'h70}; // write 0x70 to 0x026c
init_data[252] = {1'b1, 8'h67}; // write 0x67 to 0x026d
init_data[253] = {1'b1, 8'h61}; // write 0x61 to 0x026e
init_data[254] = {1'b1, 8'h00}; // write 0x00 to 0x026f
init_data[255] = {1'b1, 8'h00}; // write 0x00 to 0x0270
init_data[256] = {1'b1, 8'h00}; // write 0x00 to 0x0271
init_data[257] = {1'b1, 8'h00}; // write 0x00 to 0x0272
init_data[258] = {2'b01, 7'h77};
init_data[259] = {1'b1, 8'h01};
init_data[260] = {1'b1, 8'h03}; // set page 0x03
init_data[261] = {2'b01, 7'h77};
init_data[262] = {1'b1, 8'h02};
init_data[263] = {1'b1, 8'h00}; // write 0x00 to 0x0302
init_data[264] = {1'b1, 8'h00}; // write 0x00 to 0x0303
init_data[265] = {1'b1, 8'h00}; // write 0x00 to 0x0304
init_data[266] = {1'b1, 8'h80}; // write 0x80 to 0x0305
init_data[267] = {1'b1, 8'h14}; // write 0x14 to 0x0306
init_data[268] = {1'b1, 8'h00}; // write 0x00 to 0x0307
init_data[269] = {1'b1, 8'h00}; // write 0x00 to 0x0308
init_data[270] = {1'b1, 8'h00}; // write 0x00 to 0x0309
init_data[271] = {1'b1, 8'h00}; // write 0x00 to 0x030a
init_data[272] = {1'b1, 8'h80}; // write 0x80 to 0x030b
init_data[273] = {1'b1, 8'h00}; // write 0x00 to 0x030c
init_data[274] = {1'b1, 8'h00}; // write 0x00 to 0x030d
init_data[275] = {1'b1, 8'h00}; // write 0x00 to 0x030e
init_data[276] = {1'b1, 8'h00}; // write 0x00 to 0x030f
init_data[277] = {1'b1, 8'h80}; // write 0x80 to 0x0310
init_data[278] = {1'b1, 8'h14}; // write 0x14 to 0x0311
init_data[279] = {1'b1, 8'h00}; // write 0x00 to 0x0312
init_data[280] = {1'b1, 8'h00}; // write 0x00 to 0x0313
init_data[281] = {1'b1, 8'h00}; // write 0x00 to 0x0314
init_data[282] = {1'b1, 8'h00}; // write 0x00 to 0x0315
init_data[283] = {1'b1, 8'h80}; // write 0x80 to 0x0316
init_data[284] = {1'b1, 8'h00}; // write 0x00 to 0x0317
init_data[285] = {1'b1, 8'h00}; // write 0x00 to 0x0318
init_data[286] = {1'b1, 8'h00}; // write 0x00 to 0x0319
init_data[287] = {1'b1, 8'h00}; // write 0x00 to 0x031a
init_data[288] = {1'b1, 8'h80}; // write 0x80 to 0x031b
init_data[289] = {1'b1, 8'h14}; // write 0x14 to 0x031c
init_data[290] = {1'b1, 8'h00}; // write 0x00 to 0x031d
init_data[291] = {1'b1, 8'h00}; // write 0x00 to 0x031e
init_data[292] = {1'b1, 8'h00}; // write 0x00 to 0x031f
init_data[293] = {1'b1, 8'h00}; // write 0x00 to 0x0320
init_data[294] = {1'b1, 8'h80}; // write 0x80 to 0x0321
init_data[295] = {1'b1, 8'h00}; // write 0x00 to 0x0322
init_data[296] = {1'b1, 8'h00}; // write 0x00 to 0x0323
init_data[297] = {1'b1, 8'h00}; // write 0x00 to 0x0324
init_data[298] = {1'b1, 8'h00}; // write 0x00 to 0x0325
init_data[299] = {1'b1, 8'h80}; // write 0x80 to 0x0326
init_data[300] = {1'b1, 8'h14}; // write 0x14 to 0x0327
init_data[301] = {1'b1, 8'h00}; // write 0x00 to 0x0328
init_data[302] = {1'b1, 8'h00}; // write 0x00 to 0x0329
init_data[303] = {1'b1, 8'h00}; // write 0x00 to 0x032a
init_data[304] = {1'b1, 8'h00}; // write 0x00 to 0x032b
init_data[305] = {1'b1, 8'h80}; // write 0x80 to 0x032c
init_data[306] = {1'b1, 8'h00}; // write 0x00 to 0x032d
init_data[307] = {1'b1, 8'h00}; // write 0x00 to 0x032e
init_data[308] = {1'b1, 8'h00}; // write 0x00 to 0x032f
init_data[309] = {1'b1, 8'h10}; // write 0x10 to 0x0330
init_data[310] = {1'b1, 8'h42}; // write 0x42 to 0x0331
init_data[311] = {1'b1, 8'h08}; // write 0x08 to 0x0332
init_data[312] = {1'b1, 8'h00}; // write 0x00 to 0x0333
init_data[313] = {1'b1, 8'h00}; // write 0x00 to 0x0334
init_data[314] = {1'b1, 8'h00}; // write 0x00 to 0x0335
init_data[315] = {1'b1, 8'h00}; // write 0x00 to 0x0336
init_data[316] = {1'b1, 8'h80}; // write 0x80 to 0x0337
init_data[317] = {1'b1, 8'h00}; // write 0x00 to 0x0338
init_data[318] = {1'b1, 8'h1f}; // write 0x1f to 0x0339
init_data[319] = {2'b01, 7'h77};
init_data[320] = {1'b1, 8'h3b};
init_data[321] = {1'b1, 8'h00}; // write 0x00 to 0x033b
init_data[322] = {1'b1, 8'h00}; // write 0x00 to 0x033c
init_data[323] = {1'b1, 8'h00}; // write 0x00 to 0x033d
init_data[324] = {1'b1, 8'h00}; // write 0x00 to 0x033e
init_data[325] = {1'b1, 8'h00}; // write 0x00 to 0x033f
init_data[326] = {1'b1, 8'h00}; // write 0x00 to 0x0340
init_data[327] = {1'b1, 8'h00}; // write 0x00 to 0x0341
init_data[328] = {1'b1, 8'h00}; // write 0x00 to 0x0342
init_data[329] = {1'b1, 8'h00}; // write 0x00 to 0x0343
init_data[330] = {1'b1, 8'h00}; // write 0x00 to 0x0344
init_data[331] = {1'b1, 8'h00}; // write 0x00 to 0x0345
init_data[332] = {1'b1, 8'h00}; // write 0x00 to 0x0346
init_data[333] = {1'b1, 8'h00}; // write 0x00 to 0x0347
init_data[334] = {1'b1, 8'h00}; // write 0x00 to 0x0348
init_data[335] = {1'b1, 8'h00}; // write 0x00 to 0x0349
init_data[336] = {1'b1, 8'h00}; // write 0x00 to 0x034a
init_data[337] = {1'b1, 8'h00}; // write 0x00 to 0x034b
init_data[338] = {1'b1, 8'h00}; // write 0x00 to 0x034c
init_data[339] = {1'b1, 8'h00}; // write 0x00 to 0x034d
init_data[340] = {1'b1, 8'h00}; // write 0x00 to 0x034e
init_data[341] = {1'b1, 8'h00}; // write 0x00 to 0x034f
init_data[342] = {1'b1, 8'h00}; // write 0x00 to 0x0350
init_data[343] = {1'b1, 8'h00}; // write 0x00 to 0x0351
init_data[344] = {1'b1, 8'h00}; // write 0x00 to 0x0352
init_data[345] = {1'b1, 8'h00}; // write 0x00 to 0x0353
init_data[346] = {1'b1, 8'h00}; // write 0x00 to 0x0354
init_data[347] = {1'b1, 8'h00}; // write 0x00 to 0x0355
init_data[348] = {1'b1, 8'h00}; // write 0x00 to 0x0356
init_data[349] = {1'b1, 8'h00}; // write 0x00 to 0x0357
init_data[350] = {1'b1, 8'h00}; // write 0x00 to 0x0358
init_data[351] = {1'b1, 8'h00}; // write 0x00 to 0x0359
init_data[352] = {1'b1, 8'h00}; // write 0x00 to 0x035a
init_data[353] = {1'b1, 8'h00}; // write 0x00 to 0x035b
init_data[354] = {1'b1, 8'h00}; // write 0x00 to 0x035c
init_data[355] = {1'b1, 8'h00}; // write 0x00 to 0x035d
init_data[356] = {1'b1, 8'h00}; // write 0x00 to 0x035e
init_data[357] = {1'b1, 8'h00}; // write 0x00 to 0x035f
init_data[358] = {1'b1, 8'h00}; // write 0x00 to 0x0360
init_data[359] = {1'b1, 8'h00}; // write 0x00 to 0x0361
init_data[360] = {1'b1, 8'h00}; // write 0x00 to 0x0362
init_data[361] = {2'b01, 7'h77};
init_data[362] = {1'b1, 8'h01};
init_data[363] = {1'b1, 8'h08}; // set page 0x08
init_data[364] = {2'b01, 7'h77};
init_data[365] = {1'b1, 8'h02};
init_data[366] = {1'b1, 8'h00}; // write 0x00 to 0x0802
init_data[367] = {1'b1, 8'h00}; // write 0x00 to 0x0803
init_data[368] = {1'b1, 8'h00}; // write 0x00 to 0x0804
init_data[369] = {1'b1, 8'h00}; // write 0x00 to 0x0805
init_data[370] = {1'b1, 8'h00}; // write 0x00 to 0x0806
init_data[371] = {1'b1, 8'h00}; // write 0x00 to 0x0807
init_data[372] = {1'b1, 8'h00}; // write 0x00 to 0x0808
init_data[373] = {1'b1, 8'h00}; // write 0x00 to 0x0809
init_data[374] = {1'b1, 8'h00}; // write 0x00 to 0x080a
init_data[375] = {1'b1, 8'h00}; // write 0x00 to 0x080b
init_data[376] = {1'b1, 8'h00}; // write 0x00 to 0x080c
init_data[377] = {1'b1, 8'h00}; // write 0x00 to 0x080d
init_data[378] = {1'b1, 8'h00}; // write 0x00 to 0x080e
init_data[379] = {1'b1, 8'h00}; // write 0x00 to 0x080f
init_data[380] = {1'b1, 8'h00}; // write 0x00 to 0x0810
init_data[381] = {1'b1, 8'h00}; // write 0x00 to 0x0811
init_data[382] = {1'b1, 8'h00}; // write 0x00 to 0x0812
init_data[383] = {1'b1, 8'h00}; // write 0x00 to 0x0813
init_data[384] = {1'b1, 8'h00}; // write 0x00 to 0x0814
init_data[385] = {1'b1, 8'h00}; // write 0x00 to 0x0815
init_data[386] = {1'b1, 8'h00}; // write 0x00 to 0x0816
init_data[387] = {1'b1, 8'h00}; // write 0x00 to 0x0817
init_data[388] = {1'b1, 8'h00}; // write 0x00 to 0x0818
init_data[389] = {1'b1, 8'h00}; // write 0x00 to 0x0819
init_data[390] = {1'b1, 8'h00}; // write 0x00 to 0x081a
init_data[391] = {1'b1, 8'h00}; // write 0x00 to 0x081b
init_data[392] = {1'b1, 8'h00}; // write 0x00 to 0x081c
init_data[393] = {1'b1, 8'h00}; // write 0x00 to 0x081d
init_data[394] = {1'b1, 8'h00}; // write 0x00 to 0x081e
init_data[395] = {1'b1, 8'h00}; // write 0x00 to 0x081f
init_data[396] = {1'b1, 8'h00}; // write 0x00 to 0x0820
init_data[397] = {1'b1, 8'h00}; // write 0x00 to 0x0821
init_data[398] = {1'b1, 8'h00}; // write 0x00 to 0x0822
init_data[399] = {1'b1, 8'h00}; // write 0x00 to 0x0823
init_data[400] = {1'b1, 8'h00}; // write 0x00 to 0x0824
init_data[401] = {1'b1, 8'h00}; // write 0x00 to 0x0825
init_data[402] = {1'b1, 8'h00}; // write 0x00 to 0x0826
init_data[403] = {1'b1, 8'h00}; // write 0x00 to 0x0827
init_data[404] = {1'b1, 8'h00}; // write 0x00 to 0x0828
init_data[405] = {1'b1, 8'h00}; // write 0x00 to 0x0829
init_data[406] = {1'b1, 8'h00}; // write 0x00 to 0x082a
init_data[407] = {1'b1, 8'h00}; // write 0x00 to 0x082b
init_data[408] = {1'b1, 8'h00}; // write 0x00 to 0x082c
init_data[409] = {1'b1, 8'h00}; // write 0x00 to 0x082d
init_data[410] = {1'b1, 8'h00}; // write 0x00 to 0x082e
init_data[411] = {1'b1, 8'h00}; // write 0x00 to 0x082f
init_data[412] = {1'b1, 8'h00}; // write 0x00 to 0x0830
init_data[413] = {1'b1, 8'h00}; // write 0x00 to 0x0831
init_data[414] = {1'b1, 8'h00}; // write 0x00 to 0x0832
init_data[415] = {1'b1, 8'h00}; // write 0x00 to 0x0833
init_data[416] = {1'b1, 8'h00}; // write 0x00 to 0x0834
init_data[417] = {1'b1, 8'h00}; // write 0x00 to 0x0835
init_data[418] = {1'b1, 8'h00}; // write 0x00 to 0x0836
init_data[419] = {1'b1, 8'h00}; // write 0x00 to 0x0837
init_data[420] = {1'b1, 8'h00}; // write 0x00 to 0x0838
init_data[421] = {1'b1, 8'h00}; // write 0x00 to 0x0839
init_data[422] = {1'b1, 8'h00}; // write 0x00 to 0x083a
init_data[423] = {1'b1, 8'h00}; // write 0x00 to 0x083b
init_data[424] = {1'b1, 8'h00}; // write 0x00 to 0x083c
init_data[425] = {1'b1, 8'h00}; // write 0x00 to 0x083d
init_data[426] = {1'b1, 8'h00}; // write 0x00 to 0x083e
init_data[427] = {1'b1, 8'h00}; // write 0x00 to 0x083f
init_data[428] = {1'b1, 8'h00}; // write 0x00 to 0x0840
init_data[429] = {1'b1, 8'h00}; // write 0x00 to 0x0841
init_data[430] = {1'b1, 8'h00}; // write 0x00 to 0x0842
init_data[431] = {1'b1, 8'h00}; // write 0x00 to 0x0843
init_data[432] = {1'b1, 8'h00}; // write 0x00 to 0x0844
init_data[433] = {1'b1, 8'h00}; // write 0x00 to 0x0845
init_data[434] = {1'b1, 8'h00}; // write 0x00 to 0x0846
init_data[435] = {1'b1, 8'h00}; // write 0x00 to 0x0847
init_data[436] = {1'b1, 8'h00}; // write 0x00 to 0x0848
init_data[437] = {1'b1, 8'h00}; // write 0x00 to 0x0849
init_data[438] = {1'b1, 8'h00}; // write 0x00 to 0x084a
init_data[439] = {1'b1, 8'h00}; // write 0x00 to 0x084b
init_data[440] = {1'b1, 8'h00}; // write 0x00 to 0x084c
init_data[441] = {1'b1, 8'h00}; // write 0x00 to 0x084d
init_data[442] = {1'b1, 8'h00}; // write 0x00 to 0x084e
init_data[443] = {1'b1, 8'h00}; // write 0x00 to 0x084f
init_data[444] = {1'b1, 8'h00}; // write 0x00 to 0x0850
init_data[445] = {1'b1, 8'h00}; // write 0x00 to 0x0851
init_data[446] = {1'b1, 8'h00}; // write 0x00 to 0x0852
init_data[447] = {1'b1, 8'h00}; // write 0x00 to 0x0853
init_data[448] = {1'b1, 8'h00}; // write 0x00 to 0x0854
init_data[449] = {1'b1, 8'h00}; // write 0x00 to 0x0855
init_data[450] = {1'b1, 8'h00}; // write 0x00 to 0x0856
init_data[451] = {1'b1, 8'h00}; // write 0x00 to 0x0857
init_data[452] = {1'b1, 8'h00}; // write 0x00 to 0x0858
init_data[453] = {1'b1, 8'h00}; // write 0x00 to 0x0859
init_data[454] = {1'b1, 8'h00}; // write 0x00 to 0x085a
init_data[455] = {1'b1, 8'h00}; // write 0x00 to 0x085b
init_data[456] = {1'b1, 8'h00}; // write 0x00 to 0x085c
init_data[457] = {1'b1, 8'h00}; // write 0x00 to 0x085d
init_data[458] = {1'b1, 8'h00}; // write 0x00 to 0x085e
init_data[459] = {1'b1, 8'h00}; // write 0x00 to 0x085f
init_data[460] = {1'b1, 8'h00}; // write 0x00 to 0x0860
init_data[461] = {1'b1, 8'h00}; // write 0x00 to 0x0861
init_data[462] = {2'b01, 7'h77};
init_data[463] = {1'b1, 8'h01};
init_data[464] = {1'b1, 8'h09}; // set page 0x09
init_data[465] = {2'b01, 7'h77};
init_data[466] = {1'b1, 8'h0e};
init_data[467] = {1'b1, 8'h00}; // write 0x00 to 0x090e
init_data[468] = {2'b01, 7'h77};
init_data[469] = {1'b1, 8'h1c};
init_data[470] = {1'b1, 8'h04}; // write 0x04 to 0x091c
init_data[471] = {2'b01, 7'h77};
init_data[472] = {1'b1, 8'h43};
init_data[473] = {1'b1, 8'h00}; // write 0x00 to 0x0943
init_data[474] = {2'b01, 7'h77};
init_data[475] = {1'b1, 8'h49};
init_data[476] = {1'b1, 8'h03}; // write 0x03 to 0x0949
init_data[477] = {1'b1, 8'h30}; // write 0x30 to 0x094a
init_data[478] = {2'b01, 7'h77};
init_data[479] = {1'b1, 8'h4e};
init_data[480] = {1'b1, 8'h49}; // write 0x49 to 0x094e
init_data[481] = {1'b1, 8'h02}; // write 0x02 to 0x094f
init_data[482] = {2'b01, 7'h77};
init_data[483] = {1'b1, 8'h5e};
init_data[484] = {1'b1, 8'h00}; // write 0x00 to 0x095e
init_data[485] = {2'b01, 7'h77};
init_data[486] = {1'b1, 8'h01};
init_data[487] = {1'b1, 8'h0a}; // set page 0x0a
init_data[488] = {2'b01, 7'h77};
init_data[489] = {1'b1, 8'h02};
init_data[490] = {1'b1, 8'h00}; // write 0x00 to 0x0a02
init_data[491] = {1'b1, 8'h1f}; // write 0x1f to 0x0a03
init_data[492] = {1'b1, 8'h0f}; // write 0x0f to 0x0a04
init_data[493] = {1'b1, 8'h1f}; // write 0x1f to 0x0a05
init_data[494] = {2'b01, 7'h77};
init_data[495] = {1'b1, 8'h14};
init_data[496] = {1'b1, 8'h00}; // write 0x00 to 0x0a14
init_data[497] = {2'b01, 7'h77};
init_data[498] = {1'b1, 8'h1a};
init_data[499] = {1'b1, 8'h00}; // write 0x00 to 0x0a1a
init_data[500] = {2'b01, 7'h77};
init_data[501] = {1'b1, 8'h20};
init_data[502] = {1'b1, 8'h00}; // write 0x00 to 0x0a20
init_data[503] = {2'b01, 7'h77};
init_data[504] = {1'b1, 8'h26};
init_data[505] = {1'b1, 8'h00}; // write 0x00 to 0x0a26
init_data[506] = {2'b01, 7'h77};
init_data[507] = {1'b1, 8'h2c};
init_data[508] = {1'b1, 8'h00}; // write 0x00 to 0x0a2c
init_data[509] = {2'b01, 7'h77};
init_data[510] = {1'b1, 8'h01};
init_data[511] = {1'b1, 8'h0b}; // set page 0x0b
init_data[512] = {2'b01, 7'h77};
init_data[513] = {1'b1, 8'h44};
init_data[514] = {1'b1, 8'h0f}; // write 0x0f to 0x0b44
init_data[515] = {2'b01, 7'h77};
init_data[516] = {1'b1, 8'h4a};
init_data[517] = {1'b1, 8'h00}; // write 0x00 to 0x0b4a
init_data[518] = {2'b01, 7'h77};
init_data[519] = {1'b1, 8'h57};
init_data[520] = {1'b1, 8'ha5}; // write 0xa5 to 0x0b57
init_data[521] = {1'b1, 8'h00}; // write 0x00 to 0x0b58
// End configuration registers
//
// Start configuration postamble
init_data[522] = {2'b01, 7'h77};
init_data[523] = {1'b1, 8'h01};
init_data[524] = {1'b1, 8'h00}; // set page 0x00
init_data[525] = {2'b01, 7'h77};
init_data[526] = {1'b1, 8'h1c};
init_data[527] = {1'b1, 8'h01}; // write 0x01 to 0x001c
init_data[528] = {2'b01, 7'h77};
init_data[529] = {1'b1, 8'h01};
init_data[530] = {1'b1, 8'h0b}; // set page 0x0b
init_data[531] = {2'b01, 7'h77};
init_data[532] = {1'b1, 8'h24};
init_data[533] = {1'b1, 8'hc3}; // write 0xc3 to 0x0b24
init_data[534] = {1'b1, 8'h02}; // write 0x02 to 0x0b25
// End configuration postamble
init_data[535] = 9'd0; // end
end
localparam [3:0]
STATE_IDLE = 3'd0,
STATE_RUN = 3'd1,
STATE_TABLE_1 = 3'd2,
STATE_TABLE_2 = 3'd3,
STATE_TABLE_3 = 3'd4;
reg [4:0] state_reg = STATE_IDLE, state_next;
parameter AW = $clog2(INIT_DATA_LEN);
reg [8:0] init_data_reg = 9'd0;
reg [AW-1:0] address_reg = {AW{1'b0}}, address_next;
reg [AW-1:0] address_ptr_reg = {AW{1'b0}}, address_ptr_next;
reg [AW-1:0] data_ptr_reg = {AW{1'b0}}, data_ptr_next;
reg [6:0] cur_address_reg = 7'd0, cur_address_next;
reg [31:0] delay_counter_reg = 32'd0, delay_counter_next;
reg [6:0] m_axis_cmd_address_reg = 7'd0, m_axis_cmd_address_next;
reg m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next;
reg m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next;
reg m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next;
reg m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next;
reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next;
reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next;
reg start_flag_reg = 1'b0, start_flag_next;
reg busy_reg = 1'b0;
assign m_axis_cmd_address = m_axis_cmd_address_reg;
assign m_axis_cmd_start = m_axis_cmd_start_reg;
assign m_axis_cmd_read = 1'b0;
assign m_axis_cmd_write = m_axis_cmd_write_reg;
assign m_axis_cmd_write_multiple = 1'b0;
assign m_axis_cmd_stop = m_axis_cmd_stop_reg;
assign m_axis_cmd_valid = m_axis_cmd_valid_reg;
assign m_axis_data_tdata = m_axis_data_tdata_reg;
assign m_axis_data_tvalid = m_axis_data_tvalid_reg;
assign m_axis_data_tlast = 1'b1;
assign busy = busy_reg;
always @* begin
state_next = STATE_IDLE;
address_next = address_reg;
address_ptr_next = address_ptr_reg;
data_ptr_next = data_ptr_reg;
cur_address_next = cur_address_reg;
delay_counter_next = delay_counter_reg;
m_axis_cmd_address_next = m_axis_cmd_address_reg;
m_axis_cmd_start_next = m_axis_cmd_start_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready);
m_axis_cmd_write_next = m_axis_cmd_write_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready);
m_axis_cmd_stop_next = m_axis_cmd_stop_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready);
m_axis_cmd_valid_next = m_axis_cmd_valid_reg & ~m_axis_cmd_ready;
m_axis_data_tdata_next = m_axis_data_tdata_reg;
m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready;
start_flag_next = start_flag_reg;
if (m_axis_cmd_valid | m_axis_data_tvalid) begin
// wait for output registers to clear
state_next = state_reg;
end else if (delay_counter_reg != 0) begin
// delay
delay_counter_next = delay_counter_reg - 1;
state_next = state_reg;
end else begin
case (state_reg)
STATE_IDLE: begin
// wait for start signal
if (~start_flag_reg & start) begin
address_next = {AW{1'b0}};
start_flag_next = 1'b1;
state_next = STATE_RUN;
end else begin
state_next = STATE_IDLE;
end
end
STATE_RUN: begin
// process commands
if (init_data_reg[8] == 1'b1) begin
// write data
m_axis_cmd_write_next = 1'b1;
m_axis_cmd_stop_next = 1'b0;
m_axis_cmd_valid_next = 1'b1;
m_axis_data_tdata_next = init_data_reg[7:0];
m_axis_data_tvalid_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg[8:7] == 2'b01) begin
// write address
m_axis_cmd_address_next = init_data_reg[6:0];
m_axis_cmd_start_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg[8:4] == 5'b00001) begin
// delay
delay_counter_next = 32'd1 << (init_data_reg[3:0]+16);
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'b001000001) begin
// send stop
m_axis_cmd_write_next = 1'b0;
m_axis_cmd_start_next = 1'b0;
m_axis_cmd_stop_next = 1'b1;
m_axis_cmd_valid_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 9'd0) begin
// stop
m_axis_cmd_start_next = 1'b0;
m_axis_cmd_write_next = 1'b0;
m_axis_cmd_stop_next = 1'b1;
m_axis_cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_RUN;
end
end
STATE_TABLE_1: begin
// find address table start
if (init_data_reg == 9'b000001000) begin
// address table start
address_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_2;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 1) begin
// exit mode
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'd0) begin
// stop
m_axis_cmd_start_next = 1'b0;
m_axis_cmd_write_next = 1'b0;
m_axis_cmd_stop_next = 1'b1;
m_axis_cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end
end
STATE_TABLE_2: begin
// find next address
if (init_data_reg[8:7] == 2'b01) begin
// write address command
// store address and move to data table
cur_address_next = init_data_reg[6:0];
address_ptr_next = address_reg + 1;
address_next = data_ptr_reg;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 9'd1) begin
// exit mode
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'd0) begin
// stop
m_axis_cmd_start_next = 1'b0;
m_axis_cmd_write_next = 1'b0;
m_axis_cmd_stop_next = 1'b1;
m_axis_cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_TABLE_2;
end
end
STATE_TABLE_3: begin
// process data table with selected address
if (init_data_reg[8] == 1'b1) begin
// write data
m_axis_cmd_write_next = 1'b1;
m_axis_cmd_stop_next = 1'b0;
m_axis_cmd_valid_next = 1'b1;
m_axis_data_tdata_next = init_data_reg[7:0];
m_axis_data_tvalid_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg[8:7] == 2'b01) begin
// write address
m_axis_cmd_address_next = init_data_reg[6:0];
m_axis_cmd_start_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b000000011) begin
// write current address
m_axis_cmd_address_next = cur_address_reg;
m_axis_cmd_start_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b001000001) begin
// send stop
m_axis_cmd_write_next = 1'b0;
m_axis_cmd_start_next = 1'b0;
m_axis_cmd_stop_next = 1'b1;
m_axis_cmd_valid_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 9'b000001000) begin
// address table start
address_next = address_ptr_reg;
state_next = STATE_TABLE_2;
end else if (init_data_reg == 9'd1) begin
// exit mode
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'd0) begin
// stop
m_axis_cmd_start_next = 1'b0;
m_axis_cmd_write_next = 1'b0;
m_axis_cmd_stop_next = 1'b1;
m_axis_cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end
end
endcase
end
end
always @(posedge clk) begin
state_reg <= state_next;
// read init_data ROM
init_data_reg <= init_data[address_next];
address_reg <= address_next;
address_ptr_reg <= address_ptr_next;
data_ptr_reg <= data_ptr_next;
cur_address_reg <= cur_address_next;
delay_counter_reg <= delay_counter_next;
m_axis_cmd_address_reg <= m_axis_cmd_address_next;
m_axis_cmd_start_reg <= m_axis_cmd_start_next;
m_axis_cmd_write_reg <= m_axis_cmd_write_next;
m_axis_cmd_stop_reg <= m_axis_cmd_stop_next;
m_axis_cmd_valid_reg <= m_axis_cmd_valid_next;
m_axis_data_tdata_reg <= m_axis_data_tdata_next;
m_axis_data_tvalid_reg <= m_axis_data_tvalid_next;
start_flag_reg <= start & start_flag_next;
busy_reg <= (state_reg != STATE_IDLE);
if (rst) begin
state_reg <= STATE_IDLE;
init_data_reg <= 9'd0;
address_reg <= {AW{1'b0}};
address_ptr_reg <= {AW{1'b0}};
data_ptr_reg <= {AW{1'b0}};
cur_address_reg <= 7'd0;
delay_counter_reg <= 32'd0;
m_axis_cmd_valid_reg <= 1'b0;
m_axis_data_tvalid_reg <= 1'b0;
start_flag_reg <= 1'b0;
busy_reg <= 1'b0;
end
end
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1P_BLACKBOX_V
`define SKY130_FD_SC_HDLL__INPUTISO1P_BLACKBOX_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso1p (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1P_BLACKBOX_V
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
`include "defines.v"
module kotku_ml403 (
`ifdef DEBUG
output rs_,
output rw_,
output e_,
output [7:4] db_,
input butc_,
input bute_,
input butw_,
input butn_,
input buts_,
output trx_,
`endif
output tft_lcd_clk_,
output [ 1:0] tft_lcd_r_,
output [ 1:0] tft_lcd_g_,
output [ 1:0] tft_lcd_b_,
output tft_lcd_hsync_,
output tft_lcd_vsync_,
input sys_clk_in_,
output sram_clk_,
output [20:0] sram_flash_addr_,
inout [31:0] sram_flash_data_,
output sram_flash_oe_n_,
output sram_flash_we_n_,
output [ 3:0] sram_bw_,
output sram_cen_,
output sram_adv_ld_n_,
output flash_ce2_,
inout ps2_clk_,
inout ps2_data_
);
// Net declarations
wire clk;
wire sys_clk;
wire rst2;
wire rst_lck;
wire [15:0] dat_i;
wire [15:0] dat_o;
wire [19:1] adr;
wire we;
wire tga;
wire stb;
wire ack;
wire [15:0] io_dat_i;
wire [ 1:0] sel;
wire cyc;
wire [ 7:0] keyb_dat_o;
wire keyb_io_arena;
wire keyb_io_status;
wire keyb_arena;
wire [15:0] vdu_dat_o;
wire vdu_ack_o;
wire vdu_mem_arena;
wire vdu_io_arena;
wire vdu_arena;
wire [15:0] flash_dat_o;
wire flash_stb;
wire flash_ack;
wire flash_mem_arena;
wire flash_io_arena;
wire flash_arena;
wire [15:0] zbt_dat_o;
wire zbt_stb;
wire zbt_ack;
wire [20:0] flash_addr_;
wire [20:0] sram_addr_;
wire flash_we_n_;
wire sram_we_n_;
wire intr;
wire inta;
wire clk_100M;
wire rst;
wire [15:0] vdu_dat_i;
wire [11:1] vdu_adr_i;
wire vdu_we_i;
wire [ 1:0] vdu_sel_i;
wire vdu_stb_i;
wire vdu_tga_i;
wire [19:1] zbt_adr_i;
wire zbt_we_i;
wire [ 1:0] zbt_sel_i;
wire zbt_stb_i;
`ifdef DEBUG
reg [31:0] cnt_time;
wire [35:0] control0;
wire [ 5:0] funct;
wire [ 2:0] state, next_state;
wire [15:0] x, y;
wire [15:0] imm;
wire [63:0] f1, f2;
wire [15:0] m1, m2;
wire [19:0] pc;
wire [15:0] cs, ip;
wire [15:0] aluo;
wire [ 2:0] cnt;
wire op;
wire block;
wire cpu_block;
wire clk_921600;
wire [15:0] ax, dx, bp, si, es;
wire [15:0] c;
wire [ 3:0] addr_c;
wire [15:0] cpu_dat_o;
wire [15:0] d;
wire [ 3:0] addr_d;
wire byte_op;
wire [ 8:0] flags;
wire [15:0] dbg_vdu_dat_o;
wire [11:1] dbg_vdu_adr_o;
wire dbg_vdu_we_o;
wire dbg_vdu_stb_o;
wire [ 1:0] dbg_vdu_sel_o;
wire dbg_vdu_tga_o;
wire [19:1] dbg_zbt_adr_o;
wire dbg_zbt_we_o;
wire [ 1:0] dbg_zbt_sel_o;
wire dbg_zbt_stb_o;
wire [ 2:0] old_zet_st;
wire [ 4:0] pack;
wire [19:0] tr_dat;
wire tr_new_pc;
wire tr_st;
wire tr_stb;
wire tr_ack;
wire addr_st;
wire end_seq;
wire ext_int;
wire cpu_block2;
`endif
// Register declarations
reg [15:0] io_reg;
reg [ 1:0] vdu_stb_sync;
reg [ 1:0] vdu_ack_sync;
// Module instantiations
clock c0 (
.clk_100M (clk_100M),
.sys_clk_in_ (sys_clk_in_),
.clk (sys_clk),
.vdu_clk (tft_lcd_clk_),
.rst (rst_lck)
);
vdu vdu0 (
// Wishbone signals
.wb_clk_i (tft_lcd_clk_), // 25 Mhz VDU clock
.wb_rst_i (rst2),
.wb_dat_i (vdu_dat_i),
.wb_dat_o (vdu_dat_o),
.wb_adr_i (vdu_adr_i),
.wb_we_i (vdu_we_i),
.wb_tga_i (vdu_tga_i),
.wb_sel_i (vdu_sel_i),
.wb_stb_i (vdu_stb_sync[1]),
.wb_cyc_i (vdu_stb_sync[1]),
.wb_ack_o (vdu_ack_o),
// VGA pad signals
.vga_red_o (tft_lcd_r_),
.vga_green_o (tft_lcd_g_),
.vga_blue_o (tft_lcd_b_),
.horiz_sync (tft_lcd_hsync_),
.vert_sync (tft_lcd_vsync_)
);
flash_cntrl fc0 (
// Wishbone slave interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_o),
.wb_dat_o (flash_dat_o),
.wb_adr_i (adr[16:1]),
.wb_we_i (we),
.wb_tga_i (tga),
.wb_stb_i (flash_stb),
.wb_cyc_i (flash_stb),
.wb_ack_o (flash_ack),
// Pad signals
.flash_addr_ (flash_addr_),
.flash_data_ (sram_flash_data_[15:0]),
.flash_we_n_ (flash_we_n_),
.flash_ce2_ (flash_ce2_)
);
zbt_cntrl zbt0 (
`ifdef DEBUG
.cnt (cnt),
.op (op),
`endif
.wb_clk_i (clk),
.wb_rst_i (rst2),
.wb_dat_i (dat_o),
.wb_dat_o (zbt_dat_o),
.wb_adr_i (zbt_adr_i),
.wb_we_i (zbt_we_i),
.wb_sel_i (zbt_sel_i),
.wb_stb_i (zbt_stb_i),
.wb_cyc_i (zbt_stb_i),
.wb_ack_o (zbt_ack),
// Pad signals
.sram_clk_ (sram_clk_),
.sram_addr_ (sram_addr_),
.sram_data_ (sram_flash_data_),
.sram_we_n_ (sram_we_n_),
.sram_bw_ (sram_bw_),
.sram_cen_ (sram_cen_),
.sram_adv_ld_n_ (sram_adv_ld_n_)
);
ps2_keyb #(5900, // number of clks for 60usec.
13, // number of bits needed for 60usec. timer
126, // number of clks for debounce
7, // number of bits needed for debounce timer
0 // Trap the shift keys, no event generated
) keyboard0 ( // Instance name
.wb_clk_i (clk_100M),
.wb_rst_i (rst),
.wb_dat_o (keyb_dat_o),
.wb_tgc_o (intr),
.wb_tgc_i (inta),
.ps2_clk_ (ps2_clk_),
.ps2_data_ (ps2_data_)
);
/*
timer timer0 (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_tgc_o (intr),
.wb_tgc_i (inta)
);
*/
cpu zet_proc (
`ifdef DEBUG
.cs (cs),
.ip (ip),
.state (state),
.next_state (next_state),
.iralu (funct),
.x (x),
.y (y),
.imm (imm),
.aluo (aluo),
.ax (ax),
.dx (dx),
.bp (bp),
.si (si),
.es (es),
.dbg_block (cpu_block),
.c (c),
.addr_c (addr_c),
.cpu_dat_o (cpu_dat_o),
.d (d),
.byte_exec (byte_op),
.addr_d (addr_d),
.flags (flags),
.end_seq (end_seq),
.ext_int (ext_int),
.cpu_block (cpu_block2),
`endif
// Wishbone master interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_adr_o (adr),
.wb_we_o (we),
.wb_tga_o (tga),
.wb_sel_o (sel),
.wb_stb_o (stb),
.wb_cyc_o (cyc),
.wb_ack_i (ack),
.wb_tgc_i (intr),
.wb_tgc_o (inta)
);
`ifdef DEBUG
// Module instantiations
icon icon0 (
.CONTROL0 (control0)
);
ila ila0 (
.CONTROL (control0),
.CLK (clk),
.TRIG0 (adr),
.TRIG1 ({dat_o,dat_i}),
.TRIG2 (pc),
.TRIG3 ({clk,we,tga,cyc,stb,ack}),
.TRIG4 (funct),
.TRIG5 ({state,next_state}),
.TRIG6 ({intr,inta,flags,byte_op,addr_d}),
// .TRIG7 (imm),
// .TRIG7 (tr_dat[15:0]),
.TRIG7 (d),
.TRIG8 ({x,y}),
.TRIG9 (aluo),
.TRIG10 (sram_flash_addr_),
.TRIG11 (sram_flash_data_),
.TRIG12 ({sram_flash_oe_n_, sram_flash_we_n_, sram_bw_,
sram_cen_, sram_adv_ld_n_, flash_ce2_}),
.TRIG13 (cnt),
.TRIG14 ({vdu_mem_arena,flash_mem_arena,flash_stb,zbt_stb,op}),
.TRIG15 (cnt_time)
// .TRIG15 ({block,trx_,rst2,rst,tr_ack,tr_stb,tr_st,tr_new_pc,addr_st,11'h0,pack,old_zet_st,tr_dat[19:16]})
);
lcd_display lcd0 (
.f1 (f1), // 1st row
.f2 (f2), // 2nd row
.m1 (m1), // 1st row mask
.m2 (m2), // 2nd row mask
.clk (clk_100M), // 100 Mhz clock
.rst (rst_lck),
// Pad signals
.lcd_rs_ (rs_),
.lcd_rw_ (rw_),
.lcd_e_ (e_),
.lcd_dat_ (db_)
);
hw_dbg dbg0 (
.clk (clk),
.rst_lck (rst2),
.rst (rst),
.butc_ (butc_),
.bute_ (bute_),
.butw_ (butw_),
.butn_ (butn_),
.buts_ (buts_),
.vdu_dat_o (dbg_vdu_dat_o),
.vdu_adr_o (dbg_vdu_adr_o),
.vdu_we_o (dbg_vdu_we_o),
.vdu_stb_o (dbg_vdu_stb_o),
.vdu_sel_o (dbg_vdu_sel_o),
.vdu_tga_o (dbg_vdu_tga_o),
.vdu_ack_i (vdu_ack_sync[1]),
.zbt_dat_i (zbt_dat_o),
.zbt_adr_o (dbg_zbt_adr_o),
.zbt_we_o (dbg_zbt_we_o),
.zbt_sel_o (dbg_zbt_sel_o),
.zbt_stb_o (dbg_zbt_stb_o),
.zbt_ack_i (zbt_ack)
);
clk_uart clk0 (
.clk_100M (clk_100M),
.rst (rst_lck),
.clk_921600 (clk_921600),
.rst2 (rst2)
);
pc_trace pc0 (
.old_zet_st (old_zet_st),
.dat (tr_dat),
.new_pc (tr_new_pc),
.st (tr_st),
.stb (tr_stb),
.ack (tr_ack),
.pack (pack),
.addr_st (addr_st),
.trx_ (trx_),
.clk (clk),
.rst (rst2),
.pc (pc),
.zet_st (state),
.block (block)
);
// Continuous assignments
assign f1 = { 3'b0, rst, 4'h0, io_reg, 4'h0, dat_o, 7'h0, tga, 7'h0, ack, 4'h0 };
assign f2 = { adr, 7'h0, we, 3'h0, stb, 3'h0, cyc, 8'h0, pc };
assign m1 = 16'b1011110111101010;
assign m2 = 16'b1111101110011111;
assign pc = (cs << 4) + ip;
assign vdu_dat_i = rst ? dbg_vdu_dat_o : dat_o;
assign vdu_adr_i = rst ? dbg_vdu_adr_o : adr[11:1];
assign vdu_we_i = rst ? dbg_vdu_we_o : we;
assign vdu_sel_i = rst ? dbg_vdu_sel_o : sel;
assign vdu_stb_i = rst ? dbg_vdu_stb_o : stb & cyc & vdu_arena;
assign vdu_tga_i = rst ? dbg_vdu_tga_o : tga;
assign zbt_adr_i = rst ? dbg_zbt_adr_o : adr;
assign zbt_we_i = rst ? dbg_zbt_we_o : we;
assign zbt_sel_i = rst ? dbg_zbt_sel_o : sel;
assign zbt_stb_i = rst ? dbg_zbt_stb_o : zbt_stb;
`ifdef DEBUG_TRACE
assign cpu_block = block;
`else
assign cpu_block = 1'b0;
`endif
`else
assign vdu_dat_i = dat_o;
assign vdu_adr_i = adr[11:1];
assign vdu_we_i = we;
assign vdu_sel_i = sel;
assign vdu_stb_i = stb & cyc & vdu_arena;
assign vdu_tga_i = tga;
assign zbt_adr_i = adr;
assign zbt_we_i = we;
assign zbt_sel_i = sel;
assign zbt_stb_i = zbt_stb;
assign rst2 = rst_lck;
`endif
`ifdef DEBUG_TRACE
assign clk = clk_921600;
`else
assign clk = sys_clk;
`endif
assign io_dat_i = flash_io_arena ? flash_dat_o
: (vdu_io_arena ? vdu_dat_o
: (keyb_io_arena ? keyb_dat_o
: (keyb_io_status ? 16'h10 : 16'h0)));
assign dat_i = inta ? 16'd9 : (tga ? io_dat_i
: (vdu_mem_arena ? vdu_dat_o
: (flash_mem_arena ? flash_dat_o : zbt_dat_o)));
assign flash_mem_arena = (adr[19:16]==4'hc || adr[19:16]==4'hf);
assign vdu_mem_arena = (adr[19:12]==8'hb8);
assign flash_io_arena = (adr[15:9]==7'b1110_000);
assign vdu_io_arena = (adr[15:4]==12'h03d) &&
((adr[3:1]==3'h2 && we)
|| (adr[3:1]==3'h5 && !we));
assign keyb_io_arena = (adr[15:1]==15'h0030 && !we);
// MS-DOS is reading IO address 0x64 to check the inhibit bit
assign keyb_io_status = (adr[15:1]==15'h0032 && !we);
assign flash_arena = (!tga & flash_mem_arena)
| (tga & flash_io_arena);
assign vdu_arena = (!tga & vdu_mem_arena)
| (tga & vdu_io_arena);
assign keyb_arena = (tga & keyb_io_arena);
assign flash_stb = flash_arena & stb & cyc;
assign zbt_stb = !vdu_mem_arena & !flash_mem_arena
& !tga & stb & cyc;
assign ack = tga ? (flash_io_arena ? flash_ack
: (vdu_io_arena ? vdu_ack_sync[1] : (stb & cyc)))
: (vdu_mem_arena ? vdu_ack_sync[1]
: (flash_mem_arena ? flash_ack : zbt_ack));
assign sram_flash_oe_n_ = 1'b0;
assign sram_flash_addr_ = flash_arena ? flash_addr_
: sram_addr_;
assign sram_flash_we_n_ = flash_arena ? flash_we_n_
: sram_we_n_;
// Behaviour
// vdu_stb_sync[0]
always @(posedge tft_lcd_clk_)
vdu_stb_sync[0] <= vdu_stb_i;
// vdu_stb_sync[1]
always @(posedge clk)
vdu_stb_sync[1] <= vdu_stb_sync[0];
// vdu_ack_sync[0]
always @(posedge clk) vdu_ack_sync[0] <= vdu_ack_o;
// vdu_ack_sync[1]
always @(posedge clk) vdu_ack_sync[1] <= vdu_ack_sync[0];
// io_reg
always @(posedge clk)
io_reg <= rst ? 16'h0
: ((tga && stb && cyc && we && adr[15:8]==8'hf1) ?
dat_o : io_reg );
`ifdef DEBUG
// cnt_time
always @(posedge clk)
cnt_time <= rst ? 32'h0 : (cnt_time + 32'h1);
`else
assign rst = rst_lck;
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__SDFXBP_FUNCTIONAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_hdll__udp_dff_p.v"
`celldefine
module sky130_fd_sc_hdll__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXBP_FUNCTIONAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sat May 27 20:55:50 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_g8_to_rgb888_0_0/system_g8_to_rgb888_0_0_sim_netlist.v
// Design : system_g8_to_rgb888_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_g8_to_rgb888_0_0,g8_to_rgb888,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "g8_to_rgb888,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_g8_to_rgb888_0_0
(g8,
rgb888);
input [7:0]g8;
output [23:0]rgb888;
wire [7:0]g8;
assign rgb888[23:16] = g8;
assign rgb888[15:8] = g8;
assign rgb888[7:0] = g8;
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//SPI interface module (8 bits)
//this is a slave module, clock is controlled by host
//clock is high when bus is idle
//ingoing data is sampled at the positive clock edge
//outgoing data is shifted/changed at the negative clock edge
//msb is sent first
// ____ _ _ _ _
//sck -> |_| |_| |_| |_|
//data -> 777 666 555 444
//sample -> ^ ^ ^ ^
//strobe is asserted at the end of every byte and signals that new data must
//be registered at the out output. At the same time, new data is read from the in input.
//The data at input in is also sent as the first byte after _scs is asserted (without strobe!).
module userio_osd_spi
(
input clk, //pixel clock
input clk7_en,
input clk7n_en,
input _scs, //SPI chip select
input sdi, //SPI data in
output sdo, //SPI data out
input sck, //SPI clock
input [7:0] in, //parallel input data
output reg [7:0] out, //parallel output data
output reg rx, //byte received
output reg cmd, //first byte received
output vld // valid
);
//locals
reg [2:0] bit_cnt; //bit counter
reg [7:0] sdi_reg; //input shift register (rising edge of SPI clock)
reg [7:0] sdo_reg; //output shift register (falling edge of SPI clock)
reg new_byte; //new byte (8 bits) received
reg rx_sync; //synchronization to clk (first stage)
reg first_byte; //first byte is going to be received
// spi valid synchronizers
reg spi_valid=0, spi_valid_sync=0;
always @ (posedge clk) begin
if (clk7_en) begin
{spi_valid, spi_valid_sync} <= #1 {spi_valid_sync, ~_scs};
end
end
assign vld = spi_valid;
//------ input shift register ------//
always @(posedge sck)
sdi_reg <= #1 {sdi_reg[6:0],sdi};
always @(posedge sck)
if (bit_cnt==7)
out <= #1 {sdi_reg[6:0],sdi};
//------ receive bit counter ------//
always @(posedge sck or posedge _scs)
if (_scs)
bit_cnt <= #1 0; //always clear bit counter when CS is not active
else
bit_cnt <= #1 bit_cnt + 3'd1; //increment bit counter when new bit has been received
//----- rx signal ------//
//this signal goes high for one clk clock period just after new byte has been received
//it's synchronous with clk, output data shouldn't change when rx is active
always @(posedge sck or posedge rx)
if (rx)
new_byte <= #1 0; //cleared asynchronously when rx is high (rx is synchronous with clk)
else if (bit_cnt == 3'd7)
new_byte <= #1 1; //set when last bit of a new byte has been just received
always @(posedge clk)
if (clk7n_en) begin
rx_sync <= #1 new_byte; //double synchronization to avoid metastability
end
always @(posedge clk)
if (clk7_en) begin
rx <= #1 rx_sync; //synchronous with clk
end
//------ cmd signal generation ------//
//this signal becomes active after reception of first byte
//when any other byte is received it's deactivated indicating data bytes
always @(posedge sck or posedge _scs)
if (_scs)
first_byte <= #1 1'b1; //set when CS is not active
else if (bit_cnt == 3'd7)
first_byte <= #1 1'b0; //cleared after reception of first byte
always @(posedge sck)
if (bit_cnt == 3'd7)
cmd <= #1 first_byte; //active only when first byte received
//------ serial data output register ------//
always @(negedge sck) //output change on falling SPI clock
if (bit_cnt == 3'd0)
sdo_reg <= #1 in;
else
sdo_reg <= #1 {sdo_reg[6:0],1'b0};
//------ SPI output signal ------//
assign sdo = ~_scs & sdo_reg[7]; //force zero if SPI not selected
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_PP_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fill_diode (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_PP_V |
//MODULE REFERENCE
`define tenv_clock tenv_clock
`define tenv_descstd_device tenv_descstd_device
module tenv_usbdev #(parameter DATA_MAXSIZE=64);
//IFACE
reg rst0_async=1;
reg rst0_sync=1;
wire[1:0] trsac_type;
localparam TYPE_SETUP=0,
TYPE_OUT=1,
TYPE_IN=2;
wire[3:0] trsac_ep;
wire[1:0] trsac_req;
localparam REQ_OK=0,
REQ_ACTIVE=1,
REQ_FAIL=2;
reg[1:0] trsac_reply=0;
localparam ACK=0,
NAK=1,
STALL=2;
reg rfifo_rd=0;
wire rfifo_empty;
wire[7:0] rfifo_rdata;
reg tfifo_wr=0;
wire tfifo_full;
reg[7:0] tfifo_wdata=0;
reg[15:1] ep_enable=15'h7FFF;
reg[15:1] ep_isoch=15'b100_0000_0000_0000;
reg[15:1] ep_intnoretry=15'b000_0010_0000_0000;
reg speed=0;
reg device_wakeup=0;
reg device_addr_wr=0;
reg[6:0] device_addr=0;
reg device_config_wr=0;
reg[7:0] device_config=0;
wire[2:0] device_state;
parameter POWERED=3'd0,
DEFAULT=3'd1,
ADDRESSED=3'd2,
CONFIGURED=3'd3,
SPND_PWR=3'd4,
SPND_DFT=3'd5,
SPND_ADDR=3'd6,
SPND_CONF=3'd7;
wire sof_tick;
wire[10:0] sof_value;
reg[7:0] buffer[DATA_MAXSIZE-1:0];
integer reply_delay=0;
//LOCAL
localparam block_name="tenv_usbdev";
reg[7:0] bm_request_type=0;
reg[7:0] b_request=0;
reg[15:0] w_value=0;
reg[15:0] w_index=0;
reg[15:0] w_length=0;
localparam GET_STATUS=0,
CLEAR_FEATURE=1,
SET_FEATURE=3,
SET_ADDRESS=5,
GET_DESCRIPTOR=6,
SET_DESCRIPTOR=7,
GET_CONFIGURATION=8,
SET_CONFIGURATION=9,
GET_INTERFACE=10,
SET_INTERFACE=11,
SYNCH_FRAME=12;
//TASKS
`include "tenv_usbdev/tenv_usbdev.mntr_trsac_off.v"
`include "tenv_usbdev/tenv_usbdev.mntr_devstate.v"
`include "tenv_usbdev/tenv_usbdev.reset.v"
`include "tenv_usbdev/tenv_usbdev.gen_data.v"
`include "tenv_usbdev/tenv_usbdev.trsac_in.v"
`include "tenv_usbdev/tenv_usbdev.trsac_out.v"
`include "tenv_usbdev/tenv_usbdev.trsac_setup.v"
`include "tenv_usbdev/tenv_usbdev.trfer_in.v"
`include "tenv_usbdev/tenv_usbdev.trfer_out.v"
`include "tenv_usbdev/tenv_usbdev.reqstd_getdesc.v"
`include "tenv_usbdev/tenv_usbdev.reqstd_setconf.v"
`include "tenv_usbdev/tenv_usbdev.reqstd_setaddr.v"
`include "tenv_usbdev/tenv_usbdev.reqstd_clrfeat.v"
endmodule
|
`default_nettype none
`timescale 1ns / 1ps
// Main board module.
module s6atlys(
// Global clock
input wire CLK_100M,
// onboard HDMI OUT
//output wire HDMIOUTCLKP,
//output wire HDMIOUTCLKN,
//output wire HDMIOUTD0P,
//output wire HDMIOUTD0N,
//output wire HDMIOUTD1P,
//output wire HDMIOUTD1N,
//output wire HDMIOUTD2P,
//output wire HDMIOUTD2N,
//output wire HDMIOUTSCL,
//output wire HDMIOUTSDA,
// LEDs
output wire [7:0] LED,
// Switches
input wire [7:0] SW,
// Buttons
input wire [5:0] BTN,
// PMOD Connector
inout wire [7:0] JB
);
//
// Initialize outputs -- remove these when they're actually used
//
// Audio output
//assign AUD_L = 0;
//assign AUD_R = 0;
// VGA output
//assign VGA_R = 0;
//assign VGA_G = 0;
//assign VGA_B = 0;
//assign VGA_HSYNC = 0;
//assign VGA_VSYNC = 0;
//
// Clocks (GameBoy clock runs at ~4.194304 MHz)
//
// FPGABoy runs at 33.33 MHz, mostly to simplify the video controller.
// Certain cycle sensitive modules, such as the CPU and Timer are
// internally clocked down to the GameBoy's normal speed.
//
// Core Clock: 33.33 MHz
wire coreclk, core_clock;
DCM_SP core_clock_dcm (.CLKIN(CLK_100M), .CLKFX(coreclk), .RST(1'b0));
defparam core_clock_dcm.CLKFX_DIVIDE = 6;
defparam core_clock_dcm.CLKFX_MULTIPLY = 2;
defparam core_clock_dcm.CLKDV_DIVIDE = 3.0;
defparam core_clock_dcm.CLKIN_PERIOD = 10.000;
BUFG core_clock_buf (.I(coreclk), .O(core_clock));
// Initial Reset
wire reset_init, reset;
SRL16 reset_sr(.D(1'b0), .CLK(core_clock), .Q(reset_init),
.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1));
// HDMI Clocks
// TODO: No idea what these look like yet.
// Joypad Clock: 1 KHz
wire pulse_1khz;
reg clock_1khz;
divider#(.DELAY(33333)) div_1ms (
.reset(reset_init),
.clock(core_clock),
.enable(pulse_1khz)
);
// CLS Clock: 200 Khz
wire pulse_200khz;
reg clock_200khz;
divider#(.DELAY(166)) div_5us (
.reset(reset_init),
.clock(core_clock),
.enable(pulse_200khz)
);
//
// CPU clock - overflows every 8 cycles
//
reg [2:0] clock_divider;
wire cpu_clock;
BUFG cpu_clock_buf(.I(clock_divider[2]), .O(cpu_clock));
//
// Switches
//
// SW0-SW4 - Breakpoints Switches (Not Implemented)
// SW5 - Step Clock
// SW6 - Step Enable
// SW7 - Power (Reset)
//
wire reset_sync, step_sync, step_enable;
debounce debounce_step_sync(reset_init, core_clock, SW[5], step_sync);
debounce debounce_step_enable(reset_init, core_clock, SW[6], step_enable);
debounce debounce_reset_sync(reset_init, core_clock, !SW[7], reset_sync);
assign reset = (reset_init || reset_sync);
// Game Clock
wire clock;
BUFGMUX clock_mux(.S(step_enable), .O(clock),
.I0(core_clock), .I1(step_sync));
//
// Buttons
//
// BTN0 - Not Implemented
// BTN1 - Joypad
// BTN2 - PC SP
// BTN3 - AF BC
// BTN4 - DE HL
//
reg [1:0] mode;
wire mode0_sync, mode1_sync, mode2_sync, mode3_sync;
debounce debounce_mode0_sync(reset_init, core_clock, BTN[2], mode0_sync);
debounce debounce_mode1_sync(reset_init, core_clock, BTN[3], mode1_sync);
debounce debounce_mode2_sync(reset_init, core_clock, BTN[4], mode2_sync);
debounce debounce_mode3_sync(reset_init, core_clock, BTN[1], mode3_sync);
//
// GameBoy
//
// GB <-> Cartridge + WRAM
wire [15:0] A;
wire [7:0] Di;
wire [7:0] Do;
wire wr_n, rd_n, cs_n;
// GB <-> VRAM
wire [15:0] A_vram;
wire [7:0] Di_vram;
wire [7:0] Do_vram;
wire wr_vram_n, rd_vram_n, cs_vram_n;
// GB <-> Display Adapter
wire [1:0] pixel_data;
wire pixel_clock;
wire pixel_latch;
wire hsync, vsync;
// GB <-> Joypad Adapter
wire [3:0] joypad_data;
wire [1:0] joypad_sel;
// GB <-> Audio Adapter
wire audio_left, audio_right;
// GB <-> CLS SPI
wire [15:0] PC;
wire [15:0] SP;
wire [15:0] AF;
wire [15:0] BC;
wire [15:0] DE;
wire [15:0] HL;
wire [15:0] A_cpu;
wire [7:0] Di_cpu;
wire [7:0] Do_cpu;
gameboy gameboy (
.clock(clock),
.cpu_clock(cpu_clock),
.reset(reset),
.reset_init(reset_init),
.A(A),
.Di(Di),
.Do(Do),
.wr_n(wr_n),
.rd_n(rd_n),
.cs_n(cs_n),
.A_vram(A_vram),
.Di_vram(Di_vram),
.Do_vram(Do_vram),
.wr_vram_n(wr_vram_n),
.rd_vram_n(rd_vram_n),
.cs_vram_n(cs_vram_n),
.pixel_data(pixel_data),
.pixel_clock(pixel_clock),
.pixel_latch(pixel_latch),
.hsync(hsync),
.vsync(vsync),
.joypad_data(joypad_data),
.joypad_sel(joypad_sel),
.audio_left(audio_left),
.audio_right(audio_right),
// debug output
.dbg_led(LED),
.PC(PC),
.SP(SP),
.AF(AF),
.BC(BC),
.DE(DE),
.HL(HL),
.A_cpu(A_cpu),
.Di_cpu(Di_cpu),
.Do_cpu(Do_cpu)
);
// Internal ROMs and RAMs
reg [7:0] tetris_rom [0:32767];
initial begin
$readmemh("data/tetris.hex", tetris_rom, 0, 32767);
end
wire [7:0] Di_wram;
// WRAM
async_mem #(.asz(8), .depth(8192)) wram (
.rd_data(Di_wram),
.wr_clk(clock),
.wr_data(Do),
.wr_cs(!cs_n && !wr_n),
.addr(A),
.rd_cs(!cs_n && !rd_n)
);
// VRAM
async_mem #(.asz(8), .depth(8192)) vram (
.rd_data(Di_vram),
.wr_clk(clock),
.wr_data(Do_vram),
.wr_cs(!cs_vram_n && !wr_vram_n),
.addr(A_vram),
.rd_cs(!cs_vram_n && !rd_vram_n)
);
assign Di = A[14] ? Di_wram : tetris_rom[A];
// Joypad Adapter
wire [15:0] joypad_state;
joypad_snes_adapter joypad_adapter(
.clock(clock_1khz),
.reset(reset),
.button_sel(joypad_sel),
.button_data(joypad_data),
.button_state(joypad_state),
.controller_data(JB[4]),
.controller_clock(JB[5]),
.controller_latch(JB[6])
);
cls_spi cls_spi(
.clock(clock_200khz),
.reset(reset),
.mode(mode),
.ss(JB[0]),
.mosi(JB[1]),
.miso(JB[2]),
.sclk(JB[3]),
.A(A_cpu),
.Di(Di_cpu),
.Do(Do_cpu),
.PC(PC),
.SP(SP),
.AF(AF),
.BC(BC),
.DE(DE),
.HL(HL),
.joypad_state(joypad_state)
);
// driver for divider clocks and debug elements
always @(posedge core_clock) begin
if (reset_init) begin
clock_1khz <= 1'b0;
clock_200khz <= 1'b0;
mode <= 2'b0;
end else begin
if (pulse_1khz)
clock_1khz <= !clock_1khz;
if (pulse_200khz)
clock_200khz <= !clock_200khz;
if (mode0_sync)
mode <= 2'b00;
else if (mode1_sync)
mode <= 2'b01;
else if (mode2_sync)
mode <= 2'b10;
else if (mode3_sync)
mode <= 2'b11;
end
end
always @(posedge clock) begin
if (reset_init) begin
clock_divider <= 1'b0;
end else begin
if (step_enable)
clock_divider <= clock_divider + 4;
else
clock_divider <= clock_divider + 1;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_tfifo.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// Modified for use in the ZAP project by Revanth Kamaraj ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 1'b0;
count <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 1'b0;
count <= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= top_plus_1;
count <= count + 1'b1;
end
2'b01 : if(count>0)
begin
bottom <= bottom + 1'b1;
count <= count - 1'b1;
end
2'b11 : begin
bottom <= bottom + 1'b1;
top <= top_plus_1;
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & (count==fifo_depth))
overrun <= 1'b1;
end // always
endmodule
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Radio-86RK video output
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
// Modified by: Andy Karpov <[email protected]> for WXEDA board
//
// Design File: rk_video.v
//
module rk_video(
input clk,
output hr,
output vr,
output hr_wg75,
output vr_wg75,
output cce,
output [4:0] r,
output [5:0] g,
output [4:0] b,
input[3:0] line,
input[6:0] ichar,
input vsp,
input lten,
input rvv
);
// rk related
reg[1:0] state;
reg[10:0] h_cnt;
reg[10:0] v_cnt;
reg[10:0] v_cnt2;
reg[1:0] v_cnt_line;
reg[2:0] d_cnt;
reg[5:0] data;
wire[7:0] fdata;
// framebuffer 408x300 (384x250 + gaps)
reg[17:0] address_in;
reg[17:0] address_out;
reg data_in;
wire data_out;
rambuffer framebuf(
.address_a(address_in),
.address_b(address_out),
.clock(clk),
.data_a(data_in),
.data_b(),
.wren_a(1'b1),
.wren_b(1'b0),
.q_a(),
.q_b(data_out)
);
assign hr_wg75 = h_cnt >= 10'd468 && h_cnt < 10'd516 ? 1'b0 : 1'b1; // wg75 hsync
assign vr_wg75 = v_cnt >= 10'd600 && v_cnt < 10'd620 ? 1'b0 : 1'b1; // wg75 vsync
assign cce = d_cnt==3'b000 && state == 2'b01; // wg75 chip enable signal
font from(.address({ichar[6:0],line[2:0]}), .clock(clk), .q(fdata));
always @(posedge clk)
begin
// 3x divider to get 16MHz clock from 48MHz
casex (state)
2'b00: state <= 2'b01;
2'b01: state <= 2'b10;
2'b1x: state <= 2'b00;
endcase
if (state == 2'b00)
begin
if (d_cnt==3'b101)
data <= lten ? 6'h3F : vsp ? 6'b0 : fdata[5:0]^{6{rvv}};
else
data <= {data[4:0],1'b0};
// write visible data to framebuffer
if (h_cnt >= 60 && h_cnt < 468 && v_cnt2 >= 0 && v_cnt2 < 300 && v_cnt_line == 2'b00)
begin
address_in <= h_cnt - 60 + (10'd408*(v_cnt2 - 0));
data_in <= data[5];
//data_in <= 1'b1; // test white screen
end
if (h_cnt+1'b1 == 10'd516) // 516 - end of line
begin
h_cnt <= 0;
d_cnt <= 0;
if (v_cnt+1'b1 == 10'd620 ) // 310 - end of frame
begin
v_cnt <= 0;
v_cnt2 <= 0;
end
else begin
v_cnt <= v_cnt+1'b1;
casex (v_cnt_line)
2'b00: v_cnt_line <= 2'b01;
2'b01: v_cnt_line <= 2'b00;
2'b1x: v_cnt_line <= 2'b00;
endcase
if (v_cnt_line == 2'b00)
v_cnt2 <= v_cnt2+1'b1;
end
end
else
begin
h_cnt <= h_cnt+1'b1;
if (d_cnt+1'b1 == 3'b110) // end of char
d_cnt <= 0;
else
d_cnt <= d_cnt+1'b1;
end
end
end
// vga sync generator
wire[10:0] CounterX;
wire[10:0] CounterY;
wire inDisplay;
hvsync_generator vgasync(
.clk(clk),
.vga_h_sync(hr),
.vga_v_sync(vr),
.inDisplayArea(inDisplay),
.CounterX(CounterX),
.CounterY(CounterY)
);
// vga signal generator
reg[1:0] pixel_state;
reg[1:0] line_state;
reg[10:0] pixel_cnt;
reg[10:0] line_cnt;
assign r = data_out && inDisplay ? 5'b10000 : 5'b0;
assign g = data_out && inDisplay ? 6'b100000 : 6'b0;
assign b = data_out && inDisplay ? 5'b10000 : 5'b0;
always @(posedge clk)
begin
if (CounterX >= 0 && CounterX < 816 && CounterY >= 0 && CounterY < 600) // doubledot visible area
begin
casex (pixel_state)
2'b00: pixel_state <= 2'b01;
2'b01: pixel_state <= 2'b00;
endcase
address_out <= pixel_cnt + (line_cnt*408);
if (pixel_state == 2'b01)
pixel_cnt <= pixel_cnt + 1;
if (CounterX+1 == 816)
begin
pixel_cnt <= 0;
casex (line_state)
2'b00: line_state <= 2'b01;
2'b01: line_state <= 2'b00;
endcase
if (line_state == 2'b01)
line_cnt <= line_cnt + 1;
end
if (CounterY+1 == 600)
begin
line_cnt <= 0;
pixel_cnt <= 0;
line_state <= 0;
end
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: clock_generator_pll_s16_diff.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: June 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: PLL Based clock generator. Takes in a differential clock and multiplies it
// by the amount specified. Instantiates a BUFIO2, BUFPLL and a PLL using
// INTERNAL feedback
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module clock_generator_pll_s16_diff (clkin_p, clkin_n, ioclk, serdesstrobe, reset, gclk1, gclk2, bufpll_lckd) ;
parameter integer S = 16 ; // Parameter to set the serdes factor 1..8
parameter integer PLLX = 16 ; // Parameter to set the multiplication factor in the PLL
parameter integer PLLD = 1 ; // Parameter to set the division factor in the PLL
parameter real CLKIN_PERIOD = 6.000 ; // clock period (ns) of input clock on clkin_p
parameter DIFF_TERM = "FALSE" ; // Parameter to enable internal differential termination
input reset ; // reset (active high)
input clkin_p, clkin_n ; // differential clock inputs
output ioclk ; // ioclock from BUFPLL
output serdesstrobe ; // serdes strobe from BUFPLL
output gclk1 ; // global clock output from BUFG x1
output gclk2 ; // global clock output from BUFG x2
output bufpll_lckd ; // Locked output from BUFPLL
IBUFGDS #(
.DIFF_TERM (DIFF_TERM))
iob_clkint (
.I (clkin_p),
.IB (clkin_n),
.O (clkint));
PLL_ADV #(
.BANDWIDTH ("OPTIMIZED"), // "high", "low" or "optimized"
.CLKFBOUT_MULT (PLLX), // multiplication factor for all output clocks
.CLKFBOUT_PHASE (0.0), // phase shift (degrees) of all output clocks
.CLKIN1_PERIOD (CLKIN_PERIOD), // clock period (ns) of input clock on clkin1
.CLKIN2_PERIOD (CLKIN_PERIOD), // clock period (ns) of input clock on clkin2
.CLKOUT0_DIVIDE (1), // division factor for clkout0 (1 to 128)
.CLKOUT0_DUTY_CYCLE (0.5), // duty cycle for clkout0 (0.01 to 0.99)
.CLKOUT0_PHASE (0.0), // phase shift (degrees) for clkout0 (0.0 to 360.0)
.CLKOUT1_DIVIDE (1), // division factor for clkout1 (1 to 128)
.CLKOUT1_DUTY_CYCLE (0.5), // duty cycle for clkout1 (0.01 to 0.99)
.CLKOUT1_PHASE (0.0), // phase shift (degrees) for clkout1 (0.0 to 360.0)
.CLKOUT2_DIVIDE (S), // division factor for clkout2 (1 to 128)
.CLKOUT2_DUTY_CYCLE (0.5), // duty cycle for clkout2 (0.01 to 0.99)
.CLKOUT2_PHASE (0.0), // phase shift (degrees) for clkout2 (0.0 to 360.0)
.CLKOUT3_DIVIDE (S/2), // division factor for clkout3 (1 to 128)
.CLKOUT3_DUTY_CYCLE (0.5), // duty cycle for clkout3 (0.01 to 0.99)
.CLKOUT3_PHASE (0.0), // phase shift (degrees) for clkout3 (0.0 to 360.0)
.CLKOUT4_DIVIDE (S), // division factor for clkout4 (1 to 128)
.CLKOUT4_DUTY_CYCLE (0.5), // duty cycle for clkout4 (0.01 to 0.99)
.CLKOUT4_PHASE (0.0), // phase shift (degrees) for clkout4 (0.0 to 360.0)
.CLKOUT5_DIVIDE (S), // division factor for clkout5 (1 to 128)
.CLKOUT5_DUTY_CYCLE (0.5), // duty cycle for clkout5 (0.01 to 0.99)
.CLKOUT5_PHASE (0.0), // phase shift (degrees) for clkout5 (0.0 to 360.0)
.COMPENSATION ("INTERNAL"), // "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
.DIVCLK_DIVIDE (PLLD), // division factor for all clocks (1 to 52)
.REF_JITTER (0.100)) // input reference jitter (0.000 to 0.999 ui%)
tx_pll_adv_inst (
.CLKFBDCM (), // output feedback signal used when pll feeds a dcm
.CLKFBOUT (dummy), // general output feedback signal
.CLKOUT0 (pllout_xs), // x10 clock for transmitter
.CLKOUT1 (), //
.CLKOUT2 (pllout_x1), // x1 clock for BUFG
.CLKOUT3 (pllout_x2), // x2 clock for BUFG
.CLKOUT4 (), // one of six general clock output signals
.CLKOUT5 (), // one of six general clock output signals
.CLKOUTDCM0 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM1 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM2 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM3 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM4 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM5 (), // one of six clock outputs to connect to the dcm
.DO (), // dynamic reconfig data output (16-bits)
.DRDY (), // dynamic reconfig ready output
.LOCKED (pll_lckd), // active high pll lock signal
.CLKFBIN (dummy), // clock feedback input
.CLKIN1 (clkint), // primary clock input
.CLKIN2 (1'b0), // secondary clock input
.CLKINSEL (1'b1), // selects '1' = clkin1, '0' = clkin2
.DADDR (5'b00000), // dynamic reconfig address input (5-bits)
.DCLK (1'b0), // dynamic reconfig clock input
.DEN (1'b0), // dynamic reconfig enable input
.DI (16'h0000), // dynamic reconfig data input (16-bits)
.DWE (1'b0), // dynamic reconfig write enable input
.RST (reset), // asynchronous pll reset
.REL (1'b0)) ; // used to force the state of the PFD outputs (test only)
BUFG bufg_tx_x1 (.I(pllout_x1), .O(gclk1) ) ;
BUFG bufg_tx_x2 (.I(pllout_x2), .O(gclk2) ) ;
BUFPLL #(
.DIVIDE (S/2)) // PLLIN0 divide-by value to produce SERDESSTROBE (1 to 8); default 1
tx_bufpll_inst (
.PLLIN (pllout_xs), // PLL Clock input
.GCLK (gclk2), // Global Clock input
.LOCKED (pll_lckd), // Clock0 locked input
.IOCLK (ioclk), // Output PLL Clock
.LOCK (buf_pll_lckd), // BUFPLL Clock and strobe locked
.SERDESSTROBE (serdesstrobe)) ; // Output SERDES strobe
assign bufpll_lckd = buf_pll_lckd & pll_lckd ;
endmodule
|
//`define ICDEBUG 1
`ifdef FPGA
// `define DUMMY_CACHE
`endif
// Number of cache lines
`define IC_WIDTH_BITS 4
`define IC_LINES_BITS 6
`define IC_WIDTH_ZERO 4'b0000
`define IC_WIDTH_ONES 4'b1111
`define IC_WIDTH (1<<`IC_WIDTH_BITS)
`define IC_LINES (1<<`IC_LINES_BITS)
`ifdef DUMMY_CACHE
module toy_icache(input clk,
input reset,
input [31:0] ic_addr,
input ic_rq,
output reg ic_data_out_valid,
output reg [31:0] ic_data_out,
// memory bus interface
input [31:0] data_in, // bus data in
input data_in_ready, // bus data ready
output reg data_rd, // request data read
output reg [31:0] data_address // output data address
);
always @(posedge clk)
begin
data_address <= ic_addr;
data_rd <= ic_rq;
ic_data_out <= data_in;
ic_data_out_valid <= data_in_ready;
end
endmodule
`endif
`ifndef DUMMY_CACHE
module toy_icache(input clk,
input reset,
input [31:0] ic_addr,
input ic_rq,
output reg ic_data_out_valid,
output reg [31:0] ic_data_out,
// memory bus interface
input [31:0] data_in, // bus data in
input data_in_ready, // bus data ready
output reg data_rd, // request data read
output reg [31:0] data_address // output data address
);
// bits 2-0 are cache line address
// bits 31-3 are a tag
// bits 7-3 are a line address
// bits 7-0 are
reg [31-`IC_WIDTH_BITS+1:0] ictags[0:`IC_LINES-1];
reg [31:0] cacheram[0:`IC_LINES*`IC_WIDTH-1];
wire [31-`IC_WIDTH_BITS:0] addrtag;
assign addrtag = ic_addr[31:`IC_WIDTH_BITS];
reg [31-`IC_WIDTH_BITS+1:0] icnewtag;
parameter S_IDLE = 0;
parameter S_FILL = 1;
parameter S_FILL_STEP = 2;
reg [1:0] ic_state;
reg [31:0] ictagsout;
reg [1:0] ic_rq_shift;
always @(posedge clk)
if (!reset) begin
ic_data_out_valid <= 0;
ic_data_out <= 0;
icnewtag <= 0;
data_rd <= 0;
ic_state <= S_IDLE;
ictagsout <= 0;
ic_rq_shift <= 0;
end else begin
ic_rq_shift <= {ic_rq_shift[0],ic_rq};
ictagsout <= ictags[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:`IC_WIDTH_BITS]];
case (ic_state)
S_IDLE:
if (ic_rq_shift[1]) begin
if(ictagsout == {1'b1,addrtag}) // hit
begin
`ifdef ICDEBUG
$display("ICACHE HIT: %X -> %X", ic_addr, cacheram[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:0]]);
`endif
ic_data_out <= cacheram[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:0]];
ic_data_out_valid <= 1;
end else begin // sorry, miss
`ifdef ICDEBUG
$display("ICACHE SHIT: %X [%X vs. %X] at %X", ic_addr, ictags[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:`IC_WIDTH_BITS]], {1'b1,addrtag}, ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:`IC_WIDTH_BITS]);
`endif
ic_data_out_valid <= 0;
ictags[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:`IC_WIDTH_BITS]] <= 0; // evict
ic_state <= S_FILL;
data_address <= {ic_addr[31:`IC_WIDTH_BITS],`IC_WIDTH_ZERO}; // start of the line
data_rd <= 1;
icnewtag <= {1'b1, addrtag};
end
end else begin
ic_data_out_valid <= 0;
ic_data_out <= 0;
end
S_FILL: begin
if (data_in_ready) begin
`ifdef ICDEBUG
$display("ICACHE FILL %X <- %X", data_address, data_in);
`endif
if (ic_rq && data_address == ic_addr) begin // a possibly premature hit, report it
`ifdef ICDEBUG
$display("ICACHE FHIT: %X -> %X", ic_addr, data_in);
`endif
ic_data_out <= data_in;
ic_data_out_valid <= 1;
end else begin
ic_data_out_valid <= 0;
ic_data_out <= 0;
end
cacheram[data_address[`IC_LINES_BITS+`IC_WIDTH_BITS-1:0]] <= data_in;
data_rd <= 0;
if (data_address[`IC_WIDTH_BITS-1:0] == `IC_WIDTH_ONES) begin
`ifdef ICDEBUG
$display("ICACHE FILLING DONE %X at %X", icnewtag, data_address[`IC_LINES_BITS+`IC_WIDTH_BITS-1:`IC_WIDTH_BITS]);
`endif
ictags[data_address[`IC_LINES_BITS+`IC_WIDTH_BITS-1:`IC_WIDTH_BITS]] <= icnewtag; // reclaim a line
ic_state <= S_IDLE;
end else begin
ic_state <= S_FILL_STEP;
data_address <= data_address + 1;
end
end else begin // if (data_in_ready && ~stall)
if (ic_rq &&
data_address[`IC_LINES_BITS+`IC_WIDTH_BITS-1:`IC_WIDTH_BITS]
==
ic_addr[`IC_LINES_BITS+`IC_WIDTH_BITS-1:`IC_WIDTH_BITS]
&& !(data_address[31:`IC_WIDTH_BITS] == ic_addr[31:`IC_WIDTH_BITS])) begin
// have to evict before completion
ictags[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:`IC_WIDTH_BITS]] <= 0;
ic_state <= S_IDLE;
ic_data_out_valid <= 0;
end
if (ic_rq && data_address[31:`IC_WIDTH_BITS] == ic_addr[31:`IC_WIDTH_BITS]
&& ic_addr[`IC_WIDTH_BITS-1:0] < data_address[`IC_WIDTH_BITS-1:0]) begin
`ifdef ICDEBUG
$display("ICACHE FFHIT: %X -> %X [%X vs %X]", ic_addr, cacheram[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:0]],
ic_addr[`IC_WIDTH_BITS-1:0], data_address[`IC_WIDTH_BITS-1:0]);
`endif
ic_data_out <= cacheram[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:0]];
ic_data_out_valid <= 1;
end else begin
ic_data_out_valid <= 0;
ic_data_out <= 0;
end
end
end // case: S_FILL
S_FILL_STEP: begin
data_rd <= 1;
ic_state <= S_FILL;
ic_data_out_valid <= 0;
ic_data_out <= 0;
end
endcase // case (ic_state)
end
endmodule
`endif // `ifndef DUMMY_CACHE
|
`include "../../../rtl/verilog/gfx/gfx_wbm_write.v"
`include "../../../rtl/verilog/gfx/basic_fifo.v"
module wbm_w_bench();
// wishbone signals
reg clk_i; // master clock reg
reg rst_i; // synchronous active high reset
wire cyc_o; // cycle wire
wire stb_o; // strobe output
wire [ 2:0] cti_o; // cycle type id
wire [ 1:0] bte_o; // burst type extension
wire we_o; // write enable wire
wire [31:0] adr_o; // address wire
wire [ 3:0] sel_o; // byte select wires (only 32bits accesses are supported)
reg ack_i; // wishbone cycle acknowledge
reg err_i; // wishbone cycle error
wire [31:0] dat_o; // wishbone data out
wire sint_o; // non recoverable error, interrupt host
// Renderer stuff
reg write_i;
wire ack_o;
reg [31:2] render_addr_i;
reg [3:0] render_sel_i;
reg [31:0] render_dat_i;
initial begin
$dumpfile("wbm_w.vcd");
$dumpvars(0,wbm_w_bench);
// init values
clk_i = 0;
rst_i = 1;
err_i = 0;
write_i = 0;
render_addr_i = 0;
render_sel_i = 4'b1111;
render_dat_i = 32'h12345678;
#2 rst_i = 0;
//timing
# 10 write_i = 1;
# 2 write_i = 0;
# 4 write_i = 1;
# 2 write_i = 0;
// end sim
#100 $finish;
end
always @(posedge clk_i)
begin
ack_i <= #1 cyc_o & !ack_i;
end
always begin
#1 clk_i = ~clk_i;
end
gfx_wbm_write wbm_w(
// WB signals
.clk_i (clk_i),
.rst_i (rst_i),
.cyc_o (cyc_o),
.stb_o (stb_o),
.cti_o (cti_o),
.bte_o (bte_o),
.we_o (we_o),
.adr_o (adr_o),
.sel_o (sel_o),
.ack_i (ack_i),
.err_i (err_i),
.dat_o (dat_o),
.sint_o (sint_o),
// Control signals
.write_i (write_i),
.ack_o (ack_o),
.render_addr_i (render_addr_i),
.render_sel_i (render_sel_i),
.render_dat_i (render_dat_i)
);
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2014 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Set Implicit Arguments.
Require Import Notations.
(** * Propositional connectives *)
(** [True] is the always true proposition *)
Inductive True : Prop :=
I : True.
(** [False] is the always false proposition *)
Inductive False : Prop :=.
(** [not A], written [~A], is the negation of [A] *)
Definition not (A:Prop) := A -> False.
Notation "~ x" := (not x) : type_scope.
Hint Unfold not: core.
(** [and A B], written [A /\ B], is the conjunction of [A] and [B]
[conj p q] is a proof of [A /\ B] as soon as
[p] is a proof of [A] and [q] a proof of [B]
[proj1] and [proj2] are first and second projections of a conjunction *)
Inductive and (A B:Prop) : Prop :=
conj : A -> B -> A /\ B
where "A /\ B" := (and A B) : type_scope.
Section Conjunction.
Variables A B : Prop.
Theorem proj1 : A /\ B -> A.
Proof.
destruct 1; trivial.
Qed.
Theorem proj2 : A /\ B -> B.
Proof.
destruct 1; trivial.
Qed.
End Conjunction.
(** [or A B], written [A \/ B], is the disjunction of [A] and [B] *)
Inductive or (A B:Prop) : Prop :=
| or_introl : A -> A \/ B
| or_intror : B -> A \/ B
where "A \/ B" := (or A B) : type_scope.
Arguments or_introl [A B] _, [A] B _.
Arguments or_intror [A B] _, A [B] _.
(** [iff A B], written [A <-> B], expresses the equivalence of [A] and [B] *)
Definition iff (A B:Prop) := (A -> B) /\ (B -> A).
Notation "A <-> B" := (iff A B) : type_scope.
Section Equivalence.
Theorem iff_refl : forall A:Prop, A <-> A.
Proof.
split; auto.
Qed.
Theorem iff_trans : forall A B C:Prop, (A <-> B) -> (B <-> C) -> (A <-> C).
Proof.
intros A B C [H1 H2] [H3 H4]; split; auto.
Qed.
Theorem iff_sym : forall A B:Prop, (A <-> B) -> (B <-> A).
Proof.
intros A B [H1 H2]; split; auto.
Qed.
End Equivalence.
Hint Unfold iff: extcore.
(** Some equivalences *)
Theorem neg_false : forall A : Prop, ~ A <-> (A <-> False).
Proof.
intro A; unfold not; split.
- intro H; split; [exact H | intro H1; elim H1].
- intros [H _]; exact H.
Qed.
Theorem and_cancel_l : forall A B C : Prop,
(B -> A) -> (C -> A) -> ((A /\ B <-> A /\ C) <-> (B <-> C)).
Proof.
intros; tauto.
Qed.
Theorem and_cancel_r : forall A B C : Prop,
(B -> A) -> (C -> A) -> ((B /\ A <-> C /\ A) <-> (B <-> C)).
Proof.
intros; tauto.
Qed.
Theorem and_comm : forall A B : Prop, A /\ B <-> B /\ A.
Proof.
intros; tauto.
Qed.
Theorem and_assoc : forall A B C : Prop, (A /\ B) /\ C <-> A /\ B /\ C.
Proof.
intros; tauto.
Qed.
Theorem or_cancel_l : forall A B C : Prop,
(B -> ~ A) -> (C -> ~ A) -> ((A \/ B <-> A \/ C) <-> (B <-> C)).
Proof.
intros; tauto.
Qed.
Theorem or_cancel_r : forall A B C : Prop,
(B -> ~ A) -> (C -> ~ A) -> ((B \/ A <-> C \/ A) <-> (B <-> C)).
Proof.
intros; tauto.
Qed.
Theorem or_comm : forall A B : Prop, (A \/ B) <-> (B \/ A).
Proof.
intros; tauto.
Qed.
Theorem or_assoc : forall A B C : Prop, (A \/ B) \/ C <-> A \/ B \/ C.
Proof.
intros; tauto.
Qed.
(** Backward direction of the equivalences above does not need assumptions *)
Theorem and_iff_compat_l : forall A B C : Prop,
(B <-> C) -> (A /\ B <-> A /\ C).
Proof.
intros; tauto.
Qed.
Theorem and_iff_compat_r : forall A B C : Prop,
(B <-> C) -> (B /\ A <-> C /\ A).
Proof.
intros; tauto.
Qed.
Theorem or_iff_compat_l : forall A B C : Prop,
(B <-> C) -> (A \/ B <-> A \/ C).
Proof.
intros; tauto.
Qed.
Theorem or_iff_compat_r : forall A B C : Prop,
(B <-> C) -> (B \/ A <-> C \/ A).
Proof.
intros; tauto.
Qed.
Lemma iff_and : forall A B : Prop, (A <-> B) -> (A -> B) /\ (B -> A).
Proof.
intros A B []; split; trivial.
Qed.
Lemma iff_to_and : forall A B : Prop, (A <-> B) <-> (A -> B) /\ (B -> A).
Proof.
intros; tauto.
Qed.
(** [(IF_then_else P Q R)], written [IF P then Q else R] denotes
either [P] and [Q], or [~P] and [Q] *)
Definition IF_then_else (P Q R:Prop) := P /\ Q \/ ~ P /\ R.
Notation "'IF' c1 'then' c2 'else' c3" := (IF_then_else c1 c2 c3)
(at level 200, right associativity) : type_scope.
(** * First-order quantifiers *)
(** [ex P], or simply [exists x, P x], or also [exists x:A, P x],
expresses the existence of an [x] of some type [A] in [Set] which
satisfies the predicate [P]. This is existential quantification.
[ex2 P Q], or simply [exists2 x, P x & Q x], or also
[exists2 x:A, P x & Q x], expresses the existence of an [x] of
type [A] which satisfies both predicates [P] and [Q].
Universal quantification is primitively written [forall x:A, Q]. By
symmetry with existential quantification, the construction [all P]
is provided too.
*)
Inductive ex (A:Type) (P:A -> Prop) : Prop :=
ex_intro : forall x:A, P x -> ex (A:=A) P.
Inductive ex2 (A:Type) (P Q:A -> Prop) : Prop :=
ex_intro2 : forall x:A, P x -> Q x -> ex2 (A:=A) P Q.
Definition all (A:Type) (P:A -> Prop) := forall x:A, P x.
(* Rule order is important to give printing priority to fully typed exists *)
Notation "'exists' x .. y , p" := (ex (fun x => .. (ex (fun y => p)) ..))
(at level 200, x binder, right associativity,
format "'[' 'exists' '/ ' x .. y , '/ ' p ']'")
: type_scope.
Notation "'exists2' x , p & q" := (ex2 (fun x => p) (fun x => q))
(at level 200, x ident, p at level 200, right associativity) : type_scope.
Notation "'exists2' x : t , p & q" := (ex2 (fun x:t => p) (fun x:t => q))
(at level 200, x ident, t at level 200, p at level 200, right associativity,
format "'[' 'exists2' '/ ' x : t , '/ ' '[' p & '/' q ']' ']'")
: type_scope.
(** Derived rules for universal quantification *)
Section universal_quantification.
Variable A : Type.
Variable P : A -> Prop.
Theorem inst : forall x:A, all (fun x => P x) -> P x.
Proof.
unfold all; auto.
Qed.
Theorem gen : forall (B:Prop) (f:forall y:A, B -> P y), B -> all P.
Proof.
red; auto.
Qed.
End universal_quantification.
(** * Equality *)
(** [eq x y], or simply [x=y] expresses the equality of [x] and
[y]. Both [x] and [y] must belong to the same type [A].
The definition is inductive and states the reflexivity of the equality.
The others properties (symmetry, transitivity, replacement of
equals by equals) are proved below. The type of [x] and [y] can be
made explicit using the notation [x = y :> A]. This is Leibniz equality
as it expresses that [x] and [y] are equal iff every property on
[A] which is true of [x] is also true of [y] *)
Inductive eq (A:Type) (x:A) : A -> Prop :=
eq_refl : x = x :>A
where "x = y :> A" := (@eq A x y) : type_scope.
Notation "x = y" := (x = y :>_) : type_scope.
Notation "x <> y :> T" := (~ x = y :>T) : type_scope.
Notation "x <> y" := (x <> y :>_) : type_scope.
Arguments eq {A} x _.
Arguments eq_refl {A x} , [A] x.
Arguments eq_ind [A] x P _ y _.
Arguments eq_rec [A] x P _ y _.
Arguments eq_rect [A] x P _ y _.
Hint Resolve I conj or_introl or_intror eq_refl: core.
Hint Resolve ex_intro ex_intro2: core.
Section Logic_lemmas.
Theorem absurd : forall A C:Prop, A -> ~ A -> C.
Proof.
unfold not; intros A C h1 h2.
destruct (h2 h1).
Qed.
Section equality.
Variables A B : Type.
Variable f : A -> B.
Variables x y z : A.
Theorem eq_sym : x = y -> y = x.
Proof.
destruct 1; trivial.
Defined.
Opaque eq_sym.
Theorem eq_trans : x = y -> y = z -> x = z.
Proof.
destruct 2; trivial.
Defined.
Opaque eq_trans.
Theorem f_equal : x = y -> f x = f y.
Proof.
destruct 1; trivial.
Defined.
Opaque f_equal.
Theorem not_eq_sym : x <> y -> y <> x.
Proof.
red; intros h1 h2; apply h1; destruct h2; trivial.
Qed.
End equality.
Definition eq_ind_r :
forall (A:Type) (x:A) (P:A -> Prop), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
Definition eq_rec_r :
forall (A:Type) (x:A) (P:A -> Set), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
Definition eq_rect_r :
forall (A:Type) (x:A) (P:A -> Type), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
End Logic_lemmas.
Module EqNotations.
Notation "'rew' H 'in' H'" := (eq_rect _ _ H' _ H)
(at level 10, H' at level 10).
Notation "'rew' <- H 'in' H'" := (eq_rect_r _ H' H)
(at level 10, H' at level 10).
Notation "'rew' -> H 'in' H'" := (eq_rect _ _ H' _ H)
(at level 10, H' at level 10, only parsing).
End EqNotations.
Theorem f_equal2 :
forall (A1 A2 B:Type) (f:A1 -> A2 -> B) (x1 y1:A1)
(x2 y2:A2), x1 = y1 -> x2 = y2 -> f x1 x2 = f y1 y2.
Proof.
destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal3 :
forall (A1 A2 A3 B:Type) (f:A1 -> A2 -> A3 -> B) (x1 y1:A1)
(x2 y2:A2) (x3 y3:A3),
x1 = y1 -> x2 = y2 -> x3 = y3 -> f x1 x2 x3 = f y1 y2 y3.
Proof.
destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal4 :
forall (A1 A2 A3 A4 B:Type) (f:A1 -> A2 -> A3 -> A4 -> B)
(x1 y1:A1) (x2 y2:A2) (x3 y3:A3) (x4 y4:A4),
x1 = y1 -> x2 = y2 -> x3 = y3 -> x4 = y4 -> f x1 x2 x3 x4 = f y1 y2 y3 y4.
Proof.
destruct 1; destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal5 :
forall (A1 A2 A3 A4 A5 B:Type) (f:A1 -> A2 -> A3 -> A4 -> A5 -> B)
(x1 y1:A1) (x2 y2:A2) (x3 y3:A3) (x4 y4:A4) (x5 y5:A5),
x1 = y1 ->
x2 = y2 ->
x3 = y3 -> x4 = y4 -> x5 = y5 -> f x1 x2 x3 x4 x5 = f y1 y2 y3 y4 y5.
Proof.
destruct 1; destruct 1; destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
(* Aliases *)
Notation sym_eq := eq_sym (compat "8.3").
Notation trans_eq := eq_trans (compat "8.3").
Notation sym_not_eq := not_eq_sym (compat "8.3").
Notation refl_equal := eq_refl (compat "8.3").
Notation sym_equal := eq_sym (compat "8.3").
Notation trans_equal := eq_trans (compat "8.3").
Notation sym_not_equal := not_eq_sym (compat "8.3").
Hint Immediate eq_sym not_eq_sym: core.
(** Basic definitions about relations and properties *)
Definition subrelation (A B : Type) (R R' : A->B->Prop) :=
forall x y, R x y -> R' x y.
Definition unique (A : Type) (P : A->Prop) (x:A) :=
P x /\ forall (x':A), P x' -> x=x'.
Definition uniqueness (A:Type) (P:A->Prop) := forall x y, P x -> P y -> x = y.
(** Unique existence *)
Notation "'exists' ! x .. y , p" :=
(ex (unique (fun x => .. (ex (unique (fun y => p))) ..)))
(at level 200, x binder, right associativity,
format "'[' 'exists' ! '/ ' x .. y , '/ ' p ']'")
: type_scope.
Lemma unique_existence : forall (A:Type) (P:A->Prop),
((exists x, P x) /\ uniqueness P) <-> (exists! x, P x).
Proof.
intros A P; split.
- intros ((x,Hx),Huni); exists x; red; auto.
- intros (x,(Hx,Huni)); split.
+ exists x; assumption.
+ intros x' x'' Hx' Hx''; transitivity x.
symmetry; auto.
auto.
Qed.
Lemma forall_exists_unique_domain_coincide :
forall A (P:A->Prop), (exists! x, P x) ->
forall Q:A->Prop, (forall x, P x -> Q x) <-> (exists x, P x /\ Q x).
Proof.
intros A P (x & Hp & Huniq); split.
- intro; exists x; auto.
- intros (x0 & HPx0 & HQx0) x1 HPx1.
replace x1 with x0 by (transitivity x; [symmetry|]; auto).
assumption.
Qed.
Lemma forall_exists_coincide_unique_domain :
forall A (P:A->Prop),
(forall Q:A->Prop, (forall x, P x -> Q x) <-> (exists x, P x /\ Q x))
-> (exists! x, P x).
Proof.
intros A P H.
destruct H with (Q:=P) as ((x & Hx & _),_); [trivial|].
exists x. split; [trivial|].
destruct H with (Q:=fun x'=>x=x') as (_,Huniq).
apply Huniq. exists x; auto.
Qed.
(** * Being inhabited *)
(** The predicate [inhabited] can be used in different contexts. If [A] is
thought as a type, [inhabited A] states that [A] is inhabited. If [A] is
thought as a computationally relevant proposition, then
[inhabited A] weakens [A] so as to hide its computational meaning.
The so-weakened proof remains computationally relevant but only in
a propositional context.
*)
Inductive inhabited (A:Type) : Prop := inhabits : A -> inhabited A.
Hint Resolve inhabits: core.
Lemma exists_inhabited : forall (A:Type) (P:A->Prop),
(exists x, P x) -> inhabited A.
Proof.
destruct 1; auto.
Qed.
(** Declaration of stepl and stepr for eq and iff *)
Lemma eq_stepl : forall (A : Type) (x y z : A), x = y -> x = z -> z = y.
Proof.
intros A x y z H1 H2. rewrite <- H2; exact H1.
Qed.
Declare Left Step eq_stepl.
Declare Right Step eq_trans.
Lemma iff_stepl : forall A B C : Prop, (A <-> B) -> (A <-> C) -> (C <-> B).
Proof.
intros; tauto.
Qed.
Declare Left Step iff_stepl.
Declare Right Step iff_trans.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKBUF_2_V
`define SKY130_FD_SC_HS__CLKBUF_2_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkbuf_2 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkbuf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKBUF_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_2_V
`define SKY130_FD_SC_LP__AND4_2_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4_2 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4_2 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_2_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_ncio.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
//
// Where Instantiated: jbi
// Description: Non-Cached IO Block
// This block includes the PIO and Mondo Interrupt blocks
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
`include "jbi.h"
module jbi_ncio (/*AUTOARG*/
// Outputs
ncio_csr_err_intr_to, ncio_csr_perf_pio_rd_out, ncio_csr_perf_pio_wr,
ncio_csr_perf_pio_rd_latency, ncio_csr_read_addr, ncio_csr_write,
ncio_csr_write_addr, ncio_csr_write_data, jbi_iob_pio_vld,
jbi_iob_pio_data, jbi_iob_pio_stall, jbi_iob_mondo_vld,
jbi_iob_mondo_data, ncio_pio_req, ncio_pio_req_rw, ncio_pio_req_dest,
ncio_pio_ue, ncio_pio_be, ncio_pio_ad, ncio_yid, ncio_prqq_level,
ncio_mondo_req, ncio_mondo_ack, ncio_mondo_agnt_id,
ncio_mondo_cpu_id, ncio_makq_level, ncio_mout_nack_pop,
// Inputs
clk, rst_l, arst_l, cpu_clk, cpu_rst_l, cpu_rx_en, cpu_tx_en, hold,
testmux_sel, scan_en, rst_tri_en, csr_16x65array_margin,
csr_16x81array_margin, csr_jbi_config2_max_pio,
csr_jbi_config2_ord_int, csr_jbi_config2_ord_pio,
csr_jbi_intr_timeout_timeval, csr_jbi_intr_timeout_rst_l,
csr_int_req, csr_csr_read_data, iob_jbi_pio_stall, iob_jbi_pio_vld,
iob_jbi_pio_data, iob_jbi_mondo_ack, iob_jbi_mondo_nack,
io_jbi_j_ad_ff, min_pio_rtrn_push, min_pio_data_err,
min_mondo_hdr_push, min_mondo_data_push, min_mondo_data_err,
min_oldest_wri_tag, min_pre_wri_tag, mout_trans_yid, mout_pio_pop,
mout_pio_req_adv, mout_mondo_pop, mout_nack, mout_nack_buf_id,
mout_nack_thr_id
);
input clk;
input rst_l;
input arst_l;
input cpu_clk;
input cpu_rst_l;
input cpu_rx_en;
input cpu_tx_en;
input hold;
input testmux_sel;
input scan_en;
input rst_tri_en;
// CSR Interface
input [4:0] csr_16x65array_margin;
input [4:0] csr_16x81array_margin;
input [3:0] csr_jbi_config2_max_pio;
input csr_jbi_config2_ord_int;
input csr_jbi_config2_ord_pio;
input [31:0] csr_jbi_intr_timeout_timeval;
input csr_jbi_intr_timeout_rst_l;
input csr_int_req;
output [31:0] ncio_csr_err_intr_to;
output ncio_csr_perf_pio_rd_out;
output ncio_csr_perf_pio_wr;
output [4:0] ncio_csr_perf_pio_rd_latency;
input [`JBI_CSR_WIDTH-1:0] csr_csr_read_data;
output [`JBI_CSR_ADDR_WIDTH-1:0] ncio_csr_read_addr;
output ncio_csr_write;
output [`JBI_CSR_ADDR_WIDTH-1:0] ncio_csr_write_addr;
output [`JBI_CSR_WIDTH-1:0] ncio_csr_write_data;
// IOB Interface.
input iob_jbi_pio_stall;
input iob_jbi_pio_vld;
input [`IOB_JBI_WIDTH-1:0] iob_jbi_pio_data;
input iob_jbi_mondo_ack;
input iob_jbi_mondo_nack;
output jbi_iob_pio_vld;
output [`JBI_IOB_WIDTH-1:0] jbi_iob_pio_data;
output jbi_iob_pio_stall;
output jbi_iob_mondo_vld;
output [`JBI_IOB_MONDO_BUS_WIDTH-1:0] jbi_iob_mondo_data;
// Memory In (min) Interface
input [127:0] io_jbi_j_ad_ff; // flopped version of j_ad
input min_pio_rtrn_push;
input min_pio_data_err;
input min_mondo_hdr_push;
input min_mondo_data_push;
input min_mondo_data_err;
input [`JBI_WRI_TAG_WIDTH-1:0] min_oldest_wri_tag;
input [`JBI_WRI_TAG_WIDTH-1:0] min_pre_wri_tag;
// Memory Out (mout) Interface
input [`JBI_YID_WIDTH-1:0] mout_trans_yid;
input mout_pio_pop;
input mout_pio_req_adv;
input mout_mondo_pop;
output ncio_pio_req;
output ncio_pio_req_rw;
output [1:0] ncio_pio_req_dest;
output ncio_pio_ue;
output [15:0] ncio_pio_be;
output [63:0] ncio_pio_ad;
output [`JBI_YID_WIDTH-1:0] ncio_yid;
output [`JBI_PRQQ_ADDR_WIDTH:0] ncio_prqq_level;
output ncio_mondo_req;
output ncio_mondo_ack; // 1=ack; 0=nack
output [`JBI_AD_INT_AGTID_WIDTH-1:0] ncio_mondo_agnt_id;
output [`JBI_AD_INT_CPUID_WIDTH-1:0] ncio_mondo_cpu_id;
output [`JBI_MAKQ_ADDR_WIDTH:0] ncio_makq_level;
input mout_nack;
input [`UCB_BUF_HI-`UCB_BUF_LO:0] mout_nack_buf_id;
input [`UCB_THR_HI-`UCB_THR_LO:0] mout_nack_thr_id;
output ncio_mout_nack_pop;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire cpu_rx_en_ff; // From u_dff_cpu_rx_en_ff of dff_ns.v
wire cpu_tx_en_ff; // From u_dff_cpu_tx_en_ff of dff_ns.v
wire iob_jbi_mondo_ack_ff; // From u_mrqq_ctl of jbi_ncio_mrqq_ctl.v
wire iob_jbi_mondo_nack_ff; // From u_mrqq_ctl of jbi_ncio_mrqq_ctl.v
wire makq_csn_wr; // From u_makq_ctl of jbi_ncio_makq_ctl.v
wire makq_nack; // From u_mrqq_ctl of jbi_ncio_mrqq_ctl.v
wire makq_push; // From u_mrqq_ctl of jbi_ncio_mrqq_ctl.v
wire [`JBI_MAKQ_ADDR_WIDTH-1:0]makq_raddr; // From u_makq_ctl of jbi_ncio_makq_ctl.v
wire [9:0] makq_rdata; // From u_makq_buf of jbi_1r1w_16x10.v
wire [`JBI_MAKQ_ADDR_WIDTH-1:0]makq_waddr; // From u_makq_ctl of jbi_ncio_makq_ctl.v
wire [`JBI_MAKQ_WIDTH-1:0]makq_wdata; // From u_mrqq_ctl of jbi_ncio_mrqq_ctl.v
wire [`JBI_MRQQ_ADDR_WIDTH-1:0]mrqq_raddr; // From u_mrqq_ctl of jbi_ncio_mrqq_ctl.v
wire mrqq_rd_en; // From u_mrqq_ctl of jbi_ncio_mrqq_ctl.v
wire [`JBI_MRQQ_WIDTH-1:0]mrqq_rdata; // From u_mrqq_buf of jbi_ncio_mrqq_buf.v
wire [`JBI_MRQQ_ADDR_WIDTH-1:0]mrqq_waddr; // From u_mrqq_ctl of jbi_ncio_mrqq_ctl.v
wire [`JBI_MRQQ_WIDTH-1:0]mrqq_wdata; // From u_mrqq_ctl of jbi_ncio_mrqq_ctl.v
wire mrqq_wr_en; // From u_mrqq_ctl of jbi_ncio_mrqq_ctl.v
wire mtag_byps; // From u_mtag of jbi_ncio_tag.v
wire mtag_csn_wr; // From u_mrqq_ctl of jbi_ncio_mrqq_ctl.v
wire [3:0] mtag_raddr; // From u_mrqq_ctl of jbi_ncio_mrqq_ctl.v
wire [3:0] mtag_waddr; // From u_mrqq_ctl of jbi_ncio_mrqq_ctl.v
wire pio_ucbp_req_acpted; // From u_prqq_ctl of jbi_ncio_prqq_ctl.v
wire prqq_ack; // From u_prqq_ctl of jbi_ncio_prqq_ctl.v
wire [`UCB_BUF_HI-`UCB_BUF_LO:0]prqq_ack_buf_id;// From u_prqq_ctl of jbi_ncio_prqq_ctl.v
wire [`UCB_THR_HI-`UCB_THR_LO:0]prqq_ack_thr_id;// From u_prqq_ctl of jbi_ncio_prqq_ctl.v
wire prqq_csn_rd; // From u_prqq_ctl of jbi_ncio_prqq_ctl.v
wire prqq_csn_wr; // From u_prqq_ctl of jbi_ncio_prqq_ctl.v
wire [`JBI_PRQQ_ADDR_WIDTH-1:0]prqq_raddr; // From u_prqq_ctl of jbi_ncio_prqq_ctl.v
wire [`UCB_BUF_HI-`UCB_BUF_LO:0]prqq_rd16_buf_id;// From u_prqq_ctl of jbi_ncio_prqq_ctl.v
wire [`UCB_THR_HI-`UCB_THR_LO:0]prqq_rd16_thr_id;// From u_prqq_ctl of jbi_ncio_prqq_ctl.v
wire [`JBI_PRQQ_WIDTH-1:0]prqq_rdata; // From u_prqq_buf of jbi_ncio_prqq_buf.v
wire prqq_stall_rd16; // From u_prqq_ctl of jbi_ncio_prqq_ctl.v
wire [`JBI_PRQQ_ADDR_WIDTH-1:0]prqq_waddr; // From u_prqq_ctl of jbi_ncio_prqq_ctl.v
wire [`JBI_PRQQ_WIDTH-1:0]prqq_wdata; // From u_prqq_ctl of jbi_ncio_prqq_ctl.v
wire [`UCB_BUF_HI-`UCB_BUF_LO:0]prtq_buf_id_out;// From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire prtq_csn_rd; // From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire prtq_csn_wr; // From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire prtq_data128; // From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire [127:0] prtq_data_out; // From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire prtq_decr_rd_pend_cnt; // From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire [`UCB_INT_DEV_WIDTH-1:0]prtq_dev_id; // From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire [`UCB_PKT_WIDTH-1:0]prtq_int_type; // From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire prtq_int_vld; // From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire [`JBI_PRTQ_ADDR_WIDTH-1:0]prtq_raddr; // From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire prtq_rcv_rtrn16; // From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire prtq_rd_ack_vld; // From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire prtq_rd_nack_vld; // From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire [`JBI_PRTQ_WIDTH-1:0]prtq_rdata; // From u_prtq_buf of jbi_ncio_prtq_buf.v
wire prtq_tag_byps; // From u_prtq_tag of jbi_ncio_tag.v
wire [`UCB_THR_HI-`UCB_THR_LO:0]prtq_thr_id_out;// From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire [`JBI_PRTQ_ADDR_WIDTH-1:0]prtq_waddr; // From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire [`JBI_PRTQ_WIDTH-1:0]prtq_wdata; // From u_prtq_ctl of jbi_ncio_prtq_ctl.v
wire ucbp_ack_busy; // From u_ncio_ucbp of ucb_flow_jbi.v
wire [`UCB_ADDR_HI-`UCB_ADDR_LO:0]ucbp_addr_in; // From u_ncio_ucbp of ucb_flow_jbi.v
wire [`UCB_BUF_HI-`UCB_BUF_LO:0]ucbp_buf_id_in; // From u_ncio_ucbp of ucb_flow_jbi.v
wire [`UCB_DATA_HI-`UCB_DATA_LO:0]ucbp_data_in; // From u_ncio_ucbp of ucb_flow_jbi.v
wire ucbp_rd_req_vld; // From u_ncio_ucbp of ucb_flow_jbi.v
wire [`UCB_SIZE_HI-`UCB_SIZE_LO:0]ucbp_size_in; // From u_ncio_ucbp of ucb_flow_jbi.v
wire [`UCB_THR_HI-`UCB_THR_LO:0]ucbp_thr_id_in; // From u_ncio_ucbp of ucb_flow_jbi.v
wire ucbp_wr_req_vld; // From u_ncio_ucbp of ucb_flow_jbi.v
// End of automatics
//
// Code start here
//
//*******************************************************************************
// Flop Sync Pulses
//*******************************************************************************
/* dff_ns AUTO_TEMPLATE (
.din(cpu_rx_en),
.clk(cpu_clk),
.q(cpu_rx_en_ff),
); */
dff_ns #(1) u_dff_cpu_rx_en_ff (/*AUTOINST*/
// Outputs
.q (cpu_rx_en_ff), // Templated
// Inputs
.din (cpu_rx_en), // Templated
.clk (cpu_clk)); // Templated
/* dff_ns AUTO_TEMPLATE (
.din(cpu_tx_en),
.clk(cpu_clk),
.q(cpu_tx_en_ff),
); */
dff_ns #(1) u_dff_cpu_tx_en_ff (/*AUTOINST*/
// Outputs
.q (cpu_tx_en_ff), // Templated
// Inputs
.din (cpu_tx_en), // Templated
.clk (cpu_clk)); // Templated
//*******************************************************************************
// PIO blocks
//*******************************************************************************
//-------------------
// PIO UCB
//-------------------
/* ucb_flow_jbi AUTO_TEMPLATE (
.iob_ucb_\(.*\) (iob_jbi_pio_\1),
.iob_ucb_data (iob_jbi_pio_data),
.ucb_iob_\(.*\) (jbi_iob_pio_\1),
.ucb_iob_data (jbi_iob_pio_data),
.\([a-z]*\)_req_vld (ucbp_\1_req_vld),
.\(.*\)_in (ucbp_\1_in[]),
.req_acpted (pio_ucbp_req_acpted),
.rd_ack_vld (prtq_rd_ack_vld),
.rd_nack_vld (prtq_rd_nack_vld),
.thr_id_out (prtq_thr_id_out[]),
.buf_id_out (prtq_buf_id_out[]),
.data_out (prtq_data_out[127:0]),
.data128 (prtq_data128),
.ack_busy (ucbp_ack_busy),
.int_vld (prtq_int_vld),
.int_typ (prtq_int_type),
.int_thr_id ({`UCB_THR_WIDTH{1'b0}}),
.dev_id (prtq_dev_id),
.int_stat ({`UCB_INT_STAT_WIDTH{1'b0}}),
.int_vec ({`UCB_INT_VEC_WIDTH{1'b0}}),
.int_busy (),
); */
ucb_flow_jbi #(`IOB_JBI_WIDTH,`JBI_IOB_WIDTH) u_ncio_ucbp (/*AUTOINST*/
// Outputs
.ucb_iob_stall(jbi_iob_pio_stall), // Templated
.rd_req_vld(ucbp_rd_req_vld), // Templated
.wr_req_vld(ucbp_wr_req_vld), // Templated
.thr_id_in(ucbp_thr_id_in[`UCB_THR_HI-`UCB_THR_LO:0]), // Templated
.buf_id_in(ucbp_buf_id_in[`UCB_BUF_HI-`UCB_BUF_LO:0]), // Templated
.size_in(ucbp_size_in[`UCB_SIZE_HI-`UCB_SIZE_LO:0]), // Templated
.addr_in(ucbp_addr_in[`UCB_ADDR_HI-`UCB_ADDR_LO:0]), // Templated
.data_in(ucbp_data_in[`UCB_DATA_HI-`UCB_DATA_LO:0]), // Templated
.ack_busy(ucbp_ack_busy), // Templated
.int_busy(), // Templated
.ucb_iob_vld(jbi_iob_pio_vld), // Templated
.ucb_iob_data(jbi_iob_pio_data), // Templated
// Inputs
.clk(clk),
.rst_l(rst_l),
.iob_ucb_vld(iob_jbi_pio_vld), // Templated
.iob_ucb_data(iob_jbi_pio_data), // Templated
.req_acpted(pio_ucbp_req_acpted), // Templated
.rd_ack_vld(prtq_rd_ack_vld), // Templated
.rd_nack_vld(prtq_rd_nack_vld), // Templated
.thr_id_out(prtq_thr_id_out[`UCB_THR_HI-`UCB_THR_LO:0]), // Templated
.buf_id_out(prtq_buf_id_out[`UCB_BUF_HI-`UCB_BUF_LO:0]), // Templated
.data128(prtq_data128), // Templated
.data_out(prtq_data_out[127:0]), // Templated
.int_vld(prtq_int_vld), // Templated
.int_typ(prtq_int_type), // Templated
.int_thr_id({`UCB_THR_WIDTH{1'b0}}), // Templated
.dev_id(prtq_dev_id), // Templated
.int_stat({`UCB_INT_STAT_WIDTH{1'b0}}), // Templated
.int_vec({`UCB_INT_VEC_WIDTH{1'b0}}), // Templated
.iob_ucb_stall(iob_jbi_pio_stall)); // Templated
//-------------------
// PIO Requeust Queue
//-------------------
jbi_ncio_prqq_ctl u_prqq_ctl (/*AUTOINST*/
// Outputs
.ncio_csr_write(ncio_csr_write),
.ncio_csr_write_addr(ncio_csr_write_addr[`JBI_CSR_ADDR_WIDTH-1:0]),
.ncio_csr_write_data(ncio_csr_write_data[`JBI_CSR_WIDTH-1:0]),
.ncio_csr_read_addr(ncio_csr_read_addr[`JBI_CSR_ADDR_WIDTH-1:0]),
.ncio_csr_perf_pio_rd_out(ncio_csr_perf_pio_rd_out),
.ncio_csr_perf_pio_wr(ncio_csr_perf_pio_wr),
.ncio_csr_perf_pio_rd_latency(ncio_csr_perf_pio_rd_latency[4:0]),
.pio_ucbp_req_acpted(pio_ucbp_req_acpted),
.ncio_pio_req(ncio_pio_req),
.ncio_pio_req_rw(ncio_pio_req_rw),
.ncio_pio_req_dest(ncio_pio_req_dest[1:0]),
.ncio_pio_ue(ncio_pio_ue),
.ncio_pio_be(ncio_pio_be[15:0]),
.ncio_pio_ad(ncio_pio_ad[63:0]),
.ncio_yid (ncio_yid[`JBI_YID_WIDTH-1:0]),
.ncio_prqq_level(ncio_prqq_level[`JBI_PRQQ_ADDR_WIDTH:0]),
.prqq_csn_wr(prqq_csn_wr),
.prqq_csn_rd(prqq_csn_rd),
.prqq_waddr(prqq_waddr[`JBI_PRQQ_ADDR_WIDTH-1:0]),
.prqq_wdata(prqq_wdata[`JBI_PRQQ_WIDTH-1:0]),
.prqq_raddr(prqq_raddr[`JBI_PRQQ_ADDR_WIDTH-1:0]),
.prqq_ack (prqq_ack),
.prqq_ack_thr_id(prqq_ack_thr_id[`UCB_THR_HI-`UCB_THR_LO:0]),
.prqq_ack_buf_id(prqq_ack_buf_id[`UCB_BUF_HI-`UCB_BUF_LO:0]),
.prqq_rd16_thr_id(prqq_rd16_thr_id[`UCB_THR_HI-`UCB_THR_LO:0]),
.prqq_rd16_buf_id(prqq_rd16_buf_id[`UCB_BUF_HI-`UCB_BUF_LO:0]),
.prqq_stall_rd16(prqq_stall_rd16),
// Inputs
.clk (clk),
.rst_l (rst_l),
.csr_jbi_config2_max_pio(csr_jbi_config2_max_pio[3:0]),
.ucbp_rd_req_vld(ucbp_rd_req_vld),
.ucbp_wr_req_vld(ucbp_wr_req_vld),
.ucbp_thr_id_in(ucbp_thr_id_in[`UCB_THR_HI-`UCB_THR_LO:0]),
.ucbp_buf_id_in(ucbp_buf_id_in[`UCB_BUF_HI-`UCB_BUF_LO:0]),
.ucbp_size_in(ucbp_size_in[`UCB_SIZE_HI-`UCB_SIZE_LO:0]),
.ucbp_addr_in(ucbp_addr_in[`UCB_ADDR_HI-`UCB_ADDR_LO:0]),
.ucbp_data_in(ucbp_data_in[`UCB_DATA_HI-`UCB_DATA_LO:0]),
.ucbp_ack_busy(ucbp_ack_busy),
.mout_pio_pop(mout_pio_pop),
.mout_pio_req_adv(mout_pio_req_adv),
.prqq_rdata(prqq_rdata[`JBI_PRQQ_WIDTH-1:0]),
.prtq_decr_rd_pend_cnt(prtq_decr_rd_pend_cnt),
.prtq_rcv_rtrn16(prtq_rcv_rtrn16));
jbi_ncio_prqq_buf u_prqq_buf (/*AUTOINST*/
// Outputs
.prqq_rdata(prqq_rdata[`JBI_PRQQ_WIDTH-1:0]),
// Inputs
.clk (clk),
.hold (hold),
.testmux_sel(testmux_sel),
.scan_en (scan_en),
.csr_16x81array_margin(csr_16x81array_margin[4:0]),
.prqq_csn_wr(prqq_csn_wr),
.prqq_csn_rd(prqq_csn_rd),
.prqq_waddr(prqq_waddr[`JBI_PRQQ_ADDR_WIDTH-1:0]),
.prqq_raddr(prqq_raddr[`JBI_PRQQ_ADDR_WIDTH-1:0]),
.prqq_wdata(prqq_wdata[`JBI_PRQQ_WIDTH-1:0]));
//----------------------
// PIO Data Return Queue
//----------------------
jbi_ncio_prtq_ctl u_prtq_ctl (/*AUTOINST*/
// Outputs
.prtq_rd_ack_vld(prtq_rd_ack_vld),
.prtq_rd_nack_vld(prtq_rd_nack_vld),
.prtq_thr_id_out(prtq_thr_id_out[`UCB_THR_HI-`UCB_THR_LO:0]),
.prtq_buf_id_out(prtq_buf_id_out[`UCB_BUF_HI-`UCB_BUF_LO:0]),
.prtq_data_out(prtq_data_out[127:0]),
.prtq_data128(prtq_data128),
.prtq_int_vld(prtq_int_vld),
.prtq_int_type(prtq_int_type[`UCB_PKT_WIDTH-1:0]),
.prtq_dev_id(prtq_dev_id[`UCB_INT_DEV_WIDTH-1:0]),
.ncio_mout_nack_pop(ncio_mout_nack_pop),
.prtq_csn_wr(prtq_csn_wr),
.prtq_csn_rd(prtq_csn_rd),
.prtq_waddr(prtq_waddr[`JBI_PRTQ_ADDR_WIDTH-1:0]),
.prtq_wdata(prtq_wdata[`JBI_PRTQ_WIDTH-1:0]),
.prtq_raddr(prtq_raddr[`JBI_PRTQ_ADDR_WIDTH-1:0]),
.prtq_decr_rd_pend_cnt(prtq_decr_rd_pend_cnt),
.prtq_rcv_rtrn16(prtq_rcv_rtrn16),
// Inputs
.clk (clk),
.rst_l (rst_l),
.csr_jbi_config2_ord_pio(csr_jbi_config2_ord_pio),
.csr_csr_read_data(csr_csr_read_data[`JBI_CSR_WIDTH-1:0]),
.csr_int_req(csr_int_req),
.ucbp_ack_busy(ucbp_ack_busy),
.io_jbi_j_ad_ff(io_jbi_j_ad_ff[127:0]),
.min_pio_rtrn_push(min_pio_rtrn_push),
.min_pio_data_err(min_pio_data_err),
.mout_trans_yid(mout_trans_yid[`JBI_YID_WIDTH-1:0]),
.mout_nack(mout_nack),
.mout_nack_thr_id(mout_nack_thr_id[`UCB_THR_HI-`UCB_THR_LO:0]),
.mout_nack_buf_id(mout_nack_buf_id[`UCB_BUF_HI-`UCB_BUF_LO:0]),
.prtq_rdata(prtq_rdata[`JBI_PRTQ_WIDTH-1:0]),
.prtq_tag_byps(prtq_tag_byps),
.prqq_ack (prqq_ack),
.prqq_ack_thr_id(prqq_ack_thr_id[`UCB_THR_HI-`UCB_THR_LO:0]),
.prqq_ack_buf_id(prqq_ack_buf_id[`UCB_BUF_HI-`UCB_BUF_LO:0]),
.prqq_stall_rd16(prqq_stall_rd16),
.prqq_rd16_thr_id(prqq_rd16_thr_id[`UCB_THR_HI-`UCB_THR_LO:0]),
.prqq_rd16_buf_id(prqq_rd16_buf_id[`UCB_BUF_HI-`UCB_BUF_LO:0]));
jbi_ncio_prtq_buf u_prtq_buf (/*AUTOINST*/
// Outputs
.prtq_rdata(prtq_rdata[`JBI_PRTQ_WIDTH-1:0]),
// Inputs
.clk (clk),
.hold (hold),
.testmux_sel(testmux_sel),
.scan_en (scan_en),
.csr_16x81array_margin(csr_16x81array_margin[4:0]),
.csr_16x65array_margin(csr_16x65array_margin[4:0]),
.prtq_csn_wr(prtq_csn_wr),
.prtq_csn_rd(prtq_csn_rd),
.prtq_waddr(prtq_waddr[`JBI_PRTQ_ADDR_WIDTH-1:0]),
.prtq_raddr(prtq_raddr[`JBI_PRTQ_ADDR_WIDTH-1:0]),
.prtq_wdata(prtq_wdata[`JBI_PRTQ_WIDTH-1:0]));
/* jbi_ncio_tag AUTO_TEMPLATE (
.raddr (prtq_raddr[]),
.waddr (prtq_waddr[]),
.csn_wr (prtq_csn_wr),
.tag_in (min_pre_wri_tag[]),
.tag_byps_in (1'b0),
.j_tag_byps_out (prtq_tag_byps),
.cpu_tx_en (cpu_tx_en_ff),
.cpu_rx_en (cpu_rx_en_ff),
); */
jbi_ncio_tag u_prtq_tag (/*AUTOINST*/
// Outputs
.j_tag_byps_out(prtq_tag_byps), // Templated
// Inputs
.clk (clk),
.rst_l (rst_l),
.cpu_clk (cpu_clk),
.cpu_rst_l (cpu_rst_l),
.cpu_rx_en (cpu_rx_en_ff), // Templated
.cpu_tx_en (cpu_tx_en_ff), // Templated
.min_oldest_wri_tag(min_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_byps_in (1'b0), // Templated
.tag_in (min_pre_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]), // Templated
.csn_wr (prtq_csn_wr), // Templated
.waddr (prtq_waddr[3:0]), // Templated
.raddr (prtq_raddr[3:0])); // Templated
//*******************************************************************************
// Mondo Block
//*******************************************************************************
//---------------------
// Mondo Requeust Queue
//---------------------
jbi_ncio_mrqq_ctl u_mrqq_ctl (/*AUTOINST*/
// Outputs
.jbi_iob_mondo_vld(jbi_iob_mondo_vld),
.jbi_iob_mondo_data(jbi_iob_mondo_data[`JBI_IOB_MONDO_BUS_WIDTH-1:0]),
.iob_jbi_mondo_ack_ff(iob_jbi_mondo_ack_ff),
.iob_jbi_mondo_nack_ff(iob_jbi_mondo_nack_ff),
.makq_push(makq_push),
.makq_wdata(makq_wdata[`JBI_MAKQ_WIDTH-1:0]),
.makq_nack(makq_nack),
.mrqq_wr_en(mrqq_wr_en),
.mrqq_rd_en(mrqq_rd_en),
.mrqq_waddr(mrqq_waddr[`JBI_MRQQ_ADDR_WIDTH-1:0]),
.mrqq_wdata(mrqq_wdata[`JBI_MRQQ_WIDTH-1:0]),
.mrqq_raddr(mrqq_raddr[`JBI_MRQQ_ADDR_WIDTH-1:0]),
.mtag_csn_wr(mtag_csn_wr),
.mtag_waddr(mtag_waddr[3:0]),
.mtag_raddr(mtag_raddr[3:0]),
// Inputs
.clk (clk),
.rst_l (rst_l),
.csr_jbi_config2_ord_int(csr_jbi_config2_ord_int),
.io_jbi_j_ad_ff(io_jbi_j_ad_ff[127:0]),
.min_mondo_hdr_push(min_mondo_hdr_push),
.min_mondo_data_push(min_mondo_data_push),
.min_mondo_data_err(min_mondo_data_err),
.iob_jbi_mondo_ack(iob_jbi_mondo_ack),
.iob_jbi_mondo_nack(iob_jbi_mondo_nack),
.mrqq_rdata(mrqq_rdata[`JBI_MRQQ_WIDTH-1:0]),
.mtag_byps(mtag_byps));
jbi_ncio_mrqq_buf u_mrqq_buf (/*AUTOINST*/
// Outputs
.mrqq_rdata(mrqq_rdata[`JBI_MRQQ_WIDTH-1:0]),
// Inputs
.clk (clk),
.arst_l (arst_l),
.hold (hold),
.rst_tri_en(rst_tri_en),
.mrqq_wr_en(mrqq_wr_en),
.mrqq_rd_en(mrqq_rd_en),
.mrqq_waddr(mrqq_waddr[`JBI_MRQQ_ADDR_WIDTH-1:0]),
.mrqq_raddr(mrqq_raddr[`JBI_MRQQ_ADDR_WIDTH-1:0]),
.mrqq_wdata(mrqq_wdata[`JBI_MRQQ_WIDTH-1:0]));
/* jbi_ncio_tag AUTO_TEMPLATE (
.raddr (mtag_raddr[]),
.waddr (mtag_waddr[]),
.csn_wr (mtag_csn_wr),
.tag_in (min_pre_wri_tag[]),
.tag_byps_in (1'b0),
.j_tag_byps_out (mtag_byps),
.cpu_tx_en (cpu_tx_en_ff),
.cpu_rx_en (cpu_rx_en_ff),
); */
jbi_ncio_tag u_mtag (/*AUTOINST*/
// Outputs
.j_tag_byps_out (mtag_byps), // Templated
// Inputs
.clk (clk),
.rst_l (rst_l),
.cpu_clk (cpu_clk),
.cpu_rst_l (cpu_rst_l),
.cpu_rx_en (cpu_rx_en_ff), // Templated
.cpu_tx_en (cpu_tx_en_ff), // Templated
.min_oldest_wri_tag(min_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_byps_in (1'b0), // Templated
.tag_in (min_pre_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]), // Templated
.csn_wr (mtag_csn_wr), // Templated
.waddr (mtag_waddr[3:0]), // Templated
.raddr (mtag_raddr[3:0])); // Templated
//---------------------
// Mondo Ack Queue
//---------------------
jbi_ncio_makq_ctl u_makq_ctl (/*AUTOINST*/
// Outputs
.makq_csn_wr(makq_csn_wr),
.makq_waddr(makq_waddr[`JBI_MAKQ_ADDR_WIDTH-1:0]),
.makq_raddr(makq_raddr[`JBI_MAKQ_ADDR_WIDTH-1:0]),
.ncio_mondo_req(ncio_mondo_req),
.ncio_mondo_ack(ncio_mondo_ack),
.ncio_mondo_agnt_id(ncio_mondo_agnt_id[`JBI_AD_INT_AGTID_WIDTH-1:0]),
.ncio_mondo_cpu_id(ncio_mondo_cpu_id[`JBI_AD_INT_CPUID_WIDTH-1:0]),
.ncio_makq_level(ncio_makq_level[`JBI_MAKQ_ADDR_WIDTH:0]),
// Inputs
.clk (clk),
.rst_l (rst_l),
.makq_push(makq_push),
.makq_nack(makq_nack),
.iob_jbi_mondo_ack_ff(iob_jbi_mondo_ack_ff),
.iob_jbi_mondo_nack_ff(iob_jbi_mondo_nack_ff),
.makq_rdata(makq_rdata[`JBI_MAKQ_WIDTH-1:0]),
.mout_mondo_pop(mout_mondo_pop));
/*jbi_1r1w_16x10 AUTO_TEMPLATE (
.do (makq_rdata[]),
.rd_a (makq_raddr[]),
.wr_a (makq_waddr[]),
.di (makq_wdata[]),
.rd_clk (clk),
.wr_clk (clk),
.csn_rd (makq_csn_rd),
.csn_wr (makq_csn_wr),
); */
jbi_1r1w_16x10 u_makq_buf (/*AUTOINST*/
// Outputs
.do (makq_rdata[9:0]), // Templated
// Inputs
.rd_a (makq_raddr[3:0]), // Templated
.wr_a (makq_waddr[3:0]), // Templated
.di (makq_wdata[9:0]), // Templated
.rd_clk (clk), // Templated
.wr_clk (clk), // Templated
.csn_wr (makq_csn_wr)); // Templated
//---------------------
// Mondo IntAck Timeout
//---------------------
jbi_ncio_mto_ctl u_mto (/*AUTOINST*/
// Outputs
.ncio_csr_err_intr_to(ncio_csr_err_intr_to[31:0]),
// Inputs
.clk (clk),
.rst_l (rst_l),
.csr_jbi_intr_timeout_timeval(csr_jbi_intr_timeout_timeval[31:0]),
.csr_jbi_intr_timeout_rst_l(csr_jbi_intr_timeout_rst_l),
.mout_mondo_pop (mout_mondo_pop),
.ncio_mondo_ack (ncio_mondo_ack),
.ncio_mondo_cpu_id(ncio_mondo_cpu_id[`JBI_AD_INT_CPUID_WIDTH-1:0]),
.min_mondo_hdr_push(min_mondo_hdr_push),
.io_jbi_j_ad_ff (io_jbi_j_ad_ff[`JBI_AD_INT_CPUID_HI:`JBI_AD_INT_CPUID_LO]));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/rtl" "../../../common/rtl")
// verilog-library-files:("../../../common/rtl/swrvr_u1_clib.v")
// verilog-auto-sense-defines-constant:t
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MAJ3_BLACKBOX_V
`define SKY130_FD_SC_HS__MAJ3_BLACKBOX_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__maj3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MAJ3_BLACKBOX_V
|
/* Concrete parameterizations of a census transform for testing.
*
* Copyright (c) 2016, Stephen Longfield, stephenlongfield.com
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`include "census.v"
module census_test(
input clk,
input rst,
input wire [(32*5*5-1):0] inp,
output wire [(5*5-1):0] outp
);
census#(.WIDTH(32), .WINDOW_WIDTH(5), .WINDOW_HEIGHT(5))
ct(clk, rst, inp, outp);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module start_for_Loop_lojbC_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module start_for_Loop_lojbC (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_Loop_lojbC_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_start_for_Loop_lojbC_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTN_BLACKBOX_V
`define SKY130_FD_SC_HD__DLRTN_BLACKBOX_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTN_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9643 (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// master-slave interface
adc_start_out,
dma_start_out,
adc_start_in,
dma_start_in,
// delay interface
delay_clk,
// dma interface
adc_dvalid,
adc_ddata,
adc_overflow,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
// debug signals
adc_clk,
adc_mon_valid,
adc_mon_data);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// master-slave interface
output adc_start_out;
output dma_start_out;
input adc_start_in;
input dma_start_in;
// delay interface
input delay_clk;
// dma interface
output adc_dvalid;
output [63:0] adc_ddata;
input adc_overflow;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// debug signals
output adc_clk;
output adc_mon_valid;
output [59:0] adc_mon_data;
// internal registers
reg adc_start_out = 'd0;
reg [ 1:0] adc_data_cnt = 'd0;
reg adc_valid = 'd0;
reg [63:0] adc_data = 'd0;
reg up_adc_status_pn_err = 'd0;
reg up_adc_status_pn_oos = 'd0;
reg up_adc_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire adc_start_s;
wire dma_start_s;
wire [13:0] adc_data_a_s;
wire [13:0] adc_data_b_s;
wire adc_or_a_s;
wire adc_or_b_s;
wire [15:0] adc_dcfilter_data_a_s;
wire [15:0] adc_dcfilter_data_b_s;
wire [15:0] adc_channel_data_a_s;
wire [15:0] adc_channel_data_b_s;
wire adc_enable_a_s;
wire adc_enable_b_s;
wire up_adc_pn_err_a_s;
wire up_adc_pn_oos_a_s;
wire up_adc_or_a_s;
wire up_adc_pn_err_b_s;
wire up_adc_pn_oos_b_s;
wire up_adc_or_b_s;
wire adc_ddr_edgesel_s;
wire adc_pin_mode_s;
wire adc_status_s;
wire delay_rst_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire delay_locked_s;
wire dma_valid_s;
wire dma_last_s;
wire [63:0] dma_data_s;
wire dma_ready_s;
wire dma_status_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
wire [31:0] up_adc_channel_rdata_a_s;
wire up_adc_channel_ack_a_s;
wire [31:0] up_adc_channel_rdata_b_s;
wire up_adc_channel_ack_b_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// monitor signals
assign adc_mon_valid = 1'b1;
assign adc_mon_data[15: 0] = adc_channel_data_a_s;
assign adc_mon_data[31:16] = adc_channel_data_b_s;
assign adc_mon_data[45:32] = adc_data_a_s;
assign adc_mon_data[59:46] = adc_data_b_s;
// multiple instances synchronization
assign adc_start_s = (PCORE_ID == 32'd0) ? adc_start_out : adc_start_in;
assign dma_start_s = (PCORE_ID == 32'd0) ? dma_start_out : dma_start_in;
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
adc_start_out <= 1'b0;
end else begin
adc_start_out <= 1'b1;
end
end
// User Channels
// ----------------------------
// The default provided here has two channels. However, provisions are added to software
// to support up to 16 user channels (that is 14, if you keep these two as it is).
// The channels may implement any post processing- such as decimation or filtering.
// If using the same processor controls, an enable is provided for each channel.
// You may use this signal to control the write to the DMA interface.
// Also note that the data bitwidths may require padding or truncation to match the
// external DMA bus width. This design as it is, uses 64bits.
// THIS IS NOT A COMPLETE SOLUTION and individual needs may vary.
// adc channels - dma interface
always @(posedge adc_clk) begin
adc_data_cnt <= adc_data_cnt + 1'b1;
case ({adc_enable_b_s, adc_enable_a_s})
2'b11: begin // both I and Q
adc_valid <= adc_data_cnt[0] & adc_start_s;
adc_data <= {adc_channel_data_b_s, adc_channel_data_a_s, adc_data[63:32]};
end
2'b10: begin // Q only
adc_valid <= adc_data_cnt[0] & adc_data_cnt[1] & adc_start_s;
adc_data <= {adc_channel_data_b_s, adc_data[63:16]};
end
2'b01: begin // I only
adc_valid <= adc_data_cnt[0] & adc_data_cnt[1] & adc_start_s;
adc_data <= {adc_channel_data_a_s, adc_data[63:16]};
end
default: begin // no channels
adc_valid <= adc_start_s;
adc_data <= {4{16'hdead}};
end
endcase
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_status_pn_err <= 'd0;
up_adc_status_pn_oos <= 'd0;
up_adc_status_or <= 'd0;
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_adc_status_pn_err <= up_adc_pn_err_a_s | up_adc_pn_err_b_s;
up_adc_status_pn_oos <= up_adc_pn_oos_a_s | up_adc_pn_oos_b_s;
up_adc_status_or <= up_adc_or_a_s | up_adc_or_b_s;
up_rdata <= up_adc_common_rdata_s | up_adc_channel_rdata_a_s | up_adc_channel_rdata_b_s;
up_ack <= up_adc_common_ack_s | up_adc_channel_ack_a_s | up_adc_channel_ack_b_s;
end
end
// channel
axi_ad9643_channel #(.IQSEL(0), .CHID(0)) i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
.adc_or (adc_or_a_s),
.adc_dcfilter_data_out (adc_dcfilter_data_a_s),
.adc_dcfilter_data_in (adc_dcfilter_data_b_s),
.adc_iqcor_data (adc_channel_data_a_s),
.adc_enable (adc_enable_a_s),
.up_adc_pn_err (up_adc_pn_err_a_s),
.up_adc_pn_oos (up_adc_pn_oos_a_s),
.up_adc_or (up_adc_or_a_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_a_s),
.up_ack (up_adc_channel_ack_a_s));
// channel
axi_ad9643_channel #(.IQSEL(1), .CHID(1)) i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
.adc_or (adc_or_b_s),
.adc_dcfilter_data_out (adc_dcfilter_data_b_s),
.adc_dcfilter_data_in (adc_dcfilter_data_a_s),
.adc_iqcor_data (adc_channel_data_b_s),
.adc_enable (adc_enable_b_s),
.up_adc_pn_err (up_adc_pn_err_b_s),
.up_adc_pn_oos (up_adc_pn_oos_b_s),
.up_adc_or (up_adc_or_b_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_b_s),
.up_ack (up_adc_channel_ack_b_s));
// main (dma interface)
assign adc_dvalid = adc_valid;
assign adc_ddata = adc_data;
// main (device interface)
axi_ad9643_if #(
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_clk (adc_clk),
.adc_data_a (adc_data_a_s),
.adc_data_b (adc_data_b_s),
.adc_or_a (adc_or_a_s),
.adc_or_b (adc_or_b_s),
.adc_status (adc_status_s),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (adc_pin_mode_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s));
// common processor control
up_adc_common #(
.PCORE_ID(PCORE_ID),
.PCORE_VERSION(32'h00060061)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (adc_pin_mode_s),
.adc_status (adc_status_s),
.adc_status_pn_err (up_adc_status_pn_err),
.adc_status_pn_oos (up_adc_status_pn_oos),
.adc_status_or (up_adc_status_or),
.adc_clk_ratio (32'd1),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ack_t (1'd0),
.dma_clk (adc_clk),
.dma_start (dma_start_out),
.dma_stream (),
.dma_count (),
.dma_ovf (adc_overflow),
.dma_unf (1'b0),
.dma_bw (32'h00000008),
.dma_status (dma_status_s),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_common_rdata_s),
.up_ack (up_adc_common_ack_s));
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 13:58:03 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_exp_operation_A_S,
FSM_selector_A, FSM_selector_C, Exp_module_Overflow_flag_A, n167,
n168, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179,
n180, n181, n182, n183, n184, n185, n186, n187, n188, n189, n190,
n191, n192, n193, n194, n195, n196, n197, n198, n199, n200, n201,
n202, n203, n204, n205, n206, n207, n208, n209, n210, n211, n212,
n213, n214, n215, n216, n217, n218, n219, n220, n221, n222, n223,
n224, n225, n226, n227, n228, n229, n230, n231, n232, n233, n234,
n235, n236, n237, n238, n239, n240, n241, n242, n243, n244, n245,
n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, n256,
n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267,
n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278,
n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, n289,
n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300,
n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, n311,
n312, n313, n314, n315, n316, n317, n318, n319, n320, n321, n322,
n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, n333,
n334, n335, n336, n337, n338, n339, n340, n341, n342, n343, n344,
n345, n346, n347, n348, n349, n350, n351, n352, n353, n354, n355,
n356, n357, n358, n359, n360, n361, n362, n363, n364, n365, n366,
n367, n368, n369, n370, n371, n372, n373, n374, n375, n376, n377,
n378, n379, n380, n381, DP_OP_36J3_123_9196_n22,
DP_OP_36J3_123_9196_n21, DP_OP_36J3_123_9196_n20,
DP_OP_36J3_123_9196_n19, DP_OP_36J3_123_9196_n18,
DP_OP_36J3_123_9196_n17, DP_OP_36J3_123_9196_n16,
DP_OP_36J3_123_9196_n15, DP_OP_36J3_123_9196_n9,
DP_OP_36J3_123_9196_n8, DP_OP_36J3_123_9196_n7,
DP_OP_36J3_123_9196_n6, DP_OP_36J3_123_9196_n5,
DP_OP_36J3_123_9196_n4, DP_OP_36J3_123_9196_n3,
DP_OP_36J3_123_9196_n2, DP_OP_36J3_123_9196_n1,
DP_OP_110J3_122_4535_n1246, DP_OP_110J3_122_4535_n1142,
DP_OP_110J3_122_4535_n1138, DP_OP_110J3_122_4535_n1130,
DP_OP_110J3_122_4535_n1129, DP_OP_110J3_122_4535_n1126,
DP_OP_110J3_122_4535_n1125, DP_OP_110J3_122_4535_n1123,
DP_OP_110J3_122_4535_n1122, DP_OP_110J3_122_4535_n1121,
DP_OP_110J3_122_4535_n1118, DP_OP_110J3_122_4535_n1117,
DP_OP_110J3_122_4535_n1116, DP_OP_110J3_122_4535_n1115,
DP_OP_110J3_122_4535_n1114, DP_OP_110J3_122_4535_n1113,
DP_OP_110J3_122_4535_n1112, DP_OP_110J3_122_4535_n1110,
DP_OP_110J3_122_4535_n1109, DP_OP_110J3_122_4535_n1108,
DP_OP_110J3_122_4535_n1107, DP_OP_110J3_122_4535_n1106,
DP_OP_110J3_122_4535_n1105, DP_OP_110J3_122_4535_n1104,
DP_OP_110J3_122_4535_n1102, DP_OP_110J3_122_4535_n1101,
DP_OP_110J3_122_4535_n1100, DP_OP_110J3_122_4535_n1099,
DP_OP_110J3_122_4535_n1096, DP_OP_110J3_122_4535_n1095,
DP_OP_110J3_122_4535_n1093, DP_OP_110J3_122_4535_n1090,
DP_OP_110J3_122_4535_n1089, DP_OP_110J3_122_4535_n1088,
DP_OP_110J3_122_4535_n1086, DP_OP_110J3_122_4535_n1085,
DP_OP_110J3_122_4535_n1084, DP_OP_110J3_122_4535_n1083,
DP_OP_110J3_122_4535_n1080, DP_OP_110J3_122_4535_n1079,
DP_OP_110J3_122_4535_n1078, DP_OP_110J3_122_4535_n1077,
DP_OP_110J3_122_4535_n1076, DP_OP_110J3_122_4535_n1075,
DP_OP_110J3_122_4535_n1074, DP_OP_110J3_122_4535_n1073,
DP_OP_110J3_122_4535_n1072, DP_OP_110J3_122_4535_n1071,
DP_OP_110J3_122_4535_n1070, DP_OP_110J3_122_4535_n1069,
DP_OP_110J3_122_4535_n1068, DP_OP_110J3_122_4535_n1067,
DP_OP_110J3_122_4535_n1047, DP_OP_110J3_122_4535_n1044,
DP_OP_110J3_122_4535_n1043, DP_OP_110J3_122_4535_n1042,
DP_OP_110J3_122_4535_n1041, DP_OP_110J3_122_4535_n1040,
DP_OP_110J3_122_4535_n1039, DP_OP_110J3_122_4535_n1038,
DP_OP_110J3_122_4535_n1037, DP_OP_110J3_122_4535_n1036,
DP_OP_110J3_122_4535_n1035, DP_OP_110J3_122_4535_n1034,
DP_OP_110J3_122_4535_n1033, DP_OP_110J3_122_4535_n1032,
DP_OP_110J3_122_4535_n1031, DP_OP_110J3_122_4535_n1030,
DP_OP_110J3_122_4535_n1029, DP_OP_110J3_122_4535_n1028,
DP_OP_110J3_122_4535_n1027, DP_OP_110J3_122_4535_n1026,
DP_OP_110J3_122_4535_n1025, DP_OP_110J3_122_4535_n1024,
DP_OP_110J3_122_4535_n1023, DP_OP_110J3_122_4535_n1022,
DP_OP_110J3_122_4535_n1021, DP_OP_110J3_122_4535_n1020,
DP_OP_110J3_122_4535_n1019, DP_OP_110J3_122_4535_n1018,
DP_OP_110J3_122_4535_n1017, DP_OP_110J3_122_4535_n1016,
DP_OP_110J3_122_4535_n1015, DP_OP_110J3_122_4535_n1014,
DP_OP_110J3_122_4535_n1013, DP_OP_110J3_122_4535_n1012,
DP_OP_110J3_122_4535_n1011, DP_OP_110J3_122_4535_n1010,
DP_OP_110J3_122_4535_n1009, DP_OP_110J3_122_4535_n1008,
DP_OP_110J3_122_4535_n1007, DP_OP_110J3_122_4535_n1006,
DP_OP_110J3_122_4535_n1005, DP_OP_110J3_122_4535_n1004,
DP_OP_110J3_122_4535_n1003, DP_OP_110J3_122_4535_n1001,
DP_OP_110J3_122_4535_n1000, DP_OP_110J3_122_4535_n999,
DP_OP_110J3_122_4535_n998, DP_OP_110J3_122_4535_n997,
DP_OP_110J3_122_4535_n996, DP_OP_110J3_122_4535_n995,
DP_OP_110J3_122_4535_n994, DP_OP_110J3_122_4535_n991,
DP_OP_110J3_122_4535_n990, DP_OP_110J3_122_4535_n989,
DP_OP_110J3_122_4535_n988, DP_OP_110J3_122_4535_n987,
DP_OP_110J3_122_4535_n986, DP_OP_110J3_122_4535_n985,
DP_OP_110J3_122_4535_n984, DP_OP_110J3_122_4535_n983,
DP_OP_110J3_122_4535_n982, DP_OP_110J3_122_4535_n981,
DP_OP_110J3_122_4535_n980, DP_OP_110J3_122_4535_n979,
DP_OP_110J3_122_4535_n978, DP_OP_110J3_122_4535_n977,
DP_OP_110J3_122_4535_n976, DP_OP_110J3_122_4535_n973,
DP_OP_110J3_122_4535_n972, DP_OP_110J3_122_4535_n971,
DP_OP_110J3_122_4535_n970, DP_OP_110J3_122_4535_n969,
DP_OP_110J3_122_4535_n968, DP_OP_110J3_122_4535_n967,
DP_OP_110J3_122_4535_n966, DP_OP_110J3_122_4535_n965,
DP_OP_110J3_122_4535_n964, DP_OP_110J3_122_4535_n963,
DP_OP_110J3_122_4535_n962, DP_OP_110J3_122_4535_n959,
DP_OP_110J3_122_4535_n958, DP_OP_110J3_122_4535_n957,
DP_OP_110J3_122_4535_n956, DP_OP_110J3_122_4535_n955,
DP_OP_110J3_122_4535_n954, DP_OP_110J3_122_4535_n953,
DP_OP_110J3_122_4535_n952, DP_OP_110J3_122_4535_n951,
DP_OP_110J3_122_4535_n950, DP_OP_110J3_122_4535_n948,
DP_OP_110J3_122_4535_n947, DP_OP_110J3_122_4535_n946,
DP_OP_110J3_122_4535_n945, DP_OP_110J3_122_4535_n944,
DP_OP_110J3_122_4535_n943, DP_OP_110J3_122_4535_n942,
DP_OP_110J3_122_4535_n905, DP_OP_110J3_122_4535_n761,
DP_OP_110J3_122_4535_n757, DP_OP_110J3_122_4535_n749,
DP_OP_110J3_122_4535_n748, DP_OP_110J3_122_4535_n745,
DP_OP_110J3_122_4535_n744, DP_OP_110J3_122_4535_n742,
DP_OP_110J3_122_4535_n741, DP_OP_110J3_122_4535_n740,
DP_OP_110J3_122_4535_n737, DP_OP_110J3_122_4535_n736,
DP_OP_110J3_122_4535_n735, DP_OP_110J3_122_4535_n734,
DP_OP_110J3_122_4535_n733, DP_OP_110J3_122_4535_n732,
DP_OP_110J3_122_4535_n731, DP_OP_110J3_122_4535_n729,
DP_OP_110J3_122_4535_n728, DP_OP_110J3_122_4535_n727,
DP_OP_110J3_122_4535_n726, DP_OP_110J3_122_4535_n725,
DP_OP_110J3_122_4535_n724, DP_OP_110J3_122_4535_n723,
DP_OP_110J3_122_4535_n721, DP_OP_110J3_122_4535_n720,
DP_OP_110J3_122_4535_n719, DP_OP_110J3_122_4535_n718,
DP_OP_110J3_122_4535_n715, DP_OP_110J3_122_4535_n714,
DP_OP_110J3_122_4535_n712, DP_OP_110J3_122_4535_n709,
DP_OP_110J3_122_4535_n708, DP_OP_110J3_122_4535_n707,
DP_OP_110J3_122_4535_n705, DP_OP_110J3_122_4535_n704,
DP_OP_110J3_122_4535_n703, DP_OP_110J3_122_4535_n702,
DP_OP_110J3_122_4535_n699, DP_OP_110J3_122_4535_n698,
DP_OP_110J3_122_4535_n697, DP_OP_110J3_122_4535_n696,
DP_OP_110J3_122_4535_n695, DP_OP_110J3_122_4535_n694,
DP_OP_110J3_122_4535_n693, DP_OP_110J3_122_4535_n692,
DP_OP_110J3_122_4535_n691, DP_OP_110J3_122_4535_n690,
DP_OP_110J3_122_4535_n689, DP_OP_110J3_122_4535_n688,
DP_OP_110J3_122_4535_n687, DP_OP_110J3_122_4535_n686,
DP_OP_110J3_122_4535_n680, DP_OP_110J3_122_4535_n678,
DP_OP_110J3_122_4535_n665, DP_OP_110J3_122_4535_n662,
DP_OP_110J3_122_4535_n661, DP_OP_110J3_122_4535_n660,
DP_OP_110J3_122_4535_n659, DP_OP_110J3_122_4535_n658,
DP_OP_110J3_122_4535_n657, DP_OP_110J3_122_4535_n656,
DP_OP_110J3_122_4535_n655, DP_OP_110J3_122_4535_n654,
DP_OP_110J3_122_4535_n653, DP_OP_110J3_122_4535_n652,
DP_OP_110J3_122_4535_n651, DP_OP_110J3_122_4535_n650,
DP_OP_110J3_122_4535_n649, DP_OP_110J3_122_4535_n648,
DP_OP_110J3_122_4535_n647, DP_OP_110J3_122_4535_n646,
DP_OP_110J3_122_4535_n645, DP_OP_110J3_122_4535_n644,
DP_OP_110J3_122_4535_n643, DP_OP_110J3_122_4535_n642,
DP_OP_110J3_122_4535_n641, DP_OP_110J3_122_4535_n640,
DP_OP_110J3_122_4535_n639, DP_OP_110J3_122_4535_n638,
DP_OP_110J3_122_4535_n637, DP_OP_110J3_122_4535_n636,
DP_OP_110J3_122_4535_n635, DP_OP_110J3_122_4535_n634,
DP_OP_110J3_122_4535_n633, DP_OP_110J3_122_4535_n632,
DP_OP_110J3_122_4535_n631, DP_OP_110J3_122_4535_n630,
DP_OP_110J3_122_4535_n629, DP_OP_110J3_122_4535_n628,
DP_OP_110J3_122_4535_n627, DP_OP_110J3_122_4535_n626,
DP_OP_110J3_122_4535_n625, DP_OP_110J3_122_4535_n624,
DP_OP_110J3_122_4535_n623, DP_OP_110J3_122_4535_n622,
DP_OP_110J3_122_4535_n621, DP_OP_110J3_122_4535_n619,
DP_OP_110J3_122_4535_n618, DP_OP_110J3_122_4535_n617,
DP_OP_110J3_122_4535_n616, DP_OP_110J3_122_4535_n615,
DP_OP_110J3_122_4535_n614, DP_OP_110J3_122_4535_n613,
DP_OP_110J3_122_4535_n612, DP_OP_110J3_122_4535_n609,
DP_OP_110J3_122_4535_n608, DP_OP_110J3_122_4535_n607,
DP_OP_110J3_122_4535_n606, DP_OP_110J3_122_4535_n605,
DP_OP_110J3_122_4535_n604, DP_OP_110J3_122_4535_n603,
DP_OP_110J3_122_4535_n602, DP_OP_110J3_122_4535_n601,
DP_OP_110J3_122_4535_n600, DP_OP_110J3_122_4535_n599,
DP_OP_110J3_122_4535_n598, DP_OP_110J3_122_4535_n597,
DP_OP_110J3_122_4535_n596, DP_OP_110J3_122_4535_n595,
DP_OP_110J3_122_4535_n594, DP_OP_110J3_122_4535_n593,
DP_OP_110J3_122_4535_n592, DP_OP_110J3_122_4535_n591,
DP_OP_110J3_122_4535_n590, DP_OP_110J3_122_4535_n589,
DP_OP_110J3_122_4535_n588, DP_OP_110J3_122_4535_n587,
DP_OP_110J3_122_4535_n586, DP_OP_110J3_122_4535_n585,
DP_OP_110J3_122_4535_n584, DP_OP_110J3_122_4535_n583,
DP_OP_110J3_122_4535_n582, DP_OP_110J3_122_4535_n581,
DP_OP_110J3_122_4535_n580, DP_OP_110J3_122_4535_n577,
DP_OP_110J3_122_4535_n576, DP_OP_110J3_122_4535_n575,
DP_OP_110J3_122_4535_n574, DP_OP_110J3_122_4535_n573,
DP_OP_110J3_122_4535_n572, DP_OP_110J3_122_4535_n571,
DP_OP_110J3_122_4535_n570, DP_OP_110J3_122_4535_n569,
DP_OP_110J3_122_4535_n568, DP_OP_110J3_122_4535_n567,
DP_OP_110J3_122_4535_n566, DP_OP_110J3_122_4535_n565,
DP_OP_110J3_122_4535_n564, DP_OP_110J3_122_4535_n563,
DP_OP_110J3_122_4535_n562, DP_OP_110J3_122_4535_n561,
DP_OP_110J3_122_4535_n560, DP_OP_110J3_122_4535_n528,
DP_OP_110J3_122_4535_n527, DP_OP_110J3_122_4535_n526,
DP_OP_110J3_122_4535_n525, DP_OP_110J3_122_4535_n523,
DP_OP_110J3_122_4535_n522, DP_OP_110J3_122_4535_n521,
DP_OP_110J3_122_4535_n520, DP_OP_110J3_122_4535_n519,
DP_OP_110J3_122_4535_n518, DP_OP_110J3_122_4535_n517,
DP_OP_110J3_122_4535_n516, DP_OP_110J3_122_4535_n513,
DP_OP_110J3_122_4535_n508, DP_OP_110J3_122_4535_n346,
DP_OP_110J3_122_4535_n344, DP_OP_110J3_122_4535_n342,
DP_OP_110J3_122_4535_n341, DP_OP_110J3_122_4535_n340,
DP_OP_110J3_122_4535_n339, DP_OP_110J3_122_4535_n338,
DP_OP_110J3_122_4535_n337, DP_OP_110J3_122_4535_n336,
DP_OP_110J3_122_4535_n335, DP_OP_110J3_122_4535_n333,
DP_OP_110J3_122_4535_n332, DP_OP_110J3_122_4535_n329,
DP_OP_110J3_122_4535_n325, DP_OP_110J3_122_4535_n324,
DP_OP_110J3_122_4535_n323, DP_OP_110J3_122_4535_n322,
DP_OP_110J3_122_4535_n321, DP_OP_110J3_122_4535_n317,
DP_OP_110J3_122_4535_n316, DP_OP_110J3_122_4535_n312,
DP_OP_110J3_122_4535_n308, DP_OP_110J3_122_4535_n307,
DP_OP_110J3_122_4535_n306, DP_OP_110J3_122_4535_n305,
DP_OP_110J3_122_4535_n304, DP_OP_110J3_122_4535_n303,
DP_OP_110J3_122_4535_n302, DP_OP_110J3_122_4535_n301,
DP_OP_110J3_122_4535_n299, DP_OP_110J3_122_4535_n292,
DP_OP_110J3_122_4535_n291, DP_OP_110J3_122_4535_n288,
DP_OP_110J3_122_4535_n287, DP_OP_110J3_122_4535_n286,
DP_OP_110J3_122_4535_n285, DP_OP_110J3_122_4535_n284,
DP_OP_110J3_122_4535_n283, DP_OP_110J3_122_4535_n279,
DP_OP_110J3_122_4535_n278, DP_OP_110J3_122_4535_n275,
DP_OP_110J3_122_4535_n274, DP_OP_110J3_122_4535_n273,
DP_OP_110J3_122_4535_n272, DP_OP_110J3_122_4535_n271,
DP_OP_110J3_122_4535_n270, DP_OP_110J3_122_4535_n269,
DP_OP_110J3_122_4535_n268, DP_OP_110J3_122_4535_n267,
DP_OP_110J3_122_4535_n266, DP_OP_110J3_122_4535_n265,
DP_OP_110J3_122_4535_n264, DP_OP_110J3_122_4535_n263,
DP_OP_110J3_122_4535_n262, DP_OP_110J3_122_4535_n261,
DP_OP_110J3_122_4535_n259, DP_OP_110J3_122_4535_n258,
DP_OP_110J3_122_4535_n257, DP_OP_110J3_122_4535_n256,
DP_OP_110J3_122_4535_n255, DP_OP_110J3_122_4535_n254,
DP_OP_110J3_122_4535_n253, DP_OP_110J3_122_4535_n252,
DP_OP_110J3_122_4535_n249, DP_OP_110J3_122_4535_n248,
DP_OP_110J3_122_4535_n246, DP_OP_110J3_122_4535_n243,
DP_OP_110J3_122_4535_n242, DP_OP_110J3_122_4535_n241,
DP_OP_110J3_122_4535_n240, DP_OP_110J3_122_4535_n239,
DP_OP_110J3_122_4535_n236, DP_OP_110J3_122_4535_n235,
DP_OP_110J3_122_4535_n234, DP_OP_110J3_122_4535_n233,
DP_OP_110J3_122_4535_n232, DP_OP_110J3_122_4535_n231,
DP_OP_110J3_122_4535_n230, DP_OP_110J3_122_4535_n229,
DP_OP_110J3_122_4535_n228, DP_OP_110J3_122_4535_n227,
DP_OP_110J3_122_4535_n226, DP_OP_110J3_122_4535_n225,
DP_OP_110J3_122_4535_n224, DP_OP_110J3_122_4535_n223,
DP_OP_110J3_122_4535_n222, DP_OP_110J3_122_4535_n221,
DP_OP_110J3_122_4535_n220, DP_OP_110J3_122_4535_n219,
DP_OP_110J3_122_4535_n218, DP_OP_110J3_122_4535_n217,
DP_OP_110J3_122_4535_n216, DP_OP_110J3_122_4535_n212,
DP_OP_110J3_122_4535_n211, DP_OP_110J3_122_4535_n210,
DP_OP_110J3_122_4535_n207, DP_OP_110J3_122_4535_n206,
DP_OP_110J3_122_4535_n205, DP_OP_110J3_122_4535_n204,
DP_OP_110J3_122_4535_n202, DP_OP_110J3_122_4535_n201,
DP_OP_110J3_122_4535_n200, DP_OP_110J3_122_4535_n199,
DP_OP_110J3_122_4535_n198, DP_OP_110J3_122_4535_n196,
DP_OP_110J3_122_4535_n195, DP_OP_110J3_122_4535_n194,
DP_OP_110J3_122_4535_n193, DP_OP_110J3_122_4535_n192,
DP_OP_110J3_122_4535_n191, DP_OP_110J3_122_4535_n190,
DP_OP_110J3_122_4535_n189, DP_OP_110J3_122_4535_n188,
DP_OP_110J3_122_4535_n187, DP_OP_110J3_122_4535_n186,
DP_OP_110J3_122_4535_n184, DP_OP_110J3_122_4535_n183,
DP_OP_110J3_122_4535_n182, DP_OP_110J3_122_4535_n181,
DP_OP_110J3_122_4535_n180, DP_OP_110J3_122_4535_n179,
DP_OP_110J3_122_4535_n178, DP_OP_110J3_122_4535_n176,
DP_OP_110J3_122_4535_n175, DP_OP_110J3_122_4535_n174,
DP_OP_110J3_122_4535_n173, DP_OP_110J3_122_4535_n172,
DP_OP_110J3_122_4535_n171, DP_OP_110J3_122_4535_n169,
DP_OP_110J3_122_4535_n168, DP_OP_110J3_122_4535_n167,
DP_OP_110J3_122_4535_n166, DP_OP_110J3_122_4535_n165,
DP_OP_110J3_122_4535_n164, DP_OP_110J3_122_4535_n163,
DP_OP_110J3_122_4535_n162, DP_OP_110J3_122_4535_n161,
DP_OP_110J3_122_4535_n160, DP_OP_110J3_122_4535_n159,
DP_OP_110J3_122_4535_n158, DP_OP_110J3_122_4535_n157,
DP_OP_110J3_122_4535_n156, DP_OP_110J3_122_4535_n155,
DP_OP_110J3_122_4535_n154, DP_OP_110J3_122_4535_n153,
DP_OP_110J3_122_4535_n152, DP_OP_110J3_122_4535_n151,
DP_OP_110J3_122_4535_n149, DP_OP_110J3_122_4535_n148,
DP_OP_110J3_122_4535_n147, DP_OP_110J3_122_4535_n146,
DP_OP_110J3_122_4535_n145, DP_OP_110J3_122_4535_n144,
DP_OP_110J3_122_4535_n143, DP_OP_110J3_122_4535_n142,
DP_OP_110J3_122_4535_n141, DP_OP_110J3_122_4535_n140,
DP_OP_110J3_122_4535_n138, DP_OP_110J3_122_4535_n137,
DP_OP_110J3_122_4535_n136, DP_OP_110J3_122_4535_n135,
DP_OP_110J3_122_4535_n134, DP_OP_110J3_122_4535_n133,
DP_OP_110J3_122_4535_n132, DP_OP_110J3_122_4535_n131,
DP_OP_110J3_122_4535_n130, DP_OP_110J3_122_4535_n129,
DP_OP_110J3_122_4535_n128, DP_OP_110J3_122_4535_n127,
DP_OP_110J3_122_4535_n126, DP_OP_110J3_122_4535_n125,
DP_OP_110J3_122_4535_n124, DP_OP_110J3_122_4535_n123,
DP_OP_110J3_122_4535_n122, DP_OP_110J3_122_4535_n121,
DP_OP_110J3_122_4535_n120, DP_OP_110J3_122_4535_n119,
DP_OP_110J3_122_4535_n118, DP_OP_110J3_122_4535_n117,
DP_OP_110J3_122_4535_n116, DP_OP_110J3_122_4535_n115,
DP_OP_110J3_122_4535_n114, DP_OP_110J3_122_4535_n113,
DP_OP_110J3_122_4535_n112, DP_OP_110J3_122_4535_n111,
DP_OP_110J3_122_4535_n110, DP_OP_110J3_122_4535_n109,
DP_OP_110J3_122_4535_n108, DP_OP_110J3_122_4535_n107,
DP_OP_110J3_122_4535_n106, DP_OP_110J3_122_4535_n105,
DP_OP_110J3_122_4535_n104, DP_OP_110J3_122_4535_n103,
DP_OP_110J3_122_4535_n102, DP_OP_110J3_122_4535_n101,
DP_OP_110J3_122_4535_n100, DP_OP_110J3_122_4535_n99,
DP_OP_110J3_122_4535_n98, DP_OP_110J3_122_4535_n97,
DP_OP_110J3_122_4535_n96, DP_OP_110J3_122_4535_n95,
DP_OP_110J3_122_4535_n94, DP_OP_110J3_122_4535_n93,
DP_OP_110J3_122_4535_n92, DP_OP_110J3_122_4535_n91,
DP_OP_110J3_122_4535_n90, DP_OP_110J3_122_4535_n89,
DP_OP_110J3_122_4535_n88, DP_OP_110J3_122_4535_n87,
DP_OP_110J3_122_4535_n86, DP_OP_110J3_122_4535_n85,
DP_OP_110J3_122_4535_n84, DP_OP_110J3_122_4535_n83,
DP_OP_110J3_122_4535_n82, DP_OP_110J3_122_4535_n81,
DP_OP_110J3_122_4535_n80, DP_OP_110J3_122_4535_n79,
DP_OP_110J3_122_4535_n78, DP_OP_110J3_122_4535_n77,
DP_OP_110J3_122_4535_n76, DP_OP_110J3_122_4535_n75,
DP_OP_110J3_122_4535_n74, DP_OP_110J3_122_4535_n73,
DP_OP_110J3_122_4535_n72, DP_OP_110J3_122_4535_n71,
DP_OP_110J3_122_4535_n70, DP_OP_110J3_122_4535_n69,
DP_OP_110J3_122_4535_n68, DP_OP_110J3_122_4535_n67,
DP_OP_110J3_122_4535_n66, DP_OP_110J3_122_4535_n65,
DP_OP_110J3_122_4535_n64, DP_OP_110J3_122_4535_n63,
DP_OP_110J3_122_4535_n62, DP_OP_110J3_122_4535_n61,
DP_OP_110J3_122_4535_n60, DP_OP_110J3_122_4535_n59,
DP_OP_110J3_122_4535_n58, DP_OP_110J3_122_4535_n57,
DP_OP_110J3_122_4535_n56, DP_OP_110J3_122_4535_n55,
DP_OP_110J3_122_4535_n54, DP_OP_110J3_122_4535_n53,
DP_OP_110J3_122_4535_n52, DP_OP_110J3_122_4535_n51,
DP_OP_110J3_122_4535_n50, DP_OP_110J3_122_4535_n49,
DP_OP_110J3_122_4535_n48, DP_OP_110J3_122_4535_n47,
DP_OP_110J3_122_4535_n46, DP_OP_110J3_122_4535_n45,
DP_OP_110J3_122_4535_n44, DP_OP_110J3_122_4535_n43,
DP_OP_110J3_122_4535_n42, DP_OP_110J3_122_4535_n41,
DP_OP_110J3_122_4535_n40, DP_OP_110J3_122_4535_n39,
DP_OP_110J3_122_4535_n38, DP_OP_110J3_122_4535_n37,
DP_OP_110J3_122_4535_n36, DP_OP_110J3_122_4535_n35,
DP_OP_110J3_122_4535_n34, DP_OP_110J3_122_4535_n33,
DP_OP_110J3_122_4535_n32, n391, n392, n393, n394, n395, n396, n397,
n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408,
n409, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420,
n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, n431,
n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442,
n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453,
n454, n455, n456, n457, n458, n459, n460, n461, n462, n463, n464,
n465, n466, n467, n468, n469, n470, n471, n472, n473, n474, n475,
n476, n477, n478, n479, n480, n481, n482, n483, n484, n485, n486,
n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, n497,
n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, n508,
n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519,
n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530,
n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541,
n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552,
n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563,
n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, n574,
n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585,
n586, n587, n588, n589, n590, n591, n592, n593, n594, n595, n596,
n597, n598, n599, n600, n601, n602, n603, n604, n605, n606, n607,
n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, n618,
n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629,
n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640,
n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662,
n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684,
n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695,
n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706,
n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717,
n718, n719, n720, n721, n722, n723, n724, n725, n726, n727, n728,
n729, n730, n731, n732, n733, n734, n735, n736, n737, n738, n739,
n740, n741, n742, n743, n744, n745, n746, n747, n748, n749, n750,
n751, n752, n753, n754, n755, n756, n757, n758, n759, n760, n761,
n762, n763, n764, n765, n766, n767, n768, n769, n770, n771, n772,
n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783,
n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794,
n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805,
n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816,
n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827,
n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838,
n839, n840, n841, n842, n843, n844, n845, n846, n847, n848, n849,
n850, n851, n852, n853, n854, n855, n856, n857, n858, n859, n860,
n861, n862, n863, n864, n865, n866, n867, n868, n869, n870, n871,
n872, n873, n874, n875, n876, n877, n878, n879, n880, n881, n882,
n883, n884, n885, n886, n887, n888, n889, n890, n891, n892, n893,
n894, n895, n896, n897, n898, n899, n900, n901, n902, n903, n904,
n905, n906, n907, n908, n909, n910, n911, n912, n913, n914, n915,
n916, n917, n918, n919, n920, n921, n922, n923, n924, n925, n926,
n927, n928, n929, n930, n931, n932, n933, n934, n935, n936, n937,
n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, n948,
n949, n950, n951, n953, n954, n955, n956, n957, n958, n959, n960,
n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, n971,
n972, n973, n974, n975, n976, n977, n978, n979, n980, n981, n982,
n983, n984, n985, n986, n987, n988, n989, n990, n991, n992, n993,
n994, n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1060, n1061, n1062, n1063, n1064, n1065,
n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075,
n1076, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1150, n1152, n1153, n1154, n1155, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1194, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599;
wire [47:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
wire [23:14] Sgf_operation_EVEN1_Q_left;
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n381), .CK(clk), .RN(
n1585), .Q(Op_MY[31]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n357), .CK(clk), .RN(
n1586), .Q(Op_MX[13]), .QN(n398) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n356), .CK(clk), .RN(
n1586), .Q(Op_MX[12]), .QN(n426) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n347), .CK(clk), .RN(
n1587), .Q(Op_MX[3]), .QN(n424) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n344), .CK(clk), .RN(
n1587), .Q(Op_MX[0]), .QN(n435) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n1587), .Q(Op_MX[31]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n309), .CK(clk), .RN(n1588),
.Q(Add_result[0]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n286), .CK(clk), .RN(n1588),
.Q(Add_result[23]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n330), .CK(clk), .RN(
n1589), .Q(Op_MY[18]), .QN(n441) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n329), .CK(clk), .RN(
n1589), .Q(Op_MY[17]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n328), .CK(clk), .RN(
n1590), .Q(Op_MY[16]), .QN(n425) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(clk), .RN(
n1590), .Q(Op_MY[15]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n326), .CK(clk), .RN(
n1590), .Q(Op_MY[14]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(clk), .RN(
n1590), .Q(Op_MY[13]), .QN(n427) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(clk), .RN(
n1591), .Q(Op_MY[1]), .QN(n397) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n269), .CK(clk), .RN(
n1596), .Q(P_Sgf[31]), .QN(n411) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n260), .CK(clk), .RN(
n1598), .Q(P_Sgf[22]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n248), .CK(clk), .RN(
n1597), .Q(P_Sgf[10]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n244), .CK(clk), .RN(
n1597), .Q(P_Sgf[6]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n240), .CK(clk), .RN(
n1598), .Q(P_Sgf[2]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n239), .CK(clk), .RN(
n1597), .Q(P_Sgf[1]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n238), .CK(clk), .RN(
n1597), .Q(P_Sgf[0]) );
DFFRXLTS Sel_B_Q_reg_0_ ( .D(n236), .CK(clk), .RN(n1591), .Q(
FSM_selector_B[0]), .QN(n1565) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n212), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[10]), .QN(n1562) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n210), .CK(clk),
.RN(n1593), .Q(Sgf_normalized_result[8]), .QN(n1561) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n206), .CK(clk),
.RN(n1593), .Q(Sgf_normalized_result[4]), .QN(n1559) );
CMPR32X2TS DP_OP_36J3_123_9196_U10 ( .A(S_Oper_A_exp[0]), .B(
FSM_exp_operation_A_S), .C(DP_OP_36J3_123_9196_n22), .CO(
DP_OP_36J3_123_9196_n9), .S(Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_36J3_123_9196_U9 ( .A(DP_OP_36J3_123_9196_n21), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J3_123_9196_n9), .CO(
DP_OP_36J3_123_9196_n8), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J3_123_9196_U8 ( .A(DP_OP_36J3_123_9196_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J3_123_9196_n8), .CO(
DP_OP_36J3_123_9196_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J3_123_9196_U7 ( .A(DP_OP_36J3_123_9196_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J3_123_9196_n7), .CO(
DP_OP_36J3_123_9196_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J3_123_9196_U6 ( .A(DP_OP_36J3_123_9196_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J3_123_9196_n6), .CO(
DP_OP_36J3_123_9196_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J3_123_9196_U5 ( .A(DP_OP_36J3_123_9196_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J3_123_9196_n5), .CO(
DP_OP_36J3_123_9196_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J3_123_9196_U4 ( .A(DP_OP_36J3_123_9196_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J3_123_9196_n4), .CO(
DP_OP_36J3_123_9196_n3), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J3_123_9196_U3 ( .A(DP_OP_36J3_123_9196_n15), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J3_123_9196_n3), .CO(
DP_OP_36J3_123_9196_n2), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_36J3_123_9196_U2 ( .A(FSM_exp_operation_A_S), .B(
S_Oper_A_exp[8]), .C(DP_OP_36J3_123_9196_n2), .CO(
DP_OP_36J3_123_9196_n1), .S(Exp_module_Data_S[8]) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n201), .CK(clk), .RN(n1593),
.Q(underflow_flag), .QN(n1584) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n168),
.CK(clk), .RN(n1595), .Q(final_result_ieee[31]), .QN(n1583) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n267), .CK(clk), .RN(
n1596), .Q(P_Sgf[29]), .QN(n1581) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n268), .CK(clk), .RN(
n1596), .Q(P_Sgf[30]), .QN(n1580) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n262), .CK(clk), .RN(
n1596), .Q(P_Sgf[24]), .QN(n1579) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n263), .CK(clk), .RN(
n1596), .Q(P_Sgf[25]), .QN(n1578) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n264), .CK(clk), .RN(
n1596), .Q(P_Sgf[26]), .QN(n1577) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n265), .CK(clk), .RN(
n1596), .Q(P_Sgf[27]), .QN(n1576) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n266), .CK(clk), .RN(
n1596), .Q(P_Sgf[28]), .QN(n1575) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n376), .CK(clk), .RN(n1585), .Q(FSM_selector_A),
.QN(n1572) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n235), .CK(clk), .RN(n1591), .Q(
FSM_selector_B[1]), .QN(n1566) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n379), .CK(clk), .RN(n167), .Q(
FS_Module_state_reg[0]), .QN(n1558) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n377), .CK(clk), .RN(n167), .Q(
FS_Module_state_reg[2]), .QN(n1557) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n200),
.CK(clk), .RN(n1593), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n199),
.CK(clk), .RN(n1593), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n198),
.CK(clk), .RN(n1593), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n197),
.CK(clk), .RN(n1593), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n196),
.CK(clk), .RN(n1593), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n195),
.CK(clk), .RN(n1594), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n194),
.CK(clk), .RN(n1594), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n193),
.CK(clk), .RN(n1594), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n192),
.CK(clk), .RN(n1594), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n191),
.CK(clk), .RN(n1594), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n190),
.CK(clk), .RN(n1594), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n189),
.CK(clk), .RN(n1594), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n188),
.CK(clk), .RN(n1594), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n187),
.CK(clk), .RN(n1594), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n186),
.CK(clk), .RN(n1594), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n185),
.CK(clk), .RN(n1594), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n184),
.CK(clk), .RN(n1594), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n183),
.CK(clk), .RN(n1594), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n182),
.CK(clk), .RN(n1594), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n181),
.CK(clk), .RN(n1594), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n180),
.CK(clk), .RN(n1595), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n179),
.CK(clk), .RN(n1595), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n178),
.CK(clk), .RN(n1595), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n177),
.CK(clk), .RN(n1595), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n176),
.CK(clk), .RN(n1595), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n175),
.CK(clk), .RN(n1595), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n174),
.CK(clk), .RN(n1595), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n173),
.CK(clk), .RN(n1595), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n172),
.CK(clk), .RN(n1595), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n171),
.CK(clk), .RN(n1595), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n170),
.CK(clk), .RN(n1595), .Q(final_result_ieee[30]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n225), .CK(clk), .RN(n1591), .Q(
Exp_module_Overflow_flag_A) );
CMPR42X1TS DP_OP_110J3_122_4535_U800 ( .A(DP_OP_110J3_122_4535_n1106), .B(
DP_OP_110J3_122_4535_n1142), .C(DP_OP_110J3_122_4535_n1130), .D(
DP_OP_110J3_122_4535_n1118), .ICI(DP_OP_110J3_122_4535_n1047), .S(
DP_OP_110J3_122_4535_n1044), .ICO(DP_OP_110J3_122_4535_n1042), .CO(
DP_OP_110J3_122_4535_n1043) );
CMPR42X1TS DP_OP_110J3_122_4535_U798 ( .A(DP_OP_110J3_122_4535_n1129), .B(
DP_OP_110J3_122_4535_n1105), .C(DP_OP_110J3_122_4535_n1117), .D(
DP_OP_110J3_122_4535_n1042), .ICI(DP_OP_110J3_122_4535_n1041), .S(
DP_OP_110J3_122_4535_n1039), .ICO(DP_OP_110J3_122_4535_n1037), .CO(
DP_OP_110J3_122_4535_n1038) );
CMPR42X1TS DP_OP_110J3_122_4535_U796 ( .A(DP_OP_110J3_122_4535_n1116), .B(
DP_OP_110J3_122_4535_n1104), .C(DP_OP_110J3_122_4535_n1040), .D(
DP_OP_110J3_122_4535_n1037), .ICI(DP_OP_110J3_122_4535_n1036), .S(
DP_OP_110J3_122_4535_n1034), .ICO(DP_OP_110J3_122_4535_n1032), .CO(
DP_OP_110J3_122_4535_n1033) );
CMPR42X1TS DP_OP_110J3_122_4535_U793 ( .A(DP_OP_110J3_122_4535_n1115), .B(
DP_OP_110J3_122_4535_n1035), .C(DP_OP_110J3_122_4535_n1031), .D(
DP_OP_110J3_122_4535_n1029), .ICI(DP_OP_110J3_122_4535_n1032), .S(
DP_OP_110J3_122_4535_n1027), .ICO(DP_OP_110J3_122_4535_n1025), .CO(
DP_OP_110J3_122_4535_n1026) );
CMPR42X1TS DP_OP_110J3_122_4535_U792 ( .A(DP_OP_110J3_122_4535_n1078), .B(
DP_OP_110J3_122_4535_n1138), .C(DP_OP_110J3_122_4535_n1126), .D(
DP_OP_110J3_122_4535_n1114), .ICI(DP_OP_110J3_122_4535_n1090), .S(
DP_OP_110J3_122_4535_n1024), .ICO(DP_OP_110J3_122_4535_n1022), .CO(
DP_OP_110J3_122_4535_n1023) );
CMPR42X1TS DP_OP_110J3_122_4535_U791 ( .A(DP_OP_110J3_122_4535_n1102), .B(
DP_OP_110J3_122_4535_n1030), .C(DP_OP_110J3_122_4535_n1028), .D(
DP_OP_110J3_122_4535_n1025), .ICI(DP_OP_110J3_122_4535_n1024), .S(
DP_OP_110J3_122_4535_n1021), .ICO(DP_OP_110J3_122_4535_n1019), .CO(
DP_OP_110J3_122_4535_n1020) );
CMPR42X1TS DP_OP_110J3_122_4535_U789 ( .A(DP_OP_110J3_122_4535_n1125), .B(
DP_OP_110J3_122_4535_n1077), .C(DP_OP_110J3_122_4535_n1113), .D(
DP_OP_110J3_122_4535_n1089), .ICI(DP_OP_110J3_122_4535_n1018), .S(
DP_OP_110J3_122_4535_n1016), .ICO(DP_OP_110J3_122_4535_n1014), .CO(
DP_OP_110J3_122_4535_n1015) );
CMPR42X1TS DP_OP_110J3_122_4535_U788 ( .A(DP_OP_110J3_122_4535_n1101), .B(
DP_OP_110J3_122_4535_n1022), .C(DP_OP_110J3_122_4535_n1023), .D(
DP_OP_110J3_122_4535_n1019), .ICI(DP_OP_110J3_122_4535_n1016), .S(
DP_OP_110J3_122_4535_n1013), .ICO(DP_OP_110J3_122_4535_n1011), .CO(
DP_OP_110J3_122_4535_n1012) );
CMPR42X1TS DP_OP_110J3_122_4535_U786 ( .A(DP_OP_110J3_122_4535_n1112), .B(
DP_OP_110J3_122_4535_n1076), .C(DP_OP_110J3_122_4535_n1100), .D(
DP_OP_110J3_122_4535_n1088), .ICI(DP_OP_110J3_122_4535_n1010), .S(
DP_OP_110J3_122_4535_n1008), .ICO(DP_OP_110J3_122_4535_n1006), .CO(
DP_OP_110J3_122_4535_n1007) );
CMPR42X1TS DP_OP_110J3_122_4535_U785 ( .A(DP_OP_110J3_122_4535_n1017), .B(
DP_OP_110J3_122_4535_n1014), .C(DP_OP_110J3_122_4535_n1015), .D(
DP_OP_110J3_122_4535_n1008), .ICI(DP_OP_110J3_122_4535_n1011), .S(
DP_OP_110J3_122_4535_n1005), .ICO(DP_OP_110J3_122_4535_n1003), .CO(
DP_OP_110J3_122_4535_n1004) );
CMPR42X1TS DP_OP_110J3_122_4535_U782 ( .A(DP_OP_110J3_122_4535_n1099), .B(
DP_OP_110J3_122_4535_n1075), .C(DP_OP_110J3_122_4535_n1123), .D(n398),
.ICI(DP_OP_110J3_122_4535_n1001), .S(DP_OP_110J3_122_4535_n999), .ICO(
DP_OP_110J3_122_4535_n997), .CO(DP_OP_110J3_122_4535_n998) );
CMPR42X1TS DP_OP_110J3_122_4535_U781 ( .A(DP_OP_110J3_122_4535_n1006), .B(
DP_OP_110J3_122_4535_n1009), .C(DP_OP_110J3_122_4535_n1007), .D(
DP_OP_110J3_122_4535_n999), .ICI(DP_OP_110J3_122_4535_n1003), .S(
DP_OP_110J3_122_4535_n996), .ICO(DP_OP_110J3_122_4535_n994), .CO(
DP_OP_110J3_122_4535_n995) );
CMPR42X1TS DP_OP_110J3_122_4535_U778 ( .A(DP_OP_110J3_122_4535_n1086), .B(
DP_OP_110J3_122_4535_n1122), .C(DP_OP_110J3_122_4535_n1110), .D(
DP_OP_110J3_122_4535_n1074), .ICI(DP_OP_110J3_122_4535_n1000), .S(
DP_OP_110J3_122_4535_n989), .ICO(DP_OP_110J3_122_4535_n987), .CO(
DP_OP_110J3_122_4535_n988) );
CMPR42X1TS DP_OP_110J3_122_4535_U777 ( .A(DP_OP_110J3_122_4535_n997), .B(
DP_OP_110J3_122_4535_n991), .C(DP_OP_110J3_122_4535_n998), .D(
DP_OP_110J3_122_4535_n989), .ICI(DP_OP_110J3_122_4535_n994), .S(
DP_OP_110J3_122_4535_n986), .ICO(DP_OP_110J3_122_4535_n984), .CO(
DP_OP_110J3_122_4535_n985) );
CMPR42X1TS DP_OP_110J3_122_4535_U775 ( .A(DP_OP_110J3_122_4535_n1085), .B(
DP_OP_110J3_122_4535_n1073), .C(DP_OP_110J3_122_4535_n1109), .D(
DP_OP_110J3_122_4535_n1121), .ICI(DP_OP_110J3_122_4535_n983), .S(
DP_OP_110J3_122_4535_n981), .ICO(DP_OP_110J3_122_4535_n979), .CO(
DP_OP_110J3_122_4535_n980) );
CMPR42X1TS DP_OP_110J3_122_4535_U774 ( .A(DP_OP_110J3_122_4535_n987), .B(
DP_OP_110J3_122_4535_n990), .C(DP_OP_110J3_122_4535_n988), .D(
DP_OP_110J3_122_4535_n981), .ICI(DP_OP_110J3_122_4535_n984), .S(
DP_OP_110J3_122_4535_n978), .ICO(DP_OP_110J3_122_4535_n976), .CO(
DP_OP_110J3_122_4535_n977) );
CMPR42X1TS DP_OP_110J3_122_4535_U772 ( .A(n425), .B(
DP_OP_110J3_122_4535_n1084), .C(DP_OP_110J3_122_4535_n1096), .D(
DP_OP_110J3_122_4535_n1072), .ICI(DP_OP_110J3_122_4535_n1108), .S(
DP_OP_110J3_122_4535_n973), .ICO(DP_OP_110J3_122_4535_n971), .CO(
DP_OP_110J3_122_4535_n972) );
CMPR42X1TS DP_OP_110J3_122_4535_U771 ( .A(DP_OP_110J3_122_4535_n979), .B(
DP_OP_110J3_122_4535_n982), .C(DP_OP_110J3_122_4535_n980), .D(
DP_OP_110J3_122_4535_n973), .ICI(DP_OP_110J3_122_4535_n976), .S(
DP_OP_110J3_122_4535_n970), .ICO(DP_OP_110J3_122_4535_n968), .CO(
DP_OP_110J3_122_4535_n969) );
CMPR42X1TS DP_OP_110J3_122_4535_U770 ( .A(Op_MY[16]), .B(Op_MY[17]), .C(
DP_OP_110J3_122_4535_n1095), .D(DP_OP_110J3_122_4535_n1083), .ICI(
DP_OP_110J3_122_4535_n1071), .S(DP_OP_110J3_122_4535_n967), .ICO(
DP_OP_110J3_122_4535_n965), .CO(DP_OP_110J3_122_4535_n966) );
CMPR42X1TS DP_OP_110J3_122_4535_U769 ( .A(DP_OP_110J3_122_4535_n1107), .B(
DP_OP_110J3_122_4535_n971), .C(DP_OP_110J3_122_4535_n972), .D(
DP_OP_110J3_122_4535_n967), .ICI(DP_OP_110J3_122_4535_n968), .S(
DP_OP_110J3_122_4535_n964), .ICO(DP_OP_110J3_122_4535_n962), .CO(
DP_OP_110J3_122_4535_n963) );
CMPR42X1TS DP_OP_110J3_122_4535_U766 ( .A(DP_OP_110J3_122_4535_n1070), .B(
DP_OP_110J3_122_4535_n965), .C(DP_OP_110J3_122_4535_n959), .D(
DP_OP_110J3_122_4535_n966), .ICI(DP_OP_110J3_122_4535_n962), .S(
DP_OP_110J3_122_4535_n957), .ICO(DP_OP_110J3_122_4535_n955), .CO(
DP_OP_110J3_122_4535_n956) );
CMPR42X1TS DP_OP_110J3_122_4535_U764 ( .A(DP_OP_110J3_122_4535_n1069), .B(
DP_OP_110J3_122_4535_n1093), .C(DP_OP_110J3_122_4535_n954), .D(
DP_OP_110J3_122_4535_n958), .ICI(DP_OP_110J3_122_4535_n955), .S(
DP_OP_110J3_122_4535_n952), .ICO(DP_OP_110J3_122_4535_n950), .CO(
DP_OP_110J3_122_4535_n951) );
CMPR42X1TS DP_OP_110J3_122_4535_U762 ( .A(n421), .B(
DP_OP_110J3_122_4535_n1080), .C(DP_OP_110J3_122_4535_n1068), .D(
DP_OP_110J3_122_4535_n953), .ICI(DP_OP_110J3_122_4535_n950), .S(
DP_OP_110J3_122_4535_n947), .ICO(DP_OP_110J3_122_4535_n945), .CO(
DP_OP_110J3_122_4535_n946) );
CMPR42X1TS DP_OP_110J3_122_4535_U761 ( .A(DP_OP_110J3_122_4535_n948), .B(
Op_MY[21]), .C(DP_OP_110J3_122_4535_n1067), .D(
DP_OP_110J3_122_4535_n1079), .ICI(DP_OP_110J3_122_4535_n945), .S(
DP_OP_110J3_122_4535_n944), .ICO(DP_OP_110J3_122_4535_n942), .CO(
DP_OP_110J3_122_4535_n943) );
CMPR42X1TS DP_OP_110J3_122_4535_U481 ( .A(DP_OP_110J3_122_4535_n725), .B(
DP_OP_110J3_122_4535_n761), .C(DP_OP_110J3_122_4535_n749), .D(
DP_OP_110J3_122_4535_n737), .ICI(DP_OP_110J3_122_4535_n665), .S(
DP_OP_110J3_122_4535_n662), .ICO(DP_OP_110J3_122_4535_n660), .CO(
DP_OP_110J3_122_4535_n661) );
CMPR42X1TS DP_OP_110J3_122_4535_U479 ( .A(DP_OP_110J3_122_4535_n748), .B(
DP_OP_110J3_122_4535_n724), .C(DP_OP_110J3_122_4535_n736), .D(
DP_OP_110J3_122_4535_n660), .ICI(DP_OP_110J3_122_4535_n659), .S(
DP_OP_110J3_122_4535_n657), .ICO(DP_OP_110J3_122_4535_n655), .CO(
DP_OP_110J3_122_4535_n656) );
CMPR42X1TS DP_OP_110J3_122_4535_U477 ( .A(DP_OP_110J3_122_4535_n735), .B(
DP_OP_110J3_122_4535_n723), .C(DP_OP_110J3_122_4535_n658), .D(
DP_OP_110J3_122_4535_n655), .ICI(DP_OP_110J3_122_4535_n654), .S(
DP_OP_110J3_122_4535_n652), .ICO(DP_OP_110J3_122_4535_n650), .CO(
DP_OP_110J3_122_4535_n651) );
CMPR42X1TS DP_OP_110J3_122_4535_U473 ( .A(DP_OP_110J3_122_4535_n697), .B(
DP_OP_110J3_122_4535_n757), .C(DP_OP_110J3_122_4535_n745), .D(
DP_OP_110J3_122_4535_n733), .ICI(DP_OP_110J3_122_4535_n709), .S(
DP_OP_110J3_122_4535_n642), .ICO(DP_OP_110J3_122_4535_n640), .CO(
DP_OP_110J3_122_4535_n641) );
CMPR42X1TS DP_OP_110J3_122_4535_U472 ( .A(DP_OP_110J3_122_4535_n721), .B(
DP_OP_110J3_122_4535_n648), .C(DP_OP_110J3_122_4535_n646), .D(
DP_OP_110J3_122_4535_n643), .ICI(DP_OP_110J3_122_4535_n642), .S(
DP_OP_110J3_122_4535_n639), .ICO(DP_OP_110J3_122_4535_n637), .CO(
DP_OP_110J3_122_4535_n638) );
CMPR42X1TS DP_OP_110J3_122_4535_U470 ( .A(DP_OP_110J3_122_4535_n744), .B(
DP_OP_110J3_122_4535_n696), .C(DP_OP_110J3_122_4535_n732), .D(
DP_OP_110J3_122_4535_n708), .ICI(DP_OP_110J3_122_4535_n636), .S(
DP_OP_110J3_122_4535_n634), .ICO(DP_OP_110J3_122_4535_n632), .CO(
DP_OP_110J3_122_4535_n633) );
CMPR42X1TS DP_OP_110J3_122_4535_U469 ( .A(DP_OP_110J3_122_4535_n720), .B(
DP_OP_110J3_122_4535_n640), .C(DP_OP_110J3_122_4535_n641), .D(
DP_OP_110J3_122_4535_n637), .ICI(DP_OP_110J3_122_4535_n634), .S(
DP_OP_110J3_122_4535_n631), .ICO(DP_OP_110J3_122_4535_n629), .CO(
DP_OP_110J3_122_4535_n630) );
CMPR42X1TS DP_OP_110J3_122_4535_U467 ( .A(DP_OP_110J3_122_4535_n731), .B(
DP_OP_110J3_122_4535_n695), .C(DP_OP_110J3_122_4535_n719), .D(
DP_OP_110J3_122_4535_n707), .ICI(DP_OP_110J3_122_4535_n628), .S(
DP_OP_110J3_122_4535_n626), .ICO(DP_OP_110J3_122_4535_n624), .CO(
DP_OP_110J3_122_4535_n625) );
CMPR42X1TS DP_OP_110J3_122_4535_U466 ( .A(DP_OP_110J3_122_4535_n635), .B(
DP_OP_110J3_122_4535_n632), .C(DP_OP_110J3_122_4535_n633), .D(
DP_OP_110J3_122_4535_n626), .ICI(DP_OP_110J3_122_4535_n629), .S(
DP_OP_110J3_122_4535_n623), .ICO(DP_OP_110J3_122_4535_n621), .CO(
DP_OP_110J3_122_4535_n622) );
CMPR42X1TS DP_OP_110J3_122_4535_U463 ( .A(DP_OP_110J3_122_4535_n718), .B(
DP_OP_110J3_122_4535_n694), .C(DP_OP_110J3_122_4535_n742), .D(n396),
.ICI(DP_OP_110J3_122_4535_n619), .S(DP_OP_110J3_122_4535_n617), .ICO(
DP_OP_110J3_122_4535_n615), .CO(DP_OP_110J3_122_4535_n616) );
CMPR42X1TS DP_OP_110J3_122_4535_U462 ( .A(DP_OP_110J3_122_4535_n624), .B(
DP_OP_110J3_122_4535_n627), .C(DP_OP_110J3_122_4535_n625), .D(
DP_OP_110J3_122_4535_n617), .ICI(DP_OP_110J3_122_4535_n621), .S(
DP_OP_110J3_122_4535_n614), .ICO(DP_OP_110J3_122_4535_n612), .CO(
DP_OP_110J3_122_4535_n613) );
CMPR42X1TS DP_OP_110J3_122_4535_U459 ( .A(DP_OP_110J3_122_4535_n705), .B(
DP_OP_110J3_122_4535_n741), .C(DP_OP_110J3_122_4535_n729), .D(
DP_OP_110J3_122_4535_n693), .ICI(DP_OP_110J3_122_4535_n618), .S(
DP_OP_110J3_122_4535_n607), .ICO(DP_OP_110J3_122_4535_n605), .CO(
DP_OP_110J3_122_4535_n606) );
CMPR42X1TS DP_OP_110J3_122_4535_U458 ( .A(DP_OP_110J3_122_4535_n615), .B(
DP_OP_110J3_122_4535_n609), .C(DP_OP_110J3_122_4535_n616), .D(
DP_OP_110J3_122_4535_n607), .ICI(DP_OP_110J3_122_4535_n612), .S(
DP_OP_110J3_122_4535_n604), .ICO(DP_OP_110J3_122_4535_n602), .CO(
DP_OP_110J3_122_4535_n603) );
CMPR42X1TS DP_OP_110J3_122_4535_U456 ( .A(DP_OP_110J3_122_4535_n704), .B(
DP_OP_110J3_122_4535_n692), .C(DP_OP_110J3_122_4535_n728), .D(
DP_OP_110J3_122_4535_n740), .ICI(DP_OP_110J3_122_4535_n601), .S(
DP_OP_110J3_122_4535_n599), .ICO(DP_OP_110J3_122_4535_n597), .CO(
DP_OP_110J3_122_4535_n598) );
CMPR42X1TS DP_OP_110J3_122_4535_U455 ( .A(DP_OP_110J3_122_4535_n605), .B(
DP_OP_110J3_122_4535_n608), .C(DP_OP_110J3_122_4535_n606), .D(
DP_OP_110J3_122_4535_n599), .ICI(DP_OP_110J3_122_4535_n602), .S(
DP_OP_110J3_122_4535_n596), .ICO(DP_OP_110J3_122_4535_n594), .CO(
DP_OP_110J3_122_4535_n595) );
CMPR42X1TS DP_OP_110J3_122_4535_U453 ( .A(DP_OP_110J3_122_4535_n593), .B(
DP_OP_110J3_122_4535_n703), .C(DP_OP_110J3_122_4535_n715), .D(
DP_OP_110J3_122_4535_n691), .ICI(DP_OP_110J3_122_4535_n727), .S(
DP_OP_110J3_122_4535_n591), .ICO(DP_OP_110J3_122_4535_n589), .CO(
DP_OP_110J3_122_4535_n590) );
CMPR42X1TS DP_OP_110J3_122_4535_U452 ( .A(DP_OP_110J3_122_4535_n597), .B(
DP_OP_110J3_122_4535_n600), .C(DP_OP_110J3_122_4535_n598), .D(
DP_OP_110J3_122_4535_n591), .ICI(DP_OP_110J3_122_4535_n594), .S(
DP_OP_110J3_122_4535_n588), .ICO(DP_OP_110J3_122_4535_n586), .CO(
DP_OP_110J3_122_4535_n587) );
CMPR42X1TS DP_OP_110J3_122_4535_U451 ( .A(DP_OP_110J3_122_4535_n592), .B(
DP_OP_110J3_122_4535_n680), .C(DP_OP_110J3_122_4535_n714), .D(
DP_OP_110J3_122_4535_n702), .ICI(DP_OP_110J3_122_4535_n690), .S(
DP_OP_110J3_122_4535_n585), .ICO(DP_OP_110J3_122_4535_n583), .CO(
DP_OP_110J3_122_4535_n584) );
CMPR42X1TS DP_OP_110J3_122_4535_U450 ( .A(DP_OP_110J3_122_4535_n726), .B(
DP_OP_110J3_122_4535_n589), .C(DP_OP_110J3_122_4535_n590), .D(
DP_OP_110J3_122_4535_n585), .ICI(DP_OP_110J3_122_4535_n586), .S(
DP_OP_110J3_122_4535_n582), .ICO(DP_OP_110J3_122_4535_n580), .CO(
DP_OP_110J3_122_4535_n581) );
CMPR42X1TS DP_OP_110J3_122_4535_U447 ( .A(DP_OP_110J3_122_4535_n689), .B(
DP_OP_110J3_122_4535_n583), .C(DP_OP_110J3_122_4535_n577), .D(
DP_OP_110J3_122_4535_n584), .ICI(DP_OP_110J3_122_4535_n580), .S(
DP_OP_110J3_122_4535_n575), .ICO(DP_OP_110J3_122_4535_n573), .CO(
DP_OP_110J3_122_4535_n574) );
CMPR42X1TS DP_OP_110J3_122_4535_U445 ( .A(DP_OP_110J3_122_4535_n688), .B(
DP_OP_110J3_122_4535_n712), .C(DP_OP_110J3_122_4535_n572), .D(
DP_OP_110J3_122_4535_n576), .ICI(DP_OP_110J3_122_4535_n573), .S(
DP_OP_110J3_122_4535_n570), .ICO(DP_OP_110J3_122_4535_n568), .CO(
DP_OP_110J3_122_4535_n569) );
CMPR42X1TS DP_OP_110J3_122_4535_U443 ( .A(DP_OP_110J3_122_4535_n567), .B(
DP_OP_110J3_122_4535_n699), .C(DP_OP_110J3_122_4535_n687), .D(
DP_OP_110J3_122_4535_n571), .ICI(DP_OP_110J3_122_4535_n568), .S(
DP_OP_110J3_122_4535_n565), .ICO(DP_OP_110J3_122_4535_n563), .CO(
DP_OP_110J3_122_4535_n564) );
CMPR42X1TS DP_OP_110J3_122_4535_U442 ( .A(DP_OP_110J3_122_4535_n566), .B(
DP_OP_110J3_122_4535_n678), .C(DP_OP_110J3_122_4535_n686), .D(
DP_OP_110J3_122_4535_n698), .ICI(DP_OP_110J3_122_4535_n563), .S(
DP_OP_110J3_122_4535_n562), .ICO(DP_OP_110J3_122_4535_n560), .CO(
DP_OP_110J3_122_4535_n561) );
CMPR42X1TS DP_OP_110J3_122_4535_U98 ( .A(DP_OP_110J3_122_4535_n528), .B(
DP_OP_110J3_122_4535_n346), .C(DP_OP_110J3_122_4535_n236), .D(
DP_OP_110J3_122_4535_n527), .ICI(DP_OP_110J3_122_4535_n333), .S(
DP_OP_110J3_122_4535_n212), .ICO(DP_OP_110J3_122_4535_n210), .CO(
DP_OP_110J3_122_4535_n211) );
CMPR42X1TS DP_OP_110J3_122_4535_U96 ( .A(DP_OP_110J3_122_4535_n235), .B(
DP_OP_110J3_122_4535_n526), .C(DP_OP_110J3_122_4535_n332), .D(
DP_OP_110J3_122_4535_n243), .ICI(DP_OP_110J3_122_4535_n211), .S(
DP_OP_110J3_122_4535_n207), .ICO(DP_OP_110J3_122_4535_n205), .CO(
DP_OP_110J3_122_4535_n206) );
CMPR42X1TS DP_OP_110J3_122_4535_U94 ( .A(DP_OP_110J3_122_4535_n344), .B(
DP_OP_110J3_122_4535_n234), .C(DP_OP_110J3_122_4535_n525), .D(
DP_OP_110J3_122_4535_n205), .ICI(DP_OP_110J3_122_4535_n204), .S(
DP_OP_110J3_122_4535_n202), .ICO(DP_OP_110J3_122_4535_n200), .CO(
DP_OP_110J3_122_4535_n201) );
CMPR42X1TS DP_OP_110J3_122_4535_U90 ( .A(DP_OP_110J3_122_4535_n329), .B(
DP_OP_110J3_122_4535_n316), .C(DP_OP_110J3_122_4535_n198), .D(
DP_OP_110J3_122_4535_n342), .ICI(DP_OP_110J3_122_4535_n232), .S(
DP_OP_110J3_122_4535_n192), .ICO(DP_OP_110J3_122_4535_n190), .CO(
DP_OP_110J3_122_4535_n191) );
CMPR42X1TS DP_OP_110J3_122_4535_U86 ( .A(DP_OP_110J3_122_4535_n231), .B(
DP_OP_110J3_122_4535_n186), .C(DP_OP_110J3_122_4535_n302), .D(
DP_OP_110J3_122_4535_n241), .ICI(DP_OP_110J3_122_4535_n188), .S(
DP_OP_110J3_122_4535_n181), .ICO(DP_OP_110J3_122_4535_n179), .CO(
DP_OP_110J3_122_4535_n180) );
CMPR42X1TS DP_OP_110J3_122_4535_U83 ( .A(DP_OP_110J3_122_4535_n340), .B(
DP_OP_110J3_122_4535_n182), .C(DP_OP_110J3_122_4535_n521), .D(
DP_OP_110J3_122_4535_n179), .ICI(DP_OP_110J3_122_4535_n180), .S(
DP_OP_110J3_122_4535_n173), .ICO(DP_OP_110J3_122_4535_n171), .CO(
DP_OP_110J3_122_4535_n172) );
CMPR42X1TS DP_OP_110J3_122_4535_U78 ( .A(DP_OP_110J3_122_4535_n312), .B(
DP_OP_110J3_122_4535_n299), .C(DP_OP_110J3_122_4535_n169), .D(
DP_OP_110J3_122_4535_n325), .ICI(DP_OP_110J3_122_4535_n167), .S(
DP_OP_110J3_122_4535_n160), .ICO(DP_OP_110J3_122_4535_n158), .CO(
DP_OP_110J3_122_4535_n159) );
CMPR42X1TS DP_OP_110J3_122_4535_U77 ( .A(DP_OP_110J3_122_4535_n286), .B(
DP_OP_110J3_122_4535_n338), .C(DP_OP_110J3_122_4535_n228), .D(
DP_OP_110J3_122_4535_n273), .ICI(DP_OP_110J3_122_4535_n161), .S(
DP_OP_110J3_122_4535_n157), .ICO(DP_OP_110J3_122_4535_n155), .CO(
DP_OP_110J3_122_4535_n156) );
CMPR42X1TS DP_OP_110J3_122_4535_U74 ( .A(DP_OP_110J3_122_4535_n158), .B(
DP_OP_110J3_122_4535_n324), .C(DP_OP_110J3_122_4535_n151), .D(
DP_OP_110J3_122_4535_n285), .ICI(DP_OP_110J3_122_4535_n159), .S(
DP_OP_110J3_122_4535_n149), .ICO(DP_OP_110J3_122_4535_n147), .CO(
DP_OP_110J3_122_4535_n148) );
CMPR42X1TS DP_OP_110J3_122_4535_U72 ( .A(DP_OP_110J3_122_4535_n337), .B(
DP_OP_110J3_122_4535_n149), .C(DP_OP_110J3_122_4535_n272), .D(
DP_OP_110J3_122_4535_n239), .ICI(DP_OP_110J3_122_4535_n153), .S(
DP_OP_110J3_122_4535_n143), .ICO(DP_OP_110J3_122_4535_n141), .CO(
DP_OP_110J3_122_4535_n142) );
CMPR42X1TS DP_OP_110J3_122_4535_U70 ( .A(DP_OP_110J3_122_4535_n284), .B(
DP_OP_110J3_122_4535_n140), .C(DP_OP_110J3_122_4535_n323), .D(
DP_OP_110J3_122_4535_n147), .ICI(DP_OP_110J3_122_4535_n148), .S(
DP_OP_110J3_122_4535_n138), .ICO(DP_OP_110J3_122_4535_n136), .CO(
DP_OP_110J3_122_4535_n137) );
CMPR42X1TS DP_OP_110J3_122_4535_U69 ( .A(DP_OP_110J3_122_4535_n336), .B(
DP_OP_110J3_122_4535_n258), .C(DP_OP_110J3_122_4535_n226), .D(
DP_OP_110J3_122_4535_n517), .ICI(DP_OP_110J3_122_4535_n138), .S(
DP_OP_110J3_122_4535_n135), .ICO(DP_OP_110J3_122_4535_n133), .CO(
DP_OP_110J3_122_4535_n134) );
CMPR42X1TS DP_OP_110J3_122_4535_U62 ( .A(DP_OP_110J3_122_4535_n308), .B(
DP_OP_110J3_122_4535_n128), .C(DP_OP_110J3_122_4535_n118), .D(
DP_OP_110J3_122_4535_n125), .ICI(DP_OP_110J3_122_4535_n321), .S(
DP_OP_110J3_122_4535_n116), .ICO(DP_OP_110J3_122_4535_n114), .CO(
DP_OP_110J3_122_4535_n115) );
CMPR42X1TS DP_OP_110J3_122_4535_U54 ( .A(DP_OP_110J3_122_4535_n96), .B(
DP_OP_110J3_122_4535_n106), .C(DP_OP_110J3_122_4535_n306), .D(
DP_OP_110J3_122_4535_n254), .ICI(DP_OP_110J3_122_4535_n267), .S(
DP_OP_110J3_122_4535_n94), .ICO(DP_OP_110J3_122_4535_n92), .CO(
DP_OP_110J3_122_4535_n93) );
CMPR42X1TS DP_OP_110J3_122_4535_U52 ( .A(DP_OP_110J3_122_4535_n101), .B(
DP_OP_110J3_122_4535_n222), .C(DP_OP_110J3_122_4535_n513), .D(
DP_OP_110J3_122_4535_n97), .ICI(DP_OP_110J3_122_4535_n91), .S(
DP_OP_110J3_122_4535_n88), .ICO(DP_OP_110J3_122_4535_n86), .CO(
DP_OP_110J3_122_4535_n87) );
CMPR42X1TS DP_OP_110J3_122_4535_U51 ( .A(DP_OP_110J3_122_4535_n279), .B(
DP_OP_110J3_122_4535_n305), .C(DP_OP_110J3_122_4535_n95), .D(
DP_OP_110J3_122_4535_n292), .ICI(DP_OP_110J3_122_4535_n253), .S(
DP_OP_110J3_122_4535_n85), .ICO(DP_OP_110J3_122_4535_n83), .CO(
DP_OP_110J3_122_4535_n84) );
CMPR42X1TS DP_OP_110J3_122_4535_U48 ( .A(DP_OP_110J3_122_4535_n304), .B(
DP_OP_110J3_122_4535_n278), .C(DP_OP_110J3_122_4535_n291), .D(
DP_OP_110J3_122_4535_n83), .ICI(DP_OP_110J3_122_4535_n252), .S(
DP_OP_110J3_122_4535_n76), .ICO(DP_OP_110J3_122_4535_n74), .CO(
DP_OP_110J3_122_4535_n75) );
CMPR42X1TS DP_OP_110J3_122_4535_U44 ( .A(DP_OP_110J3_122_4535_n264), .B(
DP_OP_110J3_122_4535_n74), .C(DP_OP_110J3_122_4535_n67), .D(
DP_OP_110J3_122_4535_n75), .ICI(DP_OP_110J3_122_4535_n71), .S(
DP_OP_110J3_122_4535_n65), .ICO(DP_OP_110J3_122_4535_n63), .CO(
DP_OP_110J3_122_4535_n64) );
CMPR42X1TS DP_OP_110J3_122_4535_U41 ( .A(DP_OP_110J3_122_4535_n263), .B(
DP_OP_110J3_122_4535_n66), .C(DP_OP_110J3_122_4535_n59), .D(
DP_OP_110J3_122_4535_n63), .ICI(DP_OP_110J3_122_4535_n64), .S(
DP_OP_110J3_122_4535_n57), .ICO(DP_OP_110J3_122_4535_n55), .CO(
DP_OP_110J3_122_4535_n56) );
CMPR42X1TS DP_OP_110J3_122_4535_U39 ( .A(DP_OP_110J3_122_4535_n275), .B(
DP_OP_110J3_122_4535_n249), .C(DP_OP_110J3_122_4535_n262), .D(
DP_OP_110J3_122_4535_n58), .ICI(DP_OP_110J3_122_4535_n55), .S(
DP_OP_110J3_122_4535_n51), .ICO(DP_OP_110J3_122_4535_n49), .CO(
DP_OP_110J3_122_4535_n50) );
CMPR42X1TS DP_OP_110J3_122_4535_U37 ( .A(DP_OP_110J3_122_4535_n274), .B(
DP_OP_110J3_122_4535_n248), .C(DP_OP_110J3_122_4535_n261), .D(
DP_OP_110J3_122_4535_n49), .ICI(DP_OP_110J3_122_4535_n50), .S(
DP_OP_110J3_122_4535_n45), .ICO(DP_OP_110J3_122_4535_n43), .CO(
DP_OP_110J3_122_4535_n44) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n202), .CK(clk),
.RN(n1593), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(clk), .RN(
n1590), .Q(Op_MY[9]), .QN(n402) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n354), .CK(clk), .RN(
n1586), .Q(Op_MX[10]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n364), .CK(clk), .RN(
n1585), .Q(Op_MX[20]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n353), .CK(clk), .RN(
n1586), .Q(Op_MX[9]), .QN(n436) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n365), .CK(clk), .RN(
n1585), .Q(Op_MX[21]), .QN(n428) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n378), .CK(clk), .RN(n167), .Q(
FS_Module_state_reg[1]), .QN(n1599) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n380), .CK(clk), .RN(n167), .Q(
FS_Module_state_reg[3]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(clk), .RN(
n1589), .Q(Op_MY[22]), .QN(n422) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n322), .CK(clk), .RN(
n1590), .Q(Op_MY[10]), .QN(n437) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(clk), .RN(
n1590), .Q(Op_MY[11]), .QN(n438) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n366), .CK(clk), .RN(
n1585), .Q(Op_MX[22]), .QN(DP_OP_110J3_122_4535_n1246) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n1585), .Q(zero_flag), .QN(n1582) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n358), .CK(clk), .RN(
n1586), .Q(Op_MX[14]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n363), .CK(clk), .RN(
n1586), .Q(Op_MX[19]), .QN(n445) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n349), .CK(clk), .RN(
n1586), .Q(Op_MX[5]), .QN(n442) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n361), .CK(clk), .RN(
n1586), .Q(Op_MX[17]), .QN(n440) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n317), .CK(clk), .RN(
n1590), .Q(Op_MY[5]), .QN(n431) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n318), .CK(clk), .RN(
n1590), .Q(Op_MY[6]), .QN(n429) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n351), .CK(clk), .RN(
n1586), .Q(Op_MX[7]), .QN(n423) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n332), .CK(clk), .RN(
n1589), .Q(Op_MY[20]), .QN(n421) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n203), .CK(clk),
.RN(n1593), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n209), .CK(clk),
.RN(n1593), .Q(Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n221), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n223), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n207), .CK(clk),
.RN(n1593), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n211), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n213), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n215), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n219), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n205), .CK(clk),
.RN(n1593), .Q(Sgf_normalized_result[3]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n217), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(n270), .CK(clk), .RN(
n1596), .Q(P_Sgf[32]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(n277), .CK(clk), .RN(
n167), .Q(P_Sgf[39]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(n278), .CK(clk), .RN(
n167), .Q(P_Sgf[40]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(n280), .CK(clk), .RN(
n1597), .Q(P_Sgf[42]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(n281), .CK(clk), .RN(
n1596), .Q(P_Sgf[43]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(n282), .CK(clk), .RN(
n1598), .Q(P_Sgf[44]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(n283), .CK(clk), .RN(
n1597), .Q(P_Sgf[45]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(n276), .CK(clk), .RN(
n167), .Q(P_Sgf[38]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n1585), .Q(Op_MX[27]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(n237), .CK(clk), .RN(
n167), .Q(P_Sgf[47]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n1589), .Q(Op_MY[30]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n308), .CK(clk), .RN(n1588),
.Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n302), .CK(clk), .RN(n1588),
.Q(Add_result[7]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n271), .CK(clk), .RN(
n1596), .Q(P_Sgf[33]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n272), .CK(clk), .RN(
n1596), .Q(P_Sgf[34]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n273), .CK(clk), .RN(
n167), .Q(P_Sgf[35]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(n274), .CK(clk), .RN(
n167), .Q(P_Sgf[36]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(n275), .CK(clk), .RN(
n167), .Q(P_Sgf[37]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(n279), .CK(clk), .RN(
n1598), .Q(P_Sgf[41]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n1589), .Q(Op_MY[27]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n306), .CK(clk), .RN(n1588),
.Q(Add_result[3]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n304), .CK(clk), .RN(n1588),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n285), .CK(clk), .RN(
n1589), .Q(FSM_add_overflow_flag) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n1585), .Q(Op_MX[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n1585), .Q(Op_MX[28]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n1585), .Q(Op_MX[24]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n228), .CK(clk), .RN(n1591),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n231), .CK(clk), .RN(n1591),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n232), .CK(clk), .RN(n1591),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n234), .CK(clk), .RN(n1591),
.Q(exp_oper_result[0]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk), .RN(
n1589), .Q(Op_MY[23]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n243), .CK(clk), .RN(
n1598), .Q(P_Sgf[5]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(n284), .CK(clk), .RN(
n1597), .Q(P_Sgf[46]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n252), .CK(clk), .RN(
n167), .Q(P_Sgf[14]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n256), .CK(clk), .RN(
n1598), .Q(P_Sgf[18]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n261), .CK(clk), .RN(
n1596), .Q(P_Sgf[23]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n310), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[23]), .QN(n1574) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n204), .CK(clk),
.RN(n1593), .Q(Sgf_normalized_result[2]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n355), .CK(clk), .RN(
n1586), .Q(Op_MX[11]), .QN(DP_OP_110J3_122_4535_n905) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n1585), .Q(Op_MX[25]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n1585), .Q(Op_MX[29]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n1585), .Q(Op_MX[26]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n1585), .Q(Op_MX[23]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n303), .CK(clk), .RN(n1588),
.Q(Add_result[6]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n287), .CK(clk), .RN(n1587),
.Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n305), .CK(clk), .RN(n1588),
.Q(Add_result[4]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n1589), .Q(Op_MY[25]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n1589), .Q(Op_MY[29]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n1589), .Q(Op_MY[26]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n1589), .Q(Op_MY[28]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n1589), .Q(Op_MY[24]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n233), .CK(clk), .RN(n1591),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n230), .CK(clk), .RN(n1591),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n229), .CK(clk), .RN(n1591),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n227), .CK(clk), .RN(n1591),
.Q(exp_oper_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n301), .CK(clk), .RN(n1588),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n289), .CK(clk), .RN(n1587),
.Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n291), .CK(clk), .RN(n1587),
.Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n293), .CK(clk), .RN(n1587),
.Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n295), .CK(clk), .RN(n1587),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n297), .CK(clk), .RN(n1588),
.Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n299), .CK(clk), .RN(n1588),
.Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n288), .CK(clk), .RN(n1587),
.Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n290), .CK(clk), .RN(n1587),
.Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n292), .CK(clk), .RN(n1587),
.Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n294), .CK(clk), .RN(n1587),
.Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n296), .CK(clk), .RN(n1588),
.Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n298), .CK(clk), .RN(n1588),
.Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n300), .CK(clk), .RN(n1588),
.Q(Add_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n218), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[16]), .QN(n1567) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n214), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[12]), .QN(n1563) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n224), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[22]), .QN(n1571) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n251), .CK(clk), .RN(
n1597), .Q(P_Sgf[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n222), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[20]), .QN(n1570) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n220), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[18]), .QN(n1568) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n216), .CK(clk),
.RN(n1592), .Q(Sgf_normalized_result[14]), .QN(n1564) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n208), .CK(clk),
.RN(n1593), .Q(Sgf_normalized_result[6]), .QN(n1560) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n247), .CK(clk), .RN(
n1597), .Q(P_Sgf[9]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n258), .CK(clk), .RN(
n1598), .Q(P_Sgf[20]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n254), .CK(clk), .RN(
n1598), .Q(P_Sgf[16]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n250), .CK(clk), .RN(
n1597), .Q(P_Sgf[12]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n257), .CK(clk), .RN(
n1598), .Q(P_Sgf[19]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n253), .CK(clk), .RN(
n1598), .Q(P_Sgf[15]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n259), .CK(clk), .RN(
n1598), .Q(P_Sgf[21]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n255), .CK(clk), .RN(
n1598), .Q(P_Sgf[17]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n246), .CK(clk), .RN(
n1597), .Q(P_Sgf[8]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n242), .CK(clk), .RN(
n1598), .Q(P_Sgf[4]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n249), .CK(clk), .RN(
n1597), .Q(P_Sgf[11]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n245), .CK(clk), .RN(
n1597), .Q(P_Sgf[7]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n241), .CK(clk), .RN(
n1598), .Q(P_Sgf[3]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n307), .CK(clk), .RN(n1588),
.Q(Add_result[2]), .QN(n1573) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n320), .CK(clk), .RN(
n1590), .Q(Op_MY[8]), .QN(n401) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(clk), .RN(
n1590), .Q(Op_MY[7]), .QN(n400) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n315), .CK(clk), .RN(
n1590), .Q(Op_MY[3]), .QN(n399) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n362), .CK(clk), .RN(
n1586), .Q(Op_MX[18]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n360), .CK(clk), .RN(
n1586), .Q(Op_MX[16]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n352), .CK(clk), .RN(
n1586), .Q(Op_MX[8]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n350), .CK(clk), .RN(
n1586), .Q(Op_MX[6]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n348), .CK(clk), .RN(
n1587), .Q(Op_MX[4]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n346), .CK(clk), .RN(
n1587), .Q(Op_MX[2]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n345), .CK(clk), .RN(
n1587), .Q(Op_MX[1]), .QN(n396) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n324), .CK(clk), .RN(
n1590), .Q(Op_MY[12]), .QN(n408) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(clk), .RN(
n1590), .Q(Op_MY[4]), .QN(n432) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n1591), .Q(FSM_selector_C),
.QN(n1569) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n226), .CK(clk), .RN(n1591),
.Q(exp_oper_result[8]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n359), .CK(clk), .RN(
n1586), .Q(Op_MX[15]), .QN(n439) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n312), .CK(clk), .RN(
n1591), .Q(Op_MY[0]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(clk), .RN(
n1590), .Q(Op_MY[2]), .QN(n433) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n331), .CK(clk), .RN(
n1589), .Q(Op_MY[19]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n333), .CK(clk), .RN(
n1589), .Q(Op_MY[21]) );
NAND2X4TS U406 ( .A(n1276), .B(n1196), .Y(n1197) );
NOR2X6TS U407 ( .A(n652), .B(n928), .Y(n724) );
NAND2X1TS U408 ( .A(Sgf_normalized_result[21]), .B(n1540), .Y(n1542) );
NAND2X4TS U409 ( .A(n652), .B(n928), .Y(n1223) );
NAND2X1TS U410 ( .A(Sgf_operation_EVEN1_Q_left[21]), .B(n718), .Y(n725) );
NOR2X1TS U411 ( .A(n701), .B(n700), .Y(n718) );
NAND2X1TS U412 ( .A(Sgf_normalized_result[19]), .B(n1535), .Y(n1537) );
XOR2X1TS U413 ( .A(DP_OP_110J3_122_4535_n33), .B(n543), .Y(n544) );
NOR2X2TS U414 ( .A(n648), .B(n917), .Y(n1423) );
INVX2TS U415 ( .A(Sgf_operation_EVEN1_Q_left[23]), .Y(n721) );
NAND2X1TS U416 ( .A(Sgf_normalized_result[17]), .B(n1531), .Y(n1533) );
NAND2X1TS U417 ( .A(Sgf_operation_EVEN1_Q_left[17]), .B(n692), .Y(n672) );
NAND2X1TS U418 ( .A(n639), .B(n927), .Y(n1358) );
NAND2X1TS U419 ( .A(Sgf_operation_EVEN1_Q_left[15]), .B(
Sgf_operation_EVEN1_Q_left[14]), .Y(n665) );
NAND2X1TS U420 ( .A(Sgf_normalized_result[13]), .B(n1523), .Y(n1525) );
OAI21X1TS U421 ( .A0(n1366), .A1(n1363), .B0(n1367), .Y(n633) );
NAND2X1TS U422 ( .A(Sgf_normalized_result[11]), .B(n406), .Y(n1521) );
ADDFHX1TS U423 ( .A(DP_OP_110J3_122_4535_n951), .B(DP_OP_110J3_122_4535_n947), .CI(n699), .CO(n707), .S(n926) );
NAND2X1TS U424 ( .A(n629), .B(n1143), .Y(n1374) );
NAND2X1TS U425 ( .A(n628), .B(n1115), .Y(n1383) );
NOR2X2TS U426 ( .A(n628), .B(n1115), .Y(n1382) );
NAND2X1TS U427 ( .A(n446), .B(n1389), .Y(n1378) );
NOR2X1TS U428 ( .A(n1191), .B(n603), .Y(n1321) );
NAND2X1TS U429 ( .A(n1191), .B(n603), .Y(n1322) );
CMPR32X2TS U430 ( .A(DP_OP_110J3_122_4535_n957), .B(
DP_OP_110J3_122_4535_n963), .C(n671), .CO(n676), .S(n921) );
CMPR32X2TS U431 ( .A(DP_OP_110J3_122_4535_n561), .B(n558), .C(n557), .CO(
n510), .S(n1187) );
NAND2X1TS U432 ( .A(n624), .B(n623), .Y(n1204) );
CMPR32X2TS U433 ( .A(DP_OP_110J3_122_4535_n564), .B(
DP_OP_110J3_122_4535_n562), .C(n560), .CO(n557), .S(n1191) );
CMPR32X2TS U434 ( .A(DP_OP_110J3_122_4535_n970), .B(
DP_OP_110J3_122_4535_n977), .C(n664), .CO(n668), .S(n915) );
CMPR42X1TS U435 ( .A(DP_OP_110J3_122_4535_n256), .B(
DP_OP_110J3_122_4535_n269), .C(DP_OP_110J3_122_4535_n126), .D(
DP_OP_110J3_122_4535_n122), .ICI(Sgf_operation_EVEN1_Q_left[14]), .S(
DP_OP_110J3_122_4535_n113), .ICO(DP_OP_110J3_122_4535_n111), .CO(
DP_OP_110J3_122_4535_n112) );
NOR2X1TS U436 ( .A(n1190), .B(n594), .Y(n1306) );
NAND2X1TS U437 ( .A(n1190), .B(n594), .Y(n1307) );
NAND2X1TS U438 ( .A(Sgf_normalized_result[7]), .B(n1513), .Y(n1515) );
CMPR32X2TS U439 ( .A(DP_OP_110J3_122_4535_n986), .B(
DP_OP_110J3_122_4535_n995), .C(n658), .CO(n661), .S(
Sgf_operation_EVEN1_Q_left[14]) );
NAND2X1TS U440 ( .A(n1182), .B(n593), .Y(n1301) );
ADDFX2TS U441 ( .A(DP_OP_110J3_122_4535_n575), .B(DP_OP_110J3_122_4535_n581),
.CI(n566), .CO(n564), .S(n1186) );
NAND2X1TS U442 ( .A(Sgf_normalized_result[5]), .B(n1509), .Y(n1511) );
CMPR32X2TS U443 ( .A(DP_OP_110J3_122_4535_n588), .B(
DP_OP_110J3_122_4535_n595), .C(n571), .CO(n568), .S(n1182) );
NAND2X1TS U444 ( .A(n1183), .B(n591), .Y(n1297) );
INVX4TS U445 ( .A(n745), .Y(n1039) );
CMPR42X1TS U446 ( .A(DP_OP_110J3_122_4535_n339), .B(
DP_OP_110J3_122_4535_n171), .C(DP_OP_110J3_122_4535_n287), .D(
DP_OP_110J3_122_4535_n240), .ICI(DP_OP_110J3_122_4535_n172), .S(
DP_OP_110J3_122_4535_n163), .ICO(DP_OP_110J3_122_4535_n161), .CO(
DP_OP_110J3_122_4535_n162) );
NAND2X1TS U447 ( .A(n1185), .B(n589), .Y(n1293) );
BUFX3TS U448 ( .A(n745), .Y(n1037) );
CMPR32X2TS U449 ( .A(DP_OP_110J3_122_4535_n596), .B(
DP_OP_110J3_122_4535_n603), .C(n573), .CO(n571), .S(n1183) );
CMPR32X2TS U450 ( .A(DP_OP_110J3_122_4535_n1013), .B(
DP_OP_110J3_122_4535_n1020), .C(n551), .CO(n548), .S(n1096) );
ADDHXLTS U451 ( .A(n977), .B(n976), .CO(n981), .S(DP_OP_110J3_122_4535_n151)
);
NAND2X1TS U452 ( .A(n1340), .B(n1339), .Y(n1341) );
BUFX4TS U453 ( .A(n741), .Y(n780) );
CMPR32X2TS U454 ( .A(DP_OP_110J3_122_4535_n614), .B(
DP_OP_110J3_122_4535_n622), .C(n579), .CO(n576), .S(n1184) );
CMPR32X2TS U455 ( .A(DP_OP_110J3_122_4535_n1021), .B(
DP_OP_110J3_122_4535_n1026), .C(n553), .CO(n551), .S(n917) );
CMPR42X1TS U456 ( .A(DP_OP_110J3_122_4535_n190), .B(
DP_OP_110J3_122_4535_n341), .C(DP_OP_110J3_122_4535_n522), .D(
DP_OP_110J3_122_4535_n187), .ICI(DP_OP_110J3_122_4535_n191), .S(
DP_OP_110J3_122_4535_n184), .ICO(DP_OP_110J3_122_4535_n182), .CO(
DP_OP_110J3_122_4535_n183) );
NAND2X4TS U457 ( .A(n787), .B(n790), .Y(n788) );
CMPR32X2TS U458 ( .A(n570), .B(n569), .C(DP_OP_110J3_122_4535_n195), .CO(
n567), .S(n594) );
CMPR32X2TS U459 ( .A(DP_OP_110J3_122_4535_n1027), .B(
DP_OP_110J3_122_4535_n1033), .C(n645), .CO(n553), .S(n925) );
CMPR32X2TS U460 ( .A(DP_OP_110J3_122_4535_n1034), .B(
DP_OP_110J3_122_4535_n1038), .C(n642), .CO(n645), .S(n929) );
CMPR32X2TS U461 ( .A(DP_OP_110J3_122_4535_n639), .B(
DP_OP_110J3_122_4535_n644), .C(n1159), .CO(n1177), .S(n1337) );
CMPR32X2TS U462 ( .A(n1125), .B(n1124), .C(n1123), .CO(
DP_OP_110J3_122_4535_n1035), .S(DP_OP_110J3_122_4535_n1036) );
CMPR32X2TS U463 ( .A(Op_MY[7]), .B(Op_MY[19]), .C(n771), .CO(n754), .S(n772)
);
CMPR32X2TS U464 ( .A(Op_MX[20]), .B(Op_MX[8]), .C(n784), .CO(n737), .S(n786)
);
NAND2X4TS U465 ( .A(n812), .B(n811), .Y(n813) );
BUFX3TS U466 ( .A(n710), .Y(n1020) );
CMPR32X2TS U467 ( .A(n525), .B(n524), .C(n523), .CO(n636), .S(n631) );
CMPR32X2TS U468 ( .A(Op_MY[6]), .B(Op_MY[18]), .C(n756), .CO(n771), .S(n757)
);
CMPR32X2TS U469 ( .A(DP_OP_110J3_122_4535_n657), .B(
DP_OP_110J3_122_4535_n661), .C(n922), .CO(n923), .S(n1348) );
CMPR32X2TS U470 ( .A(Op_MY[5]), .B(Op_MY[17]), .C(n732), .CO(n756), .S(n966)
);
CMPR32X2TS U471 ( .A(Op_MX[18]), .B(Op_MX[6]), .C(n799), .CO(n785), .S(n801)
);
BUFX3TS U472 ( .A(Op_MX[21]), .Y(n1092) );
NAND2X4TS U473 ( .A(n531), .B(n533), .Y(n532) );
CMPR32X2TS U474 ( .A(n1011), .B(n1010), .C(n1009), .CO(
DP_OP_110J3_122_4535_n653), .S(DP_OP_110J3_122_4535_n654) );
CMPR32X2TS U475 ( .A(DP_OP_110J3_122_4535_n662), .B(n931), .C(n930), .CO(
n922), .S(n1347) );
NAND2X4TS U476 ( .A(n477), .B(n475), .Y(n476) );
CMPR32X2TS U477 ( .A(Op_MX[16]), .B(Op_MX[4]), .C(n537), .CO(n800), .S(n810)
);
CMPR32X2TS U478 ( .A(n919), .B(n920), .C(n918), .CO(n930), .S(n1329) );
NAND2X4TS U479 ( .A(n829), .B(n827), .Y(n828) );
CMPR32X2TS U480 ( .A(Op_MX[14]), .B(Op_MX[2]), .C(n528), .CO(n534), .S(n530)
);
CMPR32X2TS U481 ( .A(n1106), .B(n1105), .C(n1104), .CO(n1126), .S(n1327) );
NAND2X4TS U482 ( .A(n834), .B(n832), .Y(n833) );
BUFX4TS U483 ( .A(n456), .Y(n1121) );
CMPR32X2TS U484 ( .A(Op_MX[1]), .B(Op_MX[13]), .C(n527), .CO(n528), .S(n529)
);
NAND2X4TS U485 ( .A(Op_MX[13]), .B(n426), .Y(n1118) );
BUFX4TS U486 ( .A(Op_MX[15]), .Y(n998) );
BUFX3TS U487 ( .A(Op_MX[5]), .Y(n1164) );
BUFX3TS U488 ( .A(Op_MX[13]), .Y(n1290) );
NOR2XLTS U489 ( .A(DP_OP_110J3_122_4535_n905), .B(n433), .Y(n840) );
OAI21XLTS U490 ( .A0(n1021), .A1(n409), .B0(n1020), .Y(n1024) );
NOR2XLTS U491 ( .A(n398), .B(n426), .Y(n883) );
INVX2TS U492 ( .A(n1021), .Y(n708) );
BUFX3TS U493 ( .A(Op_MX[3]), .Y(n1155) );
NAND2X1TS U494 ( .A(Sgf_operation_EVEN1_Q_left[19]), .B(n679), .Y(n700) );
NOR2X1TS U495 ( .A(n1182), .B(n593), .Y(n1300) );
OR2X1TS U496 ( .A(n1189), .B(n598), .Y(n416) );
OR2X1TS U497 ( .A(n1561), .B(n1515), .Y(n394) );
OR2X1TS U498 ( .A(n1185), .B(n589), .Y(n412) );
NOR2X2TS U499 ( .A(n649), .B(n1096), .Y(n1213) );
OA21X1TS U500 ( .A0(n1300), .A1(n1303), .B0(n1301), .Y(n414) );
NAND2X1TS U501 ( .A(Sgf_normalized_result[9]), .B(n407), .Y(n1518) );
NAND2X1TS U502 ( .A(Sgf_normalized_result[15]), .B(n1527), .Y(n1529) );
OAI21XLTS U503 ( .A0(n1206), .A1(n1205), .B0(n1204), .Y(n1211) );
OAI211XLTS U504 ( .A0(Sgf_normalized_result[21]), .A1(n1540), .B0(n1539),
.C0(n1542), .Y(n1541) );
AOI211XLTS U505 ( .A0(n1571), .A1(n1542), .B0(n1546), .C0(n1545), .Y(n1543)
);
CLKXOR2X2TS U506 ( .A(n697), .B(n696), .Y(n698) );
CLKXOR2X2TS U507 ( .A(n722), .B(n721), .Y(n723) );
INVX2TS U508 ( .A(n1223), .Y(n653) );
INVX4TS U509 ( .A(n1206), .Y(n1390) );
INVX2TS U510 ( .A(n916), .Y(n728) );
MX2X1TS U511 ( .A(P_Sgf[17]), .B(n1310), .S0(n1295), .Y(n255) );
MX2X1TS U512 ( .A(P_Sgf[18]), .B(n1314), .S0(n1295), .Y(n256) );
AO22XLTS U513 ( .A0(n1550), .A1(n1534), .B0(n1544), .B1(Add_result[18]), .Y(
n291) );
AO22XLTS U514 ( .A0(n1550), .A1(n1530), .B0(n1544), .B1(Add_result[16]), .Y(
n293) );
NAND3XLTS U515 ( .A(n1473), .B(n1472), .C(n1471), .Y(n377) );
INVX3TS U516 ( .A(n1556), .Y(n1552) );
INVX2TS U517 ( .A(n1273), .Y(n1271) );
AO21XLTS U518 ( .A0(n1176), .A1(n1174), .B0(n424), .Y(
DP_OP_110J3_122_4535_n740) );
AO21XLTS U519 ( .A0(n875), .A1(n1119), .B0(n428), .Y(
DP_OP_110J3_122_4535_n1079) );
NAND2BX1TS U520 ( .AN(n409), .B(n954), .Y(n955) );
BUFX3TS U521 ( .A(Op_MX[7]), .Y(n1166) );
BUFX4TS U522 ( .A(Op_MY[0]), .Y(n1169) );
XOR2X2TS U523 ( .A(n690), .B(n689), .Y(n691) );
XOR2X2TS U524 ( .A(n684), .B(n683), .Y(n685) );
XOR2X2TS U525 ( .A(n705), .B(DP_OP_110J3_122_4535_n508), .Y(n706) );
XOR2X2TS U526 ( .A(n729), .B(n728), .Y(n730) );
XOR2X2TS U527 ( .A(n662), .B(DP_OP_110J3_122_4535_n513), .Y(n663) );
OR2X4TS U528 ( .A(n1218), .B(n450), .Y(n651) );
NOR2X2TS U529 ( .A(n1223), .B(n686), .Y(n687) );
NOR2X2TS U530 ( .A(n1223), .B(n700), .Y(n674) );
NOR2X2TS U531 ( .A(n1223), .B(n693), .Y(n694) );
NOR2X2TS U532 ( .A(n1223), .B(n672), .Y(n666) );
NOR2X2TS U533 ( .A(n1223), .B(n725), .Y(n726) );
NOR2X2TS U534 ( .A(n1223), .B(n665), .Y(n659) );
NOR2X2TS U535 ( .A(n1223), .B(n430), .Y(n719) );
NOR2X2TS U536 ( .A(n1223), .B(n680), .Y(n681) );
NOR2X2TS U537 ( .A(n1223), .B(n702), .Y(n703) );
ADDFHX2TS U538 ( .A(DP_OP_110J3_122_4535_n70), .B(DP_OP_110J3_122_4535_n78),
.CI(n635), .CO(n554), .S(n638) );
NOR2X2TS U539 ( .A(n1382), .B(n1378), .Y(n1373) );
ADDFHX2TS U540 ( .A(DP_OP_110J3_122_4535_n79), .B(DP_OP_110J3_122_4535_n87),
.CI(n608), .CO(n635), .S(n632) );
OAI211XLTS U541 ( .A0(Sgf_normalized_result[19]), .A1(n1535), .B0(n1539),
.C0(n1537), .Y(n1536) );
AO22XLTS U542 ( .A0(n1550), .A1(n1526), .B0(n1544), .B1(Add_result[14]), .Y(
n295) );
AO21X1TS U543 ( .A0(n740), .A1(n783), .B0(n766), .Y(
DP_OP_110J3_122_4535_n259) );
NAND3BXLTS U544 ( .AN(Exp_module_Data_S[7]), .B(n1496), .C(n1403), .Y(n1404)
);
OAI211XLTS U545 ( .A0(n1411), .A1(n1576), .B0(n1248), .C0(n1247), .Y(n205)
);
OAI211XLTS U546 ( .A0(n1411), .A1(n1580), .B0(n1256), .C0(n1255), .Y(n208)
);
OAI211XLTS U547 ( .A0(n1411), .A1(n1578), .B0(n1252), .C0(n1251), .Y(n203)
);
OAI211XLTS U548 ( .A0(n1411), .A1(n1579), .B0(n1242), .C0(n1241), .Y(n202)
);
OAI211XLTS U549 ( .A0(n1411), .A1(n1581), .B0(n1246), .C0(n1245), .Y(n207)
);
OAI211XLTS U550 ( .A0(n1411), .A1(n1577), .B0(n1244), .C0(n1243), .Y(n204)
);
OAI211XLTS U551 ( .A0(n1411), .A1(n1575), .B0(n1250), .C0(n1249), .Y(n206)
);
OAI211XLTS U552 ( .A0(n1501), .A1(n1499), .B0(n1259), .C0(n1258), .Y(n224)
);
OAI211XLTS U553 ( .A0(n1582), .A1(n1472), .B0(n1498), .C0(n1260), .Y(n380)
);
INVX3TS U554 ( .A(n1551), .Y(n1553) );
INVX3TS U555 ( .A(n1545), .Y(n1539) );
AO21XLTS U556 ( .A0(n828), .A1(n1194), .B0(n436), .Y(
DP_OP_110J3_122_4535_n698) );
NAND3XLTS U557 ( .A(n1267), .B(n1266), .C(n1265), .Y(n1270) );
BUFX4TS U558 ( .A(n876), .Y(n1119) );
XNOR2X1TS U559 ( .A(n998), .B(Op_MY[13]), .Y(n467) );
BUFX8TS U560 ( .A(Op_MX[1]), .Y(n1278) );
BUFX3TS U561 ( .A(Op_MX[9]), .Y(n1133) );
MX2X2TS U562 ( .A(P_Sgf[40]), .B(n663), .S0(n1428), .Y(n278) );
MX2X2TS U563 ( .A(P_Sgf[39]), .B(n691), .S0(n1428), .Y(n277) );
MX2X2TS U564 ( .A(P_Sgf[47]), .B(n723), .S0(n1428), .Y(n237) );
MX2X2TS U565 ( .A(P_Sgf[41]), .B(n698), .S0(n1428), .Y(n279) );
MX2X2TS U566 ( .A(P_Sgf[45]), .B(n706), .S0(n1398), .Y(n283) );
MX2X2TS U567 ( .A(P_Sgf[46]), .B(n730), .S0(n1398), .Y(n284) );
MX2X2TS U568 ( .A(P_Sgf[43]), .B(n685), .S0(n1428), .Y(n281) );
ADDFHX2TS U569 ( .A(DP_OP_110J3_122_4535_n42), .B(DP_OP_110J3_122_4535_n47),
.CI(n552), .CO(n549), .S(n648) );
NOR2X2TS U570 ( .A(n643), .B(n929), .Y(n1405) );
NAND2X2TS U571 ( .A(n606), .B(n605), .Y(n1395) );
INVX2TS U572 ( .A(n1187), .Y(DP_OP_110J3_122_4535_n216) );
INVX4TS U573 ( .A(Sgf_operation_EVEN1_Q_left[21]), .Y(
DP_OP_110J3_122_4535_n508) );
ADDFHX2TS U574 ( .A(DP_OP_110J3_122_4535_n88), .B(DP_OP_110J3_122_4535_n98),
.CI(n609), .CO(n608), .S(n629) );
NOR2X2TS U575 ( .A(n1568), .B(n1533), .Y(n1535) );
ADDFHX2TS U576 ( .A(DP_OP_110J3_122_4535_n132), .B(DP_OP_110J3_122_4535_n142), .CI(n622), .CO(n621), .S(n624) );
OAI211XLTS U577 ( .A0(Sgf_normalized_result[17]), .A1(n1531), .B0(n1539),
.C0(n1533), .Y(n1532) );
OR2X2TS U578 ( .A(n1184), .B(n587), .Y(n392) );
NOR2X2TS U579 ( .A(n1567), .B(n1529), .Y(n1531) );
INVX2TS U580 ( .A(n1096), .Y(DP_OP_110J3_122_4535_n518) );
NOR2X2TS U581 ( .A(n1564), .B(n1525), .Y(n1527) );
AO22XLTS U582 ( .A0(n1550), .A1(n1522), .B0(n1544), .B1(Add_result[12]), .Y(
n297) );
AO22XLTS U583 ( .A0(n1550), .A1(n1519), .B0(n1544), .B1(Add_result[10]), .Y(
n299) );
NOR2X2TS U584 ( .A(n1563), .B(n1521), .Y(n1523) );
OR2X4TS U585 ( .A(n746), .B(Op_MY[11]), .Y(n541) );
INVX2TS U586 ( .A(n395), .Y(n406) );
CMPR42X1TS U587 ( .A(DP_OP_110J3_122_4535_n233), .B(
DP_OP_110J3_122_4535_n242), .C(DP_OP_110J3_122_4535_n317), .D(
DP_OP_110J3_122_4535_n199), .ICI(DP_OP_110J3_122_4535_n201), .S(
DP_OP_110J3_122_4535_n195), .ICO(DP_OP_110J3_122_4535_n193), .CO(
DP_OP_110J3_122_4535_n194) );
INVX2TS U588 ( .A(n394), .Y(n407) );
BUFX3TS U589 ( .A(n1240), .Y(n1469) );
INVX3TS U590 ( .A(n1238), .Y(n404) );
INVX3TS U591 ( .A(n1545), .Y(n1550) );
NAND2X4TS U592 ( .A(n876), .B(n874), .Y(n875) );
NAND2BX1TS U593 ( .AN(Op_MY[0]), .B(n1145), .Y(n1017) );
BUFX6TS U594 ( .A(n482), .Y(n1174) );
NAND2X4TS U595 ( .A(Op_MX[1]), .B(n435), .Y(n483) );
MX2X2TS U596 ( .A(P_Sgf[42]), .B(n670), .S0(n1428), .Y(n280) );
MX2X2TS U597 ( .A(P_Sgf[38]), .B(n657), .S0(n1428), .Y(n276) );
MX2X2TS U598 ( .A(P_Sgf[44]), .B(n678), .S0(n1398), .Y(n282) );
XOR2X2TS U599 ( .A(n654), .B(n686), .Y(n657) );
XOR2X2TS U600 ( .A(n669), .B(n673), .Y(n670) );
MX2X2TS U601 ( .A(P_Sgf[37]), .B(n1227), .S0(n1428), .Y(n275) );
XOR2X2TS U602 ( .A(n677), .B(n701), .Y(n678) );
CLKMX2X2TS U603 ( .A(P_Sgf[36]), .B(n1222), .S0(n1428), .Y(n274) );
CLKMX2X2TS U604 ( .A(P_Sgf[35]), .B(n1217), .S0(n1428), .Y(n273) );
CLKMX2X2TS U605 ( .A(P_Sgf[34]), .B(n1429), .S0(n1428), .Y(n272) );
CLKMX2X2TS U606 ( .A(P_Sgf[33]), .B(n1419), .S0(n1428), .Y(n271) );
CLKMX2X2TS U607 ( .A(P_Sgf[32]), .B(n1410), .S0(n1428), .Y(n270) );
CLKMX2X2TS U608 ( .A(P_Sgf[31]), .B(n1361), .S0(n1398), .Y(n269) );
CLKMX2X2TS U609 ( .A(P_Sgf[26]), .B(n1394), .S0(n1398), .Y(n264) );
NAND2X2TS U610 ( .A(n1224), .B(n1223), .Y(n1226) );
CLKMX2X2TS U611 ( .A(P_Sgf[27]), .B(n1387), .S0(n1398), .Y(n265) );
CLKMX2X2TS U612 ( .A(P_Sgf[29]), .B(n1371), .S0(n1398), .Y(n267) );
CLKMX2X2TS U613 ( .A(P_Sgf[28]), .B(n1377), .S0(n1398), .Y(n266) );
CLKMX2X2TS U614 ( .A(P_Sgf[30]), .B(n1357), .S0(n1398), .Y(n268) );
CLKMX2X2TS U615 ( .A(P_Sgf[23]), .B(n1399), .S0(n1398), .Y(n261) );
CLKMX2X2TS U616 ( .A(P_Sgf[22]), .B(n1334), .S0(n1346), .Y(n260) );
CLKMX2X2TS U617 ( .A(P_Sgf[21]), .B(n1326), .S0(n1346), .Y(n259) );
OAI21X2TS U618 ( .A0(n1330), .A1(n418), .B0(n1331), .Y(n1396) );
NAND2X2TS U619 ( .A(n648), .B(n917), .Y(n1424) );
NAND2X2TS U620 ( .A(n646), .B(n925), .Y(n1416) );
CLKMX2X2TS U621 ( .A(P_Sgf[20]), .B(n1320), .S0(n1346), .Y(n258) );
NAND2X2TS U622 ( .A(n643), .B(n929), .Y(n1406) );
AOI21X2TS U623 ( .A0(n417), .A1(n600), .B0(n602), .Y(n1324) );
CLKMX2X2TS U624 ( .A(P_Sgf[19]), .B(n1317), .S0(n1346), .Y(n257) );
OR2X2TS U625 ( .A(n606), .B(n605), .Y(n419) );
OR2X2TS U626 ( .A(n639), .B(n927), .Y(n448) );
OR2X2TS U627 ( .A(n728), .B(n725), .Y(n430) );
AO21X2TS U628 ( .A0(n416), .A1(n597), .B0(n599), .Y(n600) );
XOR2X2TS U629 ( .A(n510), .B(n509), .Y(n606) );
CLKXOR2X2TS U630 ( .A(n715), .B(n714), .Y(Sgf_operation_EVEN1_Q_left[23]) );
AO21X1TS U631 ( .A0(Add_result[22]), .A1(n1544), .B0(n1543), .Y(n287) );
OAI21X2TS U632 ( .A0(n1382), .A1(n1379), .B0(n1383), .Y(n1372) );
OAI21X1TS U633 ( .A0(n1546), .A1(Sgf_normalized_result[23]), .B0(n1549), .Y(
n1547) );
AOI2BB1X1TS U634 ( .A0N(n1550), .A1N(FSM_add_overflow_flag), .B0(n1549), .Y(
n285) );
ADDFHX2TS U635 ( .A(DP_OP_110J3_122_4535_n946), .B(DP_OP_110J3_122_4535_n944), .CI(n707), .CO(n716), .S(Sgf_operation_EVEN1_Q_left[21]) );
OR2X2TS U636 ( .A(n1188), .B(n601), .Y(n417) );
AO21X2TS U637 ( .A0(n415), .A1(n1312), .B0(n596), .Y(n597) );
AO22X1TS U638 ( .A0(n1550), .A1(n1538), .B0(n1544), .B1(Add_result[20]), .Y(
n289) );
ADDFHX2TS U639 ( .A(DP_OP_110J3_122_4535_n569), .B(DP_OP_110J3_122_4535_n565), .CI(n562), .CO(n560), .S(n1188) );
OAI21X2TS U640 ( .A0(n1306), .A1(n414), .B0(n1307), .Y(n1312) );
OR2X2TS U641 ( .A(n626), .B(n1098), .Y(n446) );
ADDFHX2TS U642 ( .A(DP_OP_110J3_122_4535_n574), .B(DP_OP_110J3_122_4535_n570), .CI(n564), .CO(n562), .S(n1189) );
OR2X2TS U643 ( .A(n1186), .B(n595), .Y(n415) );
NOR2X2TS U644 ( .A(n624), .B(n623), .Y(n1205) );
OR2X2TS U645 ( .A(n1183), .B(n591), .Y(n413) );
ADDFHX2TS U646 ( .A(DP_OP_110J3_122_4535_n978), .B(DP_OP_110J3_122_4535_n985), .CI(n661), .CO(n664), .S(Sgf_operation_EVEN1_Q_left[15]) );
ADDFHX2TS U647 ( .A(DP_OP_110J3_122_4535_n996), .B(
DP_OP_110J3_122_4535_n1004), .CI(n546), .CO(n658), .S(n928) );
ADDFHX2TS U648 ( .A(DP_OP_110J3_122_4535_n623), .B(DP_OP_110J3_122_4535_n630), .CI(n583), .CO(n579), .S(n1340) );
NOR2X1TS U649 ( .A(n1039), .B(n750), .Y(n542) );
ADDFHX2TS U650 ( .A(DP_OP_110J3_122_4535_n1005), .B(
DP_OP_110J3_122_4535_n1012), .CI(n548), .CO(n546), .S(n1097) );
AO21X1TS U651 ( .A0(n788), .A1(n1074), .B0(n792), .Y(
DP_OP_110J3_122_4535_n274) );
NAND2X4TS U652 ( .A(n739), .B(n742), .Y(n740) );
ADDFHX2TS U653 ( .A(DP_OP_110J3_122_4535_n645), .B(DP_OP_110J3_122_4535_n651), .CI(n1170), .CO(n1159), .S(n1350) );
ADDFHX2TS U654 ( .A(DP_OP_110J3_122_4535_n652), .B(DP_OP_110J3_122_4535_n656), .CI(n923), .CO(n1170), .S(n1349) );
OR2X2TS U655 ( .A(n1562), .B(n1518), .Y(n395) );
AO21X1TS U656 ( .A0(n813), .A1(n1056), .B0(n816), .Y(
DP_OP_110J3_122_4535_n304) );
AO21XLTS U657 ( .A0(n532), .A1(n1153), .B0(n1088), .Y(n972) );
OAI211XLTS U658 ( .A0(n1414), .A1(n411), .B0(n1413), .C0(n1412), .Y(n1415)
);
CLKBUFX3TS U659 ( .A(n1469), .Y(n405) );
CLKINVX3TS U660 ( .A(n1238), .Y(n403) );
OR3X2TS U661 ( .A(underflow_flag), .B(overflow_flag), .C(n1554), .Y(n1551)
);
NOR2X4TS U662 ( .A(n1428), .B(n1496), .Y(n1400) );
NOR2XLTS U663 ( .A(n1470), .B(n1235), .Y(n379) );
NOR2X4TS U664 ( .A(FSM_selector_C), .B(n1239), .Y(n1257) );
NOR2X1TS U665 ( .A(n1569), .B(n1239), .Y(n1240) );
AO21X1TS U666 ( .A0(n833), .A1(n1192), .B0(n423), .Y(
DP_OP_110J3_122_4535_n712) );
OR2X1TS U667 ( .A(n1501), .B(n1569), .Y(n1238) );
AO21X1TS U668 ( .A0(n937), .A1(n935), .B0(n440), .Y(
DP_OP_110J3_122_4535_n1107) );
AO21X1TS U669 ( .A0(n1181), .A1(n1179), .B0(n442), .Y(
DP_OP_110J3_122_4535_n726) );
AO21X1TS U670 ( .A0(n455), .A1(n1121), .B0(n439), .Y(
DP_OP_110J3_122_4535_n1121) );
AO21X1TS U671 ( .A0(n1003), .A1(n889), .B0(n445), .Y(
DP_OP_110J3_122_4535_n1093) );
NAND3X1TS U672 ( .A(n1273), .B(FS_Module_state_reg[1]), .C(
FSM_add_overflow_flag), .Y(n655) );
XNOR2X1TS U673 ( .A(n1290), .B(Op_MY[19]), .Y(n1117) );
NAND2BX1TS U674 ( .AN(n409), .B(n1092), .Y(n1093) );
XNOR2X1TS U675 ( .A(n1290), .B(DP_OP_110J3_122_4535_n948), .Y(n1116) );
BUFX4TS U676 ( .A(n477), .Y(n1147) );
NAND3X1TS U677 ( .A(FS_Module_state_reg[3]), .B(n1277), .C(n1557), .Y(n1548)
);
NAND2BX1TS U678 ( .AN(n1169), .B(n1133), .Y(n1013) );
NAND2X4TS U679 ( .A(n456), .B(n454), .Y(n455) );
NAND2X4TS U680 ( .A(n482), .B(n481), .Y(n1176) );
NAND2BX1TS U681 ( .AN(n409), .B(n1290), .Y(n473) );
NAND2X4TS U682 ( .A(n889), .B(n878), .Y(n1003) );
NAND2X1TS U683 ( .A(n709), .B(DP_OP_110J3_122_4535_n1246), .Y(n710) );
NAND2BXLTS U684 ( .AN(n1169), .B(n1166), .Y(n1130) );
OR2X2TS U685 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
NOR2XLTS U686 ( .A(n1599), .B(n1558), .Y(n1229) );
XNOR2X1TS U687 ( .A(Op_MX[22]), .B(Op_MX[21]), .Y(n709) );
INVX4TS U688 ( .A(n408), .Y(n409) );
XNOR2X1TS U689 ( .A(Op_MX[7]), .B(Op_MX[8]), .Y(n829) );
NOR2X1TS U690 ( .A(DP_OP_110J3_122_4535_n905), .B(n400), .Y(n831) );
NOR2X1TS U691 ( .A(DP_OP_110J3_122_4535_n905), .B(n399), .Y(n836) );
XNOR2X1TS U692 ( .A(Op_MX[5]), .B(Op_MX[6]), .Y(n834) );
ADDFHX2TS U693 ( .A(DP_OP_110J3_122_4535_n604), .B(DP_OP_110J3_122_4535_n613), .CI(n576), .CO(n573), .S(n1185) );
OA21X4TS U694 ( .A0(n1321), .A1(n1324), .B0(n1322), .Y(n418) );
ADDFHX2TS U695 ( .A(DP_OP_110J3_122_4535_n110), .B(DP_OP_110J3_122_4535_n120), .CI(n617), .CO(n613), .S(n626) );
ADDFHX2TS U696 ( .A(DP_OP_110J3_122_4535_n121), .B(DP_OP_110J3_122_4535_n131), .CI(n621), .CO(n617), .S(n625) );
AOI21X4TS U697 ( .A0(n1224), .A1(n1225), .B0(n653), .Y(n654) );
XNOR2X2TS U698 ( .A(n1290), .B(Op_MY[14]), .Y(n472) );
OAI21X4TS U699 ( .A0(n1355), .A1(n1352), .B0(n1353), .Y(n1359) );
AOI21X4TS U700 ( .A0(n1417), .A1(n393), .B0(n647), .Y(n1426) );
XOR2X4TS U701 ( .A(n545), .B(n544), .Y(n652) );
ADDFHX4TS U702 ( .A(DP_OP_110J3_122_4535_n34), .B(DP_OP_110J3_122_4535_n36),
.CI(n547), .CO(n545), .S(n650) );
CMPR42X2TS U703 ( .A(DP_OP_110J3_122_4535_n45), .B(DP_OP_110J3_122_4535_n508), .C(DP_OP_110J3_122_4535_n46), .D(DP_OP_110J3_122_4535_n216), .ICI(n728), .S(
DP_OP_110J3_122_4535_n42), .ICO(DP_OP_110J3_122_4535_n40), .CO(
DP_OP_110J3_122_4535_n41) );
INVX4TS U704 ( .A(n724), .Y(n1224) );
NAND2X8TS U705 ( .A(n651), .B(n1219), .Y(n1225) );
AOI21X4TS U706 ( .A0(n419), .A1(n1396), .B0(n607), .Y(n1206) );
OAI21X4TS U707 ( .A0(n1408), .A1(n1405), .B0(n1406), .Y(n1417) );
XNOR2X1TS U708 ( .A(n1278), .B(Op_MY[2]), .Y(n499) );
OAI22X1TS U709 ( .A0(n788), .A1(n1075), .B0(n968), .B1(n1074), .Y(n973) );
AO21X1TS U710 ( .A0(n803), .A1(n1079), .B0(n1035), .Y(n1041) );
INVX2TS U711 ( .A(n1358), .Y(n640) );
INVX2TS U712 ( .A(n1395), .Y(n607) );
BUFX3TS U713 ( .A(Op_MX[11]), .Y(n1145) );
BUFX4TS U714 ( .A(n709), .Y(n1021) );
CMPR42X2TS U715 ( .A(DP_OP_110J3_122_4535_n57), .B(n683), .C(
DP_OP_110J3_122_4535_n60), .D(DP_OP_110J3_122_4535_n218), .ICI(n701),
.S(DP_OP_110J3_122_4535_n54), .ICO(DP_OP_110J3_122_4535_n52), .CO(
DP_OP_110J3_122_4535_n53) );
OAI22X1TS U716 ( .A0(n1176), .A1(n1137), .B0(n1174), .B1(n1136), .Y(n1141)
);
AOI21X2TS U717 ( .A0(n446), .A1(n1388), .B0(n627), .Y(n1379) );
INVX2TS U718 ( .A(n1391), .Y(n627) );
AOI21X2TS U719 ( .A0(n413), .A1(n434), .B0(n592), .Y(n1303) );
NOR2X2TS U720 ( .A(n650), .B(n1097), .Y(n1218) );
NAND2X2TS U721 ( .A(n650), .B(n1097), .Y(n1219) );
NAND2X2TS U722 ( .A(n649), .B(n1096), .Y(n1214) );
NOR2X2TS U723 ( .A(n1366), .B(n1362), .Y(n634) );
NOR2X2TS U724 ( .A(n638), .B(n924), .Y(n1352) );
NAND2X2TS U725 ( .A(n638), .B(n924), .Y(n1353) );
NOR2X2TS U726 ( .A(n1187), .B(n604), .Y(n1330) );
NAND2X2TS U727 ( .A(n1187), .B(n604), .Y(n1331) );
BUFX4TS U728 ( .A(n814), .Y(n1052) );
BUFX4TS U729 ( .A(n804), .Y(n987) );
BUFX4TS U730 ( .A(n535), .Y(n1085) );
NOR2X1TS U731 ( .A(DP_OP_110J3_122_4535_n905), .B(n429), .Y(n942) );
INVX2TS U732 ( .A(n837), .Y(n842) );
BUFX3TS U733 ( .A(n747), .Y(n1026) );
XNOR2X2TS U734 ( .A(n538), .B(Op_MX[11]), .Y(n741) );
ADDFHX2TS U735 ( .A(Op_MY[2]), .B(Op_MY[14]), .CI(n512), .CO(n540), .S(n821)
);
BUFX4TS U736 ( .A(n789), .Y(n1025) );
NAND2BXLTS U737 ( .AN(n1086), .B(n1052), .Y(n815) );
NAND2BXLTS U738 ( .AN(n762), .B(n1025), .Y(n791) );
NAND2BXLTS U739 ( .AN(n1086), .B(n987), .Y(n806) );
INVX2TS U740 ( .A(n987), .Y(n1035) );
INVX2TS U741 ( .A(n1085), .Y(n1088) );
NAND2X4TS U742 ( .A(n802), .B(n805), .Y(n803) );
OAI22X1TS U743 ( .A0(n1118), .A1(n1116), .B0(n1091), .B1(n426), .Y(n1095) );
OAI22X1TS U744 ( .A0(n875), .A1(n997), .B0(n1119), .B1(n996), .Y(n1006) );
NOR2BX1TS U745 ( .AN(n409), .B(n1119), .Y(n1124) );
OAI22X1TS U746 ( .A0(n1118), .A1(n1117), .B0(n1116), .B1(n426), .Y(n1125) );
NAND2BXLTS U747 ( .AN(n762), .B(n780), .Y(n765) );
NOR2X1TS U748 ( .A(DP_OP_110J3_122_4535_n905), .B(n401), .Y(
DP_OP_110J3_122_4535_n566) );
ADDHXLTS U749 ( .A(n957), .B(n956), .CO(DP_OP_110J3_122_4535_n1040), .S(
DP_OP_110J3_122_4535_n1041) );
OAI22X1TS U750 ( .A0(n1118), .A1(n953), .B0(n1117), .B1(n426), .Y(n957) );
BUFX4TS U751 ( .A(n529), .Y(n961) );
CMPR42X1TS U752 ( .A(DP_OP_110J3_122_4535_n523), .B(
DP_OP_110J3_122_4535_n303), .C(DP_OP_110J3_122_4535_n196), .D(
DP_OP_110J3_122_4535_n193), .ICI(DP_OP_110J3_122_4535_n194), .S(
DP_OP_110J3_122_4535_n189), .ICO(DP_OP_110J3_122_4535_n187), .CO(
DP_OP_110J3_122_4535_n188) );
CMPR42X1TS U753 ( .A(DP_OP_110J3_122_4535_n51), .B(DP_OP_110J3_122_4535_n56),
.C(DP_OP_110J3_122_4535_n52), .D(Sgf_operation_EVEN1_Q_left[21]),
.ICI(DP_OP_110J3_122_4535_n217), .S(DP_OP_110J3_122_4535_n48), .ICO(
DP_OP_110J3_122_4535_n46), .CO(DP_OP_110J3_122_4535_n47) );
CMPR42X1TS U754 ( .A(Sgf_operation_EVEN1_Q_left[15]), .B(
DP_OP_110J3_122_4535_n223), .C(DP_OP_110J3_122_4535_n112), .D(
DP_OP_110J3_122_4535_n108), .ICI(DP_OP_110J3_122_4535_n102), .S(
DP_OP_110J3_122_4535_n99), .ICO(DP_OP_110J3_122_4535_n97), .CO(
DP_OP_110J3_122_4535_n98) );
CMPR42X1TS U755 ( .A(DP_OP_110J3_122_4535_n144), .B(
DP_OP_110J3_122_4535_n271), .C(DP_OP_110J3_122_4535_n145), .D(
DP_OP_110J3_122_4535_n141), .ICI(DP_OP_110J3_122_4535_n135), .S(
DP_OP_110J3_122_4535_n132), .ICO(DP_OP_110J3_122_4535_n130), .CO(
DP_OP_110J3_122_4535_n131) );
ADDHXLTS U756 ( .A(n995), .B(n994), .CO(DP_OP_110J3_122_4535_n1047), .S(n524) );
NAND2BXLTS U757 ( .AN(Op_MY[12]), .B(n903), .Y(n462) );
CMPR42X1TS U758 ( .A(DP_OP_110J3_122_4535_n90), .B(DP_OP_110J3_122_4535_n82),
.C(Sgf_operation_EVEN1_Q_left[17]), .D(DP_OP_110J3_122_4535_n86),
.ICI(DP_OP_110J3_122_4535_n221), .S(DP_OP_110J3_122_4535_n79), .ICO(
DP_OP_110J3_122_4535_n77), .CO(DP_OP_110J3_122_4535_n78) );
NOR2BX1TS U759 ( .AN(n1169), .B(n1194), .Y(n1010) );
CMPR42X1TS U760 ( .A(DP_OP_110J3_122_4535_n164), .B(
DP_OP_110J3_122_4535_n519), .C(DP_OP_110J3_122_4535_n160), .D(
DP_OP_110J3_122_4535_n165), .ICI(DP_OP_110J3_122_4535_n162), .S(
DP_OP_110J3_122_4535_n154), .ICO(DP_OP_110J3_122_4535_n152), .CO(
DP_OP_110J3_122_4535_n153) );
CMPR42X1TS U761 ( .A(DP_OP_110J3_122_4535_n65), .B(DP_OP_110J3_122_4535_n72),
.C(DP_OP_110J3_122_4535_n68), .D(Sgf_operation_EVEN1_Q_left[19]),
.ICI(DP_OP_110J3_122_4535_n219), .S(DP_OP_110J3_122_4535_n62), .ICO(
DP_OP_110J3_122_4535_n60), .CO(DP_OP_110J3_122_4535_n61) );
ADDFHX2TS U762 ( .A(DP_OP_110J3_122_4535_n173), .B(DP_OP_110J3_122_4535_n176), .CI(n563), .CO(n561), .S(n601) );
XOR3X1TS U763 ( .A(n506), .B(n505), .C(n504), .Y(n507) );
ADDFHX2TS U764 ( .A(DP_OP_110J3_122_4535_n189), .B(DP_OP_110J3_122_4535_n192), .CI(n567), .CO(n565), .S(n595) );
NAND2BXLTS U765 ( .AN(n1169), .B(n1164), .Y(n489) );
NOR2X1TS U766 ( .A(n673), .B(n672), .Y(n679) );
NOR2X1TS U767 ( .A(DP_OP_110J3_122_4535_n513), .B(n665), .Y(n692) );
NAND2BXLTS U768 ( .AN(n409), .B(n998), .Y(n471) );
ADDHX1TS U769 ( .A(n519), .B(n518), .CO(n618), .S(n1150) );
NOR2X2TS U770 ( .A(n625), .B(n1150), .Y(n1207) );
INVX2TS U771 ( .A(n1374), .Y(n630) );
NAND2X1TS U772 ( .A(n447), .B(n1373), .Y(n1362) );
NOR2X2TS U773 ( .A(n632), .B(n631), .Y(n1366) );
ADDFHX2TS U774 ( .A(DP_OP_110J3_122_4535_n154), .B(DP_OP_110J3_122_4535_n157), .CI(n559), .CO(n556), .S(n604) );
ADDFHX2TS U775 ( .A(DP_OP_110J3_122_4535_n62), .B(DP_OP_110J3_122_4535_n69),
.CI(n554), .CO(n641), .S(n639) );
NAND2BXLTS U776 ( .AN(n1169), .B(n1155), .Y(n498) );
NAND2X1TS U777 ( .A(n1189), .B(n598), .Y(n1315) );
INVX2TS U778 ( .A(n1311), .Y(n596) );
NAND2X1TS U779 ( .A(n1188), .B(n601), .Y(n1318) );
INVX2TS U780 ( .A(n1315), .Y(n599) );
NAND2X1TS U781 ( .A(n1186), .B(n595), .Y(n1311) );
NAND2X2TS U782 ( .A(n656), .B(n655), .Y(n1295) );
NOR2X1TS U783 ( .A(n724), .B(n725), .Y(n727) );
INVX2TS U784 ( .A(n692), .Y(n693) );
NOR2X1TS U785 ( .A(n724), .B(n693), .Y(n695) );
INVX2TS U786 ( .A(n1416), .Y(n647) );
NOR2X1TS U787 ( .A(n724), .B(n430), .Y(n720) );
INVX2TS U788 ( .A(n718), .Y(n702) );
NOR2X1TS U789 ( .A(n724), .B(n702), .Y(n704) );
NOR2X1TS U790 ( .A(n724), .B(n700), .Y(n675) );
INVX2TS U791 ( .A(n679), .Y(n680) );
NOR2X1TS U792 ( .A(n724), .B(n680), .Y(n682) );
NOR2X1TS U793 ( .A(n724), .B(n672), .Y(n667) );
NOR2X1TS U794 ( .A(n724), .B(n665), .Y(n660) );
NOR2X1TS U795 ( .A(n724), .B(n686), .Y(n688) );
BUFX4TS U796 ( .A(n1295), .Y(n1428) );
INVX2TS U797 ( .A(n1378), .Y(n1381) );
INVX2TS U798 ( .A(n1379), .Y(n1380) );
INVX2TS U799 ( .A(n1382), .Y(n1384) );
OAI21X1TS U800 ( .A0(n1207), .A1(n1204), .B0(n1208), .Y(n1388) );
NOR2X1TS U801 ( .A(n1207), .B(n1205), .Y(n1389) );
NAND2X1TS U802 ( .A(n626), .B(n1098), .Y(n1391) );
NAND2X1TS U803 ( .A(n625), .B(n1150), .Y(n1208) );
INVX2TS U804 ( .A(n1363), .Y(n1364) );
INVX2TS U805 ( .A(n1362), .Y(n1365) );
NAND2X1TS U806 ( .A(n632), .B(n631), .Y(n1367) );
INVX2TS U807 ( .A(n1366), .Y(n1368) );
BUFX3TS U808 ( .A(n1548), .Y(n1545) );
ADDHX1TS U809 ( .A(n517), .B(n516), .CO(n1101), .S(n1336) );
NAND2BXLTS U810 ( .AN(n1169), .B(n1278), .Y(n500) );
XOR2X1TS U811 ( .A(n1309), .B(n414), .Y(n1310) );
NAND2X1TS U812 ( .A(n1308), .B(n1307), .Y(n1309) );
XOR2X1TS U813 ( .A(n1325), .B(n1324), .Y(n1326) );
NAND2X1TS U814 ( .A(n1323), .B(n1322), .Y(n1325) );
INVX2TS U815 ( .A(n1321), .Y(n1323) );
MX2X1TS U816 ( .A(P_Sgf[15]), .B(n1299), .S0(n1295), .Y(n253) );
XNOR2X1TS U817 ( .A(n1298), .B(n434), .Y(n1299) );
XNOR2X1TS U818 ( .A(n1316), .B(n597), .Y(n1317) );
NAND2X1TS U819 ( .A(n416), .B(n1315), .Y(n1316) );
MX2X1TS U820 ( .A(P_Sgf[12]), .B(n444), .S0(n1346), .Y(n250) );
MX2X1TS U821 ( .A(P_Sgf[16]), .B(n1305), .S0(n1295), .Y(n254) );
XOR2X1TS U822 ( .A(n1304), .B(n1303), .Y(n1305) );
NAND2X1TS U823 ( .A(n1302), .B(n1301), .Y(n1304) );
XNOR2X1TS U824 ( .A(n1319), .B(n600), .Y(n1320) );
NAND2X1TS U825 ( .A(n417), .B(n1318), .Y(n1319) );
MX2X1TS U826 ( .A(P_Sgf[13]), .B(n1345), .S0(n1346), .Y(n251) );
AO22XLTS U827 ( .A0(n1550), .A1(n1516), .B0(n1544), .B1(Add_result[8]), .Y(
n301) );
AO22XLTS U828 ( .A0(n1550), .A1(n1508), .B0(n1544), .B1(Add_result[4]), .Y(
n305) );
AO22XLTS U829 ( .A0(n1550), .A1(n1512), .B0(n1544), .B1(Add_result[6]), .Y(
n303) );
XNOR2X1TS U830 ( .A(n1397), .B(n1396), .Y(n1399) );
NAND2X1TS U831 ( .A(n419), .B(n1395), .Y(n1397) );
XNOR2X1TS U832 ( .A(n1313), .B(n1312), .Y(n1314) );
NAND2X1TS U833 ( .A(n415), .B(n1311), .Y(n1313) );
MX2X1TS U834 ( .A(P_Sgf[14]), .B(n1296), .S0(n1295), .Y(n252) );
XNOR2X1TS U835 ( .A(n1226), .B(n1225), .Y(n1227) );
XOR2X1TS U836 ( .A(n1221), .B(n450), .Y(n1222) );
NAND2X1TS U837 ( .A(n1220), .B(n1219), .Y(n1221) );
INVX2TS U838 ( .A(n1218), .Y(n1220) );
XOR2X1TS U839 ( .A(n1216), .B(n449), .Y(n1217) );
NAND2X1TS U840 ( .A(n1215), .B(n1214), .Y(n1216) );
INVX2TS U841 ( .A(n1213), .Y(n1215) );
XOR2X1TS U842 ( .A(n1427), .B(n1426), .Y(n1429) );
NAND2X1TS U843 ( .A(n1425), .B(n1424), .Y(n1427) );
INVX2TS U844 ( .A(n1423), .Y(n1425) );
XNOR2X1TS U845 ( .A(n1418), .B(n1417), .Y(n1419) );
NAND2X1TS U846 ( .A(n393), .B(n1416), .Y(n1418) );
NAND2X1TS U847 ( .A(n1407), .B(n1406), .Y(n1409) );
INVX2TS U848 ( .A(n1405), .Y(n1407) );
MX2X1TS U849 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(n1400),
.Y(n226) );
MX2X1TS U850 ( .A(Exp_module_Overflow_flag_A), .B(n1401), .S0(n1428), .Y(
n225) );
OAI31X1TS U851 ( .A0(FS_Module_state_reg[1]), .A1(n1271), .A2(n1272), .B0(
n1569), .Y(n375) );
NAND2X1TS U852 ( .A(n447), .B(n1374), .Y(n1375) );
AOI21X1TS U853 ( .A0(n1390), .A1(n1373), .B0(n1372), .Y(n1376) );
XOR2X1TS U854 ( .A(n1386), .B(n1385), .Y(n1387) );
NAND2X1TS U855 ( .A(n1384), .B(n1383), .Y(n1385) );
AOI21X1TS U856 ( .A0(n1390), .A1(n1381), .B0(n1380), .Y(n1386) );
XOR2X1TS U857 ( .A(n1393), .B(n1392), .Y(n1394) );
NAND2X1TS U858 ( .A(n446), .B(n1391), .Y(n1392) );
AOI21X1TS U859 ( .A0(n1390), .A1(n1389), .B0(n1388), .Y(n1393) );
CLKMX2X2TS U860 ( .A(P_Sgf[25]), .B(n1212), .S0(n1398), .Y(n263) );
XNOR2X1TS U861 ( .A(n1211), .B(n1210), .Y(n1212) );
NAND2X1TS U862 ( .A(n1209), .B(n1208), .Y(n1210) );
CLKMX2X2TS U863 ( .A(P_Sgf[24]), .B(n1203), .S0(n1398), .Y(n262) );
XNOR2X1TS U864 ( .A(n1390), .B(n1202), .Y(n1203) );
NAND2X1TS U865 ( .A(n1201), .B(n1204), .Y(n1202) );
XOR2X1TS U866 ( .A(n1356), .B(n1355), .Y(n1357) );
INVX2TS U867 ( .A(n1352), .Y(n1354) );
XOR2X1TS U868 ( .A(n1370), .B(n1369), .Y(n1371) );
NAND2X1TS U869 ( .A(n1368), .B(n1367), .Y(n1369) );
AOI21X1TS U870 ( .A0(n1390), .A1(n1365), .B0(n1364), .Y(n1370) );
XOR2X1TS U871 ( .A(n1333), .B(n418), .Y(n1334) );
INVX2TS U872 ( .A(n1330), .Y(n1332) );
XNOR2X1TS U873 ( .A(n1360), .B(n1359), .Y(n1361) );
NAND2X1TS U874 ( .A(n448), .B(n1358), .Y(n1360) );
CMPR42X2TS U875 ( .A(DP_OP_110J3_122_4535_n155), .B(
DP_OP_110J3_122_4535_n227), .C(DP_OP_110J3_122_4535_n518), .D(
DP_OP_110J3_122_4535_n152), .ICI(DP_OP_110J3_122_4535_n156), .S(
DP_OP_110J3_122_4535_n146), .ICO(DP_OP_110J3_122_4535_n144), .CO(
DP_OP_110J3_122_4535_n145) );
AO21X2TS U876 ( .A0(n392), .A1(n1343), .B0(n588), .Y(n391) );
NAND2X4TS U877 ( .A(n529), .B(n513), .Y(n514) );
CMPR32X4TS U878 ( .A(Op_MY[10]), .B(Op_MY[22]), .C(n743), .CO(n746), .S(n744) );
OR2X2TS U879 ( .A(n646), .B(n925), .Y(n393) );
CLKBUFX2TS U880 ( .A(Op_MY[7]), .Y(n1007) );
CLKBUFX2TS U881 ( .A(Op_MY[8]), .Y(n1008) );
XNOR2X2TS U882 ( .A(Op_MX[16]), .B(Op_MX[15]), .Y(n452) );
NOR4X1TS U883 ( .A(P_Sgf[9]), .B(P_Sgf[7]), .C(P_Sgf[8]), .D(P_Sgf[6]), .Y(
n1261) );
NOR4X1TS U884 ( .A(P_Sgf[13]), .B(P_Sgf[11]), .C(P_Sgf[12]), .D(P_Sgf[10]),
.Y(n1262) );
NOR4X1TS U885 ( .A(Op_MX[2]), .B(Op_MX[0]), .C(Op_MX[13]), .D(Op_MX[12]),
.Y(n1488) );
NOR2X1TS U886 ( .A(DP_OP_110J3_122_4535_n905), .B(n432), .Y(
DP_OP_110J3_122_4535_n592) );
XNOR2X2TS U887 ( .A(n738), .B(n789), .Y(n742) );
BUFX4TS U888 ( .A(n742), .Y(n783) );
BUFX4TS U889 ( .A(n790), .Y(n1074) );
BUFX4TS U890 ( .A(n805), .Y(n1079) );
XNOR2X2TS U891 ( .A(n801), .B(n814), .Y(n805) );
XNOR2X2TS U892 ( .A(n530), .B(n529), .Y(n533) );
BUFX4TS U893 ( .A(n536), .Y(n1056) );
AOI32X1TS U894 ( .A0(n1501), .A1(n1500), .A2(n1499), .B0(n1574), .B1(n1498),
.Y(n310) );
NOR4X1TS U895 ( .A(P_Sgf[5]), .B(P_Sgf[3]), .C(P_Sgf[4]), .D(P_Sgf[2]), .Y(
n1264) );
NOR4X1TS U896 ( .A(Op_MY[22]), .B(Op_MY[21]), .C(Op_MY[20]), .D(Op_MY[14]),
.Y(n1477) );
NOR4X1TS U897 ( .A(Op_MX[9]), .B(Op_MX[7]), .C(Op_MX[5]), .D(Op_MX[1]), .Y(
n1490) );
NOR4X1TS U898 ( .A(Op_MX[21]), .B(Op_MX[19]), .C(Op_MX[17]), .D(Op_MX[15]),
.Y(n1486) );
BUFX4TS U899 ( .A(n479), .Y(n1179) );
XNOR2X2TS U900 ( .A(Op_MX[3]), .B(Op_MX[4]), .Y(n479) );
OAI22X2TS U901 ( .A0(ack_FSM), .A1(n1233), .B0(beg_FSM), .B1(n1585), .Y(
n1470) );
NOR2X2TS U902 ( .A(n1560), .B(n1511), .Y(n1513) );
NOR3XLTS U903 ( .A(Op_MY[11]), .B(Op_MY[12]), .C(Op_MY[23]), .Y(n1479) );
NOR3XLTS U904 ( .A(Op_MX[11]), .B(Op_MX[3]), .C(Op_MX[24]), .Y(n1487) );
NOR4X1TS U905 ( .A(Op_MX[30]), .B(Op_MX[29]), .C(Op_MX[22]), .D(Op_MX[28]),
.Y(n1483) );
OAI211XLTS U906 ( .A0(Sgf_normalized_result[13]), .A1(n1523), .B0(n1539),
.C0(n1525), .Y(n1524) );
OAI211XLTS U907 ( .A0(Sgf_normalized_result[11]), .A1(n406), .B0(n1539),
.C0(n1521), .Y(n1520) );
OAI211XLTS U908 ( .A0(Sgf_normalized_result[9]), .A1(n407), .B0(n1539), .C0(
n1518), .Y(n1517) );
OAI211XLTS U909 ( .A0(Sgf_normalized_result[7]), .A1(n1513), .B0(n1539),
.C0(n1515), .Y(n1514) );
AND2X2TS U910 ( .A(n1277), .B(n1276), .Y(n420) );
BUFX4TS U911 ( .A(n1552), .Y(n1554) );
CLKBUFX2TS U912 ( .A(Op_MY[22]), .Y(n951) );
INVX4TS U913 ( .A(rst), .Y(n167) );
AO21X1TS U914 ( .A0(n412), .A1(n391), .B0(n590), .Y(n434) );
CLKBUFX2TS U915 ( .A(Op_MY[11]), .Y(n1016) );
BUFX4TS U916 ( .A(Op_MX[17]), .Y(n903) );
OR2X1TS U917 ( .A(n1340), .B(n1339), .Y(n443) );
CLKAND2X2TS U918 ( .A(n443), .B(n1341), .Y(n444) );
BUFX4TS U919 ( .A(Op_MX[19]), .Y(n954) );
INVX2TS U920 ( .A(Sgf_operation_EVEN1_Q_left[14]), .Y(n686) );
OR2X2TS U921 ( .A(n629), .B(n1143), .Y(n447) );
INVX2TS U922 ( .A(Sgf_operation_EVEN1_Q_left[15]), .Y(n689) );
INVX2TS U923 ( .A(Sgf_operation_EVEN1_Q_left[17]), .Y(n696) );
INVX2TS U924 ( .A(n921), .Y(n673) );
INVX2TS U925 ( .A(Sgf_operation_EVEN1_Q_left[19]), .Y(n683) );
INVX2TS U926 ( .A(n926), .Y(n701) );
OA21X4TS U927 ( .A0(n1423), .A1(n1426), .B0(n1424), .Y(n449) );
OA21X4TS U928 ( .A0(n1213), .A1(n449), .B0(n1214), .Y(n450) );
XNOR2X2TS U929 ( .A(n786), .B(n804), .Y(n790) );
XNOR2X1TS U930 ( .A(n810), .B(n535), .Y(n811) );
INVX2TS U931 ( .A(n772), .Y(n1038) );
OAI22X1TS U932 ( .A0(n788), .A1(n990), .B0(n1076), .B1(n1074), .Y(n991) );
OAI22X1TS U933 ( .A0(n1039), .A1(n1038), .B0(n1037), .B1(n1036), .Y(n1040)
);
NOR2X1TS U934 ( .A(DP_OP_110J3_122_4535_n905), .B(n397), .Y(n837) );
BUFX4TS U935 ( .A(n533), .Y(n1153) );
OAI22X1TS U936 ( .A0(n1003), .A1(n445), .B0(n1001), .B1(n955), .Y(n956) );
OAI22X1TS U937 ( .A0(n1003), .A1(n1002), .B0(n1001), .B1(n1000), .Y(n1004)
);
OAI22X1TS U938 ( .A0(n1118), .A1(n1022), .B0(n426), .B1(n1290), .Y(n1023) );
BUFX4TS U939 ( .A(n889), .Y(n1001) );
CLKBUFX3TS U940 ( .A(n762), .Y(n1086) );
ADDHXLTS U941 ( .A(n735), .B(n734), .CO(DP_OP_110J3_122_4535_n198), .S(
DP_OP_110J3_122_4535_n199) );
CMPR42X1TS U942 ( .A(DP_OP_110J3_122_4535_n265), .B(DP_OP_110J3_122_4535_n84), .C(DP_OP_110J3_122_4535_n76), .D(DP_OP_110J3_122_4535_n80), .ICI(
DP_OP_110J3_122_4535_n81), .S(DP_OP_110J3_122_4535_n73), .ICO(
DP_OP_110J3_122_4535_n71), .CO(DP_OP_110J3_122_4535_n72) );
BUFX4TS U943 ( .A(n452), .Y(n935) );
BUFX4TS U944 ( .A(n829), .Y(n1194) );
AOI21X2TS U945 ( .A0(n447), .A1(n1372), .B0(n630), .Y(n1363) );
OAI22X1TS U946 ( .A0(n1176), .A1(n1173), .B0(n1174), .B1(n1137), .Y(n1009)
);
BUFX4TS U947 ( .A(n834), .Y(n1192) );
INVX2TS U948 ( .A(n1297), .Y(n592) );
INVX2TS U949 ( .A(n1318), .Y(n602) );
NAND2X1TS U950 ( .A(n1354), .B(n1353), .Y(n1356) );
BUFX3TS U951 ( .A(n1257), .Y(n1467) );
NAND2X1TS U952 ( .A(n1332), .B(n1331), .Y(n1333) );
XOR2X1TS U953 ( .A(n1376), .B(n1375), .Y(n1377) );
XNOR2X1TS U954 ( .A(n1344), .B(n1343), .Y(n1345) );
XOR2X1TS U955 ( .A(n1409), .B(n1408), .Y(n1410) );
BUFX4TS U956 ( .A(n1295), .Y(n1398) );
INVX4TS U957 ( .A(n420), .Y(n1351) );
OAI21XLTS U958 ( .A0(Sgf_normalized_result[1]), .A1(Sgf_normalized_result[0]), .B0(Sgf_normalized_result[2]), .Y(n1504) );
OAI211XLTS U959 ( .A0(Sgf_normalized_result[15]), .A1(n1527), .B0(n1539),
.C0(n1529), .Y(n1528) );
INVX4TS U960 ( .A(n420), .Y(n1289) );
INVX4TS U961 ( .A(n420), .Y(n1291) );
XOR2X1TS U962 ( .A(Op_MX[16]), .B(Op_MX[17]), .Y(n451) );
NAND2X4TS U963 ( .A(n452), .B(n451), .Y(n937) );
XNOR2X1TS U964 ( .A(n903), .B(n409), .Y(n453) );
XNOR2X1TS U965 ( .A(n903), .B(Op_MY[13]), .Y(n906) );
OAI22X1TS U966 ( .A0(n937), .A1(n453), .B0(n935), .B1(n906), .Y(n460) );
XNOR2X2TS U967 ( .A(Op_MX[14]), .B(Op_MX[13]), .Y(n456) );
XOR2X1TS U968 ( .A(Op_MX[14]), .B(Op_MX[15]), .Y(n454) );
XNOR2X1TS U969 ( .A(n998), .B(Op_MY[14]), .Y(n457) );
XNOR2X1TS U970 ( .A(n998), .B(Op_MY[15]), .Y(n911) );
OAI22X1TS U971 ( .A0(n455), .A1(n457), .B0(n1121), .B1(n911), .Y(n459) );
XNOR2X1TS U972 ( .A(n1290), .B(Op_MY[15]), .Y(n466) );
XNOR2X1TS U973 ( .A(n1290), .B(Op_MY[16]), .Y(n461) );
OAI22X1TS U974 ( .A0(n1118), .A1(n466), .B0(n461), .B1(n426), .Y(n465) );
NOR2BX1TS U975 ( .AN(Op_MY[12]), .B(n935), .Y(n464) );
OAI22X1TS U976 ( .A0(n455), .A1(n467), .B0(n1121), .B1(n457), .Y(n463) );
CMPR32X2TS U977 ( .A(n460), .B(n459), .C(n458), .CO(n637), .S(n525) );
XNOR2X1TS U978 ( .A(n1290), .B(Op_MY[17]), .Y(n912) );
OAI22X1TS U979 ( .A0(n1118), .A1(n461), .B0(n912), .B1(n426), .Y(n995) );
OAI22X1TS U980 ( .A0(n937), .A1(n440), .B0(n935), .B1(n462), .Y(n994) );
CMPR32X2TS U981 ( .A(n465), .B(n464), .C(n463), .CO(n458), .S(n612) );
OAI22X1TS U982 ( .A0(n1118), .A1(n472), .B0(n466), .B1(n426), .Y(n470) );
XNOR2X1TS U983 ( .A(n998), .B(n409), .Y(n468) );
OAI22X1TS U984 ( .A0(n455), .A1(n468), .B0(n1121), .B1(n467), .Y(n469) );
ADDHX1TS U985 ( .A(n470), .B(n469), .CO(n611), .S(n616) );
OAI22X1TS U986 ( .A0(n455), .A1(n439), .B0(n1121), .B1(n471), .Y(n615) );
XNOR2X1TS U987 ( .A(Op_MX[13]), .B(Op_MY[13]), .Y(n474) );
OAI22X1TS U988 ( .A0(n1118), .A1(n474), .B0(n472), .B1(n426), .Y(n620) );
NOR2BX1TS U989 ( .AN(Op_MY[12]), .B(n1121), .Y(n619) );
NAND2X1TS U990 ( .A(n473), .B(n1118), .Y(n519) );
OAI22X1TS U991 ( .A0(n1118), .A1(Op_MY[12]), .B0(n474), .B1(n426), .Y(n518)
);
XNOR2X1TS U992 ( .A(Op_MX[9]), .B(Op_MX[10]), .Y(n477) );
XOR2X1TS U993 ( .A(Op_MX[10]), .B(Op_MX[11]), .Y(n475) );
XNOR2X1TS U994 ( .A(n1145), .B(n1016), .Y(n844) );
OAI22X1TS U995 ( .A0(n476), .A1(n844), .B0(n1147), .B1(
DP_OP_110J3_122_4535_n905), .Y(n503) );
NOR2X1TS U996 ( .A(DP_OP_110J3_122_4535_n905), .B(n437), .Y(n506) );
INVX2TS U997 ( .A(n506), .Y(n502) );
XOR2X1TS U998 ( .A(Op_MX[5]), .B(Op_MX[4]), .Y(n478) );
NAND2X4TS U999 ( .A(n479), .B(n478), .Y(n1181) );
XNOR2X1TS U1000 ( .A(n1164), .B(n1169), .Y(n480) );
XNOR2X1TS U1001 ( .A(n1164), .B(Op_MY[1]), .Y(n1165) );
OAI22X1TS U1002 ( .A0(n1181), .A1(n480), .B0(n1179), .B1(n1165), .Y(n487) );
XNOR2X2TS U1003 ( .A(Op_MX[1]), .B(Op_MX[2]), .Y(n482) );
XOR2X1TS U1004 ( .A(Op_MX[3]), .B(Op_MX[2]), .Y(n481) );
XNOR2X1TS U1005 ( .A(n1155), .B(Op_MY[2]), .Y(n484) );
XNOR2X1TS U1006 ( .A(n1155), .B(Op_MY[3]), .Y(n1156) );
OAI22X1TS U1007 ( .A0(n1176), .A1(n484), .B0(n1174), .B1(n1156), .Y(n486) );
XNOR2X1TS U1008 ( .A(n1278), .B(Op_MY[3]), .Y(n493) );
XNOR2X1TS U1009 ( .A(n1278), .B(Op_MY[4]), .Y(n488) );
OAI22X1TS U1010 ( .A0(n483), .A1(n493), .B0(n488), .B1(n435), .Y(n492) );
NOR2BX1TS U1011 ( .AN(n1169), .B(n1179), .Y(n491) );
XNOR2X1TS U1012 ( .A(n1155), .B(Op_MY[1]), .Y(n494) );
OAI22X1TS U1013 ( .A0(n1176), .A1(n494), .B0(n1174), .B1(n484), .Y(n490) );
CMPR32X2TS U1014 ( .A(n487), .B(n486), .C(n485), .CO(n931), .S(n920) );
XNOR2X1TS U1015 ( .A(n1278), .B(Op_MY[5]), .Y(n1172) );
OAI22X1TS U1016 ( .A0(n483), .A1(n488), .B0(n1172), .B1(n435), .Y(n1044) );
OAI22X1TS U1017 ( .A0(n1181), .A1(n442), .B0(n1179), .B1(n489), .Y(n1043) );
CMPR32X2TS U1018 ( .A(n492), .B(n491), .C(n490), .CO(n485), .S(n1128) );
OAI22X1TS U1019 ( .A0(n483), .A1(n499), .B0(n493), .B1(n435), .Y(n497) );
XNOR2X1TS U1020 ( .A(n1155), .B(n1169), .Y(n495) );
OAI22X1TS U1021 ( .A0(n1176), .A1(n495), .B0(n1174), .B1(n494), .Y(n496) );
ADDHX1TS U1022 ( .A(n497), .B(n496), .CO(n1127), .S(n1106) );
OAI22X1TS U1023 ( .A0(n1176), .A1(n424), .B0(n1174), .B1(n498), .Y(n1105) );
XNOR2X1TS U1024 ( .A(Op_MX[1]), .B(Op_MY[1]), .Y(n501) );
OAI22X1TS U1025 ( .A0(n483), .A1(n501), .B0(n499), .B1(n435), .Y(n1103) );
NOR2BX1TS U1026 ( .AN(n1169), .B(n1174), .Y(n1102) );
NAND2X1TS U1027 ( .A(n500), .B(n483), .Y(n517) );
OAI22X1TS U1028 ( .A0(n483), .A1(n1169), .B0(n501), .B1(n435), .Y(n516) );
CMPR32X2TS U1029 ( .A(n503), .B(n502), .C(DP_OP_110J3_122_4535_n560), .CO(
n508), .S(n558) );
NOR2X1TS U1030 ( .A(DP_OP_110J3_122_4535_n905), .B(n438), .Y(n505) );
AO21XLTS U1031 ( .A0(n476), .A1(n1147), .B0(DP_OP_110J3_122_4535_n905), .Y(
n504) );
XOR2X1TS U1032 ( .A(n508), .B(n507), .Y(n509) );
INVX2TS U1033 ( .A(n606), .Y(n550) );
XNOR2X1TS U1034 ( .A(n963), .B(n961), .Y(n1113) );
ADDHX1TS U1035 ( .A(Op_MX[0]), .B(Op_MX[12]), .CO(n527), .S(n511) );
INVX4TS U1036 ( .A(n511), .Y(n513) );
XNOR2X1TS U1037 ( .A(n821), .B(n961), .Y(n1090) );
OAI22X1TS U1038 ( .A0(n1113), .A1(n513), .B0(n1090), .B1(n514), .Y(n526) );
ADDHX4TS U1039 ( .A(Op_MY[12]), .B(Op_MY[0]), .CO(n520), .S(n762) );
NAND2BXLTS U1040 ( .AN(n1086), .B(n961), .Y(n515) );
NAND2X1TS U1041 ( .A(n515), .B(n514), .Y(n582) );
NOR2BX2TS U1042 ( .AN(n409), .B(n426), .Y(n623) );
INVX2TS U1043 ( .A(n623), .Y(n586) );
NOR2BX1TS U1044 ( .AN(n1169), .B(n435), .Y(n1335) );
INVX2TS U1045 ( .A(n1335), .Y(n585) );
NOR2BX1TS U1046 ( .AN(n1086), .B(n513), .Y(n584) );
INVX2TS U1047 ( .A(n1336), .Y(n522) );
CMPR32X2TS U1048 ( .A(Op_MY[1]), .B(Op_MY[13]), .C(n520), .CO(n512), .S(n820) );
XNOR2X1TS U1049 ( .A(n961), .B(n820), .Y(n1089) );
OAI22X1TS U1050 ( .A0(n514), .A1(n1086), .B0(n1089), .B1(n513), .Y(n521) );
CMPR32X2TS U1051 ( .A(n522), .B(n1150), .C(n521), .CO(n577), .S(n580) );
INVX2TS U1052 ( .A(n631), .Y(n1049) );
ADDHXLTS U1053 ( .A(DP_OP_110J3_122_4535_n210), .B(n526), .CO(n1047), .S(
n575) );
XOR2X1TS U1054 ( .A(n535), .B(n530), .Y(n531) );
XNOR2X1TS U1055 ( .A(n1085), .B(n820), .Y(n1072) );
XNOR2X1TS U1056 ( .A(n1085), .B(n821), .Y(n731) );
OAI22X1TS U1057 ( .A0(n532), .A1(n1072), .B0(n731), .B1(n1153), .Y(n1046) );
ADDFHX2TS U1058 ( .A(Op_MX[3]), .B(Op_MX[15]), .CI(n534), .CO(n537), .S(n535) );
CLKBUFX2TS U1059 ( .A(n811), .Y(n536) );
NOR2BX1TS U1060 ( .AN(n1086), .B(n536), .Y(n1045) );
OR2X2TS U1061 ( .A(n538), .B(Op_MX[11]), .Y(n539) );
XNOR2X2TS U1062 ( .A(n741), .B(n539), .Y(n745) );
CMPR32X2TS U1063 ( .A(Op_MY[3]), .B(Op_MY[15]), .C(n540), .CO(n733), .S(n963) );
INVX2TS U1064 ( .A(n541), .Y(n750) );
XOR2X1TS U1065 ( .A(DP_OP_110J3_122_4535_n32), .B(n542), .Y(n543) );
ADDFHX4TS U1066 ( .A(DP_OP_110J3_122_4535_n37), .B(n550), .CI(n549), .CO(
n547), .S(n649) );
CMPR32X2TS U1067 ( .A(DP_OP_110J3_122_4535_n1039), .B(
DP_OP_110J3_122_4535_n1043), .C(n555), .CO(n642), .S(n927) );
CMPR32X2TS U1068 ( .A(n556), .B(DP_OP_110J3_122_4535_n146), .C(
DP_OP_110J3_122_4535_n143), .CO(n622), .S(n605) );
CMPR32X2TS U1069 ( .A(DP_OP_110J3_122_4535_n163), .B(
DP_OP_110J3_122_4535_n166), .C(n561), .CO(n559), .S(n603) );
CMPR32X2TS U1070 ( .A(DP_OP_110J3_122_4535_n181), .B(
DP_OP_110J3_122_4535_n184), .C(n565), .CO(n563), .S(n598) );
CMPR32X2TS U1071 ( .A(DP_OP_110J3_122_4535_n582), .B(
DP_OP_110J3_122_4535_n587), .C(n568), .CO(n566), .S(n1190) );
CMPR32X2TS U1072 ( .A(DP_OP_110J3_122_4535_n202), .B(
DP_OP_110J3_122_4535_n206), .C(n572), .CO(n570), .S(n593) );
CMPR32X2TS U1073 ( .A(DP_OP_110J3_122_4535_n207), .B(n575), .C(n574), .CO(
n572), .S(n591) );
CMPR32X2TS U1074 ( .A(n578), .B(n577), .C(DP_OP_110J3_122_4535_n212), .CO(
n574), .S(n589) );
CMPR32X2TS U1075 ( .A(n582), .B(n581), .C(n580), .CO(n578), .S(n587) );
CMPR32X2TS U1076 ( .A(n586), .B(n585), .C(n584), .CO(n581), .S(n1339) );
INVX2TS U1077 ( .A(n1341), .Y(n1343) );
NAND2X2TS U1078 ( .A(n1184), .B(n587), .Y(n1342) );
INVX2TS U1079 ( .A(n1342), .Y(n588) );
INVX2TS U1080 ( .A(n1293), .Y(n590) );
CMPR32X2TS U1081 ( .A(n612), .B(n611), .C(n610), .CO(n523), .S(n1143) );
CMPR32X2TS U1082 ( .A(DP_OP_110J3_122_4535_n99), .B(
DP_OP_110J3_122_4535_n109), .C(n613), .CO(n609), .S(n628) );
CMPR32X2TS U1083 ( .A(n616), .B(n615), .C(n614), .CO(n610), .S(n1115) );
CMPR32X2TS U1084 ( .A(n620), .B(n619), .C(n618), .CO(n614), .S(n1098) );
AOI21X4TS U1085 ( .A0(n1390), .A1(n634), .B0(n633), .Y(n1355) );
CMPR32X2TS U1086 ( .A(DP_OP_110J3_122_4535_n1044), .B(n637), .C(n636), .CO(
n555), .S(n924) );
AOI21X4TS U1087 ( .A0(n448), .A1(n1359), .B0(n640), .Y(n1408) );
CMPR32X2TS U1088 ( .A(DP_OP_110J3_122_4535_n54), .B(DP_OP_110J3_122_4535_n61), .C(n641), .CO(n644), .S(n643) );
CMPR32X2TS U1089 ( .A(DP_OP_110J3_122_4535_n48), .B(DP_OP_110J3_122_4535_n53), .C(n644), .CO(n552), .S(n646) );
NOR3X2TS U1090 ( .A(n1557), .B(FS_Module_state_reg[3]), .C(
FS_Module_state_reg[0]), .Y(n1236) );
INVX2TS U1091 ( .A(n1236), .Y(n656) );
NAND2X1TS U1092 ( .A(FS_Module_state_reg[3]), .B(n1557), .Y(n1199) );
NOR2X2TS U1093 ( .A(FS_Module_state_reg[0]), .B(n1199), .Y(n1273) );
AOI21X4TS U1094 ( .A0(n660), .A1(n1225), .B0(n659), .Y(n662) );
AOI21X4TS U1095 ( .A0(n667), .A1(n1225), .B0(n666), .Y(n669) );
CMPR32X2TS U1096 ( .A(DP_OP_110J3_122_4535_n964), .B(
DP_OP_110J3_122_4535_n969), .C(n668), .CO(n671), .S(
Sgf_operation_EVEN1_Q_left[17]) );
AOI21X4TS U1097 ( .A0(n675), .A1(n1225), .B0(n674), .Y(n677) );
CMPR32X2TS U1098 ( .A(DP_OP_110J3_122_4535_n956), .B(
DP_OP_110J3_122_4535_n952), .C(n676), .CO(n699), .S(
Sgf_operation_EVEN1_Q_left[19]) );
AOI21X4TS U1099 ( .A0(n682), .A1(n1225), .B0(n681), .Y(n684) );
AOI21X4TS U1100 ( .A0(n688), .A1(n1225), .B0(n687), .Y(n690) );
AOI21X4TS U1101 ( .A0(n695), .A1(n1225), .B0(n694), .Y(n697) );
AOI21X4TS U1102 ( .A0(n704), .A1(n1225), .B0(n703), .Y(n705) );
CMPR32X2TS U1103 ( .A(n708), .B(n422), .C(DP_OP_110J3_122_4535_n942), .CO(
n713), .S(n717) );
CLKAND2X2TS U1104 ( .A(n1020), .B(n1021), .Y(n711) );
XNOR2X1TS U1105 ( .A(n711), .B(n951), .Y(n712) );
XOR2X1TS U1106 ( .A(n713), .B(n712), .Y(n714) );
CMPR32X2TS U1107 ( .A(DP_OP_110J3_122_4535_n943), .B(n717), .C(n716), .CO(
n715), .S(n916) );
AOI21X4TS U1108 ( .A0(n720), .A1(n1225), .B0(n719), .Y(n722) );
AOI21X4TS U1109 ( .A0(n727), .A1(n1225), .B0(n726), .Y(n729) );
XNOR2X1TS U1110 ( .A(n1085), .B(n963), .Y(n825) );
OAI22X1TS U1111 ( .A0(n532), .A1(n731), .B0(n825), .B1(n1153), .Y(n735) );
XNOR2X1TS U1112 ( .A(n966), .B(n961), .Y(n1157) );
ADDFHX2TS U1113 ( .A(Op_MY[4]), .B(Op_MY[16]), .CI(n733), .CO(n732), .S(
n1051) );
XNOR2X1TS U1114 ( .A(n1051), .B(n961), .Y(n1114) );
OAI22X1TS U1115 ( .A0(n1157), .A1(n513), .B0(n1114), .B1(n514), .Y(n734) );
CMPR32X2TS U1116 ( .A(Op_MX[22]), .B(Op_MX[10]), .C(n736), .CO(n538), .S(
n738) );
XOR2X1TS U1117 ( .A(n741), .B(n738), .Y(n739) );
CMPR32X2TS U1118 ( .A(Op_MX[9]), .B(Op_MX[21]), .C(n737), .CO(n736), .S(n789) );
XNOR2X1TS U1119 ( .A(n780), .B(n541), .Y(n767) );
INVX2TS U1120 ( .A(n780), .Y(n766) );
OAI22X1TS U1121 ( .A0(n740), .A1(n767), .B0(n766), .B1(n783), .Y(n749) );
INVX2TS U1122 ( .A(n744), .Y(n753) );
XNOR2X1TS U1123 ( .A(n746), .B(Op_MY[11]), .Y(n747) );
INVX2TS U1124 ( .A(n1026), .Y(n751) );
OAI22X1TS U1125 ( .A0(n1039), .A1(n753), .B0(n1037), .B1(n751), .Y(n748) );
CMPR32X2TS U1126 ( .A(n749), .B(n748), .C(DP_OP_110J3_122_4535_n43), .CO(
DP_OP_110J3_122_4535_n38), .S(DP_OP_110J3_122_4535_n39) );
OAI22X1TS U1127 ( .A0(n1039), .A1(n751), .B0(n1037), .B1(n750), .Y(
DP_OP_110J3_122_4535_n246) );
CMPR32X2TS U1128 ( .A(Op_MY[9]), .B(Op_MY[21]), .C(n752), .CO(n743), .S(n969) );
INVX2TS U1129 ( .A(n969), .Y(n755) );
OAI22X1TS U1130 ( .A0(n1039), .A1(n755), .B0(n1037), .B1(n753), .Y(
DP_OP_110J3_122_4535_n248) );
CMPR32X2TS U1131 ( .A(Op_MY[8]), .B(Op_MY[20]), .C(n754), .CO(n752), .S(n988) );
INVX2TS U1132 ( .A(n988), .Y(n1036) );
OAI22X1TS U1133 ( .A0(n1039), .A1(n1036), .B0(n1037), .B1(n755), .Y(
DP_OP_110J3_122_4535_n249) );
INVX2TS U1134 ( .A(n966), .Y(n758) );
INVX2TS U1135 ( .A(n757), .Y(n1029) );
OAI22X1TS U1136 ( .A0(n1039), .A1(n758), .B0(n1037), .B1(n1029), .Y(
DP_OP_110J3_122_4535_n252) );
INVX2TS U1137 ( .A(n1051), .Y(n759) );
OAI22X1TS U1138 ( .A0(n1039), .A1(n759), .B0(n1037), .B1(n758), .Y(
DP_OP_110J3_122_4535_n253) );
INVX2TS U1139 ( .A(n963), .Y(n760) );
OAI22X1TS U1140 ( .A0(n1039), .A1(n760), .B0(n1037), .B1(n759), .Y(
DP_OP_110J3_122_4535_n254) );
INVX2TS U1141 ( .A(n821), .Y(n761) );
OAI22X1TS U1142 ( .A0(n1039), .A1(n761), .B0(n1037), .B1(n760), .Y(
DP_OP_110J3_122_4535_n255) );
INVX2TS U1143 ( .A(n820), .Y(n763) );
OAI22X1TS U1144 ( .A0(n1039), .A1(n763), .B0(n1037), .B1(n761), .Y(
DP_OP_110J3_122_4535_n256) );
INVX2TS U1145 ( .A(n762), .Y(n764) );
OAI22X1TS U1146 ( .A0(n1039), .A1(n764), .B0(n1037), .B1(n763), .Y(
DP_OP_110J3_122_4535_n257) );
NOR2BX1TS U1147 ( .AN(n762), .B(n1037), .Y(DP_OP_110J3_122_4535_n258) );
OAI22X1TS U1148 ( .A0(n740), .A1(n766), .B0(n765), .B1(n783), .Y(
DP_OP_110J3_122_4535_n239) );
XNOR2X1TS U1149 ( .A(n780), .B(n1026), .Y(n768) );
OAI22X1TS U1150 ( .A0(n740), .A1(n768), .B0(n767), .B1(n783), .Y(
DP_OP_110J3_122_4535_n261) );
XNOR2X1TS U1151 ( .A(n780), .B(n744), .Y(n769) );
OAI22X1TS U1152 ( .A0(n740), .A1(n769), .B0(n768), .B1(n783), .Y(
DP_OP_110J3_122_4535_n262) );
XNOR2X1TS U1153 ( .A(n780), .B(n969), .Y(n770) );
OAI22X1TS U1154 ( .A0(n740), .A1(n770), .B0(n769), .B1(n783), .Y(
DP_OP_110J3_122_4535_n263) );
XNOR2X1TS U1155 ( .A(n780), .B(n988), .Y(n773) );
OAI22X1TS U1156 ( .A0(n740), .A1(n773), .B0(n770), .B1(n783), .Y(
DP_OP_110J3_122_4535_n264) );
XNOR2X1TS U1157 ( .A(n780), .B(n772), .Y(n774) );
OAI22X1TS U1158 ( .A0(n740), .A1(n774), .B0(n773), .B1(n783), .Y(
DP_OP_110J3_122_4535_n265) );
XNOR2X1TS U1159 ( .A(n780), .B(n757), .Y(n775) );
OAI22X1TS U1160 ( .A0(n740), .A1(n775), .B0(n774), .B1(n783), .Y(
DP_OP_110J3_122_4535_n266) );
XNOR2X1TS U1161 ( .A(n780), .B(n966), .Y(n776) );
OAI22X1TS U1162 ( .A0(n740), .A1(n776), .B0(n775), .B1(n783), .Y(
DP_OP_110J3_122_4535_n267) );
XNOR2X1TS U1163 ( .A(n780), .B(n1051), .Y(n777) );
OAI22X1TS U1164 ( .A0(n740), .A1(n777), .B0(n776), .B1(n783), .Y(
DP_OP_110J3_122_4535_n268) );
XNOR2X1TS U1165 ( .A(n780), .B(n963), .Y(n778) );
OAI22X1TS U1166 ( .A0(n740), .A1(n778), .B0(n777), .B1(n783), .Y(
DP_OP_110J3_122_4535_n269) );
XNOR2X1TS U1167 ( .A(n780), .B(n821), .Y(n779) );
OAI22X1TS U1168 ( .A0(n740), .A1(n779), .B0(n778), .B1(n783), .Y(
DP_OP_110J3_122_4535_n270) );
XNOR2X1TS U1169 ( .A(n780), .B(n820), .Y(n781) );
OAI22X1TS U1170 ( .A0(n740), .A1(n781), .B0(n779), .B1(n783), .Y(
DP_OP_110J3_122_4535_n271) );
XNOR2X1TS U1171 ( .A(n780), .B(n762), .Y(n782) );
OAI22X1TS U1172 ( .A0(n740), .A1(n782), .B0(n781), .B1(n783), .Y(
DP_OP_110J3_122_4535_n272) );
NOR2BX1TS U1173 ( .AN(n762), .B(n742), .Y(DP_OP_110J3_122_4535_n273) );
XOR2X1TS U1174 ( .A(n789), .B(n786), .Y(n787) );
CMPR32X2TS U1175 ( .A(Op_MX[7]), .B(Op_MX[19]), .C(n785), .CO(n784), .S(n804) );
INVX2TS U1176 ( .A(n1025), .Y(n792) );
OAI22X1TS U1177 ( .A0(n788), .A1(n792), .B0(n791), .B1(n1074), .Y(
DP_OP_110J3_122_4535_n240) );
XNOR2X1TS U1178 ( .A(n541), .B(n1025), .Y(n1033) );
OAI22X1TS U1179 ( .A0(n1033), .A1(n788), .B0(n792), .B1(n1074), .Y(
DP_OP_110J3_122_4535_n275) );
XNOR2X1TS U1180 ( .A(n744), .B(n1025), .Y(n1027) );
XNOR2X1TS U1181 ( .A(n1025), .B(n969), .Y(n793) );
OAI22X1TS U1182 ( .A0(n1027), .A1(n1074), .B0(n788), .B1(n793), .Y(
DP_OP_110J3_122_4535_n278) );
XNOR2X1TS U1183 ( .A(n1025), .B(n988), .Y(n968) );
OAI22X1TS U1184 ( .A0(n788), .A1(n968), .B0(n793), .B1(n1074), .Y(
DP_OP_110J3_122_4535_n279) );
XNOR2X1TS U1185 ( .A(n1025), .B(n1051), .Y(n794) );
XNOR2X1TS U1186 ( .A(n1025), .B(n966), .Y(n990) );
OAI22X1TS U1187 ( .A0(n788), .A1(n794), .B0(n990), .B1(n1074), .Y(
DP_OP_110J3_122_4535_n283) );
XNOR2X1TS U1188 ( .A(n1025), .B(n963), .Y(n795) );
OAI22X1TS U1189 ( .A0(n788), .A1(n795), .B0(n794), .B1(n1074), .Y(
DP_OP_110J3_122_4535_n284) );
XNOR2X1TS U1190 ( .A(n1025), .B(n821), .Y(n796) );
OAI22X1TS U1191 ( .A0(n788), .A1(n796), .B0(n795), .B1(n1074), .Y(
DP_OP_110J3_122_4535_n285) );
XNOR2X1TS U1192 ( .A(n1025), .B(n820), .Y(n797) );
OAI22X1TS U1193 ( .A0(n788), .A1(n797), .B0(n796), .B1(n1074), .Y(
DP_OP_110J3_122_4535_n286) );
XNOR2X1TS U1194 ( .A(n1025), .B(n762), .Y(n798) );
OAI22X1TS U1195 ( .A0(n788), .A1(n798), .B0(n797), .B1(n1074), .Y(
DP_OP_110J3_122_4535_n287) );
NOR2BX1TS U1196 ( .AN(n762), .B(n790), .Y(DP_OP_110J3_122_4535_n288) );
XOR2X1TS U1197 ( .A(n804), .B(n801), .Y(n802) );
ADDFHX2TS U1198 ( .A(Op_MX[5]), .B(Op_MX[17]), .CI(n800), .CO(n799), .S(n814) );
OAI22X1TS U1199 ( .A0(n803), .A1(n1035), .B0(n806), .B1(n1079), .Y(
DP_OP_110J3_122_4535_n241) );
XNOR2X1TS U1200 ( .A(n1026), .B(n987), .Y(n807) );
XNOR2X1TS U1201 ( .A(n541), .B(n987), .Y(n1028) );
OAI22X1TS U1202 ( .A0(n807), .A1(n803), .B0(n1028), .B1(n1079), .Y(
DP_OP_110J3_122_4535_n291) );
XNOR2X1TS U1203 ( .A(n744), .B(n987), .Y(n970) );
OAI22X1TS U1204 ( .A0(n807), .A1(n1079), .B0(n970), .B1(n803), .Y(
DP_OP_110J3_122_4535_n292) );
XNOR2X1TS U1205 ( .A(n987), .B(n963), .Y(n1062) );
XNOR2X1TS U1206 ( .A(n987), .B(n1051), .Y(n967) );
OAI22X1TS U1207 ( .A0(n803), .A1(n1062), .B0(n967), .B1(n1079), .Y(
DP_OP_110J3_122_4535_n299) );
XNOR2X1TS U1208 ( .A(n987), .B(n820), .Y(n808) );
XNOR2X1TS U1209 ( .A(n987), .B(n821), .Y(n1063) );
OAI22X1TS U1210 ( .A0(n803), .A1(n808), .B0(n1063), .B1(n1079), .Y(
DP_OP_110J3_122_4535_n301) );
XNOR2X1TS U1211 ( .A(n987), .B(n762), .Y(n809) );
OAI22X1TS U1212 ( .A0(n803), .A1(n809), .B0(n808), .B1(n1079), .Y(
DP_OP_110J3_122_4535_n302) );
NOR2BX1TS U1213 ( .AN(n762), .B(n805), .Y(DP_OP_110J3_122_4535_n303) );
XOR2X1TS U1214 ( .A(n814), .B(n810), .Y(n812) );
INVX2TS U1215 ( .A(n1052), .Y(n816) );
OAI22X1TS U1216 ( .A0(n813), .A1(n816), .B0(n815), .B1(n1056), .Y(
DP_OP_110J3_122_4535_n242) );
XNOR2X1TS U1217 ( .A(n541), .B(n1052), .Y(n817) );
OAI22X1TS U1218 ( .A0(n817), .A1(n813), .B0(n816), .B1(n1056), .Y(
DP_OP_110J3_122_4535_n305) );
XNOR2X1TS U1219 ( .A(n1026), .B(n1052), .Y(n818) );
OAI22X1TS U1220 ( .A0(n818), .A1(n813), .B0(n817), .B1(n1056), .Y(
DP_OP_110J3_122_4535_n306) );
XNOR2X1TS U1221 ( .A(n744), .B(n1052), .Y(n819) );
OAI22X1TS U1222 ( .A0(n818), .A1(n1056), .B0(n819), .B1(n813), .Y(
DP_OP_110J3_122_4535_n307) );
XNOR2X1TS U1223 ( .A(n969), .B(n1052), .Y(n979) );
OAI22X1TS U1224 ( .A0(n819), .A1(n1056), .B0(n979), .B1(n813), .Y(
DP_OP_110J3_122_4535_n308) );
XNOR2X1TS U1225 ( .A(n757), .B(n1052), .Y(n965) );
XNOR2X1TS U1226 ( .A(n1052), .B(n966), .Y(n1057) );
OAI22X1TS U1227 ( .A0(n965), .A1(n1056), .B0(n813), .B1(n1057), .Y(
DP_OP_110J3_122_4535_n312) );
XNOR2X1TS U1228 ( .A(n1052), .B(n820), .Y(n822) );
XNOR2X1TS U1229 ( .A(n1052), .B(n821), .Y(n964) );
OAI22X1TS U1230 ( .A0(n813), .A1(n822), .B0(n964), .B1(n1056), .Y(
DP_OP_110J3_122_4535_n316) );
XNOR2X1TS U1231 ( .A(n1052), .B(n1086), .Y(n823) );
OAI22X1TS U1232 ( .A0(n813), .A1(n823), .B0(n822), .B1(n1056), .Y(
DP_OP_110J3_122_4535_n317) );
XNOR2X1TS U1233 ( .A(n1026), .B(n1085), .Y(n824) );
XNOR2X1TS U1234 ( .A(n541), .B(n1085), .Y(n1081) );
OAI22X1TS U1235 ( .A0(n824), .A1(n532), .B0(n1081), .B1(n1153), .Y(
DP_OP_110J3_122_4535_n321) );
XNOR2X1TS U1236 ( .A(n744), .B(n1085), .Y(n914) );
OAI22X1TS U1237 ( .A0(n824), .A1(n1153), .B0(n914), .B1(n532), .Y(
DP_OP_110J3_122_4535_n322) );
XNOR2X1TS U1238 ( .A(n988), .B(n1085), .Y(n1152) );
XNOR2X1TS U1239 ( .A(n772), .B(n1085), .Y(n1061) );
OAI22X1TS U1240 ( .A0(n1152), .A1(n1153), .B0(n1061), .B1(n532), .Y(
DP_OP_110J3_122_4535_n325) );
XNOR2X1TS U1241 ( .A(n1051), .B(n1085), .Y(n962) );
OAI22X1TS U1242 ( .A0(n962), .A1(n1153), .B0(n532), .B1(n825), .Y(
DP_OP_110J3_122_4535_n329) );
NOR2BX1TS U1243 ( .AN(n1086), .B(n1153), .Y(DP_OP_110J3_122_4535_n333) );
XNOR2X1TS U1244 ( .A(n1026), .B(n961), .Y(n826) );
XNOR2X1TS U1245 ( .A(n541), .B(n961), .Y(n913) );
OAI22X1TS U1246 ( .A0(n826), .A1(n514), .B0(n913), .B1(n513), .Y(
DP_OP_110J3_122_4535_n336) );
XNOR2X1TS U1247 ( .A(n744), .B(n961), .Y(n1163) );
OAI22X1TS U1248 ( .A0(n826), .A1(n513), .B0(n1163), .B1(n514), .Y(
DP_OP_110J3_122_4535_n337) );
XNOR2X1TS U1249 ( .A(n969), .B(n961), .Y(n1162) );
XNOR2X1TS U1250 ( .A(n988), .B(n961), .Y(n1161) );
OAI22X1TS U1251 ( .A0(n1162), .A1(n513), .B0(n1161), .B1(n514), .Y(
DP_OP_110J3_122_4535_n339) );
XOR2X1TS U1252 ( .A(Op_MX[9]), .B(Op_MX[8]), .Y(n827) );
XNOR2X1TS U1253 ( .A(n1133), .B(Op_MY[10]), .Y(n940) );
XNOR2X1TS U1254 ( .A(n1133), .B(n1016), .Y(n853) );
OAI22X1TS U1255 ( .A0(n828), .A1(n940), .B0(n1194), .B1(n853), .Y(n830) );
CMPR32X2TS U1256 ( .A(n831), .B(n942), .C(n830), .CO(
DP_OP_110J3_122_4535_n571), .S(DP_OP_110J3_122_4535_n572) );
XOR2X1TS U1257 ( .A(Op_MX[7]), .B(Op_MX[6]), .Y(n832) );
XNOR2X1TS U1258 ( .A(n1166), .B(n1008), .Y(n838) );
XNOR2X1TS U1259 ( .A(n1166), .B(Op_MY[9]), .Y(n862) );
OAI22X1TS U1260 ( .A0(n833), .A1(n838), .B0(n1192), .B1(n862), .Y(n835) );
CMPR32X2TS U1261 ( .A(n836), .B(n837), .C(n835), .CO(
DP_OP_110J3_122_4535_n600), .S(DP_OP_110J3_122_4535_n601) );
XNOR2X1TS U1262 ( .A(n1166), .B(n1007), .Y(n863) );
OAI22X1TS U1263 ( .A0(n833), .A1(n863), .B0(n1192), .B1(n838), .Y(n839) );
CMPR32X2TS U1264 ( .A(n842), .B(n840), .C(n839), .CO(
DP_OP_110J3_122_4535_n608), .S(DP_OP_110J3_122_4535_n609) );
XNOR2X1TS U1265 ( .A(n1133), .B(Op_MY[4]), .Y(n858) );
XNOR2X1TS U1266 ( .A(n1133), .B(Op_MY[5]), .Y(n857) );
OAI22X1TS U1267 ( .A0(n828), .A1(n858), .B0(n1194), .B1(n857), .Y(n843) );
XNOR2X1TS U1268 ( .A(n1164), .B(n1008), .Y(n870) );
XNOR2X1TS U1269 ( .A(n1164), .B(Op_MY[9]), .Y(n869) );
OAI22X1TS U1270 ( .A0(n1181), .A1(n870), .B0(n1179), .B1(n869), .Y(n841) );
CMPR32X2TS U1271 ( .A(n843), .B(n842), .C(n841), .CO(
DP_OP_110J3_122_4535_n618), .S(DP_OP_110J3_122_4535_n619) );
XNOR2X1TS U1272 ( .A(n1145), .B(Op_MY[10]), .Y(n845) );
OAI22X1TS U1273 ( .A0(n476), .A1(n845), .B0(n1147), .B1(n844), .Y(
DP_OP_110J3_122_4535_n686) );
XNOR2X1TS U1274 ( .A(n1145), .B(Op_MY[9]), .Y(n846) );
OAI22X1TS U1275 ( .A0(n476), .A1(n846), .B0(n1147), .B1(n845), .Y(
DP_OP_110J3_122_4535_n687) );
XNOR2X1TS U1276 ( .A(n1145), .B(n1008), .Y(n847) );
OAI22X1TS U1277 ( .A0(n476), .A1(n847), .B0(n1147), .B1(n846), .Y(
DP_OP_110J3_122_4535_n688) );
XNOR2X1TS U1278 ( .A(n1145), .B(n1007), .Y(n848) );
OAI22X1TS U1279 ( .A0(n476), .A1(n848), .B0(n1147), .B1(n847), .Y(
DP_OP_110J3_122_4535_n689) );
XNOR2X1TS U1280 ( .A(n1145), .B(Op_MY[6]), .Y(n849) );
OAI22X1TS U1281 ( .A0(n476), .A1(n849), .B0(n1147), .B1(n848), .Y(
DP_OP_110J3_122_4535_n690) );
XNOR2X1TS U1282 ( .A(n1145), .B(Op_MY[5]), .Y(n850) );
OAI22X1TS U1283 ( .A0(n476), .A1(n850), .B0(n1147), .B1(n849), .Y(
DP_OP_110J3_122_4535_n691) );
XNOR2X1TS U1284 ( .A(n1145), .B(Op_MY[4]), .Y(n851) );
OAI22X1TS U1285 ( .A0(n476), .A1(n851), .B0(n1147), .B1(n850), .Y(
DP_OP_110J3_122_4535_n692) );
XNOR2X1TS U1286 ( .A(n1145), .B(Op_MY[3]), .Y(n852) );
OAI22X1TS U1287 ( .A0(n476), .A1(n852), .B0(n1147), .B1(n851), .Y(
DP_OP_110J3_122_4535_n693) );
XNOR2X1TS U1288 ( .A(n1145), .B(Op_MY[2]), .Y(n1144) );
OAI22X1TS U1289 ( .A0(n476), .A1(n1144), .B0(n1147), .B1(n852), .Y(
DP_OP_110J3_122_4535_n694) );
OAI22X1TS U1290 ( .A0(n828), .A1(n853), .B0(n1194), .B1(n436), .Y(
DP_OP_110J3_122_4535_n699) );
XNOR2X1TS U1291 ( .A(n1133), .B(n1008), .Y(n854) );
XNOR2X1TS U1292 ( .A(n1133), .B(Op_MY[9]), .Y(n941) );
OAI22X1TS U1293 ( .A0(n828), .A1(n854), .B0(n1194), .B1(n941), .Y(
DP_OP_110J3_122_4535_n702) );
XNOR2X1TS U1294 ( .A(n1133), .B(n1007), .Y(n855) );
OAI22X1TS U1295 ( .A0(n828), .A1(n855), .B0(n1194), .B1(n854), .Y(
DP_OP_110J3_122_4535_n703) );
XNOR2X1TS U1296 ( .A(n1133), .B(Op_MY[6]), .Y(n856) );
OAI22X1TS U1297 ( .A0(n828), .A1(n856), .B0(n1194), .B1(n855), .Y(
DP_OP_110J3_122_4535_n704) );
OAI22X1TS U1298 ( .A0(n828), .A1(n857), .B0(n1194), .B1(n856), .Y(
DP_OP_110J3_122_4535_n705) );
XNOR2X1TS U1299 ( .A(n1133), .B(Op_MY[3]), .Y(n859) );
OAI22X1TS U1300 ( .A0(n828), .A1(n859), .B0(n1194), .B1(n858), .Y(
DP_OP_110J3_122_4535_n707) );
XNOR2X1TS U1301 ( .A(n1133), .B(Op_MY[2]), .Y(n860) );
OAI22X1TS U1302 ( .A0(n828), .A1(n860), .B0(n1194), .B1(n859), .Y(
DP_OP_110J3_122_4535_n708) );
XNOR2X1TS U1303 ( .A(n1133), .B(Op_MY[1]), .Y(n1134) );
OAI22X1TS U1304 ( .A0(n828), .A1(n1134), .B0(n1194), .B1(n860), .Y(
DP_OP_110J3_122_4535_n709) );
XNOR2X1TS U1305 ( .A(n1166), .B(Op_MY[10]), .Y(n861) );
XNOR2X1TS U1306 ( .A(n1166), .B(n1016), .Y(n943) );
OAI22X1TS U1307 ( .A0(n833), .A1(n861), .B0(n1192), .B1(n943), .Y(
DP_OP_110J3_122_4535_n714) );
OAI22X1TS U1308 ( .A0(n833), .A1(n862), .B0(n1192), .B1(n861), .Y(
DP_OP_110J3_122_4535_n715) );
XNOR2X1TS U1309 ( .A(n1166), .B(Op_MY[6]), .Y(n864) );
OAI22X1TS U1310 ( .A0(n833), .A1(n864), .B0(n1192), .B1(n863), .Y(
DP_OP_110J3_122_4535_n718) );
XNOR2X1TS U1311 ( .A(n1166), .B(Op_MY[5]), .Y(n865) );
OAI22X1TS U1312 ( .A0(n833), .A1(n865), .B0(n1192), .B1(n864), .Y(
DP_OP_110J3_122_4535_n719) );
XNOR2X1TS U1313 ( .A(n1166), .B(Op_MY[4]), .Y(n866) );
OAI22X1TS U1314 ( .A0(n833), .A1(n866), .B0(n1192), .B1(n865), .Y(
DP_OP_110J3_122_4535_n720) );
XNOR2X1TS U1315 ( .A(n1166), .B(Op_MY[3]), .Y(n1138) );
OAI22X1TS U1316 ( .A0(n833), .A1(n1138), .B0(n1192), .B1(n866), .Y(
DP_OP_110J3_122_4535_n721) );
XNOR2X1TS U1317 ( .A(n1164), .B(n1016), .Y(n867) );
OAI22X1TS U1318 ( .A0(n1181), .A1(n867), .B0(n1179), .B1(n442), .Y(
DP_OP_110J3_122_4535_n727) );
XNOR2X1TS U1319 ( .A(n1164), .B(Op_MY[10]), .Y(n868) );
OAI22X1TS U1320 ( .A0(n1181), .A1(n868), .B0(n1179), .B1(n867), .Y(
DP_OP_110J3_122_4535_n728) );
OAI22X1TS U1321 ( .A0(n1181), .A1(n869), .B0(n1179), .B1(n868), .Y(
DP_OP_110J3_122_4535_n729) );
XNOR2X1TS U1322 ( .A(n1164), .B(n1007), .Y(n871) );
OAI22X1TS U1323 ( .A0(n1181), .A1(n871), .B0(n1179), .B1(n870), .Y(
DP_OP_110J3_122_4535_n731) );
XNOR2X1TS U1324 ( .A(n1164), .B(Op_MY[6]), .Y(n958) );
OAI22X1TS U1325 ( .A0(n1181), .A1(n958), .B0(n1179), .B1(n871), .Y(
DP_OP_110J3_122_4535_n732) );
XNOR2X1TS U1326 ( .A(n1155), .B(n1016), .Y(n872) );
OAI22X1TS U1327 ( .A0(n1176), .A1(n872), .B0(n1174), .B1(n424), .Y(
DP_OP_110J3_122_4535_n741) );
XNOR2X1TS U1328 ( .A(n1155), .B(Op_MY[10]), .Y(n1108) );
OAI22X1TS U1329 ( .A0(n1176), .A1(n1108), .B0(n1174), .B1(n872), .Y(
DP_OP_110J3_122_4535_n742) );
XNOR2X1TS U1330 ( .A(n1155), .B(n1008), .Y(n873) );
XNOR2X1TS U1331 ( .A(n1155), .B(Op_MY[9]), .Y(n1109) );
OAI22X1TS U1332 ( .A0(n1176), .A1(n873), .B0(n1174), .B1(n1109), .Y(
DP_OP_110J3_122_4535_n744) );
XNOR2X1TS U1333 ( .A(n1155), .B(n1007), .Y(n1136) );
OAI22X1TS U1334 ( .A0(n1176), .A1(n1136), .B0(n1174), .B1(n873), .Y(
DP_OP_110J3_122_4535_n745) );
XNOR2X2TS U1335 ( .A(Op_MX[20]), .B(Op_MX[19]), .Y(n876) );
XOR2X1TS U1336 ( .A(Op_MX[20]), .B(Op_MX[21]), .Y(n874) );
XNOR2X1TS U1337 ( .A(n1092), .B(Op_MY[22]), .Y(n947) );
OAI22X1TS U1338 ( .A0(n875), .A1(n947), .B0(n1119), .B1(n1092), .Y(n877) );
CMPR32X2TS U1339 ( .A(Op_MY[19]), .B(Op_MY[18]), .C(n877), .CO(
DP_OP_110J3_122_4535_n953), .S(DP_OP_110J3_122_4535_n954) );
XNOR2X2TS U1340 ( .A(Op_MX[18]), .B(Op_MX[17]), .Y(n889) );
XOR2X1TS U1341 ( .A(Op_MX[18]), .B(Op_MX[19]), .Y(n878) );
XNOR2X1TS U1342 ( .A(n954), .B(DP_OP_110J3_122_4535_n948), .Y(n880) );
XNOR2X1TS U1343 ( .A(n954), .B(Op_MY[21]), .Y(n891) );
OAI22X1TS U1344 ( .A0(n1003), .A1(n880), .B0(n1001), .B1(n891), .Y(n879) );
CMPR32X2TS U1345 ( .A(Op_MY[15]), .B(Op_MY[13]), .C(n879), .CO(
DP_OP_110J3_122_4535_n982), .S(DP_OP_110J3_122_4535_n983) );
XNOR2X1TS U1346 ( .A(n954), .B(Op_MY[19]), .Y(n892) );
OAI22X1TS U1347 ( .A0(n1003), .A1(n892), .B0(n1001), .B1(n880), .Y(n881) );
CMPR32X2TS U1348 ( .A(n427), .B(Op_MY[14]), .C(n881), .CO(
DP_OP_110J3_122_4535_n990), .S(DP_OP_110J3_122_4535_n991) );
XNOR2X1TS U1349 ( .A(n998), .B(Op_MY[21]), .Y(n908) );
XNOR2X1TS U1350 ( .A(n998), .B(Op_MY[22]), .Y(n907) );
OAI22X1TS U1351 ( .A0(n455), .A1(n908), .B0(n1121), .B1(n907), .Y(n882) );
CMPR32X2TS U1352 ( .A(n883), .B(n409), .C(n882), .CO(
DP_OP_110J3_122_4535_n1009), .S(DP_OP_110J3_122_4535_n1010) );
OAI22X1TS U1353 ( .A0(n1020), .A1(Op_MY[21]), .B0(n1021), .B1(n951), .Y(
DP_OP_110J3_122_4535_n1068) );
INVX2TS U1354 ( .A(n421), .Y(DP_OP_110J3_122_4535_n948) );
OAI22X1TS U1355 ( .A0(n1020), .A1(DP_OP_110J3_122_4535_n948), .B0(n1021),
.B1(Op_MY[21]), .Y(DP_OP_110J3_122_4535_n1069) );
OAI22X1TS U1356 ( .A0(n1020), .A1(Op_MY[19]), .B0(n1021), .B1(
DP_OP_110J3_122_4535_n948), .Y(DP_OP_110J3_122_4535_n1070) );
OAI22X1TS U1357 ( .A0(n1020), .A1(Op_MY[18]), .B0(n1021), .B1(Op_MY[19]),
.Y(DP_OP_110J3_122_4535_n1071) );
OAI22X1TS U1358 ( .A0(n1020), .A1(Op_MY[17]), .B0(n1021), .B1(Op_MY[18]),
.Y(DP_OP_110J3_122_4535_n1072) );
OAI22X1TS U1359 ( .A0(n1020), .A1(Op_MY[16]), .B0(n1021), .B1(Op_MY[17]),
.Y(DP_OP_110J3_122_4535_n1073) );
OAI22X1TS U1360 ( .A0(n1020), .A1(Op_MY[15]), .B0(n1021), .B1(Op_MY[16]),
.Y(DP_OP_110J3_122_4535_n1074) );
OAI22X1TS U1361 ( .A0(n1020), .A1(Op_MY[14]), .B0(n1021), .B1(Op_MY[15]),
.Y(DP_OP_110J3_122_4535_n1075) );
OAI22X1TS U1362 ( .A0(n1020), .A1(Op_MY[13]), .B0(n1021), .B1(Op_MY[14]),
.Y(DP_OP_110J3_122_4535_n1076) );
OAI22X1TS U1363 ( .A0(n1020), .A1(n409), .B0(n1021), .B1(Op_MY[13]), .Y(
DP_OP_110J3_122_4535_n1077) );
NOR2BX1TS U1364 ( .AN(n409), .B(n1021), .Y(DP_OP_110J3_122_4535_n1078) );
OAI22X1TS U1365 ( .A0(n875), .A1(Op_MX[21]), .B0(n1119), .B1(n428), .Y(
DP_OP_110J3_122_4535_n1080) );
XNOR2X1TS U1366 ( .A(n1092), .B(DP_OP_110J3_122_4535_n948), .Y(n884) );
XNOR2X1TS U1367 ( .A(n1092), .B(Op_MY[21]), .Y(n948) );
OAI22X1TS U1368 ( .A0(n875), .A1(n884), .B0(n1119), .B1(n948), .Y(
DP_OP_110J3_122_4535_n1083) );
XNOR2X1TS U1369 ( .A(n1092), .B(Op_MY[19]), .Y(n885) );
OAI22X1TS U1370 ( .A0(n875), .A1(n885), .B0(n1119), .B1(n884), .Y(
DP_OP_110J3_122_4535_n1084) );
XNOR2X1TS U1371 ( .A(n1092), .B(Op_MY[18]), .Y(n886) );
OAI22X1TS U1372 ( .A0(n875), .A1(n886), .B0(n1119), .B1(n885), .Y(
DP_OP_110J3_122_4535_n1085) );
XNOR2X1TS U1373 ( .A(n1092), .B(Op_MY[17]), .Y(n932) );
OAI22X1TS U1374 ( .A0(n875), .A1(n932), .B0(n1119), .B1(n886), .Y(
DP_OP_110J3_122_4535_n1086) );
XNOR2X1TS U1375 ( .A(n1092), .B(Op_MY[15]), .Y(n887) );
XNOR2X1TS U1376 ( .A(n1092), .B(Op_MY[16]), .Y(n933) );
OAI22X1TS U1377 ( .A0(n875), .A1(n887), .B0(n1119), .B1(n933), .Y(
DP_OP_110J3_122_4535_n1088) );
XNOR2X1TS U1378 ( .A(n1092), .B(Op_MY[14]), .Y(n888) );
OAI22X1TS U1379 ( .A0(n875), .A1(n888), .B0(n1119), .B1(n887), .Y(
DP_OP_110J3_122_4535_n1089) );
XNOR2X1TS U1380 ( .A(n1092), .B(Op_MY[13]), .Y(n996) );
OAI22X1TS U1381 ( .A0(n875), .A1(n996), .B0(n1119), .B1(n888), .Y(
DP_OP_110J3_122_4535_n1090) );
XNOR2X1TS U1382 ( .A(n954), .B(Op_MY[22]), .Y(n890) );
OAI22X1TS U1383 ( .A0(n1003), .A1(n890), .B0(n1001), .B1(n954), .Y(
DP_OP_110J3_122_4535_n1095) );
OAI22X1TS U1384 ( .A0(n1003), .A1(n891), .B0(n1001), .B1(n890), .Y(
DP_OP_110J3_122_4535_n1096) );
XNOR2X1TS U1385 ( .A(n954), .B(Op_MY[18]), .Y(n893) );
OAI22X1TS U1386 ( .A0(n1003), .A1(n893), .B0(n1001), .B1(n892), .Y(
DP_OP_110J3_122_4535_n1099) );
XNOR2X1TS U1387 ( .A(n954), .B(Op_MY[17]), .Y(n894) );
OAI22X1TS U1388 ( .A0(n1003), .A1(n894), .B0(n1001), .B1(n893), .Y(
DP_OP_110J3_122_4535_n1100) );
XNOR2X1TS U1389 ( .A(n954), .B(Op_MY[16]), .Y(n895) );
OAI22X1TS U1390 ( .A0(n1003), .A1(n895), .B0(n1001), .B1(n894), .Y(
DP_OP_110J3_122_4535_n1101) );
XNOR2X1TS U1391 ( .A(n954), .B(Op_MY[15]), .Y(n1000) );
OAI22X1TS U1392 ( .A0(n1003), .A1(n1000), .B0(n1001), .B1(n895), .Y(
DP_OP_110J3_122_4535_n1102) );
XNOR2X1TS U1393 ( .A(n954), .B(Op_MY[13]), .Y(n896) );
XNOR2X1TS U1394 ( .A(n954), .B(Op_MY[14]), .Y(n1002) );
OAI22X1TS U1395 ( .A0(n1003), .A1(n896), .B0(n1001), .B1(n1002), .Y(
DP_OP_110J3_122_4535_n1104) );
XNOR2X1TS U1396 ( .A(n954), .B(n409), .Y(n897) );
OAI22X1TS U1397 ( .A0(n1003), .A1(n897), .B0(n1001), .B1(n896), .Y(
DP_OP_110J3_122_4535_n1105) );
NOR2BX1TS U1398 ( .AN(n409), .B(n1001), .Y(DP_OP_110J3_122_4535_n1106) );
OAI22X1TS U1399 ( .A0(n937), .A1(n903), .B0(n935), .B1(n440), .Y(
DP_OP_110J3_122_4535_n1108) );
XNOR2X1TS U1400 ( .A(n903), .B(Op_MY[22]), .Y(n898) );
OAI22X1TS U1401 ( .A0(n937), .A1(n898), .B0(n935), .B1(n903), .Y(
DP_OP_110J3_122_4535_n1109) );
XNOR2X1TS U1402 ( .A(n903), .B(Op_MY[21]), .Y(n934) );
OAI22X1TS U1403 ( .A0(n937), .A1(n934), .B0(n935), .B1(n898), .Y(
DP_OP_110J3_122_4535_n1110) );
XNOR2X1TS U1404 ( .A(n903), .B(Op_MY[19]), .Y(n899) );
XNOR2X1TS U1405 ( .A(n903), .B(DP_OP_110J3_122_4535_n948), .Y(n936) );
OAI22X1TS U1406 ( .A0(n937), .A1(n899), .B0(n935), .B1(n936), .Y(
DP_OP_110J3_122_4535_n1112) );
XNOR2X1TS U1407 ( .A(n903), .B(Op_MY[18]), .Y(n900) );
OAI22X1TS U1408 ( .A0(n937), .A1(n900), .B0(n935), .B1(n899), .Y(
DP_OP_110J3_122_4535_n1113) );
XNOR2X1TS U1409 ( .A(n903), .B(Op_MY[17]), .Y(n901) );
OAI22X1TS U1410 ( .A0(n937), .A1(n901), .B0(n935), .B1(n900), .Y(
DP_OP_110J3_122_4535_n1114) );
XNOR2X1TS U1411 ( .A(n903), .B(Op_MY[16]), .Y(n902) );
OAI22X1TS U1412 ( .A0(n937), .A1(n902), .B0(n935), .B1(n901), .Y(
DP_OP_110J3_122_4535_n1115) );
XNOR2X1TS U1413 ( .A(n903), .B(Op_MY[15]), .Y(n904) );
OAI22X1TS U1414 ( .A0(n937), .A1(n904), .B0(n935), .B1(n902), .Y(
DP_OP_110J3_122_4535_n1116) );
XNOR2X1TS U1415 ( .A(n903), .B(Op_MY[14]), .Y(n905) );
OAI22X1TS U1416 ( .A0(n937), .A1(n905), .B0(n935), .B1(n904), .Y(
DP_OP_110J3_122_4535_n1117) );
OAI22X1TS U1417 ( .A0(n937), .A1(n906), .B0(n935), .B1(n905), .Y(
DP_OP_110J3_122_4535_n1118) );
OAI22X1TS U1418 ( .A0(n455), .A1(Op_MX[15]), .B0(n1121), .B1(n439), .Y(
DP_OP_110J3_122_4535_n1122) );
OAI22X1TS U1419 ( .A0(n455), .A1(n907), .B0(n1121), .B1(n998), .Y(
DP_OP_110J3_122_4535_n1123) );
XNOR2X1TS U1420 ( .A(n998), .B(Op_MY[20]), .Y(n909) );
OAI22X1TS U1421 ( .A0(n455), .A1(n909), .B0(n1121), .B1(n908), .Y(
DP_OP_110J3_122_4535_n1125) );
XNOR2X1TS U1422 ( .A(n998), .B(Op_MY[19]), .Y(n999) );
OAI22X1TS U1423 ( .A0(n455), .A1(n999), .B0(n1121), .B1(n909), .Y(
DP_OP_110J3_122_4535_n1126) );
XNOR2X1TS U1424 ( .A(n998), .B(Op_MY[16]), .Y(n910) );
XNOR2X1TS U1425 ( .A(n998), .B(Op_MY[17]), .Y(n1122) );
OAI22X1TS U1426 ( .A0(n455), .A1(n910), .B0(n1121), .B1(n1122), .Y(
DP_OP_110J3_122_4535_n1129) );
OAI22X1TS U1427 ( .A0(n455), .A1(n911), .B0(n1121), .B1(n910), .Y(
DP_OP_110J3_122_4535_n1130) );
XNOR2X1TS U1428 ( .A(n1290), .B(Op_MY[21]), .Y(n1091) );
XNOR2X1TS U1429 ( .A(n1290), .B(Op_MY[22]), .Y(n1022) );
OAI22X1TS U1430 ( .A0(n1118), .A1(n1091), .B0(n1022), .B1(n426), .Y(
DP_OP_110J3_122_4535_n1138) );
XNOR2X1TS U1431 ( .A(n1290), .B(Op_MY[18]), .Y(n953) );
OAI22X1TS U1432 ( .A0(n1118), .A1(n912), .B0(n953), .B1(n426), .Y(
DP_OP_110J3_122_4535_n1142) );
INVX2TS U1433 ( .A(n961), .Y(n992) );
OAI22X1TS U1434 ( .A0(n913), .A1(n514), .B0(n992), .B1(n513), .Y(
DP_OP_110J3_122_4535_n335) );
XNOR2X1TS U1435 ( .A(n969), .B(n1085), .Y(n1154) );
OAI22X1TS U1436 ( .A0(n914), .A1(n1153), .B0(n1154), .B1(n532), .Y(
DP_OP_110J3_122_4535_n323) );
INVX2TS U1437 ( .A(n915), .Y(DP_OP_110J3_122_4535_n513) );
INVX2TS U1438 ( .A(n917), .Y(DP_OP_110J3_122_4535_n519) );
INVX2TS U1439 ( .A(n1329), .Y(DP_OP_110J3_122_4535_n233) );
INVX2TS U1440 ( .A(n1348), .Y(DP_OP_110J3_122_4535_n231) );
INVX2TS U1441 ( .A(n1349), .Y(DP_OP_110J3_122_4535_n230) );
INVX2TS U1442 ( .A(n924), .Y(DP_OP_110J3_122_4535_n523) );
INVX2TS U1443 ( .A(n925), .Y(DP_OP_110J3_122_4535_n520) );
INVX2TS U1444 ( .A(n927), .Y(DP_OP_110J3_122_4535_n522) );
INVX2TS U1445 ( .A(n928), .Y(DP_OP_110J3_122_4535_n516) );
INVX2TS U1446 ( .A(n929), .Y(DP_OP_110J3_122_4535_n521) );
INVX2TS U1447 ( .A(n1347), .Y(DP_OP_110J3_122_4535_n232) );
OAI22X1TS U1448 ( .A0(n875), .A1(n933), .B0(n1119), .B1(n932), .Y(n939) );
OAI22X1TS U1449 ( .A0(n937), .A1(n936), .B0(n935), .B1(n934), .Y(n938) );
CMPR32X2TS U1450 ( .A(n939), .B(n427), .C(n938), .CO(
DP_OP_110J3_122_4535_n1000), .S(DP_OP_110J3_122_4535_n1001) );
INVX2TS U1451 ( .A(DP_OP_110J3_122_4535_n592), .Y(DP_OP_110J3_122_4535_n593)
);
OAI22X1TS U1452 ( .A0(n828), .A1(n941), .B0(n1194), .B1(n940), .Y(n946) );
INVX2TS U1453 ( .A(n942), .Y(n945) );
OAI22X1TS U1454 ( .A0(n833), .A1(n943), .B0(n1192), .B1(n423), .Y(n944) );
CMPR32X2TS U1455 ( .A(n946), .B(n945), .C(n944), .CO(
DP_OP_110J3_122_4535_n576), .S(DP_OP_110J3_122_4535_n577) );
NOR2X1TS U1456 ( .A(DP_OP_110J3_122_4535_n905), .B(n431), .Y(
DP_OP_110J3_122_4535_n680) );
OAI22X1TS U1457 ( .A0(n875), .A1(n948), .B0(n1119), .B1(n947), .Y(n950) );
OAI22X1TS U1458 ( .A0(n1003), .A1(n954), .B0(n1001), .B1(n445), .Y(n949) );
CMPR32X2TS U1459 ( .A(n950), .B(n441), .C(n949), .CO(
DP_OP_110J3_122_4535_n958), .S(DP_OP_110J3_122_4535_n959) );
INVX2TS U1460 ( .A(DP_OP_110J3_122_4535_n566), .Y(DP_OP_110J3_122_4535_n567)
);
NOR2X1TS U1461 ( .A(DP_OP_110J3_122_4535_n905), .B(n402), .Y(
DP_OP_110J3_122_4535_n678) );
NOR2X1TS U1462 ( .A(n1020), .B(n951), .Y(DP_OP_110J3_122_4535_n1067) );
XNOR2X1TS U1463 ( .A(n1164), .B(Op_MY[3]), .Y(n1178) );
XNOR2X1TS U1464 ( .A(n1164), .B(Op_MY[4]), .Y(n960) );
OAI22X1TS U1465 ( .A0(n1181), .A1(n1178), .B0(n1179), .B1(n960), .Y(
DP_OP_110J3_122_4535_n735) );
XNOR2X1TS U1466 ( .A(n1164), .B(Op_MY[5]), .Y(n959) );
OAI22X1TS U1467 ( .A0(n1181), .A1(n959), .B0(n1179), .B1(n958), .Y(
DP_OP_110J3_122_4535_n733) );
OAI22X1TS U1468 ( .A0(n1181), .A1(n960), .B0(n1179), .B1(n959), .Y(
DP_OP_110J3_122_4535_n734) );
XNOR2X1TS U1469 ( .A(n1166), .B(Op_MY[1]), .Y(n1167) );
XNOR2X1TS U1470 ( .A(n1166), .B(Op_MY[2]), .Y(n1139) );
OAI22X1TS U1471 ( .A0(n833), .A1(n1167), .B0(n1192), .B1(n1139), .Y(
DP_OP_110J3_122_4535_n723) );
NOR2BX1TS U1472 ( .AN(Op_MY[0]), .B(n1147), .Y(DP_OP_110J3_122_4535_n697) );
XNOR2X1TS U1473 ( .A(n772), .B(n961), .Y(n1160) );
XNOR2X1TS U1474 ( .A(n757), .B(n961), .Y(n1158) );
OAI22X1TS U1475 ( .A0(n1160), .A1(n513), .B0(n1158), .B1(n514), .Y(
DP_OP_110J3_122_4535_n341) );
XNOR2X1TS U1476 ( .A(n966), .B(n1085), .Y(n1050) );
OAI22X1TS U1477 ( .A0(n1050), .A1(n1153), .B0(n962), .B1(n532), .Y(n1055) );
XNOR2X1TS U1478 ( .A(n1052), .B(n963), .Y(n1053) );
OAI22X1TS U1479 ( .A0(n813), .A1(n964), .B0(n1053), .B1(n1056), .Y(n1054) );
XNOR2X1TS U1480 ( .A(n772), .B(n1052), .Y(n974) );
OAI22X1TS U1481 ( .A0(n974), .A1(n1056), .B0(n965), .B1(n813), .Y(n977) );
XNOR2X1TS U1482 ( .A(n987), .B(n966), .Y(n975) );
OAI22X1TS U1483 ( .A0(n803), .A1(n967), .B0(n975), .B1(n1079), .Y(n976) );
XNOR2X1TS U1484 ( .A(n1025), .B(n772), .Y(n1075) );
XNOR2X1TS U1485 ( .A(n969), .B(n987), .Y(n1080) );
OAI22X1TS U1486 ( .A0(n970), .A1(n1079), .B0(n1080), .B1(n803), .Y(n971) );
CMPR32X2TS U1487 ( .A(n973), .B(n972), .C(n971), .CO(
DP_OP_110J3_122_4535_n95), .S(DP_OP_110J3_122_4535_n96) );
XNOR2X1TS U1488 ( .A(n988), .B(n1052), .Y(n978) );
OAI22X1TS U1489 ( .A0(n978), .A1(n1056), .B0(n974), .B1(n813), .Y(n983) );
XNOR2X1TS U1490 ( .A(n987), .B(n757), .Y(n980) );
OAI22X1TS U1491 ( .A0(n803), .A1(n975), .B0(n980), .B1(n1079), .Y(n982) );
OAI22X1TS U1492 ( .A0(n979), .A1(n1056), .B0(n978), .B1(n813), .Y(n986) );
XNOR2X1TS U1493 ( .A(n987), .B(n772), .Y(n989) );
OAI22X1TS U1494 ( .A0(n803), .A1(n980), .B0(n989), .B1(n1079), .Y(n985) );
CMPR32X2TS U1495 ( .A(n983), .B(n982), .C(n981), .CO(n984), .S(
DP_OP_110J3_122_4535_n140) );
CMPR32X2TS U1496 ( .A(n986), .B(n985), .C(n984), .CO(
DP_OP_110J3_122_4535_n128), .S(DP_OP_110J3_122_4535_n129) );
XNOR2X1TS U1497 ( .A(n988), .B(n987), .Y(n1078) );
OAI22X1TS U1498 ( .A0(n1078), .A1(n1079), .B0(n803), .B1(n989), .Y(n993) );
XNOR2X1TS U1499 ( .A(n1025), .B(n757), .Y(n1076) );
CMPR32X2TS U1500 ( .A(n993), .B(n992), .C(n991), .CO(
DP_OP_110J3_122_4535_n117), .S(DP_OP_110J3_122_4535_n118) );
XNOR2X1TS U1501 ( .A(n1092), .B(n409), .Y(n997) );
XNOR2X1TS U1502 ( .A(n998), .B(Op_MY[18]), .Y(n1120) );
OAI22X1TS U1503 ( .A0(n455), .A1(n1120), .B0(n1121), .B1(n999), .Y(n1005) );
CMPR32X2TS U1504 ( .A(n1006), .B(n1005), .C(n1004), .CO(
DP_OP_110J3_122_4535_n1028), .S(DP_OP_110J3_122_4535_n1029) );
XNOR2X1TS U1505 ( .A(n1278), .B(n1007), .Y(n1129) );
XNOR2X1TS U1506 ( .A(n1278), .B(n1008), .Y(n1012) );
OAI22X1TS U1507 ( .A0(n483), .A1(n1129), .B0(n1012), .B1(n435), .Y(n1011) );
XNOR2X1TS U1508 ( .A(n1155), .B(Op_MY[5]), .Y(n1173) );
XNOR2X1TS U1509 ( .A(n1155), .B(Op_MY[6]), .Y(n1137) );
XNOR2X1TS U1510 ( .A(n1278), .B(Op_MY[9]), .Y(n1100) );
OAI22X1TS U1511 ( .A0(n483), .A1(n1012), .B0(n1100), .B1(n435), .Y(n1015) );
OAI22X1TS U1512 ( .A0(n828), .A1(n436), .B0(n1194), .B1(n1013), .Y(n1014) );
ADDHXLTS U1513 ( .A(n1015), .B(n1014), .CO(DP_OP_110J3_122_4535_n648), .S(
DP_OP_110J3_122_4535_n649) );
XNOR2X1TS U1514 ( .A(n1278), .B(Op_MY[10]), .Y(n1099) );
XNOR2X1TS U1515 ( .A(n1278), .B(n1016), .Y(n1107) );
OAI22X1TS U1516 ( .A0(n483), .A1(n1099), .B0(n1107), .B1(n435), .Y(n1019) );
OAI22X1TS U1517 ( .A0(n476), .A1(DP_OP_110J3_122_4535_n905), .B0(n1147),
.B1(n1017), .Y(n1018) );
ADDHXLTS U1518 ( .A(n1019), .B(n1018), .CO(DP_OP_110J3_122_4535_n635), .S(
DP_OP_110J3_122_4535_n636) );
ADDHXLTS U1519 ( .A(n1024), .B(n1023), .CO(DP_OP_110J3_122_4535_n1017), .S(
DP_OP_110J3_122_4535_n1018) );
XNOR2X1TS U1520 ( .A(n1026), .B(n1025), .Y(n1034) );
OAI22X1TS U1521 ( .A0(n1034), .A1(n1074), .B0(n1027), .B1(n788), .Y(n1032)
);
OAI22X1TS U1522 ( .A0(n1028), .A1(n803), .B0(n1035), .B1(n1079), .Y(n1031)
);
OAI22X1TS U1523 ( .A0(n1039), .A1(n1029), .B0(n1037), .B1(n1038), .Y(n1030)
);
CMPR32X2TS U1524 ( .A(n1032), .B(n1031), .C(n1030), .CO(
DP_OP_110J3_122_4535_n66), .S(DP_OP_110J3_122_4535_n67) );
OAI22X1TS U1525 ( .A0(n1034), .A1(n788), .B0(n1033), .B1(n1074), .Y(n1042)
);
CMPR32X2TS U1526 ( .A(n1042), .B(n1041), .C(n1040), .CO(
DP_OP_110J3_122_4535_n58), .S(DP_OP_110J3_122_4535_n59) );
ADDHXLTS U1527 ( .A(n1044), .B(n1043), .CO(DP_OP_110J3_122_4535_n665), .S(
n919) );
CMPR32X2TS U1528 ( .A(n1047), .B(n1046), .C(n1045), .CO(n1048), .S(
DP_OP_110J3_122_4535_n204) );
CMPR32X2TS U1529 ( .A(n1049), .B(DP_OP_110J3_122_4535_n200), .C(n1048), .CO(
DP_OP_110J3_122_4535_n196), .S(n569) );
XNOR2X1TS U1530 ( .A(n757), .B(n1085), .Y(n1060) );
OAI22X1TS U1531 ( .A0(n1060), .A1(n1153), .B0(n1050), .B1(n532), .Y(n1066)
);
XNOR2X1TS U1532 ( .A(n1052), .B(n1051), .Y(n1058) );
OAI22X1TS U1533 ( .A0(n813), .A1(n1053), .B0(n1058), .B1(n1056), .Y(n1065)
);
ADDHX1TS U1534 ( .A(n1055), .B(n1054), .CO(n1064), .S(
DP_OP_110J3_122_4535_n186) );
OAI22X1TS U1535 ( .A0(n813), .A1(n1058), .B0(n1057), .B1(n1056), .Y(n1068)
);
OAI22X1TS U1536 ( .A0(n1061), .A1(n1153), .B0(n1060), .B1(n532), .Y(n1067)
);
OAI22X1TS U1537 ( .A0(n803), .A1(n1063), .B0(n1062), .B1(n1079), .Y(n1071)
);
CMPR32X2TS U1538 ( .A(n1066), .B(n1065), .C(n1064), .CO(n1070), .S(
DP_OP_110J3_122_4535_n178) );
ADDHXLTS U1539 ( .A(n1068), .B(n1067), .CO(DP_OP_110J3_122_4535_n169), .S(
n1069) );
CMPR32X2TS U1540 ( .A(n1071), .B(n1070), .C(n1069), .CO(
DP_OP_110J3_122_4535_n167), .S(DP_OP_110J3_122_4535_n168) );
XNOR2X1TS U1541 ( .A(n1085), .B(n1086), .Y(n1073) );
OAI22X1TS U1542 ( .A0(n532), .A1(n1073), .B0(n1072), .B1(n533), .Y(
DP_OP_110J3_122_4535_n332) );
OAI22X1TS U1543 ( .A0(n788), .A1(n1076), .B0(n1075), .B1(n1074), .Y(n1084)
);
OAI22X1TS U1544 ( .A0(n1080), .A1(n1079), .B0(n1078), .B1(n803), .Y(n1083)
);
OAI22X1TS U1545 ( .A0(n1081), .A1(n532), .B0(n1088), .B1(n1153), .Y(n1082)
);
CMPR32X2TS U1546 ( .A(n1084), .B(n1083), .C(n1082), .CO(
DP_OP_110J3_122_4535_n106), .S(DP_OP_110J3_122_4535_n107) );
NAND2BXLTS U1547 ( .AN(n1086), .B(n1085), .Y(n1087) );
OAI22X1TS U1548 ( .A0(n532), .A1(n1088), .B0(n1087), .B1(n1153), .Y(
DP_OP_110J3_122_4535_n243) );
OAI22X1TS U1549 ( .A0(n1090), .A1(n513), .B0(n514), .B1(n1089), .Y(
DP_OP_110J3_122_4535_n346) );
OAI22X1TS U1550 ( .A0(n875), .A1(n428), .B0(n1119), .B1(n1093), .Y(n1094) );
ADDHXLTS U1551 ( .A(n1095), .B(n1094), .CO(DP_OP_110J3_122_4535_n1030), .S(
DP_OP_110J3_122_4535_n1031) );
INVX2TS U1552 ( .A(n1097), .Y(DP_OP_110J3_122_4535_n517) );
INVX2TS U1553 ( .A(n1098), .Y(DP_OP_110J3_122_4535_n527) );
OAI22X1TS U1554 ( .A0(n483), .A1(n1100), .B0(n1099), .B1(n435), .Y(
DP_OP_110J3_122_4535_n757) );
CMPR32X2TS U1555 ( .A(n1103), .B(n1102), .C(n1101), .CO(n1104), .S(n1198) );
INVX2TS U1556 ( .A(n1198), .Y(DP_OP_110J3_122_4535_n236) );
INVX2TS U1557 ( .A(n1327), .Y(DP_OP_110J3_122_4535_n235) );
OAI22X1TS U1558 ( .A0(n483), .A1(n1107), .B0(n396), .B1(n435), .Y(n1112) );
NOR2BX1TS U1559 ( .AN(Op_MY[0]), .B(DP_OP_110J3_122_4535_n905), .Y(n1111) );
OAI22X1TS U1560 ( .A0(n1176), .A1(n1109), .B0(n1174), .B1(n1108), .Y(n1110)
);
CMPR32X2TS U1561 ( .A(n1112), .B(n1111), .C(n1110), .CO(
DP_OP_110J3_122_4535_n627), .S(DP_OP_110J3_122_4535_n628) );
OAI22X1TS U1562 ( .A0(n1114), .A1(n513), .B0(n1113), .B1(n514), .Y(
DP_OP_110J3_122_4535_n344) );
INVX2TS U1563 ( .A(n1115), .Y(DP_OP_110J3_122_4535_n526) );
OAI22X1TS U1564 ( .A0(n455), .A1(n1122), .B0(n1121), .B1(n1120), .Y(n1123)
);
CMPR32X2TS U1565 ( .A(n1128), .B(n1127), .C(n1126), .CO(n918), .S(n1328) );
INVX2TS U1566 ( .A(n1328), .Y(DP_OP_110J3_122_4535_n234) );
XNOR2X1TS U1567 ( .A(n1278), .B(Op_MY[6]), .Y(n1171) );
OAI22X1TS U1568 ( .A0(n483), .A1(n1171), .B0(n1129), .B1(n435), .Y(n1132) );
OAI22X1TS U1569 ( .A0(n833), .A1(n423), .B0(n1192), .B1(n1130), .Y(n1131) );
ADDHXLTS U1570 ( .A(n1132), .B(n1131), .CO(DP_OP_110J3_122_4535_n658), .S(
DP_OP_110J3_122_4535_n659) );
XNOR2X1TS U1571 ( .A(n1133), .B(n1169), .Y(n1135) );
OAI22X1TS U1572 ( .A0(n828), .A1(n1135), .B0(n1194), .B1(n1134), .Y(n1142)
);
OAI22X1TS U1573 ( .A0(n833), .A1(n1139), .B0(n1192), .B1(n1138), .Y(n1140)
);
CMPR32X2TS U1574 ( .A(n1142), .B(n1141), .C(n1140), .CO(
DP_OP_110J3_122_4535_n646), .S(DP_OP_110J3_122_4535_n647) );
INVX2TS U1575 ( .A(n1143), .Y(DP_OP_110J3_122_4535_n525) );
XNOR2X1TS U1576 ( .A(n1145), .B(Op_MY[1]), .Y(n1146) );
OAI22X1TS U1577 ( .A0(n476), .A1(n1146), .B0(n1147), .B1(n1144), .Y(
DP_OP_110J3_122_4535_n695) );
XNOR2X1TS U1578 ( .A(n1145), .B(Op_MY[0]), .Y(n1148) );
OAI22X1TS U1579 ( .A0(n476), .A1(n1148), .B0(n1147), .B1(n1146), .Y(
DP_OP_110J3_122_4535_n696) );
INVX2TS U1580 ( .A(n1150), .Y(DP_OP_110J3_122_4535_n528) );
OAI22X1TS U1581 ( .A0(n1154), .A1(n1153), .B0(n1152), .B1(n532), .Y(
DP_OP_110J3_122_4535_n324) );
XNOR2X1TS U1582 ( .A(n1155), .B(Op_MY[4]), .Y(n1175) );
OAI22X1TS U1583 ( .A0(n1176), .A1(n1156), .B0(n1174), .B1(n1175), .Y(
DP_OP_110J3_122_4535_n749) );
OAI22X1TS U1584 ( .A0(n1158), .A1(n513), .B0(n1157), .B1(n514), .Y(
DP_OP_110J3_122_4535_n342) );
INVX2TS U1585 ( .A(n1337), .Y(DP_OP_110J3_122_4535_n228) );
OAI22X1TS U1586 ( .A0(n1161), .A1(n513), .B0(n1160), .B1(n514), .Y(
DP_OP_110J3_122_4535_n340) );
OAI22X1TS U1587 ( .A0(n1163), .A1(n513), .B0(n1162), .B1(n514), .Y(
DP_OP_110J3_122_4535_n338) );
XNOR2X1TS U1588 ( .A(n1164), .B(Op_MY[2]), .Y(n1180) );
OAI22X1TS U1589 ( .A0(n1181), .A1(n1165), .B0(n1179), .B1(n1180), .Y(
DP_OP_110J3_122_4535_n737) );
XNOR2X1TS U1590 ( .A(n1166), .B(n1169), .Y(n1168) );
OAI22X1TS U1591 ( .A0(n833), .A1(n1168), .B0(n1192), .B1(n1167), .Y(
DP_OP_110J3_122_4535_n724) );
NOR2BX1TS U1592 ( .AN(n1169), .B(n1192), .Y(DP_OP_110J3_122_4535_n725) );
INVX2TS U1593 ( .A(n1350), .Y(DP_OP_110J3_122_4535_n229) );
OAI22X1TS U1594 ( .A0(n483), .A1(n1172), .B0(n1171), .B1(n435), .Y(
DP_OP_110J3_122_4535_n761) );
OAI22X1TS U1595 ( .A0(n1176), .A1(n1175), .B0(n1174), .B1(n1173), .Y(
DP_OP_110J3_122_4535_n748) );
CMPR32X2TS U1596 ( .A(DP_OP_110J3_122_4535_n631), .B(
DP_OP_110J3_122_4535_n638), .C(n1177), .CO(n583), .S(n1338) );
INVX2TS U1597 ( .A(n1338), .Y(DP_OP_110J3_122_4535_n227) );
OAI22X1TS U1598 ( .A0(n1181), .A1(n1180), .B0(n1179), .B1(n1178), .Y(
DP_OP_110J3_122_4535_n736) );
INVX2TS U1599 ( .A(n1340), .Y(DP_OP_110J3_122_4535_n226) );
INVX2TS U1600 ( .A(n1182), .Y(DP_OP_110J3_122_4535_n222) );
INVX2TS U1601 ( .A(n1183), .Y(DP_OP_110J3_122_4535_n223) );
INVX2TS U1602 ( .A(n1184), .Y(DP_OP_110J3_122_4535_n225) );
INVX2TS U1603 ( .A(n1185), .Y(DP_OP_110J3_122_4535_n224) );
INVX2TS U1604 ( .A(n1186), .Y(DP_OP_110J3_122_4535_n220) );
INVX2TS U1605 ( .A(n1188), .Y(DP_OP_110J3_122_4535_n218) );
INVX2TS U1606 ( .A(n1189), .Y(DP_OP_110J3_122_4535_n219) );
INVX2TS U1607 ( .A(n1190), .Y(DP_OP_110J3_122_4535_n221) );
INVX2TS U1608 ( .A(n1191), .Y(DP_OP_110J3_122_4535_n217) );
BUFX4TS U1609 ( .A(n167), .Y(n1598) );
BUFX4TS U1610 ( .A(n167), .Y(n1597) );
BUFX4TS U1611 ( .A(n167), .Y(n1596) );
NOR2X2TS U1612 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[2]), .Y(
n1276) );
NOR2XLTS U1613 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[1]), .Y(
n1196) );
BUFX4TS U1614 ( .A(n1197), .Y(n1595) );
BUFX4TS U1615 ( .A(n1295), .Y(n1346) );
MX2X1TS U1616 ( .A(P_Sgf[2]), .B(n1198), .S0(n1346), .Y(n240) );
NOR3X1TS U1617 ( .A(n1199), .B(n1599), .C(n1558), .Y(n1200) );
BUFX3TS U1618 ( .A(n1200), .Y(n1556) );
OA22X1TS U1619 ( .A0(n1556), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n1551), .Y(n173) );
BUFX4TS U1620 ( .A(n1197), .Y(n1585) );
AND2X4TS U1621 ( .A(n1236), .B(n1599), .Y(FSM_exp_operation_A_S) );
INVX2TS U1622 ( .A(n1205), .Y(n1201) );
INVX2TS U1623 ( .A(n1207), .Y(n1209) );
BUFX4TS U1624 ( .A(n1197), .Y(n1592) );
BUFX4TS U1625 ( .A(n1197), .Y(n1593) );
BUFX4TS U1626 ( .A(n1197), .Y(n1594) );
BUFX4TS U1627 ( .A(n1197), .Y(n1591) );
BUFX4TS U1628 ( .A(n1197), .Y(n1587) );
BUFX4TS U1629 ( .A(n1197), .Y(n1586) );
BUFX4TS U1630 ( .A(n1197), .Y(n1588) );
BUFX4TS U1631 ( .A(n1197), .Y(n1590) );
BUFX4TS U1632 ( .A(n1197), .Y(n1589) );
NOR2X2TS U1633 ( .A(n1558), .B(FS_Module_state_reg[1]), .Y(n1277) );
NOR2X1TS U1634 ( .A(FS_Module_state_reg[3]), .B(n1557), .Y(n1237) );
NAND2X1TS U1635 ( .A(n1277), .B(n1237), .Y(n1471) );
NOR2BX1TS U1636 ( .AN(P_Sgf[47]), .B(n1471), .Y(n1230) );
NAND2X1TS U1637 ( .A(n1276), .B(n1229), .Y(n1497) );
OAI211XLTS U1638 ( .A0(n1230), .A1(n1565), .B0(n1545), .C0(n1497), .Y(n236)
);
INVX2TS U1639 ( .A(n1497), .Y(n1496) );
INVX2TS U1640 ( .A(n1230), .Y(n1231) );
OAI31X1TS U1641 ( .A0(n1496), .A1(n1550), .A2(n1566), .B0(n1231), .Y(n235)
);
XOR2X1TS U1642 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n1268) );
NOR2XLTS U1643 ( .A(n1268), .B(underflow_flag), .Y(n1232) );
OAI32X1TS U1644 ( .A0(n1554), .A1(n1232), .A2(overflow_flag), .B0(n1556),
.B1(n1583), .Y(n168) );
NAND2X1TS U1645 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n1274) );
NOR3X1TS U1646 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[0]), .C(
n1274), .Y(ready) );
INVX2TS U1647 ( .A(ready), .Y(n1233) );
INVX2TS U1648 ( .A(FSM_exp_operation_A_S), .Y(n1472) );
OAI22X1TS U1649 ( .A0(n1472), .A1(zero_flag), .B0(FS_Module_state_reg[0]),
.B1(FS_Module_state_reg[2]), .Y(n1234) );
AOI2BB1XLTS U1650 ( .A0N(n1471), .A1N(P_Sgf[47]), .B0(n1234), .Y(n1235) );
AOI32X4TS U1651 ( .A0(FSM_add_overflow_flag), .A1(FS_Module_state_reg[1]),
.A2(n1273), .B0(n1236), .B1(FS_Module_state_reg[1]), .Y(n1501) );
OR2X2TS U1652 ( .A(n1501), .B(FSM_selector_C), .Y(n1411) );
OA21X2TS U1653 ( .A0(n1237), .A1(n1273), .B0(FS_Module_state_reg[1]), .Y(
n1500) );
INVX3TS U1654 ( .A(n1500), .Y(n1463) );
AOI22X1TS U1655 ( .A0(Sgf_normalized_result[0]), .A1(n1463), .B0(n404), .B1(
Add_result[1]), .Y(n1242) );
NAND2X1TS U1656 ( .A(n1500), .B(n1501), .Y(n1239) );
AOI22X1TS U1657 ( .A0(n1467), .A1(P_Sgf[23]), .B0(n405), .B1(Add_result[0]),
.Y(n1241) );
INVX3TS U1658 ( .A(n1500), .Y(n1498) );
AOI22X1TS U1659 ( .A0(Sgf_normalized_result[2]), .A1(n1498), .B0(n404), .B1(
Add_result[3]), .Y(n1244) );
AOI22X1TS U1660 ( .A0(n1467), .A1(P_Sgf[25]), .B0(n405), .B1(Add_result[2]),
.Y(n1243) );
AOI22X1TS U1661 ( .A0(Sgf_normalized_result[5]), .A1(n1498), .B0(
Add_result[6]), .B1(n404), .Y(n1246) );
AOI22X1TS U1662 ( .A0(n1467), .A1(P_Sgf[28]), .B0(n405), .B1(Add_result[5]),
.Y(n1245) );
AOI22X1TS U1663 ( .A0(Sgf_normalized_result[3]), .A1(n1498), .B0(n404), .B1(
Add_result[4]), .Y(n1248) );
AOI22X1TS U1664 ( .A0(n1467), .A1(P_Sgf[26]), .B0(n405), .B1(Add_result[3]),
.Y(n1247) );
AOI22X1TS U1665 ( .A0(Sgf_normalized_result[4]), .A1(n1498), .B0(n404), .B1(
Add_result[5]), .Y(n1250) );
AOI22X1TS U1666 ( .A0(n1467), .A1(P_Sgf[27]), .B0(n405), .B1(Add_result[4]),
.Y(n1249) );
AOI22X1TS U1667 ( .A0(Sgf_normalized_result[1]), .A1(n1498), .B0(n404), .B1(
Add_result[2]), .Y(n1252) );
AOI22X1TS U1668 ( .A0(n1467), .A1(P_Sgf[24]), .B0(n405), .B1(Add_result[1]),
.Y(n1251) );
AOI22X1TS U1669 ( .A0(Sgf_normalized_result[7]), .A1(n1498), .B0(
Add_result[8]), .B1(n404), .Y(n1254) );
AOI22X1TS U1670 ( .A0(Add_result[7]), .A1(n405), .B0(n1467), .B1(P_Sgf[30]),
.Y(n1253) );
OAI211XLTS U1671 ( .A0(n1411), .A1(n411), .B0(n1254), .C0(n1253), .Y(n209)
);
AOI22X1TS U1672 ( .A0(Sgf_normalized_result[6]), .A1(n1498), .B0(
Add_result[7]), .B1(n404), .Y(n1256) );
AOI22X1TS U1673 ( .A0(Add_result[6]), .A1(n405), .B0(n1467), .B1(P_Sgf[29]),
.Y(n1255) );
AOI22X1TS U1674 ( .A0(FSM_selector_C), .A1(Add_result[23]), .B0(P_Sgf[46]),
.B1(n1569), .Y(n1499) );
AOI22X1TS U1675 ( .A0(Sgf_normalized_result[22]), .A1(n1498), .B0(
Add_result[22]), .B1(n405), .Y(n1259) );
NAND2X1TS U1676 ( .A(n1257), .B(P_Sgf[45]), .Y(n1258) );
OAI21XLTS U1677 ( .A0(n1557), .A1(n1470), .B0(FS_Module_state_reg[3]), .Y(
n1260) );
NOR4X1TS U1678 ( .A(P_Sgf[14]), .B(P_Sgf[15]), .C(P_Sgf[16]), .D(P_Sgf[17]),
.Y(n1267) );
NOR4X1TS U1679 ( .A(P_Sgf[18]), .B(P_Sgf[19]), .C(P_Sgf[20]), .D(P_Sgf[21]),
.Y(n1266) );
NOR3XLTS U1680 ( .A(P_Sgf[22]), .B(P_Sgf[0]), .C(P_Sgf[1]), .Y(n1263) );
AND4X1TS U1681 ( .A(n1264), .B(n1263), .C(n1262), .D(n1261), .Y(n1265) );
MXI2X1TS U1682 ( .A(round_mode[0]), .B(round_mode[1]), .S0(n1268), .Y(n1269)
);
OAI211X1TS U1683 ( .A0(round_mode[0]), .A1(round_mode[1]), .B0(n1270), .C0(
n1269), .Y(n1272) );
AOI22X1TS U1684 ( .A0(n1277), .A1(n1274), .B0(n1273), .B1(n1272), .Y(n1275)
);
OAI31X1TS U1685 ( .A0(FS_Module_state_reg[0]), .A1(FS_Module_state_reg[2]),
.A2(n1599), .B0(n1275), .Y(n378) );
MX2X1TS U1686 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n1289), .Y(n344) );
MX2X1TS U1687 ( .A(Data_MX[1]), .B(n1278), .S0(n1289), .Y(n345) );
INVX4TS U1688 ( .A(n420), .Y(n1292) );
MX2X1TS U1689 ( .A(Data_MY[0]), .B(Op_MY[0]), .S0(n1292), .Y(n312) );
NOR3BX1TS U1690 ( .AN(Op_MY[30]), .B(FSM_selector_B[0]), .C(
FSM_selector_B[1]), .Y(n1279) );
XOR2X1TS U1691 ( .A(FSM_exp_operation_A_S), .B(n1279), .Y(
DP_OP_36J3_123_9196_n15) );
OR2X2TS U1692 ( .A(FSM_selector_B[1]), .B(n1565), .Y(n1286) );
OAI2BB1X1TS U1693 ( .A0N(Op_MY[29]), .A1N(n1566), .B0(n1286), .Y(n1280) );
XOR2X1TS U1694 ( .A(FSM_exp_operation_A_S), .B(n1280), .Y(
DP_OP_36J3_123_9196_n16) );
OAI2BB1X1TS U1695 ( .A0N(Op_MY[28]), .A1N(n1566), .B0(n1286), .Y(n1281) );
XOR2X1TS U1696 ( .A(FSM_exp_operation_A_S), .B(n1281), .Y(
DP_OP_36J3_123_9196_n17) );
OAI2BB1X1TS U1697 ( .A0N(Op_MY[27]), .A1N(n1566), .B0(n1286), .Y(n1282) );
XOR2X1TS U1698 ( .A(FSM_exp_operation_A_S), .B(n1282), .Y(
DP_OP_36J3_123_9196_n18) );
OAI2BB1X1TS U1699 ( .A0N(Op_MY[26]), .A1N(n1566), .B0(n1286), .Y(n1283) );
XOR2X1TS U1700 ( .A(FSM_exp_operation_A_S), .B(n1283), .Y(
DP_OP_36J3_123_9196_n19) );
OAI2BB1X1TS U1701 ( .A0N(Op_MY[25]), .A1N(n1566), .B0(n1286), .Y(n1284) );
XOR2X1TS U1702 ( .A(FSM_exp_operation_A_S), .B(n1284), .Y(
DP_OP_36J3_123_9196_n20) );
OAI2BB1X1TS U1703 ( .A0N(Op_MY[24]), .A1N(n1566), .B0(n1286), .Y(n1285) );
XOR2X1TS U1704 ( .A(FSM_exp_operation_A_S), .B(n1285), .Y(
DP_OP_36J3_123_9196_n21) );
NOR2XLTS U1705 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n1287) );
OAI21XLTS U1706 ( .A0(FSM_selector_B[0]), .A1(n1287), .B0(n1286), .Y(n1288)
);
XOR2X1TS U1707 ( .A(FSM_exp_operation_A_S), .B(n1288), .Y(
DP_OP_36J3_123_9196_n22) );
MX2X1TS U1708 ( .A(Data_MX[11]), .B(Op_MX[11]), .S0(n1289), .Y(n355) );
MX2X1TS U1709 ( .A(Data_MX[10]), .B(Op_MX[10]), .S0(n1289), .Y(n354) );
MX2X1TS U1710 ( .A(Data_MX[9]), .B(Op_MX[9]), .S0(n1289), .Y(n353) );
MX2X1TS U1711 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n1289), .Y(n352) );
MX2X1TS U1712 ( .A(Data_MX[7]), .B(Op_MX[7]), .S0(n1289), .Y(n351) );
MX2X1TS U1713 ( .A(Data_MX[6]), .B(Op_MX[6]), .S0(n1289), .Y(n350) );
MX2X1TS U1714 ( .A(Data_MX[5]), .B(Op_MX[5]), .S0(n1289), .Y(n349) );
MX2X1TS U1715 ( .A(Data_MX[4]), .B(Op_MX[4]), .S0(n1289), .Y(n348) );
MX2X1TS U1716 ( .A(Data_MX[3]), .B(Op_MX[3]), .S0(n1289), .Y(n347) );
MX2X1TS U1717 ( .A(Data_MX[2]), .B(Op_MX[2]), .S0(n1289), .Y(n346) );
MX2X1TS U1718 ( .A(Data_MX[22]), .B(Op_MX[22]), .S0(n1289), .Y(n366) );
MX2X1TS U1719 ( .A(Data_MX[21]), .B(Op_MX[21]), .S0(n1291), .Y(n365) );
MX2X1TS U1720 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(n1291), .Y(n364) );
MX2X1TS U1721 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n1291), .Y(n363) );
MX2X1TS U1722 ( .A(Data_MX[18]), .B(Op_MX[18]), .S0(n1291), .Y(n362) );
MX2X1TS U1723 ( .A(Data_MX[17]), .B(Op_MX[17]), .S0(n1291), .Y(n361) );
MX2X1TS U1724 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n1291), .Y(n360) );
MX2X1TS U1725 ( .A(Data_MX[15]), .B(Op_MX[15]), .S0(n1291), .Y(n359) );
MX2X1TS U1726 ( .A(Data_MX[14]), .B(Op_MX[14]), .S0(n1291), .Y(n358) );
MX2X1TS U1727 ( .A(Data_MX[13]), .B(n1290), .S0(n1291), .Y(n357) );
MX2X1TS U1728 ( .A(Data_MX[12]), .B(Op_MX[12]), .S0(n1291), .Y(n356) );
MX2X1TS U1729 ( .A(Data_MY[11]), .B(Op_MY[11]), .S0(n1291), .Y(n323) );
MX2X1TS U1730 ( .A(Data_MY[10]), .B(Op_MY[10]), .S0(n1291), .Y(n322) );
MX2X1TS U1731 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(n1291), .Y(n321) );
MX2X1TS U1732 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n1292), .Y(n320) );
MX2X1TS U1733 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(n1292), .Y(n319) );
MX2X1TS U1734 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(n1292), .Y(n318) );
MX2X1TS U1735 ( .A(Data_MY[5]), .B(Op_MY[5]), .S0(n1292), .Y(n317) );
MX2X1TS U1736 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(n1292), .Y(n316) );
MX2X1TS U1737 ( .A(Data_MY[3]), .B(Op_MY[3]), .S0(n1292), .Y(n315) );
MX2X1TS U1738 ( .A(Data_MY[2]), .B(Op_MY[2]), .S0(n1292), .Y(n314) );
MX2X1TS U1739 ( .A(Data_MY[1]), .B(Op_MY[1]), .S0(n1292), .Y(n313) );
MX2X1TS U1740 ( .A(Data_MY[22]), .B(Op_MY[22]), .S0(n1292), .Y(n334) );
MX2X1TS U1741 ( .A(Data_MY[21]), .B(Op_MY[21]), .S0(n1292), .Y(n333) );
MX2X1TS U1742 ( .A(Data_MY[20]), .B(Op_MY[20]), .S0(n1292), .Y(n332) );
MX2X1TS U1743 ( .A(Data_MY[19]), .B(Op_MY[19]), .S0(n1292), .Y(n331) );
MX2X1TS U1744 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n1351), .Y(n330) );
MX2X1TS U1745 ( .A(Data_MY[17]), .B(Op_MY[17]), .S0(n1351), .Y(n329) );
MX2X1TS U1746 ( .A(Data_MY[16]), .B(Op_MY[16]), .S0(n1351), .Y(n328) );
MX2X1TS U1747 ( .A(Data_MY[15]), .B(Op_MY[15]), .S0(n1351), .Y(n327) );
MX2X1TS U1748 ( .A(Data_MY[14]), .B(Op_MY[14]), .S0(n1351), .Y(n326) );
MX2X1TS U1749 ( .A(Data_MY[13]), .B(Op_MY[13]), .S0(n1351), .Y(n325) );
MX2X1TS U1750 ( .A(Data_MY[12]), .B(Op_MY[12]), .S0(n1351), .Y(n324) );
NAND2X1TS U1751 ( .A(n412), .B(n1293), .Y(n1294) );
XNOR2X1TS U1752 ( .A(n1294), .B(n391), .Y(n1296) );
NAND2X1TS U1753 ( .A(n413), .B(n1297), .Y(n1298) );
INVX2TS U1754 ( .A(n1300), .Y(n1302) );
INVX2TS U1755 ( .A(n1306), .Y(n1308) );
MX2X1TS U1756 ( .A(P_Sgf[3]), .B(n1327), .S0(n1346), .Y(n241) );
MX2X1TS U1757 ( .A(P_Sgf[4]), .B(n1328), .S0(n1346), .Y(n242) );
MX2X1TS U1758 ( .A(P_Sgf[5]), .B(n1329), .S0(n1346), .Y(n243) );
MX2X1TS U1759 ( .A(P_Sgf[0]), .B(n1335), .S0(n1346), .Y(n238) );
MX2X1TS U1760 ( .A(P_Sgf[1]), .B(n1336), .S0(n1346), .Y(n239) );
MX2X1TS U1761 ( .A(P_Sgf[10]), .B(n1337), .S0(n1346), .Y(n248) );
MX2X1TS U1762 ( .A(P_Sgf[11]), .B(n1338), .S0(n1346), .Y(n249) );
NAND2X1TS U1763 ( .A(n392), .B(n1342), .Y(n1344) );
MX2X1TS U1764 ( .A(P_Sgf[6]), .B(n1347), .S0(n1346), .Y(n244) );
MX2X1TS U1765 ( .A(P_Sgf[7]), .B(n1348), .S0(n1398), .Y(n245) );
MX2X1TS U1766 ( .A(P_Sgf[8]), .B(n1349), .S0(n1398), .Y(n246) );
MX2X1TS U1767 ( .A(P_Sgf[9]), .B(n1350), .S0(n1398), .Y(n247) );
MX2X1TS U1768 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n1351), .Y(n342) );
MX2X1TS U1769 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n1351), .Y(n341) );
MX2X1TS U1770 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n1351), .Y(n340) );
MX2X1TS U1771 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n1351), .Y(n339) );
MX2X1TS U1772 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n1351), .Y(n338) );
MX2X1TS U1773 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n1351), .Y(n337) );
INVX3TS U1774 ( .A(n420), .Y(n1474) );
MX2X1TS U1775 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n1474), .Y(n336) );
MX2X1TS U1776 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n1474), .Y(n335) );
MX2X1TS U1777 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n1474), .Y(n374) );
MX2X1TS U1778 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n1474), .Y(n373) );
MX2X1TS U1779 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n1474), .Y(n372) );
MX2X1TS U1780 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n1474), .Y(n371) );
MX2X1TS U1781 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n1474), .Y(n370) );
MX2X1TS U1782 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n1474), .Y(n369) );
MX2X1TS U1783 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n1474), .Y(n367) );
MX2X1TS U1784 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n1474), .Y(n368) );
NAND2X1TS U1785 ( .A(n1497), .B(n1572), .Y(n376) );
NOR2BX1TS U1786 ( .AN(exp_oper_result[8]), .B(n1572), .Y(S_Oper_A_exp[8]) );
MX2X1TS U1787 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(n1400),
.Y(n227) );
MX2X1TS U1788 ( .A(Op_MX[30]), .B(exp_oper_result[7]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[7]) );
MX2X1TS U1789 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(n1400),
.Y(n228) );
MX2X1TS U1790 ( .A(Op_MX[29]), .B(exp_oper_result[6]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[6]) );
MX2X1TS U1791 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(n1400),
.Y(n229) );
MX2X1TS U1792 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
MX2X1TS U1793 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(n1400),
.Y(n230) );
MX2X1TS U1794 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
MX2X1TS U1795 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(n1400),
.Y(n231) );
MX2X1TS U1796 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
MX2X1TS U1797 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n1400),
.Y(n232) );
MX2X1TS U1798 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
MX2X1TS U1799 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n1400),
.Y(n233) );
MX2X1TS U1800 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
MX2X1TS U1801 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n1400),
.Y(n234) );
MX2X1TS U1802 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
XNOR2X1TS U1803 ( .A(DP_OP_36J3_123_9196_n1), .B(n1472), .Y(n1401) );
NAND4XLTS U1804 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n1402) );
NAND4BXLTS U1805 ( .AN(n1402), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n1403) );
OAI22X1TS U1806 ( .A0(Exp_module_Data_S[8]), .A1(n1404), .B0(n1496), .B1(
n1584), .Y(n201) );
INVX2TS U1807 ( .A(n1257), .Y(n1414) );
AOI22X1TS U1808 ( .A0(Sgf_normalized_result[8]), .A1(n1498), .B0(
Add_result[9]), .B1(n403), .Y(n1413) );
INVX3TS U1809 ( .A(n1411), .Y(n1465) );
NAND2X1TS U1810 ( .A(n1465), .B(P_Sgf[32]), .Y(n1412) );
AO21XLTS U1811 ( .A0(n1469), .A1(Add_result[8]), .B0(n1415), .Y(n210) );
AOI22X1TS U1812 ( .A0(Sgf_normalized_result[9]), .A1(n1498), .B0(
Add_result[10]), .B1(n403), .Y(n1420) );
OAI2BB1X1TS U1813 ( .A0N(P_Sgf[33]), .A1N(n1465), .B0(n1420), .Y(n1421) );
AOI21X1TS U1814 ( .A0(n1257), .A1(P_Sgf[32]), .B0(n1421), .Y(n1422) );
OAI2BB1X1TS U1815 ( .A0N(n1469), .A1N(Add_result[9]), .B0(n1422), .Y(n211)
);
AOI22X1TS U1816 ( .A0(Sgf_normalized_result[10]), .A1(n1498), .B0(
Add_result[11]), .B1(n403), .Y(n1430) );
OAI2BB1X1TS U1817 ( .A0N(P_Sgf[34]), .A1N(n1465), .B0(n1430), .Y(n1431) );
AOI21X1TS U1818 ( .A0(n1257), .A1(P_Sgf[33]), .B0(n1431), .Y(n1432) );
OAI2BB1X1TS U1819 ( .A0N(n1469), .A1N(Add_result[10]), .B0(n1432), .Y(n212)
);
AOI22X1TS U1820 ( .A0(Sgf_normalized_result[11]), .A1(n1463), .B0(
Add_result[12]), .B1(n403), .Y(n1433) );
OAI2BB1X1TS U1821 ( .A0N(P_Sgf[35]), .A1N(n1465), .B0(n1433), .Y(n1434) );
AOI21X1TS U1822 ( .A0(n1257), .A1(P_Sgf[34]), .B0(n1434), .Y(n1435) );
OAI2BB1X1TS U1823 ( .A0N(n1469), .A1N(Add_result[11]), .B0(n1435), .Y(n213)
);
AOI22X1TS U1824 ( .A0(Sgf_normalized_result[12]), .A1(n1463), .B0(
Add_result[13]), .B1(n403), .Y(n1436) );
OAI2BB1X1TS U1825 ( .A0N(P_Sgf[36]), .A1N(n1465), .B0(n1436), .Y(n1437) );
AOI21X1TS U1826 ( .A0(n1257), .A1(P_Sgf[35]), .B0(n1437), .Y(n1438) );
OAI2BB1X1TS U1827 ( .A0N(n1469), .A1N(Add_result[12]), .B0(n1438), .Y(n214)
);
AOI22X1TS U1828 ( .A0(Sgf_normalized_result[13]), .A1(n1463), .B0(
Add_result[14]), .B1(n403), .Y(n1439) );
OAI2BB1X1TS U1829 ( .A0N(P_Sgf[37]), .A1N(n1465), .B0(n1439), .Y(n1440) );
AOI21X1TS U1830 ( .A0(n1257), .A1(P_Sgf[36]), .B0(n1440), .Y(n1441) );
OAI2BB1X1TS U1831 ( .A0N(n1469), .A1N(Add_result[13]), .B0(n1441), .Y(n215)
);
AOI22X1TS U1832 ( .A0(Sgf_normalized_result[14]), .A1(n1463), .B0(
Add_result[15]), .B1(n403), .Y(n1442) );
OAI2BB1X1TS U1833 ( .A0N(P_Sgf[38]), .A1N(n1465), .B0(n1442), .Y(n1443) );
AOI21X1TS U1834 ( .A0(n1257), .A1(P_Sgf[37]), .B0(n1443), .Y(n1444) );
OAI2BB1X1TS U1835 ( .A0N(n1469), .A1N(Add_result[14]), .B0(n1444), .Y(n216)
);
AOI22X1TS U1836 ( .A0(Sgf_normalized_result[15]), .A1(n1463), .B0(
Add_result[16]), .B1(n403), .Y(n1445) );
OAI2BB1X1TS U1837 ( .A0N(P_Sgf[39]), .A1N(n1465), .B0(n1445), .Y(n1446) );
AOI21X1TS U1838 ( .A0(n1257), .A1(P_Sgf[38]), .B0(n1446), .Y(n1447) );
OAI2BB1X1TS U1839 ( .A0N(n1469), .A1N(Add_result[15]), .B0(n1447), .Y(n217)
);
AOI22X1TS U1840 ( .A0(Sgf_normalized_result[16]), .A1(n1463), .B0(
Add_result[17]), .B1(n403), .Y(n1448) );
OAI2BB1X1TS U1841 ( .A0N(P_Sgf[40]), .A1N(n1465), .B0(n1448), .Y(n1449) );
AOI21X1TS U1842 ( .A0(n1257), .A1(P_Sgf[39]), .B0(n1449), .Y(n1450) );
OAI2BB1X1TS U1843 ( .A0N(n1469), .A1N(Add_result[16]), .B0(n1450), .Y(n218)
);
AOI22X1TS U1844 ( .A0(Sgf_normalized_result[17]), .A1(n1463), .B0(
Add_result[18]), .B1(n404), .Y(n1451) );
OAI2BB1X1TS U1845 ( .A0N(P_Sgf[41]), .A1N(n1465), .B0(n1451), .Y(n1452) );
AOI21X1TS U1846 ( .A0(n1467), .A1(P_Sgf[40]), .B0(n1452), .Y(n1453) );
OAI2BB1X1TS U1847 ( .A0N(n1469), .A1N(Add_result[17]), .B0(n1453), .Y(n219)
);
AOI22X1TS U1848 ( .A0(Sgf_normalized_result[18]), .A1(n1463), .B0(
Add_result[19]), .B1(n403), .Y(n1454) );
OAI2BB1X1TS U1849 ( .A0N(P_Sgf[42]), .A1N(n1465), .B0(n1454), .Y(n1455) );
AOI21X1TS U1850 ( .A0(n1467), .A1(P_Sgf[41]), .B0(n1455), .Y(n1456) );
OAI2BB1X1TS U1851 ( .A0N(n1469), .A1N(Add_result[18]), .B0(n1456), .Y(n220)
);
AOI22X1TS U1852 ( .A0(Sgf_normalized_result[19]), .A1(n1463), .B0(
Add_result[20]), .B1(n404), .Y(n1457) );
OAI2BB1X1TS U1853 ( .A0N(P_Sgf[43]), .A1N(n1465), .B0(n1457), .Y(n1458) );
AOI21X1TS U1854 ( .A0(n1467), .A1(P_Sgf[42]), .B0(n1458), .Y(n1459) );
OAI2BB1X1TS U1855 ( .A0N(n1469), .A1N(Add_result[19]), .B0(n1459), .Y(n221)
);
AOI22X1TS U1856 ( .A0(Sgf_normalized_result[20]), .A1(n1463), .B0(
Add_result[21]), .B1(n404), .Y(n1460) );
OAI2BB1X1TS U1857 ( .A0N(P_Sgf[44]), .A1N(n1465), .B0(n1460), .Y(n1461) );
AOI21X1TS U1858 ( .A0(n1467), .A1(P_Sgf[43]), .B0(n1461), .Y(n1462) );
OAI2BB1X1TS U1859 ( .A0N(n1469), .A1N(Add_result[20]), .B0(n1462), .Y(n222)
);
AOI22X1TS U1860 ( .A0(Sgf_normalized_result[21]), .A1(n1463), .B0(
Add_result[22]), .B1(n404), .Y(n1464) );
OAI2BB1X1TS U1861 ( .A0N(P_Sgf[45]), .A1N(n1465), .B0(n1464), .Y(n1466) );
AOI21X1TS U1862 ( .A0(n1467), .A1(P_Sgf[44]), .B0(n1466), .Y(n1468) );
OAI2BB1X1TS U1863 ( .A0N(n1469), .A1N(Add_result[21]), .B0(n1468), .Y(n223)
);
AO22XLTS U1864 ( .A0(n420), .A1(Data_MY[31]), .B0(n1474), .B1(Op_MY[31]),
.Y(n381) );
AOI32X1TS U1865 ( .A0(FS_Module_state_reg[1]), .A1(n1557), .A2(
FS_Module_state_reg[0]), .B0(FS_Module_state_reg[2]), .B1(n1470), .Y(
n1473) );
AO22XLTS U1866 ( .A0(n420), .A1(Data_MX[31]), .B0(n1474), .B1(Op_MX[31]),
.Y(n343) );
NOR4X1TS U1867 ( .A(Op_MY[19]), .B(Op_MY[18]), .C(Op_MY[16]), .D(Op_MY[15]),
.Y(n1478) );
NOR4X1TS U1868 ( .A(Op_MY[27]), .B(Op_MY[26]), .C(Op_MY[25]), .D(Op_MY[24]),
.Y(n1476) );
NOR4X1TS U1869 ( .A(Op_MY[30]), .B(Op_MY[29]), .C(Op_MY[17]), .D(Op_MY[28]),
.Y(n1475) );
NAND4XLTS U1870 ( .A(n1478), .B(n1477), .C(n1476), .D(n1475), .Y(n1494) );
NOR4X1TS U1871 ( .A(Op_MY[9]), .B(Op_MY[6]), .C(Op_MY[4]), .D(Op_MY[1]), .Y(
n1482) );
NOR4X1TS U1872 ( .A(Op_MY[10]), .B(Op_MY[8]), .C(Op_MY[3]), .D(Op_MY[2]),
.Y(n1481) );
NOR4X1TS U1873 ( .A(Op_MY[7]), .B(Op_MY[5]), .C(Op_MY[13]), .D(Op_MY[0]),
.Y(n1480) );
NAND4XLTS U1874 ( .A(n1482), .B(n1481), .C(n1480), .D(n1479), .Y(n1493) );
NOR4X1TS U1875 ( .A(Op_MX[20]), .B(Op_MX[18]), .C(Op_MX[16]), .D(Op_MX[14]),
.Y(n1485) );
NOR4X1TS U1876 ( .A(Op_MX[27]), .B(Op_MX[26]), .C(Op_MX[25]), .D(Op_MX[23]),
.Y(n1484) );
NAND4XLTS U1877 ( .A(n1486), .B(n1485), .C(n1484), .D(n1483), .Y(n1492) );
NOR4X1TS U1878 ( .A(Op_MX[10]), .B(Op_MX[8]), .C(Op_MX[6]), .D(Op_MX[4]),
.Y(n1489) );
NAND4XLTS U1879 ( .A(n1490), .B(n1489), .C(n1488), .D(n1487), .Y(n1491) );
OAI22X1TS U1880 ( .A0(n1494), .A1(n1493), .B0(n1492), .B1(n1491), .Y(n1495)
);
AO22XLTS U1881 ( .A0(n1497), .A1(zero_flag), .B0(n1496), .B1(n1495), .Y(n311) );
AOI2BB2XLTS U1882 ( .B0(n1539), .B1(Sgf_normalized_result[0]), .A0N(
Add_result[0]), .A1N(n1550), .Y(n309) );
NOR2XLTS U1883 ( .A(Sgf_normalized_result[1]), .B(Sgf_normalized_result[0]),
.Y(n1502) );
AOI21X1TS U1884 ( .A0(Sgf_normalized_result[0]), .A1(
Sgf_normalized_result[1]), .B0(n1502), .Y(n1503) );
AOI2BB2XLTS U1885 ( .B0(n1539), .B1(n1503), .A0N(Add_result[1]), .A1N(n1550),
.Y(n308) );
OR3X1TS U1886 ( .A(Sgf_normalized_result[2]), .B(Sgf_normalized_result[1]),
.C(Sgf_normalized_result[0]), .Y(n1505) );
AOI32X1TS U1887 ( .A0(n1505), .A1(n1539), .A2(n1504), .B0(n1573), .B1(n1545),
.Y(n307) );
BUFX4TS U1888 ( .A(n1545), .Y(n1544) );
NAND2X1TS U1889 ( .A(Sgf_normalized_result[3]), .B(n1505), .Y(n1507) );
OAI211XLTS U1890 ( .A0(Sgf_normalized_result[3]), .A1(n1505), .B0(n1539),
.C0(n1507), .Y(n1506) );
OAI2BB1X1TS U1891 ( .A0N(Add_result[3]), .A1N(n1544), .B0(n1506), .Y(n306)
);
NAND2X1TS U1892 ( .A(n1559), .B(n1507), .Y(n1509) );
OAI21XLTS U1893 ( .A0(n1507), .A1(n1559), .B0(n1509), .Y(n1508) );
OAI211XLTS U1894 ( .A0(Sgf_normalized_result[5]), .A1(n1509), .B0(n1539),
.C0(n1511), .Y(n1510) );
OAI2BB1X1TS U1895 ( .A0N(Add_result[5]), .A1N(n1544), .B0(n1510), .Y(n304)
);
AOI21X1TS U1896 ( .A0(n1560), .A1(n1511), .B0(n1513), .Y(n1512) );
OAI2BB1X1TS U1897 ( .A0N(Add_result[7]), .A1N(n1544), .B0(n1514), .Y(n302)
);
AOI21X1TS U1898 ( .A0(n1561), .A1(n1515), .B0(n407), .Y(n1516) );
OAI2BB1X1TS U1899 ( .A0N(Add_result[9]), .A1N(n1545), .B0(n1517), .Y(n300)
);
AOI21X1TS U1900 ( .A0(n1562), .A1(n1518), .B0(n406), .Y(n1519) );
OAI2BB1X1TS U1901 ( .A0N(Add_result[11]), .A1N(n1545), .B0(n1520), .Y(n298)
);
AOI21X1TS U1902 ( .A0(n1563), .A1(n1521), .B0(n1523), .Y(n1522) );
OAI2BB1X1TS U1903 ( .A0N(Add_result[13]), .A1N(n1545), .B0(n1524), .Y(n296)
);
AOI21X1TS U1904 ( .A0(n1564), .A1(n1525), .B0(n1527), .Y(n1526) );
OAI2BB1X1TS U1905 ( .A0N(Add_result[15]), .A1N(n1544), .B0(n1528), .Y(n294)
);
AOI21X1TS U1906 ( .A0(n1567), .A1(n1529), .B0(n1531), .Y(n1530) );
OAI2BB1X1TS U1907 ( .A0N(Add_result[17]), .A1N(n1545), .B0(n1532), .Y(n292)
);
AOI21X1TS U1908 ( .A0(n1568), .A1(n1533), .B0(n1535), .Y(n1534) );
OAI2BB1X1TS U1909 ( .A0N(Add_result[19]), .A1N(n1545), .B0(n1536), .Y(n290)
);
NOR2X2TS U1910 ( .A(n1570), .B(n1537), .Y(n1540) );
AOI21X1TS U1911 ( .A0(n1570), .A1(n1537), .B0(n1540), .Y(n1538) );
OAI2BB1X1TS U1912 ( .A0N(Add_result[21]), .A1N(n1544), .B0(n1541), .Y(n288)
);
NOR2X2TS U1913 ( .A(n1571), .B(n1542), .Y(n1546) );
AOI21X1TS U1914 ( .A0(n1546), .A1(Sgf_normalized_result[23]), .B0(n1545),
.Y(n1549) );
OAI2BB1X1TS U1915 ( .A0N(Add_result[23]), .A1N(n1548), .B0(n1547), .Y(n286)
);
AO22XLTS U1916 ( .A0(Sgf_normalized_result[0]), .A1(n1553), .B0(
final_result_ieee[0]), .B1(n1554), .Y(n200) );
AO22XLTS U1917 ( .A0(Sgf_normalized_result[1]), .A1(n1553), .B0(
final_result_ieee[1]), .B1(n1554), .Y(n199) );
AO22XLTS U1918 ( .A0(Sgf_normalized_result[2]), .A1(n1553), .B0(
final_result_ieee[2]), .B1(n1552), .Y(n198) );
AO22XLTS U1919 ( .A0(Sgf_normalized_result[3]), .A1(n1553), .B0(
final_result_ieee[3]), .B1(n1552), .Y(n197) );
AO22XLTS U1920 ( .A0(Sgf_normalized_result[4]), .A1(n1553), .B0(
final_result_ieee[4]), .B1(n1552), .Y(n196) );
AO22XLTS U1921 ( .A0(Sgf_normalized_result[5]), .A1(n1553), .B0(
final_result_ieee[5]), .B1(n1552), .Y(n195) );
AO22XLTS U1922 ( .A0(Sgf_normalized_result[6]), .A1(n1553), .B0(
final_result_ieee[6]), .B1(n1552), .Y(n194) );
AO22XLTS U1923 ( .A0(Sgf_normalized_result[7]), .A1(n1553), .B0(
final_result_ieee[7]), .B1(n1552), .Y(n193) );
AO22XLTS U1924 ( .A0(Sgf_normalized_result[8]), .A1(n1553), .B0(
final_result_ieee[8]), .B1(n1552), .Y(n192) );
AO22XLTS U1925 ( .A0(Sgf_normalized_result[9]), .A1(n1553), .B0(
final_result_ieee[9]), .B1(n1552), .Y(n191) );
AO22XLTS U1926 ( .A0(Sgf_normalized_result[10]), .A1(n1553), .B0(
final_result_ieee[10]), .B1(n1552), .Y(n190) );
AO22XLTS U1927 ( .A0(Sgf_normalized_result[11]), .A1(n1553), .B0(
final_result_ieee[11]), .B1(n1552), .Y(n189) );
AO22XLTS U1928 ( .A0(Sgf_normalized_result[12]), .A1(n1553), .B0(
final_result_ieee[12]), .B1(n1554), .Y(n188) );
INVX2TS U1929 ( .A(n1551), .Y(n1555) );
AO22XLTS U1930 ( .A0(Sgf_normalized_result[13]), .A1(n1555), .B0(
final_result_ieee[13]), .B1(n1554), .Y(n187) );
AO22XLTS U1931 ( .A0(Sgf_normalized_result[14]), .A1(n1555), .B0(
final_result_ieee[14]), .B1(n1554), .Y(n186) );
AO22XLTS U1932 ( .A0(Sgf_normalized_result[15]), .A1(n1555), .B0(
final_result_ieee[15]), .B1(n1554), .Y(n185) );
AO22XLTS U1933 ( .A0(Sgf_normalized_result[16]), .A1(n1555), .B0(
final_result_ieee[16]), .B1(n1554), .Y(n184) );
AO22XLTS U1934 ( .A0(Sgf_normalized_result[17]), .A1(n1555), .B0(
final_result_ieee[17]), .B1(n1554), .Y(n183) );
AO22XLTS U1935 ( .A0(Sgf_normalized_result[18]), .A1(n1555), .B0(
final_result_ieee[18]), .B1(n1554), .Y(n182) );
AO22XLTS U1936 ( .A0(Sgf_normalized_result[19]), .A1(n1555), .B0(
final_result_ieee[19]), .B1(n1554), .Y(n181) );
AO22XLTS U1937 ( .A0(Sgf_normalized_result[20]), .A1(n1555), .B0(
final_result_ieee[20]), .B1(n1554), .Y(n180) );
AO22XLTS U1938 ( .A0(Sgf_normalized_result[21]), .A1(n1555), .B0(
final_result_ieee[21]), .B1(n1554), .Y(n179) );
AO22XLTS U1939 ( .A0(Sgf_normalized_result[22]), .A1(n1555), .B0(
final_result_ieee[22]), .B1(n1554), .Y(n178) );
OA22X1TS U1940 ( .A0(n1556), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n1551), .Y(n177) );
OA22X1TS U1941 ( .A0(n1556), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n1551), .Y(n176) );
OA22X1TS U1942 ( .A0(n1556), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n1551), .Y(n175) );
OA22X1TS U1943 ( .A0(n1556), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n1551), .Y(n174) );
OA22X1TS U1944 ( .A0(n1556), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n1551), .Y(n172) );
OA22X1TS U1945 ( .A0(n1556), .A1(final_result_ieee[29]), .B0(
exp_oper_result[6]), .B1(n1551), .Y(n171) );
OA22X1TS U1946 ( .A0(n1556), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n1551), .Y(n170) );
CMPR42X2TS U1947 ( .A(DP_OP_110J3_122_4535_n39), .B(DP_OP_110J3_122_4535_n44), .C(DP_OP_110J3_122_4535_n40), .D(DP_OP_110J3_122_4535_n41), .ICI(
Sgf_operation_EVEN1_Q_left[23]), .S(DP_OP_110J3_122_4535_n37), .ICO(
DP_OP_110J3_122_4535_n35), .CO(DP_OP_110J3_122_4535_n36) );
CMPR42X2TS U1948 ( .A(DP_OP_110J3_122_4535_n137), .B(
DP_OP_110J3_122_4535_n257), .C(DP_OP_110J3_122_4535_n270), .D(
DP_OP_110J3_122_4535_n133), .ICI(DP_OP_110J3_122_4535_n516), .S(
DP_OP_110J3_122_4535_n124), .ICO(DP_OP_110J3_122_4535_n122), .CO(
DP_OP_110J3_122_4535_n123) );
CMPR42X2TS U1949 ( .A(DP_OP_110J3_122_4535_n225), .B(
DP_OP_110J3_122_4535_n127), .C(DP_OP_110J3_122_4535_n130), .D(
DP_OP_110J3_122_4535_n134), .ICI(DP_OP_110J3_122_4535_n124), .S(
DP_OP_110J3_122_4535_n121), .ICO(DP_OP_110J3_122_4535_n119), .CO(
DP_OP_110J3_122_4535_n120) );
CMPR42X1TS U1950 ( .A(DP_OP_110J3_122_4535_n266), .B(
DP_OP_110J3_122_4535_n92), .C(DP_OP_110J3_122_4535_n85), .D(
DP_OP_110J3_122_4535_n93), .ICI(DP_OP_110J3_122_4535_n89), .S(
DP_OP_110J3_122_4535_n82), .ICO(DP_OP_110J3_122_4535_n80), .CO(
DP_OP_110J3_122_4535_n81) );
CMPR42X1TS U1951 ( .A(DP_OP_110J3_122_4535_n246), .B(
DP_OP_110J3_122_4535_n259), .C(DP_OP_110J3_122_4535_n38), .D(
DP_OP_110J3_122_4535_n35), .ICI(n721), .S(DP_OP_110J3_122_4535_n34),
.ICO(DP_OP_110J3_122_4535_n32), .CO(DP_OP_110J3_122_4535_n33) );
CMPR42X2TS U1952 ( .A(DP_OP_110J3_122_4535_n103), .B(
DP_OP_110J3_122_4535_n104), .C(DP_OP_110J3_122_4535_n100), .D(
DP_OP_110J3_122_4535_n94), .ICI(n689), .S(DP_OP_110J3_122_4535_n91),
.ICO(DP_OP_110J3_122_4535_n89), .CO(DP_OP_110J3_122_4535_n90) );
CMPR42X2TS U1953 ( .A(DP_OP_110J3_122_4535_n174), .B(
DP_OP_110J3_122_4535_n229), .C(DP_OP_110J3_122_4535_n520), .D(
DP_OP_110J3_122_4535_n168), .ICI(DP_OP_110J3_122_4535_n175), .S(
DP_OP_110J3_122_4535_n166), .ICO(DP_OP_110J3_122_4535_n164), .CO(
DP_OP_110J3_122_4535_n165) );
CMPR42X2TS U1954 ( .A(DP_OP_110J3_122_4535_n268), .B(
DP_OP_110J3_122_4535_n115), .C(DP_OP_110J3_122_4535_n111), .D(n686),
.ICI(DP_OP_110J3_122_4535_n105), .S(DP_OP_110J3_122_4535_n102), .ICO(
DP_OP_110J3_122_4535_n100), .CO(DP_OP_110J3_122_4535_n101) );
CMPR42X1TS U1955 ( .A(DP_OP_110J3_122_4535_n301), .B(
DP_OP_110J3_122_4535_n178), .C(DP_OP_110J3_122_4535_n230), .D(
DP_OP_110J3_122_4535_n288), .ICI(DP_OP_110J3_122_4535_n183), .S(
DP_OP_110J3_122_4535_n176), .ICO(DP_OP_110J3_122_4535_n174), .CO(
DP_OP_110J3_122_4535_n175) );
CMPR42X2TS U1956 ( .A(DP_OP_110J3_122_4535_n116), .B(
DP_OP_110J3_122_4535_n224), .C(DP_OP_110J3_122_4535_n123), .D(
DP_OP_110J3_122_4535_n119), .ICI(DP_OP_110J3_122_4535_n113), .S(
DP_OP_110J3_122_4535_n110), .ICO(DP_OP_110J3_122_4535_n108), .CO(
DP_OP_110J3_122_4535_n109) );
CMPR42X2TS U1957 ( .A(DP_OP_110J3_122_4535_n283), .B(
DP_OP_110J3_122_4535_n335), .C(DP_OP_110J3_122_4535_n129), .D(
DP_OP_110J3_122_4535_n136), .ICI(DP_OP_110J3_122_4535_n322), .S(
DP_OP_110J3_122_4535_n127), .ICO(DP_OP_110J3_122_4535_n125), .CO(
DP_OP_110J3_122_4535_n126) );
CMPR42X1TS U1958 ( .A(DP_OP_110J3_122_4535_n117), .B(
DP_OP_110J3_122_4535_n107), .C(DP_OP_110J3_122_4535_n114), .D(
DP_OP_110J3_122_4535_n307), .ICI(DP_OP_110J3_122_4535_n255), .S(
DP_OP_110J3_122_4535_n105), .ICO(DP_OP_110J3_122_4535_n103), .CO(
DP_OP_110J3_122_4535_n104) );
CMPR42X1TS U1959 ( .A(DP_OP_110J3_122_4535_n734), .B(
DP_OP_110J3_122_4535_n653), .C(DP_OP_110J3_122_4535_n649), .D(
DP_OP_110J3_122_4535_n647), .ICI(DP_OP_110J3_122_4535_n650), .S(
DP_OP_110J3_122_4535_n645), .ICO(DP_OP_110J3_122_4535_n643), .CO(
DP_OP_110J3_122_4535_n644) );
CMPR42X2TS U1960 ( .A(n696), .B(DP_OP_110J3_122_4535_n73), .C(
DP_OP_110J3_122_4535_n77), .D(DP_OP_110J3_122_4535_n220), .ICI(n673),
.S(DP_OP_110J3_122_4535_n70), .ICO(DP_OP_110J3_122_4535_n68), .CO(
DP_OP_110J3_122_4535_n69) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk20.tcl_KOA_1STAGE_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O21AI_FUNCTIONAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21AI_FUNCTIONAL_PP_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 18 23:18:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_stub.v
// Design : system_xlconstant_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_xlconstant_0_0(dout)
/* synthesis syn_black_box black_box_pad_pin="dout[0:0]" */;
output [0:0]dout;
endmodule
|
module rc4_tb();
wire control_out;
wire [7:0] streamvalue;
reg clk, rst_n, control_in, write, read;
reg [7:0] keylength, keydata;
rc4 U1(
.control_out(control_out),
.streamvalue(streamvalue),
.clk(clk),
.rst_n(rst_n),
.control_in(control_in),
.keylength(keylength),
.keydata(keydata),
.write(write),
.read(read)
);
initial begin
clk = 0;
rst_n = 1;
control_in = 0; write = 0;
keylength = 8'b0;
keydata = 8'b0;
write = 0;
read = 0;
#1;
keylength = 3;
keydata = 75;
write = 1;
#1 write = 0;
#9;
keydata = 101;
write = 1;
#1 write = 0;
#9;
keydata = 121;
write = 1;
#1 write = 0;
#1525;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
end
always @(posedge clk) begin
/*if (control_out) begin
control_in = 0; write = 0;
end*/
end
always #1 clk = ~clk;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/*`include "sys.h"
`include "iop.h"
`include "ifu.h"
`include "tlu.h"
`include "lsu.h"
*/
`define PCX_WIDTH 124 //PCX payload packet width
`define CPX_WIDTH 145 //CPX payload packet width
module sparc (/*AUTOARG*/
// Outputs
spc_pcx_req_pq, spc_pcx_atom_pq, spc_pcx_data_pa, spc_sscan_so,
spc_scanout0, spc_scanout1, tst_ctu_mbist_done,
tst_ctu_mbist_fail, spc_efc_ifuse_data, spc_efc_dfuse_data,
// Inputs
pcx_spc_grant_px, cpx_spc_data_rdy_cx2, cpx_spc_data_cx2,
const_cpuid, const_maskid, ctu_tck, ctu_sscan_se, ctu_sscan_snap,
ctu_sscan_tid, ctu_tst_mbist_enable, efc_spc_fuse_clk1,
efc_spc_fuse_clk2, efc_spc_ifuse_ashift, efc_spc_ifuse_dshift,
efc_spc_ifuse_data, efc_spc_dfuse_ashift, efc_spc_dfuse_dshift,
efc_spc_dfuse_data, ctu_tst_macrotest, ctu_tst_scan_disable,
ctu_tst_short_chain, global_shift_enable, ctu_tst_scanmode,
spc_scanin0, spc_scanin1, cluster_cken, gclk, cmp_grst_l,
cmp_arst_l, ctu_tst_pre_grst_l, adbginit_l, gdbginit_l
);
// these are the only legal IOs
// pcx
output [4:0] spc_pcx_req_pq; // processor to pcx request
output spc_pcx_atom_pq; // processor to pcx atomic request
output [`PCX_WIDTH-1:0] spc_pcx_data_pa; // processor to pcx packet
// shadow scan
output spc_sscan_so; // From ifu of sparc_ifu.v
output spc_scanout0; // From test_stub of test_stub_bist.v
output spc_scanout1; // From test_stub of test_stub_bist.v
// bist
output tst_ctu_mbist_done; // From test_stub of test_stub_two_bist.v
output tst_ctu_mbist_fail; // From test_stub of test_stub_two_bist.v
// fuse
output spc_efc_ifuse_data; // From ifu of sparc_ifu.v
output spc_efc_dfuse_data; // From ifu of sparc_ifu.v
// cpx interface
input [4:0] pcx_spc_grant_px; // pcx to processor grant info
input cpx_spc_data_rdy_cx2; // cpx data inflight to sparc
input [`CPX_WIDTH-1:0] cpx_spc_data_cx2; // cpx to sparc data packet
input [3:0] const_cpuid;
input [7:0] const_maskid; // To ifu of sparc_ifu.v
// sscan
input ctu_tck; // To ifu of sparc_ifu.v
input ctu_sscan_se; // To ifu of sparc_ifu.v
input ctu_sscan_snap; // To ifu of sparc_ifu.v
input [3:0] ctu_sscan_tid; // To ifu of sparc_ifu.v
// bist
input ctu_tst_mbist_enable; // To test_stub of test_stub_bist.v
// efuse
input efc_spc_fuse_clk1;
input efc_spc_fuse_clk2;
input efc_spc_ifuse_ashift;
input efc_spc_ifuse_dshift;
input efc_spc_ifuse_data;
input efc_spc_dfuse_ashift;
input efc_spc_dfuse_dshift;
input efc_spc_dfuse_data;
// scan and macro test
input ctu_tst_macrotest; // To test_stub of test_stub_bist.v
input ctu_tst_scan_disable; // To test_stub of test_stub_bist.v
input ctu_tst_short_chain; // To test_stub of test_stub_bist.v
input global_shift_enable; // To test_stub of test_stub_two_bist.v
input ctu_tst_scanmode; // To test_stub of test_stub_two_bist.v
input spc_scanin0;
input spc_scanin1;
// clk
input cluster_cken; // To spc_hdr of cluster_header.v
input gclk; // To spc_hdr of cluster_header.v
// reset
input cmp_grst_l;
input cmp_arst_l;
input ctu_tst_pre_grst_l; // To test_stub of test_stub_bist.v
input adbginit_l; // To spc_hdr of cluster_header.v
input gdbginit_l; // To spc_hdr of cluster_header.v
// ----------------- End of IOs -------------------------- //
endmodule // sparc
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog wrapper for clkdlybuf4s18 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkdlybuf4s18.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s18_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkdlybuf4s18 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s18_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkdlybuf4s18 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_AVMM_DATA_CONTROLLER (PARALLEL-to-PARALLEL MODE)
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_avmm_data_controller (
// To/From System
clock,
reset_n,
// To/From Flash IP interface
flash_busy,
flash_se_pass,
flash_sp_pass,
flash_osc,
flash_drdout,
flash_xe_ye,
flash_se,
flash_arclk,
flash_arshft,
flash_drclk,
flash_drshft,
flash_drdin,
flash_nprogram,
flash_nerase,
flash_ardin,
// To/From Avalon_MM data slave interface
avmm_read,
avmm_write,
avmm_addr,
avmm_writedata,
avmm_burstcount,
avmm_waitrequest,
avmm_readdatavalid,
avmm_readdata,
// To/From Avalon_MM csr slave interface
csr_control,
csr_status
);
parameter READ_AND_WRITE_MODE = 0;
parameter WRAPPING_BURST_MODE = 0;
parameter DATA_WIDTH = 32;
parameter AVMM_DATA_ADDR_WIDTH = 20;
parameter AVMM_DATA_BURSTCOUNT_WIDTH = 4;
parameter FLASH_ADDR_WIDTH = 23;
parameter FLASH_SEQ_READ_DATA_COUNT = 2; //number of 32-bit data per sequential read
parameter FLASH_READ_CYCLE_MAX_INDEX = 3; //period to for each sequential read
parameter FLASH_ADDR_ALIGNMENT_BITS = 1; //number of last addr bits for alignment
parameter FLASH_RESET_CYCLE_MAX_INDEX = 28; //period that required by flash before back to idle for erase and program operation
parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (1200ns)
parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
localparam [1:0] ERASE_ST_IDLE = 0,
ERASE_ST_PENDING = 1,
ERASE_ST_BUSY = 2;
localparam [1:0] STATUS_IDLE = 0,
STATUS_BUSY_ERASE = 1,
STATUS_BUSY_WRITE = 2,
STATUS_BUSY_READ = 3;
localparam [2:0] WRITE_STATE_IDLE = 0,
WRITE_STATE_ADDR = 1,
WRITE_STATE_WRITE = 2,
WRITE_STATE_WAIT_BUSY = 3,
WRITE_STATE_WAIT_DONE = 4,
WRITE_STATE_RESET = 5,
WRITE_STATE_ERROR = 6;
localparam [2:0] ERASE_STATE_IDLE = 0,
ERASE_STATE_ADDR = 1,
ERASE_STATE_WAIT_BUSY = 2,
ERASE_STATE_WAIT_DONE = 3,
ERASE_STATE_RESET = 4,
ERASE_STATE_ERROR = 5;
localparam [2:0] READ_STATE_IDLE = 0,
READ_STATE_ADDR = 1,
READ_STATE_READ = 2,
READ_STATE_SETUP = 2,
READ_STATE_DUMMY = 3,
READ_STATE_READY = 4,
READ_STATE_FINAL = 5,
READ_STATE_CLEAR = 6,
READ_STATE_PULSE_SE = 7;
localparam [0:0] READ_SETUP = 0,
READ_RECV_DATA = 1;
localparam [1:0] READ_VALID_IDLE = 0,
READ_VALID_READING = 1,
READ_VALID_PRE_READING = 2;
// To/From System
input clock;
input reset_n;
// To/From Flash IP interface
input flash_busy;
input flash_se_pass;
input flash_sp_pass;
input flash_osc;
input [DATA_WIDTH-1:0] flash_drdout;
output flash_xe_ye;
output flash_se;
output flash_arclk;
output flash_arshft;
output flash_drclk;
output flash_drshft;
output flash_drdin;
output flash_nprogram;
output flash_nerase;
output [FLASH_ADDR_WIDTH-1:0] flash_ardin;
// To/From Avalon_MM data slave interface
input avmm_read;
input avmm_write;
input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_addr;
input [DATA_WIDTH-1:0] avmm_writedata;
input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount;
output avmm_waitrequest;
output avmm_readdatavalid;
output reg [DATA_WIDTH-1:0] avmm_readdata;
// To/From Avalon_MM csr slave interface
input [31:0] csr_control;
output [9:0] csr_status;
reg reset_n_reg1;
reg reset_n_reg2;
reg [1:0] csr_status_busy;
reg csr_status_e_pass;
reg csr_status_w_pass;
reg csr_status_r_pass;
reg [2:0] erase_state;
reg [2:0] write_state;
reg [2:0] read_state;
reg avmm_read_state;
reg [1:0] avmm_read_valid_state;
reg avmm_readdatavalid_reg;
reg avmm_readdata_ready;
reg [2:0] flash_sector_addr;
reg [FLASH_ADDR_WIDTH-1:0] flash_page_addr;
reg [FLASH_ADDR_WIDTH-1:0] flash_seq_read_ardin;
reg [FLASH_ADDR_WIDTH-1:0] flash_addr_wire_neg_reg;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_reg;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_backup_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_input_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_reg;
reg write_drclk_en;
reg read_drclk_en;
reg enable_arclk_sync_reg;
reg enable_arclk_neg_reg;
reg enable_arclk_neg_pos_reg;
reg enable_drclk_neg_reg;
reg enable_drclk_neg_pos_reg;
reg enable_drclk_neg_pos_write_reg;
reg flash_drdin_neg_reg;
reg [15:0] write_count;
reg [25:0] erase_count;
reg [2:0] read_count;
reg [2:0] read_ctrl_count;
reg [2:0] data_count;
reg write_timeout;
reg write_wait;
reg write_wait_neg;
reg erase_timeout;
reg read_wait;
reg read_wait_neg;
reg flash_drshft_reg;
reg flash_drshft_neg_reg;
reg flash_se_neg_reg;
reg flash_se_pass_reg;
reg flash_sp_pass_reg;
reg flash_busy_reg;
reg flash_busy_clear_reg;
reg erase_busy_scan;
reg write_busy_scan;
reg is_sector1_writable_reg;
reg is_sector2_writable_reg;
reg is_sector3_writable_reg;
reg is_sector4_writable_reg;
reg is_sector5_writable_reg;
wire reset_n_w;
wire is_addr_within_valid_range;
wire is_addr_writable;
wire is_sector_writable;
wire is_erase_addr_writable;
wire [2:0] cur_e_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_a_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] flash_addr_wire;
wire [FLASH_ADDR_WIDTH-1:0] flash_page_addr_wire;
wire [2:0] flash_sector_wire;
wire is_valid_write_burst_count;
wire is_erase_busy;
wire is_write_busy;
wire is_read_busy;
wire [FLASH_ADDR_WIDTH-1:0] flash_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] next_flash_read_ardin;
wire [19:0] csr_page_erase_addr;
wire [2:0] csr_sector_erase_addr;
wire valid_csr_sector_erase_addr;
wire [1:0] csr_erase_state;
wire [4:0] csr_write_protection_mode;
wire valid_csr_erase;
wire valid_command;
wire flash_drdin_w;
wire flash_arclk_arshft_en_w;
wire flash_se_w;
wire is_busy;
wire write_wait_w;
wire read_wait_w;
wire flash_busy_sync;
wire flash_busy_clear_sync;
generate // generate combi based on read and write mode
if (READ_AND_WRITE_MODE == 1) begin
assign is_erase_busy = (erase_state != ERASE_STATE_IDLE);
assign is_write_busy = (write_state != WRITE_STATE_IDLE);
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_erase_busy || is_write_busy || is_read_busy;
assign flash_drdin = flash_drdin_neg_reg;
assign write_wait_w = (write_wait || write_wait_neg);
assign is_erase_addr_writable =
(valid_csr_erase && valid_csr_sector_erase_addr) ? is_sector_writable : is_addr_writable;
assign csr_write_protection_mode = csr_control[27:23];
assign is_valid_write_burst_count = (avmm_burstcount == 1);
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_addr_wire_neg_reg <= 0;
end
else if (valid_csr_erase && valid_csr_sector_erase_addr) begin
flash_addr_wire_neg_reg <= { flash_sector_addr, 1'b0, {(19){1'b1}}};
end
else begin
flash_addr_wire_neg_reg <= flash_page_addr;
end
end
end
else begin
assign is_erase_busy = 1'b0;
assign is_write_busy = 1'b0;
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_read_busy;
assign flash_drdin = 1'b1;
assign write_wait_w = 1'b0;
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_addr_wire_neg_reg <= 0;
end
else begin
flash_addr_wire_neg_reg <= flash_page_addr;
end
end
end
endgenerate
assign csr_status = { SECTOR_READ_PROTECTION_MODE[4:0], csr_status_e_pass, csr_status_w_pass, csr_status_r_pass, csr_status_busy};
assign csr_page_erase_addr = csr_control[19:0];
assign csr_sector_erase_addr = csr_control[22:20];
assign csr_erase_state = csr_control[31:30];
assign valid_csr_sector_erase_addr = (csr_sector_erase_addr != {(3){1'b1}});
assign valid_csr_erase = (csr_erase_state == ERASE_ST_PENDING);
assign valid_command = (valid_csr_erase == 1) || (avmm_write == 1);
assign cur_read_addr = avmm_addr;
assign read_wait_w = (read_wait || read_wait_neg);
generate // generate combi based on read burst mode
if (WRAPPING_BURST_MODE == 0) begin
// incrementing read
assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
assign cur_e_addr = csr_sector_erase_addr;
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : flash_read_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (is_read_busy && (read_state == READ_STATE_FINAL || read_state == READ_STATE_ADDR));
assign flash_se_w = (read_state == READ_STATE_SETUP);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
assign next_flash_read_ardin = {flash_seq_read_ardin[FLASH_ADDR_WIDTH-1:FLASH_ADDR_ALIGNMENT_BITS], {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}}} + FLASH_SEQ_READ_DATA_COUNT[22:0];
end
else begin
// wrapping read
assign cur_e_addr = csr_sector_erase_addr;
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : avmm_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (read_wait && read_ctrl_count <= 1 && avmm_read);
assign flash_se_w = (read_state == READ_STATE_READ && read_ctrl_count==FLASH_READ_CYCLE_MAX_INDEX+1);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
end
endgenerate
assign flash_arshft = 1'b1;
assign flash_drshft = flash_drshft_neg_reg;
assign flash_arclk = (~enable_arclk_neg_reg || clock || enable_arclk_neg_pos_reg);
assign flash_drclk = (~enable_drclk_neg_reg || clock || enable_drclk_neg_pos_reg || enable_drclk_neg_pos_write_reg);
assign flash_nerase = ~(erase_state == ERASE_STATE_WAIT_BUSY || erase_state == ERASE_STATE_WAIT_DONE);
assign flash_nprogram = ~(write_state == WRITE_STATE_WAIT_BUSY || write_state == WRITE_STATE_WAIT_DONE);
assign flash_xe_ye = ((~is_busy && avmm_read) || is_read_busy);
assign flash_se = flash_se_neg_reg;
assign flash_ardin = flash_addr_wire_neg_reg;
assign avmm_readdatavalid = avmm_readdatavalid_reg;
always @(posedge clock) begin
if (~reset_n_w | ~csr_status_r_pass) begin
avmm_readdata <= 32'hffffffff;
end
else begin
avmm_readdata <= flash_drdout;
end
end
// avoid async reset removal issue
assign reset_n_w = reset_n_reg2;
// initial register
initial begin
csr_status_busy = STATUS_IDLE;
csr_status_e_pass = 0;
csr_status_w_pass = 0;
csr_status_r_pass = 0;
avmm_burstcount_input_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
avmm_burstcount_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
erase_state = ERASE_STATE_IDLE;
write_state = WRITE_STATE_IDLE;
read_state = READ_STATE_IDLE;
avmm_read_state = READ_SETUP;
avmm_read_valid_state = READ_VALID_IDLE;
avmm_readdatavalid_reg = 0;
avmm_readdata_ready = 0;
flash_sector_addr = 0;
flash_page_addr = 0;
flash_ardin_align_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
flash_ardin_align_backup_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
write_drclk_en = 0;
read_drclk_en = 0;
flash_drshft_reg = 1;
flash_drshft_neg_reg = 1;
flash_busy_reg = 0;
flash_busy_clear_reg = 0;
flash_se_neg_reg = 0;
flash_se_pass_reg = 0;
flash_sp_pass_reg = 0;
erase_busy_scan = 0;
write_busy_scan = 0;
flash_seq_read_ardin = 0;
enable_arclk_neg_reg = 0;
enable_arclk_neg_pos_reg = 0;
enable_drclk_neg_reg = 0;
enable_drclk_neg_pos_reg = 0;
enable_drclk_neg_pos_write_reg = 0;
flash_drdin_neg_reg = 0;
write_count = 0;
erase_count = 0;
read_ctrl_count = 0;
data_count = 0;
write_timeout = 0;
erase_timeout = 0;
write_wait = 0;
write_wait_neg = 0;
reset_n_reg1 = 0;
reset_n_reg2 = 0;
read_wait = 0;
read_wait_neg = 0;
read_count = 0;
is_sector1_writable_reg = 0;
is_sector2_writable_reg = 0;
is_sector3_writable_reg = 0;
is_sector4_writable_reg = 0;
is_sector5_writable_reg = 0;
end
// -------------------------------------------------------------------
// Avoid async reset removal issue
// -------------------------------------------------------------------
always @ (negedge reset_n or posedge clock) begin
if (~reset_n) begin
{reset_n_reg2, reset_n_reg1} <= 2'b0;
end
else begin
{reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
end
end
// -------------------------------------------------------------------
// Sync combinational output before feeding into flash
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_sync_reg <= 0;
end
else begin
enable_arclk_sync_reg <= flash_arclk_arshft_en_w;
end
end
// -------------------------------------------------------------------
// Get rid of the race condition between different dynamic clock. Trigger clock enable in early half cycle.
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_reg <= 0;
enable_drclk_neg_reg <= 0;
flash_drshft_neg_reg <= 1;
flash_se_neg_reg <= 0;
write_wait_neg <= 0;
read_wait_neg <= 0;
end
else begin
enable_arclk_neg_reg <= enable_arclk_sync_reg;
enable_drclk_neg_reg <= (write_drclk_en || read_drclk_en);
flash_drshft_neg_reg <= flash_drshft_reg;
flash_se_neg_reg <= flash_se_w;
write_wait_neg <= write_wait;
read_wait_neg <= read_wait;
end
end
// -------------------------------------------------------------------
// Get rid of glitch for pos clock
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_pos_reg <= 0;
end
else begin
enable_arclk_neg_pos_reg <= enable_arclk_neg_reg;
end
end
// -------------------------------------------------------------------
// Pine line page address path
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_page_addr <= 0;
end
else begin
flash_page_addr <= flash_page_addr_wire;
end
end
generate // generate always block based on read and write mode. Write and erase operation is unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Pine line sector address path
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_sector_addr <= 0;
end
else begin
flash_sector_addr <= flash_sector_wire;
end
end
// -------------------------------------------------------------------
// Minitor flash pass signal and update CSR busy status
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_se_pass_reg <= 0;
flash_sp_pass_reg <= 0;
csr_status_busy <= STATUS_IDLE;
end
else begin
flash_se_pass_reg <= flash_se_pass;
flash_sp_pass_reg <= flash_sp_pass;
if (is_erase_busy) begin
csr_status_busy <= STATUS_BUSY_ERASE;
end
else if (is_write_busy) begin
csr_status_busy <= STATUS_BUSY_WRITE;
end
else if (is_read_busy) begin
csr_status_busy <= STATUS_BUSY_READ;
end
else begin
csr_status_busy <= STATUS_IDLE;
end
end
end
// -------------------------------------------------------------------
// Monitor and store flash busy signal, it may faster then the clock
// -------------------------------------------------------------------
wire busy_scan;
assign busy_scan = (erase_busy_scan || write_busy_scan);
always @ (negedge reset_n or negedge busy_scan or posedge flash_osc) begin
if (~reset_n || ~busy_scan) begin
flash_busy_reg <= 0;
flash_busy_clear_reg <= 0;
end
else if (flash_busy_reg) begin
flash_busy_reg <= flash_busy_reg;
flash_busy_clear_reg <= ~flash_busy;
end
else begin
flash_busy_reg <= flash_busy;
flash_busy_clear_reg <= 0;
end
end
altera_std_synchronizer #(
.depth (2)
) stdsync_busy (
.clk(clock), // clock
.din(flash_busy_reg), // busy signal
.dout(flash_busy_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
altera_std_synchronizer #(
.depth (2)
) stdsync_busy_clear (
.clk(clock), // clock
.din(flash_busy_clear_reg), // busy signal
.dout(flash_busy_clear_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
// -------------------------------------------------------------------
// Get rid of the race condition of shftreg signal (drdin), add half cycle delay to the data
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_drdin_neg_reg <= 1;
end
else begin
flash_drdin_neg_reg <= flash_drdin_w;
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Write Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
write_state <= WRITE_STATE_IDLE;
write_wait <= 0;
end
else begin
case (write_state)
WRITE_STATE_IDLE: begin
// reset all register
write_count <= 0;
write_timeout <= 1'b0;
write_busy_scan <= 1'b0;
enable_drclk_neg_pos_write_reg <= 0;
// check command
if (avmm_write) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_read_busy) begin
write_state <= WRITE_STATE_ADDR;
write_wait <= 1;
end
end
end
WRITE_STATE_ADDR: begin
if (is_addr_writable && is_valid_write_burst_count) begin
write_count <= DATA_WIDTH[5:0];
write_state <= WRITE_STATE_WRITE;
end
else begin
write_wait <= 0;
write_count <= 2;
write_state <= WRITE_STATE_ERROR;
end
end
WRITE_STATE_WRITE: begin
if (write_count != 0) begin
write_drclk_en <= 1;
write_count <= write_count - 16'd1;
end
else begin
enable_drclk_neg_pos_write_reg <= 1;
write_drclk_en <= 0;
write_busy_scan <= 1'b1;
write_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_BUSY;
end
end
WRITE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
write_count <= FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_DONE;
end
else begin
if (write_count != 0)
write_count <= write_count - 16'd1;
else begin
write_timeout <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
else begin
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_timeout <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_RESET: begin
write_busy_scan <= 1'b0;
if (write_timeout) begin
csr_status_w_pass <= 1'b0;
end
else begin
csr_status_w_pass <= flash_sp_pass_reg;
end
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
WRITE_STATE_ERROR: begin
csr_status_w_pass <= 1'b0;
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
default: begin
write_state <= WRITE_STATE_IDLE;
end
endcase
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Erase Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
erase_state <= ERASE_STATE_IDLE;
end
else begin
case (erase_state)
ERASE_STATE_IDLE: begin
// reset all register
erase_count <= 0;
erase_timeout <= 1'b0;
erase_busy_scan <= 1'b0;
// check command
if (valid_csr_erase && ~is_write_busy && ~is_read_busy) begin
erase_state <= ERASE_STATE_ADDR;
end
end
ERASE_STATE_ADDR: begin
if (is_erase_addr_writable) begin
erase_busy_scan <= 1'b1;
erase_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_BUSY;
end
else begin
erase_count <= 2;
erase_state <= ERASE_STATE_ERROR;
end
end
ERASE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
erase_count <= FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_DONE;
end
else begin
if (erase_count != 0)
erase_count <= erase_count - 26'd1;
else begin
erase_timeout <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
else begin
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_timeout <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_RESET: begin
erase_busy_scan <= 1'b0;
if (erase_timeout) begin
csr_status_e_pass <= 1'b0;
end
else begin
csr_status_e_pass <= flash_se_pass_reg;
end
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
ERASE_STATE_ERROR: begin
csr_status_e_pass <= 1'b0;
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
default: begin
erase_state <= ERASE_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate always block for read operation based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Increamenting Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_read_state <= READ_SETUP;
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
avmm_burstcount_input_reg <= 0;
enable_drclk_neg_pos_reg <= 0;
read_drclk_en <= 0;
flash_drshft_reg <= 1;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
read_state <= READ_STATE_ADDR;
flash_seq_read_ardin <= avmm_addr;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
READ_STATE_ADDR: begin
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_wait <= 0;
read_state <= READ_STATE_PULSE_SE;
end
READ_STATE_PULSE_SE: begin
read_wait <= 1;
read_state <= READ_STATE_SETUP;
end
// incrementing read
READ_STATE_SETUP: begin
if (next_flash_read_ardin > MAX_VALID_ADDR) begin
flash_seq_read_ardin <= MIN_VALID_ADDR[FLASH_ADDR_WIDTH-1:0];
end
else begin
flash_seq_read_ardin <= next_flash_read_ardin;
end
flash_ardin_align_reg <= flash_seq_read_ardin[FLASH_ADDR_ALIGNMENT_BITS-1:0];
if (FLASH_READ_CYCLE_MAX_INDEX[2:0] > 2) begin
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] - 3'd2;
read_state <= READ_STATE_DUMMY;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_DUMMY: begin
if (read_ctrl_count > 1) begin
read_ctrl_count <= read_ctrl_count - 3'd1;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_READY: begin
if (avmm_read_state == READ_SETUP) begin
avmm_readdata_ready <= 1;
end
read_drclk_en <= 1;
flash_drshft_reg <= 0;
read_state <= READ_STATE_FINAL;
end
READ_STATE_FINAL: begin
flash_drshft_reg <= 1;
avmm_readdata_ready <= 0;
avmm_read_state <= READ_RECV_DATA;
if ((avmm_read_state == READ_RECV_DATA) && (avmm_burstcount_reg == 0)) begin
read_state <= READ_STATE_CLEAR;
read_drclk_en <= 0;
enable_drclk_neg_pos_reg <= 1;
end
else begin
read_state <= READ_STATE_PULSE_SE;
end
end
// Dummy state to clear arclk glitch
READ_STATE_CLEAR: begin
read_wait <= 0;
read_state <= READ_STATE_IDLE;
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Wrapping Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
enable_drclk_neg_pos_reg <= 0;
flash_drshft_reg <= 1;
read_drclk_en <= 0;
avmm_burstcount_input_reg <= 0;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
read_state <= READ_STATE_ADDR;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
READ_STATE_ADDR: begin
read_wait <= 0;
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_state <= READ_STATE_PULSE_SE;
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] + 3'd1;
end
READ_STATE_PULSE_SE: begin
read_wait <= 1;
read_state <= READ_STATE_READ;
end
// wrapping read
READ_STATE_READ: begin
// read control signal
if (read_ctrl_count > 0) begin
read_ctrl_count <= read_ctrl_count - 3'd1;
end
if (read_ctrl_count == 2) begin
avmm_readdata_ready <= 1;
read_drclk_en <= 1;
flash_drshft_reg <= 0;
end
else begin
flash_drshft_reg <= 1;
end
if (avmm_read && ~read_wait) begin
read_wait <= 1;
end
if (avmm_readdata_ready || read_ctrl_count == 0) begin
avmm_readdata_ready <= 0;
if (avmm_read) begin
avmm_burstcount_input_reg <= avmm_burstcount;
read_state <= READ_STATE_ADDR;
end
end
// read data signal
if (read_count > 0) begin
read_count <= read_count - 3'd1;
end
else begin
if (avmm_readdata_ready) begin
read_count <= FLASH_SEQ_READ_DATA_COUNT[2:0] - 3'd1;
end
end
// back to idle if both control and read cycle are finished
if (read_ctrl_count == 0 && read_count == 0 && ~avmm_read) begin
read_state <= READ_STATE_IDLE;
read_drclk_en <= 0;
read_wait <= 0;
enable_drclk_neg_pos_reg <= 1;
end
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate readdatavalid control signal always block based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Control readdatavalid signal - incrementing read
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
if (avmm_readdata_ready) begin
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_read_valid_state <= READ_VALID_PRE_READING;
avmm_burstcount_reg <= avmm_burstcount_input_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
flash_ardin_align_backup_reg <= flash_ardin_align_reg;
end
end
READ_VALID_PRE_READING: begin
avmm_readdatavalid_reg <= 1;
avmm_read_valid_state <= READ_VALID_READING;
end
READ_VALID_READING: begin
if (avmm_burstcount_reg == 0) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
if (data_count > 0) begin
if ((FLASH_READ_CYCLE_MAX_INDEX - data_count + 1 + flash_ardin_align_backup_reg) < FLASH_SEQ_READ_DATA_COUNT) begin
avmm_readdatavalid_reg <= 1;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
end
else begin
avmm_readdatavalid_reg <= 0;
end
data_count <= data_count - 3'd1;
end
else begin
flash_ardin_align_backup_reg <= 0;
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_read_valid_state <= READ_VALID_PRE_READING;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Control readdatavalid signal - wrapping read with fixed burst count
// Burst count
// 1~2 - ZB8
// 1~4 - all other devices
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
data_count <= 0;
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3'd1;
avmm_read_valid_state <= READ_VALID_PRE_READING;
end
end
READ_VALID_PRE_READING: begin
avmm_readdatavalid_reg <= 1;
avmm_read_valid_state <= READ_VALID_READING;
end
READ_VALID_READING: begin
if (data_count > 0) begin
data_count <= data_count - 3'd1;
end
else begin
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3'd1;
end
else begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate shiftreg based on read and write mode. Unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Instantiate a shift register to send the data to UFM serially (load parallel)
// -------------------------------------------------------------------
lpm_shiftreg # (
.lpm_type ("LPM_SHIFTREG"),
.lpm_width (DATA_WIDTH),
.lpm_direction ("LEFT")
) ufm_data_shiftreg (
.data(avmm_writedata),
.clock(clock),
.enable(write_state == WRITE_STATE_WRITE),
.load(write_count == DATA_WIDTH),
.shiftout(flash_drdin_w),
.aclr(write_state == WRITE_STATE_IDLE)
);
end
endgenerate
altera_onchip_flash_address_range_check # (
.MIN_VALID_ADDR(MIN_VALID_ADDR),
.MAX_VALID_ADDR(MAX_VALID_ADDR)
) address_range_checker (
.address(cur_read_addr),
.is_addr_within_valid_range(is_addr_within_valid_range)
);
altera_onchip_flash_convert_address # (
.ADDR_RANGE1_END_ADDR(ADDR_RANGE1_END_ADDR),
.ADDR_RANGE1_OFFSET(ADDR_RANGE1_OFFSET),
.ADDR_RANGE2_OFFSET(ADDR_RANGE2_OFFSET)
) address_convertor (
.address(cur_a_addr),
.flash_addr(flash_page_addr_wire)
);
generate // sector address convertsion is unnecessary in read only mode
if (READ_AND_WRITE_MODE == 1) begin
// pipe line addr legality check logic
always @ (posedge clock) begin
if (~reset_n_w) begin
is_sector1_writable_reg <= 1'b0;
is_sector2_writable_reg <= 1'b0;
is_sector3_writable_reg <= 1'b0;
is_sector4_writable_reg <= 1'b0;
is_sector5_writable_reg <= 1'b0;
end
else begin
is_sector1_writable_reg <= ~(csr_write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
is_sector2_writable_reg <= ~(csr_write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
is_sector3_writable_reg <= ~(csr_write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
is_sector4_writable_reg <= ~(csr_write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
is_sector5_writable_reg <= ~(csr_write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
end
end
altera_onchip_flash_a_address_write_protection_check # (
.SECTOR1_START_ADDR(SECTOR1_START_ADDR),
.SECTOR1_END_ADDR(SECTOR1_END_ADDR),
.SECTOR2_START_ADDR(SECTOR2_START_ADDR),
.SECTOR2_END_ADDR(SECTOR2_END_ADDR),
.SECTOR3_START_ADDR(SECTOR3_START_ADDR),
.SECTOR3_END_ADDR(SECTOR3_END_ADDR),
.SECTOR4_START_ADDR(SECTOR4_START_ADDR),
.SECTOR4_END_ADDR(SECTOR4_END_ADDR),
.SECTOR5_START_ADDR(SECTOR5_START_ADDR),
.SECTOR5_END_ADDR(SECTOR5_END_ADDR)
) access_address_write_protection_checker (
.address(cur_a_addr),
.is_sector1_writable(is_sector1_writable_reg),
.is_sector2_writable(is_sector2_writable_reg),
.is_sector3_writable(is_sector3_writable_reg),
.is_sector4_writable(is_sector4_writable_reg),
.is_sector5_writable(is_sector5_writable_reg),
.is_addr_writable(is_addr_writable)
);
altera_onchip_flash_s_address_write_protection_check sector_address_write_protection_checker (
.address(cur_e_addr[2:0]),
.is_sector1_writable(is_sector1_writable_reg),
.is_sector2_writable(is_sector2_writable_reg),
.is_sector3_writable(is_sector3_writable_reg),
.is_sector4_writable(is_sector4_writable_reg),
.is_sector5_writable(is_sector5_writable_reg),
.is_addr_writable(is_sector_writable)
);
altera_onchip_flash_convert_sector # (
.SECTOR1_MAP(SECTOR1_MAP),
.SECTOR2_MAP(SECTOR2_MAP),
.SECTOR3_MAP(SECTOR3_MAP),
.SECTOR4_MAP(SECTOR4_MAP),
.SECTOR5_MAP(SECTOR5_MAP)
) sector_convertor (
.sector(cur_e_addr[2:0]),
.flash_sector(flash_sector_wire)
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211AI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O211AI_PP_SYMBOL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o211ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211AI_PP_SYMBOL_V
|
//Control circuit
`include "verilog/mips_instr_defines.v"
module control
(
input wire[5:0] instr_op_ctl_i,
input wire[5:0] instr_funct_ctl_i,
output wire reg_src_ctl_o,
output wire reg_dst_ctl_o,
output wire jump_ctl_o,
output wire branch_ctl_o,
output wire mem_read_ctl_o,
output wire mem_to_reg_ctl_o,
output wire[5:0] alu_op_ctl_o,
output wire mem_wr_ctl_o,
output wire[2:0] alu_src_ctl_o,
output wire reg_wr_ctl_o,
output wire sign_ext_ctl_o
);
wire reg_src_ctl;
wire reg_dst_ctl;
wire jump_ctl;
wire branch_ctl;
wire mem_read_ctl;
wire mem_to_reg_ctl;
wire[5:0] alu_op_ctl;
wire mem_wr_ctl;
wire[2:0] alu_src_ctl;
wire reg_wr_ctl;
wire sign_ext_ctl;
reg[17:0] controls;
assign reg_src_ctl_o = reg_src_ctl;
assign reg_dst_ctl_o = reg_dst_ctl;
assign jump_ctl_o = jump_ctl;
assign branch_ctl_o = branch_ctl;
assign mem_read_ctl_o = mem_read_ctl;
assign mem_to_reg_ctl_o = mem_to_reg_ctl;
assign alu_op_ctl_o = alu_op_ctl;
assign mem_wr_ctl_o = mem_wr_ctl;
assign alu_src_ctl_o = alu_src_ctl;
assign reg_wr_ctl_o = reg_wr_ctl;
assign sign_ext_ctl_o = sign_ext_ctl;
assign {reg_src_ctl, reg_dst_ctl, jump_ctl, branch_ctl, mem_read_ctl, mem_to_reg_ctl,
alu_op_ctl, mem_wr_ctl, alu_src_ctl, reg_wr_ctl, sign_ext_ctl} = controls;
always @ *
begin
case (instr_op_ctl_i)
//alu_op_ctl:
//6'b000_00_0: ADD
//6'b000_00_1: SUB
//6'b000_01_0: shift left
//6'b000_10_0: logical shift right
//6'b000_11_0: arithmetic shift right
//6'b001_00_0: logical OR
//6'b010_00_0: logical AND
//6'b011_00_0: logical NOR
//6'b100_00_0: logical XOR
//alu_src_ctl:
//3'b000: sends rf port 2 value to ALU
//3'b001: sends sign_imm to ALU
//3'b010: sends zero extended shamt value to ALU
//3'b100: send 32'b0 to ALU
//reg_src_ctl, reg_dst_ctl, jump_ctl, branch_ctl, mem_read_ctl, mem_to_reg_ctl, alu_op_ctl, mem_wr_ctl, alu_src_ctl, reg_wr_ctl, sign_ext
`ADDI : controls = 18'b0_0_0_0_0_0_000000_0_001_1_1; // I
`ADDIU : controls = 18'b0_0_0_0_0_0_000000_0_001_1_1; // I
`ANDI : controls = 18'b0_0_0_0_0_0_010000_0_001_1_0; // I
`SLTI : controls = 18'b0_0_0_0_0_0_101001_0_001_1_1; // I
`SLTIU : controls = 18'b0_0_0_0_0_0_110001_0_001_1_1; // I
`ORI : controls = 18'b0_0_0_0_0_0_001000_0_001_1_0; // I
`XORI : controls = 18'b0_0_0_0_0_0_100000_0_001_1_0; // I
`BEQ : controls = 18'b0_0_0_1_0_0_000001_0_000_0_1; // I
`BVAR : controls = 18'b0_0_0_1_0_0_000001_0_100_0_1; // I
`BGTZ : controls = 18'b0_0_0_1_0_0_000000_0_100_0_1; // I
`BLEZ : controls = 18'b0_0_0_1_0_0_000000_0_100_0_1; // I
`BNE : controls = 18'b0_0_0_1_0_0_000001_0_000_0_1; // I
`LB : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LBU : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LH : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LHU : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LUI : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LW : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`SB : controls = 18'b0_0_0_0_0_0_000000_1_001_0_1; // I
`SH : controls = 18'b0_0_0_0_0_0_000000_1_001_0_1; // I
`SW : controls = 18'b0_0_0_0_0_0_000000_1_001_0_1; // I
`J : controls = 18'b0_0_1_0_0_0_000000_0_001_0_1; // J
`JAL : controls = 18'b0_0_1_0_0_0_000000_0_001_1_1; // J
5'b00000:
case (instr_funct_ctl_i)
//alu_op_ctl:
//6'b000_00_0: ADD
//6'b000_00_1: SUB
//6'b000_01_0: shift left
//6'b000_10_0: logical shift right
//6'b000_11_0: arithmetic shift right
//6'b001_00_0: logical OR
//6'b010_00_0: logical AND
//6'b011_00_0: logical NOR
//6'b100_00_0: logical XOR
//alu_src_ctl:
//3'b000: sends rf port 2 value to ALU
//3'b001: sends sign_imm to ALU
//3'b010: sends zero extended shamt value to ALU
//3'b100: send 32'b0 to ALU
//reg_src_ctl,reg_dst_ctl, jump_ctl, branch_ctl, mem_read_ctl, mem_to_reg_ctl, alu_op_ctl, mem_wr_ctl, alu_src_ctl, reg_wr_ctl,sign_ext_ctl
`ADD : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`ADDU : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`AND : controls = 18'b0_1_0_0_0_0_010000_0_000_1_0; // R
`DIV : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`DIVU : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`JALR : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`JR : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MFHI : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MFLO : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MTHI : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MTLO : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MULT : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MULTU : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`NOR : controls = 18'b0_1_0_0_0_0_011000_0_000_1_0; // R
`OR : controls = 18'b0_1_0_0_0_0_001000_0_000_1_0; // R
`SLLV : controls = 18'b1_1_0_0_0_0_000010_0_010_1_0; // R
`SLT : controls = 18'b0_1_0_0_0_0_101001_0_000_1_0; // R
`SLTU : controls = 18'b0_1_0_0_0_0_110001_0_000_1_0; // R
`SRA : controls = 18'b1_1_0_0_0_0_000110_0_010_1_0; // R
`SRAV : controls = 18'b1_1_0_0_0_0_000110_0_010_1_0; // R
`SRL : controls = 18'b1_1_0_0_0_0_000100_0_010_1_0; // R
`SRLV : controls = 18'b1_1_0_0_0_0_000100_0_010_1_0; // R
`SUB : controls = 18'b0_1_0_0_0_0_000001_0_000_1_0; // R
`SUBU : controls = 18'b0_1_0_0_0_0_000001_0_000_1_0; // R
`SYSCALL: controls = 18'b0_1_0_0_0_0_000000_0_000_0_0; // R
`XOR : controls = 18'b0_1_0_0_0_0_100000_0_000_1_0; // R
`SLL : controls = 18'b1_1_0_0_0_0_000010_0_010_1_0; // R
default : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0;
endcase
default : controls = 18'b0_1_0_0_0_0_000000_0_0_0_0;
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:26:17 03/17/2015
// Design Name:
// Module Name: alt_ctl
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alt_ctl(op,func,aluc
);
input [5:0] op,func;
output reg [4:0] aluc;
always @*
begin
case(op)
6'b000000 : begin //R type
case(func)//Same op, distinguished by function code. 17 instructions
6'b100000 : aluc = 0; //add
6'b100001 : aluc = 1; //addu
6'b100010 : aluc = 2; //sub
6'b100011 : aluc = 3; //subu
6'b100100 : aluc = 4; //and
6'b100101 : aluc = 5; //or
6'b100110 : aluc = 6; //xor
6'b100111 : aluc = 7; //nor
6'b101010 : aluc = 8; //slt
6'b101011 : aluc = 9; //sltu
6'b000000 : aluc = 10; //sll
6'b000010 : aluc = 11; //srl
6'b000011 : aluc = 12; //sra
6'b000100 : aluc = 10; //sllv
6'b000110 : aluc = 11; //srlv
6'b000111 : aluc = 12; //srav
6'b000001 : aluc = 13; //slc?
6'b000010 : aluc = 13; //slcv?
default : aluc = 0;
endcase
end // I type
6'b001000 : aluc = 0; //addi
6'b001001 : aluc = 1; //addiu
6'b001100 : aluc = 4; //andi
6'b001101 : aluc = 5; //ori
6'b001101 : aluc = 6; //xori
6'b001010 : aluc = 8; //slti
6'b001101 : aluc = 9; //sltiu
6'b001111 : aluc = 14;//lui
default : aluc = 0;
endcase
end
endmodule
|
module DLX ( clk, rst, iram_data, Data_out_fromRAM, addr_to_iram, read_op,
write_op, nibble, write_byte, Address_toRAM, Data_in );
input [31:0] iram_data;
input [31:0] Data_out_fromRAM;
output [31:0] addr_to_iram;
output [1:0] nibble;
output [31:0] Address_toRAM;
output [31:0] Data_in;
input clk, rst;
output read_op, write_op, write_byte;
wire n8641, n8642, n8643, n8644, n8645, n8646, n8647, n8648, n8649, n8650,
n8651, n8652, n8653, n8654, n8655, n8656, n8657, n8658, n8659, n8660,
n8661, n8662, n8663, n8664, n8665, n8666, n8667, n8668, n8669, n8670,
n8671, n8672, n8673, n8674, n8675, \u_DataPath/reg_write_i ,
\u_DataPath/jump_i , \u_DataPath/u_fetch/pc1/N3 ,
\u_DataPath/u_decode_unit/reg_file0/N154 ,
\u_DataPath/u_decode_unit/reg_file0/N153 ,
\u_DataPath/u_decode_unit/reg_file0/N152 ,
\u_DataPath/u_decode_unit/reg_file0/N151 ,
\u_DataPath/u_decode_unit/reg_file0/N150 ,
\u_DataPath/u_decode_unit/reg_file0/N149 ,
\u_DataPath/u_decode_unit/reg_file0/N148 ,
\u_DataPath/u_decode_unit/reg_file0/N147 ,
\u_DataPath/u_decode_unit/reg_file0/N146 ,
\u_DataPath/u_decode_unit/reg_file0/N145 ,
\u_DataPath/u_decode_unit/reg_file0/N144 ,
\u_DataPath/u_decode_unit/reg_file0/N143 ,
\u_DataPath/u_decode_unit/reg_file0/N142 ,
\u_DataPath/u_decode_unit/reg_file0/N141 ,
\u_DataPath/u_decode_unit/reg_file0/N140 ,
\u_DataPath/u_decode_unit/reg_file0/N139 ,
\u_DataPath/u_decode_unit/reg_file0/N138 ,
\u_DataPath/u_decode_unit/reg_file0/N137 ,
\u_DataPath/u_decode_unit/reg_file0/N136 ,
\u_DataPath/u_decode_unit/reg_file0/N135 ,
\u_DataPath/u_decode_unit/reg_file0/N134 ,
\u_DataPath/u_decode_unit/reg_file0/N133 ,
\u_DataPath/u_decode_unit/reg_file0/N132 ,
\u_DataPath/u_decode_unit/reg_file0/N131 ,
\u_DataPath/u_decode_unit/reg_file0/N130 ,
\u_DataPath/u_decode_unit/reg_file0/N129 ,
\u_DataPath/u_decode_unit/reg_file0/N128 ,
\u_DataPath/u_decode_unit/reg_file0/N127 ,
\u_DataPath/u_decode_unit/reg_file0/N126 ,
\u_DataPath/u_decode_unit/reg_file0/N125 ,
\u_DataPath/u_decode_unit/reg_file0/N92 ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][0] ,
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\u_DataPath/u_decode_unit/reg_file0/bank_register[23][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][0] ,
\u_DataPath/u_idexreg/N184 , \u_DataPath/u_idexreg/N33 ,
\u_DataPath/u_idexreg/N31 , \u_DataPath/u_idexreg/N16 ,
\u_DataPath/u_idexreg/N15 , \u_DataPath/u_idexreg/N10 ,
\u_DataPath/u_idexreg/N3 , \u_DataPath/u_execute/ovf_i ,
\u_DataPath/u_execute/EXALU/N811 , \u_DataPath/u_execute/EXALU/N810 ,
\u_DataPath/u_exmemreg/N78 , \u_DataPath/u_memwbreg/N64 , n2733,
\lte_x_59/B[28] , \lte_x_59/B[26] , \lte_x_59/B[24] ,
\lte_x_59/B[22] , \lte_x_59/B[21] , \lte_x_59/B[18] ,
\lte_x_59/B[16] , \lte_x_59/B[15] , \lte_x_59/B[14] , \lte_x_59/B[9] ,
\lte_x_59/B[8] , \lte_x_59/B[7] , \lte_x_59/B[6] , \lte_x_59/B[5] ,
\lte_x_59/B[4] , \lte_x_59/B[3] , \lte_x_59/B[1] , \sub_x_53/A[30] ,
\sub_x_53/A[29] , \sub_x_53/A[27] , \sub_x_53/A[25] ,
\sub_x_53/A[23] , \sub_x_53/A[20] , \sub_x_53/A[17] , \sub_x_53/A[2] ,
\sub_x_53/A[0] , n2773, n2774, n2776, n2778, n2780, n2782, n2784,
n2787, n2789, n2791, n2793, n2795, n2797, n2799, n2801, n2803, n2805,
n2807, n2809, n2811, n2813, n2815, n2817, n2819, n2821, n2823, n2825,
n2829, n2831, n2833, n2835, n2838, n2840, n2842, n2843, n2844, n2845,
n2846, n2847, n2848, n2849, n2851, n2853, n2854, n2855, n2856, n2857,
n2858, n2859, n2860, n2864, n2865, n2866, n2867, n2869, n2870, n2871,
n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881,
n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891,
n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901,
n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911,
n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921,
n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931,
n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941,
n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951,
n2952, n2953, n2954, n2956, n2957, n2958, n2959, n2960, n2961, n2962,
n2963, n2964, n2965, n2966, n2968, n2969, n2970, n2971, n2972, n2973,
n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983,
n2984, n2985, n2986, n2987, n2988, n2989, n2993, n2994, n2995, n2996,
n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007,
n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3018,
n3020, n3021, n3022, n3023, n3024, n3025, n3028, n3029, n3030, n3031,
n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041,
n3042, n3043, n3044, n3045, n3047, n3048, n3049, n3050, n3051, n3052,
n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062,
n3063, n3064, n3066, n3067, n3068, n3069, n3070, n3072, n3073, n3074,
n3075, n3076, n3077, n3079, n3080, n3081, n3082, n3084, n3085, n3086,
n3088, n3089, n3090, n3091, n3093, n3094, n3095, n3096, n3098, n3099,
n3100, n3101, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110,
n3111, n3112, n3113, n3114, n3115, n3116, n3118, n3119, n3120, n3121,
n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131,
n3132, n3133, n3134, n3135, n3137, n3138, n3139, n3140, n3141, n3142,
n3143, n3144, n3145, n3146, n3147, n3148, n3150, n3151, n3152, n3153,
n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163,
n3164, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3175,
n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3185, n3186,
n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196,
n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206,
n3207, n3208, n3209, n3210, n3212, n3213, n3214, n3215, n3216, n3217,
n3218, n3219, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228,
n3229, n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238,
n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3248, n3249,
n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3259, n3260,
n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3269, n3270, n3271,
n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281,
n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291,
n3292, n3293, n3294, n3295, n3296, n3298, n3299, n3300, n3301, n3302,
n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312,
n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322,
n3323, n3324, n3325, n3327, n3328, n3329, n3330, n3331, n3332, n3333,
n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343,
n3344, n3345, n3346, n3347, n3348, n3349, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415,
n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425,
n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435,
n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445,
n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455,
n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465,
n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475,
n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485,
n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495,
n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505,
n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515,
n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525,
n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535,
n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545,
n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555,
n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565,
n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575,
n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584, n3585,
n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595,
n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605,
n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615,
n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625,
n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634, n3635,
n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644, n3645,
n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654, n3655,
n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664, n3665,
n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674, n3675,
n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684, n3685,
n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694, n3695,
n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704, n3705,
n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715,
n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725,
n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735,
n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745,
n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755,
n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765,
n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775,
n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785,
n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795,
n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805,
n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815,
n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825,
n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835,
n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845,
n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855,
n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865,
n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875,
n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885,
n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895,
n3896, n3897, n3898, n3899, n3902, n3903, n3904, n3905, n3906, n3907,
n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915, n3916, n3917,
n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925, n3926, n3927,
n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935, n3936, n3937,
n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945, n3946, n3947,
n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955, n3956, n3957,
n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965, n3966, n3967,
n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975, n3976, n3977,
n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985, n3986, n3987,
n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995, n3996, n3997,
n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005, n4006, n4007,
n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015, n4016, n4017,
n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025, n4026, n4027,
n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035, n4036, n4037,
n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045, n4046, n4047,
n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055, n4056, n4057,
n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065, n4066, n4067,
n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075, n4076, n4077,
n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085, n4086, n4087,
n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095, n4096, n4097,
n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105, n4106, n4107,
n4108, n4109, n4110, n4111, n4113, n4114, n4115, n4116, n4117, n4118,
n4119, n4120, n4121, n4122, n4123, n4124, n4125, n4126, n4128, n4129,
n4130, n4131, n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139,
n4140, n4141, n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149,
n4150, n4151, n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159,
n4160, n4161, n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169,
n4170, n4171, n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179,
n4180, n4181, n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189,
n4190, n4191, n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199,
n4200, n4201, n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209,
n4210, n4211, n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219,
n4220, n4221, n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229,
n4230, n4231, n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239,
n4240, n4241, n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249,
n4250, n4251, n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259,
n4260, n4261, n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269,
n4270, n4271, n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279,
n4280, n4281, n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289,
n4290, n4291, n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299,
n4300, n4301, n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309,
n4310, n4311, n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319,
n4320, n4321, n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329,
n4330, n4331, n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339,
n4340, n4341, n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349,
n4350, n4351, n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359,
n4360, n4361, n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369,
n4370, n4371, n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379,
n4380, n4381, n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389,
n4390, n4391, n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399,
n4400, n4401, n4402, n4403, n4404, n4405, n4406, n4407, n4408, n4409,
n4410, n4411, n4412, n4413, n4414, n4415, n4416, n4417, n4418, n4419,
n4420, n4421, n4422, n4423, n4424, n4425, n4426, n4427, n4428, n4429,
n4430, n4431, n4432, n4433, n4434, n4435, n4436, n4437, n4438, n4439,
n4440, n4441, n4442, n4443, n4444, n4445, n4446, n4447, n4448, n4449,
n4450, n4451, n4452, n4453, n4454, n4455, n4456, n4457, n4458, n4459,
n4460, n4461, n4462, n4463, n4464, n4465, n4466, n4467, n4468, n4469,
n4470, n4471, n4472, n4473, n4474, n4475, n4476, n4477, n4478, n4479,
n4480, n4481, n4482, n4483, n4484, n4485, n4486, n4487, n4488, n4489,
n4490, n4491, n4492, n4493, n4494, n4495, n4496, n4497, n4498, n4499,
n4500, n4501, n4502, n4503, n4504, n4505, n4506, n4507, n4508, n4509,
n4510, n4511, n4512, n4513, n4514, n4515, n4516, n4517, n4518, n4519,
n4520, n4521, n4522, n4523, n4524, n4525, n4526, n4527, n4528, n4529,
n4530, n4531, n4532, n4533, n4534, n4535, n4536, n4537, n4538, n4539,
n4540, n4541, n4542, n4543, n4544, n4545, n4546, n4547, n4548, n4549,
n4550, n4551, n4552, n4553, n4554, n4555, n4556, n4557, n4558, n4559,
n4560, n4561, n4562, n4563, n4564, n4565, n4566, n4567, n4568, n4569,
n4570, n4571, n4572, n4573, n4574, n4575, n4576, n4577, n4578, n4579,
n4580, n4581, n4582, n4583, n4584, n4585, n4586, n4587, n4588, n4589,
n4590, n4591, n4592, n4593, n4594, n4595, n4596, n4597, n4598, n4599,
n4600, n4601, n4602, n4603, n4604, n4605, n4606, n4607, n4608, n4609,
n4610, n4611, n4612, n4613, n4614, n4615, n4616, n4617, n4618, n4619,
n4620, n4621, n4622, n4623, n4624, n4625, n4626, n4627, n4628, n4629,
n4630, n4631, n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639,
n4640, n4641, n4642, n4643, n4644, n4645, n4646, n4647, n4648, n4649,
n4650, n4651, n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659,
n4660, n4661, n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669,
n4670, n4671, n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679,
n4680, n4681, n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689,
n4690, n4691, n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699,
n4700, n4701, n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709,
n4710, n4711, n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719,
n4720, n4721, n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729,
n4730, n4731, n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739,
n4740, n4741, n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749,
n4750, n4751, n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759,
n4760, n4761, n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769,
n4770, n4771, n4772, n4773, n4774, n4775, n4776, n4777, n4778, n4779,
n4780, n4781, n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789,
n4790, n4791, n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799,
n4800, n4801, n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809,
n4810, n4811, n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819,
n4820, n4821, n4823, n4824, n4825, n4826, n4827, n4829, n4830, n4831,
n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841,
n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851,
n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861,
n4862, n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871,
n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881,
n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891,
n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901,
n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911,
n4912, n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921,
n4922, n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931,
n4932, n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941,
n4942, n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951,
n4952, n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961,
n4962, n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971,
n4972, n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981,
n4982, n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991,
n4992, n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001,
n5002, n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011,
n5012, n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021,
n5022, n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031,
n5032, n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041,
n5042, n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051,
n5052, n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061,
n5062, n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071,
n5072, n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081,
n5082, n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091,
n5092, n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101,
n5102, n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111,
n5112, n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121,
n5122, n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131,
n5132, n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141,
n5142, n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151,
n5152, n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161,
n5162, n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171,
n5172, n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181,
n5182, n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191,
n5192, n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201,
n5202, n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211,
n5212, n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221,
n5222, n5224, n5225, n5226, n5227, n5228, n5229, n5231, n5232, n5233,
n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243,
n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253,
n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263,
n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273,
n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283,
n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293,
n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303,
n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313,
n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323,
n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333,
n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343,
n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353,
n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363,
n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373,
n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383,
n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393,
n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403,
n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413,
n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423,
n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433,
n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443,
n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453,
n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463,
n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473,
n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483,
n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493,
n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503,
n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513,
n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523,
n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533,
n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543,
n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553,
n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563,
n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573,
n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583,
n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593,
n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603,
n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613,
n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623,
n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633,
n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643,
n5644, n5645, n5646, n5647, n5648, n5649, n5651, n5652, n5653, n5654,
n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664,
n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674,
n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684,
n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694,
n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704,
n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714,
n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724,
n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734,
n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744,
n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5755,
n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765,
n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775,
n5777, n5778, n5779, n5780, n5781, n5782, n5784, n5785, n5786, n5787,
n5788, n5789, n5790, n5791, n5793, n5794, n5795, n5796, n5797, n5798,
n5799, n5800, n5801, n5802, n5803, n5804, n5805, n5806, n5807, n5808,
n5809, n5810, n5811, n5812, n5813, n5814, n5815, n5816, n5817, n5818,
n5819, n5820, n5821, n5822, n5823, n5824, n5825, n5826, n5827, n5828,
n5830, n5831, n5832, n5833, n5834, n5835, n5836, n5837, n5838, n5839,
n5841, n5842, n5844, n5845, n5846, n5848, n5849, n5850, n5851, n5852,
n5853, n5854, n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5863,
n5864, n5865, n5866, n5867, n5868, n5869, n5871, n5872, n5873, n5874,
n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884,
n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894,
n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905,
n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915,
n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925,
n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935,
n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945,
n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955,
n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965,
n5966, n5967, n5969, n5970, n5971, n5972, n5973, n5974, n5975, n5976,
n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985, n5986,
n5987, n5989, n5990, n5992, n5993, n5994, n5995, n5996, n5997, n5998,
n5999, n6000, n6001, n6002, n6003, n6004, n6005, n6006, n6007, n6008,
n6009, n6010, n6011, n6012, n6013, n6014, n6015, n6016, n6017, n6018,
n6019, n6020, n6021, n6022, n6023, n6024, n6025, n6026, n6027, n6028,
n6029, n6030, n6031, n6032, n6034, n6035, n6036, n6037, n6038, n6040,
n6041, n6042, n6043, n6044, n6045, n6046, n6047, n6048, n6049, n6050,
n6051, n6052, n6053, n6054, n6055, n6056, n6057, n6058, n6059, n6060,
n6061, n6062, n6063, n6064, n6065, n6066, n6067, n6068, n6069, n6070,
n6071, n6072, n6073, n6075, n6076, n6077, n6078, n6079, n6080, n6081,
n6082, n6083, n6084, n6085, n6087, n6088, n6089, n6090, n6091, n6092,
n6094, n6095, n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103,
n6104, n6105, n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113,
n6114, n6115, n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123,
n6124, n6125, n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133,
n6134, n6135, n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143,
n6144, n6145, n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153,
n6154, n6155, n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163,
n6164, n6165, n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173,
n6174, n6175, n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183,
n6184, n6185, n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193,
n6194, n6195, n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203,
n6204, n6205, n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213,
n6214, n6215, n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223,
n6224, n6225, n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233,
n6234, n6235, n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243,
n6244, n6245, n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253,
n6254, n6255, n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263,
n6264, n6265, n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273,
n6274, n6275, n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283,
n6284, n6285, n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293,
n6294, n6295, n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303,
n6304, n6305, n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313,
n6314, n6315, n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323,
n6324, n6325, n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333,
n6334, n6335, n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343,
n6344, n6345, n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353,
n6354, n6355, n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363,
n6364, n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374,
n6375, n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384,
n6385, n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394,
n6395, n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404,
n6405, n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414,
n6415, n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424,
n6425, n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434,
n6435, n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444,
n6445, n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454,
n6455, n6456, n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464,
n6465, n6466, n6467, n6468, n6469, n6470, n6471, n6472, n6473, n6474,
n6475, n6476, n6477, n6478, n6479, n6480, n6481, n6482, n6483, n6484,
n6485, n6486, n6487, n6488, n6489, n6490, n6491, n6492, n6493, n6494,
n6495, n6496, n6497, n6498, n6499, n6500, n6501, n6502, n6503, n6504,
n6505, n6506, n6507, n6508, n6509, n6510, n6511, n6512, n6513, n6514,
n6515, n6516, n6517, n6518, n6519, n6520, n6521, n6522, n6523, n6524,
n6525, n6526, n6527, n6528, n6529, n6530, n6531, n6532, n6533, n6534,
n6535, n6536, n6537, n6538, n6539, n6540, n6541, n6542, n6543, n6544,
n6545, n6546, n6547, n6548, n6549, n6550, n6551, n6552, n6553, n6554,
n6555, n6556, n6557, n6558, n6559, n6560, n6561, n6562, n6563, n6564,
n6565, n6566, n6567, n6568, n6569, n6570, n6571, n6572, n6573, n6574,
n6575, n6576, n6577, n6578, n6579, n6580, n6581, n6582, n6583, n6584,
n6585, n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594,
n6595, n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604,
n6605, n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614,
n6615, n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624,
n6625, n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634,
n6635, n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644,
n6645, n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654,
n6655, n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664,
n6665, n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674,
n6675, n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684,
n6685, n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694,
n6695, n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704,
n6705, n6706, n6707, n6708, n6709, n6710, n6711, n6712, n6713, n6714,
n6715, n6716, n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724,
n6725, n6726, n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734,
n6735, n6736, n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744,
n6745, n6746, n6747, n6748, n6749, n6750, n6751, n6752, n6753, n6754,
n6755, n6756, n6757, n6758, n6759, n6760, n6761, n6762, n6763, n6764,
n6765, n6766, n6767, n6768, n6769, n6770, n6771, n6772, n6773, n6774,
n6775, n6776, n6777, n6778, n6779, n6780, n6781, n6782, n6783, n6784,
n6785, n6786, n6787, n6788, n6789, n6790, n6791, n6792, n6793, n6794,
n6795, n6796, n6797, n6798, n6799, n6800, n6801, n6802, n6803, n6804,
n6805, n6806, n6807, n6808, n6809, n6810, n6811, n6812, n6813, n6814,
n6815, n6816, n6817, n6818, n6819, n6820, n6821, n6822, n6823, n6824,
n6825, n6826, n6827, n6828, n6829, n6830, n6831, n6832, n6833, n6834,
n6835, n6836, n6837, n6838, n6839, n6840, n6841, n6842, n6843, n6844,
n6845, n6846, n6847, n6848, n6849, n6850, n6851, n6852, n6853, n6854,
n6855, n6856, n6857, n6858, n6859, n6860, n6861, n6862, n6863, n6864,
n6865, n6866, n6867, n6868, n6869, n6870, n6871, n6872, n6873, n6874,
n6875, n6876, n6877, n6878, n6879, n6880, n6881, n6882, n6883, n6884,
n6885, n6886, n6887, n6888, n6889, n6890, n6891, n6892, n6893, n6894,
n6895, n6896, n6897, n6898, n6899, n6900, n6901, n6902, n6903, n6904,
n6905, n6906, n6907, n6908, n6909, n6910, n6911, n6912, n6913, n6914,
n6915, n6916, n6917, n6918, n6919, n6920, n6921, n6922, n6923, n6924,
n6925, n6926, n6927, n6929, n6930, n6931, n6932, n6933, n6934, n6935,
n6936, n6937, n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945,
n6946, n6947, n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955,
n6956, n6957, n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965,
n6966, n6967, n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975,
n6976, n6977, n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985,
n6986, n6987, n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995,
n6996, n6997, n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005,
n7006, n7007, n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015,
n7016, n7017, n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025,
n7026, n7027, n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035,
n7036, n7037, n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045,
n7046, n7047, n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055,
n7056, n7057, n7058, n7059, n7060, n7061, n7062, n7063, n7064, n7065,
n7066, n7067, n7068, n7069, n7070, n7071, n7072, n7073, n7074, n7075,
n7076, n7077, n7078, n7079, n7080, n7081, n7082, n7083, n7084, n7085,
n7086, n7087, n7088, n7089, n7090, n7091, n7092, n7093, n7094, n7095,
n7096, n7097, n7098, n7099, n7100, n7101, n7102, n7103, n7104, n7105,
n7106, n7107, n7108, n7109, n7110, n7111, n7112, n7113, n7114, n7115,
n7116, n7117, n7118, n7119, n7120, n7121, n7122, n7123, n7124, n7125,
n7126, n7127, n7128, n7129, n7130, n7131, n7132, n7133, n7134, n7135,
n7136, n7137, n7138, n7139, n7140, n7141, n7142, n7143, n7144, n7145,
n7146, n7147, n7148, n7149, n7150, n7151, n7152, n7153, n7154, n7155,
n7156, n7157, n7158, n7159, n7160, n7161, n7162, n7163, n7164, n7165,
n7166, n7167, n7168, n7169, n7170, n7171, n7172, n7173, n7174, n7175,
n7176, n7177, n7178, n7179, n7180, n7181, n7182, n7183, n7184, n7185,
n7186, n7187, n7188, n7189, n7190, n7191, n7192, n7193, n7194, n7195,
n7196, n7197, n7198, n7199, n7200, n7201, n7202, n7203, n7204, n7205,
n7206, n7207, n7208, n7209, n7210, n7211, n7212, n7213, n7214, n7215,
n7216, n7217, n7218, n7219, n7220, n7221, n7222, n7223, n7224, n7225,
n7226, n7227, n7228, n7229, n7230, n7231, n7232, n7233, n7234, n7235,
n7236, n7237, n7238, n7239, n7240, n7241, n7242, n7243, n7244, n7245,
n7246, n7247, n7248, n7249, n7250, n7251, n7252, n7253, n7254, n7255,
n7256, n7257, n7258, n7259, n7260, n7261, n7262, n7263, n7264, n7265,
n7266, n7267, n7268, n7269, n7270, n7271, n7272, n7273, n7274, n7275,
n7276, n7277, n7278, n7279, n7280, n7281, n7282, n7283, n7284, n7285,
n7286, n7287, n7288, n7289, n7290, n7291, n7292, n7293, n7294, n7295,
n7296, n7297, n7298, n7299, n7300, n7301, n7302, n7303, n7304, n7305,
n7306, n7307, n7308, n7309, n7310, n7311, n7312, n7313, n7314, n7315,
n7316, n7317, n7318, n7319, n7320, n7321, n7322, n7323, n7324, n7325,
n7326, n7327, n7328, n7329, n7330, n7331, n7332, n7333, n7334, n7335,
n7336, n7337, n7338, n7339, n7340, n7341, n7342, n7343, n7344, n7345,
n7346, n7347, n7348, n7349, n7350, n7351, n7352, n7353, n7354, n7355,
n7356, n7357, n7358, n7359, n7360, n7361, n7362, n7363, n7364, n7365,
n7366, n7367, n7368, n7369, n7370, n7371, n7372, n7373, n7374, n7375,
n7376, n7377, n7378, n7379, n7380, n7381, n7382, n7383, n7384, n7385,
n7386, n7387, n7388, n7389, n7390, n7391, n7392, n7393, n7394, n7395,
n7396, n7397, n7398, n7399, n7400, n7401, n7402, n7403, n7404, n7405,
n7406, n7407, n7408, n7409, n7410, n7411, n7412, n7413, n7414, n7415,
n7416, n7417, n7418, n7419, n7420, n7421, n7422, n7423, n7424, n7425,
n7426, n7427, n7428, n7429, n7430, n7431, n7432, n7433, n7434, n7435,
n7436, n7437, n7438, n7439, n7440, n7441, n7442, n7443, n7444, n7445,
n7446, n7447, n7448, n7449, n7450, n7451, n7452, n7453, n7454, n7455,
n7456, n7457, n7458, n7459, n7460, n7461, n7462, n7463, n7464, n7465,
n7466, n7467, n7468, n7469, n7470, n7471, n7472, n7473, n7474, n7475,
n7476, n7477, n7478, n7479, n7480, n7481, n7482, n7483, n7484, n7485,
n7486, n7487, n7488, n7489, n7490, n7491, n7492, n7493, n7494, n7495,
n7496, n7497, n7498, n7499, n7500, n7501, n7502, n7503, n7504, n7505,
n7506, n7507, n7508, n7509, n7510, n7511, n7512, n7513, n7514, n7515,
n7516, n7517, n7518, n7519, n7520, n7521, n7522, n7523, n7524, n7525,
n7526, n7527, n7528, n7529, n7530, n7531, n7532, n7533, n7534, n7535,
n7536, n7537, n7538, n7539, n7540, n7541, n7542, n7543, n7544, n7545,
n7546, n7547, n7548, n7549, n7550, n7551, n7552, n7553, n7554, n7555,
n7556, n7557, n7558, n7559, n7560, n7561, n7562, n7563, n7564, n7565,
n7566, n7567, n7568, n7569, n7570, n7571, n7572, n7573, n7574, n7575,
n7576, n7577, n7578, n7579, n7580, n7581, n7582, n7583, n7584, n7585,
n7586, n7587, n7588, n7589, n7590, n7591, n7592, n7593, n7594, n7595,
n7596, n7597, n7598, n7599, n7600, n7601, n7602, n7603, n7604, n7605,
n7606, n7607, n7608, n7609, n7610, n7611, n7612, n7613, n7614, n7615,
n7616, n7617, n7618, n7619, n7621, n7622, n7623, n7624, n7625, n7626,
n7627, n7628, n7629, n7630, n7631, n7633, n7634, n7635, n7636, n7637,
n7638, n7639, n7640, n7641, n7642, n7643, n7644, n7645, n7646, n7647,
n7648, n7649, n7650, n7652, n7653, n7654, n7655, n7657, n7658, n7659,
n7660, n7661, n7663, n7665, n7666, n7667, n7668, n7669, n7670, n7671,
n7672, n7673, n7674, n7676, n7677, n7678, n7679, n7680, n7682, n7683,
n7684, n7685, n7686, n7687, n7688, n7689, n7690, n7691, n7692, n7693,
n7694, n7695, n7696, n7697, n7698, n7699, n7700, n7701, n7702, n7703,
n7704, n7705, n7706, n7707, n7708, n7709, n7710, n7711, n7712, n7713,
n7714, n7715, n7716, n7717, n7718, n7719, n7720, n7721, n7722, n7723,
n7724, n7725, n7726, n7727, n7728, n7729, n7730, n7731, n7732, n7733,
n7734, n7735, n7736, n7737, n7738, n7739, n7740, n7741, n7742, n7743,
n7744, n7745, n7746, n7747, n7749, n7750, n7752, n7753, n7754, n7755,
n7756, n7757, n7758, n7759, n7760, n7761, n7762, n7763, n7764, n7765,
n7766, n7767, n7768, n7769, n7770, n7771, n7772, n7773, n7774, n7775,
n7776, n7777, n7778, n7779, n7780, n7781, n7782, n7783, n7784, n7785,
n7786, n7787, n7788, n7789, n7790, n7791, n7792, n7793, n7794, n7795,
n7796, n7797, n7798, n7799, n7800, n7801, n7802, n7803, n7833, n7834,
n7835, n7836, n7837, n7838, n7839, n7840, n7841, n7842, n7843, n7844,
n7845, n7846, n7847, n7848, n7849, n7850, n7851, n7852, n7853, n7854,
n7855, n7856, n7857, n7858, n7859, n7860, n7861, n7862, n7863, n7864,
n7865, n7866, n7867, n7868, n7869, n7870, n7871, n7872, n7873, n7874,
n7877, n7878, n7879, n7881, n7882, n7883, n7884, n7885, n7886, n7887,
n7888, n7889, n7890, n7891, n7892, n7893, n7894, n7895, n7896, n7897,
n7898, n7899, n7900, n7901, n7902, n7903, n7904, n7905, n7906, n7907,
n7908, n7913, n7914, n7915, n7916, n7917, n7918, n7920, n7921, n7922,
n7923, n7924, n7926, n7927, n7928, n7929, n7930, n7931, n7932, n7933,
n7934, n7935, n7936, n7937, n7938, n7939, n7940, n7941, n7942, n7943,
n7944, n7945, n7946, n7947, n7948, n7949, n7950, n7951, n7952, n7953,
n7954, n7955, n7956, n7957, n7958, n7959, n7960, n7961, n7962, n7963,
n7964, n7965, n7966, n7967, n7968, n7969, n7970, n7971, n7972, n7973,
n7974, n7975, n7976, n7977, n7978, n7979, n7980, n7981, n7982, n7983,
n7984, n7985, n7986, n7987, n7988, n7989, n7990, n7991, n7992, n7993,
n7994, n7995, n7996, n7997, n7998, n7999, n8000, n8001, n8002, n8003,
n8004, n8005, n8006, n8007, n8008, n8009, n8010, n8011, n8012, n8013,
n8014, n8015, n8016, n8017, n8018, n8019, n8020, n8021, n8022, n8023,
n8024, n8025, n8026, n8027, n8028, n8029, n8030, n8031, n8032, n8033,
n8034, n8035, n8036, n8037, n8038, n8039, n8040, n8041, n8042, n8043,
n8044, n8045, n8046, n8047, n8048, n8049, n8050, n8051, n8052, n8053,
n8054, n8055, n8056, n8057, n8058, n8059, n8061, n8062, n8063, n8064,
n8065, n8066, n8067, n8068, n8069, n8070, n8071, n8072, n8073, n8074,
n8075, n8076, n8077, n8078, n8079, n8080, n8081, n8082, n8083, n8084,
n8085, n8086, n8087, n8088, n8089, n8090, n8091, n8092, n8093, n8094,
n8095, n8096, n8097, n8098, n8099, n8100, n8101, n8102, n8103, n8104,
n8105, n8106, n8107, n8108, n8109, n8110, n8111, n8112, n8113, n8114,
n8115, n8116, n8117, n8118, n8119, n8120, n8121, n8122, n8123, n8124,
n8125, n8126, n8127, n8128, n8129, n8130, n8131, n8132, n8133, n8134,
n8135, n8136, n8137, n8138, n8139, n8140, n8141, n8142, n8143, n8144,
n8145, n8146, n8147, n8148, n8149, n8150, n8151, n8152, n8153, n8155,
n8156, n8157, n8158, n8159, n8160, n8161, n8162, n8163, n8164, n8165,
n8166, n8167, n8168, n8169, n8170, n8171, n8172, n8173, n8174, n8175,
n8176, n8177, n8178, n8179, n8180, n8181, n8182, n8183, n8184, n8185,
n8186, n8187, n8188, n8190, n8191, n8193, n8194, n8196, n8197, n8198,
n8200, n8202, n8204, n8205, n8206, n8208, n8209, n8211, n8212, n8213,
n8214, n8216, n8218, n8219, n8221, n8222, n8223, n8224, n8225, n8226,
n8227, n8228, n8229, n8230, n8231, n8233, n8234, n8235, n8236, n8238,
n8240, n8242, n8243, n8245, n8247, n8251, n8253, n8255, n8258, n8259,
n8260, n8261, n8262, n8263, n8264, n8265, n8266, n8267, n8268, n8269,
n8270, n8271, n8272, n8273, n8274, n8275, n8277, n8280, n8281, n8282,
n8283, n8284, n8285, n8286, n8287, n8288, n8289, n8290, n8291, n8292,
n8293, n8294, n8295, n8296, n8297, n8298, n8299, n8300, n8301, n8302,
n8303, n8304, n8305, n8306, n8307, n8308, n8309, n8310, n8311, n8312,
n8313, n8314, n8315, n8316, n8317, n8318, n8319, n8320, n8321, n8322,
n8323, n8324, n8325, n8326, n8327, n8328, n8329, n8330, n8331, n8332,
n8333, n8334, n8335, n8336, n8337, n8338, n8339, n8340, n8341, n8342,
n8343, n8344, n8345, n8346, n8347, n8348, n8349, n8350, n8351, n8352,
n8353, n8354, n8355, n8356, n8357, n8358, n8359, n8360, n8361, n8362,
n8363, n8364, n8365, n8366, n8367, n8368, n8369, n8370, n8371, n8372,
n8373, n8374, n8375, n8376, n8377, n8378, n8379, n8380, n8381, n8382,
n8383, n8384, n8385, n8386, n8387, n8388, n8389, n8390, n8391, n8392,
n8393, n8394, n8395, n8396, n8397, n8398, n8399, n8400, n8401, n8402,
n8403, n8404, n8405, n8406, n8407, n8408, n8409, n8410, n8411, n8412,
n8413, n8414, n8415, n8416, n8417, n8418, n8419, n8420, n8421, n8422,
n8423, n8424, n8425, n8426, n8427, n8428, n8429, n8430, n8431, n8432,
n8433, n8434, n8435, n8436, n8437, n8438, n8439, n8440, n8441, n8442,
n8443, n8444, n8445, n8446, n8447, n8448, n8449, n8450, n8451, n8452,
n8453, n8454, n8455, n8456, n8457, n8458, n8459, n8460, n8461, n8462,
n8463, n8464, n8465, n8466, n8467, n8468, n8469, n8470, n8471, n8472,
n8473, n8474, n8475, n8476, n8477, n8478, n8479, n8480, n8481, n8482,
n8483, n8484, n8485, n8486, n8487, n8488, n8489, n8490, n8491, n8492,
n8493, n8494, n8495, n8496, n8497, n8498, n8499, n8500, n8501, n8502,
n8503, n8504, n8505, n8506, n8507, n8508, n8509, n8510, n8511, n8512,
n8513, n8514, n8515, n8516, n8517, n8518, n8519, n8520, n8521, n8522,
n8523, n8524, n8525, n8526, n8527, n8528, n8529, n8530, n8531, n8532,
n8533, n8534, n8535, n8536, n8537, n8538, n8539, n8540, n8541, n8542,
n8543, n8544, n8545, n8546, n8547, n8548, n8549, n8550, n8551, n8552,
n8553, n8554, n8555, n8556, n8557, n8558, n8559, n8560, n8561, n8562,
n8563, n8564, n8565, n8566, n8567, n8568, n8569, n8570, n8571, n8572,
n8573, n8574, n8575, n8576, n8577, n8578, n8579, n8580, n8585, n8586,
n8587, n8588, n8589, n8591, n8593, n8594, n8595, n8596, n8597, n8598,
n8599, n8600, n8601, n8602, n8603, n8604, n8605, n8606, n8607, n8608,
n8609, n8610, n8611, n8612, n8613, n8614, n8616, n8618, n8620, n8621,
n8622, n8623, n8625, n8626, n8627, n8629, n8631, n8634, n8635, n8636,
n8676, n8677, n8678, n8679, n8680, n8681, n8682, n8683, n8684, n8685,
n8686, n8687, n8688, n8689, n8690, n8691, n8692, n8693, n8694, n8695,
n8696, n8697, n8698, n8699, n8700, n8701, n8702, n8703, n8704, n8705,
n8706, n8707, n8708, n8709, n8710, n8711, n8712, n8713, n8714, n8715,
n8716, n8717, n8718, n8719, n8720, n8721, n8722, n8723, n8724, n8725,
n8726, n8727, n8728, n8729, n8730, n8731, n8732, n8733, n8734, n8735,
n8736, n8737, n8738, n8739, n8740, n8741, n8742, n8743, n8744, n8745,
n8746, n8747, n8748, n8749, n8750, n8751, n8752, n8753, n8754, n8755,
n8756, n8757, n8758, n8759, n8760, n8761, n8762, n8763, n8764, n8765,
n8766, n8767, n8768, n8769, n8770, n8771, n8772, n8773, n8774, n8775,
n8776, n8777, n8778, n8779, n8780, n8781, n8782, n8783, n8784, n8785,
n8786, n8787, n8788, n8789, n8790, n8791, n8792, n8793, n8794, n8795,
n8796, n8797, n8798, n8799, n8800, n8801, n8802, n8803, n8804, n8805,
n8806, n8807, n8808, n8809, n8810, n8811, n8812, n8813, n8814, n8815,
n8816, n8817, n8818, n8819, n8820, n8821, n8822, n8823, n8824, n8825,
n8826, n8827, n8828, n8829, n8830, n8831, n8832, n8833, n8834, n8835,
n8836, n8837, n8838, n8839, n8840, n8841, n8842, n8843, n8844, n8845,
n8846, n8847, n8848, n8849, n8850, n8851, n8852, n8853, n8854, n8855,
n8856, n8857, n8858, n8859, n8860, n8861, n8862, n8863, n8864, n8865,
n8866, n8867, n8868, n8869, n8870, n8871, n8872, n8873, n8874, n8875,
n8876, n8877, n8878, n8879, n8880, n8881, n8882, n8883, n8884, n8885,
n8886, n8887, n8888, n8889, n8890, n8891, n8892, n8893, n8894, n8895,
n8896, n8897, n8898, n8899, n8900, n8901, n8902, n8903, n8904, n8905,
n8906, n8907, n8908, n8909, n8910, n8911, n8912, n8913, n8914, n8915,
n8916, n8917, n8918, n8919, n8920, n8921, n8922, n8923, n8924, n8925,
n8926, n8927, n8928, n8929, n8930, n8931, n8932, n8933, n8934, n8935,
n8936, n8937, n8938, n8939, n8940, n8941, n8942, n8943, n8944, n8945,
n8946, n8947, n8948, n8949, n8950, n8951, n8952, n8953, n8954, n8955,
n8956, n8957, n8958, n8959, n8960, n8961, n8962, n8963, n8964, n8965,
n8966, n8967, n8968, n8969, n8970, n8971, n8972, n8973, n8974, n8975,
n8976, n8977, n8978, n8979, n8980, n8981, n8982, n8983, n8984, n8985,
n8986, n8987, n8988, n8989, n8990, n8991, n8992, n8993, n8994, n8995,
n8996, n8997, n8998, n8999, n9000, n9001, n9002, n9003, n9004, n9005,
n9006, n9007, n9008, n9009, n9010, n9011, n9012, n9013, n9014, n9015,
n9016, n9017, n9018, n9019, n9020, n9021, n9022, n9023, n9024, n9025,
n9026, n9027, n9028, n9029, n9030, n9031, n9032, n9033, n9034, n9035,
n9036, n9037, n9038, n9039, n9040, n9041, n9042, n9043, n9044, n9045,
n9046, n9047, n9048, n9049, n9050, n9051, n9052, n9053, n9054, n9055,
n9056, n9057, n9058, n9059, n9060, n9061, n9062, n9063, n9064, n9065,
n9066, n9067, n9068, n9069, n9070, n9071, n9072, n9073, n9074, n9075,
n9076, n9077, n9078, n9079, n9080, n9081, n9082, n9083, n9084, n9085,
n9086, n9087, n9088, n9089, n9090, n9091, n9092, n9093, n9094, n9095,
n9096, n9097, n9098, n9099, n9100, n9101, n9102, n9103, n9104, n9105,
n9106, n9107, n9108, n9109, n9110, n9111, n9112, n9113, n9114, n9115,
n9116, n9117, n9118, n9119, n9120, n9121, n9122, n9123, n9124, n9125,
n9126, n9127, n9128, n9129, n9130, n9131, n9132, n9133, n9134, n9135,
n9136, n9137, n9138, n9139, n9140, n9141, n9142, n9143, n9144, n9145,
n9146, n9147, n9148, n9149, n9150, n9151, n9152, n9153, n9154, n9155,
n9156, n9157, n9158, n9159, n9160, n9161, n9162, n9163, n9164, n9165,
n9166, n9167, n9168, n9169, n9170, n9171, n9172, n9173, n9174, n9175,
n9176, n9177, n9178, n9179, n9180, n9181, n9182, n9183, n9184, n9185,
n9186, n9187, n9188, n9189, n9190, n9191, n9192, n9193, n9194, n9195,
n9196, n9197, n9198, n9199, n9200, n9201, n9202, n9203, n9204, n9205,
n9206, n9207, n9208, n9209, n9210, n9211, n9212, n9213, n9214, n9215,
n9216, n9217, n9218, n9219, n9220, n9221, n9222, n9223, n9224, n9225,
n9226, n9227, n9228, n9229, n9230, n9231, n9232, n9233, n9234, n9235,
n9236, n9237, n9238, n9239, n9240, n9241, n9242, n9243, n9244, n9245,
n9246, n9247, n9248, n9249, n9250, n9251, n9252, n9253, n9254, n9255,
n9256, n9257, n9258, n9259, n9260, n9261, n9262, n9263, n9264, n9265,
n9266, n9267, n9268, n9269, n9270, n9271, n9272, n9273, n9274, n9275,
n9276, n9277, n9278, n9279, n9280, n9281, n9282, n9283, n9284, n9285,
n9286, n9287, n9288, n9289, n9290, n9291, n9292, n9293, n9294, n9295,
n9296, n9297, n9298, n9299, n9300, n9301, n9302, n9303, n9304, n9305,
n9306, n9307, n9308, n9309, n9310, n9311, n9312, n9313, n9314, n9315,
n9316, n9317, n9318, n9319, n9320, n9321, n9322, n9323, n9324, n9325,
n9326, n9327, n9328, n9329, n9330, n9331, n9333, n9334, n9335, n9336,
n9337, n9338, n9339, n9340, n9341, n9342, n9343, n9344, n9345, n9346,
n9347, n9348, n9349, n9352, n9354, n9355, n9356, n9357, n9359, n9360,
n9361, n9362, n9364, n9365, n9366, n9367, n9368, n9369, n9370, n9371,
n9372, n9373, n9374, n9375, n9376, n9377, n9378, n9379, n9380, n9381,
n9382, n9383, n9384, n9385, n9386, n9387, n9388, n9389, n9390, n9391,
n9392, n9393, n9394, n9395, n9396, n9397, n9398, n9399, n9400, n9401,
n9402, n9403, n9404, n9405, n9406, n9407, n9408, n9409, n9410, n9411,
n9412, n9413, n9414, n9415, n9416, n9417, n9418, n9419, n9420, n9421,
n9422, n9423, n9424, n9425, n9426, n9427, n9428, n9429, n9431;
wire [5:0] opcode_i;
wire [4:0] \u_DataPath/regfile_addr_out_towb_i ;
wire [31:0] \u_DataPath/from_alu_data_out_i ;
wire [31:0] \u_DataPath/from_mem_data_out_i ;
wire [2:0] \u_DataPath/cw_towb_i ;
wire [4:0] \u_DataPath/RFaddr_out_memwb_i ;
wire [31:0] \u_DataPath/dataOut_exe_i ;
wire [2:0] \u_DataPath/cw_memwb_i ;
wire [31:0] \u_DataPath/mem_writedata_out_i ;
wire [10:0] \u_DataPath/cw_tomem_i ;
wire [31:0] \u_DataPath/toPC2_i ;
wire [10:0] \u_DataPath/cw_exmem_i ;
wire [4:0] \u_DataPath/rs_ex_i ;
wire [31:0] \u_DataPath/immediate_ext_ex_i ;
wire [31:0] \u_DataPath/data_read_ex_2_i ;
wire [31:0] \u_DataPath/data_read_ex_1_i ;
wire [31:0] \u_DataPath/pc_4_to_ex_i ;
wire [21:0] \u_DataPath/cw_to_ex_i ;
wire [31:0] \u_DataPath/immediate_ext_dec_i ;
wire [31:0] \u_DataPath/pc4_to_idexreg_i ;
wire [31:0] \u_DataPath/jaddr_i ;
wire [4:0] \u_DataPath/idex_rt_i ;
wire [31:0] \u_DataPath/pc_4_i ;
wire [31:0] \u_DataPath/branch_target_i ;
wire [31:0] \u_DataPath/jump_address_i ;
wire [1:0] \u_DataPath/u_decode_unit/hdu_0/current_state ;
wire [31:0] \u_DataPath/u_execute/psw_status_i ;
wire [31:0] \u_DataPath/u_execute/link_value_i ;
wire [31:0] \u_DataPath/u_execute/resAdd1_i ;
assign Address_toRAM[30] = 1'b0;
assign Address_toRAM[31] = 1'b0;
assign addr_to_iram[30] = 1'b0;
assign addr_to_iram[31] = 1'b0;
HS65_LH_CNIVX3 U151 ( .A(rst), .Z(n2733) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][30] ) );
HS65_LH_LDHQX4 \u_DataPath/u_execute/EXALU/ovf_reg ( .G(
\u_DataPath/u_execute/EXALU/N810 ), .D(
\u_DataPath/u_execute/EXALU/N811 ), .Q(\u_DataPath/u_execute/ovf_i )
);
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][27] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][31] (
.G(rst), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][31] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][0] (
.G(rst), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][0] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][1] (
.G(rst), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][1] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][6] (
.G(rst), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][6] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][18] (
.G(rst), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][18] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][2] (
.G(rst), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][2] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][17] (
.G(rst), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][17] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][16] (
.G(rst), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][16] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][20] (
.G(rst), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][20] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][8] (
.G(rst), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][8] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][4] (
.G(rst), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][4] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][22] (
.G(rst), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][22] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][28] (
.G(rst), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][28] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][24] (
.G(rst), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][24] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][9] (
.G(rst), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][9] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][25] (
.G(rst), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][25] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][5] (
.G(rst), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][5] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][21] (
.G(rst), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][21] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][29] (
.G(rst), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][29] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][13] (
.G(rst), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][13] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][7] (
.G(rst), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][7] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][12] (
.G(rst), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][12] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][30] (
.G(rst), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][30] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][23] (
.G(rst), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][23] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][26] (
.G(rst), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][26] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][10] (
.G(rst), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][10] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][3] (
.G(rst), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][3] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][19] (
.G(rst), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][19] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][11] (
.G(rst), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][11] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][15] (
.G(rst), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][15] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][14] (
.G(rst), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][14] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][27] (
.G(rst), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][30] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][31] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][20] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][26] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][28] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][19] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][17] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][18] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][13] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][4] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][3] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][1] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][21] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][27] ) );
HS65_LL_IVX18 U3438 ( .A(n3118), .Z(addr_to_iram[26]) );
HS65_LH_IVX40 U3462 ( .A(n2782), .Z(addr_to_iram[17]) );
HS65_LH_IVX40 U3463 ( .A(n2823), .Z(addr_to_iram[9]) );
HS65_LH_IVX40 U3464 ( .A(n2825), .Z(addr_to_iram[25]) );
HS65_LH_IVX40 U3466 ( .A(n2829), .Z(addr_to_iram[7]) );
HS65_LH_IVX40 U3467 ( .A(n2831), .Z(addr_to_iram[18]) );
HS65_LH_IVX40 U3468 ( .A(n2833), .Z(addr_to_iram[8]) );
HS65_LH_IVX40 U3469 ( .A(n2835), .Z(addr_to_iram[6]) );
HS65_LH_NOR4ABX2 U3470 ( .A(n6806), .B(n6805), .C(n6804), .D(n6803), .Z(
n8183) );
HS65_LH_NOR4ABX2 U3471 ( .A(n6846), .B(n6845), .C(n6844), .D(n6843), .Z(
n8156) );
HS65_LL_OR2ABX35 U3473 ( .A(n2981), .B(n2994), .Z(write_op) );
HS65_LH_IVX9 U3474 ( .A(n3003), .Z(n2787) );
HS65_LH_IVX9 U3475 ( .A(n3004), .Z(n2793) );
HS65_LH_IVX9 U3476 ( .A(n2993), .Z(n2809) );
HS65_LH_IVX9 U3477 ( .A(n3006), .Z(n2805) );
HS65_LH_IVX9 U3478 ( .A(n3005), .Z(n2803) );
HS65_LH_IVX9 U3479 ( .A(n3007), .Z(n2807) );
HS65_LH_IVX9 U3480 ( .A(n8687), .Z(\u_DataPath/pc_4_i [2]) );
HS65_LH_IVX9 U3481 ( .A(n2989), .Z(n2789) );
HS65_LH_IVX9 U3482 ( .A(n2987), .Z(n2791) );
HS65_LH_IVX9 U3483 ( .A(n3001), .Z(n2795) );
HS65_LH_IVX9 U3484 ( .A(n3000), .Z(n2797) );
HS65_LH_IVX9 U3485 ( .A(n3002), .Z(n2799) );
HS65_LH_IVX9 U3486 ( .A(n2996), .Z(n2813) );
HS65_LH_IVX9 U3487 ( .A(n2999), .Z(n2815) );
HS65_LH_IVX9 U3488 ( .A(n2995), .Z(n2817) );
HS65_LH_IVX9 U3489 ( .A(n8671), .Z(n2774) );
HS65_LH_IVX9 U3490 ( .A(n8675), .Z(n2776) );
HS65_LH_IVX9 U3491 ( .A(n8673), .Z(n2778) );
HS65_LH_IVX9 U3492 ( .A(n8672), .Z(n2819) );
HS65_LH_IVX9 U3493 ( .A(n8674), .Z(n2821) );
HS65_LH_IVX9 U3494 ( .A(n3013), .Z(n2838) );
HS65_LH_IVX9 U3495 ( .A(n2998), .Z(n2811) );
HS65_LH_IVX9 U3496 ( .A(n8692), .Z(n2782) );
HS65_LH_IVX9 U3497 ( .A(n8703), .Z(n2825) );
HS65_LH_IVX9 U3498 ( .A(n8679), .Z(n2823) );
HS65_LH_IVX9 U3500 ( .A(n8678), .Z(n2829) );
HS65_LH_IVX9 U3501 ( .A(n8697), .Z(n2831) );
HS65_LH_IVX9 U3502 ( .A(n8681), .Z(n2833) );
HS65_LH_IVX9 U3503 ( .A(n8680), .Z(n2835) );
HS65_LH_IVX9 U3504 ( .A(n8684), .Z(n7745) );
HS65_LH_IVX9 U3505 ( .A(n8686), .Z(n3126) );
HS65_LH_IVX9 U3506 ( .A(n8685), .Z(n7669) );
HS65_LH_AOI21X2 U3507 ( .A(n7631), .B(n5707), .C(n5706), .Z(n5709) );
HS65_LH_NOR2AX3 U3517 ( .A(\u_DataPath/dataOut_exe_i [29]), .B(n3116), .Z(
n2988) );
HS65_LH_NOR2AX3 U3518 ( .A(n8748), .B(n3115), .Z(n2998) );
HS65_LH_AOI21X2 U3519 ( .A(n6011), .B(n6083), .C(n6010), .Z(n6065) );
HS65_LH_IVX9 U3520 ( .A(n8713), .Z(n2780) );
HS65_LH_AOI21X2 U3521 ( .A(n6117), .B(n6119), .C(n5943), .Z(n2876) );
HS65_LL_NAND3AX6 U3522 ( .A(n5676), .B(n8478), .C(n5675), .Z(n5677) );
HS65_LH_BFX9 U3523 ( .A(n7096), .Z(n7902) );
HS65_LH_BFX9 U3528 ( .A(n7320), .Z(n7587) );
HS65_LH_BFX9 U3529 ( .A(n7330), .Z(n7600) );
HS65_LH_BFX9 U3530 ( .A(n7332), .Z(n7602) );
HS65_LH_BFX9 U3531 ( .A(n7317), .Z(n7585) );
HS65_LH_BFX9 U3532 ( .A(n6675), .Z(n7318) );
HS65_LH_BFX9 U3533 ( .A(n7311), .Z(n7579) );
HS65_LH_AOI21X2 U3534 ( .A(Data_out_fromRAM[15]), .B(n8271), .C(n7344), .Z(
n7345) );
HS65_LH_BFX9 U3535 ( .A(n6382), .Z(n7291) );
HS65_LH_BFX9 U3537 ( .A(n6681), .Z(n7523) );
HS65_LH_NOR2X6 U3541 ( .A(n6348), .B(n2878), .Z(n7578) );
HS65_LH_NOR2X6 U3542 ( .A(n6147), .B(n6153), .Z(n6617) );
HS65_LH_NOR2X6 U3543 ( .A(n6150), .B(n6147), .Z(n6162) );
HS65_LH_NOR2X6 U3545 ( .A(n6153), .B(n6140), .Z(n6635) );
HS65_LH_NOR2X6 U3546 ( .A(n6353), .B(n6352), .Z(n6967) );
HS65_LH_NOR2X6 U3548 ( .A(n6349), .B(n6332), .Z(n7311) );
HS65_LH_NOR2X6 U3549 ( .A(n6350), .B(n6331), .Z(n7317) );
HS65_LL_NAND2X4 U3550 ( .A(n4282), .B(n4281), .Z(n4453) );
HS65_LL_NAND3X5 U3551 ( .A(n7083), .B(n7082), .C(n7081), .Z(n7306) );
HS65_LH_AOI21X2 U3552 ( .A(n8056), .B(n7697), .C(n7636), .Z(n7776) );
HS65_LH_NOR2AX3 U3553 ( .A(n9111), .B(n7076), .Z(n7083) );
HS65_LL_AOI21X2 U3554 ( .A(n7115), .B(n7614), .C(n7613), .Z(n8034) );
HS65_LH_AND2X4 U3556 ( .A(\u_DataPath/jaddr_i [20]), .B(
\u_DataPath/jaddr_i [19]), .Z(n6347) );
HS65_LH_NOR4ABX2 U3558 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(n5488), .C(n5571), .D(n5353), .Z(n5372) );
HS65_LL_OAI12X2 U3559 ( .A(n5539), .B(n5538), .C(n5537), .Z(n5593) );
HS65_LHS_XNOR2X3 U3560 ( .A(n4045), .B(n4044), .Z(n4046) );
HS65_LH_OAI12X3 U3561 ( .A(n3935), .B(n4929), .C(n4085), .Z(n3847) );
HS65_LH_NOR4ABX2 U3562 ( .A(n5289), .B(n5344), .C(n5350), .D(n5288), .Z(
n5368) );
HS65_LH_IVX9 U3563 ( .A(\u_DataPath/jaddr_i [21]), .Z(n8163) );
HS65_LH_IVX9 U3564 ( .A(\u_DataPath/jaddr_i [23]), .Z(n8165) );
HS65_LH_IVX9 U3565 ( .A(write_byte), .Z(n2981) );
HS65_LL_AOI21X2 U3566 ( .A(n4431), .B(n4363), .C(n4362), .Z(n4364) );
HS65_LH_OAI12X3 U3568 ( .A(n4090), .B(n4929), .C(n4089), .Z(n4091) );
HS65_LL_NOR3X4 U3569 ( .A(n5528), .B(n5527), .C(n5513), .Z(n5559) );
HS65_LH_AOI12X2 U3573 ( .A(n5299), .B(n4017), .C(n5466), .Z(n5301) );
HS65_LH_AOI21X2 U3574 ( .A(n5632), .B(n5630), .C(n5629), .Z(n5636) );
HS65_LH_IVX9 U3576 ( .A(n5144), .Z(n4954) );
HS65_LH_AOI21X2 U3577 ( .A(n5575), .B(n5015), .C(n5014), .Z(n5016) );
HS65_LH_OAI21X2 U3578 ( .A(n5071), .B(n5070), .C(n5069), .Z(n5072) );
HS65_LH_NAND3X5 U3579 ( .A(n5479), .B(n5478), .C(n5477), .Z(n5480) );
HS65_LL_AOI21X2 U3580 ( .A(n5586), .B(n5009), .C(n5585), .Z(n5010) );
HS65_LL_OAI21X2 U3583 ( .A(n5152), .B(n5616), .C(n4167), .Z(n4168) );
HS65_LH_IVX9 U3586 ( .A(n5661), .Z(n4855) );
HS65_LL_NOR2X6 U3589 ( .A(n4502), .B(n4863), .Z(n4951) );
HS65_LH_AOI21X2 U3590 ( .A(n3521), .B(n4588), .C(n3830), .Z(n3831) );
HS65_LH_IVX9 U3592 ( .A(n4939), .Z(n6123) );
HS65_LH_AOI21X2 U3594 ( .A(n2849), .B(n4588), .C(n3904), .Z(n4496) );
HS65_LH_AOI21X2 U3595 ( .A(n5732), .B(n5758), .C(n5731), .Z(n5799) );
HS65_LH_IVX9 U3596 ( .A(n3935), .Z(n3482) );
HS65_LH_AOI21X2 U3597 ( .A(n5805), .B(n5807), .C(n5734), .Z(n5735) );
HS65_LH_IVX9 U3598 ( .A(n3426), .Z(n4502) );
HS65_LH_NOR2X6 U3599 ( .A(n4534), .B(n4581), .Z(n5207) );
HS65_LL_NAND2X7 U3600 ( .A(n4949), .B(n4836), .Z(n5646) );
HS65_LH_NAND2X7 U3601 ( .A(\u_DataPath/u_idexreg/N3 ), .B(n4550), .Z(n5249)
);
HS65_LL_NAND2X7 U3602 ( .A(n3643), .B(n3642), .Z(n4614) );
HS65_LL_NAND2X7 U3604 ( .A(n2851), .B(n4581), .Z(n4341) );
HS65_LH_AOI21X2 U3605 ( .A(n6010), .B(n5936), .C(n5935), .Z(n6000) );
HS65_LH_IVX9 U3608 ( .A(\lte_x_59/B[28] ), .Z(n4724) );
HS65_LH_NAND2X7 U3609 ( .A(n3431), .B(n5032), .Z(n4534) );
HS65_LL_NAND2X7 U3610 ( .A(n3490), .B(n3489), .Z(n4632) );
HS65_LL_NOR2X6 U3611 ( .A(\lte_x_59/B[21] ), .B(n5418), .Z(n4371) );
HS65_LH_NOR2X9 U3612 ( .A(n2840), .B(n7623), .Z(n5571) );
HS65_LH_NAND2X7 U3613 ( .A(n5021), .B(\lte_x_59/B[16] ), .Z(n4846) );
HS65_LH_NAND2X7 U3614 ( .A(\sub_x_53/A[20] ), .B(n4699), .Z(n4425) );
HS65_LH_OAI12X3 U3615 ( .A(n2860), .B(n2856), .C(n3963), .Z(n4257) );
HS65_LH_AOI21X2 U3616 ( .A(n5844), .B(n5720), .C(n5719), .Z(n5832) );
HS65_LH_AOI21X2 U3617 ( .A(n5761), .B(n5728), .C(n5727), .Z(n5729) );
HS65_LH_AOI21X2 U3618 ( .A(n5833), .B(n5722), .C(n5721), .Z(n5723) );
HS65_LH_AOI21X2 U3619 ( .A(n5811), .B(n5813), .C(n5733), .Z(n5800) );
HS65_LL_NAND2AX7 U3620 ( .A(n3546), .B(n3545), .Z(n4344) );
HS65_LH_IVX9 U3621 ( .A(\lte_x_59/B[5] ), .Z(n5041) );
HS65_LH_NAND2X7 U3622 ( .A(\lte_x_59/B[7] ), .B(n5030), .Z(n4624) );
HS65_LH_IVX9 U3625 ( .A(\lte_x_59/B[26] ), .Z(n5568) );
HS65_LL_NAND2X5 U3626 ( .A(n3474), .B(n5104), .Z(n4038) );
HS65_LL_IVX9 U3628 ( .A(n3101), .Z(\sub_x_53/A[25] ) );
HS65_LL_IVX18 U3632 ( .A(n3756), .Z(n4588) );
HS65_LH_NAND2X7 U3634 ( .A(\lte_x_59/B[5] ), .B(n5040), .Z(n4107) );
HS65_LL_NOR2AX6 U3635 ( .A(n3077), .B(n3076), .Z(\sub_x_53/A[29] ) );
HS65_LL_NOR2X6 U3637 ( .A(\sub_x_53/A[17] ), .B(n5001), .Z(n3558) );
HS65_LH_IVX9 U3640 ( .A(n2845), .Z(n2857) );
HS65_LH_OAI12X3 U3642 ( .A(n8355), .B(n3409), .C(n3094), .Z(n3095) );
HS65_LH_NOR2AX3 U3644 ( .A(n5054), .B(n2871), .Z(n4902) );
HS65_LH_AO31X9 U3646 ( .A(n8393), .B(n2866), .C(n9376), .D(n3419), .Z(n5032)
);
HS65_LL_IVX4 U3648 ( .A(n4969), .Z(n3059) );
HS65_LL_NOR2X6 U3649 ( .A(n3064), .B(n3063), .Z(\lte_x_59/B[1] ) );
HS65_LH_NOR2X6 U3650 ( .A(n3187), .B(n3186), .Z(n3432) );
HS65_LL_NOR2X6 U3652 ( .A(n3240), .B(n3239), .Z(n3474) );
HS65_LL_OAI12X6 U3653 ( .A(n3192), .B(n2894), .C(n3191), .Z(n5231) );
HS65_LL_OAI12X6 U3656 ( .A(n3224), .B(n3223), .C(n3222), .Z(n5373) );
HS65_LL_BFX9 U3657 ( .A(n3333), .Z(n3264) );
HS65_LH_IVX18 U3658 ( .A(n3082), .Z(n3403) );
HS65_LL_AOI21X2 U3660 ( .A(n3404), .B(n9385), .C(n3025), .Z(n7854) );
HS65_LH_IVX18 U3661 ( .A(n4712), .Z(n2874) );
HS65_LLS_XOR2X3 U3665 ( .A(n2940), .B(n2846), .Z(n2964) );
HS65_LL_NAND3X3 U3666 ( .A(n2941), .B(n7343), .C(n7089), .Z(n3052) );
HS65_LL_IVX9 U3668 ( .A(n7084), .Z(n2846) );
HS65_LL_NAND2X7 U3670 ( .A(\lte_x_59/B[5] ), .B(n4665), .Z(n4143) );
HS65_LL_IVX4 U3671 ( .A(n4657), .Z(n3339) );
HS65_LL_CBI4I1X5 U3673 ( .A(n5685), .B(n7853), .C(n7872), .D(n5684), .Z(
n7862) );
HS65_LL_IVX4 U3675 ( .A(n5694), .Z(n5675) );
HS65_LL_NAND2X14 U3676 ( .A(n3308), .B(n3310), .Z(n4712) );
HS65_LL_IVX9 U3677 ( .A(n3008), .Z(n7089) );
HS65_LH_NAND3X2 U3680 ( .A(n7089), .B(n9031), .C(n9078), .Z(n2773) );
HS65_LH_IVX13 U3684 ( .A(n8693), .Z(n7758) );
HS65_LH_NAND2X2 U3685 ( .A(\u_DataPath/dataOut_exe_i [1]), .B(nibble[0]),
.Z(n8575) );
HS65_LH_IVX9 U3686 ( .A(n2988), .Z(n2801) );
HS65_LL_NOR2AX25 U3687 ( .A(\u_DataPath/dataOut_exe_i [28]), .B(n3116), .Z(
Address_toRAM[26]) );
HS65_LL_NOR2AX3 U3688 ( .A(\u_DataPath/dataOut_exe_i [12]), .B(n2986), .Z(
n3005) );
HS65_LL_NOR2AX3 U3690 ( .A(\u_DataPath/dataOut_exe_i [10]), .B(n2986), .Z(
n3007) );
HS65_LH_NAND2X2 U3692 ( .A(addr_to_iram[12]), .B(addr_to_iram[13]), .Z(n7676) );
HS65_LH_NAND2X2 U3695 ( .A(n8704), .B(addr_to_iram[15]), .Z(n7648) );
HS65_LL_NOR2AX25 U3696 ( .A(\u_DataPath/dataOut_exe_i [13]), .B(n2986), .Z(
Address_toRAM[11]) );
HS65_LL_NOR2AX25 U3697 ( .A(\u_DataPath/dataOut_exe_i [27]), .B(n3116), .Z(
Address_toRAM[25]) );
HS65_LL_NOR2AX25 U3698 ( .A(n8728), .B(n3115), .Z(Data_in[31]) );
HS65_LH_NOR2X2 U3702 ( .A(n5476), .B(n5522), .Z(n5515) );
HS65_LH_OAI21X3 U3703 ( .A(n4926), .B(n3932), .C(n3934), .Z(n3477) );
HS65_LH_CNIVX3 U3704 ( .A(n3395), .Z(n3290) );
HS65_LH_NOR2X2 U3705 ( .A(n4724), .B(n5423), .Z(n5505) );
HS65_LH_NAND2X2 U3706 ( .A(n2858), .B(n2864), .Z(n3871) );
HS65_LH_CNIVX3 U3707 ( .A(n8547), .Z(n3161) );
HS65_LH_NAND2X2 U3709 ( .A(n4717), .B(n9342), .Z(n3195) );
HS65_LH_OAI21X3 U3710 ( .A(n4664), .B(n4637), .C(n4663), .Z(n5389) );
HS65_LH_NOR3X1 U3711 ( .A(n5082), .B(n5081), .C(n5080), .Z(n5114) );
HS65_LH_NAND2X2 U3715 ( .A(n4714), .B(n8518), .Z(n3254) );
HS65_LH_NAND2X2 U3716 ( .A(\lte_x_59/B[24] ), .B(n5180), .Z(n5209) );
HS65_LH_OAI21X3 U3717 ( .A(n5621), .B(n5620), .C(n5619), .Z(n5622) );
HS65_LH_CNIVX3 U3719 ( .A(n3427), .Z(n5659) );
HS65_LH_OAI21X3 U3720 ( .A(n6058), .B(n5957), .C(n5959), .Z(n5929) );
HS65_LH_NAND2X2 U3723 ( .A(n4295), .B(n5210), .Z(n4296) );
HS65_LH_CNIVX3 U3724 ( .A(n5405), .Z(n5476) );
HS65_LH_IVX9 U3725 ( .A(n5618), .Z(n5241) );
HS65_LH_NAND2X2 U3726 ( .A(\sub_x_53/A[20] ), .B(n4551), .Z(n3819) );
HS65_LH_CNIVX3 U3727 ( .A(n5128), .Z(n3773) );
HS65_LL_IVX2 U3728 ( .A(n4250), .Z(n5261) );
HS65_LH_NOR2X2 U3729 ( .A(n9030), .B(n9223), .Z(n6038) );
HS65_LH_NOR2X2 U3730 ( .A(n3905), .B(n4954), .Z(n3906) );
HS65_LH_CNIVX3 U3731 ( .A(n5400), .Z(n5466) );
HS65_LH_NAND2X2 U3732 ( .A(n3448), .B(n5469), .Z(n3449) );
HS65_LH_OAI21X3 U3733 ( .A(n5627), .B(n3702), .C(n5435), .Z(n3703) );
HS65_LH_CNIVX3 U3734 ( .A(n4230), .Z(n4303) );
HS65_LH_AOI12X2 U3735 ( .A(\lte_x_59/B[28] ), .B(n4588), .C(n3439), .Z(n3440) );
HS65_LH_CNIVX3 U3738 ( .A(n4849), .Z(n5203) );
HS65_LH_NOR2X2 U3739 ( .A(n5646), .B(n5645), .Z(n5669) );
HS65_LH_CNIVX3 U3740 ( .A(n4457), .Z(n4430) );
HS65_LH_NAND2X2 U3742 ( .A(\u_DataPath/jaddr_i [19]), .B(n6326), .Z(n6331)
);
HS65_LHS_XNOR2X3 U3743 ( .A(\u_DataPath/jaddr_i [18]), .B(n8967), .Z(n7101)
);
HS65_LH_OAI21X3 U3744 ( .A(n5730), .B(n5759), .C(n5729), .Z(n5731) );
HS65_LH_NAND2X2 U3745 ( .A(n7670), .B(n7649), .Z(n7650) );
HS65_LH_CNIVX3 U3746 ( .A(n6014), .Z(n5937) );
HS65_LH_NAND2X2 U3747 ( .A(n9185), .B(n9230), .Z(n6006) );
HS65_LH_NAND2X2 U3748 ( .A(n9183), .B(n9232), .Z(n5978) );
HS65_LH_NOR2X2 U3749 ( .A(n5987), .B(n5990), .Z(n5961) );
HS65_LH_NOR2X2 U3752 ( .A(n4502), .B(n4495), .Z(n4506) );
HS65_LH_NAND2X2 U3754 ( .A(n4084), .B(n4086), .Z(n3848) );
HS65_LH_NOR2X2 U3755 ( .A(n7713), .B(n7711), .Z(n5168) );
HS65_LH_NOR2X6 U3757 ( .A(n6153), .B(n6139), .Z(n6376) );
HS65_LH_BFX9 U3758 ( .A(n9373), .Z(n7580) );
HS65_LH_NAND3X2 U3760 ( .A(n7103), .B(n7102), .C(n7101), .Z(n7111) );
HS65_LH_NOR2X2 U3761 ( .A(n9341), .B(n9207), .Z(n5748) );
HS65_LH_NOR2X2 U3762 ( .A(n9181), .B(n9226), .Z(n5756) );
HS65_LH_NAND2X2 U3763 ( .A(n9173), .B(n9231), .Z(n5876) );
HS65_LH_CNIVX3 U3764 ( .A(n8915), .Z(n8268) );
HS65_LH_NAND2X2 U3765 ( .A(n7659), .B(n7684), .Z(n7673) );
HS65_LH_NOR2X2 U3766 ( .A(n7795), .B(n7794), .Z(n7307) );
HS65_LH_NAND2X2 U3767 ( .A(n4189), .B(n8571), .Z(n4190) );
HS65_LH_NOR2X2 U3768 ( .A(n8825), .B(n3341), .Z(n3177) );
HS65_LH_NAND2X2 U3769 ( .A(n9173), .B(n9231), .Z(n6075) );
HS65_LH_NAND2X2 U3770 ( .A(n8297), .B(n3407), .Z(n3104) );
HS65_LH_NOR2X2 U3771 ( .A(n8848), .B(n3341), .Z(n3159) );
HS65_LH_CNIVX3 U3772 ( .A(\u_DataPath/dataOut_exe_i [19]), .Z(n3188) );
HS65_LH_OAI21X3 U3774 ( .A(n4019), .B(n3815), .C(n4018), .Z(n4020) );
HS65_LH_OAI21X3 U3778 ( .A(n4349), .B(n4363), .C(n4949), .Z(n4095) );
HS65_LH_NAND2X2 U3782 ( .A(n5285), .B(n4483), .Z(n4484) );
HS65_LH_NAND2X2 U3783 ( .A(n5689), .B(n7723), .Z(n7714) );
HS65_LH_NAND2X2 U3784 ( .A(n9039), .B(n9116), .Z(n6100) );
HS65_LH_CNIVX3 U3785 ( .A(n7707), .Z(n7787) );
HS65_LH_NOR2X2 U3787 ( .A(n8172), .B(\u_DataPath/immediate_ext_dec_i [4]),
.Z(n8076) );
HS65_LH_NOR2X2 U3788 ( .A(n7668), .B(n7644), .Z(n7665) );
HS65_LH_AOI12X3 U3789 ( .A(n6053), .B(n6055), .C(n5944), .Z(n5945) );
HS65_LH_NOR2X2 U3790 ( .A(n5795), .B(n5798), .Z(n5808) );
HS65_LH_CNIVX3 U3791 ( .A(n5799), .Z(n5868) );
HS65_LH_NAND2X2 U3792 ( .A(n9179), .B(n9225), .Z(n5885) );
HS65_LHS_XNOR2X3 U3793 ( .A(n9235), .B(n8268), .Z(n2980) );
HS65_LH_NOR2X2 U3794 ( .A(n8480), .B(n7874), .Z(n7872) );
HS65_LH_NAND2X2 U3795 ( .A(n8697), .B(n7767), .Z(n7768) );
HS65_LH_CNIVX3 U3796 ( .A(n8235), .Z(n8287) );
HS65_LH_CNIVX3 U3800 ( .A(n8306), .Z(n3274) );
HS65_LHS_XNOR2X3 U3801 ( .A(n7724), .B(n7723), .Z(
\u_DataPath/u_execute/link_value_i [14]) );
HS65_LH_NOR2X2 U3802 ( .A(n8480), .B(n8306), .Z(n8600) );
HS65_LH_CNIVX3 U3804 ( .A(n8394), .Z(n3412) );
HS65_LH_NOR2X2 U3805 ( .A(n8480), .B(n8258), .Z(n8591) );
HS65_LHS_XNOR2X3 U3806 ( .A(n7709), .B(n7708), .Z(
\u_DataPath/u_execute/link_value_i [7]) );
HS65_LH_MUXI21X5 U3809 ( .D0(n3175), .D1(n9383), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8385) );
HS65_LHS_XNOR2X3 U3810 ( .A(n3517), .B(n3516), .Z(n3571) );
HS65_LH_NOR3X1 U3811 ( .A(n7094), .B(n7093), .C(n7092), .Z(n7095) );
HS65_LH_NAND2X2 U3812 ( .A(n9035), .B(n9115), .Z(n6049) );
HS65_LH_CNIVX3 U3814 ( .A(n8114), .Z(n8091) );
HS65_LH_NAND2X2 U3815 ( .A(\u_DataPath/immediate_ext_dec_i [0]), .B(n8157),
.Z(n8115) );
HS65_LH_NOR2X2 U3816 ( .A(n9082), .B(n7734), .Z(n8038) );
HS65_LHS_XNOR2X3 U3817 ( .A(n5881), .B(n5880), .Z(\u_DataPath/toPC2_i [9])
);
HS65_LH_NAND2X2 U3818 ( .A(n3470), .B(\u_DataPath/cw_to_ex_i [2]), .Z(n7617)
);
HS65_LH_NOR2X2 U3821 ( .A(n8844), .B(n4712), .Z(n8500) );
HS65_LH_CNIVX3 U3822 ( .A(n8600), .Z(n7974) );
HS65_LH_AND2X4 U3823 ( .A(n3311), .B(n3310), .Z(n3312) );
HS65_LH_CNIVX3 U3824 ( .A(n8586), .Z(n7932) );
HS65_LH_NOR2X2 U3826 ( .A(n3062), .B(n9401), .Z(n8485) );
HS65_LH_CNIVX3 U3827 ( .A(n8608), .Z(n8001) );
HS65_LH_NAND3X2 U3829 ( .A(n9005), .B(n8965), .C(n8091), .Z(n8093) );
HS65_LH_CNIVX3 U3830 ( .A(\u_DataPath/immediate_ext_dec_i [2]), .Z(n8090) );
HS65_LHS_XNOR2X3 U3833 ( .A(n7667), .B(n7666), .Z(\u_DataPath/pc_4_i [7]) );
HS65_LHS_XNOR2X3 U3834 ( .A(n3125), .B(n7672), .Z(\u_DataPath/pc_4_i [15])
);
HS65_LH_CNIVX3 U3835 ( .A(\u_DataPath/jaddr_i [22]), .Z(n8164) );
HS65_LH_NAND2X2 U3836 ( .A(n9084), .B(n9082), .Z(n8056) );
HS65_LH_NAND2X2 U3837 ( .A(n7616), .B(n7615), .Z(n8160) );
HS65_LH_OAI21X3 U3838 ( .A(n9137), .B(n8828), .C(n7847), .Z(
\u_DataPath/dataOut_exe_i [1]) );
HS65_LH_OAI22X1 U3840 ( .A(n9272), .B(n9270), .C(n9119), .D(n8752), .Z(
\u_DataPath/data_read_ex_2_i [15]) );
HS65_LH_OAI21X2 U3842 ( .A(n9189), .B(n9026), .C(n8445), .Z(
\u_DataPath/dataOut_exe_i [29]) );
HS65_LH_OAI22X1 U3844 ( .A(n7917), .B(n8431), .C(n7916), .D(n8430), .Z(
\u_DataPath/data_read_ex_1_i [4]) );
HS65_LH_OAI21X3 U3846 ( .A(n9190), .B(n8903), .C(n8312), .Z(
\u_DataPath/dataOut_exe_i [6]) );
HS65_LH_CNIVX3 U3848 ( .A(n8064), .Z(n8627) );
HS65_LH_NOR2X2 U3851 ( .A(n9168), .B(n9050), .Z(\u_DataPath/u_idexreg/N16 )
);
HS65_LH_CNIVX3 U3853 ( .A(n8240), .Z(\u_DataPath/branch_target_i [27]) );
HS65_LH_CNIVX3 U3854 ( .A(n8259), .Z(\u_DataPath/branch_target_i [10]) );
HS65_LL_OR2X9 U3855 ( .A(n3411), .B(n3410), .Z(n2840) );
HS65_LH_IVX13 U3857 ( .A(\lte_x_59/B[6] ), .Z(n2848) );
HS65_LL_NOR2X13 U3858 ( .A(n3250), .B(n3249), .Z(n2842) );
HS65_LL_OR2X9 U3859 ( .A(n3073), .B(n3072), .Z(n2843) );
HS65_LL_IVX9 U3860 ( .A(\sub_x_53/A[23] ), .Z(n2860) );
HS65_LLS_XNOR2X3 U3861 ( .A(n4160), .B(n4159), .Z(n2844) );
HS65_LL_AND2X18 U3862 ( .A(n5136), .B(n3401), .Z(n2845) );
HS65_LL_NOR3X4 U3864 ( .A(n5165), .B(n5164), .C(n5683), .Z(n7852) );
HS65_LL_NAND3AX13 U3865 ( .A(n2939), .B(n2938), .C(n2937), .Z(n3308) );
HS65_LL_NAND2X4 U3867 ( .A(n8468), .B(n8465), .Z(n4790) );
HS65_LL_AOI12X6 U3868 ( .A(n7631), .B(n4174), .C(n4173), .Z(n8465) );
HS65_LL_NAND3X3 U3869 ( .A(n4857), .B(n4744), .C(n4743), .Z(n4745) );
HS65_LL_NAND3X5 U3871 ( .A(n5561), .B(n5560), .C(n5559), .Z(n5591) );
HS65_LL_AOI12X2 U3874 ( .A(n5606), .B(n3499), .C(n3498), .Z(n3500) );
HS65_LL_NOR2X6 U3878 ( .A(n3320), .B(n3319), .Z(\lte_x_59/B[6] ) );
HS65_LL_NAND2X5 U3879 ( .A(n4365), .B(n4364), .Z(n4366) );
HS65_LL_NAND3X5 U3880 ( .A(n4361), .B(n4360), .C(n4359), .Z(n4362) );
HS65_LL_NAND2AX7 U3881 ( .A(n3551), .B(n2899), .Z(n4886) );
HS65_LL_NOR2X3 U3882 ( .A(n4755), .B(n4754), .Z(n4756) );
HS65_LL_NAND3X5 U3883 ( .A(n3487), .B(n3486), .C(n4593), .Z(n3490) );
HS65_LL_BFX9 U3885 ( .A(n3432), .Z(n2849) );
HS65_LL_OAI12X2 U3886 ( .A(n3366), .B(n5179), .C(n4940), .Z(n4941) );
HS65_LH_OAI112X3 U3887 ( .A(n5334), .B(n5301), .C(n5405), .D(n5479), .Z(
n5308) );
HS65_LL_NOR2X6 U3888 ( .A(\lte_x_59/B[1] ), .B(n4805), .Z(n4823) );
HS65_LLS_XNOR2X3 U3889 ( .A(\lte_x_59/B[1] ), .B(n4805), .Z(n4808) );
HS65_LL_IVX9 U3890 ( .A(n2840), .Z(n2851) );
HS65_LL_NOR2X3 U3891 ( .A(n8355), .B(n9401), .Z(n8525) );
HS65_LL_NOR2X3 U3892 ( .A(n5241), .B(n5240), .Z(n5242) );
HS65_LL_NOR2X6 U3896 ( .A(n3770), .B(n3769), .Z(n4522) );
HS65_LL_AOI12X2 U3897 ( .A(n4587), .B(\lte_x_59/B[15] ), .C(n3982), .Z(n3983) );
HS65_LL_NAND2X5 U3898 ( .A(\lte_x_59/B[4] ), .B(n5032), .Z(n4477) );
HS65_LL_OAI21X3 U3899 ( .A(n5646), .B(n4180), .C(n3660), .Z(n3661) );
HS65_LL_OAI211X3 U3900 ( .A(n5226), .B(n5646), .C(n4586), .D(n4585), .Z(
n4602) );
HS65_LL_NOR2X6 U3901 ( .A(n3773), .B(n3772), .Z(n4513) );
HS65_LL_AOI12X2 U3902 ( .A(n5526), .B(n5525), .C(n5524), .Z(n5538) );
HS65_LL_OAI21X3 U3903 ( .A(n5485), .B(n5337), .C(n5336), .Z(n5338) );
HS65_LL_AOI12X2 U3906 ( .A(n4551), .B(n3521), .C(n4153), .Z(n3455) );
HS65_LL_IVX9 U3907 ( .A(n3521), .Z(n4671) );
HS65_LL_IVX9 U3908 ( .A(n4966), .Z(n2873) );
HS65_LL_NAND2X14 U3909 ( .A(n3967), .B(n2872), .Z(n5152) );
HS65_LL_IVX9 U3912 ( .A(\sub_x_53/A[20] ), .Z(n4700) );
HS65_LLS_XNOR2X3 U3913 ( .A(\sub_x_53/A[20] ), .B(n4699), .Z(n4768) );
HS65_LL_AOI12X2 U3915 ( .A(\lte_x_59/B[7] ), .B(n4588), .C(n3670), .Z(n3920)
);
HS65_LL_IVX2 U3916 ( .A(\lte_x_59/B[7] ), .Z(n5031) );
HS65_LL_NOR2X13 U3917 ( .A(n3200), .B(n3199), .Z(\sub_x_53/A[17] ) );
HS65_LH_IVX13 U3918 ( .A(n5568), .Z(n2853) );
HS65_LL_IVX9 U3919 ( .A(\lte_x_59/B[26] ), .Z(n2854) );
HS65_LL_NAND2X7 U3920 ( .A(n4970), .B(n4974), .Z(n5423) );
HS65_LL_OAI211X1 U3921 ( .A(n5572), .B(n5571), .C(n5570), .D(n5569), .Z(
n5573) );
HS65_LL_NOR2X3 U3922 ( .A(n5571), .B(n4230), .Z(n5453) );
HS65_LL_OAI21X2 U3923 ( .A(n5450), .B(n5571), .C(n5449), .Z(n5451) );
HS65_LL_AOI112X4 U3925 ( .A(\lte_x_59/B[21] ), .B(n4351), .C(n3667), .D(
n3666), .Z(n4185) );
HS65_LL_AOI12X2 U3926 ( .A(\lte_x_59/B[21] ), .B(n4544), .C(n3903), .Z(n4497) );
HS65_LL_OAI21X2 U3928 ( .A(n5388), .B(n5387), .C(n4143), .Z(n5391) );
HS65_LL_IVX9 U3932 ( .A(n2843), .Z(n2858) );
HS65_LL_IVX9 U3933 ( .A(n4674), .Z(n5376) );
HS65_LL_NAND3X5 U3934 ( .A(n3837), .B(n3836), .C(n3835), .Z(n4839) );
HS65_LL_AOI12X6 U3935 ( .A(n3618), .B(n4879), .C(n3617), .Z(n5610) );
HS65_LLS_XNOR2X3 U3936 ( .A(n2849), .B(n5231), .Z(n5232) );
HS65_LLS_XNOR2X3 U3937 ( .A(\sub_x_53/A[0] ), .B(n5136), .Z(n5141) );
HS65_LL_IVX4 U3941 ( .A(n5691), .Z(n3224) );
HS65_LL_OAI21X2 U3942 ( .A(n4573), .B(n5383), .C(n5090), .Z(n5384) );
HS65_LL_AOI12X6 U3943 ( .A(n5672), .B(n5671), .C(n5670), .Z(n5673) );
HS65_LL_AOI12X2 U3945 ( .A(\lte_x_59/B[4] ), .B(n4551), .C(n3400), .Z(n3875)
);
HS65_LLS_XNOR2X3 U3947 ( .A(\lte_x_59/B[8] ), .B(n5373), .Z(n4762) );
HS65_LL_NOR2X6 U3949 ( .A(\lte_x_59/B[5] ), .B(n5040), .Z(n4105) );
HS65_LL_NAND2X4 U3950 ( .A(\lte_x_59/B[5] ), .B(n2864), .Z(n4542) );
HS65_LL_NAND2X5 U3951 ( .A(n3379), .B(n5632), .Z(n3375) );
HS65_LL_NAND2X7 U3952 ( .A(n3751), .B(n3383), .Z(n4330) );
HS65_LL_OAI21X3 U3953 ( .A(n5405), .B(n4049), .C(n4050), .Z(n4917) );
HS65_LL_IVX4 U3954 ( .A(n3474), .Z(n5105) );
HS65_LL_NAND2X4 U3957 ( .A(n4385), .B(n4382), .Z(n4121) );
HS65_LL_NAND2X4 U3959 ( .A(n4836), .B(n4886), .Z(n4382) );
HS65_LL_AOI12X2 U3960 ( .A(\lte_x_59/B[6] ), .B(n4588), .C(n3764), .Z(n3765)
);
HS65_LL_NAND3X3 U3963 ( .A(n8429), .B(n8875), .C(n8896), .Z(
\u_DataPath/dataOut_exe_i [0]) );
HS65_LH_NAND2X2 U3964 ( .A(\u_DataPath/u_execute/ovf_i ), .B(n2733), .Z(
n8423) );
HS65_LL_OAI12X3 U3967 ( .A(n9189), .B(n8901), .C(n8416), .Z(
\u_DataPath/dataOut_exe_i [28]) );
HS65_LL_OAI12X3 U3969 ( .A(n9190), .B(n8900), .C(n8328), .Z(
\u_DataPath/dataOut_exe_i [25]) );
HS65_LL_NAND2X4 U3970 ( .A(n8419), .B(n8899), .Z(
\u_DataPath/dataOut_exe_i [31]) );
HS65_LL_OAI12X3 U3971 ( .A(n9189), .B(n8891), .C(n8359), .Z(
\u_DataPath/dataOut_exe_i [23]) );
HS65_LL_CNIVX3 U3972 ( .A(n5598), .Z(n5599) );
HS65_LL_AOI12X4 U3973 ( .A(n5285), .B(n3628), .C(n3627), .Z(n8478) );
HS65_LL_OAI12X3 U3974 ( .A(n5602), .B(n5598), .C(n4243), .Z(n7841) );
HS65_LL_NAND3X2 U3975 ( .A(n3569), .B(n3568), .C(n3567), .Z(n3570) );
HS65_LL_IVX2 U3977 ( .A(n8464), .Z(n4793) );
HS65_LH_NAND2AX7 U3980 ( .A(n5705), .B(n5704), .Z(n5706) );
HS65_LL_OAI21X2 U3983 ( .A(n5633), .B(n3636), .C(n3635), .Z(n3637) );
HS65_LL_OAI21X2 U3984 ( .A(n3806), .B(n2859), .C(n3805), .Z(n3807) );
HS65_LH_NOR2X6 U3985 ( .A(n5490), .B(n5489), .Z(n5494) );
HS65_LH_IVX4 U3986 ( .A(n2859), .Z(n4297) );
HS65_LH_AOI21X6 U3987 ( .A(n5195), .B(n4238), .C(n4237), .Z(n4239) );
HS65_LH_NOR2X5 U3988 ( .A(n4995), .B(n4994), .Z(n5118) );
HS65_LH_IVX4 U3990 ( .A(n4948), .Z(n4533) );
HS65_LH_CNIVX3 U3991 ( .A(n5250), .Z(n5251) );
HS65_LH_AOI12X2 U3992 ( .A(n3389), .B(n5195), .C(n3388), .Z(n3390) );
HS65_LH_IVX7 U3993 ( .A(n4236), .Z(n4237) );
HS65_LH_NAND2X2 U3994 ( .A(n4512), .B(n5614), .Z(n4150) );
HS65_LL_NAND2X2 U3995 ( .A(n5615), .B(n4388), .Z(n4405) );
HS65_LH_IVX7 U3996 ( .A(n5616), .Z(n5623) );
HS65_LH_AOI21X4 U3997 ( .A(n5029), .B(n5020), .C(n5019), .Z(n5078) );
HS65_LH_IVX18 U3998 ( .A(n4879), .Z(n4929) );
HS65_LH_AOI31X3 U3999 ( .A(n5582), .B(n5581), .C(n5580), .D(n5579), .Z(n5589) );
HS65_LH_NAND3X5 U4001 ( .A(n4431), .B(n5321), .C(n4430), .Z(n3469) );
HS65_LL_NAND3X3 U4003 ( .A(n4010), .B(n4009), .C(n4008), .Z(n4536) );
HS65_LH_CNIVX3 U4004 ( .A(n4816), .Z(n4830) );
HS65_LH_NAND2X7 U4005 ( .A(n5208), .B(n5210), .Z(n3621) );
HS65_LH_AOI13X3 U4006 ( .A(n4845), .B(n4879), .C(n3618), .D(n3561), .Z(n3562) );
HS65_LH_NOR2X3 U4007 ( .A(n5201), .B(n5200), .Z(n5202) );
HS65_LH_NAND2X4 U4008 ( .A(n4086), .B(n3482), .Z(n4090) );
HS65_LH_AOI12X2 U4009 ( .A(n5309), .B(n5308), .C(n5307), .Z(n5339) );
HS65_LH_OAI12X3 U4010 ( .A(n5646), .B(n3966), .C(n3965), .Z(n3977) );
HS65_LH_IVX4 U4012 ( .A(n4606), .Z(n3727) );
HS65_LH_IVX4 U4014 ( .A(n5194), .Z(n5197) );
HS65_LH_NAND2X7 U4015 ( .A(n5192), .B(n5194), .Z(n3578) );
HS65_LH_NAND2X5 U4016 ( .A(n3426), .B(n4164), .Z(n5616) );
HS65_LH_NAND2X7 U4017 ( .A(n4930), .B(n3482), .Z(n4931) );
HS65_LH_OAI21X3 U4018 ( .A(n5226), .B(n3427), .C(n3711), .Z(n3730) );
HS65_LH_NOR2X6 U4019 ( .A(n5528), .B(n5527), .Z(n5584) );
HS65_LH_NOR2X6 U4020 ( .A(n3606), .B(n3605), .Z(n3607) );
HS65_LH_NAND2X5 U4021 ( .A(n3389), .B(n5194), .Z(n3391) );
HS65_LH_NAND2X5 U4022 ( .A(n4270), .B(n4269), .Z(n4271) );
HS65_LH_OAI12X3 U4024 ( .A(n4855), .B(n5620), .C(n4268), .Z(n4274) );
HS65_LH_OAI12X3 U4025 ( .A(n4855), .B(n4522), .C(n4521), .Z(n4532) );
HS65_LH_AOI21X2 U4026 ( .A(n4942), .B(n4839), .C(n3857), .Z(n3886) );
HS65_LH_OAI21X3 U4027 ( .A(n4803), .B(n5176), .C(n4133), .Z(n4137) );
HS65_LH_NOR2X5 U4028 ( .A(n4232), .B(n4330), .Z(n4238) );
HS65_LH_NAND2X5 U4029 ( .A(n5306), .B(n5305), .Z(n5307) );
HS65_LH_NAND2X7 U4030 ( .A(n5520), .B(n5515), .Z(n5541) );
HS65_LH_NOR2X6 U4031 ( .A(n5146), .B(n3858), .Z(n3859) );
HS65_LH_OAI21X3 U4032 ( .A(n5177), .B(n4838), .C(n4837), .Z(n4844) );
HS65_LH_NOR2X5 U4033 ( .A(n5018), .B(n5000), .Z(n5029) );
HS65_LH_NAND3X5 U4034 ( .A(n3776), .B(n3775), .C(n3774), .Z(n3777) );
HS65_LH_NAND2X5 U4035 ( .A(n5659), .B(n5206), .Z(n3428) );
HS65_LH_NOR2X2 U4037 ( .A(n4673), .B(n4684), .Z(n4694) );
HS65_LH_OAI21X3 U4038 ( .A(n4730), .B(n4729), .C(n4728), .Z(n4731) );
HS65_LH_IVX4 U4040 ( .A(n5542), .Z(n5106) );
HS65_LH_IVX9 U4041 ( .A(n4330), .Z(n3389) );
HS65_LH_NAND2X4 U4043 ( .A(n5564), .B(n5346), .Z(n5350) );
HS65_LH_NAND2X5 U4044 ( .A(n4497), .B(n4496), .Z(n4616) );
HS65_LH_NAND2X4 U4045 ( .A(n3426), .B(n4344), .Z(n3587) );
HS65_LL_CNIVX3 U4046 ( .A(n5211), .Z(n5212) );
HS65_LH_AO12X9 U4048 ( .A(n4041), .B(n4040), .C(n4039), .Z(n4042) );
HS65_LH_IVX9 U4050 ( .A(n4515), .Z(n5620) );
HS65_LH_IVX4 U4051 ( .A(n4610), .Z(n3865) );
HS65_LH_NOR2X5 U4052 ( .A(n4954), .B(n3555), .Z(n4874) );
HS65_LH_NAND3X3 U4054 ( .A(n3426), .B(n5672), .C(n4344), .Z(n3581) );
HS65_LH_NOR2X5 U4055 ( .A(n5241), .B(n5172), .Z(n3438) );
HS65_LH_IVX4 U4057 ( .A(n4304), .Z(n4307) );
HS65_LHS_XOR2X6 U4058 ( .A(n4574), .B(n4540), .Z(n4569) );
HS65_LH_NAND3X5 U4059 ( .A(n2864), .B(n6123), .C(n4806), .Z(n4807) );
HS65_LH_OAI21X3 U4060 ( .A(n5176), .B(n5135), .C(n5134), .Z(n5150) );
HS65_LH_NAND2X4 U4061 ( .A(n5618), .B(n5644), .Z(n4521) );
HS65_LH_IVX7 U4062 ( .A(n5644), .Z(n5645) );
HS65_LH_NAND2X7 U4063 ( .A(n4211), .B(n4290), .Z(n4220) );
HS65_LH_IVX4 U4064 ( .A(n4497), .Z(n4498) );
HS65_LH_CNIVX3 U4065 ( .A(n4500), .Z(n4501) );
HS65_LH_NOR2X6 U4066 ( .A(n4924), .B(n3936), .Z(n3939) );
HS65_LH_IVX9 U4067 ( .A(n5274), .Z(n4245) );
HS65_LH_IVX7 U4068 ( .A(n4016), .Z(n3950) );
HS65_LH_NOR3X2 U4070 ( .A(n4502), .B(n5152), .C(n4197), .Z(n4028) );
HS65_LH_NAND2X5 U4071 ( .A(n5270), .B(n3197), .Z(n5279) );
HS65_LH_NOR3X4 U4072 ( .A(n3783), .B(n3820), .C(n3782), .Z(n4526) );
HS65_LH_IVX4 U4075 ( .A(n4702), .Z(n4703) );
HS65_LH_NAND2X5 U4076 ( .A(n5286), .B(n5572), .Z(n5287) );
HS65_LH_NAND2X7 U4077 ( .A(n5572), .B(n4727), .Z(n4730) );
HS65_LH_IVX7 U4078 ( .A(n5507), .Z(n5510) );
HS65_LH_IVX4 U4079 ( .A(n4761), .Z(n3451) );
HS65_LH_NOR2X3 U4081 ( .A(n4939), .B(n4938), .Z(n4946) );
HS65_LH_NOR2X2 U4082 ( .A(n5421), .B(n5441), .Z(n5429) );
HS65_LH_OAI31X5 U4083 ( .A(n5133), .B(n5139), .C(n5132), .D(n5131), .Z(n5134) );
HS65_LH_IVX7 U4085 ( .A(n4488), .Z(n4489) );
HS65_LH_AOI21X6 U4086 ( .A(\lte_x_59/B[28] ), .B(n2864), .C(n3548), .Z(n3586) );
HS65_LH_IVX4 U4088 ( .A(n4930), .Z(n3936) );
HS65_LH_IVX7 U4089 ( .A(n5269), .Z(n3197) );
HS65_LH_NAND2X4 U4091 ( .A(n3559), .B(n3472), .Z(n3565) );
HS65_LH_NOR2X6 U4092 ( .A(\lte_x_59/B[28] ), .B(n5423), .Z(n4320) );
HS65_LH_NOR2X2 U4093 ( .A(n4630), .B(n4626), .Z(n4633) );
HS65_LH_NAND2X4 U4094 ( .A(n3474), .B(n2864), .Z(n4590) );
HS65_LH_NAND2X7 U4095 ( .A(n4930), .B(n3478), .Z(n3481) );
HS65_LH_AOI21X4 U4096 ( .A(n3478), .B(n4927), .C(n3477), .Z(n3479) );
HS65_LH_NOR2X6 U4097 ( .A(n3474), .B(n3359), .Z(n3949) );
HS65_LH_IVX7 U4098 ( .A(n3819), .Z(n3824) );
HS65_LH_NAND2X5 U4100 ( .A(n3832), .B(n3956), .Z(n3460) );
HS65_LH_OAI12X3 U4101 ( .A(n5356), .B(n5363), .C(n5292), .Z(n5586) );
HS65_LH_NAND2X7 U4102 ( .A(n3763), .B(n5127), .Z(n3766) );
HS65_LH_IVX4 U4104 ( .A(n3840), .Z(n3768) );
HS65_LH_NAND2X4 U4106 ( .A(n5234), .B(n5233), .Z(n5235) );
HS65_LH_NAND2X5 U4107 ( .A(n5256), .B(n5255), .Z(n5265) );
HS65_LH_OAI12X3 U4108 ( .A(n3749), .B(n3629), .C(n5443), .Z(n5444) );
HS65_LH_NAND2X2 U4109 ( .A(n4373), .B(n4372), .Z(n4379) );
HS65_LH_IVX9 U4110 ( .A(n5319), .Z(n5465) );
HS65_LH_NOR2X5 U4112 ( .A(n4765), .B(n4764), .Z(n4766) );
HS65_LH_NAND2X7 U4113 ( .A(\lte_x_59/B[28] ), .B(n3129), .Z(n4331) );
HS65_LH_IVX4 U4116 ( .A(n3838), .Z(n3434) );
HS65_LH_NOR2X5 U4117 ( .A(n4742), .B(n4741), .Z(n4743) );
HS65_LH_OAI21X3 U4120 ( .A(n4795), .B(n4671), .C(n4062), .Z(n3645) );
HS65_LH_IVX9 U4121 ( .A(n4507), .Z(n4197) );
HS65_LH_OAI12X3 U4123 ( .A(n4675), .B(n5129), .C(n3644), .Z(n3646) );
HS65_LH_NOR2X5 U4125 ( .A(n4682), .B(n5129), .Z(n4156) );
HS65_LH_IVX4 U4126 ( .A(n4034), .Z(n4035) );
HS65_LH_NAND2X7 U4127 ( .A(\lte_x_59/B[9] ), .B(n4587), .Z(n3870) );
HS65_LH_NAND2X5 U4128 ( .A(\lte_x_59/B[22] ), .B(n4551), .Z(n3963) );
HS65_LH_CNIVX3 U4130 ( .A(n5254), .Z(n5255) );
HS65_LH_IVX4 U4131 ( .A(n5232), .Z(n5233) );
HS65_LH_IVX4 U4132 ( .A(n4084), .Z(n4088) );
HS65_LH_CNIVX3 U4133 ( .A(n4371), .Z(n4372) );
HS65_LH_NAND2X5 U4134 ( .A(\sub_x_53/A[30] ), .B(n4966), .Z(n4289) );
HS65_LH_NAND2AX7 U4136 ( .A(n5320), .B(n2864), .Z(n5127) );
HS65_LL_OAI21X2 U4137 ( .A(n5258), .B(n5254), .C(n5256), .Z(n3496) );
HS65_LH_NAND2X4 U4138 ( .A(\lte_x_59/B[4] ), .B(n4544), .Z(n3763) );
HS65_LH_IVX4 U4139 ( .A(n4924), .Z(n4925) );
HS65_LH_IVX4 U4142 ( .A(n3800), .Z(n3801) );
HS65_LH_NOR2X6 U4143 ( .A(n4711), .B(n5129), .Z(n3548) );
HS65_LH_IVX4 U4144 ( .A(n5509), .Z(n5364) );
HS65_LH_NAND2X7 U4145 ( .A(\sub_x_53/A[30] ), .B(n4587), .Z(n3544) );
HS65_LH_NOR2X6 U4146 ( .A(n4637), .B(n4643), .Z(n3353) );
HS65_LH_NOR2X5 U4147 ( .A(n4700), .B(n4699), .Z(n5471) );
HS65_LH_NOR2X3 U4148 ( .A(n4986), .B(n5005), .Z(n5355) );
HS65_LH_IVX9 U4149 ( .A(n5531), .Z(n5511) );
HS65_LH_IVX4 U4150 ( .A(n4740), .Z(n4741) );
HS65_LH_NAND2X4 U4153 ( .A(n5004), .B(n5231), .Z(n5534) );
HS65_LH_IVX9 U4154 ( .A(n4672), .Z(n5294) );
HS65_LH_IVX7 U4155 ( .A(n5396), .Z(n5335) );
HS65_LH_NAND2X5 U4156 ( .A(n4671), .B(n5048), .Z(n5516) );
HS65_LH_IVX4 U4158 ( .A(n4768), .Z(n4441) );
HS65_LH_NAND2X4 U4159 ( .A(\lte_x_59/B[16] ), .B(n4551), .Z(n3839) );
HS65_LH_NOR2X3 U4161 ( .A(n3529), .B(n5022), .Z(n4850) );
HS65_LH_IVX9 U4162 ( .A(n5193), .Z(n3576) );
HS65_LH_IVX7 U4163 ( .A(n4774), .Z(n3610) );
HS65_LH_NAND2X5 U4164 ( .A(n5397), .B(n3231), .Z(n3853) );
HS65_LH_NAND2X5 U4165 ( .A(\lte_x_59/B[16] ), .B(n4985), .Z(n5506) );
HS65_LH_NAND2X7 U4166 ( .A(\u_DataPath/u_idexreg/N3 ), .B(n4512), .Z(n4939)
);
HS65_LH_IVX18 U4168 ( .A(n4726), .Z(\sub_x_53/A[30] ) );
HS65_LL_NOR2X2 U4169 ( .A(\lte_x_59/B[24] ), .B(n3382), .Z(n3575) );
HS65_LH_NAND2AX7 U4170 ( .A(\lte_x_59/B[14] ), .B(n5061), .Z(n4672) );
HS65_LH_IVX4 U4172 ( .A(n5095), .Z(n5096) );
HS65_LH_IVX4 U4173 ( .A(n5327), .Z(n5097) );
HS65_LL_BFX9 U4175 ( .A(n3547), .Z(\sub_x_53/A[27] ) );
HS65_LH_NAND2X7 U4176 ( .A(n2853), .B(n3384), .Z(n3749) );
HS65_LH_IVX4 U4177 ( .A(n4573), .Z(n4661) );
HS65_LL_NAND2X4 U4179 ( .A(\lte_x_59/B[18] ), .B(n5005), .Z(n5258) );
HS65_LH_NOR2X5 U4180 ( .A(n2849), .B(n5231), .Z(n5254) );
HS65_LH_NAND2X4 U4181 ( .A(n4624), .B(n4623), .Z(n4635) );
HS65_LL_CNBFX10 U4182 ( .A(n2856), .Z(n4583) );
HS65_LL_IVX18 U4184 ( .A(n3756), .Z(n4551) );
HS65_LH_OAI22X4 U4185 ( .A(n7096), .B(n8353), .C(n7900), .D(n8349), .Z(
\u_DataPath/data_read_ex_2_i [22]) );
HS65_LH_OAI22X4 U4186 ( .A(n7096), .B(n8343), .C(n7900), .D(n8338), .Z(
\u_DataPath/data_read_ex_2_i [13]) );
HS65_LH_OAI22X4 U4187 ( .A(n7096), .B(n8348), .C(n7900), .D(n8344), .Z(
\u_DataPath/data_read_ex_2_i [11]) );
HS65_LH_OAI22X4 U4188 ( .A(n7096), .B(n8337), .C(n7900), .D(n8331), .Z(
\u_DataPath/data_read_ex_2_i [9]) );
HS65_LL_NOR2X6 U4190 ( .A(n3061), .B(n3060), .Z(\lte_x_59/B[21] ) );
HS65_LH_IVX7 U4191 ( .A(n4769), .Z(n4553) );
HS65_LL_NOR2X6 U4194 ( .A(n3266), .B(n3265), .Z(n3521) );
HS65_LH_CNIVX3 U4195 ( .A(n4596), .Z(n4561) );
HS65_LL_IVX4 U4196 ( .A(n5104), .Z(n3359) );
HS65_LH_IVX18 U4199 ( .A(n5652), .Z(\lte_x_59/B[22] ) );
HS65_LH_IVX18 U4200 ( .A(n5054), .Z(\lte_x_59/B[9] ) );
HS65_LH_OAI22X6 U4201 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [27]), .C(
n8374), .D(n3409), .Z(n3107) );
HS65_LH_NOR2X3 U4204 ( .A(n9167), .B(n8916), .Z(\u_DataPath/cw_exmem_i [4])
);
HS65_LL_NOR2X3 U4205 ( .A(n3118), .B(n7770), .Z(n7780) );
HS65_LL_NAND3X5 U4206 ( .A(n2903), .B(n3081), .C(n3080), .Z(n5054) );
HS65_LHS_XOR2X3 U4207 ( .A(n3118), .B(n7770), .Z(\u_DataPath/pc_4_i [28]) );
HS65_LL_NAND2X5 U4209 ( .A(n8272), .B(n8298), .Z(n8452) );
HS65_LH_AO22X9 U4210 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][18] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][18] ), .D(
n7586), .Z(n6335) );
HS65_LH_AO22X9 U4211 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][18] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][18] ), .D(
n7318), .Z(n6336) );
HS65_LH_AO22X9 U4212 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][25] ), .B(n7578),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][25] ), .Z(n7037)
);
HS65_LH_AO22X9 U4214 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][25] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][25] ), .D(
n7318), .Z(n7041) );
HS65_LH_AO22X9 U4215 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][9] ), .B(n7578),
.C(n7310), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][9] ), .Z(n7017) );
HS65_LH_AOI22X3 U4216 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][9] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][9] ), .D(
n6625), .Z(n7129) );
HS65_LH_AOI22X3 U4219 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][9] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][9] ), .D(
n6624), .Z(n7130) );
HS65_LH_AOI22X3 U4220 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][18] ), .B(n7525),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][18] ), .Z(n6343)
);
HS65_LH_AO22X9 U4222 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][9] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][9] ), .D(n7318), .Z(n7021) );
HS65_LH_AO22X9 U4223 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][19] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][19] ), .D(
n7318), .Z(n6749) );
HS65_LH_AOI22X3 U4224 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][31] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][31] ), .D(
n2891), .Z(n6674) );
HS65_LH_AOI22X3 U4226 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][21] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][21] ), .Z(n7606)
);
HS65_LH_AO22X9 U4227 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][26] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][26] ), .D(
n7318), .Z(n7322) );
HS65_LH_AOI22X3 U4228 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][23] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][23] ), .D(
n6625), .Z(n6231) );
HS65_LH_AOI22X3 U4229 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][29] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][29] ), .Z(n7531)
);
HS65_LH_AO22X9 U4230 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][10] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][10] ), .D(
n7318), .Z(n7209) );
HS65_LH_AOI22X3 U4234 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][5] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][5] ), .D(n6957), .Z(n6705) );
HS65_LH_AOI22X3 U4237 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][31] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][31] ), .D(
n6957), .Z(n6678) );
HS65_LH_AO22X9 U4238 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][8] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][8] ), .D(n7318), .Z(n6772) );
HS65_LH_AOI22X3 U4239 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][8] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][8] ), .D(n6957), .Z(n6773) );
HS65_LH_AOI22X3 U4240 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][17] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][17] ), .D(
n6957), .Z(n6813) );
HS65_LH_AOI22X3 U4241 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][16] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][16] ), .Z(n7551)
);
HS65_LH_AOI22X3 U4242 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][20] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][20] ), .Z(n7485)
);
HS65_LH_AOI22X3 U4245 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][2] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][2] ), .Z(n6962)
);
HS65_LH_AO22X9 U4246 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][15] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][15] ), .D(
n7318), .Z(n7189) );
HS65_LH_AOI22X3 U4247 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][24] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][24] ), .Z(n7571)
);
HS65_LH_AO22X9 U4249 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][11] ), .B(n7578),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][11] ), .Z(n7057)
);
HS65_LH_AO22X9 U4251 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][11] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][11] ), .D(
n7318), .Z(n7061) );
HS65_LH_AOI22X3 U4253 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][4] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][4] ), .D(
n7285), .Z(n6639) );
HS65_LH_AO22X9 U4254 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][4] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][4] ), .D(
n7282), .Z(n6641) );
HS65_LH_AOI22X3 U4255 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][27] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][27] ), .Z(n7465)
);
HS65_LH_AO22X9 U4257 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][22] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][22] ), .D(
n7318), .Z(n7001) );
HS65_LH_AO22X9 U4258 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][22] ), .B(n7578),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][22] ), .Z(n6997)
);
HS65_LH_AOI22X3 U4262 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][12] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][12] ), .D(
n6957), .Z(n6793) );
HS65_LH_AOI22X3 U4263 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][7] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][7] ), .D(n6957), .Z(n6725) );
HS65_LH_AOI22X3 U4265 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][30] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][30] ), .D(
n6625), .Z(n6136) );
HS65_LH_AO22X9 U4267 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][12] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][12] ), .D(
n7318), .Z(n6792) );
HS65_LH_AO22X9 U4268 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][13] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][13] ), .D(
n7318), .Z(n6981) );
HS65_LH_AOI22X4 U4272 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][30] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][30] ), .Z(n7409)
);
HS65_LH_AOI22X4 U4273 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][30] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][30] ), .Z(n7410)
);
HS65_LH_AO22X9 U4275 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][7] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][7] ), .D(n7318), .Z(n6724) );
HS65_LH_AOI22X3 U4276 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][0] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][0] ), .Z(n7445)
);
HS65_LH_AOI22X3 U4277 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][7] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][7] ), .D(
n2891), .Z(n6722) );
HS65_LH_AO22X9 U4278 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][6] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][6] ), .D(n7318), .Z(n7249) );
HS65_LH_AO22X9 U4279 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][13] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][13] ), .D(
n6629), .Z(n7166) );
HS65_LL_AOI12X4 U4280 ( .A(n6105), .B(n6107), .C(n5941), .Z(n5974) );
HS65_LL_OAI12X2 U4282 ( .A(n8266), .B(n3340), .C(n3104), .Z(n3105) );
HS65_LH_IVX9 U4283 ( .A(n8497), .Z(n3323) );
HS65_LH_NOR2X6 U4284 ( .A(n8867), .B(n3341), .Z(n3342) );
HS65_LH_NOR2X6 U4285 ( .A(n3275), .B(n8522), .Z(n3276) );
HS65_LH_NOR2X2 U4286 ( .A(rst), .B(n8554), .Z(
\u_DataPath/mem_writedata_out_i [25]) );
HS65_LH_NOR2X6 U4289 ( .A(n8861), .B(n3341), .Z(n3064) );
HS65_LL_NAND3X3 U4291 ( .A(n8135), .B(n8134), .C(n8318), .Z(n8301) );
HS65_LL_IVX9 U4293 ( .A(n4712), .Z(n3291) );
HS65_LH_NOR2X6 U4294 ( .A(n3274), .B(n7868), .Z(n8522) );
HS65_LH_NAND2X5 U4295 ( .A(n4714), .B(n8524), .Z(n3275) );
HS65_LH_NOR2X6 U4296 ( .A(n8243), .B(n7868), .Z(n8547) );
HS65_LH_NAND2X4 U4297 ( .A(n8044), .B(n8043), .Z(opcode_i[0]) );
HS65_LH_NAND2X5 U4298 ( .A(n4714), .B(n8553), .Z(n3141) );
HS65_LH_NAND2X4 U4299 ( .A(n8044), .B(n8036), .Z(opcode_i[2]) );
HS65_LL_NOR2X3 U4302 ( .A(n3119), .B(n7759), .Z(n7704) );
HS65_LH_BFX18 U4303 ( .A(n8483), .Z(n7922) );
HS65_LL_AOI12X4 U4305 ( .A(\u_DataPath/dataOut_exe_i [0]), .B(n8573), .C(
n8133), .Z(n8318) );
HS65_LH_BFX18 U4306 ( .A(n8483), .Z(n7923) );
HS65_LH_AOI21X6 U4308 ( .A(n2896), .B(n3299), .C(n3298), .Z(n3300) );
HS65_LH_NAND2X7 U4309 ( .A(n3260), .B(n2866), .Z(n8514) );
HS65_LH_NAND2X7 U4310 ( .A(n2896), .B(n3257), .Z(n6125) );
HS65_LH_NAND2X4 U4312 ( .A(n3307), .B(n3407), .Z(n3304) );
HS65_LH_NOR2X5 U4313 ( .A(n7854), .B(n9401), .Z(n8528) );
HS65_LH_NOR2X6 U4315 ( .A(\u_DataPath/dataOut_exe_i [21]), .B(n8390), .Z(
n8541) );
HS65_LH_AOI21X2 U4316 ( .A(n6016), .B(n6083), .C(n6015), .Z(n6017) );
HS65_LH_NAND2X4 U4317 ( .A(n8574), .B(n3407), .Z(n3344) );
HS65_LH_NAND2X5 U4320 ( .A(n4213), .B(n7869), .Z(n8565) );
HS65_LH_OAI12X3 U4323 ( .A(n8177), .B(n8132), .C(n2733), .Z(n8133) );
HS65_LL_NAND2X4 U4324 ( .A(n9213), .B(n7118), .Z(n7796) );
HS65_LH_NAND2X4 U4325 ( .A(n9112), .B(n8576), .Z(n8134) );
HS65_LH_AOI12X2 U4326 ( .A(n5808), .B(n5868), .C(n5807), .Z(n5809) );
HS65_LH_NAND2X5 U4327 ( .A(n3127), .B(n3407), .Z(n4971) );
HS65_LH_OAI21X2 U4328 ( .A(n7762), .B(n7761), .C(n7760), .Z(n8124) );
HS65_LH_NAND2X4 U4330 ( .A(n3193), .B(n7802), .Z(n8533) );
HS65_LL_NAND2X21 U4332 ( .A(n2733), .B(n8034), .Z(
\u_DataPath/u_fetch/pc1/N3 ) );
HS65_LL_OAI12X3 U4333 ( .A(n5736), .B(n5799), .C(n5735), .Z(n5904) );
HS65_LL_BFX27 U4334 ( .A(n7802), .Z(n7869) );
HS65_LL_IVX9 U4335 ( .A(n3333), .Z(n3407) );
HS65_LH_NOR2X5 U4336 ( .A(n7724), .B(n7720), .Z(n7721) );
HS65_LH_NAND2X4 U4337 ( .A(n3256), .B(n7802), .Z(n8515) );
HS65_LH_IVX7 U4338 ( .A(n2879), .Z(n3110) );
HS65_LH_NAND2X5 U4339 ( .A(n8680), .B(n7746), .Z(n7747) );
HS65_LH_IVX9 U4340 ( .A(n7614), .Z(n7615) );
HS65_LH_NOR2X5 U4341 ( .A(n7834), .B(n3968), .Z(n4192) );
HS65_LH_IVX7 U4342 ( .A(n7903), .Z(n4243) );
HS65_LL_IVX18 U4343 ( .A(n3308), .Z(n7802) );
HS65_LHS_XNOR2X3 U4344 ( .A(n6104), .B(n6103), .Z(
\u_DataPath/u_execute/resAdd1_i [3]) );
HS65_LH_IVX7 U4347 ( .A(n3111), .Z(n8577) );
HS65_LL_NAND2X5 U4349 ( .A(n2981), .B(n3111), .Z(n3114) );
HS65_LHS_XOR2X3 U4350 ( .A(n7788), .B(n7787), .Z(
\u_DataPath/u_execute/link_value_i [6]) );
HS65_LH_NOR2X5 U4351 ( .A(n5932), .B(n5964), .Z(n5934) );
HS65_LH_NOR2X6 U4352 ( .A(n7680), .B(n7741), .Z(n7746) );
HS65_LL_NOR2X5 U4355 ( .A(n6349), .B(n6333), .Z(n6746) );
HS65_LH_CNIVX3 U4356 ( .A(n5798), .Z(n5802) );
HS65_LH_IVX7 U4357 ( .A(n7676), .Z(n7678) );
HS65_LH_CNIVX3 U4358 ( .A(n8284), .Z(\u_DataPath/branch_target_i [0]) );
HS65_LH_NOR2X6 U4359 ( .A(n5730), .B(n5760), .Z(n5732) );
HS65_LH_NOR3X4 U4360 ( .A(\u_DataPath/immediate_ext_dec_i [2]), .B(n8162),
.C(n7703), .Z(n8098) );
HS65_LH_NAND2X5 U4361 ( .A(n2733), .B(n8266), .Z(n8304) );
HS65_LH_NAND2X4 U4362 ( .A(n2733), .B(n8255), .Z(n8293) );
HS65_LH_IVX4 U4363 ( .A(n8380), .Z(n4207) );
HS65_LH_AOI21X6 U4364 ( .A(n6051), .B(n5922), .C(n5921), .Z(n6034) );
HS65_LH_NAND2X5 U4365 ( .A(n8316), .B(n2733), .Z(n8321) );
HS65_LH_NAND2X5 U4368 ( .A(n2733), .B(n8243), .Z(n8362) );
HS65_LH_NAND2X4 U4370 ( .A(n2733), .B(\u_DataPath/toPC2_i [0]), .Z(n8284) );
HS65_LH_IVX9 U4371 ( .A(n8323), .Z(n8537) );
HS65_LH_NAND2X5 U4372 ( .A(n2733), .B(n8176), .Z(n8422) );
HS65_LH_NAND2X4 U4373 ( .A(n2733), .B(n8339), .Z(n8343) );
HS65_LH_NAND2X5 U4374 ( .A(n2733), .B(n8374), .Z(n8378) );
HS65_LH_NAND2X4 U4375 ( .A(n2733), .B(n8394), .Z(n8434) );
HS65_LH_NAND2X5 U4376 ( .A(n2733), .B(n8364), .Z(n8367) );
HS65_LH_NAND2X5 U4377 ( .A(n2733), .B(n8355), .Z(n8358) );
HS65_LH_NAND2X5 U4378 ( .A(n2733), .B(n8550), .Z(n8372) );
HS65_LH_OAI21X6 U4379 ( .A(n3404), .B(n3023), .C(n3022), .Z(n5716) );
HS65_LH_IVX4 U4380 ( .A(n5844), .Z(n5898) );
HS65_LH_NAND2X4 U4381 ( .A(n2733), .B(n8332), .Z(n8337) );
HS65_LH_IVX4 U4382 ( .A(n5757), .Z(n5763) );
HS65_LH_IVX4 U4383 ( .A(n5761), .Z(n5762) );
HS65_LH_CNIVX3 U4385 ( .A(n5779), .Z(n5782) );
HS65_LH_NAND2X4 U4386 ( .A(n2733), .B(n8389), .Z(n8404) );
HS65_LH_IVX9 U4387 ( .A(n4175), .Z(n3288) );
HS65_LH_NAND2X5 U4389 ( .A(n2733), .B(n8393), .Z(n8431) );
HS65_LL_NOR3X2 U4391 ( .A(\u_DataPath/cw_to_ex_i [15]), .B(n8755), .C(n8263),
.Z(n8451) );
HS65_LH_NOR2X2 U4393 ( .A(n8065), .B(rst), .Z(
\u_DataPath/regfile_addr_out_towb_i [2]) );
HS65_LH_NOR2X5 U4395 ( .A(n8042), .B(rst), .Z(\u_DataPath/idex_rt_i [3]) );
HS65_LH_IVX4 U4397 ( .A(n5687), .Z(n5689) );
HS65_LH_NOR2X2 U4398 ( .A(n8108), .B(rst), .Z(
\u_DataPath/regfile_addr_out_towb_i [0]) );
HS65_LH_NOR2X3 U4399 ( .A(n8574), .B(rst), .Z(n8579) );
HS65_LL_NAND2X5 U4401 ( .A(\u_DataPath/jaddr_i [16]), .B(n8153), .Z(n6353)
);
HS65_LH_NAND2X5 U4402 ( .A(n2733), .B(n8311), .Z(n8314) );
HS65_LH_CNIVX3 U4403 ( .A(n7725), .Z(n7789) );
HS65_LH_NOR2X2 U4405 ( .A(n8063), .B(rst), .Z(
\u_DataPath/regfile_addr_out_towb_i [3]) );
HS65_LH_IVX4 U4406 ( .A(n5820), .Z(n5866) );
HS65_LH_NAND2X2 U4407 ( .A(\u_DataPath/cw_to_ex_i [2]), .B(n7834), .Z(n4786)
);
HS65_LH_IVX7 U4408 ( .A(\u_DataPath/dataOut_exe_i [24]), .Z(n3140) );
HS65_LH_IVX4 U4409 ( .A(\u_DataPath/immediate_ext_dec_i [0]), .Z(n8130) );
HS65_LH_IVX4 U4410 ( .A(n9077), .Z(n2943) );
HS65_LH_NAND2X5 U4412 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [10]),
.Z(n8182) );
HS65_LH_NAND2X5 U4413 ( .A(n9177), .B(n9229), .Z(n5877) );
HS65_LH_NAND2X5 U4416 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [9]),
.Z(n8185) );
HS65_LH_NAND2X5 U4417 ( .A(n9030), .B(n9223), .Z(n5838) );
HS65_LH_NAND2X5 U4418 ( .A(n9343), .B(n9221), .Z(n5819) );
HS65_LH_NAND2X7 U4419 ( .A(n9223), .B(n9219), .Z(n4001) );
HS65_LH_NOR2X6 U4420 ( .A(n9341), .B(n9218), .Z(n5795) );
HS65_LH_NAND2X2 U4421 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [2]), .Z(
n8228) );
HS65_LH_NAND2X2 U4422 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [0]), .Z(
n8230) );
HS65_LH_NAND2X5 U4424 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [8]),
.Z(n8186) );
HS65_LH_IVX7 U4425 ( .A(\u_DataPath/dataOut_exe_i [18]), .Z(n3193) );
HS65_LH_NOR2X6 U4427 ( .A(n9267), .B(n9228), .Z(n5786) );
HS65_LH_NOR3X3 U4428 ( .A(n8755), .B(n9151), .C(\u_DataPath/cw_to_ex_i [15]),
.Z(n8264) );
HS65_LH_NAND2X5 U4430 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [7]),
.Z(n8179) );
HS65_LH_IVX4 U4431 ( .A(n8876), .Z(n4715) );
HS65_LH_IVX9 U4432 ( .A(\u_DataPath/dataOut_exe_i [25]), .Z(n3132) );
HS65_LH_NAND2X5 U4433 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [6]),
.Z(n8187) );
HS65_LH_NAND2X2 U4435 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [20]),
.Z(n8205) );
HS65_LH_NAND2X2 U4436 ( .A(n2733), .B(n9427), .Z(n8196) );
HS65_LH_IVX7 U4437 ( .A(n9236), .Z(n2975) );
HS65_LH_NAND2X2 U4438 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [6]), .Z(
n8224) );
HS65_LH_IVX7 U4439 ( .A(\u_DataPath/dataOut_exe_i [13]), .Z(n3252) );
HS65_LH_IVX7 U4440 ( .A(\u_DataPath/dataOut_exe_i [4]), .Z(n8574) );
HS65_LH_IVX9 U4441 ( .A(\u_DataPath/from_mem_data_out_i [1]), .Z(n3021) );
HS65_LH_NAND2X2 U4442 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [19]),
.Z(n8206) );
HS65_LH_NAND2X2 U4443 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [27]),
.Z(n8194) );
HS65_LH_NOR2X5 U4444 ( .A(n8943), .B(n9210), .Z(n6026) );
HS65_LH_NAND2X2 U4445 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [7]), .Z(
n8223) );
HS65_LH_NAND2X2 U4446 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [8]), .Z(
n8222) );
HS65_LH_NAND2X2 U4447 ( .A(n2733), .B(n9426), .Z(n8208) );
HS65_LH_NAND2X2 U4448 ( .A(n2733), .B(n9425), .Z(n8193) );
HS65_LH_NAND2X2 U4449 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [17]),
.Z(n8209) );
HS65_LH_NAND2X2 U4450 ( .A(n2733), .B(n9424), .Z(n8211) );
HS65_LH_IVX7 U4451 ( .A(\u_DataPath/dataOut_exe_i [11]), .Z(n3232) );
HS65_LH_NAND2X2 U4452 ( .A(n2733), .B(n9423), .Z(n8221) );
HS65_LH_NAND2X2 U4455 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [29]),
.Z(n8191) );
HS65_LH_NAND2X7 U4456 ( .A(n8968), .B(n9217), .Z(n5997) );
HS65_LH_NAND2X2 U4457 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [10]),
.Z(n8219) );
HS65_LH_NAND2X7 U4458 ( .A(n9077), .B(n9218), .Z(n6063) );
HS65_LH_NAND2X2 U4459 ( .A(n2733), .B(n9422), .Z(n8218) );
HS65_LH_NAND2X2 U4460 ( .A(n2733), .B(n9421), .Z(n8190) );
HS65_LH_NAND2X2 U4461 ( .A(n2733), .B(n9419), .Z(n8216) );
HS65_LH_IVX7 U4462 ( .A(\u_DataPath/dataOut_exe_i [10]), .Z(n3242) );
HS65_LH_NAND2X2 U4463 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [13]),
.Z(n8214) );
HS65_LH_NAND2X2 U4464 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [15]),
.Z(n8212) );
HS65_LH_IVX4 U4465 ( .A(n9226), .Z(n7724) );
HS65_LH_NAND2X2 U4466 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [31]),
.Z(n8289) );
HS65_LH_NAND2X2 U4467 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [14]),
.Z(n8213) );
HS65_LH_NAND2X2 U4468 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [1]), .Z(
n8229) );
HS65_LH_IVX9 U4469 ( .A(n8724), .Z(n3345) );
HS65_LH_NAND2X5 U4470 ( .A(n9033), .B(n9215), .Z(n6099) );
HS65_LH_NAND2X7 U4471 ( .A(n8913), .B(n9219), .Z(n6094) );
HS65_LH_NAND2X2 U4472 ( .A(n2733), .B(n9420), .Z(n8200) );
HS65_LH_IVX2 U4474 ( .A(n9116), .Z(\u_DataPath/u_execute/link_value_i [2])
);
HS65_LH_NAND2X7 U4475 ( .A(n9030), .B(n9223), .Z(n6040) );
HS65_LH_NAND2X2 U4476 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [3]), .Z(
n8227) );
HS65_LH_NAND2X2 U4477 ( .A(n2733), .B(n9429), .Z(n8202) );
HS65_LH_NAND2X2 U4478 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [25]),
.Z(n8197) );
HS65_LH_NAND2X2 U4479 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [4]), .Z(
n8226) );
HS65_LH_NAND2X2 U4480 ( .A(n2733), .B(n9428), .Z(n8204) );
HS65_LH_IVX4 U4481 ( .A(n9230), .Z(n7793) );
HS65_LH_NAND2X2 U4483 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [5]), .Z(
n8225) );
HS65_LH_NAND2X2 U4484 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [24]),
.Z(n8198) );
HS65_LH_IVX7 U4487 ( .A(\u_DataPath/dataOut_exe_i [5]), .Z(n3336) );
HS65_LL_IVX7 U4489 ( .A(\u_DataPath/jaddr_i [16]), .Z(n8152) );
HS65_LH_IVX2 U4490 ( .A(Data_out_fromRAM[30]), .Z(n8402) );
HS65_LH_IVX2 U4491 ( .A(Data_out_fromRAM[29]), .Z(n8447) );
HS65_LH_IVX2 U4493 ( .A(Data_out_fromRAM[24]), .Z(n8370) );
HS65_LH_IVX2 U4494 ( .A(Data_out_fromRAM[27]), .Z(n8376) );
HS65_LH_IVX2 U4495 ( .A(Data_out_fromRAM[26]), .Z(n8319) );
HS65_LH_IVX2 U4496 ( .A(Data_out_fromRAM[25]), .Z(n8335) );
HS65_LH_OAI12X6 U4497 ( .A(n5715), .B(n5714), .C(n5713), .Z(n7860) );
HS65_LL_NAND2X4 U4498 ( .A(n7907), .B(n5694), .Z(n7855) );
HS65_LL_NAND2X2 U4499 ( .A(n7858), .B(n9063), .Z(
\u_DataPath/dataOut_exe_i [19]) );
HS65_LL_OAI12X3 U4501 ( .A(n9189), .B(n9001), .C(n8395), .Z(
\u_DataPath/dataOut_exe_i [30]) );
HS65_LL_OAI12X3 U4502 ( .A(n9189), .B(n8895), .C(n8398), .Z(
\u_DataPath/dataOut_exe_i [14]) );
HS65_LL_NAND2X2 U4503 ( .A(n7845), .B(n9060), .Z(
\u_DataPath/dataOut_exe_i [21]) );
HS65_LL_OAI12X3 U4505 ( .A(n9189), .B(n8889), .C(n8405), .Z(
\u_DataPath/dataOut_exe_i [17]) );
HS65_LL_AOI21X2 U4508 ( .A(n5643), .B(n5642), .C(n5641), .Z(n5674) );
HS65_LH_NAND2X7 U4509 ( .A(n7843), .B(n9062), .Z(
\u_DataPath/dataOut_exe_i [18]) );
HS65_LL_OAI12X3 U4510 ( .A(n9189), .B(n9059), .C(n8409), .Z(
\u_DataPath/dataOut_exe_i [20]) );
HS65_LL_NOR2AX3 U4511 ( .A(n4912), .B(n4911), .Z(n8474) );
HS65_LL_NAND2X2 U4512 ( .A(n4910), .B(n4909), .Z(n4911) );
HS65_LL_NAND2X2 U4513 ( .A(n3695), .B(n3694), .Z(n3696) );
HS65_LH_AOI21X6 U4514 ( .A(n5643), .B(n4280), .C(n4279), .Z(n4281) );
HS65_LH_NAND2X7 U4515 ( .A(n5643), .B(n3624), .Z(n3625) );
HS65_LH_NAND2X7 U4518 ( .A(n5643), .B(n3742), .Z(n3743) );
HS65_LL_NAND3X3 U4519 ( .A(n3998), .B(n3997), .C(n3996), .Z(n3999) );
HS65_LH_NAND2X7 U4520 ( .A(n5643), .B(n3693), .Z(n3694) );
HS65_LHS_XNOR2X6 U4521 ( .A(n4429), .B(n4428), .Z(n4450) );
HS65_LL_OAI21X2 U4522 ( .A(n5633), .B(n4240), .C(n4239), .Z(n4241) );
HS65_LH_AOI21X6 U4523 ( .A(n5285), .B(n4569), .C(n4568), .Z(n8464) );
HS65_LH_OAI12X3 U4524 ( .A(n4377), .B(n2859), .C(n4376), .Z(n4378) );
HS65_LL_OAI21X2 U4525 ( .A(n2859), .B(n3739), .C(n3738), .Z(n3740) );
HS65_LH_OAI12X3 U4527 ( .A(n3706), .B(n5633), .C(n3705), .Z(n3707) );
HS65_LHS_XOR2X3 U4529 ( .A(n4847), .B(n2859), .Z(n4861) );
HS65_LH_NOR2AX3 U4530 ( .A(n5672), .B(n5251), .Z(n5252) );
HS65_LL_OAI21X2 U4531 ( .A(n2859), .B(n4224), .C(n4223), .Z(n4225) );
HS65_LL_OAI21X2 U4532 ( .A(n3621), .B(n2859), .C(n3620), .Z(n3622) );
HS65_LH_AOI21X6 U4533 ( .A(n5285), .B(n4605), .C(n4604), .Z(n8463) );
HS65_LH_AOI12X2 U4534 ( .A(n3634), .B(n5195), .C(n3633), .Z(n3635) );
HS65_LH_OAI21X3 U4535 ( .A(n4993), .B(n4992), .C(n4991), .Z(n4994) );
HS65_LH_IVX4 U4536 ( .A(n4473), .Z(n4446) );
HS65_LL_AOI21X2 U4537 ( .A(n5492), .B(n4781), .C(n5122), .Z(n5159) );
HS65_LH_IVX4 U4538 ( .A(n5559), .Z(n5539) );
HS65_LH_IVX4 U4539 ( .A(n5210), .Z(n5213) );
HS65_LH_NAND2X5 U4541 ( .A(n3688), .B(n5210), .Z(n3690) );
HS65_LH_NAND3X3 U4543 ( .A(n5515), .B(n4050), .C(n5526), .Z(n5110) );
HS65_LH_OAI21X3 U4546 ( .A(n4751), .B(n5656), .C(n3771), .Z(n3787) );
HS65_LL_OAI12X3 U4550 ( .A(n4085), .B(n3481), .C(n3479), .Z(n3617) );
HS65_LH_NAND2X4 U4551 ( .A(n4222), .B(n5210), .Z(n4224) );
HS65_LH_NAND2X4 U4552 ( .A(n5429), .B(n5458), .Z(n5461) );
HS65_LH_NAND2X4 U4553 ( .A(n5029), .B(n5028), .Z(n5076) );
HS65_LH_NAND2X4 U4555 ( .A(n4528), .B(n4164), .Z(n3767) );
HS65_LL_IVX4 U4558 ( .A(n4928), .Z(n4085) );
HS65_LH_NAND2X4 U4560 ( .A(n3737), .B(n2867), .Z(n3739) );
HS65_LH_NAND2X4 U4562 ( .A(n3704), .B(n5631), .Z(n3706) );
HS65_LH_NAND2X5 U4563 ( .A(n4916), .B(n3897), .Z(n3899) );
HS65_LH_NAND2X4 U4564 ( .A(n5131), .B(n4578), .Z(n3914) );
HS65_LH_NAND2AX7 U4565 ( .A(n4689), .B(n4688), .Z(n4693) );
HS65_LH_OAI12X3 U4566 ( .A(n5147), .B(n5146), .C(n5145), .Z(n5148) );
HS65_LH_NAND2X7 U4567 ( .A(n5488), .B(n5487), .Z(n5489) );
HS65_LH_NAND3X5 U4568 ( .A(n4757), .B(n4945), .C(n4756), .Z(n4758) );
HS65_LH_IVX9 U4569 ( .A(n4522), .Z(n5666) );
HS65_LH_NAND2X4 U4570 ( .A(n4396), .B(n4395), .Z(n4397) );
HS65_LH_NOR2X6 U4571 ( .A(n4913), .B(n3282), .Z(n3897) );
HS65_LH_OAI12X3 U4572 ( .A(n5456), .B(n5455), .C(n5454), .Z(n5457) );
HS65_LH_NOR2X5 U4574 ( .A(n5456), .B(n5428), .Z(n5458) );
HS65_LH_NOR2X3 U4575 ( .A(n4955), .B(n5146), .Z(n4956) );
HS65_LH_OAI211X4 U4577 ( .A(n5656), .B(n4613), .C(n4612), .D(n4611), .Z(
n4620) );
HS65_LH_OAI21X3 U4579 ( .A(n5412), .B(n5411), .C(n5410), .Z(n5413) );
HS65_LH_NOR2X3 U4580 ( .A(n5646), .B(n4119), .Z(n4123) );
HS65_LH_NOR2X5 U4581 ( .A(n4220), .B(n4317), .Z(n4222) );
HS65_LH_NAND2X5 U4582 ( .A(n5661), .B(n5174), .Z(n5175) );
HS65_LH_AOI12X2 U4583 ( .A(n4476), .B(n4632), .C(n4109), .Z(n4110) );
HS65_LH_IVX7 U4584 ( .A(n4391), .Z(n3522) );
HS65_LH_IVX7 U4586 ( .A(n4291), .Z(n4292) );
HS65_LH_NAND3X3 U4587 ( .A(n5237), .B(n5236), .C(n5235), .Z(n5238) );
HS65_LH_NAND2X5 U4588 ( .A(n3792), .B(n3791), .Z(n3793) );
HS65_LH_OAI21X3 U4589 ( .A(n5646), .B(n4522), .C(n4267), .Z(n4275) );
HS65_LH_IVX9 U4590 ( .A(n3913), .Z(n4578) );
HS65_LH_NOR3X4 U4591 ( .A(n4710), .B(n4730), .C(n4709), .Z(n4733) );
HS65_LH_NAND2X5 U4592 ( .A(n5643), .B(n4599), .Z(n4600) );
HS65_LH_IVX7 U4593 ( .A(n4332), .Z(n3388) );
HS65_LH_AOI22X4 U4594 ( .A(n5131), .B(n4157), .C(n4887), .D(n4950), .Z(n4171) );
HS65_LH_NAND2X4 U4595 ( .A(n5661), .B(n5203), .Z(n3461) );
HS65_LH_NAND2X4 U4597 ( .A(n5618), .B(n5243), .Z(n3712) );
HS65_LH_IVX4 U4598 ( .A(n4185), .Z(n3723) );
HS65_LH_NOR2X6 U4599 ( .A(n5510), .B(n5583), .Z(n5536) );
HS65_LH_IVX9 U4604 ( .A(n4176), .Z(n5240) );
HS65_LH_IVX7 U4605 ( .A(n5505), .Z(n5562) );
HS65_LH_IVX9 U4608 ( .A(n4393), .Z(n4889) );
HS65_LH_NOR2X5 U4609 ( .A(n4320), .B(n4317), .Z(n4322) );
HS65_LH_NOR2X3 U4610 ( .A(n4333), .B(n4330), .Z(n4335) );
HS65_LH_AOI22X3 U4612 ( .A(n4508), .B(n4344), .C(n4516), .D(n4120), .Z(n3557) );
HS65_LH_NAND2X7 U4613 ( .A(n4015), .B(n4017), .Z(n3952) );
HS65_LH_IVX7 U4615 ( .A(n4290), .Z(n4293) );
HS65_LH_NOR2X5 U4617 ( .A(n3800), .B(n3685), .Z(n3688) );
HS65_LH_IVX9 U4618 ( .A(n3905), .Z(n4007) );
HS65_LH_NOR2X5 U4621 ( .A(n3747), .B(n3631), .Z(n3634) );
HS65_LH_NAND3X3 U4622 ( .A(n4672), .B(n5517), .C(n5296), .Z(n5333) );
HS65_LL_AOI21X2 U4623 ( .A(n5208), .B(n5211), .C(n3619), .Z(n3620) );
HS65_LH_NAND2X5 U4624 ( .A(n5453), .B(n5424), .Z(n5456) );
HS65_LH_NOR3X3 U4626 ( .A(n5522), .B(n5542), .C(n5099), .Z(n5100) );
HS65_LH_NAND2X5 U4627 ( .A(n4774), .B(n4773), .Z(n4775) );
HS65_LH_IVX9 U4628 ( .A(n4317), .Z(n3505) );
HS65_LH_OAI21X3 U4630 ( .A(n3863), .B(n3862), .C(n5229), .Z(n3864) );
HS65_LH_OAI211X3 U4631 ( .A(n5360), .B(n5359), .C(n5358), .D(n5478), .Z(
n5369) );
HS65_LH_NAND2X7 U4632 ( .A(n3574), .B(n3573), .Z(n3580) );
HS65_LH_CNIVX3 U4635 ( .A(n3375), .Z(n3210) );
HS65_LH_NAND2X4 U4636 ( .A(n5446), .B(n5427), .Z(n5428) );
HS65_LH_NAND2X5 U4639 ( .A(n3684), .B(n3683), .Z(n3692) );
HS65_LH_IVX7 U4640 ( .A(n4038), .Z(n4039) );
HS65_LH_NAND3X5 U4641 ( .A(n4591), .B(n4590), .C(n4589), .Z(n4617) );
HS65_LH_IVX9 U4642 ( .A(n4426), .Z(n5607) );
HS65_LH_IVX9 U4644 ( .A(n4835), .Z(n4468) );
HS65_LH_AOI22X3 U4645 ( .A(n9349), .B(n5321), .C(n5131), .D(n4584), .Z(n4585) );
HS65_LH_IVX4 U4646 ( .A(n4894), .Z(n3598) );
HS65_LH_AOI12X2 U4647 ( .A(n3586), .B(n3585), .C(n4581), .Z(n3588) );
HS65_LH_NAND3X3 U4648 ( .A(n5469), .B(n5468), .C(n5467), .Z(n5470) );
HS65_LH_NOR2X3 U4649 ( .A(n4643), .B(n4639), .Z(n4646) );
HS65_LH_NAND2X7 U4650 ( .A(n3650), .B(n3649), .Z(n3651) );
HS65_LH_IVX4 U4651 ( .A(n4496), .Z(n4499) );
HS65_LH_OA12X9 U4652 ( .A(n5656), .B(n4945), .C(n4944), .Z(n2898) );
HS65_LH_AOI12X2 U4654 ( .A(n5139), .B(n5229), .C(n5138), .Z(n5140) );
HS65_LH_NOR2X3 U4655 ( .A(n4134), .B(n4939), .Z(n4610) );
HS65_LH_NOR2X5 U4656 ( .A(n5627), .B(n3701), .Z(n3704) );
HS65_LH_IVX7 U4657 ( .A(n5499), .Z(n5563) );
HS65_LH_NAND2X4 U4658 ( .A(n5547), .B(n5091), .Z(n5474) );
HS65_LH_NOR3X4 U4660 ( .A(n4772), .B(n4771), .C(n4770), .Z(n4773) );
HS65_LH_NOR2X3 U4661 ( .A(n4328), .B(n4333), .Z(n5424) );
HS65_LH_NAND2X7 U4662 ( .A(n3615), .B(n3614), .Z(n3623) );
HS65_LH_NAND2X5 U4663 ( .A(n3750), .B(n3383), .Z(n3387) );
HS65_LH_NOR2X6 U4664 ( .A(n3640), .B(n3639), .Z(n3643) );
HS65_LH_NOR2X5 U4666 ( .A(n5389), .B(n4667), .Z(n4668) );
HS65_LH_NAND2X7 U4667 ( .A(n4154), .B(n3867), .Z(n3863) );
HS65_LH_IVX4 U4668 ( .A(n5514), .Z(n5520) );
HS65_LH_NAND2X7 U4669 ( .A(n4542), .B(n4462), .Z(n3862) );
HS65_LH_IVX7 U4670 ( .A(n5083), .Z(n5304) );
HS65_LH_NAND2X7 U4671 ( .A(n5344), .B(n5564), .Z(n4720) );
HS65_LH_OAI12X3 U4672 ( .A(n5183), .B(n5182), .C(n5181), .Z(n5184) );
HS65_LH_IVX4 U4673 ( .A(n4580), .Z(n4552) );
HS65_LH_IVX4 U4675 ( .A(n5545), .Z(n5557) );
HS65_LH_NAND2X5 U4676 ( .A(n3529), .B(n3444), .Z(n4488) );
HS65_LH_NOR2X6 U4677 ( .A(n5363), .B(n5471), .Z(n5507) );
HS65_LH_NAND2X4 U4679 ( .A(n5300), .B(n5516), .Z(n5479) );
HS65_LH_NAND2X4 U4680 ( .A(n5357), .B(n5356), .Z(n5478) );
HS65_LH_NOR2X6 U4681 ( .A(n4984), .B(n4582), .Z(n3982) );
HS65_LH_IVX4 U4682 ( .A(n4462), .Z(n4464) );
HS65_LH_IVX4 U4683 ( .A(n4059), .Z(n3535) );
HS65_LH_OAI12X3 U4684 ( .A(n2848), .B(n4795), .C(n3524), .Z(n3528) );
HS65_LH_IVX7 U4686 ( .A(n4027), .Z(n4031) );
HS65_LH_NAND2X5 U4687 ( .A(n3749), .B(n3748), .Z(n3755) );
HS65_LH_IVX7 U4688 ( .A(n3867), .Z(n3868) );
HS65_LH_IVX7 U4689 ( .A(n4289), .Z(n4218) );
HS65_LH_IVX4 U4690 ( .A(n3956), .Z(n3957) );
HS65_LH_NAND2X5 U4692 ( .A(n5531), .B(n5293), .Z(n3517) );
HS65_LH_IVX9 U4693 ( .A(n5571), .Z(n4727) );
HS65_LH_NAND2X7 U4694 ( .A(n3544), .B(n3543), .Z(n3546) );
HS65_LH_NAND2X4 U4695 ( .A(n5534), .B(n5356), .Z(n5360) );
HS65_LH_IVX4 U4696 ( .A(n5500), .Z(n5501) );
HS65_LH_NAND2X4 U4698 ( .A(n5437), .B(n5420), .Z(n5441) );
HS65_LH_NAND2X5 U4699 ( .A(n4060), .B(n4059), .Z(n4064) );
HS65_LH_OAI21X3 U4700 ( .A(n3756), .B(n2854), .C(n3758), .Z(n4255) );
HS65_LH_NAND3X5 U4702 ( .A(n5232), .B(n4808), .C(n4739), .Z(n4746) );
HS65_LH_NAND2X5 U4703 ( .A(n4062), .B(n4061), .Z(n4063) );
HS65_LH_IVX4 U4704 ( .A(n3682), .Z(n3683) );
HS65_LH_NOR2X6 U4706 ( .A(n4811), .B(n4582), .Z(n3400) );
HS65_LH_IVX9 U4709 ( .A(n5450), .Z(n4231) );
HS65_LH_IVX9 U4710 ( .A(n5183), .Z(n5139) );
HS65_LH_IVX7 U4711 ( .A(n4022), .Z(n4024) );
HS65_LH_IVX4 U4714 ( .A(n5502), .Z(n5012) );
HS65_LH_NAND2X4 U4716 ( .A(\sub_x_53/A[29] ), .B(n4587), .Z(n3441) );
HS65_LH_NAND2X7 U4717 ( .A(n5387), .B(n5324), .Z(n5464) );
HS65_LH_IVX4 U4718 ( .A(n4340), .Z(n4066) );
HS65_LH_NAND2X7 U4719 ( .A(n2854), .B(n5567), .Z(n5344) );
HS65_LH_IVX9 U4720 ( .A(n4374), .Z(n4424) );
HS65_LH_IVX9 U4721 ( .A(n4627), .Z(n4629) );
HS65_LH_NOR2X6 U4722 ( .A(\sub_x_53/A[29] ), .B(n5447), .Z(n4328) );
HS65_LH_NAND2X5 U4724 ( .A(n5509), .B(n5508), .Z(n5583) );
HS65_LH_NOR2AX3 U4725 ( .A(n5136), .B(\sub_x_53/A[0] ), .Z(n5035) );
HS65_LH_NAND2X4 U4726 ( .A(n4628), .B(n4158), .Z(n4160) );
HS65_LH_NAND2X7 U4727 ( .A(\lte_x_59/B[1] ), .B(n4587), .Z(n5128) );
HS65_LH_NAND2X5 U4728 ( .A(n4819), .B(n4818), .Z(n4820) );
HS65_LH_NAND2X4 U4729 ( .A(\sub_x_53/A[30] ), .B(n2873), .Z(n5450) );
HS65_LH_NAND2X5 U4730 ( .A(n5098), .B(n5552), .Z(n5556) );
HS65_LH_IVX7 U4731 ( .A(n4425), .Z(n4375) );
HS65_LH_NAND2X5 U4732 ( .A(n5097), .B(n5096), .Z(n5545) );
HS65_LH_NAND2X5 U4733 ( .A(\lte_x_59/B[24] ), .B(n4544), .Z(n3964) );
HS65_LH_NOR2X3 U4734 ( .A(n3698), .B(n5627), .Z(n5437) );
HS65_LH_NOR2X6 U4735 ( .A(n4675), .B(n4674), .Z(n5514) );
HS65_LH_CNIVX3 U4736 ( .A(n4407), .Z(n4408) );
HS65_LH_IVX7 U4737 ( .A(n4846), .Z(n3561) );
HS65_LH_NAND2X7 U4738 ( .A(\sub_x_53/A[27] ), .B(n2845), .Z(n3758) );
HS65_LL_NOR2X2 U4739 ( .A(n5254), .B(n4250), .Z(n3497) );
HS65_LHS_XOR2X3 U4740 ( .A(n5747), .B(n5746), .Z(\u_DataPath/toPC2_i [28])
);
HS65_LH_IVX9 U4741 ( .A(n5530), .Z(n5295) );
HS65_LH_NOR2X6 U4743 ( .A(n4144), .B(n4100), .Z(n4638) );
HS65_LH_IVX9 U4745 ( .A(n3641), .Z(n4794) );
HS65_LL_NAND2X4 U4746 ( .A(\sub_x_53/A[25] ), .B(n3593), .Z(n3615) );
HS65_LH_IVX9 U4747 ( .A(\sub_x_53/A[0] ), .Z(n4660) );
HS65_LH_NOR2X6 U4748 ( .A(\sub_x_53/A[25] ), .B(n3593), .Z(n3613) );
HS65_LH_IVX9 U4749 ( .A(n4144), .Z(n4099) );
HS65_LH_IVX9 U4750 ( .A(n3558), .Z(n3472) );
HS65_LH_IVX4 U4751 ( .A(n3893), .Z(n4678) );
HS65_LH_NAND2X5 U4752 ( .A(\sub_x_53/A[27] ), .B(n4588), .Z(n3650) );
HS65_LH_NOR2X6 U4753 ( .A(\sub_x_53/A[0] ), .B(n5123), .Z(n4821) );
HS65_LH_IVX9 U4754 ( .A(n3616), .Z(n5208) );
HS65_LL_IVX4 U4756 ( .A(n4516), .Z(n4842) );
HS65_LL_NAND2X4 U4757 ( .A(n3236), .B(n3238), .Z(n3239) );
HS65_LH_IVX9 U4759 ( .A(\lte_x_59/B[21] ), .Z(n4701) );
HS65_LH_NOR2X6 U4760 ( .A(n2858), .B(n5398), .Z(n4011) );
HS65_LH_NAND2X7 U4761 ( .A(\lte_x_59/B[9] ), .B(n2871), .Z(n4904) );
HS65_LH_NOR2X6 U4763 ( .A(\lte_x_59/B[22] ), .B(n2869), .Z(n5627) );
HS65_LH_NAND3X3 U4765 ( .A(n2851), .B(n5136), .C(n4805), .Z(n4340) );
HS65_LH_NOR2X6 U4766 ( .A(\sub_x_53/A[20] ), .B(n4699), .Z(n4374) );
HS65_LH_NOR2X5 U4767 ( .A(\lte_x_59/B[15] ), .B(n4677), .Z(n5406) );
HS65_LH_IVX4 U4769 ( .A(n5361), .Z(n5508) );
HS65_LH_IVX4 U4770 ( .A(\lte_x_59/B[14] ), .Z(n4676) );
HS65_LL_OAI21X2 U4772 ( .A(n4105), .B(n4477), .C(n4107), .Z(n4627) );
HS65_LH_IVX4 U4773 ( .A(n4817), .Z(n4818) );
HS65_LH_IVX9 U4774 ( .A(\lte_x_59/B[18] ), .Z(n4986) );
HS65_LH_NAND2X7 U4775 ( .A(n4477), .B(n4476), .Z(n4478) );
HS65_LH_NAND2X7 U4776 ( .A(\sub_x_53/A[17] ), .B(n5001), .Z(n3559) );
HS65_LH_NAND2X7 U4777 ( .A(n4481), .B(n4480), .Z(n4482) );
HS65_LH_NAND2X4 U4778 ( .A(n5234), .B(n4553), .Z(n4554) );
HS65_LH_OAI22X3 U4779 ( .A(n8906), .B(n9186), .C(n9140), .D(n8759), .Z(
\u_DataPath/data_read_ex_1_i [10]) );
HS65_LH_OAI22X3 U4781 ( .A(n7306), .B(n8168), .C(n7914), .D(n8167), .Z(
\u_DataPath/data_read_ex_1_i [1]) );
HS65_LH_OAI22X3 U4782 ( .A(n7306), .B(n8275), .C(n7914), .D(n8274), .Z(
\u_DataPath/data_read_ex_1_i [8]) );
HS65_LH_OAI22X3 U4783 ( .A(n7306), .B(n8321), .C(n7914), .D(n8320), .Z(
\u_DataPath/data_read_ex_1_i [26]) );
HS65_LH_OAI22X3 U4784 ( .A(n7306), .B(n8434), .C(n7914), .D(n8174), .Z(
\u_DataPath/data_read_ex_1_i [3]) );
HS65_LH_OAI22X3 U4785 ( .A(n7306), .B(n8314), .C(n7914), .D(n8313), .Z(
\u_DataPath/data_read_ex_1_i [6]) );
HS65_LH_OAI22X3 U4787 ( .A(n7306), .B(n8293), .C(n7914), .D(n8292), .Z(
\u_DataPath/data_read_ex_1_i [12]) );
HS65_LH_OAI22X3 U4788 ( .A(n7306), .B(n8304), .C(n7914), .D(n8303), .Z(
\u_DataPath/data_read_ex_1_i [7]) );
HS65_LH_OAI22X3 U4789 ( .A(n7306), .B(n8326), .C(n7914), .D(n8325), .Z(
\u_DataPath/data_read_ex_1_i [19]) );
HS65_LH_IVX18 U4790 ( .A(n4683), .Z(n5398) );
HS65_LH_IVX9 U4791 ( .A(n4823), .Z(n3486) );
HS65_LH_NAND2X7 U4793 ( .A(n8258), .B(n3237), .Z(n3238) );
HS65_LH_IVX4 U4794 ( .A(n4763), .Z(n4592) );
HS65_LH_NOR2X5 U4795 ( .A(n5656), .B(n4762), .Z(n3879) );
HS65_LL_NOR2X6 U4796 ( .A(n3159), .B(n3158), .Z(\sub_x_53/A[23] ) );
HS65_LH_IVX7 U4797 ( .A(n4637), .Z(n3330) );
HS65_LH_IVX9 U4798 ( .A(n4100), .Z(n4480) );
HS65_LH_IVX9 U4800 ( .A(n4481), .Z(n4102) );
HS65_LL_NOR2X3 U4802 ( .A(n3108), .B(n3107), .Z(n3547) );
HS65_LH_OAI22X6 U4803 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [23]), .C(
n8243), .D(n3409), .Z(n3158) );
HS65_LL_OAI12X6 U4804 ( .A(n3173), .B(n2905), .C(n3172), .Z(n5654) );
HS65_LL_IVX7 U4805 ( .A(n3401), .Z(n3399) );
HS65_LH_NAND2X5 U4806 ( .A(\sub_x_53/A[2] ), .B(n5088), .Z(n4595) );
HS65_LH_IVX4 U4807 ( .A(n8563), .Z(\u_DataPath/mem_writedata_out_i [28]) );
HS65_LH_IVX9 U4809 ( .A(n5231), .Z(n3372) );
HS65_LL_OAI12X3 U4810 ( .A(n7854), .B(n3409), .C(n3198), .Z(n3199) );
HS65_LH_IVX9 U4811 ( .A(n5422), .Z(n5447) );
HS65_LL_AOI12X4 U4812 ( .A(n6113), .B(n6115), .C(n5942), .Z(n5955) );
HS65_LL_IVX27 U4813 ( .A(n3270), .Z(n3409) );
HS65_LL_NAND2X2 U4815 ( .A(n3251), .B(n8517), .Z(n3255) );
HS65_LH_NAND3X3 U4816 ( .A(n8562), .B(n8566), .C(n8561), .Z(n8563) );
HS65_LL_NOR2X6 U4818 ( .A(n7799), .B(n7798), .Z(n7122) );
HS65_LH_AOI22X3 U4819 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][24] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][24] ), .D(
n6363), .Z(n6287) );
HS65_LH_AOI22X3 U4821 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][25] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][25] ), .D(
n6624), .Z(n7150) );
HS65_LH_AO22X9 U4822 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][19] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][19] ), .D(
n7282), .Z(n6526) );
HS65_LH_AOI22X3 U4823 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][24] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][24] ), .D(
n6624), .Z(n6292) );
HS65_LH_AO22X9 U4824 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][7] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][7] ), .D(
n7282), .Z(n6446) );
HS65_LH_AOI22X3 U4825 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][12] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][12] ), .Z(n6800)
);
HS65_LH_AOI22X3 U4826 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][10] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][10] ), .D(
n7171), .Z(n6402) );
HS65_LH_AOI22X3 U4827 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][22] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][22] ), .D(
n6624), .Z(n6272) );
HS65_LH_AOI22X3 U4828 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][29] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][29] ), .D(n7516),
.Z(n7521) );
HS65_LH_AOI22X3 U4829 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][8] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][8] ), .Z(n6779)
);
HS65_LH_AO22X9 U4830 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][29] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][29] ), .Z(n7512)
);
HS65_LH_AOI22X3 U4834 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][4] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][4] ), .D(n6384), .Z(n6643) );
HS65_LH_AOI22X3 U4835 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][24] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][24] ), .D(
n7285), .Z(n6294) );
HS65_LH_AOI22X3 U4836 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][29] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][29] ), .D(
n7285), .Z(n7288) );
HS65_LH_AOI22X3 U4838 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][22] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][22] ), .D(
n6363), .Z(n6267) );
HS65_LH_AOI22X3 U4839 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][30] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][30] ), .D(
n6624), .Z(n6137) );
HS65_LH_AO22X9 U4840 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][28] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][28] ), .D(
n7282), .Z(n6918) );
HS65_LH_AO22X9 U4841 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][29] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][29] ), .Z(n7533)
);
HS65_LH_AOI22X3 U4844 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][30] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][30] ), .D(
n7285), .Z(n6142) );
HS65_LH_AO22X9 U4845 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][20] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][20] ), .Z(n7487)
);
HS65_LH_AOI22X3 U4847 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][30] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][30] ), .D(
n7171), .Z(n6141) );
HS65_LH_AOI22X3 U4849 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][8] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][8] ), .Z(n6780)
);
HS65_LH_AOI22X3 U4850 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][30] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][30] ), .D(
n6384), .Z(n6155) );
HS65_LH_AOI22X3 U4851 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][24] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][24] ), .D(
n7171), .Z(n6293) );
HS65_LH_AOI22X3 U4852 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][1] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][1] ), .D(n7516),
.Z(n6834) );
HS65_LH_AO22X9 U4853 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][3] ), .B(n7580),
.C(n7579), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][3] ), .Z(n7387) );
HS65_LH_AO22X9 U4854 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][15] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][15] ), .D(
n7282), .Z(n6381) );
HS65_LH_AO22X9 U4856 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][0] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][0] ), .Z(n7447)
);
HS65_LH_AO22X9 U4857 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][3] ), .B(n7429),
.C(n6952), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][3] ), .Z(n7388) );
HS65_LH_AOI22X3 U4858 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][3] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][3] ), .D(n6740),
.Z(n7389) );
HS65_LH_AO22X9 U4859 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][28] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][28] ), .Z(n7492)
);
HS65_LH_AOI22X3 U4861 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][23] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][23] ), .D(
n2888), .Z(n6227) );
HS65_LH_AOI22X3 U4862 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][16] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][16] ), .D(
n6624), .Z(n6170) );
HS65_LH_AO22X9 U4865 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][21] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][21] ), .Z(n7608)
);
HS65_LH_AO22X9 U4866 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][23] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][23] ), .D(
n6637), .Z(n6235) );
HS65_LH_AO22X9 U4867 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][3] ), .B(n7522),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][3] ), .Z(n7398)
);
HS65_LH_AO22X9 U4869 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][23] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][23] ), .D(
n7292), .Z(n6239) );
HS65_LH_AO22X9 U4871 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][28] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][28] ), .Z(n7507)
);
HS65_LH_AOI22X3 U4873 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][23] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][23] ), .D(
n6670), .Z(n7227) );
HS65_LH_AO22X9 U4875 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][24] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][24] ), .Z(n7573)
);
HS65_LH_AO22X9 U4876 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][0] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][0] ), .Z(n7446)
);
HS65_LH_AOI22X3 U4879 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][23] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][23] ), .D(
n6624), .Z(n6232) );
HS65_LH_AOI22X3 U4881 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][26] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][26] ), .Z(n7335)
);
HS65_LH_AO22X9 U4882 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][28] ), .B(n7429),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][28] ), .Z(n7493)
);
HS65_LH_AOI22X3 U4883 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][12] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][12] ), .Z(n6799)
);
HS65_LH_AO22X9 U4884 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][0] ), .B(n7580),
.C(n7579), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][0] ), .Z(n7430) );
HS65_LH_AOI22X3 U4885 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][5] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][5] ), .D(n7516),
.Z(n6706) );
HS65_LH_AO22X9 U4887 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][16] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][16] ), .Z(n7553)
);
HS65_LH_AOI22X3 U4890 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][26] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][26] ), .Z(n7336)
);
HS65_LH_AOI22X3 U4891 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][28] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][28] ), .D(n6740),
.Z(n7494) );
HS65_LH_AOI22X3 U4892 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][21] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][21] ), .D(
n6625), .Z(n6191) );
HS65_LH_AOI22X3 U4893 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][5] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][5] ), .D(n6942), .Z(n6943) );
HS65_LH_AO22X9 U4899 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][28] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][28] ), .Z(n7506)
);
HS65_LH_AOI22X3 U4900 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][0] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][0] ), .D(n2889), .Z(n7437) );
HS65_LH_AOI22X3 U4901 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][27] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][27] ), .D(
n6624), .Z(n6212) );
HS65_LH_AOI22X3 U4903 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][28] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][28] ), .D(n7516),
.Z(n7499) );
HS65_LH_AOI22X3 U4904 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][22] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][22] ), .D(
n7171), .Z(n6273) );
HS65_LH_AOI22X3 U4907 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][11] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][11] ), .D(
n6624), .Z(n6252) );
HS65_LH_AO22X9 U4908 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][24] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][24] ), .Z(n7558)
);
HS65_LH_AOI22X3 U4910 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][11] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][11] ), .D(
n6363), .Z(n6247) );
HS65_LH_AOI22X3 U4911 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][13] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][13] ), .D(
n7171), .Z(n7172) );
HS65_LH_AOI22X3 U4912 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][4] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][4] ), .D(
n2888), .Z(n6622) );
HS65_LH_AOI22X3 U4913 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][13] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][13] ), .D(
n7285), .Z(n7173) );
HS65_LH_AOI22X3 U4914 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][31] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][31] ), .D(n7516),
.Z(n6679) );
HS65_LH_AO22X9 U4916 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][11] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][11] ), .D(
n7292), .Z(n6259) );
HS65_LH_AO22X9 U4918 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][11] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][11] ), .D(
n6637), .Z(n6255) );
HS65_LH_AO22X9 U4919 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][0] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][0] ), .D(
n7282), .Z(n6425) );
HS65_LH_AOI22X3 U4920 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][13] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][13] ), .D(
n6363), .Z(n7163) );
HS65_LH_AOI22X3 U4922 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][14] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][14] ), .D(
n7171), .Z(n6313) );
HS65_LH_AOI22X3 U4924 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][6] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][6] ), .Z(n7256)
);
HS65_LH_AOI22X3 U4926 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][12] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][12] ), .D(n7516),
.Z(n6794) );
HS65_LH_AO22X9 U4929 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][14] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][14] ), .Z(n7367)
);
HS65_LH_AOI22X3 U4930 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][6] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][6] ), .Z(n7257)
);
HS65_LH_AO22X9 U4931 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][14] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][14] ), .D(
n6637), .Z(n6315) );
HS65_LH_AOI22X3 U4932 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][14] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][14] ), .D(n7516),
.Z(n7374) );
HS65_LH_AOI22X3 U4935 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][15] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][15] ), .Z(n7196)
);
HS65_LH_AO22X9 U4937 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][27] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][27] ), .Z(n7467)
);
HS65_LH_AOI22X3 U4939 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][15] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][15] ), .Z(n7197)
);
HS65_LH_AO22X9 U4940 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][9] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][9] ), .D(
n6637), .Z(n7133) );
HS65_LH_AOI22X3 U4941 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][14] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][14] ), .D(
n6624), .Z(n6312) );
HS65_LH_AOI22X3 U4943 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][22] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][22] ), .D(
n7285), .Z(n6274) );
HS65_LH_AOI22X3 U4946 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][17] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][17] ), .D(n7516),
.Z(n6814) );
HS65_LH_AO22X9 U4947 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][10] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][10] ), .D(
n7282), .Z(n6405) );
HS65_LH_AOI22X3 U4950 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][12] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][12] ), .Z(n6796)
);
HS65_LH_AOI22X3 U4952 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][17] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][17] ), .D(
n6942), .Z(n6899) );
HS65_LH_AO22X9 U4953 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][20] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][20] ), .D(
n7282), .Z(n6858) );
HS65_LH_AOI22X3 U4954 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][29] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][29] ), .D(
n7264), .Z(n7271) );
HS65_LH_AOI22X3 U4955 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][29] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][29] ), .D(
n6363), .Z(n7270) );
HS65_LH_AO22X9 U4958 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][6] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][6] ), .D(
n7282), .Z(n6486) );
HS65_LL_NAND2X5 U4959 ( .A(n9209), .B(n7120), .Z(n7798) );
HS65_LL_NAND3X2 U4960 ( .A(n3261), .B(n6125), .C(n8514), .Z(n3262) );
HS65_LH_NOR2X6 U4961 ( .A(n3233), .B(n8510), .Z(n3234) );
HS65_LH_IVX9 U4962 ( .A(n8505), .Z(n3228) );
HS65_LH_NAND3X3 U4963 ( .A(n8535), .B(n8566), .C(n8534), .Z(n8536) );
HS65_LHS_XNOR2X3 U4964 ( .A(n5913), .B(n5912), .Z(\u_DataPath/toPC2_i [23])
);
HS65_LH_NAND2X7 U4965 ( .A(n7678), .B(n7677), .Z(n7754) );
HS65_LL_AOI12X4 U4966 ( .A(n5910), .B(n5912), .C(n5738), .Z(n5770) );
HS65_LH_NAND2X7 U4968 ( .A(n3152), .B(n2874), .Z(n8556) );
HS65_LH_NAND2X7 U4970 ( .A(n3143), .B(n2874), .Z(n8552) );
HS65_LH_NAND2AX7 U4971 ( .A(n8567), .B(n8568), .Z(n4210) );
HS65_LL_NOR2X3 U4972 ( .A(n8854), .B(n3403), .Z(n3187) );
HS65_LL_NOR2X6 U4973 ( .A(n8235), .B(n7921), .Z(n8482) );
HS65_LH_BFX18 U4974 ( .A(n8288), .Z(n7898) );
HS65_LH_NOR2X5 U4975 ( .A(n8722), .B(n4712), .Z(n8567) );
HS65_LL_OAI12X3 U4978 ( .A(n5824), .B(n5827), .C(n5826), .Z(n5912) );
HS65_LL_NOR2X5 U4979 ( .A(n7797), .B(n7796), .Z(n7120) );
HS65_LH_NAND2X4 U4980 ( .A(n8044), .B(n8035), .Z(opcode_i[4]) );
HS65_LH_NAND2X7 U4981 ( .A(n4207), .B(n2866), .Z(n8568) );
HS65_LH_NOR2X5 U4983 ( .A(n8316), .B(n7868), .Z(n8555) );
HS65_LHS_XOR2X3 U4984 ( .A(n7753), .B(n7752), .Z(\u_DataPath/pc_4_i [12]) );
HS65_LHS_XOR2X3 U4985 ( .A(n5774), .B(n5773), .Z(\u_DataPath/toPC2_i [12])
);
HS65_LL_NOR2X5 U4987 ( .A(n8049), .B(n8117), .Z(n8635) );
HS65_LH_NAND2X5 U4988 ( .A(n4714), .B(n8512), .Z(n3233) );
HS65_LL_NOR3X2 U4989 ( .A(n3413), .B(n8394), .C(n7868), .Z(n3315) );
HS65_LH_IVX9 U4990 ( .A(n8509), .Z(n3244) );
HS65_LH_NAND2X5 U4991 ( .A(n7884), .B(\u_DataPath/u_execute/resAdd1_i [16]),
.Z(n7865) );
HS65_LH_NOR2X5 U4992 ( .A(n8835), .B(n4712), .Z(n8497) );
HS65_LL_AOI12X2 U4993 ( .A(n8119), .B(n8118), .C(n8117), .Z(n8128) );
HS65_LH_NOR2X6 U4994 ( .A(n8266), .B(n7868), .Z(n8501) );
HS65_LH_CNIVX3 U4995 ( .A(n4654), .Z(n8495) );
HS65_LHS_XOR2X3 U4996 ( .A(n6008), .B(n6007), .Z(
\u_DataPath/u_execute/resAdd1_i [12]) );
HS65_LH_NOR2X6 U4997 ( .A(\u_DataPath/dataOut_exe_i [27]), .B(n8390), .Z(
n8558) );
HS65_LH_NOR2X5 U4998 ( .A(n8387), .B(n9401), .Z(n8531) );
HS65_LH_NOR2X6 U5000 ( .A(\u_DataPath/dataOut_exe_i [20]), .B(n8390), .Z(
n8538) );
HS65_LH_NAND2X4 U5001 ( .A(n4213), .B(n3407), .Z(n3075) );
HS65_LH_IVX18 U5002 ( .A(\u_DataPath/u_fetch/pc1/N3 ), .Z(n8483) );
HS65_LH_NAND2X7 U5003 ( .A(n3170), .B(n7869), .Z(n8546) );
HS65_LL_NOR2AX3 U5006 ( .A(n3055), .B(n3054), .Z(n3056) );
HS65_LH_NAND2X2 U5007 ( .A(n9376), .B(n8572), .Z(n4188) );
HS65_LL_AOI12X4 U5008 ( .A(n5902), .B(n5904), .C(n5737), .Z(n5827) );
HS65_LH_NAND2X7 U5009 ( .A(n3232), .B(n7869), .Z(n8512) );
HS65_LL_NAND2X2 U5010 ( .A(n9376), .B(n8492), .Z(n3313) );
HS65_LL_OA12X9 U5011 ( .A(n2932), .B(n3045), .C(n3333), .Z(n3082) );
HS65_LH_NAND2X4 U5012 ( .A(n3321), .B(n7802), .Z(n8499) );
HS65_LL_NOR2X5 U5014 ( .A(n7653), .B(n7650), .Z(n7661) );
HS65_LH_NAND2X7 U5018 ( .A(n6013), .B(n6016), .Z(n5939) );
HS65_LH_IVX18 U5019 ( .A(n4829), .Z(n7631) );
HS65_LH_IVX4 U5020 ( .A(n5167), .Z(n7710) );
HS65_LH_NAND2X7 U5021 ( .A(n5805), .B(n5808), .Z(n5736) );
HS65_LLS_XOR2X3 U5022 ( .A(n8969), .B(n7089), .Z(n3057) );
HS65_LH_IVX7 U5023 ( .A(n5716), .Z(n3062) );
HS65_LL_NOR2X3 U5024 ( .A(n6350), .B(n6342), .Z(n6683) );
HS65_LL_NOR2X5 U5025 ( .A(n2886), .B(n6149), .Z(n6619) );
HS65_LH_IVX7 U5026 ( .A(n7905), .Z(n7837) );
HS65_LL_NOR2X5 U5027 ( .A(n4287), .B(n4286), .Z(n5167) );
HS65_LL_OAI21X3 U5028 ( .A(n5926), .B(n6034), .C(n5925), .Z(n5962) );
HS65_LL_NAND2X5 U5029 ( .A(n9111), .B(n3052), .Z(n8262) );
HS65_LL_OAI21X3 U5030 ( .A(n5724), .B(n5832), .C(n5723), .Z(n5758) );
HS65_LL_NOR2X6 U5031 ( .A(n6349), .B(n6341), .Z(n6682) );
HS65_LL_NOR2X5 U5033 ( .A(n6348), .B(n6342), .Z(n6752) );
HS65_LL_NOR2X5 U5034 ( .A(n6150), .B(n6132), .Z(n6626) );
HS65_LH_NAND2X4 U5035 ( .A(n5959), .B(n5958), .Z(n5970) );
HS65_LL_NOR2X5 U5036 ( .A(n6148), .B(n6132), .Z(n6625) );
HS65_LH_NAND2X5 U5037 ( .A(n5924), .B(n6036), .Z(n5926) );
HS65_LL_NOR2X3 U5039 ( .A(n8961), .B(n2959), .Z(n2938) );
HS65_LL_NOR2X5 U5041 ( .A(n2886), .B(n6152), .Z(n6382) );
HS65_LH_NOR2X5 U5043 ( .A(n8480), .B(n8383), .Z(n8586) );
HS65_LH_NAND2X4 U5044 ( .A(n5885), .B(n5831), .Z(n5835) );
HS65_LL_NOR2X6 U5045 ( .A(n2885), .B(n6139), .Z(n6636) );
HS65_LL_NAND2X2 U5048 ( .A(addr_to_iram[16]), .B(n8692), .Z(n7657) );
HS65_LH_NAND2X5 U5049 ( .A(n2733), .B(n8391), .Z(n8415) );
HS65_LH_NAND2X4 U5051 ( .A(n6063), .B(n6062), .Z(n6068) );
HS65_LH_NAND2X7 U5052 ( .A(addr_to_iram[10]), .B(n8698), .Z(n7647) );
HS65_LH_NAND2X4 U5053 ( .A(n2733), .B(n8488), .Z(n8444) );
HS65_LH_NAND2X5 U5054 ( .A(n2733), .B(n8387), .Z(n8457) );
HS65_LH_NAND2X4 U5055 ( .A(n5819), .B(n5818), .Z(n5823) );
HS65_LH_IVX7 U5056 ( .A(n2937), .Z(n3041) );
HS65_LH_NAND2AX4 U5058 ( .A(n8480), .B(n4175), .Z(n7840) );
HS65_LH_CNIVX3 U5059 ( .A(n8136), .Z(\u_DataPath/cw_memwb_i [0]) );
HS65_LH_CNIVX3 U5060 ( .A(n8111), .Z(\u_DataPath/cw_tomem_i [8]) );
HS65_LH_CNIVX3 U5061 ( .A(n8112), .Z(\u_DataPath/cw_tomem_i [7]) );
HS65_LH_CNIVX3 U5062 ( .A(n8110), .Z(\u_DataPath/cw_tomem_i [6]) );
HS65_LH_CNIVX3 U5063 ( .A(n8481), .Z(\u_DataPath/cw_tomem_i [0]) );
HS65_LH_CNIVX3 U5064 ( .A(n8233), .Z(\u_DataPath/jump_i ) );
HS65_LH_IVX9 U5065 ( .A(n6054), .Z(n5944) );
HS65_LH_NAND2X7 U5066 ( .A(\u_DataPath/jaddr_i [22]), .B(n8163), .Z(n2885)
);
HS65_LH_NAND2X7 U5067 ( .A(n3021), .B(n3404), .Z(n3022) );
HS65_LH_CNIVX3 U5068 ( .A(n8218), .Z(\u_DataPath/pc_4_to_ex_i [11]) );
HS65_LH_CNIVX3 U5069 ( .A(n8221), .Z(\u_DataPath/pc_4_to_ex_i [9]) );
HS65_LH_NAND3X5 U5070 ( .A(n2947), .B(n3030), .C(n8139), .Z(n2949) );
HS65_LH_CNIVX3 U5071 ( .A(n8216), .Z(\u_DataPath/pc_4_to_ex_i [12]) );
HS65_LH_CNIVX3 U5072 ( .A(n8222), .Z(\u_DataPath/pc_4_to_ex_i [8]) );
HS65_LH_CNIVX3 U5073 ( .A(n8214), .Z(\u_DataPath/pc_4_to_ex_i [13]) );
HS65_LL_NAND4ABX3 U5074 ( .A(n8766), .B(n8763), .C(n2936), .D(n8107), .Z(
n2937) );
HS65_LH_CNIVX3 U5075 ( .A(n8223), .Z(\u_DataPath/pc_4_to_ex_i [7]) );
HS65_LH_CNIVX3 U5076 ( .A(n8213), .Z(\u_DataPath/pc_4_to_ex_i [14]) );
HS65_LH_CNIVX3 U5077 ( .A(n8224), .Z(\u_DataPath/pc_4_to_ex_i [6]) );
HS65_LH_CNIVX3 U5078 ( .A(n8212), .Z(\u_DataPath/pc_4_to_ex_i [15]) );
HS65_LH_CNIVX3 U5079 ( .A(n8225), .Z(\u_DataPath/pc_4_to_ex_i [5]) );
HS65_LH_CNIVX3 U5080 ( .A(n8211), .Z(\u_DataPath/pc_4_to_ex_i [16]) );
HS65_LH_CNIVX3 U5081 ( .A(n8209), .Z(\u_DataPath/pc_4_to_ex_i [17]) );
HS65_LH_CNIVX3 U5082 ( .A(n8208), .Z(\u_DataPath/pc_4_to_ex_i [18]) );
HS65_LH_CNIVX3 U5083 ( .A(n8226), .Z(\u_DataPath/pc_4_to_ex_i [4]) );
HS65_LH_CNIVX3 U5084 ( .A(n8206), .Z(\u_DataPath/pc_4_to_ex_i [19]) );
HS65_LH_CNIVX3 U5085 ( .A(n8205), .Z(\u_DataPath/pc_4_to_ex_i [20]) );
HS65_LH_CNIVX3 U5086 ( .A(n8204), .Z(\u_DataPath/pc_4_to_ex_i [21]) );
HS65_LH_CNIVX3 U5087 ( .A(n8227), .Z(\u_DataPath/pc_4_to_ex_i [3]) );
HS65_LH_NAND2X5 U5088 ( .A(n5859), .B(n5858), .Z(n5861) );
HS65_LH_CNIVX3 U5089 ( .A(n8219), .Z(\u_DataPath/pc_4_to_ex_i [10]) );
HS65_LH_CNIVX3 U5090 ( .A(n8202), .Z(\u_DataPath/pc_4_to_ex_i [22]) );
HS65_LH_CNIVX3 U5091 ( .A(n8229), .Z(\u_DataPath/u_execute/link_value_i [1])
);
HS65_LH_CNIVX3 U5093 ( .A(n8200), .Z(\u_DataPath/pc_4_to_ex_i [23]) );
HS65_LH_CNIVX3 U5094 ( .A(n8198), .Z(\u_DataPath/pc_4_to_ex_i [24]) );
HS65_LH_CNIVX3 U5095 ( .A(n8197), .Z(\u_DataPath/pc_4_to_ex_i [25]) );
HS65_LH_CNIVX3 U5097 ( .A(n8196), .Z(\u_DataPath/pc_4_to_ex_i [26]) );
HS65_LH_CNIVX3 U5098 ( .A(n8194), .Z(\u_DataPath/pc_4_to_ex_i [27]) );
HS65_LL_NAND2X7 U5099 ( .A(n3030), .B(n8139), .Z(n7618) );
HS65_LH_CNIVX3 U5100 ( .A(n8193), .Z(\u_DataPath/pc_4_to_ex_i [28]) );
HS65_LH_CNIVX3 U5101 ( .A(n8191), .Z(\u_DataPath/pc_4_to_ex_i [29]) );
HS65_LH_CNIVX3 U5102 ( .A(n8190), .Z(\u_DataPath/pc_4_to_ex_i [30]) );
HS65_LH_CNIVX3 U5103 ( .A(n8289), .Z(\u_DataPath/pc_4_to_ex_i [31]) );
HS65_LH_IVX44 U5105 ( .A(n3123), .Z(addr_to_iram[12]) );
HS65_LH_NOR2X6 U5106 ( .A(n6038), .B(n6041), .Z(n6036) );
HS65_LH_NOR2X5 U5107 ( .A(n6097), .B(n6102), .Z(n5922) );
HS65_LH_NOR2X5 U5109 ( .A(n5894), .B(n5899), .Z(n5720) );
HS65_LH_NOR2X6 U5110 ( .A(n7725), .B(n4001), .Z(n7707) );
HS65_LH_NOR2X6 U5111 ( .A(n5817), .B(n5820), .Z(n5814) );
HS65_LH_CNIVX3 U5112 ( .A(n9224), .Z(n7722) );
HS65_LH_NOR2X6 U5113 ( .A(\u_DataPath/jaddr_i [18]), .B(
\u_DataPath/jaddr_i [20]), .Z(n6326) );
HS65_LL_IVX7 U5116 ( .A(\u_DataPath/jaddr_i [17]), .Z(n8153) );
HS65_LH_IVX4 U5117 ( .A(\u_DataPath/dataOut_exe_i [26]), .Z(n3153) );
HS65_LH_NAND2X7 U5118 ( .A(n8969), .B(n9216), .Z(n6014) );
HS65_LH_IVX4 U5119 ( .A(n9205), .Z(n7308) );
HS65_LH_NOR2X5 U5121 ( .A(n8911), .B(n9208), .Z(n5971) );
HS65_LH_OR2X9 U5123 ( .A(n8944), .B(n9213), .Z(n6109) );
HS65_LH_IVX9 U5124 ( .A(n8967), .Z(n2940) );
HS65_LH_IVX4 U5125 ( .A(\u_DataPath/dataOut_exe_i [30]), .Z(n4208) );
HS65_LH_IVX9 U5126 ( .A(n8966), .Z(n2950) );
HS65_LL_NOR2X3 U5127 ( .A(n8761), .B(n8764), .Z(n2936) );
HS65_LH_NAND2X7 U5128 ( .A(n9037), .B(n9212), .Z(n6047) );
HS65_LH_IVX4 U5130 ( .A(\u_DataPath/dataOut_exe_i [23]), .Z(n3160) );
HS65_LH_IVX9 U5131 ( .A(n8766), .Z(n8170) );
HS65_LH_NAND2X5 U5135 ( .A(n9228), .B(n9230), .Z(n4284) );
HS65_LH_NAND2X7 U5138 ( .A(n9231), .B(n9229), .Z(n4002) );
HS65_LHS_XNOR2X3 U5139 ( .A(\u_DataPath/jaddr_i [20]), .B(n8968), .Z(n7102)
);
HS65_LH_IVX4 U5140 ( .A(\u_DataPath/dataOut_exe_i [15]), .Z(n3273) );
HS65_LH_NAND2X4 U5142 ( .A(n9039), .B(n9116), .Z(n5897) );
HS65_LH_CNIVX3 U5145 ( .A(n9221), .Z(n7717) );
HS65_LH_NAND2X5 U5146 ( .A(n9035), .B(n9115), .Z(n5850) );
HS65_LH_IVX4 U5147 ( .A(\u_DataPath/dataOut_exe_i [6]), .Z(n3321) );
HS65_LH_IVX9 U5148 ( .A(\u_DataPath/dataOut_exe_i [16]), .Z(n3205) );
HS65_LH_NOR2X5 U5150 ( .A(opcode_i[3]), .B(opcode_i[5]), .Z(n7642) );
HS65_LH_NAND2X7 U5156 ( .A(n7856), .B(n9074), .Z(
\u_DataPath/dataOut_exe_i [22]) );
HS65_LL_IVX2 U5157 ( .A(n5681), .Z(n5165) );
HS65_LL_IVX4 U5158 ( .A(n5679), .Z(n4834) );
HS65_LL_OAI12X3 U5159 ( .A(n9189), .B(n9073), .C(n8369), .Z(
\u_DataPath/dataOut_exe_i [24]) );
HS65_LL_NAND2X4 U5161 ( .A(n5674), .B(n5673), .Z(n5694) );
HS65_LL_IVX2 U5163 ( .A(n5699), .Z(n5283) );
HS65_LL_AO12X4 U5165 ( .A(n5160), .B(n5159), .C(n5158), .Z(n5710) );
HS65_LL_NAND2X2 U5166 ( .A(n7907), .B(n5699), .Z(n7857) );
HS65_LL_NAND4ABX3 U5167 ( .A(n4453), .B(n5166), .C(n8471), .D(n8470), .Z(
n4454) );
HS65_LL_AOI21X3 U5168 ( .A(n5285), .B(n3746), .C(n3745), .Z(n8459) );
HS65_LL_AOI21X3 U5169 ( .A(n7631), .B(n3813), .C(n3812), .Z(n8460) );
HS65_LL_NAND2X2 U5170 ( .A(n7907), .B(n4453), .Z(n7842) );
HS65_LL_AOI12X4 U5171 ( .A(n5285), .B(n3571), .C(n3570), .Z(n8470) );
HS65_LL_OAI12X3 U5172 ( .A(n5118), .B(n5117), .C(n5116), .Z(n5160) );
HS65_LH_NAND2X7 U5173 ( .A(n7907), .B(n5686), .Z(n7850) );
HS65_LL_NAND2X2 U5174 ( .A(n7907), .B(n5166), .Z(n7844) );
HS65_LL_NAND2X2 U5175 ( .A(n5268), .B(n5267), .Z(n5282) );
HS65_LL_NAND2X2 U5177 ( .A(n3811), .B(n3810), .Z(n3812) );
HS65_LL_NAND2X2 U5178 ( .A(n4228), .B(n4227), .Z(n5602) );
HS65_LL_NOR2AX3 U5179 ( .A(n4452), .B(n4451), .Z(n8471) );
HS65_LH_AOI21X6 U5180 ( .A(n7631), .B(n4000), .C(n3999), .Z(n8472) );
HS65_LL_NAND3X2 U5182 ( .A(n4096), .B(n4095), .C(n4094), .Z(n4097) );
HS65_LL_NAND2X2 U5183 ( .A(n3507), .B(n3506), .Z(n3508) );
HS65_LL_NAND2X2 U5184 ( .A(n3946), .B(n3945), .Z(n3947) );
HS65_LL_AOI21X4 U5185 ( .A(n5285), .B(n4141), .C(n4140), .Z(n8468) );
HS65_LH_NAND2X7 U5186 ( .A(n5643), .B(n4093), .Z(n4094) );
HS65_LL_OAI21X2 U5188 ( .A(n4863), .B(n5153), .C(n4862), .Z(n4867) );
HS65_LH_NAND2X7 U5189 ( .A(n5643), .B(n5266), .Z(n5267) );
HS65_LL_AOI211X3 U5190 ( .A(n3852), .B(n5285), .C(n3851), .D(n3850), .Z(
n8476) );
HS65_LH_NAND2X7 U5191 ( .A(n7631), .B(n4057), .Z(n4098) );
HS65_LL_NAND2X2 U5192 ( .A(n5157), .B(n5156), .Z(n5158) );
HS65_LLS_XNOR2X3 U5193 ( .A(n4253), .B(n4252), .Z(n4280) );
HS65_LL_NOR2AX3 U5194 ( .A(n4487), .B(n4486), .Z(n8466) );
HS65_LL_NAND2AX4 U5195 ( .A(n4139), .B(n4138), .Z(n4140) );
HS65_LHS_XNOR2X6 U5197 ( .A(n4092), .B(n4091), .Z(n4093) );
HS65_LLS_XNOR2X3 U5198 ( .A(n3565), .B(n3564), .Z(n3566) );
HS65_LH_IVX9 U5199 ( .A(n4312), .Z(n4313) );
HS65_LHS_XNOR2X6 U5201 ( .A(n5199), .B(n5198), .Z(n5222) );
HS65_LHS_XNOR2X6 U5202 ( .A(n4326), .B(n4325), .Z(n4327) );
HS65_LH_NAND2X7 U5203 ( .A(n7631), .B(n3902), .Z(n3948) );
HS65_LL_NOR3X1 U5204 ( .A(n3795), .B(n3794), .C(n3793), .Z(n3796) );
HS65_LH_NOR2AX3 U5205 ( .A(n3931), .B(n3930), .Z(n3946) );
HS65_LH_AOI22X6 U5206 ( .A(n9100), .B(n9368), .C(n9187), .D(n8852), .Z(n8297) );
HS65_LH_OAI12X3 U5209 ( .A(n5611), .B(n2859), .C(n5609), .Z(n5612) );
HS65_LH_CNIVX3 U5210 ( .A(n8463), .Z(n4791) );
HS65_LL_NOR2X2 U5211 ( .A(n5634), .B(n5633), .Z(n5635) );
HS65_LL_NAND3X2 U5213 ( .A(n3886), .B(n3885), .C(n3884), .Z(n3887) );
HS65_LL_NOR3X1 U5214 ( .A(n3717), .B(n3716), .C(n3715), .Z(n3729) );
HS65_LL_NOR3X1 U5215 ( .A(n3542), .B(n3541), .C(n3540), .Z(n3569) );
HS65_LL_NAND4ABX3 U5216 ( .A(n4653), .B(n4652), .C(n4651), .D(n4650), .Z(
n8467) );
HS65_LH_NOR3X4 U5217 ( .A(n4898), .B(n4897), .C(n4896), .Z(n4899) );
HS65_LL_OAI12X3 U5218 ( .A(n3992), .B(n4929), .C(n3991), .Z(n3993) );
HS65_LH_IVX9 U5219 ( .A(n4536), .Z(n7838) );
HS65_LL_NOR3X1 U5220 ( .A(n4076), .B(n4075), .C(n4074), .Z(n4096) );
HS65_LL_IVX2 U5222 ( .A(n4781), .Z(n5119) );
HS65_LL_NOR3X1 U5223 ( .A(n3989), .B(n3988), .C(n3987), .Z(n3997) );
HS65_LL_OAI12X2 U5224 ( .A(n4929), .B(n3941), .C(n3940), .Z(n3942) );
HS65_LH_NOR2AX3 U5225 ( .A(n4054), .B(n4053), .Z(n4055) );
HS65_LL_NOR2X2 U5226 ( .A(n4137), .B(n4136), .Z(n4138) );
HS65_LH_NAND2X4 U5229 ( .A(n3804), .B(n5210), .Z(n3806) );
HS65_LL_NAND2X2 U5231 ( .A(n5643), .B(n4636), .Z(n4651) );
HS65_LH_NAND2X2 U5233 ( .A(n5615), .B(n4535), .Z(n4278) );
HS65_LL_NOR3X1 U5234 ( .A(n3978), .B(n3977), .C(n3976), .Z(n3998) );
HS65_LH_NAND2X5 U5235 ( .A(n5615), .B(n5614), .Z(n5626) );
HS65_LH_NAND2AX7 U5236 ( .A(n4880), .B(n4879), .Z(n4881) );
HS65_LH_OAI21X3 U5238 ( .A(n3539), .B(n5646), .C(n3538), .Z(n3540) );
HS65_LH_OAI21X3 U5239 ( .A(n3713), .B(n4607), .C(n3712), .Z(n3716) );
HS65_LL_NOR3X1 U5240 ( .A(n5150), .B(n5149), .C(n5148), .Z(n5151) );
HS65_LH_NAND2X7 U5242 ( .A(n7631), .B(n4908), .Z(n4909) );
HS65_LH_NOR2X3 U5243 ( .A(n5152), .B(n4895), .Z(n4896) );
HS65_LH_NAND2X4 U5244 ( .A(n4424), .B(n2867), .Z(n4377) );
HS65_LH_NAND2X4 U5245 ( .A(n4919), .B(n4916), .Z(n4921) );
HS65_LH_NAND2X7 U5248 ( .A(n7631), .B(n3854), .Z(n3890) );
HS65_LH_NOR3X4 U5249 ( .A(n4760), .B(n4759), .C(n4758), .Z(n4779) );
HS65_LH_NAND2X5 U5250 ( .A(n4555), .B(n4554), .Z(n4556) );
HS65_LH_NAND2X5 U5254 ( .A(n5632), .B(n5631), .Z(n5634) );
HS65_LH_OAI12X3 U5255 ( .A(n5241), .B(n4391), .C(n4390), .Z(n4403) );
HS65_LH_AOI12X2 U5257 ( .A(n4930), .B(n4928), .C(n4927), .Z(n4933) );
HS65_LH_NOR2X5 U5258 ( .A(n5621), .B(n5226), .Z(n5227) );
HS65_LH_NOR2X5 U5260 ( .A(n3427), .B(n5204), .Z(n5205) );
HS65_LL_NOR3X1 U5261 ( .A(n4458), .B(n5321), .C(n4457), .Z(n4475) );
HS65_LH_AOI21X2 U5263 ( .A(n3939), .B(n4928), .C(n3938), .Z(n3940) );
HS65_LH_NAND2X5 U5264 ( .A(n4942), .B(n4164), .Z(n3980) );
HS65_LL_NAND3X2 U5266 ( .A(n4265), .B(n4262), .C(n4260), .Z(n4535) );
HS65_LH_NAND2X4 U5267 ( .A(n4417), .B(n5631), .Z(n4411) );
HS65_LH_OAI12X3 U5268 ( .A(n4670), .B(n4669), .C(n4668), .Z(n4695) );
HS65_LH_NAND2X4 U5269 ( .A(n3751), .B(n5194), .Z(n3753) );
HS65_LH_OAI21X3 U5272 ( .A(n5646), .B(n4889), .C(n4888), .Z(n4898) );
HS65_LH_NOR2X3 U5273 ( .A(n5621), .B(n5240), .Z(n3675) );
HS65_LH_OAI22X3 U5274 ( .A(n4954), .B(n4579), .C(n5146), .D(n3913), .Z(n4603) );
HS65_LH_IVX7 U5276 ( .A(n4232), .Z(n4233) );
HS65_LH_NAND2X7 U5277 ( .A(n2733), .B(\u_DataPath/toPC2_i [31]), .Z(n8234)
);
HS65_LH_NOR3X3 U5279 ( .A(n4795), .B(n5249), .C(n4163), .Z(n3537) );
HS65_LH_NOR2X5 U5280 ( .A(n4293), .B(n4317), .Z(n4295) );
HS65_LH_OAI21X3 U5281 ( .A(n4767), .B(n5656), .C(n4529), .Z(n4530) );
HS65_LH_AOI22X3 U5282 ( .A(n5229), .B(n4515), .C(n4951), .D(n4560), .Z(n4152) );
HS65_LH_IVX7 U5283 ( .A(n4839), .Z(n5200) );
HS65_LL_NAND2X2 U5284 ( .A(n4385), .B(n4384), .Z(n4386) );
HS65_LH_NAND2X4 U5285 ( .A(n4887), .B(n4148), .Z(n3965) );
HS65_LH_NAND2X4 U5287 ( .A(n5131), .B(n4560), .Z(n3961) );
HS65_LH_NAND3X5 U5288 ( .A(n4031), .B(n4030), .C(n4029), .Z(n4032) );
HS65_LH_NAND2X4 U5289 ( .A(n5661), .B(n4389), .Z(n4347) );
HS65_LH_AOI21X2 U5290 ( .A(n5618), .B(n5658), .C(n3973), .Z(n3974) );
HS65_LH_NAND3X5 U5291 ( .A(n5566), .B(n4723), .C(n4722), .Z(n4732) );
HS65_LH_OAI12X3 U5294 ( .A(n4307), .B(n4332), .C(n4306), .Z(n4308) );
HS65_LH_NOR2X3 U5295 ( .A(n5621), .B(n4609), .Z(n3717) );
HS65_LH_NAND3X5 U5296 ( .A(n3866), .B(n3865), .C(n3864), .Z(n3883) );
HS65_LH_OAI21X3 U5297 ( .A(n5182), .B(n4117), .C(n3601), .Z(n3606) );
HS65_LH_AOI12X2 U5298 ( .A(n4417), .B(n5630), .C(n4409), .Z(n4410) );
HS65_LL_NAND3X3 U5299 ( .A(n3491), .B(n4625), .C(n4632), .Z(n3492) );
HS65_LH_OAI12X3 U5300 ( .A(n5646), .B(n4353), .C(n4352), .Z(n4354) );
HS65_LH_NAND2X4 U5301 ( .A(n5661), .B(n5243), .Z(n3647) );
HS65_LH_IVX9 U5305 ( .A(n3923), .Z(n5243) );
HS65_LL_AOI12X2 U5306 ( .A(n4806), .B(n5672), .C(n4437), .Z(n4438) );
HS65_LH_NOR3X4 U5308 ( .A(n5466), .B(n5465), .C(n5464), .Z(n5495) );
HS65_LH_IVX4 U5309 ( .A(n4262), .Z(n4263) );
HS65_LH_NAND2X7 U5310 ( .A(n4038), .B(n4041), .Z(n3994) );
HS65_LL_NAND2X2 U5311 ( .A(n4016), .B(n3362), .Z(n3363) );
HS65_LH_NAND2X5 U5312 ( .A(n4516), .B(n4344), .Z(n4385) );
HS65_LH_NAND3X3 U5313 ( .A(n5335), .B(n5313), .C(n5402), .Z(n4673) );
HS65_LH_IVX7 U5314 ( .A(n4319), .Z(n3504) );
HS65_LH_IVX9 U5315 ( .A(n4435), .Z(n5206) );
HS65_LH_NOR3X3 U5317 ( .A(n5571), .B(n5471), .C(n5470), .Z(n5472) );
HS65_LH_IVX4 U5319 ( .A(n4868), .Z(n4803) );
HS65_LH_NAND2AX7 U5320 ( .A(n3473), .B(n3497), .Z(n4427) );
HS65_LH_NOR2X5 U5321 ( .A(n4954), .B(n4468), .Z(n3857) );
HS65_LH_OAI12X3 U5322 ( .A(n9352), .B(n3424), .C(n5423), .Z(n3429) );
HS65_LH_IVX9 U5324 ( .A(n4806), .Z(n4163) );
HS65_LL_AOI21X2 U5326 ( .A(n3804), .B(n5211), .C(n3803), .Z(n3805) );
HS65_LH_NOR2X5 U5327 ( .A(n5287), .B(n5342), .Z(n5352) );
HS65_LH_NAND2X4 U5328 ( .A(n4942), .B(n4344), .Z(n4058) );
HS65_LH_NAND2X5 U5329 ( .A(n5131), .B(n4132), .Z(n4133) );
HS65_LL_NAND2X2 U5330 ( .A(n4040), .B(n3480), .Z(n3475) );
HS65_LH_NAND2X7 U5331 ( .A(n4303), .B(n4304), .Z(n4232) );
HS65_LH_NAND2X7 U5332 ( .A(n4259), .B(n4258), .Z(n4950) );
HS65_LH_OAI21X3 U5333 ( .A(n4939), .B(n4894), .C(n4893), .Z(n4897) );
HS65_LH_NAND2AX7 U5334 ( .A(n4217), .B(n4316), .Z(n4291) );
HS65_LH_NAND2X4 U5335 ( .A(n4528), .B(n4344), .Z(n4346) );
HS65_LH_NOR2X5 U5336 ( .A(n5176), .B(n4558), .Z(n4559) );
HS65_LH_OAI12X3 U5337 ( .A(n4078), .B(n4077), .C(n4836), .Z(n4079) );
HS65_LL_IVX2 U5339 ( .A(n4101), .Z(n4645) );
HS65_LH_NOR2X6 U5341 ( .A(n4077), .B(n4078), .Z(n4391) );
HS65_LH_OAI12X3 U5343 ( .A(n3800), .B(n3686), .C(n3802), .Z(n3687) );
HS65_LH_NOR3X4 U5345 ( .A(n5186), .B(n5185), .C(n5184), .Z(n5187) );
HS65_LH_NOR3X4 U5346 ( .A(n4747), .B(n4746), .C(n4745), .Z(n4780) );
HS65_LH_AOI22X3 U5347 ( .A(n5234), .B(n4592), .C(n4951), .D(n4617), .Z(n4601) );
HS65_LH_NAND2X7 U5349 ( .A(n4318), .B(n3471), .Z(n3509) );
HS65_LH_IVX9 U5350 ( .A(n3872), .Z(n5177) );
HS65_LH_OAI12X3 U5351 ( .A(n4913), .B(n3895), .C(n4915), .Z(n3896) );
HS65_LH_IVX9 U5352 ( .A(n3555), .Z(n4873) );
HS65_LH_AOI21X2 U5354 ( .A(n4490), .B(n5672), .C(n5649), .Z(n3655) );
HS65_LH_OAI211X5 U5356 ( .A(n4671), .B(n4582), .C(n4129), .D(n4128), .Z(
n4868) );
HS65_LL_NAND3X3 U5357 ( .A(n3441), .B(n3440), .C(n4340), .Z(n3872) );
HS65_LH_NAND2X5 U5358 ( .A(n3910), .B(n3909), .Z(n3911) );
HS65_LH_NOR2X3 U5359 ( .A(n5603), .B(n3734), .Z(n3737) );
HS65_LH_OAI12X2 U5360 ( .A(n5603), .B(n3735), .C(n5605), .Z(n3736) );
HS65_LH_NOR3X4 U5361 ( .A(n3596), .B(n3908), .C(n3595), .Z(n4355) );
HS65_LH_NAND2X5 U5362 ( .A(n5229), .B(n5170), .Z(n5171) );
HS65_LH_NOR2X3 U5364 ( .A(n4314), .B(n4318), .Z(n4217) );
HS65_LH_OAI12X3 U5367 ( .A(n4596), .B(n2897), .C(n4595), .Z(n4597) );
HS65_LH_NOR2X6 U5368 ( .A(n4064), .B(n4063), .Z(n4113) );
HS65_LH_NOR2X6 U5369 ( .A(n3460), .B(n3459), .Z(n4849) );
HS65_LH_NAND2X7 U5371 ( .A(n2733), .B(\u_DataPath/toPC2_i [29]), .Z(n8238)
);
HS65_LL_NAND3X3 U5373 ( .A(n3870), .B(n3959), .C(n3790), .Z(n5660) );
HS65_LH_NAND3X5 U5374 ( .A(n4753), .B(n4752), .C(n4751), .Z(n4759) );
HS65_LH_NAND3X3 U5375 ( .A(n4763), .B(n4762), .C(n4761), .Z(n4777) );
HS65_LH_NAND3X5 U5376 ( .A(n5188), .B(n4767), .C(n4766), .Z(n4776) );
HS65_LH_OAI21X3 U5377 ( .A(n2843), .B(n5129), .C(n4590), .Z(n4077) );
HS65_LH_NAND2X7 U5378 ( .A(n4316), .B(n4315), .Z(n4326) );
HS65_LH_NOR2X5 U5379 ( .A(n5399), .B(n5298), .Z(n5402) );
HS65_LH_NOR2X5 U5380 ( .A(n4320), .B(n4314), .Z(n4290) );
HS65_LL_AOI21X2 U5381 ( .A(n4538), .B(n3318), .C(n3317), .Z(n4101) );
HS65_LH_OAI12X3 U5382 ( .A(n4924), .B(n3937), .C(n4926), .Z(n3938) );
HS65_LL_NOR2X2 U5383 ( .A(n4034), .B(n3990), .Z(n3480) );
HS65_LH_NAND2X4 U5384 ( .A(n5229), .B(n4356), .Z(n3604) );
HS65_LL_OAI21X2 U5385 ( .A(n3376), .B(n5179), .C(n5178), .Z(n4437) );
HS65_LH_IVX7 U5386 ( .A(n4800), .Z(n4132) );
HS65_LH_NAND2X5 U5387 ( .A(n3934), .B(n3933), .Z(n3943) );
HS65_LH_NOR2X6 U5388 ( .A(n4011), .B(n3949), .Z(n3362) );
HS65_LL_IVX4 U5389 ( .A(n3949), .Z(n4017) );
HS65_LH_CBI4I1X5 U5390 ( .A(n5499), .B(n5572), .C(n5503), .D(n5569), .Z(
n5488) );
HS65_LL_NAND3X3 U5392 ( .A(n3985), .B(n3871), .C(n3760), .Z(n5617) );
HS65_LL_NOR2X3 U5394 ( .A(n3415), .B(n4134), .Z(n4806) );
HS65_LL_NAND2X4 U5396 ( .A(n3503), .B(n3804), .Z(n4317) );
HS65_LH_IVX7 U5397 ( .A(n3920), .Z(n3671) );
HS65_LH_IVX9 U5398 ( .A(n5257), .Z(n3473) );
HS65_LH_NAND2X5 U5399 ( .A(n5103), .B(n5400), .Z(n5542) );
HS65_LH_NOR3X4 U5400 ( .A(n4465), .B(n4464), .C(n4463), .Z(n5135) );
HS65_LH_NOR2X6 U5401 ( .A(n3646), .B(n3645), .Z(n3923) );
HS65_LH_NOR2X5 U5402 ( .A(n4690), .B(n4702), .Z(n4708) );
HS65_LH_NOR2X5 U5405 ( .A(n4796), .B(n4582), .Z(n3669) );
HS65_LH_AOI211X3 U5406 ( .A(n5234), .B(n4750), .C(n4027), .D(n3826), .Z(
n3828) );
HS65_LL_NOR2X2 U5407 ( .A(n3932), .B(n4924), .Z(n3478) );
HS65_LH_NAND2X7 U5408 ( .A(n2892), .B(n5295), .Z(n4864) );
HS65_LH_NAND2X5 U5409 ( .A(n4904), .B(n4903), .Z(n4907) );
HS65_LH_NAND3X3 U5410 ( .A(n5502), .B(n5442), .C(n5582), .Z(n4977) );
HS65_LH_NAND3X3 U5412 ( .A(n4769), .B(n5141), .C(n4768), .Z(n4770) );
HS65_LH_NAND2X7 U5413 ( .A(n3474), .B(n3359), .Z(n5400) );
HS65_LH_NOR2X6 U5414 ( .A(\lte_x_59/B[28] ), .B(n3129), .Z(n4333) );
HS65_LH_NAND2X4 U5415 ( .A(n5292), .B(n5356), .Z(n4690) );
HS65_LH_IVX7 U5417 ( .A(n3820), .Z(n3822) );
HS65_LH_NAND2X7 U5419 ( .A(\lte_x_59/B[28] ), .B(n5423), .Z(n4318) );
HS65_LH_OA12X9 U5420 ( .A(n5126), .B(n4823), .C(n4824), .Z(n2897) );
HS65_LH_AOI12X2 U5421 ( .A(n5261), .B(n5260), .C(n5259), .Z(n5262) );
HS65_LH_NAND2X7 U5423 ( .A(n4229), .B(n5569), .Z(n4242) );
HS65_LH_NAND2X4 U5424 ( .A(\lte_x_59/B[28] ), .B(n4587), .Z(n3649) );
HS65_LH_NAND2X5 U5425 ( .A(n4878), .B(n4877), .Z(n4884) );
HS65_LH_IVX4 U5427 ( .A(n3613), .Z(n3614) );
HS65_LH_IVX4 U5429 ( .A(n4314), .Z(n4315) );
HS65_LH_AOI21X2 U5430 ( .A(n4943), .B(n4942), .C(n4941), .Z(n4944) );
HS65_LH_NOR2X6 U5431 ( .A(n4131), .B(n4130), .Z(n4800) );
HS65_LH_NAND2X5 U5432 ( .A(n4083), .B(n4082), .Z(n4092) );
HS65_LH_IVX7 U5433 ( .A(n5300), .Z(n5103) );
HS65_LH_IVX4 U5434 ( .A(n3572), .Z(n3573) );
HS65_LL_NAND2X2 U5435 ( .A(n5209), .B(n5208), .Z(n5215) );
HS65_LH_IVX7 U5436 ( .A(n4040), .Z(n3991) );
HS65_LL_NOR2X3 U5437 ( .A(n3629), .B(n3747), .Z(n3383) );
HS65_LH_IVX4 U5439 ( .A(n3594), .Z(n3596) );
HS65_LH_OAI12X3 U5440 ( .A(n5362), .B(n5364), .C(n5290), .Z(n5585) );
HS65_LH_OAI22X4 U5441 ( .A(n5130), .B(n3756), .C(n4660), .D(n5129), .Z(n3772) );
HS65_LH_IVX7 U5442 ( .A(n4049), .Z(n3267) );
HS65_LH_IVX9 U5444 ( .A(n4117), .Z(n4892) );
HS65_LH_NAND2X4 U5445 ( .A(n5193), .B(n5192), .Z(n5199) );
HS65_LH_NAND2X5 U5447 ( .A(n4418), .B(n4417), .Z(n4422) );
HS65_LH_NAND2X7 U5448 ( .A(n3802), .B(n3801), .Z(n3808) );
HS65_LH_NAND2X4 U5449 ( .A(n4425), .B(n4424), .Z(n4429) );
HS65_LH_OAI12X3 U5451 ( .A(n3893), .B(n5530), .C(n5506), .Z(n5473) );
HS65_LH_NAND2X4 U5455 ( .A(n5192), .B(n5290), .Z(n5366) );
HS65_LHS_XOR2X6 U5456 ( .A(n5126), .B(n4825), .Z(n4826) );
HS65_LH_NOR2X3 U5457 ( .A(n5004), .B(n2857), .Z(n3954) );
HS65_LH_NAND2X4 U5458 ( .A(\lte_x_59/B[14] ), .B(n2864), .Z(n4022) );
HS65_LH_CNIVX3 U5459 ( .A(n3731), .Z(n3732) );
HS65_LH_OAI22X3 U5461 ( .A(n4671), .B(n2856), .C(n3756), .D(n2843), .Z(n4023) );
HS65_LH_NAND2X5 U5462 ( .A(\sub_x_53/A[23] ), .B(n4588), .Z(n3718) );
HS65_LL_OAI22X3 U5464 ( .A(n3756), .B(n4726), .C(n2840), .D(n4583), .Z(n4943) );
HS65_LH_NAND2X2 U5465 ( .A(\lte_x_59/B[8] ), .B(n2864), .Z(n3674) );
HS65_LH_NAND2X5 U5468 ( .A(n2842), .B(n4588), .Z(n4060) );
HS65_LL_NOR2X2 U5470 ( .A(n7834), .B(n2840), .Z(n3420) );
HS65_LH_NOR2X6 U5471 ( .A(n5320), .B(n5129), .Z(n4798) );
HS65_LH_IVX9 U5474 ( .A(n4887), .Z(n5146) );
HS65_LH_OAI21X3 U5475 ( .A(n3365), .B(n5179), .C(n3825), .Z(n3826) );
HS65_LH_NOR2X3 U5476 ( .A(n4675), .B(n2856), .Z(n3830) );
HS65_LH_NAND2X4 U5478 ( .A(n4594), .B(n4593), .Z(n4598) );
HS65_LH_NOR2X3 U5479 ( .A(n2840), .B(n4193), .Z(n4194) );
HS65_LH_NAND2X7 U5480 ( .A(\lte_x_59/B[24] ), .B(n4551), .Z(n3837) );
HS65_LH_NAND2X7 U5481 ( .A(\sub_x_53/A[25] ), .B(n2845), .Z(n3836) );
HS65_LH_IVX7 U5482 ( .A(n4418), .Z(n4409) );
HS65_LH_NOR2X6 U5483 ( .A(n4984), .B(n5129), .Z(n3907) );
HS65_LH_IVX4 U5484 ( .A(n5419), .Z(n4417) );
HS65_LH_NAND2X4 U5486 ( .A(\lte_x_59/B[16] ), .B(n2864), .Z(n4061) );
HS65_LH_NAND2X5 U5487 ( .A(\lte_x_59/B[21] ), .B(n4587), .Z(n3821) );
HS65_LH_NAND2X5 U5488 ( .A(n4595), .B(n4561), .Z(n4562) );
HS65_LH_IVX9 U5489 ( .A(n4951), .Z(n5176) );
HS65_LH_IVX9 U5490 ( .A(n4341), .Z(n4490) );
HS65_LH_NAND2X7 U5491 ( .A(\sub_x_53/A[0] ), .B(n4551), .Z(n5183) );
HS65_LH_OAI21X3 U5492 ( .A(n2871), .B(n5179), .C(n4890), .Z(n4891) );
HS65_LH_IVX4 U5493 ( .A(n4757), .Z(n4033) );
HS65_LH_IVX9 U5495 ( .A(n3846), .Z(n4086) );
HS65_LH_IVX7 U5500 ( .A(n5272), .Z(n5273) );
HS65_LH_NAND2X5 U5503 ( .A(\sub_x_53/A[29] ), .B(n4588), .Z(n3545) );
HS65_LH_IVX7 U5504 ( .A(n5258), .Z(n5259) );
HS65_LH_NAND2X7 U5505 ( .A(n7866), .B(n9065), .Z(
\u_DataPath/jump_address_i [16]) );
HS65_LH_NOR2X5 U5506 ( .A(n5656), .B(n5655), .Z(n5657) );
HS65_LH_NAND2X5 U5507 ( .A(n4206), .B(n4205), .Z(n4226) );
HS65_LH_NAND2X4 U5508 ( .A(n5313), .B(n5544), .Z(n5325) );
HS65_LH_NAND2X5 U5511 ( .A(\sub_x_53/A[25] ), .B(n5425), .Z(n3574) );
HS65_LH_IVX9 U5512 ( .A(n4143), .Z(n3354) );
HS65_LH_NAND2X7 U5513 ( .A(n2733), .B(\u_DataPath/toPC2_i [27]), .Z(n8240)
);
HS65_LH_NAND2X4 U5515 ( .A(n2840), .B(n7623), .Z(n5449) );
HS65_LH_NAND2X7 U5517 ( .A(n2860), .B(n4967), .Z(n5290) );
HS65_LH_OAI12X6 U5518 ( .A(n4719), .B(n4718), .C(\sub_x_53/A[25] ), .Z(n5502) );
HS65_LH_NOR2X5 U5519 ( .A(n4981), .B(n5180), .Z(n5500) );
HS65_LH_IVX9 U5522 ( .A(n4905), .Z(n3231) );
HS65_LH_NAND2X5 U5524 ( .A(\sub_x_53/A[29] ), .B(n5422), .Z(n4316) );
HS65_LH_NOR2X6 U5526 ( .A(\sub_x_53/A[29] ), .B(n5422), .Z(n4314) );
HS65_LH_NAND2X4 U5528 ( .A(n5327), .B(n5544), .Z(n4666) );
HS65_LH_NOR2X6 U5530 ( .A(\sub_x_53/A[30] ), .B(n2873), .Z(n4230) );
HS65_LH_OAI22X4 U5532 ( .A(n7917), .B(n8404), .C(n7915), .D(n8403), .Z(
\u_DataPath/data_read_ex_1_i [14]) );
HS65_LH_OAI22X4 U5533 ( .A(n7917), .B(n8343), .C(n7915), .D(n8342), .Z(
\u_DataPath/data_read_ex_1_i [13]) );
HS65_LH_OAI22X4 U5534 ( .A(n7902), .B(n8293), .C(n7899), .D(n8183), .Z(
\u_DataPath/data_read_ex_2_i [12]) );
HS65_LH_OAI22X4 U5535 ( .A(n7917), .B(n8362), .C(n7915), .D(n8361), .Z(
\u_DataPath/data_read_ex_1_i [23]) );
HS65_LH_OAI22X4 U5536 ( .A(n7902), .B(n8415), .C(n7899), .D(n8171), .Z(
\u_DataPath/data_read_ex_2_i [5]) );
HS65_LH_OAI22X4 U5537 ( .A(n7917), .B(n8372), .C(n7915), .D(n8371), .Z(
\u_DataPath/data_read_ex_1_i [24]) );
HS65_LH_OAI22X4 U5538 ( .A(n7917), .B(n8353), .C(n7915), .D(n8352), .Z(
\u_DataPath/data_read_ex_1_i [22]) );
HS65_LH_OAI22X4 U5539 ( .A(n7902), .B(n8304), .C(n7899), .D(n8180), .Z(
\u_DataPath/data_read_ex_2_i [7]) );
HS65_LH_OAI22X4 U5540 ( .A(n7902), .B(n8457), .C(n7901), .D(n8386), .Z(
\u_DataPath/data_read_ex_2_i [18]) );
HS65_LH_OAI22X4 U5541 ( .A(n7902), .B(n8326), .C(n7900), .D(n8322), .Z(
\u_DataPath/data_read_ex_2_i [19]) );
HS65_LH_OAI22X4 U5542 ( .A(n7917), .B(n8378), .C(n7915), .D(n8377), .Z(
\u_DataPath/data_read_ex_1_i [27]) );
HS65_LH_OAI22X4 U5543 ( .A(n7902), .B(n8168), .C(n7899), .D(n8156), .Z(
\u_DataPath/data_read_ex_2_i [1]) );
HS65_LH_OAI22X4 U5544 ( .A(n7902), .B(n8362), .C(n7899), .D(n8178), .Z(
\u_DataPath/data_read_ex_2_i [23]) );
HS65_LH_OAI22X4 U5545 ( .A(n7917), .B(n8358), .C(n7915), .D(n8357), .Z(
\u_DataPath/data_read_ex_1_i [16]) );
HS65_LH_OAI22X4 U5546 ( .A(n7902), .B(n8408), .C(n7899), .D(n8175), .Z(
\u_DataPath/data_read_ex_2_i [17]) );
HS65_LH_OAI22X4 U5547 ( .A(n7917), .B(n8367), .C(n7915), .D(n8366), .Z(
\u_DataPath/data_read_ex_1_i [21]) );
HS65_LH_OAI22X4 U5548 ( .A(n7902), .B(n8321), .C(n7900), .D(n8315), .Z(
\u_DataPath/data_read_ex_2_i [26]) );
HS65_LH_OAI22X4 U5549 ( .A(n7902), .B(n8314), .C(n7899), .D(n8310), .Z(
\u_DataPath/data_read_ex_2_i [6]) );
HS65_LH_OAI22X4 U5550 ( .A(n7917), .B(n8397), .C(n7915), .D(n8396), .Z(
\u_DataPath/data_read_ex_1_i [30]) );
HS65_LH_OAI22X4 U5551 ( .A(n7902), .B(n8330), .C(n7900), .D(n8327), .Z(
\u_DataPath/data_read_ex_2_i [25]) );
HS65_LH_OAI22X4 U5552 ( .A(n7902), .B(n8422), .C(n7899), .D(n8158), .Z(
\u_DataPath/data_read_ex_2_i [31]) );
HS65_LH_OAI22X4 U5553 ( .A(n7917), .B(n8348), .C(n7915), .D(n8347), .Z(
\u_DataPath/data_read_ex_1_i [11]) );
HS65_LH_OAI22X4 U5554 ( .A(n9272), .B(n9186), .C(n9119), .D(n8753), .Z(
\u_DataPath/data_read_ex_2_i [10]) );
HS65_LH_OAI22X4 U5555 ( .A(n7902), .B(n8275), .C(n7899), .D(n8261), .Z(
\u_DataPath/data_read_ex_2_i [8]) );
HS65_LH_NOR2X5 U5556 ( .A(n4575), .B(n4570), .Z(n3318) );
HS65_LH_IVX4 U5557 ( .A(n4477), .Z(n4109) );
HS65_LH_NAND2X7 U5558 ( .A(\lte_x_59/B[14] ), .B(n3366), .Z(n4915) );
HS65_LH_NOR2X6 U5559 ( .A(\sub_x_53/A[23] ), .B(n5417), .Z(n3698) );
HS65_LL_IVX7 U5560 ( .A(n3272), .Z(\lte_x_59/B[15] ) );
HS65_LL_NOR2X5 U5561 ( .A(\lte_x_59/B[16] ), .B(n4985), .Z(n5530) );
HS65_LH_NOR2X6 U5562 ( .A(\lte_x_59/B[22] ), .B(n5654), .Z(n5603) );
HS65_LH_NAND2X5 U5563 ( .A(\sub_x_53/A[23] ), .B(n5417), .Z(n3700) );
HS65_LH_NAND2X7 U5564 ( .A(n2842), .B(n5376), .Z(n4050) );
HS65_LH_NOR2X6 U5565 ( .A(n3365), .B(n3521), .Z(n3814) );
HS65_LH_NOR2X3 U5567 ( .A(n5320), .B(n3756), .Z(n3639) );
HS65_LH_NAND2X7 U5568 ( .A(\lte_x_59/B[21] ), .B(n5418), .Z(n4373) );
HS65_LH_NAND2X7 U5569 ( .A(\lte_x_59/B[22] ), .B(n5654), .Z(n5605) );
HS65_LH_NAND2X7 U5571 ( .A(\lte_x_59/B[6] ), .B(n2865), .Z(n4641) );
HS65_LH_NAND2X7 U5572 ( .A(\sub_x_53/A[20] ), .B(n3376), .Z(n4418) );
HS65_LH_NOR2X6 U5573 ( .A(\sub_x_53/A[23] ), .B(n4967), .Z(n3731) );
HS65_LH_NAND2X7 U5574 ( .A(\sub_x_53/A[23] ), .B(n4967), .Z(n3733) );
HS65_LH_NAND2X7 U5575 ( .A(n2858), .B(n5398), .Z(n4013) );
HS65_LH_NAND2X5 U5576 ( .A(n5373), .B(n4682), .Z(n5313) );
HS65_LH_IVX9 U5577 ( .A(n3788), .Z(n5615) );
HS65_LH_NAND2X7 U5579 ( .A(n2853), .B(n5567), .Z(n3802) );
HS65_LH_IVX9 U5580 ( .A(\lte_x_59/B[16] ), .Z(n5022) );
HS65_LH_NOR2X6 U5582 ( .A(\lte_x_59/B[9] ), .B(n5053), .Z(n4876) );
HS65_LH_NAND2X7 U5583 ( .A(\lte_x_59/B[14] ), .B(n5061), .Z(n4926) );
HS65_LH_NAND2X7 U5586 ( .A(n2842), .B(n4674), .Z(n4083) );
HS65_LH_NAND2X7 U5587 ( .A(\lte_x_59/B[6] ), .B(n4147), .Z(n4628) );
HS65_LH_NOR2X6 U5588 ( .A(n4674), .B(n2842), .Z(n4081) );
HS65_LH_NAND2X7 U5589 ( .A(n3521), .B(n5048), .Z(n4084) );
HS65_LHS_XNOR2X3 U5590 ( .A(n5909), .B(n5908), .Z(\u_DataPath/toPC2_i [27])
);
HS65_LL_NOR2X3 U5592 ( .A(\lte_x_59/B[14] ), .B(n5061), .Z(n4924) );
HS65_LH_NOR2X3 U5593 ( .A(n4726), .B(n4795), .Z(n3648) );
HS65_LH_NAND2X7 U5594 ( .A(\lte_x_59/B[24] ), .B(n3382), .Z(n5193) );
HS65_LHS_XNOR2X6 U5595 ( .A(n7308), .B(n7307), .Z(
\u_DataPath/u_execute/link_value_i [28]) );
HS65_LH_NOR2X6 U5596 ( .A(\lte_x_59/B[24] ), .B(n5180), .Z(n3616) );
HS65_LH_NOR2X6 U5597 ( .A(n3521), .B(n5048), .Z(n3846) );
HS65_LH_NAND2X7 U5598 ( .A(n3521), .B(n3365), .Z(n5405) );
HS65_LH_NOR2X6 U5599 ( .A(n2858), .B(n4683), .Z(n4034) );
HS65_LH_OA12X9 U5600 ( .A(n4595), .B(n3488), .C(n4594), .Z(n3489) );
HS65_LH_NAND2X7 U5601 ( .A(n2858), .B(n4683), .Z(n4036) );
HS65_LH_NAND2X5 U5602 ( .A(n4431), .B(n4516), .Z(n5182) );
HS65_LH_IVX7 U5603 ( .A(n3488), .Z(n4593) );
HS65_LH_NAND2X7 U5604 ( .A(\lte_x_59/B[9] ), .B(n5053), .Z(n4878) );
HS65_LH_NOR2X5 U5605 ( .A(n4581), .B(n3788), .Z(n4528) );
HS65_LH_IVX9 U5606 ( .A(n8242), .Z(\u_DataPath/branch_target_i [25]) );
HS65_LH_NOR2X6 U5607 ( .A(n4105), .B(n4108), .Z(n4625) );
HS65_LHS_XOR2X3 U5608 ( .A(n5752), .B(n5751), .Z(\u_DataPath/toPC2_i [26])
);
HS65_LH_IVX9 U5609 ( .A(\lte_x_59/B[1] ), .Z(n4811) );
HS65_LH_NAND2X7 U5611 ( .A(\lte_x_59/B[4] ), .B(n3352), .Z(n4481) );
HS65_LH_IVX9 U5612 ( .A(n5418), .Z(n3377) );
HS65_LH_NOR2X6 U5613 ( .A(\lte_x_59/B[4] ), .B(n3352), .Z(n4100) );
HS65_LH_IVX9 U5615 ( .A(n5001), .Z(n2870) );
HS65_LL_NOR2X5 U5616 ( .A(n2925), .B(n3271), .Z(n3272) );
HS65_LH_IVX9 U5618 ( .A(n5061), .Z(n3366) );
HS65_LH_NAND2AX7 U5619 ( .A(n4534), .B(n3426), .Z(n3427) );
HS65_LL_IVX4 U5620 ( .A(n5152), .Z(n4512) );
HS65_LL_NOR2X2 U5621 ( .A(\lte_x_59/B[7] ), .B(n5312), .Z(n4637) );
HS65_LL_NOR2X6 U5622 ( .A(n3177), .B(n3176), .Z(\sub_x_53/A[20] ) );
HS65_LH_NAND2X7 U5624 ( .A(n2733), .B(\u_DataPath/toPC2_i [25]), .Z(n8242)
);
HS65_LH_NAND2X5 U5626 ( .A(\lte_x_59/B[8] ), .B(n5373), .Z(n4882) );
HS65_LL_OR2X18 U5627 ( .A(n3399), .B(n5136), .Z(n3756) );
HS65_LH_NOR2X6 U5628 ( .A(\lte_x_59/B[4] ), .B(n5032), .Z(n4108) );
HS65_LH_IVX9 U5630 ( .A(n5423), .Z(n3129) );
HS65_LH_NOR2X6 U5631 ( .A(\lte_x_59/B[8] ), .B(n5373), .Z(n4880) );
HS65_LH_NAND2X7 U5633 ( .A(\lte_x_59/B[3] ), .B(n5089), .Z(n4572) );
HS65_LH_IVX9 U5634 ( .A(n4838), .Z(n4508) );
HS65_LH_NAND2X5 U5635 ( .A(\lte_x_59/B[3] ), .B(n5321), .Z(n4594) );
HS65_LH_NAND2X7 U5636 ( .A(n7834), .B(n4550), .Z(n3788) );
HS65_LH_NOR2X6 U5640 ( .A(\lte_x_59/B[7] ), .B(n5030), .Z(n4622) );
HS65_LHS_XNOR2X3 U5641 ( .A(n6116), .B(n6115), .Z(
\u_DataPath/u_execute/resAdd1_i [26]) );
HS65_LH_IVX9 U5642 ( .A(\u_DataPath/u_idexreg/N16 ), .Z(n8101) );
HS65_LH_IVX9 U5643 ( .A(n8253), .Z(\u_DataPath/branch_target_i [14]) );
HS65_LH_IVX9 U5644 ( .A(n8245), .Z(\u_DataPath/branch_target_i [23]) );
HS65_LHS_XNOR2X3 U5645 ( .A(n5917), .B(n5916), .Z(\u_DataPath/toPC2_i [25])
);
HS65_LL_AOI12X4 U5646 ( .A(n5914), .B(n5916), .C(n5739), .Z(n5751) );
HS65_LL_NAND2X5 U5647 ( .A(n3148), .B(n3147), .Z(n4976) );
HS65_LH_IVX9 U5648 ( .A(n9052), .Z(n8104) );
HS65_LL_NAND2X4 U5649 ( .A(n8710), .B(n7780), .Z(n7784) );
HS65_LL_NAND2X5 U5653 ( .A(n3145), .B(n3144), .Z(n5180) );
HS65_LH_OAI22X6 U5654 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [24]), .C(
n8550), .D(n3409), .Z(n3138) );
HS65_LH_NOR2X5 U5655 ( .A(n8426), .B(n3409), .Z(n3074) );
HS65_LL_NAND2X5 U5656 ( .A(n3183), .B(n3182), .Z(n5418) );
HS65_LL_OAI22X3 U5659 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [11]), .C(
n8345), .D(n3409), .Z(n3072) );
HS65_LH_OAI22X6 U5661 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [13]), .C(
n8339), .D(n3409), .Z(n3249) );
HS65_LH_IVX9 U5662 ( .A(n5425), .Z(n4997) );
HS65_LL_IVX9 U5663 ( .A(n5321), .Z(n5089) );
HS65_LH_AOI22X3 U5665 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][2] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][2] ), .D(
n7171), .Z(n6563) );
HS65_LH_AO22X9 U5666 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][2] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][2] ), .D(
n6635), .Z(n6566) );
HS65_LH_AO22X9 U5667 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][13] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][13] ), .Z(n6991)
);
HS65_LH_AO22X9 U5668 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][13] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][13] ), .Z(n6990)
);
HS65_LH_AOI22X3 U5669 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][9] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][9] ), .D(
n7285), .Z(n7132) );
HS65_LH_AOI22X3 U5670 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][13] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][13] ), .Z(n6984)
);
HS65_LH_AOI22X3 U5671 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][31] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][31] ), .D(
n7285), .Z(n6876) );
HS65_LH_AOI22X3 U5673 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][5] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][5] ), .D(
n2888), .Z(n6931) );
HS65_LH_AOI22X3 U5674 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][13] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][13] ), .Z(n6989)
);
HS65_LH_AOI22X3 U5675 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][22] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][22] ), .Z(n7008)
);
HS65_LH_AOI22X3 U5676 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][5] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][5] ), .D(
n7264), .Z(n6932) );
HS65_LH_AO22X9 U5677 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][4] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][4] ), .Z(n7362)
);
HS65_LH_AOI22X3 U5679 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][13] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][13] ), .Z(n6988)
);
HS65_LH_AOI22X3 U5680 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][8] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][8] ), .D(
n7171), .Z(n6463) );
HS65_LH_AOI22X3 U5681 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][17] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][17] ), .D(
n2888), .Z(n6889) );
HS65_LH_AO22X9 U5682 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][25] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][25] ), .Z(n7051)
);
HS65_LH_AO22X9 U5683 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][14] ), .B(n7429),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][14] ), .Z(n7368)
);
HS65_LH_AO22X9 U5685 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][31] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][31] ), .D(
n7282), .Z(n6878) );
HS65_LH_AO22X9 U5686 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][11] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][11] ), .Z(n7056)
);
HS65_LH_AO22X9 U5687 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][2] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][2] ), .Z(n6970)
);
HS65_LH_AO22X9 U5689 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][24] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][24] ), .Z(n7572)
);
HS65_LH_AO22X9 U5690 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][2] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][2] ), .Z(n6971)
);
HS65_LH_AO22X9 U5692 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][8] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][8] ), .Z(n6778)
);
HS65_LH_AOI22X3 U5693 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][26] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][26] ), .D(
n7171), .Z(n6503) );
HS65_LH_AO22X9 U5694 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][9] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][9] ), .D(
n7292), .Z(n7137) );
HS65_LH_AOI22X3 U5695 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][6] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][6] ), .D(n7516),
.Z(n7251) );
HS65_LH_AO22X9 U5696 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][17] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][17] ), .D(
n7282), .Z(n6898) );
HS65_LH_AO22X9 U5697 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][22] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][22] ), .D(
n7586), .Z(n7000) );
HS65_LH_AOI22X3 U5698 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][9] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][9] ), .D(
n7171), .Z(n7131) );
HS65_LH_AOI22X3 U5699 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][17] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][17] ), .D(
n7285), .Z(n6896) );
HS65_LH_AO22X9 U5700 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][21] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][21] ), .Z(n7607)
);
HS65_LH_AO22X9 U5701 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][13] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][13] ), .D(
n7586), .Z(n6980) );
HS65_LH_AOI22X3 U5702 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][31] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][31] ), .D(
n6363), .Z(n6869) );
HS65_LH_AO22X9 U5703 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][25] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][25] ), .Z(n7050)
);
HS65_LH_AOI22X3 U5705 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][17] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][17] ), .D(
n7264), .Z(n6890) );
HS65_LH_AO22X9 U5706 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][2] ), .B(n7580),
.C(n7579), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][2] ), .Z(n6953) );
HS65_LH_AO22X9 U5707 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][21] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][21] ), .Z(n7581)
);
HS65_LH_AO22X9 U5712 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][13] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][13] ), .Z(n6976)
);
HS65_LH_AO22X9 U5714 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][25] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][25] ), .D(
n7586), .Z(n7040) );
HS65_LH_AO22X9 U5716 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][16] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][16] ), .Z(n7538)
);
HS65_LH_AOI22X3 U5717 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][28] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][28] ), .D(
n2889), .Z(n7498) );
HS65_LH_AO22X9 U5718 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][6] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][6] ), .D(n7266), .Z(n6476) );
HS65_LH_AOI22X3 U5719 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][28] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][28] ), .D(
n7272), .Z(n6913) );
HS65_LH_AO22X9 U5720 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][15] ), .B(n7429),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][15] ), .Z(n7185)
);
HS65_LH_AOI22X3 U5721 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][28] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][28] ), .D(
n2888), .Z(n6909) );
HS65_LH_AO22X9 U5722 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][6] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][6] ), .D(n7291), .Z(n6490) );
HS65_LH_AOI22X3 U5724 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][6] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][6] ), .D(
n7171), .Z(n6483) );
HS65_LH_AOI22X3 U5726 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][15] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][15] ), .D(
n7285), .Z(n6379) );
HS65_LH_AOI22X3 U5727 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][28] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][28] ), .D(
n7285), .Z(n6916) );
HS65_LH_AOI22X3 U5728 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][15] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][15] ), .D(
n7171), .Z(n6378) );
HS65_LH_AO22X9 U5729 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][23] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][23] ), .Z(n7235)
);
HS65_LH_AO22X9 U5730 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][25] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][25] ), .Z(n7036)
);
HS65_LH_AOI22X3 U5732 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][25] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][25] ), .Z(n7048)
);
HS65_LH_AOI22X3 U5733 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][29] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][29] ), .D(
n2889), .Z(n7520) );
HS65_LH_AOI22X3 U5734 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][23] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][23] ), .D(n7516),
.Z(n7231) );
HS65_LH_AOI22X3 U5735 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][15] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][15] ), .D(n7516),
.Z(n7191) );
HS65_LH_AOI22X3 U5736 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][9] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][9] ), .D(
n6363), .Z(n7125) );
HS65_LH_AO22X9 U5737 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][29] ), .B(n7429),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][29] ), .Z(n7513)
);
HS65_LH_AO22X9 U5738 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][14] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][14] ), .Z(n7382)
);
HS65_LH_AOI22X3 U5739 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][28] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][28] ), .D(
n7264), .Z(n6910) );
HS65_LH_AO22X9 U5740 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][31] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][31] ), .Z(n6688)
);
HS65_LH_AO22X9 U5741 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][14] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][14] ), .Z(n7378)
);
HS65_LH_AOI22X3 U5742 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][29] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][29] ), .D(
n2891), .Z(n7515) );
HS65_LH_AOI22X3 U5743 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][25] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][25] ), .Z(n7044)
);
HS65_LH_AOI22X3 U5745 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][28] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][28] ), .D(
n2891), .Z(n7495) );
HS65_LH_AO22X9 U5747 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][22] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][22] ), .Z(n7011)
);
HS65_LH_AO22X9 U5748 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][22] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][22] ), .Z(n7010)
);
HS65_LH_AO22X9 U5749 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][9] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][9] ), .D(
n7586), .Z(n7020) );
HS65_LH_AO22X9 U5750 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][20] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][20] ), .D(
n7292), .Z(n6861) );
HS65_LH_AO22X9 U5752 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][3] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][3] ), .D(
n7284), .Z(n6585) );
HS65_LH_AOI22X3 U5753 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][3] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][3] ), .D(
n7171), .Z(n6583) );
HS65_LH_AOI22X3 U5754 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][30] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][30] ), .Z(n7420)
);
HS65_LH_AOI22X3 U5756 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][20] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][20] ), .D(
n6942), .Z(n6859) );
HS65_LH_AO22X9 U5757 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][18] ), .B(n7429),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][18] ), .Z(n6328)
);
HS65_LH_AOI22X3 U5758 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][19] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][19] ), .Z(n6756)
);
HS65_LH_AO22X9 U5759 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][7] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][7] ), .Z(n6730)
);
HS65_LH_AO22X9 U5761 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][5] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][5] ), .Z(n6710)
);
HS65_LH_AOI22X3 U5762 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][20] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][20] ), .D(
n7272), .Z(n6853) );
HS65_LH_AO22X9 U5763 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][19] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][19] ), .Z(n6762)
);
HS65_LH_AO22X9 U5765 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][18] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][18] ), .D(
n7282), .Z(n6661) );
HS65_LH_AO22X9 U5766 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][19] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][19] ), .Z(n6761)
);
HS65_LH_AOI22X3 U5767 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][18] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][18] ), .D(
n7285), .Z(n6659) );
HS65_LH_AOI22X3 U5768 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][18] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][18] ), .D(
n6172), .Z(n6658) );
HS65_LH_AOI22X3 U5769 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][19] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][19] ), .Z(n6760)
);
HS65_LH_AOI22X3 U5770 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][19] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][19] ), .Z(n6759)
);
HS65_LH_AOI22X3 U5771 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][20] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][20] ), .D(
n7285), .Z(n6856) );
HS65_LH_AOI22X3 U5772 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][18] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][18] ), .D(n6740),
.Z(n6329) );
HS65_LH_AOI22X3 U5773 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][7] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][7] ), .D(
n7171), .Z(n6443) );
HS65_LH_AO22X9 U5774 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][3] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][3] ), .Z(n7402)
);
HS65_LH_AOI22X3 U5775 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][0] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][0] ), .D(n7516),
.Z(n7438) );
HS65_LH_AOI22X3 U5776 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][9] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][9] ), .Z(n7028)
);
HS65_LH_AOI22X3 U5777 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][10] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][10] ), .D(
n6670), .Z(n7207) );
HS65_LH_AOI22X3 U5779 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][0] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][0] ), .D(n6740),
.Z(n7432) );
HS65_LH_AOI22X3 U5780 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][10] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][10] ), .D(
n6942), .Z(n6406) );
HS65_LH_AOI22X3 U5781 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][20] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][20] ), .D(
n2889), .Z(n7478) );
HS65_LH_AOI22X3 U5782 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][12] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][12] ), .D(
n7171), .Z(n6543) );
HS65_LH_AOI22X3 U5783 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][22] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][22] ), .Z(n7009)
);
HS65_LH_AO22X9 U5784 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][12] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][12] ), .D(
n7282), .Z(n6546) );
HS65_LH_AOI22X3 U5785 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][10] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][10] ), .D(
n7285), .Z(n6403) );
HS65_LH_AOI22X3 U5787 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][3] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][3] ), .D(
n2891), .Z(n7390) );
HS65_LH_AO22X9 U5788 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][20] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][20] ), .Z(n7486)
);
HS65_LH_AO22X9 U5789 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][18] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][18] ), .Z(n6357)
);
HS65_LH_AO22X9 U5790 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][18] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][18] ), .Z(n6356)
);
HS65_LH_AOI22X3 U5791 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][18] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][18] ), .Z(n6355)
);
HS65_LH_AOI22X3 U5792 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][9] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][9] ), .Z(n7024)
);
HS65_LH_AOI22X3 U5793 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][18] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][18] ), .Z(n6354)
);
HS65_LH_AO22X9 U5794 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][4] ), .B(n7580),
.C(n7579), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][4] ), .Z(n7347) );
HS65_LH_AO22X9 U5795 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][9] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][9] ), .Z(n7031)
);
HS65_LH_AOI22X3 U5797 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][10] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][10] ), .D(n7516),
.Z(n7211) );
HS65_LH_AOI22X3 U5798 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][3] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][3] ), .D(n2889), .Z(n7393) );
HS65_LH_AO22X9 U5799 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][20] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][20] ), .Z(n7472)
);
HS65_LH_AO22X9 U5800 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][9] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][9] ), .Z(n7030)
);
HS65_LH_AOI22X3 U5802 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][9] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][9] ), .Z(n7029)
);
HS65_LH_AO22X9 U5804 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][19] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][19] ), .Z(n6741)
);
HS65_LH_AO22X9 U5805 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][4] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][4] ), .D(
n7586), .Z(n7351) );
HS65_LH_AO22X9 U5806 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][27] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][27] ), .Z(n7452)
);
HS65_LH_AO22X9 U5808 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][27] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][27] ), .D(
n7586), .Z(n7456) );
HS65_LH_AO22X9 U5809 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][27] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][27] ), .Z(n7466)
);
HS65_LH_AOI22X3 U5810 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][11] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][11] ), .Z(n7068)
);
HS65_LH_AO22X9 U5812 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][11] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][11] ), .Z(n7070)
);
HS65_LH_AO22X9 U5813 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][11] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][11] ), .Z(n7071)
);
HS65_LH_AOI22X3 U5814 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][11] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][11] ), .Z(n7064)
);
HS65_LH_AO22X9 U5817 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][11] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][11] ), .D(
n7586), .Z(n7060) );
HS65_LH_AO22X9 U5818 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][19] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][19] ), .D(
n7586), .Z(n6748) );
HS65_LH_AOI22X3 U5819 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][20] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][20] ), .D(
n2888), .Z(n6849) );
HS65_LH_AO22X9 U5820 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][16] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][16] ), .Z(n7552)
);
HS65_LH_AOI22X3 U5822 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][20] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][20] ), .D(
n7264), .Z(n6850) );
HS65_LH_NOR2X6 U5823 ( .A(opcode_i[5]), .B(n8046), .Z(n8636) );
HS65_LL_OAI12X3 U5824 ( .A(n5971), .B(n5974), .C(n5973), .Z(n6115) );
HS65_LH_NOR2X6 U5825 ( .A(n8794), .B(n9050), .Z(\u_DataPath/cw_exmem_i [3])
);
HS65_LH_NOR2X6 U5827 ( .A(n9168), .B(n9049), .Z(\u_DataPath/u_idexreg/N15 )
);
HS65_LH_OAI21X3 U5828 ( .A(n8871), .B(n9012), .C(n8767), .Z(n8105) );
HS65_LH_NOR2X6 U5829 ( .A(n8884), .B(n9051), .Z(n8438) );
HS65_LL_NAND2X4 U5830 ( .A(n3431), .B(n3430), .Z(n4458) );
HS65_LH_NOR2X6 U5831 ( .A(n8834), .B(n3341), .Z(n3058) );
HS65_LH_NOR2X6 U5832 ( .A(n8821), .B(n3341), .Z(n4973) );
HS65_LH_NOR2X6 U5833 ( .A(n8859), .B(n3341), .Z(n3150) );
HS65_LH_NAND2X7 U5834 ( .A(n8556), .B(n3155), .Z(n3156) );
HS65_LH_NOR2X5 U5835 ( .A(n8841), .B(n3403), .Z(n3108) );
HS65_LH_NOR2X6 U5837 ( .A(n8838), .B(n3341), .Z(n3096) );
HS65_LL_NAND2X2 U5838 ( .A(n3181), .B(n8543), .Z(n3182) );
HS65_LH_IVX9 U5839 ( .A(n8545), .Z(n3173) );
HS65_LH_NOR2X6 U5840 ( .A(n3122), .B(n7754), .Z(n7679) );
HS65_LL_OAI12X3 U5841 ( .A(n5767), .B(n5770), .C(n5769), .Z(n5916) );
HS65_LHS_XOR2X3 U5843 ( .A(n5771), .B(n5770), .Z(\u_DataPath/toPC2_i [24])
);
HS65_LH_NAND2X7 U5844 ( .A(n2733), .B(\u_DataPath/toPC2_i [23]), .Z(n8245)
);
HS65_LH_NAND2X7 U5845 ( .A(n2733), .B(\u_DataPath/toPC2_i [14]), .Z(n8253)
);
HS65_LL_NAND2X11 U5846 ( .A(n3303), .B(n3302), .Z(n5088) );
HS65_LH_NAND2X7 U5847 ( .A(n3234), .B(n8511), .Z(n3235) );
HS65_LH_NOR2X6 U5848 ( .A(n9400), .B(n3341), .Z(n3269) );
HS65_LL_IVX9 U5850 ( .A(n3340), .Z(n3270) );
HS65_LH_NAND2X7 U5851 ( .A(n8577), .B(n8318), .Z(n8300) );
HS65_LH_IVX9 U5852 ( .A(n7764), .Z(n7755) );
HS65_LH_NAND2X7 U5853 ( .A(n8038), .B(n8039), .Z(n8068) );
HS65_LH_AOI31X3 U5855 ( .A(n8086), .B(\u_DataPath/immediate_ext_dec_i [1]),
.C(n8635), .D(n8085), .Z(n8087) );
HS65_LH_IVX9 U5856 ( .A(n8277), .Z(\u_DataPath/branch_target_i [7]) );
HS65_LH_IVX9 U5857 ( .A(n8260), .Z(\u_DataPath/branch_target_i [9]) );
HS65_LH_IVX7 U5858 ( .A(n8045), .Z(n8046) );
HS65_LH_IVX9 U5859 ( .A(n8251), .Z(\u_DataPath/branch_target_i [16]) );
HS65_LH_IVX9 U5860 ( .A(n8247), .Z(\u_DataPath/branch_target_i [21]) );
HS65_LH_NAND2AX7 U5861 ( .A(\u_DataPath/data_read_ex_2_i [10]), .B(n2874),
.Z(n8508) );
HS65_LH_NOR2X6 U5862 ( .A(n8393), .B(n3340), .Z(n3343) );
HS65_LL_NAND2X4 U5863 ( .A(n3286), .B(n2874), .Z(n3287) );
HS65_LH_NAND2X7 U5864 ( .A(n8040), .B(n8039), .Z(n8069) );
HS65_LH_IVX7 U5865 ( .A(n8519), .Z(n3280) );
HS65_LH_OAI21X3 U5867 ( .A(n8125), .B(n8124), .C(n8635), .Z(n8127) );
HS65_LH_OAI21X3 U5868 ( .A(n8075), .B(n8125), .C(n8635), .Z(n8080) );
HS65_LH_NOR2X6 U5869 ( .A(n8389), .B(n7868), .Z(n8519) );
HS65_LH_IVX9 U5870 ( .A(n8188), .Z(n8288) );
HS65_LH_NAND2X7 U5871 ( .A(n2733), .B(\u_DataPath/toPC2_i [16]), .Z(n8251)
);
HS65_LH_NAND2X7 U5872 ( .A(n2733), .B(\u_DataPath/toPC2_i [21]), .Z(n8247)
);
HS65_LL_NAND3X13 U5873 ( .A(n3333), .B(n3057), .C(n3056), .Z(n3340) );
HS65_LL_BFX9 U5875 ( .A(n8483), .Z(n7921) );
HS65_LHS_XOR2X3 U5876 ( .A(n5828), .B(n5827), .Z(\u_DataPath/toPC2_i [22])
);
HS65_LH_NOR2X6 U5877 ( .A(n8037), .B(n8117), .Z(n8039) );
HS65_LH_NOR2X6 U5878 ( .A(n8041), .B(n8117), .Z(n8045) );
HS65_LH_NAND2X7 U5879 ( .A(n2733), .B(\u_DataPath/toPC2_i [10]), .Z(n8259)
);
HS65_LH_NOR2X6 U5880 ( .A(n8047), .B(n8117), .Z(n8634) );
HS65_LH_NAND2X7 U5881 ( .A(n2733), .B(\u_DataPath/toPC2_i [9]), .Z(n8260) );
HS65_LH_NAND2X7 U5882 ( .A(n2733), .B(\u_DataPath/toPC2_i [7]), .Z(n8277) );
HS65_LH_NOR2X6 U5883 ( .A(n7715), .B(n7714), .Z(n7716) );
HS65_LH_NOR2X6 U5884 ( .A(n8385), .B(n7868), .Z(n8539) );
HS65_LH_OAI211X3 U5885 ( .A(n8488), .B(n7868), .C(n8487), .D(n8566), .Z(
n8489) );
HS65_LH_NOR2X6 U5886 ( .A(n8345), .B(n7868), .Z(n8510) );
HS65_LH_NAND2X4 U5888 ( .A(n4714), .B(n8535), .Z(n3190) );
HS65_LH_NOR2X6 U5889 ( .A(n3241), .B(n7868), .Z(n8507) );
HS65_LH_IVX9 U5891 ( .A(n7671), .Z(n7677) );
HS65_LH_NOR2X6 U5892 ( .A(n8339), .B(n7868), .Z(n8516) );
HS65_LH_NAND2X7 U5893 ( .A(n3127), .B(n7869), .Z(n8562) );
HS65_LH_IVX9 U5896 ( .A(n5791), .Z(n5773) );
HS65_LH_NAND2X7 U5897 ( .A(n8566), .B(n7306), .Z(n8456) );
HS65_LH_NAND2X7 U5898 ( .A(n3140), .B(n7869), .Z(n8553) );
HS65_LH_NAND2X7 U5899 ( .A(n3153), .B(n7869), .Z(n8557) );
HS65_LHS_XNOR2X6 U5900 ( .A(n5702), .B(n5701), .Z(n5703) );
HS65_LH_NOR2X6 U5901 ( .A(n8830), .B(n7869), .Z(n3215) );
HS65_LH_NAND2X7 U5902 ( .A(n7661), .B(n7660), .Z(n7759) );
HS65_LHS_XNOR2X3 U5903 ( .A(n7713), .B(n7712), .Z(
\u_DataPath/u_execute/link_value_i [20]) );
HS65_LH_NAND2X7 U5904 ( .A(n8267), .B(n7869), .Z(n5692) );
HS65_LH_NAND2X7 U5905 ( .A(n3201), .B(n7869), .Z(n8530) );
HS65_LH_NAND2X7 U5906 ( .A(n3225), .B(n3407), .Z(n3080) );
HS65_LH_NOR2X6 U5907 ( .A(n8863), .B(n7869), .Z(n3226) );
HS65_LH_NAND2X7 U5908 ( .A(n3205), .B(n3407), .Z(n3094) );
HS65_LH_AOI12X2 U5909 ( .A(n6081), .B(n6083), .C(n6023), .Z(n6024) );
HS65_LH_NAND2X7 U5910 ( .A(n3242), .B(n7869), .Z(n8509) );
HS65_LH_NOR2X6 U5911 ( .A(n8849), .B(n7869), .Z(n3257) );
HS65_LH_NAND2X4 U5912 ( .A(n4714), .B(n8527), .Z(n3206) );
HS65_LH_IVX9 U5913 ( .A(n5992), .Z(n6007) );
HS65_LH_NAND2X7 U5915 ( .A(n3252), .B(n7869), .Z(n8518) );
HS65_LH_NAND2X7 U5916 ( .A(n3273), .B(n7869), .Z(n8524) );
HS65_LH_NAND2X7 U5917 ( .A(n3188), .B(n7869), .Z(n8535) );
HS65_LH_NAND2X7 U5919 ( .A(n3336), .B(n7869), .Z(n8496) );
HS65_LH_NAND2X7 U5920 ( .A(n2733), .B(\u_DataPath/u_fetch/pc1/N3 ), .Z(n8188) );
HS65_LH_NOR2X5 U5921 ( .A(n8842), .B(n7869), .Z(n3189) );
HS65_LH_NAND2X7 U5922 ( .A(n7670), .B(n7749), .Z(n7671) );
HS65_LH_NAND2X7 U5923 ( .A(n2733), .B(\u_DataPath/toPC2_i [3]), .Z(n8281) );
HS65_LL_OAI12X3 U5924 ( .A(n2879), .B(n3114), .C(n3113), .Z(n8576) );
HS65_LH_NAND2X7 U5925 ( .A(n2733), .B(\u_DataPath/toPC2_i [4]), .Z(n8280) );
HS65_LH_IVX9 U5927 ( .A(n7739), .Z(n8161) );
HS65_LH_IVX9 U5928 ( .A(n7720), .Z(n7723) );
HS65_LH_NAND2X5 U5929 ( .A(n3205), .B(n7802), .Z(n8527) );
HS65_LH_NOR2X6 U5931 ( .A(n3120), .B(n7673), .Z(n7660) );
HS65_LH_NAND2X7 U5932 ( .A(n3307), .B(n7802), .Z(n8492) );
HS65_LHS_XOR2X6 U5933 ( .A(n7793), .B(n7792), .Z(
\u_DataPath/u_execute/link_value_i [12]) );
HS65_LH_NAND2X7 U5934 ( .A(\u_DataPath/dataOut_exe_i [4]), .B(n7802), .Z(
n3347) );
HS65_LHS_XOR2X6 U5935 ( .A(n4005), .B(n4004), .Z(n4006) );
HS65_LH_IVX9 U5936 ( .A(n5999), .Z(n6083) );
HS65_LH_NAND3X5 U5937 ( .A(\u_DataPath/dataOut_exe_i [0]), .B(n4714), .C(
n7802), .Z(n3283) );
HS65_LH_NOR2X3 U5938 ( .A(n8833), .B(n7802), .Z(n3134) );
HS65_LH_NOR2X6 U5941 ( .A(n7691), .B(n7637), .Z(n7739) );
HS65_LH_IVX9 U5943 ( .A(n5962), .Z(n6077) );
HS65_LH_NAND2X7 U5944 ( .A(n7730), .B(n7729), .Z(n7792) );
HS65_LHS_XNOR2X6 U5946 ( .A(n7727), .B(n7729), .Z(
\u_DataPath/u_execute/link_value_i [10]) );
HS65_LH_IVX9 U5947 ( .A(n7903), .Z(n5713) );
HS65_LH_NAND2X5 U5948 ( .A(n9229), .B(n7781), .Z(n7782) );
HS65_LH_IVX9 U5949 ( .A(n5758), .Z(n5878) );
HS65_LHS_XNOR2X6 U5950 ( .A(n5901), .B(n5900), .Z(\u_DataPath/toPC2_i [3])
);
HS65_LHS_XNOR2X6 U5951 ( .A(n6096), .B(n6095), .Z(
\u_DataPath/u_execute/resAdd1_i [4]) );
HS65_LL_NAND2AX7 U5952 ( .A(n3044), .B(n3043), .Z(n3333) );
HS65_LL_NOR3X4 U5953 ( .A(n2984), .B(n9113), .C(n7640), .Z(n2879) );
HS65_LH_IVX18 U5954 ( .A(n5234), .Z(n5656) );
HS65_LL_NOR2X5 U5955 ( .A(n2964), .B(n8262), .Z(n3131) );
HS65_LL_AOI31X4 U5956 ( .A(n2965), .B(n2961), .C(n2912), .D(n2964), .Z(n3216) );
HS65_LH_IVX9 U5958 ( .A(n7905), .Z(n7904) );
HS65_LH_NAND3X5 U5960 ( .A(n2846), .B(n9031), .C(n2946), .Z(n3010) );
HS65_LH_IVX18 U5961 ( .A(n7906), .Z(n7903) );
HS65_LH_NAND2X4 U5964 ( .A(n9111), .B(n7085), .Z(n7094) );
HS65_LH_NOR2X6 U5965 ( .A(n7694), .B(n7775), .Z(n7691) );
HS65_LH_IVX9 U5966 ( .A(n7690), .Z(n7777) );
HS65_LH_NAND2X7 U5968 ( .A(n2733), .B(n7854), .Z(n8408) );
HS65_LH_NOR2X6 U5969 ( .A(n7652), .B(n7647), .Z(n7670) );
HS65_LL_NOR2X5 U5971 ( .A(n3450), .B(n3449), .Z(n5234) );
HS65_LH_NAND2X7 U5972 ( .A(n2733), .B(n8345), .Z(n8348) );
HS65_LH_NOR2X6 U5973 ( .A(n5995), .B(n5998), .Z(n6016) );
HS65_LL_NOR2X5 U5974 ( .A(n6150), .B(n6140), .Z(n6637) );
HS65_LL_NAND2X7 U5975 ( .A(n7114), .B(n7113), .Z(n7614) );
HS65_LH_NAND2X7 U5976 ( .A(n8269), .B(n2980), .Z(n3111) );
HS65_LH_IVX9 U5979 ( .A(n3314), .Z(n3413) );
HS65_LH_NOR2X6 U5980 ( .A(n7718), .B(n7787), .Z(n7781) );
HS65_LL_NOR3X4 U5981 ( .A(n3042), .B(n3041), .C(n3040), .Z(n3043) );
HS65_LH_IVX7 U5983 ( .A(n3048), .Z(n3049) );
HS65_LH_BFX18 U5984 ( .A(n8282), .Z(n7882) );
HS65_LH_NAND2X7 U5985 ( .A(n5930), .B(n5961), .Z(n5932) );
HS65_LL_NAND2X4 U5987 ( .A(n4713), .B(n9037), .Z(n3395) );
HS65_LH_NAND2X2 U5988 ( .A(n4713), .B(n9343), .Z(n3164) );
HS65_LH_OR2X9 U5989 ( .A(\u_DataPath/jaddr_i [18]), .B(n2880), .Z(n6341) );
HS65_LH_NAND2X4 U5990 ( .A(n4717), .B(n9343), .Z(n4209) );
HS65_LHS_XNOR2X3 U5991 ( .A(\u_DataPath/jaddr_i [20]), .B(n7618), .Z(n7087)
);
HS65_LH_IVX9 U5992 ( .A(n8446), .Z(n7907) );
HS65_LH_IVX7 U5993 ( .A(n5961), .Z(n5967) );
HS65_LL_NAND3X3 U5994 ( .A(n2935), .B(n2957), .C(n2963), .Z(n2939) );
HS65_LH_NAND2X7 U5995 ( .A(n4285), .B(n5688), .Z(n4286) );
HS65_LH_IVX9 U5996 ( .A(n8591), .Z(n7947) );
HS65_LL_NOR2X2 U5997 ( .A(n2959), .B(n2958), .Z(n2965) );
HS65_LL_NOR2X5 U5998 ( .A(n6334), .B(n6353), .Z(n6745) );
HS65_LH_NAND2X7 U6000 ( .A(n5811), .B(n5814), .Z(n5798) );
HS65_LL_NOR2X5 U6001 ( .A(n6147), .B(n2886), .Z(n6362) );
HS65_LH_NAND2X7 U6002 ( .A(n5728), .B(n5757), .Z(n5730) );
HS65_LH_NAND2X7 U6003 ( .A(n5853), .B(n5718), .Z(n5742) );
HS65_LH_IVX7 U6005 ( .A(n8393), .Z(n3418) );
HS65_LH_NAND2X7 U6006 ( .A(n5726), .B(n5779), .Z(n5760) );
HS65_LL_NOR2X5 U6008 ( .A(n6348), .B(n6334), .Z(n6739) );
HS65_LH_NAND2X4 U6009 ( .A(n4717), .B(n9341), .Z(n3145) );
HS65_LL_NOR2X5 U6010 ( .A(n6334), .B(n6349), .Z(n6951) );
HS65_LH_NAND2X5 U6011 ( .A(n5722), .B(n5834), .Z(n5724) );
HS65_LH_NAND2X7 U6013 ( .A(n2733), .B(n8265), .Z(n8275) );
HS65_LH_IVX4 U6014 ( .A(n7665), .Z(n7741) );
HS65_LH_NAND2X7 U6016 ( .A(\u_DataPath/jaddr_i [25]), .B(n6138), .Z(n6140)
);
HS65_LL_NOR2X3 U6017 ( .A(n6349), .B(n6352), .Z(n6689) );
HS65_LH_NAND2X7 U6019 ( .A(n2733), .B(n8426), .Z(n8449) );
HS65_LH_NAND2X7 U6020 ( .A(n2733), .B(n8380), .Z(n8397) );
HS65_LH_NAND2X7 U6021 ( .A(n2733), .B(n8385), .Z(n8412) );
HS65_LH_IVX9 U6022 ( .A(n7776), .Z(n8084) );
HS65_LH_NAND2X7 U6025 ( .A(n4713), .B(n8913), .Z(n3346) );
HS65_LH_NAND2X7 U6026 ( .A(n7695), .B(n7773), .Z(n7775) );
HS65_LH_IVX9 U6027 ( .A(n8446), .Z(n7906) );
HS65_LH_NAND2X7 U6029 ( .A(addr_to_iram[4]), .B(n8682), .Z(n7680) );
HS65_LH_NAND2X7 U6032 ( .A(n5928), .B(n5980), .Z(n5964) );
HS65_LH_NAND2X7 U6033 ( .A(n4717), .B(n9039), .Z(n3303) );
HS65_LH_NAND2X7 U6035 ( .A(n5936), .B(n6011), .Z(n5998) );
HS65_LH_NAND2X7 U6036 ( .A(n2733), .B(n8427), .Z(n8330) );
HS65_LH_NAND2X7 U6037 ( .A(n2733), .B(n8323), .Z(n8326) );
HS65_LH_IVX7 U6040 ( .A(n8446), .Z(n7905) );
HS65_LH_NAND2X7 U6041 ( .A(n2733), .B(n8350), .Z(n8353) );
HS65_LH_IVX9 U6042 ( .A(n8051), .Z(n8067) );
HS65_LH_IVX9 U6043 ( .A(n8231), .Z(n8282) );
HS65_LH_NOR2X6 U6044 ( .A(n5957), .B(n5960), .Z(n5930) );
HS65_LH_NAND2X7 U6045 ( .A(\u_DataPath/jaddr_i [22]), .B(n8163), .Z(n2886)
);
HS65_LH_NAND2X7 U6046 ( .A(n5920), .B(n5919), .Z(n5946) );
HS65_LL_NAND2X7 U6047 ( .A(n8153), .B(n8152), .Z(n6350) );
HS65_LH_IVX9 U6048 ( .A(n8052), .Z(n8629) );
HS65_LH_NOR2X6 U6049 ( .A(n5882), .B(n5887), .Z(n5722) );
HS65_LL_NAND2X7 U6050 ( .A(\u_DataPath/jaddr_i [17]), .B(n8152), .Z(n6349)
);
HS65_LH_NOR2X6 U6051 ( .A(n8090), .B(rst), .Z(
\u_DataPath/immediate_ext_ex_i [2]) );
HS65_LH_NAND2X7 U6052 ( .A(n8566), .B(n8264), .Z(n8446) );
HS65_LH_NAND2X7 U6054 ( .A(n7697), .B(n8055), .Z(n7734) );
HS65_LH_NOR2X6 U6055 ( .A(n8131), .B(rst), .Z(n8621) );
HS65_LH_NOR2X6 U6056 ( .A(n8157), .B(rst), .Z(
\u_DataPath/immediate_ext_ex_i [1]) );
HS65_LH_NOR2X6 U6058 ( .A(opcode_i[5]), .B(n8070), .Z(n7773) );
HS65_LH_NOR2X5 U6059 ( .A(\u_DataPath/dataOut_exe_i [0]), .B(n8177), .Z(
n3113) );
HS65_LH_NOR2X6 U6061 ( .A(n6073), .B(n6078), .Z(n5980) );
HS65_LH_NAND2X7 U6062 ( .A(n8165), .B(n6131), .Z(n6133) );
HS65_LH_NOR2X6 U6063 ( .A(n6019), .B(n6022), .Z(n6011) );
HS65_LH_NAND2X7 U6064 ( .A(n9084), .B(n7643), .Z(n7694) );
HS65_LH_NOR2X6 U6065 ( .A(n8130), .B(rst), .Z(
\u_DataPath/immediate_ext_ex_i [0]) );
HS65_LH_NOR2X6 U6066 ( .A(n5976), .B(n5979), .Z(n5928) );
HS65_LL_NAND2X7 U6067 ( .A(\u_DataPath/jaddr_i [21]), .B(n8164), .Z(n6148)
);
HS65_LH_NAND2X7 U6068 ( .A(n2977), .B(n2976), .Z(n2982) );
HS65_LH_IVX9 U6069 ( .A(n8050), .Z(n8631) );
HS65_LH_NAND2X7 U6071 ( .A(\u_DataPath/jaddr_i [19]), .B(n6326), .Z(n2878)
);
HS65_LH_IVX44 U6072 ( .A(n3125), .Z(addr_to_iram[13]) );
HS65_LH_IVX9 U6073 ( .A(n8062), .Z(n8623) );
HS65_LH_IVX9 U6074 ( .A(n8187), .Z(\u_DataPath/u_idexreg/N31 ) );
HS65_LH_IVX9 U6076 ( .A(n5915), .Z(n5739) );
HS65_LH_NAND2X7 U6077 ( .A(n7105), .B(n7104), .Z(n7110) );
HS65_LH_IVX9 U6078 ( .A(n5812), .Z(n5733) );
HS65_LL_NAND2X2 U6079 ( .A(n3037), .B(n3036), .Z(n3039) );
HS65_LH_NAND2X7 U6080 ( .A(n7116), .B(n9234), .Z(n8236) );
HS65_LL_IVX18 U6081 ( .A(n7758), .Z(addr_to_iram[16]) );
HS65_LH_IVX9 U6082 ( .A(n8186), .Z(\u_DataPath/u_idexreg/N33 ) );
HS65_LH_NOR2X6 U6083 ( .A(n4002), .B(n7718), .Z(n4003) );
HS65_LH_IVX9 U6084 ( .A(n8179), .Z(\u_DataPath/immediate_ext_ex_i [7]) );
HS65_LH_NOR2X6 U6085 ( .A(n4284), .B(n7728), .Z(n5688) );
HS65_LH_IVX9 U6086 ( .A(n8185), .Z(\u_DataPath/immediate_ext_ex_i [9]) );
HS65_LH_IVX9 U6088 ( .A(n8182), .Z(\u_DataPath/immediate_ext_ex_i [10]) );
HS65_LH_IVX9 U6089 ( .A(n5911), .Z(n5738) );
HS65_LH_IVX9 U6090 ( .A(n5903), .Z(n5737) );
HS65_LH_NAND2X7 U6091 ( .A(n7100), .B(n7099), .Z(n7112) );
HS65_LH_NOR2X6 U6092 ( .A(n4283), .B(n5687), .Z(n4285) );
HS65_LH_NOR2X6 U6093 ( .A(n5874), .B(n5879), .Z(n5779) );
HS65_LH_IVX9 U6095 ( .A(n5859), .Z(n5741) );
HS65_LH_NOR2X6 U6096 ( .A(n6061), .B(n6066), .Z(n5936) );
HS65_LH_IVX44 U6098 ( .A(n7742), .Z(addr_to_iram[4]) );
HS65_LH_NOR2X6 U6099 ( .A(n8162), .B(rst), .Z(
\u_DataPath/immediate_ext_ex_i [3]) );
HS65_LH_NOR2X6 U6100 ( .A(n5775), .B(n5778), .Z(n5726) );
HS65_LH_IVX9 U6101 ( .A(n6110), .Z(n5940) );
HS65_LH_NOR2X2 U6102 ( .A(n8170), .B(rst), .Z(
\u_DataPath/regfile_addr_out_towb_i [1]) );
HS65_LH_IVX9 U6103 ( .A(n6106), .Z(n5941) );
HS65_LH_IVX9 U6104 ( .A(n6114), .Z(n5942) );
HS65_LH_NOR2X6 U6105 ( .A(n5786), .B(n5772), .Z(n5757) );
HS65_LH_IVX7 U6107 ( .A(n6082), .Z(n6023) );
HS65_LH_NAND2X7 U6108 ( .A(n5852), .B(n5851), .Z(n5857) );
HS65_LH_IVX9 U6109 ( .A(n6118), .Z(n5943) );
HS65_LH_NOR2X6 U6110 ( .A(n8172), .B(rst), .Z(
\u_DataPath/immediate_ext_ex_i [5]) );
HS65_LH_IVX44 U6111 ( .A(n7753), .Z(addr_to_iram[10]) );
HS65_LH_NOR2X6 U6112 ( .A(n5753), .B(n5756), .Z(n5728) );
HS65_LH_NOR2X5 U6114 ( .A(n8911), .B(n9204), .Z(n5947) );
HS65_LH_IVX9 U6117 ( .A(\u_DataPath/dataOut_exe_i [31]), .Z(n4187) );
HS65_LH_NAND2X4 U6119 ( .A(n9037), .B(n9212), .Z(n5848) );
HS65_LH_OR2X9 U6120 ( .A(n8969), .B(n9216), .Z(n6013) );
HS65_LH_OR2X9 U6123 ( .A(n8911), .B(n9203), .Z(n6053) );
HS65_LH_NAND2X7 U6124 ( .A(n8942), .B(n9222), .Z(n6082) );
HS65_LH_NAND2X7 U6127 ( .A(n9227), .B(n9225), .Z(n7718) );
HS65_LH_NOR2X6 U6128 ( .A(n9347), .B(rst), .Z(n8066) );
HS65_LH_NAND2X4 U6129 ( .A(n9033), .B(n9215), .Z(n5896) );
HS65_LH_IVX9 U6138 ( .A(\u_DataPath/immediate_ext_dec_i [1]), .Z(n8157) );
HS65_LL_OR2X9 U6144 ( .A(\u_DataPath/jaddr_i [22]), .B(
\u_DataPath/jaddr_i [21]), .Z(n6153) );
HS65_LL_NAND2X7 U6146 ( .A(\u_DataPath/jaddr_i [21]), .B(
\u_DataPath/jaddr_i [22]), .Z(n6150) );
HS65_LH_IVX9 U6149 ( .A(\u_DataPath/immediate_ext_dec_i [5]), .Z(n8172) );
HS65_LH_IVX9 U6154 ( .A(\u_DataPath/dataOut_exe_i [22]), .Z(n3170) );
HS65_LL_NAND2X5 U6155 ( .A(\u_DataPath/jaddr_i [16]), .B(
\u_DataPath/jaddr_i [17]), .Z(n6348) );
HS65_LH_IVX7 U6156 ( .A(n9035), .Z(n3284) );
HS65_LH_NOR2X6 U6157 ( .A(\u_DataPath/jaddr_i [23]), .B(
\u_DataPath/jaddr_i [24]), .Z(n6145) );
HS65_LH_IVX9 U6158 ( .A(\u_DataPath/cw_to_ex_i [19]), .Z(n7874) );
HS65_LH_OR2X9 U6159 ( .A(n9004), .B(n9209), .Z(n6105) );
HS65_LH_IVX7 U6160 ( .A(n8944), .Z(n3029) );
HS65_LH_IVX9 U6161 ( .A(\u_DataPath/dataOut_exe_i [2]), .Z(n3296) );
HS65_LH_IVX9 U6162 ( .A(n9206), .Z(n7795) );
HS65_LH_IVX9 U6165 ( .A(n9208), .Z(n7799) );
HS65_LH_IVX9 U6166 ( .A(n8911), .Z(n3031) );
HS65_LH_OR2X9 U6167 ( .A(n8911), .B(n9207), .Z(n6113) );
HS65_LH_IVX9 U6168 ( .A(n9210), .Z(n7797) );
HS65_LH_IVX9 U6169 ( .A(n9216), .Z(n5696) );
HS65_LH_NOR2X5 U6170 ( .A(n8911), .B(n9206), .Z(n5952) );
HS65_LH_IVX9 U6171 ( .A(n9217), .Z(n7713) );
HS65_LH_NAND2X7 U6172 ( .A(n9218), .B(n9220), .Z(n7711) );
HS65_LH_NAND2X7 U6175 ( .A(n9116), .B(n9215), .Z(n7725) );
HS65_LH_NOR2X3 U6176 ( .A(n8913), .B(n9219), .Z(n5839) );
HS65_LH_IVX9 U6177 ( .A(\u_DataPath/immediate_ext_dec_i [3]), .Z(n8162) );
HS65_LH_NOR2X6 U6178 ( .A(n8910), .B(rst), .Z(n8283) );
HS65_LH_IVX9 U6180 ( .A(opcode_i[3]), .Z(n8070) );
HS65_LH_NAND2X7 U6181 ( .A(n8911), .B(n9208), .Z(n5973) );
HS65_LH_NAND2X7 U6182 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [12]),
.Z(n8052) );
HS65_LH_NAND2X7 U6183 ( .A(n8911), .B(n9207), .Z(n6114) );
HS65_LH_NAND2X7 U6184 ( .A(n8911), .B(n9206), .Z(n5954) );
HS65_LH_NAND2X7 U6185 ( .A(n8685), .B(n8684), .Z(n7644) );
HS65_LH_NAND2X7 U6186 ( .A(n8680), .B(n8678), .Z(n7645) );
HS65_LH_NAND2X7 U6187 ( .A(n9181), .B(n9226), .Z(n5863) );
HS65_LH_NAND2X7 U6188 ( .A(n8911), .B(n9205), .Z(n6118) );
HS65_LH_NOR2X6 U6189 ( .A(\u_DataPath/dataOut_exe_i [0]), .B(
\u_DataPath/dataOut_exe_i [1]), .Z(n3112) );
HS65_LH_NAND2X7 U6191 ( .A(n8911), .B(n9204), .Z(n5949) );
HS65_LH_IVX9 U6192 ( .A(\u_DataPath/dataOut_exe_i [14]), .Z(n3278) );
HS65_LH_NAND2X7 U6193 ( .A(n9343), .B(n9203), .Z(n5853) );
HS65_LH_NAND2X7 U6194 ( .A(n8681), .B(n8679), .Z(n7652) );
HS65_LH_NAND2X7 U6195 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [13]),
.Z(n8064) );
HS65_LH_NAND2X7 U6197 ( .A(n9145), .B(n9224), .Z(n5755) );
HS65_LH_NAND2X7 U6198 ( .A(n8911), .B(n9203), .Z(n6054) );
HS65_LH_NAND2X7 U6200 ( .A(n9342), .B(n9204), .Z(n5859) );
HS65_LH_IVX9 U6201 ( .A(n9235), .Z(n2977) );
HS65_LH_IVX9 U6204 ( .A(n9082), .Z(n7643) );
HS65_LH_NAND2X7 U6206 ( .A(n9343), .B(n9205), .Z(n5745) );
HS65_LH_NAND2X7 U6207 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [14]),
.Z(n8062) );
HS65_LHS_XNOR2X3 U6209 ( .A(\u_DataPath/jaddr_i [24]), .B(n9077), .Z(n7106)
);
HS65_LH_NAND2X7 U6211 ( .A(n9342), .B(n9222), .Z(n5867) );
HS65_LH_IVX9 U6212 ( .A(opcode_i[1]), .Z(n7697) );
HS65_LH_NAND2X7 U6214 ( .A(n9342), .B(n9206), .Z(n5907) );
HS65_LHS_XNOR2X3 U6216 ( .A(\u_DataPath/jaddr_i [23]), .B(n8967), .Z(n7107)
);
HS65_LH_NAND2X7 U6218 ( .A(n8706), .B(n8708), .Z(n7686) );
HS65_LH_NAND2X7 U6220 ( .A(n9341), .B(n9207), .Z(n5750) );
HS65_LH_NAND2X7 U6221 ( .A(n8705), .B(n8697), .Z(n7658) );
HS65_LHS_XNOR2X3 U6223 ( .A(\u_DataPath/jaddr_i [25]), .B(n8968), .Z(n7105)
);
HS65_LH_NAND2X7 U6224 ( .A(n9341), .B(n9208), .Z(n5915) );
HS65_LH_NAND2X7 U6225 ( .A(n9343), .B(n9220), .Z(n5812) );
HS65_LH_NAND2X7 U6226 ( .A(n9343), .B(n9209), .Z(n5769) );
HS65_LH_NAND2X7 U6227 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [15]),
.Z(n8159) );
HS65_LH_NAND2X7 U6229 ( .A(n9341), .B(n9210), .Z(n5911) );
HS65_LH_IVX9 U6231 ( .A(\u_DataPath/jaddr_i [24]), .Z(n8151) );
HS65_LH_IVX9 U6232 ( .A(\u_DataPath/dataOut_exe_i [9]), .Z(n3225) );
HS65_LH_NAND2X7 U6233 ( .A(n9343), .B(n9213), .Z(n5826) );
HS65_LH_NAND2X7 U6236 ( .A(n9341), .B(n9217), .Z(n5806) );
HS65_LH_IVX9 U6237 ( .A(n8932), .Z(n7115) );
HS65_LH_NOR2X6 U6238 ( .A(\u_DataPath/cw_exmem_i [6]), .B(
\u_DataPath/cw_exmem_i [4]), .Z(n7098) );
HS65_LH_NAND2X7 U6240 ( .A(n9343), .B(n9216), .Z(n5903) );
HS65_LH_IVX9 U6241 ( .A(n9084), .Z(n8055) );
HS65_LH_NOR2X5 U6242 ( .A(n9075), .B(n8960), .Z(n2941) );
HS65_LL_IVX4 U6243 ( .A(n9075), .Z(n2942) );
HS65_LH_NAND2X7 U6244 ( .A(n9004), .B(n9209), .Z(n6106) );
HS65_LH_IVX7 U6245 ( .A(\u_DataPath/from_mem_data_out_i [5]), .Z(n3331) );
HS65_LH_NAND2X7 U6248 ( .A(n8944), .B(n9213), .Z(n6110) );
HS65_LH_NAND2X7 U6250 ( .A(n8943), .B(n9210), .Z(n6028) );
HS65_LL_IVX7 U6251 ( .A(n8960), .Z(n8139) );
HS65_LH_IVX9 U6253 ( .A(n9068), .Z(n7695) );
HS65_LH_NAND2X7 U6254 ( .A(n9267), .B(n9228), .Z(n5788) );
HS65_LH_NAND2X7 U6255 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [11]),
.Z(n8050) );
HS65_LH_IVX9 U6258 ( .A(Data_out_fromRAM[7]), .Z(n8302) );
HS65_LL_AOI21X2 U6259 ( .A(n7852), .B(n7853), .C(n7862), .Z(
\u_DataPath/u_exmemreg/N78 ) );
HS65_LL_NAND3AX6 U6260 ( .A(n5680), .B(\u_DataPath/cw_to_ex_i [19]), .C(
n4834), .Z(n5164) );
HS65_LH_OAI12X3 U6261 ( .A(n9190), .B(n9028), .C(n8340), .Z(
\u_DataPath/dataOut_exe_i [13]) );
HS65_LL_NAND4ABX6 U6263 ( .A(n4791), .B(n4790), .C(n4789), .D(n4788), .Z(
n4792) );
HS65_LL_NAND2X4 U6264 ( .A(n4370), .B(n8469), .Z(n4455) );
HS65_LL_NAND2AX4 U6267 ( .A(n5282), .B(n5281), .Z(n5699) );
HS65_LL_NOR2AX3 U6268 ( .A(n4098), .B(n4097), .Z(n8477) );
HS65_LL_NAND2AX4 U6270 ( .A(n3744), .B(n3743), .Z(n3745) );
HS65_LH_OAI12X3 U6271 ( .A(n9189), .B(n8853), .C(n8290), .Z(
\u_DataPath/dataOut_exe_i [12]) );
HS65_LH_OAI12X3 U6272 ( .A(n9189), .B(n8887), .C(n8413), .Z(
\u_DataPath/dataOut_exe_i [5]) );
HS65_LL_AOI22X1 U6278 ( .A(n8947), .B(n9365), .C(n9187), .D(n9090), .Z(n8267) );
HS65_LH_NAND2X7 U6279 ( .A(n5285), .B(n4423), .Z(n4452) );
HS65_LH_OAI12X3 U6281 ( .A(n9189), .B(n9058), .C(n8435), .Z(
\u_DataPath/dataOut_exe_i [4]) );
HS65_LL_CNIVX3 U6282 ( .A(n8466), .Z(n5680) );
HS65_LH_NAND2X7 U6283 ( .A(n5643), .B(n3809), .Z(n3810) );
HS65_LL_NAND3X2 U6286 ( .A(n5210), .B(n3505), .C(n3495), .Z(n3507) );
HS65_LHS_XNOR2X6 U6287 ( .A(n5265), .B(n5264), .Z(n5266) );
HS65_LHS_XNOR2X6 U6288 ( .A(n3808), .B(n3807), .Z(n3809) );
HS65_LLS_XNOR2X3 U6289 ( .A(n3741), .B(n3740), .Z(n3742) );
HS65_LL_NAND2X4 U6290 ( .A(n3612), .B(n3611), .Z(n3626) );
HS65_LH_CNIVX3 U6291 ( .A(n8467), .Z(n4789) );
HS65_LH_OAI12X3 U6292 ( .A(n3690), .B(n2859), .C(n3689), .Z(n3691) );
HS65_LLS_XOR2X3 U6293 ( .A(n4056), .B(n4055), .Z(n4057) );
HS65_LH_NOR2AX3 U6294 ( .A(n4879), .B(n4931), .Z(n4932) );
HS65_LL_OAI21X2 U6296 ( .A(n3391), .B(n5633), .C(n3390), .Z(n3392) );
HS65_LL_OA112X4 U6299 ( .A(n5152), .B(n4830), .C(n4831), .D(n2926), .Z(n7848) );
HS65_LL_OAI21X3 U6300 ( .A(n4420), .B(n5633), .C(n4419), .Z(n4421) );
HS65_LL_NAND2X2 U6301 ( .A(n3563), .B(n3562), .Z(n3564) );
HS65_LL_NAND3X2 U6302 ( .A(n5115), .B(n5114), .C(n5113), .Z(n5116) );
HS65_LH_OAI21X3 U6303 ( .A(n3753), .B(n5633), .C(n3752), .Z(n3754) );
HS65_LL_OAI21X3 U6304 ( .A(n5530), .B(n5633), .C(n2892), .Z(n3516) );
HS65_LH_NAND2X7 U6305 ( .A(n4882), .B(n4881), .Z(n4883) );
HS65_LL_OA12X18 U6306 ( .A(n2929), .B(n3815), .C(n2895), .Z(n5633) );
HS65_LL_AOI12X2 U6307 ( .A(n4309), .B(n5195), .C(n4308), .Z(n4310) );
HS65_LH_IVX7 U6308 ( .A(n5195), .Z(n5196) );
HS65_LL_NAND2X2 U6309 ( .A(n5483), .B(n5482), .Z(n5490) );
HS65_LH_NOR3X4 U6312 ( .A(n3592), .B(n3591), .C(n3590), .Z(n3612) );
HS65_LH_NOR2X5 U6313 ( .A(n4088), .B(n4087), .Z(n4089) );
HS65_LH_NAND2X4 U6314 ( .A(n4845), .B(n3617), .Z(n3563) );
HS65_LH_NOR3X4 U6315 ( .A(n4403), .B(n4402), .C(n4401), .Z(n4404) );
HS65_LH_AOI21X2 U6316 ( .A(n6123), .B(n6122), .C(n6121), .Z(n8437) );
HS65_LH_NOR2AX3 U6320 ( .A(n4235), .B(n4234), .Z(n4236) );
HS65_LL_NOR2X2 U6321 ( .A(n5060), .B(n5059), .Z(n5070) );
HS65_LH_OAI21X3 U6322 ( .A(n4119), .B(n4855), .C(n3523), .Z(n3542) );
HS65_LL_NOR3X1 U6323 ( .A(n3883), .B(n3882), .C(n3881), .Z(n3884) );
HS65_LL_NOR2X2 U6324 ( .A(n5481), .B(n5480), .Z(n5483) );
HS65_LH_OAI21X3 U6325 ( .A(n5226), .B(n4855), .C(n3914), .Z(n3929) );
HS65_LH_OAI12X3 U6326 ( .A(n4921), .B(n3815), .C(n4920), .Z(n4922) );
HS65_LH_NOR2AX3 U6328 ( .A(n4086), .B(n4085), .Z(n4087) );
HS65_LL_NAND3X3 U6329 ( .A(n4780), .B(n4779), .C(n4778), .Z(n4781) );
HS65_LH_AOI12X2 U6330 ( .A(n4043), .B(n4879), .C(n4042), .Z(n4044) );
HS65_LH_NOR2X6 U6331 ( .A(n4844), .B(n4843), .Z(n5153) );
HS65_LH_NAND2X2 U6333 ( .A(n5285), .B(n5284), .Z(n5597) );
HS65_LH_OAI21X3 U6334 ( .A(n4744), .B(n5656), .C(n4272), .Z(n4273) );
HS65_LL_NAND3X2 U6336 ( .A(n3678), .B(n3677), .C(n3676), .Z(n3679) );
HS65_LH_NAND2X4 U6340 ( .A(n3618), .B(n4879), .Z(n3493) );
HS65_LL_OA12X4 U6341 ( .A(n3816), .B(n3370), .C(n3369), .Z(n2895) );
HS65_LH_NAND3X3 U6342 ( .A(n4179), .B(n4178), .C(n4177), .Z(n4204) );
HS65_LH_AOI21X2 U6343 ( .A(n5234), .B(n4765), .C(n4354), .Z(n4360) );
HS65_LL_OAI12X2 U6344 ( .A(n5102), .B(n5101), .C(n5100), .Z(n5111) );
HS65_LH_IVX9 U6345 ( .A(n3589), .Z(n4895) );
HS65_LH_OAI12X3 U6346 ( .A(n3462), .B(n5621), .C(n3461), .Z(n3463) );
HS65_LH_NAND2X4 U6348 ( .A(n3426), .B(n4504), .Z(n4607) );
HS65_LH_OAI21X3 U6350 ( .A(n4954), .B(n3962), .C(n3961), .Z(n3978) );
HS65_LH_OAI21X3 U6352 ( .A(n4220), .B(n4319), .C(n4219), .Z(n4221) );
HS65_LH_OAI21X3 U6353 ( .A(n3975), .B(n5656), .C(n3974), .Z(n3976) );
HS65_LH_NAND3AX6 U6357 ( .A(n5664), .B(n5663), .C(n5662), .Z(n5665) );
HS65_LH_NAND2X7 U6358 ( .A(n4149), .B(n4162), .Z(n5614) );
HS65_LH_NOR3X3 U6359 ( .A(n5089), .B(n4458), .C(n4457), .Z(n3845) );
HS65_LL_OAI12X2 U6361 ( .A(n5018), .B(n5017), .C(n5016), .Z(n5019) );
HS65_LH_OAI21X3 U6362 ( .A(n5182), .B(n5226), .C(n3647), .Z(n3681) );
HS65_LH_CNIVX3 U6363 ( .A(n5577), .Z(n5581) );
HS65_LH_OAI21X3 U6364 ( .A(n4954), .B(n4953), .C(n4952), .Z(n4957) );
HS65_LH_OAI21X3 U6365 ( .A(n5177), .B(n4842), .C(n4432), .Z(n4433) );
HS65_LH_NAND2X7 U6369 ( .A(n4051), .B(n4916), .Z(n4052) );
HS65_LH_NAND2X5 U6370 ( .A(n6123), .B(n4381), .Z(n4135) );
HS65_LH_NOR2AX3 U6371 ( .A(n4072), .B(n4071), .Z(n4073) );
HS65_LH_AOI21X2 U6373 ( .A(n4951), .B(n5142), .C(n3859), .Z(n3885) );
HS65_LH_NAND2AX7 U6374 ( .A(n4121), .B(n4384), .Z(n4388) );
HS65_LL_NOR2X2 U6375 ( .A(n3375), .B(n4419), .Z(n3381) );
HS65_LH_IVX9 U6376 ( .A(n8234), .Z(\u_DataPath/branch_target_i [31]) );
HS65_LH_NAND2X7 U6377 ( .A(n3557), .B(n3556), .Z(n4816) );
HS65_LH_OAI12X3 U6378 ( .A(n5200), .B(n4842), .C(n4841), .Z(n4843) );
HS65_LH_NAND3X3 U6379 ( .A(n3917), .B(n3916), .C(n3915), .Z(n3918) );
HS65_LH_NOR3X3 U6380 ( .A(n4581), .B(n5152), .C(n4025), .Z(n4026) );
HS65_LH_OAI21X3 U6381 ( .A(n3584), .B(n3101), .C(n3583), .Z(n3591) );
HS65_LH_CNIVX3 U6382 ( .A(n5486), .Z(n5305) );
HS65_LH_NAND2X4 U6383 ( .A(n5174), .B(n5229), .Z(n3827) );
HS65_LH_IVX9 U6384 ( .A(n4025), .Z(n4504) );
HS65_LH_OAI21X3 U6386 ( .A(n4737), .B(n5656), .C(n4392), .Z(n4402) );
HS65_LH_NOR2X5 U6387 ( .A(n3762), .B(n3599), .Z(n3600) );
HS65_LH_NOR3X1 U6388 ( .A(n5476), .B(n5511), .C(n5475), .Z(n5477) );
HS65_LH_NAND2X4 U6389 ( .A(n4887), .B(n4873), .Z(n4124) );
HS65_LL_NOR3X1 U6390 ( .A(n4777), .B(n4776), .C(n4775), .Z(n4778) );
HS65_LH_AOI22X3 U6391 ( .A(n4887), .B(n4839), .C(n4951), .D(n4835), .Z(n3842) );
HS65_LL_NAND2AX4 U6393 ( .A(n3476), .B(n3475), .Z(n4928) );
HS65_LH_AOI22X3 U6394 ( .A(n5144), .B(n4616), .C(n4887), .D(n4007), .Z(n4008) );
HS65_LH_AOI22X3 U6395 ( .A(n5229), .B(n4176), .C(n5618), .D(n4614), .Z(n4009) );
HS65_LL_AOI22X1 U6396 ( .A(\sub_x_53/A[30] ), .B(n4493), .C(n5672), .D(n4492), .Z(n5704) );
HS65_LH_IVX9 U6397 ( .A(n4420), .Z(n5631) );
HS65_LH_OAI21X3 U6398 ( .A(n5653), .B(n5652), .C(n5651), .Z(n5664) );
HS65_LH_AOI21X2 U6399 ( .A(n5659), .B(n5658), .C(n5657), .Z(n5663) );
HS65_LH_OAI21X3 U6400 ( .A(n4749), .B(n5656), .C(n4461), .Z(n4471) );
HS65_LH_NAND2X4 U6401 ( .A(n4951), .B(n5143), .Z(n4466) );
HS65_LHS_XNOR2X6 U6403 ( .A(n4478), .B(n4632), .Z(n4479) );
HS65_LHS_XOR2X6 U6404 ( .A(n3853), .B(n3815), .Z(n3854) );
HS65_LH_AOI21X2 U6405 ( .A(n3505), .B(n5211), .C(n3504), .Z(n3506) );
HS65_LL_OAI112X1 U6406 ( .A(n4954), .B(n4070), .C(n4069), .D(n4068), .Z(
n4071) );
HS65_LH_AOI21X2 U6407 ( .A(n4491), .B(n4508), .C(n4263), .Z(n4264) );
HS65_LH_OAI21X3 U6408 ( .A(n4740), .B(n5656), .C(n4058), .Z(n4076) );
HS65_LL_IVX4 U6409 ( .A(n3894), .Z(n4916) );
HS65_LH_NAND3X3 U6410 ( .A(n5509), .B(n4705), .C(n4704), .Z(n4706) );
HS65_LL_AOI12X2 U6411 ( .A(n4937), .B(n4887), .C(n2901), .Z(n4555) );
HS65_LH_OAI21X3 U6412 ( .A(n4439), .B(n4700), .C(n4438), .Z(n4440) );
HS65_LH_NOR2X6 U6414 ( .A(n3878), .B(n3877), .Z(n5204) );
HS65_LH_NAND2X5 U6416 ( .A(n5618), .B(n5206), .Z(n4856) );
HS65_LH_OAI12X3 U6417 ( .A(n4499), .B(n4498), .C(n4836), .Z(n4511) );
HS65_LH_IVX9 U6418 ( .A(n4614), .Z(n5226) );
HS65_LH_OAI21X3 U6420 ( .A(n3534), .B(n5656), .C(n3533), .Z(n3541) );
HS65_LL_NOR2X2 U6421 ( .A(n4992), .B(n4977), .Z(n5115) );
HS65_LH_OAI21X3 U6422 ( .A(n4117), .B(n4838), .C(n4079), .Z(n4349) );
HS65_LH_NAND2X4 U6423 ( .A(n4951), .B(n4937), .Z(n3986) );
HS65_LH_NAND2X5 U6424 ( .A(n4836), .B(n4148), .Z(n4162) );
HS65_LH_OAI21X3 U6425 ( .A(n5188), .B(n5656), .C(n5187), .Z(n5189) );
HS65_LH_NAND2X4 U6427 ( .A(n4951), .B(n4950), .Z(n4952) );
HS65_LH_AOI22X3 U6428 ( .A(n5234), .B(n4764), .C(n5144), .D(n4937), .Z(n4151) );
HS65_LL_NAND2X4 U6429 ( .A(n4037), .B(n3480), .Z(n3935) );
HS65_LH_NAND2AX7 U6430 ( .A(n4946), .B(n2898), .Z(n4947) );
HS65_LH_IVX9 U6431 ( .A(n4919), .Z(n3282) );
HS65_LL_NAND3X3 U6432 ( .A(n3985), .B(n3984), .C(n3983), .Z(n4937) );
HS65_LH_NAND2X4 U6433 ( .A(n5659), .B(n4872), .Z(n3583) );
HS65_LH_AOI21X2 U6434 ( .A(n3737), .B(n5607), .C(n3736), .Z(n3738) );
HS65_LH_AND2X4 U6436 ( .A(n2733), .B(\u_DataPath/toPC2_i [30]), .Z(
\u_DataPath/branch_target_i [30]) );
HS65_LL_NAND2X2 U6437 ( .A(n3875), .B(n3876), .Z(n3402) );
HS65_LH_IVX9 U6439 ( .A(n4513), .Z(n5658) );
HS65_LH_NOR2X6 U6440 ( .A(n4255), .B(n4254), .Z(n4955) );
HS65_LL_NAND2AX4 U6441 ( .A(n3458), .B(n3457), .Z(n5174) );
HS65_LH_OAI21X3 U6442 ( .A(n5656), .B(n5141), .C(n5140), .Z(n5149) );
HS65_LL_NAND3X2 U6443 ( .A(n3960), .B(n3959), .C(n3958), .Z(n4560) );
HS65_LH_NAND2X4 U6444 ( .A(n5661), .B(n5617), .Z(n3761) );
HS65_LH_NAND2X4 U6448 ( .A(n4516), .B(n4872), .Z(n4080) );
HS65_LH_NAND2X2 U6449 ( .A(n4887), .B(n4886), .Z(n4888) );
HS65_LH_OAI12X3 U6451 ( .A(n4681), .B(n4680), .C(n4679), .Z(n4689) );
HS65_LH_AOI21X2 U6452 ( .A(n5618), .B(n4393), .C(n3532), .Z(n3533) );
HS65_LH_NAND2X2 U6453 ( .A(n3426), .B(n5660), .Z(n4519) );
HS65_LH_OAI12X3 U6454 ( .A(n4575), .B(n4574), .C(n4573), .Z(n4576) );
HS65_LH_AOI21X2 U6455 ( .A(n4017), .B(n4016), .C(n5466), .Z(n4018) );
HS65_LH_NAND2X4 U6456 ( .A(n5144), .B(n5142), .Z(n4467) );
HS65_LH_AND2X4 U6457 ( .A(n5234), .B(n3451), .Z(n3452) );
HS65_LL_AO12X4 U6461 ( .A(n5274), .B(n3374), .C(n3373), .Z(n5630) );
HS65_LH_AOI21X2 U6462 ( .A(n5582), .B(n5580), .C(n5013), .Z(n5017) );
HS65_LL_NOR2AX3 U6463 ( .A(n3921), .B(n3671), .Z(n4609) );
HS65_LH_IVX9 U6464 ( .A(n8238), .Z(\u_DataPath/branch_target_i [29]) );
HS65_LH_NAND2X5 U6465 ( .A(n3426), .B(n4120), .Z(n4384) );
HS65_LL_OAI12X2 U6466 ( .A(n5081), .B(n5011), .C(n5010), .Z(n5020) );
HS65_LH_AOI22X3 U6467 ( .A(n5131), .B(n5142), .C(n4942), .D(n3872), .Z(n3843) );
HS65_LH_OAI12X3 U6468 ( .A(n3969), .B(n3757), .C(n5672), .Z(n3799) );
HS65_LH_IVX4 U6469 ( .A(n3876), .Z(n3877) );
HS65_LH_NAND2X4 U6470 ( .A(n5443), .B(n3630), .Z(n3638) );
HS65_LL_IVX2 U6471 ( .A(n4014), .Z(n3246) );
HS65_LH_NAND3X2 U6472 ( .A(n4852), .B(n4851), .C(n5178), .Z(n4853) );
HS65_LH_NAND2AX7 U6473 ( .A(n3520), .B(n3519), .Z(n4872) );
HS65_LH_OAI21X2 U6475 ( .A(n2873), .B(n5179), .C(n5178), .Z(n4527) );
HS65_LL_NOR2X2 U6476 ( .A(n3483), .B(n4629), .Z(n3484) );
HS65_LL_NOR2X3 U6477 ( .A(n3863), .B(n3862), .Z(n4435) );
HS65_LL_NAND2X4 U6478 ( .A(n3586), .B(n3585), .Z(n4120) );
HS65_LH_AOI21X2 U6479 ( .A(n5275), .B(n5274), .C(n5273), .Z(n5276) );
HS65_LL_NOR2X2 U6481 ( .A(n4257), .B(n4256), .Z(n4953) );
HS65_LH_OAI12X3 U6482 ( .A(n4015), .B(n4011), .C(n4013), .Z(n3364) );
HS65_LL_NAND3X3 U6483 ( .A(n4591), .B(n3674), .C(n3673), .Z(n4176) );
HS65_LL_NAND2X4 U6484 ( .A(n5304), .B(n3893), .Z(n5522) );
HS65_LH_NAND3X3 U6485 ( .A(n3531), .B(n5178), .C(n3530), .Z(n3532) );
HS65_LL_NOR3X1 U6486 ( .A(n3434), .B(n3982), .C(n3433), .Z(n5172) );
HS65_LH_NAND2X7 U6487 ( .A(n5009), .B(n5507), .Z(n5081) );
HS65_LH_NAND2X4 U6488 ( .A(n5270), .B(n5467), .Z(n5082) );
HS65_LL_NOR2X2 U6489 ( .A(n4524), .B(n3834), .Z(n3835) );
HS65_LH_OAI12X3 U6491 ( .A(n4725), .B(n4795), .C(n3759), .Z(n4254) );
HS65_LH_NAND3X3 U6492 ( .A(n3972), .B(n3971), .C(n3970), .Z(n3973) );
HS65_LH_OAI21X3 U6494 ( .A(n4197), .B(n4196), .C(n4195), .Z(n4198) );
HS65_LH_OAI21X3 U6495 ( .A(n4798), .B(n4797), .C(n5131), .Z(n4799) );
HS65_LH_IVX4 U6497 ( .A(n3841), .Z(n3781) );
HS65_LH_NAND2X5 U6498 ( .A(n5434), .B(n4408), .Z(n4413) );
HS65_LH_NAND2X5 U6499 ( .A(n3474), .B(n3359), .Z(n4015) );
HS65_LH_AOI21X6 U6500 ( .A(\sub_x_53/A[2] ), .B(n2864), .C(n4798), .Z(n3519)
);
HS65_LH_NAND2X4 U6502 ( .A(n4143), .B(n4099), .Z(n4104) );
HS65_LL_OAI12X3 U6503 ( .A(n2892), .B(n3515), .C(n5531), .Z(n5274) );
HS65_LH_NAND2X4 U6505 ( .A(n4013), .B(n4012), .Z(n4021) );
HS65_LH_NAND2X4 U6508 ( .A(n3733), .B(n3732), .Z(n3741) );
HS65_LL_OAI12X2 U6509 ( .A(n5269), .B(n5272), .C(n5270), .Z(n3373) );
HS65_LH_CBI4I1X5 U6510 ( .A(n4102), .B(n4099), .C(n3354), .D(n3353), .Z(
n3356) );
HS65_LH_OAI211X3 U6511 ( .A(n5652), .B(n4582), .C(n3603), .D(n3602), .Z(
n4356) );
HS65_LH_NAND2X4 U6512 ( .A(n4915), .B(n4914), .Z(n4923) );
HS65_LL_AOI12X3 U6513 ( .A(n3497), .B(n5260), .C(n3496), .Z(n4426) );
HS65_LL_NAND2AX4 U6514 ( .A(n3351), .B(n4638), .Z(n3358) );
HS65_LH_NOR2X6 U6515 ( .A(n3613), .B(n3616), .Z(n3804) );
HS65_LH_NAND2X4 U6516 ( .A(n5605), .B(n5604), .Z(n5613) );
HS65_LH_NAND2X4 U6517 ( .A(n4846), .B(n4845), .Z(n4847) );
HS65_LH_CNIVX3 U6518 ( .A(n4037), .Z(n3992) );
HS65_LH_NAND2X4 U6520 ( .A(n3474), .B(n4544), .Z(n3457) );
HS65_LH_NAND2X2 U6521 ( .A(n4572), .B(n4571), .Z(n4577) );
HS65_LH_OAI12X3 U6522 ( .A(n4581), .B(n4580), .C(n3529), .Z(n4804) );
HS65_LH_AOI21X6 U6523 ( .A(\sub_x_53/A[2] ), .B(n4544), .C(n4541), .Z(n3876)
);
HS65_LH_CNIVX3 U6524 ( .A(n4927), .Z(n3937) );
HS65_LH_NAND2X4 U6525 ( .A(n5275), .B(n5271), .Z(n5277) );
HS65_LH_NAND2X4 U6526 ( .A(n4507), .B(n4516), .Z(n4608) );
HS65_LH_IVX7 U6527 ( .A(n3491), .Z(n3483) );
HS65_LH_NAND2X4 U6528 ( .A(n3833), .B(n3984), .Z(n3770) );
HS65_LH_CNIVX3 U6529 ( .A(n3907), .Z(n3664) );
HS65_LH_IVX9 U6533 ( .A(n3969), .Z(n4134) );
HS65_LH_NOR2X3 U6534 ( .A(n4795), .B(n4660), .Z(n3640) );
HS65_LH_OAI21X3 U6535 ( .A(n4981), .B(n4795), .C(n3603), .Z(n3551) );
HS65_LH_AOI21X2 U6536 ( .A(\sub_x_53/A[17] ), .B(n4588), .C(n3552), .Z(n3554) );
HS65_LL_NOR2X3 U6537 ( .A(n4725), .B(n5422), .Z(n5499) );
HS65_LH_AOI21X2 U6540 ( .A(n5192), .B(n5364), .C(n5500), .Z(n5365) );
HS65_LH_IVX4 U6542 ( .A(n5271), .Z(n4246) );
HS65_LL_NAND2X2 U6544 ( .A(n5516), .B(n5297), .Z(n5334) );
HS65_LL_OAI12X3 U6545 ( .A(n5947), .B(n5950), .C(n5949), .Z(n6055) );
HS65_LH_NAND2X4 U6546 ( .A(n4107), .B(n4106), .Z(n4111) );
HS65_LH_IVX9 U6548 ( .A(n5342), .Z(n5569) );
HS65_LH_NAND2X4 U6549 ( .A(\lte_x_59/B[21] ), .B(n4551), .Z(n3550) );
HS65_LLS_XOR2X3 U6550 ( .A(n5951), .B(n2876), .Z(
\u_DataPath/u_execute/resAdd1_i [29]) );
HS65_LH_NAND2X4 U6552 ( .A(n4700), .B(n4699), .Z(n5356) );
HS65_LH_OAI12X3 U6553 ( .A(n4425), .B(n4371), .C(n4373), .Z(n5606) );
HS65_LH_NAND2X4 U6555 ( .A(n4701), .B(n5418), .Z(n5292) );
HS65_LH_NOR2X3 U6559 ( .A(n5311), .B(n5299), .Z(n5540) );
HS65_LH_NAND2X4 U6561 ( .A(\lte_x_59/B[5] ), .B(n4588), .Z(n3518) );
HS65_LL_NOR2X3 U6562 ( .A(n4622), .B(n4630), .Z(n3491) );
HS65_LH_NOR2X6 U6563 ( .A(n4880), .B(n4876), .Z(n4037) );
HS65_LH_CNIVX3 U6564 ( .A(n5624), .Z(n3713) );
HS65_LH_OAI12X3 U6566 ( .A(n5605), .B(n3731), .C(n3733), .Z(n3498) );
HS65_LH_NAND2X4 U6569 ( .A(\lte_x_59/B[6] ), .B(n4544), .Z(n4462) );
HS65_LH_OAI22X3 U6570 ( .A(n5179), .B(n2865), .C(n2848), .D(n4165), .Z(n4166) );
HS65_LL_NOR2X2 U6571 ( .A(n5310), .B(n5095), .Z(n5552) );
HS65_LH_IVX9 U6573 ( .A(n3575), .Z(n5192) );
HS65_LH_OAI22X3 U6574 ( .A(n4682), .B(n4795), .C(n5129), .D(n5031), .Z(n4131) );
HS65_LH_IVX9 U6575 ( .A(\sub_x_53/A[29] ), .Z(n4725) );
HS65_LH_NAND2X4 U6576 ( .A(n4675), .B(n4674), .Z(n5517) );
HS65_LH_NAND2X4 U6577 ( .A(n4663), .B(n3330), .Z(n4648) );
HS65_LH_NAND2X4 U6578 ( .A(\lte_x_59/B[16] ), .B(n4587), .Z(n3910) );
HS65_LH_NOR2X6 U6579 ( .A(\lte_x_59/B[15] ), .B(n5062), .Z(n3932) );
HS65_LH_IVX9 U6580 ( .A(n4244), .Z(n5275) );
HS65_LH_NAND2X7 U6581 ( .A(\lte_x_59/B[15] ), .B(n5062), .Z(n3934) );
HS65_LH_NOR2X5 U6582 ( .A(n4341), .B(n4939), .Z(n4027) );
HS65_LH_NOR2AX3 U6583 ( .A(n4587), .B(n2848), .Z(n3670) );
HS65_LL_OAI12X2 U6586 ( .A(n4144), .B(n4481), .C(n4143), .Z(n4640) );
HS65_LH_OAI12X3 U6587 ( .A(n4573), .B(n4570), .C(n4572), .Z(n3317) );
HS65_LH_NAND2X4 U6588 ( .A(n4882), .B(n3855), .Z(n3856) );
HS65_LH_CNIVX3 U6589 ( .A(n4081), .Z(n4082) );
HS65_LH_NOR2X6 U6590 ( .A(n4371), .B(n4374), .Z(n5608) );
HS65_LL_NOR2X3 U6592 ( .A(n3515), .B(n5530), .Z(n5271) );
HS65_LH_IVX9 U6593 ( .A(n3814), .Z(n4051) );
HS65_LH_CNIVX3 U6596 ( .A(n5503), .Z(n5504) );
HS65_LL_NOR2X3 U6597 ( .A(n3846), .B(n4081), .Z(n4930) );
HS65_LH_NAND2X2 U6599 ( .A(\lte_x_59/B[15] ), .B(n4588), .Z(n3644) );
HS65_LL_AOI12X3 U6600 ( .A(\sub_x_53/A[27] ), .B(n3385), .C(n5343), .Z(n5582) );
HS65_LH_IVX9 U6601 ( .A(n3560), .Z(n4845) );
HS65_LH_NAND2X4 U6602 ( .A(\lte_x_59/B[14] ), .B(n4587), .Z(n4062) );
HS65_LH_IVX9 U6604 ( .A(n5207), .Z(n5621) );
HS65_LL_NOR2X2 U6606 ( .A(n3698), .B(n5627), .Z(n3379) );
HS65_LH_OAI22X4 U6608 ( .A(n7917), .B(n8449), .C(n7916), .D(n8448), .Z(
\u_DataPath/data_read_ex_1_i [29]) );
HS65_LH_OAI22X4 U6609 ( .A(n7917), .B(n8415), .C(n7916), .D(n8414), .Z(
\u_DataPath/data_read_ex_1_i [5]) );
HS65_LH_OAI22X4 U6610 ( .A(n7917), .B(n8412), .C(n7916), .D(n8411), .Z(
\u_DataPath/data_read_ex_1_i [20]) );
HS65_LH_OAI22X4 U6611 ( .A(n7917), .B(n8457), .C(n7916), .D(n8455), .Z(
\u_DataPath/data_read_ex_1_i [18]) );
HS65_LH_OAI22X4 U6612 ( .A(n7917), .B(n8422), .C(n7916), .D(n8421), .Z(
\u_DataPath/data_read_ex_1_i [31]) );
HS65_LH_OAI22X4 U6613 ( .A(n7917), .B(n8408), .C(n7916), .D(n8407), .Z(
\u_DataPath/data_read_ex_1_i [17]) );
HS65_LH_OAI22X4 U6614 ( .A(n7917), .B(n7932), .C(n7916), .D(n8418), .Z(
\u_DataPath/data_read_ex_1_i [28]) );
HS65_LH_NOR2X6 U6615 ( .A(\lte_x_59/B[18] ), .B(n3371), .Z(n4244) );
HS65_LH_NAND2X4 U6616 ( .A(n5130), .B(n5088), .Z(n5318) );
HS65_LL_NAND2X4 U6617 ( .A(n5249), .B(n3788), .Z(n5624) );
HS65_LL_NOR2AX3 U6621 ( .A(n2848), .B(n4147), .Z(n4630) );
HS65_LH_NAND2X4 U6622 ( .A(n9188), .B(n9093), .Z(n7866) );
HS65_LL_NAND2X4 U6627 ( .A(n4726), .B(n4966), .Z(n5572) );
HS65_LH_NAND2X5 U6629 ( .A(n2849), .B(n5231), .Z(n5256) );
HS65_LH_OAI21X3 U6630 ( .A(n3352), .B(n5179), .C(n4459), .Z(n4460) );
HS65_LH_NAND2X4 U6631 ( .A(n2851), .B(n7627), .Z(n4229) );
HS65_LH_NOR2X6 U6633 ( .A(\lte_x_59/B[21] ), .B(n3377), .Z(n4407) );
HS65_LH_IVX9 U6634 ( .A(n3547), .Z(n4711) );
HS65_LH_NAND2X4 U6635 ( .A(\sub_x_53/A[17] ), .B(n2870), .Z(n5531) );
HS65_LL_AOI12X2 U6639 ( .A(n6117), .B(n6119), .C(n5943), .Z(n5950) );
HS65_LL_NOR2X3 U6640 ( .A(\lte_x_59/B[5] ), .B(n4665), .Z(n4144) );
HS65_LL_NOR2X5 U6641 ( .A(n4863), .B(n4838), .Z(n4887) );
HS65_LH_NOR2X3 U6642 ( .A(n4147), .B(n2848), .Z(n5310) );
HS65_LL_NOR2X3 U6643 ( .A(\lte_x_59/B[14] ), .B(n3366), .Z(n4913) );
HS65_LH_NAND2X5 U6644 ( .A(\sub_x_53/A[23] ), .B(n5417), .Z(n5509) );
HS65_LH_NOR4ABX2 U6645 ( .A(n6995), .B(n6994), .C(n6993), .D(n6992), .Z(
n8338) );
HS65_LH_NOR4ABX2 U6646 ( .A(n7035), .B(n7034), .C(n7033), .D(n7032), .Z(
n8331) );
HS65_LH_NOR4ABX2 U6647 ( .A(n7055), .B(n7054), .C(n7053), .D(n7052), .Z(
n8327) );
HS65_LH_NOR4ABX2 U6648 ( .A(n7075), .B(n7074), .C(n7073), .D(n7072), .Z(
n8344) );
HS65_LH_NOR4ABX2 U6649 ( .A(n7015), .B(n7014), .C(n7013), .D(n7012), .Z(
n8349) );
HS65_LH_NOR4ABX2 U6650 ( .A(n6361), .B(n6360), .C(n6359), .D(n6358), .Z(
n8386) );
HS65_LH_NOR4ABX2 U6651 ( .A(n6766), .B(n6765), .C(n6764), .D(n6763), .Z(
n8322) );
HS65_LL_NOR2X6 U6653 ( .A(n3151), .B(n3150), .Z(\lte_x_59/B[26] ) );
HS65_LH_IVX9 U6655 ( .A(n5567), .Z(n3384) );
HS65_LH_IVX9 U6656 ( .A(n5040), .Z(n4665) );
HS65_LL_NAND2X4 U6660 ( .A(n8383), .B(n3237), .Z(n4969) );
HS65_LHS_XOR2X3 U6665 ( .A(n5956), .B(n5955), .Z(
\u_DataPath/u_execute/resAdd1_i [27]) );
HS65_LL_OAI12X3 U6668 ( .A(n5748), .B(n5751), .C(n5750), .Z(n5908) );
HS65_LH_OAI211X4 U6669 ( .A(n9243), .B(n8880), .C(n8295), .D(n9086), .Z(
\u_DataPath/from_mem_data_out_i [10]) );
HS65_LL_OAI12X2 U6672 ( .A(n8964), .B(n8088), .C(n8829), .Z(
\u_DataPath/cw_to_ex_i [4]) );
HS65_LL_OR2X9 U6674 ( .A(n3100), .B(n3099), .Z(n3101) );
HS65_LH_NAND2X4 U6676 ( .A(n3352), .B(\lte_x_59/B[4] ), .Z(n5387) );
HS65_LH_IVX9 U6677 ( .A(\sub_x_53/A[2] ), .Z(n5130) );
HS65_LH_NAND2X7 U6678 ( .A(\lte_x_59/B[1] ), .B(n4805), .Z(n4824) );
HS65_LH_NOR2X5 U6679 ( .A(\lte_x_59/B[3] ), .B(n5321), .Z(n3488) );
HS65_LL_NOR2X6 U6680 ( .A(n3091), .B(n3090), .Z(\lte_x_59/B[14] ) );
HS65_LH_NOR2X5 U6681 ( .A(n9167), .B(n8104), .Z(\u_DataPath/cw_to_ex_i [19])
);
HS65_LH_IVX7 U6682 ( .A(n5136), .Z(n5123) );
HS65_LH_NAND2X4 U6683 ( .A(n5652), .B(n5654), .Z(n5362) );
HS65_LL_IVX7 U6684 ( .A(\lte_x_59/B[8] ), .Z(n4682) );
HS65_LL_OAI12X3 U6688 ( .A(n8176), .B(n3409), .C(n3408), .Z(n3410) );
HS65_LH_AO22X9 U6689 ( .A(n8820), .B(n9138), .C(n9326), .D(n9153), .Z(
\u_DataPath/jaddr_i [23]) );
HS65_LL_NAND2X5 U6690 ( .A(n4191), .B(n4190), .Z(n7623) );
HS65_LH_IVX9 U6691 ( .A(n5048), .Z(n3365) );
HS65_LH_AO22X9 U6692 ( .A(n8819), .B(n9252), .C(n9327), .D(n9153), .Z(
\u_DataPath/jaddr_i [24]) );
HS65_LL_OAI22X3 U6693 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [19]), .C(
n8323), .D(n3409), .Z(n3186) );
HS65_LL_OAI22X3 U6695 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [18]), .C(
n8387), .D(n3409), .Z(n3085) );
HS65_LH_IVX4 U6696 ( .A(\u_DataPath/u_idexreg/N15 ), .Z(n8072) );
HS65_LL_OAI12X6 U6697 ( .A(n3255), .B(n3254), .C(n3253), .Z(n4674) );
HS65_LHS_XNOR2X3 U6698 ( .A(n7119), .B(n7122), .Z(
\u_DataPath/u_execute/link_value_i [26]) );
HS65_LL_OAI12X3 U6699 ( .A(n8389), .B(n3409), .C(n3089), .Z(n3090) );
HS65_LL_NAND2AX7 U6700 ( .A(n2923), .B(n3281), .Z(n5061) );
HS65_LH_AO22X9 U6702 ( .A(n8818), .B(n9252), .C(n9318), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [15]) );
HS65_LH_IVX9 U6703 ( .A(n4534), .Z(n4431) );
HS65_LL_NAND2AX7 U6709 ( .A(n3169), .B(n3168), .Z(n5652) );
HS65_LH_AO22X9 U6711 ( .A(n8817), .B(n9138), .C(n9324), .D(n9153), .Z(
\u_DataPath/jaddr_i [21]) );
HS65_LH_AO22X9 U6712 ( .A(n8816), .B(n9138), .C(n9323), .D(n9153), .Z(
\u_DataPath/jaddr_i [20]) );
HS65_LL_NOR2X9 U6713 ( .A(n3316), .B(n3315), .Z(n5321) );
HS65_LH_BFX18 U6715 ( .A(n9086), .Z(n7913) );
HS65_LL_NAND2X5 U6716 ( .A(n3180), .B(n3179), .Z(n4699) );
HS65_LH_OAI22X6 U6717 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [20]), .C(
n8385), .D(n3409), .Z(n3176) );
HS65_LH_AOI22X3 U6720 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][8] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][8] ), .D(
n7264), .Z(n6458) );
HS65_LH_AO22X9 U6722 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][4] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][4] ), .Z(n7361)
);
HS65_LH_AOI22X3 U6723 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][20] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][20] ), .D(n7516),
.Z(n7479) );
HS65_LH_AOI22X3 U6724 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][16] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][16] ), .D(
n2889), .Z(n7544) );
HS65_LH_AOI22X3 U6726 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][6] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][6] ), .D(n6942), .Z(n6487) );
HS65_LH_AOI22X3 U6728 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][27] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][27] ), .D(
n2889), .Z(n7458) );
HS65_LH_AOI22X3 U6730 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][6] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][6] ), .D(
n7264), .Z(n6478) );
HS65_LH_AO22X9 U6731 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][6] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][6] ), .D(n7267), .Z(n6475) );
HS65_LH_AOI22X3 U6733 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][8] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][8] ), .D(n6942), .Z(n6467) );
HS65_LH_AOI22X3 U6736 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][24] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][24] ), .D(
n2889), .Z(n7564) );
HS65_LH_AOI22X3 U6737 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][2] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][2] ), .D(
n7264), .Z(n6558) );
HS65_LH_AOI22X3 U6738 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][24] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][24] ), .D(
n2891), .Z(n7561) );
HS65_LH_AOI22X3 U6739 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][2] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][2] ), .D(n6942), .Z(n6567) );
HS65_LH_AOI22X3 U6740 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][2] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][2] ), .D(
n6670), .Z(n6956) );
HS65_LH_AOI22X3 U6742 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][19] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][19] ), .D(
n7264), .Z(n6518) );
HS65_LH_AOI22X3 U6743 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][19] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][19] ), .D(
n6942), .Z(n6527) );
HS65_LH_AO22X9 U6747 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][25] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][25] ), .D(
n7292), .Z(n7155) );
HS65_LH_AOI22X3 U6748 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][25] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][25] ), .D(
n6363), .Z(n7145) );
HS65_LH_AOI22X3 U6750 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][18] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][18] ), .D(n7516),
.Z(n6338) );
HS65_LH_AO22X9 U6751 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][30] ), .B(n7585),
.C(n6957), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][30] ), .Z(n7411)
);
HS65_LH_AO22X9 U6752 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][1] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][1] ), .D(n9372), .Z(n6597) );
HS65_LH_AOI22X3 U6754 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][30] ), .B(n7586),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][30] ), .D(
n7587), .Z(n7414) );
HS65_LH_AOI22X3 U6755 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][1] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][1] ), .D(
n7264), .Z(n6599) );
HS65_LH_AOI22X3 U6756 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][10] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][10] ), .D(
n7264), .Z(n6397) );
HS65_LH_AOI22X3 U6758 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][7] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][7] ), .D(
n7264), .Z(n6438) );
HS65_LH_AOI22X3 U6759 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][7] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][7] ), .D(n6942), .Z(n6447) );
HS65_LH_AOI22X3 U6760 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][0] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][0] ), .D(
n7264), .Z(n6417) );
HS65_LH_AOI22X3 U6761 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][12] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][12] ), .D(
n6942), .Z(n6547) );
HS65_LH_AOI22X3 U6762 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][12] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][12] ), .D(
n7264), .Z(n6538) );
HS65_LH_AOI22X3 U6764 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][1] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][1] ), .D(n6942), .Z(n6609) );
HS65_LH_AOI22X3 U6765 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][26] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][26] ), .D(
n6942), .Z(n6507) );
HS65_LH_AOI22X3 U6766 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][0] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][0] ), .D(n6942), .Z(n6427) );
HS65_LH_BFX18 U6767 ( .A(n8482), .Z(n7918) );
HS65_LH_NAND2X7 U6771 ( .A(n8540), .B(n3178), .Z(n3179) );
HS65_LL_NAND4ABX3 U6772 ( .A(n8558), .B(n4713), .C(n3146), .D(n8560), .Z(
n3147) );
HS65_LH_NOR2X5 U6773 ( .A(rst), .B(n8503), .Z(
\u_DataPath/mem_writedata_out_i [8]) );
HS65_LH_NAND2X5 U6776 ( .A(n7871), .B(n7870), .Z(
\u_DataPath/mem_writedata_out_i [0]) );
HS65_LH_AO22X9 U6780 ( .A(n9254), .B(n8815), .C(n9240), .D(n8984), .Z(
\u_DataPath/pc4_to_idexreg_i [14]) );
HS65_LH_AO22X9 U6781 ( .A(n9254), .B(n8814), .C(n9240), .D(n9097), .Z(
\u_DataPath/pc4_to_idexreg_i [15]) );
HS65_LH_AO22X9 U6782 ( .A(n9254), .B(n8813), .C(n9240), .D(n8979), .Z(
\u_DataPath/pc4_to_idexreg_i [19]) );
HS65_LH_IVX9 U6783 ( .A(n5032), .Z(n3352) );
HS65_LH_AO22X9 U6784 ( .A(n9254), .B(n8812), .C(n9240), .D(n8985), .Z(
\u_DataPath/pc4_to_idexreg_i [20]) );
HS65_LL_IVX4 U6785 ( .A(n5030), .Z(n5312) );
HS65_LL_OAI12X5 U6786 ( .A(n4216), .B(n4215), .C(n4214), .Z(n5422) );
HS65_LH_NOR2X6 U6787 ( .A(n8846), .B(n3341), .Z(n3139) );
HS65_LH_AO22X9 U6788 ( .A(n9254), .B(n8811), .C(n9273), .D(n9240), .Z(
\u_DataPath/pc4_to_idexreg_i [2]) );
HS65_LH_AO22X9 U6789 ( .A(n9254), .B(n8810), .C(n9240), .D(n8970), .Z(
\u_DataPath/pc4_to_idexreg_i [3]) );
HS65_LL_AOI12X4 U6790 ( .A(n3082), .B(n3335), .C(n3334), .Z(\lte_x_59/B[5] )
);
HS65_LH_AO22X9 U6791 ( .A(n9254), .B(n8809), .C(n9240), .D(n8971), .Z(
\u_DataPath/pc4_to_idexreg_i [5]) );
HS65_LH_AO22X9 U6792 ( .A(n9254), .B(n8808), .C(n8688), .D(n9240), .Z(
\u_DataPath/pc4_to_idexreg_i [1]) );
HS65_LH_AO22X9 U6794 ( .A(n9254), .B(n8806), .C(n9240), .D(n9098), .Z(
\u_DataPath/pc4_to_idexreg_i [7]) );
HS65_LH_AO22X9 U6795 ( .A(n9254), .B(n8805), .C(n9240), .D(n9010), .Z(
\u_DataPath/pc4_to_idexreg_i [8]) );
HS65_LL_OAI12X3 U6798 ( .A(n4210), .B(n2909), .C(n4209), .Z(n4966) );
HS65_LH_AO22X9 U6802 ( .A(n9254), .B(n8803), .C(n9240), .D(n8981), .Z(
\u_DataPath/pc4_to_idexreg_i [13]) );
HS65_LH_IVX7 U6803 ( .A(n8053), .Z(n8054) );
HS65_LH_IVX7 U6805 ( .A(n8059), .Z(\u_DataPath/cw_exmem_i [9]) );
HS65_LH_NOR2AX6 U6806 ( .A(n3314), .B(n3414), .Z(n3316) );
HS65_LH_NOR2X6 U6807 ( .A(n8858), .B(n3341), .Z(n3306) );
HS65_LH_NOR2X6 U6808 ( .A(n8836), .B(n3341), .Z(n3061) );
HS65_LL_NAND2X2 U6809 ( .A(n2927), .B(n8552), .Z(n3144) );
HS65_LH_AO22X9 U6810 ( .A(n9254), .B(n8802), .C(n9240), .D(n8980), .Z(
\u_DataPath/pc4_to_idexreg_i [25]) );
HS65_LH_NAND2X7 U6811 ( .A(n3276), .B(n8523), .Z(n3277) );
HS65_LH_NOR2X6 U6814 ( .A(n8856), .B(n3403), .Z(n3266) );
HS65_LL_NAND3X2 U6815 ( .A(n3279), .B(n3280), .C(n8520), .Z(n3281) );
HS65_LH_OR2X9 U6816 ( .A(\u_DataPath/data_read_ex_1_i [10]), .B(n3341), .Z(
n3236) );
HS65_LL_NOR2X3 U6817 ( .A(n3338), .B(n7863), .Z(n4657) );
HS65_LH_NAND2AX7 U6818 ( .A(n8839), .B(n3291), .Z(n8548) );
HS65_LH_NAND2AX7 U6820 ( .A(n8866), .B(n2874), .Z(n8545) );
HS65_LL_NAND3X5 U6821 ( .A(n2879), .B(n8576), .C(n8318), .Z(n8401) );
HS65_LL_NAND2X2 U6822 ( .A(n3221), .B(n5692), .Z(n3223) );
HS65_LH_NAND2AX7 U6823 ( .A(\u_DataPath/data_read_ex_2_i [15]), .B(n2874),
.Z(n8523) );
HS65_LL_NAND2AX4 U6824 ( .A(n3301), .B(n3300), .Z(n3302) );
HS65_LH_NAND2AX7 U6825 ( .A(n8843), .B(n3291), .Z(n8532) );
HS65_LL_NOR3X1 U6826 ( .A(n4713), .B(n8538), .C(n8539), .Z(n3178) );
HS65_LH_NAND2AX7 U6827 ( .A(n8720), .B(n2874), .Z(n8540) );
HS65_LL_NOR2X2 U6828 ( .A(n3154), .B(n8555), .Z(n3155) );
HS65_LH_NAND2AX7 U6829 ( .A(n8721), .B(n3291), .Z(n8560) );
HS65_LH_NAND2AX7 U6830 ( .A(n8832), .B(n2874), .Z(n8571) );
HS65_LL_OAI22X3 U6832 ( .A(n3062), .B(n3340), .C(
\u_DataPath/dataOut_exe_i [1]), .D(n3264), .Z(n3063) );
HS65_LH_NAND2AX7 U6833 ( .A(n8718), .B(n3291), .Z(n8526) );
HS65_LH_NAND2AX7 U6834 ( .A(n8837), .B(n3291), .Z(n8529) );
HS65_LL_NAND2X7 U6835 ( .A(n2733), .B(n7902), .Z(n8443) );
HS65_LL_AOI12X2 U6836 ( .A(n3142), .B(n2866), .C(n3141), .Z(n2927) );
HS65_LL_NAND2X4 U6838 ( .A(n8703), .B(n7704), .Z(n7770) );
HS65_LH_NAND2AX7 U6839 ( .A(n8717), .B(n2874), .Z(n8543) );
HS65_LL_MUXI21X2 U6841 ( .D0(n8554), .D1(n4715), .S0(n4717), .Z(n3593) );
HS65_LH_NAND2AX7 U6842 ( .A(n8865), .B(n2874), .Z(n8517) );
HS65_LH_AOI22X4 U6843 ( .A(n8383), .B(n2866), .C(n3128), .D(n3291), .Z(n8561) );
HS65_LH_NAND2AX7 U6844 ( .A(n8723), .B(n3291), .Z(n8520) );
HS65_LH_NAND2X5 U6845 ( .A(n9084), .B(n8634), .Z(n8059) );
HS65_LL_NOR2X5 U6846 ( .A(n3313), .B(n3312), .Z(n3414) );
HS65_LL_NOR2X2 U6847 ( .A(n4188), .B(n8570), .Z(n4189) );
HS65_LL_NOR2X2 U6848 ( .A(n3206), .B(n8525), .Z(n3207) );
HS65_LH_NOR2X5 U6849 ( .A(n7673), .B(n7757), .Z(n7674) );
HS65_LH_NOR2AX3 U6852 ( .A(n4714), .B(n5693), .Z(n3221) );
HS65_LH_NAND2X7 U6853 ( .A(n3215), .B(n2896), .Z(n5691) );
HS65_LH_NAND2X4 U6854 ( .A(n4714), .B(n8569), .Z(n2909) );
HS65_LH_NOR2X5 U6855 ( .A(n3123), .B(n7671), .Z(n7672) );
HS65_LH_NOR2X6 U6858 ( .A(n7657), .B(n7757), .Z(n7767) );
HS65_LL_OAI12X12 U6859 ( .A(n3010), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N129 ) );
HS65_LH_NAND2X4 U6861 ( .A(n4714), .B(n8565), .Z(n4215) );
HS65_LL_OAI12X12 U6862 ( .A(n3009), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N92 ) );
HS65_LH_NAND2X4 U6863 ( .A(n9376), .B(n8496), .Z(n3338) );
HS65_LL_OAI12X12 U6864 ( .A(n8147), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N127 ) );
HS65_LH_NOR2X6 U6865 ( .A(n7685), .B(n7757), .Z(n7764) );
HS65_LH_NAND2X7 U6871 ( .A(n3278), .B(n3407), .Z(n3089) );
HS65_LH_NAND2X4 U6872 ( .A(n4714), .B(n8533), .Z(n3194) );
HS65_LL_NAND2X4 U6873 ( .A(n9376), .B(n8486), .Z(n3394) );
HS65_LHS_XNOR2X6 U6874 ( .A(n5869), .B(n5868), .Z(\u_DataPath/toPC2_i [16])
);
HS65_LH_NAND2X4 U6875 ( .A(n7869), .B(n8621), .Z(n7871) );
HS65_LH_NAND2X4 U6876 ( .A(n8235), .B(\u_DataPath/u_fetch/pc1/N3 ), .Z(n8044) );
HS65_LL_NOR2X2 U6877 ( .A(n8488), .B(n9401), .Z(n3301) );
HS65_LH_AND2X4 U6878 ( .A(\u_DataPath/dataOut_exe_i [15]), .B(n3407), .Z(
n3271) );
HS65_LH_NAND2X7 U6879 ( .A(n9376), .B(n8487), .Z(n3298) );
HS65_LH_IVX7 U6880 ( .A(n8280), .Z(\u_DataPath/branch_target_i [4]) );
HS65_LH_IVX7 U6881 ( .A(n8281), .Z(\u_DataPath/branch_target_i [3]) );
HS65_LH_NAND2X4 U6882 ( .A(n9376), .B(n8502), .Z(n3329) );
HS65_LHS_XNOR2X6 U6883 ( .A(n7732), .B(n7731), .Z(
\u_DataPath/u_execute/link_value_i [13]) );
HS65_LHS_XNOR2X6 U6884 ( .A(n7722), .B(n7721), .Z(
\u_DataPath/u_execute/link_value_i [15]) );
HS65_LH_IVX18 U6885 ( .A(n4548), .Z(n5648) );
HS65_LH_AOI12X2 U6887 ( .A(n6069), .B(n6071), .C(n5984), .Z(n5985) );
HS65_LHS_XNOR2X6 U6888 ( .A(n6080), .B(n6079), .Z(
\u_DataPath/u_execute/resAdd1_i [9]) );
HS65_LL_NAND2AX4 U6889 ( .A(n3034), .B(n3033), .Z(n3045) );
HS65_LL_NAND2X7 U6890 ( .A(n2733), .B(n8160), .Z(n8117) );
HS65_LH_AOI12X2 U6891 ( .A(n6002), .B(n6083), .C(n6001), .Z(n6003) );
HS65_LHS_XNOR2X6 U6893 ( .A(n6084), .B(n6083), .Z(
\u_DataPath/u_execute/resAdd1_i [16]) );
HS65_LH_OAI12X3 U6894 ( .A(n5983), .B(n6077), .C(n5982), .Z(n6071) );
HS65_LH_NOR2X5 U6895 ( .A(n5700), .B(n7710), .Z(n5701) );
HS65_LH_IVX9 U6896 ( .A(n7653), .Z(n7749) );
HS65_LH_NOR2X5 U6897 ( .A(n7711), .B(n7710), .Z(n7712) );
HS65_LH_NAND2X5 U6898 ( .A(n3160), .B(n7802), .Z(n8549) );
HS65_LH_OAI12X3 U6899 ( .A(n5964), .B(n6077), .C(n5963), .Z(n5992) );
HS65_LH_NOR2X3 U6900 ( .A(n8847), .B(n7802), .Z(n3337) );
HS65_LL_NAND2X5 U6901 ( .A(n3131), .B(n3217), .Z(n3310) );
HS65_LL_NOR2AX3 U6902 ( .A(n3032), .B(n8262), .Z(n3033) );
HS65_LH_OAI12X3 U6903 ( .A(n6078), .B(n6077), .C(n6076), .Z(n6079) );
HS65_LH_OAI12X3 U6904 ( .A(n5782), .B(n5878), .C(n5781), .Z(n5872) );
HS65_LL_NAND2X5 U6905 ( .A(n3217), .B(n3131), .Z(n2896) );
HS65_LH_OAI12X3 U6906 ( .A(n5879), .B(n5878), .C(n5877), .Z(n5880) );
HS65_LH_NOR2X3 U6909 ( .A(n8092), .B(n7762), .Z(n8075) );
HS65_LL_OAI12X3 U6910 ( .A(n5939), .B(n5999), .C(n5938), .Z(n6111) );
HS65_LH_NAND2X4 U6911 ( .A(n9114), .B(n9369), .Z(n8429) );
HS65_LH_IVX4 U6912 ( .A(n7692), .Z(n7682) );
HS65_LHS_XNOR2X6 U6913 ( .A(n5893), .B(n5892), .Z(\u_DataPath/toPC2_i [4])
);
HS65_LL_NOR4ABX9 U6914 ( .A(n2954), .B(n2953), .C(n2952), .D(n2951), .Z(
n3217) );
HS65_LL_NAND2X4 U6915 ( .A(n3057), .B(n3028), .Z(n2932) );
HS65_LH_NOR2X6 U6917 ( .A(n7834), .B(n3442), .Z(n3431) );
HS65_LHS_XNOR2X6 U6918 ( .A(n2835), .B(n7746), .Z(\u_DataPath/pc_4_i [8]) );
HS65_LH_IVX7 U6919 ( .A(n7684), .Z(n7685) );
HS65_LH_AOI21X6 U6920 ( .A(n5934), .B(n5962), .C(n5933), .Z(n5999) );
HS65_LH_NAND3X5 U6921 ( .A(n7698), .B(n7697), .C(n7777), .Z(n8083) );
HS65_LL_AOI12X2 U6922 ( .A(n6013), .B(n6015), .C(n5937), .Z(n5938) );
HS65_LH_NAND2X5 U6924 ( .A(n7091), .B(n7090), .Z(n7092) );
HS65_LL_NAND2X2 U6925 ( .A(n9111), .B(n3049), .Z(n3051) );
HS65_LH_NOR2X3 U6926 ( .A(n8086), .B(n8098), .Z(n7762) );
HS65_LH_NOR2X5 U6929 ( .A(n7788), .B(n7787), .Z(n7708) );
HS65_LH_NAND2X4 U6930 ( .A(n3395), .B(n5716), .Z(n3398) );
HS65_LL_NOR2X2 U6932 ( .A(n3048), .B(n3054), .Z(n3032) );
HS65_LH_NAND3X3 U6933 ( .A(n3011), .B(n9076), .C(n9078), .Z(n3012) );
HS65_LH_OAI12X3 U6934 ( .A(n5899), .B(n5898), .C(n5897), .Z(n5900) );
HS65_LHS_XOR2X6 U6935 ( .A(n8943), .B(n2846), .Z(n3028) );
HS65_LL_NAND2X4 U6936 ( .A(n2945), .B(n2944), .Z(n2954) );
HS65_LL_NOR2AX3 U6937 ( .A(n2733), .B(n5716), .Z(n7861) );
HS65_LL_NOR2X5 U6938 ( .A(n6348), .B(n6341), .Z(n6680) );
HS65_LH_NOR2X5 U6939 ( .A(n8090), .B(n7700), .Z(n8097) );
HS65_LL_NOR2X5 U6940 ( .A(n6148), .B(n6140), .Z(n6171) );
HS65_LL_NOR2X5 U6941 ( .A(n6350), .B(n6341), .Z(n6754) );
HS65_LH_NOR2X5 U6942 ( .A(n7742), .B(n7741), .Z(n7666) );
HS65_LH_OAI12X3 U6944 ( .A(n6102), .B(n6101), .C(n6100), .Z(n6103) );
HS65_LL_NOR2X5 U6945 ( .A(n6146), .B(n6140), .Z(n6172) );
HS65_LH_NAND2X4 U6946 ( .A(n5769), .B(n5768), .Z(n5771) );
HS65_LH_NOR3X4 U6947 ( .A(n9233), .B(n8236), .C(rst), .Z(n8285) );
HS65_LL_AOI21X2 U6948 ( .A(n5981), .B(n5928), .C(n5927), .Z(n5963) );
HS65_LH_NAND2X4 U6949 ( .A(n5826), .B(n5825), .Z(n5828) );
HS65_LH_NAND2X4 U6950 ( .A(n5750), .B(n5749), .Z(n5752) );
HS65_LH_NAND2X4 U6951 ( .A(n6082), .B(n6081), .Z(n6084) );
HS65_LH_NOR3X4 U6952 ( .A(n9236), .B(n9237), .C(n7638), .Z(n8269) );
HS65_LH_NAND2X4 U6953 ( .A(n5788), .B(n5787), .Z(n5794) );
HS65_LH_NOR2X5 U6954 ( .A(n2975), .B(n7638), .Z(n2978) );
HS65_LH_IVX7 U6955 ( .A(n8115), .Z(n8123) );
HS65_LL_NOR2X3 U6959 ( .A(n6349), .B(n2878), .Z(n6670) );
HS65_LL_NOR2X5 U6960 ( .A(n6150), .B(n6151), .Z(n2888) );
HS65_LH_NAND2X4 U6961 ( .A(n6075), .B(n5875), .Z(n6080) );
HS65_LH_NAND2X4 U6962 ( .A(n5973), .B(n5972), .Z(n5975) );
HS65_LL_NOR2X3 U6965 ( .A(n6350), .B(n6332), .Z(n6740) );
HS65_LH_NAND2X4 U6966 ( .A(n6028), .B(n6027), .Z(n6030) );
HS65_LH_NAND2X4 U6968 ( .A(n6100), .B(n6050), .Z(n6052) );
HS65_LH_NAND2X4 U6969 ( .A(n4717), .B(n9343), .Z(n4214) );
HS65_LH_NAND2X4 U6970 ( .A(n5954), .B(n5953), .Z(n5956) );
HS65_LH_NAND2X4 U6972 ( .A(n4717), .B(n9341), .Z(n4970) );
HS65_LL_NOR2X5 U6973 ( .A(n6348), .B(n6332), .Z(n6747) );
HS65_LH_NAND3X5 U6974 ( .A(n2847), .B(n3008), .C(n7086), .Z(n3009) );
HS65_LH_IVX7 U6976 ( .A(n5965), .Z(n5966) );
HS65_LHS_XNOR2X6 U6977 ( .A(n7669), .B(n7743), .Z(\u_DataPath/pc_4_i [4]) );
HS65_LHS_XNOR2X3 U6978 ( .A(n7726), .B(n7789), .Z(
\u_DataPath/u_execute/link_value_i [4]) );
HS65_LH_NAND2X4 U6979 ( .A(n4713), .B(n9341), .Z(n3204) );
HS65_LH_NAND2X4 U6980 ( .A(n6094), .B(n5890), .Z(n6096) );
HS65_LL_NOR2X5 U6981 ( .A(n6148), .B(n6139), .Z(n2887) );
HS65_LL_NAND2AX4 U6983 ( .A(n3039), .B(n3038), .Z(n3042) );
HS65_LH_MUXI21X2 U6985 ( .D0(n3406), .D1(n9395), .S0(n3404), .Z(n8176) );
HS65_LH_NAND3X5 U6986 ( .A(n9237), .B(n2975), .C(n2973), .Z(n2974) );
HS65_LH_NOR2X6 U6987 ( .A(n3121), .B(n7686), .Z(n7659) );
HS65_LL_NAND2X4 U6989 ( .A(\u_DataPath/jaddr_i [24]), .B(n6126), .Z(n6151)
);
HS65_LH_NOR2X6 U6990 ( .A(\u_DataPath/jaddr_i [24]), .B(n8165), .Z(n6138) );
HS65_LL_OR3X4 U6991 ( .A(n8165), .B(n8151), .C(\u_DataPath/jaddr_i [25]),
.Z(n6147) );
HS65_LH_NOR2X5 U6992 ( .A(n8162), .B(n8074), .Z(n8086) );
HS65_LLS_XNOR2X3 U6993 ( .A(n8944), .B(n8170), .Z(n3040) );
HS65_LL_NAND2X4 U6994 ( .A(\u_DataPath/jaddr_i [25]), .B(n6145), .Z(n6139)
);
HS65_LH_NAND2X4 U6995 ( .A(n6118), .B(n6117), .Z(n6120) );
HS65_LHS_XNOR2X3 U6996 ( .A(n9116), .B(n7706), .Z(
\u_DataPath/u_execute/link_value_i [3]) );
HS65_LH_MUXI21X2 U6997 ( .D0(n2956), .D1(n9394), .S0(n3404), .Z(n8364) );
HS65_LH_NOR2X3 U6998 ( .A(\u_DataPath/immediate_ext_dec_i [3]), .B(n8090),
.Z(n8121) );
HS65_LH_IVX4 U6999 ( .A(n8159), .Z(n8625) );
HS65_LH_NAND3X5 U7000 ( .A(n9082), .B(n9068), .C(n7642), .Z(n7688) );
HS65_LH_NAND2X5 U7001 ( .A(opcode_i[5]), .B(n7695), .Z(n8037) );
HS65_LH_NOR2X3 U7004 ( .A(n8151), .B(rst), .Z(\u_DataPath/rs_ex_i [3]) );
HS65_LH_NAND3X3 U7005 ( .A(n9082), .B(n7696), .C(n7695), .Z(n8041) );
HS65_LH_NOR2X5 U7007 ( .A(\u_DataPath/immediate_ext_dec_i [0]), .B(n8162),
.Z(n8096) );
HS65_LL_MUXI21X2 U7008 ( .D0(n3212), .D1(n9396), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8265) );
HS65_LH_NAND2X4 U7009 ( .A(n6114), .B(n6113), .Z(n6116) );
HS65_LH_IVX4 U7011 ( .A(n5855), .Z(n5718) );
HS65_LH_NAND2X4 U7013 ( .A(n5915), .B(n5914), .Z(n5917) );
HS65_LH_NAND2X4 U7016 ( .A(n5911), .B(n5910), .Z(n5913) );
HS65_LH_NOR2X6 U7017 ( .A(n7834), .B(n5491), .Z(n3421) );
HS65_LH_OAI12X3 U7018 ( .A(n6006), .B(n5987), .C(n5989), .Z(n5965) );
HS65_LL_NAND2X5 U7019 ( .A(n3030), .B(n2946), .Z(n3008) );
HS65_LL_NAND3X2 U7020 ( .A(\u_DataPath/cw_to_ex_i [4]), .B(n5492), .C(n5491),
.Z(n5493) );
HS65_LH_OAI12X3 U7021 ( .A(n6064), .B(n2875), .C(n6063), .Z(n5935) );
HS65_LH_NOR2X5 U7023 ( .A(n5836), .B(n5839), .Z(n5834) );
HS65_LH_NOR2X6 U7024 ( .A(n6085), .B(n6090), .Z(n5924) );
HS65_LL_OAI12X2 U7025 ( .A(n5850), .B(n5846), .C(n5848), .Z(n5844) );
HS65_LH_OAI12X3 U7026 ( .A(n6088), .B(n6085), .C(n6087), .Z(n5923) );
HS65_LH_NAND2X4 U7027 ( .A(n5907), .B(n5906), .Z(n5909) );
HS65_LL_NAND2AX7 U7029 ( .A(n9078), .B(n3030), .Z(n7084) );
HS65_LH_OAI12X3 U7030 ( .A(n6076), .B(n6073), .C(n6075), .Z(n5981) );
HS65_LH_IVX7 U7031 ( .A(n5867), .Z(n5821) );
HS65_LH_NAND2AX7 U7032 ( .A(n8480), .B(n9347), .Z(n8051) );
HS65_LH_NOR2X5 U7033 ( .A(n8942), .B(n9222), .Z(n6022) );
HS65_LH_NOR2X3 U7034 ( .A(\u_DataPath/jaddr_i [23]), .B(
\u_DataPath/jaddr_i [25]), .Z(n6126) );
HS65_LH_MUX21X4 U7035 ( .D0(n8908), .D1(\u_DataPath/from_mem_data_out_i [6]),
.S0(\u_DataPath/cw_towb_i [0]), .Z(n8311) );
HS65_LH_NOR2X3 U7036 ( .A(opcode_i[5]), .B(n9068), .Z(n7735) );
HS65_LH_NOR2X5 U7039 ( .A(\u_DataPath/jaddr_i [18]), .B(
\u_DataPath/jaddr_i [19]), .Z(n6339) );
HS65_LH_NOR2X5 U7040 ( .A(n9342), .B(n9209), .Z(n5767) );
HS65_LH_NOR2X5 U7041 ( .A(n9341), .B(n9213), .Z(n5824) );
HS65_LH_NOR2X3 U7042 ( .A(\u_DataPath/immediate_ext_dec_i [5]), .B(
\u_DataPath/immediate_ext_dec_i [4]), .Z(n8120) );
HS65_LL_NOR2X3 U7043 ( .A(n9341), .B(n9221), .Z(n5817) );
HS65_LH_NOR2X5 U7044 ( .A(n9341), .B(n9222), .Z(n5820) );
HS65_LH_IVX9 U7046 ( .A(n7835), .Z(n7116) );
HS65_LH_NAND2X4 U7047 ( .A(\u_DataPath/immediate_ext_dec_i [5]), .B(
\u_DataPath/immediate_ext_dec_i [4]), .Z(n8074) );
HS65_LH_NOR2X5 U7053 ( .A(n9175), .B(n9227), .Z(n5882) );
HS65_LH_NOR2X3 U7054 ( .A(n9037), .B(n9212), .Z(n6045) );
HS65_LLS_XNOR2X3 U7055 ( .A(n8761), .B(n9004), .Z(n3036) );
HS65_LH_NAND2X7 U7056 ( .A(n9179), .B(n9225), .Z(n6088) );
HS65_LH_NAND2X7 U7057 ( .A(n9175), .B(n9227), .Z(n6087) );
HS65_LLS_XNOR2X3 U7058 ( .A(n8763), .B(n8942), .Z(n2960) );
HS65_LLS_XNOR2X3 U7059 ( .A(n9077), .B(n8761), .Z(n2957) );
HS65_LLS_XNOR2X3 U7060 ( .A(n8764), .B(n8967), .Z(n2963) );
HS65_LH_IVX9 U7061 ( .A(n8762), .Z(n8107) );
HS65_LH_NAND2X7 U7062 ( .A(n9177), .B(n9229), .Z(n6076) );
HS65_LH_NAND2X7 U7064 ( .A(n9171), .B(n9214), .Z(n6070) );
HS65_LL_OAI21X2 U7065 ( .A(\u_DataPath/cw_towb_i [1]), .B(n9075), .C(n9077),
.Z(n2944) );
HS65_LL_IVX7 U7066 ( .A(n9076), .Z(n2946) );
HS65_LH_NAND2X7 U7067 ( .A(n9232), .B(n9214), .Z(n7728) );
HS65_LH_NAND2X7 U7068 ( .A(n9267), .B(n9228), .Z(n5989) );
HS65_LH_NAND2X4 U7070 ( .A(n9342), .B(n9202), .Z(n5852) );
HS65_LH_NOR2X5 U7071 ( .A(n9343), .B(n9203), .Z(n5855) );
HS65_LH_NOR2X5 U7072 ( .A(n9145), .B(n9224), .Z(n5957) );
HS65_LH_NOR2X5 U7073 ( .A(n9343), .B(n9205), .Z(n5743) );
HS65_LH_NOR2X5 U7074 ( .A(n8968), .B(n9217), .Z(n5995) );
HS65_LH_NOR2X6 U7075 ( .A(n8966), .B(n9221), .Z(n6019) );
HS65_LH_OR2X9 U7076 ( .A(n9342), .B(n9206), .Z(n5906) );
HS65_LH_NAND2X7 U7077 ( .A(n8966), .B(n9221), .Z(n6021) );
HS65_LH_NOR2X5 U7078 ( .A(n9179), .B(n9225), .Z(n5887) );
HS65_LH_NAND3X5 U7079 ( .A(opcode_i[3]), .B(opcode_i[5]), .C(n9068), .Z(
n7636) );
HS65_LH_IVX9 U7080 ( .A(n9113), .Z(n2983) );
HS65_LL_NOR2X3 U7081 ( .A(n9237), .B(n8915), .Z(n2976) );
HS65_LL_NAND3AX6 U7083 ( .A(n4833), .B(n4832), .C(n7848), .Z(n5679) );
HS65_LL_NAND3AX3 U7084 ( .A(n5602), .B(n8479), .C(n8458), .Z(n5676) );
HS65_LL_IVX4 U7086 ( .A(n5710), .Z(n5711) );
HS65_LL_NOR2AX3 U7087 ( .A(n5709), .B(n5708), .Z(n7859) );
HS65_LH_OAI12X3 U7088 ( .A(n9190), .B(n8888), .C(n8294), .Z(
\u_DataPath/dataOut_exe_i [10]) );
HS65_LH_NAND2X4 U7089 ( .A(n5285), .B(n5707), .Z(n4370) );
HS65_LL_AO12X4 U7091 ( .A(n5285), .B(n5222), .C(n5221), .Z(n5224) );
HS65_LL_NAND2AX4 U7092 ( .A(n4961), .B(n4960), .Z(n4962) );
HS65_LH_NAND3X3 U7093 ( .A(n5704), .B(n8462), .C(n4537), .Z(n4833) );
HS65_LL_NAND2AX4 U7094 ( .A(n3626), .B(n3625), .Z(n3627) );
HS65_LH_CBI4I1X5 U7095 ( .A(n8883), .B(n9201), .C(n9239), .D(n7836), .Z(
\u_DataPath/dataOut_exe_i [11]) );
HS65_LH_AND2X9 U7096 ( .A(n5285), .B(n7626), .Z(n5598) );
HS65_LHS_XNOR2X6 U7099 ( .A(n2915), .B(n4313), .Z(n5707) );
HS65_LLS_XNOR2X3 U7101 ( .A(n2914), .B(n4300), .Z(n4301) );
HS65_LL_AO12X4 U7102 ( .A(n4367), .B(n5285), .C(n4366), .Z(n4368) );
HS65_LLS_XNOR2X3 U7103 ( .A(n4413), .B(n4412), .Z(n4414) );
HS65_LLS_XNOR2X3 U7105 ( .A(n3580), .B(n3579), .Z(n3628) );
HS65_LL_AO12X4 U7106 ( .A(n5643), .B(n4450), .C(n4449), .Z(n4451) );
HS65_LHS_XNOR2X6 U7107 ( .A(n4935), .B(n4934), .Z(n4936) );
HS65_LL_NOR3X1 U7108 ( .A(n5705), .B(n4536), .C(n6121), .Z(n4537) );
HS65_LH_NOR2AX3 U7110 ( .A(n3799), .B(n3798), .Z(n3811) );
HS65_LL_AND3X4 U7111 ( .A(n4901), .B(n4900), .C(n4899), .Z(n4910) );
HS65_LL_NAND2X2 U7113 ( .A(n5217), .B(n4327), .Z(n4369) );
HS65_LH_NAND2X7 U7115 ( .A(n5643), .B(n3566), .Z(n3567) );
HS65_LLS_XNOR2X3 U7116 ( .A(n4242), .B(n4241), .Z(n7626) );
HS65_LL_NAND2X2 U7117 ( .A(n4448), .B(n4447), .Z(n4449) );
HS65_LL_AND3X4 U7118 ( .A(n5368), .B(n5341), .C(n5340), .Z(n2920) );
HS65_LH_NAND2AX7 U7119 ( .A(n3797), .B(n3796), .Z(n3798) );
HS65_LL_OAI21X3 U7120 ( .A(n4246), .B(n5633), .C(n4245), .Z(n4247) );
HS65_LLS_XNOR2X3 U7122 ( .A(n4379), .B(n4378), .Z(n4380) );
HS65_LLS_XNOR2X3 U7123 ( .A(n2907), .B(n9338), .Z(n3902) );
HS65_LL_NAND2AX4 U7124 ( .A(n5076), .B(n5075), .Z(n5077) );
HS65_LL_OAI12X3 U7125 ( .A(n5277), .B(n5633), .C(n5276), .Z(n5278) );
HS65_LHS_XNOR2X6 U7126 ( .A(n3623), .B(n3622), .Z(n3624) );
HS65_LL_OAI12X3 U7127 ( .A(n5633), .B(n4337), .C(n4336), .Z(n4338) );
HS65_LL_NOR2AX3 U7128 ( .A(n4933), .B(n4932), .Z(n4934) );
HS65_LLS_XNOR2X3 U7129 ( .A(n4226), .B(n4225), .Z(n7622) );
HS65_LH_CBI4I1X5 U7130 ( .A(n8882), .B(n8894), .C(n9189), .D(n8436), .Z(
\u_DataPath/dataOut_exe_i [2]) );
HS65_LH_OAI21X3 U7131 ( .A(n3578), .B(n5633), .C(n3577), .Z(n3579) );
HS65_LL_OAI12X3 U7132 ( .A(n4311), .B(n5633), .C(n4310), .Z(n4312) );
HS65_LH_NAND2AX7 U7133 ( .A(n5593), .B(n5592), .Z(n5594) );
HS65_LL_OAI12X3 U7134 ( .A(n4411), .B(n5633), .C(n4410), .Z(n4412) );
HS65_LL_OAI12X3 U7135 ( .A(n5197), .B(n5633), .C(n5196), .Z(n5198) );
HS65_LL_NAND3AX3 U7136 ( .A(n4172), .B(n4171), .C(n4170), .Z(n4173) );
HS65_LL_NAND2X2 U7137 ( .A(n5339), .B(n5338), .Z(n5340) );
HS65_LL_OAI12X3 U7138 ( .A(n5213), .B(n2859), .C(n5212), .Z(n5214) );
HS65_LL_NAND2X2 U7139 ( .A(n5372), .B(n5371), .Z(n5596) );
HS65_LL_NAND2AX4 U7140 ( .A(n3467), .B(n3466), .Z(n3468) );
HS65_LHS_XNOR2X6 U7142 ( .A(n3943), .B(n3942), .Z(n3944) );
HS65_LHS_XNOR2X6 U7143 ( .A(n3994), .B(n3993), .Z(n3995) );
HS65_LL_AO12X4 U7144 ( .A(n5074), .B(n5073), .C(n5072), .Z(n5075) );
HS65_LL_OAI12X3 U7145 ( .A(n3473), .B(n2859), .C(n4251), .Z(n4252) );
HS65_LL_OAI12X3 U7146 ( .A(n5263), .B(n2859), .C(n5262), .Z(n5264) );
HS65_LL_NOR2AX3 U7147 ( .A(n5591), .B(n5590), .Z(n5592) );
HS65_LL_NAND3X2 U7148 ( .A(n4278), .B(n4277), .C(n4276), .Z(n4279) );
HS65_LLS_XNOR2X3 U7149 ( .A(n4923), .B(n4922), .Z(n4963) );
HS65_LL_NAND2AX4 U7151 ( .A(n5669), .B(n5668), .Z(n5670) );
HS65_LL_NAND3AX3 U7152 ( .A(n3730), .B(n3729), .C(n3728), .Z(n3744) );
HS65_LLS_XNOR2X3 U7153 ( .A(n2906), .B(n3817), .Z(n3852) );
HS65_LL_OAI21X2 U7155 ( .A(n5152), .B(n4473), .C(n4472), .Z(n4474) );
HS65_LL_NOR2AX3 U7156 ( .A(n4388), .B(n5152), .Z(n4122) );
HS65_LL_NAND4X4 U7158 ( .A(n4567), .B(n4566), .C(n4565), .D(n4564), .Z(n4568) );
HS65_LL_AOI21X2 U7159 ( .A(n3751), .B(n5195), .C(n3750), .Z(n3752) );
HS65_LL_NAND2AX4 U7162 ( .A(n4520), .B(n4519), .Z(n4948) );
HS65_LL_NAND2X2 U7163 ( .A(n5589), .B(n5588), .Z(n5590) );
HS65_LL_OR3X4 U7164 ( .A(n4860), .B(n4859), .C(n4858), .Z(n2902) );
HS65_LL_NAND3AX3 U7165 ( .A(n3929), .B(n3928), .C(n3927), .Z(n3930) );
HS65_LH_OAI12X3 U7166 ( .A(n4387), .B(n4386), .C(n5672), .Z(n4406) );
HS65_LL_NAND3X2 U7167 ( .A(n5112), .B(n5111), .C(n5110), .Z(n5113) );
HS65_LL_NAND3X2 U7168 ( .A(n4152), .B(n4151), .C(n4150), .Z(n4172) );
HS65_LL_NAND3AX3 U7169 ( .A(n3787), .B(n3786), .C(n3785), .Z(n3794) );
HS65_LH_AOI21X2 U7170 ( .A(n5624), .B(n5623), .C(n5622), .Z(n5625) );
HS65_LL_AOI22X1 U7171 ( .A(n6123), .B(n5250), .C(n4512), .D(n5248), .Z(n8462) );
HS65_LL_AOI21X2 U7174 ( .A(n4222), .B(n5211), .C(n4221), .Z(n4223) );
HS65_LL_NAND3X2 U7175 ( .A(n5584), .B(n5536), .C(n5535), .Z(n5537) );
HS65_LH_OA12X4 U7176 ( .A(n3894), .B(n3815), .C(n3816), .Z(n3817) );
HS65_LH_NOR4ABX2 U7177 ( .A(n5335), .B(n4017), .C(n5334), .D(n5333), .Z(
n5336) );
HS65_LH_OAI21X3 U7178 ( .A(n3981), .B(n5152), .C(n3980), .Z(n3988) );
HS65_LH_NAND3X3 U7179 ( .A(n3655), .B(n3429), .C(n3428), .Z(n3467) );
HS65_LL_NAND3X2 U7181 ( .A(n4980), .B(n4979), .C(n4978), .Z(n4995) );
HS65_LL_CB4I1X4 U7182 ( .A(n4695), .B(n4694), .C(n4693), .D(n4692), .Z(n4784) );
HS65_LH_OAI21X3 U7184 ( .A(n5646), .B(n4849), .C(n4848), .Z(n4860) );
HS65_LH_AOI21X2 U7185 ( .A(n5207), .B(n5206), .C(n5205), .Z(n5219) );
HS65_LH_AOI21X2 U7186 ( .A(n5659), .B(n5239), .C(n3675), .Z(n3676) );
HS65_LL_NAND4ABX3 U7187 ( .A(n4621), .B(n4620), .C(n4619), .D(n4618), .Z(
n4652) );
HS65_LH_NAND3X3 U7188 ( .A(n3655), .B(n3654), .C(n3653), .Z(n3680) );
HS65_LH_OAI21X3 U7189 ( .A(n4753), .B(n5656), .C(n4135), .Z(n4136) );
HS65_LH_NAND3X3 U7190 ( .A(n4431), .B(n5089), .C(n4430), .Z(n4448) );
HS65_LH_OAI21X3 U7191 ( .A(n4812), .B(n4811), .C(n4810), .Z(n4813) );
HS65_LL_NAND2X2 U7192 ( .A(n4518), .B(n4517), .Z(n4520) );
HS65_LH_OAI21X3 U7193 ( .A(n5177), .B(n5176), .C(n5175), .Z(n5190) );
HS65_LH_NAND2X4 U7195 ( .A(n4309), .B(n5194), .Z(n4311) );
HS65_LL_AOI12X2 U7196 ( .A(n4516), .B(n4515), .C(n4514), .Z(n4518) );
HS65_LLS_XOR2X3 U7198 ( .A(n4104), .B(n4103), .Z(n4141) );
HS65_LL_NAND3X2 U7199 ( .A(n4202), .B(n4201), .C(n4200), .Z(n4203) );
HS65_LL_NAND2X2 U7200 ( .A(n5352), .B(n5351), .Z(n5482) );
HS65_LL_OR2X4 U7201 ( .A(n3894), .B(n3370), .Z(n2929) );
HS65_LH_NOR2AX3 U7203 ( .A(n5058), .B(n5057), .Z(n5059) );
HS65_LL_NAND3X2 U7204 ( .A(n5297), .B(n5109), .C(n5108), .Z(n5526) );
HS65_LLS_XOR2X3 U7205 ( .A(n4146), .B(n4145), .Z(n4174) );
HS65_LH_IVX9 U7206 ( .A(n4918), .Z(n3816) );
HS65_LH_AOI21X2 U7207 ( .A(n4951), .B(n4875), .C(n4874), .Z(n4901) );
HS65_LH_NAND2X4 U7209 ( .A(n4007), .B(n4836), .Z(n4606) );
HS65_LLS_XOR2X3 U7211 ( .A(n4648), .B(n4647), .Z(n4649) );
HS65_LH_AOI21X2 U7212 ( .A(n3778), .B(n5658), .C(n3777), .Z(n3786) );
HS65_LH_AOI21X2 U7213 ( .A(n5234), .B(n4033), .C(n4032), .Z(n4048) );
HS65_LH_AOI21X2 U7214 ( .A(n5131), .B(n4615), .C(n4026), .Z(n2931) );
HS65_LL_NOR2AX6 U7215 ( .A(n3482), .B(n3481), .Z(n3618) );
HS65_LH_AOI21X2 U7216 ( .A(n5144), .B(n4560), .C(n4559), .Z(n4565) );
HS65_LH_CNIVX3 U7219 ( .A(n5174), .Z(n3462) );
HS65_LH_AOI21X2 U7220 ( .A(n4887), .B(n4875), .C(n4809), .Z(n4810) );
HS65_LH_AOI21X2 U7221 ( .A(n5229), .B(n5658), .C(n4547), .Z(n4567) );
HS65_LH_NAND2X4 U7222 ( .A(n3634), .B(n5194), .Z(n3636) );
HS65_LH_IVX9 U7226 ( .A(n5630), .Z(n4419) );
HS65_LH_NAND3X3 U7227 ( .A(n5563), .B(n5574), .C(n5562), .Z(n5577) );
HS65_LH_AOI21X2 U7228 ( .A(n5575), .B(n5574), .C(n5573), .Z(n5576) );
HS65_LH_OAI21X3 U7229 ( .A(n4134), .B(n4795), .C(n4163), .Z(n4381) );
HS65_LH_AOI21X2 U7230 ( .A(n5304), .B(n5303), .C(n5302), .Z(n5486) );
HS65_LH_IVX9 U7231 ( .A(n4955), .Z(n4164) );
HS65_LH_AOI21X2 U7232 ( .A(n4625), .B(n4632), .C(n4627), .Z(n4159) );
HS65_LH_AOI21X2 U7234 ( .A(n4508), .B(n4943), .C(n4261), .Z(n4260) );
HS65_LL_OR2X4 U7235 ( .A(n3485), .B(n3484), .Z(n2924) );
HS65_LL_NAND2AX4 U7236 ( .A(n3246), .B(n3362), .Z(n3894) );
HS65_LH_IVX4 U7237 ( .A(n4558), .Z(n4157) );
HS65_LL_OAI12X2 U7238 ( .A(n5046), .B(n5045), .C(n5044), .Z(n5074) );
HS65_LL_NOR2AX3 U7239 ( .A(n3453), .B(n3452), .Z(n3454) );
HS65_LH_OAI21X3 U7240 ( .A(n4808), .B(n5656), .C(n4807), .Z(n4809) );
HS65_LH_AOI21X2 U7241 ( .A(n3704), .B(n5630), .C(n3703), .Z(n3705) );
HS65_LH_NOR2X5 U7242 ( .A(n4307), .B(n4330), .Z(n4309) );
HS65_LL_NAND2X2 U7246 ( .A(n4996), .B(n5015), .Z(n5018) );
HS65_LH_CNIVX3 U7247 ( .A(n3804), .Z(n3685) );
HS65_LH_AOI21X2 U7248 ( .A(n4424), .B(n5607), .C(n4375), .Z(n4376) );
HS65_LL_OAI112X1 U7249 ( .A(n5554), .B(n5553), .C(n5552), .D(n5551), .Z(
n5555) );
HS65_LH_AOI21X2 U7250 ( .A(n5618), .B(n4892), .C(n4891), .Z(n4893) );
HS65_LH_AOI21X2 U7251 ( .A(n4943), .B(n4528), .C(n4527), .Z(n4529) );
HS65_LH_CNIVX3 U7252 ( .A(n5366), .Z(n5291) );
HS65_LL_NOR2X2 U7253 ( .A(n5646), .B(n5172), .Z(n4434) );
HS65_LL_AOI21X2 U7254 ( .A(n9352), .B(n5567), .C(n5649), .Z(n3774) );
HS65_LH_AOI21X2 U7256 ( .A(n9349), .B(n5654), .C(n5649), .Z(n5651) );
HS65_LH_IVX7 U7257 ( .A(n4872), .Z(n4119) );
HS65_LH_AND2X4 U7258 ( .A(n3893), .B(n3892), .Z(n2907) );
HS65_LL_NOR2AX3 U7259 ( .A(n3652), .B(n3651), .Z(n4025) );
HS65_LH_OAI21X3 U7260 ( .A(n5176), .B(n4800), .C(n4799), .Z(n4815) );
HS65_LH_AOI21X2 U7261 ( .A(n3921), .B(n3920), .C(n5241), .Z(n3925) );
HS65_LL_NOR2AX3 U7262 ( .A(n3912), .B(n3911), .Z(n3913) );
HS65_LH_CNIVX3 U7263 ( .A(n5464), .Z(n5330) );
HS65_LL_OAI12X2 U7264 ( .A(n5441), .B(n5440), .C(n5439), .Z(n5459) );
HS65_LH_CNIVX3 U7265 ( .A(n4886), .Z(n4070) );
HS65_LH_AOI21X2 U7266 ( .A(n5608), .B(n5607), .C(n5606), .Z(n5609) );
HS65_LL_OAI12X2 U7267 ( .A(n5499), .B(n5346), .C(n5286), .Z(n5575) );
HS65_LH_AOI21X2 U7268 ( .A(n5234), .B(n3662), .C(n3661), .Z(n3678) );
HS65_LH_NAND2AX7 U7269 ( .A(n3766), .B(n3765), .Z(n4515) );
HS65_LH_OAI12X3 U7270 ( .A(n4915), .B(n3891), .C(n3893), .Z(n3367) );
HS65_LLS_XOR2X3 U7271 ( .A(n9202), .B(n7800), .Z(
\u_DataPath/u_execute/link_value_i [31]) );
HS65_LL_NAND3X3 U7272 ( .A(n3821), .B(n3781), .C(n3780), .Z(n5644) );
HS65_LH_AND2X4 U7273 ( .A(n5435), .B(n5628), .Z(n2917) );
HS65_LH_NAND2X7 U7274 ( .A(n3499), .B(n5608), .Z(n3501) );
HS65_LL_OAI12X3 U7276 ( .A(n4257), .B(n4256), .C(n3426), .Z(n4262) );
HS65_LH_OAI12X3 U7277 ( .A(n4630), .B(n4629), .C(n4628), .Z(n4631) );
HS65_LH_NAND3X5 U7278 ( .A(n3833), .B(n3832), .C(n3831), .Z(n5142) );
HS65_LL_NAND2AX4 U7279 ( .A(n3528), .B(n3527), .Z(n4393) );
HS65_LH_CNIVX3 U7280 ( .A(n4748), .Z(n3919) );
HS65_LH_NAND2AX4 U7281 ( .A(n3981), .B(n5615), .Z(n3792) );
HS65_LHS_XOR2X6 U7282 ( .A(n5742), .B(n5854), .Z(\u_DataPath/toPC2_i [30])
);
HS65_LL_NOR2AX3 U7283 ( .A(n3197), .B(n4244), .Z(n3374) );
HS65_LL_NAND2X4 U7284 ( .A(n4724), .B(n5423), .Z(n5346) );
HS65_LL_AOI22X1 U7286 ( .A(n8868), .B(n9180), .C(n9368), .D(n8869), .Z(n8395) );
HS65_LL_OAI12X3 U7287 ( .A(n5193), .B(n3572), .C(n3574), .Z(n3750) );
HS65_LH_AOI31X2 U7288 ( .A(n2854), .B(n5567), .C(n5566), .D(n5565), .Z(n5578) );
HS65_LL_NAND3X2 U7289 ( .A(n4061), .B(n3664), .C(n3663), .Z(n5228) );
HS65_LH_OAI12X3 U7290 ( .A(n4038), .B(n4034), .C(n4036), .Z(n3476) );
HS65_LH_AOI21X2 U7292 ( .A(n4587), .B(n2858), .C(n3957), .Z(n3958) );
HS65_LH_AOI21X2 U7293 ( .A(n4975), .B(n4974), .C(n5499), .Z(n4996) );
HS65_LH_NOR2AX3 U7294 ( .A(n3231), .B(n4902), .Z(n4014) );
HS65_LL_NAND2AX4 U7295 ( .A(n3361), .B(n4904), .Z(n4016) );
HS65_LL_NOR2X3 U7297 ( .A(\sub_x_53/A[25] ), .B(n5425), .Z(n3572) );
HS65_LH_AOI21X2 U7298 ( .A(n3426), .B(n4066), .C(n3969), .Z(n4894) );
HS65_LH_NAND2X4 U7299 ( .A(n3700), .B(n3699), .Z(n3708) );
HS65_LH_NAND2X4 U7300 ( .A(n4641), .B(n4142), .Z(n4146) );
HS65_LL_AOI22X1 U7301 ( .A(\sub_x_53/A[25] ), .B(n4551), .C(n2845), .D(
\lte_x_59/B[24] ), .Z(n3602) );
HS65_LL_AOI22X1 U7302 ( .A(n8868), .B(n9266), .C(n9365), .D(n8870), .Z(n8445) );
HS65_LH_NAND2X4 U7303 ( .A(n7631), .B(n5124), .Z(n5157) );
HS65_LL_NOR2X2 U7304 ( .A(n3731), .B(n5603), .Z(n3499) );
HS65_LH_AOI21X2 U7305 ( .A(n9352), .B(n4674), .C(n4067), .Z(n4069) );
HS65_LH_NAND2AX4 U7307 ( .A(n4643), .B(n3330), .Z(n3351) );
HS65_LL_OAI12X3 U7309 ( .A(n4882), .B(n4876), .C(n4878), .Z(n4040) );
HS65_LH_AO22X9 U7310 ( .A(n8905), .B(n9188), .C(n9133), .D(n8998), .Z(
\u_DataPath/jump_address_i [28]) );
HS65_LL_AOI12X2 U7311 ( .A(n4824), .B(n5126), .C(n4596), .Z(n3487) );
HS65_LH_NAND2X4 U7312 ( .A(n5258), .B(n5261), .Z(n4253) );
HS65_LH_AOI31X2 U7313 ( .A(\sub_x_53/A[25] ), .B(n5345), .C(n5344), .D(n5343), .Z(n5349) );
HS65_LH_AND2X4 U7315 ( .A(n4036), .B(n4035), .Z(n4045) );
HS65_LH_AOI31X2 U7316 ( .A(\lte_x_59/B[7] ), .B(n5313), .C(n5312), .D(n5311),
.Z(n5314) );
HS65_LH_OAI21X2 U7317 ( .A(n5435), .B(n3698), .C(n5509), .Z(n5436) );
HS65_LHS_XNOR2X6 U7318 ( .A(n5861), .B(n5860), .Z(\u_DataPath/toPC2_i [29])
);
HS65_LL_NOR2X2 U7319 ( .A(n4968), .B(n5361), .Z(n5009) );
HS65_LH_AOI21X2 U7320 ( .A(n4551), .B(\lte_x_59/B[15] ), .C(n3907), .Z(n3912) );
HS65_LH_OAI21X3 U7321 ( .A(n5318), .B(n5037), .C(n5317), .Z(n5554) );
HS65_LHS_XNOR2X6 U7323 ( .A(n6056), .B(n6055), .Z(
\u_DataPath/u_execute/resAdd1_i [30]) );
HS65_LH_OAI21X2 U7324 ( .A(n5065), .B(n5064), .C(n5063), .Z(n5066) );
HS65_LH_AOI21X2 U7325 ( .A(n4551), .B(\sub_x_53/A[25] ), .C(n3549), .Z(n3585) );
HS65_LH_OAI22X3 U7326 ( .A(n7306), .B(n8337), .C(n7915), .D(n8336), .Z(
\u_DataPath/data_read_ex_1_i [9]) );
HS65_LH_OAI22X3 U7327 ( .A(n7306), .B(n8330), .C(n7915), .D(n8329), .Z(
\u_DataPath/data_read_ex_1_i [25]) );
HS65_LH_OAI22X3 U7328 ( .A(n7306), .B(n8444), .C(n7914), .D(n8173), .Z(
\u_DataPath/data_read_ex_1_i [2]) );
HS65_LH_AND2X4 U7329 ( .A(\lte_x_59/B[9] ), .B(n2864), .Z(n4153) );
HS65_LH_AO22X9 U7330 ( .A(n9255), .B(n9188), .C(n9133), .D(n9013), .Z(
\u_DataPath/jump_address_i [9]) );
HS65_LH_AO222X4 U7331 ( .A(\u_DataPath/pc_4_i [31]), .B(n7896), .C(n7887),
.D(n9165), .E(n7893), .F(n9403), .Z(n8641) );
HS65_LH_OAI22X3 U7334 ( .A(n4981), .B(n5129), .C(n2854), .D(n3756), .Z(n3782) );
HS65_LL_OAI12X3 U7335 ( .A(n4418), .B(n4407), .C(n5434), .Z(n5629) );
HS65_LH_OR2X4 U7336 ( .A(\sub_x_53/A[0] ), .B(n5136), .Z(n5125) );
HS65_LH_NAND3X2 U7337 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(n5531), .C(n5506),
.Z(n5080) );
HS65_LH_NOR2X5 U7338 ( .A(n2858), .B(n5398), .Z(n5399) );
HS65_LL_NOR2X2 U7339 ( .A(n5430), .B(n4244), .Z(n5432) );
HS65_LL_NOR2X3 U7340 ( .A(n5419), .B(n4407), .Z(n5632) );
HS65_LL_OR2X4 U7341 ( .A(n5021), .B(n5022), .Z(n2892) );
HS65_LH_NOR2AX3 U7343 ( .A(n4682), .B(n3360), .Z(n4905) );
HS65_LL_NOR2X3 U7344 ( .A(n2843), .B(n4683), .Z(n5300) );
HS65_LH_NOR2X5 U7345 ( .A(n4676), .B(n5061), .Z(n5083) );
HS65_LH_NAND2X5 U7346 ( .A(n5031), .B(n5030), .Z(n5544) );
HS65_LH_NOR2X3 U7347 ( .A(n5320), .B(n5321), .Z(n5037) );
HS65_LH_NOR2X5 U7348 ( .A(n4811), .B(n4805), .Z(n5548) );
HS65_LH_NOR2X5 U7349 ( .A(n5031), .B(n5030), .Z(n5095) );
HS65_LH_NAND2X5 U7350 ( .A(n3101), .B(n4997), .Z(n5289) );
HS65_LH_NOR2X5 U7351 ( .A(n4711), .B(n4976), .Z(n5347) );
HS65_LL_NOR2X2 U7352 ( .A(n4701), .B(n5418), .Z(n5363) );
HS65_LH_NOR2AX3 U7353 ( .A(n5004), .B(n3372), .Z(n5269) );
HS65_LH_OAI12X3 U7354 ( .A(n4628), .B(n4622), .C(n4624), .Z(n3485) );
HS65_LL_NAND2X4 U7355 ( .A(\sub_x_53/A[0] ), .B(n5136), .Z(n5126) );
HS65_LH_NOR4ABX2 U7357 ( .A(n7406), .B(n7405), .C(n7404), .D(n7403), .Z(
n8433) );
HS65_LH_NOR4ABX2 U7358 ( .A(n7471), .B(n7470), .C(n7469), .D(n7468), .Z(
n8373) );
HS65_LH_NOR4ABX2 U7359 ( .A(n7386), .B(n7385), .C(n7384), .D(n7383), .Z(
n8388) );
HS65_LH_NOR4ABX2 U7360 ( .A(n7451), .B(n7450), .C(n7449), .D(n7448), .Z(
n8155) );
HS65_LH_NOR4ABX2 U7361 ( .A(n7557), .B(n7556), .C(n7555), .D(n7554), .Z(
n8354) );
HS65_LH_NOR4ABX2 U7362 ( .A(n7612), .B(n7611), .C(n7610), .D(n7609), .Z(
n8363) );
HS65_LH_NOR4ABX2 U7363 ( .A(n6204), .B(n6203), .C(n6202), .D(n6201), .Z(
n8366) );
HS65_LH_NOR4ABX2 U7364 ( .A(n6494), .B(n6493), .C(n6492), .D(n6491), .Z(
n8313) );
HS65_LH_NOR4ABX2 U7365 ( .A(n6325), .B(n6324), .C(n6323), .D(n6322), .Z(
n8403) );
HS65_LH_NOR4ABX2 U7366 ( .A(n7366), .B(n7365), .C(n7364), .D(n7363), .Z(
n8392) );
HS65_LH_NOR4ABX2 U7367 ( .A(n7537), .B(n7536), .C(n7535), .D(n7534), .Z(
n8381) );
HS65_LH_NOR4ABX2 U7368 ( .A(n7577), .B(n7576), .C(n7575), .D(n7574), .Z(
n8368) );
HS65_LH_NOR4ABX2 U7369 ( .A(n6975), .B(n6974), .C(n6973), .D(n6972), .Z(
n8442) );
HS65_LH_NOR4ABX2 U7370 ( .A(n6304), .B(n6303), .C(n6302), .D(n6301), .Z(
n8371) );
HS65_LH_NOR4ABX2 U7371 ( .A(n7491), .B(n7490), .C(n7489), .D(n7488), .Z(
n8384) );
HS65_LH_NOR4ABX2 U7372 ( .A(n6161), .B(n6160), .C(n6159), .D(n6158), .Z(
n8396) );
HS65_LH_NOR4ABX2 U7373 ( .A(n6284), .B(n6283), .C(n6282), .D(n6281), .Z(
n8352) );
HS65_LH_NOR4ABX2 U7374 ( .A(n7427), .B(n7426), .C(n7425), .D(n7424), .Z(
n8379) );
HS65_LH_NOR4ABX2 U7375 ( .A(n7511), .B(n7510), .C(n7509), .D(n7508), .Z(
n8382) );
HS65_LH_AO22X9 U7377 ( .A(n8997), .B(n9188), .C(n9133), .D(n9011), .Z(
\u_DataPath/jump_address_i [7]) );
HS65_LH_OR2X4 U7380 ( .A(n2851), .B(n7623), .Z(n4205) );
HS65_LH_AO22X9 U7382 ( .A(n9022), .B(n9188), .C(n9133), .D(n8948), .Z(
\u_DataPath/jump_address_i [14]) );
HS65_LH_NOR2X5 U7383 ( .A(\sub_x_53/A[2] ), .B(n5088), .Z(n4596) );
HS65_LH_AO22X9 U7384 ( .A(n9055), .B(n9188), .C(n9133), .D(n8934), .Z(
\u_DataPath/jump_address_i [24]) );
HS65_LH_AO22X9 U7388 ( .A(n9260), .B(n9188), .C(n9133), .D(n9054), .Z(
\u_DataPath/jump_address_i [26]) );
HS65_LH_AO222X4 U7389 ( .A(n7896), .B(\u_DataPath/pc_4_i [30]), .C(n7893),
.D(\u_DataPath/jump_address_i [30]), .E(n9025), .F(n7887), .Z(n8642)
);
HS65_LH_IVX9 U7390 ( .A(n4550), .Z(n4863) );
HS65_LL_NOR2X3 U7391 ( .A(n4726), .B(n4966), .Z(n5503) );
HS65_LH_IVX9 U7392 ( .A(\lte_x_59/B[4] ), .Z(n4796) );
HS65_LH_AOI21X2 U7400 ( .A(n5648), .B(n4147), .C(n5647), .Z(n4165) );
HS65_LH_IVX9 U7402 ( .A(n4458), .Z(n4949) );
HS65_LL_NOR2AX6 U7403 ( .A(n5088), .B(n3425), .Z(n3426) );
HS65_LH_NOR2X6 U7406 ( .A(n7785), .B(n7784), .Z(n7786) );
HS65_LL_OAI12X3 U7407 ( .A(n5952), .B(n5955), .C(n5954), .Z(n6119) );
HS65_LH_OAI21X3 U7410 ( .A(n9246), .B(n8453), .C(n9086), .Z(
\u_DataPath/from_mem_data_out_i [28]) );
HS65_LL_NOR2X6 U7416 ( .A(n3106), .B(n3105), .Z(\lte_x_59/B[7] ) );
HS65_LH_IVX9 U7417 ( .A(n4699), .Z(n3376) );
HS65_LL_AO12X4 U7418 ( .A(n3274), .B(n3270), .C(n3269), .Z(n2925) );
HS65_LH_IVX9 U7419 ( .A(n4967), .Z(n5417) );
HS65_LH_AO222X4 U7420 ( .A(n7896), .B(\u_DataPath/pc_4_i [24]), .C(n7893),
.D(\u_DataPath/jump_address_i [24]), .E(n8931), .F(n7887), .Z(n8648)
);
HS65_LHS_XOR2X3 U7421 ( .A(n7795), .B(n7794), .Z(
\u_DataPath/u_execute/link_value_i [27]) );
HS65_LH_AO222X4 U7422 ( .A(n7896), .B(\u_DataPath/pc_4_i [29]), .C(n7893),
.D(n9417), .E(n9164), .F(n7887), .Z(n8643) );
HS65_LH_AO222X4 U7423 ( .A(n7895), .B(\u_DataPath/pc_4_i [17]), .C(n7892),
.D(n9406), .E(n8928), .F(n7888), .Z(n8655) );
HS65_LH_IVX9 U7424 ( .A(n5021), .Z(n4985) );
HS65_LH_AO22X9 U7425 ( .A(n9254), .B(n8797), .C(n9240), .D(n8992), .Z(
\u_DataPath/pc4_to_idexreg_i [24]) );
HS65_LH_AO22X9 U7426 ( .A(n9254), .B(n8796), .C(n9132), .D(n8993), .Z(
\u_DataPath/pc4_to_idexreg_i [29]) );
HS65_LH_AO22X9 U7427 ( .A(n9254), .B(n8795), .C(n9240), .D(n8994), .Z(
\u_DataPath/pc4_to_idexreg_i [17]) );
HS65_LL_NAND2AX7 U7428 ( .A(n2922), .B(n3277), .Z(n5062) );
HS65_LH_AOI22X3 U7430 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][18] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][18] ), .Z(n6344)
);
HS65_LH_OAI22X6 U7431 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [21]), .C(
n8364), .D(n3409), .Z(n3060) );
HS65_LL_NAND2X5 U7432 ( .A(n3164), .B(n3163), .Z(n4967) );
HS65_LH_IVX9 U7433 ( .A(n5654), .Z(n2869) );
HS65_LH_NOR2X5 U7434 ( .A(n9399), .B(n3341), .Z(n3066) );
HS65_LH_AO22X9 U7435 ( .A(n8793), .B(n9138), .C(n9331), .D(n9153), .Z(
opcode_i[3]) );
HS65_LH_AO22X9 U7436 ( .A(n8792), .B(n9138), .C(n9329), .D(n9153), .Z(
opcode_i[1]) );
HS65_LH_NAND2X4 U7437 ( .A(n9281), .B(n8399), .Z(n8273) );
HS65_LH_NAND2X4 U7438 ( .A(n9282), .B(n8399), .Z(n8334) );
HS65_LH_AO22X9 U7439 ( .A(n8791), .B(n9252), .C(n9317), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [14]) );
HS65_LH_NAND2X4 U7440 ( .A(n9283), .B(n8399), .Z(n8295) );
HS65_LH_AO22X9 U7441 ( .A(n8790), .B(n9252), .C(n9316), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [13]) );
HS65_LH_NAND2X4 U7442 ( .A(n9284), .B(n8399), .Z(n8346) );
HS65_LH_AO22X9 U7443 ( .A(n8789), .B(n9252), .C(n9315), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [12]) );
HS65_LH_AO22X9 U7444 ( .A(n8788), .B(n9252), .C(n9314), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [11]) );
HS65_LH_NAND2X4 U7446 ( .A(n9286), .B(n8399), .Z(n8341) );
HS65_LH_NAND2X4 U7447 ( .A(n9287), .B(n8399), .Z(n8400) );
HS65_LH_NAND2X4 U7448 ( .A(n9288), .B(n8399), .Z(n8308) );
HS65_LH_AO22X9 U7449 ( .A(n8787), .B(n9252), .C(n9321), .D(n9141), .Z(
\u_DataPath/jaddr_i [18]) );
HS65_LH_BFX9 U7451 ( .A(n8443), .Z(n7901) );
HS65_LHS_XNOR2X6 U7452 ( .A(n7705), .B(n7780), .Z(\u_DataPath/pc_4_i [29])
);
HS65_LH_AO222X4 U7453 ( .A(n7895), .B(\u_DataPath/pc_4_i [22]), .C(n7892),
.D(\u_DataPath/jump_address_i [22]), .E(n8929), .F(n7887), .Z(n8650)
);
HS65_LL_OR2X4 U7455 ( .A(n8800), .B(n3341), .Z(n2903) );
HS65_LH_AO222X4 U7457 ( .A(n7896), .B(\u_DataPath/pc_4_i [28]), .C(n7893),
.D(\u_DataPath/jump_address_i [28]), .E(n8941), .F(n7887), .Z(n8644)
);
HS65_LH_OAI22X6 U7458 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [12]), .C(
n8255), .D(n3409), .Z(n3265) );
HS65_LL_NAND2X5 U7459 ( .A(n3263), .B(n3262), .Z(n5048) );
HS65_LH_AO22X9 U7460 ( .A(n8785), .B(n9138), .C(n9322), .D(n9153), .Z(
\u_DataPath/jaddr_i [19]) );
HS65_LH_AO22X9 U7462 ( .A(n8784), .B(n9253), .C(n9310), .D(n9142), .Z(
\u_DataPath/immediate_ext_dec_i [7]) );
HS65_LH_AO22X9 U7463 ( .A(n8783), .B(n9253), .C(n9311), .D(n9142), .Z(
\u_DataPath/immediate_ext_dec_i [8]) );
HS65_LH_AO22X9 U7465 ( .A(n8781), .B(n9253), .C(n9313), .D(n9142), .Z(
\u_DataPath/immediate_ext_dec_i [10]) );
HS65_LH_AO22X9 U7467 ( .A(n8779), .B(n9252), .C(n9308), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [5]) );
HS65_LH_AO22X9 U7468 ( .A(n8778), .B(n9252), .C(n9309), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [6]) );
HS65_LH_AO222X4 U7469 ( .A(n7895), .B(\u_DataPath/pc_4_i [23]), .C(n7892),
.D(n9414), .E(n9197), .F(n7887), .Z(n8649) );
HS65_LH_NAND2X7 U7470 ( .A(n9207), .B(n7122), .Z(n7794) );
HS65_LH_AO222X4 U7471 ( .A(n7895), .B(\u_DataPath/pc_4_i [21]), .C(n7892),
.D(n9405), .E(n9193), .F(n7887), .Z(n8651) );
HS65_LH_AO222X4 U7472 ( .A(n7895), .B(\u_DataPath/pc_4_i [16]), .C(n7892),
.D(\u_DataPath/jump_address_i [16]), .E(n9194), .F(n7888), .Z(n8656)
);
HS65_LHS_XNOR2X6 U7474 ( .A(n3121), .B(n7687), .Z(\u_DataPath/pc_4_i [24])
);
HS65_LH_AO22X9 U7475 ( .A(n8776), .B(n9252), .C(n9303), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [0]) );
HS65_LH_AO22X9 U7477 ( .A(n8772), .B(n9252), .C(n9306), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [3]) );
HS65_LHS_XOR2X6 U7479 ( .A(n7769), .B(n7768), .Z(\u_DataPath/pc_4_i [21]) );
HS65_LHS_XOR2X3 U7481 ( .A(n5975), .B(n5974), .Z(
\u_DataPath/u_execute/resAdd1_i [25]) );
HS65_LH_OAI21X3 U7482 ( .A(n8494), .B(n8390), .C(n8493), .Z(
\u_DataPath/mem_writedata_out_i [4]) );
HS65_LHS_XOR2X6 U7483 ( .A(n7766), .B(n7765), .Z(\u_DataPath/pc_4_i [23]) );
HS65_LL_AO12X4 U7484 ( .A(n3414), .B(n8491), .C(n3413), .Z(n3425) );
HS65_LL_NAND3AX3 U7485 ( .A(n3162), .B(n3161), .C(n8548), .Z(n3163) );
HS65_LHS_XOR2X6 U7486 ( .A(n7756), .B(n7755), .Z(\u_DataPath/pc_4_i [22]) );
HS65_LHS_XOR2X3 U7487 ( .A(n7799), .B(n7798), .Z(
\u_DataPath/u_execute/link_value_i [25]) );
HS65_LL_OR2X4 U7488 ( .A(n3171), .B(n8544), .Z(n2905) );
HS65_LH_AO222X4 U7489 ( .A(n7896), .B(\u_DataPath/pc_4_i [27]), .C(n7893),
.D(n9416), .E(n9264), .F(n7887), .Z(n8645) );
HS65_LH_BFX9 U7490 ( .A(n8482), .Z(n7920) );
HS65_LH_NOR3X2 U7491 ( .A(n8773), .B(n9099), .C(n8114), .Z(n8129) );
HS65_LH_NOR2X3 U7492 ( .A(n9083), .B(n8916), .Z(\u_DataPath/cw_exmem_i [6])
);
HS65_LHS_XOR2X6 U7493 ( .A(n3122), .B(n7754), .Z(\u_DataPath/pc_4_i [16]) );
HS65_LL_NOR3X1 U7495 ( .A(n8775), .B(n9169), .C(n8114), .Z(n8082) );
HS65_LL_NOR3X1 U7496 ( .A(n8771), .B(n9003), .C(n8114), .Z(n8106) );
HS65_LL_NAND3X3 U7497 ( .A(n4714), .B(n8562), .C(n8561), .Z(n4974) );
HS65_LL_OA31X4 U7498 ( .A(n9401), .B(n3288), .C(n4713), .D(n3287), .Z(n2910)
);
HS65_LL_NAND2AX4 U7499 ( .A(n3194), .B(n8532), .Z(n3196) );
HS65_LL_NAND3AX3 U7501 ( .A(n3228), .B(n3227), .C(n6124), .Z(n3229) );
HS65_LL_OAI22X3 U7502 ( .A(n3333), .B(\u_DataPath/dataOut_exe_i [6]), .C(
n8311), .D(n3340), .Z(n3319) );
HS65_LHS_XNOR2X6 U7503 ( .A(n2831), .B(n7767), .Z(\u_DataPath/pc_4_i [20])
);
HS65_LHS_XNOR2X6 U7504 ( .A(n3123), .B(n7677), .Z(\u_DataPath/pc_4_i [14])
);
HS65_LHS_XNOR2X3 U7505 ( .A(n7121), .B(n7120), .Z(
\u_DataPath/u_execute/link_value_i [24]) );
HS65_LH_NAND2X7 U7506 ( .A(n3292), .B(n3291), .Z(n3397) );
HS65_LHS_XNOR2X6 U7507 ( .A(n6068), .B(n6067), .Z(
\u_DataPath/u_execute/resAdd1_i [19]) );
HS65_LL_OAI22X3 U7508 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [8]), .C(
n8265), .D(n3340), .Z(n3213) );
HS65_LL_OAI12X12 U7509 ( .A(n8141), .B(n8147), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N151 ) );
HS65_LH_NAND2X5 U7510 ( .A(n2896), .B(n3189), .Z(n8534) );
HS65_LHS_XNOR2X6 U7511 ( .A(n9357), .B(n7655), .Z(\u_DataPath/pc_4_i [13])
);
HS65_LL_OAI13X5 U7512 ( .A(n3329), .B(n8501), .C(n8500), .D(n3328), .Z(n5030) );
HS65_LH_AND2X4 U7513 ( .A(n4714), .B(n8521), .Z(n3279) );
HS65_LL_OAI12X18 U7514 ( .A(n8147), .B(n8150), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N135 ) );
HS65_LH_NAND2X4 U7515 ( .A(n8566), .B(n8484), .Z(n7870) );
HS65_LL_OAI12X12 U7516 ( .A(n8145), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N125 ) );
HS65_LL_OAI12X18 U7517 ( .A(n3009), .B(n8150), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N132 ) );
HS65_LH_BFX9 U7518 ( .A(n8456), .Z(n7914) );
HS65_LL_OAI12X18 U7519 ( .A(n3010), .B(n8150), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N137 ) );
HS65_LH_NAND3X3 U7520 ( .A(\u_DataPath/immediate_ext_dec_i [2]), .B(n8120),
.C(n8635), .Z(n8077) );
HS65_LH_AOI12X2 U7521 ( .A(n6057), .B(n6059), .C(n5764), .Z(n5969) );
HS65_LHS_XNOR2X6 U7522 ( .A(n3120), .B(n7674), .Z(\u_DataPath/pc_4_i [25])
);
HS65_LL_NAND2AX4 U7523 ( .A(n7878), .B(n4212), .Z(n4216) );
HS65_LL_NOR3X1 U7525 ( .A(n8542), .B(n4713), .C(n8541), .Z(n3181) );
HS65_LH_BFX9 U7526 ( .A(n8456), .Z(n7916) );
HS65_LH_BFX9 U7527 ( .A(n8456), .Z(n7915) );
HS65_LL_OAI12X12 U7528 ( .A(n3012), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N126 ) );
HS65_LL_NOR4ABX2 U7529 ( .A(n8269), .B(n8318), .C(n9235), .D(n8268), .Z(
n8272) );
HS65_LH_OAI21X3 U7530 ( .A(n8098), .B(n8097), .C(n8635), .Z(n8094) );
HS65_LL_NOR2AX3 U7532 ( .A(n3219), .B(n3218), .Z(n5693) );
HS65_LH_BFX9 U7533 ( .A(n8287), .Z(n7896) );
HS65_LH_BFX9 U7535 ( .A(n8287), .Z(n7894) );
HS65_LL_OAI21X2 U7536 ( .A(n3284), .B(n4714), .C(n3283), .Z(n3289) );
HS65_LH_OAI12X3 U7537 ( .A(n5763), .B(n5773), .C(n5762), .Z(n5864) );
HS65_LL_NAND2X7 U7538 ( .A(n7306), .B(n7095), .Z(n7096) );
HS65_LH_OAI12X3 U7539 ( .A(n6066), .B(n6065), .C(n6064), .Z(n6067) );
HS65_LHS_XOR2X3 U7540 ( .A(n6030), .B(n6029), .Z(
\u_DataPath/u_execute/resAdd1_i [23]) );
HS65_LH_BFX9 U7541 ( .A(n8287), .Z(n7895) );
HS65_LH_AND2X4 U7542 ( .A(n8537), .B(n2866), .Z(n2894) );
HS65_LL_OAI12X3 U7543 ( .A(n6026), .B(n6029), .C(n6028), .Z(n6107) );
HS65_LL_NAND2AX4 U7544 ( .A(n8332), .B(n2866), .Z(n8505) );
HS65_LL_OA12X4 U7545 ( .A(n4713), .B(n3347), .C(n3346), .Z(n3348) );
HS65_LHS_XOR2X3 U7546 ( .A(n3119), .B(n7759), .Z(\u_DataPath/pc_4_i [26]) );
HS65_LH_BFX9 U7547 ( .A(n8483), .Z(n7924) );
HS65_LHS_XOR2X3 U7548 ( .A(n7797), .B(n7796), .Z(
\u_DataPath/u_execute/link_value_i [23]) );
HS65_LH_NOR2X3 U7549 ( .A(n8719), .B(n4712), .Z(n7878) );
HS65_LL_NAND3X3 U7550 ( .A(n8143), .B(n7619), .C(n7618), .Z(n8148) );
HS65_LH_NOR2X5 U7552 ( .A(n8716), .B(n7802), .Z(n3299) );
HS65_LH_IVX9 U7553 ( .A(n7661), .Z(n7757) );
HS65_LL_AOI12X6 U7554 ( .A(n8161), .B(n8160), .C(n8159), .Z(
\u_DataPath/u_idexreg/N184 ) );
HS65_LH_NAND2X4 U7556 ( .A(n8297), .B(n7802), .Z(n8502) );
HS65_LH_NAND2X7 U7557 ( .A(n3110), .B(n8132), .Z(n8573) );
HS65_LH_NAND2X4 U7559 ( .A(n4187), .B(n7802), .Z(n8572) );
HS65_LH_NOR2X5 U7560 ( .A(n8176), .B(n9401), .Z(n8570) );
HS65_LH_AOI12X2 U7561 ( .A(n5814), .B(n5868), .C(n5813), .Z(n5815) );
HS65_LH_NAND2X4 U7562 ( .A(n8681), .B(n7749), .Z(n7750) );
HS65_LH_NOR2X3 U7563 ( .A(n8364), .B(n9401), .Z(n8542) );
HS65_LH_NOR2X3 U7564 ( .A(n8350), .B(n9401), .Z(n8544) );
HS65_LH_AOI12X2 U7565 ( .A(n6005), .B(n5791), .C(n5790), .Z(n5793) );
HS65_LH_NAND2X5 U7566 ( .A(n3225), .B(n7802), .Z(n8506) );
HS65_LH_OR2X4 U7567 ( .A(n8426), .B(n9401), .Z(n4212) );
HS65_LH_AOI12X2 U7569 ( .A(n6069), .B(n5872), .C(n5984), .Z(n5784) );
HS65_LHS_XNOR2X6 U7570 ( .A(n5889), .B(n5888), .Z(\u_DataPath/toPC2_i [7])
);
HS65_LH_NOR2X3 U7571 ( .A(n8374), .B(n9401), .Z(n8559) );
HS65_LH_AOI12X2 U7572 ( .A(n6005), .B(n5992), .C(n5790), .Z(n5993) );
HS65_LH_AOI31X3 U7573 ( .A(n9117), .B(n9334), .C(n8714), .D(n8424), .Z(n7847) );
HS65_LH_OAI12X3 U7574 ( .A(n5887), .B(n5886), .C(n5885), .Z(n5888) );
HS65_LH_IVX9 U7576 ( .A(n8425), .Z(n8132) );
HS65_LL_NAND2X2 U7578 ( .A(n3217), .B(n3216), .Z(n3218) );
HS65_LL_NOR4ABX2 U7579 ( .A(n3053), .B(n3052), .C(n3051), .D(n3034), .Z(
n3055) );
HS65_LL_NAND2X7 U7581 ( .A(n8566), .B(n2877), .Z(n8235) );
HS65_LHS_XOR2X3 U7582 ( .A(n5700), .B(n7710), .Z(n4288) );
HS65_LH_NAND2X4 U7585 ( .A(n9214), .B(n7729), .Z(n4004) );
HS65_LH_BFX9 U7586 ( .A(n7886), .Z(n7887) );
HS65_LH_AOI12X2 U7587 ( .A(n5834), .B(n5892), .C(n5833), .Z(n5886) );
HS65_LH_BFX9 U7588 ( .A(n7886), .Z(n7888) );
HS65_LH_AOI31X2 U7589 ( .A(opcode_i[1]), .B(n9084), .C(n7771), .D(n7309),
.Z(n8119) );
HS65_LH_AOI12X2 U7590 ( .A(n6036), .B(n6095), .C(n6035), .Z(n6089) );
HS65_LH_BFX9 U7592 ( .A(n6683), .Z(n7593) );
HS65_LH_BFX9 U7593 ( .A(n7886), .Z(n7889) );
HS65_LH_BFX9 U7594 ( .A(n6746), .Z(n7516) );
HS65_LH_BFX9 U7595 ( .A(n6172), .Z(n7171) );
HS65_LH_IVX9 U7596 ( .A(n7861), .Z(n8168) );
HS65_LH_BFX9 U7597 ( .A(n6754), .Z(n7525) );
HS65_LH_BFX9 U7600 ( .A(n6635), .Z(n7282) );
HS65_LH_BFX9 U7602 ( .A(n6680), .Z(n7522) );
HS65_LH_BFX9 U7603 ( .A(n6171), .Z(n7285) );
HS65_LH_BFX9 U7607 ( .A(n6739), .Z(n7428) );
HS65_LH_BFX9 U7608 ( .A(n6634), .Z(n7283) );
HS65_LH_BFX9 U7609 ( .A(n8285), .Z(n7886) );
HS65_LL_NOR2X5 U7610 ( .A(n6353), .B(n6333), .Z(n6952) );
HS65_LL_OAI21X2 U7611 ( .A(n5932), .B(n5963), .C(n5931), .Z(n5933) );
HS65_LH_BFX9 U7612 ( .A(n7578), .Z(n7429) );
HS65_LH_BFX9 U7613 ( .A(n6689), .Z(n7603) );
HS65_LHS_XOR2X6 U7614 ( .A(n7745), .B(n7744), .Z(\u_DataPath/pc_4_i [5]) );
HS65_LH_BFX9 U7615 ( .A(n6364), .Z(n6927) );
HS65_LH_OAI211X3 U7617 ( .A(n8089), .B(n7702), .C(n7701), .D(n7700), .Z(
n8125) );
HS65_LH_BFX9 U7618 ( .A(n6745), .Z(n7434) );
HS65_LH_BFX9 U7619 ( .A(n6627), .Z(n7274) );
HS65_LH_BFX9 U7620 ( .A(n7296), .Z(n6942) );
HS65_LH_BFX9 U7621 ( .A(n6625), .Z(n7272) );
HS65_LH_BFX9 U7622 ( .A(n6376), .Z(n7286) );
HS65_LH_IVX9 U7624 ( .A(n7639), .Z(n7640) );
HS65_LH_OAI12X3 U7625 ( .A(n5795), .B(n5800), .C(n5797), .Z(n5807) );
HS65_LL_CB4I1X4 U7626 ( .A(n7834), .B(n5491), .C(n3421), .D(n3422), .Z(n3443) );
HS65_LHS_XOR2X3 U7627 ( .A(\u_DataPath/jaddr_i [16]), .B(n7089), .Z(n7091)
);
HS65_LH_BFX9 U7628 ( .A(n6636), .Z(n7170) );
HS65_LH_BFX9 U7629 ( .A(n6385), .Z(n7297) );
HS65_LH_CBI4I1X5 U7630 ( .A(n9084), .B(n7697), .C(n7688), .D(n8084), .Z(
n7637) );
HS65_LH_IVX4 U7631 ( .A(n5800), .Z(n5801) );
HS65_LH_CNIVX3 U7632 ( .A(n7906), .Z(n7849) );
HS65_LH_BFX9 U7633 ( .A(n6966), .Z(n7333) );
HS65_LHS_XOR2X6 U7634 ( .A(n8163), .B(n7089), .Z(n7077) );
HS65_LH_BFX9 U7635 ( .A(n6967), .Z(n7334) );
HS65_LH_NOR2X2 U7636 ( .A(n9233), .B(n7117), .Z(n7879) );
HS65_LH_BFX9 U7637 ( .A(n6951), .Z(n7415) );
HS65_LH_BFX9 U7638 ( .A(n8282), .Z(n7881) );
HS65_LH_BFX9 U7639 ( .A(n8451), .Z(n7908) );
HS65_LH_NAND2X4 U7640 ( .A(n5863), .B(n6057), .Z(n5865) );
HS65_LH_IVX4 U7641 ( .A(n5780), .Z(n5781) );
HS65_LH_NAND2X4 U7642 ( .A(n6058), .B(n6057), .Z(n6060) );
HS65_LL_NOR2X5 U7643 ( .A(n6148), .B(n6133), .Z(n6629) );
HS65_LH_NAND2X4 U7645 ( .A(n6064), .B(n6009), .Z(n6012) );
HS65_LH_NAND2X4 U7646 ( .A(n6040), .B(n5837), .Z(n6044) );
HS65_LLS_XNOR2X3 U7647 ( .A(n7618), .B(n3031), .Z(n3054) );
HS65_LH_NAND2X4 U7648 ( .A(n5876), .B(n5875), .Z(n5881) );
HS65_LH_NAND2X4 U7649 ( .A(n8685), .B(n7743), .Z(n7744) );
HS65_LH_BFX9 U7650 ( .A(n7890), .Z(n7891) );
HS65_LH_BFX9 U7652 ( .A(n7890), .Z(n7893) );
HS65_LH_NAND2X4 U7653 ( .A(n5896), .B(n6098), .Z(n5901) );
HS65_LH_NAND2X4 U7654 ( .A(n5848), .B(n6046), .Z(n5849) );
HS65_LL_NOR2X5 U7655 ( .A(n6153), .B(n6133), .Z(n6370) );
HS65_LHS_XNOR2X6 U7656 ( .A(n8166), .B(n7618), .Z(n7079) );
HS65_LH_NAND2X4 U7657 ( .A(n5897), .B(n6050), .Z(n5845) );
HS65_LH_NAND2X4 U7658 ( .A(n5789), .B(n6005), .Z(n5774) );
HS65_LL_NOR2X5 U7659 ( .A(n2885), .B(n6133), .Z(n6371) );
HS65_LH_NAND2X4 U7661 ( .A(n6070), .B(n6069), .Z(n6072) );
HS65_LL_NOR2X5 U7662 ( .A(n2886), .B(n6132), .Z(n6627) );
HS65_LH_IVX7 U7664 ( .A(n5121), .Z(n4787) );
HS65_LH_CNIVX3 U7665 ( .A(n8350), .Z(n3167) );
HS65_LH_NAND2X4 U7666 ( .A(n5871), .B(n6069), .Z(n5873) );
HS65_LH_OR2X9 U7667 ( .A(n3345), .B(n4713), .Z(n3349) );
HS65_LL_NOR2X5 U7668 ( .A(n2885), .B(n6151), .Z(n6364) );
HS65_LH_AND2X4 U7669 ( .A(n3327), .B(n9183), .Z(n2921) );
HS65_LL_NAND2AX4 U7670 ( .A(n7619), .B(n2943), .Z(n2945) );
HS65_LH_CNIVX3 U7671 ( .A(n8550), .Z(n3142) );
HS65_LH_NAND2X4 U7672 ( .A(n5978), .B(n5977), .Z(n5986) );
HS65_LH_NAND2X4 U7673 ( .A(n5797), .B(n5796), .Z(n5804) );
HS65_LH_NAND2X4 U7674 ( .A(n5997), .B(n5996), .Z(n6004) );
HS65_LH_NAND2X4 U7678 ( .A(n9219), .B(n7789), .Z(n7790) );
HS65_LH_IVX4 U7679 ( .A(n5981), .Z(n5982) );
HS65_LH_NAND2X4 U7680 ( .A(n5838), .B(n5837), .Z(n5842) );
HS65_LH_NAND2X4 U7681 ( .A(n6006), .B(n6005), .Z(n6008) );
HS65_LH_NAND2X4 U7682 ( .A(n6088), .B(n5831), .Z(n6037) );
HS65_LL_NOR2X5 U7683 ( .A(n6148), .B(n6147), .Z(n6383) );
HS65_LH_NAND2X4 U7684 ( .A(n5891), .B(n5890), .Z(n5893) );
HS65_LH_NAND2X4 U7685 ( .A(n6021), .B(n6020), .Z(n6025) );
HS65_LLS_XNOR2X3 U7687 ( .A(n9004), .B(n7619), .Z(n3050) );
HS65_LH_NAND3X3 U7688 ( .A(n8096), .B(n8157), .C(n8076), .Z(n7700) );
HS65_LL_AND2X4 U7690 ( .A(n2949), .B(n2948), .Z(n2952) );
HS65_LH_NAND2X4 U7691 ( .A(n6087), .B(n5883), .Z(n6092) );
HS65_LH_NAND2X4 U7692 ( .A(n5755), .B(n5958), .Z(n5766) );
HS65_LH_BFX9 U7693 ( .A(n7890), .Z(n7892) );
HS65_LLS_XNOR2X3 U7694 ( .A(\u_DataPath/jaddr_i [19]), .B(n7619), .Z(n7090)
);
HS65_LLS_XNOR2X3 U7695 ( .A(n3029), .B(n7086), .Z(n3048) );
HS65_LH_NAND2X4 U7696 ( .A(n5745), .B(n5744), .Z(n5747) );
HS65_LL_NAND2AX7 U7698 ( .A(n9031), .B(n3030), .Z(n7086) );
HS65_LH_NAND2X4 U7699 ( .A(n6014), .B(n6013), .Z(n6018) );
HS65_LH_NAND2X4 U7700 ( .A(n5903), .B(n5902), .Z(n5905) );
HS65_LL_MUXI21X2 U7701 ( .D0(n3016), .D1(n3015), .S0(n3404), .Z(n4175) );
HS65_LH_NOR2AX3 U7702 ( .A(n3024), .B(n3404), .Z(n3025) );
HS65_LL_AND2X4 U7703 ( .A(n2962), .B(n2960), .Z(n2935) );
HS65_LH_IVX4 U7704 ( .A(n6022), .Z(n6081) );
HS65_LH_NAND2X4 U7705 ( .A(n5806), .B(n5805), .Z(n5810) );
HS65_LL_AND2X4 U7706 ( .A(\u_DataPath/cw_memwb_i [2]), .B(n2960), .Z(n2961)
);
HS65_LH_MUXI21X5 U7707 ( .D0(n3098), .D1(n9377), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8427) );
HS65_LL_NAND2X5 U7708 ( .A(n3030), .B(n2942), .Z(n7619) );
HS65_LH_MUXI21X2 U7709 ( .D0(n3166), .D1(n9380), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8350) );
HS65_LH_MUXI21X2 U7711 ( .D0(n8914), .D1(
\u_DataPath/from_mem_data_out_i [28]), .S0(n3404), .Z(n8383) );
HS65_LH_OAI12X3 U7713 ( .A(n5877), .B(n5874), .C(n5876), .Z(n5780) );
HS65_LH_OAI12X3 U7714 ( .A(n6082), .B(n6019), .C(n6021), .Z(n6010) );
HS65_LHS_XNOR2X3 U7715 ( .A(n8687), .B(n3126), .Z(\u_DataPath/pc_4_i [3]) );
HS65_LH_OAI12X3 U7716 ( .A(n5871), .B(n5775), .C(n5777), .Z(n5725) );
HS65_LH_NOR2X3 U7718 ( .A(n7613), .B(n8932), .Z(n7616) );
HS65_LH_BFX9 U7719 ( .A(n8286), .Z(n7890) );
HS65_LH_OAI12X3 U7720 ( .A(n5897), .B(n5894), .C(n5896), .Z(n5719) );
HS65_LH_BFX9 U7721 ( .A(n8283), .Z(n7883) );
HS65_LH_NOR2X3 U7722 ( .A(n8163), .B(rst), .Z(\u_DataPath/rs_ex_i [0]) );
HS65_LH_NOR2X3 U7723 ( .A(n2881), .B(rst), .Z(\u_DataPath/idex_rt_i [4]) );
HS65_LH_OAI12X3 U7724 ( .A(n5891), .B(n5836), .C(n5838), .Z(n5833) );
HS65_LH_NOR2X3 U7725 ( .A(n8184), .B(rst), .Z(\u_DataPath/idex_rt_i [2]) );
HS65_LH_NOR2X3 U7726 ( .A(n8153), .B(rst), .Z(\u_DataPath/idex_rt_i [1]) );
HS65_LH_OAI12X3 U7728 ( .A(n6100), .B(n6097), .C(n6099), .Z(n5921) );
HS65_LH_OAI12X3 U7729 ( .A(n6094), .B(n6038), .C(n6040), .Z(n6035) );
HS65_LH_OAI12X3 U7730 ( .A(n5885), .B(n5882), .C(n5884), .Z(n5721) );
HS65_LH_IVX9 U7731 ( .A(n3470), .Z(n3416) );
HS65_LH_OAI12X3 U7732 ( .A(n5863), .B(n5753), .C(n5755), .Z(n5727) );
HS65_LL_OR2X4 U7733 ( .A(\u_DataPath/jaddr_i [19]), .B(n2881), .Z(n2880) );
HS65_LH_NAND2X7 U7735 ( .A(n2983), .B(n2984), .Z(n7638) );
HS65_LH_NAND2X4 U7736 ( .A(n5812), .B(n5811), .Z(n5816) );
HS65_LL_NAND2AX4 U7737 ( .A(\u_DataPath/jaddr_i [20]), .B(n6339), .Z(n6332)
);
HS65_LH_BFX9 U7738 ( .A(n8283), .Z(n7884) );
HS65_LH_NAND2AX7 U7739 ( .A(n8480), .B(n9151), .Z(n8263) );
HS65_LH_NAND2AX7 U7740 ( .A(n8480), .B(n8910), .Z(n8231) );
HS65_LH_OR2X9 U7741 ( .A(n9343), .B(n9217), .Z(n5805) );
HS65_LH_NOR2X3 U7742 ( .A(n9235), .B(n8915), .Z(n2973) );
HS65_LH_IVX9 U7744 ( .A(\u_DataPath/dataOut_exe_i [3]), .Z(n3307) );
HS65_LHS_XNOR2X6 U7747 ( .A(\u_DataPath/jaddr_i [19]), .B(n9077), .Z(n7100)
);
HS65_LH_CNIVX3 U7748 ( .A(\u_DataPath/dataOut_exe_i [0]), .Z(n8131) );
HS65_LL_IVX4 U7750 ( .A(\u_DataPath/cw_to_ex_i [3]), .Z(n5491) );
HS65_LH_IVX4 U7752 ( .A(n9225), .Z(n7788) );
HS65_LH_CNIVX3 U7753 ( .A(\u_DataPath/cw_to_ex_i [4]), .Z(n3448) );
HS65_LH_OR2X9 U7754 ( .A(n9341), .B(n9220), .Z(n5811) );
HS65_LL_IVX4 U7755 ( .A(\u_DataPath/cw_to_ex_i [2]), .Z(n5492) );
HS65_LH_NOR2X5 U7757 ( .A(n9033), .B(n9215), .Z(n6097) );
HS65_LH_NOR2X5 U7758 ( .A(n9039), .B(n9116), .Z(n6102) );
HS65_LH_OR2X9 U7759 ( .A(n9341), .B(n9204), .Z(n5858) );
HS65_LH_OR2X4 U7761 ( .A(n9035), .B(n9115), .Z(n5717) );
HS65_LH_IVX9 U7762 ( .A(\u_DataPath/jaddr_i [18]), .Z(n8184) );
HS65_LH_NOR2X5 U7765 ( .A(n8967), .B(n9220), .Z(n6066) );
HS65_LH_NOR2X3 U7766 ( .A(n9077), .B(n9218), .Z(n6061) );
HS65_LH_IVX9 U7767 ( .A(n8961), .Z(\u_DataPath/cw_memwb_i [2]) );
HS65_LH_OR2X9 U7768 ( .A(n9342), .B(n9208), .Z(n5914) );
HS65_LH_NOR2X5 U7769 ( .A(n9181), .B(n9226), .Z(n5960) );
HS65_LH_IVX7 U7770 ( .A(n8682), .Z(n7667) );
HS65_LH_IVX9 U7772 ( .A(n8700), .Z(n3120) );
HS65_LLS_XNOR2X3 U7773 ( .A(n8966), .B(n8766), .Z(n2962) );
HS65_LH_NOR2X5 U7774 ( .A(n9183), .B(n9232), .Z(n5976) );
HS65_LH_NOR2X5 U7775 ( .A(n9171), .B(n9214), .Z(n5979) );
HS65_LH_NOR2X5 U7777 ( .A(n9185), .B(n9230), .Z(n5990) );
HS65_LH_IVX4 U7778 ( .A(n9222), .Z(n7715) );
HS65_LL_NOR2AX3 U7781 ( .A(n3267), .B(n3814), .Z(n4919) );
HS65_LL_NAND4ABX3 U7782 ( .A(n4603), .B(n4602), .C(n4601), .D(n4600), .Z(
n4604) );
HS65_LL_AO12X4 U7783 ( .A(n3030), .B(n8139), .C(n2947), .Z(n2948) );
HS65_LLS_XNOR2X3 U7785 ( .A(n4248), .B(n4247), .Z(n4249) );
HS65_LH_NOR2X2 U7786 ( .A(n9077), .B(n9218), .Z(n2875) );
HS65_LH_CBI4I6X2 U7787 ( .A(n9346), .B(n5417), .C(n3529), .D(n2860), .Z(
n3709) );
HS65_LH_CNIVX3 U7788 ( .A(n9215), .Z(n7706) );
HS65_LL_NOR2AX3 U7789 ( .A(n3472), .B(n3560), .Z(n5257) );
HS65_LLS_XNOR2X3 U7790 ( .A(n8943), .B(n2847), .Z(n3053) );
HS65_LLS_XNOR2X3 U7791 ( .A(n8151), .B(n7619), .Z(n7078) );
HS65_LLS_XNOR2X3 U7792 ( .A(n8763), .B(n8969), .Z(n3035) );
HS65_LL_AOI12X2 U7794 ( .A(n5297), .B(n5466), .C(n5300), .Z(n4685) );
HS65_LL_NOR2X2 U7795 ( .A(n5041), .B(n4583), .Z(n3764) );
HS65_LL_NAND3X2 U7796 ( .A(n5534), .B(n5533), .C(n5532), .Z(n5535) );
HS65_LL_AOI12X2 U7797 ( .A(n4431), .B(n4204), .C(n4203), .Z(n4228) );
HS65_LL_AND3X4 U7798 ( .A(n4708), .B(n5432), .C(n5416), .Z(n2904) );
HS65_LLS_XNOR2X3 U7799 ( .A(n4021), .B(n4020), .Z(n5284) );
HS65_LL_NAND2X2 U7800 ( .A(n3426), .B(n4839), .Z(n4432) );
HS65_LL_OA22X4 U7801 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [30]), .C(
n8380), .D(n3409), .Z(n2916) );
HS65_LLS_XNOR2X3 U7802 ( .A(n4907), .B(n4906), .Z(n4908) );
HS65_LLS_XNOR2X3 U7803 ( .A(n5613), .B(n5612), .Z(n5642) );
HS65_LL_NOR2X2 U7804 ( .A(n4333), .B(n4328), .Z(n4304) );
HS65_LL_NOR2AX3 U7805 ( .A(n4297), .B(n4296), .Z(n4298) );
HS65_LL_NAND2X7 U7806 ( .A(n3230), .B(n3229), .Z(n5053) );
HS65_LL_NAND3X2 U7807 ( .A(n5450), .B(n4996), .C(n5449), .Z(n4992) );
HS65_LL_NOR2X3 U7808 ( .A(\lte_x_59/B[9] ), .B(n2871), .Z(n5396) );
HS65_LH_CNIVX3 U7810 ( .A(n9231), .Z(n7783) );
HS65_LL_NAND3X2 U7811 ( .A(n5534), .B(n5533), .C(n4988), .Z(n4989) );
HS65_LL_IVX2 U7812 ( .A(n5355), .Z(n5467) );
HS65_LL_AOI12X2 U7813 ( .A(n5068), .B(n5067), .C(n5066), .Z(n5069) );
HS65_LH_AOI21X2 U7815 ( .A(\lte_x_59/B[28] ), .B(n4488), .C(n3447), .Z(n3453) );
HS65_LH_CNIVX3 U7817 ( .A(n5081), .Z(n4990) );
HS65_LH_OAI21X2 U7818 ( .A(n3515), .B(n4987), .C(n5529), .Z(n4988) );
HS65_LH_CBI4I1X3 U7820 ( .A(n5587), .B(n5586), .C(n5585), .D(n5584), .Z(
n5588) );
HS65_LH_CBI4I1X3 U7821 ( .A(n5370), .B(n5369), .C(n5484), .D(n5368), .Z(
n5371) );
HS65_LH_CNIVX3 U7822 ( .A(n5482), .Z(n5353) );
HS65_LHS_XOR2X3 U7823 ( .A(n4985), .B(\lte_x_59/B[16] ), .Z(n4857) );
HS65_LH_NOR2X6 U7824 ( .A(n2840), .B(n5089), .Z(n3969) );
HS65_LH_CNIVX3 U7825 ( .A(n3803), .Z(n3686) );
HS65_LH_OAI21X3 U7826 ( .A(n4502), .B(n4889), .C(n4080), .Z(n4363) );
HS65_LH_BFX9 U7827 ( .A(n6690), .Z(n7604) );
HS65_LH_AOI22X1 U7828 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][27] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][27] ), .D(
n6362), .Z(n6208) );
HS65_LH_AOI22X1 U7829 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][11] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][11] ), .D(
n6362), .Z(n6248) );
HS65_LH_AOI22X1 U7831 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][26] ), .B(n7525),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][26] ), .Z(n7325)
);
HS65_LH_AOI22X1 U7832 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][23] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][23] ), .D(
n6362), .Z(n6228) );
HS65_LH_AOI22X1 U7833 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][25] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][25] ), .D(
n6362), .Z(n7146) );
HS65_LH_AOI22X1 U7834 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][28] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][28] ), .D(
n7296), .Z(n6919) );
HS65_LH_BFX9 U7835 ( .A(n6684), .Z(n7594) );
HS65_LH_NOR2X6 U7836 ( .A(n6153), .B(n6152), .Z(n7296) );
HS65_LH_AOI22X1 U7837 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][17] ), .B(n7525),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][17] ), .Z(n6815)
);
HS65_LH_AOI22X1 U7838 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][17] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][17] ), .D(
n2891), .Z(n6810) );
HS65_LH_AOI22X1 U7839 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][18] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][18] ), .D(
n7296), .Z(n6662) );
HS65_LH_BFX9 U7840 ( .A(n6753), .Z(n7524) );
HS65_LH_AOI22X1 U7841 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][1] ), .B(n7525),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][1] ), .Z(n6835)
);
HS65_LH_AO22X4 U7842 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][1] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][1] ), .D(n7318), .Z(n6832) );
HS65_LH_BFX9 U7843 ( .A(n7295), .Z(n6941) );
HS65_LH_AOI22X1 U7844 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][31] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][31] ), .D(
n7296), .Z(n6879) );
HS65_LH_NOR2X6 U7845 ( .A(n6348), .B(n6333), .Z(n7320) );
HS65_LL_NOR2AX3 U7847 ( .A(n3075), .B(n3074), .Z(n3077) );
HS65_LH_AOI312X2 U7848 ( .A(opcode_i[1]), .B(n7777), .C(n7693), .D(n9082),
.E(n7692), .F(n7691), .Z(n8102) );
HS65_LH_OAI21X2 U7849 ( .A(n7697), .B(n8055), .C(n9082), .Z(n7683) );
HS65_LH_CNIVX3 U7850 ( .A(n4655), .Z(n4656) );
HS65_LH_CBI4I6X2 U7851 ( .A(n5549), .B(n5548), .C(n5547), .D(n5546), .Z(
n5553) );
HS65_LL_NOR2AX3 U7852 ( .A(n5504), .B(n5571), .Z(n5574) );
HS65_LL_NOR2AX3 U7853 ( .A(n2853), .B(n5567), .Z(n5343) );
HS65_LH_NOR2X2 U7854 ( .A(n4973), .B(n4972), .Z(n4975) );
HS65_LH_AOI22X1 U7855 ( .A(n4717), .B(n4715), .C(n4714), .D(n3133), .Z(n4716) );
HS65_LH_CBI4I6X2 U7856 ( .A(n5332), .B(n5331), .C(n5330), .D(n5329), .Z(
n5337) );
HS65_LH_NAND3X2 U7857 ( .A(n5328), .B(n5327), .C(n5326), .Z(n5329) );
HS65_LH_NAND2X2 U7858 ( .A(n9376), .B(n8549), .Z(n3162) );
HS65_LL_NAND2AX4 U7859 ( .A(n3588), .B(n3587), .Z(n3589) );
HS65_LH_OAI22X1 U7860 ( .A(n5041), .B(n4583), .C(n3756), .D(n4796), .Z(n4463) );
HS65_LH_NOR2AX3 U7861 ( .A(n2864), .B(n5004), .Z(n3841) );
HS65_LH_NOR2X2 U7862 ( .A(n9346), .B(n4724), .Z(n3424) );
HS65_LH_NOR4ABX2 U7863 ( .A(n5293), .B(n5275), .C(n5360), .D(n5354), .Z(
n5341) );
HS65_LH_CNIVX3 U7864 ( .A(n5352), .Z(n5288) );
HS65_LHS_XOR2X3 U7865 ( .A(\lte_x_59/B[7] ), .B(n5030), .Z(n4771) );
HS65_LH_CNIVX3 U7866 ( .A(n4876), .Z(n4877) );
HS65_LL_NAND4ABX3 U7867 ( .A(n3841), .B(n3840), .C(n3839), .D(n3838), .Z(
n4835) );
HS65_LH_NAND2X7 U7869 ( .A(n7665), .B(n7646), .Z(n7653) );
HS65_LH_CNIVX3 U7870 ( .A(n3629), .Z(n3630) );
HS65_LH_AOI22X1 U7872 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][27] ), .B(n7604),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][27] ), .Z(n7464)
);
HS65_LH_AOI22X1 U7873 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][14] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][14] ), .D(
n6362), .Z(n6308) );
HS65_LH_AOI22X1 U7874 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][14] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][14] ), .Z(n7376)
);
HS65_LH_AOI22X1 U7875 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][3] ), .B(n7525),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][3] ), .Z(n7395)
);
HS65_LH_AOI22X1 U7876 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][10] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][10] ), .Z(n7213)
);
HS65_LH_AO22X4 U7877 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][30] ), .B(n2891),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][30] ), .D(
n7415), .Z(n7418) );
HS65_LH_AOI22X1 U7878 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][13] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][13] ), .D(
n6362), .Z(n7164) );
HS65_LH_AOI22X1 U7879 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][29] ), .B(n7604),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][29] ), .Z(n7530)
);
HS65_LH_CBI4I1X3 U7880 ( .A(n5648), .B(n5422), .C(n4488), .D(
\sub_x_53/A[29] ), .Z(n4361) );
HS65_LH_AOI22X1 U7882 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][21] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][21] ), .D(
n6362), .Z(n6188) );
HS65_LH_AOI22X1 U7883 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][21] ), .B(n7604),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][21] ), .Z(n7605)
);
HS65_LH_AOI22X1 U7884 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][21] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][21] ), .Z(n7595)
);
HS65_LH_AOI22X1 U7885 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][5] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][5] ), .Z(n6708)
);
HS65_LH_AOI22X1 U7886 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][24] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][24] ), .D(
n6362), .Z(n6288) );
HS65_LH_AOI22X1 U7887 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][24] ), .B(n7604),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][24] ), .Z(n7570)
);
HS65_LH_AOI22X1 U7888 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][28] ), .B(n7525),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][28] ), .Z(n7500)
);
HS65_LH_AOI22X1 U7889 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][28] ), .B(n7604),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][28] ), .Z(n7504)
);
HS65_LH_AOI22X1 U7890 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][16] ), .B(n7604),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][16] ), .Z(n7550)
);
HS65_LH_AOI22X1 U7891 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][16] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][16] ), .Z(n7546)
);
HS65_LH_AOI22X1 U7892 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][6] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][6] ), .Z(n7253)
);
HS65_LH_BFX9 U7893 ( .A(n7319), .Z(n7586) );
HS65_LH_BFX9 U7894 ( .A(n7329), .Z(n7599) );
HS65_LH_BFX9 U7895 ( .A(n7331), .Z(n7601) );
HS65_LH_AOI22X1 U7896 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][0] ), .B(n7604),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][0] ), .Z(n7444)
);
HS65_LH_AOI22X1 U7897 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][0] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][0] ), .Z(n7441)
);
HS65_LH_NOR2X2 U7898 ( .A(\u_DataPath/immediate_ext_dec_i [0]), .B(n8157),
.Z(n8122) );
HS65_LH_NAND2X2 U7899 ( .A(\u_DataPath/jaddr_i [22]), .B(n8163), .Z(n6146)
);
HS65_LH_AO22X4 U7905 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][27] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][27] ), .D(
n7292), .Z(n6219) );
HS65_LH_AOI22X1 U7906 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][27] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][27] ), .D(
n7296), .Z(n6217) );
HS65_LH_AO22X4 U7907 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][27] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][27] ), .D(
n6382), .Z(n6220) );
HS65_LH_AO22X4 U7908 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][27] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][27] ), .D(
n6635), .Z(n6216) );
HS65_LH_AOI22X1 U7909 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][27] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][27] ), .D(
n6172), .Z(n6213) );
HS65_LH_AO22X4 U7910 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][27] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][27] ), .D(
n6619), .Z(n6205) );
HS65_LH_AOI22X1 U7911 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][27] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][27] ), .D(
n6363), .Z(n6207) );
HS65_LH_AO22X4 U7912 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][27] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][27] ), .D(
n6629), .Z(n6209) );
HS65_LH_AO22X4 U7913 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][27] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][27] ), .D(
n6627), .Z(n6210) );
HS65_LH_AOI22X1 U7914 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][15] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][15] ), .D(
n2888), .Z(n6368) );
HS65_LH_AOI22X1 U7915 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][15] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][15] ), .D(
n7272), .Z(n6374) );
HS65_LH_AOI22X1 U7916 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][15] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][15] ), .D(
n6600), .Z(n6375) );
HS65_LH_AO22X4 U7917 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][15] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][15] ), .D(
n7276), .Z(n6372) );
HS65_LH_AO22X4 U7918 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][15] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][15] ), .D(
n6383), .Z(n6388) );
HS65_LH_AO22X4 U7919 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][15] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][15] ), .D(
n7284), .Z(n6380) );
HS65_LH_AOI22X1 U7920 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][11] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][11] ), .D(
n7296), .Z(n6257) );
HS65_LH_AO22X4 U7921 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][11] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][11] ), .D(
n6382), .Z(n6260) );
HS65_LH_AO22X4 U7922 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][11] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][11] ), .D(
n6635), .Z(n6256) );
HS65_LH_AOI22X1 U7923 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][11] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][11] ), .D(
n6172), .Z(n6253) );
HS65_LH_AO22X4 U7924 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][11] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][11] ), .D(
n6619), .Z(n6245) );
HS65_LH_AO22X4 U7925 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][11] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][11] ), .D(
n6629), .Z(n6249) );
HS65_LH_AO22X4 U7926 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][11] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][11] ), .D(
n6627), .Z(n6250) );
HS65_LH_AOI22X1 U7927 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][19] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][19] ), .D(
n2888), .Z(n6517) );
HS65_LH_AOI22X1 U7928 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][19] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][19] ), .D(
n7272), .Z(n6521) );
HS65_LH_AOI22X1 U7929 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][19] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][19] ), .D(
n6600), .Z(n6522) );
HS65_LH_AO22X4 U7930 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][19] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][19] ), .D(
n7276), .Z(n6519) );
HS65_LH_AO22X4 U7931 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][19] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][19] ), .D(
n6383), .Z(n6529) );
HS65_LH_AOI22X1 U7932 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][19] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][19] ), .D(
n6171), .Z(n6524) );
HS65_LH_AO22X4 U7933 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][19] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][19] ), .D(
n7284), .Z(n6525) );
HS65_LH_AOI22X1 U7934 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][3] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][3] ), .D(
n2888), .Z(n6577) );
HS65_LH_AOI22X1 U7935 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][3] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][3] ), .D(
n6625), .Z(n6581) );
HS65_LH_AOI22X1 U7936 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][3] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][3] ), .D(
n6600), .Z(n6582) );
HS65_LH_AO22X4 U7937 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][3] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][3] ), .D(
n7276), .Z(n6579) );
HS65_LH_AO22X4 U7938 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][3] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][3] ), .D(
n6383), .Z(n6589) );
HS65_LH_AOI22X1 U7939 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][3] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][3] ), .D(
n6171), .Z(n6584) );
HS65_LH_AO22X4 U7940 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][3] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][3] ), .D(
n7282), .Z(n6586) );
HS65_LH_AOI22X1 U7941 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][10] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][10] ), .D(
n2888), .Z(n6396) );
HS65_LH_AOI22X1 U7942 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][10] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][10] ), .D(
n7272), .Z(n6400) );
HS65_LH_AOI22X1 U7943 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][10] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][10] ), .D(
n6600), .Z(n6401) );
HS65_LH_AO22X4 U7944 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][10] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][10] ), .D(
n7276), .Z(n6398) );
HS65_LH_AO22X4 U7945 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][10] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][10] ), .D(
n6383), .Z(n6408) );
HS65_LH_AO22X4 U7946 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][10] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][10] ), .D(
n7284), .Z(n6404) );
HS65_LH_AOI22X1 U7947 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][26] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][26] ), .D(
n2888), .Z(n6497) );
HS65_LH_AOI22X1 U7948 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][26] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][26] ), .D(
n7272), .Z(n6501) );
HS65_LH_AOI22X1 U7949 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][26] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][26] ), .D(
n6600), .Z(n6502) );
HS65_LH_AO22X4 U7950 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][26] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][26] ), .D(
n7276), .Z(n6499) );
HS65_LH_AO22X4 U7951 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][26] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][26] ), .D(
n6383), .Z(n6509) );
HS65_LH_AOI22X1 U7952 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][26] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][26] ), .D(
n6171), .Z(n6504) );
HS65_LH_AO22X4 U7953 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][26] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][26] ), .D(
n7284), .Z(n6505) );
HS65_LH_AOI22X1 U7954 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][26] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][26] ), .D(n6746),
.Z(n7324) );
HS65_LH_AO22X4 U7955 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][26] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][26] ), .D(
n7319), .Z(n7321) );
HS65_LH_AOI22X1 U7956 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][26] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][26] ), .D(
n6670), .Z(n7316) );
HS65_LH_AOI22X1 U7957 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][26] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][26] ), .D(n6740),
.Z(n7315) );
HS65_LH_AO22X4 U7958 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][26] ), .B(n7578),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][26] ), .Z(n7314)
);
HS65_LH_AO22X4 U7959 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][26] ), .B(n9373),
.C(n7311), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][26] ), .Z(n7313)
);
HS65_LH_AO22X4 U7960 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][26] ), .B(n7523),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][26] ), .Z(n7327)
);
HS65_LH_AOI22X1 U7961 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][26] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][26] ), .Z(n7326)
);
HS65_LH_AO22X4 U7962 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][26] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][26] ), .Z(n7337)
);
HS65_LH_AO22X4 U7963 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][26] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][26] ), .Z(n7338)
);
HS65_LH_AOI22X1 U7964 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][23] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][23] ), .D(
n7296), .Z(n6237) );
HS65_LH_AO22X4 U7965 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][23] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][23] ), .D(
n6382), .Z(n6240) );
HS65_LH_AO22X4 U7966 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][23] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][23] ), .D(
n6635), .Z(n6236) );
HS65_LH_AOI22X1 U7967 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][23] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][23] ), .D(
n6172), .Z(n6233) );
HS65_LH_AO22X4 U7968 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][23] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][23] ), .D(
n6619), .Z(n6225) );
HS65_LH_AO22X4 U7969 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][23] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][23] ), .D(
n6629), .Z(n6229) );
HS65_LH_AO22X4 U7970 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][23] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][23] ), .D(
n6627), .Z(n6230) );
HS65_LH_AOI22X1 U7971 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][12] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][12] ), .D(
n2888), .Z(n6537) );
HS65_LH_AOI22X1 U7972 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][12] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][12] ), .D(
n6625), .Z(n6541) );
HS65_LH_AOI22X1 U7973 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][12] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][12] ), .D(
n6600), .Z(n6542) );
HS65_LH_AO22X4 U7974 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][12] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][12] ), .D(
n7276), .Z(n6539) );
HS65_LH_AO22X4 U7975 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][12] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][12] ), .D(
n6383), .Z(n6549) );
HS65_LH_AOI22X1 U7976 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][12] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][12] ), .D(
n6171), .Z(n6544) );
HS65_LH_AO22X4 U7977 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][12] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][12] ), .D(
n7284), .Z(n6545) );
HS65_LH_AOI22X1 U7978 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][7] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][7] ), .D(
n2888), .Z(n6437) );
HS65_LH_AOI22X1 U7979 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][7] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][7] ), .D(
n7272), .Z(n6441) );
HS65_LH_AOI22X1 U7980 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][7] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][7] ), .D(
n6600), .Z(n6442) );
HS65_LH_AO22X4 U7981 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][7] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][7] ), .D(
n7276), .Z(n6439) );
HS65_LH_AO22X4 U7982 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][7] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][7] ), .D(
n6383), .Z(n6449) );
HS65_LH_AOI22X1 U7983 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][7] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][7] ), .D(
n6171), .Z(n6444) );
HS65_LH_AO22X4 U7984 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][7] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][7] ), .D(
n7284), .Z(n6445) );
HS65_LH_AOI22X1 U7985 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][29] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][29] ), .D(
n7272), .Z(n7280) );
HS65_LH_AOI22X1 U7986 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][29] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][29] ), .D(
n6600), .Z(n7281) );
HS65_LH_AO22X4 U7987 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][29] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][29] ), .D(
n7284), .Z(n7289) );
HS65_LH_AOI22X1 U7988 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][29] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][29] ), .D(
n6172), .Z(n7287) );
HS65_LH_AO22X4 U7989 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][29] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][29] ), .D(
n7292), .Z(n7300) );
HS65_LH_AOI22X1 U7990 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][29] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][29] ), .D(
n7296), .Z(n7298) );
HS65_LH_AOI22X1 U7991 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][5] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][5] ), .D(
n7272), .Z(n6935) );
HS65_LH_AOI22X1 U7992 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][5] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][5] ), .D(
n6600), .Z(n6936) );
HS65_LH_AO22X4 U7993 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][5] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][5] ), .D(
n7284), .Z(n6939) );
HS65_LH_AOI22X1 U7994 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][5] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][5] ), .D(
n6172), .Z(n6937) );
HS65_LH_AO22X4 U7995 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][5] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][5] ), .D(n6382), .Z(n6946) );
HS65_LH_AO22X4 U7996 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][5] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][5] ), .D(
n6383), .Z(n6945) );
HS65_LH_AO22X4 U7997 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][25] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][25] ), .D(
n7171), .Z(n2883) );
HS65_LH_AO22X4 U7998 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][25] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][25] ), .D(
n6635), .Z(n7152) );
HS65_LH_AO22X4 U7999 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][25] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][25] ), .D(
n6637), .Z(n7151) );
HS65_LH_AO22X4 U8000 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][25] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][25] ), .D(
n7285), .Z(n2882) );
HS65_LH_AO22X4 U8001 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][25] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][25] ), .D(
n6627), .Z(n7148) );
HS65_LH_AOI22X1 U8002 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][25] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][25] ), .D(
n7296), .Z(n7153) );
HS65_LH_AO22X4 U8003 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][25] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][25] ), .D(
n6619), .Z(n7143) );
HS65_LH_AOI22X1 U8004 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][9] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][9] ), .D(
n6362), .Z(n7126) );
HS65_LH_AO22X4 U8005 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][9] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][9] ), .D(n6619), .Z(n7123) );
HS65_LH_AO22X4 U8006 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][9] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][9] ), .D(
n6627), .Z(n7128) );
HS65_LH_AO22X4 U8007 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][9] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][9] ), .D(
n6635), .Z(n7134) );
HS65_LH_AOI22X1 U8008 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][9] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][9] ), .D(n7296), .Z(n7135) );
HS65_LH_AOI22X1 U8009 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][28] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][28] ), .D(
n6624), .Z(n6914) );
HS65_LH_AO22X4 U8010 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][28] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][28] ), .D(
n7284), .Z(n6917) );
HS65_LH_AOI22X1 U8011 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][28] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][28] ), .D(
n6172), .Z(n6915) );
HS65_LH_AOI22X1 U8012 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][4] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][4] ), .D(
n7272), .Z(n6632) );
HS65_LH_AOI22X1 U8013 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][4] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][4] ), .D(
n6600), .Z(n6633) );
HS65_LH_AO22X4 U8014 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][4] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][4] ), .D(
n7284), .Z(n6640) );
HS65_LH_AOI22X1 U8015 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][4] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][4] ), .D(
n6172), .Z(n6638) );
HS65_LH_AOI22X1 U8016 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][4] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][4] ), .D(n7296), .Z(n6642) );
HS65_LH_AO22X4 U8017 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][4] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][4] ), .D(
n7292), .Z(n6644) );
HS65_LH_AOI22X1 U8018 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][4] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][4] ), .D(
n6362), .Z(n6623) );
HS65_LH_AOI22X1 U8019 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][8] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][8] ), .D(
n2888), .Z(n6457) );
HS65_LH_AOI22X1 U8020 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][8] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][8] ), .D(
n7272), .Z(n6461) );
HS65_LH_AO22X4 U8021 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][8] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][8] ), .D(
n7276), .Z(n6459) );
HS65_LH_AO22X4 U8022 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][8] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][8] ), .D(
n6383), .Z(n6469) );
HS65_LH_AOI22X1 U8023 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][8] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][8] ), .D(
n6171), .Z(n6464) );
HS65_LH_AO22X4 U8024 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][8] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][8] ), .D(
n7284), .Z(n6465) );
HS65_LH_AOI22X1 U8025 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][20] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][20] ), .D(
n6624), .Z(n6854) );
HS65_LH_AO22X4 U8026 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][20] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][20] ), .D(
n7284), .Z(n6857) );
HS65_LH_AOI22X1 U8027 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][20] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][20] ), .D(
n6172), .Z(n6855) );
HS65_LH_AOI22X1 U8028 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][16] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][16] ), .D(
n7296), .Z(n6177) );
HS65_LH_AO22X4 U8029 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][16] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][16] ), .D(
n6382), .Z(n6180) );
HS65_LH_AO22X4 U8030 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][16] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][16] ), .D(
n6635), .Z(n6176) );
HS65_LH_AOI22X1 U8031 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][16] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][16] ), .D(
n6172), .Z(n6173) );
HS65_LH_AOI22X1 U8032 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][16] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][16] ), .D(
n6171), .Z(n6174) );
HS65_LH_AO22X4 U8033 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][16] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][16] ), .D(
n6619), .Z(n6163) );
HS65_LH_AOI22X1 U8034 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][16] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][16] ), .D(
n6363), .Z(n6165) );
HS65_LH_AO22X4 U8035 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][16] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][16] ), .D(
n6629), .Z(n6167) );
HS65_LH_AO22X4 U8036 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][16] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][16] ), .D(
n6627), .Z(n6168) );
HS65_LH_AOI22X1 U8037 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][17] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][17] ), .D(
n7272), .Z(n6893) );
HS65_LH_AO22X4 U8038 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][17] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][17] ), .D(
n7284), .Z(n6897) );
HS65_LH_AOI22X1 U8039 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][17] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][17] ), .D(
n6172), .Z(n6895) );
HS65_LH_AO22X4 U8040 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][17] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][17] ), .D(
n6382), .Z(n6902) );
HS65_LH_AO22X4 U8041 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][17] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][17] ), .D(
n6383), .Z(n6901) );
HS65_LH_AO22X4 U8042 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][17] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][17] ), .D(
n7318), .Z(n6812) );
HS65_LH_AO22X4 U8043 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][17] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][17] ), .D(
n7319), .Z(n6811) );
HS65_LH_AOI22X1 U8044 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][17] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][17] ), .Z(n6820)
);
HS65_LH_AOI22X1 U8045 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][17] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][17] ), .Z(n6819)
);
HS65_LH_AO22X4 U8046 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][17] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][17] ), .Z(n6822)
);
HS65_LH_AO22X4 U8047 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][17] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][17] ), .Z(n6821)
);
HS65_LH_AO22X4 U8048 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][17] ), .B(n7523),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][17] ), .Z(n6817)
);
HS65_LH_AOI22X1 U8049 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][17] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][17] ), .Z(n6816)
);
HS65_LH_AO22X4 U8050 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][17] ), .B(n9373),
.C(n7311), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][17] ), .Z(n6807)
);
HS65_LH_AO22X4 U8051 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][17] ), .B(n7429),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][17] ), .Z(n6808)
);
HS65_LH_AOI22X1 U8052 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][17] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][17] ), .D(n6740),
.Z(n6809) );
HS65_LH_AOI22X1 U8053 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][2] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][2] ), .D(
n2888), .Z(n6557) );
HS65_LH_AOI22X1 U8054 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][2] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][2] ), .D(
n7272), .Z(n6561) );
HS65_LH_AO22X4 U8055 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][2] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][2] ), .D(
n6383), .Z(n6569) );
HS65_LH_AO22X4 U8056 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][2] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][2] ), .D(
n6637), .Z(n6565) );
HS65_LH_AOI22X1 U8057 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][18] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][18] ), .D(
n7272), .Z(n6656) );
HS65_LH_AOI22X1 U8058 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][18] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][18] ), .D(
n6624), .Z(n6657) );
HS65_LH_AO22X4 U8059 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][18] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][18] ), .D(
n7284), .Z(n6660) );
HS65_LH_AOI22X1 U8060 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][18] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][18] ), .D(
n6362), .Z(n6653) );
HS65_LH_AO22X4 U8061 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][18] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][18] ), .D(
n6382), .Z(n6665) );
HS65_LH_AO22X4 U8062 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][18] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][18] ), .D(
n6383), .Z(n6664) );
HS65_LH_AOI22X1 U8063 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][1] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][1] ), .D(
n2888), .Z(n6598) );
HS65_LH_AOI22X1 U8064 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][1] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][1] ), .D(
n6625), .Z(n6603) );
HS65_LH_AO22X4 U8065 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][1] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][1] ), .D(
n6627), .Z(n6602) );
HS65_LH_AO22X4 U8066 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][1] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][1] ), .D(
n6383), .Z(n6611) );
HS65_LH_AO22X4 U8067 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][1] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][1] ), .D(
n6637), .Z(n6607) );
HS65_LH_AO22X4 U8068 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][1] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][1] ), .D(
n6635), .Z(n6608) );
HS65_LH_AOI22X1 U8069 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][1] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][1] ), .D(
n6171), .Z(n6606) );
HS65_LH_AOI22X1 U8070 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][1] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][1] ), .D(
n6670), .Z(n6830) );
HS65_LH_AOI22X1 U8071 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][1] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][1] ), .D(n6740),
.Z(n6829) );
HS65_LH_AO22X4 U8072 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][1] ), .B(n7429),
.C(n6952), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][1] ), .Z(n6828) );
HS65_LH_AO22X4 U8073 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][1] ), .B(n9373),
.C(n7311), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][1] ), .Z(n6827) );
HS65_LH_AOI22X1 U8074 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][1] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][1] ), .Z(n6840)
);
HS65_LH_AOI22X1 U8075 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][1] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][1] ), .Z(n6839)
);
HS65_LH_AO22X4 U8076 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][1] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][1] ), .Z(n6842)
);
HS65_LH_AO22X4 U8077 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][1] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][1] ), .Z(n6841)
);
HS65_LH_AOI22X1 U8078 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][1] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][1] ), .Z(n6836)
);
HS65_LH_AO22X4 U8079 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][1] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][1] ), .D(
n7319), .Z(n6831) );
HS65_LH_AOI22X1 U8080 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][0] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][0] ), .D(
n2888), .Z(n6416) );
HS65_LH_AOI22X1 U8081 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][0] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][0] ), .D(
n7272), .Z(n6420) );
HS65_LH_AO22X4 U8082 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][0] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][0] ), .D(
n7276), .Z(n6418) );
HS65_LH_AO22X4 U8083 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][0] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][0] ), .D(
n6383), .Z(n6429) );
HS65_LH_AOI22X1 U8084 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][0] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][0] ), .D(
n6171), .Z(n6423) );
HS65_LH_AO22X4 U8085 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][0] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][0] ), .D(
n7284), .Z(n6424) );
HS65_LH_NOR2X2 U8086 ( .A(n7738), .B(n7775), .Z(n7763) );
HS65_LH_CBI4I1X3 U8087 ( .A(n8098), .B(n8122), .C(n8097), .D(n8635), .Z(
n8099) );
HS65_LH_AO22X4 U8088 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][31] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][31] ), .D(
n7284), .Z(n6877) );
HS65_LH_AOI22X1 U8089 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][31] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][31] ), .D(
n6172), .Z(n6875) );
HS65_LH_AO22X4 U8090 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][31] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][31] ), .D(
n6382), .Z(n6882) );
HS65_LH_AO22X4 U8091 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][31] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][31] ), .D(
n6383), .Z(n6881) );
HS65_LH_NOR2X2 U8093 ( .A(n2842), .B(n5376), .Z(n5404) );
HS65_LH_NAND2X2 U8094 ( .A(n5105), .B(n5104), .Z(n5052) );
HS65_LH_OAI21X2 U8095 ( .A(n5313), .B(n5299), .C(n5055), .Z(n5058) );
HS65_LH_NAND2X2 U8096 ( .A(n5054), .B(n5053), .Z(n5055) );
HS65_LH_NAND2X2 U8097 ( .A(n4676), .B(n5061), .Z(n5065) );
HS65_LH_NOR2X2 U8098 ( .A(n5062), .B(n3272), .Z(n5064) );
HS65_LH_NOR2X2 U8099 ( .A(n5300), .B(n5047), .Z(n5056) );
HS65_LH_NOR2X2 U8100 ( .A(n5105), .B(n5104), .Z(n5047) );
HS65_LH_NOR2X2 U8101 ( .A(n5083), .B(n5064), .Z(n5067) );
HS65_LH_NOR2X2 U8102 ( .A(n5004), .B(n5231), .Z(n5357) );
HS65_LH_NOR2X2 U8103 ( .A(\lte_x_59/B[3] ), .B(n5089), .Z(n5383) );
HS65_LH_NOR2X2 U8104 ( .A(n5136), .B(n4660), .Z(n5091) );
HS65_LH_NOR2X2 U8105 ( .A(n5652), .B(n5654), .Z(n5361) );
HS65_LH_NOR2X2 U8106 ( .A(n2849), .B(n3372), .Z(n5430) );
HS65_LH_NAND2X2 U8107 ( .A(\lte_x_59/B[3] ), .B(n5089), .Z(n5090) );
HS65_LH_NOR2X2 U8108 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(n7834), .Z(n5570)
);
HS65_LH_CNIVX3 U8109 ( .A(n5564), .Z(n5565) );
HS65_LH_CNIVX3 U8110 ( .A(n5325), .Z(n5326) );
HS65_LH_NAND2X2 U8111 ( .A(n5041), .B(n5040), .Z(n5328) );
HS65_LH_AOI21X2 U8112 ( .A(n5549), .B(n5547), .C(n5465), .Z(n5331) );
HS65_LH_NOR2X2 U8113 ( .A(n4575), .B(n5383), .Z(n5385) );
HS65_LH_OAI12X3 U8114 ( .A(n4817), .B(n5382), .C(n4819), .Z(n5386) );
HS65_LH_NOR2X2 U8115 ( .A(n5123), .B(\sub_x_53/A[0] ), .Z(n5382) );
HS65_LH_NOR2X2 U8116 ( .A(n5380), .B(n4637), .Z(n5390) );
HS65_LH_NOR2X2 U8117 ( .A(n2865), .B(\lte_x_59/B[6] ), .Z(n5380) );
HS65_LH_NOR2X2 U8118 ( .A(n5388), .B(n4100), .Z(n5381) );
HS65_LH_NAND2X2 U8119 ( .A(\lte_x_59/B[8] ), .B(n3360), .Z(n5397) );
HS65_LH_NAND2X2 U8120 ( .A(\lte_x_59/B[9] ), .B(n2871), .Z(n5395) );
HS65_LH_OAI21X2 U8121 ( .A(n5405), .B(n5404), .C(n4050), .Z(n5409) );
HS65_LH_OAI21X2 U8122 ( .A(n4915), .B(n5406), .C(n3893), .Z(n5407) );
HS65_LH_OAI21X2 U8123 ( .A(n5400), .B(n5399), .C(n4013), .Z(n5401) );
HS65_LH_NOR2X2 U8124 ( .A(n5404), .B(n5377), .Z(n5378) );
HS65_LH_NOR2X2 U8125 ( .A(n3521), .B(n3365), .Z(n5377) );
HS65_LH_OAI21X2 U8126 ( .A(n5272), .B(n5430), .C(n5270), .Z(n5431) );
HS65_LH_OAI21X2 U8127 ( .A(n5506), .B(n3515), .C(n5531), .Z(n5433) );
HS65_LH_OAI21X2 U8128 ( .A(n4418), .B(n4407), .C(n5434), .Z(n5438) );
HS65_LH_NAND2X2 U8129 ( .A(\sub_x_53/A[29] ), .B(n5447), .Z(n5448) );
HS65_LH_NAND2X2 U8130 ( .A(\sub_x_53/A[27] ), .B(n3385), .Z(n5443) );
HS65_LH_NOR2X2 U8131 ( .A(n5419), .B(n4407), .Z(n5420) );
HS65_LH_NOR2X2 U8132 ( .A(\sub_x_53/A[20] ), .B(n3376), .Z(n5419) );
HS65_LH_NAND2X2 U8134 ( .A(n5514), .B(n4672), .Z(n5303) );
HS65_LH_NAND2X2 U8135 ( .A(n5270), .B(n4244), .Z(n5533) );
HS65_LH_NAND2X2 U8137 ( .A(n5022), .B(n5021), .Z(n5003) );
HS65_LH_NAND2X2 U8138 ( .A(n4984), .B(n5001), .Z(n5002) );
HS65_LH_OAI21X2 U8139 ( .A(n5357), .B(n5006), .C(n5534), .Z(n5007) );
HS65_LH_NAND2X2 U8140 ( .A(n4986), .B(n5005), .Z(n5006) );
HS65_LH_OAI21X2 U8141 ( .A(n5344), .B(n5347), .C(n5564), .Z(n5013) );
HS65_LH_NOR2X2 U8142 ( .A(n5342), .B(n5503), .Z(n5015) );
HS65_LH_OAI21X3 U8143 ( .A(n5192), .B(n5012), .C(n5289), .Z(n5580) );
HS65_LH_AOI21X2 U8144 ( .A(n5098), .B(n5552), .C(n5043), .Z(n5044) );
HS65_LH_OAI21X2 U8145 ( .A(n5327), .B(n5095), .C(n5544), .Z(n5043) );
HS65_LH_NAND2X2 U8146 ( .A(n5552), .B(n5034), .Z(n5046) );
HS65_LH_NOR2X2 U8147 ( .A(n5042), .B(n5033), .Z(n5034) );
HS65_LH_AOI21X2 U8148 ( .A(n5039), .B(n5038), .C(n5554), .Z(n5045) );
HS65_LH_NOR2X2 U8149 ( .A(n5036), .B(n5037), .Z(n5038) );
HS65_LH_OAI21X2 U8150 ( .A(n5549), .B(n5548), .C(n5547), .Z(n5039) );
HS65_LH_OAI21X2 U8151 ( .A(n5052), .B(n5300), .C(n5297), .Z(n5060) );
HS65_LH_OAI21X2 U8153 ( .A(n5516), .B(n5514), .C(n5517), .Z(n5068) );
HS65_LH_NAND2X2 U8154 ( .A(n5062), .B(n3272), .Z(n5063) );
HS65_LH_NAND2X2 U8155 ( .A(n5540), .B(n5056), .Z(n5051) );
HS65_LH_NAND2X2 U8156 ( .A(n5050), .B(n5067), .Z(n5071) );
HS65_LH_NOR2X2 U8157 ( .A(n5049), .B(n5514), .Z(n5050) );
HS65_LH_NOR2X2 U8158 ( .A(n4671), .B(n5048), .Z(n5049) );
HS65_LH_NOR2X2 U8159 ( .A(n5022), .B(n5021), .Z(n5024) );
HS65_LH_NOR2X2 U8160 ( .A(n4984), .B(n5001), .Z(n5023) );
HS65_LH_NOR2X2 U8161 ( .A(n5357), .B(n5355), .Z(n5025) );
HS65_LH_NAND3X2 U8163 ( .A(n5540), .B(n5405), .C(n4050), .Z(n5099) );
HS65_LH_OAI21X2 U8164 ( .A(n5093), .B(n5092), .C(n5552), .Z(n5094) );
HS65_LH_NOR2X2 U8165 ( .A(n5548), .B(n5091), .Z(n5093) );
HS65_LH_NAND3X2 U8166 ( .A(n5318), .B(n5547), .C(n5317), .Z(n5092) );
HS65_LH_NOR2X2 U8167 ( .A(n2860), .B(n4967), .Z(n4968) );
HS65_LH_CNIVX3 U8168 ( .A(n5142), .Z(n5147) );
HS65_LH_OAI21X2 U8170 ( .A(n5130), .B(n5129), .C(n5128), .Z(n5132) );
HS65_LHS_XNOR2X3 U8171 ( .A(\lte_x_59/B[28] ), .B(n5423), .Z(n4761) );
HS65_LH_NAND2X2 U8172 ( .A(\lte_x_59/B[7] ), .B(n4351), .Z(n3524) );
HS65_LH_NOR2X2 U8173 ( .A(n4682), .B(n4583), .Z(n3525) );
HS65_LH_AND2X4 U8174 ( .A(n9376), .B(n8499), .Z(n3322) );
HS65_LH_AOI21X2 U8176 ( .A(n3446), .B(n3445), .C(n5646), .Z(n3447) );
HS65_LH_CNIVX3 U8177 ( .A(n3834), .Z(n3446) );
HS65_LH_NOR2X2 U8178 ( .A(n5373), .B(n4682), .Z(n5311) );
HS65_LH_NAND2X2 U8180 ( .A(n2843), .B(n4683), .Z(n5297) );
HS65_LH_NAND2X2 U8181 ( .A(\lte_x_59/B[7] ), .B(n5312), .Z(n4663) );
HS65_LH_NAND2X2 U8182 ( .A(n2865), .B(\lte_x_59/B[6] ), .Z(n4664) );
HS65_LH_CBI4I6X2 U8183 ( .A(n5387), .B(n5388), .C(n4143), .D(n4666), .Z(
n4667) );
HS65_LH_AND3X4 U8185 ( .A(n5322), .B(n4658), .C(n5317), .Z(n4659) );
HS65_LH_CNIVX3 U8186 ( .A(n5388), .Z(n4658) );
HS65_LH_CNIVX3 U8187 ( .A(n5583), .Z(n5587) );
HS65_LH_CNIVX3 U8188 ( .A(n5544), .Z(n5558) );
HS65_LH_CNIVX3 U8189 ( .A(n5540), .Z(n5543) );
HS65_LH_CNIVX3 U8190 ( .A(n5506), .Z(n5512) );
HS65_LH_CNIVX3 U8191 ( .A(n5541), .Z(n5525) );
HS65_LH_AOI21X2 U8192 ( .A(n5520), .B(n5519), .C(n5518), .Z(n5523) );
HS65_LH_CNIVX3 U8193 ( .A(n5516), .Z(n5519) );
HS65_LH_CNIVX3 U8194 ( .A(n5517), .Z(n5518) );
HS65_LH_CBI4I1X3 U8195 ( .A(n5531), .B(n5530), .C(n3515), .D(n5529), .Z(
n5532) );
HS65_LH_NAND3X2 U8196 ( .A(n5105), .B(n5104), .C(n5103), .Z(n5109) );
HS65_LH_CBI4I1X3 U8197 ( .A(n5107), .B(n5468), .C(n5396), .D(n5106), .Z(
n5108) );
HS65_LH_CNIVX3 U8199 ( .A(n5302), .Z(n5296) );
HS65_LH_CNIVX3 U8200 ( .A(n5310), .Z(n5316) );
HS65_LH_NAND2X2 U8201 ( .A(n5327), .B(n3354), .Z(n5315) );
HS65_LH_CNIVX3 U8202 ( .A(n5473), .Z(n5306) );
HS65_LH_NAND2X2 U8204 ( .A(n5390), .B(n5381), .Z(n5394) );
HS65_LH_AOI21X2 U8205 ( .A(n5386), .B(n5385), .C(n5384), .Z(n5393) );
HS65_LH_AOI21X2 U8206 ( .A(n5391), .B(n5390), .C(n5389), .Z(n5392) );
HS65_LH_AOI21X2 U8207 ( .A(n5403), .B(n5402), .C(n5401), .Z(n5411) );
HS65_LH_AOI21X2 U8208 ( .A(n5409), .B(n5408), .C(n5407), .Z(n5410) );
HS65_LH_OAI21X2 U8209 ( .A(n5397), .B(n5396), .C(n5395), .Z(n5403) );
HS65_LH_NOR2X2 U8210 ( .A(n5379), .B(n5412), .Z(n5415) );
HS65_LH_NAND2X2 U8211 ( .A(n5375), .B(n5402), .Z(n5379) );
HS65_LH_NOR2X2 U8212 ( .A(n5374), .B(n5396), .Z(n5375) );
HS65_LH_NOR2X2 U8213 ( .A(\lte_x_59/B[8] ), .B(n3360), .Z(n5374) );
HS65_LH_AOI21X2 U8214 ( .A(n5446), .B(n5445), .C(n5444), .Z(n5455) );
HS65_LH_AOI21X2 U8215 ( .A(n5453), .B(n5452), .C(n5451), .Z(n5454) );
HS65_LH_OAI21X2 U8216 ( .A(n5442), .B(n3572), .C(n5502), .Z(n5445) );
HS65_LH_NAND2X2 U8217 ( .A(n5416), .B(n5432), .Z(n5421) );
HS65_LH_NOR2X2 U8218 ( .A(n5426), .B(n3572), .Z(n5427) );
HS65_LH_AOI21X2 U8220 ( .A(n5347), .B(n5346), .C(n5505), .Z(n5348) );
HS65_LH_CNIVX3 U8221 ( .A(n5471), .Z(n5358) );
HS65_LH_AOI21X2 U8222 ( .A(n5275), .B(n5511), .C(n5355), .Z(n5359) );
HS65_LH_NAND2X2 U8223 ( .A(n5363), .B(n5362), .Z(n5367) );
HS65_LH_CNIVX3 U8224 ( .A(n5354), .Z(n5370) );
HS65_LH_NOR3X1 U8225 ( .A(\sub_x_53/A[30] ), .B(n2873), .C(n5342), .Z(n4964)
);
HS65_LH_AOI21X2 U8226 ( .A(n4983), .B(n5582), .C(n5013), .Z(n4993) );
HS65_LH_OAI21X2 U8227 ( .A(\sub_x_53/A[25] ), .B(n5345), .C(n4982), .Z(n4983) );
HS65_LH_NAND3X2 U8228 ( .A(n4981), .B(n5502), .C(n5180), .Z(n4982) );
HS65_LH_NAND3X2 U8229 ( .A(n5450), .B(n5449), .C(n5575), .Z(n4979) );
HS65_LH_AOI21X2 U8230 ( .A(n5008), .B(n5025), .C(n5007), .Z(n5011) );
HS65_LH_OAI21X2 U8231 ( .A(n5003), .B(n5023), .C(n5002), .Z(n5008) );
HS65_LH_NAND2X2 U8232 ( .A(n5582), .B(n4999), .Z(n5000) );
HS65_LH_NOR2X2 U8233 ( .A(n5500), .B(n4998), .Z(n4999) );
HS65_LH_NOR2X2 U8234 ( .A(n3101), .B(n4997), .Z(n4998) );
HS65_LH_OAI21X2 U8235 ( .A(n5342), .B(n5572), .C(n4229), .Z(n5014) );
HS65_LH_NOR2X2 U8236 ( .A(n5051), .B(n5071), .Z(n5073) );
HS65_LH_NOR2X2 U8237 ( .A(n5027), .B(n5081), .Z(n5028) );
HS65_LH_NAND2X2 U8238 ( .A(n5026), .B(n5025), .Z(n5027) );
HS65_LH_NOR2X2 U8239 ( .A(n5024), .B(n5023), .Z(n5026) );
HS65_LH_AOI21X2 U8240 ( .A(n5087), .B(n5086), .C(n5085), .Z(n5112) );
HS65_LH_NOR2X2 U8241 ( .A(n5084), .B(n5516), .Z(n5086) );
HS65_LH_CNIVX3 U8242 ( .A(n5522), .Z(n5087) );
HS65_LH_OAI21X2 U8243 ( .A(n5522), .B(n5517), .C(n5521), .Z(n5085) );
HS65_LL_NOR3X1 U8244 ( .A(n5550), .B(n5384), .C(n5094), .Z(n5102) );
HS65_LL_NAND3X2 U8245 ( .A(n5544), .B(n5545), .C(n5556), .Z(n5101) );
HS65_LHS_XOR2X3 U8246 ( .A(\lte_x_59/B[22] ), .B(n5654), .Z(n4772) );
HS65_LH_NOR2X2 U8247 ( .A(n5646), .B(n4526), .Z(n3784) );
HS65_LH_NAND2X2 U8248 ( .A(n5618), .B(n5666), .Z(n3771) );
HS65_LH_CNIVX3 U8249 ( .A(n5182), .Z(n3778) );
HS65_LH_AOI21X2 U8250 ( .A(n9352), .B(n4997), .C(n5649), .Z(n3601) );
HS65_LH_CNIVX3 U8251 ( .A(n4120), .Z(n3599) );
HS65_LHS_XNOR2X3 U8252 ( .A(\sub_x_53/A[27] ), .B(n4976), .Z(n4739) );
HS65_LHS_XNOR2X3 U8253 ( .A(n5062), .B(\lte_x_59/B[15] ), .Z(n4748) );
HS65_LHS_XOR2X3 U8254 ( .A(n5398), .B(n2858), .Z(n4757) );
HS65_LH_CBI4I1X3 U8255 ( .A(n3582), .B(n5231), .C(n5647), .D(n2849), .Z(
n5236) );
HS65_LH_AOI21X2 U8256 ( .A(n9352), .B(n5231), .C(n5649), .Z(n5237) );
HS65_LL_NAND2AX4 U8257 ( .A(n3190), .B(n8534), .Z(n3192) );
HS65_LHS_XNOR2X3 U8258 ( .A(n5104), .B(n5105), .Z(n4754) );
HS65_LH_AOI21X2 U8259 ( .A(n9352), .B(n4967), .C(n5649), .Z(n3721) );
HS65_LHS_XOR2X3 U8260 ( .A(\sub_x_53/A[23] ), .B(n4967), .Z(n4755) );
HS65_LH_NAND2X2 U8261 ( .A(n4836), .B(n5617), .Z(n4517) );
HS65_LL_AND2X4 U8262 ( .A(\lte_x_59/B[18] ), .B(n2864), .Z(n3908) );
HS65_LH_NAND2X2 U8263 ( .A(n4887), .B(n4120), .Z(n4068) );
HS65_LH_CBI4I6X2 U8264 ( .A(n9346), .B(n5376), .C(n3529), .D(n4675), .Z(
n4067) );
HS65_LH_AOI21X2 U8265 ( .A(n3529), .B(n3860), .C(n4682), .Z(n3861) );
HS65_LH_NAND2X2 U8266 ( .A(n5648), .B(n5373), .Z(n3860) );
HS65_LH_AOI21X2 U8267 ( .A(n5648), .B(n4699), .C(n5647), .Z(n4439) );
HS65_LH_AOI21X2 U8268 ( .A(n9349), .B(n5021), .C(n4850), .Z(n4852) );
HS65_LHS_XNOR2X3 U8269 ( .A(n5001), .B(n4984), .Z(n4742) );
HS65_LLS_XNOR2X3 U8270 ( .A(n8764), .B(n8943), .Z(n3037) );
HS65_LHS_XNOR2X6 U8271 ( .A(\sub_x_53/A[2] ), .B(n5088), .Z(n4769) );
HS65_LH_AND2X4 U8272 ( .A(\u_DataPath/jaddr_i [25]), .B(
\u_DataPath/jaddr_i [24]), .Z(n6131) );
HS65_LH_AOI112X2 U8273 ( .A(n5648), .B(n7623), .C(n4192), .D(n3443), .Z(
n4193) );
HS65_LHS_XNOR2X3 U8274 ( .A(n2851), .B(n7623), .Z(n4738) );
HS65_LH_OAI22X1 U8275 ( .A(n2854), .B(n4583), .C(n3756), .D(n4711), .Z(n3656) );
HS65_LH_OAI22X1 U8276 ( .A(n4981), .B(n4795), .C(n5129), .D(n3101), .Z(n3657) );
HS65_LH_CNIVX3 U8278 ( .A(n5286), .Z(n4710) );
HS65_LH_NAND3X2 U8279 ( .A(n5270), .B(n4698), .C(n4697), .Z(n4707) );
HS65_LH_NAND3X2 U8280 ( .A(\lte_x_59/B[18] ), .B(n5534), .C(n3371), .Z(n4698) );
HS65_LH_OAI21X2 U8281 ( .A(n5511), .B(n4696), .C(n5432), .Z(n4697) );
HS65_LH_NOR2X2 U8282 ( .A(n5506), .B(n3515), .Z(n4696) );
HS65_LH_NAND3X2 U8283 ( .A(\lte_x_59/B[22] ), .B(n2869), .C(n5290), .Z(n4705) );
HS65_LH_CBI4I1X3 U8284 ( .A(n5471), .B(n5292), .C(n5363), .D(n4703), .Z(
n4704) );
HS65_LH_AOI21X2 U8285 ( .A(n5286), .B(n5505), .C(n5499), .Z(n4729) );
HS65_LH_AOI21X2 U8286 ( .A(n5503), .B(n4727), .C(n5342), .Z(n4728) );
HS65_LH_CBI4I1X3 U8287 ( .A(n5500), .B(n5289), .C(n5012), .D(n4721), .Z(
n4722) );
HS65_LH_CNIVX3 U8288 ( .A(n4720), .Z(n4721) );
HS65_LH_CNIVX3 U8289 ( .A(n5408), .Z(n4681) );
HS65_LH_AOI21X2 U8290 ( .A(n5517), .B(n5476), .C(n5514), .Z(n4680) );
HS65_LH_AOI21X2 U8291 ( .A(n3892), .B(n5083), .C(n4678), .Z(n4679) );
HS65_LH_CB4I6X4 U8292 ( .A(n4687), .B(n4686), .C(n4685), .D(n4684), .Z(n4688) );
HS65_LH_CNIVX3 U8293 ( .A(n5402), .Z(n4686) );
HS65_LH_AOI21X2 U8294 ( .A(n5311), .B(n5335), .C(n5299), .Z(n4687) );
HS65_LH_NAND4ABX3 U8295 ( .A(n4720), .B(n4691), .C(n5346), .D(n5572), .Z(
n4735) );
HS65_LH_NAND2AX4 U8296 ( .A(n4666), .B(n4659), .Z(n4670) );
HS65_LH_NAND2X2 U8298 ( .A(n7834), .B(n5463), .Z(n5497) );
HS65_LH_NOR3X1 U8299 ( .A(n5571), .B(n4965), .C(n4964), .Z(n4980) );
HS65_LHS_XNOR2X3 U8300 ( .A(\sub_x_53/A[0] ), .B(n5123), .Z(n5124) );
HS65_LH_NAND3X2 U8301 ( .A(\u_DataPath/u_idexreg/N3 ), .B(n5121), .C(n5120),
.Z(n5122) );
HS65_LH_NAND2X2 U8302 ( .A(n4836), .B(n5672), .Z(n3762) );
HS65_LH_AOI21X2 U8303 ( .A(n5648), .B(n3593), .C(n5647), .Z(n3584) );
HS65_LH_AOI21X2 U8304 ( .A(n9352), .B(n4976), .C(n3659), .Z(n3660) );
HS65_LH_AOI21X2 U8305 ( .A(n3529), .B(n3658), .C(n4711), .Z(n3659) );
HS65_LH_NAND2X2 U8306 ( .A(n5648), .B(n4976), .Z(n3658) );
HS65_LH_CNIVX3 U8307 ( .A(n4739), .Z(n3662) );
HS65_LH_NOR2X2 U8308 ( .A(n5173), .B(n4185), .Z(n3668) );
HS65_LH_CNIVX3 U8309 ( .A(n3751), .Z(n3631) );
HS65_LH_CNIVX3 U8310 ( .A(n3750), .Z(n3632) );
HS65_LH_AND2X4 U8311 ( .A(n3170), .B(n3407), .Z(n2911) );
HS65_LH_AOI21X2 U8312 ( .A(n5965), .B(n5930), .C(n5929), .Z(n5931) );
HS65_LH_CBI4I1X3 U8313 ( .A(n3582), .B(n5062), .C(n5647), .D(
\lte_x_59/B[15] ), .Z(n3916) );
HS65_LH_NAND2X2 U8314 ( .A(n4507), .B(n4942), .Z(n3915) );
HS65_LH_AOI21X2 U8315 ( .A(n9352), .B(n5062), .C(n5649), .Z(n3917) );
HS65_LH_OAI21X2 U8316 ( .A(n3923), .B(n5646), .C(n3922), .Z(n3924) );
HS65_LH_NAND2X2 U8317 ( .A(n4887), .B(n4504), .Z(n3926) );
HS65_LH_AOI21X2 U8318 ( .A(n3897), .B(n4918), .C(n3896), .Z(n3898) );
HS65_LH_NAND2X2 U8320 ( .A(n4017), .B(n4014), .Z(n4019) );
HS65_LH_CBI4I1X3 U8321 ( .A(n4683), .B(n5648), .C(n5647), .D(n2858), .Z(
n4030) );
HS65_LH_AOI21X2 U8322 ( .A(n9349), .B(n4683), .C(n4028), .Z(n4029) );
HS65_LH_NAND2X2 U8323 ( .A(n5261), .B(n5257), .Z(n5263) );
HS65_LH_CNIVX3 U8324 ( .A(n4494), .Z(n4495) );
HS65_LH_CBI4I1X3 U8325 ( .A(n5648), .B(n5104), .C(n5647), .D(n3474), .Z(
n3970) );
HS65_LH_CNIVX3 U8326 ( .A(n5660), .Z(n3966) );
HS65_LH_CNIVX3 U8327 ( .A(n4950), .Z(n3962) );
HS65_LH_CNIVX3 U8328 ( .A(n4755), .Z(n3725) );
HS65_LH_AOI21X2 U8329 ( .A(n3710), .B(n5615), .C(n3709), .Z(n3711) );
HS65_LH_CNIVX3 U8330 ( .A(n4608), .Z(n3710) );
HS65_LH_CNIVX3 U8331 ( .A(n5606), .Z(n3735) );
HS65_LH_CNIVX3 U8333 ( .A(n5632), .Z(n3701) );
HS65_LHS_XNOR2X3 U8334 ( .A(n4671), .B(n5048), .Z(n4750) );
HS65_LH_CNIVX3 U8335 ( .A(n4625), .Z(n4626) );
HS65_LH_CNIVX3 U8336 ( .A(n4640), .Z(n4642) );
HS65_LH_AOI21X2 U8337 ( .A(n4581), .B(n4341), .C(n5249), .Z(n4342) );
HS65_LL_AOI21X2 U8338 ( .A(n9349), .B(n5422), .C(n5649), .Z(n4352) );
HS65_LHS_XOR2X3 U8340 ( .A(\sub_x_53/A[29] ), .B(n5422), .Z(n4765) );
HS65_LH_AOI21X2 U8341 ( .A(n5618), .B(n4394), .C(n4358), .Z(n4359) );
HS65_LH_CNIVX3 U8342 ( .A(n4356), .Z(n4357) );
HS65_LH_NAND2X2 U8343 ( .A(n5194), .B(n4335), .Z(n4337) );
HS65_LH_AOI21X2 U8344 ( .A(n5659), .B(n4892), .C(n4397), .Z(n4398) );
HS65_LH_AOI21X2 U8345 ( .A(n9349), .B(n5418), .C(n5649), .Z(n4395) );
HS65_LH_NAND2X2 U8346 ( .A(n5229), .B(n4394), .Z(n4399) );
HS65_LH_NAND2X2 U8347 ( .A(n5661), .B(n4393), .Z(n4400) );
HS65_LH_CNIVX3 U8348 ( .A(n4105), .Z(n4106) );
HS65_LH_AOI21X2 U8350 ( .A(n9349), .B(n5040), .C(n4115), .Z(n4116) );
HS65_LHS_XNOR2X3 U8352 ( .A(\lte_x_59/B[5] ), .B(n5040), .Z(n4753) );
HS65_LH_AND2X4 U8353 ( .A(n4714), .B(n8506), .Z(n3227) );
HS65_LH_CNIVX3 U8354 ( .A(n4902), .Z(n4903) );
HS65_LH_CNIVX3 U8355 ( .A(n3823), .Z(n3436) );
HS65_LH_OAI21X2 U8356 ( .A(n5004), .B(n2856), .C(n3819), .Z(n3433) );
HS65_LH_AOI21X2 U8357 ( .A(n5648), .B(n5654), .C(n5647), .Z(n5653) );
HS65_LH_NAND2X2 U8358 ( .A(n5608), .B(n2867), .Z(n5611) );
HS65_LH_AOI21X2 U8359 ( .A(n5139), .B(n5618), .C(n3879), .Z(n3880) );
HS65_LH_AOI21X2 U8360 ( .A(n9352), .B(n5373), .C(n3861), .Z(n3866) );
HS65_LH_AOI21X2 U8362 ( .A(n5234), .B(n4441), .C(n4440), .Z(n4442) );
HS65_LH_AOI21X2 U8363 ( .A(n5207), .B(n4892), .C(n3537), .Z(n3538) );
HS65_LH_CNIVX3 U8365 ( .A(n4542), .Z(n4543) );
HS65_LH_CBI4I6X2 U8366 ( .A(n9346), .B(n3415), .C(n3529), .D(n5130), .Z(
n4549) );
HS65_LH_CNIVX3 U8367 ( .A(n4630), .Z(n4158) );
HS65_LHS_XNOR2X3 U8368 ( .A(\lte_x_59/B[6] ), .B(n2865), .Z(n4764) );
HS65_LH_CNIVX3 U8369 ( .A(n3955), .Z(n3960) );
HS65_LLS_XNOR2X3 U8370 ( .A(n2947), .B(n8762), .Z(n2959) );
HS65_LH_CNIVX3 U8371 ( .A(n2957), .Z(n2958) );
HS65_LH_NOR2X6 U8372 ( .A(n9236), .B(n2982), .Z(n7639) );
HS65_LH_AOI21X2 U8374 ( .A(n9352), .B(n7623), .C(n4194), .Z(n4195) );
HS65_LH_AOI21X2 U8375 ( .A(n4182), .B(n4181), .C(n5646), .Z(n4183) );
HS65_LH_AOI21X2 U8376 ( .A(\lte_x_59/B[28] ), .B(n2864), .C(n4507), .Z(n4181) );
HS65_LH_AOI21X2 U8379 ( .A(n4211), .B(n4291), .C(n4218), .Z(n4219) );
HS65_LHS_XNOR2X3 U8380 ( .A(n8942), .B(\u_DataPath/jaddr_i [16]), .Z(n7103)
);
HS65_LH_AOI21X2 U8381 ( .A(n5229), .B(n4892), .C(n4801), .Z(n4802) );
HS65_LH_AOI21X2 U8382 ( .A(n5648), .B(n4805), .C(n4804), .Z(n4812) );
HS65_LH_OAI21X2 U8383 ( .A(n4796), .B(n4795), .C(n4794), .Z(n4797) );
HS65_LH_CNIVX3 U8384 ( .A(n4333), .Z(n3130) );
HS65_LL_NOR2AX3 U8385 ( .A(n2904), .B(n4735), .Z(n4692) );
HS65_LH_NOR2X2 U8386 ( .A(n5491), .B(\u_DataPath/cw_to_ex_i [4]), .Z(n5121)
);
HS65_LL_AOI21X2 U8388 ( .A(n5192), .B(n5195), .C(n3576), .Z(n3577) );
HS65_LH_NOR2X6 U8389 ( .A(n9078), .B(n9031), .Z(n7343) );
HS65_LH_CNIVX3 U8390 ( .A(n4913), .Z(n4914) );
HS65_LH_AOI21X2 U8392 ( .A(n4919), .B(n4918), .C(n4917), .Z(n4920) );
HS65_LL_NOR3AX2 U8393 ( .A(n3926), .B(n3925), .C(n3924), .Z(n3927) );
HS65_LH_AOI21X2 U8394 ( .A(n5234), .B(n3919), .C(n3918), .Z(n3928) );
HS65_LH_AOI21X2 U8395 ( .A(n4951), .B(n4616), .C(n3906), .Z(n3931) );
HS65_LH_CNIVX3 U8396 ( .A(n4011), .Z(n4012) );
HS65_LH_CNIVX3 U8397 ( .A(n4570), .Z(n4571) );
HS65_LH_AOI21X2 U8398 ( .A(n4508), .B(n4507), .C(n4506), .Z(n4509) );
HS65_LH_CNIVX3 U8400 ( .A(n4938), .Z(n4492) );
HS65_LH_AND2X4 U8401 ( .A(n5405), .B(n4051), .Z(n2906) );
HS65_LH_CNIVX3 U8404 ( .A(n4771), .Z(n4613) );
HS65_LH_AOI21X2 U8405 ( .A(n9352), .B(n5030), .C(n4610), .Z(n4611) );
HS65_LH_OAI22X1 U8406 ( .A(n4954), .B(n3913), .C(n4609), .D(n5646), .Z(n4621) );
HS65_LH_OAI21X2 U8407 ( .A(n4113), .B(n5201), .C(n4065), .Z(n4075) );
HS65_LH_AOI21X2 U8409 ( .A(n5618), .B(n5203), .C(n5202), .Z(n5220) );
HS65_LH_OAI21X2 U8410 ( .A(n3382), .B(n5179), .C(n5178), .Z(n5185) );
HS65_LH_NAND2X2 U8412 ( .A(n4516), .B(n4491), .Z(n4161) );
HS65_LHS_XOR2X3 U8413 ( .A(n3856), .B(n4929), .Z(n3888) );
HS65_LH_CNIVX3 U8414 ( .A(n4880), .Z(n3855) );
HS65_LH_NAND2X2 U8415 ( .A(n4836), .B(n4835), .Z(n4837) );
HS65_LH_CNIVX3 U8416 ( .A(n4575), .Z(n4539) );
HS65_LH_AOI21X2 U8417 ( .A(n4546), .B(n4545), .C(n5201), .Z(n4547) );
HS65_LH_CNIVX3 U8418 ( .A(n4541), .Z(n4546) );
HS65_LH_AOI21X2 U8419 ( .A(\lte_x_59/B[4] ), .B(n4544), .C(n4543), .Z(n4545)
);
HS65_LH_NOR2AX3 U8420 ( .A(n4557), .B(n4556), .Z(n4566) );
HS65_LH_AOI21X2 U8421 ( .A(n9352), .B(n5088), .C(n4549), .Z(n4557) );
HS65_LH_CNIVX3 U8422 ( .A(n4643), .Z(n4142) );
HS65_LH_IVX9 U8423 ( .A(n3409), .Z(n3237) );
HS65_LH_NOR2X2 U8424 ( .A(n9084), .B(n9082), .Z(n7693) );
HS65_LH_AOI21X2 U8425 ( .A(n9082), .B(n7734), .C(n7690), .Z(n7692) );
HS65_LH_NAND2X2 U8427 ( .A(n4836), .B(n5243), .Z(n4177) );
HS65_LH_AOI21X2 U8428 ( .A(n5661), .B(n5228), .C(n4186), .Z(n4201) );
HS65_LH_AOI21X2 U8430 ( .A(n5234), .B(n4199), .C(n4198), .Z(n4200) );
HS65_LH_NAND2X2 U8431 ( .A(n2851), .B(n7623), .Z(n4206) );
HS65_LH_IVX9 U8432 ( .A(n8683), .Z(n7742) );
HS65_LH_IVX9 U8433 ( .A(n8695), .Z(n7753) );
HS65_LH_IVX9 U8434 ( .A(n8694), .Z(n3123) );
HS65_LH_IVX9 U8435 ( .A(n8699), .Z(n3125) );
HS65_LH_IVX9 U8437 ( .A(n8709), .Z(n3124) );
HS65_LH_IVX9 U8438 ( .A(n8705), .Z(n7769) );
HS65_LH_IVX9 U8439 ( .A(n8708), .Z(n7756) );
HS65_LH_IVX9 U8440 ( .A(n8706), .Z(n7766) );
HS65_LH_IVX9 U8441 ( .A(n8711), .Z(n3121) );
HS65_LH_IVX9 U8442 ( .A(n8701), .Z(n3119) );
HS65_LH_IVX9 U8443 ( .A(n8707), .Z(n3118) );
HS65_LH_IVX9 U8444 ( .A(n8710), .Z(n7705) );
HS65_LH_IVX9 U8445 ( .A(n8712), .Z(n7785) );
HS65_LH_NOR3X1 U8446 ( .A(n7636), .B(n7778), .C(n7772), .Z(n7309) );
HS65_LH_CBI4I1X3 U8447 ( .A(n8116), .B(n7698), .C(n7689), .D(n7697), .Z(
n8118) );
HS65_LH_OAI22X1 U8448 ( .A(n7738), .B(n7690), .C(n9084), .D(n7688), .Z(n7689) );
HS65_LL_AND2X4 U8449 ( .A(n5682), .B(n5681), .Z(n5685) );
HS65_LL_NOR3AX2 U8450 ( .A(n7873), .B(n5680), .C(n5679), .Z(n5682) );
HS65_LLS_XNOR2X3 U8451 ( .A(n3393), .B(n3392), .Z(n3514) );
HS65_LLS_XNOR2X3 U8452 ( .A(n3638), .B(n3637), .Z(n3697) );
HS65_LH_IVX2 U8453 ( .A(n7622), .Z(n7621) );
HS65_LH_NAND3X2 U8454 ( .A(n7089), .B(n9031), .C(n9078), .Z(n8145) );
HS65_LH_NAND3X5 U8455 ( .A(n3011), .B(n9078), .C(n2946), .Z(n8147) );
HS65_LH_IVX9 U8456 ( .A(n7840), .Z(n8608) );
HS65_LH_OAI21X2 U8457 ( .A(n9084), .B(n7775), .C(n7774), .Z(n7779) );
HS65_LH_CNIVX3 U8459 ( .A(n6066), .Z(n6009) );
HS65_LH_CNIVX3 U8461 ( .A(n5947), .Z(n5948) );
HS65_LH_CNIVX3 U8463 ( .A(n8258), .Z(n3241) );
HS65_LH_CNIVX3 U8464 ( .A(n6061), .Z(n6062) );
HS65_LH_CNIVX3 U8465 ( .A(n5952), .Z(n5953) );
HS65_LH_AOI22X1 U8466 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][27] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][27] ), .Z(n7460)
);
HS65_LH_AO22X4 U8467 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][27] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][27] ), .Z(n7463)
);
HS65_LH_AO22X4 U8468 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][27] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][27] ), .Z(n7462)
);
HS65_LH_AOI22X1 U8469 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][27] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][27] ), .Z(n7461)
);
HS65_LH_AOI22X1 U8470 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][27] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][27] ), .D(n6746),
.Z(n7459) );
HS65_LH_AO22X4 U8471 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][27] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][27] ), .D(
n6675), .Z(n7457) );
HS65_LH_AO22X4 U8472 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][27] ), .B(n7578),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][27] ), .Z(n7453)
);
HS65_LH_AOI22X1 U8473 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][27] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][27] ), .D(n2890),
.Z(n7454) );
HS65_LH_AO22X4 U8475 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][14] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][14] ), .D(
n6627), .Z(n6310) );
HS65_LH_AO22X4 U8476 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][14] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][14] ), .D(
n6629), .Z(n6309) );
HS65_LH_AO22X4 U8477 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][14] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][14] ), .D(
n7292), .Z(n6320) );
HS65_LH_AOI22X1 U8478 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][14] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][14] ), .D(
n7296), .Z(n6318) );
HS65_LH_AO22X4 U8479 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][14] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][14] ), .D(
n6382), .Z(n6321) );
HS65_LH_AO22X4 U8480 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][14] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][14] ), .D(
n6635), .Z(n6316) );
HS65_LH_AO22X4 U8481 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][14] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][14] ), .D(
n6619), .Z(n6305) );
HS65_LH_AO22X4 U8482 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][14] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][14] ), .D(
n9371), .Z(n6306) );
HS65_LH_AOI22X1 U8483 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][14] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][14] ), .D(
n6363), .Z(n6307) );
HS65_LH_AO22X4 U8484 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][14] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][14] ), .D(
n7586), .Z(n7371) );
HS65_LH_AO22X4 U8485 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][14] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][14] ), .D(
n6675), .Z(n7372) );
HS65_LH_AOI22X1 U8486 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][14] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][14] ), .Z(n7380)
);
HS65_LH_AOI22X1 U8487 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][14] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][14] ), .Z(n7379)
);
HS65_LH_AOI22X1 U8488 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][14] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][14] ), .D(n6740),
.Z(n7369) );
HS65_LH_AOI22X1 U8489 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][14] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][14] ), .Z(n7375)
);
HS65_LH_AO22X4 U8490 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][15] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][15] ), .D(
n7319), .Z(n7188) );
HS65_LH_AOI22X1 U8491 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][15] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][15] ), .D(
n6670), .Z(n7187) );
HS65_LH_AOI22X1 U8492 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][15] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][15] ), .D(n6740),
.Z(n7186) );
HS65_LH_AO22X4 U8493 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][15] ), .B(n9373),
.C(n7311), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][15] ), .Z(n7184)
);
HS65_LH_AO22X4 U8494 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][15] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][15] ), .Z(n7198)
);
HS65_LH_AO22X4 U8495 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][15] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][15] ), .Z(n7199)
);
HS65_LH_AOI22X1 U8496 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][15] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][15] ), .Z(n7192)
);
HS65_LH_AO22X4 U8497 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][11] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][11] ), .Z(n7067)
);
HS65_LH_AOI22X1 U8498 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][11] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][11] ), .Z(n7065)
);
HS65_LH_AOI22X1 U8499 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][11] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][11] ), .D(
n6670), .Z(n7059) );
HS65_LH_AOI22X1 U8500 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][11] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][11] ), .D(n2890),
.Z(n7058) );
HS65_LH_AOI22X1 U8501 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][11] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][11] ), .D(n6746),
.Z(n7063) );
HS65_LH_CNIVX3 U8502 ( .A(n9232), .Z(n4005) );
HS65_LH_AOI22X1 U8503 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][19] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][19] ), .D(n6746),
.Z(n6751) );
HS65_LH_AOI22X1 U8504 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][19] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][19] ), .D(
n6670), .Z(n6744) );
HS65_LH_AOI22X1 U8505 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][19] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][19] ), .D(n2890),
.Z(n6743) );
HS65_LH_AO22X4 U8506 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][19] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][19] ), .Z(n6758)
);
HS65_LH_CNIVX3 U8507 ( .A(n9218), .Z(n5702) );
HS65_LH_AO22X4 U8509 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][3] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][3] ), .D(
n7586), .Z(n7391) );
HS65_LH_AO22X4 U8510 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][3] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][3] ), .D(n6675), .Z(n7392) );
HS65_LH_AOI22X1 U8511 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][3] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][3] ), .Z(n7400)
);
HS65_LH_AOI22X1 U8512 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][3] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][3] ), .Z(n7399)
);
HS65_LH_AOI22X1 U8513 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][3] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][3] ), .Z(n7396)
);
HS65_LH_AOI22X1 U8514 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][10] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][10] ), .D(n6740),
.Z(n7206) );
HS65_LH_AO22X4 U8515 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][10] ), .B(n7578),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][10] ), .Z(n7205)
);
HS65_LH_AO22X4 U8516 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][10] ), .B(n9373),
.C(n7311), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][10] ), .Z(n7204)
);
HS65_LH_AOI22X1 U8517 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][10] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][10] ), .Z(n7217)
);
HS65_LH_AOI22X1 U8518 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][10] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][10] ), .Z(n7216)
);
HS65_LH_AO22X4 U8519 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][10] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][10] ), .Z(n7219)
);
HS65_LH_AO22X4 U8520 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][10] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][10] ), .Z(n7218)
);
HS65_LH_AOI22X1 U8521 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][10] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][10] ), .Z(n7212)
);
HS65_LH_AO22X4 U8522 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][10] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][10] ), .D(
n7319), .Z(n7208) );
HS65_LH_AOI22X1 U8523 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][23] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][23] ), .D(n6740),
.Z(n7226) );
HS65_LH_AO22X4 U8524 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][23] ), .B(n7429),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][23] ), .Z(n7225)
);
HS65_LH_AO22X4 U8525 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][23] ), .B(n9373),
.C(n7311), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][23] ), .Z(n7224)
);
HS65_LH_AOI22X1 U8526 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][23] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][23] ), .Z(n7237)
);
HS65_LH_AOI22X1 U8527 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][23] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][23] ), .Z(n7236)
);
HS65_LH_AO22X4 U8528 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][23] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][23] ), .Z(n7239)
);
HS65_LH_AO22X4 U8529 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][23] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][23] ), .Z(n7238)
);
HS65_LH_AOI22X1 U8530 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][23] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][23] ), .Z(n7232)
);
HS65_LH_AO22X4 U8531 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][23] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][23] ), .D(
n7319), .Z(n7228) );
HS65_LH_AO22X4 U8532 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][30] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][30] ), .D(
n6627), .Z(n6135) );
HS65_LH_AO22X4 U8533 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][30] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][30] ), .D(
n6629), .Z(n6134) );
HS65_LH_AO22X4 U8534 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][30] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][30] ), .D(
n7292), .Z(n6156) );
HS65_LH_AOI22X1 U8535 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][30] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][30] ), .D(
n7296), .Z(n6154) );
HS65_LH_AO22X4 U8536 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][30] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][30] ), .D(
n6382), .Z(n6157) );
HS65_LH_AO22X4 U8537 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][30] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][30] ), .D(
n6637), .Z(n6143) );
HS65_LH_AO22X4 U8538 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][30] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][30] ), .D(
n6635), .Z(n6144) );
HS65_LH_AO22X4 U8539 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][30] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][30] ), .D(
n6619), .Z(n6127) );
HS65_LH_AO22X4 U8540 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][30] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][30] ), .D(
n9371), .Z(n6128) );
HS65_LH_AOI22X1 U8541 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][30] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][30] ), .D(n6746),
.Z(n7413) );
HS65_LH_AO22X4 U8542 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][30] ), .B(n6747),
.C(n6675), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][30] ), .Z(n7412)
);
HS65_LH_AO22X4 U8543 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][30] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][30] ), .Z(n7408)
);
HS65_LH_AO22X4 U8544 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][30] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][30] ), .Z(n7407)
);
HS65_LH_AOI22X1 U8545 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][30] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][30] ), .Z(n7421)
);
HS65_LH_AO22X4 U8546 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][30] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][30] ), .Z(n7423)
);
HS65_LH_AO22X4 U8547 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][30] ), .B(n7578),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][30] ), .D(
n6952), .Z(n7419) );
HS65_LH_AOI22X1 U8548 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][30] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][30] ), .D(n2890),
.Z(n7416) );
HS65_LH_AND2X4 U8549 ( .A(n5450), .B(n4303), .Z(n2915) );
HS65_LH_AO22X4 U8550 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][12] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][12] ), .D(
n7319), .Z(n6791) );
HS65_LH_AOI22X1 U8551 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][12] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][12] ), .D(
n6670), .Z(n6790) );
HS65_LH_AOI22X1 U8552 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][12] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][12] ), .D(n6740),
.Z(n6789) );
HS65_LH_AO22X4 U8553 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][12] ), .B(n7429),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][12] ), .Z(n6788)
);
HS65_LH_AO22X4 U8554 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][12] ), .B(n9373),
.C(n7311), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][12] ), .Z(n6787)
);
HS65_LH_AO22X4 U8555 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][12] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][12] ), .Z(n6801)
);
HS65_LH_AO22X4 U8556 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][12] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][12] ), .Z(n6802)
);
HS65_LH_AOI22X1 U8557 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][12] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][12] ), .Z(n6795)
);
HS65_LH_AO22X4 U8558 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][7] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][7] ), .D(
n7319), .Z(n6723) );
HS65_LH_AOI22X1 U8559 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][7] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][7] ), .Z(n6732)
);
HS65_LH_AOI22X1 U8560 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][7] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][7] ), .Z(n6731)
);
HS65_LH_AO22X4 U8561 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][7] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][7] ), .Z(n6734)
);
HS65_LH_AO22X4 U8562 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][7] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][7] ), .Z(n6733)
);
HS65_LH_AOI22X1 U8563 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][7] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][7] ), .Z(n6727)
);
HS65_LH_AO22X4 U8564 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][7] ), .B(n9373),
.C(n7311), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][7] ), .Z(n6719) );
HS65_LH_AO22X4 U8565 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][7] ), .B(n7429),
.C(n6952), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][7] ), .Z(n6720) );
HS65_LH_AOI22X1 U8566 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][7] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][7] ), .D(n6740),
.Z(n6721) );
HS65_LH_AOI22X1 U8567 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][13] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][13] ), .D(
n6625), .Z(n7168) );
HS65_LH_AO22X4 U8568 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][13] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][13] ), .D(
n6627), .Z(n7167) );
HS65_LH_AO22X4 U8569 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][13] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][13] ), .D(
n6382), .Z(n7179) );
HS65_LH_AOI22X1 U8570 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][13] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][13] ), .D(
n7296), .Z(n7176) );
HS65_LH_AO22X4 U8571 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][13] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][13] ), .D(
n6635), .Z(n7175) );
HS65_LH_AO22X4 U8572 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][13] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][13] ), .D(
n6619), .Z(n7161) );
HS65_LH_AO22X4 U8573 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][13] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][13] ), .D(
n9372), .Z(n7162) );
HS65_LH_AO22X4 U8574 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][13] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][13] ), .Z(n6987)
);
HS65_LH_AOI22X1 U8575 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][13] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][13] ), .Z(n6985)
);
HS65_LH_AOI22X1 U8576 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][13] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][13] ), .D(
n6670), .Z(n6979) );
HS65_LH_AOI22X1 U8577 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][13] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][13] ), .D(n2890),
.Z(n6978) );
HS65_LH_AOI22X1 U8578 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][13] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][13] ), .D(n6746),
.Z(n6983) );
HS65_LH_AOI22X1 U8579 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][29] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][29] ), .Z(n7527)
);
HS65_LH_AOI22X1 U8580 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][29] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][29] ), .Z(n7526)
);
HS65_LH_AO22X4 U8581 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][29] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][29] ), .D(
n7586), .Z(n7518) );
HS65_LH_AO22X4 U8582 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][29] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][29] ), .D(
n6675), .Z(n7519) );
HS65_LH_AOI22X1 U8583 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][29] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][29] ), .D(n6740),
.Z(n7514) );
HS65_LH_AO22X4 U8584 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][21] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][21] ), .D(
n6627), .Z(n6190) );
HS65_LH_AO22X4 U8585 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][21] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][21] ), .D(
n6629), .Z(n6189) );
HS65_LH_AO22X4 U8586 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][21] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][21] ), .D(
n7292), .Z(n6199) );
HS65_LH_AOI22X1 U8587 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][21] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][21] ), .D(
n7296), .Z(n6197) );
HS65_LH_AO22X4 U8588 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][21] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][21] ), .D(
n6382), .Z(n6200) );
HS65_LH_AOI22X1 U8589 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][21] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][21] ), .D(
n6171), .Z(n6194) );
HS65_LH_AO22X4 U8590 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][21] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][21] ), .D(
n6635), .Z(n6196) );
HS65_LH_AO22X4 U8591 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][21] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][21] ), .D(
n6619), .Z(n6185) );
HS65_LH_AO22X4 U8592 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][21] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][21] ), .D(
n9372), .Z(n6186) );
HS65_LH_AOI22X1 U8593 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][21] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][21] ), .D(
n6363), .Z(n6187) );
HS65_LH_AOI22X1 U8594 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][21] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][21] ), .D(
n2891), .Z(n7584) );
HS65_LH_AOI22X1 U8595 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][21] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][21] ), .D(n2890),
.Z(n7583) );
HS65_LH_AO22X4 U8596 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][21] ), .B(n7578),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][21] ), .Z(n7582)
);
HS65_LH_AOI22X1 U8597 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][21] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][21] ), .D(n6746),
.Z(n7591) );
HS65_LH_AO22X4 U8598 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][21] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][21] ), .D(
n6675), .Z(n7589) );
HS65_LH_AOI22X1 U8599 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][21] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][21] ), .Z(n7596)
);
HS65_LH_AO22X4 U8600 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][21] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][21] ), .Z(n7597)
);
HS65_LH_AO22X4 U8601 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][21] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][21] ), .Z(n7598)
);
HS65_LH_AOI22X1 U8602 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][5] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][5] ), .D(n6740),
.Z(n6701) );
HS65_LH_AO22X4 U8603 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][5] ), .B(n7429),
.C(n6952), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][5] ), .Z(n6700) );
HS65_LH_AO22X4 U8604 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][5] ), .B(n9373),
.C(n7311), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][5] ), .Z(n6699) );
HS65_LH_AOI22X1 U8605 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][5] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][5] ), .Z(n6712)
);
HS65_LH_AOI22X1 U8606 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][5] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][5] ), .Z(n6711)
);
HS65_LH_AO22X4 U8607 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][5] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][5] ), .Z(n6714)
);
HS65_LH_AO22X4 U8608 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][5] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][5] ), .Z(n6713)
);
HS65_LH_AOI22X1 U8609 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][5] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][5] ), .Z(n6707)
);
HS65_LH_AO22X4 U8610 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][5] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][5] ), .D(
n7319), .Z(n6703) );
HS65_LH_AO22X4 U8611 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][25] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][25] ), .Z(n7047)
);
HS65_LH_AOI22X1 U8612 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][25] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][25] ), .Z(n7045)
);
HS65_LH_AOI22X1 U8613 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][25] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][25] ), .D(
n6670), .Z(n7039) );
HS65_LH_AOI22X1 U8614 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][25] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][25] ), .D(n2890),
.Z(n7038) );
HS65_LH_AOI22X1 U8615 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][25] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][25] ), .D(n6746),
.Z(n7043) );
HS65_LH_AO22X4 U8616 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][9] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][9] ), .Z(n7027)
);
HS65_LH_AOI22X1 U8617 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][9] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][9] ), .Z(n7025)
);
HS65_LH_AOI22X1 U8618 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][9] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][9] ), .D(
n6670), .Z(n7019) );
HS65_LH_AOI22X1 U8619 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][9] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][9] ), .D(n2890),
.Z(n7018) );
HS65_LH_AOI22X1 U8620 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][9] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][9] ), .D(n6746),
.Z(n7023) );
HS65_LH_AO22X4 U8621 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][24] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][24] ), .D(
n6627), .Z(n6290) );
HS65_LH_AO22X4 U8622 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][24] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][24] ), .D(
n6629), .Z(n6289) );
HS65_LH_AOI22X1 U8623 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][24] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][24] ), .D(
n7296), .Z(n6297) );
HS65_LH_AO22X4 U8624 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][24] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][24] ), .D(
n6382), .Z(n6300) );
HS65_LH_AO22X4 U8625 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][24] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][24] ), .D(
n6637), .Z(n6295) );
HS65_LH_AO22X4 U8626 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][24] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][24] ), .D(
n6635), .Z(n6296) );
HS65_LH_AO22X4 U8627 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][24] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][24] ), .D(
n6619), .Z(n6285) );
HS65_LH_AO22X4 U8628 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][24] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][24] ), .D(
n9371), .Z(n6286) );
HS65_LH_AO22X4 U8629 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][24] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][24] ), .Z(n7569)
);
HS65_LH_AO22X4 U8630 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][24] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][24] ), .Z(n7568)
);
HS65_LH_AOI22X1 U8631 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][24] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][24] ), .Z(n7567)
);
HS65_LH_AOI22X1 U8632 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][24] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][24] ), .D(n6746),
.Z(n7565) );
HS65_LH_AO22X4 U8633 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][24] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][24] ), .D(
n6675), .Z(n7563) );
HS65_LH_AO22X4 U8634 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][24] ), .B(n7578),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][24] ), .Z(n7559)
);
HS65_LH_AOI22X1 U8635 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][24] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][24] ), .D(n2890),
.Z(n7560) );
HS65_LH_AO22X4 U8636 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][28] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][28] ), .D(
n7586), .Z(n7496) );
HS65_LH_AO22X4 U8637 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][28] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][28] ), .D(
n6675), .Z(n7497) );
HS65_LH_AOI22X1 U8638 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][28] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][28] ), .Z(n7501)
);
HS65_LH_AO22X4 U8639 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][22] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][22] ), .D(
n6627), .Z(n6270) );
HS65_LH_AO22X4 U8640 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][22] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][22] ), .D(
n6629), .Z(n6269) );
HS65_LH_AOI22X1 U8641 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][22] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][22] ), .D(
n7296), .Z(n6277) );
HS65_LH_AO22X4 U8642 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][22] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][22] ), .D(
n6382), .Z(n6280) );
HS65_LH_AO22X4 U8643 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][22] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][22] ), .D(
n6637), .Z(n6275) );
HS65_LH_AO22X4 U8644 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][22] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][22] ), .D(
n6635), .Z(n6276) );
HS65_LH_AO22X4 U8645 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][22] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][22] ), .D(
n6619), .Z(n6265) );
HS65_LH_AO22X4 U8646 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][22] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][22] ), .D(
n9372), .Z(n6266) );
HS65_LH_AO22X4 U8647 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][22] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][22] ), .Z(n7007)
);
HS65_LH_AOI22X1 U8648 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][22] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][22] ), .Z(n7005)
);
HS65_LH_AOI22X1 U8649 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][22] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][22] ), .D(
n6670), .Z(n6999) );
HS65_LH_AOI22X1 U8650 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][22] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][22] ), .D(n2890),
.Z(n6998) );
HS65_LH_AOI22X1 U8651 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][22] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][22] ), .D(n6746),
.Z(n7003) );
HS65_LH_CNIVX3 U8652 ( .A(n9213), .Z(n5697) );
HS65_LH_AOI22X1 U8653 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][4] ), .B(n6690),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][4] ), .Z(n7359)
);
HS65_LH_AOI22X1 U8654 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][4] ), .B(n6689),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][4] ), .Z(n7360)
);
HS65_LH_AO22X4 U8655 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][4] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][4] ), .Z(n7358)
);
HS65_LH_AOI22X1 U8656 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][4] ), .B(n6753),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][4] ), .Z(n7356)
);
HS65_LH_AO22X4 U8657 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][4] ), .B(n6681),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][4] ), .Z(n7357)
);
HS65_LH_AO22X4 U8658 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][4] ), .B(n7578),
.C(n6952), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][4] ), .Z(n7348) );
HS65_LH_AOI22X1 U8659 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][4] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][4] ), .D(n2890),
.Z(n7349) );
HS65_LH_AOI22X1 U8660 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][4] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][4] ), .D(n6746),
.Z(n7354) );
HS65_LH_AO22X4 U8661 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][4] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][4] ), .D(n6675), .Z(n7352) );
HS65_LH_AO22X4 U8662 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][8] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][8] ), .D(
n7319), .Z(n6771) );
HS65_LH_AOI22X1 U8663 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][8] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][8] ), .D(
n6670), .Z(n6770) );
HS65_LH_AOI22X1 U8664 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][8] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][8] ), .D(n6740),
.Z(n6769) );
HS65_LH_AO22X4 U8665 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][8] ), .B(n7429),
.C(n7310), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][8] ), .Z(n6768) );
HS65_LH_AO22X4 U8666 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][8] ), .B(n9373),
.C(n7311), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][8] ), .Z(n6767) );
HS65_LH_AO22X4 U8667 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][8] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][8] ), .Z(n6781)
);
HS65_LH_AO22X4 U8668 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][8] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][8] ), .Z(n6782)
);
HS65_LH_AOI22X1 U8669 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][8] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][8] ), .Z(n6775)
);
HS65_LH_AOI22X1 U8670 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][20] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][20] ), .Z(n7481)
);
HS65_LH_AOI22X1 U8671 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][20] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][20] ), .Z(n7480)
);
HS65_LH_AO22X4 U8672 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][20] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][20] ), .D(
n7586), .Z(n7476) );
HS65_LH_AO22X4 U8673 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][20] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][20] ), .D(
n6675), .Z(n7477) );
HS65_LH_AO22X4 U8674 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][20] ), .B(n7578),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][20] ), .Z(n7473)
);
HS65_LH_AOI22X1 U8675 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][16] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][16] ), .D(
n2891), .Z(n7541) );
HS65_LH_AOI22X1 U8676 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][16] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][16] ), .D(n2890),
.Z(n7540) );
HS65_LH_AO22X4 U8677 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][16] ), .B(n7578),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][16] ), .Z(n7539)
);
HS65_LH_AOI22X1 U8678 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][16] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][16] ), .D(n6746),
.Z(n7545) );
HS65_LH_AO22X4 U8679 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][16] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][16] ), .D(
n6675), .Z(n7543) );
HS65_LH_AOI22X1 U8680 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][16] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][16] ), .Z(n7547)
);
HS65_LH_AO22X4 U8681 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][16] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][16] ), .Z(n7548)
);
HS65_LH_AO22X4 U8682 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][16] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][16] ), .Z(n7549)
);
HS65_LH_AOI22X1 U8683 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][2] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][2] ), .D(n2890),
.Z(n6955) );
HS65_LH_AO22X4 U8684 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][2] ), .B(n7578),
.C(n6952), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][2] ), .Z(n6954) );
HS65_LH_AOI22X1 U8685 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][2] ), .B(n6690),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][2] ), .Z(n6968)
);
HS65_LH_AOI22X1 U8686 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][2] ), .B(n6689),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][2] ), .Z(n6969)
);
HS65_LH_AOI22X1 U8687 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][2] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][2] ), .D(n6746),
.Z(n6961) );
HS65_LH_AO22X4 U8688 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][2] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][2] ), .D(
n7586), .Z(n6958) );
HS65_LH_AO22X4 U8689 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][2] ), .B(n6681),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][2] ), .Z(n6964)
);
HS65_LH_AOI22X1 U8690 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][2] ), .B(n6753),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][2] ), .Z(n6963)
);
HS65_LH_AO22X4 U8691 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][2] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][2] ), .Z(n6965)
);
HS65_LH_CNIVX3 U8692 ( .A(n4261), .Z(n4266) );
HS65_LH_AOI22X1 U8693 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][18] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][18] ), .D(
n6670), .Z(n6330) );
HS65_LH_CNIVX3 U8694 ( .A(n9220), .Z(n5700) );
HS65_LH_AOI22X1 U8695 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][6] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][6] ), .D(
n2888), .Z(n6477) );
HS65_LH_AOI22X1 U8696 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][6] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][6] ), .D(
n7272), .Z(n6481) );
HS65_LH_AO22X4 U8697 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][6] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][6] ), .D(
n7276), .Z(n6479) );
HS65_LH_AO22X4 U8698 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][6] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][6] ), .D(
n6383), .Z(n6489) );
HS65_LH_AOI22X1 U8699 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][6] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][6] ), .D(
n6171), .Z(n6484) );
HS65_LH_AO22X4 U8700 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][6] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][6] ), .D(
n7284), .Z(n6485) );
HS65_LH_AO22X4 U8701 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][6] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][6] ), .D(
n7319), .Z(n7248) );
HS65_LH_AOI22X1 U8702 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][6] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][6] ), .D(
n6670), .Z(n7247) );
HS65_LH_AOI22X1 U8703 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][6] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][6] ), .D(n6740),
.Z(n7246) );
HS65_LH_AO22X4 U8704 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][6] ), .B(n9373),
.C(n7311), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][6] ), .Z(n7244) );
HS65_LH_AO22X4 U8705 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][6] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][6] ), .Z(n7258)
);
HS65_LH_AO22X4 U8706 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][6] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][6] ), .Z(n7259)
);
HS65_LH_AOI22X1 U8707 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][6] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][6] ), .Z(n7252)
);
HS65_LH_AO22X4 U8708 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][0] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][0] ), .D(
n7586), .Z(n7435) );
HS65_LH_AO22X4 U8709 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][0] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][0] ), .D(n6675), .Z(n7436) );
HS65_LH_AOI22X1 U8710 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][0] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][0] ), .D(
n6670), .Z(n7433) );
HS65_LH_AOI22X1 U8711 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][0] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][0] ), .Z(n7440)
);
HS65_LH_CNIVX3 U8712 ( .A(n7638), .Z(n7641) );
HS65_LH_NAND2X2 U8713 ( .A(\u_DataPath/immediate_ext_dec_i [2]), .B(
\u_DataPath/immediate_ext_dec_i [0]), .Z(n8089) );
HS65_LH_AO22X4 U8714 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][31] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][31] ), .D(
n7319), .Z(n6676) );
HS65_LH_AOI22X1 U8715 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][31] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][31] ), .Z(n6692)
);
HS65_LH_AOI22X1 U8716 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][31] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][31] ), .Z(n6691)
);
HS65_LH_AO22X4 U8717 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][31] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][31] ), .Z(n6694)
);
HS65_LH_AO22X4 U8718 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][31] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][31] ), .Z(n6693)
);
HS65_LH_AOI22X1 U8719 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][31] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][31] ), .Z(n6685)
);
HS65_LH_AO22X4 U8720 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][31] ), .B(n9373),
.C(n7311), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][31] ), .Z(n6671)
);
HS65_LH_AO22X4 U8721 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][31] ), .B(n7429),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][31] ), .Z(n6672)
);
HS65_LH_AOI22X1 U8722 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][31] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][31] ), .D(n6740),
.Z(n6673) );
HS65_LHS_XOR2X3 U8723 ( .A(n7742), .B(n7741), .Z(\u_DataPath/pc_4_i [6]) );
HS65_LHS_XOR2X3 U8724 ( .A(n7758), .B(n7757), .Z(\u_DataPath/pc_4_i [18]) );
HS65_LH_BFX9 U8725 ( .A(n8288), .Z(n7897) );
HS65_LH_CNIVX3 U8726 ( .A(n8117), .Z(n8058) );
HS65_LH_OR2X4 U8727 ( .A(n8911), .B(n9202), .Z(n5919) );
HS65_LH_IVX2 U8728 ( .A(Data_out_fromRAM[31]), .Z(n8420) );
HS65_LH_IVX44 U8736 ( .A(n8270), .Z(nibble[0]) );
HS65_LH_IVX40 U8737 ( .A(\u_DataPath/pc_4_i [2]), .Z(addr_to_iram[0]) );
HS65_LH_IVX40 U8738 ( .A(n7669), .Z(addr_to_iram[2]) );
HS65_LH_IVX40 U8739 ( .A(n7745), .Z(addr_to_iram[3]) );
HS65_LH_IVX40 U8740 ( .A(n7667), .Z(addr_to_iram[5]) );
HS65_LH_IVX40 U8741 ( .A(n7769), .Z(addr_to_iram[19]) );
HS65_LH_IVX40 U8742 ( .A(n7756), .Z(addr_to_iram[20]) );
HS65_LH_IVX40 U8743 ( .A(n7766), .Z(addr_to_iram[21]) );
HS65_LH_IVX40 U8744 ( .A(n7705), .Z(addr_to_iram[27]) );
HS65_LH_NAND2AX4 U8745 ( .A(n8480), .B(n9110), .Z(n8048) );
HS65_LH_AO22X4 U8746 ( .A(n9185), .B(n8067), .C(n8966), .D(n8066), .Z(
\u_DataPath/RFaddr_out_memwb_i [1]) );
HS65_LH_AO22X4 U8747 ( .A(n8765), .B(n9252), .C(n9325), .D(n9153), .Z(
\u_DataPath/jaddr_i [22]) );
HS65_LH_NAND2AX4 U8748 ( .A(n8480), .B(\u_DataPath/cw_exmem_i [10]), .Z(
n7833) );
HS65_LH_CNIVX3 U8749 ( .A(n8761), .Z(n8063) );
HS65_LH_CNIVX3 U8750 ( .A(n8764), .Z(n8065) );
HS65_LH_NOR2X2 U8751 ( .A(n8177), .B(rst), .Z(n8580) );
HS65_LH_NAND2AX4 U8752 ( .A(n8480), .B(n9238), .Z(n8137) );
HS65_LH_AO222X4 U8753 ( .A(n7896), .B(\u_DataPath/pc_4_i [26]), .C(n7893),
.D(\u_DataPath/jump_address_i [26]), .E(n8940), .F(n7887), .Z(n8646)
);
HS65_LH_AO222X4 U8754 ( .A(n7896), .B(\u_DataPath/pc_4_i [25]), .C(n7893),
.D(n9415), .E(n9199), .F(n7887), .Z(n8647) );
HS65_LH_AO222X4 U8755 ( .A(n7895), .B(\u_DataPath/pc_4_i [15]), .C(n7892),
.D(n9418), .E(n8930), .F(n7888), .Z(n8657) );
HS65_LH_AO222X4 U8756 ( .A(n7895), .B(\u_DataPath/pc_4_i [13]), .C(n7892),
.D(n9413), .E(n8919), .F(n7888), .Z(n8659) );
HS65_LH_AO222X4 U8757 ( .A(n7895), .B(\u_DataPath/pc_4_i [20]), .C(n7892),
.D(n9404), .E(n8926), .F(n7887), .Z(n8652) );
HS65_LH_NAND2X2 U8758 ( .A(n2733), .B(\u_DataPath/cw_memwb_i [2]), .Z(n8061)
);
HS65_LH_NOR2X2 U8759 ( .A(n8107), .B(rst), .Z(
\u_DataPath/regfile_addr_out_towb_i [4]) );
HS65_LH_CNIVX3 U8760 ( .A(n8763), .Z(n8108) );
HS65_LH_AO22X4 U8761 ( .A(n9267), .B(n8067), .C(n8967), .D(n8066), .Z(
\u_DataPath/RFaddr_out_memwb_i [2]) );
HS65_LH_AO22X4 U8762 ( .A(n9183), .B(n8067), .C(n8942), .D(n8066), .Z(
\u_DataPath/RFaddr_out_memwb_i [0]) );
HS65_LH_AO22X4 U8763 ( .A(n9145), .B(n8067), .C(n8968), .D(n8066), .Z(
\u_DataPath/RFaddr_out_memwb_i [4]) );
HS65_LH_AO22X4 U8764 ( .A(n9181), .B(n8067), .C(n9077), .D(n8066), .Z(
\u_DataPath/RFaddr_out_memwb_i [3]) );
HS65_LH_AOI22X1 U8765 ( .A(n8868), .B(n9184), .C(n9365), .D(n9057), .Z(n8416) );
HS65_LH_NAND3X2 U8766 ( .A(n2733), .B(n8715), .C(\u_DataPath/cw_to_ex_i [15]), .Z(n8428) );
HS65_LH_AOI22X1 U8768 ( .A(n8868), .B(n9170), .C(n9365), .D(n9020), .Z(n8317) );
HS65_LH_CNIVX3 U8769 ( .A(n9207), .Z(n7119) );
HS65_LH_AOI22X1 U8770 ( .A(n8868), .B(n9172), .C(n9369), .D(n8987), .Z(n8328) );
HS65_LH_OAI21X3 U8771 ( .A(n9189), .B(n8902), .C(n8375), .Z(
\u_DataPath/dataOut_exe_i [27]) );
HS65_LH_AOI22X1 U8772 ( .A(n8868), .B(n9182), .C(n9366), .D(n8996), .Z(n8375) );
HS65_LL_OAI21X12 U8773 ( .A(n3009), .B(n8140), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N140 ) );
HS65_LL_OAI21X12 U8774 ( .A(n8140), .B(n2773), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N141 ) );
HS65_LL_OAI21X12 U8775 ( .A(n8140), .B(n8147), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N143 ) );
HS65_LL_OAI21X12 U8776 ( .A(n8140), .B(n3010), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N145 ) );
HS65_LHS_XOR2X3 U8777 ( .A(n6037), .B(n6089), .Z(
\u_DataPath/u_execute/resAdd1_i [6]) );
HS65_LHS_XOR2X3 U8778 ( .A(n6012), .B(n6065), .Z(
\u_DataPath/u_execute/resAdd1_i [18]) );
HS65_LHS_XOR2X3 U8779 ( .A(n6025), .B(n6024), .Z(
\u_DataPath/u_execute/resAdd1_i [17]) );
HS65_LHS_XOR2X3 U8780 ( .A(n6004), .B(n6003), .Z(
\u_DataPath/u_execute/resAdd1_i [20]) );
HS65_LH_NAND3AX3 U8781 ( .A(n5693), .B(n5692), .C(n5691), .Z(n8503) );
HS65_LHS_XOR2X3 U8782 ( .A(n6032), .B(n6077), .Z(
\u_DataPath/u_execute/resAdd1_i [8]) );
HS65_LH_NAND2X2 U8783 ( .A(n6110), .B(n6109), .Z(n6112) );
HS65_LH_NAND2X2 U8784 ( .A(n6106), .B(n6105), .Z(n6108) );
HS65_LHS_XOR2X3 U8786 ( .A(n6044), .B(n6043), .Z(
\u_DataPath/u_execute/resAdd1_i [5]) );
HS65_LHS_XOR2X3 U8787 ( .A(n6018), .B(n6017), .Z(
\u_DataPath/u_execute/resAdd1_i [21]) );
HS65_LHS_XOR2X3 U8788 ( .A(n5994), .B(n5993), .Z(
\u_DataPath/u_execute/resAdd1_i [13]) );
HS65_LH_CNIVX3 U8789 ( .A(n6125), .Z(n8513) );
HS65_LH_AO22X9 U8790 ( .A(n9258), .B(n9188), .C(n9133), .D(n8999), .Z(
\u_DataPath/jump_address_i [30]) );
HS65_LHS_XNOR2X3 U8791 ( .A(n6072), .B(n6071), .Z(
\u_DataPath/u_execute/resAdd1_i [10]) );
HS65_LH_AOI21X2 U8792 ( .A(n2866), .B(n8537), .C(n8536), .Z(
\u_DataPath/mem_writedata_out_i [19]) );
HS65_LHS_XOR2X3 U8793 ( .A(n5986), .B(n5985), .Z(
\u_DataPath/u_execute/resAdd1_i [11]) );
HS65_LH_NOR4ABX2 U8794 ( .A(n6224), .B(n6223), .C(n6222), .D(n6221), .Z(
n8377) );
HS65_LHS_XOR2X3 U8795 ( .A(n5970), .B(n5969), .Z(
\u_DataPath/u_execute/resAdd1_i [15]) );
HS65_LHS_XNOR2X3 U8796 ( .A(n6060), .B(n6059), .Z(
\u_DataPath/u_execute/resAdd1_i [14]) );
HS65_LH_NOR4ABX2 U8797 ( .A(n6393), .B(n6392), .C(n6391), .D(n6390), .Z(
n8309) );
HS65_LH_NOR4ABX2 U8798 ( .A(n6264), .B(n6263), .C(n6262), .D(n6261), .Z(
n8347) );
HS65_LH_NOR4ABX2 U8799 ( .A(n6534), .B(n6533), .C(n6532), .D(n6531), .Z(
n8325) );
HS65_LH_NOR4ABX2 U8801 ( .A(n6594), .B(n6593), .C(n6592), .D(n6591), .Z(
n8174) );
HS65_LH_NOR4ABX2 U8802 ( .A(n6413), .B(n6412), .C(n6411), .D(n6410), .Z(
n8296) );
HS65_LH_CNIVX3 U8803 ( .A(n9214), .Z(n7727) );
HS65_LH_NOR4ABX2 U8804 ( .A(n6514), .B(n6513), .C(n6512), .D(n6511), .Z(
n8320) );
HS65_LH_NOR4ABX2 U8805 ( .A(n6244), .B(n6243), .C(n6242), .D(n6241), .Z(
n8361) );
HS65_LH_AOI22X1 U8806 ( .A(n8868), .B(n9174), .C(n9368), .D(n8975), .Z(n8359) );
HS65_LH_NOR4ABX2 U8807 ( .A(n6554), .B(n6553), .C(n6552), .D(n6551), .Z(
n8292) );
HS65_LH_NOR4ABX2 U8808 ( .A(n6454), .B(n6453), .C(n6452), .D(n6451), .Z(
n8303) );
HS65_LH_CNIVX3 U8809 ( .A(n9227), .Z(n7709) );
HS65_LH_CNIVX3 U8810 ( .A(n9228), .Z(n7732) );
HS65_LH_NOR4ABX2 U8811 ( .A(n6950), .B(n6949), .C(n6948), .D(n6947), .Z(
n8414) );
HS65_LH_AOI22X1 U8813 ( .A(n8868), .B(n9176), .C(n9369), .D(n8983), .Z(n8369) );
HS65_LH_CNIVX3 U8814 ( .A(n9209), .Z(n7121) );
HS65_LH_NOR4ABX2 U8815 ( .A(n6926), .B(n6925), .C(n6924), .D(n6923), .Z(
n8418) );
HS65_LH_AOI22X1 U8816 ( .A(n8868), .B(n9178), .C(n9365), .D(n8938), .Z(n7856) );
HS65_LH_CBI4I1X3 U8817 ( .A(n2874), .B(n8724), .C(n7846), .D(n8566), .Z(
n8493) );
HS65_LH_AO22X9 U8818 ( .A(n8872), .B(n9188), .C(n9133), .D(n9041), .Z(
\u_DataPath/jump_address_i [4]) );
HS65_LH_NOR4ABX2 U8819 ( .A(n6649), .B(n6648), .C(n6647), .D(n6646), .Z(
n8430) );
HS65_LH_CNIVX3 U8820 ( .A(n9219), .Z(n7726) );
HS65_LH_NOR4ABX2 U8821 ( .A(n6474), .B(n6473), .C(n6472), .D(n6471), .Z(
n8274) );
HS65_LHS_XNOR2X3 U8822 ( .A(n7719), .B(n7781), .Z(
\u_DataPath/u_execute/link_value_i [8]) );
HS65_LH_CNIVX3 U8823 ( .A(n9229), .Z(n7719) );
HS65_LH_NOR4ABX2 U8824 ( .A(n6866), .B(n6865), .C(n6864), .D(n6863), .Z(
n8411) );
HS65_LH_AOI22X1 U8825 ( .A(n8868), .B(n8912), .C(n9366), .D(n9046), .Z(n8409) );
HS65_LH_NOR4ABX2 U8826 ( .A(n6184), .B(n6183), .C(n6182), .D(n6181), .Z(
n8357) );
HS65_LHS_XOR2X3 U8828 ( .A(n7715), .B(n7714), .Z(n5690) );
HS65_LH_NOR4ABX2 U8829 ( .A(n6906), .B(n6905), .C(n6904), .D(n6903), .Z(
n8407) );
HS65_LH_AOI22X1 U8830 ( .A(n8868), .B(n9036), .C(n9366), .D(n9017), .Z(n8405) );
HS65_LH_AOI21X2 U8831 ( .A(n2874), .B(n8490), .C(n8489), .Z(
\u_DataPath/mem_writedata_out_i [2]) );
HS65_LH_AO22X9 U8832 ( .A(n9188), .B(n9021), .C(n9133), .D(n8945), .Z(
\u_DataPath/jump_address_i [2]) );
HS65_LHS_XOR2X3 U8833 ( .A(n6052), .B(n6101), .Z(
\u_DataPath/u_execute/resAdd1_i [2]) );
HS65_LH_NOR4ABX2 U8834 ( .A(n6574), .B(n6573), .C(n6572), .D(n6571), .Z(
n8173) );
HS65_LH_NOR4ABX2 U8835 ( .A(n6669), .B(n6668), .C(n6667), .D(n6666), .Z(
n8455) );
HS65_LH_MX41X4 U8836 ( .D0(n8441), .S0(n9280), .D1(n8440), .S1(n9295), .D2(
n9302), .S2(n8439), .D3(n8438), .S3(n9287), .Z(
\u_DataPath/from_mem_data_out_i [6]) );
HS65_LH_MX41X4 U8837 ( .D0(n8441), .S0(n9279), .D1(n8440), .S1(n9294), .D2(
n9301), .S2(n8439), .D3(n8438), .S3(n9286), .Z(
\u_DataPath/from_mem_data_out_i [5]) );
HS65_LH_MX41X4 U8838 ( .D0(n8441), .S0(n9278), .D1(n8440), .S1(n9293), .D2(
n9300), .S2(n8439), .D3(n8438), .S3(n9285), .Z(
\u_DataPath/from_mem_data_out_i [4]) );
HS65_LH_MX41X4 U8839 ( .D0(n8441), .S0(n9277), .D1(n8440), .S1(n9292), .D2(
n9299), .S2(n8439), .D3(n8438), .S3(n9284), .Z(
\u_DataPath/from_mem_data_out_i [3]) );
HS65_LH_MX41X4 U8840 ( .D0(n8441), .S0(n9276), .D1(n8440), .S1(n9291), .D2(
n9298), .S2(n8439), .D3(n8438), .S3(n9283), .Z(
\u_DataPath/from_mem_data_out_i [2]) );
HS65_LH_AO22X9 U8841 ( .A(n9133), .B(n8935), .C(n9188), .D(n9105), .Z(
\u_DataPath/jump_address_i [1]) );
HS65_LH_NOR4ABX2 U8843 ( .A(n6616), .B(n6615), .C(n6614), .D(n6613), .Z(
n8167) );
HS65_LH_OR2X4 U8846 ( .A(n9035), .B(n9115), .Z(n5918) );
HS65_LH_NOR4ABX2 U8847 ( .A(n6434), .B(n6433), .C(n6432), .D(n6431), .Z(
n8169) );
HS65_LH_NOR4ABX2 U8848 ( .A(n6886), .B(n6885), .C(n6884), .D(n6883), .Z(
n8421) );
HS65_LH_AO22X4 U8849 ( .A(n8757), .B(n9138), .C(n9320), .D(n9153), .Z(
\u_DataPath/jaddr_i [17]) );
HS65_LH_NOR2X2 U8850 ( .A(n8164), .B(rst), .Z(\u_DataPath/rs_ex_i [1]) );
HS65_LH_NOR2X2 U8851 ( .A(n8165), .B(rst), .Z(\u_DataPath/rs_ex_i [2]) );
HS65_LH_AO22X4 U8852 ( .A(n8756), .B(n9252), .C(n9328), .D(n9153), .Z(
\u_DataPath/jaddr_i [25]) );
HS65_LH_NAND2AX4 U8853 ( .A(n8480), .B(\u_DataPath/u_idexreg/N10 ), .Z(n8136) );
HS65_LH_NAND2AX4 U8854 ( .A(n8480), .B(\u_DataPath/u_idexreg/N16 ), .Z(n8111) );
HS65_LH_NAND2AX4 U8855 ( .A(n8480), .B(\u_DataPath/cw_exmem_i [5]), .Z(n8113) );
HS65_LH_NAND2AX4 U8856 ( .A(n8480), .B(\u_DataPath/u_idexreg/N15 ), .Z(n8112) );
HS65_LH_NAND2AX4 U8857 ( .A(n8480), .B(\u_DataPath/cw_exmem_i [4]), .Z(n8109) );
HS65_LH_NOR4ABX4 U8858 ( .A(opcode_i[1]), .B(n8116), .C(n8056), .D(n8117),
.Z(\u_DataPath/cw_to_ex_i [17]) );
HS65_LH_NAND2AX4 U8859 ( .A(n8480), .B(\u_DataPath/cw_exmem_i [6]), .Z(n8110) );
HS65_LH_NAND2AX4 U8860 ( .A(n8480), .B(n9052), .Z(n8481) );
HS65_LH_NAND2AX4 U8861 ( .A(n8480), .B(n9048), .Z(n8233) );
HS65_LH_NOR2X2 U8862 ( .A(n8152), .B(rst), .Z(\u_DataPath/idex_rt_i [0]) );
HS65_LH_AO22X4 U8863 ( .A(n8754), .B(n9138), .C(n9319), .D(n9153), .Z(
\u_DataPath/jaddr_i [16]) );
HS65_LH_AND2X4 U8864 ( .A(n2733), .B(\u_DataPath/toPC2_i [28]), .Z(
\u_DataPath/branch_target_i [28]) );
HS65_LH_CNIVX3 U8865 ( .A(n5743), .Z(n5744) );
HS65_LH_AND2X4 U8866 ( .A(n2733), .B(\u_DataPath/toPC2_i [26]), .Z(
\u_DataPath/branch_target_i [26]) );
HS65_LHS_XOR2X3 U8867 ( .A(n5810), .B(n5809), .Z(\u_DataPath/toPC2_i [20])
);
HS65_LHS_XOR2X3 U8868 ( .A(n5804), .B(n5803), .Z(\u_DataPath/toPC2_i [19])
);
HS65_LHS_XOR2X3 U8869 ( .A(n5816), .B(n5815), .Z(\u_DataPath/toPC2_i [18])
);
HS65_LHS_XOR2X3 U8870 ( .A(n5823), .B(n5822), .Z(\u_DataPath/toPC2_i [17])
);
HS65_LHS_XOR2X3 U8871 ( .A(n5766), .B(n5765), .Z(\u_DataPath/toPC2_i [15])
);
HS65_LH_AOI12X2 U8872 ( .A(n6057), .B(n5864), .C(n5764), .Z(n5765) );
HS65_LHS_XNOR2X3 U8873 ( .A(n5865), .B(n5864), .Z(\u_DataPath/toPC2_i [14])
);
HS65_LHS_XOR2X3 U8874 ( .A(n5794), .B(n5793), .Z(\u_DataPath/toPC2_i [13])
);
HS65_LHS_XOR2X3 U8875 ( .A(n5785), .B(n5784), .Z(\u_DataPath/toPC2_i [11])
);
HS65_LHS_XNOR2X3 U8876 ( .A(n5873), .B(n5872), .Z(\u_DataPath/toPC2_i [10])
);
HS65_LHS_XOR2X3 U8877 ( .A(n5830), .B(n5878), .Z(\u_DataPath/toPC2_i [8]) );
HS65_LHS_XOR2X3 U8879 ( .A(n5835), .B(n5886), .Z(\u_DataPath/toPC2_i [6]) );
HS65_LHS_XOR2X3 U8881 ( .A(n5842), .B(n5841), .Z(\u_DataPath/toPC2_i [5]) );
HS65_LHS_XOR2X3 U8882 ( .A(n5845), .B(n5898), .Z(\u_DataPath/toPC2_i [2]) );
HS65_LL_NOR4ABX2 U8885 ( .A(n7243), .B(n7242), .C(n7241), .D(n7240), .Z(
n8178) );
HS65_LL_NOR4ABX2 U8887 ( .A(n7342), .B(n7341), .C(n7340), .D(n7339), .Z(
n8315) );
HS65_LL_NOR4ABX2 U8889 ( .A(n7263), .B(n7262), .C(n7261), .D(n7260), .Z(
n8310) );
HS65_LLS_XNOR2X3 U8892 ( .A(n4422), .B(n4421), .Z(n4423) );
HS65_LL_AND2X4 U8893 ( .A(n4714), .B(n8515), .Z(n3261) );
HS65_LH_AOI22X1 U8894 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][4] ), .B(n6754),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][4] ), .Z(n7355)
);
HS65_LH_NOR2X6 U8895 ( .A(n6353), .B(n6332), .Z(n2889) );
HS65_LH_NOR2X6 U8896 ( .A(n6350), .B(n6332), .Z(n2890) );
HS65_LH_NOR2X6 U8897 ( .A(n6349), .B(n2878), .Z(n2891) );
HS65_LH_AOI22X1 U8898 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][23] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][23] ), .D(
n6171), .Z(n6234) );
HS65_LH_AOI22X1 U8899 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][27] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][27] ), .D(
n6171), .Z(n6214) );
HS65_LL_NOR3AX9 U8901 ( .A(n3344), .B(n3343), .C(n3342), .Z(\lte_x_59/B[4] )
);
HS65_LH_NOR2X2 U8902 ( .A(n3474), .B(n3359), .Z(n5298) );
HS65_LL_NAND4ABX3 U8903 ( .A(n3824), .B(n3823), .C(n3822), .D(n3821), .Z(
n4840) );
HS65_LH_NOR2X2 U8904 ( .A(\lte_x_59/B[24] ), .B(n3382), .Z(n5426) );
HS65_LH_AND3X4 U8905 ( .A(n4836), .B(\sub_x_53/A[2] ), .C(n4552), .Z(n2901)
);
HS65_LL_NOR2AX3 U8906 ( .A(n3554), .B(n3553), .Z(n3555) );
HS65_LL_AND2X4 U8907 ( .A(n9205), .B(n7307), .Z(n2908) );
HS65_LL_AND2X4 U8908 ( .A(n2963), .B(n2962), .Z(n2912) );
HS65_LL_OR2X4 U8909 ( .A(n8798), .B(n3403), .Z(n2913) );
HS65_LL_AND2X4 U8910 ( .A(n4289), .B(n4211), .Z(n2914) );
HS65_LL_AND2X4 U8911 ( .A(n4714), .B(n8530), .Z(n2919) );
HS65_LL_AND2X4 U8912 ( .A(n3327), .B(n9145), .Z(n2922) );
HS65_LH_AND2X4 U8913 ( .A(n4717), .B(n9181), .Z(n2923) );
HS65_LH_IVX9 U8915 ( .A(n7802), .Z(n8390) );
HS65_LLS_XNOR2X3 U8916 ( .A(n3008), .B(n8942), .Z(n2953) );
HS65_LLS_XNOR2X3 U8917 ( .A(n7086), .B(n2950), .Z(n2951) );
HS65_LL_AND2ABX18 U8919 ( .A(n7638), .B(n2974), .Z(write_byte) );
HS65_LL_AND2X18 U8920 ( .A(n8879), .B(write_op), .Z(Data_in[4]) );
HS65_LL_NOR2AX25 U8921 ( .A(\u_DataPath/dataOut_exe_i [31]), .B(n3116), .Z(
Address_toRAM[29]) );
HS65_LL_NOR2AX25 U8922 ( .A(\u_DataPath/dataOut_exe_i [9]), .B(n2986), .Z(
Address_toRAM[7]) );
HS65_LL_NOR2AX25 U8923 ( .A(\u_DataPath/dataOut_exe_i [7]), .B(n2986), .Z(
Address_toRAM[5]) );
HS65_LL_NOR2AX25 U8924 ( .A(\u_DataPath/dataOut_exe_i [14]), .B(n2986), .Z(
Address_toRAM[12]) );
HS65_LL_NOR2AX25 U8925 ( .A(\u_DataPath/dataOut_exe_i [16]), .B(n2986), .Z(
Address_toRAM[14]) );
HS65_LL_NOR2AX25 U8926 ( .A(n8738), .B(n2994), .Z(Data_in[16]) );
HS65_LL_NOR2AX25 U8927 ( .A(n8739), .B(n2994), .Z(Data_in[14]) );
HS65_LL_NOR2AX25 U8928 ( .A(n8730), .B(n2994), .Z(Data_in[12]) );
HS65_LL_NOR2AX25 U8929 ( .A(n8735), .B(n2994), .Z(Data_in[11]) );
HS65_LL_NOR2AX25 U8930 ( .A(n8741), .B(n2994), .Z(Data_in[10]) );
HS65_LL_NOR2AX25 U8931 ( .A(n8734), .B(n2994), .Z(Data_in[15]) );
HS65_LL_NOR2AX25 U8932 ( .A(n8740), .B(n2994), .Z(Data_in[17]) );
HS65_LL_NOR2AX25 U8933 ( .A(n8746), .B(n2994), .Z(Data_in[21]) );
HS65_LL_NOR2AX25 U8934 ( .A(n8747), .B(n2994), .Z(Data_in[20]) );
HS65_LL_NOR2AX25 U8935 ( .A(\u_DataPath/dataOut_exe_i [15]), .B(n2986), .Z(
Address_toRAM[13]) );
HS65_LL_NOR2AX25 U8936 ( .A(\u_DataPath/dataOut_exe_i [17]), .B(n2986), .Z(
Address_toRAM[15]) );
HS65_LL_NOR2AX25 U8937 ( .A(\u_DataPath/dataOut_exe_i [26]), .B(n3116), .Z(
Address_toRAM[24]) );
HS65_LH_IVX2 U8939 ( .A(n7086), .Z(n3011) );
HS65_LL_AND2X18 U8940 ( .A(n9018), .B(write_op), .Z(Data_in[0]) );
HS65_LH_OAI22X1 U8941 ( .A(n3285), .B(n4712), .C(n3288), .D(n9401), .Z(n8484) );
HS65_LH_MUXI21X2 U8942 ( .D0(n3018), .D1(n9379), .S0(n3404), .Z(n8243) );
HS65_LH_MUXI21X2 U8943 ( .D0(n3020), .D1(n9393), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8374) );
HS65_LH_NAND2X7 U8944 ( .A(\u_DataPath/cw_memwb_i [2]), .B(n3035), .Z(n3044)
);
HS65_LLS_XNOR2X3 U8945 ( .A(n8762), .B(n8911), .Z(n3038) );
HS65_LH_MUXI21X2 U8946 ( .D0(n3047), .D1(n9392), .S0(n3404), .Z(n8380) );
HS65_LH_AND2X4 U8947 ( .A(\u_DataPath/dataOut_exe_i [0]), .B(n3407), .Z(
n3068) );
HS65_LH_NOR2X6 U8948 ( .A(n8831), .B(n3341), .Z(n3073) );
HS65_LH_NOR2X6 U8949 ( .A(n8826), .B(n3341), .Z(n3076) );
HS65_LH_MUXI21X2 U8950 ( .D0(n3079), .D1(n9398), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8332) );
HS65_LH_MUXI21X2 U8951 ( .D0(n3084), .D1(n9391), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8387) );
HS65_LH_NOR2X6 U8952 ( .A(n8851), .B(n3341), .Z(n3091) );
HS65_LH_MUXI21X2 U8953 ( .D0(n3088), .D1(n9382), .S0(n3404), .Z(n8389) );
HS65_LH_MUXI21X2 U8954 ( .D0(n3093), .D1(n9390), .S0(n3404), .Z(n8355) );
HS65_LH_NOR2X6 U8955 ( .A(n8855), .B(n3403), .Z(n3106) );
HS65_LH_MUXI21X2 U8956 ( .D0(n3103), .D1(n9378), .S0(n3404), .Z(n8266) );
HS65_LL_AO112X18 U8957 ( .A(n8578), .B(n3112), .C(n2879), .D(n8577), .Z(
read_op) );
HS65_LL_OR2ABX18 U8958 ( .A(n8576), .B(n8575), .Z(nibble[1]) );
HS65_LL_NOR2AX25 U8959 ( .A(\u_DataPath/dataOut_exe_i [6]), .B(n2986), .Z(
Address_toRAM[4]) );
HS65_LL_NOR2AX25 U8960 ( .A(\u_DataPath/dataOut_exe_i [5]), .B(n2986), .Z(
Address_toRAM[3]) );
HS65_LL_NOR2AX25 U8961 ( .A(\u_DataPath/dataOut_exe_i [3]), .B(n2986), .Z(
Address_toRAM[1]) );
HS65_LL_NOR2AX25 U8962 ( .A(\u_DataPath/dataOut_exe_i [19]), .B(n3116), .Z(
Address_toRAM[17]) );
HS65_LL_NOR2AX25 U8963 ( .A(\u_DataPath/dataOut_exe_i [18]), .B(n3116), .Z(
Address_toRAM[16]) );
HS65_LL_NOR2AX25 U8964 ( .A(\u_DataPath/dataOut_exe_i [2]), .B(n3116), .Z(
Address_toRAM[0]) );
HS65_LL_NOR2AX25 U8965 ( .A(n8733), .B(n3115), .Z(Data_in[26]) );
HS65_LL_NOR2AX25 U8966 ( .A(n9085), .B(n3115), .Z(Data_in[25]) );
HS65_LL_NOR2AX25 U8967 ( .A(n8732), .B(n3115), .Z(Data_in[24]) );
HS65_LL_AND2ABX18 U8968 ( .A(n8574), .B(n3116), .Z(Address_toRAM[2]) );
HS65_LH_IVX40 U8969 ( .A(n3126), .Z(addr_to_iram[1]) );
HS65_LL_AND2X18 U8970 ( .A(n8731), .B(write_op), .Z(Data_in[5]) );
HS65_LL_AND2X18 U8971 ( .A(n8744), .B(write_op), .Z(Data_in[1]) );
HS65_LL_AND2X18 U8972 ( .A(n8745), .B(write_op), .Z(Data_in[7]) );
HS65_LL_AND2X18 U8973 ( .A(n8725), .B(write_op), .Z(Data_in[3]) );
HS65_LL_AND2X18 U8974 ( .A(n8873), .B(write_op), .Z(Data_in[2]) );
HS65_LL_AND2X18 U8975 ( .A(n8743), .B(write_op), .Z(Data_in[6]) );
HS65_LH_BFX18 U8978 ( .A(n9376), .Z(n4714) );
HS65_LH_NOR2X6 U8980 ( .A(n3572), .B(n3575), .Z(n3751) );
HS65_LH_MUXI21X2 U8981 ( .D0(n7877), .D1(n9388), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8316) );
HS65_LL_MUXI21X2 U8982 ( .D0(n3185), .D1(n9387), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8323) );
HS65_LH_IVX9 U8983 ( .A(n5005), .Z(n3371) );
HS65_LH_NOR2X6 U8984 ( .A(n8822), .B(n3403), .Z(n3200) );
HS65_LH_NOR2X6 U8985 ( .A(\sub_x_53/A[17] ), .B(n2870), .Z(n3515) );
HS65_LH_NOR2X6 U8986 ( .A(n8860), .B(n3403), .Z(n3214) );
HS65_LH_NOR2X2 U8987 ( .A(n8265), .B(n8262), .Z(n3219) );
HS65_LH_MUXI21X2 U8989 ( .D0(n3248), .D1(n9397), .S0(n3404), .Z(n8339) );
HS65_LH_MUXI21X2 U8990 ( .D0(n3259), .D1(n9381), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8255) );
HS65_LH_MUXI21X2 U8991 ( .D0(n8909), .D1(
\u_DataPath/from_mem_data_out_i [15]), .S0(\u_DataPath/cw_towb_i [0]),
.Z(n8306) );
HS65_LH_NOR2X6 U8992 ( .A(n8840), .B(n3290), .Z(n3292) );
HS65_LL_OAI22X3 U8993 ( .A(n3333), .B(\u_DataPath/dataOut_exe_i [2]), .C(
n8488), .D(n3340), .Z(n3295) );
HS65_LH_NAND2X7 U8994 ( .A(n3296), .B(n7802), .Z(n8487) );
HS65_LH_AND2X4 U8995 ( .A(n3309), .B(n3308), .Z(n3311) );
HS65_LH_NOR2X6 U8996 ( .A(n8857), .B(n3403), .Z(n3320) );
HS65_LH_AND2X4 U8998 ( .A(n2896), .B(n3337), .Z(n7863) );
HS65_LH_NAND2X7 U8999 ( .A(\lte_x_59/B[18] ), .B(n3371), .Z(n5272) );
HS65_LH_NAND2X7 U9000 ( .A(n2849), .B(n3372), .Z(n5270) );
HS65_LH_MUX21I1X3 U9001 ( .D0(n3402), .D1(n5183), .S0(n5088), .Z(n4457) );
HS65_LH_NOR2X6 U9002 ( .A(n8823), .B(n3403), .Z(n3411) );
HS65_LL_NOR2AX3 U9003 ( .A(n2866), .B(n3418), .Z(n7846) );
HS65_LH_AOI22X1 U9004 ( .A(\sub_x_53/A[23] ), .B(n4587), .C(n2864), .D(
\lte_x_59/B[21] ), .Z(n3435) );
HS65_LH_NOR2X2 U9005 ( .A(n4726), .B(n2893), .Z(n3439) );
HS65_LH_NAND3X2 U9006 ( .A(n4551), .B(n4836), .C(n4949), .Z(n3444) );
HS65_LH_AOI22X1 U9007 ( .A(\sub_x_53/A[27] ), .B(n4587), .C(n3789), .D(
\sub_x_53/A[25] ), .Z(n3445) );
HS65_LH_NAND2X7 U9008 ( .A(n5321), .B(n5088), .Z(n4838) );
HS65_LH_OAI21X3 U9009 ( .A(n3272), .B(n2857), .C(n3839), .Z(n3459) );
HS65_LH_NOR2AX3 U9010 ( .A(n3469), .B(n3468), .Z(n3512) );
HS65_LH_CNIVX3 U9012 ( .A(n3617), .Z(n3494) );
HS65_LH_NAND2X2 U9014 ( .A(\lte_x_59/B[9] ), .B(n4551), .Z(n3526) );
HS65_LH_NAND3X2 U9015 ( .A(\sub_x_53/A[17] ), .B(n3582), .C(n5001), .Z(n3531) );
HS65_LH_CBI4I1X3 U9016 ( .A(n9352), .B(n5001), .C(\sub_x_53/A[17] ), .D(
n5647), .Z(n3530) );
HS65_LH_OAI21X3 U9017 ( .A(n5621), .B(n4889), .C(n3604), .Z(n3605) );
HS65_LH_NOR2AX3 U9018 ( .A(\sub_x_53/A[2] ), .B(n2857), .Z(n3641) );
HS65_LH_OA12X9 U9019 ( .A(n5129), .B(n4811), .C(n4794), .Z(n3642) );
HS65_LH_NOR2X6 U9020 ( .A(n2840), .B(n3756), .Z(n4507) );
HS65_LH_NAND3X2 U9022 ( .A(n4836), .B(n5624), .C(n4504), .Z(n3653) );
HS65_LH_AOI22X1 U9023 ( .A(n2849), .B(n4588), .C(n4587), .D(\lte_x_59/B[18] ), .Z(n3663) );
HS65_LH_AOI21X2 U9024 ( .A(n5618), .B(n5228), .C(n3668), .Z(n3677) );
HS65_LL_NOR3X1 U9025 ( .A(n3681), .B(n3680), .C(n3679), .Z(n3695) );
HS65_LLS_XNOR2X3 U9026 ( .A(n3692), .B(n3691), .Z(n3693) );
HS65_LLS_XNOR2X3 U9027 ( .A(n3708), .B(n3707), .Z(n3746) );
HS65_LH_OAI21X3 U9028 ( .A(n5240), .B(n4855), .C(n3714), .Z(n3715) );
HS65_LH_CNIVX3 U9029 ( .A(n5608), .Z(n3734) );
HS65_LLS_XNOR2X3 U9030 ( .A(n3755), .B(n3754), .Z(n3813) );
HS65_LH_MUXI21X2 U9031 ( .D0(n4726), .D1(n2840), .S0(n3756), .Z(n4491) );
HS65_LHS_XNOR2X3 U9032 ( .A(n2853), .B(n5567), .Z(n4751) );
HS65_LH_OAI21X3 U9033 ( .A(n4986), .B(n3756), .C(n3768), .Z(n3769) );
HS65_LH_NAND3X2 U9034 ( .A(n3582), .B(n2853), .C(n5567), .Z(n3776) );
HS65_LH_NAND2X2 U9035 ( .A(n5647), .B(n2853), .Z(n3775) );
HS65_LH_AND2X4 U9036 ( .A(\lte_x_59/B[7] ), .B(n3789), .Z(n4465) );
HS65_LH_NAND2X2 U9037 ( .A(n5207), .B(n5660), .Z(n3791) );
HS65_LH_CBI4I1X3 U9038 ( .A(n3582), .B(n5048), .C(n5647), .D(n3521), .Z(
n3825) );
HS65_LH_NAND2X7 U9039 ( .A(n4836), .B(n4550), .Z(n5201) );
HS65_LHS_XNOR2X6 U9041 ( .A(n3848), .B(n3847), .Z(n3849) );
HS65_LH_CNIVX3 U9042 ( .A(n5143), .Z(n3874) );
HS65_LH_NAND3X2 U9043 ( .A(n4512), .B(n3426), .C(n3872), .Z(n3873) );
HS65_LH_NAND3X2 U9044 ( .A(n4949), .B(n3426), .C(n4176), .Z(n3922) );
HS65_LH_CNIVX3 U9045 ( .A(n4754), .Z(n3975) );
HS65_LH_NAND3X2 U9046 ( .A(n4192), .B(n5032), .C(n3969), .Z(n3972) );
HS65_LH_NAND2X2 U9047 ( .A(n9352), .B(n5104), .Z(n3971) );
HS65_LH_IVX9 U9048 ( .A(n4287), .Z(n7729) );
HS65_LH_AND2X4 U9049 ( .A(n4041), .B(n4037), .Z(n4043) );
HS65_LHS_XNOR2X3 U9050 ( .A(n4674), .B(n2842), .Z(n4740) );
HS65_LH_AOI22X1 U9051 ( .A(n4516), .B(n5239), .C(n4508), .D(n4614), .Z(n4179) );
HS65_LH_NAND2X2 U9052 ( .A(n3426), .B(n4176), .Z(n4178) );
HS65_LH_AOI22X1 U9053 ( .A(\sub_x_53/A[30] ), .B(n4587), .C(n4351), .D(
\sub_x_53/A[29] ), .Z(n4182) );
HS65_LH_CNIVX3 U9054 ( .A(n4738), .Z(n4199) );
HS65_LLS_XNOR2X3 U9055 ( .A(n5005), .B(\lte_x_59/B[18] ), .Z(n4744) );
HS65_LH_CBI4I1X3 U9056 ( .A(n5648), .B(n5005), .C(n5647), .D(
\lte_x_59/B[18] ), .Z(n4270) );
HS65_LL_AOI22X1 U9057 ( .A(n8868), .B(n9038), .C(n9366), .D(n8972), .Z(n7843) );
HS65_LLS_XNOR2X3 U9058 ( .A(n4339), .B(n4338), .Z(n4367) );
HS65_LH_NAND2X2 U9059 ( .A(n4340), .B(n4341), .Z(n4343) );
HS65_LH_OAI22X1 U9060 ( .A(n2854), .B(n4795), .C(n2857), .D(n4724), .Z(n4350) );
HS65_LHS_XNOR2X3 U9061 ( .A(\lte_x_59/B[21] ), .B(n5418), .Z(n4737) );
HS65_LH_NAND2X2 U9062 ( .A(n5207), .B(n4872), .Z(n4392) );
HS65_LH_CBI4I1X3 U9063 ( .A(n5648), .B(n5418), .C(n5647), .D(
\lte_x_59/B[21] ), .Z(n4396) );
HS65_LL_NAND3X2 U9064 ( .A(n4400), .B(n4399), .C(n4398), .Z(n4401) );
HS65_LHS_XNOR2X3 U9065 ( .A(\lte_x_59/B[4] ), .B(n5032), .Z(n4749) );
HS65_LH_CBI4I1X3 U9066 ( .A(n5648), .B(n2872), .C(n3443), .D(\lte_x_59/B[4] ), .Z(n4459) );
HS65_LH_NOR2X2 U9067 ( .A(n4513), .B(n4838), .Z(n4514) );
HS65_LH_OAI22X1 U9068 ( .A(n4725), .B(n4583), .C(n5129), .D(n4724), .Z(n4523) );
HS65_LHS_XNOR2X6 U9069 ( .A(\sub_x_53/A[30] ), .B(n4966), .Z(n4767) );
HS65_LH_NOR2AX3 U9070 ( .A(n4535), .B(n5152), .Z(n6121) );
HS65_LH_NAND2X2 U9071 ( .A(n4551), .B(n4550), .Z(n4580) );
HS65_LH_NAND2X2 U9072 ( .A(n5217), .B(n4563), .Z(n4564) );
HS65_LLS_XNOR2X3 U9073 ( .A(n4577), .B(n4576), .Z(n4605) );
HS65_LH_CBI4I1X3 U9074 ( .A(n5648), .B(n5321), .C(n4804), .D(\lte_x_59/B[3] ), .Z(n4586) );
HS65_LH_OAI222X2 U9075 ( .A(n4796), .B(n4583), .C(n2848), .D(n4582), .E(
n2893), .F(n5041), .Z(n4584) );
HS65_LHS_XNOR2X3 U9076 ( .A(\lte_x_59/B[3] ), .B(n5321), .Z(n4763) );
HS65_LH_AOI22X1 U9077 ( .A(\lte_x_59/B[7] ), .B(n4588), .C(n4587), .D(
\lte_x_59/B[8] ), .Z(n4589) );
HS65_LH_CBI4I1X3 U9078 ( .A(n3582), .B(n5030), .C(n5647), .D(\lte_x_59/B[7] ), .Z(n4612) );
HS65_LH_CNIVX3 U9079 ( .A(n4638), .Z(n4639) );
HS65_LH_NAND2X5 U9080 ( .A(n5032), .B(n4796), .Z(n5322) );
HS65_LH_CB4I1X9 U9081 ( .A(n4657), .B(n8495), .C(n4656), .D(n5041), .Z(n5388) );
HS65_LH_NAND2X7 U9083 ( .A(n4711), .B(n4976), .Z(n5564) );
HS65_LH_NAND2X7 U9084 ( .A(n4725), .B(n5422), .Z(n5286) );
HS65_LH_NAND4ABX3 U9085 ( .A(n5426), .B(n5571), .C(n5286), .D(n5289), .Z(
n4691) );
HS65_LH_NAND3X2 U9086 ( .A(n3384), .B(n2853), .C(n5564), .Z(n4723) );
HS65_LH_NOR3X1 U9087 ( .A(n4713), .B(n8833), .C(n4712), .Z(n4719) );
HS65_LH_OAI31X1 U9088 ( .A(n4717), .B(n8427), .C(n7868), .D(n4716), .Z(n4718) );
HS65_LHS_XNOR2X3 U9089 ( .A(\lte_x_59/B[9] ), .B(n5053), .Z(n4870) );
HS65_LHS_XNOR2X3 U9090 ( .A(n5061), .B(\lte_x_59/B[14] ), .Z(n4945) );
HS65_LHS_XNOR2X3 U9091 ( .A(\lte_x_59/B[24] ), .B(n5180), .Z(n5188) );
HS65_LH_NOR3X4 U9092 ( .A(n4815), .B(n4814), .C(n4813), .Z(n4831) );
HS65_LH_NAND3X2 U9093 ( .A(n5021), .B(n3582), .C(\lte_x_59/B[16] ), .Z(n4851) );
HS65_LH_OAI21X3 U9094 ( .A(n4855), .B(n5204), .C(n4854), .Z(n4859) );
HS65_LH_OAI21X3 U9095 ( .A(n4857), .B(n5656), .C(n4856), .Z(n4858) );
HS65_LLS_XOR2X6 U9096 ( .A(n4864), .B(n5633), .Z(n4865) );
HS65_LH_NAND2X7 U9097 ( .A(n7631), .B(n4865), .Z(n4866) );
HS65_LH_OAI21X3 U9098 ( .A(n4870), .B(n5656), .C(n4869), .Z(n4871) );
HS65_LH_CBI4I1X3 U9099 ( .A(n5648), .B(n5053), .C(n5647), .D(\lte_x_59/B[9] ), .Z(n4890) );
HS65_LH_CBI4I1X3 U9100 ( .A(n5648), .B(n5061), .C(n3443), .D(
\lte_x_59/B[14] ), .Z(n4940) );
HS65_LH_NAND2X2 U9101 ( .A(\lte_x_59/B[24] ), .B(n3382), .Z(n5442) );
HS65_LH_CBI4I1X3 U9102 ( .A(n5009), .B(n5586), .C(n5585), .D(n5115), .Z(
n4978) );
HS65_LH_NOR3AX2 U9103 ( .A(n5022), .B(n5023), .C(n4985), .Z(n4987) );
HS65_LH_NOR2X3 U9104 ( .A(n5041), .B(n5040), .Z(n5042) );
HS65_LH_NOR2X2 U9105 ( .A(n4796), .B(n5032), .Z(n5033) );
HS65_LH_NOR2X2 U9106 ( .A(n5088), .B(n5130), .Z(n5036) );
HS65_LH_OAI21X3 U9107 ( .A(n5322), .B(n5042), .C(n5328), .Z(n5098) );
HS65_LH_AND2X4 U9109 ( .A(n5126), .B(n5125), .Z(n5155) );
HS65_LH_CBI4I1X3 U9110 ( .A(n5648), .B(n5136), .C(n3443), .D(\sub_x_53/A[0] ), .Z(n5137) );
HS65_LH_NAND2X7 U9111 ( .A(n5168), .B(n5167), .Z(n5695) );
HS65_LHS_XOR2X3 U9112 ( .A(n5696), .B(n5695), .Z(n5169) );
HS65_LH_CBI4I1X3 U9113 ( .A(n5648), .B(n5180), .C(n5647), .D(
\lte_x_59/B[24] ), .Z(n5181) );
HS65_LH_NAND3X3 U9116 ( .A(n5292), .B(n5362), .C(n5291), .Z(n5354) );
HS65_LH_NOR2X2 U9118 ( .A(n5321), .B(n5320), .Z(n5323) );
HS65_LH_AOI21X2 U9119 ( .A(n5433), .B(n5432), .C(n5431), .Z(n5440) );
HS65_LH_NAND2X2 U9120 ( .A(\lte_x_59/B[21] ), .B(n3377), .Z(n5434) );
HS65_LH_NAND2X2 U9121 ( .A(\lte_x_59/B[22] ), .B(n2869), .Z(n5435) );
HS65_LH_AOI21X2 U9122 ( .A(n5438), .B(n5437), .C(n5436), .Z(n5439) );
HS65_LL_AOI12X2 U9123 ( .A(n5495), .B(n5494), .C(n5493), .Z(n5496) );
HS65_LH_NAND3X5 U9124 ( .A(n5574), .B(n5582), .C(n5562), .Z(n5527) );
HS65_LH_NAND4ABX3 U9125 ( .A(n5512), .B(n5511), .C(n5529), .D(n5536), .Z(
n5513) );
HS65_LL_NAND4ABX3 U9126 ( .A(n5558), .B(n5557), .C(n5556), .D(n5555), .Z(
n5560) );
HS65_LH_OAI21X3 U9127 ( .A(n5578), .B(n5577), .C(n5576), .Z(n5579) );
HS65_LHS_XNOR2X3 U9128 ( .A(\lte_x_59/B[22] ), .B(n5654), .Z(n5655) );
HS65_LHS_XNOR2X3 U9129 ( .A(n5697), .B(n7118), .Z(n5698) );
HS65_LL_AOI22X1 U9130 ( .A(n8868), .B(n9032), .C(n9369), .D(n9047), .Z(n7858) );
HS65_LH_AND2X4 U9131 ( .A(n5850), .B(n5717), .Z(\u_DataPath/toPC2_i [0]) );
HS65_LH_CNIVX3 U9132 ( .A(n5748), .Z(n5749) );
HS65_LH_CNIVX3 U9133 ( .A(n5767), .Z(n5768) );
HS65_LH_CNIVX3 U9134 ( .A(n5817), .Z(n5818) );
HS65_LH_AOI21X2 U9136 ( .A(n5890), .B(n5892), .C(n6042), .Z(n5841) );
HS65_LHS_XOR2X3 U9137 ( .A(n5850), .B(n5849), .Z(\u_DataPath/toPC2_i [1]) );
HS65_LH_OR2X4 U9138 ( .A(n9341), .B(n9202), .Z(n5851) );
HS65_LLS_XNOR2X3 U9139 ( .A(n5857), .B(n5856), .Z(\u_DataPath/toPC2_i [31])
);
HS65_LHS_XNOR2X3 U9140 ( .A(n5905), .B(n5904), .Z(\u_DataPath/toPC2_i [21])
);
HS65_LH_AND2X4 U9141 ( .A(n6049), .B(n5918), .Z(
\u_DataPath/u_execute/resAdd1_i [0]) );
HS65_LH_CNIVX3 U9145 ( .A(n5971), .Z(n5972) );
HS65_LH_CNIVX3 U9146 ( .A(n5995), .Z(n5996) );
HS65_LH_CNIVX3 U9147 ( .A(n5998), .Z(n6002) );
HS65_LH_CNIVX3 U9148 ( .A(n6026), .Z(n6027) );
HS65_LH_AOI21X2 U9149 ( .A(n5890), .B(n6095), .C(n6042), .Z(n6043) );
HS65_LHS_XOR2X3 U9150 ( .A(n6049), .B(n6048), .Z(
\u_DataPath/u_execute/resAdd1_i [1]) );
HS65_LH_NAND2X2 U9152 ( .A(n6099), .B(n6098), .Z(n6104) );
HS65_LHS_XNOR2X3 U9153 ( .A(n6108), .B(n6107), .Z(
\u_DataPath/u_execute/resAdd1_i [24]) );
HS65_LHS_XNOR2X3 U9154 ( .A(n6112), .B(n6111), .Z(
\u_DataPath/u_execute/resAdd1_i [22]) );
HS65_LH_AOI22X1 U9155 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][30] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][30] ), .D(
n6362), .Z(n6130) );
HS65_LH_BFX9 U9156 ( .A(n6162), .Z(n7265) );
HS65_LH_NOR2X6 U9157 ( .A(n6150), .B(n6151), .Z(n6363) );
HS65_LH_NOR4ABX2 U9158 ( .A(n6130), .B(n6129), .C(n6128), .D(n6127), .Z(
n6161) );
HS65_LH_BFX9 U9159 ( .A(n6370), .Z(n7165) );
HS65_LH_BFX9 U9160 ( .A(n6371), .Z(n7273) );
HS65_LH_NOR2X13 U9161 ( .A(n6150), .B(n6133), .Z(n6628) );
HS65_LH_NOR4ABX2 U9162 ( .A(n6137), .B(n6136), .C(n6135), .D(n6134), .Z(
n6160) );
HS65_LH_NOR2X6 U9163 ( .A(n6148), .B(n6139), .Z(n6377) );
HS65_LH_NAND4ABX3 U9164 ( .A(n6144), .B(n6143), .C(n6142), .D(n6141), .Z(
n6159) );
HS65_LH_BFX9 U9165 ( .A(n6383), .Z(n7292) );
HS65_LH_NOR2X6 U9166 ( .A(n6150), .B(n6152), .Z(n7295) );
HS65_LH_NOR2X6 U9167 ( .A(n6153), .B(n6151), .Z(n6385) );
HS65_LH_NAND4ABX3 U9168 ( .A(n6157), .B(n6156), .C(n6155), .D(n6154), .Z(
n6158) );
HS65_LH_AOI22X1 U9169 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][16] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][16] ), .D(
n6362), .Z(n6166) );
HS65_LH_AO22X9 U9170 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][16] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][16] ), .D(
n9371), .Z(n6164) );
HS65_LH_NOR4ABX2 U9171 ( .A(n6166), .B(n6165), .C(n6164), .D(n6163), .Z(
n6184) );
HS65_LH_NOR4ABX2 U9172 ( .A(n6170), .B(n6169), .C(n6168), .D(n6167), .Z(
n6183) );
HS65_LH_NAND4ABX3 U9173 ( .A(n6176), .B(n6175), .C(n6174), .D(n6173), .Z(
n6182) );
HS65_LH_AO22X9 U9174 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][16] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][16] ), .D(
n7292), .Z(n6179) );
HS65_LH_AOI22X1 U9175 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][16] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][16] ), .D(
n6384), .Z(n6178) );
HS65_LH_NAND4ABX3 U9176 ( .A(n6180), .B(n6179), .C(n6178), .D(n6177), .Z(
n6181) );
HS65_LH_NOR4ABX2 U9177 ( .A(n6188), .B(n6187), .C(n6186), .D(n6185), .Z(
n6204) );
HS65_LH_NOR4ABX2 U9178 ( .A(n6192), .B(n6191), .C(n6190), .D(n6189), .Z(
n6203) );
HS65_LH_NAND4ABX3 U9179 ( .A(n6196), .B(n6195), .C(n6194), .D(n6193), .Z(
n6202) );
HS65_LH_AOI22X1 U9180 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][21] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][21] ), .D(
n6384), .Z(n6198) );
HS65_LH_NAND4ABX3 U9181 ( .A(n6200), .B(n6199), .C(n6198), .D(n6197), .Z(
n6201) );
HS65_LH_AO22X9 U9182 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][27] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][27] ), .D(
n9371), .Z(n6206) );
HS65_LH_NOR4ABX2 U9183 ( .A(n6208), .B(n6207), .C(n6206), .D(n6205), .Z(
n6224) );
HS65_LH_NOR4ABX2 U9184 ( .A(n6212), .B(n6211), .C(n6210), .D(n6209), .Z(
n6223) );
HS65_LH_NAND4ABX3 U9185 ( .A(n6216), .B(n6215), .C(n6214), .D(n6213), .Z(
n6222) );
HS65_LH_AOI22X1 U9186 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][27] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][27] ), .D(
n6384), .Z(n6218) );
HS65_LH_NAND4ABX3 U9187 ( .A(n6220), .B(n6219), .C(n6218), .D(n6217), .Z(
n6221) );
HS65_LH_AO22X9 U9188 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][23] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][23] ), .D(
n9372), .Z(n6226) );
HS65_LH_NOR4ABX2 U9189 ( .A(n6228), .B(n6227), .C(n6226), .D(n6225), .Z(
n6244) );
HS65_LH_NOR4ABX2 U9190 ( .A(n6232), .B(n6231), .C(n6230), .D(n6229), .Z(
n6243) );
HS65_LH_NAND4ABX3 U9191 ( .A(n6236), .B(n6235), .C(n6234), .D(n6233), .Z(
n6242) );
HS65_LH_BFX9 U9192 ( .A(n6317), .Z(n7293) );
HS65_LH_AOI22X1 U9193 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][23] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][23] ), .D(
n6384), .Z(n6238) );
HS65_LH_NAND4ABX3 U9194 ( .A(n6240), .B(n6239), .C(n6238), .D(n6237), .Z(
n6241) );
HS65_LH_AO22X9 U9195 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][11] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][11] ), .D(
n9372), .Z(n6246) );
HS65_LH_NOR4ABX2 U9196 ( .A(n6248), .B(n6247), .C(n6246), .D(n6245), .Z(
n6264) );
HS65_LH_NOR4ABX2 U9197 ( .A(n6252), .B(n6251), .C(n6250), .D(n6249), .Z(
n6263) );
HS65_LH_NAND4ABX3 U9198 ( .A(n6256), .B(n6255), .C(n6254), .D(n6253), .Z(
n6262) );
HS65_LH_AOI22X1 U9199 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][11] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][11] ), .D(
n6384), .Z(n6258) );
HS65_LH_NAND4ABX3 U9200 ( .A(n6260), .B(n6259), .C(n6258), .D(n6257), .Z(
n6261) );
HS65_LH_AOI22X1 U9201 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][22] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][22] ), .D(
n6362), .Z(n6268) );
HS65_LH_NOR4ABX2 U9202 ( .A(n6268), .B(n6267), .C(n6266), .D(n6265), .Z(
n6284) );
HS65_LH_NOR4ABX2 U9203 ( .A(n6272), .B(n6271), .C(n6270), .D(n6269), .Z(
n6283) );
HS65_LH_NAND4ABX3 U9204 ( .A(n6276), .B(n6275), .C(n6274), .D(n6273), .Z(
n6282) );
HS65_LH_AOI22X1 U9205 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][22] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][22] ), .D(
n6384), .Z(n6278) );
HS65_LH_NAND4ABX3 U9206 ( .A(n6280), .B(n6279), .C(n6278), .D(n6277), .Z(
n6281) );
HS65_LH_NOR4ABX2 U9207 ( .A(n6288), .B(n6287), .C(n6286), .D(n6285), .Z(
n6304) );
HS65_LH_NOR4ABX2 U9208 ( .A(n6292), .B(n6291), .C(n6290), .D(n6289), .Z(
n6303) );
HS65_LH_NAND4ABX3 U9209 ( .A(n6296), .B(n6295), .C(n6294), .D(n6293), .Z(
n6302) );
HS65_LH_AOI22X1 U9210 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][24] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][24] ), .D(
n6384), .Z(n6298) );
HS65_LH_NAND4ABX3 U9211 ( .A(n6300), .B(n6299), .C(n6298), .D(n6297), .Z(
n6301) );
HS65_LH_NOR4ABX2 U9212 ( .A(n6308), .B(n6307), .C(n6306), .D(n6305), .Z(
n6325) );
HS65_LH_NOR4ABX2 U9213 ( .A(n6312), .B(n6311), .C(n6310), .D(n6309), .Z(
n6324) );
HS65_LH_NAND4ABX3 U9214 ( .A(n6316), .B(n6315), .C(n6314), .D(n6313), .Z(
n6323) );
HS65_LH_AOI22X1 U9215 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][14] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][14] ), .D(
n6384), .Z(n6319) );
HS65_LH_NAND4ABX3 U9216 ( .A(n6321), .B(n6320), .C(n6319), .D(n6318), .Z(
n6322) );
HS65_LH_NAND3X5 U9217 ( .A(\u_DataPath/jaddr_i [19]), .B(
\u_DataPath/jaddr_i [18]), .C(n2881), .Z(n6334) );
HS65_LH_NOR2X6 U9218 ( .A(\u_DataPath/jaddr_i [19]), .B(n8184), .Z(n6340) );
HS65_LH_NOR4ABX2 U9220 ( .A(n6330), .B(n6329), .C(n6328), .D(n6327), .Z(
n6361) );
HS65_LH_NOR2X6 U9221 ( .A(n6353), .B(n6332), .Z(n6957) );
HS65_LH_AOI22X1 U9222 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][18] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][18] ), .D(
n6957), .Z(n6337) );
HS65_LH_BFX9 U9223 ( .A(n6747), .Z(n7517) );
HS65_LH_NOR2X6 U9224 ( .A(n6350), .B(n6333), .Z(n6675) );
HS65_LH_NOR2X6 U9225 ( .A(n6350), .B(n6334), .Z(n7319) );
HS65_LH_NOR4ABX2 U9226 ( .A(n6338), .B(n6337), .C(n6336), .D(n6335), .Z(
n6360) );
HS65_LH_NAND2X7 U9227 ( .A(\u_DataPath/jaddr_i [20]), .B(n6340), .Z(n6342)
);
HS65_LH_AO22X9 U9228 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][18] ), .B(n7522),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][18] ), .Z(n6346)
);
HS65_LH_NOR2X6 U9230 ( .A(n6353), .B(n6342), .Z(n6753) );
HS65_LH_NOR2X6 U9231 ( .A(n6349), .B(n6342), .Z(n6684) );
HS65_LH_NAND4ABX3 U9232 ( .A(n6346), .B(n6345), .C(n6344), .D(n6343), .Z(
n6359) );
HS65_LH_NAND2X7 U9233 ( .A(n8184), .B(n6347), .Z(n6351) );
HS65_LH_NOR2X6 U9234 ( .A(n6348), .B(n6351), .Z(n7330) );
HS65_LH_NOR2X6 U9235 ( .A(n6349), .B(n6351), .Z(n7329) );
HS65_LH_NAND2X7 U9236 ( .A(\u_DataPath/jaddr_i [18]), .B(n6347), .Z(n6352)
);
HS65_LH_NOR2X6 U9237 ( .A(n6348), .B(n6352), .Z(n7332) );
HS65_LH_NOR2X6 U9238 ( .A(n6350), .B(n6351), .Z(n7331) );
HS65_LH_NOR2X6 U9239 ( .A(n6353), .B(n6351), .Z(n6690) );
HS65_LH_NAND4ABX3 U9240 ( .A(n6357), .B(n6356), .C(n6355), .D(n6354), .Z(
n6358) );
HS65_LH_BFX9 U9241 ( .A(n6617), .Z(n6595) );
HS65_LH_BFX9 U9242 ( .A(n6362), .Z(n7264) );
HS65_LH_AO22X9 U9243 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][15] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][15] ), .D(
n7266), .Z(n6367) );
HS65_LH_AO22X9 U9244 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][15] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][15] ), .D(
n7267), .Z(n6366) );
HS65_LH_NOR4ABX2 U9245 ( .A(n6369), .B(n6368), .C(n6367), .D(n6366), .Z(
n6393) );
HS65_LH_AO22X9 U9247 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][15] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][15] ), .D(
n7274), .Z(n6373) );
HS65_LH_NOR4ABX2 U9248 ( .A(n6375), .B(n6374), .C(n6373), .D(n6372), .Z(
n6392) );
HS65_LH_NAND4ABX3 U9249 ( .A(n6381), .B(n6380), .C(n6379), .D(n6378), .Z(
n6391) );
HS65_LH_AO22X9 U9250 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][15] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][15] ), .D(
n7291), .Z(n6389) );
HS65_LH_BFX9 U9251 ( .A(n6384), .Z(n7294) );
HS65_LH_NAND4ABX3 U9252 ( .A(n6389), .B(n6388), .C(n6387), .D(n6386), .Z(
n6390) );
HS65_LH_AO22X9 U9253 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][10] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][10] ), .D(
n7266), .Z(n6395) );
HS65_LH_AO22X9 U9254 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][10] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][10] ), .D(
n7267), .Z(n6394) );
HS65_LH_NOR4ABX2 U9255 ( .A(n6397), .B(n6396), .C(n6395), .D(n6394), .Z(
n6413) );
HS65_LH_AO22X9 U9256 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][10] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][10] ), .D(
n7274), .Z(n6399) );
HS65_LH_NOR4ABX2 U9257 ( .A(n6401), .B(n6400), .C(n6399), .D(n6398), .Z(
n6412) );
HS65_LH_NAND4ABX3 U9258 ( .A(n6405), .B(n6404), .C(n6403), .D(n6402), .Z(
n6411) );
HS65_LH_NAND4ABX3 U9260 ( .A(n6409), .B(n6408), .C(n6407), .D(n6406), .Z(
n6410) );
HS65_LH_AO22X9 U9261 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][0] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][0] ), .D(n7266), .Z(n6415) );
HS65_LH_AO22X9 U9262 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][0] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][0] ), .D(n7267), .Z(n6414) );
HS65_LH_NOR4ABX2 U9263 ( .A(n6417), .B(n6416), .C(n6415), .D(n6414), .Z(
n6434) );
HS65_LH_AOI22X1 U9264 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][0] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][0] ), .D(
n6600), .Z(n6421) );
HS65_LH_AO22X9 U9265 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][0] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][0] ), .D(
n7274), .Z(n6419) );
HS65_LH_NOR4ABX2 U9266 ( .A(n6421), .B(n6420), .C(n6419), .D(n6418), .Z(
n6433) );
HS65_LH_NAND4ABX3 U9267 ( .A(n6425), .B(n6424), .C(n6423), .D(n6422), .Z(
n6432) );
HS65_LH_AOI22X3 U9269 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][0] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][0] ), .D(n7294), .Z(n6428) );
HS65_LH_NAND4ABX3 U9270 ( .A(n6430), .B(n6429), .C(n6428), .D(n6427), .Z(
n6431) );
HS65_LH_AO22X9 U9271 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][7] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][7] ), .D(n7266), .Z(n6436) );
HS65_LH_NOR4ABX2 U9273 ( .A(n6438), .B(n6437), .C(n6436), .D(n6435), .Z(
n6454) );
HS65_LH_AO22X9 U9274 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][7] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][7] ), .D(
n7274), .Z(n6440) );
HS65_LH_NOR4ABX2 U9275 ( .A(n6442), .B(n6441), .C(n6440), .D(n6439), .Z(
n6453) );
HS65_LH_NAND4ABX3 U9276 ( .A(n6446), .B(n6445), .C(n6444), .D(n6443), .Z(
n6452) );
HS65_LH_AOI22X3 U9278 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][7] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][7] ), .D(n7294), .Z(n6448) );
HS65_LH_NAND4ABX3 U9279 ( .A(n6450), .B(n6449), .C(n6448), .D(n6447), .Z(
n6451) );
HS65_LH_AO22X9 U9280 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][8] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][8] ), .D(n7266), .Z(n6456) );
HS65_LH_NOR4ABX2 U9282 ( .A(n6458), .B(n6457), .C(n6456), .D(n6455), .Z(
n6474) );
HS65_LH_AOI22X1 U9283 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][8] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][8] ), .D(
n6600), .Z(n6462) );
HS65_LH_AO22X9 U9284 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][8] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][8] ), .D(
n7274), .Z(n6460) );
HS65_LH_NOR4ABX2 U9285 ( .A(n6462), .B(n6461), .C(n6460), .D(n6459), .Z(
n6473) );
HS65_LH_NAND4ABX3 U9286 ( .A(n6466), .B(n6465), .C(n6464), .D(n6463), .Z(
n6472) );
HS65_LH_AO22X9 U9287 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][8] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][8] ), .D(n7291), .Z(n6470) );
HS65_LH_AOI22X3 U9288 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][8] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][8] ), .D(n7294), .Z(n6468) );
HS65_LH_NAND4ABX3 U9289 ( .A(n6470), .B(n6469), .C(n6468), .D(n6467), .Z(
n6471) );
HS65_LH_NOR4ABX2 U9290 ( .A(n6478), .B(n6477), .C(n6476), .D(n6475), .Z(
n6494) );
HS65_LH_AOI22X1 U9291 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][6] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][6] ), .D(
n6600), .Z(n6482) );
HS65_LH_NOR4ABX2 U9292 ( .A(n6482), .B(n6481), .C(n6480), .D(n6479), .Z(
n6493) );
HS65_LH_NAND4ABX3 U9293 ( .A(n6486), .B(n6485), .C(n6484), .D(n6483), .Z(
n6492) );
HS65_LH_NAND4ABX3 U9294 ( .A(n6490), .B(n6489), .C(n6488), .D(n6487), .Z(
n6491) );
HS65_LH_AO22X9 U9295 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][26] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][26] ), .D(
n7266), .Z(n6496) );
HS65_LH_AO22X9 U9296 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][26] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][26] ), .D(
n7267), .Z(n6495) );
HS65_LH_NOR4ABX2 U9297 ( .A(n6498), .B(n6497), .C(n6496), .D(n6495), .Z(
n6514) );
HS65_LH_AO22X9 U9298 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][26] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][26] ), .D(
n7274), .Z(n6500) );
HS65_LH_NOR4ABX2 U9299 ( .A(n6502), .B(n6501), .C(n6500), .D(n6499), .Z(
n6513) );
HS65_LH_NAND4ABX3 U9300 ( .A(n6506), .B(n6505), .C(n6504), .D(n6503), .Z(
n6512) );
HS65_LH_AO22X9 U9301 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][26] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][26] ), .D(
n7291), .Z(n6510) );
HS65_LH_AOI22X3 U9302 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][26] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][26] ), .D(
n7294), .Z(n6508) );
HS65_LH_NAND4ABX3 U9303 ( .A(n6510), .B(n6509), .C(n6508), .D(n6507), .Z(
n6511) );
HS65_LH_AO22X9 U9304 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][19] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][19] ), .D(
n7266), .Z(n6516) );
HS65_LH_NOR4ABX2 U9306 ( .A(n6518), .B(n6517), .C(n6516), .D(n6515), .Z(
n6534) );
HS65_LH_AO22X9 U9307 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][19] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][19] ), .D(
n7274), .Z(n6520) );
HS65_LH_NOR4ABX2 U9308 ( .A(n6522), .B(n6521), .C(n6520), .D(n6519), .Z(
n6533) );
HS65_LH_NAND4ABX3 U9309 ( .A(n6526), .B(n6525), .C(n6524), .D(n6523), .Z(
n6532) );
HS65_LH_AO22X9 U9310 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][19] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][19] ), .D(
n7291), .Z(n6530) );
HS65_LH_AOI22X3 U9311 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][19] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][19] ), .D(
n7294), .Z(n6528) );
HS65_LH_NAND4ABX3 U9312 ( .A(n6530), .B(n6529), .C(n6528), .D(n6527), .Z(
n6531) );
HS65_LH_AO22X9 U9313 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][12] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][12] ), .D(
n7266), .Z(n6536) );
HS65_LH_NOR4ABX2 U9315 ( .A(n6538), .B(n6537), .C(n6536), .D(n6535), .Z(
n6554) );
HS65_LH_AO22X9 U9316 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][12] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][12] ), .D(
n7274), .Z(n6540) );
HS65_LH_NOR4ABX2 U9317 ( .A(n6542), .B(n6541), .C(n6540), .D(n6539), .Z(
n6553) );
HS65_LH_NAND4ABX3 U9318 ( .A(n6546), .B(n6545), .C(n6544), .D(n6543), .Z(
n6552) );
HS65_LH_AOI22X3 U9320 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][12] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][12] ), .D(
n7294), .Z(n6548) );
HS65_LH_NAND4ABX3 U9321 ( .A(n6550), .B(n6549), .C(n6548), .D(n6547), .Z(
n6551) );
HS65_LH_AO22X9 U9322 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][2] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][2] ), .D(n9371), .Z(n6556) );
HS65_LH_NOR4ABX2 U9324 ( .A(n6558), .B(n6557), .C(n6556), .D(n6555), .Z(
n6574) );
HS65_LH_AOI22X1 U9325 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][2] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][2] ), .D(
n6600), .Z(n6562) );
HS65_LH_AO22X9 U9326 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][2] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][2] ), .D(
n6627), .Z(n6560) );
HS65_LH_AO22X9 U9327 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][2] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][2] ), .D(
n6629), .Z(n6559) );
HS65_LH_NOR4ABX2 U9328 ( .A(n6562), .B(n6561), .C(n6560), .D(n6559), .Z(
n6573) );
HS65_LH_NAND4ABX3 U9329 ( .A(n6566), .B(n6565), .C(n6564), .D(n6563), .Z(
n6572) );
HS65_LH_AO22X9 U9330 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][2] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][2] ), .D(n7291), .Z(n6570) );
HS65_LH_AOI22X3 U9331 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][2] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][2] ), .D(n7294), .Z(n6568) );
HS65_LH_NAND4ABX3 U9332 ( .A(n6570), .B(n6569), .C(n6568), .D(n6567), .Z(
n6571) );
HS65_LH_AO22X9 U9333 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][3] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][3] ), .D(n7266), .Z(n6576) );
HS65_LH_AO22X9 U9334 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][3] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][3] ), .D(n7267), .Z(n6575) );
HS65_LH_NOR4ABX2 U9335 ( .A(n6578), .B(n6577), .C(n6576), .D(n6575), .Z(
n6594) );
HS65_LH_NOR4ABX2 U9336 ( .A(n6582), .B(n6581), .C(n6580), .D(n6579), .Z(
n6593) );
HS65_LH_NAND4ABX3 U9337 ( .A(n6586), .B(n6585), .C(n6584), .D(n6583), .Z(
n6592) );
HS65_LH_AO22X9 U9338 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][3] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][3] ), .D(n7291), .Z(n6590) );
HS65_LH_AOI22X3 U9339 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][3] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][3] ), .D(n7294), .Z(n6588) );
HS65_LH_NAND4ABX3 U9340 ( .A(n6590), .B(n6589), .C(n6588), .D(n6587), .Z(
n6591) );
HS65_LH_AO22X9 U9341 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][1] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][1] ), .D(n6619), .Z(n6596) );
HS65_LH_NOR4ABX2 U9342 ( .A(n6599), .B(n6598), .C(n6597), .D(n6596), .Z(
n6616) );
HS65_LH_AO22X9 U9343 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][1] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][1] ), .D(
n6629), .Z(n6601) );
HS65_LH_NOR4ABX2 U9344 ( .A(n6604), .B(n6603), .C(n6602), .D(n6601), .Z(
n6615) );
HS65_LH_NAND4ABX3 U9345 ( .A(n6608), .B(n6607), .C(n6606), .D(n6605), .Z(
n6614) );
HS65_LH_AO22X9 U9346 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][1] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][1] ), .D(n7291), .Z(n6612) );
HS65_LH_AOI22X3 U9347 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][1] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][1] ), .D(n7294), .Z(n6610) );
HS65_LH_NAND4ABX3 U9348 ( .A(n6612), .B(n6611), .C(n6610), .D(n6609), .Z(
n6613) );
HS65_LH_BFX9 U9349 ( .A(n9370), .Z(n7266) );
HS65_LH_AO22X9 U9350 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][4] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][4] ), .D(n7266), .Z(n6621) );
HS65_LH_BFX9 U9351 ( .A(n6619), .Z(n7267) );
HS65_LH_NOR4ABX2 U9353 ( .A(n6623), .B(n6622), .C(n6621), .D(n6620), .Z(
n6649) );
HS65_LH_BFX9 U9354 ( .A(n6626), .Z(n7275) );
HS65_LH_AO22X9 U9355 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][4] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][4] ), .D(
n7274), .Z(n6631) );
HS65_LH_BFX9 U9356 ( .A(n6628), .Z(n7277) );
HS65_LH_BFX9 U9357 ( .A(n6629), .Z(n7276) );
HS65_LH_AO22X9 U9358 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][4] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][4] ), .D(
n7276), .Z(n6630) );
HS65_LH_NOR4ABX2 U9359 ( .A(n6633), .B(n6632), .C(n6631), .D(n6630), .Z(
n6648) );
HS65_LH_NAND4ABX3 U9360 ( .A(n6641), .B(n6640), .C(n6639), .D(n6638), .Z(
n6647) );
HS65_LH_NAND4ABX3 U9362 ( .A(n6645), .B(n6644), .C(n6643), .D(n6642), .Z(
n6646) );
HS65_LH_AO22X9 U9363 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][18] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][18] ), .D(
n7266), .Z(n6651) );
HS65_LH_AO22X9 U9364 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][18] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][18] ), .D(
n7267), .Z(n6650) );
HS65_LH_NOR4ABX2 U9365 ( .A(n6653), .B(n6652), .C(n6651), .D(n6650), .Z(
n6669) );
HS65_LH_AO22X9 U9367 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][18] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][18] ), .D(
n7276), .Z(n6654) );
HS65_LH_NOR4ABX2 U9368 ( .A(n6657), .B(n6656), .C(n6655), .D(n6654), .Z(
n6668) );
HS65_LH_NAND4ABX3 U9369 ( .A(n6661), .B(n6660), .C(n6659), .D(n6658), .Z(
n6667) );
HS65_LH_AOI22X3 U9370 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][18] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][18] ), .D(
n7294), .Z(n6663) );
HS65_LH_NAND4ABX3 U9371 ( .A(n6665), .B(n6664), .C(n6663), .D(n6662), .Z(
n6666) );
HS65_LH_NOR4ABX2 U9372 ( .A(n6674), .B(n6673), .C(n6672), .D(n6671), .Z(
n6698) );
HS65_LH_NOR4ABX2 U9373 ( .A(n6679), .B(n6678), .C(n6677), .D(n6676), .Z(
n6697) );
HS65_LH_BFX9 U9374 ( .A(n6752), .Z(n7439) );
HS65_LH_NAND4ABX3 U9375 ( .A(n6688), .B(n6687), .C(n6686), .D(n6685), .Z(
n6696) );
HS65_LH_NAND4ABX3 U9376 ( .A(n6694), .B(n6693), .C(n6692), .D(n6691), .Z(
n6695) );
HS65_LH_NOR4ABX2 U9378 ( .A(n6702), .B(n6701), .C(n6700), .D(n6699), .Z(
n6718) );
HS65_LH_NOR4ABX2 U9379 ( .A(n6706), .B(n6705), .C(n6704), .D(n6703), .Z(
n6717) );
HS65_LH_NAND4ABX3 U9380 ( .A(n6710), .B(n6709), .C(n6708), .D(n6707), .Z(
n6716) );
HS65_LH_NAND4ABX3 U9381 ( .A(n6714), .B(n6713), .C(n6712), .D(n6711), .Z(
n6715) );
HS65_LH_NOR4ABX2 U9383 ( .A(n6722), .B(n6721), .C(n6720), .D(n6719), .Z(
n6738) );
HS65_LH_NOR4ABX2 U9384 ( .A(n6726), .B(n6725), .C(n6724), .D(n6723), .Z(
n6737) );
HS65_LH_NAND4ABX3 U9385 ( .A(n6730), .B(n6729), .C(n6728), .D(n6727), .Z(
n6736) );
HS65_LH_NAND4ABX3 U9386 ( .A(n6734), .B(n6733), .C(n6732), .D(n6731), .Z(
n6735) );
HS65_LH_NOR4ABX2 U9388 ( .A(n6744), .B(n6743), .C(n6742), .D(n6741), .Z(
n6766) );
HS65_LH_AOI22X1 U9389 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][19] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][19] ), .D(
n6957), .Z(n6750) );
HS65_LH_NOR4ABX2 U9390 ( .A(n6751), .B(n6750), .C(n6749), .D(n6748), .Z(
n6765) );
HS65_LH_NAND4ABX3 U9391 ( .A(n6758), .B(n6757), .C(n6756), .D(n6755), .Z(
n6764) );
HS65_LH_NAND4ABX3 U9392 ( .A(n6762), .B(n6761), .C(n6760), .D(n6759), .Z(
n6763) );
HS65_LH_NOR4ABX2 U9393 ( .A(n6770), .B(n6769), .C(n6768), .D(n6767), .Z(
n6786) );
HS65_LH_NOR4ABX2 U9394 ( .A(n6774), .B(n6773), .C(n6772), .D(n6771), .Z(
n6785) );
HS65_LH_NAND4ABX3 U9395 ( .A(n6778), .B(n6777), .C(n6776), .D(n6775), .Z(
n6784) );
HS65_LH_NAND4ABX3 U9396 ( .A(n6782), .B(n6781), .C(n6780), .D(n6779), .Z(
n6783) );
HS65_LL_NOR4ABX2 U9397 ( .A(n6786), .B(n6785), .C(n6784), .D(n6783), .Z(
n8261) );
HS65_LH_NOR4ABX2 U9398 ( .A(n6790), .B(n6789), .C(n6788), .D(n6787), .Z(
n6806) );
HS65_LH_NOR4ABX2 U9399 ( .A(n6794), .B(n6793), .C(n6792), .D(n6791), .Z(
n6805) );
HS65_LH_NAND4ABX3 U9400 ( .A(n6798), .B(n6797), .C(n6796), .D(n6795), .Z(
n6804) );
HS65_LH_NAND4ABX3 U9401 ( .A(n6802), .B(n6801), .C(n6800), .D(n6799), .Z(
n6803) );
HS65_LH_NOR4ABX2 U9402 ( .A(n6810), .B(n6809), .C(n6808), .D(n6807), .Z(
n6826) );
HS65_LH_NOR4ABX2 U9403 ( .A(n6814), .B(n6813), .C(n6812), .D(n6811), .Z(
n6825) );
HS65_LH_NAND4ABX3 U9404 ( .A(n6818), .B(n6817), .C(n6816), .D(n6815), .Z(
n6824) );
HS65_LH_NAND4ABX3 U9405 ( .A(n6822), .B(n6821), .C(n6820), .D(n6819), .Z(
n6823) );
HS65_LH_NOR4ABX2 U9407 ( .A(n6830), .B(n6829), .C(n6828), .D(n6827), .Z(
n6846) );
HS65_LH_NOR4ABX2 U9408 ( .A(n6834), .B(n6833), .C(n6832), .D(n6831), .Z(
n6845) );
HS65_LH_NAND4ABX3 U9409 ( .A(n6838), .B(n6837), .C(n6836), .D(n6835), .Z(
n6844) );
HS65_LH_NAND4ABX3 U9410 ( .A(n6842), .B(n6841), .C(n6840), .D(n6839), .Z(
n6843) );
HS65_LH_AO22X9 U9412 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][20] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][20] ), .D(
n7267), .Z(n6847) );
HS65_LH_NOR4ABX2 U9413 ( .A(n6850), .B(n6849), .C(n6848), .D(n6847), .Z(
n6866) );
HS65_LH_AO22X9 U9414 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][20] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][20] ), .D(
n7274), .Z(n6852) );
HS65_LH_NOR4ABX2 U9416 ( .A(n6854), .B(n6853), .C(n6852), .D(n6851), .Z(
n6865) );
HS65_LH_NAND4ABX3 U9417 ( .A(n6858), .B(n6857), .C(n6856), .D(n6855), .Z(
n6864) );
HS65_LH_AO22X9 U9418 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][20] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][20] ), .D(
n7291), .Z(n6862) );
HS65_LH_AOI22X3 U9419 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][20] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][20] ), .D(
n7294), .Z(n6860) );
HS65_LH_NAND4ABX3 U9420 ( .A(n6862), .B(n6861), .C(n6860), .D(n6859), .Z(
n6863) );
HS65_LH_AO22X9 U9421 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][31] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][31] ), .D(
n7266), .Z(n6868) );
HS65_LH_AO22X9 U9422 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][31] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][31] ), .D(
n7267), .Z(n6867) );
HS65_LH_NOR4ABX2 U9423 ( .A(n6870), .B(n6869), .C(n6868), .D(n6867), .Z(
n6886) );
HS65_LH_AOI22X1 U9424 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][31] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][31] ), .D(
n6600), .Z(n6874) );
HS65_LH_AO22X9 U9425 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][31] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][31] ), .D(
n7274), .Z(n6872) );
HS65_LH_AO22X9 U9426 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][31] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][31] ), .D(
n7276), .Z(n6871) );
HS65_LH_NOR4ABX2 U9427 ( .A(n6874), .B(n6873), .C(n6872), .D(n6871), .Z(
n6885) );
HS65_LH_NAND4ABX3 U9428 ( .A(n6878), .B(n6877), .C(n6876), .D(n6875), .Z(
n6884) );
HS65_LH_NAND4ABX3 U9429 ( .A(n6882), .B(n6881), .C(n6880), .D(n6879), .Z(
n6883) );
HS65_LH_AO22X9 U9430 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][17] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][17] ), .D(
n7266), .Z(n6888) );
HS65_LH_NOR4ABX2 U9432 ( .A(n6890), .B(n6889), .C(n6888), .D(n6887), .Z(
n6906) );
HS65_LH_AOI22X1 U9433 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][17] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][17] ), .D(
n6600), .Z(n6894) );
HS65_LH_AO22X9 U9434 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][17] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][17] ), .D(
n7274), .Z(n6892) );
HS65_LH_AO22X9 U9435 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][17] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][17] ), .D(
n7276), .Z(n6891) );
HS65_LH_NOR4ABX2 U9436 ( .A(n6894), .B(n6893), .C(n6892), .D(n6891), .Z(
n6905) );
HS65_LH_NAND4ABX3 U9437 ( .A(n6898), .B(n6897), .C(n6896), .D(n6895), .Z(
n6904) );
HS65_LH_NAND4ABX3 U9439 ( .A(n6902), .B(n6901), .C(n6900), .D(n6899), .Z(
n6903) );
HS65_LH_AO22X9 U9440 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][28] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][28] ), .D(
n7266), .Z(n6908) );
HS65_LH_NOR4ABX2 U9442 ( .A(n6910), .B(n6909), .C(n6908), .D(n6907), .Z(
n6926) );
HS65_LH_AO22X9 U9443 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][28] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][28] ), .D(
n7274), .Z(n6912) );
HS65_LH_AO22X9 U9444 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][28] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][28] ), .D(
n7276), .Z(n6911) );
HS65_LH_NOR4ABX2 U9445 ( .A(n6914), .B(n6913), .C(n6912), .D(n6911), .Z(
n6925) );
HS65_LH_NAND4ABX3 U9446 ( .A(n6918), .B(n6917), .C(n6916), .D(n6915), .Z(
n6924) );
HS65_LH_AO22X9 U9447 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][28] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][28] ), .D(
n7291), .Z(n6922) );
HS65_LH_AOI22X3 U9448 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][28] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][28] ), .D(
n7294), .Z(n6920) );
HS65_LH_NAND4ABX3 U9449 ( .A(n6922), .B(n6921), .C(n6920), .D(n6919), .Z(
n6923) );
HS65_LH_AO22X9 U9450 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][5] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][5] ), .D(n7266), .Z(n6930) );
HS65_LH_AO22X9 U9451 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][5] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][5] ), .D(n7267), .Z(n6929) );
HS65_LH_NOR4ABX2 U9452 ( .A(n6932), .B(n6931), .C(n6930), .D(n6929), .Z(
n6950) );
HS65_LH_AO22X9 U9453 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][5] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][5] ), .D(
n7274), .Z(n6934) );
HS65_LH_AO22X9 U9454 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][5] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][5] ), .D(
n7276), .Z(n6933) );
HS65_LH_NOR4ABX2 U9455 ( .A(n6936), .B(n6935), .C(n6934), .D(n6933), .Z(
n6949) );
HS65_LH_NAND4ABX3 U9456 ( .A(n6940), .B(n6939), .C(n6938), .D(n6937), .Z(
n6948) );
HS65_LH_AOI22X3 U9457 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][5] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][5] ), .D(n7294), .Z(n6944) );
HS65_LH_NAND4ABX3 U9458 ( .A(n6946), .B(n6945), .C(n6944), .D(n6943), .Z(
n6947) );
HS65_LH_NOR4ABX2 U9459 ( .A(n6956), .B(n6955), .C(n6954), .D(n6953), .Z(
n6975) );
HS65_LH_NOR4ABX2 U9460 ( .A(n6961), .B(n6960), .C(n6959), .D(n6958), .Z(
n6974) );
HS65_LH_NAND4ABX3 U9461 ( .A(n6965), .B(n6964), .C(n6963), .D(n6962), .Z(
n6973) );
HS65_LH_NAND4ABX3 U9462 ( .A(n6971), .B(n6970), .C(n6969), .D(n6968), .Z(
n6972) );
HS65_LH_NOR4ABX2 U9463 ( .A(n6979), .B(n6978), .C(n6977), .D(n6976), .Z(
n6995) );
HS65_LH_AOI22X1 U9464 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][13] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][13] ), .D(
n6957), .Z(n6982) );
HS65_LH_NOR4ABX2 U9465 ( .A(n6983), .B(n6982), .C(n6981), .D(n6980), .Z(
n6994) );
HS65_LH_NAND4ABX3 U9466 ( .A(n6987), .B(n6986), .C(n6985), .D(n6984), .Z(
n6993) );
HS65_LH_NAND4ABX3 U9467 ( .A(n6991), .B(n6990), .C(n6989), .D(n6988), .Z(
n6992) );
HS65_LH_NOR4ABX2 U9468 ( .A(n6999), .B(n6998), .C(n6997), .D(n6996), .Z(
n7015) );
HS65_LH_AOI22X1 U9469 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][22] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][22] ), .D(
n6957), .Z(n7002) );
HS65_LH_NOR4ABX2 U9470 ( .A(n7003), .B(n7002), .C(n7001), .D(n7000), .Z(
n7014) );
HS65_LH_NAND4ABX3 U9471 ( .A(n7007), .B(n7006), .C(n7005), .D(n7004), .Z(
n7013) );
HS65_LH_NAND4ABX3 U9472 ( .A(n7011), .B(n7010), .C(n7009), .D(n7008), .Z(
n7012) );
HS65_LH_NOR4ABX2 U9473 ( .A(n7019), .B(n7018), .C(n7017), .D(n7016), .Z(
n7035) );
HS65_LH_AOI22X1 U9474 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][9] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][9] ), .D(n6957), .Z(n7022) );
HS65_LH_NOR4ABX2 U9475 ( .A(n7023), .B(n7022), .C(n7021), .D(n7020), .Z(
n7034) );
HS65_LH_NAND4ABX3 U9476 ( .A(n7027), .B(n7026), .C(n7025), .D(n7024), .Z(
n7033) );
HS65_LH_NAND4ABX3 U9477 ( .A(n7031), .B(n7030), .C(n7029), .D(n7028), .Z(
n7032) );
HS65_LH_NOR4ABX2 U9478 ( .A(n7039), .B(n7038), .C(n7037), .D(n7036), .Z(
n7055) );
HS65_LH_AOI22X1 U9479 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][25] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][25] ), .D(
n6957), .Z(n7042) );
HS65_LH_NOR4ABX2 U9480 ( .A(n7043), .B(n7042), .C(n7041), .D(n7040), .Z(
n7054) );
HS65_LH_NAND4ABX3 U9481 ( .A(n7047), .B(n7046), .C(n7045), .D(n7044), .Z(
n7053) );
HS65_LH_NAND4ABX3 U9482 ( .A(n7051), .B(n7050), .C(n7049), .D(n7048), .Z(
n7052) );
HS65_LH_NOR4ABX2 U9483 ( .A(n7059), .B(n7058), .C(n7057), .D(n7056), .Z(
n7075) );
HS65_LH_AOI22X1 U9484 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][11] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][11] ), .D(
n6957), .Z(n7062) );
HS65_LH_NOR4ABX2 U9485 ( .A(n7063), .B(n7062), .C(n7061), .D(n7060), .Z(
n7074) );
HS65_LH_NAND4ABX3 U9486 ( .A(n7067), .B(n7066), .C(n7065), .D(n7064), .Z(
n7073) );
HS65_LH_NAND4ABX3 U9487 ( .A(n7071), .B(n7070), .C(n7069), .D(n7068), .Z(
n7072) );
HS65_LH_NOR2X6 U9488 ( .A(n7078), .B(n7077), .Z(n7082) );
HS65_LH_NOR2X6 U9489 ( .A(n7080), .B(n7079), .Z(n7081) );
HS65_LH_NAND2X7 U9491 ( .A(n7088), .B(n7087), .Z(n7093) );
HS65_LH_NOR2X6 U9492 ( .A(\u_DataPath/cw_exmem_i [5]), .B(
\u_DataPath/cw_exmem_i [3]), .Z(n7097) );
HS65_LH_NAND2X7 U9493 ( .A(n7098), .B(n7097), .Z(n7114) );
HS65_LH_NOR2X2 U9494 ( .A(n8426), .B(n9401), .Z(n8564) );
HS65_LH_AO22X9 U9495 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][9] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][9] ), .D(n9371), .Z(n7124) );
HS65_LH_NOR4ABX2 U9496 ( .A(n7126), .B(n7125), .C(n7124), .D(n7123), .Z(
n7142) );
HS65_LH_NOR4ABX2 U9498 ( .A(n7130), .B(n7129), .C(n7128), .D(n7127), .Z(
n7141) );
HS65_LH_NAND4ABX3 U9499 ( .A(n7134), .B(n7133), .C(n7132), .D(n7131), .Z(
n7140) );
HS65_LH_AOI22X1 U9501 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][9] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][9] ), .D(n7294), .Z(n7136) );
HS65_LH_NAND4ABX3 U9502 ( .A(n7138), .B(n7137), .C(n7136), .D(n7135), .Z(
n7139) );
HS65_LH_NOR4ABX2 U9503 ( .A(n7142), .B(n7141), .C(n7140), .D(n7139), .Z(
n8336) );
HS65_LH_AO22X9 U9504 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][25] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][25] ), .D(
n9372), .Z(n7144) );
HS65_LH_NOR4ABX2 U9505 ( .A(n7146), .B(n7145), .C(n7144), .D(n7143), .Z(
n7160) );
HS65_LH_NOR4ABX2 U9507 ( .A(n7150), .B(n7149), .C(n7148), .D(n7147), .Z(
n7159) );
HS65_LH_AO22X9 U9508 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][25] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][25] ), .D(
n7291), .Z(n7156) );
HS65_LH_AOI22X1 U9509 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][25] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][25] ), .D(
n6384), .Z(n7154) );
HS65_LH_NAND4ABX3 U9510 ( .A(n7156), .B(n7155), .C(n7154), .D(n7153), .Z(
n7157) );
HS65_LH_NOR4ABX2 U9511 ( .A(n7160), .B(n7159), .C(n7158), .D(n7157), .Z(
n8329) );
HS65_LH_NOR4ABX2 U9512 ( .A(n7164), .B(n7163), .C(n7162), .D(n7161), .Z(
n7183) );
HS65_LH_NOR4ABX2 U9513 ( .A(n7169), .B(n7168), .C(n7167), .D(n7166), .Z(
n7182) );
HS65_LH_NAND4ABX3 U9514 ( .A(n7175), .B(n7174), .C(n7173), .D(n7172), .Z(
n7181) );
HS65_LH_AOI22X1 U9515 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][13] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][13] ), .D(
n6384), .Z(n7177) );
HS65_LH_NAND4ABX3 U9516 ( .A(n7179), .B(n7178), .C(n7177), .D(n7176), .Z(
n7180) );
HS65_LH_NOR4ABX2 U9517 ( .A(n7183), .B(n7182), .C(n7181), .D(n7180), .Z(
n8342) );
HS65_LH_NOR4ABX2 U9518 ( .A(n7187), .B(n7186), .C(n7185), .D(n7184), .Z(
n7203) );
HS65_LH_AOI22X1 U9519 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][15] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][15] ), .D(
n6957), .Z(n7190) );
HS65_LH_NOR4ABX2 U9520 ( .A(n7191), .B(n7190), .C(n7189), .D(n7188), .Z(
n7202) );
HS65_LH_NAND4ABX3 U9521 ( .A(n7195), .B(n7194), .C(n7193), .D(n7192), .Z(
n7201) );
HS65_LH_NAND4ABX3 U9522 ( .A(n7199), .B(n7198), .C(n7197), .D(n7196), .Z(
n7200) );
HS65_LH_NOR4ABX2 U9523 ( .A(n7207), .B(n7206), .C(n7205), .D(n7204), .Z(
n7223) );
HS65_LH_AOI22X1 U9524 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][10] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][10] ), .D(
n6957), .Z(n7210) );
HS65_LH_NOR4ABX2 U9525 ( .A(n7211), .B(n7210), .C(n7209), .D(n7208), .Z(
n7222) );
HS65_LH_NAND4ABX3 U9526 ( .A(n7215), .B(n7214), .C(n7213), .D(n7212), .Z(
n7221) );
HS65_LH_NAND4ABX3 U9527 ( .A(n7219), .B(n7218), .C(n7217), .D(n7216), .Z(
n7220) );
HS65_LH_NOR4ABX2 U9528 ( .A(n7227), .B(n7226), .C(n7225), .D(n7224), .Z(
n7243) );
HS65_LH_AOI22X1 U9529 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][23] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][23] ), .D(
n6957), .Z(n7230) );
HS65_LH_NOR4ABX2 U9530 ( .A(n7231), .B(n7230), .C(n7229), .D(n7228), .Z(
n7242) );
HS65_LH_NAND4ABX3 U9531 ( .A(n7235), .B(n7234), .C(n7233), .D(n7232), .Z(
n7241) );
HS65_LH_NAND4ABX3 U9532 ( .A(n7239), .B(n7238), .C(n7237), .D(n7236), .Z(
n7240) );
HS65_LH_NOR4ABX2 U9533 ( .A(n7247), .B(n7246), .C(n7245), .D(n7244), .Z(
n7263) );
HS65_LH_AOI22X1 U9534 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][6] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][6] ), .D(n6957), .Z(n7250) );
HS65_LH_NOR4ABX2 U9535 ( .A(n7251), .B(n7250), .C(n7249), .D(n7248), .Z(
n7262) );
HS65_LH_NAND4ABX3 U9536 ( .A(n7255), .B(n7254), .C(n7253), .D(n7252), .Z(
n7261) );
HS65_LH_NAND4ABX3 U9537 ( .A(n7259), .B(n7258), .C(n7257), .D(n7256), .Z(
n7260) );
HS65_LH_AO22X9 U9538 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][29] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][29] ), .D(
n7266), .Z(n7269) );
HS65_LH_NOR4ABX2 U9540 ( .A(n7271), .B(n7270), .C(n7269), .D(n7268), .Z(
n7305) );
HS65_LH_AO22X9 U9541 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][29] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][29] ), .D(
n7274), .Z(n7279) );
HS65_LH_AO22X9 U9542 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][29] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][29] ), .D(
n7276), .Z(n7278) );
HS65_LH_NOR4ABX2 U9543 ( .A(n7281), .B(n7280), .C(n7279), .D(n7278), .Z(
n7304) );
HS65_LH_NAND4ABX3 U9544 ( .A(n7290), .B(n7289), .C(n7288), .D(n7287), .Z(
n7303) );
HS65_LH_AO22X9 U9545 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][29] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][29] ), .D(
n7291), .Z(n7301) );
HS65_LH_AOI22X1 U9546 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][29] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][29] ), .D(
n7294), .Z(n7299) );
HS65_LH_NAND4ABX3 U9547 ( .A(n7301), .B(n7300), .C(n7299), .D(n7298), .Z(
n7302) );
HS65_LH_NOR4ABX2 U9548 ( .A(n7305), .B(n7304), .C(n7303), .D(n7302), .Z(
n8448) );
HS65_LH_NOR2X2 U9549 ( .A(n8550), .B(n9401), .Z(n8551) );
HS65_LH_CNIVX3 U9550 ( .A(n7694), .Z(n7772) );
HS65_LH_NOR4ABX2 U9551 ( .A(n7316), .B(n7315), .C(n7314), .D(n7313), .Z(
n7342) );
HS65_LH_AOI22X1 U9552 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][26] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][26] ), .D(
n6957), .Z(n7323) );
HS65_LH_NOR4ABX2 U9553 ( .A(n7324), .B(n7323), .C(n7322), .D(n7321), .Z(
n7341) );
HS65_LH_NAND4ABX3 U9554 ( .A(n7328), .B(n7327), .C(n7326), .D(n7325), .Z(
n7340) );
HS65_LH_NAND4ABX3 U9555 ( .A(n7338), .B(n7337), .C(n7336), .D(n7335), .Z(
n7339) );
HS65_LH_NAND2X2 U9556 ( .A(n7343), .B(n7089), .Z(n8146) );
HS65_LH_NOR4ABX2 U9559 ( .A(n7350), .B(n7349), .C(n7348), .D(n7347), .Z(
n7366) );
HS65_LH_NOR4ABX2 U9560 ( .A(n7354), .B(n7353), .C(n7352), .D(n7351), .Z(
n7365) );
HS65_LH_NAND4ABX3 U9561 ( .A(n7358), .B(n7357), .C(n7356), .D(n7355), .Z(
n7364) );
HS65_LH_NAND4ABX3 U9562 ( .A(n7362), .B(n7361), .C(n7360), .D(n7359), .Z(
n7363) );
HS65_LH_NOR4ABX2 U9563 ( .A(n7370), .B(n7369), .C(n7368), .D(n7367), .Z(
n7386) );
HS65_LH_NOR4ABX2 U9564 ( .A(n7374), .B(n7373), .C(n7372), .D(n7371), .Z(
n7385) );
HS65_LH_NAND4ABX3 U9565 ( .A(n7378), .B(n7377), .C(n7376), .D(n7375), .Z(
n7384) );
HS65_LH_NAND4ABX3 U9566 ( .A(n7382), .B(n7381), .C(n7380), .D(n7379), .Z(
n7383) );
HS65_LH_NOR4ABX2 U9567 ( .A(n7390), .B(n7389), .C(n7388), .D(n7387), .Z(
n7406) );
HS65_LH_NOR4ABX2 U9568 ( .A(n7394), .B(n7393), .C(n7392), .D(n7391), .Z(
n7405) );
HS65_LH_NAND4ABX3 U9569 ( .A(n7398), .B(n7397), .C(n7396), .D(n7395), .Z(
n7404) );
HS65_LH_NAND4ABX3 U9570 ( .A(n7402), .B(n7401), .C(n7400), .D(n7399), .Z(
n7403) );
HS65_LH_NOR4ABX2 U9571 ( .A(n7410), .B(n7409), .C(n7408), .D(n7407), .Z(
n7427) );
HS65_LH_NOR4ABX2 U9572 ( .A(n7414), .B(n7413), .C(n7412), .D(n7411), .Z(
n7426) );
HS65_LH_NAND4ABX3 U9573 ( .A(n7419), .B(n7418), .C(n7417), .D(n7416), .Z(
n7425) );
HS65_LH_NAND4ABX3 U9574 ( .A(n7423), .B(n7422), .C(n7421), .D(n7420), .Z(
n7424) );
HS65_LH_NOR4ABX2 U9575 ( .A(n7433), .B(n7432), .C(n7431), .D(n7430), .Z(
n7451) );
HS65_LH_NOR4ABX2 U9576 ( .A(n7438), .B(n7437), .C(n7436), .D(n7435), .Z(
n7450) );
HS65_LH_NAND4ABX3 U9577 ( .A(n7443), .B(n7442), .C(n7441), .D(n7440), .Z(
n7449) );
HS65_LH_NAND4ABX3 U9578 ( .A(n7447), .B(n7446), .C(n7445), .D(n7444), .Z(
n7448) );
HS65_LH_NOR4ABX2 U9579 ( .A(n7455), .B(n7454), .C(n7453), .D(n7452), .Z(
n7471) );
HS65_LH_NOR4ABX2 U9580 ( .A(n7459), .B(n7458), .C(n7457), .D(n7456), .Z(
n7470) );
HS65_LH_NAND4ABX3 U9581 ( .A(n7463), .B(n7462), .C(n7461), .D(n7460), .Z(
n7469) );
HS65_LH_NAND4ABX3 U9582 ( .A(n7467), .B(n7466), .C(n7465), .D(n7464), .Z(
n7468) );
HS65_LH_AOI22X1 U9583 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][20] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][20] ), .D(n6740),
.Z(n7474) );
HS65_LH_NOR4ABX2 U9584 ( .A(n7475), .B(n7474), .C(n7473), .D(n7472), .Z(
n7491) );
HS65_LH_NOR4ABX2 U9585 ( .A(n7479), .B(n7478), .C(n7477), .D(n7476), .Z(
n7490) );
HS65_LH_NAND4ABX3 U9586 ( .A(n7483), .B(n7482), .C(n7481), .D(n7480), .Z(
n7489) );
HS65_LH_NAND4ABX3 U9587 ( .A(n7487), .B(n7486), .C(n7485), .D(n7484), .Z(
n7488) );
HS65_LH_NOR4ABX2 U9588 ( .A(n7495), .B(n7494), .C(n7493), .D(n7492), .Z(
n7511) );
HS65_LH_NOR4ABX2 U9589 ( .A(n7499), .B(n7498), .C(n7497), .D(n7496), .Z(
n7510) );
HS65_LH_NAND4ABX3 U9590 ( .A(n7503), .B(n7502), .C(n7501), .D(n7500), .Z(
n7509) );
HS65_LH_NAND4ABX3 U9591 ( .A(n7507), .B(n7506), .C(n7505), .D(n7504), .Z(
n7508) );
HS65_LH_NOR4ABX2 U9592 ( .A(n7515), .B(n7514), .C(n7513), .D(n7512), .Z(
n7537) );
HS65_LH_NOR4ABX2 U9593 ( .A(n7521), .B(n7520), .C(n7519), .D(n7518), .Z(
n7536) );
HS65_LH_NAND4ABX3 U9594 ( .A(n7529), .B(n7528), .C(n7527), .D(n7526), .Z(
n7535) );
HS65_LH_NAND4ABX3 U9595 ( .A(n7533), .B(n7532), .C(n7531), .D(n7530), .Z(
n7534) );
HS65_LH_NOR4ABX2 U9596 ( .A(n7541), .B(n7540), .C(n7539), .D(n7538), .Z(
n7557) );
HS65_LH_NOR4ABX2 U9597 ( .A(n7545), .B(n7544), .C(n7543), .D(n7542), .Z(
n7556) );
HS65_LH_NAND4ABX3 U9598 ( .A(n7549), .B(n7548), .C(n7547), .D(n7546), .Z(
n7555) );
HS65_LH_NAND4ABX3 U9599 ( .A(n7553), .B(n7552), .C(n7551), .D(n7550), .Z(
n7554) );
HS65_LH_NOR4ABX2 U9600 ( .A(n7561), .B(n7560), .C(n7559), .D(n7558), .Z(
n7577) );
HS65_LH_NOR4ABX2 U9601 ( .A(n7565), .B(n7564), .C(n7563), .D(n7562), .Z(
n7576) );
HS65_LH_NAND4ABX3 U9602 ( .A(n7569), .B(n7568), .C(n7567), .D(n7566), .Z(
n7575) );
HS65_LH_NAND4ABX3 U9603 ( .A(n7573), .B(n7572), .C(n7571), .D(n7570), .Z(
n7574) );
HS65_LH_NOR4ABX2 U9604 ( .A(n7584), .B(n7583), .C(n7582), .D(n7581), .Z(
n7612) );
HS65_LH_NOR4ABX2 U9605 ( .A(n7591), .B(n7590), .C(n7589), .D(n7588), .Z(
n7611) );
HS65_LH_NAND4ABX3 U9606 ( .A(n7598), .B(n7597), .C(n7596), .D(n7595), .Z(
n7610) );
HS65_LH_NAND4ABX3 U9607 ( .A(n7608), .B(n7607), .C(n7606), .D(n7605), .Z(
n7609) );
HS65_LH_NOR2X2 U9608 ( .A(\u_DataPath/u_idexreg/N3 ), .B(n7617), .Z(
\u_DataPath/u_execute/EXALU/N810 ) );
HS65_LH_IVX2 U9609 ( .A(n7618), .Z(n8138) );
HS65_LH_IVX2 U9610 ( .A(n7619), .Z(n8142) );
HS65_LH_NOR2AX3 U9611 ( .A(n9076), .B(n2847), .Z(n7733) );
HS65_LH_NAND2X2 U9612 ( .A(n7733), .B(n9031), .Z(n8149) );
HS65_LH_NOR2X2 U9613 ( .A(n2851), .B(n7621), .Z(n7625) );
HS65_LH_NOR2X2 U9614 ( .A(n7622), .B(n2840), .Z(n7624) );
HS65_LH_MUXI21X2 U9615 ( .D0(n7625), .D1(n7624), .S0(n7623), .Z(n7635) );
HS65_LH_NAND2X2 U9616 ( .A(n7626), .B(n2840), .Z(n7629) );
HS65_LH_NOR2X2 U9617 ( .A(n7626), .B(n2840), .Z(n7628) );
HS65_LH_MUX21I1X3 U9618 ( .D0(n7629), .D1(n7628), .S0(n7627), .Z(n7630) );
HS65_LH_NAND2X2 U9619 ( .A(n7631), .B(n7630), .Z(n7633) );
HS65_LH_CBI4I6X2 U9620 ( .A(n7635), .B(n7634), .C(n7633), .D(
\u_DataPath/u_idexreg/N3 ), .Z(\u_DataPath/u_execute/EXALU/N811 ) );
HS65_LH_CNIVX3 U9621 ( .A(\u_DataPath/jaddr_i [19]), .Z(n8042) );
HS65_LH_IVX2 U9622 ( .A(n8716), .Z(n8490) );
HS65_LH_IVX2 U9624 ( .A(Data_out_fromRAM[18]), .Z(n8454) );
HS65_LH_IVX2 U9625 ( .A(Data_out_fromRAM[19]), .Z(n8324) );
HS65_LH_IVX2 U9626 ( .A(Data_out_fromRAM[22]), .Z(n8351) );
HS65_LH_IVX2 U9627 ( .A(Data_out_fromRAM[16]), .Z(n8356) );
HS65_LH_IVX2 U9628 ( .A(Data_out_fromRAM[17]), .Z(n8406) );
HS65_LH_NOR2X6 U9631 ( .A(n7648), .B(n7676), .Z(n7649) );
HS65_LH_CNIVX3 U9632 ( .A(n7652), .Z(n7654) );
HS65_LH_NOR2X2 U9635 ( .A(opcode_i[1]), .B(opcode_i[3]), .Z(n7696) );
HS65_LH_CNIVX3 U9636 ( .A(n8086), .Z(n7702) );
HS65_LH_NOR3X1 U9637 ( .A(\u_DataPath/immediate_ext_dec_i [2]), .B(
\u_DataPath/immediate_ext_dec_i [3]), .C(n8092), .Z(n7699) );
HS65_LH_NAND2X2 U9638 ( .A(n8076), .B(n7699), .Z(n7701) );
HS65_LH_CNIVX3 U9639 ( .A(n8076), .Z(n7703) );
HS65_LH_NAND4ABX3 U9640 ( .A(opcode_i[3]), .B(n9082), .C(n7735), .D(n7778),
.Z(n8049) );
HS65_LH_NOR3X1 U9641 ( .A(\u_DataPath/immediate_ext_dec_i [2]), .B(
\u_DataPath/immediate_ext_dec_i [3]), .C(
\u_DataPath/immediate_ext_dec_i [10]), .Z(n7737) );
HS65_LH_NOR2X2 U9642 ( .A(\u_DataPath/immediate_ext_dec_i [8]), .B(
\u_DataPath/immediate_ext_dec_i [9]), .Z(n7736) );
HS65_LH_NAND4ABX3 U9643 ( .A(\u_DataPath/immediate_ext_dec_i [6]), .B(
\u_DataPath/immediate_ext_dec_i [7]), .C(n7737), .D(n7736), .Z(n8073)
);
HS65_LH_NAND4ABX3 U9644 ( .A(n7763), .B(n7740), .C(n7739), .D(n8083), .Z(
n8057) );
HS65_LH_NAND4ABX3 U9646 ( .A(n8123), .B(n8122), .C(n8121), .D(n8120), .Z(
n7760) );
HS65_LH_AOI21X2 U9647 ( .A(n7772), .B(n7777), .C(n7763), .Z(n8100) );
HS65_LH_AOI21X2 U9648 ( .A(n7773), .B(n7772), .C(n7771), .Z(n7774) );
HS65_LH_AOI222X2 U9649 ( .A(n7779), .B(opcode_i[1]), .C(n7778), .D(n7777),
.E(n9084), .F(n7776), .Z(n8081) );
HS65_LH_HA1X4 U9650 ( .A0(n2908), .B0(n9204), .CO(n7801), .S0(
\u_DataPath/u_execute/link_value_i [29]) );
HS65_LH_HA1X4 U9651 ( .A0(n7801), .B0(n9203), .CO(n7800), .S0(
\u_DataPath/u_execute/link_value_i [30]) );
HS65_LH_NOR2X2 U9652 ( .A(n8840), .B(n7802), .Z(n7803) );
HS65_LH_AND2X4 U9653 ( .A(n2896), .B(n7803), .Z(n7864) );
HS65_LL_OAI21X18 U9655 ( .A(n3009), .B(n8141), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N148 ) );
HS65_LL_OAI21X18 U9656 ( .A(n3010), .B(n8141), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N153 ) );
HS65_LL_OAI21X12 U9657 ( .A(n8141), .B(n2773), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N149 ) );
HS65_LL_OAI21X12 U9658 ( .A(n8150), .B(n8145), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N133 ) );
HS65_LL_OAI21X12 U9659 ( .A(n8150), .B(n3012), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N134 ) );
HS65_LL_OAI21X12 U9660 ( .A(n8141), .B(n3012), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N150 ) );
HS65_LL_OAI21X12 U9661 ( .A(n8140), .B(n3012), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N142 ) );
HS65_LH_NOR2X2 U9662 ( .A(rst), .B(n8160), .Z(
\u_DataPath/u_decode_unit/hdu_0/current_state [1]) );
HS65_LH_BFX18 U9663 ( .A(n8443), .Z(n7899) );
HS65_LH_BFX18 U9664 ( .A(n8443), .Z(n7900) );
HS65_LH_NAND3X3 U9665 ( .A(n8142), .B(n8143), .C(n8139), .Z(n8141) );
HS65_LH_NAND3X2 U9666 ( .A(n9075), .B(n8138), .C(n8143), .Z(n8140) );
HS65_LH_AND2X4 U9667 ( .A(n2733), .B(\u_DataPath/toPC2_i [24]), .Z(
\u_DataPath/branch_target_i [24]) );
HS65_LH_NOR4ABX2 U9668 ( .A(n8566), .B(n8565), .C(n8564), .D(n7878), .Z(
\u_DataPath/mem_writedata_out_i [29]) );
HS65_LH_NOR4ABX2 U9669 ( .A(n8566), .B(n8560), .C(n8559), .D(n8558), .Z(
\u_DataPath/mem_writedata_out_i [27]) );
HS65_LH_NOR4ABX2 U9670 ( .A(n8566), .B(n8540), .C(n8539), .D(n8538), .Z(
\u_DataPath/mem_writedata_out_i [20]) );
HS65_LH_NOR4ABX2 U9671 ( .A(n8566), .B(n8543), .C(n8542), .D(n8541), .Z(
\u_DataPath/mem_writedata_out_i [21]) );
HS65_LH_AND2X4 U9674 ( .A(n2733), .B(\u_DataPath/toPC2_i [15]), .Z(
\u_DataPath/branch_target_i [15]) );
HS65_LH_AO222X4 U9675 ( .A(n7895), .B(\u_DataPath/pc_4_i [12]), .C(n7892),
.D(n9412), .E(n8917), .F(n7888), .Z(n8660) );
HS65_LH_AO222X4 U9676 ( .A(n7895), .B(\u_DataPath/pc_4_i [14]), .C(n7892),
.D(\u_DataPath/jump_address_i [14]), .E(n9198), .F(n7888), .Z(n8658)
);
HS65_LH_AO222X4 U9677 ( .A(n7895), .B(\u_DataPath/pc_4_i [18]), .C(n7892),
.D(n9411), .E(n8927), .F(n7887), .Z(n8654) );
HS65_LH_AO222X4 U9678 ( .A(n7895), .B(\u_DataPath/pc_4_i [19]), .C(n7892),
.D(\u_DataPath/jump_address_i [19]), .E(n8925), .F(n7887), .Z(n8653)
);
HS65_LH_NOR3AX4 U9679 ( .A(n8755), .B(rst), .C(\u_DataPath/cw_to_ex_i [15]),
.Z(n8450) );
HS65_LH_NOR4ABX2 U9680 ( .A(n8566), .B(n8502), .C(n8501), .D(n8500), .Z(
\u_DataPath/mem_writedata_out_i [7]) );
HS65_LH_NOR4ABX2 U9681 ( .A(n8566), .B(n8486), .C(n7864), .D(n8485), .Z(
\u_DataPath/mem_writedata_out_i [1]) );
HS65_LH_NOR4ABX2 U9682 ( .A(n8566), .B(n8499), .C(n8498), .D(n8497), .Z(
\u_DataPath/mem_writedata_out_i [6]) );
HS65_LH_NOR4ABX2 U9683 ( .A(n8518), .B(n8517), .C(n8516), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [13]) );
HS65_LH_NOR4ABX2 U9684 ( .A(n8509), .B(n8508), .C(n8507), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [10]) );
HS65_LH_NOR4ABX2 U9685 ( .A(n8530), .B(n8529), .C(n8528), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [17]) );
HS65_LH_NOR4ABX2 U9686 ( .A(n8521), .B(n8520), .C(n8519), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [14]) );
HS65_LH_NOR4ABX2 U9687 ( .A(n8527), .B(n8526), .C(n8525), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [16]) );
HS65_LH_NOR4ABX2 U9688 ( .A(n8533), .B(n8532), .C(n8531), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [18]) );
HS65_LH_NOR4ABX2 U9689 ( .A(n8549), .B(n8548), .C(n8547), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [23]) );
HS65_LH_NOR4ABX2 U9690 ( .A(n8512), .B(n8511), .C(n8510), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [11]) );
HS65_LH_NOR4ABX2 U9691 ( .A(n8524), .B(n8523), .C(n8522), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [15]) );
HS65_LH_NOR4ABX2 U9692 ( .A(n8557), .B(n8556), .C(n8555), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [26]) );
HS65_LH_NOR4ABX2 U9693 ( .A(n8553), .B(n8552), .C(rst), .D(n8551), .Z(
\u_DataPath/mem_writedata_out_i [24]) );
HS65_LH_NOR4ABX2 U9694 ( .A(n8496), .B(n8495), .C(n7863), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [5]) );
HS65_LH_NOR4ABX2 U9695 ( .A(n8515), .B(n8514), .C(n8513), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [12]) );
HS65_LH_NOR4ABX2 U9696 ( .A(n8569), .B(n8568), .C(n8567), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [30]) );
HS65_LH_NOR4ABX2 U9697 ( .A(n8572), .B(n8571), .C(n8570), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [31]) );
HS65_LH_NOR4ABX2 U9698 ( .A(n8546), .B(n8545), .C(n8544), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [22]) );
HS65_LH_AND2X4 U9699 ( .A(n2733), .B(\u_DataPath/toPC2_i [22]), .Z(
\u_DataPath/branch_target_i [22]) );
HS65_LH_AND2X4 U9700 ( .A(n2733), .B(\u_DataPath/toPC2_i [17]), .Z(
\u_DataPath/branch_target_i [17]) );
HS65_LH_AND2X4 U9701 ( .A(n2733), .B(\u_DataPath/toPC2_i [18]), .Z(
\u_DataPath/branch_target_i [18]) );
HS65_LH_AND2X4 U9702 ( .A(n2733), .B(\u_DataPath/toPC2_i [20]), .Z(
\u_DataPath/branch_target_i [20]) );
HS65_LH_AND2X4 U9703 ( .A(n2733), .B(\u_DataPath/toPC2_i [19]), .Z(
\u_DataPath/branch_target_i [19]) );
HS65_LH_NOR2X2 U9704 ( .A(n8262), .B(rst), .Z(n8143) );
HS65_LH_BFX4 U9705 ( .A(n8609), .Z(n8004) );
HS65_LH_BFX4 U9706 ( .A(n8607), .Z(n7995) );
HS65_LH_BFX4 U9707 ( .A(n8599), .Z(n7968) );
HS65_LH_BFX4 U9708 ( .A(n8593), .Z(n7950) );
HS65_LH_BFX4 U9709 ( .A(n8595), .Z(n7956) );
HS65_LH_BFX4 U9710 ( .A(n8610), .Z(n8007) );
HS65_LH_BFX4 U9711 ( .A(n8598), .Z(n7965) );
HS65_LH_BFX4 U9712 ( .A(n8616), .Z(n8022) );
HS65_LH_BFX4 U9713 ( .A(n8606), .Z(n7992) );
HS65_LH_BFX4 U9714 ( .A(n8612), .Z(n8013) );
HS65_LH_BFX4 U9715 ( .A(n8603), .Z(n7983) );
HS65_LH_BFX4 U9716 ( .A(n8601), .Z(n7977) );
HS65_LH_BFX4 U9717 ( .A(n8622), .Z(n8031) );
HS65_LH_BFX4 U9718 ( .A(n8588), .Z(n7938) );
HS65_LH_BFX4 U9719 ( .A(n8596), .Z(n7959) );
HS65_LH_BFX4 U9720 ( .A(n8594), .Z(n7953) );
HS65_LH_BFX4 U9721 ( .A(n8604), .Z(n7986) );
HS65_LH_BFX4 U9722 ( .A(n8620), .Z(n8028) );
HS65_LH_BFX4 U9723 ( .A(n8602), .Z(n7980) );
HS65_LH_BFX4 U9724 ( .A(n8613), .Z(n8016) );
HS65_LH_BFX4 U9725 ( .A(n8618), .Z(n8025) );
HS65_LH_BFX4 U9726 ( .A(n8611), .Z(n8011) );
HS65_LH_BFX4 U9727 ( .A(n8611), .Z(n8012) );
HS65_LH_BFX4 U9728 ( .A(n8587), .Z(n7935) );
HS65_LH_CNIVX3 U9729 ( .A(n8608), .Z(n8003) );
HS65_LH_BFX4 U9730 ( .A(n8585), .Z(n7928) );
HS65_LH_BFX4 U9731 ( .A(n8605), .Z(n7991) );
HS65_LH_BFX4 U9732 ( .A(n8589), .Z(n7943) );
HS65_LH_BFX4 U9733 ( .A(n8597), .Z(n7964) );
HS65_LH_BFX4 U9734 ( .A(n8614), .Z(n8021) );
HS65_LH_BFX4 U9735 ( .A(n8609), .Z(n8006) );
HS65_LH_BFX4 U9736 ( .A(n8607), .Z(n7997) );
HS65_LH_BFX4 U9737 ( .A(n8599), .Z(n7970) );
HS65_LH_BFX4 U9738 ( .A(n8614), .Z(n8019) );
HS65_LH_BFX4 U9739 ( .A(n8597), .Z(n7962) );
HS65_LH_BFX4 U9740 ( .A(n8589), .Z(n7941) );
HS65_LH_CNIVX3 U9741 ( .A(n8600), .Z(n7976) );
HS65_LH_BFX4 U9742 ( .A(n8605), .Z(n7989) );
HS65_LH_BFX4 U9743 ( .A(n8585), .Z(n7926) );
HS65_LH_BFX4 U9744 ( .A(n8587), .Z(n7936) );
HS65_LH_CNIVX3 U9745 ( .A(n8608), .Z(n8002) );
HS65_LH_BFX4 U9746 ( .A(n8618), .Z(n8026) );
HS65_LH_BFX4 U9747 ( .A(n8613), .Z(n8017) );
HS65_LH_BFX4 U9748 ( .A(n8602), .Z(n7981) );
HS65_LH_BFX4 U9749 ( .A(n8620), .Z(n8029) );
HS65_LH_BFX4 U9750 ( .A(n8604), .Z(n7987) );
HS65_LH_BFX4 U9751 ( .A(n8594), .Z(n7954) );
HS65_LH_BFX4 U9752 ( .A(n8596), .Z(n7960) );
HS65_LH_BFX4 U9753 ( .A(n8588), .Z(n7939) );
HS65_LH_BFX4 U9754 ( .A(n8622), .Z(n8032) );
HS65_LH_BFX4 U9755 ( .A(n8601), .Z(n7978) );
HS65_LH_BFX4 U9756 ( .A(n8603), .Z(n7984) );
HS65_LH_BFX4 U9757 ( .A(n8612), .Z(n8014) );
HS65_LH_BFX4 U9758 ( .A(n8606), .Z(n7993) );
HS65_LH_BFX4 U9759 ( .A(n8616), .Z(n8023) );
HS65_LH_BFX4 U9760 ( .A(n8598), .Z(n7966) );
HS65_LH_BFX4 U9761 ( .A(n8610), .Z(n8008) );
HS65_LH_BFX4 U9762 ( .A(n8595), .Z(n7957) );
HS65_LH_BFX4 U9763 ( .A(n8593), .Z(n7951) );
HS65_LH_BFX4 U9764 ( .A(n8599), .Z(n7969) );
HS65_LH_CNIVX3 U9765 ( .A(n8293), .Z(n8599) );
HS65_LH_BFX4 U9766 ( .A(n8611), .Z(n8010) );
HS65_LH_CNIVX3 U9767 ( .A(n8397), .Z(n8611) );
HS65_LH_BFX4 U9768 ( .A(n8607), .Z(n7996) );
HS65_LH_CNIVX3 U9769 ( .A(n8362), .Z(n8607) );
HS65_LH_BFX4 U9770 ( .A(n8609), .Z(n8005) );
HS65_LH_CNIVX3 U9771 ( .A(n8321), .Z(n8609) );
HS65_LH_CNIVX3 U9772 ( .A(n8591), .Z(n7948) );
HS65_LH_BFX4 U9773 ( .A(n8614), .Z(n8020) );
HS65_LH_CNIVX3 U9774 ( .A(n8434), .Z(n8614) );
HS65_LH_BFX4 U9775 ( .A(n8597), .Z(n7963) );
HS65_LH_CNIVX3 U9776 ( .A(n8326), .Z(n8597) );
HS65_LH_BFX4 U9777 ( .A(n8589), .Z(n7942) );
HS65_LH_CNIVX3 U9778 ( .A(n8348), .Z(n8589) );
HS65_LH_CNIVX3 U9779 ( .A(n8600), .Z(n7975) );
HS65_LH_BFX4 U9780 ( .A(n8605), .Z(n7990) );
HS65_LH_CNIVX3 U9781 ( .A(n8404), .Z(n8605) );
HS65_LH_BFX4 U9782 ( .A(n8585), .Z(n7927) );
HS65_LH_CNIVX3 U9783 ( .A(n8378), .Z(n8585) );
HS65_LH_BFX4 U9784 ( .A(n8587), .Z(n7937) );
HS65_LH_CNIVX3 U9785 ( .A(n8422), .Z(n8587) );
HS65_LH_BFX4 U9786 ( .A(n8618), .Z(n8027) );
HS65_LH_CNIVX3 U9787 ( .A(n8168), .Z(n8618) );
HS65_LH_CNIVX3 U9788 ( .A(n8591), .Z(n7949) );
HS65_LH_BFX4 U9789 ( .A(n8613), .Z(n8018) );
HS65_LH_CNIVX3 U9790 ( .A(n8314), .Z(n8613) );
HS65_LH_BFX4 U9791 ( .A(n8593), .Z(n7952) );
HS65_LH_CNIVX3 U9792 ( .A(n8304), .Z(n8593) );
HS65_LH_BFX4 U9793 ( .A(n8595), .Z(n7958) );
HS65_LH_CNIVX3 U9794 ( .A(n8343), .Z(n8595) );
HS65_LH_BFX4 U9795 ( .A(n8610), .Z(n8009) );
HS65_LH_CNIVX3 U9796 ( .A(n8449), .Z(n8610) );
HS65_LH_BFX4 U9797 ( .A(n8598), .Z(n7967) );
HS65_LH_CNIVX3 U9798 ( .A(n8367), .Z(n8598) );
HS65_LH_BFX4 U9799 ( .A(n8602), .Z(n7982) );
HS65_LH_CNIVX3 U9800 ( .A(n8457), .Z(n8602) );
HS65_LH_BFX4 U9801 ( .A(n8616), .Z(n8024) );
HS65_LH_CNIVX3 U9802 ( .A(n8415), .Z(n8616) );
HS65_LH_BFX4 U9803 ( .A(n8606), .Z(n7994) );
HS65_LH_CNIVX3 U9804 ( .A(n8330), .Z(n8606) );
HS65_LH_BFX4 U9805 ( .A(n8612), .Z(n8015) );
HS65_LH_CNIVX3 U9806 ( .A(n8337), .Z(n8612) );
HS65_LH_BFX4 U9807 ( .A(n8603), .Z(n7985) );
HS65_LH_CNIVX3 U9808 ( .A(n8372), .Z(n8603) );
HS65_LH_BFX4 U9809 ( .A(n8596), .Z(n7961) );
HS65_LH_CNIVX3 U9810 ( .A(n8412), .Z(n8596) );
HS65_LH_BFX4 U9811 ( .A(n8622), .Z(n8033) );
HS65_LH_CNIVX3 U9812 ( .A(n8431), .Z(n8622) );
HS65_LH_BFX4 U9813 ( .A(n8604), .Z(n7988) );
HS65_LH_CNIVX3 U9814 ( .A(n8408), .Z(n8604) );
HS65_LH_BFX4 U9815 ( .A(n8620), .Z(n8030) );
HS65_LH_CNIVX3 U9816 ( .A(n8444), .Z(n8620) );
HS65_LH_BFX4 U9817 ( .A(n8594), .Z(n7955) );
HS65_LH_CNIVX3 U9818 ( .A(n8358), .Z(n8594) );
HS65_LH_BFX4 U9819 ( .A(n8588), .Z(n7940) );
HS65_LH_CNIVX3 U9820 ( .A(n8275), .Z(n8588) );
HS65_LH_BFX4 U9821 ( .A(n8601), .Z(n7979) );
HS65_LH_CNIVX3 U9822 ( .A(n8353), .Z(n8601) );
HS65_LH_AND2X4 U9823 ( .A(n2733), .B(\u_DataPath/toPC2_i [1]), .Z(
\u_DataPath/branch_target_i [1]) );
HS65_LH_NOR4ABX2 U9824 ( .A(n8506), .B(n8505), .C(n8504), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [9]) );
HS65_LH_AND2X4 U9825 ( .A(n2733), .B(\u_DataPath/toPC2_i [2]), .Z(
\u_DataPath/branch_target_i [2]) );
HS65_LH_NOR4ABX2 U9826 ( .A(n8492), .B(n8491), .C(n3312), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [3]) );
HS65_LH_NOR2X2 U9827 ( .A(rst), .B(n8034), .Z(
\u_DataPath/u_decode_unit/hdu_0/current_state [0]) );
HS65_LH_AND2X4 U9828 ( .A(n2733), .B(\u_DataPath/toPC2_i [5]), .Z(
\u_DataPath/branch_target_i [5]) );
HS65_LH_AND2X4 U9829 ( .A(n2733), .B(\u_DataPath/toPC2_i [6]), .Z(
\u_DataPath/branch_target_i [6]) );
HS65_LH_AND2X4 U9830 ( .A(n2733), .B(\u_DataPath/toPC2_i [8]), .Z(
\u_DataPath/branch_target_i [8]) );
HS65_LH_AND2X4 U9831 ( .A(n2733), .B(\u_DataPath/toPC2_i [13]), .Z(
\u_DataPath/branch_target_i [13]) );
HS65_LH_AND2X4 U9832 ( .A(n2733), .B(\u_DataPath/toPC2_i [11]), .Z(
\u_DataPath/branch_target_i [11]) );
HS65_LH_AND2X4 U9833 ( .A(n2733), .B(\u_DataPath/toPC2_i [12]), .Z(
\u_DataPath/branch_target_i [12]) );
HS65_LH_OAI12X6 U9834 ( .A(n8140), .B(n8149), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N144 ) );
HS65_LH_OAI12X6 U9835 ( .A(n8141), .B(n8149), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N152 ) );
HS65_LH_OAI12X6 U9836 ( .A(n8144), .B(n8150), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N138 ) );
HS65_LH_OAI12X6 U9837 ( .A(n8144), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N130 ) );
HS65_LH_OAI12X6 U9838 ( .A(n8146), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N131 ) );
HS65_LH_OAI12X6 U9839 ( .A(n8140), .B(n8144), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N146 ) );
HS65_LH_OAI12X6 U9840 ( .A(n8149), .B(n8150), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N136 ) );
HS65_LH_OAI12X6 U9841 ( .A(n8144), .B(n8141), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N154 ) );
HS65_LH_OAI12X6 U9842 ( .A(n8140), .B(n8146), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N147 ) );
HS65_LH_OAI12X6 U9843 ( .A(n8146), .B(n8150), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N139 ) );
HS65_LH_NAND3X5 U9844 ( .A(n8960), .B(n8142), .C(n8143), .Z(n8150) );
HS65_LH_OAI12X6 U9845 ( .A(n8149), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N128 ) );
HS65_LH_CNIVX3 U9846 ( .A(n7934), .Z(n7929) );
HS65_LH_CNIVX3 U9847 ( .A(n8586), .Z(n7934) );
HS65_LH_CNIVX3 U9848 ( .A(n8003), .Z(n7998) );
HS65_LH_CNIVX3 U9849 ( .A(n7974), .Z(n7973) );
HS65_LH_CNIVX3 U9850 ( .A(n7947), .Z(n7946) );
HS65_LH_CNIVX3 U9851 ( .A(n7976), .Z(n7971) );
HS65_LH_CNIVX3 U9852 ( .A(n8002), .Z(n7999) );
HS65_LH_CNIVX3 U9853 ( .A(n7933), .Z(n7930) );
HS65_LH_CNIVX3 U9854 ( .A(n8586), .Z(n7933) );
HS65_LH_CNIVX3 U9855 ( .A(n7948), .Z(n7945) );
HS65_LH_CNIVX3 U9856 ( .A(n7975), .Z(n7972) );
HS65_LH_CNIVX3 U9857 ( .A(n8001), .Z(n8000) );
HS65_LH_CNIVX3 U9858 ( .A(n7949), .Z(n7944) );
HS65_LH_CNIVX3 U9859 ( .A(n7932), .Z(n7931) );
HS65_LH_CNIVX3 U9860 ( .A(n8423), .Z(\u_DataPath/u_execute/psw_status_i [1])
);
HS65_LH_CNIVX3 U9864 ( .A(n8228), .Z(\u_DataPath/pc_4_to_ex_i [2]) );
HS65_LH_CNIVX3 U9865 ( .A(n8230), .Z(\u_DataPath/u_execute/link_value_i [0])
);
HS65_LH_CNIVX3 U9866 ( .A(n8113), .Z(\u_DataPath/cw_tomem_i [5]) );
HS65_LH_CNIVX3 U9867 ( .A(n8109), .Z(\u_DataPath/cw_tomem_i [4]) );
HS65_LH_CNIVX3 U9868 ( .A(n8061), .Z(\u_DataPath/reg_write_i ) );
HS65_LH_CNIVX3 U9869 ( .A(n8263), .Z(\u_DataPath/cw_memwb_i [1]) );
HS65_LH_CNIVX3 U9870 ( .A(n8579), .Z(n8494) );
HS65_LL_OAI22X1 U9871 ( .A(n7096), .B(n8431), .C(n7901), .D(n8392), .Z(
\u_DataPath/data_read_ex_2_i [4]) );
HS65_LL_OAI22X1 U9872 ( .A(n7096), .B(n8404), .C(n7901), .D(n8388), .Z(
\u_DataPath/data_read_ex_2_i [14]) );
HS65_LL_OAI22X1 U9873 ( .A(n7096), .B(n8434), .C(n7901), .D(n8433), .Z(
\u_DataPath/data_read_ex_2_i [3]) );
HS65_LH_NAND2X7 U9875 ( .A(opcode_i[5]), .B(n8045), .Z(n8053) );
HS65_LL_OAI22X1 U9876 ( .A(n7096), .B(n8397), .C(n7900), .D(n8379), .Z(
\u_DataPath/data_read_ex_2_i [30]) );
HS65_LL_OAI22X1 U9877 ( .A(n7902), .B(n8001), .C(n7899), .D(n8155), .Z(
\u_DataPath/data_read_ex_2_i [0]) );
HS65_LL_OAI22X1 U9878 ( .A(n7096), .B(n8378), .C(n7900), .D(n8373), .Z(
\u_DataPath/data_read_ex_2_i [27]) );
HS65_LL_OAI22X1 U9879 ( .A(n7096), .B(n8412), .C(n7901), .D(n8384), .Z(
\u_DataPath/data_read_ex_2_i [20]) );
HS65_LL_OAI22X1 U9880 ( .A(n7096), .B(n7932), .C(n7901), .D(n8382), .Z(
\u_DataPath/data_read_ex_2_i [28]) );
HS65_LL_OAI22X1 U9881 ( .A(n7096), .B(n8449), .C(n7901), .D(n8381), .Z(
\u_DataPath/data_read_ex_2_i [29]) );
HS65_LL_OAI22X1 U9882 ( .A(n7096), .B(n8358), .C(n7900), .D(n8354), .Z(
\u_DataPath/data_read_ex_2_i [16]) );
HS65_LL_OAI22X1 U9883 ( .A(n7096), .B(n8372), .C(n7900), .D(n8368), .Z(
\u_DataPath/data_read_ex_2_i [24]) );
HS65_LL_OAI22X1 U9884 ( .A(n7096), .B(n8367), .C(n7900), .D(n8363), .Z(
\u_DataPath/data_read_ex_2_i [21]) );
HS65_LH_OAI211X3 U9885 ( .A(n8696), .B(n9012), .C(n8885), .D(n8079), .Z(
\u_DataPath/cw_to_ex_i [1]) );
HS65_LL_OAI22X1 U9888 ( .A(n7096), .B(n8444), .C(n7901), .D(n8442), .Z(
\u_DataPath/data_read_ex_2_i [2]) );
HS65_LH_NOR2AX3 U9889 ( .A(n9233), .B(rst), .Z(n8286) );
HS65_LH_IVX9 U9890 ( .A(n8480), .Z(n7873) );
HS65_LH_NOR2AX3 U9891 ( .A(\u_DataPath/cw_exmem_i [3]), .B(rst), .Z(
\u_DataPath/cw_tomem_i [3]) );
HS65_LH_NOR2AX3 U9892 ( .A(\u_DataPath/dataOut_exe_i [31]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [31]) );
HS65_LH_NOR2AX3 U9893 ( .A(\u_DataPath/dataOut_exe_i [17]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [17]) );
HS65_LH_NOR2AX3 U9894 ( .A(\u_DataPath/dataOut_exe_i [16]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [16]) );
HS65_LH_NOR2AX3 U9895 ( .A(\u_DataPath/dataOut_exe_i [22]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [22]) );
HS65_LH_NOR2AX3 U9896 ( .A(\u_DataPath/dataOut_exe_i [28]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [28]) );
HS65_LH_NOR2AX3 U9897 ( .A(\u_DataPath/dataOut_exe_i [9]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [9]) );
HS65_LH_NOR2AX3 U9898 ( .A(\u_DataPath/dataOut_exe_i [7]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [7]) );
HS65_LH_NOR2AX3 U9899 ( .A(\u_DataPath/dataOut_exe_i [3]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [3]) );
HS65_LH_NOR2AX3 U9900 ( .A(\u_DataPath/dataOut_exe_i [29]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [29]) );
HS65_LH_NOR2AX3 U9901 ( .A(\u_DataPath/dataOut_exe_i [14]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [14]) );
HS65_LH_NOR2AX3 U9902 ( .A(\u_DataPath/immediate_ext_dec_i [4]), .B(rst),
.Z(\u_DataPath/immediate_ext_ex_i [4]) );
HS65_LH_NOR2X6 U9903 ( .A(n8166), .B(rst), .Z(n8626) );
HS65_LH_AND2X4 U9904 ( .A(n9068), .B(n8634), .Z(\u_DataPath/cw_to_ex_i [20])
);
HS65_LH_MUXI21X2 U9905 ( .D0(n9084), .D1(iram_data[26]), .S0(
\u_DataPath/u_fetch/pc1/N3 ), .Z(n8043) );
HS65_LH_MUXI21X2 U9906 ( .D0(n9082), .D1(iram_data[28]), .S0(
\u_DataPath/u_fetch/pc1/N3 ), .Z(n8036) );
HS65_LH_MUXI21X2 U9907 ( .D0(n9068), .D1(iram_data[30]), .S0(
\u_DataPath/u_fetch/pc1/N3 ), .Z(n8035) );
HS65_LH_NOR2AX3 U9908 ( .A(\u_DataPath/dataOut_exe_i [15]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [15]) );
HS65_LH_NOR2AX3 U9909 ( .A(\u_DataPath/dataOut_exe_i [6]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [6]) );
HS65_LH_NOR2AX3 U9910 ( .A(\u_DataPath/dataOut_exe_i [5]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [5]) );
HS65_LH_NOR2AX3 U9911 ( .A(\u_DataPath/dataOut_exe_i [23]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [23]) );
HS65_LH_NOR2AX3 U9912 ( .A(\u_DataPath/dataOut_exe_i [30]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [30]) );
HS65_LH_NOR2AX3 U9913 ( .A(\u_DataPath/dataOut_exe_i [8]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [8]) );
HS65_LH_NOR2AX3 U9914 ( .A(\u_DataPath/dataOut_exe_i [26]), .B(rst), .Z(
\u_DataPath/u_memwbreg/N64 ) );
HS65_LH_NOR2AX3 U9915 ( .A(\u_DataPath/dataOut_exe_i [24]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [24]) );
HS65_LH_NOR2AX3 U9916 ( .A(\u_DataPath/dataOut_exe_i [2]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [2]) );
HS65_LH_NOR2AX3 U9917 ( .A(\u_DataPath/dataOut_exe_i [19]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [19]) );
HS65_LH_NOR2AX3 U9918 ( .A(\u_DataPath/dataOut_exe_i [18]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [18]) );
HS65_LH_NOR2AX3 U9919 ( .A(\u_DataPath/dataOut_exe_i [12]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [12]) );
HS65_LH_NOR2AX3 U9920 ( .A(\u_DataPath/dataOut_exe_i [25]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [25]) );
HS65_LH_NOR2AX3 U9921 ( .A(\u_DataPath/dataOut_exe_i [13]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [13]) );
HS65_LH_NOR2AX3 U9922 ( .A(\u_DataPath/dataOut_exe_i [11]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [11]) );
HS65_LH_NOR2AX3 U9923 ( .A(\u_DataPath/dataOut_exe_i [21]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [21]) );
HS65_LH_NOR2AX3 U9924 ( .A(\u_DataPath/dataOut_exe_i [27]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [27]) );
HS65_LH_NOR2AX3 U9925 ( .A(\u_DataPath/dataOut_exe_i [20]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [20]) );
HS65_LH_NOR2AX3 U9926 ( .A(\u_DataPath/dataOut_exe_i [10]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [10]) );
HS65_LH_AO22X4 U9927 ( .A(n8580), .B(n8425), .C(n8621), .D(n8573), .Z(
\u_DataPath/u_execute/psw_status_i [0]) );
HS65_LH_AO222X4 U9928 ( .A(n7894), .B(n8691), .C(n7891), .D(
\u_DataPath/jump_address_i [0]), .E(n9250), .F(n7889), .Z(
\u_DataPath/pc_4_i [0]) );
HS65_LH_AO222X4 U9929 ( .A(n7894), .B(n8689), .C(n7891), .D(
\u_DataPath/jump_address_i [1]), .E(n8924), .F(n7889), .Z(
\u_DataPath/pc_4_i [1]) );
HS65_LH_AO222X4 U9930 ( .A(n7894), .B(\u_DataPath/pc_4_i [2]), .C(n7891),
.D(\u_DataPath/jump_address_i [2]), .E(n8923), .F(n7889), .Z(n8670) );
HS65_LH_BFX4 U9931 ( .A(n8283), .Z(n7885) );
HS65_LH_AO222X4 U9932 ( .A(n7894), .B(\u_DataPath/pc_4_i [3]), .C(n7891),
.D(\u_DataPath/jump_address_i [3]), .E(n9147), .F(n7889), .Z(n8669) );
HS65_LH_AO222X4 U9933 ( .A(n7894), .B(\u_DataPath/pc_4_i [4]), .C(n7891),
.D(\u_DataPath/jump_address_i [4]), .E(n9148), .F(n7888), .Z(n8668) );
HS65_LH_AO222X4 U9934 ( .A(n7894), .B(\u_DataPath/pc_4_i [5]), .C(n7891),
.D(n9409), .E(n8922), .F(n7888), .Z(n8667) );
HS65_LH_AO222X4 U9935 ( .A(n7894), .B(\u_DataPath/pc_4_i [6]), .C(n7891),
.D(n9410), .E(n8921), .F(n7888), .Z(n8666) );
HS65_LH_AO222X4 U9937 ( .A(n7894), .B(\u_DataPath/pc_4_i [7]), .C(n7891),
.D(\u_DataPath/jump_address_i [7]), .E(n9196), .F(n7888), .Z(n8665) );
HS65_LH_AO222X4 U9938 ( .A(n7894), .B(\u_DataPath/pc_4_i [10]), .C(n7891),
.D(\u_DataPath/jump_address_i [10]), .E(n9263), .F(n7888), .Z(n8662)
);
HS65_LH_AO222X4 U9939 ( .A(n7894), .B(\u_DataPath/pc_4_i [8]), .C(n7891),
.D(n9408), .E(n8920), .F(n7888), .Z(n8664) );
HS65_LH_AO222X4 U9940 ( .A(n7894), .B(\u_DataPath/pc_4_i [11]), .C(n7891),
.D(n9407), .E(n8918), .F(n7888), .Z(n8661) );
HS65_LH_AO222X4 U9941 ( .A(n7894), .B(\u_DataPath/pc_4_i [9]), .C(n7891),
.D(\u_DataPath/jump_address_i [9]), .E(n9195), .F(n7888), .Z(n8663) );
HS65_LH_AOI21X2 U9946 ( .A(n8084), .B(n8083), .C(n8117), .Z(n8085) );
HS65_LH_CNIVX27 U9948 ( .A(rst), .Z(n8566) );
HS65_LH_CNIVX27 U9949 ( .A(n2733), .Z(n8480) );
HS65_LL_DFPQX4 clk_r_REG0_S1 ( .D(n2733), .CP(clk), .Q(n9334) );
HS65_LL_DFPQX4 clk_r_REG648_S1 ( .D(Data_out_fromRAM[30]), .CP(clk), .Q(
n9302) );
HS65_LL_DFPQX4 clk_r_REG650_S1 ( .D(Data_out_fromRAM[29]), .CP(clk), .Q(
n9301) );
HS65_LL_DFPQX4 clk_r_REG652_S1 ( .D(Data_out_fromRAM[28]), .CP(clk), .Q(
n9300) );
HS65_LL_DFPQX4 clk_r_REG654_S1 ( .D(Data_out_fromRAM[27]), .CP(clk), .Q(
n9299) );
HS65_LL_DFPQX4 clk_r_REG656_S1 ( .D(Data_out_fromRAM[26]), .CP(clk), .Q(
n9298) );
HS65_LL_DFPQX4 clk_r_REG658_S1 ( .D(Data_out_fromRAM[25]), .CP(clk), .Q(
n9297) );
HS65_LL_DFPQX4 clk_r_REG663_S1 ( .D(Data_out_fromRAM[22]), .CP(clk), .Q(
n9295) );
HS65_LL_DFPQX4 clk_r_REG667_S1 ( .D(Data_out_fromRAM[20]), .CP(clk), .Q(
n9293) );
HS65_LL_DFPQX4 clk_r_REG669_S1 ( .D(Data_out_fromRAM[19]), .CP(clk), .Q(
n9292) );
HS65_LL_DFPQX4 clk_r_REG671_S1 ( .D(Data_out_fromRAM[18]), .CP(clk), .Q(
n9291) );
HS65_LL_DFPQX4 clk_r_REG673_S1 ( .D(Data_out_fromRAM[17]), .CP(clk), .Q(
n9290) );
HS65_LL_DFPQX4 clk_r_REG675_S1 ( .D(Data_out_fromRAM[16]), .CP(clk), .Q(
n9289) );
HS65_LL_DFPQX4 clk_r_REG677_S1 ( .D(Data_out_fromRAM[15]), .CP(clk), .Q(
n9288) );
HS65_LL_DFPQX4 clk_r_REG678_S1 ( .D(Data_out_fromRAM[14]), .CP(clk), .Q(
n9287) );
HS65_LL_DFPQX4 clk_r_REG679_S1 ( .D(Data_out_fromRAM[13]), .CP(clk), .Q(
n9286) );
HS65_LL_DFPQX4 clk_r_REG680_S1 ( .D(Data_out_fromRAM[12]), .CP(clk), .Q(
n9285) );
HS65_LL_DFPQX4 clk_r_REG681_S1 ( .D(Data_out_fromRAM[11]), .CP(clk), .Q(
n9284) );
HS65_LL_DFPQX4 clk_r_REG682_S1 ( .D(Data_out_fromRAM[10]), .CP(clk), .Q(
n9283) );
HS65_LL_DFPQX4 clk_r_REG683_S1 ( .D(Data_out_fromRAM[9]), .CP(clk), .Q(n9282) );
HS65_LL_DFPQX4 clk_r_REG684_S1 ( .D(Data_out_fromRAM[8]), .CP(clk), .Q(n9281) );
HS65_LL_DFPQX4 clk_r_REG688_S1 ( .D(Data_out_fromRAM[4]), .CP(clk), .Q(n9278) );
HS65_LL_DFPQX4 clk_r_REG689_S1 ( .D(Data_out_fromRAM[3]), .CP(clk), .Q(n9277) );
HS65_LL_DFPQX4 clk_r_REG690_S1 ( .D(Data_out_fromRAM[2]), .CP(clk), .Q(n9276) );
HS65_LL_DFPQX4 clk_r_REG691_S1 ( .D(Data_out_fromRAM[1]), .CP(clk), .Q(n9275) );
HS65_LL_DFPQX4 clk_r_REG692_S1 ( .D(Data_out_fromRAM[0]), .CP(clk), .Q(n9274) );
HS65_LL_DFPQX4 clk_r_REG446_S2 ( .D(n7902), .CP(clk), .Q(n9272) );
HS65_LL_DFPQX4 clk_r_REG337_S2 ( .D(\sub_x_53/A[25] ), .CP(clk), .Q(n9271)
);
HS65_LL_DFPQX4 clk_r_REG346_S1 ( .D(n7974), .CP(clk), .Q(n9270) );
HS65_LL_DFPQX4 clk_r_REG389_S1 ( .D(n8001), .CP(clk), .Q(n9269) );
HS65_LL_DFPQX4 clk_r_REG662_S1 ( .D(n8360), .CP(clk), .Q(n9268) );
HS65_LL_DFPQX4 clk_r_REG605_S1 ( .D(n8627), .CP(clk), .Q(n9267) );
HS65_LL_DFPQX4 clk_r_REG606_S2 ( .D(n9267), .CP(clk), .Q(n9266) );
HS65_LL_DFPQX4 clk_r_REG173_S1 ( .D(\u_DataPath/branch_target_i [27]), .CP(
clk), .Q(n9264) );
HS65_LL_DFPQX4 clk_r_REG116_S1 ( .D(\u_DataPath/branch_target_i [10]), .CP(
clk), .Q(n9263) );
HS65_LL_DFPQX4 clk_r_REG277_S3 ( .D(n2853), .CP(clk), .Q(n9260) );
HS65_LL_DFPQX4 clk_r_REG38_S2 ( .D(n2858), .CP(clk), .Q(n9259) );
HS65_LL_DFPQX4 clk_r_REG406_S3 ( .D(\sub_x_53/A[30] ), .CP(clk), .Q(n9258)
);
HS65_LL_DFPQX4 clk_r_REG412_S2 ( .D(\sub_x_53/A[27] ), .CP(clk), .Q(n9257)
);
HS65_LL_DFPQX4 clk_r_REG333_S2 ( .D(\lte_x_59/B[22] ), .CP(clk), .Q(n9256)
);
HS65_LL_DFPQX4 clk_r_REG110_S2 ( .D(\lte_x_59/B[9] ), .CP(clk), .Q(n9255) );
HS65_LL_DFPRQX4 clk_r_REG615_S1 ( .D(n7922), .CP(clk), .RN(n7879), .Q(n9254)
);
HS65_LL_DFPQX4 clk_r_REG452_S2 ( .D(n8578), .CP(clk), .Q(n9251) );
HS65_LL_DFPQX4 clk_r_REG433_S1 ( .D(\u_DataPath/branch_target_i [0]), .CP(
clk), .Q(n9250) );
HS65_LL_DFPQX4 clk_r_REG374_S2 ( .D(\u_DataPath/u_execute/link_value_i [2]),
.CP(clk), .Q(n9249) );
HS65_LL_DFPQX4 clk_r_REG649_S1 ( .D(n8402), .CP(clk), .Q(n9248) );
HS65_LL_DFPQX4 clk_r_REG651_S1 ( .D(n8447), .CP(clk), .Q(n9247) );
HS65_LL_DFPQX4 clk_r_REG661_S1 ( .D(n8370), .CP(clk), .Q(n9245) );
HS65_LL_DFPQX4 clk_r_REG655_S1 ( .D(n8376), .CP(clk), .Q(n9244) );
HS65_LL_DFPQX4 clk_r_REG659_S1 ( .D(n8335), .CP(clk), .Q(n9242) );
HS65_LL_DFPQX4 clk_r_REG354_S2 ( .D(\u_DataPath/mem_writedata_out_i [28]),
.CP(clk), .Q(n9241) );
HS65_LL_DFPRQX4 clk_r_REG513_S1 ( .D(n7898), .CP(clk), .RN(n9361), .Q(n9240)
);
HS65_LL_DFPQX4 clk_r_REG469_S4 ( .D(n7837), .CP(clk), .Q(n9239) );
HS65_LL_DFPQX4 clk_r_REG449_S1 ( .D(\u_DataPath/cw_memwb_i [0]), .CP(clk),
.Q(n9238) );
HS65_LL_DFPQX4 clk_r_REG484_S1 ( .D(\u_DataPath/cw_tomem_i [8]), .CP(clk),
.Q(n9237) );
HS65_LL_DFPQX4 clk_r_REG479_S1 ( .D(\u_DataPath/cw_tomem_i [7]), .CP(clk),
.Q(n9236) );
HS65_LL_DFPQX4 clk_r_REG510_S1 ( .D(\u_DataPath/cw_tomem_i [6]), .CP(clk),
.Q(n9235) );
HS65_LL_DFPQX4 clk_r_REG518_S1 ( .D(\u_DataPath/cw_tomem_i [0]), .CP(clk),
.Q(n9234) );
HS65_LL_DFPQX4 clk_r_REG473_S1 ( .D(\u_DataPath/jump_i ), .CP(clk), .Q(n9233) );
HS65_LL_DFPQX4 clk_r_REG266_S1 ( .D(\u_DataPath/pc_4_to_ex_i [11]), .CP(clk),
.Q(n9232) );
HS65_LL_DFPQX4 clk_r_REG259_S1 ( .D(\u_DataPath/pc_4_to_ex_i [12]), .CP(clk),
.Q(n9230) );
HS65_LL_DFPQX4 clk_r_REG313_S1 ( .D(\u_DataPath/pc_4_to_ex_i [8]), .CP(clk),
.Q(n9229) );
HS65_LL_DFPQX4 clk_r_REG126_S1 ( .D(\u_DataPath/pc_4_to_ex_i [13]), .CP(clk),
.Q(n9228) );
HS65_LL_DFPQX4 clk_r_REG319_S1 ( .D(\u_DataPath/pc_4_to_ex_i [7]), .CP(clk),
.Q(n9227) );
HS65_LL_DFPQX4 clk_r_REG132_S1 ( .D(\u_DataPath/pc_4_to_ex_i [14]), .CP(clk),
.Q(n9226) );
HS65_LL_DFPQX4 clk_r_REG308_S1 ( .D(\u_DataPath/pc_4_to_ex_i [6]), .CP(clk),
.Q(n9225) );
HS65_LL_DFPQX4 clk_r_REG251_S1 ( .D(\u_DataPath/pc_4_to_ex_i [15]), .CP(clk),
.Q(n9224) );
HS65_LL_DFPQX4 clk_r_REG327_S1 ( .D(\u_DataPath/pc_4_to_ex_i [5]), .CP(clk),
.Q(n9223) );
HS65_LL_DFPQX4 clk_r_REG244_S1 ( .D(\u_DataPath/pc_4_to_ex_i [16]), .CP(clk),
.Q(n9222) );
HS65_LL_DFPQX4 clk_r_REG237_S1 ( .D(\u_DataPath/pc_4_to_ex_i [17]), .CP(clk),
.Q(n9221) );
HS65_LL_DFPQX4 clk_r_REG216_S1 ( .D(\u_DataPath/pc_4_to_ex_i [18]), .CP(clk),
.Q(n9220) );
HS65_LL_DFPQX4 clk_r_REG299_S1 ( .D(\u_DataPath/pc_4_to_ex_i [4]), .CP(clk),
.Q(n9219) );
HS65_LL_DFPQX4 clk_r_REG224_S1 ( .D(\u_DataPath/pc_4_to_ex_i [19]), .CP(clk),
.Q(n9218) );
HS65_LL_DFPQX4 clk_r_REG229_S1 ( .D(\u_DataPath/pc_4_to_ex_i [20]), .CP(clk),
.Q(n9217) );
HS65_LL_DFPQX4 clk_r_REG5_S1 ( .D(\u_DataPath/pc_4_to_ex_i [3]), .CP(clk),
.Q(n9215) );
HS65_LL_DFPQX4 clk_r_REG120_S1 ( .D(\u_DataPath/pc_4_to_ex_i [10]), .CP(clk),
.Q(n9214) );
HS65_LL_DFPQX4 clk_r_REG156_S1 ( .D(\u_DataPath/pc_4_to_ex_i [22]), .CP(clk),
.Q(n9213) );
HS65_LL_DFPQX4 clk_r_REG367_S1 ( .D(\u_DataPath/u_execute/link_value_i [1]),
.CP(clk), .Q(n9212) );
HS65_LL_DFPQX4 clk_r_REG209_S1 ( .D(\u_DataPath/pc_4_to_ex_i [23]), .CP(clk),
.Q(n9210) );
HS65_LL_DFPQX4 clk_r_REG161_S1 ( .D(\u_DataPath/pc_4_to_ex_i [24]), .CP(clk),
.Q(n9209) );
HS65_LL_DFPQX4 clk_r_REG166_S1 ( .D(\u_DataPath/pc_4_to_ex_i [25]), .CP(clk),
.Q(n9208) );
HS65_LL_DFPQX4 clk_r_REG171_S1 ( .D(\u_DataPath/pc_4_to_ex_i [26]), .CP(clk),
.Q(n9207) );
HS65_LL_DFPQX4 clk_r_REG177_S1 ( .D(\u_DataPath/pc_4_to_ex_i [27]), .CP(clk),
.Q(n9206) );
HS65_LL_DFPQX4 clk_r_REG183_S1 ( .D(\u_DataPath/pc_4_to_ex_i [28]), .CP(clk),
.Q(n9205) );
HS65_LL_DFPQX4 clk_r_REG200_S1 ( .D(\u_DataPath/pc_4_to_ex_i [29]), .CP(clk),
.Q(n9204) );
HS65_LL_DFPQX4 clk_r_REG188_S1 ( .D(\u_DataPath/pc_4_to_ex_i [30]), .CP(clk),
.Q(n9203) );
HS65_LL_DFPQX4 clk_r_REG193_S1 ( .D(\u_DataPath/pc_4_to_ex_i [31]), .CP(clk),
.Q(n9202) );
HS65_LL_DFPQX4 clk_r_REG343_S3 ( .D(\lte_x_59/B[15] ), .CP(clk), .Q(n9200)
);
HS65_LL_DFPQX4 clk_r_REG203_S1 ( .D(\u_DataPath/branch_target_i [25]), .CP(
clk), .Q(n9199) );
HS65_LL_DFPQX4 clk_r_REG128_S1 ( .D(\u_DataPath/branch_target_i [14]), .CP(
clk), .Q(n9198) );
HS65_LL_DFPQX4 clk_r_REG210_S1 ( .D(\u_DataPath/branch_target_i [23]), .CP(
clk), .Q(n9197) );
HS65_LL_DFPQX4 clk_r_REG315_S1 ( .D(\u_DataPath/branch_target_i [7]), .CP(
clk), .Q(n9196) );
HS65_LL_DFPQX4 clk_r_REG240_S1 ( .D(\u_DataPath/branch_target_i [16]), .CP(
clk), .Q(n9194) );
HS65_LL_DFPQX4 clk_r_REG135_S1 ( .D(\u_DataPath/branch_target_i [21]), .CP(
clk), .Q(n9193) );
HS65_LL_DFPRQX4 clk_r_REG535_S1 ( .D(n7921), .CP(clk), .RN(n9354), .Q(n9191)
);
HS65_LL_DFPQX4 clk_r_REG468_S4 ( .D(n7904), .CP(clk), .Q(n9190) );
HS65_LL_DFPQX4 clk_r_REG471_S4 ( .D(n7903), .CP(clk), .Q(n9189) );
HS65_LL_DFPQX4 clk_r_REG462_S1 ( .D(n7882), .CP(clk), .Q(n9188) );
HS65_LL_DFPQX4 clk_r_REG472_S4 ( .D(n7907), .CP(clk), .Q(n9187) );
HS65_LL_DFPQX4 clk_r_REG602_S1 ( .D(n8629), .CP(clk), .Q(n9185) );
HS65_LL_DFPQX4 clk_r_REG603_S2 ( .D(n9185), .CP(clk), .Q(n9184) );
HS65_LL_DFPQX4 clk_r_REG599_S1 ( .D(n8631), .CP(clk), .Q(n9183) );
HS65_LL_DFPQX4 clk_r_REG600_S2 ( .D(n9183), .CP(clk), .Q(n9182) );
HS65_LL_DFPQX4 clk_r_REG608_S1 ( .D(n8623), .CP(clk), .Q(n9181) );
HS65_LL_DFPQX4 clk_r_REG609_S2 ( .D(n9181), .CP(clk), .Q(n9180) );
HS65_LL_DFPQX4 clk_r_REG588_S1 ( .D(\u_DataPath/u_idexreg/N31 ), .CP(clk),
.Q(n9179) );
HS65_LL_DFPQX4 clk_r_REG545_S1 ( .D(\u_DataPath/u_idexreg/N33 ), .CP(clk),
.Q(n9177) );
HS65_LL_DFPQX4 clk_r_REG546_S2 ( .D(n9177), .CP(clk), .Q(n9176) );
HS65_LL_DFPQX4 clk_r_REG542_S1 ( .D(\u_DataPath/immediate_ext_ex_i [7]),
.CP(clk), .Q(n9175) );
HS65_LL_DFPQX4 clk_r_REG543_S2 ( .D(n9175), .CP(clk), .Q(n9174) );
HS65_LL_DFPQX4 clk_r_REG548_S1 ( .D(\u_DataPath/immediate_ext_ex_i [9]),
.CP(clk), .Q(n9173) );
HS65_LL_DFPQX4 clk_r_REG549_S2 ( .D(n9173), .CP(clk), .Q(n9172) );
HS65_LL_DFPQX4 clk_r_REG552_S2 ( .D(n9171), .CP(clk), .Q(n9170) );
HS65_LL_DFPQX4 clk_r_REG571_S3 ( .D(n8162), .CP(clk), .Q(n9169) );
HS65_LL_DFPQX4 clk_r_REG527_S2 ( .D(n8070), .CP(clk), .Q(n9168) );
HS65_LL_DFPQX4 clk_r_REG509_S3 ( .D(n8055), .CP(clk), .Q(n9167) );
HS65_LL_DFPQX4 clk_r_REG685_S1 ( .D(n8302), .CP(clk), .Q(n9166) );
HS65_LL_DFPQX4 clk_r_REG194_S1 ( .D(\u_DataPath/branch_target_i [31]), .CP(
clk), .Q(n9165) );
HS65_LL_DFPQX4 clk_r_REG201_S1 ( .D(\u_DataPath/branch_target_i [29]), .CP(
clk), .Q(n9164) );
HS65_LL_DFPRQX4 clk_r_REG555_S2 ( .D(n7918), .CP(clk), .RN(n9356), .Q(n9153)
);
HS65_LL_DFPQX4 clk_r_REG442_S3 ( .D(n8054), .CP(clk), .Q(n9152) );
HS65_LL_DFPQX4 clk_r_REG464_S3 ( .D(\u_DataPath/cw_exmem_i [9]), .CP(clk),
.Q(n9151) );
HS65_LL_DFPQX4 clk_r_REG385_S3 ( .D(n8271), .CP(clk), .Q(n9150) );
HS65_LL_DFPQX4 clk_r_REG489_S3 ( .D(n8095), .CP(clk), .Q(n9149) );
HS65_LL_DFPQX4 clk_r_REG322_S1 ( .D(\u_DataPath/branch_target_i [4]), .CP(
clk), .Q(n9148) );
HS65_LL_DFPQX4 clk_r_REG611_S1 ( .D(n8625), .CP(clk), .Q(n9145) );
HS65_LL_DFPQX4 clk_r_REG612_S2 ( .D(n9145), .CP(clk), .Q(n9144) );
HS65_LL_DFPRQX4 clk_r_REG538_S2 ( .D(n7920), .CP(clk), .RN(n9355), .Q(n9141)
);
HS65_LL_DFPQX4 clk_r_REG448_S2 ( .D(n7914), .CP(clk), .Q(n9140) );
HS65_LL_DFPRQX4 clk_r_REG514_S1 ( .D(n7924), .CP(clk), .RN(n9354), .Q(n9138)
);
HS65_LL_DFPQX4 clk_r_REG470_S4 ( .D(n7849), .CP(clk), .Q(n9137) );
HS65_LL_DFPQX4 clk_r_REG461_S1 ( .D(n7881), .CP(clk), .Q(n9136) );
HS65_LL_DFPQX4 clk_r_REG467_S1 ( .D(n7908), .CP(clk), .Q(n9135) );
HS65_LL_DFPQX4 clk_r_REG460_S1 ( .D(n7883), .CP(clk), .Q(n9134) );
HS65_LL_DFPQX4 clk_r_REG459_S1 ( .D(n7884), .CP(clk), .Q(n9133) );
HS65_LL_DFPRQX4 clk_r_REG511_S1 ( .D(n7897), .CP(clk), .RN(n9355), .Q(n9131)
);
HS65_LL_DFPQX4 clk_r_REG647_S1 ( .D(n8420), .CP(clk), .Q(n9129) );
HS65_LL_DFPQX4 clk_r_REG383_S3 ( .D(n8299), .CP(clk), .Q(n9127) );
HS65_LL_DFPQX4 clk_r_REG666_S1 ( .D(n8365), .CP(clk), .Q(n9126) );
HS65_LL_DFPQX4 clk_r_REG672_S1 ( .D(n8454), .CP(clk), .Q(n9125) );
HS65_LL_DFPQX4 clk_r_REG670_S1 ( .D(n8324), .CP(clk), .Q(n9124) );
HS65_LL_DFPQX4 clk_r_REG664_S1 ( .D(n8351), .CP(clk), .Q(n9123) );
HS65_LL_DFPQX4 clk_r_REG676_S1 ( .D(n8356), .CP(clk), .Q(n9122) );
HS65_LL_DFPQX4 clk_r_REG674_S1 ( .D(n8406), .CP(clk), .Q(n9121) );
HS65_LL_DFPQX4 clk_r_REG668_S1 ( .D(n8410), .CP(clk), .Q(n9120) );
HS65_LL_DFPQX4 clk_r_REG447_S1 ( .D(n7899), .CP(clk), .Q(n9119) );
HS65_LL_DFPQX4 clk_r_REG45_S1 ( .D(\u_DataPath/u_execute/psw_status_i [1]),
.CP(clk), .Q(n9118) );
HS65_LL_DFPQX4 clk_r_REG373_S1 ( .D(\u_DataPath/pc_4_to_ex_i [2]), .CP(clk),
.Q(n9116) );
HS65_LL_DFPQX4 clk_r_REG430_S1 ( .D(\u_DataPath/u_execute/link_value_i [0]),
.CP(clk), .Q(n9115) );
HS65_LL_DFPQX4 clk_r_REG444_S1 ( .D(\u_DataPath/reg_write_i ), .CP(clk), .Q(
n9111) );
HS65_LL_DFPQX4 clk_r_REG465_S1 ( .D(\u_DataPath/cw_memwb_i [1]), .CP(clk),
.Q(n9110) );
HS65_LL_DFPQX4 clk_r_REG458_S1 ( .D(n7885), .CP(clk), .Q(n9109) );
HS65_LL_DFPRQX4 clk_r_REG191_S4 ( .D(\u_DataPath/pc_4_i [31]), .CP(clk),
.RN(n9361), .Q(n9108) );
HS65_LL_DFPQX4 clk_r_REG68_S2 ( .D(\sub_x_53/A[29] ), .CP(clk), .Q(n9107) );
HS65_LL_DFPQX4 clk_r_REG26_S3 ( .D(\lte_x_59/B[18] ), .CP(clk), .Q(n9106) );
HS65_LL_DFPQX4 clk_r_REG52_S2 ( .D(\lte_x_59/B[1] ), .CP(clk), .Q(n9105) );
HS65_LL_DFPQX4 clk_r_REG350_S2 ( .D(n3474), .CP(clk), .Q(n9104) );
HS65_LL_DFPQX4 clk_r_REG394_S3 ( .D(n8575), .CP(clk), .Q(n9103) );
HS65_LL_DFPQX4 clk_r_REG594_S3 ( .D(n8076), .CP(clk), .Q(n9102) );
HS65_LL_DFPQX4 clk_r_REG134_S2 ( .D(\u_DataPath/u_execute/link_value_i [14]),
.CP(clk), .Q(n9101) );
HS65_LL_DFPQX4 clk_r_REG301_S2 ( .D(\u_DataPath/u_execute/link_value_i [7]),
.CP(clk), .Q(n9100) );
HS65_LL_DFPQX4 clk_r_REG581_S3 ( .D(n8115), .CP(clk), .Q(n9099) );
HS65_LL_DFPQX4 clk_r_REG347_S3 ( .D(n2842), .CP(clk), .Q(n9096) );
HS65_LL_DFPQX4 clk_r_REG92_S2 ( .D(\sub_x_53/A[17] ), .CP(clk), .Q(n9094) );
HS65_LL_DFPQX4 clk_r_REG417_S2 ( .D(\lte_x_59/B[16] ), .CP(clk), .Q(n9093)
);
HS65_LL_DFPQX4 clk_r_REG10_S3 ( .D(\sub_x_53/A[0] ), .CP(clk), .Q(n9092) );
HS65_LL_DFPQX4 clk_r_REG403_S4 ( .D(\lte_x_59/B[8] ), .CP(clk), .Q(n9091) );
HS65_LL_DFPQX4 clk_r_REG32_S3 ( .D(n7867), .CP(clk), .Q(n9090) );
HS65_LL_DFPQX4 clk_r_REG107_S4 ( .D(\lte_x_59/B[21] ), .CP(clk), .Q(n9089)
);
HS65_LL_DFPQX4 clk_r_REG421_S3 ( .D(n3521), .CP(clk), .Q(n9088) );
HS65_LL_DFPRQX4 clk_r_REG181_S4 ( .D(\u_DataPath/pc_4_i [28]), .CP(clk),
.RN(n8677), .Q(n9087) );
HS65_LL_DFPQX4 clk_r_REG384_S3 ( .D(n8452), .CP(clk), .Q(n9086) );
HS65_LL_DFPQX4 clk_r_REG339_S1 ( .D(\u_DataPath/mem_writedata_out_i [25]),
.CP(clk), .Q(n9085) );
HS65_LL_DFPQX4 clk_r_REG508_S3 ( .D(n9084), .CP(clk), .Q(n9083) );
HS65_LL_DFPQX4 clk_r_REG375_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [3]),
.CP(clk), .Q(n9080) );
HS65_LL_DFPQX4 clk_r_REG303_S2 ( .D(\u_DataPath/u_execute/link_value_i [6]),
.CP(clk), .Q(n9079) );
HS65_LL_DFPQX4 clk_r_REG503_S1 ( .D(\u_DataPath/regfile_addr_out_towb_i [2]),
.CP(clk), .Q(n9078) );
HS65_LL_DFPQX4 clk_r_REG530_S1 ( .D(\u_DataPath/idex_rt_i [3]), .CP(clk),
.Q(n9077) );
HS65_LL_DFPQX4 clk_r_REG501_S1 ( .D(\u_DataPath/regfile_addr_out_towb_i [0]),
.CP(clk), .Q(n9076) );
HS65_LL_DFPQX4 clk_r_REG497_S1 ( .D(\u_DataPath/regfile_addr_out_towb_i [3]),
.CP(clk), .Q(n9075) );
HS65_LL_DFPQX4 clk_r_REG85_S2 ( .D(n7855), .CP(clk), .Q(n9074) );
HS65_LL_DFPQX4 clk_r_REG79_S3 ( .D(n8458), .CP(clk), .Q(n9073) );
HS65_LL_DFPQX4 clk_r_REG108_S2 ( .D(n8474), .CP(clk), .Q(n9072) );
HS65_LL_DFPQX4 clk_r_REG100_S3 ( .D(\sub_x_53/A[23] ), .CP(clk), .Q(n9071)
);
HS65_LL_DFPRQX4 clk_r_REG175_S3 ( .D(\u_DataPath/pc_4_i [27]), .CP(clk),
.RN(n9361), .Q(n9070) );
HS65_LL_DFPQX4 clk_r_REG246_S2 ( .D(n7865), .CP(clk), .Q(n9065) );
HS65_LL_DFPQX4 clk_r_REG93_S2 ( .D(n7857), .CP(clk), .Q(n9063) );
HS65_LL_DFPQX4 clk_r_REG24_S2 ( .D(n7842), .CP(clk), .Q(n9062) );
HS65_LL_DFPQX4 clk_r_REG20_S2 ( .D(n7850), .CP(clk), .Q(n9061) );
HS65_LL_DFPQX4 clk_r_REG104_S3 ( .D(n7844), .CP(clk), .Q(n9060) );
HS65_LL_DFPQX4 clk_r_REG95_S3 ( .D(n8471), .CP(clk), .Q(n9059) );
HS65_LL_DFPQX4 clk_r_REG87_S2 ( .D(n8466), .CP(clk), .Q(n9058) );
HS65_LL_DFPQX4 clk_r_REG97_S4 ( .D(\sub_x_53/A[20] ), .CP(clk), .Q(n9056) );
HS65_LL_DFPQX4 clk_r_REG340_S4 ( .D(\lte_x_59/B[24] ), .CP(clk), .Q(n9055)
);
HS65_LL_DFPQX4 clk_r_REG167_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [26]),
.CP(clk), .Q(n9054) );
HS65_LL_DFPQX4 clk_r_REG8_S2 ( .D(\lte_x_59/B[3] ), .CP(clk), .Q(n9053) );
HS65_LL_DFPQX4 clk_r_REG517_S2 ( .D(n8636), .CP(clk), .Q(n9052) );
HS65_LL_DFPQX4 clk_r_REG393_S3 ( .D(n8300), .CP(clk), .Q(n9051) );
HS65_LL_DFPQX4 clk_r_REG483_S3 ( .D(n8068), .CP(clk), .Q(n9050) );
HS65_LL_DFPQX4 clk_r_REG477_S3 ( .D(n8069), .CP(clk), .Q(n9049) );
HS65_LL_DFPQX4 clk_r_REG456_S3 ( .D(n8634), .CP(clk), .Q(n9048) );
HS65_LL_DFPQX4 clk_r_REG218_S2 ( .D(n5703), .CP(clk), .Q(n9047) );
HS65_LL_DFPQX4 clk_r_REG219_S2 ( .D(\u_DataPath/u_execute/link_value_i [20]),
.CP(clk), .Q(n9046) );
HS65_LL_DFPQX4 clk_r_REG115_S2 ( .D(\u_DataPath/u_execute/link_value_i [9]),
.CP(clk), .Q(n9045) );
HS65_LL_DFPQX4 clk_r_REG260_S2 ( .D(\u_DataPath/u_execute/link_value_i [12]),
.CP(clk), .Q(n9044) );
HS65_LL_DFPQX4 clk_r_REG267_S2 ( .D(n4006), .CP(clk), .Q(n9043) );
HS65_LL_DFPQX4 clk_r_REG330_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [4]),
.CP(clk), .Q(n9041) );
HS65_LL_DFPQX4 clk_r_REG328_S2 ( .D(\u_DataPath/u_execute/link_value_i [5]),
.CP(clk), .Q(n9040) );
HS65_LL_DFPQX4 clk_r_REG567_S1 ( .D(\u_DataPath/immediate_ext_ex_i [2]),
.CP(clk), .Q(n9039) );
HS65_LL_DFPQX4 clk_r_REG568_S2 ( .D(n9039), .CP(clk), .Q(n9038) );
HS65_LL_DFPQX4 clk_r_REG579_S1 ( .D(\u_DataPath/immediate_ext_ex_i [1]),
.CP(clk), .Q(n9037) );
HS65_LL_DFPQX4 clk_r_REG580_S2 ( .D(n9037), .CP(clk), .Q(n9036) );
HS65_LL_DFPQX4 clk_r_REG586_S2 ( .D(n9035), .CP(clk), .Q(n9034) );
HS65_LL_DFPQX4 clk_r_REG574_S1 ( .D(\u_DataPath/immediate_ext_ex_i [3]),
.CP(clk), .Q(n9033) );
HS65_LL_DFPQX4 clk_r_REG575_S2 ( .D(n9033), .CP(clk), .Q(n9032) );
HS65_LL_DFPQX4 clk_r_REG505_S1 ( .D(\u_DataPath/regfile_addr_out_towb_i [1]),
.CP(clk), .Q(n9031) );
HS65_LL_DFPQX4 clk_r_REG592_S1 ( .D(\u_DataPath/immediate_ext_ex_i [5]),
.CP(clk), .Q(n9030) );
HS65_LL_DFPQX4 clk_r_REG593_S2 ( .D(n9030), .CP(clk), .Q(n9029) );
HS65_LL_DFPQX4 clk_r_REG73_S2 ( .D(n8477), .CP(clk), .Q(n9028) );
HS65_LL_DFPQX4 clk_r_REG63_S2 ( .D(n8469), .CP(clk), .Q(n9026) );
HS65_LL_DFPQX4 clk_r_REG195_S1 ( .D(\u_DataPath/branch_target_i [30]), .CP(
clk), .Q(n9025) );
HS65_LL_DFPQX4 clk_r_REG196_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [29]),
.CP(clk), .Q(n9024) );
HS65_LL_DFPQX4 clk_r_REG178_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [27]),
.CP(clk), .Q(n9023) );
HS65_LL_DFPQX4 clk_r_REG19_S2 ( .D(\lte_x_59/B[14] ), .CP(clk), .Q(n9022) );
HS65_LL_DFPQX4 clk_r_REG41_S3 ( .D(\sub_x_53/A[2] ), .CP(clk), .Q(n9021) );
HS65_LL_DFPQX4 clk_r_REG34_S1 ( .D(\u_DataPath/mem_writedata_out_i [8]),
.CP(clk), .Q(n9019) );
HS65_LL_DFPQX4 clk_r_REG388_S3 ( .D(\u_DataPath/mem_writedata_out_i [0]),
.CP(clk), .Q(n9018) );
HS65_LL_DFPQX4 clk_r_REG238_S2 ( .D(\u_DataPath/u_execute/link_value_i [17]),
.CP(clk), .Q(n9017) );
HS65_LL_DFPQX4 clk_r_REG463_S3 ( .D(n8059), .CP(clk), .Q(n9016) );
HS65_LL_DFPQX4 clk_r_REG127_S2 ( .D(\u_DataPath/u_execute/link_value_i [13]),
.CP(clk), .Q(n9015) );
HS65_LL_DFPQX4 clk_r_REG133_S2 ( .D(\u_DataPath/u_execute/link_value_i [15]),
.CP(clk), .Q(n9014) );
HS65_LL_DFPQX4 clk_r_REG271_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [9]),
.CP(clk), .Q(n9013) );
HS65_LL_DFPQX4 clk_r_REG616_S1 ( .D(n8117), .CP(clk), .Q(n9012) );
HS65_LL_DFPQX4 clk_r_REG320_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [7]),
.CP(clk), .Q(n9011) );
HS65_LL_DFPQX4 clk_r_REG300_S2 ( .D(\u_DataPath/u_execute/link_value_i [4]),
.CP(clk), .Q(n9008) );
HS65_LL_DFPQX4 clk_r_REG6_S2 ( .D(\u_DataPath/u_execute/link_value_i [3]),
.CP(clk), .Q(n9006) );
HS65_LL_DFPQX4 clk_r_REG566_S3 ( .D(n8121), .CP(clk), .Q(n9005) );
HS65_LL_DFPQX4 clk_r_REG558_S1 ( .D(\u_DataPath/rs_ex_i [3]), .CP(clk), .Q(
n9004) );
HS65_LL_DFPQX4 clk_r_REG572_S3 ( .D(n8096), .CP(clk), .Q(n9003) );
HS65_LL_DFPQX4 clk_r_REG30_S2 ( .D(n7859), .CP(clk), .Q(n9001) );
HS65_LL_DFPQX4 clk_r_REG148_S2 ( .D(\u_DataPath/u_execute/link_value_i [31]),
.CP(clk), .Q(n9000) );
HS65_LL_DFPQX4 clk_r_REG184_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [30]),
.CP(clk), .Q(n8999) );
HS65_LL_DFPQX4 clk_r_REG179_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [28]),
.CP(clk), .Q(n8998) );
HS65_LL_DFPQX4 clk_r_REG425_S2 ( .D(\lte_x_59/B[7] ), .CP(clk), .Q(n8997) );
HS65_LL_DFPQX4 clk_r_REG145_S2 ( .D(\u_DataPath/u_execute/link_value_i [27]),
.CP(clk), .Q(n8996) );
HS65_LL_DFPRQX4 clk_r_REG159_S4 ( .D(\u_DataPath/pc_4_i [24]), .CP(clk),
.RN(n8677), .Q(n8992) );
HS65_LL_DFPRQX4 clk_r_REG137_S3 ( .D(\u_DataPath/pc_4_i [21]), .CP(clk),
.RN(n9354), .Q(n8991) );
HS65_LL_DFPQX4 clk_r_REG162_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [25]),
.CP(clk), .Q(n8990) );
HS65_LL_DFPRQX4 clk_r_REG207_S4 ( .D(\u_DataPath/pc_4_i [23]), .CP(clk),
.RN(n9361), .Q(n8989) );
HS65_LL_DFPQX4 clk_r_REG144_S2 ( .D(\u_DataPath/u_execute/link_value_i [25]),
.CP(clk), .Q(n8987) );
HS65_LL_DFPRQX4 clk_r_REG242_S3 ( .D(\u_DataPath/pc_4_i [16]), .CP(clk),
.RN(n8677), .Q(n8986) );
HS65_LL_DFPRQX4 clk_r_REG227_S3 ( .D(\u_DataPath/pc_4_i [20]), .CP(clk),
.RN(n9361), .Q(n8985) );
HS65_LL_DFPQX4 clk_r_REG143_S2 ( .D(\u_DataPath/u_execute/link_value_i [24]),
.CP(clk), .Q(n8983) );
HS65_LL_DFPQX4 clk_r_REG231_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [19]),
.CP(clk), .Q(n8982) );
HS65_LL_DFPRQX4 clk_r_REG124_S3 ( .D(\u_DataPath/pc_4_i [13]), .CP(clk),
.RN(n9361), .Q(n8981) );
HS65_LL_DFPRQX4 clk_r_REG264_S3 ( .D(\u_DataPath/pc_4_i [11]), .CP(clk),
.RN(n9361), .Q(n8978) );
HS65_LL_DFPQX4 clk_r_REG205_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [23]),
.CP(clk), .Q(n8977) );
HS65_LL_DFPQX4 clk_r_REG142_S2 ( .D(\u_DataPath/u_execute/link_value_i [23]),
.CP(clk), .Q(n8975) );
HS65_LL_DFPRQX4 clk_r_REG118_S3 ( .D(\u_DataPath/pc_4_i [10]), .CP(clk),
.RN(n2877), .Q(n8974) );
HS65_LL_DFPQX4 clk_r_REG217_S2 ( .D(n4288), .CP(clk), .Q(n8972) );
HS65_LL_DFPQX4 clk_r_REG522_S1 ( .D(\u_DataPath/rs_ex_i [0]), .CP(clk), .Q(
n8969) );
HS65_LL_DFPQX4 clk_r_REG524_S1 ( .D(\u_DataPath/idex_rt_i [4]), .CP(clk),
.Q(n8968) );
HS65_LL_DFPQX4 clk_r_REG554_S1 ( .D(\u_DataPath/idex_rt_i [2]), .CP(clk),
.Q(n8967) );
HS65_LL_DFPQX4 clk_r_REG532_S1 ( .D(\u_DataPath/idex_rt_i [1]), .CP(clk),
.Q(n8966) );
HS65_LL_DFPQX4 clk_r_REG578_S3 ( .D(n8092), .CP(clk), .Q(n8965) );
HS65_LL_DFPQX4 clk_r_REG565_S3 ( .D(n8089), .CP(clk), .Q(n8964) );
HS65_LL_DFPRQX4 clk_r_REG306_S3 ( .D(\u_DataPath/pc_4_i [6]), .CP(clk), .RN(
n9361), .Q(n8963) );
HS65_LL_DFPRQX4 clk_r_REG214_S3 ( .D(\u_DataPath/pc_4_i [18]), .CP(clk),
.RN(n2877), .Q(n8962) );
HS65_LL_DFPQX4 clk_r_REG443_S1 ( .D(n7833), .CP(clk), .Q(n8961) );
HS65_LL_DFPQX4 clk_r_REG499_S1 ( .D(\u_DataPath/regfile_addr_out_towb_i [4]),
.CP(clk), .Q(n8960) );
HS65_LL_DFPQX4 clk_r_REG232_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [18]),
.CP(clk), .Q(n8958) );
HS65_LL_DFPQX4 clk_r_REG239_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [17]),
.CP(clk), .Q(n8957) );
HS65_LL_DFPQX4 clk_r_REG230_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [20]),
.CP(clk), .Q(n8956) );
HS65_LL_DFPQX4 clk_r_REG314_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [8]),
.CP(clk), .Q(n8955) );
HS65_LL_DFPQX4 clk_r_REG329_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [5]),
.CP(clk), .Q(n8954) );
HS65_LL_DFPQX4 clk_r_REG151_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [21]),
.CP(clk), .Q(n8953) );
HS65_LL_DFPQX4 clk_r_REG254_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [13]),
.CP(clk), .Q(n8952) );
HS65_LL_DFPQX4 clk_r_REG269_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [10]),
.CP(clk), .Q(n8951) );
HS65_LL_DFPQX4 clk_r_REG252_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [15]),
.CP(clk), .Q(n8949) );
HS65_LL_DFPQX4 clk_r_REG253_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [14]),
.CP(clk), .Q(n8948) );
HS65_LL_DFPQX4 clk_r_REG302_S2 ( .D(\u_DataPath/u_execute/link_value_i [8]),
.CP(clk), .Q(n8947) );
HS65_LL_DFPQX4 clk_r_REG245_S2 ( .D(n5690), .CP(clk), .Q(n8946) );
HS65_LL_DFPQX4 clk_r_REG369_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [2]),
.CP(clk), .Q(n8945) );
HS65_LL_DFPQX4 clk_r_REG560_S1 ( .D(\u_DataPath/rs_ex_i [1]), .CP(clk), .Q(
n8944) );
HS65_LL_DFPQX4 clk_r_REG520_S1 ( .D(\u_DataPath/rs_ex_i [2]), .CP(clk), .Q(
n8943) );
HS65_LL_DFPQX4 clk_r_REG534_S1 ( .D(\u_DataPath/idex_rt_i [0]), .CP(clk),
.Q(n8942) );
HS65_LL_DFPQX4 clk_r_REG202_S1 ( .D(\u_DataPath/branch_target_i [28]), .CP(
clk), .Q(n8941) );
HS65_LL_DFPQX4 clk_r_REG172_S1 ( .D(\u_DataPath/branch_target_i [26]), .CP(
clk), .Q(n8940) );
HS65_LL_DFPQX4 clk_r_REG140_S2 ( .D(n5169), .CP(clk), .Q(n8939) );
HS65_LL_DFPQX4 clk_r_REG141_S2 ( .D(n5698), .CP(clk), .Q(n8938) );
HS65_LL_DFPQX4 clk_r_REG432_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [0]),
.CP(clk), .Q(n8937) );
HS65_LL_DFPQX4 clk_r_REG189_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [31]),
.CP(clk), .Q(n8936) );
HS65_LL_DFPQX4 clk_r_REG157_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [24]),
.CP(clk), .Q(n8934) );
HS65_LL_DFPQX4 clk_r_REG152_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [22]),
.CP(clk), .Q(n8933) );
HS65_LL_DFPQX4 clk_r_REG453_S1 ( .D(
\u_DataPath/u_decode_unit/hdu_0/current_state [1]), .CP(clk), .Q(n8932) );
HS65_LL_DFPQX4 clk_r_REG204_S1 ( .D(\u_DataPath/branch_target_i [24]), .CP(
clk), .Q(n8931) );
HS65_LL_DFPQX4 clk_r_REG247_S1 ( .D(\u_DataPath/branch_target_i [15]), .CP(
clk), .Q(n8930) );
HS65_LL_DFPQX4 clk_r_REG233_S1 ( .D(\u_DataPath/branch_target_i [17]), .CP(
clk), .Q(n8928) );
HS65_LL_DFPQX4 clk_r_REG212_S1 ( .D(\u_DataPath/branch_target_i [18]), .CP(
clk), .Q(n8927) );
HS65_LL_DFPQX4 clk_r_REG225_S1 ( .D(\u_DataPath/branch_target_i [20]), .CP(
clk), .Q(n8926) );
HS65_LL_DFPQX4 clk_r_REG220_S1 ( .D(\u_DataPath/branch_target_i [19]), .CP(
clk), .Q(n8925) );
HS65_LL_DFPQX4 clk_r_REG379_S1 ( .D(\u_DataPath/branch_target_i [1]), .CP(
clk), .Q(n8924) );
HS65_LL_DFPQX4 clk_r_REG376_S1 ( .D(\u_DataPath/branch_target_i [2]), .CP(
clk), .Q(n8923) );
HS65_LL_DFPQX4 clk_r_REG323_S1 ( .D(\u_DataPath/branch_target_i [5]), .CP(
clk), .Q(n8922) );
HS65_LL_DFPQX4 clk_r_REG304_S1 ( .D(\u_DataPath/branch_target_i [6]), .CP(
clk), .Q(n8921) );
HS65_LL_DFPQX4 clk_r_REG309_S1 ( .D(\u_DataPath/branch_target_i [8]), .CP(
clk), .Q(n8920) );
HS65_LL_DFPQX4 clk_r_REG262_S1 ( .D(\u_DataPath/branch_target_i [11]), .CP(
clk), .Q(n8918) );
HS65_LL_DFPQX4 clk_r_REG255_S1 ( .D(\u_DataPath/branch_target_i [12]), .CP(
clk), .Q(n8917) );
HS65_LL_DFPQX4 clk_r_REG441_S3 ( .D(n8053), .CP(clk), .Q(n8916) );
HS65_LL_DFPQX4 clk_r_REG62_S1 ( .D(\u_DataPath/from_alu_data_out_i [28]),
.CP(clk), .Q(n8914) );
HS65_LL_DFPQX4 clk_r_REG596_S1 ( .D(\u_DataPath/immediate_ext_ex_i [4]),
.CP(clk), .Q(n8913) );
HS65_LL_DFPQX4 clk_r_REG597_S2 ( .D(n8913), .CP(clk), .Q(n8912) );
HS65_LL_DFPQX4 clk_r_REG457_S3 ( .D(\u_DataPath/cw_to_ex_i [20]), .CP(clk),
.Q(n8910) );
HS65_LL_DFPQX4 clk_r_REG77_S1 ( .D(\u_DataPath/from_alu_data_out_i [15]),
.CP(clk), .Q(n8909) );
HS65_LL_DFPQX4 clk_r_REG71_S1 ( .D(\u_DataPath/from_alu_data_out_i [10]),
.CP(clk), .Q(n8907) );
HS65_LL_DFPQX4 clk_r_REG445_S2 ( .D(n7306), .CP(clk), .Q(n8906) );
HS65_LL_DFPQX4 clk_r_REG355_S2 ( .D(\lte_x_59/B[28] ), .CP(clk), .Q(n8905)
);
HS65_LL_DFPQX4 clk_r_REG47_S3 ( .D(\u_DataPath/dataOut_exe_i [1]), .CP(clk),
.Q(n8904) );
HS65_LL_DFPQX4 clk_r_REG58_S4 ( .D(n8465), .CP(clk), .Q(n8903) );
HS65_LL_DFPQX4 clk_r_REG27_S3 ( .D(n8461), .CP(clk), .Q(n8902) );
HS65_LL_DFPQX4 clk_r_REG82_S2 ( .D(n8478), .CP(clk), .Q(n8900) );
HS65_LL_DFPQX4 clk_r_REG42_S3 ( .D(n7841), .CP(clk), .Q(n8899) );
HS65_LL_DFPQX4 clk_r_REG391_S3 ( .D(n8301), .CP(clk), .Q(n8898) );
HS65_LL_DFPQX4 clk_r_REG392_S3 ( .D(n8318), .CP(clk), .Q(n8897) );
HS65_LL_DFPQX4 clk_r_REG9_S2 ( .D(n7860), .CP(clk), .Q(n8896) );
HS65_LL_DFPQX4 clk_r_REG17_S2 ( .D(n8475), .CP(clk), .Q(n8895) );
HS65_LL_DFPQX4 clk_r_REG53_S3 ( .D(n8463), .CP(clk), .Q(n8893) );
HS65_LL_DFPQX4 clk_r_REG476_S3 ( .D(n8128), .CP(clk), .Q(n8892) );
HS65_LL_DFPQX4 clk_r_REG98_S2 ( .D(n8459), .CP(clk), .Q(n8891) );
HS65_LL_DFPQX4 clk_r_REG102_S2 ( .D(n8460), .CP(clk), .Q(n8890) );
HS65_LL_DFPQX4 clk_r_REG89_S3 ( .D(n8470), .CP(clk), .Q(n8889) );
HS65_LL_DFPQX4 clk_r_REG70_S2 ( .D(n8472), .CP(clk), .Q(n8888) );
HS65_LL_DFPQX4 clk_r_REG55_S3 ( .D(n8468), .CP(clk), .Q(n8887) );
HS65_LL_DFPQX4 clk_r_REG495_S3 ( .D(n8127), .CP(clk), .Q(n8886) );
HS65_LL_DFPQX4 clk_r_REG494_S3 ( .D(n8080), .CP(clk), .Q(n8885) );
HS65_LL_DFPQX4 clk_r_REG382_S3 ( .D(n8576), .CP(clk), .Q(n8884) );
HS65_LL_DFPQNX27 clk_r_REG1_S1 ( .D(\u_DataPath/u_exmemreg/N78 ), .CP(clk),
.QN(n7835) );
HS65_LL_DFPQX4 clk_r_REG35_S2 ( .D(n7839), .CP(clk), .Q(n8883) );
HS65_LL_DFPQX4 clk_r_REG69_S2 ( .D(n8437), .CP(clk), .Q(n8882) );
HS65_LL_DFPQX4 clk_r_REG57_S4 ( .D(\lte_x_59/B[5] ), .CP(clk), .Q(n8881) );
HS65_LL_DFPQX4 clk_r_REG390_S3 ( .D(n8401), .CP(clk), .Q(n8880) );
HS65_LL_DFPQX4 clk_r_REG294_S1 ( .D(\u_DataPath/mem_writedata_out_i [4]),
.CP(clk), .Q(n8879) );
HS65_LL_DFPQX4 clk_r_REG493_S3 ( .D(n8077), .CP(clk), .Q(n8878) );
HS65_LL_DFPQX4 clk_r_REG492_S3 ( .D(n8094), .CP(clk), .Q(n8877) );
HS65_LL_DFPQX4 clk_r_REG50_S1 ( .D(n8428), .CP(clk), .Q(n8875) );
HS65_LL_DFPQX4 clk_r_REG290_S2 ( .D(\u_DataPath/mem_writedata_out_i [19]),
.CP(clk), .Q(n8874) );
HS65_LL_DFPQX4 clk_r_REG398_S2 ( .D(\u_DataPath/mem_writedata_out_i [2]),
.CP(clk), .Q(n8873) );
HS65_LL_DFPQX4 clk_r_REG295_S2 ( .D(\lte_x_59/B[4] ), .CP(clk), .Q(n8872) );
HS65_LL_DFPQX4 clk_r_REG475_S3 ( .D(n8100), .CP(clk), .Q(n8871) );
HS65_LL_DFPQX4 clk_r_REG147_S2 ( .D(\u_DataPath/u_execute/link_value_i [30]),
.CP(clk), .Q(n8869) );
HS65_LL_DFPQX4 clk_r_REG487_S1 ( .D(n8450), .CP(clk), .Q(n8868) );
HS65_LL_DFPQX4 clk_r_REG332_S1 ( .D(\u_DataPath/data_read_ex_1_i [4]), .CP(
clk), .Q(n8867) );
HS65_LL_DFPQX4 clk_r_REG336_S1 ( .D(\u_DataPath/data_read_ex_2_i [22]), .CP(
clk), .Q(n8866) );
HS65_LL_DFPQX4 clk_r_REG349_S1 ( .D(\u_DataPath/data_read_ex_2_i [13]), .CP(
clk), .Q(n8865) );
HS65_LL_DFPQX4 clk_r_REG401_S1 ( .D(\u_DataPath/data_read_ex_2_i [11]), .CP(
clk), .Q(n8864) );
HS65_LL_DFPQX4 clk_r_REG274_S1 ( .D(\u_DataPath/data_read_ex_2_i [9]), .CP(
clk), .Q(n8863) );
HS65_LL_DFPQX4 clk_r_REG51_S1 ( .D(\u_DataPath/data_read_ex_1_i [1]), .CP(
clk), .Q(n8861) );
HS65_LL_DFPQX4 clk_r_REG404_S1 ( .D(\u_DataPath/data_read_ex_1_i [8]), .CP(
clk), .Q(n8860) );
HS65_LL_DFPQX4 clk_r_REG280_S1 ( .D(\u_DataPath/data_read_ex_1_i [26]), .CP(
clk), .Q(n8859) );
HS65_LL_DFPQX4 clk_r_REG439_S1 ( .D(\u_DataPath/data_read_ex_1_i [3]), .CP(
clk), .Q(n8858) );
HS65_LL_DFPQX4 clk_r_REG360_S1 ( .D(\u_DataPath/data_read_ex_1_i [6]), .CP(
clk), .Q(n8857) );
HS65_LL_DFPQX4 clk_r_REG422_S1 ( .D(\u_DataPath/data_read_ex_1_i [12]), .CP(
clk), .Q(n8856) );
HS65_LL_DFPQX4 clk_r_REG424_S1 ( .D(\u_DataPath/data_read_ex_1_i [7]), .CP(
clk), .Q(n8855) );
HS65_LL_DFPQX4 clk_r_REG288_S1 ( .D(\u_DataPath/data_read_ex_1_i [19]), .CP(
clk), .Q(n8854) );
HS65_LL_DFPQX4 clk_r_REG14_S2 ( .D(n8476), .CP(clk), .Q(n8853) );
HS65_LL_DFPQX4 clk_r_REG11_S3 ( .D(n8467), .CP(clk), .Q(n8852) );
HS65_LL_DFPQX4 clk_r_REG420_S1 ( .D(\u_DataPath/data_read_ex_1_i [14]), .CP(
clk), .Q(n8851) );
HS65_LL_DFPQX4 clk_r_REG348_S1 ( .D(\u_DataPath/data_read_ex_1_i [13]), .CP(
clk), .Q(n8850) );
HS65_LL_DFPQX4 clk_r_REG423_S1 ( .D(\u_DataPath/data_read_ex_2_i [12]), .CP(
clk), .Q(n8849) );
HS65_LL_DFPQX4 clk_r_REG362_S1 ( .D(\u_DataPath/data_read_ex_2_i [5]), .CP(
clk), .Q(n8847) );
HS65_LL_DFPQX4 clk_r_REG342_S1 ( .D(\u_DataPath/data_read_ex_1_i [24]), .CP(
clk), .Q(n8846) );
HS65_LL_DFPQX4 clk_r_REG335_S1 ( .D(\u_DataPath/data_read_ex_1_i [22]), .CP(
clk), .Q(n8845) );
HS65_LL_DFPQX4 clk_r_REG426_S1 ( .D(\u_DataPath/data_read_ex_2_i [7]), .CP(
clk), .Q(n8844) );
HS65_LL_DFPQX4 clk_r_REG414_S1 ( .D(\u_DataPath/data_read_ex_2_i [18]), .CP(
clk), .Q(n8843) );
HS65_LL_DFPQX4 clk_r_REG289_S1 ( .D(\u_DataPath/data_read_ex_2_i [19]), .CP(
clk), .Q(n8842) );
HS65_LL_DFPQX4 clk_r_REG411_S1 ( .D(\u_DataPath/data_read_ex_1_i [27]), .CP(
clk), .Q(n8841) );
HS65_LL_DFPQX4 clk_r_REG380_S1 ( .D(\u_DataPath/data_read_ex_2_i [1]), .CP(
clk), .Q(n8840) );
HS65_LL_DFPQX4 clk_r_REG281_S1 ( .D(\u_DataPath/data_read_ex_2_i [23]), .CP(
clk), .Q(n8839) );
HS65_LL_DFPQX4 clk_r_REG416_S1 ( .D(\u_DataPath/data_read_ex_1_i [16]), .CP(
clk), .Q(n8838) );
HS65_LL_DFPQX4 clk_r_REG291_S1 ( .D(\u_DataPath/data_read_ex_2_i [17]), .CP(
clk), .Q(n8837) );
HS65_LL_DFPQX4 clk_r_REG276_S1 ( .D(\u_DataPath/data_read_ex_1_i [21]), .CP(
clk), .Q(n8836) );
HS65_LL_DFPQX4 clk_r_REG359_S1 ( .D(\u_DataPath/data_read_ex_2_i [6]), .CP(
clk), .Q(n8835) );
HS65_LL_DFPQX4 clk_r_REG338_S1 ( .D(\u_DataPath/data_read_ex_2_i [25]), .CP(
clk), .Q(n8833) );
HS65_LL_DFPQX4 clk_r_REG397_S1 ( .D(\u_DataPath/data_read_ex_2_i [31]), .CP(
clk), .Q(n8832) );
HS65_LL_DFPQX4 clk_r_REG37_S1 ( .D(\u_DataPath/data_read_ex_1_i [11]), .CP(
clk), .Q(n8831) );
HS65_LL_DFPQX4 clk_r_REG405_S1 ( .D(\u_DataPath/data_read_ex_2_i [8]), .CP(
clk), .Q(n8830) );
HS65_LL_DFPQX4 clk_r_REG488_S3 ( .D(n8087), .CP(clk), .Q(n8829) );
HS65_LL_DFPQX4 clk_r_REG54_S3 ( .D(n7848), .CP(clk), .Q(n8828) );
HS65_LL_DFPRQX4 clk_r_REG192_S5 ( .D(\u_DataPath/pc4_to_idexreg_i [31]),
.CP(clk), .RN(n8676), .Q(n8827) );
HS65_LL_DFPQX4 clk_r_REG67_S1 ( .D(\u_DataPath/data_read_ex_1_i [29]), .CP(
clk), .Q(n8826) );
HS65_LL_DFPQX4 clk_r_REG286_S1 ( .D(\u_DataPath/data_read_ex_1_i [20]), .CP(
clk), .Q(n8825) );
HS65_LL_DFPQX4 clk_r_REG413_S1 ( .D(\u_DataPath/data_read_ex_1_i [18]), .CP(
clk), .Q(n8824) );
HS65_LL_DFPQX4 clk_r_REG396_S1 ( .D(\u_DataPath/data_read_ex_1_i [31]), .CP(
clk), .Q(n8823) );
HS65_LL_DFPQX4 clk_r_REG91_S1 ( .D(\u_DataPath/data_read_ex_1_i [17]), .CP(
clk), .Q(n8822) );
HS65_LL_DFPQX4 clk_r_REG357_S2 ( .D(\u_DataPath/data_read_ex_1_i [28]), .CP(
clk), .Q(n8821) );
HS65_LL_DFPRQX4 clk_r_REG610_S3 ( .D(\u_DataPath/immediate_ext_dec_i [15]),
.CP(clk), .RN(n9354), .Q(n8818) );
HS65_LL_DFPRQX4 clk_r_REG131_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [14]),
.CP(clk), .RN(n8676), .Q(n8815) );
HS65_LL_DFPRQX4 clk_r_REG250_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [15]),
.CP(clk), .RN(n9361), .Q(n8814) );
HS65_LL_DFPRQX4 clk_r_REG372_S3 ( .D(\u_DataPath/pc4_to_idexreg_i [2]), .CP(
clk), .RN(n2877), .Q(n8811) );
HS65_LL_DFPRQX4 clk_r_REG4_S3 ( .D(\u_DataPath/pc4_to_idexreg_i [3]), .CP(
clk), .RN(n9361), .Q(n8810) );
HS65_LL_DFPQX4 clk_r_REG88_S3 ( .D(n8462), .CP(clk), .Q(n8801) );
HS65_LL_DFPQX4 clk_r_REG273_S1 ( .D(\u_DataPath/data_read_ex_1_i [9]), .CP(
clk), .Q(n8800) );
HS65_LL_DFPQX4 clk_r_REG84_S1 ( .D(\u_DataPath/data_read_ex_1_i [25]), .CP(
clk), .Q(n8799) );
HS65_LL_DFPQX4 clk_r_REG400_S1 ( .D(\u_DataPath/data_read_ex_1_i [2]), .CP(
clk), .Q(n8798) );
HS65_LL_DFPRQX4 clk_r_REG199_S5 ( .D(\u_DataPath/pc4_to_idexreg_i [29]),
.CP(clk), .RN(n9361), .Q(n8796) );
HS65_LL_DFPRQX4 clk_r_REG236_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [17]),
.CP(clk), .RN(n8676), .Q(n8795) );
HS65_LL_DFPQX4 clk_r_REG526_S2 ( .D(opcode_i[3]), .CP(clk), .Q(n8794) );
HS65_LL_DFPRQX4 clk_r_REG607_S3 ( .D(\u_DataPath/immediate_ext_dec_i [14]),
.CP(clk), .RN(n9354), .Q(n8791) );
HS65_LL_DFPRQX4 clk_r_REG601_S3 ( .D(\u_DataPath/immediate_ext_dec_i [12]),
.CP(clk), .RN(n9354), .Q(n8789) );
HS65_LL_DFPRQX4 clk_r_REG598_S3 ( .D(\u_DataPath/immediate_ext_dec_i [11]),
.CP(clk), .RN(n9354), .Q(n8788) );
HS65_LL_DFPRQX4 clk_r_REG595_S3 ( .D(\u_DataPath/immediate_ext_dec_i [4]),
.CP(clk), .RN(n9354), .Q(n8780) );
HS65_LL_DFPRQX4 clk_r_REG590_S3 ( .D(\u_DataPath/immediate_ext_dec_i [5]),
.CP(clk), .RN(n9354), .Q(n8779) );
HS65_LL_DFPRQX4 clk_r_REG587_S3 ( .D(\u_DataPath/immediate_ext_dec_i [6]),
.CP(clk), .RN(n9354), .Q(n8778) );
HS65_LL_DFPQX4 clk_r_REG584_S3 ( .D(\u_DataPath/immediate_ext_dec_i [0]),
.CP(clk), .Q(n8777) );
HS65_LL_DFPRQX4 clk_r_REG583_S3 ( .D(\u_DataPath/immediate_ext_dec_i [0]),
.CP(clk), .RN(n9354), .Q(n8776) );
HS65_LL_DFPQX4 clk_r_REG577_S3 ( .D(\u_DataPath/immediate_ext_dec_i [1]),
.CP(clk), .Q(n8775) );
HS65_LL_DFPRQX4 clk_r_REG576_S3 ( .D(\u_DataPath/immediate_ext_dec_i [1]),
.CP(clk), .RN(n9354), .Q(n8774) );
HS65_LL_DFPRQX4 clk_r_REG569_S3 ( .D(\u_DataPath/immediate_ext_dec_i [3]),
.CP(clk), .RN(n9354), .Q(n8772) );
HS65_LL_DFPQX4 clk_r_REG564_S3 ( .D(\u_DataPath/immediate_ext_dec_i [2]),
.CP(clk), .Q(n8771) );
HS65_LL_DFPRQX4 clk_r_REG563_S3 ( .D(\u_DataPath/immediate_ext_dec_i [2]),
.CP(clk), .RN(n9354), .Q(n8770) );
HS65_LL_DFPQX4 clk_r_REG491_S3 ( .D(n8099), .CP(clk), .Q(n8767) );
HS65_LL_DFPQX4 clk_r_REG504_S1 ( .D(\u_DataPath/RFaddr_out_memwb_i [1]),
.CP(clk), .Q(n8766) );
HS65_LL_DFPQX4 clk_r_REG502_S1 ( .D(\u_DataPath/RFaddr_out_memwb_i [2]),
.CP(clk), .Q(n8764) );
HS65_LL_DFPQX4 clk_r_REG500_S1 ( .D(\u_DataPath/RFaddr_out_memwb_i [0]),
.CP(clk), .Q(n8763) );
HS65_LL_DFPQX4 clk_r_REG498_S1 ( .D(\u_DataPath/RFaddr_out_memwb_i [4]),
.CP(clk), .Q(n8762) );
HS65_LL_DFPQX4 clk_r_REG496_S1 ( .D(\u_DataPath/RFaddr_out_memwb_i [3]),
.CP(clk), .Q(n8761) );
HS65_LL_DFPQX4 clk_r_REG78_S2 ( .D(n8309), .CP(clk), .Q(n8760) );
HS65_LL_DFPQX4 clk_r_REG352_S2 ( .D(n8296), .CP(clk), .Q(n8759) );
HS65_LL_DFPQX4 clk_r_REG386_S2 ( .D(n8169), .CP(clk), .Q(n8758) );
HS65_LL_DFPRQX4 clk_r_REG561_S3 ( .D(\u_DataPath/jaddr_i [25]), .CP(clk),
.RN(n9354), .Q(n8756) );
HS65_LL_DFPQX4 clk_r_REG486_S3 ( .D(\u_DataPath/cw_to_ex_i [17]), .CP(clk),
.Q(n8755) );
HS65_LL_DFPRQX4 clk_r_REG533_S2 ( .D(\u_DataPath/jaddr_i [16]), .CP(clk),
.RN(n9354), .Q(n8754) );
HS65_LL_DFPQX4 clk_r_REG351_S2 ( .D(n8181), .CP(clk), .Q(n8753) );
HS65_LL_DFPQX4 clk_r_REG344_S2 ( .D(n8305), .CP(clk), .Q(n8752) );
HS65_LL_DFPQX4 clk_r_REG481_S3 ( .D(n8057), .CP(clk), .Q(n8750) );
HS65_LL_DFPQX4 clk_r_REG65_S2 ( .D(\u_DataPath/mem_writedata_out_i [29]),
.CP(clk), .Q(n8749) );
HS65_LL_DFPQX4 clk_r_REG285_S2 ( .D(\u_DataPath/mem_writedata_out_i [20]),
.CP(clk), .Q(n8747) );
HS65_LL_DFPQX4 clk_r_REG106_S2 ( .D(\u_DataPath/mem_writedata_out_i [21]),
.CP(clk), .Q(n8746) );
HS65_LL_DFPQX4 clk_r_REG13_S2 ( .D(\u_DataPath/mem_writedata_out_i [7]),
.CP(clk), .Q(n8745) );
HS65_LL_DFPQX4 clk_r_REG381_S2 ( .D(\u_DataPath/mem_writedata_out_i [1]),
.CP(clk), .Q(n8744) );
HS65_LL_DFPQX4 clk_r_REG358_S2 ( .D(\u_DataPath/mem_writedata_out_i [6]),
.CP(clk), .Q(n8743) );
HS65_LL_DFPQX4 clk_r_REG75_S1 ( .D(\u_DataPath/mem_writedata_out_i [13]),
.CP(clk), .Q(n8742) );
HS65_LL_DFPQX4 clk_r_REG72_S1 ( .D(\u_DataPath/mem_writedata_out_i [10]),
.CP(clk), .Q(n8741) );
HS65_LL_DFPQX4 clk_r_REG418_S1 ( .D(\u_DataPath/mem_writedata_out_i [14]),
.CP(clk), .Q(n8739) );
HS65_LL_DFPQX4 clk_r_REG23_S1 ( .D(\u_DataPath/mem_writedata_out_i [16]),
.CP(clk), .Q(n8738) );
HS65_LL_DFPQX4 clk_r_REG415_S1 ( .D(\u_DataPath/mem_writedata_out_i [18]),
.CP(clk), .Q(n8737) );
HS65_LL_DFPQX4 clk_r_REG282_S1 ( .D(\u_DataPath/mem_writedata_out_i [23]),
.CP(clk), .Q(n8736) );
HS65_LL_DFPQX4 clk_r_REG402_S1 ( .D(\u_DataPath/mem_writedata_out_i [11]),
.CP(clk), .Q(n8735) );
HS65_LL_DFPQX4 clk_r_REG345_S1 ( .D(\u_DataPath/mem_writedata_out_i [15]),
.CP(clk), .Q(n8734) );
HS65_LL_DFPQX4 clk_r_REG278_S1 ( .D(\u_DataPath/mem_writedata_out_i [26]),
.CP(clk), .Q(n8733) );
HS65_LL_DFPQX4 clk_r_REG363_S1 ( .D(\u_DataPath/mem_writedata_out_i [5]),
.CP(clk), .Q(n8731) );
HS65_LL_DFPQX4 clk_r_REG16_S1 ( .D(\u_DataPath/mem_writedata_out_i [12]),
.CP(clk), .Q(n8730) );
HS65_LL_DFPQX4 clk_r_REG408_S1 ( .D(\u_DataPath/mem_writedata_out_i [30]),
.CP(clk), .Q(n8729) );
HS65_LL_DFPQX4 clk_r_REG44_S1 ( .D(\u_DataPath/mem_writedata_out_i [31]),
.CP(clk), .Q(n8728) );
HS65_LL_DFPQX4 clk_r_REG334_S1 ( .D(\u_DataPath/mem_writedata_out_i [22]),
.CP(clk), .Q(n8727) );
HS65_LL_DFPQX4 clk_r_REG272_S1 ( .D(\u_DataPath/mem_writedata_out_i [9]),
.CP(clk), .Q(n8726) );
HS65_LL_DFPQX4 clk_r_REG331_S1 ( .D(\u_DataPath/data_read_ex_2_i [4]), .CP(
clk), .Q(n8724) );
HS65_LL_DFPQX4 clk_r_REG419_S1 ( .D(\u_DataPath/data_read_ex_2_i [14]), .CP(
clk), .Q(n8723) );
HS65_LL_DFPQX4 clk_r_REG407_S1 ( .D(\u_DataPath/data_read_ex_2_i [30]), .CP(
clk), .Q(n8722) );
HS65_LL_DFPQX4 clk_r_REG410_S1 ( .D(\u_DataPath/data_read_ex_2_i [27]), .CP(
clk), .Q(n8721) );
HS65_LL_DFPQX4 clk_r_REG284_S1 ( .D(\u_DataPath/data_read_ex_2_i [20]), .CP(
clk), .Q(n8720) );
HS65_LL_DFPQX4 clk_r_REG66_S1 ( .D(\u_DataPath/data_read_ex_2_i [29]), .CP(
clk), .Q(n8719) );
HS65_LL_DFPQX4 clk_r_REG22_S1 ( .D(\u_DataPath/data_read_ex_2_i [16]), .CP(
clk), .Q(n8718) );
HS65_LL_DFPQX4 clk_r_REG275_S1 ( .D(\u_DataPath/data_read_ex_2_i [21]), .CP(
clk), .Q(n8717) );
HS65_LL_DFPQX4 clk_r_REG399_S1 ( .D(\u_DataPath/data_read_ex_2_i [2]), .CP(
clk), .Q(n8716) );
HS65_LL_DFPQX4 clk_r_REG49_S1 ( .D(\u_DataPath/u_execute/psw_status_i [0]),
.CP(clk), .Q(n8715) );
HS65_LL_DFPQX4 clk_r_REG480_S3 ( .D(n8102), .CP(clk), .Q(n8702) );
HS65_LL_DFPQX4 clk_r_REG474_S3 ( .D(n8081), .CP(clk), .Q(n8696) );
HS65_LH_IVX2 U3797 ( .A(n9330), .Z(n8676) );
HS65_LH_IVX2 U3799 ( .A(n9330), .Z(n8677) );
HS65_LH_IVX2 U5114 ( .A(n2877), .Z(n9330) );
HS65_LH_DFPHQX4 clk_r_REG190_S3 ( .D(n8641), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8713) );
HS65_LH_DFPRQX4 clk_r_REG537_S2 ( .D(n8482), .CP(clk), .RN(n9356), .Q(n9069)
);
HS65_LH_DFPRQX4 clk_r_REG428_S2 ( .D(n8691), .CP(clk), .RN(n8676), .Q(n8690)
);
HS65_LH_DFPRQX4 clk_r_REG365_S2 ( .D(n8689), .CP(clk), .RN(n9361), .Q(n8688)
);
HS65_LH_DFPRQX4 clk_r_REG646_S1 ( .D(iram_data[0]), .CP(clk), .RN(n9355),
.Q(n9303) );
HS65_LH_DFPRQX4 clk_r_REG645_S1 ( .D(iram_data[1]), .CP(clk), .RN(n9356),
.Q(n9304) );
HS65_LH_DFPRQX4 clk_r_REG644_S1 ( .D(iram_data[2]), .CP(clk), .RN(n9355),
.Q(n9305) );
HS65_LH_DFPRQX4 clk_r_REG643_S1 ( .D(iram_data[3]), .CP(clk), .RN(n9356),
.Q(n9306) );
HS65_LH_DFPRQX4 clk_r_REG642_S1 ( .D(iram_data[4]), .CP(clk), .RN(n9355),
.Q(n9307) );
HS65_LH_DFPRQX4 clk_r_REG641_S1 ( .D(iram_data[5]), .CP(clk), .RN(n9356),
.Q(n9308) );
HS65_LH_DFPRQX4 clk_r_REG640_S1 ( .D(iram_data[6]), .CP(clk), .RN(n9355),
.Q(n9309) );
HS65_LH_DFPRQX4 clk_r_REG638_S1 ( .D(iram_data[8]), .CP(clk), .RN(n9354),
.Q(n9311) );
HS65_LH_DFPRQX4 clk_r_REG637_S1 ( .D(iram_data[9]), .CP(clk), .RN(n9361),
.Q(n9312) );
HS65_LH_DFPRQX4 clk_r_REG635_S1 ( .D(iram_data[11]), .CP(clk), .RN(n9356),
.Q(n9314) );
HS65_LH_DFPRQX4 clk_r_REG634_S1 ( .D(iram_data[12]), .CP(clk), .RN(n9355),
.Q(n9315) );
HS65_LH_DFPRQX4 clk_r_REG633_S1 ( .D(iram_data[13]), .CP(clk), .RN(n9356),
.Q(n9316) );
HS65_LH_DFPRQX4 clk_r_REG632_S1 ( .D(iram_data[14]), .CP(clk), .RN(n9355),
.Q(n9317) );
HS65_LH_DFPRQX4 clk_r_REG631_S1 ( .D(iram_data[15]), .CP(clk), .RN(n9356),
.Q(n9318) );
HS65_LH_DFPRQX4 clk_r_REG630_S1 ( .D(iram_data[16]), .CP(clk), .RN(n9355),
.Q(n9319) );
HS65_LH_DFPRQX4 clk_r_REG629_S1 ( .D(iram_data[17]), .CP(clk), .RN(n9356),
.Q(n9320) );
HS65_LH_DFPRQX4 clk_r_REG628_S1 ( .D(iram_data[18]), .CP(clk), .RN(n9355),
.Q(n9321) );
HS65_LH_DFPRQX4 clk_r_REG627_S1 ( .D(iram_data[19]), .CP(clk), .RN(n9356),
.Q(n9322) );
HS65_LH_DFPRQX4 clk_r_REG626_S1 ( .D(iram_data[20]), .CP(clk), .RN(n9355),
.Q(n9323) );
HS65_LH_DFPRQX4 clk_r_REG625_S1 ( .D(iram_data[21]), .CP(clk), .RN(n9356),
.Q(n9324) );
HS65_LH_DFPRQX4 clk_r_REG624_S1 ( .D(iram_data[22]), .CP(clk), .RN(n9355),
.Q(n9325) );
HS65_LH_DFPRQX4 clk_r_REG623_S1 ( .D(iram_data[23]), .CP(clk), .RN(n9356),
.Q(n9326) );
HS65_LH_DFPRQX4 clk_r_REG622_S1 ( .D(iram_data[24]), .CP(clk), .RN(n9355),
.Q(n9327) );
HS65_LH_DFPRQX4 clk_r_REG621_S1 ( .D(iram_data[25]), .CP(clk), .RN(n9356),
.Q(n9328) );
HS65_LH_DFPRQX4 clk_r_REG620_S1 ( .D(iram_data[27]), .CP(clk), .RN(n9355),
.Q(n9329) );
HS65_LH_DFPRQX4 clk_r_REG619_S1 ( .D(iram_data[29]), .CP(clk), .RN(n9356),
.Q(n9331) );
HS65_LH_DFPRQX4 clk_r_REG544_S3 ( .D(\u_DataPath/immediate_ext_dec_i [8]),
.CP(clk), .RN(n8676), .Q(n8783) );
HS65_LH_DFPRQX4 clk_r_REG547_S3 ( .D(\u_DataPath/immediate_ext_dec_i [9]),
.CP(clk), .RN(n9361), .Q(n8782) );
HS65_LH_DFPRQX4 clk_r_REG155_S5 ( .D(n9429), .CP(clk), .RN(n9355), .Q(n9159)
);
HS65_LH_DFPRQX4 clk_r_REG138_S4 ( .D(n9428), .CP(clk), .RN(n9356), .Q(n9163)
);
HS65_LH_DFPRQX4 clk_r_REG516_S2 ( .D(opcode_i[5]), .CP(clk), .RN(n8676), .Q(
n8786) );
HS65_LH_DFPRQX4 clk_r_REG265_S4 ( .D(n9422), .CP(clk), .RN(n9361), .Q(n9158)
);
HS65_LH_DFPRQX4 clk_r_REG215_S4 ( .D(n9426), .CP(clk), .RN(n8676), .Q(n9156)
);
HS65_LH_DFPRQX4 clk_r_REG208_S5 ( .D(n9420), .CP(clk), .RN(n9361), .Q(n9161)
);
HS65_LH_DFPRQX4 clk_r_REG170_S5 ( .D(n9427), .CP(clk), .RN(n8676), .Q(n9155)
);
HS65_LH_DFPRQX4 clk_r_REG113_S5 ( .D(n9423), .CP(clk), .RN(n9361), .Q(n9157)
);
HS65_LH_DFPRQX4 clk_r_REG519_S2 ( .D(\u_DataPath/jaddr_i [23]), .CP(clk),
.RN(n9355), .Q(n8820) );
HS65_LH_DFPRQX4 clk_r_REG525_S2 ( .D(opcode_i[3]), .CP(clk), .RN(n9355), .Q(
n8793) );
HS65_LH_DFPRQX4 clk_r_REG528_S2 ( .D(opcode_i[1]), .CP(clk), .RN(n9356), .Q(
n8792) );
HS65_LH_DFPRQX4 clk_r_REG521_S2 ( .D(\u_DataPath/jaddr_i [21]), .CP(clk),
.RN(n9356), .Q(n8817) );
HS65_LH_DFPRQX4 clk_r_REG557_S3 ( .D(\u_DataPath/jaddr_i [24]), .CP(clk),
.RN(n9355), .Q(n8819) );
HS65_LH_DFPRQX4 clk_r_REG553_S3 ( .D(\u_DataPath/jaddr_i [18]), .CP(clk),
.RN(n9356), .Q(n8787) );
HS65_LH_DFPRQX4 clk_r_REG523_S2 ( .D(\u_DataPath/jaddr_i [20]), .CP(clk),
.RN(n9355), .Q(n8816) );
HS65_LH_DFPRQX4 clk_r_REG297_S4 ( .D(\u_DataPath/pc_4_i [4]), .CP(clk), .RN(
n8676), .Q(n9009) );
HS65_LH_DFPRQX4 clk_r_REG529_S2 ( .D(\u_DataPath/jaddr_i [19]), .CP(clk),
.RN(n9356), .Q(n8785) );
HS65_LH_DFPRQX4 clk_r_REG531_S2 ( .D(\u_DataPath/jaddr_i [17]), .CP(clk),
.RN(n9355), .Q(n8757) );
HS65_LH_DFPRQX4 clk_r_REG326_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [5]), .CP(
clk), .RN(n9361), .Q(n8809) );
HS65_LH_DFPRQX4 clk_r_REG307_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [6]), .CP(
clk), .RN(n8676), .Q(n8807) );
HS65_LH_DFPRQX4 clk_r_REG298_S5 ( .D(\u_DataPath/pc4_to_idexreg_i [4]), .CP(
clk), .RN(n9361), .Q(n8768) );
HS65_LH_DFPSQX4 clk_r_REG507_S2 ( .D(opcode_i[0]), .CP(clk), .SN(n7879), .Q(
n9084) );
HS65_LH_DFPSQX4 clk_r_REG455_S2 ( .D(opcode_i[2]), .CP(clk), .SN(n7879), .Q(
n9082) );
HS65_LH_DFPSQX4 clk_r_REG440_S2 ( .D(opcode_i[4]), .CP(clk), .SN(n7879), .Q(
n9068) );
HS65_LH_DFPHQX4 clk_r_REG427_S1 ( .D(\u_DataPath/pc_4_i [0]), .E(
\u_DataPath/u_fetch/pc1/N3 ), .CP(clk), .Q(n8691) );
HS65_LH_DFPHQX4 clk_r_REG370_S1 ( .D(n8670), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8687) );
HS65_LH_DFPHQX4 clk_r_REG364_S1 ( .D(\u_DataPath/pc_4_i [1]), .E(
\u_DataPath/u_fetch/pc1/N3 ), .CP(clk), .Q(n8689) );
HS65_LH_DFPHQX4 clk_r_REG324_S2 ( .D(n8667), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8684) );
HS65_LH_DFPHQX4 clk_r_REG316_S2 ( .D(n8665), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8682) );
HS65_LH_DFPHQX4 clk_r_REG310_S2 ( .D(n8664), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8680) );
HS65_LH_DFPHQX4 clk_r_REG305_S2 ( .D(n8666), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8683) );
HS65_LH_DFPHQX4 clk_r_REG296_S3 ( .D(n8668), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8685) );
HS65_LH_DFPHQX4 clk_r_REG263_S2 ( .D(n8661), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8679) );
HS65_LH_DFPHQX4 clk_r_REG117_S2 ( .D(n8662), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8681) );
HS65_LH_DFPHQX4 clk_r_REG111_S3 ( .D(n8663), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8678) );
HS65_LH_DFPHQX4 clk_r_REG2_S1 ( .D(n8669), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8686) );
HS65_LH_DFPHQX4 clk_r_REG256_S2 ( .D(n8660), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8695) );
HS65_LH_DFPHQX4 clk_r_REG129_S2 ( .D(n8658), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8694) );
HS65_LH_DFPHQX4 clk_r_REG123_S2 ( .D(n8659), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8698) );
HS65_LH_DFPHQX4 clk_r_REG213_S2 ( .D(n8654), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8693) );
HS65_LH_DFPHQX4 clk_r_REG168_S3 ( .D(n8646), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8701) );
HS65_LH_DFPHQX4 clk_r_REG248_S2 ( .D(n8657), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8699) );
HS65_LH_DFPHQX4 clk_r_REG174_S2 ( .D(n8645), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8703) );
HS65_LH_DFPHQX4 clk_r_REG241_S2 ( .D(n8656), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8704) );
HS65_LH_DFPHQX4 clk_r_REG221_S2 ( .D(n8653), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8692) );
HS65_LH_DFPHQX4 clk_r_REG163_S3 ( .D(n8647), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8700) );
HS65_LH_DFPHQX4 clk_r_REG226_S2 ( .D(n8652), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8697) );
HS65_LH_DFPHQX4 clk_r_REG180_S3 ( .D(n8644), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8707) );
HS65_LH_DFPHQX4 clk_r_REG234_S2 ( .D(n8655), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8709) );
HS65_LH_DFPHQX4 clk_r_REG153_S3 ( .D(n8650), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8708) );
HS65_LH_DFPHQX4 clk_r_REG197_S3 ( .D(n8643), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8710) );
HS65_LH_DFPHQX4 clk_r_REG206_S3 ( .D(n8649), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8706) );
HS65_LH_DFPHQX4 clk_r_REG158_S3 ( .D(n8648), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8711) );
HS65_LH_DFPHQX4 clk_r_REG185_S3 ( .D(n8642), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8712) );
HS65_LH_DFPHQX4 clk_r_REG136_S2 ( .D(n8651), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8705) );
HS65_LH_DFPQX4 clk_r_REG46_S2 ( .D(n9118), .CP(clk), .Q(n9117) );
HS65_LL_DFPQNX4 clk_r_REG466_S1 ( .D(n8048), .CP(clk), .QN(
\u_DataPath/cw_towb_i [1]) );
HS65_LH_DFPQX9 clk_r_REG436_S3 ( .D(nibble[0]), .CP(clk), .Q(n9128) );
HS65_LL_DFPRQX9 clk_r_REG613_S1 ( .D(n7923), .CP(clk), .RN(n9356), .Q(n9252)
);
HS65_LL_DFPQX9 clk_r_REG562_S1 ( .D(n8626), .CP(clk), .Q(n8911) );
HS65_LH_DFPQX9 clk_r_REG541_S3 ( .D(n8073), .CP(clk), .Q(n8751) );
HS65_LH_DFPQX9 clk_r_REG591_S3 ( .D(n8074), .CP(clk), .Q(n9002) );
HS65_LH_DFPQX9 clk_r_REG582_S3 ( .D(n8123), .CP(clk), .Q(n9146) );
HS65_LH_DFPQX9 clk_r_REG482_S4 ( .D(\u_DataPath/u_idexreg/N184 ), .CP(clk),
.Q(n8876) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][12] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][14] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][8] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][28] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][7] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][13] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][11] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][30] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][20] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][24] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][13] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][14] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][14] ) );
HS65_LH_DFPQX4 clk_r_REG665_S1 ( .D(Data_out_fromRAM[21]), .CP(clk), .Q(
n9294) );
HS65_LH_DFPQX4 clk_r_REG687_S1 ( .D(Data_out_fromRAM[5]), .CP(clk), .Q(n9279) );
HS65_LH_DFPQX4 clk_r_REG287_S3 ( .D(n2849), .CP(clk), .Q(n9262) );
HS65_LH_DFPQX4 clk_r_REG653_S1 ( .D(n8417), .CP(clk), .Q(n9246) );
HS65_LH_DFPQX4 clk_r_REG114_S1 ( .D(\u_DataPath/pc_4_to_ex_i [9]), .CP(clk),
.Q(n9231) );
HS65_LH_DFPQX4 clk_r_REG139_S1 ( .D(\u_DataPath/pc_4_to_ex_i [21]), .CP(clk),
.Q(n9216) );
HS65_LH_DFPQX4 clk_r_REG101_S3 ( .D(n7838), .CP(clk), .Q(n9201) );
HS65_LH_DFPQX4 clk_r_REG353_S1 ( .D(n7947), .CP(clk), .Q(n9186) );
HS65_LH_DFPQX4 clk_r_REG551_S1 ( .D(\u_DataPath/immediate_ext_ex_i [10]),
.CP(clk), .Q(n9171) );
HS65_LH_DFPQX4 clk_r_REG377_S1 ( .D(\u_DataPath/branch_target_i [3]), .CP(
clk), .Q(n9147) );
HS65_LH_DFPQX4 clk_r_REG617_S1 ( .D(n8058), .CP(clk), .Q(n9130) );
HS65_LH_DFPQX4 clk_r_REG478_S1 ( .D(\u_DataPath/cw_tomem_i [5]), .CP(clk),
.Q(n9113) );
HS65_LH_DFPRQX9 clk_r_REG317_S3 ( .D(\u_DataPath/pc_4_i [7]), .CP(clk), .RN(
n9362), .Q(n9098) );
HS65_LH_DFPQX4 clk_r_REG261_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [12]),
.CP(clk), .Q(n9064) );
HS65_LH_DFPQX4 clk_r_REG585_S1 ( .D(\u_DataPath/immediate_ext_ex_i [0]),
.CP(clk), .Q(n9035) );
HS65_LH_DFPQX4 clk_r_REG150_S2 ( .D(\u_DataPath/u_execute/link_value_i [26]),
.CP(clk), .Q(n9020) );
HS65_LH_DFPRQX4 clk_r_REG112_S4 ( .D(\u_DataPath/pc_4_i [9]), .CP(clk), .RN(
n2877), .Q(n8973) );
HS65_LH_DFPQX4 clk_r_REG321_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [6]),
.CP(clk), .Q(n8959) );
HS65_LH_DFPQX4 clk_r_REG211_S1 ( .D(\u_DataPath/branch_target_i [22]), .CP(
clk), .Q(n8929) );
HS65_LH_DFPQX4 clk_r_REG485_S1 ( .D(\u_DataPath/cw_tomem_i [3]), .CP(clk),
.Q(n8915) );
HS65_LH_DFPQX4 clk_r_REG59_S1 ( .D(\u_DataPath/from_alu_data_out_i [6]),
.CP(clk), .Q(n8908) );
HS65_LH_DFPQNX4 clk_r_REG28_S1 ( .D(\u_DataPath/from_alu_data_out_i [27]),
.CP(clk), .QN(n3020) );
HS65_LH_DFPQX4 clk_r_REG39_S2 ( .D(n8464), .CP(clk), .Q(n8894) );
HS65_LH_DFPQX4 clk_r_REG283_S1 ( .D(\u_DataPath/data_read_ex_1_i [23]), .CP(
clk), .Q(n8848) );
HS65_LH_DFPQX4 clk_r_REG409_S1 ( .D(\u_DataPath/data_read_ex_1_i [30]), .CP(
clk), .Q(n8834) );
HS65_LH_DFPRQX4 clk_r_REG160_S5 ( .D(\u_DataPath/pc4_to_idexreg_i [24]),
.CP(clk), .RN(n9361), .Q(n8797) );
HS65_LH_DFPQX4 clk_r_REG570_S3 ( .D(\u_DataPath/immediate_ext_dec_i [3]),
.CP(clk), .Q(n8773) );
HS65_LH_DFPQX4 clk_r_REG292_S1 ( .D(\u_DataPath/mem_writedata_out_i [17]),
.CP(clk), .Q(n8740) );
HS65_LH_DFPQX4 clk_r_REG438_S1 ( .D(\u_DataPath/mem_writedata_out_i [3]),
.CP(clk), .Q(n8725) );
HS65_LH_DFPQX4 clk_r_REG506_S4 ( .D(\u_DataPath/cw_to_ex_i [15]), .CP(clk),
.Q(n8714) );
HS65_LH_DFPRQX9 clk_r_REG318_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [7]), .CP(
clk), .RN(n9360), .Q(n8806) );
HS65_LH_DFPRQX9 clk_r_REG3_S2 ( .D(\u_DataPath/pc_4_i [3]), .CP(clk), .RN(
n9360), .Q(n8970) );
HS65_LH_DFPRQX9 clk_r_REG187_S5 ( .D(n9421), .CP(clk), .RN(n9360), .Q(n9143)
);
HS65_LH_DFPRQX9 clk_r_REG258_S4 ( .D(n9419), .CP(clk), .RN(n9360), .Q(n9265)
);
HS65_LH_DFPRQX9 clk_r_REG550_S3 ( .D(\u_DataPath/immediate_ext_dec_i [10]),
.CP(clk), .RN(n9360), .Q(n8781) );
HS65_LH_DFPRQX9 clk_r_REG371_S2 ( .D(\u_DataPath/pc_4_i [2]), .CP(clk), .RN(
n9360), .Q(n9273) );
HS65_LH_DFPRQX9 clk_r_REG223_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [19]),
.CP(clk), .RN(n9360), .Q(n8813) );
HS65_LH_DFPRQX9 clk_r_REG165_S5 ( .D(\u_DataPath/pc4_to_idexreg_i [25]),
.CP(clk), .RN(n9360), .Q(n8802) );
HS65_LH_DFPRQX9 clk_r_REG119_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [10]),
.CP(clk), .RN(n9360), .Q(n8804) );
HS65_LH_DFPRQX9 clk_r_REG325_S3 ( .D(\u_DataPath/pc_4_i [5]), .CP(clk), .RN(
n9360), .Q(n8971) );
HS65_LH_DFPRQX9 clk_r_REG311_S3 ( .D(\u_DataPath/pc_4_i [8]), .CP(clk), .RN(
n9360), .Q(n9010) );
HS65_LH_DFPRQX9 clk_r_REG130_S3 ( .D(\u_DataPath/pc_4_i [14]), .CP(clk),
.RN(n9360), .Q(n8984) );
HS65_LH_DFPRQX9 clk_r_REG249_S3 ( .D(\u_DataPath/pc_4_i [15]), .CP(clk),
.RN(n9360), .Q(n9097) );
HS65_LH_DFPRQX9 clk_r_REG164_S4 ( .D(\u_DataPath/pc_4_i [25]), .CP(clk),
.RN(n9360), .Q(n8980) );
HS65_LH_DFPRQX9 clk_r_REG198_S4 ( .D(\u_DataPath/pc_4_i [29]), .CP(clk),
.RN(n9360), .Q(n8993) );
HS65_LH_DFPRQX9 clk_r_REG536_S1 ( .D(n7921), .CP(clk), .RN(n9360), .Q(n9192)
);
HS65_LH_DFPRQX9 clk_r_REG515_S1 ( .D(n7924), .CP(clk), .RN(n9360), .Q(n9139)
);
HS65_LH_DFPRQX9 clk_r_REG556_S2 ( .D(n7918), .CP(clk), .RN(n9360), .Q(n9154)
);
HS65_LH_DFPRQX9 clk_r_REG636_S1 ( .D(iram_data[10]), .CP(clk), .RN(n9360),
.Q(n9313) );
HS65_LH_DFPRQX9 clk_r_REG312_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [8]), .CP(
clk), .RN(n9362), .Q(n8805) );
HS65_LH_DFPRQX9 clk_r_REG429_S3 ( .D(\u_DataPath/pc4_to_idexreg_i [0]), .CP(
clk), .RN(n9362), .Q(n8862) );
HS65_LH_DFPRQX9 clk_r_REG182_S5 ( .D(n9425), .CP(clk), .RN(n9362), .Q(n9160)
);
HS65_LH_DFPRQX9 clk_r_REG243_S4 ( .D(n9424), .CP(clk), .RN(n9362), .Q(n9162)
);
HS65_LH_DFPRQX9 clk_r_REG540_S3 ( .D(\u_DataPath/immediate_ext_dec_i [7]),
.CP(clk), .RN(n9362), .Q(n8784) );
HS65_LH_DFPRQX9 clk_r_REG228_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [20]),
.CP(clk), .RN(n9362), .Q(n8812) );
HS65_LH_DFPRQX9 clk_r_REG176_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [27]),
.CP(clk), .RN(n9362), .Q(n8769) );
HS65_LH_DFPRQX9 clk_r_REG125_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [13]),
.CP(clk), .RN(n9362), .Q(n8803) );
HS65_LH_DFPRQX9 clk_r_REG366_S3 ( .D(\u_DataPath/pc4_to_idexreg_i [1]), .CP(
clk), .RN(n9362), .Q(n8808) );
HS65_LH_DFPRQX9 clk_r_REG257_S3 ( .D(\u_DataPath/pc_4_i [12]), .CP(clk),
.RN(n9362), .Q(n9067) );
HS65_LH_DFPRQX9 clk_r_REG169_S4 ( .D(\u_DataPath/pc_4_i [26]), .CP(clk),
.RN(n9362), .Q(n8976) );
HS65_LH_DFPRQX9 clk_r_REG222_S3 ( .D(\u_DataPath/pc_4_i [19]), .CP(clk),
.RN(n9362), .Q(n8979) );
HS65_LH_DFPRQX9 clk_r_REG235_S3 ( .D(\u_DataPath/pc_4_i [17]), .CP(clk),
.RN(n9362), .Q(n8994) );
HS65_LH_DFPRQX9 clk_r_REG186_S4 ( .D(\u_DataPath/pc_4_i [30]), .CP(clk),
.RN(n9362), .Q(n8995) );
HS65_LH_DFPRQX9 clk_r_REG614_S1 ( .D(n7923), .CP(clk), .RN(n9362), .Q(n9253)
);
HS65_LH_DFPRQX9 clk_r_REG539_S2 ( .D(n7920), .CP(clk), .RN(n9362), .Q(n9142)
);
HS65_LH_DFPRQX9 clk_r_REG618_S1 ( .D(iram_data[31]), .CP(clk), .RN(n9362),
.Q(n9333) );
HS65_LH_DFPRQX9 clk_r_REG639_S1 ( .D(iram_data[7]), .CP(clk), .RN(n9362),
.Q(n9310) );
HS65_LL_IVX18 U3679 ( .A(\u_DataPath/cw_towb_i [1]), .Z(n3030) );
HS65_LH_IVX9 U4423 ( .A(n8968), .Z(n2947) );
HS65_LH_DFPQNX4 clk_r_REG33_S1 ( .D(\u_DataPath/from_alu_data_out_i [8]),
.CP(clk), .QN(n3212) );
HS65_LH_DFPQNX4 clk_r_REG109_S1 ( .D(\u_DataPath/from_alu_data_out_i [9]),
.CP(clk), .QN(n3079) );
HS65_LH_DFPQNX4 clk_r_REG434_S1 ( .D(n8621), .CP(clk), .QN(n3016) );
HS65_LL_DFPQNX4 clk_r_REG36_S1 ( .D(\u_DataPath/from_alu_data_out_i [11]),
.CP(clk), .QN(n3069) );
HS65_LH_DFPQNX4 clk_r_REG90_S1 ( .D(\u_DataPath/from_alu_data_out_i [17]),
.CP(clk), .QN(n3024) );
HS65_LH_DFPQNX4 clk_r_REG74_S1 ( .D(\u_DataPath/from_alu_data_out_i [13]),
.CP(clk), .QN(n3248) );
HS65_LH_CBI4I1X5 U3841 ( .A(n8801), .B(n8893), .C(n9189), .D(n8432), .Z(
\u_DataPath/dataOut_exe_i [3]) );
HS65_LH_IVX18 U4322 ( .A(n9401), .Z(n2866) );
HS65_LH_DFPQNX4 clk_r_REG15_S1 ( .D(\u_DataPath/from_alu_data_out_i [12]),
.CP(clk), .QN(n3259) );
HS65_LL_DFPQNX4 clk_r_REG437_S1 ( .D(\u_DataPath/data_read_ex_2_i [3]), .CP(
clk), .QN(n3309) );
HS65_LH_DFPQNX4 clk_r_REG43_S1 ( .D(\u_DataPath/from_alu_data_out_i [31]),
.CP(clk), .QN(n3406) );
HS65_LH_DFPQNX4 clk_r_REG21_S1 ( .D(\u_DataPath/from_alu_data_out_i [16]),
.CP(clk), .QN(n3093) );
HS65_LH_DFPQNX4 clk_r_REG86_S1 ( .D(\u_DataPath/from_alu_data_out_i [22]),
.CP(clk), .QN(n3166) );
HS65_LH_DFPQNX4 clk_r_REG18_S1 ( .D(\u_DataPath/from_alu_data_out_i [14]),
.CP(clk), .QN(n3088) );
HS65_LH_DFPQNX4 clk_r_REG31_S1 ( .D(\u_DataPath/from_alu_data_out_i [30]),
.CP(clk), .QN(n3047) );
HS65_LH_DFPQNX4 clk_r_REG94_S1 ( .D(\u_DataPath/from_alu_data_out_i [19]),
.CP(clk), .QN(n3185) );
HS65_LH_DFPQNX4 clk_r_REG96_S1 ( .D(\u_DataPath/from_alu_data_out_i [20]),
.CP(clk), .QN(n3175) );
HS65_LH_DFPQNX4 clk_r_REG293_S1 ( .D(n8579), .CP(clk), .QN(n2972) );
HS65_LH_DFPQNX4 clk_r_REG40_S1 ( .D(\u_DataPath/from_alu_data_out_i [2]),
.CP(clk), .QN(n2934) );
HS65_LH_DFPQNX4 clk_r_REG12_S1 ( .D(\u_DataPath/from_alu_data_out_i [7]),
.CP(clk), .QN(n3103) );
HS65_LH_DFPQNX4 clk_r_REG64_S1 ( .D(\u_DataPath/from_alu_data_out_i [29]),
.CP(clk), .QN(n2968) );
HS65_LH_DFPQNX4 clk_r_REG99_S1 ( .D(\u_DataPath/from_alu_data_out_i [23]),
.CP(clk), .QN(n3018) );
HS65_LH_DFPQNX4 clk_r_REG103_S1 ( .D(\u_DataPath/u_memwbreg/N64 ), .CP(clk),
.QN(n7877) );
HS65_LH_DFPQNX4 clk_r_REG105_S1 ( .D(\u_DataPath/from_alu_data_out_i [21]),
.CP(clk), .QN(n2956) );
HS65_LH_DFPQNX4 clk_r_REG80_S1 ( .D(\u_DataPath/from_alu_data_out_i [24]),
.CP(clk), .QN(n3137) );
HS65_LH_DFPQNX4 clk_r_REG7_S1 ( .D(\u_DataPath/from_alu_data_out_i [3]),
.CP(clk), .QN(n2970) );
HS65_LH_DFPQNX4 clk_r_REG56_S1 ( .D(\u_DataPath/from_alu_data_out_i [5]),
.CP(clk), .QN(n3332) );
HS65_LL_NAND2AX14 U3939 ( .A(n3289), .B(n2910), .Z(n5136) );
HS65_LL_IVX18 U4300 ( .A(n3082), .Z(n3341) );
HS65_LH_DFPQNX4 clk_r_REG25_S1 ( .D(\u_DataPath/from_alu_data_out_i [18]),
.CP(clk), .QN(n3084) );
HS65_LH_DFPQNX4 clk_r_REG83_S1 ( .D(\u_DataPath/from_alu_data_out_i [25]),
.CP(clk), .QN(n3098) );
HS65_LH_NAND3AX6 U3714 ( .A(n8507), .B(n9376), .C(n8508), .Z(n3245) );
HS65_LH_IVX9 U3930 ( .A(n2845), .Z(n2855) );
HS65_LL_DFPQNX4 clk_r_REG279_S1 ( .D(\u_DataPath/data_read_ex_2_i [26]),
.CP(clk), .QN(n3152) );
HS65_LL_DFPQNX4 clk_r_REG341_S1 ( .D(\u_DataPath/data_read_ex_2_i [24]),
.CP(clk), .QN(n3143) );
HS65_LL_DFPQNX4 clk_r_REG361_S1 ( .D(\u_DataPath/data_read_ex_1_i [5]), .CP(
clk), .QN(n3335) );
HS65_LL_DFPQNX4 clk_r_REG356_S2 ( .D(\u_DataPath/data_read_ex_2_i [28]),
.CP(clk), .QN(n3128) );
HS65_LH_NAND2AX7 U4801 ( .A(n3058), .B(n2916), .Z(n4726) );
HS65_LL_AOI21X2 U6685 ( .A(n4175), .B(n3237), .C(n3066), .Z(n3067) );
HS65_LL_NAND2AX7 U3938 ( .A(n3068), .B(n3067), .Z(\sub_x_53/A[0] ) );
HS65_LL_NOR2AX6 U6694 ( .A(n2913), .B(n3295), .Z(\sub_x_53/A[2] ) );
HS65_LL_NOR2X6 U5629 ( .A(n3139), .B(n3138), .Z(\lte_x_59/B[24] ) );
HS65_LL_IVX18 U3931 ( .A(n2845), .Z(n2856) );
HS65_LL_IVX9 U4762 ( .A(n2855), .Z(n4587) );
HS65_LH_IVX9 U3929 ( .A(n3432), .Z(n5004) );
HS65_LH_NOR2X9 U3955 ( .A(n3474), .B(n5104), .Z(n3990) );
HS65_LH_IVX9 U4755 ( .A(\lte_x_59/B[24] ), .Z(n4981) );
HS65_LH_IVX9 U7378 ( .A(\lte_x_59/B[3] ), .Z(n5320) );
HS65_LH_OAI12X3 U5426 ( .A(n3101), .B(n4795), .C(n3964), .Z(n4256) );
HS65_LH_IVX9 U3607 ( .A(n4836), .Z(n4581) );
HS65_LH_OAI12X3 U5416 ( .A(n2854), .B(n4795), .C(n3719), .Z(n4500) );
HS65_LH_OAI12X3 U3713 ( .A(n4084), .B(n4081), .C(n4083), .Z(n4927) );
HS65_LH_IVX9 U5614 ( .A(n7623), .Z(n7627) );
HS65_LH_AOI21X2 U4124 ( .A(n3474), .B(n4587), .C(n3672), .Z(n3673) );
HS65_LL_AND2X4 U3674 ( .A(n3356), .B(n3355), .Z(n3357) );
HS65_LH_OAI12X3 U5525 ( .A(n4846), .B(n3558), .C(n3559), .Z(n5260) );
HS65_LH_AOI21X2 U4105 ( .A(n2842), .B(n4587), .C(n3955), .Z(n3760) );
HS65_LL_NOR2X6 U4183 ( .A(n2851), .B(n7627), .Z(n5342) );
HS65_LH_AOI21X2 U7697 ( .A(n6035), .B(n5924), .C(n5923), .Z(n5925) );
HS65_LH_IVX9 U4764 ( .A(n5201), .Z(n5131) );
HS65_LL_NOR2X6 U4758 ( .A(n3818), .B(n4863), .Z(n5144) );
HS65_LL_NOR2AX6 U5259 ( .A(n2867), .B(n3501), .Z(n5210) );
HS65_LL_AOI21X2 U3893 ( .A(n4836), .B(n4491), .C(n4490), .Z(n4938) );
HS65_LL_AOI21X2 U3962 ( .A(n4836), .B(n4840), .C(n4433), .Z(n4473) );
HS65_LH_AOI21X2 U4039 ( .A(n5672), .B(n3598), .C(n3597), .Z(n3608) );
HS65_LHS_XNOR2X3 U7745 ( .A(\u_DataPath/jaddr_i [22]), .B(n8966), .Z(n7104)
);
HS65_LL_XNOR2X4 U3786 ( .A(n8164), .B(n7086), .Z(n7080) );
HS65_LHS_XNOR2X3 U7689 ( .A(n8165), .B(n2847), .Z(n7076) );
HS65_LHS_XNOR2X3 U7663 ( .A(\u_DataPath/jaddr_i [18]), .B(n2847), .Z(n7085)
);
HS65_LH_DFPQNX9 clk_r_REG454_S1 ( .D(
\u_DataPath/u_decode_unit/hdu_0/current_state [0]), .CP(clk), .QN(
n7613) );
HS65_LH_NOR2X6 U7651 ( .A(n6150), .B(n6139), .Z(n6634) );
HS65_LH_NOR2X6 U3759 ( .A(n6150), .B(n6149), .Z(n6384) );
HS65_LH_NOR2AX3 U6856 ( .A(n8729), .B(n3115), .Z(n2995) );
HS65_LH_NOR2AX3 U3681 ( .A(n8736), .B(n2994), .Z(n8671) );
HS65_LH_NOR2AX3 U3683 ( .A(n8737), .B(n2994), .Z(n8673) );
HS65_LH_NOR2AX3 U3693 ( .A(n8727), .B(n2994), .Z(n8672) );
HS65_LH_NOR2AX3 U3701 ( .A(n8874), .B(n2994), .Z(n3013) );
HS65_LH_NOR2AX3 U3691 ( .A(\u_DataPath/dataOut_exe_i [11]), .B(n2986), .Z(
n2993) );
HS65_LH_NOR2AX3 U6775 ( .A(\u_DataPath/dataOut_exe_i [21]), .B(n3116), .Z(
n3001) );
HS65_LH_NOR2AX3 U6769 ( .A(\u_DataPath/dataOut_exe_i [22]), .B(n3116), .Z(
n2989) );
HS65_LH_NOR2AX3 U6770 ( .A(\u_DataPath/dataOut_exe_i [25]), .B(n3116), .Z(
n2987) );
HS65_LH_NOR2AX3 U6774 ( .A(\u_DataPath/dataOut_exe_i [24]), .B(n3116), .Z(
n3004) );
HS65_LH_NOR2AX3 U6777 ( .A(\u_DataPath/dataOut_exe_i [20]), .B(n3116), .Z(
n3000) );
HS65_LH_NOR2AX3 U6779 ( .A(\u_DataPath/dataOut_exe_i [30]), .B(n3116), .Z(
n3002) );
HS65_LH_AOI21X2 U6280 ( .A(n5284), .B(n5285), .C(n4302), .Z(n7839) );
HS65_LL_NAND2X7 U3946 ( .A(n3204), .B(n3203), .Z(n5001) );
HS65_LL_AOI12X2 U4319 ( .A(n6109), .B(n6111), .C(n5940), .Z(n6029) );
HS65_LH_NOR2AX3 U6857 ( .A(n8749), .B(n3115), .Z(n2999) );
HS65_LH_NOR2AX3 U6860 ( .A(n9241), .B(n3115), .Z(n2996) );
HS65_LH_IVX9 U3434 ( .A(n8698), .Z(n9357) );
HS65_LL_NOR2X6 U3437 ( .A(n6153), .B(n6149), .Z(n6317) );
HS65_LL_AOI21X2 U3446 ( .A(\lte_x_59/B[18] ), .B(n4588), .C(n3954), .Z(n4258) );
HS65_LL_NOR2X6 U3447 ( .A(n5152), .B(n4581), .Z(n4942) );
HS65_LH_IVX18 U3448 ( .A(n5173), .Z(n5667) );
HS65_LL_NAND2X7 U3465 ( .A(n4949), .B(n3426), .Z(n5173) );
HS65_LL_OAI21X3 U3499 ( .A(n8427), .B(n9401), .C(n3135), .Z(n8554) );
HS65_LL_IVX18 U3508 ( .A(n2893), .Z(n4351) );
HS65_LL_NOR2X2 U3509 ( .A(n9401), .B(n8311), .Z(n8498) );
HS65_LL_MUXI21X2 U3511 ( .D0(n2934), .D1(n2933), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8488) );
HS65_LL_IVX18 U3512 ( .A(n9376), .Z(n4713) );
HS65_LL_IVX18 U3516 ( .A(n3119), .Z(addr_to_iram[24]) );
HS65_LH_IVX40 U3526 ( .A(n9357), .Z(addr_to_iram[11]) );
HS65_LL_NAND2X7 U3538 ( .A(\u_DataPath/dataOut_exe_i [0]), .B(n3114), .Z(
n8270) );
HS65_LL_AOI12X9 U3540 ( .A(n5858), .B(n5860), .C(n5741), .Z(n5854) );
HS65_LL_NOR2X6 U3547 ( .A(n6153), .B(n6132), .Z(n6624) );
HS65_LL_OAI21X12 U3555 ( .A(n5743), .B(n5746), .C(n5745), .Z(n5860) );
HS65_LL_AOI21X6 U3567 ( .A(n5285), .B(n3514), .C(n3513), .Z(n8479) );
HS65_LL_NOR2AX3 U3570 ( .A(n5225), .B(n5224), .Z(n8458) );
HS65_LL_NAND3X5 U3571 ( .A(n4416), .B(n2900), .C(n4415), .Z(n5166) );
HS65_LL_AND3X4 U3572 ( .A(n4406), .B(n4405), .C(n4404), .Z(n2900) );
HS65_LL_NAND2X7 U3575 ( .A(\u_DataPath/jaddr_i [23]), .B(n6131), .Z(n6132)
);
HS65_LL_AOI21X6 U3581 ( .A(n5285), .B(n4963), .C(n4962), .Z(n8475) );
HS65_LH_NAND4ABX3 U3582 ( .A(n3845), .B(n3844), .C(n3843), .D(n3842), .Z(
n3851) );
HS65_LH_OAI21X3 U3584 ( .A(n5462), .B(n5461), .C(n5460), .Z(n5498) );
HS65_LL_AOI21X2 U3585 ( .A(n5234), .B(n3610), .C(n3609), .Z(n3611) );
HS65_LL_OAI12X3 U3587 ( .A(n2859), .B(n4324), .C(n4323), .Z(n4325) );
HS65_LL_NOR4ABX2 U3591 ( .A(n4959), .B(n4958), .C(n4957), .D(n4956), .Z(
n4960) );
HS65_LL_NOR2AX3 U3593 ( .A(n5253), .B(n5252), .Z(n5268) );
HS65_LH_AOI21X2 U3603 ( .A(n5667), .B(n5666), .C(n5665), .Z(n5668) );
HS65_LH_AOI21X2 U3606 ( .A(n5667), .B(n4184), .C(n4183), .Z(n4202) );
HS65_LH_OAI12X3 U3623 ( .A(n3246), .B(n3815), .C(n3950), .Z(n3951) );
HS65_LH_NOR2AX3 U3624 ( .A(n5217), .B(n4936), .Z(n4961) );
HS65_LH_NAND3X3 U3627 ( .A(n3608), .B(n2930), .C(n3607), .Z(n3609) );
HS65_LH_AOI21X2 U3629 ( .A(n5618), .B(n4389), .C(n3600), .Z(n2930) );
HS65_LL_OAI21X2 U3630 ( .A(n7634), .B(n9339), .C(n4126), .Z(n4139) );
HS65_LH_AOI21X2 U3631 ( .A(n5667), .B(n5644), .C(n3784), .Z(n3785) );
HS65_LL_NOR2AX3 U3633 ( .A(n5636), .B(n5635), .Z(n5637) );
HS65_LL_AOI21X2 U3636 ( .A(n4480), .B(n4645), .C(n4102), .Z(n4103) );
HS65_LH_AOI21X2 U3638 ( .A(n5667), .B(n5203), .C(n4434), .Z(n4444) );
HS65_LH_AOI21X2 U3641 ( .A(n5618), .B(n5174), .C(n4436), .Z(n4443) );
HS65_LL_AOI21X2 U3643 ( .A(n5629), .B(n3379), .C(n3378), .Z(n3380) );
HS65_LL_AOI21X2 U3645 ( .A(n6123), .B(n5671), .C(n4168), .Z(n4169) );
HS65_LL_AOI21X2 U3651 ( .A(n4259), .B(n4258), .C(n4581), .Z(n4261) );
HS65_LL_NOR4ABX4 U3655 ( .A(n4125), .B(n4124), .C(n4123), .D(n4122), .Z(
n4126) );
HS65_LH_AOI21X2 U3659 ( .A(n3893), .B(n5294), .C(n5406), .Z(n5521) );
HS65_LL_AOI21X2 U3663 ( .A(\sub_x_53/A[20] ), .B(n4544), .C(n3953), .Z(n4259) );
HS65_LL_NOR2X6 U3664 ( .A(n4965), .B(n3416), .Z(n5285) );
HS65_LH_AOI21X2 U3667 ( .A(\lte_x_59/B[22] ), .B(n4588), .C(n3779), .Z(n3780) );
HS65_LH_NAND3X5 U3669 ( .A(n3837), .B(n3436), .C(n3435), .Z(n5170) );
HS65_LH_AOI21X2 U3672 ( .A(n5667), .B(n5658), .C(n4166), .Z(n4167) );
HS65_LL_CNIVX7 U3678 ( .A(n5249), .Z(n5672) );
HS65_LL_AND2X4 U3682 ( .A(n4949), .B(n4508), .Z(n5661) );
HS65_LL_NAND2AX14 U3689 ( .A(n2924), .B(n3492), .Z(n4879) );
HS65_LL_OA12X9 U3694 ( .A(n4101), .B(n3358), .C(n3357), .Z(n3815) );
HS65_LL_CNIVX7 U3708 ( .A(n5178), .Z(n5649) );
HS65_LH_AOI21X2 U3712 ( .A(\lte_x_59/B[5] ), .B(n4544), .C(n3669), .Z(n3921)
);
HS65_LL_IVX9 U3722 ( .A(n3529), .Z(n5647) );
HS65_LH_IVX27 U3737 ( .A(n3789), .Z(n4582) );
HS65_LL_IVX9 U3741 ( .A(n4795), .Z(n3789) );
HS65_LL_BFX9 U3751 ( .A(n2893), .Z(n5129) );
HS65_LL_NAND2X21 U3753 ( .A(n3399), .B(n5136), .Z(n4795) );
HS65_LL_IVX9 U3756 ( .A(n3430), .Z(n2872) );
HS65_LH_IVX9 U3773 ( .A(n4147), .Z(n2865) );
HS65_LL_NOR2X6 U3775 ( .A(n3417), .B(n3416), .Z(n3967) );
HS65_LL_OAI12X6 U3776 ( .A(n3196), .B(n8531), .C(n3195), .Z(n5005) );
HS65_LL_NAND2X7 U3777 ( .A(n3209), .B(n3208), .Z(n5021) );
HS65_LH_NOR2X13 U3780 ( .A(n3306), .B(n3305), .Z(\lte_x_59/B[3] ) );
HS65_LL_OAI12X6 U3781 ( .A(n3325), .B(n8498), .C(n3324), .Z(n4147) );
HS65_LL_OAI21X3 U3798 ( .A(n8394), .B(n3340), .C(n3304), .Z(n3305) );
HS65_LL_AOI21X2 U3803 ( .A(n3167), .B(n3270), .C(n2911), .Z(n3168) );
HS65_LL_CNIVX7 U3807 ( .A(\u_DataPath/u_idexreg/N3 ), .Z(n7834) );
HS65_LH_AOI21X2 U3813 ( .A(n2896), .B(n3134), .C(n3133), .Z(n3135) );
HS65_LL_OAI12X6 U3819 ( .A(n3245), .B(n3244), .C(n3243), .Z(n5104) );
HS65_LL_NAND4ABX3 U3820 ( .A(n8129), .B(n8892), .C(n8886), .D(n8126), .Z(
\u_DataPath/u_idexreg/N3 ) );
HS65_LL_MUXI21X5 U3825 ( .D0(n2970), .D1(n2969), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8394) );
HS65_LL_MUXI21X2 U3831 ( .D0(n3332), .D1(n3331), .S0(n3404), .Z(n8391) );
HS65_LH_OAI12X3 U3832 ( .A(n9190), .B(n8890), .C(n8317), .Z(
\u_DataPath/dataOut_exe_i [26]) );
HS65_LH_MUXI21X2 U3839 ( .D0(n8907), .D1(
\u_DataPath/from_mem_data_out_i [10]), .S0(\u_DataPath/cw_towb_i [0]),
.Z(n8258) );
HS65_LL_OAI12X3 U3843 ( .A(n8777), .B(n8114), .C(n8878), .Z(n8078) );
HS65_LL_OAI21X2 U3845 ( .A(n8702), .B(n9012), .C(n8101), .Z(n8103) );
HS65_LH_OAI12X3 U3849 ( .A(n9190), .B(n9072), .C(n8333), .Z(
\u_DataPath/dataOut_exe_i [9]) );
HS65_LL_OAI13X5 U3850 ( .A(n8904), .B(n9051), .C(n9081), .D(n8880), .Z(n8440) );
HS65_LL_OAI12X3 U3852 ( .A(n9051), .B(n9103), .C(n8898), .Z(n8441) );
HS65_LL_AOI21X6 U3863 ( .A(n9130), .B(n8750), .C(\u_DataPath/u_idexreg/N10 ),
.Z(n8071) );
HS65_LL_OR3X9 U3866 ( .A(\u_DataPath/cw_exmem_i [5]), .B(
\u_DataPath/cw_exmem_i [3]), .C(n9152), .Z(\u_DataPath/u_idexreg/N10 )
);
HS65_LH_IVX2 U3870 ( .A(n5056), .Z(n5057) );
HS65_LH_OAI21X2 U3872 ( .A(n5123), .B(n5179), .C(n5137), .Z(n5138) );
HS65_LH_NAND3X2 U3873 ( .A(n4971), .B(n4970), .C(n4969), .Z(n4972) );
HS65_LH_NAND2X2 U3875 ( .A(n5144), .B(n5143), .Z(n5145) );
HS65_LH_NAND2X2 U3876 ( .A(n5387), .B(n4143), .Z(n5550) );
HS65_LH_IVX2 U3884 ( .A(n4997), .Z(n5345) );
HS65_LH_NOR2X2 U3895 ( .A(n3285), .B(n4713), .Z(n3286) );
HS65_LH_NAND2X2 U3904 ( .A(n4714), .B(n8557), .Z(n3154) );
HS65_LH_IVX2 U3905 ( .A(n4750), .Z(n4752) );
HS65_LH_IVX2 U3910 ( .A(n5550), .Z(n5551) );
HS65_LH_IVX2 U3911 ( .A(n5313), .Z(n5107) );
HS65_LH_IVX2 U3914 ( .A(n5035), .Z(n5549) );
HS65_LH_IVX2 U3940 ( .A(n8528), .Z(n3202) );
HS65_LH_NAND2X2 U3944 ( .A(n5320), .B(n5321), .Z(n5317) );
HS65_LH_NAND2X2 U3956 ( .A(n4738), .B(n4737), .Z(n4747) );
HS65_LH_NAND2X2 U3968 ( .A(n5323), .B(n5322), .Z(n5324) );
HS65_LH_NAND2X2 U3976 ( .A(n5408), .B(n5378), .Z(n5412) );
HS65_LH_NAND3X2 U3978 ( .A(n5322), .B(n5318), .C(n5317), .Z(n5332) );
HS65_LH_IVX2 U3979 ( .A(n8559), .Z(n3146) );
HS65_LH_AOI21X2 U3981 ( .A(n4351), .B(\sub_x_53/A[27] ), .C(n4350), .Z(n4353) );
HS65_LH_IVX2 U3982 ( .A(n8516), .Z(n3251) );
HS65_LH_NAND2X2 U3989 ( .A(n2849), .B(n4351), .Z(n3594) );
HS65_LH_IVX2 U4002 ( .A(n5627), .Z(n5628) );
HS65_LH_NAND2X2 U4011 ( .A(n4713), .B(n9030), .Z(n4655) );
HS65_LH_NAND2X2 U4013 ( .A(n2842), .B(n2864), .Z(n3956) );
HS65_LH_IVX2 U4023 ( .A(n5347), .Z(n5566) );
HS65_LH_NAND2X2 U4036 ( .A(n5290), .B(n5362), .Z(n4702) );
HS65_LH_OAI21X2 U4047 ( .A(n5523), .B(n5522), .C(n5521), .Z(n5524) );
HS65_LH_IVX2 U4049 ( .A(n5333), .Z(n5309) );
HS65_LL_IVX2 U4053 ( .A(n5209), .Z(n3619) );
HS65_LH_NOR2X2 U4056 ( .A(n3657), .B(n3656), .Z(n4180) );
HS65_LH_NAND2X2 U4069 ( .A(\lte_x_59/B[7] ), .B(n2845), .Z(n4154) );
HS65_LH_OAI21X2 U4073 ( .A(n4524), .B(n4523), .C(n5229), .Z(n4525) );
HS65_LH_NAND2X2 U4074 ( .A(n3327), .B(n9267), .Z(n3253) );
HS65_LH_IVX2 U4080 ( .A(n4355), .Z(n4394) );
HS65_LH_NOR2X2 U4084 ( .A(n5005), .B(\lte_x_59/B[18] ), .Z(n4250) );
HS65_LH_IVX2 U4087 ( .A(n3875), .Z(n3878) );
HS65_LH_NOR2X2 U4090 ( .A(n2854), .B(n2893), .Z(n3834) );
HS65_LH_AOI21X2 U4103 ( .A(\sub_x_53/A[29] ), .B(n4544), .C(n3648), .Z(n3652) );
HS65_LH_IVX2 U4114 ( .A(n3990), .Z(n4041) );
HS65_LH_IVX2 U4115 ( .A(n5629), .Z(n3702) );
HS65_LH_IVX2 U4119 ( .A(n3908), .Z(n3909) );
HS65_LH_IVX2 U4129 ( .A(n4180), .Z(n4184) );
HS65_LH_IVX2 U4135 ( .A(n4320), .Z(n3471) );
HS65_LH_NAND2X2 U4140 ( .A(\lte_x_59/B[14] ), .B(n4588), .Z(n3985) );
HS65_LHS_XNOR2X3 U4141 ( .A(\u_DataPath/jaddr_i [17]), .B(n8966), .Z(n7099)
);
HS65_LH_OAI21X2 U4152 ( .A(n4344), .B(n4343), .C(n4342), .Z(n4345) );
HS65_LH_IVX2 U4157 ( .A(n3932), .Z(n3933) );
HS65_LH_IVX2 U4160 ( .A(n4108), .Z(n4476) );
HS65_LH_NAND2X2 U4171 ( .A(n3426), .B(n4840), .Z(n4841) );
HS65_LH_AOI22X1 U4174 ( .A(n3474), .B(n4587), .C(n4551), .D(\lte_x_59/B[9] ),
.Z(n4128) );
HS65_LH_OA12X4 U4178 ( .A(n4641), .B(n4637), .C(n4663), .Z(n3355) );
HS65_LH_IVX2 U4189 ( .A(n5806), .Z(n5734) );
HS65_LH_NOR2X2 U4192 ( .A(n2843), .B(n3756), .Z(n3672) );
HS65_LH_NAND2X2 U4193 ( .A(n4824), .B(n3486), .Z(n4825) );
HS65_LH_OAI21X2 U4198 ( .A(n4643), .B(n4642), .C(n4641), .Z(n4644) );
HS65_LH_NAND2X2 U4202 ( .A(\lte_x_59/B[14] ), .B(n4544), .Z(n3832) );
HS65_LH_NOR2X6 U4208 ( .A(n6353), .B(n6341), .Z(n6681) );
HS65_LH_NAND2X2 U4231 ( .A(n4943), .B(n3426), .Z(n3981) );
HS65_LH_IVX2 U4235 ( .A(n4389), .Z(n3539) );
HS65_LH_OAI21X2 U4244 ( .A(n3762), .B(n4955), .C(n3761), .Z(n3797) );
HS65_LH_NAND2X2 U4260 ( .A(n4926), .B(n4925), .Z(n4935) );
HS65_LH_NAND2X2 U4261 ( .A(n4238), .B(n5194), .Z(n4240) );
HS65_LH_OAI21X2 U4266 ( .A(n4391), .B(n4855), .C(n3581), .Z(n3592) );
HS65_LH_NAND3X2 U4271 ( .A(n3426), .B(n4507), .C(n5615), .Z(n3654) );
HS65_LH_AOI21X2 U4274 ( .A(n5780), .B(n5726), .C(n5725), .Z(n5759) );
HS65_LH_OR2X4 U4281 ( .A(\sub_x_53/A[30] ), .B(n4966), .Z(n4211) );
HS65_LH_NAND3X2 U4287 ( .A(n4347), .B(n4346), .C(n4345), .Z(n4348) );
HS65_LH_NOR2X2 U4290 ( .A(n4052), .B(n3815), .Z(n4053) );
HS65_LH_NAND2X4 U4292 ( .A(n3374), .B(n5271), .Z(n4420) );
HS65_LH_NOR2X2 U4301 ( .A(n4134), .B(n5249), .Z(n5186) );
HS65_LH_NAND2X2 U4307 ( .A(n7631), .B(n5638), .Z(n5639) );
HS65_LH_OAI21X2 U4314 ( .A(n3874), .B(n5201), .C(n3873), .Z(n3882) );
HS65_LL_NOR3X4 U4318 ( .A(n9150), .B(n9128), .C(n9051), .Z(n8439) );
HS65_LH_NAND2X14 U4329 ( .A(n9251), .B(n8897), .Z(n8453) );
HS65_LH_NAND2X2 U4331 ( .A(n3415), .B(n5321), .Z(n3818) );
HS65_LH_XNOR2X4 U4346 ( .A(\u_DataPath/jaddr_i [17]), .B(n7086), .Z(n7088)
);
HS65_LH_AO22X4 U4353 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][2] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][2] ), .D(n7318), .Z(n6959) );
HS65_LH_AO22X4 U4367 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][21] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][21] ), .D(
n7586), .Z(n7588) );
HS65_LH_AOI22X1 U4369 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][24] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][24] ), .Z(n7566)
);
HS65_LH_AO22X4 U4384 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][29] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][29] ), .Z(n7532)
);
HS65_LH_AOI22X1 U4388 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][28] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][28] ), .Z(n7505)
);
HS65_LH_AOI22X1 U4390 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][20] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][20] ), .Z(n7484)
);
HS65_LH_AOI22X1 U4394 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][20] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][20] ), .D(
n2891), .Z(n7475) );
HS65_LH_AOI22X1 U4396 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][27] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][27] ), .D(
n2891), .Z(n7455) );
HS65_LH_AO22X4 U4400 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][0] ), .B(n7429),
.C(n7310), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][0] ), .Z(n7431) );
HS65_LH_AOI22X1 U4404 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][3] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][3] ), .D(n7516),
.Z(n7394) );
HS65_LH_AOI22X1 U4411 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][14] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][14] ), .D(
n2889), .Z(n7373) );
HS65_LH_AOI22X1 U4414 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][4] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][4] ), .D(n2889), .Z(n7353) );
HS65_LH_BFX4 U4415 ( .A(n6952), .Z(n7310) );
HS65_LH_BFX4 U4426 ( .A(n6682), .Z(n7592) );
HS65_LH_NOR2X5 U4429 ( .A(n6148), .B(n6152), .Z(n2884) );
HS65_LH_BFX4 U4453 ( .A(n6624), .Z(n6600) );
HS65_LH_AOI22X1 U4473 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][2] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][2] ), .D(
n6171), .Z(n6564) );
HS65_LH_AO22X4 U4482 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][25] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][25] ), .D(
n6629), .Z(n7147) );
HS65_LH_AO22X4 U4485 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][9] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][9] ), .D(n7291), .Z(n7138) );
HS65_LH_AO22X4 U4486 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][28] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][28] ), .D(
n7267), .Z(n6907) );
HS65_LH_AO22X4 U4488 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][17] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][17] ), .D(
n7267), .Z(n6887) );
HS65_LH_AOI22X1 U4506 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][31] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][31] ), .D(
n7272), .Z(n6873) );
HS65_LH_AO22X4 U4507 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][18] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][18] ), .D(
n7274), .Z(n6655) );
HS65_LH_AO22X4 U4516 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][20] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][20] ), .D(
n7276), .Z(n6851) );
HS65_LH_AO22X4 U4526 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][5] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][5] ), .D(
n7282), .Z(n6940) );
HS65_LH_AO22X4 U4528 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][29] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][29] ), .D(
n7282), .Z(n7290) );
HS65_LH_AOI22X1 U4540 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][8] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][8] ), .Z(n6776)
);
HS65_LH_AOI22X1 U4544 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][11] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][11] ), .D(
n7285), .Z(n6254) );
HS65_LH_AOI22X1 U4547 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][31] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][31] ), .Z(n6686)
);
HS65_LH_AOI22X1 U4548 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][25] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][25] ), .Z(n7049)
);
HS65_LH_AO22X4 U4549 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][6] ), .B(n7429),
.C(n7310), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][6] ), .Z(n7245) );
HS65_LH_AOI22X1 U4554 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][21] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][21] ), .D(
n7171), .Z(n6193) );
HS65_LH_AOI22X1 U4556 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][21] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][21] ), .D(
n6624), .Z(n6192) );
HS65_LH_AOI22X1 U4557 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][16] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][16] ), .D(
n6625), .Z(n6169) );
HS65_LH_AO22X4 U4561 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][23] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][23] ), .D(
n7318), .Z(n7229) );
HS65_LH_AO22X4 U4585 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][1] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][1] ), .Z(n6838)
);
HS65_LH_AO22X4 U4596 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][27] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][27] ), .D(
n6637), .Z(n6215) );
HS65_LH_AOI22X1 U4600 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][19] ), .B(n7525),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][19] ), .Z(n6755)
);
HS65_LH_AOI22X1 U4601 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][7] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][7] ), .Z(n6728)
);
HS65_LH_AO22X4 U4603 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][22] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][22] ), .D(
n7292), .Z(n6279) );
HS65_LH_AO22X4 U4614 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][24] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][24] ), .D(
n7292), .Z(n6299) );
HS65_LH_AO22X4 U4616 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][5] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][5] ), .Z(n6709)
);
HS65_LH_AOI22X1 U4619 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][5] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][5] ), .D(
n6670), .Z(n6702) );
HS65_LH_AO22X4 U4620 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][13] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][13] ), .D(
n7292), .Z(n7178) );
HS65_LH_AOI22X1 U4629 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][13] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][13] ), .D(
n6624), .Z(n7169) );
HS65_LH_AOI22X1 U4634 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][14] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][14] ), .D(
n6625), .Z(n6311) );
HS65_LH_AO22X4 U4637 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][19] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][19] ), .D(
n7267), .Z(n6515) );
HS65_LH_AO22X4 U4643 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][7] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][7] ), .D(n7267), .Z(n6435) );
HS65_LH_AO22X4 U4659 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][12] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][12] ), .D(
n7267), .Z(n6535) );
HS65_LH_AO22X4 U4665 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][6] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][6] ), .D(
n7274), .Z(n6480) );
HS65_LH_AO22X4 U4674 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][3] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][3] ), .D(
n7274), .Z(n6580) );
HS65_LH_AO22X4 U4678 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][26] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][26] ), .D(
n7282), .Z(n6506) );
HS65_LH_AO22X4 U4685 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][8] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][8] ), .D(
n7282), .Z(n6466) );
HS65_LH_AOI22X1 U4691 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][1] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][1] ), .D(
n7171), .Z(n6605) );
HS65_LH_AOI22X1 U4697 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][11] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][11] ), .Z(n7069)
);
HS65_LH_NOR2AX3 U4707 ( .A(n3069), .B(\u_DataPath/cw_towb_i [0]), .Z(n3070)
);
HS65_LH_AO22X4 U4708 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][13] ), .B(n7578),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][13] ), .Z(n6977)
);
HS65_LH_AO22X4 U4712 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][22] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][22] ), .Z(n6996)
);
HS65_LH_AO22X4 U4713 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][4] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][4] ), .D(n7267), .Z(n6620) );
HS65_LH_IVX2 U4715 ( .A(n3050), .Z(n3034) );
HS65_LH_IVX2 U4723 ( .A(n4579), .Z(n4615) );
HS65_LH_NOR2X2 U4742 ( .A(n4939), .B(n3979), .Z(n3989) );
HS65_LH_IVX2 U4744 ( .A(n3515), .Z(n5293) );
HS65_LH_IVX2 U4771 ( .A(n3698), .Z(n3699) );
HS65_LH_NOR2X3 U4780 ( .A(\sub_x_53/A[2] ), .B(n3415), .Z(n4575) );
HS65_LH_AOI21X2 U4786 ( .A(n4949), .B(n4948), .C(n4947), .Z(n4958) );
HS65_LH_OAI21X2 U4792 ( .A(n5760), .B(n5878), .C(n5759), .Z(n5791) );
HS65_LH_IVX2 U4799 ( .A(n5795), .Z(n5796) );
HS65_LH_OR2X4 U4808 ( .A(n9342), .B(n9216), .Z(n5902) );
HS65_LH_IVX2 U4814 ( .A(n5907), .Z(n5740) );
HS65_LH_NAND2X2 U4817 ( .A(n9185), .B(n9230), .Z(n5789) );
HS65_LH_NOR2X2 U4831 ( .A(n7645), .B(n7680), .Z(n7646) );
HS65_LH_NOR2X2 U4833 ( .A(n9173), .B(n9231), .Z(n5874) );
HS65_LH_NAND2X2 U4837 ( .A(n4050), .B(n3267), .Z(n4056) );
HS65_LH_NAND2X2 U4843 ( .A(n5217), .B(n4885), .Z(n4900) );
HS65_LH_IVX2 U4860 ( .A(n8262), .Z(n2966) );
HS65_LH_NOR3X1 U4863 ( .A(\u_DataPath/dataOut_exe_i [1]), .B(n8360), .C(
n8270), .Z(n7344) );
HS65_LH_NAND2X2 U4872 ( .A(n5867), .B(n5866), .Z(n5869) );
HS65_LH_OAI22X1 U4874 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [26]), .C(
n8316), .D(n3409), .Z(n3151) );
HS65_LH_NAND2X2 U4878 ( .A(n4713), .B(n9342), .Z(n4191) );
HS65_LH_NAND2X2 U4886 ( .A(n9368), .B(n9008), .Z(n8435) );
HS65_LH_NAND2X2 U4888 ( .A(n8687), .B(n8686), .Z(n7668) );
HS65_LH_IVX2 U4906 ( .A(n8255), .Z(n3260) );
HS65_LH_IVX2 U4909 ( .A(\u_DataPath/dataOut_exe_i [17]), .Z(n3201) );
HS65_LH_AOI22X1 U4917 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][15] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][15] ), .Z(n7193)
);
HS65_LH_AO22X4 U4925 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][10] ), .B(n7523),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][10] ), .Z(n7214)
);
HS65_LH_AO22X4 U4927 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][0] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][0] ), .D(n7291), .Z(n6430) );
HS65_LH_AOI22X1 U4928 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][10] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][10] ), .D(
n7294), .Z(n6407) );
HS65_LH_AOI22X1 U4936 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][15] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][15] ), .D(
n6942), .Z(n6386) );
HS65_LH_AOI22X1 U4938 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][15] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][15] ), .D(
n7264), .Z(n6369) );
HS65_LH_MUXI21X2 U4942 ( .D0(n2968), .D1(n9384), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8426) );
HS65_LH_AOI21X2 U4948 ( .A(n3404), .B(n9386), .C(n3070), .Z(n8345) );
HS65_LH_NAND2X2 U4956 ( .A(n9068), .B(n7773), .Z(n7690) );
HS65_LH_OAI21X2 U4967 ( .A(n4255), .B(n4254), .C(n4516), .Z(n4265) );
HS65_LH_IVX2 U4976 ( .A(n8056), .Z(n7698) );
HS65_LH_IVX2 U4977 ( .A(n4538), .Z(n4574) );
HS65_LL_OA12X4 U4982 ( .A(n7634), .B(n2844), .C(n4169), .Z(n4170) );
HS65_LH_AOI22X1 U4986 ( .A(n8868), .B(n9029), .C(n9369), .D(n8939), .Z(n7845) );
HS65_LH_NAND2X2 U4999 ( .A(n5777), .B(n5977), .Z(n5785) );
HS65_LH_AOI21X2 U5004 ( .A(n5802), .B(n5868), .C(n5801), .Z(n5803) );
HS65_LH_OAI21X2 U5005 ( .A(n6049), .B(n6045), .C(n6047), .Z(n6051) );
HS65_LH_IVX2 U5013 ( .A(n5980), .Z(n5983) );
HS65_LH_IVX2 U5015 ( .A(n6000), .Z(n6001) );
HS65_LH_NAND2X2 U5016 ( .A(n7707), .B(n4003), .Z(n4287) );
HS65_LH_MUXI21X5 U5017 ( .D0(n3137), .D1(n9389), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8550) );
HS65_LH_NAND2X2 U5032 ( .A(n3201), .B(n3407), .Z(n3198) );
HS65_LH_AOI22X1 U5040 ( .A(n4951), .B(n4578), .C(n5667), .D(n5239), .Z(n4010) );
HS65_LH_NOR2X2 U5046 ( .A(n8845), .B(n3341), .Z(n3169) );
HS65_LH_OAI22X1 U5047 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [25]), .C(
n8427), .D(n3409), .Z(n3099) );
HS65_LH_NOR2AX3 U5050 ( .A(n8726), .B(n2994), .Z(n8675) );
HS65_LH_NOR2AX3 U5057 ( .A(n8742), .B(n2994), .Z(n8674) );
HS65_LH_NOR2AX3 U5092 ( .A(\u_DataPath/dataOut_exe_i [8]), .B(n2986), .Z(
n3006) );
HS65_LH_NOR2AX3 U5096 ( .A(\u_DataPath/dataOut_exe_i [23]), .B(n3116), .Z(
n3003) );
HS65_LH_IVX2 U5104 ( .A(n9112), .Z(n2984) );
HS65_LH_AO22X4 U5115 ( .A(n9262), .B(n9188), .C(n9133), .D(n8982), .Z(
\u_DataPath/jump_address_i [19]) );
HS65_LH_AO22X4 U5122 ( .A(n9104), .B(n9188), .C(n9133), .D(n8951), .Z(
\u_DataPath/jump_address_i [10]) );
HS65_LH_IVX2 U5129 ( .A(n7668), .Z(n7743) );
HS65_LH_NAND2X2 U5132 ( .A(n2985), .B(n3109), .Z(n8425) );
HS65_LH_NAND2X2 U5133 ( .A(n3412), .B(n2866), .Z(n8491) );
HS65_LH_NAND2X2 U5134 ( .A(n4208), .B(n7869), .Z(n8569) );
HS65_LH_NAND2X2 U5136 ( .A(n3278), .B(n7869), .Z(n8521) );
HS65_LL_NAND3X2 U5141 ( .A(n4511), .B(n4510), .C(n4509), .Z(n5248) );
HS65_LH_OA12X4 U5143 ( .A(n4829), .B(n9402), .C(n4827), .Z(n2926) );
HS65_LH_NOR4ABX2 U5144 ( .A(n6826), .B(n6825), .C(n6824), .D(n6823), .Z(
n8175) );
HS65_LH_NOR4ABX2 U5151 ( .A(n6718), .B(n6717), .C(n6716), .D(n6715), .Z(
n8171) );
HS65_LH_AOI31X2 U5152 ( .A(n4608), .B(n4607), .C(n4606), .D(n5152), .Z(n4653) );
HS65_LH_BFX4 U5153 ( .A(n7306), .Z(n7917) );
HS65_LH_NOR2X2 U5154 ( .A(n7641), .B(n7640), .Z(n8135) );
HS65_LH_NOR2X2 U5155 ( .A(n5696), .B(n5695), .Z(n7118) );
HS65_LH_OAI21X2 U5160 ( .A(n5967), .B(n6007), .C(n5966), .Z(n6059) );
HS65_LH_NAND2X2 U5162 ( .A(n6076), .B(n6031), .Z(n6032) );
HS65_LH_NOR2X2 U5164 ( .A(n7758), .B(n7757), .Z(n7663) );
HS65_LH_NAND2X2 U5176 ( .A(n8708), .B(n7764), .Z(n7765) );
HS65_LH_NAND2X2 U5181 ( .A(n6054), .B(n6053), .Z(n6056) );
HS65_LH_NOR2X2 U5187 ( .A(n7793), .B(n7792), .Z(n7731) );
HS65_LH_NAND2X2 U5196 ( .A(n5949), .B(n5948), .Z(n5951) );
HS65_LH_IVX2 U5200 ( .A(n6034), .Z(n6095) );
HS65_LH_NOR2X2 U5212 ( .A(n7697), .B(n7694), .Z(n8040) );
HS65_LH_NOR2X2 U5221 ( .A(n4475), .B(n4474), .Z(n4487) );
HS65_LH_AOI21X2 U5227 ( .A(n5667), .B(n4872), .C(n4871), .Z(n4912) );
HS65_LH_NOR2X2 U5228 ( .A(\u_DataPath/dataOut_exe_i [10]), .B(n3264), .Z(
n3240) );
HS65_LH_OAI211X1 U5230 ( .A(n8302), .B(n8575), .C(n7346), .D(n7345), .Z(
n8298) );
HS65_LH_NAND3X2 U5232 ( .A(n9113), .B(n2984), .C(n7639), .Z(n3109) );
HS65_LH_NAND2AX4 U5241 ( .A(n9031), .B(n7733), .Z(n8144) );
HS65_LH_NAND2X4 U5246 ( .A(n7851), .B(n9061), .Z(
\u_DataPath/dataOut_exe_i [16]) );
HS65_LH_AO22X4 U5247 ( .A(n9254), .B(n8768), .C(n9132), .D(n9009), .Z(
\u_DataPath/pc4_to_idexreg_i [4]) );
HS65_LH_AO22X4 U5251 ( .A(n8786), .B(n9139), .C(n9333), .D(n9154), .Z(
opcode_i[5]) );
HS65_LH_NOR4ABX2 U5252 ( .A(n7203), .B(n7202), .C(n7201), .D(n7200), .Z(
n8305) );
HS65_LH_AO22X4 U5253 ( .A(n9254), .B(n8769), .C(n9240), .D(n9070), .Z(
\u_DataPath/pc4_to_idexreg_i [27]) );
HS65_LH_AO22X4 U5256 ( .A(n8780), .B(n9252), .C(n9307), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [4]) );
HS65_LH_AO22X4 U5262 ( .A(n9254), .B(n8804), .C(n9240), .D(n8974), .Z(
\u_DataPath/pc4_to_idexreg_i [10]) );
HS65_LH_AO22X4 U5265 ( .A(n9254), .B(n8827), .C(n9240), .D(n9108), .Z(
\u_DataPath/pc4_to_idexreg_i [31]) );
HS65_LHS_XOR2X3 U5271 ( .A(n5946), .B(n5945), .Z(
\u_DataPath/u_execute/resAdd1_i [31]) );
HS65_LH_NAND2X2 U5275 ( .A(\u_DataPath/immediate_ext_dec_i [0]), .B(
\u_DataPath/immediate_ext_dec_i [1]), .Z(n8092) );
HS65_LHS_XNOR2X3 U5278 ( .A(n2782), .B(n7663), .Z(\u_DataPath/pc_4_i [19])
);
HS65_LHS_XNOR2X3 U5286 ( .A(n3124), .B(n7679), .Z(\u_DataPath/pc_4_i [17])
);
HS65_LHS_XNOR2X3 U5292 ( .A(n6092), .B(n6091), .Z(
\u_DataPath/u_execute/resAdd1_i [7]) );
HS65_LL_NOR2AX6 U5302 ( .A(n4369), .B(n4368), .Z(n8469) );
HS65_LHS_XOR2X3 U5303 ( .A(n7783), .B(n7782), .Z(
\u_DataPath/u_execute/link_value_i [9]) );
HS65_LHS_XNOR2X3 U5304 ( .A(n2825), .B(n7704), .Z(\u_DataPath/pc_4_i [27])
);
HS65_LH_IVX2 U5307 ( .A(Data_out_fromRAM[20]), .Z(n8410) );
HS65_LH_IVX2 U5316 ( .A(Data_out_fromRAM[21]), .Z(n8365) );
HS65_LH_IVX2 U5318 ( .A(n7740), .Z(n8095) );
HS65_LH_NOR2X2 U5323 ( .A(n9175), .B(n9227), .Z(n6085) );
HS65_LH_IVX2 U5325 ( .A(n5882), .Z(n5883) );
HS65_LH_NOR2X2 U5338 ( .A(n9145), .B(n9224), .Z(n5753) );
HS65_LH_IVX2 U5340 ( .A(n5957), .Z(n5958) );
HS65_LH_NOR2X2 U5342 ( .A(n9033), .B(n9215), .Z(n5894) );
HS65_LH_IVX2 U5348 ( .A(n6097), .Z(n6098) );
HS65_LH_NOR2X2 U5353 ( .A(n9179), .B(n9225), .Z(n6090) );
HS65_LH_IVX2 U5363 ( .A(n5887), .Z(n5831) );
HS65_LH_NOR2X2 U5365 ( .A(n8913), .B(n9219), .Z(n6041) );
HS65_LH_IVX2 U5366 ( .A(n5839), .Z(n5890) );
HS65_LH_OR2X4 U5370 ( .A(n6148), .B(n6151), .Z(n9335) );
HS65_LH_OR2X4 U5372 ( .A(n9002), .B(n8751), .Z(n9336) );
HS65_LH_OR2X4 U5391 ( .A(n9344), .B(n9345), .Z(n9337) );
HS65_LH_NOR2X2 U5393 ( .A(n9267), .B(n9228), .Z(n5987) );
HS65_LH_IVX2 U5403 ( .A(n5786), .Z(n5787) );
HS65_LH_IVX2 U5404 ( .A(n5960), .Z(n6057) );
HS65_LH_NAND2X2 U5411 ( .A(n9181), .B(n9226), .Z(n6058) );
HS65_LH_IVX2 U5418 ( .A(n5863), .Z(n5764) );
HS65_LH_NOR2X2 U5422 ( .A(n9039), .B(n9116), .Z(n5899) );
HS65_LH_IVX2 U5428 ( .A(n6102), .Z(n6050) );
HS65_LH_IVX2 U5438 ( .A(n5836), .Z(n5837) );
HS65_LH_NOR2X2 U5443 ( .A(n9177), .B(n9229), .Z(n5879) );
HS65_LH_IVX2 U5446 ( .A(n6078), .Z(n6031) );
HS65_LH_NAND2X2 U5450 ( .A(n9171), .B(n9214), .Z(n5871) );
HS65_LH_IVX2 U5452 ( .A(n6070), .Z(n5984) );
HS65_LH_NOR2X2 U5454 ( .A(n9171), .B(n9214), .Z(n5778) );
HS65_LH_IVX2 U5460 ( .A(n5979), .Z(n6069) );
HS65_LH_NAND2X2 U5463 ( .A(n8913), .B(n9219), .Z(n5891) );
HS65_LH_IVX2 U5466 ( .A(n6094), .Z(n6042) );
HS65_LH_IVX2 U5467 ( .A(n5285), .Z(n4829) );
HS65_LH_NOR2X2 U5469 ( .A(n9183), .B(n9232), .Z(n5775) );
HS65_LH_IVX2 U5472 ( .A(n5976), .Z(n5977) );
HS65_LH_IVX2 U5477 ( .A(n5789), .Z(n5790) );
HS65_LH_NOR2X2 U5485 ( .A(n9185), .B(n9230), .Z(n5772) );
HS65_LH_IVX2 U5494 ( .A(n5990), .Z(n6005) );
HS65_LH_NOR2X2 U5497 ( .A(n9037), .B(n9212), .Z(n5846) );
HS65_LH_IVX2 U5498 ( .A(n6045), .Z(n6046) );
HS65_LH_NOR2X2 U5499 ( .A(n9173), .B(n9231), .Z(n6073) );
HS65_LH_IVX2 U5501 ( .A(n5874), .Z(n5875) );
HS65_LH_OA12X4 U5502 ( .A(n3899), .B(n3815), .C(n3898), .Z(n9338) );
HS65_LHS_XNOR2X3 U5509 ( .A(n4111), .B(n4110), .Z(n9339) );
HS65_LH_IVX9 U5510 ( .A(n8876), .Z(n9340) );
HS65_LH_IVX9 U5514 ( .A(n9340), .Z(n9341) );
HS65_LH_IVX9 U5516 ( .A(n9340), .Z(n9342) );
HS65_LH_IVX9 U5520 ( .A(n9340), .Z(n9343) );
HS65_LH_NOR2X2 U5521 ( .A(n9336), .B(n9337), .Z(\u_DataPath/cw_to_ex_i [15])
);
HS65_LH_CNIVX3 U5523 ( .A(n9347), .Z(n9344) );
HS65_LH_CNIVX3 U5527 ( .A(n9146), .Z(n9345) );
HS65_LH_IVX2 U5529 ( .A(n3582), .Z(n9346) );
HS65_LL_NOR2X6 U5566 ( .A(n5491), .B(n3423), .Z(n3582) );
HS65_LH_IVX9 U5570 ( .A(n3582), .Z(n4548) );
HS65_LH_AOI21X6 U5581 ( .A(n5643), .B(n4861), .C(n2902), .Z(n4862) );
HS65_LL_BFX9 U5584 ( .A(n5179), .Z(n9348) );
HS65_LH_AOI12X3 U5591 ( .A(n9349), .B(n5005), .C(n5649), .Z(n4269) );
HS65_LH_NAND3X5 U5610 ( .A(n4990), .B(n5115), .C(n4989), .Z(n4991) );
HS65_LL_IVX2 U5617 ( .A(n5082), .Z(n5529) );
HS65_LH_NOR2X2 U5625 ( .A(n8824), .B(n3403), .Z(n3086) );
HS65_LH_OAI21X2 U5637 ( .A(n4905), .B(n3815), .C(n5397), .Z(n4906) );
HS65_LH_IVX7 U5658 ( .A(n9330), .Z(n9354) );
HS65_LH_IVX7 U5660 ( .A(n9330), .Z(n9355) );
HS65_LH_IVX7 U5664 ( .A(n9330), .Z(n9356) );
HS65_LHS_XOR2X3 U5678 ( .A(addr_to_iram[29]), .B(n7786), .Z(
\u_DataPath/pc_4_i [31]) );
HS65_LH_IVX44 U5688 ( .A(n2780), .Z(addr_to_iram[29]) );
HS65_LH_IVX44 U5691 ( .A(n3124), .Z(addr_to_iram[15]) );
HS65_LH_IVX2 U5704 ( .A(n8677), .Z(n9359) );
HS65_LH_IVX4 U5713 ( .A(n9359), .Z(n9360) );
HS65_LH_IVX7 U5715 ( .A(n9359), .Z(n9361) );
HS65_LH_IVX4 U5731 ( .A(n9359), .Z(n9362) );
HS65_LH_IVX9 U5760 ( .A(n9135), .Z(n9364) );
HS65_LH_IVX9 U5778 ( .A(n9364), .Z(n9365) );
HS65_LH_IVX9 U5811 ( .A(n9364), .Z(n9366) );
HS65_LH_IVX9 U5815 ( .A(n9135), .Z(n9367) );
HS65_LH_IVX9 U5816 ( .A(n9367), .Z(n9368) );
HS65_LH_IVX9 U5826 ( .A(n9367), .Z(n9369) );
HS65_LH_AOI21X2 U5836 ( .A(n9007), .B(n9347), .C(n8082), .Z(n8088) );
HS65_LL_OR2X18 U5854 ( .A(n3401), .B(n5136), .Z(n2893) );
HS65_LH_OAI21X2 U5866 ( .A(n3427), .B(n5620), .C(n3767), .Z(n3795) );
HS65_LH_OAI21X3 U5874 ( .A(n5173), .B(n5620), .C(n3986), .Z(n3987) );
HS65_LL_NAND3X5 U5887 ( .A(n2931), .B(n4048), .C(n4047), .Z(n4302) );
HS65_LH_OAI21X2 U5890 ( .A(n2848), .B(n3756), .C(n4154), .Z(n4155) );
HS65_LH_NAND2X7 U5894 ( .A(n5643), .B(n4046), .Z(n4047) );
HS65_LH_IVX9 U5895 ( .A(n5088), .Z(n3415) );
HS65_LL_NAND4ABX6 U5914 ( .A(n5601), .B(n5600), .C(n8460), .D(n5599), .Z(
n5678) );
HS65_LL_AOI12X2 U5930 ( .A(n5415), .B(n5414), .C(n5413), .Z(n5462) );
HS65_LH_AOI21X6 U5939 ( .A(n5459), .B(n5458), .C(n5457), .Z(n5460) );
HS65_LH_NOR2X6 U5940 ( .A(\sub_x_53/A[27] ), .B(n3385), .Z(n3629) );
HS65_LL_IVX2 U5942 ( .A(n4976), .Z(n3385) );
HS65_LL_NAND2X2 U5957 ( .A(n4714), .B(n8546), .Z(n3171) );
HS65_LL_NOR3AX9 U5959 ( .A(n4456), .B(n4455), .C(n4454), .Z(n5681) );
HS65_LL_AOI21X2 U5963 ( .A(n4295), .B(n5211), .C(n4294), .Z(n4299) );
HS65_LL_NAND2AX14 U5967 ( .A(n3381), .B(n3380), .Z(n5195) );
HS65_LL_CNIVX3 U5970 ( .A(n5714), .Z(n4788) );
HS65_LL_NOR3X7 U5978 ( .A(n4787), .B(n4786), .C(n4785), .Z(n5714) );
HS65_LL_NAND3X3 U5982 ( .A(n2919), .B(n3202), .C(n8529), .Z(n3203) );
HS65_LL_OAI12X6 U5986 ( .A(n3501), .B(n4426), .C(n3500), .Z(n5211) );
HS65_LL_NOR2X2 U6012 ( .A(\sub_x_53/A[27] ), .B(n4976), .Z(n3682) );
HS65_LL_OAI21X2 U6015 ( .A(n4736), .B(n4735), .C(n4734), .Z(n4783) );
HS65_LL_BFX4 U6018 ( .A(n6618), .Z(n9370) );
HS65_LH_BFX9 U6024 ( .A(n6618), .Z(n9371) );
HS65_LH_BFX2 U6030 ( .A(n6618), .Z(n9372) );
HS65_LL_NOR2X2 U6031 ( .A(n6148), .B(n6149), .Z(n6618) );
HS65_LL_AOI22X3 U6034 ( .A(\lte_x_59/B[1] ), .B(n4588), .C(n4587), .D(
\sub_x_53/A[0] ), .Z(n4117) );
HS65_LH_BFX9 U6039 ( .A(n7312), .Z(n9373) );
HS65_LH_NOR2X2 U6053 ( .A(n6353), .B(n6331), .Z(n7312) );
HS65_LH_NOR2X2 U6060 ( .A(n5530), .B(n3515), .Z(n5416) );
HS65_LH_NAND2X7 U6070 ( .A(n3420), .B(n4512), .Z(n5178) );
HS65_LH_AOI12X3 U6087 ( .A(n5207), .B(n5658), .C(n4271), .Z(n4272) );
HS65_LH_AOI21X2 U6094 ( .A(n4051), .B(n4918), .C(n5476), .Z(n4054) );
HS65_LL_NAND2AX7 U6097 ( .A(n3364), .B(n3363), .Z(n4918) );
HS65_LL_AOI21X2 U6113 ( .A(n5195), .B(n4335), .C(n4334), .Z(n4336) );
HS65_LL_NOR2AX6 U6115 ( .A(n3387), .B(n3386), .Z(n4332) );
HS65_LL_OAI21X2 U6116 ( .A(n3749), .B(n3629), .C(n5443), .Z(n3386) );
HS65_LL_NOR2X6 U6118 ( .A(\lte_x_59/B[15] ), .B(n4677), .Z(n3891) );
HS65_LH_IVX9 U6121 ( .A(n3891), .Z(n3892) );
HS65_LH_NOR2X6 U6122 ( .A(n3891), .B(n4913), .Z(n3368) );
HS65_LH_OAI12X3 U6126 ( .A(n5435), .B(n3698), .C(n3700), .Z(n3378) );
HS65_LH_OAI21X2 U6131 ( .A(n4671), .B(n4583), .C(n4060), .Z(n4078) );
HS65_LH_OAI22X1 U6132 ( .A(n2848), .B(n4583), .C(n3756), .D(n5041), .Z(n4130) );
HS65_LH_OA12X4 U6134 ( .A(n5652), .B(n4583), .C(n3550), .Z(n2899) );
HS65_LH_OAI22X1 U6135 ( .A(n5652), .B(n4583), .C(n3756), .D(n2860), .Z(n3666) );
HS65_LL_NOR2X2 U6136 ( .A(n2843), .B(n4583), .Z(n3456) );
HS65_LL_NOR2X2 U6137 ( .A(n4986), .B(n4583), .Z(n3552) );
HS65_LL_NOR2X2 U6139 ( .A(n5320), .B(n4583), .Z(n4541) );
HS65_LH_OAI22X1 U6140 ( .A(n4700), .B(n4583), .C(n3756), .D(n4701), .Z(n3595) );
HS65_LL_OAI12X2 U6141 ( .A(n4583), .B(n4796), .C(n3518), .Z(n3520) );
HS65_LL_OAI21X2 U6142 ( .A(n4583), .B(n4981), .C(n3718), .Z(n4494) );
HS65_LL_NOR2X2 U6143 ( .A(n4700), .B(n4583), .Z(n3904) );
HS65_LL_NOR2X2 U6145 ( .A(n4984), .B(n4583), .Z(n3840) );
HS65_LH_NOR2X6 U6147 ( .A(n2854), .B(n4583), .Z(n3549) );
HS65_LL_NAND2X7 U6150 ( .A(n3890), .B(n3889), .Z(n7867) );
HS65_LH_OAI21X2 U6152 ( .A(n4293), .B(n4319), .C(n4292), .Z(n4294) );
HS65_LL_AOI12X3 U6153 ( .A(n3803), .B(n3503), .C(n3502), .Z(n4319) );
HS65_LH_OAI12X3 U6163 ( .A(n3802), .B(n3682), .C(n3684), .Z(n3502) );
HS65_LL_OAI12X3 U6164 ( .A(n5209), .B(n3613), .C(n3615), .Z(n3803) );
HS65_LL_NAND2X4 U6174 ( .A(n2881), .B(n6340), .Z(n6333) );
HS65_LL_AOI12X2 U6179 ( .A(n4733), .B(n4732), .C(n4731), .Z(n4734) );
HS65_LL_NOR3X2 U6190 ( .A(n4275), .B(n4274), .C(n4273), .Z(n4276) );
HS65_LL_NAND2X2 U6196 ( .A(n5661), .B(n5660), .Z(n5662) );
HS65_LH_NAND2X2 U6199 ( .A(n5618), .B(n5660), .Z(n4268) );
HS65_LL_NOR3X1 U6202 ( .A(n4156), .B(n4153), .C(n4155), .Z(n4558) );
HS65_LH_NOR2X2 U6203 ( .A(n5652), .B(n2893), .Z(n3823) );
HS65_LL_NOR2X2 U6205 ( .A(n4465), .B(n4156), .Z(n3790) );
HS65_LL_NOR2X2 U6208 ( .A(n4671), .B(n2893), .Z(n3955) );
HS65_LL_IVX9 U6210 ( .A(n2893), .Z(n4544) );
HS65_LL_OA12X9 U6213 ( .A(n5498), .B(n5497), .C(n5496), .Z(n5595) );
HS65_LL_NOR2X2 U6215 ( .A(n8794), .B(n9049), .Z(\u_DataPath/cw_exmem_i [5])
);
HS65_LL_NAND2AX4 U6217 ( .A(n5640), .B(n5639), .Z(n5641) );
HS65_LLS_XNOR2X3 U6219 ( .A(n2917), .B(n5637), .Z(n5638) );
HS65_LL_NOR2X3 U6230 ( .A(n5397), .B(n4902), .Z(n3361) );
HS65_LL_CNIVX3 U6234 ( .A(n5373), .Z(n3360) );
HS65_LL_NAND2X4 U6235 ( .A(n5078), .B(n5077), .Z(n5079) );
HS65_LH_IVX9 U6246 ( .A(\sub_x_53/A[17] ), .Z(n4984) );
HS65_LH_NAND2X7 U6247 ( .A(n5667), .B(n4389), .Z(n4390) );
HS65_LL_NAND3X3 U6249 ( .A(n3910), .B(n4022), .C(n3536), .Z(n4389) );
HS65_LH_AOI12X3 U6257 ( .A(\sub_x_53/A[17] ), .B(n4588), .C(n3535), .Z(n3536) );
HS65_LH_AOI12X3 U6262 ( .A(n4431), .B(n4349), .C(n4348), .Z(n4365) );
HS65_LH_IVX9 U6265 ( .A(n9335), .Z(n9374) );
HS65_LH_IVX9 U6266 ( .A(n9335), .Z(n9375) );
HS65_LL_NOR2X2 U6269 ( .A(n4494), .B(n4500), .Z(n3905) );
HS65_LH_AOI12X3 U6274 ( .A(n4516), .B(n4504), .C(n4503), .Z(n4510) );
HS65_LL_NAND2X2 U6276 ( .A(\lte_x_59/B[18] ), .B(n4351), .Z(n3838) );
HS65_LL_NOR2X2 U6277 ( .A(n4502), .B(n4501), .Z(n4503) );
HS65_LH_NAND2X2 U6284 ( .A(n2858), .B(n4351), .Z(n4129) );
HS65_LL_AOI211X1 U6285 ( .A(n2842), .B(n4351), .C(n4024), .D(n4023), .Z(
n4579) );
HS65_LH_NAND2X2 U6297 ( .A(\lte_x_59/B[9] ), .B(n4351), .Z(n4591) );
HS65_LH_NAND2X2 U6298 ( .A(n2851), .B(n4351), .Z(n3543) );
HS65_LH_NAND2X2 U6310 ( .A(\lte_x_59/B[16] ), .B(n4351), .Z(n3984) );
HS65_LH_NAND2X2 U6311 ( .A(\lte_x_59/B[15] ), .B(n4351), .Z(n4059) );
HS65_LL_NAND2X2 U6317 ( .A(\sub_x_53/A[25] ), .B(n4351), .Z(n3719) );
HS65_LL_NAND2X4 U6332 ( .A(\lte_x_59/B[28] ), .B(n4351), .Z(n3759) );
HS65_LH_OAI21X3 U6335 ( .A(n5394), .B(n5393), .C(n5392), .Z(n5414) );
HS65_LL_NAND2X2 U6337 ( .A(n3327), .B(n9179), .Z(n3324) );
HS65_LH_NAND2X2 U6338 ( .A(n3327), .B(n9343), .Z(n3157) );
HS65_LL_NAND2X2 U6339 ( .A(n3327), .B(n9171), .Z(n3243) );
HS65_LH_NAND2X2 U6347 ( .A(n3327), .B(n9342), .Z(n3148) );
HS65_LH_NAND2X2 U6349 ( .A(n3327), .B(n9343), .Z(n3209) );
HS65_LH_NAND2X2 U6355 ( .A(n3327), .B(n9342), .Z(n3172) );
HS65_LH_NAND2X2 U6356 ( .A(n3327), .B(n9342), .Z(n3180) );
HS65_LH_NAND2X2 U6360 ( .A(n3327), .B(n9185), .Z(n3263) );
HS65_LH_NAND2X2 U6366 ( .A(n3327), .B(n9173), .Z(n3230) );
HS65_LL_NAND2X2 U6367 ( .A(n3327), .B(n9175), .Z(n3328) );
HS65_LH_NAND2X2 U6372 ( .A(n3327), .B(n9341), .Z(n3191) );
HS65_LL_NAND2X4 U6392 ( .A(n3327), .B(n9033), .Z(n3314) );
HS65_LL_NOR3X1 U6402 ( .A(n4471), .B(n4470), .C(n4469), .Z(n4472) );
HS65_LL_OAI12X3 U6413 ( .A(n4468), .B(n5146), .C(n4467), .Z(n4469) );
HS65_LH_AOI12X2 U6426 ( .A(n3474), .B(n4544), .C(n3868), .Z(n3869) );
HS65_LL_NAND2AX4 U6435 ( .A(n5473), .B(n5472), .Z(n5481) );
HS65_LL_NAND2X2 U6438 ( .A(n4805), .B(n4811), .Z(n5547) );
HS65_LL_AOI12X2 U6447 ( .A(n5615), .B(n5248), .C(n5247), .Z(n5253) );
HS65_LH_NOR2X2 U6450 ( .A(n4806), .B(n4506), .Z(n4505) );
HS65_LH_NAND2X2 U6459 ( .A(n5448), .B(n4329), .Z(n4339) );
HS65_LH_IVX2 U6460 ( .A(n4305), .Z(n4306) );
HS65_LH_AOI12X6 U6474 ( .A(n4303), .B(n4305), .C(n4231), .Z(n4235) );
HS65_LL_OAI12X2 U6480 ( .A(n4331), .B(n4328), .C(n5448), .Z(n5452) );
HS65_LL_OAI12X2 U6490 ( .A(n4331), .B(n4328), .C(n5448), .Z(n4305) );
HS65_LL_NAND2X4 U6493 ( .A(n9369), .B(n9042), .Z(n8294) );
HS65_LL_IVX4 U6496 ( .A(\u_DataPath/dataOut_exe_i [29]), .Z(n4213) );
HS65_LL_NAND2X2 U6501 ( .A(n9366), .B(n9079), .Z(n8312) );
HS65_LL_NAND2X2 U6504 ( .A(n9368), .B(n9006), .Z(n8432) );
HS65_LL_NAND2X4 U6507 ( .A(n9368), .B(n9101), .Z(n8398) );
HS65_LL_NAND2X4 U6519 ( .A(n9366), .B(n9043), .Z(n7836) );
HS65_LL_NAND2X4 U6530 ( .A(n9365), .B(n9044), .Z(n8290) );
HS65_LL_NAND2X4 U6531 ( .A(n9366), .B(n9015), .Z(n8340) );
HS65_LL_NAND2X4 U6532 ( .A(n8166), .B(n6138), .Z(n6149) );
HS65_LL_AOI22X3 U6538 ( .A(n8868), .B(n9034), .C(n9368), .D(n8946), .Z(n7851) );
HS65_LL_NAND2X2 U6539 ( .A(n9369), .B(n9014), .Z(n8307) );
HS65_LL_NAND2X2 U6547 ( .A(n9365), .B(n9249), .Z(n8436) );
HS65_LL_NAND2X2 U6551 ( .A(n9369), .B(n9045), .Z(n8333) );
HS65_LL_NAND2X4 U6554 ( .A(n4322), .B(n5210), .Z(n4324) );
HS65_LL_AOI21X2 U6556 ( .A(n4322), .B(n5211), .C(n4321), .Z(n4323) );
HS65_LL_NOR2X6 U6557 ( .A(n3682), .B(n3800), .Z(n3503) );
HS65_LL_NOR2X5 U6558 ( .A(n2853), .B(n5567), .Z(n3800) );
HS65_LL_NAND2X11 U6560 ( .A(n3157), .B(n3156), .Z(n5567) );
HS65_LL_NOR3X4 U6565 ( .A(n5486), .B(n5485), .C(n5484), .Z(n5487) );
HS65_LL_CBI4I1X3 U6567 ( .A(n5508), .B(n5367), .C(n5366), .D(n5365), .Z(
n5484) );
HS65_LL_AOI12X2 U6568 ( .A(n5643), .B(n5155), .C(n5154), .Z(n5156) );
HS65_LL_OAI12X2 U6572 ( .A(n5153), .B(n5152), .C(n5151), .Z(n5154) );
HS65_LL_IVX7 U6585 ( .A(n5646), .Z(n5229) );
HS65_LL_NOR2X2 U6591 ( .A(\lte_x_59/B[3] ), .B(n5089), .Z(n4570) );
HS65_LL_AOI12X2 U6594 ( .A(n4638), .B(n4645), .C(n4640), .Z(n4145) );
HS65_LL_CNIVX3 U6595 ( .A(n9376), .Z(n3327) );
HS65_LL_CNIVX3 U6598 ( .A(n3593), .Z(n5425) );
HS65_LL_AND2X4 U6603 ( .A(n3132), .B(n7802), .Z(n3133) );
HS65_LL_AOI21X2 U6605 ( .A(n5229), .B(n3723), .C(n3722), .Z(n3724) );
HS65_LL_AOI12X2 U6618 ( .A(n3727), .B(n5624), .C(n3726), .Z(n3728) );
HS65_LH_OAI21X2 U6619 ( .A(n3725), .B(n5656), .C(n3724), .Z(n3726) );
HS65_LL_MUXI21X5 U6620 ( .D0(n2972), .D1(n2971), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8393) );
HS65_LL_CNIVX3 U6623 ( .A(\u_DataPath/from_mem_data_out_i [4]), .Z(n2971) );
HS65_LL_NAND3X2 U6624 ( .A(n4163), .B(n4162), .C(n4161), .Z(n5671) );
HS65_LL_NAND2X5 U6625 ( .A(n8177), .B(n7802), .Z(n8486) );
HS65_LL_IVX7 U6626 ( .A(n4953), .Z(n4148) );
HS65_LH_AOI12X2 U6628 ( .A(n5144), .B(n4875), .C(n4118), .Z(n4125) );
HS65_LL_IVX4 U6632 ( .A(n4113), .Z(n4875) );
HS65_LH_OAI21X2 U6636 ( .A(n5173), .B(n4117), .C(n4116), .Z(n4118) );
HS65_LL_AOI21X2 U6637 ( .A(n3529), .B(n4114), .C(n5041), .Z(n4115) );
HS65_LL_NAND2X2 U6638 ( .A(n5648), .B(n5040), .Z(n4114) );
HS65_LL_OAI21X3 U6652 ( .A(n4821), .B(n4817), .C(n4819), .Z(n4538) );
HS65_LL_NAND2X4 U6654 ( .A(\lte_x_59/B[1] ), .B(n3294), .Z(n4819) );
HS65_LL_NOR2X5 U6657 ( .A(\lte_x_59/B[1] ), .B(n3294), .Z(n4817) );
HS65_LH_IVX2 U6658 ( .A(n4805), .Z(n3294) );
HS65_LL_AOI21X4 U6659 ( .A(n5624), .B(n4446), .C(n4445), .Z(n4447) );
HS65_LL_NAND3X5 U6661 ( .A(n4444), .B(n4443), .C(n4442), .Z(n4445) );
HS65_LH_NOR2X2 U6662 ( .A(n4855), .B(n4435), .Z(n4436) );
HS65_LL_AND2ABX9 U6663 ( .A(n4458), .B(n4842), .Z(n5618) );
HS65_LL_NOR3X7 U6664 ( .A(n4782), .B(n4783), .C(n4784), .Z(n4785) );
HS65_LL_NAND3X3 U6666 ( .A(n5516), .B(n5517), .C(n5408), .Z(n4684) );
HS65_LL_NOR2X5 U6667 ( .A(n5406), .B(n5294), .Z(n5408) );
HS65_LL_OAI112X1 U6670 ( .A(n9129), .B(n8880), .C(n8308), .D(n9086), .Z(
\u_DataPath/from_mem_data_out_i [15]) );
HS65_LLS_XOR2X3 U6671 ( .A(n4635), .B(n4634), .Z(n4636) );
HS65_LL_AOI12X2 U6675 ( .A(n4633), .B(n4632), .C(n4631), .Z(n4634) );
HS65_LL_AOI12X12 U6687 ( .A(n5906), .B(n5908), .C(n5740), .Z(n5746) );
HS65_LL_OAI12X2 U6701 ( .A(n5855), .B(n5854), .C(n5853), .Z(n5856) );
HS65_LH_OAI21X3 U6704 ( .A(n5867), .B(n5817), .C(n5819), .Z(n5813) );
HS65_LL_NOR2X3 U6705 ( .A(n3629), .B(n3747), .Z(n5446) );
HS65_LL_NOR2AX3 U6706 ( .A(n4233), .B(n4332), .Z(n4234) );
HS65_LH_OAI21X2 U6707 ( .A(n3747), .B(n3632), .C(n3749), .Z(n3633) );
HS65_LH_OAI12X2 U6708 ( .A(n4333), .B(n4332), .C(n4331), .Z(n4334) );
HS65_LL_NOR2X6 U6710 ( .A(n2853), .B(n3384), .Z(n3747) );
HS65_LL_NAND2AX7 U6714 ( .A(n7634), .B(n7622), .Z(n4227) );
HS65_LL_NAND2AX4 U6718 ( .A(n7634), .B(n4380), .Z(n4416) );
HS65_LL_AND2X4 U6719 ( .A(n5217), .B(n4301), .Z(n5708) );
HS65_LL_NAND2X2 U6721 ( .A(n5217), .B(n3510), .Z(n3511) );
HS65_LL_AND2X4 U6734 ( .A(n5217), .B(n3849), .Z(n3850) );
HS65_LL_NAND2X2 U6741 ( .A(n5217), .B(n3944), .Z(n3945) );
HS65_LL_NAND2X4 U6745 ( .A(n5217), .B(n3995), .Z(n3996) );
HS65_LH_NAND2X2 U6753 ( .A(n5217), .B(n4479), .Z(n4485) );
HS65_LL_IVX9 U6768 ( .A(n7634), .Z(n5643) );
HS65_LL_CNIVX3 U6778 ( .A(n5217), .Z(n7634) );
HS65_LH_NAND2X2 U6796 ( .A(\u_DataPath/cw_to_ex_i [3]), .B(n5492), .Z(n3450)
);
HS65_LL_NOR2X2 U6797 ( .A(\u_DataPath/cw_to_ex_i [3]), .B(
\u_DataPath/cw_to_ex_i [4]), .Z(n3470) );
HS65_LL_NAND2X5 U6799 ( .A(n7631), .B(n5280), .Z(n5281) );
HS65_LLS_XNOR2X6 U6800 ( .A(n5279), .B(n5278), .Z(n5280) );
HS65_LL_MX41X4 U6801 ( .D0(n8440), .S0(n9289), .D1(n8441), .S1(n9274), .D2(
n8439), .S2(n9296), .D3(n8438), .S3(n9281), .Z(
\u_DataPath/from_mem_data_out_i [0]) );
HS65_LL_OAI21X2 U6804 ( .A(n4534), .B(n4533), .C(n2928), .Z(n5705) );
HS65_LL_NOR3X4 U6812 ( .A(n4532), .B(n4531), .C(n4530), .Z(n2928) );
HS65_LH_IVX9 U6813 ( .A(\u_DataPath/from_mem_data_out_i [0]), .Z(n3015) );
HS65_LL_NOR2X2 U6819 ( .A(n4700), .B(n5129), .Z(n3779) );
HS65_LL_NAND2X7 U6840 ( .A(\lte_x_59/B[15] ), .B(n4677), .Z(n3893) );
HS65_LH_CNIVX7 U6850 ( .A(n5062), .Z(n4677) );
HS65_LL_NAND3X2 U6851 ( .A(n8775), .B(n9169), .C(n8078), .Z(n8079) );
HS65_LL_NOR2X9 U6867 ( .A(\u_DataPath/cw_to_ex_i [4]), .B(n5120), .Z(n3422)
);
HS65_LH_IVX9 U6868 ( .A(n3422), .Z(n3423) );
HS65_LL_NAND2X4 U6870 ( .A(n5491), .B(n3422), .Z(n3442) );
HS65_LL_NAND3X2 U6916 ( .A(n5090), .B(n5474), .C(n5319), .Z(n4662) );
HS65_LL_NOR2X3 U6923 ( .A(n4661), .B(n5548), .Z(n5319) );
HS65_LL_NAND2X5 U6927 ( .A(\sub_x_53/A[2] ), .B(n3415), .Z(n4573) );
HS65_LL_OAI12X2 U6928 ( .A(n5546), .B(n5318), .C(n4662), .Z(n4669) );
HS65_LL_NAND2X2 U6931 ( .A(n5090), .B(n4573), .Z(n5546) );
HS65_LL_IVX7 U6943 ( .A(\u_DataPath/from_mem_data_out_i [2]), .Z(n2933) );
HS65_LL_NAND2X7 U6957 ( .A(n3512), .B(n3511), .Z(n3513) );
HS65_LLS_XNOR2X6 U6963 ( .A(n3509), .B(n3508), .Z(n3510) );
HS65_LL_IVX7 U6964 ( .A(\u_DataPath/from_mem_data_out_i [3]), .Z(n2969) );
HS65_LL_OAI22X1 U6971 ( .A(n3333), .B(\u_DataPath/dataOut_exe_i [5]), .C(
n8391), .D(n3340), .Z(n3334) );
HS65_LH_NOR2X5 U6975 ( .A(n8391), .B(n9401), .Z(n4654) );
HS65_LLS_XNOR2X3 U6984 ( .A(n4884), .B(n4883), .Z(n4885) );
HS65_LL_NOR3X4 U6988 ( .A(n3465), .B(n3464), .C(n3463), .Z(n3466) );
HS65_LL_NAND2AX4 U7002 ( .A(n3438), .B(n3437), .Z(n3465) );
HS65_LL_OAI31X2 U7006 ( .A(n5177), .B(n4581), .C(n3713), .D(n3454), .Z(n3464) );
HS65_LH_NAND2X5 U7010 ( .A(n5170), .B(n5667), .Z(n3437) );
HS65_LL_NOR3X4 U7012 ( .A(\u_DataPath/u_idexreg/N15 ), .B(n8103), .C(
\u_DataPath/u_idexreg/N10 ), .Z(n8126) );
HS65_LH_NAND2X7 U7014 ( .A(n7631), .B(n4414), .Z(n4415) );
HS65_LL_NOR2X3 U7015 ( .A(\lte_x_59/B[6] ), .B(n2865), .Z(n4643) );
HS65_LL_NAND2X4 U7037 ( .A(n3323), .B(n3322), .Z(n3325) );
HS65_LL_NAND3X5 U7045 ( .A(n5220), .B(n5219), .C(n5218), .Z(n5221) );
HS65_LL_NAND2X4 U7048 ( .A(n5217), .B(n5216), .Z(n5218) );
HS65_LL_NOR2X5 U7049 ( .A(\lte_x_59/B[16] ), .B(n5021), .Z(n3560) );
HS65_LL_NAND2X5 U7051 ( .A(n3207), .B(n8526), .Z(n3208) );
HS65_LLS_XNOR2X3 U7063 ( .A(n5215), .B(n5214), .Z(n5216) );
HS65_LL_NAND2X4 U7069 ( .A(n5672), .B(n6122), .Z(n4277) );
HS65_LL_NAND3X5 U7082 ( .A(n4266), .B(n4265), .C(n4264), .Z(n6122) );
HS65_LL_AND2X4 U7085 ( .A(n9211), .B(n9366), .Z(n8424) );
HS65_LL_CNIVX7 U7097 ( .A(\u_DataPath/dataOut_exe_i [1]), .Z(n8177) );
HS65_LL_NOR2X3 U7098 ( .A(n4701), .B(n4582), .Z(n3953) );
HS65_LL_NAND2X7 U7100 ( .A(n8166), .B(n6145), .Z(n6152) );
HS65_LH_IVX2 U7104 ( .A(\u_DataPath/jaddr_i [25]), .Z(n8166) );
HS65_LL_AND2ABX18 U7109 ( .A(n3425), .B(n5088), .Z(n4836) );
HS65_LL_AOI21X2 U7114 ( .A(n5661), .B(n5239), .C(n5238), .Z(n5245) );
HS65_LL_IVX7 U7121 ( .A(n4609), .Z(n5239) );
HS65_LL_AOI21X2 U7154 ( .A(n5229), .B(n5228), .C(n5227), .Z(n5246) );
HS65_LL_NAND3AX6 U7160 ( .A(n3829), .B(n3828), .C(n3827), .Z(n3844) );
HS65_LL_CNIVX3 U7161 ( .A(n4840), .Z(n3858) );
HS65_LL_NOR2AX3 U7172 ( .A(n3789), .B(n2860), .Z(n3820) );
HS65_LLS_XNOR2X3 U7173 ( .A(n4482), .B(n4645), .Z(n4483) );
HS65_LL_AOI21X2 U7180 ( .A(n4646), .B(n4645), .C(n4644), .Z(n4647) );
HS65_LL_OAI21X2 U7183 ( .A(n3394), .B(n8485), .C(n3395), .Z(n3293) );
HS65_LL_MX41X4 U7194 ( .D0(n8441), .S0(n9275), .D1(n8440), .S1(n9290), .D2(
n9297), .S2(n8439), .D3(n8438), .S3(n9282), .Z(
\u_DataPath/from_mem_data_out_i [1]) );
HS65_LL_NAND4ABX3 U7197 ( .A(n8106), .B(n8105), .C(n8104), .D(n8126), .Z(
\u_DataPath/cw_to_ex_i [2]) );
HS65_LL_NAND2X2 U7208 ( .A(n5667), .B(n3522), .Z(n3523) );
HS65_LL_NOR2X2 U7210 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(n5079), .Z(n5117)
);
HS65_LH_OAI21X2 U7217 ( .A(n5173), .B(n5204), .C(n3880), .Z(n3881) );
HS65_LH_AOI22X1 U7218 ( .A(n4951), .B(n4615), .C(n5667), .D(n4614), .Z(n4619) );
HS65_LH_NAND2X2 U7223 ( .A(n5667), .B(n5228), .Z(n3714) );
HS65_LL_NOR2X2 U7224 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(n5119), .Z(n4782)
);
HS65_LL_NAND2X2 U7225 ( .A(n5667), .B(n5174), .Z(n4848) );
HS65_LH_NOR2X2 U7233 ( .A(n5173), .B(n4357), .Z(n4358) );
HS65_LL_OAI21X2 U7245 ( .A(n5173), .B(n4526), .C(n4525), .Z(n4531) );
HS65_LL_NAND2X2 U7255 ( .A(n5667), .B(n5617), .Z(n4267) );
HS65_LH_OAI22X1 U7275 ( .A(n4435), .B(n5173), .C(n4954), .D(n3858), .Z(n3829) );
HS65_LL_NOR2X2 U7285 ( .A(n5173), .B(n4355), .Z(n3597) );
HS65_LL_AOI12X2 U7306 ( .A(n5667), .B(n5243), .C(n5242), .Z(n5244) );
HS65_LL_NAND2X2 U7308 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(
\u_DataPath/cw_to_ex_i [2]), .Z(n4965) );
HS65_LL_NOR2X2 U7314 ( .A(\u_DataPath/u_idexreg/N3 ), .B(n5463), .Z(n5469)
);
HS65_LL_NOR2X2 U7333 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(n7617), .Z(n5217)
);
HS65_LL_NAND2X4 U7356 ( .A(n5463), .B(n5492), .Z(n5120) );
HS65_LL_NAND2X4 U7376 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(n5492), .Z(n3417)
);
HS65_LL_IVX2 U7379 ( .A(\u_DataPath/cw_to_ex_i [1]), .Z(n5463) );
HS65_LH_IVX2 U7381 ( .A(n8704), .Z(n3122) );
HS65_LL_AND3X18 U7386 ( .A(n8101), .B(n8072), .C(n8071), .Z(n9376) );
HS65_LL_OA12X4 U7387 ( .A(n9242), .B(n8453), .C(n7913), .Z(n9377) );
HS65_LH_OA222X4 U7393 ( .A(n9166), .B(n8898), .C(n9051), .D(n9127), .E(n8880), .F(n9268), .Z(n9378) );
HS65_LL_OA12X4 U7394 ( .A(n9268), .B(n8453), .C(n7913), .Z(n9379) );
HS65_LL_OA12X4 U7395 ( .A(n9123), .B(n8453), .C(n7913), .Z(n9380) );
HS65_LH_IVX2 U7396 ( .A(n8267), .Z(\u_DataPath/dataOut_exe_i [8]) );
HS65_LL_OA112X4 U7397 ( .A(n9246), .B(n8880), .C(n8291), .D(n9086), .Z(n9381) );
HS65_LL_OA12X4 U7399 ( .A(n9120), .B(n8453), .C(n9086), .Z(n9383) );
HS65_LL_OA12X4 U7401 ( .A(n9247), .B(n8453), .C(n9086), .Z(n9384) );
HS65_LL_OA12X4 U7404 ( .A(n9121), .B(n8453), .C(n7913), .Z(n9385) );
HS65_LL_OA112X4 U7405 ( .A(n9244), .B(n8880), .C(n8346), .D(n9086), .Z(n9386) );
HS65_LL_OA12X4 U7408 ( .A(n9124), .B(n8453), .C(n7913), .Z(n9387) );
HS65_LL_OA12X4 U7409 ( .A(n9243), .B(n8453), .C(n9086), .Z(n9388) );
HS65_LH_OA12X9 U7411 ( .A(n9245), .B(n8453), .C(n7913), .Z(n9389) );
HS65_LL_OA12X4 U7413 ( .A(n9125), .B(n8453), .C(n7913), .Z(n9391) );
HS65_LL_OA12X4 U7414 ( .A(n9248), .B(n8453), .C(n7913), .Z(n9392) );
HS65_LL_OA12X4 U7415 ( .A(n9244), .B(n8453), .C(n7913), .Z(n9393) );
HS65_LL_OA12X4 U7450 ( .A(n9126), .B(n8453), .C(n7913), .Z(n9394) );
HS65_LL_OA12X4 U7454 ( .A(n9129), .B(n8453), .C(n9086), .Z(n9395) );
HS65_LL_OA112X4 U7456 ( .A(n8880), .B(n9245), .C(n8273), .D(n9086), .Z(n9396) );
HS65_LH_IVX2 U7461 ( .A(n8297), .Z(\u_DataPath/dataOut_exe_i [7]) );
HS65_LL_OA112X4 U7466 ( .A(n9247), .B(n8880), .C(n8341), .D(n9086), .Z(n9397) );
HS65_LL_OA112X4 U7473 ( .A(n9242), .B(n8880), .C(n8334), .D(n9086), .Z(n9398) );
HS65_LH_OA22X4 U7480 ( .A(n8906), .B(n9269), .C(n9140), .D(n8758), .Z(n9399)
);
HS65_LH_OA22X4 U7494 ( .A(n8906), .B(n9270), .C(n9140), .D(n8760), .Z(n9400)
);
HS65_LL_OR3ABCX35 U7500 ( .A(n3217), .B(n2966), .C(n3216), .Z(n9401) );
HS65_LH_IVX18 U7524 ( .A(n2846), .Z(n2847) );
HS65_LLS_XNOR2X3 U7531 ( .A(n4821), .B(n4820), .Z(n9402) );
HS65_LH_AO22X4 U7551 ( .A(n9261), .B(n9136), .C(n9134), .D(n8936), .Z(n9403)
);
HS65_LH_AO22X4 U7555 ( .A(n9056), .B(n9136), .C(n9134), .D(n8956), .Z(n9404)
);
HS65_LH_AO22X4 U7575 ( .A(n9089), .B(n9136), .C(n9134), .D(n8953), .Z(n9405)
);
HS65_LH_AO22X4 U7577 ( .A(n9094), .B(n9136), .C(n9134), .D(n8957), .Z(n9406)
);
HS65_LH_AO22X4 U7583 ( .A(n9259), .B(n9136), .C(n9134), .D(n8950), .Z(n9407)
);
HS65_LH_AO22X4 U7584 ( .A(n9091), .B(n9136), .C(n9134), .D(n8955), .Z(n9408)
);
HS65_LH_AO22X4 U7591 ( .A(n8881), .B(n9136), .C(n9134), .D(n8954), .Z(n9409)
);
HS65_LH_AO22X4 U7598 ( .A(n9095), .B(n9136), .C(n9134), .D(n8959), .Z(n9410)
);
HS65_LH_AO22X4 U7599 ( .A(n9106), .B(n9136), .C(n9134), .D(n8958), .Z(n9411)
);
HS65_LH_AO22X4 U7604 ( .A(n9088), .B(n9136), .C(n9134), .D(n9064), .Z(n9412)
);
HS65_LH_AO22X4 U7605 ( .A(n9096), .B(n9136), .C(n9134), .D(n8952), .Z(n9413)
);
HS65_LH_AO22X4 U7606 ( .A(n9071), .B(n9136), .C(n9133), .D(n8977), .Z(n9414)
);
HS65_LH_AO22X4 U7660 ( .A(n9271), .B(n9188), .C(n9133), .D(n8990), .Z(n9415)
);
HS65_LH_AO22X4 U7676 ( .A(n9257), .B(n9188), .C(n9133), .D(n9023), .Z(n9416)
);
HS65_LH_AO22X4 U7677 ( .A(n9107), .B(n9188), .C(n9133), .D(n9024), .Z(n9417)
);
HS65_LH_AO22X4 U7686 ( .A(n9136), .B(n9200), .C(n9134), .D(n8949), .Z(n9418)
);
HS65_LH_IVX7 U7710 ( .A(n8704), .Z(n2784) );
HS65_LH_AO22X4 U7727 ( .A(n9192), .B(n9265), .C(n9132), .D(n9067), .Z(n9419)
);
HS65_LH_AO22X4 U7734 ( .A(n9192), .B(n9161), .C(n9132), .D(n8989), .Z(n9420)
);
HS65_LH_AO22X4 U7743 ( .A(n9192), .B(n9143), .C(n9132), .D(n8995), .Z(n9421)
);
HS65_LH_AO22X4 U7746 ( .A(n9192), .B(n9158), .C(n9132), .D(n8978), .Z(n9422)
);
HS65_LH_AO22X4 U7749 ( .A(n9192), .B(n9157), .C(n9132), .D(n8973), .Z(n9423)
);
HS65_LH_AO22X4 U7751 ( .A(n9192), .B(n9162), .C(n9132), .D(n8986), .Z(n9424)
);
HS65_LH_AO22X4 U7763 ( .A(n9192), .B(n9160), .C(n9132), .D(n9087), .Z(n9425)
);
HS65_LH_AO22X4 U7764 ( .A(n9192), .B(n9156), .C(n9132), .D(n8962), .Z(n9426)
);
HS65_LH_AO22X4 U7771 ( .A(n9192), .B(n9155), .C(n9132), .D(n8976), .Z(n9427)
);
HS65_LH_AO22X4 U7776 ( .A(n9191), .B(n9163), .C(n9131), .D(n8991), .Z(n9428)
);
HS65_LH_AO22X4 U7779 ( .A(n9191), .B(n9159), .C(n9131), .D(n8988), .Z(n9429)
);
HS65_LH_NOR2X2 U7780 ( .A(n9233), .B(n7117), .Z(n2877) );
HS65_LH_NAND4ABX3 U7809 ( .A(n9347), .B(n8755), .C(n9016), .D(n8071), .Z(
\u_DataPath/cw_exmem_i [10]) );
HS65_LL_DFPQX9 clk_r_REG490_S3 ( .D(n8635), .CP(clk), .Q(n9066) );
HS65_LL_OAI211X5 U3847 ( .A(n9149), .B(n9012), .C(n8877), .D(n8093), .Z(
\u_DataPath/cw_to_ex_i [3]) );
HS65_LL_NAND2AX7 U6275 ( .A(n4867), .B(n4866), .Z(n5686) );
HS65_LH_DFPQX4 clk_r_REG48_S1 ( .D(n8580), .CP(clk), .Q(n3023) );
HS65_LH_DFPQX4 clk_r_REG435_S3 ( .D(n8270), .CP(clk), .Q(n9081) );
HS65_LL_DFPQX4 clk_r_REG387_S2 ( .D(\u_DataPath/data_read_ex_2_i [0]), .CP(
clk), .Q(n9431) );
HS65_LH_DFPQX4 clk_r_REG431_S2 ( .D(n9115), .CP(clk), .Q(n9114) );
HS65_LL_DFPQNX9 clk_r_REG450_S1 ( .D(n8137), .CP(clk), .QN(
\u_DataPath/cw_towb_i [0]) );
HS65_LH_DFPQX9 clk_r_REG76_S2 ( .D(n8473), .CP(clk), .Q(n9027) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][27] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][24] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][17] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][9] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][27] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][17] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][9] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][23] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][0] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][17] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][22] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][21] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][23] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][11] ) );
HS65_LH_DFPQX4 clk_r_REG660_S1 ( .D(Data_out_fromRAM[24]), .CP(clk), .Q(
n9296) );
HS65_LH_DFPQX4 clk_r_REG686_S1 ( .D(Data_out_fromRAM[6]), .CP(clk), .Q(n9280) );
HS65_LH_DFPQX4 clk_r_REG395_S2 ( .D(n2851), .CP(clk), .Q(n9261) );
HS65_LH_DFPQX9 clk_r_REG657_S1 ( .D(n8319), .CP(clk), .Q(n9243) );
HS65_LH_DFPQX4 clk_r_REG368_S2 ( .D(n9212), .CP(clk), .Q(n9211) );
HS65_LH_DFPQX4 clk_r_REG270_S1 ( .D(\u_DataPath/branch_target_i [9]), .CP(
clk), .Q(n9195) );
HS65_LH_DFPQX4 clk_r_REG589_S2 ( .D(n9179), .CP(clk), .Q(n9178) );
HS65_LH_DFPRQX4 clk_r_REG512_S1 ( .D(n7897), .CP(clk), .RN(n7879), .Q(n9132)
);
HS65_LH_DFPQX4 clk_r_REG451_S1 ( .D(\u_DataPath/cw_tomem_i [4]), .CP(clk),
.Q(n9112) );
HS65_LH_DFPQX4 clk_r_REG60_S5 ( .D(\lte_x_59/B[6] ), .CP(clk), .Q(n9095) );
HS65_LH_DFPQX4 clk_r_REG149_S2 ( .D(\u_DataPath/u_execute/link_value_i [28]),
.CP(clk), .Q(n9057) );
HS65_LH_DFPQX4 clk_r_REG121_S2 ( .D(\u_DataPath/u_execute/link_value_i [10]),
.CP(clk), .Q(n9042) );
HS65_LH_DFPQX4 clk_r_REG573_S3 ( .D(n8086), .CP(clk), .Q(n9007) );
HS65_LH_DFPRQX4 clk_r_REG154_S4 ( .D(\u_DataPath/pc_4_i [22]), .CP(clk),
.RN(n9354), .Q(n8988) );
HS65_LH_DFPQX4 clk_r_REG268_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [11]),
.CP(clk), .Q(n8950) );
HS65_LH_DFPQX4 clk_r_REG378_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [1]),
.CP(clk), .Q(n8935) );
HS65_LH_DFPQX4 clk_r_REG122_S1 ( .D(\u_DataPath/branch_target_i [13]), .CP(
clk), .Q(n8919) );
HS65_LH_DFPQX4 clk_r_REG61_S5 ( .D(n8479), .CP(clk), .Q(n8901) );
HS65_LH_DFPQX4 clk_r_REG146_S2 ( .D(\u_DataPath/u_execute/link_value_i [29]),
.CP(clk), .Q(n8870) );
HS65_LH_DFPRQX4 clk_r_REG604_S3 ( .D(\u_DataPath/immediate_ext_dec_i [13]),
.CP(clk), .RN(n9354), .Q(n8790) );
HS65_LH_DFPRQX4 clk_r_REG559_S3 ( .D(\u_DataPath/jaddr_i [22]), .CP(clk),
.RN(n9354), .Q(n8765) );
HS65_LH_DFPQX4 clk_r_REG29_S2 ( .D(\u_DataPath/mem_writedata_out_i [27]),
.CP(clk), .Q(n8748) );
HS65_LH_DFPQX4 clk_r_REG81_S1 ( .D(\u_DataPath/mem_writedata_out_i [24]),
.CP(clk), .Q(n8732) );
HS65_LL_IVX9 U3856 ( .A(n8898), .Z(n8399) );
HS65_LL_NAND2X7 U7793 ( .A(n9102), .B(n9066), .Z(n8114) );
HS65_LH_OAI12X3 U6125 ( .A(n9190), .B(n9027), .C(n8307), .Z(
\u_DataPath/dataOut_exe_i [15]) );
HS65_LL_BFX18 U4321 ( .A(n9401), .Z(n7868) );
HS65_LL_NOR2X6 U3948 ( .A(n3214), .B(n3213), .Z(\lte_x_59/B[8] ) );
HS65_LL_OAI12X3 U3808 ( .A(n3349), .B(n4712), .C(n3348), .Z(n3419) );
HS65_LH_IVX9 U6106 ( .A(n5053), .Z(n2871) );
HS65_LL_OAI12X6 U6982 ( .A(n4654), .B(n3339), .C(n4655), .Z(n5040) );
HS65_LL_AOI21X2 U6075 ( .A(n9376), .B(n7846), .C(n3419), .Z(n3430) );
HS65_LL_NOR3AX9 U3639 ( .A(n4971), .B(n4973), .C(n3059), .Z(\lte_x_59/B[28] ) );
HS65_LL_NOR2X6 U5623 ( .A(n3086), .B(n3085), .Z(\lte_x_59/B[18] ) );
HS65_LL_AND2ABX18 U3927 ( .A(n3096), .B(n3095), .Z(\lte_x_59/B[16] ) );
HS65_LL_NAND2X7 U5585 ( .A(n3421), .B(n3422), .Z(n5179) );
HS65_LL_IVX9 U3750 ( .A(n3443), .Z(n3529) );
HS65_LL_IVX27 U3472 ( .A(n4795), .Z(n2864) );
HS65_LH_IVX9 U6673 ( .A(n5180), .Z(n3382) );
HS65_LH_NOR2AX6 U3718 ( .A(n3967), .B(n2872), .Z(n4550) );
HS65_LL_NOR2AX6 U3894 ( .A(n3210), .B(n4420), .Z(n5194) );
HS65_LH_NOR2AX3 U3700 ( .A(n9019), .B(n2994), .Z(n3014) );
HS65_LL_IVX18 U3452 ( .A(n2774), .Z(Data_in[23]) );
HS65_LL_IVX18 U3453 ( .A(n2776), .Z(Data_in[9]) );
HS65_LL_IVX18 U3454 ( .A(n2778), .Z(Data_in[18]) );
HS65_LL_IVX18 U3459 ( .A(n2819), .Z(Data_in[22]) );
HS65_LL_IVX18 U3460 ( .A(n2821), .Z(Data_in[13]) );
HS65_LL_IVX18 U3461 ( .A(n2838), .Z(Data_in[19]) );
HS65_LL_CNBFX14 U3699 ( .A(n3014), .Z(Data_in[8]) );
HS65_LL_IVX18 U3439 ( .A(n2787), .Z(Address_toRAM[21]) );
HS65_LL_IVX18 U3440 ( .A(n2789), .Z(Address_toRAM[20]) );
HS65_LL_IVX18 U3441 ( .A(n2791), .Z(Address_toRAM[23]) );
HS65_LL_IVX18 U3442 ( .A(n2793), .Z(Address_toRAM[22]) );
HS65_LL_IVX18 U3443 ( .A(n2795), .Z(Address_toRAM[19]) );
HS65_LL_IVX18 U3444 ( .A(n2797), .Z(Address_toRAM[18]) );
HS65_LL_IVX18 U3445 ( .A(n2799), .Z(Address_toRAM[28]) );
HS65_LL_IVX18 U3450 ( .A(n2801), .Z(Address_toRAM[27]) );
HS65_LL_IVX18 U3456 ( .A(n2805), .Z(Address_toRAM[6]) );
HS65_LL_IVX18 U3458 ( .A(n2809), .Z(Address_toRAM[9]) );
HS65_LL_IVX18 U3451 ( .A(n2811), .Z(Data_in[27]) );
HS65_LL_IVX18 U3524 ( .A(n2815), .Z(Data_in[29]) );
HS65_LL_IVX18 U3525 ( .A(n2813), .Z(Data_in[28]) );
HS65_LL_IVX18 U3527 ( .A(n2817), .Z(Data_in[30]) );
HS65_LL_IVX18 U3455 ( .A(n2803), .Z(Address_toRAM[10]) );
HS65_LL_IVX18 U3457 ( .A(n2807), .Z(Address_toRAM[8]) );
HS65_LL_IVX18 U3449 ( .A(n2784), .Z(addr_to_iram[14]) );
HS65_LL_NAND2X7 U6252 ( .A(n3395), .B(n3394), .Z(n3396) );
HS65_LH_BFX35 U3435 ( .A(n2986), .Z(n3116) );
HS65_LL_IVX18 U3436 ( .A(n3120), .Z(addr_to_iram[23]) );
HS65_LL_IVX18 U3510 ( .A(n7785), .Z(addr_to_iram[28]) );
HS65_LL_IVX18 U3513 ( .A(n3121), .Z(addr_to_iram[22]) );
HS65_LH_BFX9 U3514 ( .A(n2994), .Z(n3115) );
HS65_LL_NAND2X14 U3515 ( .A(n3112), .B(n2979), .Z(n2994) );
HS65_LH_AND2ABX27 U3536 ( .A(n3114), .B(n8573), .Z(n2986) );
HS65_LL_AOI21X2 U3539 ( .A(n5643), .B(n3888), .C(n3887), .Z(n3889) );
HS65_LH_OAI21X3 U3544 ( .A(n5201), .B(n5135), .C(n4466), .Z(n4470) );
HS65_LL_CNBFX21 U3557 ( .A(n5610), .Z(n2859) );
HS65_LH_IVX9 U3588 ( .A(n9348), .Z(n9349) );
HS65_LL_NOR2AX3 U3647 ( .A(n3415), .B(n5089), .Z(n4516) );
HS65_LH_NOR2X6 U3654 ( .A(n2842), .B(n5376), .Z(n4049) );
HS65_LL_OAI211X8 U3662 ( .A(n7868), .B(n3398), .C(n3397), .D(n3396), .Z(
n3401) );
HS65_LH_IVX2 U3721 ( .A(n5127), .Z(n5133) );
HS65_LH_IVX2 U3736 ( .A(n5474), .Z(n5475) );
HS65_LH_IVX2 U3779 ( .A(n4050), .Z(n5084) );
HS65_LH_NAND2X2 U3828 ( .A(n3892), .B(n5295), .Z(n5302) );
HS65_LH_IVX2 U3877 ( .A(n3967), .Z(n3968) );
HS65_LH_IVX2 U3924 ( .A(n5299), .Z(n5468) );
HS65_LH_IVX2 U3958 ( .A(n5186), .Z(n3720) );
HS65_LH_NAND2X4 U3961 ( .A(n4147), .B(n2848), .Z(n5327) );
HS65_LH_NAND3X2 U3965 ( .A(n4749), .B(n4870), .C(n4748), .Z(n4760) );
HS65_LH_NAND3X2 U3966 ( .A(n5563), .B(n5502), .C(n5501), .Z(n5528) );
HS65_LH_OAI21X2 U4000 ( .A(n5350), .B(n5349), .C(n5348), .Z(n5351) );
HS65_LH_IVX2 U4042 ( .A(n3665), .Z(n3667) );
HS65_LH_IVX2 U4099 ( .A(n3836), .Z(n3783) );
HS65_LH_NAND2X2 U4111 ( .A(n4717), .B(n9342), .Z(n3183) );
HS65_LH_OR2X4 U4118 ( .A(n4700), .B(n4795), .Z(n3665) );
HS65_LH_NAND2X2 U4122 ( .A(n5618), .B(n5617), .Z(n5619) );
HS65_LH_IVX2 U4151 ( .A(n4917), .Z(n3895) );
HS65_LH_NAND2X2 U4167 ( .A(\sub_x_53/A[23] ), .B(n4351), .Z(n3603) );
HS65_LH_NAND2X2 U4197 ( .A(n3721), .B(n3720), .Z(n3722) );
HS65_LH_IVX2 U4203 ( .A(n5346), .Z(n4709) );
HS65_LH_NOR3X1 U4213 ( .A(n5543), .B(n5542), .C(n5541), .Z(n5561) );
HS65_LH_CBI4I1X3 U4217 ( .A(n5316), .B(n5315), .C(n5325), .D(n5314), .Z(
n5485) );
HS65_LH_IVX2 U4218 ( .A(n4528), .Z(n4196) );
HS65_LH_NAND2X2 U4221 ( .A(n3494), .B(n3493), .Z(n3495) );
HS65_LH_NOR2AX3 U4225 ( .A(n3526), .B(n3525), .Z(n3527) );
HS65_LH_AOI21X2 U4232 ( .A(n5207), .B(n5139), .C(n4853), .Z(n4854) );
HS65_LH_NAND2X2 U4233 ( .A(n3665), .B(n3594), .Z(n3553) );
HS65_LH_NAND2X2 U4236 ( .A(n3327), .B(n9177), .Z(n3222) );
HS65_LH_NAND2X2 U4243 ( .A(n3482), .B(n3939), .Z(n3941) );
HS65_LHS_XNOR2X3 U4248 ( .A(n8942), .B(\u_DataPath/jaddr_i [21]), .Z(n7108)
);
HS65_LH_NOR2X2 U4250 ( .A(n5652), .B(n4582), .Z(n3903) );
HS65_LH_NOR2X2 U4252 ( .A(n4711), .B(n4582), .Z(n4524) );
HS65_LH_NOR2X2 U4256 ( .A(n5241), .B(n4185), .Z(n4186) );
HS65_LH_NAND2X2 U4259 ( .A(\sub_x_53/A[27] ), .B(n4976), .Z(n3684) );
HS65_LH_AOI21X2 U4264 ( .A(n3368), .B(n4917), .C(n3367), .Z(n3369) );
HS65_LH_NAND2X2 U4269 ( .A(n4516), .B(n4943), .Z(n4149) );
HS65_LH_NAND2X2 U4270 ( .A(n9221), .B(n9222), .Z(n4283) );
HS65_LH_OAI21X2 U4288 ( .A(n4320), .B(n4319), .C(n4318), .Z(n4321) );
HS65_LH_OAI21X2 U4304 ( .A(n4066), .B(n4490), .C(n6123), .Z(n4072) );
HS65_LH_AOI21X2 U4311 ( .A(n6123), .B(n4806), .C(n4460), .Z(n4461) );
HS65_LH_IVX2 U4345 ( .A(n4381), .Z(n4383) );
HS65_LH_IVX2 U4348 ( .A(n5260), .Z(n4251) );
HS65_LL_NAND3X2 U4354 ( .A(n5246), .B(n5245), .C(n5244), .Z(n5247) );
HS65_LH_NAND2AX4 U4366 ( .A(n3456), .B(n3455), .Z(n3458) );
HS65_LH_IVX2 U4392 ( .A(n5603), .Z(n5604) );
HS65_LH_OAI21X2 U4434 ( .A(n5789), .B(n5786), .C(n5788), .Z(n5761) );
HS65_LH_NAND2X2 U4454 ( .A(n3474), .B(n4588), .Z(n3959) );
HS65_LH_NAND3X2 U4492 ( .A(n7108), .B(n7107), .C(n7106), .Z(n7109) );
HS65_LH_NOR2X2 U4500 ( .A(n5179), .B(n3294), .Z(n4801) );
HS65_LH_IVX2 U4504 ( .A(n4622), .Z(n4623) );
HS65_LH_NAND2X2 U4517 ( .A(\lte_x_59/B[15] ), .B(n2864), .Z(n3833) );
HS65_LH_NAND2X2 U4542 ( .A(n3426), .B(n4491), .Z(n3979) );
HS65_LH_IVX2 U4545 ( .A(n4742), .Z(n3534) );
HS65_LH_IVX2 U4559 ( .A(n3979), .Z(n3757) );
HS65_LL_AOI12X2 U4573 ( .A(n4708), .B(n4707), .C(n4706), .Z(n4736) );
HS65_LH_NOR2X2 U4576 ( .A(n3788), .B(n4895), .Z(n3590) );
HS65_LH_OAI21X2 U4578 ( .A(n6070), .B(n5976), .C(n5978), .Z(n5927) );
HS65_LH_OAI21X2 U4602 ( .A(n2873), .B(n9346), .C(n4489), .Z(n4493) );
HS65_LH_IVX2 U4606 ( .A(n4328), .Z(n4329) );
HS65_LH_NAND2X2 U4607 ( .A(n4873), .B(n4951), .Z(n4065) );
HS65_LH_NAND2X2 U4611 ( .A(n4383), .B(n4382), .Z(n4387) );
HS65_LH_NAND2X2 U4625 ( .A(n5272), .B(n5275), .Z(n4248) );
HS65_LH_NAND2X2 U4633 ( .A(n9285), .B(n8399), .Z(n8291) );
HS65_LH_NAND2X2 U4638 ( .A(n9175), .B(n9227), .Z(n5884) );
HS65_LH_AO22X4 U4653 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][0] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][0] ), .Z(n7443)
);
HS65_LH_AO22X4 U4701 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][28] ), .B(n7522),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][28] ), .Z(n7503)
);
HS65_LH_AOI22X1 U4705 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][5] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][5] ), .D(
n7285), .Z(n6938) );
HS65_LH_AO22X4 U4768 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][24] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][24] ), .D(
n7586), .Z(n7562) );
HS65_LH_AO22X4 U4820 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][26] ), .B(n7522),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][26] ), .Z(n7328)
);
HS65_LH_AO22X4 U4832 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][3] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][3] ), .Z(n7401)
);
HS65_LH_NOR2X2 U4842 ( .A(n7658), .B(n7657), .Z(n7684) );
HS65_LH_AOI22X1 U4846 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][30] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][30] ), .D(
n2888), .Z(n6129) );
HS65_LH_IVX2 U4848 ( .A(n5824), .Z(n5825) );
HS65_LH_OAI22X1 U4855 ( .A(n7112), .B(n7111), .C(n7110), .D(n7109), .Z(n7113) );
HS65_LH_AOI22X1 U4864 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][2] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][2] ), .D(n2889), .Z(n6960) );
HS65_LH_AOI22X1 U4868 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][21] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][21] ), .D(
n2889), .Z(n7590) );
HS65_LH_AO22X4 U4870 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][16] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][16] ), .D(
n7586), .Z(n7542) );
HS65_LH_AO22X4 U4877 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][29] ), .B(n7522),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][29] ), .Z(n7529)
);
HS65_LH_AO22X4 U4880 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][20] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][20] ), .Z(n7483)
);
HS65_LH_AOI22X1 U4889 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][30] ), .B(n7580),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][30] ), .D(
n7579), .Z(n7417) );
HS65_LH_AO22X4 U4894 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][14] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][14] ), .Z(n7381)
);
HS65_LH_AOI22X1 U4895 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][14] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][14] ), .D(
n2891), .Z(n7370) );
HS65_LH_AOI22X1 U4896 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][4] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][4] ), .D(
n2891), .Z(n7350) );
HS65_LH_NOR2X6 U4897 ( .A(n6350), .B(n6352), .Z(n6966) );
HS65_LH_NOR2X9 U4898 ( .A(n6148), .B(n6152), .Z(n6426) );
HS65_LH_BFX4 U4902 ( .A(n6637), .Z(n7284) );
HS65_LH_AO22X4 U4905 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][2] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][2] ), .D(n6619), .Z(n6555) );
HS65_LH_AOI22X1 U4915 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][25] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][25] ), .D(
n6625), .Z(n7149) );
HS65_LH_AO22X4 U4921 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][9] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][9] ), .D(
n6629), .Z(n7127) );
HS65_LH_AO22X4 U4923 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][28] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][28] ), .D(
n7292), .Z(n6921) );
HS65_LH_AOI22X1 U4933 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][17] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][17] ), .D(
n7294), .Z(n6900) );
HS65_LH_AOI22X1 U4934 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][31] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][31] ), .D(
n6384), .Z(n6880) );
HS65_LH_AOI22X1 U4944 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][31] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][31] ), .D(
n7264), .Z(n6870) );
HS65_LH_AOI22X1 U4945 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][18] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][18] ), .D(
n2888), .Z(n6652) );
HS65_LH_AO22X4 U4949 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][20] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][20] ), .D(
n7266), .Z(n6848) );
HS65_LH_AO22X4 U4951 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][29] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][29] ), .D(
n7267), .Z(n7268) );
HS65_LH_AOI22X1 U4957 ( .A(n3426), .B(n4886), .C(n4836), .D(n4873), .Z(n3556) );
HS65_LH_AOI22X1 U4969 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][8] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][8] ), .D(n7516),
.Z(n6774) );
HS65_LH_AOI22X1 U5038 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][11] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][11] ), .D(
n6625), .Z(n6251) );
HS65_LH_AO22X4 U5042 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][31] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][31] ), .D(
n7318), .Z(n6677) );
HS65_LH_AO22X4 U5108 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][6] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][6] ), .Z(n7255)
);
HS65_LH_AO22X4 U5120 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][21] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][21] ), .D(
n6637), .Z(n6195) );
HS65_LH_AO22X4 U5137 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][17] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][17] ), .Z(n6818)
);
HS65_LH_AO22X4 U5149 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][16] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][16] ), .D(
n6637), .Z(n6175) );
HS65_LH_AOI22X1 U5207 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][23] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][23] ), .Z(n7233)
);
HS65_LH_AOI22X1 U5208 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][1] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][1] ), .D(n2889), .Z(n6833) );
HS65_LH_AOI22X1 U5237 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][27] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][27] ), .D(
n6625), .Z(n6211) );
HS65_LH_AO22X4 U5270 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][19] ), .B(n7578),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][19] ), .Z(n6742)
);
HS65_LH_AO22X4 U5293 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][18] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][18] ), .Z(n6327)
);
HS65_LH_AOI22X1 U5344 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][7] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][7] ), .D(n7516),
.Z(n6726) );
HS65_LH_AOI22X1 U5355 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][22] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][22] ), .D(
n6625), .Z(n6271) );
HS65_LH_AOI22X1 U5395 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][24] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][24] ), .D(
n6625), .Z(n6291) );
HS65_LH_AO22X4 U5453 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][5] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][5] ), .D(n7318), .Z(n6704) );
HS65_LH_AO22X4 U5473 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][12] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][12] ), .Z(n6798)
);
HS65_LH_AO22X4 U5496 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][13] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][13] ), .D(
n6637), .Z(n7174) );
HS65_LH_AOI22X1 U5531 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][14] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][14] ), .D(
n7285), .Z(n6314) );
HS65_LH_AOI22X1 U5578 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][19] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][19] ), .D(
n7171), .Z(n6523) );
HS65_LH_AO22X4 U5632 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][7] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][7] ), .D(n7291), .Z(n6450) );
HS65_LH_AO22X4 U5638 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][12] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][12] ), .D(
n7291), .Z(n6550) );
HS65_LH_AOI22X1 U5639 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][6] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][6] ), .D(n7294), .Z(n6488) );
HS65_LH_AOI22X1 U5650 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][3] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][3] ), .D(n6942), .Z(n6587) );
HS65_LH_AOI22X1 U5651 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][3] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][3] ), .D(
n7264), .Z(n6578) );
HS65_LH_AOI22X1 U5652 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][26] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][26] ), .D(
n7264), .Z(n6498) );
HS65_LH_AO22X4 U5657 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][8] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][8] ), .D(n7267), .Z(n6455) );
HS65_LH_AOI22X1 U5672 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][1] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][1] ), .D(
n6600), .Z(n6604) );
HS65_LH_AO22X4 U5684 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][9] ), .B(n7580),
.C(n7579), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][9] ), .Z(n7016) );
HS65_LH_AOI22X1 U5708 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][22] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][22] ), .Z(n7004)
);
HS65_LH_AO22X4 U5709 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][4] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][4] ), .D(n7291), .Z(n6645) );
HS65_LH_IVX2 U5710 ( .A(n3747), .Z(n3748) );
HS65_LH_NAND2X2 U5711 ( .A(n5131), .B(n4937), .Z(n4959) );
HS65_LH_NAND2X2 U5723 ( .A(n9183), .B(n9232), .Z(n5777) );
HS65_LH_NAND2X2 U5725 ( .A(n9342), .B(n9218), .Z(n5797) );
HS65_LH_OR2X4 U5744 ( .A(n9342), .B(n9210), .Z(n5910) );
HS65_LH_NAND2X2 U5746 ( .A(n9224), .B(n9226), .Z(n5687) );
HS65_LH_NOR2X2 U5751 ( .A(n9030), .B(n9223), .Z(n5836) );
HS65_LH_NOR2AX3 U5755 ( .A(n4299), .B(n4298), .Z(n4300) );
HS65_LH_OA112X4 U5764 ( .A(n9248), .B(n8880), .C(n8400), .D(n9086), .Z(n9382) );
HS65_LH_IVX2 U5786 ( .A(n4073), .Z(n4074) );
HS65_LH_NAND2X2 U5796 ( .A(n5131), .B(n4868), .Z(n4869) );
HS65_LH_OA12X4 U5801 ( .A(n9122), .B(n8453), .C(n7913), .Z(n9390) );
HS65_LH_IVX2 U5803 ( .A(n5832), .Z(n5892) );
HS65_LH_NAND2X2 U5807 ( .A(n5884), .B(n5883), .Z(n5889) );
HS65_LH_NAND2X2 U5821 ( .A(n4187), .B(n3407), .Z(n3408) );
HS65_LH_NAND2X2 U5842 ( .A(n4573), .B(n4539), .Z(n4540) );
HS65_LH_NAND3X2 U5849 ( .A(n2977), .B(n2978), .C(n2976), .Z(n2985) );
HS65_LH_NAND2X2 U5918 ( .A(n2896), .B(n3226), .Z(n6124) );
HS65_LH_IVX2 U5926 ( .A(\u_DataPath/dataOut_exe_i [12]), .Z(n3256) );
HS65_LH_AO22X4 U5945 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][15] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][15] ), .Z(n7195)
);
HS65_LH_AO22X4 U5962 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][10] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][10] ), .Z(n7215)
);
HS65_LH_AOI22X1 U5977 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][0] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][0] ), .D(
n7171), .Z(n6422) );
HS65_LH_AO22X4 U5999 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][10] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][10] ), .D(
n7291), .Z(n6409) );
HS65_LH_AOI22X1 U6004 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][15] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][15] ), .D(
n7294), .Z(n6387) );
HS65_LH_OR4X4 U6007 ( .A(n7152), .B(n7151), .C(n2882), .D(n2883), .Z(n7158)
);
HS65_LH_NAND2X2 U6023 ( .A(n5643), .B(n4826), .Z(n4827) );
HS65_LH_OAI21X2 U6028 ( .A(n4803), .B(n4954), .C(n4802), .Z(n4814) );
HS65_LH_AOI22X1 U6038 ( .A(n5131), .B(n4617), .C(n4887), .D(n4616), .Z(n4618) );
HS65_LH_IVX2 U6057 ( .A(n7693), .Z(n7738) );
HS65_LH_IVX2 U6130 ( .A(n8122), .Z(n7761) );
HS65_LH_NAND2X2 U6133 ( .A(n5624), .B(n4816), .Z(n3568) );
HS65_LH_IVX2 U6148 ( .A(n7688), .Z(n7771) );
HS65_LL_OAI112X3 U6151 ( .A(n2920), .B(n5596), .C(n5595), .D(n5594), .Z(
n5712) );
HS65_LH_NAND2X2 U6173 ( .A(n4331), .B(n3130), .Z(n3393) );
HS65_LH_IVX2 U6222 ( .A(\u_DataPath/dataOut_exe_i [28]), .Z(n3127) );
HS65_LH_NAND2X2 U6228 ( .A(n5877), .B(n6031), .Z(n5830) );
HS65_LH_AOI21X2 U6239 ( .A(n5866), .B(n5868), .C(n5821), .Z(n5822) );
HS65_LH_NAND2X2 U6256 ( .A(n8911), .B(n9202), .Z(n5920) );
HS65_LH_NAND2X2 U6273 ( .A(n9145), .B(n9224), .Z(n5959) );
HS65_LH_OAI21X2 U6295 ( .A(n5995), .B(n6000), .C(n5997), .Z(n6015) );
HS65_LH_IVX2 U6318 ( .A(n6019), .Z(n6020) );
HS65_LH_NAND2X2 U6319 ( .A(n8967), .B(n9220), .Z(n6064) );
HS65_LH_NOR2X2 U6327 ( .A(n9177), .B(n9229), .Z(n6078) );
HS65_LH_OR2X4 U6351 ( .A(n8911), .B(n9205), .Z(n6117) );
HS65_LH_IVX2 U6354 ( .A(n7728), .Z(n7730) );
HS65_LH_NAND2X2 U6368 ( .A(n7631), .B(n4249), .Z(n4282) );
HS65_LH_OAI21X2 U6385 ( .A(n5173), .B(n5172), .C(n5171), .Z(n5191) );
HS65_LH_NAND2X2 U6415 ( .A(n5688), .B(n7729), .Z(n7720) );
HS65_LH_NAND3X2 U6419 ( .A(Data_out_fromRAM[31]), .B(n8270), .C(n8576), .Z(
n7346) );
HS65_LH_OR2X4 U6445 ( .A(n8332), .B(n3340), .Z(n3081) );
HS65_LH_NOR2X2 U6446 ( .A(n8799), .B(n3403), .Z(n3100) );
HS65_LH_NAND2X2 U6458 ( .A(n9365), .B(n9040), .Z(n8413) );
HS65_LH_AOI22X1 U6506 ( .A(n8868), .B(n9144), .C(n9368), .D(n9000), .Z(n8419) );
HS65_LH_IVX2 U6541 ( .A(n2985), .Z(n2979) );
HS65_LH_NAND2X2 U6543 ( .A(n7654), .B(n7749), .Z(n7752) );
HS65_LH_AO22X4 U6584 ( .A(n9256), .B(n9188), .C(n9133), .D(n8933), .Z(
\u_DataPath/jump_address_i [22]) );
HS65_LH_AO22X4 U6607 ( .A(n9053), .B(n9188), .C(n9133), .D(n9080), .Z(
\u_DataPath/jump_address_i [3]) );
HS65_LH_AO22X4 U6686 ( .A(n8937), .B(n9109), .C(n9188), .D(n9092), .Z(
\u_DataPath/jump_address_i [0]) );
HS65_LH_IVX2 U6725 ( .A(n7734), .Z(n7778) );
HS65_LH_IVX2 U6727 ( .A(n6124), .Z(n8504) );
HS65_LH_NAND2AX4 U6729 ( .A(n8864), .B(n3291), .Z(n8511) );
HS65_LH_IVX2 U6732 ( .A(n7775), .Z(n8116) );
HS65_LL_NAND3X2 U6735 ( .A(n4505), .B(n4511), .C(n4510), .Z(n5250) );
HS65_LH_NOR4ABX2 U6744 ( .A(n6698), .B(n6697), .C(n6696), .D(n6695), .Z(
n8158) );
HS65_LH_NOR4ABX2 U6746 ( .A(n6738), .B(n6737), .C(n6736), .D(n6735), .Z(
n8180) );
HS65_LH_NAND2X2 U6749 ( .A(n7631), .B(n4649), .Z(n4650) );
HS65_LHS_XNOR2X3 U6757 ( .A(n3952), .B(n3951), .Z(n4000) );
HS65_LH_NAND2X4 U6763 ( .A(n5712), .B(n5711), .Z(n5715) );
HS65_LH_NAND2X2 U6793 ( .A(n6047), .B(n6046), .Z(n6048) );
HS65_LH_IVX2 U6831 ( .A(n6051), .Z(n6101) );
HS65_LH_NAND2X2 U6837 ( .A(n5989), .B(n5787), .Z(n5994) );
HS65_LH_NOR2X2 U6866 ( .A(n7753), .B(n7752), .Z(n7655) );
HS65_LH_NOR2X2 U6869 ( .A(n7686), .B(n7755), .Z(n7687) );
HS65_LH_OAI21X2 U6886 ( .A(n6090), .B(n6089), .C(n6088), .Z(n6091) );
HS65_LH_IVX2 U6892 ( .A(n9223), .Z(n7791) );
HS65_LH_NAND3X2 U6907 ( .A(opcode_i[1]), .B(n7643), .C(n7642), .Z(n8047) );
HS65_LH_NAND2X2 U6908 ( .A(n4485), .B(n4484), .Z(n4486) );
HS65_LH_NOR3X1 U6956 ( .A(n5191), .B(n5190), .C(n5189), .Z(n5225) );
HS65_LH_NOR2X2 U6958 ( .A(n8850), .B(n3403), .Z(n3250) );
HS65_LH_OAI21X2 U6967 ( .A(n7775), .B(n7683), .C(n7682), .Z(n7740) );
HS65_LH_IVX2 U7003 ( .A(n8236), .Z(n7117) );
HS65_LHS_XOR2X3 U7022 ( .A(n7785), .B(n7784), .Z(\u_DataPath/pc_4_i [30]) );
HS65_LH_AO22X4 U7028 ( .A(n9192), .B(n8862), .C(n8690), .D(n9240), .Z(
\u_DataPath/pc4_to_idexreg_i [0]) );
HS65_LHS_XOR2X3 U7038 ( .A(n2829), .B(n7747), .Z(\u_DataPath/pc_4_i [9]) );
HS65_LH_IVX2 U7050 ( .A(Data_out_fromRAM[28]), .Z(n8417) );
HS65_LH_AO22X4 U7052 ( .A(n9254), .B(n8807), .C(n9240), .D(n8963), .Z(
\u_DataPath/pc4_to_idexreg_i [6]) );
HS65_LH_AO22X4 U7090 ( .A(n8782), .B(n9253), .C(n9312), .D(n9142), .Z(
\u_DataPath/immediate_ext_dec_i [9]) );
HS65_LH_NOR4ABX2 U7112 ( .A(n7223), .B(n7222), .C(n7221), .D(n7220), .Z(
n8181) );
HS65_LH_AO22X4 U7141 ( .A(n8770), .B(n9252), .C(n9305), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [2]) );
HS65_LH_AO22X4 U7150 ( .A(n8774), .B(n9252), .C(n9304), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [1]) );
HS65_LHS_XNOR2X3 U7157 ( .A(n2833), .B(n7749), .Z(\u_DataPath/pc_4_i [10])
);
HS65_LHS_XOR2X3 U7202 ( .A(n2823), .B(n7750), .Z(\u_DataPath/pc_4_i [11]) );
HS65_LHS_XNOR2X3 U7243 ( .A(n6120), .B(n6119), .Z(
\u_DataPath/u_execute/resAdd1_i [28]) );
HS65_LHS_XNOR2X3 U7244 ( .A(n7717), .B(n7716), .Z(
\u_DataPath/u_execute/link_value_i [17]) );
HS65_LHS_XOR2X3 U7291 ( .A(n7791), .B(n7790), .Z(
\u_DataPath/u_execute/link_value_i [5]) );
HS65_LH_IVX2 U7296 ( .A(n8298), .Z(n8299) );
HS65_LH_IVX2 U7322 ( .A(n8576), .Z(n8271) );
HS65_LH_IVX2 U7332 ( .A(n3109), .Z(n8578) );
HS65_LH_IVX2 U7342 ( .A(Data_out_fromRAM[23]), .Z(n8360) );
HS65_LH_IVX18 U7385 ( .A(n2842), .Z(n4675) );
HS65_LH_NAND2X7 U7398 ( .A(n5626), .B(n5625), .Z(n5640) );
HS65_LL_NAND3X6 U7412 ( .A(n8476), .B(n8477), .C(n2918), .Z(n5163) );
HS65_LH_NAND2AX4 U7429 ( .A(n3282), .B(n3368), .Z(n3370) );
HS65_LL_AND2X4 U7445 ( .A(n8473), .B(n8472), .Z(n2918) );
HS65_LL_NOR2AX6 U7464 ( .A(n3948), .B(n3947), .Z(n8473) );
HS65_LL_NAND2AX7 U7476 ( .A(n2921), .B(n3235), .Z(n4683) );
HS65_LL_OAI21X2 U7478 ( .A(n4427), .B(n2859), .C(n4426), .Z(n4428) );
HS65_LL_CNBFX17 U7534 ( .A(\u_DataPath/cw_towb_i [0]), .Z(n3404) );
HS65_LH_IVX9 U7558 ( .A(n9431), .Z(n3285) );
HS65_LL_NAND2X7 U7568 ( .A(n7874), .B(n5683), .Z(n5684) );
HS65_LL_NOR2X9 U7580 ( .A(n5678), .B(n5677), .Z(n7853) );
HS65_LL_NOR2X6 U7601 ( .A(n4793), .B(n4792), .Z(n4832) );
HS65_LHS_XOR2X3 U7616 ( .A(n4562), .B(n2897), .Z(n4563) );
HS65_LL_NAND2X4 U7623 ( .A(n5597), .B(n5712), .Z(n5600) );
HS65_LL_NAND3X6 U7644 ( .A(n8461), .B(n8459), .C(n5283), .Z(n5601) );
HS65_LL_BFX9 U7675 ( .A(n9066), .Z(n9347) );
HS65_LL_NAND2AX21 U7712 ( .A(n5163), .B(n5162), .Z(n5683) );
HS65_LHS_XOR2X3 U7717 ( .A(n3101), .B(n4997), .Z(n4774) );
HS65_LL_AOI21X6 U7756 ( .A(n5285), .B(n3697), .C(n3696), .Z(n8461) );
HS65_LH_AO22X4 U7760 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][15] ), .B(n7523),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][15] ), .Z(n7194)
);
HS65_LH_AO22X4 U7784 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][8] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][8] ), .Z(n6777)
);
HS65_LH_AO22X4 U7814 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][23] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][23] ), .Z(n7234)
);
HS65_LH_AO22X4 U7816 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][6] ), .B(n7523),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][6] ), .Z(n7254)
);
HS65_LH_AO22X4 U7819 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][31] ), .B(n7523),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][31] ), .Z(n6687)
);
HS65_LH_AO22X4 U7830 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][7] ), .B(n7523),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][7] ), .Z(n6729)
);
HS65_LH_AO22X4 U7846 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][30] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][30] ), .Z(n7422)
);
HS65_LH_AO22X4 U7868 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][20] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][20] ), .Z(n7482)
);
HS65_LH_AO22X4 U7871 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][3] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][3] ), .Z(n7397)
);
HS65_LH_AO22X4 U7881 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][28] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][28] ), .Z(n7502)
);
HS65_LH_AO22X4 U7900 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][14] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][14] ), .Z(n7377)
);
HS65_LH_AO22X4 U7901 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][29] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][29] ), .Z(n7528)
);
HS65_LH_AO22X4 U7902 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][0] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][0] ), .Z(n7442)
);
HS65_LH_AO22X4 U7903 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][13] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][13] ), .Z(n6986)
);
HS65_LH_AO22X4 U7904 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][22] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][22] ), .Z(n7006)
);
HS65_LH_AO22X4 U8092 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][9] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][9] ), .Z(n7026)
);
HS65_LH_AO22X4 U8133 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][11] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][11] ), .Z(n7066)
);
HS65_LH_AO22X4 U8136 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][25] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][25] ), .Z(n7046)
);
HS65_LH_AO22X4 U8152 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][19] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][19] ), .Z(n6757)
);
HS65_LH_AO22X4 U8162 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][18] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][18] ), .Z(n6345)
);
HS65_LH_AO22X4 U8169 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][12] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][12] ), .Z(n6797)
);
HS65_LH_AO22X4 U8175 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][1] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][1] ), .Z(n6837)
);
HS65_LHS_XNOR2X3 U8179 ( .A(n4598), .B(n4597), .Z(n4599) );
HS65_LL_AND2X9 U8184 ( .A(n3397), .B(n3293), .Z(n4805) );
HS65_LL_NOR2X5 U8198 ( .A(n5161), .B(n5710), .Z(n5162) );
HS65_LL_NAND3AX6 U8203 ( .A(n5686), .B(n8474), .C(n8475), .Z(n5161) );
HS65_LL_NOR3X4 U8219 ( .A(n7867), .B(n4302), .C(n5708), .Z(n4456) );
HS65_LH_NAND2X7 U8277 ( .A(\lte_x_59/B[8] ), .B(n4551), .Z(n3867) );
HS65_LH_AOI12X2 U8297 ( .A(n3688), .B(n5211), .C(n3687), .Z(n3689) );
HS65_LL_CNIVX7 U8319 ( .A(n4427), .Z(n2867) );
HS65_LH_IVX4 U8332 ( .A(n9348), .Z(n9352) );
HS65_LH_IVX7 U8339 ( .A(n9376), .Z(n4717) );
HS65_LH_CNIVX3 U8349 ( .A(\u_DataPath/jaddr_i [20]), .Z(n2881) );
HS65_LH_NOR2X5 U8351 ( .A(n5054), .B(n5053), .Z(n5299) );
HS65_LL_NAND3X2 U8361 ( .A(n3871), .B(n3870), .C(n3869), .Z(n5143) );
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:04:28 04/05/2016
// Design Name:
// Module Name: ALU_1bit_overflow
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALU_1bit_overflow
(
// Input
input a_in,
input b_in,
input carry_in,
input b_invert,
input less,
input [1:0] op,
// Output
output wire result,
output wire carry_out,
output wire set,
output wire overflow
);
// Internal Variables
reg b_invert_out;
reg mux_out;
reg check;
wire fa_01_out;
wire and_out;
wire or_out;
//assign
assign set = fa_01_out;
assign overflow = check;
assign result = mux_out;
//submodule
full_adder fa_01 (
.x_in ( a_in ),
.y_in ( b_invert_out ),
.c_in ( carry_in ),
.s_out ( fa_01_out ),
.c_out ( carry_out )
); // Full_Adder
// b_Inverter
always @ ( b_invert or b_in )
begin : Binvert
if ( !b_invert )
b_invert_out = b_in; // b
else
b_invert_out = ~ b_in; // b'
end
// Logical_operation
assign and_out = a_in & b_invert_out;
assign or_out = a_in | b_invert_out;
// op_Selection
always @ ( op or and_out or or_out or less or fa_01_out )
begin : Operation
if ( op == 0 )
mux_out = and_out;
else if ( op == 1)
mux_out = or_out;
else if ( op == 2)
mux_out = fa_01_out;
else
mux_out = less;
end
//Overflow_detection
always @ ( op or a_in or b_invert_out or fa_01_out)
begin : Checker
if ( op == 0 || op == 1 )
check = 1'b0;
else if ( !( a_in ) && !(b_invert_out) && fa_01_out )
check = 1'b1;
else if ( a_in && b_invert_out && !( fa_01_out ) )
check = 1'b1;
else
check = 1'b0;
end
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
* 2019 Eddie Hung <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$__SHREG_ (input C, input D, input E, output Q);
parameter DEPTH = 0;
parameter [DEPTH-1:0] INIT = 0;
parameter CLKPOL = 1;
parameter ENPOL = 2;
\$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));
endmodule
module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
parameter DEPTH = 0;
parameter [DEPTH-1:0] INIT = 0;
parameter CLKPOL = 1;
parameter ENPOL = 2;
// shregmap's INIT parameter shifts out LSB first;
// however Xilinx expects MSB first
function [DEPTH-1:0] brev;
input [DEPTH-1:0] din;
integer i;
begin
for (i = 0; i < DEPTH; i=i+1)
brev[i] = din[DEPTH-1-i];
end
endfunction
localparam [DEPTH-1:0] INIT_R = brev(INIT);
parameter _TECHMAP_CONSTMSK_L_ = 0;
wire CE;
generate
if (ENPOL == 0)
assign CE = ~E;
else if (ENPOL == 1)
assign CE = E;
else
assign CE = 1'b1;
if (DEPTH == 1) begin
if (CLKPOL)
FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
else
FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
end else
if (DEPTH <= 16) begin
SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
end else
if (DEPTH > 17 && DEPTH <= 32) begin
SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
end else
if (DEPTH > 33 && DEPTH <= 64) begin
wire T0, T1, T2;
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
if (&_TECHMAP_CONSTMSK_L_)
assign Q = T2;
else
MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
end else
if (DEPTH > 65 && DEPTH <= 96) begin
wire T0, T1, T2, T3, T4, T5, T6;
SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
if (&_TECHMAP_CONSTMSK_L_)
assign Q = T4;
else
\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(1'bx), .S0(L[5]), .S1(L[6]), .O(Q));
end else
if (DEPTH > 97 && DEPTH < 128) begin
wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
if (&_TECHMAP_CONSTMSK_L_)
assign Q = T6;
else
\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));
end
else if (DEPTH == 128) begin
wire T0, T1, T2, T3, T4, T5, T6;
SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));
if (&_TECHMAP_CONSTMSK_L_)
assign Q = T6;
else
\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));
end
// For fixed length, if just 1 over a convenient value, decompose
else if (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_) begin
wire T;
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl (.C(C), .D(D), .L({32{1'b1}}), .E(E), .Q(T));
\$__XILINX_SHREG_ #(.DEPTH(1), .INIT(INIT[0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(T), .L(L), .E(E), .Q(Q));
end
// For variable length, if just 1 over a convenient value, then bump up one more
else if (DEPTH < 129 && ~&_TECHMAP_CONSTMSK_L_)
\$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
else begin
localparam depth0 = 128;
localparam num_srl128 = DEPTH / depth0;
localparam depthN = DEPTH % depth0;
wire [num_srl128 + (depthN > 0 ? 1 : 0) - 1:0] T;
wire [num_srl128 + (depthN > 0 ? 1 : 0) :0] S;
assign S[0] = D;
genvar i;
for (i = 0; i < num_srl128; i++)
\$__XILINX_SHREG_ #(.DEPTH(depth0), .INIT(INIT[DEPTH-1-i*depth0-:depth0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl (.C(C), .D(S[i]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[i]), .SO(S[i+1]));
if (depthN > 0)
\$__XILINX_SHREG_ #(.DEPTH(depthN), .INIT(INIT[depthN-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(S[num_srl128]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[num_srl128]));
if (&_TECHMAP_CONSTMSK_L_)
assign Q = T[num_srl128 + (depthN > 0 ? 1 : 0) - 1];
else
assign Q = T[L[DEPTH-1:$clog2(depth0)]];
end
endgenerate
endmodule
`ifdef MIN_MUX_INPUTS
module \$__XILINX_SHIFTX (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
function integer A_WIDTH_trimmed;
input integer start;
begin
A_WIDTH_trimmed = start;
while (A_WIDTH_trimmed > 0 && _TECHMAP_CONSTMSK_A_[A_WIDTH_trimmed-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH_trimmed-1] === 1'bx)
A_WIDTH_trimmed = A_WIDTH_trimmed - 1;
end
endfunction
generate
genvar i, j;
// Bit-blast
if (Y_WIDTH > 1) begin
for (i = 0; i < Y_WIDTH; i++)
\$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
end
// If the LSB of B is constant zero (and Y_WIDTH is 1) then
// we can optimise by removing every other entry from A
// and popping the constant zero from B
else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
wire [(A_WIDTH+1)/2-1:0] A_i;
for (i = 0; i < (A_WIDTH+1)/2; i++)
assign A_i[i] = A[i*2];
\$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
end
// Trim off any leading 1'bx -es in A
else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin
localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1);
\$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y));
end
else if (A_WIDTH < `MIN_MUX_INPUTS) begin
wire _TECHMAP_FAIL_ = 1;
end
else if (A_WIDTH == 2) begin
MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));
end
else if (A_WIDTH <= 4) begin
wire [4-1:0] Ax;
if (A_WIDTH == 4)
assign Ax = A;
else
// Rather than extend with 1'bx which gets flattened to 1'b0
// causing the "don't care" status to get lost, extend with
// the same driver of F7B.I0 so that we can optimise F7B away
// later
assign Ax = {A[1], A};
\$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y));
end
// Note that the following decompositions are 'backwards' in that
// the LSBs are placed on the hard resources, and the soft resources
// are used for MSBs.
// This has the effect of more effectively utilising the hard mux;
// take for example a 5:1 multiplexer, currently this would map as:
//
// A[0] \___ __ A[0] \__ __
// A[4] / \| \ whereas the more A[1] / \| \
// A[1] _____| | obvious mapping A[2] \___| |
// A[2] _____| |-- of MSBs to hard A[3] / | |__
// A[3]______| | resources would A[4] ____| |
// |__/ lead to: 1'bx ____| |
// || |__/
// || ||
// B[1:0] B[1:2]
//
// Expectation would be that the 'forward' mapping (right) is more
// area efficient (consider a 9:1 multiplexer using 2x4:1 multiplexers
// on its I0 and I1 inputs, and A[8] and 1'bx on its I2 and I3 inputs)
// but that the 'backwards' mapping (left) is more delay efficient
// since smaller LUTs are faster than wider ones.
else if (A_WIDTH <= 8) begin
wire [8-1:0] Ax = {{{8-A_WIDTH}{1'bx}}, A};
wire T0 = B[2] ? Ax[4] : Ax[0];
wire T1 = B[2] ? Ax[5] : Ax[1];
wire T2 = B[2] ? Ax[6] : Ax[2];
wire T3 = B[2] ? Ax[7] : Ax[3];
\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));
end
else if (A_WIDTH <= 16) begin
wire [16-1:0] Ax = {{{16-A_WIDTH}{1'bx}}, A};
wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4]
: B[3] ? Ax[ 8] : Ax[0];
wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5]
: B[3] ? Ax[ 9] : Ax[1];
wire T2 = B[2] ? B[3] ? Ax[14] : Ax[6]
: B[3] ? Ax[10] : Ax[2];
wire T3 = B[2] ? B[3] ? Ax[15] : Ax[7]
: B[3] ? Ax[11] : Ax[3];
\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));
end
else begin
localparam num_mux16 = (A_WIDTH+15) / 16;
localparam clog2_num_mux16 = $clog2(num_mux16);
wire [num_mux16-1:0] T;
wire [num_mux16*16-1:0] Ax = {{(num_mux16*16-A_WIDTH){1'bx}}, A};
for (i = 0; i < num_mux16; i++)
\$__XILINX_SHIFTX #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(16),
.B_WIDTH(4),
.Y_WIDTH(Y_WIDTH)
) fpga_mux (
.A(Ax[i*16+:16]),
.B(B[3:0]),
.Y(T[i])
);
\$__XILINX_SHIFTX #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(num_mux16),
.B_WIDTH(clog2_num_mux16),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(T),
.B(B[B_WIDTH-1-:clog2_num_mux16]),
.Y(Y));
end
endgenerate
endmodule
(* techmap_celltype = "$__XILINX_SHIFTX" *)
module _90__XILINX_SHIFTX (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
endmodule
module \$_MUX_ (A, B, S, Y);
input A, B, S;
output Y;
generate
if (`MIN_MUX_INPUTS == 2)
\$__XILINX_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(2), .B_WIDTH(1), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({B,A}), .B(S), .Y(Y));
else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
module \$_MUX4_ (A, B, C, D, S, T, Y);
input A, B, C, D, S, T;
output Y;
\$__XILINX_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({D,C,B,A}), .B({T,S}), .Y(Y));
endmodule
module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
input A, B, C, D, E, F, G, H, S, T, U;
output Y;
\$__XILINX_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
endmodule
module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
output Y;
\$__XILINX_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
endmodule
`endif
module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
output O;
input I0, I1, I2, I3, S0, S1;
wire T0, T1;
parameter _TECHMAP_BITS_CONNMAP_ = 0;
parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
parameter _TECHMAP_CONSTMSK_S0_ = 0;
parameter _TECHMAP_CONSTVAL_S0_ = 0;
parameter _TECHMAP_CONSTMSK_S1_ = 0;
parameter _TECHMAP_CONSTVAL_S1_ = 0;
if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
assign T0 = I1;
else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
assign T0 = I0;
else
MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
assign T1 = I3;
else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
assign T1 = I2;
else
MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
assign O = T1;
else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
assign O = T0;
else
MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
endmodule
module \$__XILINX_TINOUTPAD (input I, OE, output O, inout IO);
IOBUF _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE), .IO(IO));
endmodule
module \$__XILINX_TOUTPAD (input I, OE, output O);
OBUFT _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE));
endmodule
|
/*
* File: pippo_operandmuxes.v
* Project: pippo
* Designer: fang@ali
* Mainteiner: fang@ali
* Checker:
* Assigner:
* Description:
* Mux.A:
* input: rf_a, wb_fwd
* output: bus a (alu, mac, lsu)
* Mux.B:
* input: rf_b, imm, wb_fwd
* output: bus b (alu, mac, lsu, sprs(dat_i), except(datain))
*
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module pippo_operandmuxes(
rf_dataa, rf_datab, wb_fwd, imm,
sel_a, sel_b,
bus_a, bus_b
);
parameter width = `OPERAND_WIDTH;
//
// I/O
//
input [width-1:0] rf_dataa;
input [width-1:0] rf_datab;
input [width-1:0] wb_fwd;
input [width-1:0] imm;
input [`OPSEL_WIDTH-1:0] sel_a;
input [`OPSEL_WIDTH-1:0] sel_b;
output [width-1:0] bus_a;
output [width-1:0] bus_b;
//
// Internal wires and regs
//
reg [width-1:0] bus_a;
reg [width-1:0] bus_b;
//
// Multiplexer for operand bus A
// source: rf_dataa, wb_fwd
//
always @(wb_fwd or rf_dataa or sel_a) begin
`ifdef pippo_ADDITIONAL_SYNOPSYS_DIRECTIVES
casex (sel_a) // synopsys parallel_case infer_mux
`else
casex (sel_a) // synopsys parallel_case
`endif
`OPSEL_WBFWD:
bus_a = wb_fwd;
`OPSEL_RF:
bus_a = rf_dataa;
default:
bus_a = rf_dataa;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("%t: WARNING: OperandMux enter default case %h", $time);
// synopsys translate_on
`endif
endcase
end
//
// Multiplexer for operand bus B
// source: imm, rf_datab, wb_fwd
//
always @(imm or wb_fwd or rf_datab or sel_b) begin
`ifdef pippo_ADDITIONAL_SYNOPSYS_DIRECTIVES
casex (sel_b) // synopsys parallel_case infer_mux
`else
casex (sel_b) // synopsys parallel_case
`endif
`OPSEL_IMM:
bus_b = imm;
`OPSEL_WBFWD:
bus_b = wb_fwd;
`OPSEL_RF:
bus_b = rf_datab;
default:
bus_b = rf_datab;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("%t: WARNING: OperandMux enter default case %h", $time);
// synopsys translate_on
`endif
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKBUF_SYMBOL_V
`define SKY130_FD_SC_MS__CLKBUF_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKBUF_SYMBOL_V
|
// ***************************************************************************
// $Header: /var/lib/cvs/dncvs/FPGA/dini/fifo/fifo_addr.v,v 1.38 2015/04/30 00:38:34 bpoladian Exp $
// ***************************************************************************
// $Log: fifo_addr.v,v $
// Revision 1.38 2015/04/30 00:38:34 bpoladian
// When not generating read or write counts, keep overriding always block hidden from synthesis for ISE compatibility.
//
// Revision 1.37 2015/03/12 00:18:45 bpoladian
// Added define to not include overflow check.
//
// Revision 1.36 2015/03/12 00:13:24 bpoladian
// Drive almostfull to 0 in synthesis when not generating signal.
//
// Revision 1.35 2015/03/11 23:50:21 bpoladian
// Drive counts to 0 in synthesis when not enabling them.
//
// Revision 1.34 2014/12/04 01:17:34 bpoladian
// Commented out assignment of unused register b/c of optimization error in ISE.
//
// Revision 1.33 2014/11/11 05:35:45 bpoladian
// Prevent declaration of registers with async_reg attribute when those registers will not be used.
//
// Revision 1.32 2014/10/29 20:03:15 neal
// Fixed some bit-width issues.
//
// Revision 1.31 2014/09/02 21:51:45 neal
// Added an option to allow selectram FIFOs have quicker data output when empty.
//
// Revision 1.30 2014/08/25 23:59:26 neal
// Reduced simulation collision warnings.
//
// Revision 1.29 2014/08/24 00:42:45 neal
// Made infer_blkram instances do an extra write and read before the first valid one.
//
// Revision 1.28 2014/08/13 15:34:11 neal
// Don't read_en the ram until after the write has been completed.
//
// Revision 1.27 2014/08/07 05:00:40 neal
// Removed a comment.
//
// Revision 1.26 2014/07/18 18:10:58 neal
// Added a check for reasonable almost full limits.
//
// Revision 1.25 2014/07/18 17:08:10 neal
// Added an almostfull check.
//
// Revision 1.24 2014/07/17 22:00:37 neal
// Added Vivado constraints for ASYNC_REG.
//
// Revision 1.23 2014/07/10 03:05:02 claudiug
// added synthesis translate_off/on around simulation block
//
// Revision 1.22 2014/07/02 12:54:39 neal
// Disabled some of the extra checksum checks (to make it smaller).
//
// Revision 1.21 2014/07/01 19:18:45 neal
// Added checksums to wr_din and rd_dout with a sticky error bit that can be read back.
//
// Revision 1.20 2014/05/19 16:56:59 neal
// Added a parameter to remove some safety logic to increase the clock rate.
//
// Revision 1.19 2014/05/09 20:43:10 bpoladian
// Added simulation check for ONECLOCK parameter.
//
// Revision 1.18 2013/12/19 00:05:07 bpoladian
// Updated value of syn_preserve to avoid warning.
//
// Revision 1.17 2013/01/23 21:22:29 claudiug
// removed timescale declaration from all fifo_ files
//
// Revision 1.16 2013/01/07 19:55:57 neal
// Timing closure changes.
// Added a write and read data checksum (for logic analyzer use).
// Added optional clobbering of output data when not reading (simulation only).
//
// Revision 1.15 2012/12/06 20:23:27 claudiug
// added ifndef so that iverilog simulation works
//
// Revision 1.14 2012/10/04 19:57:32 bpoladian
// Added overflow bit that doesn't leave this module - for internal debugger purposes only.
//
// Revision 1.13 2012/06/28 17:44:49 neal
// Added a simulation initial value.
//
// Revision 1.12 2012/06/19 23:30:07 neal
// Resync'd reset to the correct clock domain.
//
// Revision 1.11 2012/04/24 17:36:28 bpoladian
// Changed synthesis ifdefs to translate directives.
//
// Revision 1.10 2011/12/21 19:46:26 bpoladian
// Don't synthesize count assignments to X w/ empty sensitivity lists.
//
// Revision 1.9 2011/12/05 22:16:04 neal
// Fixed toe_interrupt.
// Reduced toe ram utilization.
// Allowed digitfinder to have some constant input ports (selectable by parameter).
// Changed some brams to be single bram with byte write enables.
// Allowed some FIFO ports to not be generated (xst warnings).
//
// Revision 1.8 2011/09/29 20:25:26 neal
// Fixed a synthesis warning.
//
// Revision 1.7 2011/09/29 20:05:01 neal
// Fixed some synthesis warnings.
//
// Revision 1.6 2011/09/14 01:02:08 bpoladian
// Changed asynchronous always blocks into assign statements.
//
// Revision 1.5 2010/11/16 03:12:15 bpoladian
// Added read enable port for blockram.
//
// Revision 1.4 2010/10/05 22:12:51 bpoladian
// Added syn_keep to gray counter registers.
//
// Revision 1.3 2008/04/11 01:38:02 bpoladian
// Ran dos2unix. Removed comments on `else and `endif lines.
//
// Revision 1.2 2007/08/16 22:45:11 jperry
// Removed #1 to assignments, because it made it a blocking statement and was messing up simulation.
// We may need to add something like this again if we ever use Silos to simulate this file.
//
// Revision 1.1 2007/06/13 17:54:39 jperry
// copied from timelogic area. Not sure where this stuff will go in the end.
//
// Revision 1.11 2007/04/25 14:15:15 neal
// Removed the ifndef lines because Silos wouldn't accept them.
//
// Revision 1.10 2007/04/24 18:10:22 neal
// ifdef'd out the $display statements during synthesis.
//
// Revision 1.9 2007/04/23 20:37:21 neal
// Removed a "$stop;" because Silos crashes.
//
// Revision 1.8 2007/04/13 22:59:45 neal
// Added simulation error messages for invalid control signals to the FIFO.
//
// Revision 1.7 2007/03/24 01:22:00 neal
// Fixed some infinite loops with Silos simulator.
//
// Revision 1.6 2007/03/06 16:03:59 neal
// Made the fifo able to be synchronous to 1 clock domain to make it smaller and faster.
//
// Revision 1.5 2007/02/20 18:46:49 neal
// Fixed a mistake with the empty flag.
//
// Revision 1.4 2007/02/20 18:25:47 neal
// Fixed the FIFO controls so that it behaves in the proper manner.
// Cleaned up the code, and removed some duplicate registers.
// Decreased the fan-out on rd_en and wr_en.
// Made rd_en only control a single logic delay before any FF to improve timing.
// Fixed the empty_count and full_count outputs so that they are accurate and are relative to the correct empty/full-ness of the FIFO (instead of both being related to empty).
//
// Revision 1.3 2007/02/11 01:06:15 neal
// Made the blast design meet 100 Mhz timing.
//
// Revision 1.2 2007/02/08 18:17:20 neal
// Made the files get through Silos compilation.
//
// Revision 1.1 2007/02/05 17:11:30 jperry
// initial async FIFO files. Copied, modified from dn_fpgacode/FIFO. This may be cleaned up later.
//
// ***************************************************************************
`ifdef INCL_FIFO_ADDR
`else
`define INCL_FIFO_ADDR
// DEFINE "BETTER_TIMING" TO MAKE IT 4 CLOCK CYCLES FROM wr_en -> EMPTY_FLAG AND rd_en -> FULL_FLAG
// THIS WILL MAKE THE FIFO RUN AT MUCH HIGHER SPEEDS BY SPLITTING GREY-CODE LOGIC ACROSS 2 CLOCK CYCLES
// IF NOT DEFINED, IT IS 3 CLOCK CYCLES FROM wr_en -> empty FLAG AND rd_en -> FULL_FLAG
`include "dini/misc/reset_resync.v"
`define BETTER_TIMING
module fifo_addr
(
wr_clk,
wr_en,
wr_addr,
wr_en_ram,
wr_full,
wr_almost_full,
wr_full_count, // amount can write until full
rd_clk,
rd_en,
rd_addr,
rd_en_ram,
rd_empty,
rd_empty_count, // amount can read until empty
fifo_reset
);
// removed CNTR_W, because counters will be 1 bit more than addresses
parameter ADDR_W = 5; // number of bits wide for address
parameter ALMOSTFULL_LIMIT = 4; // number of entries left before almost full active
parameter DELAY_READ = 0; // Set to 1 when using blockram (1 clock delay to
// get data back), set to 0 when using selectram
parameter ONECLOCK = 1'b0; // set to 1 to get rid of resync logic.
parameter GEN_RDCOUNT = 1;
parameter GEN_WRCOUNT = 1;
parameter GEN_WRALMOSTFULL = 1;
parameter IGNORE_FULL_WR = 1'b0; // set to 1 to allow WR to go through when FULL is asserted (breaks the FIFO, but allows much higher clock rates). WARNING: setting this parameter can make the FIFO misbehave
parameter IGNORE_EMPTY_RD = 1'b0; // set to 1 to allow RD to go through when EMPTY is asserted (breaks the FIFO, but allows much higher clock rates). WARNING: setting this parameter can make the FIFO misbehave
parameter FAST_WR_TO_RD = 1'b0; // set to 1 to allow RD the following clk after WR
input wr_clk;
input wr_en;
output [ADDR_W-1:0] wr_addr;
output wr_en_ram;
output wr_full;
output wr_almost_full;
output [ADDR_W:0] wr_full_count; // amount can write until full
input rd_clk;
input rd_en;
output [ADDR_W-1:0] rd_addr;
output rd_empty;
output [ADDR_W:0] rd_empty_count; // amount can read until empty
output rd_en_ram;
input fifo_reset;
// **********************************************************
// Reg and wire declarations
// **********************************************************
reg allempty_rdclk;
reg allfull_wrclk;
reg wr_almost_full;
wire read_allow, write_allow;
reg [ADDR_W:0] read_address;
wire [ADDR_W:0] read_address_plus1 /* synthesis syn_keep=1 */;
reg [ADDR_W:0] read_addrgray /* synthesis syn_keep=1 */;
reg [ADDR_W:0] write_address;
reg [ADDR_W:0] write_addrgray /* synthesis syn_keep=1 */;
// Calculation of empty count
reg [ADDR_W:0] write_address_r;
wire write_equals_read_noread /* synthesis syn_keep=1 */;
wire write_equals_read_withread /* synthesis syn_keep=1 */;
wire [ADDR_W:0] write_minus_read_noread /* synthesis syn_keep=1 */;
wire [ADDR_W:0] write_minus_read_withread /* synthesis syn_keep=1 */;
reg [ADDR_W:0] rd_empty_count;
// Calculation of full count
reg [ADDR_W:0] read_address_w;
wire [ADDR_W:0] read_minus_write;
reg [ADDR_W:0] wr_full_count;
genvar ra_cnt;
//reg wr_en_ram_d;
// **********************************************************
// output assignments
// **********************************************************
reg pre_first_read;
wire reset_rdclk;
always @(posedge rd_clk or posedge reset_rdclk) begin
if (reset_rdclk) begin
pre_first_read <= 1'b1;
end else begin
//if (read_allow)
pre_first_read <= 1'b0;
end
end
assign wr_full = allfull_wrclk;
assign rd_empty = allempty_rdclk;
assign wr_en_ram = write_allow | fifo_reset; // 7series rams have reset assertion issues for the first read/write, so do a bunch of extra writes.
//assign rd_en_ram = (read_allow ? (~write_equals_read_withread) : (allempty_rdclk & (~write_equals_read_noread) )) | reset_rdclk; // 7series RAMS have reset assertion issues for the first read/write, so do a bunch of extra reads.
assign rd_en_ram = (read_allow ? (~write_equals_read_withread) : (allempty_rdclk & (~write_equals_read_noread) )) | ((~reset_rdclk) & pre_first_read) | (wr_en & FAST_WR_TO_RD[0] & ONECLOCK[0]); // 7series RAMS have reset assertion issues for the first read/write, so do a bunch of extra reads.
//always @ (posedge wr_clk or posedge fifo_reset) begin
//if (fifo_reset) begin
//wr_en_ram_d <= 'b0;
//end else begin
//wr_en_ram_d <= wr_en_ram;
//end
//end
// when blockram, output next address 1 clock cycle early
// to compensate for 1 clock cycle out of block ram
assign read_address_plus1 = read_address + 1'b1;
assign rd_addr = (DELAY_READ ? (read_allow ? read_address_plus1[ADDR_W-1:0] : read_address[ADDR_W-1:0] ) : read_address[ADDR_W-1:0]);
assign wr_addr = write_address[ADDR_W-1:0];
/**********************************************************\
* *
* Generation of Read address pointers. Several Gray- *
* code addresses are pipelined; each calculates one *
* particular level of Almost Full or Almost Empty. At *
* each end of the pipeline is a binary counter from *
* which the Gray-code values are calculated. The Gray- *
* code registers' initial values are important, as they *
* need to be in proper Gray-code sequence for the Full, *
* Empty, et al flags to work properly. *
* *
* Gray-code addresses are used so that the registered *
* Full and Empty flags are always clean, and are never *
* in a spurious state brought about by the Read and *
* Write clocks' asynchronicity. In the worst-case *
* scenario, Full and Empty would simply stay active one *
* cycle longer, and they would not generate an error or *
* give false values. *
* *
\**********************************************************/
`ifndef NO_OVERFLOW_CHECK
(* dont_touch = "true", keep = "true" *) reg overflow;
always @ (posedge wr_clk or posedge fifo_reset) begin
if(fifo_reset) begin
overflow <= 'b0;
end else begin
if(wr_en & wr_full) begin
overflow <= 'b1;
/* synthesis translate_off*/
$display("WARNING: %m: writing to a full fifo: time=%t",$time);
if (IGNORE_FULL_WR) begin
$display("ERROR: %m: Writing to a FULL FIFO: IGNORE_FULL_WR=1, FULL=1, WR=1, time=%t",$time);
$stop;
end
/* synthesis translate_on*/
end
end
end
`endif
integer rg_cnt;
reset_resync i_rst (
.clk_in(wr_clk),
.rst_in(fifo_reset),
.clk_out(rd_clk),
.rst_out(reset_rdclk)
);
always @(posedge rd_clk or posedge reset_rdclk) begin
if (reset_rdclk) begin
read_address <= 0;
read_addrgray <= 0;
end else begin
/* synthesis translate_off*/
if ( (rd_en!==1'b0) && (rd_en!==1'b1) ) begin
$display("ERROR: rd_en=%x not valid: %m time=%t",rd_en,$time);
$stop;
end
/* synthesis translate_on*/
if (read_allow)
read_address <= read_address_plus1;
read_addrgray[ADDR_W] <= read_address[ADDR_W];
for (rg_cnt=0;rg_cnt<ADDR_W;rg_cnt=rg_cnt+1)
read_addrgray[rg_cnt] <= read_address[rg_cnt+1] ^ read_address[rg_cnt];
/* synthesis translate_off*/
if ((IGNORE_EMPTY_RD!=0) && (rd_en==1'b1) && (allempty_rdclk==1'b1)) begin
$display("ERROR: %m: Reading from an EMPTY FIFO: IGNORE_EMPTY_RD=1, EMPTY=1, RD=1, time=%t",$time);
$stop;
end
/* synthesis translate_on*/
end
end
/**********************************************************\
* *
* Generation of Write address pointers. Similar to read *
* pointer generation above, except for names. Also, the *
* write counters only advance - there is no "write *
* backup" capability. Because of this, a binary counter *
* is only present at one end of the address pipeline. *
* *
\**********************************************************/
integer wg_cnt;
always @(posedge wr_clk or posedge fifo_reset) begin
if (fifo_reset) begin
write_address <= 'b0;
write_addrgray <= 0;
end else begin
/* synthesis translate_off*/
if ( ($time>0) && (wr_en!==1'b0) && (wr_en!==1'b1) ) begin
$display("ERROR: wr_en=%x not valid: %m time=%t",wr_en,$time);
//$stop;
end
/* synthesis translate_on*/
if (write_allow)
write_address <= write_address + 1'b1;
write_addrgray[ADDR_W] <= write_address[ADDR_W];
for(wg_cnt=0;wg_cnt<ADDR_W;wg_cnt=wg_cnt+1)
write_addrgray[wg_cnt] <= write_address[wg_cnt+1] ^ write_address[wg_cnt];
end
end
/**********************************************************\
* *
* Allow flags determine whether FIFO control logic can *
* operate. If read_allow is driven high, and the FIFO *
* is not Empty, then Reads are allowed. Similarly, if *
* the write_allow signal is high, and the FIFO is not *
* Full, then Writes are allowed. *
* *
\**********************************************************/
assign read_allow = rd_en & (IGNORE_EMPTY_RD[0] | (~allempty_rdclk) | (wr_en & FAST_WR_TO_RD[0] & ONECLOCK[0]));
assign write_allow = wr_en & (IGNORE_FULL_WR[0] | (~allfull_wrclk));
/**********************************************************\
* *
* Empty-count generation occurs in four stages. The *
* first two stages use the positive edge
* of the read clock to provide metastable recovery of *
* the Gray-code write address. The third stage converts *
* this address back to binary, and the final stage does *
* the subtraction between the read address and the write *
* address. *
* *
* In the final stage, read_allow is inverted and used as *
* the borrow input into the subtraction carry chain. *
* This adjusts the empty count down by 1, to reflect the *
* FIFO data about to be read. *
* *
\**********************************************************/
generate
if(ONECLOCK==0) begin : gen_write_address_async
// We don't want to declare ASYNC_REGs that are unused because they will act as a keep in synthesis and a don't touch in place/route
(* ASYNC_REG = "TRUE" *) reg [ADDR_W:0] write_addrgray_m /* synthesis syn_keep=1 */;
(* ASYNC_REG = "TRUE" *) reg [ADDR_W:0] write_addrgray_r /* synthesis syn_keep=1 */;
always @(posedge rd_clk or posedge reset_rdclk) begin
if (reset_rdclk) begin
write_addrgray_m <= 'b0;
write_addrgray_r <= 'b0;
end else begin
write_addrgray_m <= write_addrgray;
write_addrgray_r <= write_addrgray_m;
end
end
// Gray-code conversion to binary
genvar wa_cnt;
// ADDS 1 CLOCK CYCLE DELAY THROUGH FIFO TO EMPTY FLAG, SPLITTING LOGIC ACROSS TWO CLOCKS
wire [ADDR_W:0] write_address_c;
assign write_address_c[ADDR_W] = write_addrgray_r[ADDR_W];
for (wa_cnt=0;wa_cnt <ADDR_W;wa_cnt=wa_cnt+1) begin:gen_wr_addr_c
assign write_address_c[wa_cnt] = ^(write_addrgray_r[ADDR_W:0] >> wa_cnt);
end
`ifdef BETTER_TIMING
always @(posedge rd_clk or posedge reset_rdclk)
if (reset_rdclk)
write_address_r <= 0;
else begin
`else
// CUTS OUT 1 CLOCK CYCLE DELAY THROUGH FIFO TO EMPTY FLAG, BUT MORE LOGIC IN THIS CLOCK CYCLE
always @(*) begin
`endif
write_address_r <= write_address_c;
end
//end else begin : gen_write_address_sync
// // We don't use this register when synchronous
// always @ (*)
// write_address_r <= 'bx;
end
endgenerate
always @(posedge rd_clk or posedge reset_rdclk) begin
if (reset_rdclk) begin
if (GEN_RDCOUNT == 1)
rd_empty_count <= 0;
allempty_rdclk <= 1;
end else begin
if (GEN_RDCOUNT == 1)
rd_empty_count <= (read_allow ? write_minus_read_withread : write_minus_read_noread );
allempty_rdclk <= (read_allow ? (write_minus_read_withread==0) : write_equals_read_noread) & (~(wr_en & FAST_WR_TO_RD[0] & ONECLOCK[0]));
end
end
/* synthesis translate_off*/
always @(*) begin
if (GEN_RDCOUNT == 0) begin
rd_empty_count <= 'b0;
`ifndef IVERILOG_SIM
rd_empty_count <= {ADDR_W+1{1'bx}};
`endif
end
end
/* synthesis translate_on*/
// **********************************************************
// Check that ONECLOCK is set correctly
// **********************************************************
// synthesis translate_off
initial begin
if (ALMOSTFULL_LIMIT+1 > (1 << ADDR_W)) begin
$display("ERROR: %m ALMOSTFULL_LIMIT set larger than FIFO");
$stop;
end
if ((ONECLOCK==0) && (GEN_WRALMOSTFULL!=0) && (ALMOSTFULL_LIMIT+12 > (1 << ADDR_W)) && (ALMOSTFULL_LIMIT*2 > (1 << ADDR_W)) ) begin
$display("WARNING: %m ALMOSTFULL_LIMIT=%d should be at least 12 less than fifo depth=%d for ASYNC FIFOs",ALMOSTFULL_LIMIT,(1<<ADDR_W));
$stop;
end
wait(fifo_reset===1'b0);
repeat(100) @(posedge rd_clk);
repeat(100) begin
@(posedge rd_clk);
if(ONECLOCK && (rd_clk!=wr_clk)) begin
$display("%m: ERROR: ONECLOCK parameter is not set correctly; async domains detected!");
$stop;
end
@(posedge wr_clk);
if(ONECLOCK && (rd_clk!=wr_clk)) begin
$display("%m: ERROR: ONECLOCK parameter is not set correctly; async domains detected!");
$stop;
end
end
end
// synthesis translate_on
// Pre-calculate the emptiness with and without read, and mux in
// read as the very last stage.
assign write_minus_read_noread = ((ONECLOCK ? write_address : write_address_r ) - read_address);
assign write_equals_read_noread = ((ONECLOCK ? write_address : write_address_r ) == read_address);
assign write_minus_read_withread = ((ONECLOCK ? write_address : write_address_r ) - read_address - 1'b1);
assign write_equals_read_withread = (write_minus_read_withread==0);
/**********************************************************\
* *
* Full-count generation also occurs in four stages. The *
* subtraction, in this case, is read minus write. *
* *
* In the final stage, write_allow is inverted and used *
* as the borrow input into the subtraction carry chain. *
* This adjusts the full count down by 1, to reflect the *
* FIFO data about to be written. *
* *
\**********************************************************/
generate
if(ONECLOCK==0) begin : gen_read_address_async
// We don't want to declare ASYNC_REGs that are unused because they will act as a keep in synthesis and a don't touch in place/route
(* ASYNC_REG = "TRUE" *) reg [ADDR_W:0] read_addrgray_m /* synthesis syn_keep=1 */;
(* ASYNC_REG = "TRUE" *) reg [ADDR_W:0] read_addrgray_md /* synthesis syn_keep=1 */;
wire [ADDR_W:0] read_address_c;
always @(posedge wr_clk or posedge fifo_reset) begin
if (fifo_reset) begin
read_addrgray_m <= 'b0;
read_addrgray_md <= 'b0;
end else begin
read_addrgray_m <= read_addrgray;
read_addrgray_md <= read_addrgray_m;
end
end
// Gray-code conversion to binary
// ADDS 1 CLOCK CYCLE DELAY THROUGH FIFO TO FULL FLAG, SPLITTING LOGIC ACROSS TWO CLOCKS
assign read_address_c[ADDR_W] = read_addrgray_md[ADDR_W];
for(ra_cnt=0;ra_cnt<ADDR_W;ra_cnt=ra_cnt+1) begin:gen_rd_addr_c
assign read_address_c[ra_cnt] = (^(read_addrgray_md[ADDR_W:0]>>ra_cnt) );
end
`ifdef BETTER_TIMING
always @(posedge wr_clk or posedge fifo_reset)
if (fifo_reset) begin
read_address_w <= 0;
end else begin
`else
// CUTS OUT 1 CLOCK CYCLE DELAY THROUGH FIFO TO FULL FLAG, BUT MORE LOGIC IN THIS CLOCK CYCLE
always @(*) begin
`endif
read_address_w <= read_address_c;
end
//end else begin : gen_read_address_sync
// // We don't use this register when synchronous
// always @(*)
// read_address_w <= 'bx;
end
endgenerate
// FULL COUNT
always @(posedge wr_clk or posedge fifo_reset) begin
if (fifo_reset) begin
if (GEN_WRCOUNT==1) begin
wr_full_count <= 0;
wr_full_count[ADDR_W] <= 1;
end
if (GEN_WRALMOSTFULL==1) begin
wr_almost_full <= 1'b0;
end
allfull_wrclk <= 1'b0;
end else begin
if (GEN_WRCOUNT==1) begin
wr_full_count <= read_minus_write;
end
if (GEN_WRALMOSTFULL==1) begin
wr_almost_full <= (read_minus_write < ALMOSTFULL_LIMIT);
end
allfull_wrclk <= (read_minus_write == 0);
end
end
/* synthesis translate_off*/
always @(*) begin
if (GEN_WRCOUNT == 0) begin
wr_full_count <= 'b0;
`ifndef IVERILOG_SIM
wr_full_count <= {ADDR_W+1{1'bx}};
`endif
end
if (GEN_WRALMOSTFULL == 0) begin
wr_almost_full <= 'b0;
`ifndef IVERILOG_SIM
wr_almost_full <= 'bx;
`endif
end
end
/* synthesis translate_on*/
assign read_minus_write = ((ONECLOCK ? {~read_address[ADDR_W],read_address[ADDR_W-1:0]} : {~read_address_w[ADDR_W],read_address_w[ADDR_W-1:0]}) - write_address - {{(ADDR_W-1){1'b0}}, write_allow});
/* synthesis translate_off*/
always @(posedge wr_clk)
if (~fifo_reset) begin
if ( wr_en & wr_full )
$display("Warning: Writing to a full fifo %m: time=%t",$time);
end
/* synthesis translate_on*/
/*
always @(posedge rd_clk)
if (~reset_rdclk) begin
if ( rd_en & rd_empty )
$display("Warning: Reading from an empty fifo %m: time=%t",$time);
end
*/
endmodule
`endif
|
`timescale 1ns/1ns
module menc_sincos
(input c,
input [13:0] menc,
input [10:0] offset,
input [7:0] poles,
output [31:0] sin,
output [31:0] cos);
wire toggle;
r toggle_r(.c(c), .en(1'b1), .rst(1'b0), .d(~toggle), .q(toggle));
wire [10:0] sin_addr, cos_addr;
d1 #(11) sin_addr_r(.c(c), .d(menc + offset), .q(sin_addr));
d1 #(11) cos_addr_r(.c(c), .d(menc + offset + 11'd512), .q(cos_addr));
wire [10:0] table_addr = toggle ? sin_addr : cos_addr;
wire [31:0] table_q;
sine_table_11bit_float32 table_inst
(.c(c), .angle(table_addr), .sine(table_q));
r #(32) sin_r(.c(c), .en(~toggle), .rst(1'b0), .d(~(~table_q)), .q(sin));
r #(32) cos_r(.c(c), .en( toggle), .rst(1'b0), .d(~(~table_q)), .q(cos));
endmodule
////////////////////////////////////////////////////////////////
`ifdef test_menc_sincos
module menc_sincos_tb();
wire c;
sim_clk #(125) clk_125(.clk(c));
reg [10:0] offset;
reg [10:0] menc;
wire [31:0] sin, cos;
menc_sincos dut(.*);
initial begin
$dumpfile("menc_sincos.lxt");
$dumpvars();
offset = 11'h0;
menc = 11'h50;
$display("testing...");
wait(c);
wait(~c);
#1000 $finish();
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211AI_4_V
`define SKY130_FD_SC_MS__O211AI_4_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211ai_4 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211AI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLCLKP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLCLKP_PP_SYMBOL_V
/**
* dlclkp: Clock gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLCLKP_PP_SYMBOL_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: Audio_PLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Audio_PLL (
areset,
inclk0,
c0);
input areset;
input inclk0;
output c0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 135,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 92,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.400000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.40000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "Audio_PLL.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "135"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "92"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_PLL.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_PLL.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_PLL.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_PLL.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_PLL.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_PLL_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_PLL_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_PLL_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Audio_PLL_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file I_cache.v when simulating
// the core, I_cache. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module I_cache(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [0 : 0] wea;
input [6 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V4_2 #(
.C_ADDRA_WIDTH(7),
.C_ADDRB_WIDTH(7),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(128),
.C_READ_DEPTH_B(128),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(128),
.C_WRITE_DEPTH_B(128),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of I_cache is "black_box"
endmodule
|
(** * Prop_J: 命題と根拠 *)
(* $Date: 2011-06-27 09:22:51 -0400 (Mon, 27 Jun 2011) $ *)
(** "アルゴリズムは計算可能な証明である。"(Robert Harper) *)
Require Export Poly_J.
(* ##################################################### *)
(* ##################################################### *)
(** * 命題によるプログラミング *)
(* _Note to readers_: Some of the concepts in this chapter may
seem quite abstract on a first encounter. We've included a _lot_
of exercises, most of which should be quite approachable even if
you're still working on understanding the details of the text.
Try to work as many of them as you can, especially the one-starred
exercises. *)
(** 読者への注意: この章で紹介するコンセプトは、初めて見た時には抽象的すぎるように感じられるかもしれません。
たくさんの練習問題を用意しておいたので、テキストの詳細を理解する途中であっても大部分は解けるはずです。
できるかぎり多くの問題、特に★の問題には重点的に挑戦するようにしてください。 *)
(* So far, the only statements we have been able to state and
prove have been in the form of _equalities_. However, the
language of mathematical statements and proofs is much richer than
this! In this chapter we will take a much closer and more
fundamental look at the sorts of mathematical statements
(_propositions_) we can make in Coq, and how we go about proving
them by providing logical _evidence_. *)
(** これまで宣言したり証明した文は等式の形をしたものだけでした。
しかし、数学で用いられる文や証明にはもっと豊かな表現力があります。
この章では Coq で作れる数学的な文（命題; _proposition_ ）の種類と、その証明を「根拠（ _evidence_ ）を与えること」でどのように進めていくか、もう少し詳しく、基本的な部分から見ていきましょう。
*)
(* A _proposition_ is a statement expressing a factual claim,
like "two plus two equals four." In Coq, propositions are written
as expressions of type [Prop]. Although we haven't mentioned it
explicitly, we have already seen numerous examples. *)
(** 命題（ _proposition_ ）は、"2足す2は4と等しい"のような事実に基づく主張を表現するための文です。
Coq において命題は [Prop] 型の式として書かれます。
これまであまりそれについて明示的に触れてはきませんでしたが、皆さんはすでに多くの例を見てきています。 *)
Check (2 + 2 = 4).
(* ===> 2 + 2 = 4 : Prop *)
Check (ble_nat 3 2 = false).
(* ===> ble_nat 3 2 = false : Prop *)
(* Both provable and unprovable claims are perfectly good
propositions. Simply _being_ a proposition is one thing; being
_provable_ is something else! *)
(** 証明可能な主張も証明不能な主張も、どちらも完全な命題であると言えます。
しかし単に命題であるということと、証明可能であるということは別ものです！ *)
Check (2 + 2 = 5).
(* ===> 2 + 2 = 5 : Prop *)
(** [2 + 2 = 4] も [2 + 2 = 5] も [Prop] の型をもった妥当な式です。 *)
(* We've seen one way that propositions can be used in Coq: in
[Theorem] (and [Lemma] and [Example]) declarations. *)
(** これまで Coq の中で命題を使う方法は1つしか見ていません。 [Theorem]（あるいは [Lemma]、[Example]）の宣言の中でだけです。 *)
Theorem plus_2_2_is_4 :
2 + 2 = 4.
Proof. reflexivity. Qed.
(* But they can be used in many other ways. For example, we
can give a name to a proposition using a [Definition], just as we
have given names to expressions of other sorts (numbers,
functions, types, type functions, ...). *)
(** しかし命題にはもっといろいろな使い方があります。
例えば、他の種類の式（数字、関数、型、型関数など）と同様に、[Definition] を使うことで命題に名前を与えることができます。 *)
Definition plus_fact : Prop := 2 + 2 = 4.
Check plus_fact.
(* ===> plus_fact : Prop *)
(* Now we can use this name in any situation where a proposition is
expected -- for example, as the claim in a [Theorem]
declaration. *)
(** こうすることで、命題が使える場所ならどこでも、例えば、[Theorem] 宣言内の主張などとして使うことができます。 *)
Theorem plus_fact_is_true :
plus_fact.
Proof. reflexivity. Qed.
(* So far, all the propositions we have seen are equality
propositions. We can also form new propositions out of old
ones. For example, given propositions [P] and [Q], we can form
the proposition "[P] implies [Q]." *)
(** ここまでに登場したすべての命題は等式の形をした命題でした。
それ以外にも新しい命題の形を作ることができます。
例えば、命題 [P] と [Q] が与えられば、" [P] ならば [Q] "という命題を作れます。
*)
Definition strange_prop1 : Prop :=
(2 + 2 = 5) -> (99 + 26 = 42).
(* Also, given a proposition [P] with a free variable [n], we can
form the proposition [forall n, P]. *)
(** また、自由変数[n]を含む命題 [P] が与えられれば、[forall n, P] という形の命題を作れます。 *)
Definition strange_prop2 :=
forall n, (ble_nat n 17 = true) -> (ble_nat n 99 = true).
(* Finally, we can define _parameterized propositions_. For
example, what does it mean to claim that "a number n is even"? We
have written a function that tests evenness, so one possible
definition of what it means to be even is "[n] is even iff [evenb
n = true]." *)
(** 最後に、パラメータ化された命題（_parameterized proposition_ ）の定義を紹介します。
例えば、"数nが偶数である"という主張はどのようになるでしょうか？
偶数を判定する関数は書いてあるので、偶数であるという定義は" [n] が偶数であることと [evenb n = true] は同値である"が考えられます。 *)
Definition even (n:nat) : Prop :=
evenb n = true.
(* This defines [even] as a _function_ that, when applied to a number
[n], _yields a proposition_ asserting that [n] is even. *)
(** これは [even] を関数として定義します。
この関数は数 [n] を適用されると、[n] が偶数であることを示す命題を返します。 *)
Check even.
(* ===> even : nat -> Prop *)
Check (even 4).
(* ===> even 4 : Prop *)
Check (even 3).
(* ===> even 3 : Prop *)
(* The type of [even], [nat->Prop], can be pronounced in three
ways: (1) "[even] is a _function_ from numbers to
propositions," (2) "[even] is a _family_ of propositions, indexed
by a number [n]," or (3) "[even] is a _property_ of numbers." *)
(** [even]の型 [nat -> Prop]は3つの意味を持っています。
(1) "[even]は数から命題への関数である。"
(2) "[even]は数[n]でインデックスされた命題の集りである"。
(3) "[even]は数の性質(_property_)である。" *)
(* Propositions -- including parameterized propositions -- are
first-class citizens in Coq. We can use them in other
definitions: *)
(** 命題（パラメータ化された命題も含む）はCoqにおける第一級（_first-class_）市民です。
このため、ほかの定義の中でこれらの命題を使うことができます。 *)
Definition even_n__even_SSn (n:nat) : Prop :=
(even n) -> (even (S (S n))).
(* We can define them to take multiple arguments... *)
(** 複数の引数を受け取るように定義することや.. *)
Definition between (n m o: nat) : Prop :=
andb (ble_nat n o) (ble_nat o m) = true.
(* ... and then partially apply them: *)
(** ...部分適用もできます。 *)
Definition teen : nat->Prop := between 13 19.
(* We can even pass propositions -- including parameterized
propositions -- as arguments to functions: *)
(** 他の関数に、引数として命題（パラメータ化された命題も含む）を渡すことすらできます。 *)
Definition true_for_zero (P:nat->Prop) : Prop :=
P 0.
Definition true_for_n__true_for_Sn (P:nat->Prop) (n:nat) : Prop :=
P n -> P (S n).
(* (Names of the form [x__y], with two underscores in a row, can be
read "[x] implies [y].") *)
(** 2つのアンダースコアを続けた [x__y] という形式の名前は、" [x] ならば [y] である"と読みます。 *)
(* Here are two more examples of passing parameterized
propositions as arguments to a function. The first makes the
claim that a whenever a proposition [P] is true for some natural
number [n'], it is also true by the successor of [n']: *)
(** パラメータ化された命題を引数として渡す関数をさらに2つ紹介します。
1つ目の関数は、ある自然数 [n'] について [P] が真ならば常に [n'] の次の数でも [P] が真であることを述べています。
*)
Definition preserved_by_S (P:nat->Prop) : Prop :=
forall n', P n' -> P (S n').
(* And this one simply claims that a proposition is true for
all natural numbers: *)
(** そして次の関数は、すべての自然数について与えられた命題が真であることを述べています。 *)
Definition true_for_all_numbers (P:nat->Prop) : Prop :=
forall n, P n.
(* We can put these pieces together to manually restate the
principle of induction for natural numbers. Given a parameterized
proposition [P], if [P] is true for [0], and [P (S n')] is true
whenever [P n'] is, then [P] is true for all natural numbers. *)
(** これらを一つにまとめることで、自然数に関する帰納法の原理を自分で再宣言できます。
パラメータ化された命題 [P] が与えられた場合、[0] について [P] が真であり、[P n'] が真のとき [P (S n')] が真であるならば、すべての自然数について [P] は真である。
*)
Definition our_nat_induction (P:nat->Prop) : Prop :=
(true_for_zero P) ->
(preserved_by_S P) ->
(true_for_all_numbers P).
(* * Evidence *)
(** * 根拠 *)
(* We've seen that well-formed expressions of type [Prop] can
embody both provable and unprovable propositions. Naturally,
we're particularly interested in the provable ones. When [P] is a
proposition and [e] is a proof of [P] -- i.e., [e] is evidence
that [P] is true -- we'll write "[e : P]." This overloading of
the "has type" or "inhabits" notation is not accidental: we'll see
that there is a fundamental and fruitful analogy between data
values inhabiting types and evidence "inhabiting" propositions. *)
(** [Prop]型として妥当な式には証明可能な命題と証明不能な命題の両方があることは既にお話ししました。
当然、証明可能なものの方に興味が向かいます。
[P] が命題であり [e] が [P] の証明である場合、すなわち [e] が「 [P] が真である」ということの根拠となっている場合、それを" [e : P] "と書くことができます。
"型を持っている"や"属している"を表わす記法と同じなのは決して偶然ではありません。
型に属する値と命題に"属する"根拠の間には根本的で有益な類似性があるのです。 *)
(* The next question is "what are proofs?" -- i.e., what sorts of
things would we be willing to accept as evidence that particular
propositions are true? *)
(** 次の疑問は"証明とはなにか？"です。
すなわち、ある命題が真であるという根拠として使えるものは、どのようなものでしょうか？ *)
(* ##################################################### *)
(* ** Inductively Defined Propositions *)
(** ** 帰納的に定義された命題 *)
(* The answer, of course, depends on the form of the
proposition -- evidence for implication propositions ([P->Q]) is
different from evidence for conjunctions ([P/\Q]), etc. In this
chapter and the next, we'll address a number of specific cases.
To begin with, consider _atomic_ propositions -- ones that aren't
built into the logic we're using, but are rather introduced to
model useful concepts in a particular domain. For example, having
defined a type [day] as we did in Basics.v, we might have some
concept in our minds about certain days, say the fact that
[saturday] and [sunday] are "good" ones. If we want to use Coq to
state and prove theorems involving good days, we need to begin by
telling it what we mean by "good" -- that is, we need to specify
what counts as as evidence that some day [d] is good (namely, that
[d] is either [saturday] or [sunday]. The following declaration
achieves this: *)
(** もちろん、その答は命題の形に依存します。
例えば、含意の命題 [P->Q] に対する根拠と連言の命題 [P/\Q] に対する根拠は異なります。
この章では以後、たくさんの具体的な例を示します。
まずは、不可分（ _atomic_ ）な命題を考えましょう。
それは私達が使っている論理にあらかじめ組み込まれているものはなく、特定のドメイン（領域）に有用な概念を導入するものです。
例えば、Basic_J.v で [day] 型を定義したので、[saturday] と [sunday] は"良い"日であるといったような、特定の日に対して何らかの概念を考えてみましょう。
良い日に関する定理を宣言し証明したい場合はまず、"良い"とはどういう意味かをCoqに教えなければなりません。
ある日 [d] が良い（すなわち [d] が [saturday] か [sunday] である）とする根拠として何を使うかを決める必要があります。
このためには次のように宣言します。 *)
Inductive good_day : day -> Prop :=
| gd_sat : good_day saturday
| gd_sun : good_day sunday.
(* The [Inductive] keyword means exactly the same thing whether
we are using it to define sets of data values (in the [Type]
world) or sets of evidence (in the [Prop] world). Consider the
parts of the definition above:
- The first line declares that [good_day] is a proposition indexed
by a day.
- The second line declares that the constructor [gd_sat] can be
taken as evidence for the assertion [good_day saturday].
- The third line declares that the constructor [gd_sun] can be
taken as evidence for the assertion [good_day sunday]. *)
(** [Inductive] キーワードは、「データ値の集合を定義する場合( [Type] の世界)」であっても「根拠の集合を定義する場合( [Prop] の世界)」であってもまったく同じ意味で使われます。
上記の定義の意味はそれぞれ次のようになっています:
- 最初の行は「 [good_day] は日によってインデックスされた命題であること」を宣言しています。
- 二行目は [gd_sat] コンストラクタを宣言しています。このコンストラクタは [good_day saturday] という主張の根拠として使えます。
- 三行目は [gd_sun] コンストラクタを宣言しています。このコンストラクタは [good_day sunday] という主張の根拠として使えます。
*)
(* That is, we're _defining_ what we mean by days being good by
saying "Saturday is good, sunday is good, and that's all." Then
someone can _prove_ that Sunday is good simply by observing that
we said it was when we defined what [good_day] meant. *)
(** 言い換えると、ある日が良いということを"土曜日は良い、日曜日は良い、それだけだ"と言うことで定義しています。
これによって、日曜日が良いということを証明したいときは、[good_day] の意味を定義したときにそう言っていたかを調べるだけで済みます。 *)
Theorem gds : good_day sunday.
Proof. apply gd_sun. Qed.
(* The constructor [gd_sun] is "primitive evidence" -- an _axiom_ --
justifying the claim that Sunday is good. *)
(** コンストラクタ [gd_sun] は、日曜日が良いという主張を正当化する"原始的（primitive）な根拠"、つまり公理です。*)
(* Similarly, we can define a proposition [day_before]
parameterized by _two_ days, together with axioms stating that
Monday comes before Tuesday, Tuesday before Wednesday, and so
on. *)
(** 同様に、月曜日は火曜日の前に来て、火曜日は水曜日の前に来て、...、ということを宣言する公理を、2つの日をパラメータとして取る命題 [day_before] として定義できます。*)
Inductive day_before : day -> day -> Prop :=
| db_tue : day_before tuesday monday
| db_wed : day_before wednesday tuesday
| db_thu : day_before thursday wednesday
| db_fri : day_before friday thursday
| db_sat : day_before saturday friday
| db_sun : day_before sunday saturday
| db_mon : day_before monday sunday.
(* The axioms that we introduce along with an inductively
defined proposition can also involve universal quantifiers. For
example, it is well known that every day is a fine day forsinging a song: *)
(** 帰納的な定義による命題で導入される公理では全称記号を使うこともできます。
例えば、「どの日だって歌いだしたくなるほど素敵な日だ」という事実については、
わざわざ説明する必要もないでしょう *)
Inductive fine_day_for_singing : day -> Prop :=
| fdfs_any : forall d:day, fine_day_for_singing d.
(* The line above declares that, if [d] is a day, then [fdfs_any d]
can be taken as evidence for [fine_day_for_singing d]. That is,
we can construct evidence that [d] is a [fine_day_for_singing]
by applying the constructor [fdfs_any] to [d].
In particular, Wednesday is a fine day for singing. *)
(** この行は、もし [d] が日ならば、[fdfs_any d] は [fine_day_for_singing d] の根拠として使えるということを宣言してます。
言い換えると、[d] が [fine_day_for_singing] であるという根拠を [fdfs_any] を [d] に適用することで作ることができます。
要するに、水曜日は「歌いだしたくなるほど素敵な日」だということです。
*)
Theorem fdfs_wed : fine_day_for_singing wednesday.
Proof. apply fdfs_any. Qed.
(* As always, the first line here can be read "I'm about to
show you some evidence for the proposition [fine_day_for_singing
wednesday], and I want to introduce the name [fdfs_wed] to refer
to that evidence later on." The second line then instructs Coq
how to assemble the evidence. *)
(** これも同じように、最初の行は"私は命題 [fine_day_for_singing wednesday] に対する根拠を示し、その根拠をあとで参照するために [fdfs_wed] という名前を導入しようと思っている"と解釈できます。
二行目は、Coqにその根拠をどのように組み立てるかを示しています。 *)
(* ##################################################### *)
(* ** Proof Objects *)
(** ** 証明オブジェクト *)
(* There's another -- more primitive -- way to accomplish the
same thing: we can use a [Definition] whose left-hand side is the
name we're introducing and whose right-hand side is the evidence
_itself_, rather than a script for how to build it. *)
(** 同じことができる、もっと原始的な方法もあります。
[Definiton] の左辺を導入しようとしている名前にし、右辺を根拠の構築方法ではなく、根拠そのものにすればいいのです。 *)
Definition fdfs_wed' : fine_day_for_singing wednesday :=
fdfs_any wednesday.
Check fdfs_wed.
Check fdfs_wed'.
(* The expression [fdfs_any wednesday] can be thought of as
instantiating the parameterized axiom [fdfs_any] with the specific
argument [wednesday]. Alternatively, we can think of [fdfs_any]
as a primitive "evidence constructor" that, when applied to a
particular day, stands as evidence that that day is a fine day for
singing; its type, [forall d:day, fine_day_for_singing d],
expresses this functionality, in the same way that the polymorphic
type [forall X, list X] in the previous chapter expressed the fact
that the constructor [nil] can be thought of as a function from
types to empty lists with elements of that type. *)
(** 式 [fdfs_any wednesday] は、パラメータを受け取る公理 [fdfs_any]を 特定の引数 [wednesday] によって具体化したものととらえることができます。
別の見方をすれば、[fdfs_any] を原始的な"根拠コンストラクタ"として捉えることもできます。この根拠コンストラクタは、特定の日を適用されると、その日が「歌わずにはいられないほどよい日」である根拠を表します。
型 [forall d:day, fine_day_for_singing d] はこの機能を表しています。
これは、前章で登場した多相型 [forall X, list X] において [nil] コンストラクタが型からその型を持つ空リストを返す関数であったことと同様です。 *)
(* Let's take a slightly more interesting example. Let's say
that a day of the week is "ok" if either (1) it is a good day or
else (2) it falls the day before an ok day. *)
(** もうちょっと面白い例を見てみましょう。
"OK"な日とは(1)良い日であるか(2)OKな日の前日であるとしましょう。*)
Inductive ok_day : day -> Prop :=
| okd_gd : forall d,
good_day d ->
ok_day d
| okd_before : forall d1 d2,
ok_day d2 ->
day_before d2 d1 ->
ok_day d1.
(* The first constructor can be read "One way to show that [d]
is an ok day is to present evidence that [d] is good." The second
can be read, "Another way to show that a day [d1] is ok is to
present evidence that it is the day before some other day [d2]
together with evidence that [d2] is ok." *)
(** 最初のコンストラクタは"[d]がOKな日であることを示す一つ目の方法は、[d]が良い日であるという根拠を示すことである"と読めます。
二番目のは"[d1]がOKであることを示す別の方法は、その日が別の日 [d2] の前日であり、[d2]がOKであるという根拠を示すことである"と読めます。 *)
(* Now suppose that we want to prove that [wednesday] is ok.
There are two ways to do it. First, we have the primitive way,
where we simply write down an expression that has the right
type -- a big nested application of constructors: *)
(** ここで [wednesday] がOKであることを証明したいとしましょう。
証明するには2つの方法があります
1つめは原始的な方法であり、コンストラクタの適用を何度もネストすることで、
正しい型を持つ式を書き下します。 *)
Definition okdw : ok_day wednesday :=
okd_before wednesday thursday
(okd_before thursday friday
(okd_before friday saturday
(okd_gd saturday gd_sat)
db_sat)
db_fri)
db_thu.
(* Second, we have the machine-assisted way, where we go into [Proof]
mode and Coq guides us through a series of goals and subgoals
until it is finally satisfied: *)
(** 2つめの方法は、機械に支援してもらう方法です。証明モードに入り、最終的に満たされるまでゴールやサブゴールを通してCoqに案内してもらいます。 *)
Theorem okdw' : ok_day wednesday.
Proof.
(* wednesday is OK because it's the day before an OK day *)
apply okd_before with (d2:=thursday).
(* "subgoal: show that thursday is ok". *)
(* thursday is OK because it's the day before an OK day *)
apply okd_before with (d2:=friday).
(* "subgoal: show that friday is ok". *)
(* friday is OK because it's the day before an OK day *)
apply okd_before with (d2:=saturday).
(* "subgoal: show that saturday is ok". *)
(* saturday is OK because it's good! *)
apply okd_gd. apply gd_sat.
(* "subgoal: show that the day before saturday is friday". *)
apply db_sat.
(* "subgoal: show that the day before friday is thursday". *)
apply db_fri.
(* "subgoal: show that the day before thursday is wednesday". *)
apply db_thu. Qed.
(* Fundamentally, though, these two ways of making proofs are the
same, in the sense that what Coq is actually doing when it's
following the commands in a [Proof] script is _literally_
attempting to construct an expression with the desired type. *)
(** しかし、根本的なところでこの2つの証明方法は同じです。
証明スクリプト内のコマンドを実行するときにCoqが実際にやっていることは、目的の型を持つ式を構築することと全く同じです。
*)
Print okdw'.
(* ===> okdw' = okd_before wednesday thursday
(okd_before thursday friday
(okd_before friday saturday
(okd_gd saturday gd_sat) db_sat)
db_fri)
db_thu
: ok_day wednesday *)
(* These expressions are often called _proof objects_. *)
(** この式は一般的に証明オブジェクト（Proof object）と呼ばれます。 *)
(* Proof objects are the bedrock of Coq. Tactic proofs are
essentially _programs_ that instruct Coq how to construct proof
objects for us instead of our writing them out explicitly. Here,
of course, the proof object is actually shorter than the tactic
proof. But the proof objects for more interesting proofs can
become quite large and complex -- building them by hand would be
painful. Moreover, we'll see later on in the course that Coq has
a number of automation tactics that can construct quite complex
proof objects without our needing to specify every step. *)
(** 証明オジェクトはCoqの根本を支えています。
タクティックによる証明は、自分で証明オブジェクトを書く代わりに、証明オブジェクトを構築する方法をCoqに指示する基本的なプログラムです。
もちろん、この例では証明オブジェクトはタクティックによる証明よりも短くなっています。
しかし、もっと興味深い証明では証明オブジェクトを手で構築することが苦痛に思えるほど大きく複雑になります。
この後の章では、各ステップを書くことなく複雑な証明オブジェクトを構築できる自動化されたタクティックをたくさん紹介します。 *)
(* ##################################################### *)
(* ** The Curry-Howard Correspondence *)
(** ** カリー・ハワード対応 *)
(* The analogy
<<
propositions ~ sets / types
proofs ~ data values
>>
is called the _Curry-Howard correspondence_ (or _Curry-Howard
isomorphism_). Many wonderful things follow from it. *)
(** この
<<
命題 ~ 集合 / 型
証明 ~ 元、要素 / データ値
>>
という類似性は、カリー・ハワード対応（もしくはカリー・ハワード同型, Curry-Howard correspondence, Curry-Howard isomorphism）と呼ばれます。
これにより多くのおもしろい性質が導けます。
*)
(* Just as a set can be empty, a singleton, finite, or infinite -- it
can have zero, one, or many inhabitants -- a proposition may be
inhabited by zero, one, many, or infinitely many proofs. Each
inhabitant of a proposition [P] is a different way of giving
evidence for [P]. If there are none, then [P] is not provable.
If there are many, then [P] has many different proofs. *)
(** 集合に空集合、単集合、有限集合、無限集合があり、それぞれが0個、1個、多数の元を持っているように、命題も0個、1個、多数、無限の証明を持ちえます。
命題 [P] の各要素は、それぞれ異なる [P] の根拠です。
もし要素がないならば、[P] は証明不能です。
もしたくさんの要素があるならば、[P] には多数の異なった証明があります。 *)
(* ##################################################### *)
(* ** Implication *)
(** ** 含意 *)
(* We've seen that the [->] operator (implication) builds bigger
propositions from smaller ones. What constitutes evidence for
propositions built in this way? Consider this statement: *)
(** これまで [->] 演算子(含意)を小さい命題から大きな命題を作るために使ってきました。
このような命題に対する根拠はどのようになるでしょうか?
次の文を考えてみてください。 *)
Definition okd_before2 := forall d1 d2 d3,
ok_day d3 ->
day_before d2 d1 ->
day_before d3 d2 ->
ok_day d1.
(* In English: if we have three days, [d1] which is before [d2]
which is before [d3], and if we know [d3] is ok, then so is
[d1].
It should be easy to see how we'd construct a tactic proof of
[okd_before2]... *)
(** これを日本語で書くと、もし3つの日があるとして、[d1] が [d2] の前日であり、[d2] が [d3] の前日であり、かつ [d3] がOKであるということがわかっているならば、[d1] もOKである、という意味になります。
[okd_before2] をタクティッックを使って証明するのは簡単なはずです... *)
(* **** Exercise: 1 star, optional (okd_before2_valid) *)
(** **** 練習問題: ★, optional (okd_before2_valid) *)
Theorem okd_before2_valid : okd_before2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* But what should the corresponding proof object look like?
Answer: We've made a notational pun between [->] as implication
and [->] as the type of functions. If we take this pun seriously,
then what we're looking for is an expression with _type_ [forall
d1 d2 d3, ok_day d3 -> day_before d2 d1 -> day_before d3 d2 ->
ok_day d1], and so what we want is a _function_ that takes six
arguments (three days and three pieces of evidence) and returns a
piece of evidence! Here it is: *)
(** ところで、これに対応する証明オブジェクトはどんな感じでしょうか?
答: 含意としての [->] と、関数の型の [->] の記法はそっくりです。
これをそのまま解釈すると、[forall d1 d2 d3, ok_day d3 -> day_before d2 d1 -> day_before d3 d2 -> ok_day d1] という型をもった式を見付ける必要があります。
なので探すものは6個の引数(3個の日と、3個の根拠)を受け取り、1個の根拠を返す関数です!
それはこんな感じです。
*)
Definition okd_before2_valid' : okd_before2 :=
fun (d1 d2 d3 : day) =>
fun (H : ok_day d3) =>
fun (H0 : day_before d2 d1) =>
fun (H1 : day_before d3 d2) =>
okd_before d1 d2 (okd_before d2 d3 H H1) H0.
(* **** Exercise: 1 star, optional (okd_before2_valid_defn) *)
(** **** 練習問題: ★, optional (okd_before2_valid_defn) *)
(* Predict what Coq will print in response to this: *)
(** 下記の結果としてCoqが出力するものを予測しなさい。 *)
Print okd_before2_valid.
(* ##################################################### *)
(* ** Induction Principles for Inductively Defined Types *)
(** ** 帰納的に定義された型に対する帰納法の原理 *)
(* Every time we declare a new [Inductive] datatype, Coq
automatically generates an axiom that embodies an _induction
principle_ for this type.
The induction principle for a type [t] is called [t_ind]. Here is
the one for natural numbers: *)
(** [Inductive] でデータ型を新たに定義するたびに、Coqは帰納法の原理に対応する公理を自動生成します。
型[t]に対応する帰納法の原理は[t_ind]という名前になります。
ここでは自然数に対するものを示します。 *)
Check nat_ind.
(* ===> nat_ind : forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(* Note that this is exactly the [our_nat_induction] property from
above. *)
(** これは先ほど定義した [our_nat_induction] の性質とまったく同じであることに注意してください。 *)
(* The [induction] tactic is a straightforward wrapper that, at
its core, simply performs [apply t_ind]. To see this more
clearly, let's experiment a little with using [apply nat_ind]
directly, instead of the [induction] tactic, to carry out some
proofs. Here, for example, is an alternate proof of a theorem
that we saw in the [Basics] chapter. *)
(** [induction] タクティックは、基本的には [apply t_ind] の単純なラッパーです。
もっとわかりやすくするために、[induction] タクティックのかわりに [apply nat_ind] を使っていくつかの証明をしてみる実験をしてみましょう。
例えば、[Basics_J] の章で見た定理の別の証明を見てみましょう。 *)
Theorem mult_0_r' : forall n:nat,
n * 0 = 0.
Proof.
apply nat_ind.
Case "O". reflexivity.
Case "S". simpl. intros n IHn. rewrite -> IHn.
reflexivity. Qed.
(* This proof is basically the same as the earlier one, but a
few minor differences are worth noting. First, in the induction
step of the proof (the ["S"] case), we have to do a little
bookkeeping manually (the [intros]) that [induction] does
automatically.
Second, we do not introduce [n] into the context before applying
[nat_ind] -- the conclusion of [nat_ind] is a quantified formula,
and [apply] needs this conclusion to exactly match the shape of
the goal state, including the quantifier. The [induction] tactic
works either with a variable in the context or a quantified
variable in the goal.
Third, the [apply] tactic automatically chooses variable names for
us (in the second subgoal, here), whereas [induction] lets us
specify (with the [as...] clause) what names should be used. The
automatic choice is actually a little unfortunate, since it
re-uses the name [n] for a variable that is different from the [n]
in the original theorem. This is why the [Case] annotation is
just [S] -- if we tried to write it out in the more explicit form
that we've been using for most proofs, we'd have to write [n = S
n], which doesn't make a lot of sense! All of these conveniences
make [induction] nicer to use in practice than applying induction
principles like [nat_ind] directly. But it is important to
realize that, modulo this little bit of bookkeeping, applying
[nat_ind] is what we are really doing. *)
(** この証明は基本的には前述のものと同じですが、細かい点で特筆すべき違いがあります。
1つめは、帰納段階の証明（["S"] の場合）において、[induction] が自動でやってくれること（[intros]）を手作業で行なう必要があることです。
2つめは、[nat_ind] を適用する前にコンテキストに [n] を導入していないことです。
[nat_ind] の結論は限量子を含む式であり、[apply] で使うためにはこの結論と限量子を含んだゴールの形とぴったりと一致する必要があります。
[induction] タクティックはコンテキストにある変数にもゴール内の量子化された変数のどちらにでも使えます。
3つめは、[apply] タクティックは変数名（この場合はサブゴール内で使われる変数名）を自動で選びますが、[induction] は（[as ...] 節によって）使う名前を指定できることです。
実際には、この自動選択にはちょっと不都合な点があります。元の定理の [n] とは別の変数として [n] を再利用してしまいます。
これは [Case] 注釈がただの [S] だからです。
ほかの証明で使ってきたように省略しない形で書くと、これは [n = S n] という意味のなさない形になってしまいます。
このようなことがあるため、実際には [nat_ind] のような帰納法の原理を直接適用するよりも、素直に [induction] を使ったほうがよいでしょう。
しかし、ちょっとした例外を除けば実際にやりたいのは [nat_ind] の適用であるということを知っておくことは重要です。 *)
(* **** Exercise: 2 stars (plus_one_r') *)
(** **** 練習問題: ★★ (plus_one_r') *)
(* Complete this proof without using the [induction] tactic. *)
(** [induction] タクティックを使わずに、下記の証明を完成させなさい。 *)
Theorem plus_one_r' : forall n:nat,
n + 1 = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* The induction principles that Coq generates for other
datatypes defined with [Inductive] follow a similar pattern. If we
define a type [t] with constructors [c1] ... [cn], Coq generates a
theorem with this shape:
[[
t_ind :
forall P : t -> Prop,
... case for c1 ... ->
... case for c2 ... ->
... ->
... case for cn ... ->
forall n : t, P n
]]
The specific shape of each case depends on the arguments to the
corresponding constructor. Before trying to write down a general
rule, let's look at some more examples. First, an example where
the constructors take no arguments: *)
(** ほかの [Inductive] によって定義されたデータ型に対しても、Coqは似た形の帰納法の原理を生成します。
コンストラクタ [c1] ... [cn] を持った型 [t] を定義すると、Coqは次の形の定理を生成します。
[[
t_ind :
forall P : t -> Prop,
... c1の場合 ... ->
... c2の場合 ... ->
... ->
... cnの場合 ... ->
forall n : t, P n
]]
各場合分けの形は、対応するコンストラクタの引数の数によって決まります。
一般的な規則を紹介する前に、もっと例を見てみましょう。
最初は、コンストラクタが引数を取らない場合です。
*)
Inductive yesno : Type :=
| yes : yesno
| no : yesno.
Check yesno_ind.
(* ===> yesno_ind : forall P : yesno -> Prop,
P yes ->
P no ->
forall y : yesno, P y *)
(* **** Exercise: 1 star (rgb) *)
(** **** 練習問題: ★ (rgb) *)
(* Write out the induction principle that Coq will generate for
the following datatype. Write down your answer on paper, and
then compare it with what Coq prints. *)
(** 次のデータ型に対してCoqが生成する帰納法の原理を予測しなさい。
紙に答えを書いたのち、Coqの出力と比較しなさい。 *)
Inductive rgb : Type :=
| red : rgb
| green : rgb
| blue : rgb.
Check rgb_ind.
(** [] *)
(* Here's another example, this time with one of the constructors
taking some arguments. *)
(** 別の例を見てみましょう。引数を受け取るコンストラクタがある場合です。 *)
Inductive natlist : Type :=
| nnil : natlist
| ncons : nat -> natlist -> natlist.
Check natlist_ind.
(* ===> (modulo a little tidying)
natlist_ind :
forall P : natlist -> Prop,
P nnil ->
(forall (n : nat) (l : natlist), P l -> P (ncons n l)) ->
forall n : natlist, P n *)
(* **** Exercise: 1 star (natlist1) *)
(** **** 練習問題: ★ (natlist1) *)
(* Suppose we had written the above definition a little
differently: *)
(** 上記の定義をすこし変えたとしましょう。 *)
Inductive natlist1 : Type :=
| nnil1 : natlist1
| nsnoc1 : natlist1 -> nat -> natlist1.
(* Now what will the induction principle look like? *)
(** このとき、帰納法の原理はどのようになるでしょうか？ *)
(** [] *)
(* From these examples, we can extract this general rule:
- The type declaration gives several constructors; each
corresponds to one clause of the induction principle.
- Each constructor [c] takes argument types [a1]...[an].
- Each [ai] can be either [t] (the datatype we are defining) or
some other type [s].
- The corresponding case of the induction principle
says (in English):
- "for all values [x1]...[xn] of types [a1]...[an], if
[P] holds for each of the [x]s of type [t], then [P]
holds for [c x1 ... xn]". *)
(** これらの例より、一般的な規則を導くことができます。
- 型宣言は複数のコンストラクタを持ち、各コンストラクタが帰納法の原理の各節に対応する。
- 各コンストラクタ [c] は引数 [a1]..[an] を取る。
- [ai] は [t]（定義しようとしているデータ型）、もしくは別の型 [s] かのどちらかである。
- 帰納法の原理において各節は以下のことを述べている。
- "型 [a1]...[an] のすべての値 [x1]...[xn] について、各 [x] について [P] が成り立つならば、[c x1 ... xn] についても [P] が成り立つ"
*)
(* **** Exercise: 1 star (ExSet) *)
(** **** 練習問題: ★ (ExSet) *)
(* Here is an induction principle for an inductively defined
set.
[[
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
]]
Give an [Inductive] definition of [ExSet]: *)
(** 帰納的に定義された集合に対する帰納法の原理が次のようなものだとします。
[[
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
]]
[ExSet] の帰納的な定義を示しなさい。 *)
Inductive ExSet : Type :=
(* FILL IN HERE *)
.
(** [] *)
(* What about polymorphic datatypes?
The inductive definition of polymorphic lists
[[
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
]]
is very similar to that of [natlist]. The main difference is
that, here, the whole definition is _parameterized_ on a set [X]:
that is, we are defining a _family_ of inductive types [list X],
one for each [X]. (Note that, wherever [list] appears in the body
of the declaration, it is always applied to the parameter [X].)
The induction principle is likewise parameterized on [X]:
[[
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
]]
Note the wording here (and, accordingly, the form of [list_ind]):
The _whole_ induction principle is parameterized on [X]. That is,
[list_ind] can be thought of as a polymorphic function that, when
applied to a type [X], gives us back an induction principle
specialized to the type [list X]. *)
(** 多相的なデータ型ではどのようになるでしょうか？
多相的なリストの帰納的定義は [natlist] によく似ています。
[[
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
]]
ここでの主な違いは、定義全体が集合 [X] によってパラメータ化されていることです。
つまり、それぞれの [X] ごとに帰納型 [list X] を定義していることになります。
(定義本体で [list] が登場するときは、常にパラメータ [X] に適用されていることに
注意してください。)
帰納法の原理も同様に [X] によってパラメータ化されます。
[[
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
]]
この表現（と [list_ind] の全体的な形）に注目してください。帰納法の原理全体が
[X] によってパラメータ化されています。
別の見方をすると、[list_ind] は多相関数と考えることができます。この関数は、型
[X] が適用されると、[list X] に特化した帰納法の原理を返します。 *)
(* **** Exercise: 1 star (tree) *)
(** **** 練習問題: ★ (tree) *)
(* Write out the induction principle that Coq will generate for
the following datatype. Compare your answer with what Coq
prints. *)
(** 次のデータ型に対してCoqが生成する帰納法の原理を予測しなさい。
答えが書けたら、それをCoqの出力と比較しなさい。 *)
Inductive tree (X:Type) : Type :=
| leaf : X -> tree X
| node : tree X -> tree X -> tree X.
Check tree_ind.
(** [] *)
(* **** Exercise: 1 star (mytype) *)
(** **** 練習問題: ★ (mytype) *)
(* Find an inductive definition that gives rise to the
following induction principle:
[[
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
]]
*)
(** 以下の帰納法の原理を生成する帰納的定義を探しなさい。
[[
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
]]
*)
(** [] *)
(* **** Exercise: 1 star, optional (foo) *)
(** **** 練習問題: ★, optional (foo) *)
(* Find an inductive definition that gives rise to the
following induction principle:
[[
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
]]
*)
(** 以下の帰納法の原理を生成する帰納的定義を探しなさい。
[[
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
]]
*)
(** [] *)
(* **** Exercise: 1 star, optional (foo') *)
(** **** 練習問題: ★, optional (foo') *)
(* Consider the following inductive definition: *)
(** 次のような帰納的定義があるとします。 *)
Inductive foo' (X:Type) : Type :=
| C1 : list X -> foo' X -> foo' X
| C2 : foo' X.
(* What induction principle will Coq generate for [foo']? Fill
in the blanks, then check your answer with Coq.)
[[
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
]]
*)
(** [foo'] に対してCoqはどのような帰納法の原理を生成するでしょうか?
空欄を埋め、Coqの結果と比較しなさい
[[
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
]]
*)
(** [] *)
(* ##################################################### *)
(* ** Induction Hypotheses *)
(** ** 帰納法の仮定 *)
(* Where does the phrase "induction hypothesis" fit into this
picture?
The induction principle for numbers
[[
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
]]
is a generic statement that holds for all propositions
[P] (strictly speaking, for all families of propositions [P]
indexed by a number [n]). Each time we use this principle, we
are choosing [P] to be a particular expression of type
[nat->Prop].
We can make the proof more explicit by giving this expression a
name. For example, instead of stating the theorem [mult_0_r] as
"[forall n, n * 0 = 0]," we can write it as "[forall n, P_m0r
n]", where [P_m0r] is defined as... *)
(** この概念において"帰納法の仮定"はどこにあてはまるでしょうか?
数に関する帰納法の原理
[[
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
]]
は、すべての命題 [P]（より正確には数値 n を引数にとる命題 [P] ）について成り立つ一般的な文です。
この原理を使うときはいつも、[nat->Prop] という型を持つ式を [P] として選びます。
この式に名前を与えることで、証明をもっと明確にできます。
例えば、[mult_0_r] を"[forall n, n * 0 = 0]"と宣言するかわりに、"[forall n, P_m0r n]"と宣言します。
なお、ここで [P_m0r] は次のように定義されています。
*)
Definition P_m0r (n:nat) : Prop :=
n * 0 = 0.
(* ... or equivalently... *)
(** あるいは *)
Definition P_m0r' : nat->Prop :=
fun n => n * 0 = 0.
(** でも同じ意味です。 *)
(* Now when we do the proof it is easier to see where [P_m0r]
appears. *)
(** これで、証明する際に [P_m0r] がどこに表われるかが分かりやすくなります。 *)
Theorem mult_0_r'' : forall n:nat,
P_m0r n.
Proof.
apply nat_ind.
Case "n = O". reflexivity.
Case "n = S n'".
(* Note the proof state at this point! *)
unfold P_m0r. simpl. intros n' IHn'.
apply IHn'. Qed.
(* This extra naming step isn't something that we'll do in
normal proofs, but it is useful to do it explicitly for an example
or two, because it allows us to see exactly what the induction
hypothesis is. If we prove [forall n, P_m0r n] by induction on
[n] (using either [induction] or [apply nat_ind]), we see that the
first subgoal requires us to prove [P_m0r 0] ("[P] holds for
zero"), while the second subgoal requires us to prove [forall n',
P_m0r n' -> P_m0r n' (S n')] (that is "[P] holds of [S n'] if it
holds of [n']" or, more elegantly, "[P] is preserved by [S]").
The _induction hypothesis_ is the premise of this latter
implication -- the assumption that [P] holds of [n'], which we are
allowed to use in proving that [P] holds for [S n']. *)
(** このように名前をつける手順は通常の証明では不要です。
しかし、1つ2つ試してみると、帰納法の仮定がどのようなものなのかが分かりやすくなります。
[forall n, P_m0r n] を [n] による帰納法（[induction] か [apply nat_ind] を使う）によって証明しようとすると、最初のサブゴールでは [P_m0r 0]（"[P] が0に対して成り立つ"）を証明しなければならず、2つめのサブゴールでは [forall n', P_m0r n' -> P_m0r (S n')]（"[P] が [n'] について成り立つならば、[P] が [S n'] についても成り立つ"あるいは" [P] が [S] によって保存される"）を証明しなければなりません。
帰納法の仮定は、2つめの推論の基礎になっています -- [P] が [n'] について成り立つことを仮定することにより、それによって [P] が [S n'] について成り立つことを示すことができます。
*)
(* ####################################################### *)
(* ** Evenness Again *)
(** ** 偶数について再び *)
(* Some of the examples in the opening discussion of
propositions involved the concept of _evenness_. We began with a
computation [evenb n] that _checks_ evenness, yielding a boolean.
From this, we built a proposition [even n] (defined in terms of
[evenb]) that _asserts_ that [n] is even. That is, we defined
"[n] is even" to mean "[evenb] returns [true] when applied to
[n]."
Another alternative is to define the concept of evenness directly.
Instead of going indirectly via the [evenb] function ("a number is
even if a certain computation yields [true]"), we can say directly
what the concept of evenness means in terms of evidence. *)
(** 最初の方で命題に関して議論してきた例のいくつかは、偶数の概念に結びついてきます。
これまでは偶数を判定するために [evenb n] を計算することから始め、真偽値を返していました。
つぎに、[n] が偶数であることを主張する命題 [even n] を( [evenb] を使うことで）作りました。
つまり、"[n] が偶数である"を" [evenb] が [n] を適用されたときに [true] を返す"と定義していました。
偶数性の概念をそのまま定義する別の方法があります。
[evenb] 関数（"ある計算が [true] を返すなら、その数は偶数である"）を使って間接的に定義するのではなく、「偶数とは何を意味するか」を根拠を使って直接定義することができるのです。
*)
Inductive ev : nat -> Prop :=
| ev_0 : ev O
| ev_SS : forall n:nat, ev n -> ev (S (S n)).
(* This definition says that there are two ways to give
evidence that a number [m] is even. First, [0] is even, and
[ev_0] is evidence for this. Second, if [m = S (S n)] for some
[n] and we can give evidence [e] that [n] is even, then [m] is
also even, and [ev_SS n e] is the evidence. *)
(** この定義は、数 [m] が偶数であるという根拠を与える方法が2つあることを示しています。
第一に、[0] は偶数であり、[ev_0] がこれに対する根拠です。
次に、任意の [n] に対して [m = S (S n)] とし、[n] が偶数であるという根拠 [e] を与えることができるならば、[m] も偶数であると言え、[ev_SS n e] がその根拠となります。 *)
(* **** Exercise: 1 star, optional (four_ev) *)
(** **** 練習問題: ★, optional (four_ev) *)
(* Give a tactic proof and a proof object showing that four is even. *)
(** 4が偶数であることをタクティックによる証明と証明オブジェクトによる証明で示しなさい。 *)
Theorem four_ev' :
ev 4.
Proof.
(* FILL IN HERE *) Admitted.
Definition four_ev : ev 4 :=
(* FILL IN HERE *) admit.
(** [] *)
(* **** Exercise: 2 stars (ev_plus4) *)
(** **** 練習問題: ★★ (ev_plus4) *)
(* Give a tactic proof and a proof object showing that, if [n] is
even, then so is [4+n]. *)
(** [n] が偶数ならば [4+n] も偶数であることをタクティックによる証明と証明オブジェクトによる証明で示しなさい。 *)
Definition ev_plus4 : forall n, ev n -> ev (4 + n) :=
(* FILL IN HERE *) admit.
Theorem ev_plus4' : forall n,
ev n -> ev (4 + n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 2 stars (double_even) *)
(** **** 練習問題: ★★ (double_even) *)
(* Construct a tactic proof of the following proposition. *)
(** 次の命題をタクティックによって証明しなさい。 *)
Theorem double_even : forall n,
ev (double n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 4 stars, optional (double_even_pfobj) *)
(** **** 練習問題: ★★★★, optional (double_even_pfobj) *)
(* Try to predict what proof object is constructed by the above
tactic proof. (Before checking your answer, you'll want to
strip out any uses of [Case], as these will make the proof
object look a bit cluttered.) *)
(** 上記のタクティックによる証明でどのような証明オブジェクトが構築されるかを予想しなさい。
(答を確かめる前に、[Case] を除去しましょう。 これがあると証明オブジェクトが少し見づらくなります。)
*)
(** [] *)
(* ####################################################### *)
(* ** Reasoning by Induction Over Evidence *)
(** ** 根拠に対する帰納法の推論 *)
(* The highly "orthogonal" organization of Coq's design might
suggest that, since we use the keyword [Induction] to define
primitive propositions together with their evidence, there must be
some sort of induction principles associated with these
definitions. Indeed there are, and in this section we'll take a
look at how they can be used. To get warmed up, let's look at how
the simpler [destruct] tactic works with inductively defined
evidence. *)
(** Coqの設計は非常に直交しているので、素朴な命題を根拠と共に定義するために [Inductive] キーワードを使った場合、その定義と関連する帰納法の原理が使えるはずです。
実際、関連する帰納法の原理は存在しており、この節ではそれをどう使うかについて見ていきます。
ウォーミングアップとして、単純な [destruct] が帰納的に定義された根拠に対してどのように働くかを見てみましょう。
*)
(* Besides _constructing_ evidence of evenness, we can also _reason
about_ evidence of evenness. The fact that we introduced [ev]
with an [Inductive] declaration tells us not only that the
constructors [ev_0] and [ev_SS] are ways to build evidence of
evenness, but also that these two constructors are the _only_ ways
that evidence of evenness can be built.
In other words, if someone gives us evidence [E] justifying the
assertion [ev n], then we know that [E] can only have one of two
forms: either [E] is [ev_0] (and [n] is [O]), or [E] is [ev_SS n'
E'] (and [n] is [S (S n')]) and [E'] is evidence that [n'] is
even.
Thus, it makes sense to use the tactics that we have already seen
for inductively defined _data_ to reason instead about inductively
defined _evidence_.
For example, here we use a [destruct] on evidence that [n] is even
in order to show that [ev n] implies [ev (n-2)]. *)
(** 偶数であるという根拠を作るだけでなく、偶数であるという根拠に対して推論を行います。
帰納的な宣言によって [ev] を導入したことにより、「 [ev_0] と [ev_SS] が、偶数であるという根拠を作る唯一の方法である」ということが分かるだけでなく、「この2つのコンストラクタによってのみ偶数であるという根拠が構築される」ということが分かります。
言い換えると、 [ev n] という根拠 [E] があった場合、 [E] は2つの形式のどちらか片方であることが分かります : 「[E] が [ev_0] (かつ [n] が [0] )である」か、「 [E] が [ev_SS n' E'](かつ [n] が [S (S n')]) かつ [E'] が [n'] が偶数であるということの根拠である」かのどちらかです。
なので、これまで見てきたように帰納的に定義されたデータに対してだけでなく、帰納的に定義された根拠に対しても、 [destruct] タクティックを使うことは有用です。
一例として、[ev n] ならば [ev (n-2)] を示すために、 [n] が偶数であるという根拠に対して [destruct] タクティックを使ってみましょう。
*)
Theorem ev_minus2: forall n,
ev n -> ev (pred (pred n)).
Proof.
intros n E.
destruct E as [| n' E'].
Case "E = ev_0". simpl. apply ev_0.
Case "E = ev_SS n' E'". simpl. apply E'. Qed.
(* **** Exercise: 1 star (ev_minus2_n) *)
(** **** 練習問題: ★ (ev_minus2_n) *)
(* What happens if we try to [destruct] on [n] instead of [E]? *)
(** [E] の代わりに [n] に対して [destruct] するとどうなるでしょうか? *)
(** [] *)
(* [] *)
(* We can also perform _induction_ on evidence that [n] is
even. Here we use it to show that the old [evenb] function
returns [true] on [n] when [n] is even according to [ev]. *)
(** [n] が偶数であるという根拠に対して [induction] を実行することもできます。
[ev] を満たす [n] に対して、先に定義した [evenb] 関数が [true] を返すことを示すために使ってみましょう。
*)
Theorem ev_even : forall n,
ev n -> even n.
Proof.
intros n E. induction E as [| n' E'].
Case "E = ev_0".
unfold even. reflexivity.
Case "E = ev_SS n' E'".
unfold even. apply IHE'. Qed.
(* (Of course, we'd expect that [even n -> ev n] also holds. We'll
see how to prove it in the next chapter.) *)
(** (もちろん、 [even n -> ev n] も成り立つはずです。 どのように証明するかは次の章で説明します。) *)
(* **** Exercise: 1 star (ev_even_n) *)
(** **** 練習問題: ★ (ev_even_n) *)
(** *)
(** この証明を [E] でなく [n] に対する帰納法として実施できますか? *)
(* Could this proof be carried out by induction on [n] instead
of [E]? *)
(** [] *)
(* [] *)
(* The induction principle for inductively defined propositions does
not follow quite the same form as that of inductively defined
sets. For now, you can take the intuitive view that induction on
evidence [ev n] is similar to induction on [n], but restricts our
attention to only those numbers for which evidence [ev n] could be
generated. We'll look at the induction principle of [ev] in more
depth below, to explain what's really going on. *)
(** 帰納的に定義された命題に対する帰納法の原理は、帰納的に定義された集合のそれとまったく同じ形をしているわけではありません。
今の段階では、根拠 [ev n] に対する帰納法は [n] に対する帰納法に似ているが、 [ev n] が成立する数についてのみ着目することができると直感的に理解しておいて問題ありません。
[ev] の帰納法の原理をもっと深く見て行き、実際に何を起こっているかを説明します。*)
(* **** Exercise: 1 star (l_fails) *)
(** **** 練習問題: ★ (l_fails) *)
(* The following proof attempt will not succeed.[[
Theorem l : forall n,
ev n.
Proof.
intros n. induction n.
Case "O". simpl. apply ev_0.
Case "S".
...
]]
Briefly explain why.
(* FILL IN HERE *)
*)
(** 次の証明はうまくいきません。 [[
Theorem l : forall n,
ev n.
Proof.
intros n. induction n.
Case "O". simpl. apply ev_0.
Case "S".
...
]]
理由を簡潔に説明しない。
(* FILL IN HERE *)
*)
(** [] *)
(* [] *)
(* **** Exercise: 2 stars (ev_sum) *)
(** **** 練習問題: ★★ (ev_sum) *)
(* Here's another exercise requiring induction. *)
(** 帰納法が必要な別の練習問題をやってみましょう。 *)
Theorem ev_sum : forall n m,
ev n -> ev m -> ev (n+m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* Here's another situation where we want to analyze evidence for
evenness: proving that if [n+2] is even, then [n] is. Our first
idea might be to use [destruct] for this kind of case analysis: *)
(** 「[n+2] が偶数ならば [n] も偶数である」という偶数に関する根拠を分析したいとします。
この種の場合分けに [destruct] を使ってみたくなるかもしれません。 *)
Theorem SSev_ev_firsttry : forall n,
ev (S (S n)) -> ev n.
Proof.
intros n E.
destruct E as [| n' E'].
(* Stuck: [destruct] は証明できないサブゴールを提示してしまいます！ *)
Admitted.
(* But this doesn't work. For example, in the first sub-goal, we've
lost the information that [n] is [0]. The right thing to use
here, it turns out, is [inversion]: *)
(** しかし、これはうまくいきません。 例えば、最初のサブゴールにおいて、 [n] が [0] であるという情報が失われてしまいます。
ここで使うべきは、 [inversion] です。 *)
Theorem SSev_even : forall n,
ev (S (S n)) -> ev n.
Proof.
intros n E. inversion E as [| n' E']. apply E'. Qed.
(* Print SSev_even. *)
(* This use of [inversion] may seem a bit mysterious at first.
Until now, we've only used [inversion] on equality
propositions, to utilize injectivity of constructors or to
discriminate between different constructors. But we see here
that [inversion] can also be applied to analyzing evidence
for inductively defined propositions.
Here's how [inversion] works in general. Suppose the name
[I] refers to an assumption [P] in the current context, where
[P] has been defined by an [Inductive] declaration. Then,
for each of the constructors of [P], [inversion I] generates
a subgoal in which [I] has been replaced by the exact,
specific conditions under which this constructor could have
been used to prove [P]. Some of these subgoals will be
self-contradictory; [inversion] throws these away. The ones
that are left represent the cases that must be proved to
establish the original goal.
In this particular case, the [inversion] analyzed the construction
[ev (S (S n))], determined that this could only have been
constructed using [ev_SS], and generated a new subgoal with the
arguments of that constructor as new hypotheses. (It also
produced an auxiliary equality, which happens to be useless here.)
We'll begin exploring this more general behavior of inversion in
what follows. *)
(** このような [inversion] の使い方は最初はちょっと謎めいて思えるかもしれません。
これまでは、 [inversion] は等号に関する命題に対して使い、コンストラクタから元のデータを取り出すためか、別のコンストラクタを区別するためににしか使っていませんでした。
しかし、ここでは [inversion] が 帰納的に定義された命題に対する根拠を分析するためにも使えることを紹介しました。
ここで、[inversion] が一般にはどのように動作するかを説明します。
[I] が現在のコンテキストにおいて帰納的に宣言された仮定 [P] を参照しているとします。
ここで、[inversion I] は、[P]のコンストラクタごとにサブゴールを生成します。 各サブゴールにおいて、 コンストラクタが [P] を証明するのに必要な条件によって [I] が置き換えられます。
サブゴールのうちいくつかは矛盾が存在するので、 [inversion] はそれらを除外します。
残っているのは、元のゴールが成り立つことを示すのに必要なサブゴールです。
先ほどの例で、 [inversion] は [ev (S (S n))] の分析に用いられ、 これはコンストラクタ [ev_SS] を使って構築されていることを判定し、そのコンストラクタの引数を仮定に追加した新しいサブゴールを生成しました。(今回は使いませんでしたが、補助的な等式も生成しています。)
このあとの例では、inversion のより一般的な振る舞いについて調べていきましょう。
*)
(* **** Exercise: 1 star (inversion_practice) *)
(** **** 練習問題: ★ (inversion_practice) *)
Theorem SSSSev_even : forall n,
ev (S (S (S (S n)))) -> ev n.
Proof.
(* FILL IN HERE *) Admitted.
(* The [inversion] tactic can also be used to derive goals by showing
the absurdity of a hypothesis. *)
(** [inversion] タクティックは、仮定が矛盾していることを示し、ゴールを達成するためにも使えます。
*)
Theorem even5_nonsense :
ev 5 -> 2 + 2 = 9.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* We can generally use [inversion] instead of [destruct] on
inductive propositions. This illustrates that in general, we
get one case for each possible constructor. Again, we also
get some auxiliary equalities that are rewritten in the goal
but not in the other hypotheses. *)
(** 一般に、帰納的な命題には [destruct] の代わりに [inversion] を使えます。
このことは一般的に、コンストラクタごとに場合分けができることを示しています。
加えて、いくつかの補助的な等式も得ることができます。
なお、ゴールはその等式によって書き換えられていますが、その他の仮定は書き換えられていません。
*)
Theorem ev_minus2': forall n,
ev n -> ev (pred (pred n)).
Proof.
intros n E. inversion E as [| n' E'].
Case "E = ev_0". simpl. apply ev_0.
Case "E = ev_SS n' E'". simpl. apply E'. Qed.
(* **** Exercise: 3 stars (ev_ev_even) *)
(** **** 練習問題: ★★★ (ev_ev_even) *)
(* Finding the appropriate thing to do induction on is a
bit tricky here: *)
(** 何に対して帰納法を行えばいいかを探しなさい。(ちょっとトリッキーですが) *)
Theorem ev_ev_even : forall n m,
ev (n+m) -> ev n -> ev m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 3 stars, optional (ev_plus_plus) *)
(** **** 練習問題: ★★★, optional (ev_plus_plus) *)
(* Here's an exercise that just requires applying existing lemmas. No
induction or even case analysis is needed, but some of the rewriting
may be tedious. You'll want the [replace] tactic used for [plus_swap']
in Basics.v *)
(** 既存の補題を適用する必要のある練習問題です。
帰納法も場合分けも不要ですが、書き換えのうちいくつかはちょっと大変です。
Basics_J.v の [plus_swap'] で使った [replace] タクティックを使うとよいかもしれません。 *)
Theorem ev_plus_plus : forall n m p,
ev (n+m) -> ev (n+p) -> ev (m+p).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ##################################################### *)
(* ** Why Define Propositions Inductively? *)
(** ** なぜ命題を帰納的に定義するのか? *)
(* We have seen that the proposition "some number is even" can
be phrased in two different ways -- indirectly, via a testing
function [evenb], or directly, by inductively describing what
constitutes evidence for evenness. These two ways of
defining evenness are about equally easy to state and work
with. Which we choose is basically a question of taste.
However, for many other properties of interest, the direct
inductive definition is preferable, since writing a testing
function may be awkward or even impossible. For example, consider
the property [MyProp] defined as follows:
- the number [4] has property [MyProp]
- if [n] has property [MyProp], then so does [4+n]
- if [2+n] has property [MyProp], then so does [n]
- no other numbers have property [MyProp]
This is a perfectly sensible definition of a set of numbers, but
we cannot translate this definition directly as a Coq Fixpoint (or
translate it directly into a recursive function in any other
programming language). We might be able to find a clever way of
testing this property using a [Fixpoint] (indeed, it is not too
hard to find one in this case), but in general this could require
arbitrarily much thinking. In fact, if the property we are
interested in is uncomputable, then we cannot define it as a
[Fixpoint] no matter how hard we try, because Coq requires that
all [Fixpoint]s correspond to terminating computations.
On the other hand, writing an inductive definition of what it
means to give evidence for the property [MyProp] is
straightforward: *)
(** ここまで見てきたように "ある数が偶数である" というのは次の2通りの方法で解釈されます。
間接的には「テスト用の [evenb] 関数」によって、直接的には「偶数であることの根拠の構築方法を帰納的に記述すること」によってです。
これら2つの偶数の定義は、ほぼ同じくらい楽に宣言できますし、同じように動きます。
どちらを選ぶかは基本的に好みの問題です。
しかし、興味深いほかの性質、例えば「テスト用の関数を書くのが難しかったり不可能だったりする」ようなことがあることを考えると、直接的な帰納的な定義のほうが好ましいと言えます。
例えば以下のように定義される [MyProp] という性質について考えてみましょう。
- [4] は性質 [MyProp] を満たす
- [n] が性質 [MyProp] を満たすならば、 [4+n] も満たす
- もし[2+n]が性質 [MyProp] を満たすならば、 [n] も満たす
- その他の数は、性質 [MyProp] を満たさない
これは数の集合の定義としてはなんの問題もありませんが、この定義をそのままCoqのFixPointに変換することはできません。
(それだけでなく他の言語の再帰関数に変換することもできません。)
[Fixpoint] を用いてこの性質をテストするうまい方法を見つけられるかもしれません。(実際のところ、この場合はそれほど難しいことではありません)
しかし、一般的にこういうことをしようとすると、かなりあれこれ考える必要があるでしょう。
実際、Coqの [Fixpoint] は停止する計算しか定義できないので、
定義しようとする性質が計算不能なものだった場合、どれだけがんばっても [Fixpoint] では定義できません。
一方、性質 [MyProp] がどのようなものかの根拠を与える帰納的な定義を書くことは、非常に簡単です。
*)
Inductive MyProp : nat -> Prop :=
| MyProp1 : MyProp 4
| MyProp2 : forall n:nat, MyProp n -> MyProp (4 + n)
| MyProp3 : forall n:nat, MyProp (2 + n) -> MyProp n.
(* The first three clauses in the informal definition of [MyProp]
above are reflected in the first three clauses of the inductive
definition. The fourth clause is the precise force of the keyword
[Inductive]. *)
(** [MyProp] の非形式的な定義の最初の3つの節は、帰納的な定義の最初の3つの節に反映されています。
4つ目の節は、[Inductive] キーワードによって強制されます。
*)
(* As we did with evenness, we can now construct evidence that
certain numbers satisfy [MyProp]. *)
(** これで、偶数のときにやったように、ある数が [MyProp] を満たすことの根拠を作ることができます。 *)
Theorem MyProp_ten : MyProp 10.
Proof.
apply MyProp3. simpl.
assert (12 = 4 + 8) as H12.
Case "Proof of assertion". reflexivity.
rewrite -> H12.
apply MyProp2.
assert (8 = 4 + 4) as H8.
Case "Proof of assertion". reflexivity.
rewrite -> H8.
apply MyProp2.
apply MyProp1. Qed.
(* **** Exercise: 2 stars (MyProp) *)
(** **** 練習問題: ★★ (MyProp) *)
(* Here are two useful facts about MyProp. The proofs are left
to you. *)
(** MyPropに関する便利な2つの事実があります。
証明はあなたのために残してあります。 *)
Theorem MyProp_0 : MyProp 0.
Proof.
(* FILL IN HERE *) Admitted.
Theorem MyProp_plustwo : forall n:nat, MyProp n -> MyProp (S (S n)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* With these, we can show that [MyProp] holds of all even numbers,
and vice versa. *)
(** これらを使って、 [MyProp] は全ての奇数について成り立つことと、その逆も成り立つをことを示せます。 *)
Theorem MyProp_ev : forall n:nat,
ev n -> MyProp n.
Proof.
intros n E.
induction E as [| n' E'].
Case "E = ev_0".
apply MyProp_0.
Case "E = ev_SS n' E'".
apply MyProp_plustwo. apply IHE'. Qed.
(* Here's an informal proof of this theorem:
_Theorem_: For any nat [n], if [ev n] then [MyProp n].
_Proof_: Suppose [n] is a [nat] and [E] is a derivation of [ev n].
We must exhibit a derivation of [MyProp n]. The proof is by
induction on [E]. There are two cases to consider:
- If the last step in [E] is a use of [ev_0], then [n] is [0].
Then we must show that [MyProp 0] holds; this is true by
lemma [MyProp_0].
- If the last step in [E] is a use of [ev_SS], then [n = S (S n')]
for some [n'], and there is a derivation of [ev n']. We must
show [MyProp (S (S n'))], with the induction hypothesis that
[MyProp n'] holds. But by lemma [MyProp_plustwo], it's enough
to show [MyProp n'], which is exactly the induction
hypothesis. [] *)
(** この定理の非形式的な証明は次のようになります。
_Theorem_ : 任意の自然数 [n] において、もし [ev n] ならば [MyProp n] が成り立つ。
_Proof_ : [n] を [nat] とし、[ev n] の導出を [E] とします。
[MyProp n] の導出を示さなければなりません。
[E] の帰納法について証明を行うので、以下の2つの場合について考えなければなりません。
- [E] の最後のステップが[ev_0]だった場合、 [n] は [0] となる。
その場合、[MyProp 0]が成り立つをことを示さなければならない;
補題 [MyProp_0] よりこれは真である。
- [E] の最後のステップが [ev_SS] だった場合、 [n = S (S n')] となる [n'] が存在し、 [ev n'] の導出が存在する。
[MyProp n'] が成り立つという帰納法の仮定を用いて、[MyProp (S (S n'))] を示さなければなりません。
しかし、補題 [MyProp_plustwo] により、[MyProp n'] を示せば十分であることがわかり、さらにそれは帰納法の仮定そのものです。
*)
(* **** Exercise: 3 stars (ev_MyProp) *)
(** **** 練習問題: ★★★ (ev_MyProp) *)
Theorem ev_MyProp : forall n:nat,
MyProp n -> ev n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 3 stars, optional (ev_MyProp_informal) *)
(** **** 練習問題: ★★★, optional (ev_MyProp_informal) *)
(* Write an informal proof corresponding to your
formal proof of [ev_MyProp]:
Theorem: For any nat [n], if [MyProp n] then [ev n].
Proof:
(* FILL IN HERE *)
[] *)
(** [ev_MyProp] の 形式的な証明に対応する非形式的な証明を書きなさい。
定理: すべての自然数 [n] に対して、 [MyProp n] ならば [ev n]。
証明: (ここを埋める)
[] *)
(* ##################################################### *)
(* * The Big Picture: Coq's Two Universes *)
(** * 全体像: Coqの2つの空間 *)
(* Now that we've touched on several of Coq's basic structures,
it may be useful to take a step back and talk a little about how
it all fits together. *)
(** これまで Coq の基本的な構造についていくつか触れてきたので、
ここでは一歩引いてそれらがどのように組み合わさっているか少しだけ見てみましょう。
*)
(* Expressions in Coq live in two distinct universes:
- [Type] is the universe of _computations_ and _data_.
- [Prop] is the universe of _logical assertions_ and _evidence_.
The two universes have some deep similarities -- in each, we can
talk about values, inductive definitions, quantification, etc. --
but they play quite different roles in defining and reasoning about
mathematical structures. *)
(** Coq の式は2つの異なる空間のどちらかに属しています。
- [Type] は計算とデータの空間です。
- [Prop] は論理的表明と根拠の空間です。
2つの空間には深い類似性がありますが（それぞれについて値、帰納的な定義、限量子などについて言及できます）、
数学的構造の定義や推論において、これらはまったく異なる役割を果たします。
*)
(* ** Values *)
(** ** 値 *)
(* Both universes start with an infinite set of _constructors_.
Constructors have no internal structure: they are just atomic
symbols. For example, [true], [false], [O], [S], [nil], [cons],
[ev_0], [ev_SS], ...
The simplest values are expressions consisting entirely of
constructor applications. Examples include:
- [true]
- [O]
- [S (S (S O))]
- [ev_0]
- [ev_SS (S (S O)) ev_0]
- [ev_SS (S (S (S (S O)))) (ev_SS (S (S O)) ev_0)]
Such expressions can be thought of as trees. Their leaves are
nullary constructors (applied to no arguments), and their internal
nodes are applications of constructors to one or more values. In
the universe [Type], we think of values as _data_. In [Prop], we
think of values as _evidence_. Values in [Prop] are sometimes
called _derivation trees_.
Functions are also values -- for example:
- [fun x => true]
- [fun b => negb b]
- [fun n => S (S (S n))]
- [fun n => fun (P : ev n) => ev_SS (S (S n)) P]
Functions that return values in the universe [Type] represent
_computations_: they take some input values and return an output
value computed from the inputs. Functions returning values in
[Prop] are _universally quantified evidence_: that is, they use
their inputs to build evidence for some proposition (whose
statement may also involve these inputs). *)
(** どちらのの空間もコンストラクタの無限集合をスタート地点とします。
コンストラクタは内部構造を全く持っておらず、ただのアトミックなシンボルです。
例えば、[true], [false], [O], [S], [nil], [cons],
[ev_0], [ev_SS], ... などです。
最も単純な値は、コンストラクタの適用だけによって構成されます。
例えば:
- [true]
- [O]
- [S (S (S O))]
- [ev_0]
- [ev_SS (S (S O)) ev_0]
- [ev_SS (S (S (S (S O)))) (ev_SS (S (S O)) ev_0)]
そのような式は木として考えることもできます。
葉は0引数のコンストラクタ（引数なしで適用された）であり、内部ノードは1個以上の値に対して適用されたコンストラクタです。
[Type] 空間において、値はデータとして捉えます。
[Prop] において、値を根拠として捉えます。
[Prop] における値は、導出木と呼ばれることもあります。
関数もまた値です。例えば、
- [fun x => true]
- [fun b => negb b]
- [fun n => S (S (S n))]
- [fun n => fun (P : ev n) => ev_SS (S (S n)) P]
[Type] 空間の値を返す関数は、計算を表します: 入力値を受け取り、入力から計算した出力値を返します。
[Prop] の値を返す関数は、全量子化された根拠と呼ばれます。 すなわち、ある命題に対する根拠を作るのに入力も用います。
（作られる命題も入力を使うかもしれません。）
*)
(* ** Inductive Definitions *)
(** ** 帰納的定義 *)
(* [Inductive] declarations give names to subsets of the set of all
values. For example, the declaration of the inductive type [nat]
defines a _set_ whose _elements_ are values representing natural
numbers. That is, it picks out a subset [nat] of the set of all
values that satisfies the following properties:
- the value [O] is in this set;
- the set is _closed_ under applications of [S] (i.e., if a
value [n] is in the set, then [S n] is too);
- it is the smallest set satisfying these conditions (i.e., the
only values in [nat] are the ones that _must_ be, according to
the previous two conditions; there is no other "junk").
Inductively defined sets can themselves appear as arguments to
constructors in compound values. Examples:
- [nat]
- [nil nat]
- [cons nat O (cons nat (S O) (nil nat))]
Also, we can write functions that take sets as arguments and
return sets as results. For example, [list] is a function that
takes a set [X] as argument and returns as result the set [list
X] (whose members are lists with elements drawn from [X]).
Similarly, the declaration of the inductive type [ev] defines a
_family of propositions_ whose _elements_ are values representing
evidence that numbers are even. That is, for each [n], the
definition picks out a subset [ev n] of the set of all values,
satisfying the following properties:
- the value [ev_0] is in the set [ev O];
- the sets are _closed_ under well-typed applications of
[ev_SS] -- i.e., if [e] is in the set [ev n], then
[ev_SS n e] is in the set [ev (S (S n))];
- it is the smallest family of sets satisfying these
conditions (i.e., the only values in any set [ev n] are the
ones that _must_ be, according to the previous two conditions;
there is no other junk). *)
(** 帰納的（[Inductive]）な定義をするということは、全ての値の集合の「特定の部分集合に名前を与える」ということです。
例えば、帰納的な型 [nat] の定義は、要素の全てが自然数を表しているような集合を表します。つまり、 帰納的な定義が「全ての値の集合」から以下のような属性を持つ要素だけを抜き出して部分集合 [nat] を作っていると考えられます。
- 値 [O] はこの集合の要素である。
- この集合は、 [S] の適用に対し閉じている（つまり、値 [n] がこの集合の要素なら [S n] もまたこの集合の要素である）。
- これらの条件を満たす最小の集合がこの集合である。（つまり集合 [nat] の要素だけが上の二つの条件を満たしていて、それ以外のものはこの集合に入っていない）。
帰納的に定義された集合は、それ自身が複合的な値のコンストラクタの引数となることもあります。例えば、以下のようなものです。
- [nat]
- [nil nat]
- [cons nat O (cons nat (S O) (nil nat))]
また、引数や戻り値が集合となっているような関数を書くこともできます。例えば、 [list] は集合 [X] を引数にとり、 [list X] の集合を返す関数です（この集合の要素は、集合 [X] の要素を持つリストです）。
同様に、帰納的な型 [ev] の定義は、その数字が偶数であるという根拠となる命題を集めたものの定義です。このことは、全ての [n] について、この定義が全ての値の集合から以下の条件を満たす値を全て集めて部分集合 [ev n] を抜き出してくるような定義、ということです。
- 値 [ev_0] は集合 [ev O] の要素である。
- この集合は [ev_SS] の型が正しい（well-typed な）適用に関して閉じている。
-- つまり、もし値 [e] が集合 [ev n] の要素なら、
値[ev_SS n e] は集合 [ev (S (S n))] の要素である。;
- これらの条件を満たす最小の集合がこの集合である。 (つまり集合 [ev n] の要素だけが上の二つの条件を満たしていて、それ以外のものはこの集合に入っていない）。 *)
(* ** Types and Kinds *)
(** ** 型とカインド *)
(* Informally, a _type_ in Coq is an expression that is used to
classify other expressions. For example, [bool], [nat], [list
bool], [list nat], [nat->nat], and so on are all types. The type
[bool] classifies [true] and [false]; the type [nat] classifies
[O], [S O], [S (S O)], etc.; the type [nat->nat] classifies
function values (like [fun n => S n]) that yield a number when
given a number as input.
[Type], [Prop], and compound expressions built from them (like
[Type->Type]) play a similar classifying role "one level up" --
that is, they can be thought of as the _types of type (and
proposition) expressions_. Technically, they are called _kinds_,
to avoid too many uses of the word "type." For example, the
expressions [nat], [nat->nat] and [list nat] all have kind [Type],
while [list] itself has kind [Type->Type] and [ev] has kind
[nat->Prop]. *)
(** ざっくり言うと、Coqにおける「型」は、「式の分類に使われる式」です。例えば、 [bool], [nat], [list bool], [list nat], [nat->nat] などは全て「型」です。[bool] という型は、 [true] や [false] を他の値と区別しますし、[nat] 型は [O], [S O], [S (S O)] など、[nat->nat] 型は [fun n => S n] のように数を引数にとって数を返す関数値を他の値と区別します。
[Type] や [Prop] 、そしてそれらの複合式（ [Type -> Type] など）には、「ひとつ上位の」分類 -- それは, 「型（もしくは命題）の型を表す式」のようなものと考えてもらっていいですが -- が可能です。それを、単なる「型」と混同しないために「カインド」と呼ぶことにします。例えば、[nat] や [nat->nat] 、[list nat] などは全て [Type] という「カインド」を持ち、 [list] は [Type -> Type]、 [ev] は [nat -> Prop] というカインドを持ちます。 *)
(** ** 命題 vs. ブール値 *)
(* Propositions and booleans are superficially similar, but they are
really quite different things!
- Booleans are _values_ in the _computational_ world. Every
expression of type [bool] (with no free variables) can be
simplified to either [true] or [false].
- Propositions are _types_ in the _logical_ world. They are
either _provable_ (i.e., there is some expression that has this
type) or not (there is no such expression). It doesn't make
sense to say that a proposition is "equivalent to [true]."
We sometimes use the words "true" and "false" informally when
referring to propositions. Strictly speaking, this is wrong: a
proposition is either provable or it is not. *)
(** 命題とブール値は、一見とてもよく似ているように見えます。しかしこの二つは根本的に違うものです！
- ブール値は、「計算の世界における値」です。 [bool] 型の式は全て、（自由変数を持っていない限り）必ず [true] か [false] のどちらかに簡約することができます。
- 命題は「論理の世界における型」です。これらは「証明可能（この型の式を書くことができる）」か、「証明不能（そのような式は存在しない）」かのいずれかです。従って「命題が [true] である」というような言い方は意味を持ちません。
我々は時折、命題に対してそれが "true" か "false" というようなことを言ってしまいがちですが、厳格に言えばこれは間違っています。命題は「証明可能かそうでないか」のどちらかです。 *)
(* ** Functions vs. Quantifiers *)
(** ** 関数 vs. 限量子 *)
(* The types [A->B] and [forall x:A, B] both describe functions from
[A] to [B]. The only difference is that, in the second case, the
expression [B] -- the type of the result -- can mention the
argument [x] by name. For example:
- The function [fun x:nat => x + x] has type [nat->nat] --
that is, it maps each number [n] to a number.
- The function [fun X:Type => nil (list X)] has type [forall
X:Type, list (list X)] -- that is, it maps each set [X] to a
particular list of lists of [X]s. (Of course, [nil] is
usually written as [[]] instead of [nil X].)
In fact, the two ways of writing function types are really the
same: In Coq, [A->B] is actually just an abbreviation for [forall
x:A, B], where [x] is some variable name not occurring in [B]. For
example, the type of [fun x:nat => x + x] can be written, if we
like, as [forall x:nat, nat]. *)
(** [A->B] という型も [forall x:A, B] という型も、どちらも型 [A] から型 [B] への関数である、という点については同じです。この二つの唯一の違いは、後者の場合戻り値の型 [B] が引数 [x] を参照できるということです。たとえば、
- 関数 [fun x:nat => x + x] は型 [nat->nat] を持っていますが、このことは任意の数 [n] を別の数に対応させるもの、ということです。
- 対して、関数 [fun X : Type => nil (list X)] は [forall
X : Type, list (list X)] という型になります。これは、任意の集合 [X] を、 [X] 型のリストのリストに対応させるもの、ということになります。（もちろん、[nil] は通常 [nil X] と書く代わりに [[]] と書くのが普通ですが。）
実際、関数を記述するためのこれら二つの書き方はほぼ同じですが、 Coq では [A->B] の書き方は、[x] が[B] の定義の中に変数として現れない限り、[fun x:nat => x + x] のただの省略形と考えていいでしょう。例えば、好みならばこれを [forall x:nat, nat] と書いてもいいのです。 *)
(** ** 関数 vs. 含意 *)
(* In both [Type] and [Prop], we can write functions that transform
values into other values. Also, functions themselves are values;
this means we can
- write higher-order functions that take functions as arguments
or return functions as results, and
- apply constructors to functions to build complex values
containing functions.
A function of type [P->Q] in [Prop] is something that takes
evidence for [P] as an argument and yields evidence for [Q] as its
result. Such a function can be regarded as _evidence_ that [P]
implies [Q], since, whenever we have evidence that [P] is true, we
can apply the function and get back evidence that [Q] is true:
evidence for an implication is a function on evidence. This is why
we use the same notation for functions and logical implications in
Coq: they are exactly the same thing! *)
(** [Type] にしろ [Prop] にしろ、我々はその値を別の値に変換する関数を書くことができます。 また、関数はそれ自身が値です。
このことは、我々が、次のようなことが出来ることを意味しています。
- 関数を引数にしたり、関数を戻り値にしたりする高階関数を書くこと。
- 関数をコンストラクタに適用し、関数を保持したさらに複雑な値を作り出すこと。
[Prop] 型を扱う [P->Q] という型の関数は、 [P] の根拠を引数にとり、新たな [Q] の根拠を結果として生成するものです。このような関数はそれ自身が「[P] ならば [Q] である」ということの根拠であると見なせます。そのことから、[P] が真であるという根拠があるなら、それを関数に適用して [Q] が真であるという根拠を得ることができます。含意に根拠を与えるということは、根拠の関数を与えるということと同じです。このことが、我々が Coq で関数と論理学の「含意」に同じ表記を与えている理由です。これらは全く同じものなのです。 *)
(* ####################################################### *)
(* * Informal Proofs *)
(** * 非形式的な証明 *)
(* Q: What is the relation between a formal proof of a proposition
[P] and an informal proof of the same proposition [P]?
A: The latter should _teach_ the reader how to produce the
former.
Q: How much detail is needed?
A: There is no single right answer; rather, there is a range
of choices.
At one end of the spectrum, we can essentially give the
reader the whole formal proof (i.e., the informal proof
amounts to just transcribing the formal one into words).
This gives the reader the _ability_ to reproduce the formal
one for themselves, but it doesn't _teach_ them anything.
At the other end of the spectrum, we can say "The theorem
is true and you can figure out why for yourself if you
think about it hard enough." This is also not a good
teaching strategy, because usually writing the proof
requires some deep insights into the thing we're proving,
and most readers will give up before they rediscover all
the same insights as we did.
In the middle is the golden mean -- a proof that includes
all of the essential insights (saving the reader the hard
part of work that we went through to find the proof in the
first place) and clear high-level suggestions for the more
routine parts to save the reader from spending too much
time reconstructing these parts (e.g., what the IH says and
what must be shown in each case of an inductive proof), but
not so much detail that the main ideas are obscured.
Another key point: if we're talking about a formal proof of a
proposition P and an informal proof of P, the proposition P doesn't
change. That is, formal and informal proofs are _talking about the
same world_ and they must _play by the same rules_. *)
(** Q: 命題 [P] の形式的な証明と、同じ命題 [P] の非形式的な証明の間にはどのような関係があるのでしょうか？
A: 後者は、読む人に「どのように形式的な証明を導くか」を示すようなものとなっているべきです。
Q: どの程度細かく書く必要があるのですか？
A: この問いに唯一と言えるような解答はありません。回答には選択の幅があります。
その範囲の片方の端は、読み手にただ形式的な証明全体を与えればよいという考えです。つまり非形式的な証明は、形式的な証明をただ単に普通の言葉で書き換えただけ 、ということです。この方法は、読み手に形式的な証明を書かせるための能力を与えることはできますが、それについて何かも「教えてくれる」訳ではありません。
これに対しもう一方の端は、「その定理は真で、頑張ればできるはず」ような記述です。この方法も、「教える」ということに関してはあまりいいやり方とはいえません。なぜなら、証明を記述するときはいつも、今証明しようとしているものの奥深くにまで目を向け考えることが必要とされますが、細かく書きすぎると証明を読む側の人の多くは自分自身の力で同じ思考にたどり着くことなく、あきらめて証明の記述に頼ってしまうでしょう。
一番の答えはその中間にあります。全ての要点をかいつまんだ証明というのは、「かつてあなたが証明をしたときに非常に苦労した部分について、読む人が同じ苦労をしなくて済むようになっている」ようなものです。そしてまた、読み手が同じような苦労を何時間もかけてする必要がないよう、証明の中で使える部品などを高度に示唆するものでなければなりません（例えば、仮定 IH が何を言っているかや、帰納的な証明のどの部分に現れるかなど）。しかし、詳細が少なすぎると、証明の主要なアイデアがうまく伝わりません。
もう一つのキーポイント：もし我々が命題 P の形式的な証明と非形式的な証明について話しているならば、命題 P 自体は何も変わりません。このことは、形式的な証明も非形式的な証明も、同じ「世界」について話をしていて、同じルールに基づいていなければならない、と言うことを意味しています。
*)
(* ####################################################### *)
(* ** Informal Proofs by Induction *)
(** ** 帰納法による非形式的な証明 *)
(* Since we've spent much of this chapter looking "under the hood" at
formal proofs by induction, now is a good moment to talk a little
about _informal_ proofs by induction.
In the real world of mathematical communication, written proofs
range from extremely longwinded and pedantic to extremely brief
and telegraphic. The ideal is somewhere in between, of course,
but while you are getting used to the style it is better to start
out at the pedantic end. Also, during the learning phase, it is
probably helpful to have a clear standard to compare against.
With this in mind, we offer two templates below -- one for proofs
by induction over _data_ (i.e., where the thing we're doing
induction on lives in [Type]) and one for proofs by induction over
_evidence_ (i.e., where the inductively defined thing lives in
[Prop]). In the rest of this course, please follow one of the two
for _all_ of your inductive proofs. *)
(** ここまで、我々は「帰納法を使った形式的な証明の舞台裏」を覗くことにずいぶん章を割いてきました。そろそろ「帰納法を使った非形式的な証明」に話を向けてみましょう。
現実世界の数学的な事柄をやりとりするた記述された証明を見てみると、極端に風呂敷が広く衒学的なものから、逆に短く簡潔すぎるものまで様々です。理想的なものはその間のとこかにあります。もちろん、じぶんなりのスタイルを見つけるまでは、衒学的なスタイルから始めてみるほうがいいでしょう。また、学習中には、標準的なテンプレートと比較してみることも、学習の一助になるでしょう。
このような考えから、我々は以下の二つのテンプレートを用意しました。一つは「データ」に対して（「型」に潜む帰納的な構造について）帰納法を適用したもの、もう一つは「命題」に対して（命題に潜む機能的な定義について）帰納法を適用したものです。このコースが終わるまでに、あなたが行った帰納的な証明の全てに、どちらかの方法を適用してみましょう。
*)
(* *** Induction Over an Inductively Defined Set *)
(** *** 帰納的に定義された集合についての帰納法 *)
(* _Template_:
- _Theorem_: <Universally quantified proposition of the form
"For all [n:S], [P(n)]," where [S] is some inductively defined
set.>
_Proof_: By induction on [n].
<one case for each constructor [c] of [S]...>
- Suppose [n = c a1 ... ak], where <...and here we state
the IH for each of the [a]'s that has type [S], if any>.
We must show <...and here we restate [P(c a1 ... ak)]>.
<go on and prove [P(n)] to finish the case...>
- <other cases similarly...> []
_Example_:
- _Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_: By induction on [l].
- Suppose [l = []]. We must show, for all numbers [n],
that, if length [[] = n], then [index (S n) [] =
None].
This follows immediately from the definition of index.
- Suppose [l = x :: l'] for some [x] and [l'], where
[length l' = n'] implies [index (S n') l' = None], for
any number [n']. We must show, for all [n], that, if
[length (x::l') = n] then [index (S n) (x::l') =
None].
Let [n] be a number with [length l = n]. Since
[[
length l = length (x::l') = S (length l'),
]]
it suffices to show that
[[
index (S (length l')) l' = None.
]]
But this follows directly from the induction hypothesis,
picking [n'] to be length [l']. [] *)
(** _Template_:
- 定理: < "For all [n:S], [P(n)],"の形で全量子化された命題。ただし [S] は帰納的に定義された集合。>
証明: [n] についての帰納法で証明する。
<集合 [S] の各コンストラクタ [c] について...>
- [n = c a1 ... ak] と仮定して、<...もし必要なら [S] のそれぞれの要素 [a] についてIHであることをを示す。>ならば
<...ここで再び [P(c a1 ... ak)] を示す> である。
< [P(n)] を証明してこのケースを終わらせる...>
- <他のケースも同様に記述する...> []
_Example_:
- _Theorem_: 任意の集合 [X] 、リスト [l : list X]、 自然数 [n] について、
もし [length l = n] が成り立つなら、[index (S n) l = None] も成り立つ。
_Proof_: [l] についての帰納法で証明する。
- まず、[l = []] と仮定して、任意の [n] でこれが成り立つことを示す。もし length [[] = n] ならば [index (S n) [] = None] 。
これは index の定義から直接導かれる 。
- 次に、 [x] と [l'] において [l = x :: l'] と仮定して、任意の [n'] について
[length l' = n'] ならば [index (S n') l' = None] である時、任意の [n] について、
もし [length (x::l') = n] ならば [index (S n) (x::l') = None] を示す。
[n] を [length l = n] となるような数とすると、
[[
length l = length (x::l') = S (length l'),
]]
これは以下の十分条件である。
[[
index (S (length l')) l' = None.
]]
しかしこれは帰納法の仮定から直接導かれる。
[l'] の length となるような [n'] を選択すればよい。 [] *)
(* *** Induction Over an Inductively Defined Proposition *)
(** *** 帰納的に定義された命題についての帰納法 *)
(* Since inductively defined proof objects are often called
"derivation trees," this form of proof is also known as _induction
on derivations_.
_Template_:
- _Theorem_: <Proposition of the form "[Q -> P]," where [Q] is
some inductively defined proposition (more generally,
"For all [x] [y] [z], [Q x y z -> P x y z]")>
_Proof_: By induction on a derivation of [Q]. <Or, more
generally, "Suppose we are given [x], [y], and [z]. We
show that [Q x y z] implies [P x y z], by induction on a
derivation of [Q x y z]"...>
<one case for each constructor [c] of [Q]...>
- Suppose the final rule used to show [Q] is [c]. Then
<...and here we state the types of all of the [a]'s
together with any equalities that follow from the
definition of the constructor and the IH for each of
the [a]'s that has type [Q], if there are any>. We must
show <...and here we restate [P]>.
<go on and prove [P] to finish the case...>
- <other cases similarly...> []
*)
(** 帰納的に定義された証明オブジェクトは、しばしば”導出木”と呼ばれるため、この形の証明は「導出による帰納法（ _induction on derivations_ ）」として知られています。
_Template_ :
- _Theorem_ : <"[Q -> P]," という形を持った命題。ただし [Q] は帰納的に定義された命題（さらに一般的には、"For all [x] [y] [z], [Q x y z -> P x y z]" という形の命題）>
_Proof_ : [Q] の導出による帰納法で証明する。 <もしくは、さらに一般化して、" [x], [y], [z]を仮定して、[Q x y z] ならば [P x y z] を示す。[Q x y z]の導出による帰納法によって"...>
<各コンストラクタ [c] による値 [Q] について...>
- [Q] が [c] であることを示した最後のルールを仮定して、
<...ここで [a] の全ての型をコンストラクタの定義にある等式と
共に示し、型 [Q] を持つ [a] がIHであることをそれぞれ示す。>
ならば <...ここで再び [P] を示す> である。
<がんばって [P] を証明し、このケースを閉じる...>
- <他のケースも同様に...> []
*)
(*
_Example_
- _Theorem_ : The [<=] relation is transitive -- i.e., for all
numbers [n], [m], and [o], if [n <= m] and [m <= o], then
[n <= o].
_Proof_: By induction on a derivation of [m <= o].
- Suppose the final rule used to show [m <= o] is
[le_n]. Then [m = o] and the result is immediate.
- Suppose the final rule used to show [m <= o] is
[le_S]. Then [o = S o'] for some [o'] with [m <= o'].
By induction hypothesis, [n <= o'].
But then, by [le_S], [n <= o]. [] *)
(**
_Example_
- _Theorem_ : [<=] という関係は推移的である -- すなわち、任意の
数値 [n], [m], [o] について、もし [n <= m] と [m <= o] が成り立つ
ならば [n <= o] である。
_Proof_ : [m <= o] についての帰納法で証明する。
- [m <= o] が [le_n] であることを示した最後のルールを仮定する。
それにより [m = o] であることとその結果が直接導かれる。
- [m <= o] が [le_S] であることを示した最後のルールを仮定する。
それにより [m <= o'] を満たす [o'] について [o = S o'] が成り立つ。
帰納法の仮定法より [n <= o'] である。
従って[le_S] より [n <= o] である。 [] *)
(* ##################################################### *)
(* * Optional Material *)
(** * 選択課題 *)
(* This section offers some additional details on how induction works
in Coq. It can safely be skimmed on a first reading. (We
recommend skimming rather than skipping over it outright: it
answers some questions that occur to many Coq users at some point,
so it is useful to have a rough idea of what's here.) *)
(** この項では、Coq において帰納法がどのように機能しているか、もう少し詳しく示していきたいと思います。
最初にこの項を読むときは、全体を読み流す感じでもかまいません（完全に
読み飛ばすのではなく、概要だけでも眺めてください。ここに書いてあることは、
多くの Coq ユーザーにとって、概要だけでも頭に入れておくことで、いつか直面する問題に
対する回答となりえるものです。） *)
(* ##################################################### *)
(* ** More on the [induction] Tactic *)
(** ** [induction] タクティックについてもう少し *)
(* The [induction] tactic actually does even more low-level
bookkeeping for us than we discussed above.
Recall the informal statement of the induction principle for
natural numbers:
- If [P n] is some proposition involving a natural number n, and
we want to show that P holds for _all_ numbers n, we can
reason like this:
- show that [P O] holds
- show that, if [P n'] holds, then so does [P (S n')]
- conclude that [P n] holds for all n.
So, when we begin a proof with [intros n] and then [induction n],
we are first telling Coq to consider a _particular_ [n] (by
introducing it into the context) and then telling it to prove
something about _all_ numbers (by using induction).
What Coq actually does in this situation, internally, is to
"re-generalize" the variable we perform induction on. For
example, in the proof above that [plus] is associative...
*)
(** [induction] タクティックは、実はこれまで見てきたような、いささか
低レベルな作業をこなすだけのものではありません。
自然数に関する帰納的な公理の非形式的な記述を思い出してみてください。:
- もし [P n] が数値 n を意味する何かの命題だとして、命題 P が全ての数値 n に
ついて成り立つことを示したい場合は、このような推論を
することができます。:
- [P O] が成り立つことを示す
- もし [P n'] が成り立つなら, [P (S n')] が成り立つことを示す。
- 任意の n について [P n] が成り立つと結論する。
我々が証明を [intros n] で始め、次に [induction n] とすると、
これはCoqに「特定の」 [n] について（それを仮定取り込むことで）考えて
から、その後でそれを帰納法を使って任意の数値にまで推し進めるよう
示していることになります。
このようなときに Coq が内部的に行っていることは、帰納法を適用した変数を
「再一般化（ _re-generalize_ ）」することです。
例えば、[plus] の結合則を証明するケースでは、
*)
Theorem plus_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
(* ...we first introduce all 3 variables into the context,
which amounts to saying "Consider an arbitrary [n], [m], and
[p]..." *)
(** ...最初に 3個の変数を全てコンテキストに導入しています。
これはつまり"任意の [n], [m], [p] について考える"という
意味になっています... *)
intros n m p.
(* ...We now use the [induction] tactic to prove [P n] (that
is, [n + (m + p) = (n + m) + p]) for _all_ [n],
and hence also for the particular [n] that is in the context
at the moment. *)
(** ...ここで、[induction] タクティックを使い [P n] （任意の [n] に
ついて [n + (m + p) = (n + m) + p]）を証明し、すぐに、
コンテキストにある特定の [n] についても証明します。 *)
induction n as [| n'].
Case "n = O". reflexivity.
Case "n = S n'".
(* In the second subgoal generated by [induction] -- the
"inductive step" -- we must prove that [P n'] implies
[P (S n')] for all [n']. The [induction] tactic
automatically introduces [n'] and [P n'] into the context
for us, leaving just [P (S n')] as the goal. *)
(** [induction] が作成した（帰納法の手順とも言うべき）二つ目の
ゴールでは、 [P n'] ならば任意の [n'] で [P (S n')] が成り立つ
ことを証明する必要があります。 この時に [induction] タクティックは
[P (S n')] をゴールにしたまま、自動的に [n'] と [P n'] を
コンテキストに導入してくれます。
*)
simpl. rewrite -> IHn'. reflexivity. Qed.
(* It also works to apply [induction] to a variable that is
quantified in the goal. *)
(** [induction] をゴールにある量化された変数に適用してもかまいません。 *)
Theorem plus_comm' : forall n m : nat,
n + m = m + n.
Proof.
induction n as [| n'].
Case "n = O". intros m. rewrite -> plus_0_r. reflexivity.
Case "n = S n'". intros m. simpl. rewrite -> IHn'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(* Note that [induction n] leaves [m] still bound in the goal --
i.e., what we are proving inductively is a statement beginning
with [forall m].
If we do [induction] on a variable that is quantified in the goal
_after_ some other quantifiers, the [induction] tactic will
automatically introduce the variables bound by these quantifiers
into the context. *)
(** [induction n] が [m] をゴールに残したままにしていることに注目してください。
つまり、今証明しようとしている帰納的な性質は、[forall m] で表されて
いるということです。
もし [induction] をゴールにおいて量化された変数に対して他の量化子の後に
適用すると、[induction] タクティックは自動的に変数をその量化子に基づいて
コンテキストに導入します。 *)
Theorem plus_comm'' : forall n m : nat,
n + m = m + n.
Proof.
(* Let's do induction on [m] this time, instead of [n]... *)
(** ここで [n] の代わりに [m] を induction しましょう。... *)
induction m as [| m'].
Case "m = O". simpl. rewrite -> plus_0_r. reflexivity.
Case "m = S m'". simpl. rewrite <- IHm'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** **** 練習問題: ★, optional (plus_explicit_prop) *)
(* Rewrite both [plus_assoc'] and [plus_comm'] and their proofs in
the same style as [mult_0_r''] above -- that is, for each theorem,
give an explicit [Definition] of the proposition being proved by
induction, and state the theorem and proof in terms of this
defined proposition. *)
(** [plus_assoc'] と [plus_comm'] を、その証明とともに上の [mult_0_r''] と
同じスタイルになるよう書き直しなさい。このことは、それぞれの定理が
帰納法で証明された命題に明確な定義を与え、この定義された命題から定理と
証明を示しています。 *)
(* FILL IN HERE *)
(** [] *)
(* ##################################################### *)
(* One more quick digression, for adventurous souls: if we can define
parameterized propositions using [Definition], then can we also
define them using [Fixpoint]? Of course we can! However, this
kind of "recursive parameterization" doesn't correspond to
anything very familiar from everyday mathematics. The following
exercise gives a slightly contrived example. *)
(** 冒険心を満足させるために、もう少し脱線してみましょう。
[Definition] でパラメータ化された命題を定義できるなら、 [Fixpoint] でも
定義できていいのではないでしょうか？もちろんできます！しかし、この種の
「再帰的なパラメータ化」は、日常的に使われる数学の分野と必ずしも調和するわけでは
ありません。そんなわけで次の練習問題は、例としてはいささか不自然かもしれません。
*)
(* **** Exercise: 4 stars, optional (true_upto_n__true_everywhere) *)
(** **** 練習問題: ★★★★, optional (true_upto_n__true_everywhere) *)
(* Define a recursive function
[true_upto_n__true_everywhere] that makes
[true_upto_n_example] work. *)
(** [true_upto_n_example] を満たすような再帰関数 [true_upto_n__true_everywhere]
を定義しなさい。
*)
(*
Fixpoint true_upto_n__true_everywhere
(* FILL IN HERE *)
Example true_upto_n_example :
(true_upto_n__true_everywhere 3 (fun n => even n))
= (even 3 -> even 2 -> even 1 -> forall m : nat, even m).
Proof. reflexivity. Qed.
*)
(** [] *)
(* ##################################################### *)
(* ** Induction Principles in [Prop] *)
(** ** [Prop] における帰納法の原理 *)
(* Earlier, we looked in detail at the induction principles that Coq
generates for inductively defined _sets_. The induction principles
for inductively defined _propositions_ like [ev] are a tiny bit
more complicated. As with all induction principles, we want to use
the induction principle on [ev] to prove things by inductively
considering the possible shapes that something in [ev] can have --
either it is evidence that [0] is even, or it is evidence that,
for some [n], [S (S n)] is even, and it includes evidence that [n]
itself is. Intuitively speaking, however, what we want to prove
are not statements about _evidence_ but statements about _numbers_.
So we want an induction principle that lets us prove properties of
numbers by induction on evidence.
For example, from what we've said so far, you might expect the
inductive definition of [ev]...
[[
Inductive ev : nat -> Prop :=
| ev_0 : ev O
| ev_SS : forall n:nat, ev n -> ev (S (S n)).
]]
...to give rise to an induction principle that looks like this...
[[
ev_ind_max :
forall P : (forall n : nat, ev n -> Prop),
P O ev_0 ->
(forall (n : nat) (e : ev n),
P n e -> P (S (S n)) (ev_SS n e)) ->
forall (n : nat) (e : ev n), P n e
]]
... because:
- Since [ev] is indexed by a number [n] (every [ev] object
[e] is a piece of evidence that some particular number [n]
is even), the proposition [P] is parameterized by both [n]
and [e] -- that is, the induction principle can be used to
prove assertions involving both an even number and the
evidence that it is even.
- Since there are two ways of giving evidence of evenness
([ev] has two constructors), applying the induction
principle generates two subgoals:
- We must prove that [P] holds for [O] and [ev_0].
- We must prove that, whenever [n] is an even number and
[e] is evidence of its evenness, if [P] holds of [n]
and [e], then it also holds of [S (S n)] and [ev_SS n
e].
- If these subgoals can be proved, then the induction
principle tells us that [P] is true for _all_ even numbers
[n] and evidence [e] of their evenness.
But this is a little more flexibility than we actually need or
want: it is giving us a way to prove logical assertions where the
assertion involves properties of some piece of _evidence_ of
evenness, while all we really care about is proving properties of
_numbers_ that are even -- we are interested in assertions about
numbers, not about evidence. It would therefore be more convenient
to have an induction principle for proving propositions [P] that
are parameterized just by [n] and whose conclusion establishes [P]
for all even numbers [n]:
[[
forall P : nat -> Prop,
... ->
forall n : nat, ev n -> P n
]]
For this reason, Coq actually generates the following simplified
induction principle for [ev]: *)
(** 最初のほうで、我々は帰納的に定義された「集合」に対して、Coqが生成する
帰納法の原理をつぶさに見てきました。[ev] のように、帰納的に定義された
「命題」の帰納法の原理は、やや複雑でした。これらに共通して言えることですが、
これらを [ev] の証明に使おうとする際、帰納的な発想のもとで [ev] が持ちうる
ものの中から使えそうな形になっているものを探します。それは [0] が偶数であることの
根拠であったり、ある [n] について [S (S n)] は偶数であるという根拠（もちろん、
これには [n] 自身が偶数であるということの根拠も含まれていなければ
なりませんが）だったりするでしょう。しかしながら直観的な言い方をすると、
我々が証明したいものは根拠についての事柄ではなく、数値についての事柄です。
つまり、我々は根拠をベースに数値の属性を証明できるような帰納法の原理を
必要としているわけです。
例えば、ずいぶん前にお話ししたように、[ev] の帰納的な定義は、
こんな感じで...
[[
Inductive ev : nat -> Prop :=
| ev_0 : ev O
| ev_SS : forall n:nat, ev n -> ev (S (S n)).
]]
... ここから生成される帰納法の原理はこんな風になります ...
[[
ev_ind_max :
forall P : (forall n : nat, ev n -> Prop),
P O ev_0 ->
(forall (n : nat) (e : ev n),
P n e -> P (S (S n)) (ev_SS n e)) ->
forall (n : nat) (e : ev n), P n e
]]
... なぜなら：
- [ev] は数値 [n] でインデックスされている（ [ev] に属するオブジェクト [e] は、いずれも特定の数 [n] が偶数であることの根拠となっている）ため、この命題 [P] は [n] と[e] の両方でパラメータ化されている。-- つまり、この帰納法の原理は一つの偶数と、それが偶数であることの根拠が揃っているような主張の証明に使われる。
- 偶数であることに根拠を与える方法は二つある（ [ev] のコンストラクタは二つある）ので、帰納法の原理を適用すると、二つのゴールが生成されます。:
- [P] が [O] と [ev_0] で成り立つことを証明する必要がある。
- [n] が偶数で [e] がその偶数性の根拠であるとき、もし [P] が [n] と [e] のもとで成り立つなら、[S (S n)] と [ev_SS n e] のもとで成り立つことを証明する必要がある。
- もしこれらのサブゴールが証明できれば、この帰納法の原理によって [P] が全ての偶数 [n] とその偶数性の根拠 [e] のもとで真であることが示される。
しかしこれは、私たちが求めたり必要としているものより少しだけ柔軟にできていて、偶数性の根拠の断片を属性として含むような論理的主張を証明する方法を与えてくれます。我々の興味の対象は「数値の属性が偶数である」ことの証明なのですから、その興味の対象も数値に関する主張であって、根拠に対するものではないはずです。これにより、単に [n] だけでパラメータ化されていて、[P] がすべての偶数 [n] で成り立つことを示せるような命題 [P] を証明する際に帰納法の原理を得ることがより楽になります。
[[
forall P : nat -> Prop,
... ->
forall n : nat, ev n -> P n
]]
このような理由で、Coqは実際には [ev] のために次のような帰納法の原理を生成します。: *)
Check ev_ind.
(* ===> ev_ind
: forall P : nat -> Prop,
P 0 ->
(forall n : nat, ev n -> P n -> P (S (S n))) ->
forall n : nat, ev n -> P n *)
(* In particular, Coq has dropped the evidence term [e] as a parameter
of the the proposition [P], and consequently has rewritten the
assumption [forall (n:nat) (e:ev n), ...] to be [forall (n:nat), ev
n -> ...]; i.e., we no longer require explicit evidence of the
provability of [ev n]. *)
(** Coqが根拠の式 [e] を、命題 [P] のパラメータから取り去っていることに注目してください。
その結果として、仮定 [forall (n:nat) (e:ev n), ...] を [forall (n:nat), ev
n -> ...] に書き換えています。すなわち、我々はすでに [ev n] から証明可能であることの
明白な根拠を求められていないのです。 *)
(* In English, [ev_ind] says:
- Suppose, [P] is a property of natural numbers (that is, [P
n] is a [Prop] for every [n]). To show that [P n] holds
whenever [n] is even, it suffices to show:
- [P] holds for [0]
- for any [n], if [n] is even and [P] holds for [n],
then [P] holds for [S (S n)]. *)
(** [ev_ind] を自然言語で書き直すと、
- [P] が自然数の属性である（つまり、[P] が全ての [n] についての命題である）と仮定し、[P n] が偶数の場合常に成り立つことを示す。これは、以下を示すのに十分である。:
- [P] が [0] において成り立つ。
- 全ての [n] において、もし [n] が偶数で [P] が [n] において成り立つなら、[P] は [S (S n)] においても成り立つ。 *)
(* We can apply [ev_ind] directly instead of using [induction],
following pretty much the same pattern as above. *)
(** [induction] とする代わりに [ev_ind] を直接 apply することもできます。
以下は、これと同じパターンです。 *)
Theorem ev_even' : forall n,
ev n -> even n.
Proof.
apply ev_ind.
Case "ev_0". unfold even. reflexivity.
Case "ev_SS". intros n' E' IHE'. unfold even. apply IHE'. Qed.
(* **** Exercise: 3 stars, optional (prop_ind) *)
(** **** 練習問題: ★★★, optional (prop_ind) *)
(* Write out the induction principles that Coq will generate for the
inductive declarations [list] and [MyProp]. Compare your answers
against the results Coq prints for the following queries. *)
(** 帰納的に定義された [list] と [MyProp] に対し、Coq がどのような帰納法の原理を
生成するか、予想して書き出し、次の行を実行した結果と比較しなさい。 *)
Check list_ind.
Check MyProp_ind.
(** [] *)
(* **** Exercise: 3 stars, optional (ev_MyProp') *)
(** **** 練習問題: ★★★, optional (ev_MyProp') *)
(* Prove [ev_MyProp] again, using [apply MyProp_ind] instead
of the [induction] tactic. *)
(** もう一度 [ev_MyProp] を証明しなさい。ただし、今度は [induction] タクティックの代わりに
[apply MyProp_ind] を使いなさい。 *)
Theorem ev_MyProp' : forall n:nat,
MyProp n -> ev n.
Proof.
apply MyProp_ind.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 4 stars, optional (MyProp_pfobj) *)
(** **** 練習問題: ★★★★, optional (MyProp_pfobj) *)
(* Prove [MyProp_ev] and [ev_MyProp] again by constructing
explicit proof objects by hand (as you did above in
[ev_plus4], for example). *)
(** もう一度 [MyProp_ev] と [ev_MyProp] を証明しなさい。ただし今度は、明確な
証明オブジェクトを手作業で構築（上の [ev_plus4] でやったように）することで
証明しなさい。 *)
(* FILL IN HERE *)
(** [] *)
Module P.
(* **** Exercise: 3 stars, optional (p_provability) *)
(** **** 練習問題: ★★★, optional (p_provability) *)
(* Consider the following inductively defined proposition: *)
(** 次の、帰納的に定義された命題について考えてみてください。： *)
Inductive p : (tree nat) -> nat -> Prop :=
| c1 : forall n, p (leaf _ n) 1
| c2 : forall t1 t2 n1 n2,
p t1 n1 -> p t2 n2 -> p (node _ t1 t2) (n1 + n2)
| c3 : forall t n, p t n -> p t (S n).
(* Describe, in English, the conditions under which the
proposition [p t n] is provable.
(* FILL IN HERE *)
*)
(** これについて、どのような時に [p t n] が証明可能であるか、その
条件をを自然言語で説明しなさい。
(* FILL IN HERE *)
*)
(** [] *)
End P.
(* ####################################################### *)
(* * Additional Exercises *)
(** * 追加練習問題 *)
(* **** Exercise: 4 stars (palindromes) *)
(** **** 練習問題: ★★★★ (palindromes) *)
(* A palindrome is a sequence that reads the same backwards as
forwards.
- Define an inductive proposition [pal] on [list X] that
captures what it means to be a palindrome. (Hint: You'll need
three cases. Your definition should be based on the structure
of the list; just having a single constructor
[[
c : forall l, l = rev l -> pal l
]]
may seem obvious, but will not work very well.)
- Prove that
[[
forall l, pal (l ++ rev l).
]]
- Prove that
[[
forall l, pal l -> l = rev l.
]]
*)
(** palindrome（回文）は、最初から読んでも逆から読んでも同じになるような
シーケンスです。
- [list X] でパラメータ化され、それが palindrome であることを示すような帰納的
命題 [pal] を定義しなさい。（ヒント：これには三つのケースが必要です。この定義は、
リストの構造に基いたものとなるはずです。まず一つのコンストラクタ、
[[
c : forall l, l = rev l -> pal l
]]
は明らかですが、これはあまりうまくいきません。）
- 以下を証明しなさい。
[[
forall l, pal (l ++ rev l).
]]
- 以下を証明しなさい。
[[
forall l, pal l -> l = rev l.
]]
*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 5 stars, optional (palindrome_converse) *)
(** **** 練習問題: ★★★★★, optional (palindrome_converse) *)
(* Using your definition of [pal] from the previous exercise, prove
that
[[
forall l, l = rev l -> pal l.
]]
*)
(** 一つ前の練習問題で定義した [pal] を使って、これを証明しなさい。
[[
forall l, l = rev l -> pal l.
]]
*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 4 stars (subsequence) *)
(** **** 練習問題: ★★★★ (subsequence) *)
(* A list is a _subsequence_ of another list if all of the elements
in the first list occur in the same order in the second list,
possibly with some extra elements in between. For example,
[[
[1,2,3]
]]
is a subsequence of each of the lists
[[
[1,2,3]
[1,1,1,2,2,3]
[1,2,7,3]
[5,6,1,9,9,2,7,3,8]
]]
but it is _not_ a subsequence of any of the lists
[[
[1,2]
[1,3]
[5,6,2,1,7,3,8]
]]
- Define an inductive proposition [subseq] on [list nat] that
captures what it means to be a subsequence. (Hint: You'll need
three cases.)
- Prove that subsequence is reflexive, that is, any list is a
subsequence of itself.
- Prove that for any lists [l1], [l2], and [l3], if [l1] is a
subsequence of [l2], then [l1] is also a subsequence of [l2 ++
l3].
- (Optional, harder) Prove that subsequence is transitive -- that
is, if [l1] is a subsequence of [l2] and [l2] is a subsequence
of [l3], then [l1] is a subsequence of [l3]. Hint: choose your
induction carefully!
*)
(** あるリストが、別のリストのサブシーケンス（ _subsequence_ ）であるとは、
最初のリストの要素が全て二つ目のリストに同じ順序で現れるということです。
ただし、その間に何か別の要素が入ってもかまいません。例えば、
[[
[1,2,3]
]]
は、次のいずれのリストのサブシーケンスでもあります。
[[
[1,2,3]
[1,1,1,2,2,3]
[1,2,7,3]
[5,6,1,9,9,2,7,3,8]
]]
しかし、次のいずれのリストのサブシーケンスでもありません。
[[
[1,2]
[1,3]
[5,6,2,1,7,3,8]
]]
- [list nat] 上に、そのリストがサブシーケンスであることを意味するような命題 [subseq] を定義しなさい。（ヒント：三つのケースが必要になります）
- サブシーケンスである、という関係が「反射的」であることを証明しなさい。つまり、どのようなリストも、それ自身のサブシーケンスであるということです。
- 任意のリスト [l1]、 [l2]、 [l3] について、もし [l1] が [l2] のサブシーケンスならば、 [l1] は [l2 ++ l3] のサブシーケンスでもある、ということを証明しなさい。.
- （これは少し難しいですので、任意とします）サブシーケンスという関係は推移的である、つまり、 [l1] が [l2] のサブシーケンスであり、 [l2] が [l3] のサブシーケンスであるなら、 [l1] は [l3] のサブシーケンスである、というような関係であることを証明しなさい。（ヒント：何について帰納法を適用するか、よくよく注意して下さい。）
*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 2 stars, optional (foo_ind_principle) *)
(** **** 練習問題: ★★, optional (foo_ind_principle) *)
(* Suppose we make the following inductive definition:
[[
Inductive foo (X : Set) (Y : Set) : Set :=
| foo1 : X -> foo X Y
| foo2 : Y -> foo X Y
| foo3 : foo X Y -> foo X Y.
]]
Fill in the blanks to complete the induction principle that will be
generated by Coq.
[[
foo_ind
: forall (X Y : Set) (P : foo X Y -> Prop),
(forall x : X, __________________________________) ->
(forall y : Y, __________________________________) ->
(________________________________________________) ->
________________________________________________
]]
*)
(** 次のような、帰納的な定義をしたとします：
[[
Inductive foo (X : Set) (Y : Set) : Set :=
| foo1 : X -> foo X Y
| foo2 : Y -> foo X Y
| foo3 : foo X Y -> foo X Y.
]]
次の空欄を埋め、この定義のために Coq が生成する帰納法の原理を完成させなさい。
[[
foo_ind
: forall (X Y : Set) (P : foo X Y -> Prop),
(forall x : X, __________________________________) ->
(forall y : Y, __________________________________) ->
(________________________________________________) ->
________________________________________________
]]
*)
(** [] *)
(** **** 練習問題: ★★, optional (bar_ind_principle) *)
(* Consider the following induction principle:
[[
bar_ind
: forall P : bar -> Prop,
(forall n : nat, P (bar1 n)) ->
(forall b : bar, P b -> P (bar2 b)) ->
(forall (b : bool) (b0 : bar), P b0 -> P (bar3 b b0)) ->
forall b : bar, P b
]]
Write out the corresponding inductive set definition.
[[
Inductive bar : Set :=
| bar1 : ________________________________________
| bar2 : ________________________________________
| bar3 : ________________________________________.
]]
*)
(** 次に挙げた帰納法の原理について考えてみましょう：
[[
bar_ind
: forall P : bar -> Prop,
(forall n : nat, P (bar1 n)) ->
(forall b : bar, P b -> P (bar2 b)) ->
(forall (b : bool) (b0 : bar), P b0 -> P (bar3 b b0)) ->
forall b : bar, P b
]]
これに対応する帰納的な集合の定義を書きなさい。
[[
Inductive bar : Set :=
| bar1 : ________________________________________
| bar2 : ________________________________________
| bar3 : ________________________________________.
]]
*)
(** [] *)
(* **** Exercise: 2 stars, optional (no_longer_than_ind) *)
(** **** 練習問題: ★★, optional (no_longer_than_ind) *)
(* Given the following inductively defined proposition:
[[
Inductive no_longer_than (X : Set) : (list X) -> nat -> Prop :=
| nlt_nil : forall n, no_longer_than X [] n
| nlt_cons : forall x l n, no_longer_than X l n ->
no_longer_than X (x::l) (S n)
| nlt_succ : forall l n, no_longer_than X l n ->
no_longer_than X l (S n).
]]
write the induction principle generated by Coq.
[[
no_longer_than_ind
: forall (X : Set) (P : list X -> nat -> Prop),
(forall n : nat, ____________________) ->
(forall (x : X) (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
(forall (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
forall (l : list X) (n : nat), no_longer_than X l n ->
____________________
]]
*)
(** 次のような、帰納的に定義された命題が与えられたとします：
[[
Inductive no_longer_than (X : Set) : (list X) -> nat -> Prop :=
| nlt_nil : forall n, no_longer_than X [] n
| nlt_cons : forall x l n, no_longer_than X l n ->
no_longer_than X (x::l) (S n)
| nlt_succ : forall l n, no_longer_than X l n ->
no_longer_than X l (S n).
]]
この命題のために Coq が生成する帰納法の原理を完成させなさい。
[[
no_longer_than_ind
: forall (X : Set) (P : list X -> nat -> Prop),
(forall n : nat, ____________________) ->
(forall (x : X) (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
(forall (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
forall (l : list X) (n : nat), no_longer_than X l n ->
____________________
]]
*)
(** [] *)
(* **** Exercise: 2 stars, optional (R_provability) *)
(** **** 練習問題: ★★, optional (R_provability) *)
(* Suppose we give Coq the following definition:
[[
Inductive R : nat -> list nat -> Prop :=
| c1 : R 0 []
| c2 : forall n l, R n l -> R (S n) (n :: l)
| c3 : forall n l, R (S n) l -> R n l.
]]
Which of the following propositions are provable?
- [R 2 [1,0]]
- [R 1 [1,2,1,0]]
- [R 6 [3,2,1,0]]
*)
(** Coq に次のような定義を与えたとします：
[[
Inductive R : nat -> list nat -> Prop :=
| c1 : R 0 []
| c2 : forall n l, R n l -> R (S n) (n :: l)
| c3 : forall n l, R (S n) l -> R n l.
]]
次のうち、証明可能なのはどの命題でしょうか？
- [R 2 [1,0]]
- [R 1 [1,2,1,0]]
- [R 6 [3,2,1,0]]
*)
(** [] *)
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: busdelay.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: Delay any access to the wishbone bus by a single clock.
//
// When the first Zip System would not meet the timing requirements of
// the board it was placed upon, this bus delay was added to help out.
// It may no longer be necessary, having cleaned some other problems up
// first, but it will remain here as a means of alleviating timing
// problems.
//
// The specific problem takes place on the stall line: a wishbone master
// *must* know on the first clock whether or not the bus will stall.
//
//
// After a period of time, I started a new design where the timing
// associated with this original bus clock just wasn't ... fast enough.
// I needed to delay the stall line as well. A new busdelay was then
// written and debugged whcih delays the stall line. (I know, you aren't
// supposed to delay the stall line--but what if you *have* to in order
// to meet timing?) This new logic has been merged in with the old,
// and the DELAY_STALL line can be set to non-zero to use it instead
// of the original logic. Don't use it if you don't need it: it will
// consume resources and slow your bus down more, but if you do need
// it--don't be afraid to use it.
//
// Both versions of the bus delay will maintain a single access per
// clock when pipelined, they only delay the time between the strobe
// going high and the actual command being accomplished.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module busdelay(i_clk,
// The input bus
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
o_wb_ack, o_wb_stall, o_wb_data, o_wb_err,
// The delayed bus
o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr,o_dly_data,o_dly_sel,
i_dly_ack, i_dly_stall, i_dly_data, i_dly_err);
parameter AW=32, DW=32, DELAY_STALL = 0;
input wire i_clk;
// Input/master bus
input wire i_wb_cyc, i_wb_stb, i_wb_we;
input wire [(AW-1):0] i_wb_addr;
input wire [(DW-1):0] i_wb_data;
input wire [(DW/8-1):0] i_wb_sel;
output reg o_wb_ack;
output wire o_wb_stall;
output reg [(DW-1):0] o_wb_data;
output wire o_wb_err;
// Delayed bus
output reg o_dly_cyc, o_dly_stb, o_dly_we;
output reg [(AW-1):0] o_dly_addr;
output reg [(DW-1):0] o_dly_data;
output reg [(DW/8-1):0] o_dly_sel;
input wire i_dly_ack;
input wire i_dly_stall;
input wire [(DW-1):0] i_dly_data;
input wire i_dly_err;
generate
if (DELAY_STALL != 0)
begin
reg r_stb, r_we, r_rtn_stall, r_rtn_err;
reg [(AW-1):0] r_addr;
reg [(DW-1):0] r_data;
reg [(DW/8-1):0] r_sel;
initial o_dly_cyc = 1'b0;
initial r_rtn_stall= 1'b0;
initial r_stb = 1'b0;
always @(posedge i_clk)
begin
o_dly_cyc <= (i_wb_cyc);
if (!i_dly_stall)
begin
r_we <= i_wb_we;
r_addr <= i_wb_addr;
r_data <= i_wb_data;
r_sel <= i_wb_sel;
if (r_stb)
begin
o_dly_we <= r_we;
o_dly_addr <= r_addr;
o_dly_data <= r_data;
o_dly_sel <= r_sel;
o_dly_stb <= 1'b1;
end else begin
o_dly_we <= i_wb_we;
o_dly_addr <= i_wb_addr;
o_dly_data <= i_wb_data;
o_dly_sel <= i_wb_sel;
o_dly_stb <= i_wb_stb;
end
r_stb <= 1'b0;
end else if (!o_dly_stb)
begin
o_dly_we <= i_wb_we;
o_dly_addr <= i_wb_addr;
o_dly_data <= i_wb_data;
o_dly_sel <= i_wb_sel;
o_dly_stb <= i_wb_stb;
end else if ((!r_stb)&&(!o_wb_stall))
begin
r_we <= i_wb_we;
r_addr <= i_wb_addr;
r_data <= i_wb_data;
r_sel <= i_wb_sel;
r_stb <= i_wb_stb;
end
if (!i_wb_cyc)
begin
o_dly_stb <= 1'b0;
r_stb <= 1'b0;
end
o_wb_ack <= (i_dly_ack)&&(i_wb_cyc)&&(o_dly_cyc);
o_wb_data <= i_dly_data;
r_rtn_err <= (i_dly_err)&&(i_wb_cyc)&&(o_dly_cyc);
end
assign o_wb_stall = r_stb;
assign o_wb_err = r_rtn_err;
end else begin
initial o_dly_cyc = 1'b0;
initial o_dly_stb = 1'b0;
always @(posedge i_clk)
o_dly_cyc <= i_wb_cyc;
// Add the i_wb_cyc criteria here, so we can simplify the
// o_wb_stall criteria below, which would otherwise *and*
// these two.
always @(posedge i_clk)
if (!o_wb_stall)
o_dly_stb <= ((i_wb_cyc)&&(i_wb_stb));
always @(posedge i_clk)
if (!o_wb_stall)
o_dly_we <= i_wb_we;
always @(posedge i_clk)
if (!o_wb_stall)
o_dly_addr<= i_wb_addr;
always @(posedge i_clk)
if (!o_wb_stall)
o_dly_data <= i_wb_data;
always @(posedge i_clk)
if (!o_wb_stall)
o_dly_sel <= i_wb_sel;
always @(posedge i_clk)
o_wb_ack <= (i_dly_ack)&&(o_dly_cyc)&&(i_wb_cyc);
always @(posedge i_clk)
o_wb_data <= i_dly_data;
// Our only non-delayed line, yet still really delayed. Perhaps
// there's a way to register this?
// o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
// assign o_wb_stall=((i_wb_cyc)&&(i_dly_stall)&&(o_dly_stb));//&&o_cyc
assign o_wb_stall = ((i_dly_stall)&&(o_dly_stb));//&&o_cyc
assign o_wb_err = i_dly_err;
end endgenerate
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : OBUFDS_GTE3_ADV.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 08/28/2013 - Initial model
// 06/02/14 - New simulation library message format.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OBUFDS_GTE3_ADV #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter [4:0] REFCLK_ICNTL_TX = 5'b00000
)(
output O,
output OB,
input CEB,
input [3:0] I,
input [1:0] RXRECCLK_SEL
);
// define constants
localparam MODULE_NAME = "OBUFDS_GTE3_ADV";
reg I_delay;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
localparam [4:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX;
`endif
wire REFCLK_EN_TX_PATH_BIN;
wire [4:0] REFCLK_ICNTL_TX_BIN;
tri0 GTS = glbl.GTS;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFDS_GTE3_ADV_dr.v"
`endif
assign REFCLK_EN_TX_PATH_BIN = REFCLK_EN_TX_PATH_REG;
assign REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG;
wire t1;
wire t2;
or O1 (t1, GTS, CEB);
or O2 (t2, ~REFCLK_EN_TX_PATH_BIN, t1);
// =====================
// Generate I_delay
// =====================
always @(*) begin
case (RXRECCLK_SEL)
2'b00: I_delay <= I[0];
2'b01: I_delay <= I[1];
2'b10: I_delay <= I[2];
2'b11: I_delay <= I[3];
default : I_delay <= I[0];
endcase
end
bufif0 B1 (O, I_delay, t2);
notif0 N1 (OB, I_delay, t2);
specify
(I[0] => O) = (0:0:0, 0:0:0);
(I[0] => OB) = (0:0:0, 0:0:0);
(I[1] => O) = (0:0:0, 0:0:0);
(I[1] => OB) = (0:0:0, 0:0:0);
(I[2] => O) = (0:0:0, 0:0:0);
(I[2] => OB) = (0:0:0, 0:0:0);
(I[3] => O) = (0:0:0, 0:0:0);
(I[3] => OB) = (0:0:0, 0:0:0);
(CEB => O) = (0:0:0, 0:0:0);
(CEB => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:52:03 2016
/////////////////////////////////////////////////////////////
module GDA_St_N8_M8_P2 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36,
n37, n38, n39, n40;
CLKAND2X2TS U25 ( .A(in2[0]), .B(in1[0]), .Y(n25) );
OAI21XLTS U26 ( .A0(in1[3]), .A1(in2[3]), .B0(n34), .Y(n29) );
AOI31XLTS U27 ( .A0(n28), .A1(in2[1]), .A2(in1[1]), .B0(n27), .Y(n30) );
AOI2BB2XLTS U28 ( .B0(n34), .B1(n31), .A0N(in1[3]), .A1N(in2[3]), .Y(n32) );
OAI21XLTS U29 ( .A0(in2[5]), .A1(in1[5]), .B0(n37), .Y(n36) );
OAI21XLTS U30 ( .A0(n34), .A1(n33), .B0(n38), .Y(n35) );
AOI2BB2XLTS U31 ( .B0(n38), .B1(n37), .A0N(in2[5]), .A1N(in1[5]), .Y(n40) );
AOI2BB1XLTS U32 ( .A0N(in2[0]), .A1N(in1[0]), .B0(n25), .Y(res[0]) );
NAND2X1TS U33 ( .A(in2[5]), .B(in1[5]), .Y(n37) );
NAND2X1TS U34 ( .A(in1[6]), .B(in2[6]), .Y(n23) );
OAI21X1TS U35 ( .A0(in1[6]), .A1(in2[6]), .B0(n23), .Y(n39) );
OAI2BB2XLTS U36 ( .B0(n37), .B1(n39), .A0N(in1[6]), .A1N(in2[6]), .Y(n24) );
CMPR32X2TS U37 ( .A(in2[7]), .B(in1[7]), .C(n24), .CO(res[8]), .S(res[7]) );
NAND2X1TS U38 ( .A(in1[2]), .B(in2[2]), .Y(n31) );
OA21XLTS U39 ( .A0(in1[2]), .A1(in2[2]), .B0(n31), .Y(n28) );
CMPR32X2TS U40 ( .A(in1[1]), .B(in2[1]), .C(n25), .CO(n26), .S(res[1]) );
XOR2XLTS U41 ( .A(n28), .B(n26), .Y(res[2]) );
INVX2TS U42 ( .A(n31), .Y(n27) );
NAND2X1TS U43 ( .A(in1[3]), .B(in2[3]), .Y(n34) );
XOR2XLTS U44 ( .A(n30), .B(n29), .Y(res[3]) );
NAND2X1TS U45 ( .A(in1[4]), .B(in2[4]), .Y(n38) );
OAI21X1TS U46 ( .A0(in1[4]), .A1(in2[4]), .B0(n38), .Y(n33) );
XNOR2X1TS U47 ( .A(n32), .B(n33), .Y(res[4]) );
XNOR2X1TS U48 ( .A(n36), .B(n35), .Y(res[5]) );
XNOR2X1TS U49 ( .A(n40), .B(n39), .Y(res[6]) );
initial $sdf_annotate("GDA_St_N8_M8_P2_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_PP_V |
module transmision (input enable,
input wire [7:0] din,
output busy,
output reg done,
input wire clk_div,
output reg tx);
parameter count = 8;
initial begin
tx <= 1'b1;
done=0;
end
parameter STATE_IDLE = 2'b00;
//parameter STATE_START = 2'b01;
parameter STATE_DATA = 2'b10;
parameter STATE_STOP = 2'b11;
reg [7:0] data = 8'b11111111;
reg [2:0] bitpos = 0;
reg [1:0] state = STATE_IDLE;
always @(posedge clk_div) begin
case (state)
STATE_IDLE: begin
done<=0;
tx <= 1'b1;
if(enable & ~busy)begin
// state <= STATE_START;
tx<=1'b0;
data <= din;
bitpos <= 0;
state<=STATE_DATA;
end
end
//STATE_START: begin
//tx <= 1'b0;
//state <= STATE_DATA;
//end
STATE_DATA: begin
if (bitpos == count-1)begin
tx<=data[bitpos];
state <= STATE_STOP;
end
else begin
tx<=data[bitpos];
bitpos <= bitpos + 1;
end
end
STATE_STOP: begin
tx <= 1'b1;
done<=1;
state <= STATE_IDLE;
end
default: begin
tx <= 1'b1;
state <= STATE_IDLE;
end
endcase
end
assign busy = (state != STATE_IDLE);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ucb_noflow.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: ucb_noflow
// Description: Unit Control Block
// - supports 64 or 128-bit read with flow control
// - supports 64-bit write without flow control
// - automactically drops non-64-bit writes
// - supports interrupt return to IO Bridge
// - provides only single buffer at each interface
//
// This module is intended for units that have
// both 64 and 128 bit registers.
//
// Data bus width to and from the IO Bridge is
// configured through parameters UCB_IOB_WIDTH and
// IOB_UCB_WIDTH. Supported widths are:
//
// IOB_UCB_WIDTH UCB_IOB_WIDTH
// ----------------------------
// 32 8
// 16 8
// 8 8
// 4 4
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which
// contains the time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module ucb_noflow (/*AUTOARG*/
// Outputs
ucb_iob_stall, rd_req_vld, wr_req_vld, thr_id_in, buf_id_in,
size_in, addr_in, data_in, int_busy, ucb_iob_vld, ucb_iob_data,
// Inputs
clk, rst_l, iob_ucb_vld, iob_ucb_data, rd_ack_vld, rd_nack_vld,
thr_id_out, buf_id_out, data128, data_out, int_vld, int_typ,
int_thr_id, dev_id, int_stat, int_vec, iob_ucb_stall
);
// synopsys template
parameter IOB_UCB_WIDTH = 32; // data bus width from IOB to UCB
parameter UCB_IOB_WIDTH = 8; // data bus width from UCB to IOB
parameter REG_WIDTH = 64; // set this to 128 if unit needs to
// return 128-bit data
// Globals
input clk;
input rst_l;
// Request from IO Bridge
input iob_ucb_vld;
input [IOB_UCB_WIDTH-1:0] iob_ucb_data;
output ucb_iob_stall;
// Request to local unit
output rd_req_vld;
output wr_req_vld;
output [`UCB_THR_HI-`UCB_THR_LO:0] thr_id_in;
output [`UCB_BUF_HI-`UCB_BUF_LO:0] buf_id_in;
output [`UCB_SIZE_HI-`UCB_SIZE_LO:0] size_in; // only pertinent to PCI
output [`UCB_ADDR_HI-`UCB_ADDR_LO:0] addr_in;
output [`UCB_DATA_HI-`UCB_DATA_LO:0] data_in;
// Ack/Nack from local unit
input rd_ack_vld;
input rd_nack_vld;
input [`UCB_THR_HI-`UCB_THR_LO:0] thr_id_out;
input [`UCB_BUF_HI-`UCB_BUF_LO:0] buf_id_out;
input data128; // set to 1 if data returned is 128 bit
input [REG_WIDTH-1:0] data_out;
// Interrupt from local unit
input int_vld;
input [`UCB_PKT_HI-`UCB_PKT_LO:0] int_typ; // interrupt type
input [`UCB_THR_HI-`UCB_THR_LO:0] int_thr_id; // interrupt thread ID
input [`UCB_INT_DEV_HI-`UCB_INT_DEV_LO:0] dev_id; // interrupt device ID
input [`UCB_INT_STAT_HI-`UCB_INT_STAT_LO:0] int_stat; // interrupt status
input [`UCB_INT_VEC_HI-`UCB_INT_VEC_LO:0] int_vec; // interrupt vector
output int_busy; // interrupt buffer busy
// Output to IO Bridge
output ucb_iob_vld;
output [UCB_IOB_WIDTH-1:0] ucb_iob_data;
input iob_ucb_stall;
// Local signals
wire indata_buf_vld;
wire [127:0] indata_buf;
wire ucb_iob_stall_a1;
wire read_pending;
wire read_outstanding;
wire read_outstanding_next;
wire write_pending;
wire illegal_write_size;
wire ack_buf_rd;
wire ack_buf_wr;
wire ack_buf_vld;
wire ack_buf_vld_next;
wire ack_buf_is_nack;
wire ack_buf_is_data128;
wire [`UCB_PKT_HI-`UCB_PKT_LO:0] ack_typ_out;
wire [REG_WIDTH+`UCB_BUF_HI-`UCB_PKT_LO:0] ack_buf_in;
wire [REG_WIDTH+`UCB_BUF_HI-`UCB_PKT_LO:0] ack_buf;
wire [(REG_WIDTH+64)/UCB_IOB_WIDTH-1:0] ack_buf_vec;
wire int_buf_rd;
wire int_buf_wr;
wire int_buf_vld;
wire int_buf_vld_next;
wire [`UCB_INT_VEC_HI-`UCB_PKT_LO:0] int_buf_in;
wire [`UCB_INT_VEC_HI-`UCB_PKT_LO:0] int_buf;
wire [(REG_WIDTH+64)/UCB_IOB_WIDTH-1:0] int_buf_vec;
wire int_last_rd;
wire outdata_buf_busy;
wire outdata_buf_wr;
wire [REG_WIDTH+63:0] outdata_buf_in;
wire [(REG_WIDTH+64)/UCB_IOB_WIDTH-1:0] outdata_vec_in;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
/************************************************************
* Inbound Data
************************************************************/
// Register size is hardcoded to 64 bits here because all
// units using the UCB module will only write to 64 bit registers.
ucb_bus_in #(IOB_UCB_WIDTH,64) ucb_bus_in (.rst_l(rst_l),
.clk(clk),
.vld(iob_ucb_vld),
.data(iob_ucb_data),
.stall(ucb_iob_stall),
.indata_buf_vld(indata_buf_vld),
.indata_buf(indata_buf),
.stall_a1(ucb_iob_stall_a1));
/************************************************************
* Decode inbound packet type
************************************************************/
assign read_pending = (indata_buf[`UCB_PKT_HI:`UCB_PKT_LO] ==
`UCB_READ_REQ) &
indata_buf_vld;
// Assertion: rd_req_vld and ack_buf_rd must be
// mutually exclusive
assign read_outstanding_next = rd_req_vld ? 1'b1 :
ack_buf_rd ? 1'b0 :
read_outstanding;
dffrl_ns #(1) read_outstanding_ff (.din(read_outstanding_next),
.clk(clk),
.rst_l(rst_l),
.q(read_outstanding));
assign ucb_iob_stall_a1 = read_pending & read_outstanding;
assign write_pending = (indata_buf[`UCB_PKT_HI:`UCB_PKT_LO] ==
`UCB_WRITE_REQ) &
indata_buf_vld;
// 3'b011 is the encoding for double word. All writes have to be
// 64 bits except writes going to PCI. PCI will instantiate a
// customized version of UCB.
assign illegal_write_size = (indata_buf[`UCB_SIZE_HI:`UCB_SIZE_LO] !=
3'b011);
/************************************************************
* Inbound interface to local unit
************************************************************/
assign rd_req_vld = read_pending & ~read_outstanding;
assign wr_req_vld = write_pending & ~illegal_write_size;
assign thr_id_in = indata_buf[`UCB_THR_HI:`UCB_THR_LO];
assign buf_id_in = indata_buf[`UCB_BUF_HI:`UCB_BUF_LO];
assign size_in = indata_buf[`UCB_SIZE_HI:`UCB_SIZE_LO];
assign addr_in = indata_buf[`UCB_ADDR_HI:`UCB_ADDR_LO];
assign data_in = indata_buf[`UCB_DATA_HI:`UCB_DATA_LO];
/************************************************************
* Outbound Ack/Nack
************************************************************/
assign ack_buf_wr = rd_ack_vld | rd_nack_vld;
assign ack_buf_vld_next = ack_buf_wr ? 1'b1 :
ack_buf_rd ? 1'b0 :
ack_buf_vld;
dffrl_ns #(1) ack_buf_vld_ff (.din(ack_buf_vld_next),
.clk(clk),
.rst_l(rst_l),
.q(ack_buf_vld));
dffe_ns #(1) ack_buf_is_nack_ff (.din(rd_nack_vld),
.en(ack_buf_wr),
.clk(clk),
.q(ack_buf_is_nack));
dffe_ns #(1) ack_buf_is_data128_ff (.din(data128),
.en(ack_buf_wr),
.clk(clk),
.q(ack_buf_is_data128));
assign ack_typ_out = rd_ack_vld ? `UCB_READ_ACK:
`UCB_READ_NACK;
assign ack_buf_in = {data_out,
buf_id_out,
thr_id_out,
ack_typ_out};
dffe_ns #(REG_WIDTH+`UCB_BUF_HI-`UCB_PKT_LO+1) ack_buf_ff (.din(ack_buf_in),
.en(ack_buf_wr),
.clk(clk),
.q(ack_buf));
assign ack_buf_vec = ack_buf_is_nack ? {{REG_WIDTH/UCB_IOB_WIDTH{1'b0}},
{64/UCB_IOB_WIDTH{1'b1}}} :
ack_buf_is_data128 ? {(REG_WIDTH+64)/UCB_IOB_WIDTH{1'b1}} :
{(64+64)/UCB_IOB_WIDTH{1'b1}};
/************************************************************
* Outbound Interrupt
************************************************************/
// Assertion: int_buf_wr shoudn't be asserted if int_buf_busy
assign int_buf_wr = int_vld;
assign int_buf_vld_next = int_buf_wr ? 1'b1 :
int_buf_rd ? 1'b0 :
int_buf_vld;
dffrl_ns #(1) int_buf_vld_ff (.din(int_buf_vld_next),
.clk(clk),
.rst_l(rst_l),
.q(int_buf_vld));
assign int_buf_in = {int_vec,
int_stat,
dev_id,
int_thr_id,
int_typ};
dffe_ns #(`UCB_INT_VEC_HI-`UCB_PKT_LO+1) int_buf_ff (.din(int_buf_in),
.en(int_buf_wr),
.clk(clk),
.q(int_buf));
assign int_buf_vec = {{REG_WIDTH/UCB_IOB_WIDTH{1'b0}},
{64/UCB_IOB_WIDTH{1'b1}}};
assign int_busy = int_buf_vld;
/************************************************************
* Outbound ack/interrupt Arbitration
************************************************************/
dffrle_ns #(1) int_last_rd_ff (.din(int_buf_rd),
.en(ack_buf_rd|int_buf_rd),
.rst_l(rst_l),
.clk(clk),
.q(int_last_rd));
assign ack_buf_rd = ~outdata_buf_busy & ack_buf_vld &
(~int_buf_vld | int_last_rd);
assign int_buf_rd = ~outdata_buf_busy & int_buf_vld &
(~ack_buf_vld | ~int_last_rd);
assign outdata_buf_wr = ack_buf_rd | int_buf_rd;
assign outdata_buf_in = ack_buf_rd ? {ack_buf[REG_WIDTH+`UCB_BUF_HI:`UCB_BUF_HI+1],
{(`UCB_RSV_HI-`UCB_RSV_LO+1){1'b0}},
{(`UCB_ADDR_HI-`UCB_ADDR_LO+1){1'b0}},
{(`UCB_SIZE_HI-`UCB_SIZE_LO+1){1'b0}},
ack_buf[`UCB_BUF_HI:`UCB_BUF_LO],
ack_buf[`UCB_THR_HI:`UCB_THR_LO],
ack_buf[`UCB_PKT_HI:`UCB_PKT_LO]}:
{{REG_WIDTH{1'b0}},
{(`UCB_INT_RSV_HI-`UCB_INT_RSV_LO+1){1'b0}},
int_buf[`UCB_INT_VEC_HI:`UCB_INT_VEC_LO],
int_buf[`UCB_INT_STAT_HI:`UCB_INT_STAT_LO],
int_buf[`UCB_INT_DEV_HI:`UCB_INT_DEV_LO],
int_buf[`UCB_THR_HI:`UCB_THR_LO],
int_buf[`UCB_PKT_HI:`UCB_PKT_LO]};
assign outdata_vec_in = ack_buf_rd ? ack_buf_vec :
int_buf_vec;
ucb_bus_out #(UCB_IOB_WIDTH, REG_WIDTH) ucb_bus_out (.rst_l(rst_l),
.clk(clk),
.outdata_buf_wr(outdata_buf_wr),
.outdata_buf_in(outdata_buf_in),
.outdata_vec_in(outdata_vec_in),
.outdata_buf_busy(outdata_buf_busy),
.vld(ucb_iob_vld),
.data(ucb_iob_data),
.stall(iob_ucb_stall));
endmodule // ucb_noflow
// Local Variables:
// verilog-library-directories:(".")
// End:
|
`include "../../../rtl/verilog/gfx/gfx_triangle.v"
`include "../../../rtl/verilog/gfx/div_uu.v"
module triangle_bench();
parameter point_width = 16;
parameter subpixel_width = 16;
reg clk_i;
reg rst_i;
reg ack_i;
wire ack_o;
reg triangle_write_i;
reg texture_enable_i;
reg signed [point_width-1:-subpixel_width] dest_pixel0_x_i;
reg signed [point_width-1:-subpixel_width] dest_pixel0_y_i;
reg signed [point_width-1:-subpixel_width] dest_pixel1_x_i;
reg signed [point_width-1:-subpixel_width] dest_pixel1_y_i;
reg signed [point_width-1:-subpixel_width] dest_pixel2_x_i;
reg signed [point_width-1:-subpixel_width] dest_pixel2_y_i;
wire [point_width-1:0] x_counter_o;
wire [point_width-1:0] y_counter_o;
wire write_o;
initial begin
$dumpfile("triangle.vcd");
$dumpvars(0,triangle_bench);
// init values
clk_i = 0;
rst_i = 1;
ack_i = 0;
triangle_write_i = 0;
dest_pixel0_x_i = -5 << subpixel_width;
dest_pixel0_y_i = 5 << subpixel_width;
dest_pixel1_x_i = 210 << subpixel_width;
dest_pixel1_y_i = 10 << subpixel_width;
dest_pixel2_x_i = 5 << subpixel_width;
dest_pixel2_y_i = 210 << subpixel_width;
texture_enable_i = 0;
//timing
#4 rst_i = 0;
#10 triangle_write_i = 1;
#2 triangle_write_i = 0;
#200
dest_pixel0_x_i = 5 << subpixel_width;
dest_pixel0_y_i = 15 << subpixel_width;
dest_pixel1_x_i = 10 << subpixel_width;
dest_pixel1_y_i = 10 << subpixel_width;
dest_pixel2_x_i = 5 << subpixel_width;
dest_pixel2_y_i = 10 << subpixel_width;
#10 triangle_write_i = 1;
#2 triangle_write_i = 0;
// end sim
#1000 $finish;
end
always begin
#1 clk_i = ~clk_i;
end
always @(posedge clk_i)
begin
ack_i <= #1 write_o;
end
gfx_triangle triangle(
.clk_i (clk_i),
.rst_i (rst_i),
.ack_i (ack_i),
.ack_o (ack_o),
.triangle_write_i (triangle_write_i),
.texture_enable_i (texture_enable_i),
.dest_pixel0_x_i (dest_pixel0_x_i),
.dest_pixel0_y_i (dest_pixel0_y_i),
.dest_pixel1_x_i (dest_pixel1_x_i),
.dest_pixel1_y_i (dest_pixel1_y_i),
.dest_pixel2_x_i (dest_pixel2_x_i),
.dest_pixel2_y_i (dest_pixel2_y_i),
.x_counter_o (x_counter_o),
.y_counter_o (y_counter_o),
.write_o (write_o)
);
defparam triangle.point_width = point_width;
defparam triangle.subpixel_width = subpixel_width;
endmodule
|
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//Register map:
//addr register type
//0 read data r
//1 write data w
//2 status r/w
//3 control r/w
//4 reserved
//5 slave-enable r/w
//6 end-of-packet-value r/w
//INPUT_CLOCK: 100000000
//ISMASTER: 1
//DATABITS: 16
//TARGETCLOCK: 7142858
//NUMSLAVES: 1
//CPOL: 0
//CPHA: 0
//LSBFIRST: 0
//EXTRADELAY: 0
//TARGETSSDELAY: 0
module wasca_spi_stm32 (
// inputs:
MISO,
clk,
data_from_cpu,
mem_addr,
read_n,
reset_n,
spi_select,
write_n,
// outputs:
MOSI,
SCLK,
SS_n,
data_to_cpu,
dataavailable,
endofpacket,
irq,
readyfordata
)
;
output MOSI;
output SCLK;
output SS_n;
output [ 15: 0] data_to_cpu;
output dataavailable;
output endofpacket;
output irq;
output readyfordata;
input MISO;
input clk;
input [ 15: 0] data_from_cpu;
input [ 2: 0] mem_addr;
input read_n;
input reset_n;
input spi_select;
input write_n;
wire E;
reg EOP;
reg MISO_reg;
wire MOSI;
reg ROE;
reg RRDY;
wire SCLK;
reg SCLK_reg;
reg SSO_reg;
wire SS_n;
wire TMT;
reg TOE;
wire TRDY;
wire control_wr_strobe;
reg data_rd_strobe;
reg [ 15: 0] data_to_cpu;
reg data_wr_strobe;
wire dataavailable;
wire ds_MISO;
wire enableSS;
wire endofpacket;
reg [ 15: 0] endofpacketvalue_reg;
wire endofpacketvalue_wr_strobe;
reg iEOP_reg;
reg iE_reg;
reg iROE_reg;
reg iRRDY_reg;
reg iTMT_reg;
reg iTOE_reg;
reg iTRDY_reg;
wire irq;
reg irq_reg;
wire p1_data_rd_strobe;
wire [ 15: 0] p1_data_to_cpu;
wire p1_data_wr_strobe;
wire p1_rd_strobe;
wire [ 2: 0] p1_slowcount;
wire p1_wr_strobe;
reg rd_strobe;
wire readyfordata;
reg [ 15: 0] rx_holding_reg;
reg [ 15: 0] shift_reg;
wire slaveselect_wr_strobe;
wire slowclock;
reg [ 2: 0] slowcount;
wire [ 10: 0] spi_control;
reg [ 15: 0] spi_slave_select_holding_reg;
reg [ 15: 0] spi_slave_select_reg;
wire [ 10: 0] spi_status;
reg [ 5: 0] state;
reg stateZero;
wire status_wr_strobe;
reg transmitting;
reg tx_holding_primed;
reg [ 15: 0] tx_holding_reg;
reg wr_strobe;
wire write_shift_reg;
wire write_tx_holding;
//spi_control_port, which is an e_avalon_slave
assign p1_rd_strobe = ~rd_strobe & spi_select & ~read_n;
// Read is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_strobe <= 0;
else
rd_strobe <= p1_rd_strobe;
end
assign p1_data_rd_strobe = p1_rd_strobe & (mem_addr == 0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_rd_strobe <= 0;
else
data_rd_strobe <= p1_data_rd_strobe;
end
assign p1_wr_strobe = ~wr_strobe & spi_select & ~write_n;
// Write is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wr_strobe <= 0;
else
wr_strobe <= p1_wr_strobe;
end
assign p1_data_wr_strobe = p1_wr_strobe & (mem_addr == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_wr_strobe <= 0;
else
data_wr_strobe <= p1_data_wr_strobe;
end
assign control_wr_strobe = wr_strobe & (mem_addr == 3);
assign status_wr_strobe = wr_strobe & (mem_addr == 2);
assign slaveselect_wr_strobe = wr_strobe & (mem_addr == 5);
assign endofpacketvalue_wr_strobe = wr_strobe & (mem_addr == 6);
assign TMT = ~transmitting & ~tx_holding_primed;
assign E = ROE | TOE;
assign spi_status = {EOP, E, RRDY, TRDY, TMT, TOE, ROE, 3'b0};
// Streaming data ready for pickup.
assign dataavailable = RRDY;
// Ready to accept streaming data.
assign readyfordata = TRDY;
// Endofpacket condition detected.
assign endofpacket = EOP;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
iEOP_reg <= 0;
iE_reg <= 0;
iRRDY_reg <= 0;
iTRDY_reg <= 0;
iTMT_reg <= 0;
iTOE_reg <= 0;
iROE_reg <= 0;
SSO_reg <= 0;
end
else if (control_wr_strobe)
begin
iEOP_reg <= data_from_cpu[9];
iE_reg <= data_from_cpu[8];
iRRDY_reg <= data_from_cpu[7];
iTRDY_reg <= data_from_cpu[6];
iTMT_reg <= data_from_cpu[5];
iTOE_reg <= data_from_cpu[4];
iROE_reg <= data_from_cpu[3];
SSO_reg <= data_from_cpu[10];
end
end
assign spi_control = {SSO_reg, iEOP_reg, iE_reg, iRRDY_reg, iTRDY_reg, 1'b0, iTOE_reg, iROE_reg, 3'b0};
// IRQ output.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_reg <= 0;
else
irq_reg <= (EOP & iEOP_reg) | ((TOE | ROE) & iE_reg) | (RRDY & iRRDY_reg) | (TRDY & iTRDY_reg) | (TOE & iTOE_reg) | (ROE & iROE_reg);
end
assign irq = irq_reg;
// Slave select register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
spi_slave_select_reg <= 1;
else if (write_shift_reg || control_wr_strobe & data_from_cpu[10] & ~SSO_reg)
spi_slave_select_reg <= spi_slave_select_holding_reg;
end
// Slave select holding register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
spi_slave_select_holding_reg <= 1;
else if (slaveselect_wr_strobe)
spi_slave_select_holding_reg <= data_from_cpu;
end
// slowclock is active once every 7 system clock pulses.
assign slowclock = slowcount == 3'h6;
assign p1_slowcount = ({3 {(transmitting && !slowclock)}} & (slowcount + 1)) |
({3 {(~((transmitting && !slowclock)))}} & 0);
// Divide counter for SPI clock.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
slowcount <= 0;
else
slowcount <= p1_slowcount;
end
// End-of-packet value register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
endofpacketvalue_reg <= 0;
else if (endofpacketvalue_wr_strobe)
endofpacketvalue_reg <= data_from_cpu;
end
assign p1_data_to_cpu = ((mem_addr == 2))? spi_status :
((mem_addr == 3))? spi_control :
((mem_addr == 6))? endofpacketvalue_reg :
((mem_addr == 5))? spi_slave_select_reg :
rx_holding_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_to_cpu <= 0;
else
// Data to cpu.
data_to_cpu <= p1_data_to_cpu;
end
// 'state' counts from 0 to 33.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
state <= 0;
stateZero <= 1;
end
else if (transmitting & slowclock)
begin
stateZero <= state == 33;
if (state == 33)
state <= 0;
else
state <= state + 1;
end
end
assign enableSS = transmitting & ~stateZero;
assign MOSI = shift_reg[15];
assign SS_n = (enableSS | SSO_reg) ? ~spi_slave_select_reg : {1 {1'b1} };
assign SCLK = SCLK_reg;
// As long as there's an empty spot somewhere,
//it's safe to write data.
assign TRDY = ~(transmitting & tx_holding_primed);
// Enable write to tx_holding_register.
assign write_tx_holding = data_wr_strobe & TRDY;
// Enable write to shift register.
assign write_shift_reg = tx_holding_primed & ~transmitting;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
shift_reg <= 0;
rx_holding_reg <= 0;
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
tx_holding_reg <= 0;
tx_holding_primed <= 0;
transmitting <= 0;
SCLK_reg <= 0;
MISO_reg <= 0;
end
else
begin
if (write_tx_holding)
begin
tx_holding_reg <= data_from_cpu;
tx_holding_primed <= 1;
end
if (data_wr_strobe & ~TRDY)
// You wrote when I wasn't ready.
TOE <= 1;
// EOP must be updated by the last (2nd) cycle of access.
if ((p1_data_rd_strobe && (rx_holding_reg == endofpacketvalue_reg)) || (p1_data_wr_strobe && (data_from_cpu == endofpacketvalue_reg)))
EOP <= 1;
if (write_shift_reg)
begin
shift_reg <= tx_holding_reg;
transmitting <= 1;
end
if (write_shift_reg & ~write_tx_holding)
// Clear tx_holding_primed
tx_holding_primed <= 0;
if (data_rd_strobe)
// On data read, clear the RRDY bit.
RRDY <= 0;
if (status_wr_strobe)
begin
// On status write, clear all status bits (ignore the data).
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
end
if (slowclock)
begin
if (state == 33)
begin
transmitting <= 0;
RRDY <= 1;
rx_holding_reg <= shift_reg;
SCLK_reg <= 0;
if (RRDY)
ROE <= 1;
end
else if (state != 0)
if (transmitting)
SCLK_reg <= ~SCLK_reg;
if (SCLK_reg ^ 0 ^ 0)
begin
if (1)
shift_reg <= {shift_reg[14 : 0], MISO_reg};
end
else
MISO_reg <= ds_MISO;
end
end
end
assign ds_MISO = MISO;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_cfg.v
// Version : 1.8
//--
//--------------------------------------------------------------------------------
`include "board_common.v"
module pci_exp_usrapp_cfg (
cfg_do,
cfg_di,
cfg_byte_en_n,
cfg_dwaddr,
cfg_wr_en_n,
cfg_rd_en_n,
cfg_rd_wr_done_n,
cfg_err_cor_n,
cfg_err_ur_n,
cfg_err_ecrc_n,
cfg_err_cpl_timeout_n,
cfg_err_cpl_abort_n,
cfg_err_cpl_unexpect_n,
cfg_err_posted_n,
cfg_err_tlp_cpl_header,
cfg_interrupt_n,
cfg_interrupt_rdy_n,
cfg_turnoff_ok_n,
cfg_to_turnoff_n,
cfg_bus_number,
cfg_device_number,
cfg_function_number,
cfg_status,
cfg_command,
cfg_dstatus,
cfg_dcommand,
cfg_lstatus,
cfg_lcommand,
cfg_pcie_link_state_n,
cfg_trn_pending_n,
cfg_pm_wake_n,
trn_clk,
trn_reset_n
);
input [(32 - 1):0] cfg_do;
output [(32 - 1):0] cfg_di;
output [(32/8 - 1):0] cfg_byte_en_n;
output [(10 - 1):0] cfg_dwaddr;
output cfg_wr_en_n;
output cfg_rd_en_n;
input cfg_rd_wr_done_n;
output cfg_err_cor_n;
output cfg_err_ur_n;
output cfg_err_ecrc_n;
output cfg_err_cpl_timeout_n;
output cfg_err_cpl_abort_n;
output cfg_err_cpl_unexpect_n;
output cfg_err_posted_n;
output [(48 - 1):0] cfg_err_tlp_cpl_header;
output cfg_interrupt_n;
input cfg_interrupt_rdy_n;
output cfg_turnoff_ok_n;
input cfg_to_turnoff_n;
output cfg_pm_wake_n;
input [(8 - 1):0] cfg_bus_number;
input [(5 - 1):0] cfg_device_number;
input [(3 - 1):0] cfg_function_number;
input [(16 - 1):0] cfg_status;
input [(16- 1):0] cfg_command;
input [(16- 1):0] cfg_dstatus;
input [(16 - 1):0] cfg_dcommand;
input [(16 - 1):0] cfg_lstatus;
input [(16 - 1):0] cfg_lcommand;
input [(3 - 1):0] cfg_pcie_link_state_n;
output cfg_trn_pending_n;
input trn_clk;
input trn_reset_n;
parameter Tcq = 1;
reg [(32 - 1):0] cfg_di;
reg [(32/8 - 1):0] cfg_byte_en_n;
reg [(10 - 1):0] cfg_dwaddr;
reg cfg_wr_en_n;
reg cfg_rd_en_n;
reg cfg_err_cor_n;
reg cfg_err_ecrc_n;
reg cfg_err_ur_n;
reg cfg_err_cpl_timeout_n;
reg cfg_err_cpl_abort_n;
reg cfg_err_cpl_unexpect_n;
reg cfg_err_posted_n;
reg [(48 - 1):0] cfg_err_tlp_cpl_header;
reg cfg_interrupt_n;
reg cfg_turnoff_ok_n;
reg cfg_pm_wake_n;
reg cfg_trn_pending_n;
initial begin
cfg_err_cor_n <= 1'b1;
cfg_err_ur_n <= 1'b1;
cfg_err_ecrc_n <= 1'b1;
cfg_err_cpl_timeout_n <= 1'b1;
cfg_err_cpl_abort_n <= 1'b1;
cfg_err_cpl_unexpect_n <= 1'b1;
cfg_err_posted_n <= 1'b0;
cfg_interrupt_n <= 1'b1;
cfg_turnoff_ok_n <= 1'b1;
cfg_dwaddr <= 0;
cfg_err_tlp_cpl_header <= 0;
cfg_di <= 0;
cfg_byte_en_n <= 4'hf;
cfg_wr_en_n <= 1;
cfg_rd_en_n <= 1;
cfg_pm_wake_n <= 1;
cfg_trn_pending_n <= 1'b0;
end
/************************************************************
Task : TSK_READ_CFG_DW
Description : Read Configuration Space DW
*************************************************************/
task TSK_READ_CFG_DW;
input [31:0] addr_;
begin
if (!trn_reset_n) begin
$display("[%t] : trn_reset_n is asserted", $realtime);
$finish(1);
end
wait ( cfg_rd_wr_done_n == 1'b1)
@(posedge trn_clk);
cfg_dwaddr <= #(Tcq) addr_;
cfg_wr_en_n <= #(Tcq) 1'b1;
cfg_rd_en_n <= #(Tcq) 1'b0;
$display("[%t] : Reading Cfg Addr [0x%h]", $realtime, addr_);
$fdisplay(board.RP.com_usrapp.tx_file_ptr,
"\n[%t] : Local Configuration Read Access :",
$realtime);
@(posedge trn_clk);
#(Tcq);
wait ( cfg_rd_wr_done_n == 1'b0)
#(Tcq);
$fdisplay(board.RP.com_usrapp.tx_file_ptr,
"\t\t\tCfg Addr [0x%h] -> Data [0x%h]\n",
{addr_,2'b00}, cfg_do);
cfg_rd_en_n <= #(Tcq) 1'b1;
end
endtask // TSK_READ_CFG_DW;
/************************************************************
Task : TSK_WRITE_CFG_DW
Description : Write Configuration Space DW
*************************************************************/
task TSK_WRITE_CFG_DW;
input [31:0] addr_;
input [31:0] data_;
input [3:0] ben_;
begin
if (!trn_reset_n) begin
$display("[%t] : trn_reset_n is asserted", $realtime);
$finish(1);
end
wait ( cfg_rd_wr_done_n == 1'b1)
@(posedge trn_clk);
cfg_dwaddr <= #(Tcq) addr_;
cfg_di <= #(Tcq) data_;
cfg_byte_en_n <= #(Tcq) ben_;
cfg_wr_en_n <= #(Tcq) 1'b0;
cfg_rd_en_n <= #(Tcq) 1'b1;
$display("[%t] : Writing Cfg Addr [0x%h]", $realtime, addr_);
$fdisplay(board.RP.com_usrapp.tx_file_ptr,
"\n[%t] : Local Configuration Write Access :",
$realtime);
@(posedge trn_clk);
#(Tcq);
wait ( cfg_rd_wr_done_n == 1'b0)
#(Tcq);
cfg_wr_en_n <= #(Tcq) 1'b1;
end
endtask // TSK_WRITE_CFG_DW;
endmodule // pci_exp_usrapp_cfg
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_impctl_smachine_new.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_impctl_smachine_new(z_post ,deltabit ,ctu_io_sscan_se ,
updclk ,we_csr ,l2clk ,ctu_io_sscan_in ,from_csr ,above ,bypass ,
config_pmos ,global_reset_n ,hard_reset_n ,ctu_global_snap ,sclk ,
avgcntr_rst ,so ,se ,si_l ,io_ctu_sscan_out ,tclk ,
ctu_io_sscan_update ,clk_en_l ,to_csr ,d );
output [7:0] z_post ;
output [7:0] to_csr ;
output [7:0] d ;
input [7:0] from_csr ;
output deltabit ;
output so ;
output io_ctu_sscan_out ;
input ctu_io_sscan_se ;
input updclk ;
input we_csr ;
input l2clk ;
input ctu_io_sscan_in ;
input above ;
input bypass ;
input config_pmos ;
input global_reset_n ;
input hard_reset_n ;
input ctu_global_snap ;
input sclk ;
input avgcntr_rst ;
input se ;
input si_l ;
input tclk ;
input ctu_io_sscan_update ;
input clk_en_l ;
wire [7:0] sz ;
wire adv_sgn ;
wire scan_n ;
wire freeze ;
wire se_l ;
wire l1clk0 ;
wire l1clk1 ;
wire l1clk2 ;
wire so_l ;
wire net064 ;
wire net066 ;
wire net068 ;
wire net58 ;
wire net077 ;
bw_io_impctl_clnew I179 (
.sz ({sz } ),
.z ({to_csr } ),
.ctu_io_sscan_update (ctu_io_sscan_update ),
.ctu_io_sscan_out (io_ctu_sscan_out ),
.clk (l1clk2 ),
.si (net58 ),
.so (so ),
.ctu_global_snap (ctu_global_snap ),
.ctu_io_sscan_se (ctu_io_sscan_se ),
.tclk (tclk ),
.snap_enable (net077 ),
.se (se ),
.freeze (freeze ),
.hard_reset_n (hard_reset_n ),
.ctu_io_sscan_in (ctu_io_sscan_in ) );
bw_u1_ckenbuf_4p5x I30 (
.clk (l1clk0 ),
.rclk (l2clk ),
.en_l (clk_en_l ),
.tm_l (se_l ) );
bw_io_impctl_clsm I208 (
.sz ({sz } ),
.to_csr ({to_csr } ),
.z_post ({z_post } ),
.from_csr ({from_csr } ),
.d ({d } ),
.clk (l1clk1 ),
.deltabit (deltabit ),
.we_csr (we_csr ),
.synced_upd_imped (ctu_io_sscan_update ),
.updclk (updclk ),
.hard_reset_n (hard_reset_n ),
.adv_sgn (adv_sgn ),
.si_l (scan_n ),
.config_pmos (config_pmos ),
.se (se ),
.freeze (freeze ),
.so_l (so_l ),
.above (above ),
.bypass (bypass ),
.global_reset_n (global_reset_n ) );
bw_io_impctl_avgcnt I209 (
.adv_sgn (adv_sgn ),
.so_i (scan_n ),
.above (above ),
.sclk (sclk ),
.avgcntr_rst (avgcntr_rst ),
.se (se ),
.si_l (si_l ),
.global_reset_n (global_reset_n ),
.l2clk (l1clk0 ) );
bw_u1_ckenbuf_4p5x I210 (
.clk (l1clk1 ),
.rclk (l2clk ),
.en_l (clk_en_l ),
.tm_l (se_l ) );
bw_u1_ckenbuf_6x I213 (
.clk (l1clk2 ),
.rclk (l2clk ),
.en_l (clk_en_l ),
.tm_l (se_l ) );
bw_u1_inv_8x I218 (
.z (net58 ),
.a (so_l ) );
bw_u1_inv_8x I219 (
.z (se_l ),
.a (se ) );
bw_u1_inv_8x I220 (
.z (net064 ),
.a (l1clk0 ) );
bw_u1_inv_8x I221 (
.z (net066 ),
.a (l1clk1 ) );
bw_u1_inv_8x I222 (
.z (net068 ),
.a (l1clk2 ) );
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Nov 2 11:07:40 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, Sgf_operation_EVEN1_left_N23,
Sgf_operation_EVEN1_left_N22, Sgf_operation_EVEN1_left_N21,
Sgf_operation_EVEN1_left_N20, Sgf_operation_EVEN1_left_N19,
Sgf_operation_EVEN1_left_N18, Sgf_operation_EVEN1_left_N17,
Sgf_operation_EVEN1_left_N16, Sgf_operation_EVEN1_left_N15,
Sgf_operation_EVEN1_left_N14, Sgf_operation_EVEN1_left_N13,
Sgf_operation_EVEN1_left_N12, Sgf_operation_EVEN1_left_N11,
Sgf_operation_EVEN1_left_N10, Sgf_operation_EVEN1_left_N9,
Sgf_operation_EVEN1_left_N8, Sgf_operation_EVEN1_left_N7,
Sgf_operation_EVEN1_left_N6, Sgf_operation_EVEN1_left_N5,
Sgf_operation_EVEN1_left_N4, Sgf_operation_EVEN1_left_N3,
Sgf_operation_EVEN1_left_N2, Sgf_operation_EVEN1_left_N1,
Sgf_operation_EVEN1_left_N0, Sgf_operation_EVEN1_middle_N25,
Sgf_operation_EVEN1_middle_N24, Sgf_operation_EVEN1_middle_N23,
Sgf_operation_EVEN1_middle_N22, Sgf_operation_EVEN1_middle_N21,
Sgf_operation_EVEN1_middle_N20, Sgf_operation_EVEN1_middle_N19,
Sgf_operation_EVEN1_middle_N18, Sgf_operation_EVEN1_middle_N17,
Sgf_operation_EVEN1_middle_N16, Sgf_operation_EVEN1_middle_N15,
Sgf_operation_EVEN1_middle_N14, Sgf_operation_EVEN1_middle_N13,
Sgf_operation_EVEN1_middle_N12, Sgf_operation_EVEN1_middle_N11,
Sgf_operation_EVEN1_middle_N10, Sgf_operation_EVEN1_middle_N9,
Sgf_operation_EVEN1_middle_N8, Sgf_operation_EVEN1_middle_N7,
Sgf_operation_EVEN1_middle_N6, Sgf_operation_EVEN1_middle_N5,
Sgf_operation_EVEN1_middle_N4, Sgf_operation_EVEN1_middle_N3,
Sgf_operation_EVEN1_middle_N2, Sgf_operation_EVEN1_middle_N1,
Sgf_operation_EVEN1_middle_N0, Sgf_operation_EVEN1_right_N23,
Sgf_operation_EVEN1_right_N22, Sgf_operation_EVEN1_right_N21,
Sgf_operation_EVEN1_right_N20, Sgf_operation_EVEN1_right_N19,
Sgf_operation_EVEN1_right_N18, Sgf_operation_EVEN1_right_N17,
Sgf_operation_EVEN1_right_N16, Sgf_operation_EVEN1_right_N15,
Sgf_operation_EVEN1_right_N14, Sgf_operation_EVEN1_right_N13,
Sgf_operation_EVEN1_right_N12, Sgf_operation_EVEN1_right_N11,
Sgf_operation_EVEN1_right_N10, Sgf_operation_EVEN1_right_N9,
Sgf_operation_EVEN1_right_N8, Sgf_operation_EVEN1_right_N7,
Sgf_operation_EVEN1_right_N6, Sgf_operation_EVEN1_right_N5,
Sgf_operation_EVEN1_right_N4, Sgf_operation_EVEN1_right_N3,
Sgf_operation_EVEN1_right_N2, Sgf_operation_EVEN1_right_N1,
Sgf_operation_EVEN1_right_N0, n168, n170, n171, n172, n173, n174,
n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185,
n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196,
n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218,
n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229,
n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240,
n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251,
n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262,
n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273,
n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284,
n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295,
n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306,
n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317,
n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328,
n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350,
n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361,
n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372,
n373, n374, n375, n376, n377, n378, n380, n381,
DP_OP_111J19_123_4462_n252, DP_OP_111J19_123_4462_n251,
DP_OP_111J19_123_4462_n250, DP_OP_111J19_123_4462_n249,
DP_OP_111J19_123_4462_n248, DP_OP_111J19_123_4462_n247,
DP_OP_111J19_123_4462_n246, DP_OP_111J19_123_4462_n245,
DP_OP_111J19_123_4462_n240, DP_OP_111J19_123_4462_n236,
DP_OP_111J19_123_4462_n235, DP_OP_111J19_123_4462_n234,
DP_OP_111J19_123_4462_n233, DP_OP_111J19_123_4462_n232,
DP_OP_111J19_123_4462_n231, DP_OP_111J19_123_4462_n227,
DP_OP_111J19_123_4462_n223, DP_OP_111J19_123_4462_n219,
DP_OP_111J19_123_4462_n218, DP_OP_111J19_123_4462_n217,
DP_OP_111J19_123_4462_n216, DP_OP_111J19_123_4462_n215,
DP_OP_111J19_123_4462_n214, DP_OP_111J19_123_4462_n213,
DP_OP_111J19_123_4462_n212, DP_OP_111J19_123_4462_n210,
DP_OP_111J19_123_4462_n204, DP_OP_111J19_123_4462_n203,
DP_OP_111J19_123_4462_n202, DP_OP_111J19_123_4462_n200,
DP_OP_111J19_123_4462_n199, DP_OP_111J19_123_4462_n198,
DP_OP_111J19_123_4462_n197, DP_OP_111J19_123_4462_n196,
DP_OP_111J19_123_4462_n195, DP_OP_111J19_123_4462_n191,
DP_OP_111J19_123_4462_n188, DP_OP_111J19_123_4462_n187,
DP_OP_111J19_123_4462_n186, DP_OP_111J19_123_4462_n185,
DP_OP_111J19_123_4462_n184, DP_OP_111J19_123_4462_n183,
DP_OP_111J19_123_4462_n182, DP_OP_111J19_123_4462_n181,
DP_OP_111J19_123_4462_n180, DP_OP_111J19_123_4462_n179,
DP_OP_111J19_123_4462_n178, DP_OP_111J19_123_4462_n177,
DP_OP_111J19_123_4462_n176, DP_OP_111J19_123_4462_n175,
DP_OP_111J19_123_4462_n172, DP_OP_111J19_123_4462_n171,
DP_OP_111J19_123_4462_n170, DP_OP_111J19_123_4462_n169,
DP_OP_111J19_123_4462_n168, DP_OP_111J19_123_4462_n167,
DP_OP_111J19_123_4462_n166, DP_OP_111J19_123_4462_n165,
DP_OP_111J19_123_4462_n164, DP_OP_111J19_123_4462_n163,
DP_OP_111J19_123_4462_n162, DP_OP_111J19_123_4462_n156,
DP_OP_111J19_123_4462_n155, DP_OP_111J19_123_4462_n148,
DP_OP_111J19_123_4462_n145, DP_OP_111J19_123_4462_n144,
DP_OP_111J19_123_4462_n143, DP_OP_111J19_123_4462_n142,
DP_OP_111J19_123_4462_n140, DP_OP_111J19_123_4462_n139,
DP_OP_111J19_123_4462_n138, DP_OP_111J19_123_4462_n137,
DP_OP_111J19_123_4462_n135, DP_OP_111J19_123_4462_n134,
DP_OP_111J19_123_4462_n133, DP_OP_111J19_123_4462_n131,
DP_OP_111J19_123_4462_n130, DP_OP_111J19_123_4462_n129,
DP_OP_111J19_123_4462_n128, DP_OP_111J19_123_4462_n127,
DP_OP_111J19_123_4462_n126, DP_OP_111J19_123_4462_n125,
DP_OP_111J19_123_4462_n124, DP_OP_111J19_123_4462_n123,
DP_OP_111J19_123_4462_n122, DP_OP_111J19_123_4462_n121,
DP_OP_111J19_123_4462_n120, DP_OP_111J19_123_4462_n119,
DP_OP_111J19_123_4462_n117, DP_OP_111J19_123_4462_n116,
DP_OP_111J19_123_4462_n115, DP_OP_111J19_123_4462_n114,
DP_OP_111J19_123_4462_n113, DP_OP_111J19_123_4462_n112,
DP_OP_111J19_123_4462_n111, DP_OP_111J19_123_4462_n109,
DP_OP_111J19_123_4462_n108, DP_OP_111J19_123_4462_n107,
DP_OP_111J19_123_4462_n106, DP_OP_111J19_123_4462_n105,
DP_OP_111J19_123_4462_n104, DP_OP_111J19_123_4462_n103,
DP_OP_111J19_123_4462_n102, DP_OP_111J19_123_4462_n101,
DP_OP_111J19_123_4462_n100, DP_OP_111J19_123_4462_n99,
DP_OP_111J19_123_4462_n98, DP_OP_111J19_123_4462_n97,
DP_OP_111J19_123_4462_n96, DP_OP_111J19_123_4462_n94,
DP_OP_111J19_123_4462_n93, DP_OP_111J19_123_4462_n92,
DP_OP_111J19_123_4462_n91, DP_OP_111J19_123_4462_n90,
DP_OP_111J19_123_4462_n89, DP_OP_111J19_123_4462_n88,
DP_OP_111J19_123_4462_n87, DP_OP_111J19_123_4462_n84,
DP_OP_111J19_123_4462_n83, DP_OP_111J19_123_4462_n82,
DP_OP_111J19_123_4462_n81, DP_OP_111J19_123_4462_n80,
DP_OP_111J19_123_4462_n79, DP_OP_111J19_123_4462_n78,
DP_OP_111J19_123_4462_n77, DP_OP_111J19_123_4462_n76,
DP_OP_111J19_123_4462_n75, DP_OP_111J19_123_4462_n74,
DP_OP_111J19_123_4462_n73, DP_OP_111J19_123_4462_n72,
DP_OP_111J19_123_4462_n71, DP_OP_111J19_123_4462_n70,
DP_OP_111J19_123_4462_n69, DP_OP_111J19_123_4462_n68,
DP_OP_111J19_123_4462_n67, DP_OP_111J19_123_4462_n66,
DP_OP_111J19_123_4462_n65, DP_OP_111J19_123_4462_n64,
DP_OP_111J19_123_4462_n63, DP_OP_111J19_123_4462_n62,
DP_OP_111J19_123_4462_n61, DP_OP_111J19_123_4462_n60,
DP_OP_111J19_123_4462_n59, DP_OP_111J19_123_4462_n58,
DP_OP_111J19_123_4462_n57, DP_OP_111J19_123_4462_n56,
DP_OP_111J19_123_4462_n55, DP_OP_111J19_123_4462_n52,
DP_OP_111J19_123_4462_n51, DP_OP_111J19_123_4462_n50,
DP_OP_111J19_123_4462_n49, DP_OP_111J19_123_4462_n48,
DP_OP_111J19_123_4462_n47, DP_OP_111J19_123_4462_n46,
DP_OP_111J19_123_4462_n45, DP_OP_111J19_123_4462_n44,
DP_OP_111J19_123_4462_n43, DP_OP_111J19_123_4462_n42,
DP_OP_111J19_123_4462_n41, DP_OP_111J19_123_4462_n40,
DP_OP_111J19_123_4462_n39, DP_OP_111J19_123_4462_n38,
DP_OP_111J19_123_4462_n37, DP_OP_111J19_123_4462_n36,
DP_OP_111J19_123_4462_n35, mult_x_55_n232, mult_x_55_n228,
mult_x_55_n220, mult_x_55_n219, mult_x_55_n216, mult_x_55_n215,
mult_x_55_n213, mult_x_55_n212, mult_x_55_n211, mult_x_55_n208,
mult_x_55_n207, mult_x_55_n206, mult_x_55_n205, mult_x_55_n204,
mult_x_55_n203, mult_x_55_n202, mult_x_55_n200, mult_x_55_n199,
mult_x_55_n198, mult_x_55_n197, mult_x_55_n196, mult_x_55_n195,
mult_x_55_n194, mult_x_55_n192, mult_x_55_n191, mult_x_55_n190,
mult_x_55_n189, mult_x_55_n186, mult_x_55_n185, mult_x_55_n183,
mult_x_55_n180, mult_x_55_n179, mult_x_55_n178, mult_x_55_n176,
mult_x_55_n175, mult_x_55_n174, mult_x_55_n173, mult_x_55_n170,
mult_x_55_n169, mult_x_55_n168, mult_x_55_n167, mult_x_55_n166,
mult_x_55_n165, mult_x_55_n164, mult_x_55_n163, mult_x_55_n162,
mult_x_55_n161, mult_x_55_n160, mult_x_55_n159, mult_x_55_n158,
mult_x_55_n157, mult_x_55_n151, mult_x_55_n149, mult_x_55_n136,
mult_x_55_n133, mult_x_55_n132, mult_x_55_n131, mult_x_55_n130,
mult_x_55_n129, mult_x_55_n128, mult_x_55_n127, mult_x_55_n126,
mult_x_55_n125, mult_x_55_n124, mult_x_55_n123, mult_x_55_n122,
mult_x_55_n121, mult_x_55_n120, mult_x_55_n119, mult_x_55_n118,
mult_x_55_n117, mult_x_55_n116, mult_x_55_n115, mult_x_55_n114,
mult_x_55_n113, mult_x_55_n112, mult_x_55_n111, mult_x_55_n110,
mult_x_55_n109, mult_x_55_n108, mult_x_55_n107, mult_x_55_n106,
mult_x_55_n105, mult_x_55_n104, mult_x_55_n103, mult_x_55_n102,
mult_x_55_n101, mult_x_55_n100, mult_x_55_n99, mult_x_55_n98,
mult_x_55_n97, mult_x_55_n96, mult_x_55_n95, mult_x_55_n94,
mult_x_55_n93, mult_x_55_n92, mult_x_55_n90, mult_x_55_n89,
mult_x_55_n88, mult_x_55_n87, mult_x_55_n86, mult_x_55_n85,
mult_x_55_n84, mult_x_55_n83, mult_x_55_n80, mult_x_55_n79,
mult_x_55_n78, mult_x_55_n77, mult_x_55_n76, mult_x_55_n75,
mult_x_55_n74, mult_x_55_n73, mult_x_55_n72, mult_x_55_n71,
mult_x_55_n70, mult_x_55_n69, mult_x_55_n68, mult_x_55_n67,
mult_x_55_n66, mult_x_55_n65, mult_x_55_n64, mult_x_55_n63,
mult_x_55_n62, mult_x_55_n61, mult_x_55_n60, mult_x_55_n59,
mult_x_55_n58, mult_x_55_n57, mult_x_55_n56, mult_x_55_n55,
mult_x_55_n54, mult_x_55_n53, mult_x_55_n52, mult_x_55_n51,
mult_x_55_n48, mult_x_55_n47, mult_x_55_n46, mult_x_55_n45,
mult_x_55_n44, mult_x_55_n43, mult_x_55_n42, mult_x_55_n41,
mult_x_55_n40, mult_x_55_n39, mult_x_55_n38, mult_x_55_n37,
mult_x_55_n36, mult_x_55_n35, mult_x_55_n34, mult_x_55_n33,
mult_x_55_n32, mult_x_55_n31, mult_x_23_n226, mult_x_23_n222,
mult_x_23_n219, mult_x_23_n214, mult_x_23_n213, mult_x_23_n210,
mult_x_23_n209, mult_x_23_n207, mult_x_23_n206, mult_x_23_n205,
mult_x_23_n202, mult_x_23_n201, mult_x_23_n200, mult_x_23_n199,
mult_x_23_n198, mult_x_23_n197, mult_x_23_n196, mult_x_23_n194,
mult_x_23_n193, mult_x_23_n192, mult_x_23_n191, mult_x_23_n190,
mult_x_23_n189, mult_x_23_n188, mult_x_23_n186, mult_x_23_n185,
mult_x_23_n184, mult_x_23_n183, mult_x_23_n180, mult_x_23_n179,
mult_x_23_n177, mult_x_23_n174, mult_x_23_n173, mult_x_23_n172,
mult_x_23_n170, mult_x_23_n169, mult_x_23_n168, mult_x_23_n167,
mult_x_23_n164, mult_x_23_n163, mult_x_23_n162, mult_x_23_n161,
mult_x_23_n160, mult_x_23_n159, mult_x_23_n158, mult_x_23_n157,
mult_x_23_n156, mult_x_23_n155, mult_x_23_n154, mult_x_23_n153,
mult_x_23_n152, mult_x_23_n151, mult_x_23_n136, mult_x_23_n133,
mult_x_23_n132, mult_x_23_n131, mult_x_23_n130, mult_x_23_n129,
mult_x_23_n128, mult_x_23_n127, mult_x_23_n126, mult_x_23_n125,
mult_x_23_n124, mult_x_23_n123, mult_x_23_n122, mult_x_23_n121,
mult_x_23_n120, mult_x_23_n119, mult_x_23_n118, mult_x_23_n117,
mult_x_23_n116, mult_x_23_n115, mult_x_23_n114, mult_x_23_n113,
mult_x_23_n112, mult_x_23_n111, mult_x_23_n110, mult_x_23_n109,
mult_x_23_n108, mult_x_23_n107, mult_x_23_n106, mult_x_23_n105,
mult_x_23_n104, mult_x_23_n103, mult_x_23_n102, mult_x_23_n101,
mult_x_23_n100, mult_x_23_n99, mult_x_23_n98, mult_x_23_n97,
mult_x_23_n96, mult_x_23_n95, mult_x_23_n94, mult_x_23_n93,
mult_x_23_n92, mult_x_23_n90, mult_x_23_n89, mult_x_23_n88,
mult_x_23_n87, mult_x_23_n86, mult_x_23_n85, mult_x_23_n84,
mult_x_23_n83, mult_x_23_n80, mult_x_23_n79, mult_x_23_n78,
mult_x_23_n77, mult_x_23_n76, mult_x_23_n75, mult_x_23_n74,
mult_x_23_n73, mult_x_23_n72, mult_x_23_n71, mult_x_23_n70,
mult_x_23_n69, mult_x_23_n68, mult_x_23_n67, mult_x_23_n66,
mult_x_23_n65, mult_x_23_n64, mult_x_23_n62, mult_x_23_n61,
mult_x_23_n60, mult_x_23_n59, mult_x_23_n58, mult_x_23_n57,
mult_x_23_n56, mult_x_23_n55, mult_x_23_n54, mult_x_23_n53,
mult_x_23_n52, mult_x_23_n51, mult_x_23_n48, mult_x_23_n47,
mult_x_23_n46, mult_x_23_n45, mult_x_23_n44, mult_x_23_n43,
mult_x_23_n42, mult_x_23_n41, mult_x_23_n40, mult_x_23_n39,
mult_x_23_n38, mult_x_23_n36, mult_x_23_n35, mult_x_23_n34,
mult_x_23_n33, mult_x_23_n32, mult_x_23_n31, DP_OP_36J19_124_9196_n22,
DP_OP_36J19_124_9196_n21, DP_OP_36J19_124_9196_n20,
DP_OP_36J19_124_9196_n19, DP_OP_36J19_124_9196_n18,
DP_OP_36J19_124_9196_n17, DP_OP_36J19_124_9196_n16,
DP_OP_36J19_124_9196_n15, DP_OP_36J19_124_9196_n9,
DP_OP_36J19_124_9196_n8, DP_OP_36J19_124_9196_n7,
DP_OP_36J19_124_9196_n6, DP_OP_36J19_124_9196_n5,
DP_OP_36J19_124_9196_n4, DP_OP_36J19_124_9196_n3,
DP_OP_36J19_124_9196_n2, DP_OP_36J19_124_9196_n1, intadd_47_A_24_,
intadd_47_A_23_, intadd_47_A_22_, intadd_47_A_21_, intadd_47_A_20_,
intadd_47_A_19_, intadd_47_A_18_, intadd_47_A_17_, intadd_47_A_16_,
intadd_47_A_15_, intadd_47_A_14_, intadd_47_A_13_, intadd_47_A_12_,
intadd_47_A_11_, intadd_47_A_10_, intadd_47_A_9_, intadd_47_A_8_,
intadd_47_A_7_, intadd_47_A_6_, intadd_47_A_5_, intadd_47_A_4_,
intadd_47_A_3_, intadd_47_A_2_, intadd_47_B_24_, intadd_47_B_23_,
intadd_47_B_22_, intadd_47_B_21_, intadd_47_B_20_, intadd_47_B_19_,
intadd_47_B_18_, intadd_47_B_17_, intadd_47_B_16_, intadd_47_B_15_,
intadd_47_B_14_, intadd_47_B_13_, intadd_47_B_12_, intadd_47_B_11_,
intadd_47_B_10_, intadd_47_B_9_, intadd_47_B_8_, intadd_47_B_7_,
intadd_47_B_6_, intadd_47_B_5_, intadd_47_B_4_, intadd_47_B_3_,
intadd_47_B_2_, intadd_47_B_1_, intadd_47_B_0_, intadd_47_SUM_24_,
intadd_47_SUM_23_, intadd_47_SUM_22_, intadd_47_SUM_21_,
intadd_47_SUM_20_, intadd_47_SUM_19_, intadd_47_SUM_18_,
intadd_47_SUM_17_, intadd_47_SUM_16_, intadd_47_SUM_15_,
intadd_47_SUM_14_, intadd_47_SUM_13_, intadd_47_SUM_12_,
intadd_47_SUM_11_, intadd_47_SUM_10_, intadd_47_SUM_9_,
intadd_47_SUM_8_, intadd_47_SUM_7_, intadd_47_SUM_6_,
intadd_47_SUM_5_, intadd_47_SUM_4_, intadd_47_SUM_3_,
intadd_47_SUM_2_, intadd_47_SUM_1_, intadd_47_SUM_0_, intadd_47_n25,
intadd_47_n24, intadd_47_n23, intadd_47_n22, intadd_47_n21,
intadd_47_n20, intadd_47_n19, intadd_47_n18, intadd_47_n17,
intadd_47_n16, intadd_47_n15, intadd_47_n14, intadd_47_n13,
intadd_47_n12, intadd_47_n11, intadd_47_n10, intadd_47_n9,
intadd_47_n8, intadd_47_n7, intadd_47_n6, intadd_47_n5, intadd_47_n4,
intadd_47_n3, intadd_47_n2, intadd_47_n1, intadd_48_B_23_,
intadd_48_B_22_, intadd_48_B_21_, intadd_48_B_20_, intadd_48_B_19_,
intadd_48_B_18_, intadd_48_B_17_, intadd_48_B_16_, intadd_48_B_15_,
intadd_48_B_14_, intadd_48_B_13_, intadd_48_B_12_, intadd_48_B_11_,
intadd_48_B_10_, intadd_48_B_9_, intadd_48_B_8_, intadd_48_B_7_,
intadd_48_B_6_, intadd_48_B_5_, intadd_48_B_4_, intadd_48_B_3_,
intadd_48_B_2_, intadd_48_B_1_, intadd_48_B_0_, intadd_48_CI,
intadd_48_SUM_23_, intadd_48_SUM_22_, intadd_48_SUM_21_,
intadd_48_SUM_20_, intadd_48_SUM_19_, intadd_48_SUM_18_,
intadd_48_SUM_17_, intadd_48_SUM_16_, intadd_48_SUM_15_,
intadd_48_SUM_14_, intadd_48_SUM_13_, intadd_48_SUM_12_,
intadd_48_SUM_11_, intadd_48_SUM_10_, intadd_48_SUM_9_,
intadd_48_SUM_8_, intadd_48_SUM_7_, intadd_48_SUM_6_,
intadd_48_SUM_5_, intadd_48_SUM_4_, intadd_48_SUM_3_,
intadd_48_SUM_2_, intadd_48_SUM_1_, intadd_48_SUM_0_, intadd_48_n24,
intadd_48_n23, intadd_48_n22, intadd_48_n21, intadd_48_n20,
intadd_48_n19, intadd_48_n18, intadd_48_n17, intadd_48_n16,
intadd_48_n15, intadd_48_n14, intadd_48_n13, intadd_48_n12,
intadd_48_n11, intadd_48_n10, intadd_48_n9, intadd_48_n8,
intadd_48_n7, intadd_48_n6, intadd_48_n5, intadd_48_n4, intadd_48_n3,
intadd_48_n2, intadd_48_n1, intadd_49_A_21_, intadd_49_A_20_,
intadd_49_A_19_, intadd_49_A_18_, intadd_49_A_17_, intadd_49_A_16_,
intadd_49_A_15_, intadd_49_A_14_, intadd_49_A_13_, intadd_49_A_12_,
intadd_49_A_11_, intadd_49_A_10_, intadd_49_A_9_, intadd_49_A_8_,
intadd_49_A_7_, intadd_49_A_6_, intadd_49_A_5_, intadd_49_A_4_,
intadd_49_A_3_, intadd_49_A_2_, intadd_49_A_1_, intadd_49_A_0_,
intadd_49_B_21_, intadd_49_B_20_, intadd_49_B_19_, intadd_49_B_18_,
intadd_49_B_17_, intadd_49_B_16_, intadd_49_B_15_, intadd_49_B_14_,
intadd_49_B_13_, intadd_49_B_12_, intadd_49_B_11_, intadd_49_B_10_,
intadd_49_B_9_, intadd_49_B_8_, intadd_49_B_7_, intadd_49_B_6_,
intadd_49_B_5_, intadd_49_B_4_, intadd_49_B_3_, intadd_49_B_2_,
intadd_49_B_1_, intadd_49_B_0_, intadd_49_CI, intadd_49_SUM_21_,
intadd_49_SUM_20_, intadd_49_SUM_19_, intadd_49_SUM_18_,
intadd_49_SUM_17_, intadd_49_SUM_16_, intadd_49_SUM_15_,
intadd_49_SUM_14_, intadd_49_SUM_13_, intadd_49_SUM_12_,
intadd_49_SUM_11_, intadd_49_SUM_10_, intadd_49_SUM_9_,
intadd_49_SUM_8_, intadd_49_SUM_7_, intadd_49_SUM_6_,
intadd_49_SUM_5_, intadd_49_SUM_4_, intadd_49_SUM_3_,
intadd_49_SUM_2_, intadd_49_SUM_1_, intadd_49_SUM_0_, intadd_49_n22,
intadd_49_n21, intadd_49_n20, intadd_49_n19, intadd_49_n18,
intadd_49_n17, intadd_49_n16, intadd_49_n15, intadd_49_n14,
intadd_49_n13, intadd_49_n12, intadd_49_n11, intadd_49_n10,
intadd_49_n9, intadd_49_n8, intadd_49_n7, intadd_49_n6, intadd_49_n5,
intadd_49_n4, intadd_49_n3, intadd_49_n2, intadd_49_n1,
intadd_50_A_19_, intadd_50_A_18_, intadd_50_A_17_, intadd_50_A_16_,
intadd_50_A_15_, intadd_50_A_14_, intadd_50_A_13_, intadd_50_A_12_,
intadd_50_A_11_, intadd_50_A_10_, intadd_50_A_9_, intadd_50_A_8_,
intadd_50_A_7_, intadd_50_A_6_, intadd_50_A_5_, intadd_50_A_4_,
intadd_50_A_3_, intadd_50_A_2_, intadd_50_A_1_, intadd_50_A_0_,
intadd_50_B_19_, intadd_50_B_18_, intadd_50_B_17_, intadd_50_B_16_,
intadd_50_B_15_, intadd_50_B_14_, intadd_50_B_13_, intadd_50_B_12_,
intadd_50_B_11_, intadd_50_B_10_, intadd_50_B_9_, intadd_50_B_8_,
intadd_50_B_7_, intadd_50_B_6_, intadd_50_B_5_, intadd_50_B_4_,
intadd_50_B_3_, intadd_50_B_2_, intadd_50_B_1_, intadd_50_B_0_,
intadd_50_CI, intadd_50_SUM_19_, intadd_50_SUM_18_, intadd_50_SUM_17_,
intadd_50_SUM_16_, intadd_50_SUM_15_, intadd_50_SUM_14_,
intadd_50_SUM_13_, intadd_50_SUM_12_, intadd_50_SUM_11_,
intadd_50_SUM_10_, intadd_50_SUM_9_, intadd_50_SUM_8_,
intadd_50_SUM_7_, intadd_50_SUM_6_, intadd_50_SUM_5_,
intadd_50_SUM_4_, intadd_50_SUM_3_, intadd_50_SUM_2_,
intadd_50_SUM_1_, intadd_50_SUM_0_, intadd_50_n20, intadd_50_n19,
intadd_50_n18, intadd_50_n17, intadd_50_n16, intadd_50_n15,
intadd_50_n14, intadd_50_n13, intadd_50_n12, intadd_50_n11,
intadd_50_n10, intadd_50_n9, intadd_50_n8, intadd_50_n7, intadd_50_n6,
intadd_50_n5, intadd_50_n4, intadd_50_n3, intadd_50_n2, intadd_50_n1,
intadd_51_A_19_, intadd_51_A_18_, intadd_51_A_17_, intadd_51_A_16_,
intadd_51_A_15_, intadd_51_A_14_, intadd_51_A_13_, intadd_51_A_12_,
intadd_51_A_11_, intadd_51_A_10_, intadd_51_A_9_, intadd_51_A_8_,
intadd_51_A_7_, intadd_51_A_6_, intadd_51_A_5_, intadd_51_A_4_,
intadd_51_A_3_, intadd_51_A_2_, intadd_51_A_1_, intadd_51_A_0_,
intadd_51_B_19_, intadd_51_B_18_, intadd_51_B_17_, intadd_51_B_16_,
intadd_51_B_15_, intadd_51_B_14_, intadd_51_B_13_, intadd_51_B_12_,
intadd_51_B_11_, intadd_51_B_10_, intadd_51_B_9_, intadd_51_B_8_,
intadd_51_B_7_, intadd_51_B_6_, intadd_51_B_5_, intadd_51_B_4_,
intadd_51_B_3_, intadd_51_B_2_, intadd_51_B_1_, intadd_51_B_0_,
intadd_51_CI, intadd_51_SUM_19_, intadd_51_SUM_18_, intadd_51_SUM_17_,
intadd_51_SUM_16_, intadd_51_SUM_15_, intadd_51_SUM_14_,
intadd_51_SUM_13_, intadd_51_SUM_12_, intadd_51_SUM_11_,
intadd_51_SUM_10_, intadd_51_SUM_9_, intadd_51_SUM_8_,
intadd_51_SUM_7_, intadd_51_SUM_6_, intadd_51_SUM_5_,
intadd_51_SUM_4_, intadd_51_SUM_3_, intadd_51_SUM_2_,
intadd_51_SUM_1_, intadd_51_SUM_0_, intadd_51_n20, intadd_51_n19,
intadd_51_n18, intadd_51_n17, intadd_51_n16, intadd_51_n15,
intadd_51_n14, intadd_51_n13, intadd_51_n12, intadd_51_n11,
intadd_51_n10, intadd_51_n9, intadd_51_n8, intadd_51_n7, intadd_51_n6,
intadd_51_n5, intadd_51_n4, intadd_51_n3, intadd_51_n2, intadd_51_n1,
intadd_52_CI, intadd_52_SUM_9_, intadd_52_SUM_8_, intadd_52_SUM_7_,
intadd_52_SUM_6_, intadd_52_SUM_5_, intadd_52_SUM_4_,
intadd_52_SUM_3_, intadd_52_SUM_2_, intadd_52_SUM_1_,
intadd_52_SUM_0_, intadd_52_n10, intadd_52_n9, intadd_52_n8,
intadd_52_n7, intadd_52_n6, intadd_52_n5, intadd_52_n4, intadd_52_n3,
intadd_52_n2, intadd_52_n1, intadd_53_CI, intadd_53_SUM_9_,
intadd_53_SUM_8_, intadd_53_SUM_7_, intadd_53_SUM_6_,
intadd_53_SUM_5_, intadd_53_SUM_4_, intadd_53_SUM_3_,
intadd_53_SUM_2_, intadd_53_SUM_1_, intadd_53_SUM_0_, intadd_53_n10,
intadd_53_n9, intadd_53_n8, intadd_53_n7, intadd_53_n6, intadd_53_n5,
intadd_53_n4, intadd_53_n3, intadd_53_n2, intadd_53_n1, n390, n391,
n392, n393, n394, n395, n396, n397, n398, n399, n400, n401, n402,
n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, n413,
n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424,
n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446,
n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457,
n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468,
n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479,
n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490,
n491, n492, n493, n494, n495, n496, n497, n498, n499, n500, n501,
n502, n503, n504, n505, n506, n507, n508, n509, n510, n511, n512,
n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, n523,
n524, n525, n526, n527, n528, n529, n530, n531, n532, n533, n534,
n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, n545,
n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556,
n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578,
n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589,
n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600,
n601, n602, n603, n604, n605, n606, n607, n608, n609, n610, n611,
n612, n613, n614, n615, n616, n617, n618, n619, n620, n621, n622,
n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, n633,
n634, n635, n636, n637, n638, n639, n640, n641, n642, n643, n644,
n645, n646, n647, n648, n649, n650, n651, n652, n653, n654, n655,
n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, n666,
n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712,
n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734,
n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745,
n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756,
n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767,
n768, n769, n770, n771, n772, n773, n774, n775, n776, n777, n778,
n779, n780, n781, n782, n783, n784, n785, n786, n787, n788, n789,
n790, n791, n792, n793, n794, n795, n796, n797, n798, n799, n800,
n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811,
n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822,
n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833,
n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844,
n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888,
n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910,
n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921,
n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954,
n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965,
n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976,
n977, n978, n979, n980, n981, n982, n983, n984, n985, n986, n987,
n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998,
n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008,
n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018,
n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028,
n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038,
n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048,
n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058,
n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068,
n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078,
n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088,
n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098,
n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108,
n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118,
n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128,
n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138,
n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148,
n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218,
n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278,
n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288,
n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298,
n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308,
n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318,
n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328,
n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338,
n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348,
n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358,
n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368,
n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378,
n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388,
n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398,
n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408,
n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418,
n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428,
n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438,
n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448,
n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458,
n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468,
n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478,
n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488,
n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498,
n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508,
n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518,
n1519, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548;
wire [47:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
wire [11:0] Sgf_operation_Result;
wire [25:0] Sgf_operation_EVEN1_Q_middle;
wire [23:12] Sgf_operation_EVEN1_Q_right;
wire [23:0] Sgf_operation_EVEN1_Q_left;
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n311), .CK(clk), .RN(
n1539), .Q(Op_MY[31]) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n354), .CK(clk), .RN(
n1544), .Q(Op_MX[9]) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n350), .CK(clk), .RN(
n1544), .Q(Op_MX[5]), .QN(n1498) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n348), .CK(clk), .RN(
n1544), .Q(Op_MX[3]), .QN(n1495) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n344), .CK(clk), .RN(
n1543), .Q(Op_MX[31]) );
DFFRXLTS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n283), .CK(clk), .RN(
n1541), .Q(FSM_add_overflow_flag) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n340), .CK(clk), .RN(
n1541), .Q(Op_MY[27]), .QN(n610) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n339), .CK(clk), .RN(
n1540), .Q(Op_MY[26]), .QN(n611) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n338), .CK(clk), .RN(
n1540), .Q(Op_MY[25]), .QN(n612) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n337), .CK(clk), .RN(
n1540), .Q(Op_MY[24]), .QN(n609) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n334), .CK(clk), .RN(
n1540), .Q(Op_MY[21]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n333), .CK(clk), .RN(
n1540), .Q(Op_MY[20]), .QN(n623) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n332), .CK(clk), .RN(
n1540), .Q(Op_MY[19]), .QN(n403) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n331), .CK(clk), .RN(
n1540), .Q(Op_MY[18]), .QN(n628) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n329), .CK(clk), .RN(
n1539), .Q(Op_MY[16]), .QN(n621) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n328), .CK(clk), .RN(
n1539), .Q(Op_MY[15]), .QN(n626) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n327), .CK(clk), .RN(
n1539), .Q(Op_MY[14]), .QN(n618) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n325), .CK(clk), .RN(
n1539), .Q(Op_MY[12]), .QN(n625) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n324), .CK(clk), .RN(
n1539), .Q(Op_MY[11]), .QN(n549) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n323), .CK(clk), .RN(
n1539), .Q(Op_MY[10]), .QN(n395) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n322), .CK(clk), .RN(
n1539), .Q(Op_MY[9]), .QN(n620) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n321), .CK(clk), .RN(
n1539), .Q(Op_MY[8]), .QN(n627) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n320), .CK(clk), .RN(
n1538), .Q(Op_MY[7]), .QN(n624) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n319), .CK(clk), .RN(
n1538), .Q(Op_MY[6]), .QN(n402) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n318), .CK(clk), .RN(
n1538), .Q(Op_MY[5]), .QN(n608) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n316), .CK(clk), .RN(
n1538), .Q(Op_MY[3]), .QN(n615) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n315), .CK(clk), .RN(
n1538), .Q(Op_MY[2]), .QN(n617) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n314), .CK(clk), .RN(
n1538), .Q(Op_MY[1]), .QN(n614) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n313), .CK(clk), .RN(
n1538), .Q(Op_MY[0]), .QN(n619) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n312), .CK(clk),
.RN(n1538), .Q(zero_flag), .QN(n613) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(n260), .CK(clk), .RN(
n1526), .Q(P_Sgf[44]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(n258), .CK(clk), .RN(
n1526), .Q(P_Sgf[42]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(n256), .CK(clk), .RN(
n1526), .Q(P_Sgf[40]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(n254), .CK(clk), .RN(
n1527), .Q(P_Sgf[38]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n239), .CK(clk), .RN(
n1528), .Q(P_Sgf[23]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n238), .CK(clk), .RN(
n1528), .Q(P_Sgf[22]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n237), .CK(clk), .RN(
n1528), .Q(P_Sgf[21]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n236), .CK(clk), .RN(
n1528), .Q(P_Sgf[20]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n235), .CK(clk), .RN(
n1528), .Q(P_Sgf[19]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n234), .CK(clk), .RN(
n1528), .Q(P_Sgf[18]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n233), .CK(clk), .RN(
n1529), .Q(P_Sgf[17]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n232), .CK(clk), .RN(
n1529), .Q(P_Sgf[16]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n231), .CK(clk), .RN(
n1529), .Q(P_Sgf[15]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n230), .CK(clk), .RN(
n1529), .Q(P_Sgf[14]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n229), .CK(clk), .RN(
n1529), .Q(P_Sgf[13]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n228), .CK(clk), .RN(
n1529), .Q(P_Sgf[12]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n227), .CK(clk), .RN(
n1529), .Q(P_Sgf[11]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n226), .CK(clk), .RN(
n1529), .Q(P_Sgf[10]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n225), .CK(clk), .RN(
n1529), .Q(P_Sgf[9]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n224), .CK(clk), .RN(
n1529), .Q(P_Sgf[8]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n223), .CK(clk), .RN(
n1530), .Q(P_Sgf[7]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n222), .CK(clk), .RN(
n1530), .Q(P_Sgf[6]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n221), .CK(clk), .RN(
n1530), .Q(P_Sgf[5]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n220), .CK(clk), .RN(
n1530), .Q(P_Sgf[4]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n219), .CK(clk), .RN(
n1530), .Q(P_Sgf[3]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n218), .CK(clk), .RN(
n1530), .Q(P_Sgf[2]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n217), .CK(clk), .RN(
n1530), .Q(P_Sgf[1]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n216), .CK(clk), .RN(
n1530), .Q(P_Sgf[0]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n308), .CK(clk),
.RN(n1536), .Q(Sgf_normalized_result[23]) );
CMPR42X1TS DP_OP_111J19_123_4462_U75 ( .A(DP_OP_111J19_123_4462_n240), .B(
DP_OP_111J19_123_4462_n227), .C(DP_OP_111J19_123_4462_n148), .D(
DP_OP_111J19_123_4462_n252), .ICI(DP_OP_111J19_123_4462_n214), .S(
DP_OP_111J19_123_4462_n145), .ICO(DP_OP_111J19_123_4462_n143), .CO(
DP_OP_111J19_123_4462_n144) );
CMPR42X1TS DP_OP_111J19_123_4462_U73 ( .A(DP_OP_111J19_123_4462_n143), .B(
DP_OP_111J19_123_4462_n251), .C(DP_OP_111J19_123_4462_n142), .D(
DP_OP_111J19_123_4462_n213), .ICI(DP_OP_111J19_123_4462_n156), .S(
DP_OP_111J19_123_4462_n140), .ICO(DP_OP_111J19_123_4462_n138), .CO(
DP_OP_111J19_123_4462_n139) );
CMPR42X1TS DP_OP_111J19_123_4462_U71 ( .A(DP_OP_111J19_123_4462_n212), .B(
DP_OP_111J19_123_4462_n137), .C(DP_OP_111J19_123_4462_n138), .D(
DP_OP_111J19_123_4462_n250), .ICI(DP_OP_111J19_123_4462_n200), .S(
DP_OP_111J19_123_4462_n135), .ICO(DP_OP_111J19_123_4462_n133), .CO(
DP_OP_111J19_123_4462_n134) );
CMPR42X1TS DP_OP_111J19_123_4462_U68 ( .A(DP_OP_111J19_123_4462_n133), .B(
DP_OP_111J19_123_4462_n249), .C(DP_OP_111J19_123_4462_n130), .D(
DP_OP_111J19_123_4462_n199), .ICI(DP_OP_111J19_123_4462_n155), .S(
DP_OP_111J19_123_4462_n128), .ICO(DP_OP_111J19_123_4462_n126), .CO(
DP_OP_111J19_123_4462_n127) );
CMPR42X1TS DP_OP_111J19_123_4462_U67 ( .A(DP_OP_111J19_123_4462_n223), .B(
DP_OP_111J19_123_4462_n210), .C(DP_OP_111J19_123_4462_n131), .D(
DP_OP_111J19_123_4462_n236), .ICI(DP_OP_111J19_123_4462_n129), .S(
DP_OP_111J19_123_4462_n125), .ICO(DP_OP_111J19_123_4462_n123), .CO(
DP_OP_111J19_123_4462_n124) );
CMPR42X1TS DP_OP_111J19_123_4462_U66 ( .A(DP_OP_111J19_123_4462_n198), .B(
DP_OP_111J19_123_4462_n248), .C(DP_OP_111J19_123_4462_n187), .D(
DP_OP_111J19_123_4462_n126), .ICI(DP_OP_111J19_123_4462_n125), .S(
DP_OP_111J19_123_4462_n122), .ICO(DP_OP_111J19_123_4462_n120), .CO(
DP_OP_111J19_123_4462_n121) );
CMPR42X1TS DP_OP_111J19_123_4462_U64 ( .A(DP_OP_111J19_123_4462_n123), .B(
DP_OP_111J19_123_4462_n235), .C(DP_OP_111J19_123_4462_n119), .D(
DP_OP_111J19_123_4462_n197), .ICI(DP_OP_111J19_123_4462_n124), .S(
DP_OP_111J19_123_4462_n117), .ICO(DP_OP_111J19_123_4462_n115), .CO(
DP_OP_111J19_123_4462_n116) );
CMPR42X1TS DP_OP_111J19_123_4462_U63 ( .A(DP_OP_111J19_123_4462_n120), .B(
DP_OP_111J19_123_4462_n117), .C(DP_OP_111J19_123_4462_n247), .D(
DP_OP_111J19_123_4462_n121), .ICI(DP_OP_111J19_123_4462_n186), .S(
DP_OP_111J19_123_4462_n114), .ICO(DP_OP_111J19_123_4462_n112), .CO(
DP_OP_111J19_123_4462_n113) );
CMPR42X1TS DP_OP_111J19_123_4462_U61 ( .A(DP_OP_111J19_123_4462_n196), .B(
DP_OP_111J19_123_4462_n111), .C(DP_OP_111J19_123_4462_n115), .D(
DP_OP_111J19_123_4462_n234), .ICI(DP_OP_111J19_123_4462_n116), .S(
DP_OP_111J19_123_4462_n109), .ICO(DP_OP_111J19_123_4462_n107), .CO(
DP_OP_111J19_123_4462_n108) );
CMPR42X1TS DP_OP_111J19_123_4462_U60 ( .A(DP_OP_111J19_123_4462_n246), .B(
DP_OP_111J19_123_4462_n172), .C(DP_OP_111J19_123_4462_n185), .D(
DP_OP_111J19_123_4462_n109), .ICI(DP_OP_111J19_123_4462_n112), .S(
DP_OP_111J19_123_4462_n106), .ICO(DP_OP_111J19_123_4462_n104), .CO(
DP_OP_111J19_123_4462_n105) );
CMPR42X1TS DP_OP_111J19_123_4462_U58 ( .A(DP_OP_111J19_123_4462_n195), .B(
DP_OP_111J19_123_4462_n245), .C(DP_OP_111J19_123_4462_n103), .D(
DP_OP_111J19_123_4462_n107), .ICI(DP_OP_111J19_123_4462_n233), .S(
DP_OP_111J19_123_4462_n101), .ICO(DP_OP_111J19_123_4462_n99), .CO(
DP_OP_111J19_123_4462_n100) );
CMPR42X1TS DP_OP_111J19_123_4462_U57 ( .A(DP_OP_111J19_123_4462_n108), .B(
DP_OP_111J19_123_4462_n171), .C(DP_OP_111J19_123_4462_n184), .D(
DP_OP_111J19_123_4462_n101), .ICI(DP_OP_111J19_123_4462_n104), .S(
DP_OP_111J19_123_4462_n98), .ICO(DP_OP_111J19_123_4462_n96), .CO(
DP_OP_111J19_123_4462_n97) );
CMPR42X1TS DP_OP_111J19_123_4462_U54 ( .A(DP_OP_111J19_123_4462_n219), .B(
DP_OP_111J19_123_4462_n102), .C(DP_OP_111J19_123_4462_n94), .D(
DP_OP_111J19_123_4462_n99), .ICI(DP_OP_111J19_123_4462_n232), .S(
DP_OP_111J19_123_4462_n92), .ICO(DP_OP_111J19_123_4462_n90), .CO(
DP_OP_111J19_123_4462_n91) );
CMPR42X1TS DP_OP_111J19_123_4462_U53 ( .A(DP_OP_111J19_123_4462_n170), .B(
DP_OP_111J19_123_4462_n183), .C(DP_OP_111J19_123_4462_n100), .D(
DP_OP_111J19_123_4462_n96), .ICI(DP_OP_111J19_123_4462_n92), .S(
DP_OP_111J19_123_4462_n89), .ICO(DP_OP_111J19_123_4462_n87), .CO(
DP_OP_111J19_123_4462_n88) );
CMPR42X1TS DP_OP_111J19_123_4462_U50 ( .A(DP_OP_111J19_123_4462_n231), .B(
DP_OP_111J19_123_4462_n93), .C(DP_OP_111J19_123_4462_n84), .D(
DP_OP_111J19_123_4462_n90), .ICI(DP_OP_111J19_123_4462_n218), .S(
DP_OP_111J19_123_4462_n82), .ICO(DP_OP_111J19_123_4462_n80), .CO(
DP_OP_111J19_123_4462_n81) );
CMPR42X1TS DP_OP_111J19_123_4462_U49 ( .A(DP_OP_111J19_123_4462_n169), .B(
DP_OP_111J19_123_4462_n182), .C(DP_OP_111J19_123_4462_n91), .D(
DP_OP_111J19_123_4462_n87), .ICI(DP_OP_111J19_123_4462_n82), .S(
DP_OP_111J19_123_4462_n79), .ICO(DP_OP_111J19_123_4462_n77), .CO(
DP_OP_111J19_123_4462_n78) );
CMPR42X1TS DP_OP_111J19_123_4462_U47 ( .A(DP_OP_111J19_123_4462_n204), .B(
DP_OP_111J19_123_4462_n83), .C(DP_OP_111J19_123_4462_n76), .D(
DP_OP_111J19_123_4462_n80), .ICI(DP_OP_111J19_123_4462_n217), .S(
DP_OP_111J19_123_4462_n74), .ICO(DP_OP_111J19_123_4462_n72), .CO(
DP_OP_111J19_123_4462_n73) );
CMPR42X1TS DP_OP_111J19_123_4462_U46 ( .A(DP_OP_111J19_123_4462_n168), .B(
DP_OP_111J19_123_4462_n181), .C(DP_OP_111J19_123_4462_n81), .D(
DP_OP_111J19_123_4462_n74), .ICI(DP_OP_111J19_123_4462_n77), .S(
DP_OP_111J19_123_4462_n71), .ICO(DP_OP_111J19_123_4462_n69), .CO(
DP_OP_111J19_123_4462_n70) );
CMPR42X1TS DP_OP_111J19_123_4462_U44 ( .A(DP_OP_111J19_123_4462_n68), .B(
DP_OP_111J19_123_4462_n216), .C(DP_OP_111J19_123_4462_n75), .D(
DP_OP_111J19_123_4462_n72), .ICI(DP_OP_111J19_123_4462_n203), .S(
DP_OP_111J19_123_4462_n66), .ICO(DP_OP_111J19_123_4462_n64), .CO(
DP_OP_111J19_123_4462_n65) );
CMPR42X1TS DP_OP_111J19_123_4462_U43 ( .A(DP_OP_111J19_123_4462_n167), .B(
DP_OP_111J19_123_4462_n180), .C(DP_OP_111J19_123_4462_n73), .D(
DP_OP_111J19_123_4462_n66), .ICI(DP_OP_111J19_123_4462_n69), .S(
DP_OP_111J19_123_4462_n63), .ICO(DP_OP_111J19_123_4462_n61), .CO(
DP_OP_111J19_123_4462_n62) );
CMPR42X1TS DP_OP_111J19_123_4462_U42 ( .A(DP_OP_111J19_123_4462_n215), .B(
DP_OP_111J19_123_4462_n67), .C(DP_OP_111J19_123_4462_n191), .D(
DP_OP_111J19_123_4462_n64), .ICI(DP_OP_111J19_123_4462_n202), .S(
DP_OP_111J19_123_4462_n60), .ICO(DP_OP_111J19_123_4462_n58), .CO(
DP_OP_111J19_123_4462_n59) );
CMPR42X1TS DP_OP_111J19_123_4462_U41 ( .A(DP_OP_111J19_123_4462_n166), .B(
DP_OP_111J19_123_4462_n179), .C(DP_OP_111J19_123_4462_n65), .D(
DP_OP_111J19_123_4462_n60), .ICI(DP_OP_111J19_123_4462_n61), .S(
DP_OP_111J19_123_4462_n57), .ICO(DP_OP_111J19_123_4462_n55), .CO(
DP_OP_111J19_123_4462_n56) );
CMPR42X1TS DP_OP_111J19_123_4462_U38 ( .A(DP_OP_111J19_123_4462_n165), .B(
DP_OP_111J19_123_4462_n178), .C(DP_OP_111J19_123_4462_n52), .D(
DP_OP_111J19_123_4462_n59), .ICI(DP_OP_111J19_123_4462_n55), .S(
DP_OP_111J19_123_4462_n50), .ICO(DP_OP_111J19_123_4462_n48), .CO(
DP_OP_111J19_123_4462_n49) );
CMPR42X1TS DP_OP_111J19_123_4462_U36 ( .A(DP_OP_111J19_123_4462_n164), .B(
DP_OP_111J19_123_4462_n177), .C(DP_OP_111J19_123_4462_n51), .D(
DP_OP_111J19_123_4462_n47), .ICI(DP_OP_111J19_123_4462_n48), .S(
DP_OP_111J19_123_4462_n45), .ICO(DP_OP_111J19_123_4462_n43), .CO(
DP_OP_111J19_123_4462_n44) );
CMPR42X1TS DP_OP_111J19_123_4462_U34 ( .A(DP_OP_111J19_123_4462_n42), .B(
DP_OP_111J19_123_4462_n163), .C(DP_OP_111J19_123_4462_n176), .D(
DP_OP_111J19_123_4462_n46), .ICI(DP_OP_111J19_123_4462_n43), .S(
DP_OP_111J19_123_4462_n40), .ICO(DP_OP_111J19_123_4462_n38), .CO(
DP_OP_111J19_123_4462_n39) );
CMPR42X1TS DP_OP_111J19_123_4462_U33 ( .A(DP_OP_111J19_123_4462_n188), .B(
DP_OP_111J19_123_4462_n41), .C(DP_OP_111J19_123_4462_n162), .D(
DP_OP_111J19_123_4462_n175), .ICI(DP_OP_111J19_123_4462_n38), .S(
DP_OP_111J19_123_4462_n37), .ICO(DP_OP_111J19_123_4462_n35), .CO(
DP_OP_111J19_123_4462_n36) );
CMPR42X1TS mult_x_55_U69 ( .A(mult_x_55_n196), .B(mult_x_55_n232), .C(
mult_x_55_n220), .D(n557), .ICI(mult_x_55_n136), .S(mult_x_55_n133),
.ICO(mult_x_55_n131), .CO(mult_x_55_n132) );
CMPR42X1TS mult_x_55_U67 ( .A(mult_x_55_n219), .B(mult_x_55_n195), .C(
mult_x_55_n207), .D(mult_x_55_n131), .ICI(mult_x_55_n130), .S(
mult_x_55_n128), .ICO(mult_x_55_n126), .CO(mult_x_55_n127) );
CMPR42X1TS mult_x_55_U65 ( .A(mult_x_55_n206), .B(mult_x_55_n194), .C(
mult_x_55_n129), .D(mult_x_55_n126), .ICI(mult_x_55_n125), .S(
mult_x_55_n123), .ICO(mult_x_55_n121), .CO(mult_x_55_n122) );
CMPR42X1TS mult_x_55_U62 ( .A(mult_x_55_n205), .B(mult_x_55_n124), .C(
mult_x_55_n120), .D(mult_x_55_n118), .ICI(mult_x_55_n121), .S(
mult_x_55_n116), .ICO(mult_x_55_n114), .CO(mult_x_55_n115) );
CMPR42X1TS mult_x_55_U61 ( .A(mult_x_55_n168), .B(mult_x_55_n228), .C(
mult_x_55_n216), .D(mult_x_55_n204), .ICI(mult_x_55_n180), .S(
mult_x_55_n113), .ICO(mult_x_55_n111), .CO(mult_x_55_n112) );
CMPR42X1TS mult_x_55_U60 ( .A(mult_x_55_n192), .B(mult_x_55_n119), .C(
mult_x_55_n117), .D(mult_x_55_n114), .ICI(mult_x_55_n113), .S(
mult_x_55_n110), .ICO(mult_x_55_n108), .CO(mult_x_55_n109) );
CMPR42X1TS mult_x_55_U58 ( .A(mult_x_55_n215), .B(mult_x_55_n167), .C(
mult_x_55_n203), .D(mult_x_55_n179), .ICI(mult_x_55_n107), .S(
mult_x_55_n105), .ICO(mult_x_55_n103), .CO(mult_x_55_n104) );
CMPR42X1TS mult_x_55_U57 ( .A(mult_x_55_n191), .B(mult_x_55_n111), .C(
mult_x_55_n108), .D(mult_x_55_n112), .ICI(mult_x_55_n105), .S(
mult_x_55_n102), .ICO(mult_x_55_n100), .CO(mult_x_55_n101) );
CMPR42X1TS mult_x_55_U55 ( .A(mult_x_55_n202), .B(mult_x_55_n166), .C(
mult_x_55_n190), .D(mult_x_55_n178), .ICI(mult_x_55_n99), .S(
mult_x_55_n97), .ICO(mult_x_55_n95), .CO(mult_x_55_n96) );
CMPR42X1TS mult_x_55_U54 ( .A(mult_x_55_n106), .B(mult_x_55_n103), .C(
mult_x_55_n104), .D(mult_x_55_n97), .ICI(mult_x_55_n100), .S(
mult_x_55_n94), .ICO(mult_x_55_n92), .CO(mult_x_55_n93) );
CMPR42X1TS mult_x_55_U51 ( .A(mult_x_55_n189), .B(mult_x_55_n165), .C(
mult_x_55_n213), .D(n669), .ICI(mult_x_55_n90), .S(mult_x_55_n88),
.ICO(mult_x_55_n86), .CO(mult_x_55_n87) );
CMPR42X1TS mult_x_55_U50 ( .A(mult_x_55_n95), .B(mult_x_55_n98), .C(
mult_x_55_n96), .D(mult_x_55_n88), .ICI(mult_x_55_n92), .S(
mult_x_55_n85), .ICO(mult_x_55_n83), .CO(mult_x_55_n84) );
CMPR42X1TS mult_x_55_U47 ( .A(mult_x_55_n176), .B(mult_x_55_n212), .C(
mult_x_55_n200), .D(mult_x_55_n164), .ICI(mult_x_55_n89), .S(
mult_x_55_n78), .ICO(mult_x_55_n76), .CO(mult_x_55_n77) );
CMPR42X1TS mult_x_55_U46 ( .A(mult_x_55_n86), .B(mult_x_55_n80), .C(
mult_x_55_n87), .D(mult_x_55_n78), .ICI(mult_x_55_n83), .S(
mult_x_55_n75), .ICO(mult_x_55_n73), .CO(mult_x_55_n74) );
CMPR42X1TS mult_x_55_U44 ( .A(mult_x_55_n175), .B(mult_x_55_n163), .C(
mult_x_55_n199), .D(mult_x_55_n211), .ICI(mult_x_55_n72), .S(
mult_x_55_n70), .ICO(mult_x_55_n68), .CO(mult_x_55_n69) );
CMPR42X1TS mult_x_55_U43 ( .A(mult_x_55_n76), .B(mult_x_55_n79), .C(
mult_x_55_n77), .D(mult_x_55_n70), .ICI(mult_x_55_n73), .S(
mult_x_55_n67), .ICO(mult_x_55_n65), .CO(mult_x_55_n66) );
CMPR42X1TS mult_x_55_U41 ( .A(mult_x_55_n64), .B(mult_x_55_n174), .C(
mult_x_55_n186), .D(mult_x_55_n162), .ICI(mult_x_55_n198), .S(
mult_x_55_n62), .ICO(mult_x_55_n60), .CO(mult_x_55_n61) );
CMPR42X1TS mult_x_55_U40 ( .A(mult_x_55_n68), .B(mult_x_55_n71), .C(
mult_x_55_n69), .D(mult_x_55_n62), .ICI(mult_x_55_n65), .S(
mult_x_55_n59), .ICO(mult_x_55_n57), .CO(mult_x_55_n58) );
CMPR42X1TS mult_x_55_U39 ( .A(mult_x_55_n63), .B(mult_x_55_n151), .C(
mult_x_55_n185), .D(mult_x_55_n173), .ICI(mult_x_55_n161), .S(
mult_x_55_n56), .ICO(mult_x_55_n54), .CO(mult_x_55_n55) );
CMPR42X1TS mult_x_55_U38 ( .A(mult_x_55_n197), .B(mult_x_55_n60), .C(
mult_x_55_n61), .D(mult_x_55_n56), .ICI(mult_x_55_n57), .S(
mult_x_55_n53), .ICO(mult_x_55_n51), .CO(mult_x_55_n52) );
CMPR42X1TS mult_x_55_U35 ( .A(mult_x_55_n160), .B(mult_x_55_n54), .C(
mult_x_55_n48), .D(mult_x_55_n55), .ICI(mult_x_55_n51), .S(
mult_x_55_n46), .ICO(mult_x_55_n44), .CO(mult_x_55_n45) );
CMPR42X1TS mult_x_55_U33 ( .A(mult_x_55_n159), .B(mult_x_55_n183), .C(
mult_x_55_n43), .D(mult_x_55_n47), .ICI(mult_x_55_n44), .S(
mult_x_55_n41), .ICO(mult_x_55_n39), .CO(mult_x_55_n40) );
CMPR42X1TS mult_x_55_U31 ( .A(mult_x_55_n38), .B(mult_x_55_n170), .C(
mult_x_55_n158), .D(mult_x_55_n42), .ICI(mult_x_55_n39), .S(
mult_x_55_n36), .ICO(mult_x_55_n34), .CO(mult_x_55_n35) );
CMPR42X1TS mult_x_55_U30 ( .A(mult_x_55_n37), .B(mult_x_55_n149), .C(
mult_x_55_n157), .D(mult_x_55_n169), .ICI(mult_x_55_n34), .S(
mult_x_55_n33), .ICO(mult_x_55_n31), .CO(mult_x_55_n32) );
CMPR42X1TS mult_x_23_U69 ( .A(mult_x_23_n190), .B(mult_x_23_n226), .C(
mult_x_23_n214), .D(mult_x_23_n202), .ICI(mult_x_23_n136), .S(
mult_x_23_n133), .ICO(mult_x_23_n131), .CO(mult_x_23_n132) );
CMPR42X1TS mult_x_23_U67 ( .A(mult_x_23_n213), .B(mult_x_23_n189), .C(
mult_x_23_n201), .D(mult_x_23_n131), .ICI(mult_x_23_n130), .S(
mult_x_23_n128), .ICO(mult_x_23_n126), .CO(mult_x_23_n127) );
CMPR42X1TS mult_x_23_U65 ( .A(mult_x_23_n200), .B(mult_x_23_n188), .C(
mult_x_23_n129), .D(mult_x_23_n126), .ICI(mult_x_23_n125), .S(
mult_x_23_n123), .ICO(mult_x_23_n121), .CO(mult_x_23_n122) );
CMPR42X1TS mult_x_23_U62 ( .A(mult_x_23_n199), .B(mult_x_23_n124), .C(
mult_x_23_n120), .D(mult_x_23_n118), .ICI(mult_x_23_n121), .S(
mult_x_23_n116), .ICO(mult_x_23_n114), .CO(mult_x_23_n115) );
CMPR42X1TS mult_x_23_U61 ( .A(mult_x_23_n162), .B(mult_x_23_n222), .C(
mult_x_23_n210), .D(mult_x_23_n198), .ICI(mult_x_23_n174), .S(
mult_x_23_n113), .ICO(mult_x_23_n111), .CO(mult_x_23_n112) );
CMPR42X1TS mult_x_23_U60 ( .A(mult_x_23_n186), .B(mult_x_23_n119), .C(
mult_x_23_n117), .D(mult_x_23_n114), .ICI(mult_x_23_n113), .S(
mult_x_23_n110), .ICO(mult_x_23_n108), .CO(mult_x_23_n109) );
CMPR42X1TS mult_x_23_U58 ( .A(mult_x_23_n209), .B(mult_x_23_n161), .C(
mult_x_23_n197), .D(mult_x_23_n173), .ICI(mult_x_23_n107), .S(
mult_x_23_n105), .ICO(mult_x_23_n103), .CO(mult_x_23_n104) );
CMPR42X1TS mult_x_23_U57 ( .A(mult_x_23_n185), .B(mult_x_23_n111), .C(
mult_x_23_n108), .D(mult_x_23_n112), .ICI(mult_x_23_n105), .S(
mult_x_23_n102), .ICO(mult_x_23_n100), .CO(mult_x_23_n101) );
CMPR42X1TS mult_x_23_U55 ( .A(mult_x_23_n196), .B(mult_x_23_n160), .C(
mult_x_23_n184), .D(mult_x_23_n172), .ICI(mult_x_23_n99), .S(
mult_x_23_n97), .ICO(mult_x_23_n95), .CO(mult_x_23_n96) );
CMPR42X1TS mult_x_23_U54 ( .A(mult_x_23_n106), .B(mult_x_23_n103), .C(
mult_x_23_n104), .D(mult_x_23_n97), .ICI(mult_x_23_n100), .S(
mult_x_23_n94), .ICO(mult_x_23_n92), .CO(mult_x_23_n93) );
CMPR42X1TS mult_x_23_U51 ( .A(mult_x_23_n183), .B(mult_x_23_n159), .C(
mult_x_23_n207), .D(mult_x_23_n219), .ICI(mult_x_23_n90), .S(
mult_x_23_n88), .ICO(mult_x_23_n86), .CO(mult_x_23_n87) );
CMPR42X1TS mult_x_23_U50 ( .A(mult_x_23_n95), .B(mult_x_23_n98), .C(
mult_x_23_n96), .D(mult_x_23_n88), .ICI(mult_x_23_n92), .S(
mult_x_23_n85), .ICO(mult_x_23_n83), .CO(mult_x_23_n84) );
CMPR42X1TS mult_x_23_U47 ( .A(mult_x_23_n170), .B(mult_x_23_n206), .C(
mult_x_23_n194), .D(mult_x_23_n158), .ICI(mult_x_23_n89), .S(
mult_x_23_n78), .ICO(mult_x_23_n76), .CO(mult_x_23_n77) );
CMPR42X1TS mult_x_23_U46 ( .A(mult_x_23_n86), .B(mult_x_23_n80), .C(
mult_x_23_n87), .D(mult_x_23_n78), .ICI(mult_x_23_n83), .S(
mult_x_23_n75), .ICO(mult_x_23_n73), .CO(mult_x_23_n74) );
CMPR42X1TS mult_x_23_U44 ( .A(mult_x_23_n169), .B(mult_x_23_n157), .C(
mult_x_23_n193), .D(mult_x_23_n205), .ICI(mult_x_23_n72), .S(
mult_x_23_n70), .ICO(mult_x_23_n68), .CO(mult_x_23_n69) );
CMPR42X1TS mult_x_23_U43 ( .A(mult_x_23_n76), .B(mult_x_23_n79), .C(
mult_x_23_n77), .D(mult_x_23_n70), .ICI(mult_x_23_n73), .S(
mult_x_23_n67), .ICO(mult_x_23_n65), .CO(mult_x_23_n66) );
CMPR42X1TS mult_x_23_U41 ( .A(mult_x_23_n64), .B(mult_x_23_n168), .C(
mult_x_23_n180), .D(mult_x_23_n156), .ICI(mult_x_23_n192), .S(
mult_x_23_n62), .ICO(mult_x_23_n60), .CO(mult_x_23_n61) );
CMPR42X1TS mult_x_23_U40 ( .A(mult_x_23_n68), .B(mult_x_23_n71), .C(
mult_x_23_n69), .D(mult_x_23_n62), .ICI(mult_x_23_n65), .S(
mult_x_23_n59), .ICO(mult_x_23_n57), .CO(mult_x_23_n58) );
CMPR42X1TS mult_x_23_U39 ( .A(n533), .B(n521), .C(mult_x_23_n179), .D(
mult_x_23_n167), .ICI(mult_x_23_n155), .S(mult_x_23_n56), .ICO(
mult_x_23_n54), .CO(mult_x_23_n55) );
CMPR42X1TS mult_x_23_U38 ( .A(mult_x_23_n191), .B(mult_x_23_n60), .C(
mult_x_23_n61), .D(mult_x_23_n56), .ICI(mult_x_23_n57), .S(
mult_x_23_n53), .ICO(mult_x_23_n51), .CO(mult_x_23_n52) );
CMPR42X1TS mult_x_23_U35 ( .A(mult_x_23_n154), .B(mult_x_23_n54), .C(
mult_x_23_n48), .D(mult_x_23_n55), .ICI(mult_x_23_n51), .S(
mult_x_23_n46), .ICO(mult_x_23_n44), .CO(mult_x_23_n45) );
CMPR42X1TS mult_x_23_U33 ( .A(mult_x_23_n153), .B(mult_x_23_n177), .C(
mult_x_23_n43), .D(mult_x_23_n47), .ICI(mult_x_23_n44), .S(
mult_x_23_n41), .ICO(mult_x_23_n39), .CO(mult_x_23_n40) );
CMPR42X1TS mult_x_23_U31 ( .A(mult_x_23_n38), .B(mult_x_23_n164), .C(
mult_x_23_n152), .D(mult_x_23_n42), .ICI(mult_x_23_n39), .S(
mult_x_23_n36), .ICO(mult_x_23_n34), .CO(mult_x_23_n35) );
CMPR42X1TS mult_x_23_U30 ( .A(n532), .B(n1514), .C(mult_x_23_n151), .D(
mult_x_23_n163), .ICI(mult_x_23_n34), .S(mult_x_23_n33), .ICO(
mult_x_23_n31), .CO(mult_x_23_n32) );
CMPR32X2TS DP_OP_36J19_124_9196_U9 ( .A(DP_OP_36J19_124_9196_n21), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J19_124_9196_n9), .CO(
DP_OP_36J19_124_9196_n8), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J19_124_9196_U8 ( .A(DP_OP_36J19_124_9196_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J19_124_9196_n8), .CO(
DP_OP_36J19_124_9196_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J19_124_9196_U7 ( .A(DP_OP_36J19_124_9196_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J19_124_9196_n7), .CO(
DP_OP_36J19_124_9196_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J19_124_9196_U6 ( .A(DP_OP_36J19_124_9196_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J19_124_9196_n6), .CO(
DP_OP_36J19_124_9196_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J19_124_9196_U5 ( .A(DP_OP_36J19_124_9196_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J19_124_9196_n5), .CO(
DP_OP_36J19_124_9196_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J19_124_9196_U4 ( .A(DP_OP_36J19_124_9196_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J19_124_9196_n4), .CO(
DP_OP_36J19_124_9196_n3), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J19_124_9196_U3 ( .A(DP_OP_36J19_124_9196_n15), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J19_124_9196_n3), .CO(
DP_OP_36J19_124_9196_n2), .S(Exp_module_Data_S[7]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_0_ ( .D(
Sgf_operation_EVEN1_left_N0), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[0]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_1_ ( .D(
Sgf_operation_EVEN1_left_N1), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[1]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_2_ ( .D(
Sgf_operation_EVEN1_left_N2), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[2]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_3_ ( .D(
Sgf_operation_EVEN1_left_N3), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[3]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_4_ ( .D(
Sgf_operation_EVEN1_left_N4), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[4]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_5_ ( .D(
Sgf_operation_EVEN1_left_N5), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[5]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_6_ ( .D(
Sgf_operation_EVEN1_left_N6), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[6]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_7_ ( .D(
Sgf_operation_EVEN1_left_N7), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[7]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_8_ ( .D(
Sgf_operation_EVEN1_left_N8), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[8]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_9_ ( .D(
Sgf_operation_EVEN1_left_N9), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[9]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_10_ ( .D(
Sgf_operation_EVEN1_left_N10), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[10]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_11_ ( .D(
Sgf_operation_EVEN1_left_N11), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[11]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_12_ ( .D(
Sgf_operation_EVEN1_left_N12), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[12]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_13_ ( .D(
Sgf_operation_EVEN1_left_N13), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[13]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_14_ ( .D(
Sgf_operation_EVEN1_left_N14), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[14]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_15_ ( .D(
Sgf_operation_EVEN1_left_N15), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[15]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_16_ ( .D(
Sgf_operation_EVEN1_left_N16), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[16]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_17_ ( .D(
Sgf_operation_EVEN1_left_N17), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[17]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_18_ ( .D(
Sgf_operation_EVEN1_left_N18), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[18]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_19_ ( .D(
Sgf_operation_EVEN1_left_N19), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[19]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_20_ ( .D(
Sgf_operation_EVEN1_left_N20), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[20]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_21_ ( .D(
Sgf_operation_EVEN1_left_N21), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[21]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_22_ ( .D(
Sgf_operation_EVEN1_left_N22), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[22]) );
DFFQX1TS Sgf_operation_EVEN1_left_Data_S_o_reg_23_ ( .D(
Sgf_operation_EVEN1_left_N23), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_left[23]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_0_ ( .D(
Sgf_operation_EVEN1_middle_N0), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[0]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_1_ ( .D(
Sgf_operation_EVEN1_middle_N1), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[1]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_2_ ( .D(
Sgf_operation_EVEN1_middle_N2), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[2]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_3_ ( .D(
Sgf_operation_EVEN1_middle_N3), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[3]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_4_ ( .D(
Sgf_operation_EVEN1_middle_N4), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[4]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_5_ ( .D(
Sgf_operation_EVEN1_middle_N5), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[5]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_6_ ( .D(
Sgf_operation_EVEN1_middle_N6), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[6]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_7_ ( .D(
Sgf_operation_EVEN1_middle_N7), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[7]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_8_ ( .D(
Sgf_operation_EVEN1_middle_N8), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[8]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_9_ ( .D(
Sgf_operation_EVEN1_middle_N9), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[9]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_10_ ( .D(
Sgf_operation_EVEN1_middle_N10), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[10]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_11_ ( .D(
Sgf_operation_EVEN1_middle_N11), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[11]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_12_ ( .D(
Sgf_operation_EVEN1_middle_N12), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[12]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_13_ ( .D(
Sgf_operation_EVEN1_middle_N13), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[13]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_14_ ( .D(
Sgf_operation_EVEN1_middle_N14), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[14]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_15_ ( .D(
Sgf_operation_EVEN1_middle_N15), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[15]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_16_ ( .D(
Sgf_operation_EVEN1_middle_N16), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[16]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_17_ ( .D(
Sgf_operation_EVEN1_middle_N17), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[17]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_18_ ( .D(
Sgf_operation_EVEN1_middle_N18), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[18]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_19_ ( .D(
Sgf_operation_EVEN1_middle_N19), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[19]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_20_ ( .D(
Sgf_operation_EVEN1_middle_N20), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[20]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_21_ ( .D(
Sgf_operation_EVEN1_middle_N21), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[21]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_22_ ( .D(
Sgf_operation_EVEN1_middle_N22), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[22]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_23_ ( .D(
Sgf_operation_EVEN1_middle_N23), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[23]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_24_ ( .D(
Sgf_operation_EVEN1_middle_N24), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[24]) );
DFFQX1TS Sgf_operation_EVEN1_middle_Data_S_o_reg_25_ ( .D(
Sgf_operation_EVEN1_middle_N25), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_middle[25]) );
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_0_ ( .D(
Sgf_operation_EVEN1_right_N0), .CK(1'b0), .Q(Sgf_operation_Result[0])
);
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_1_ ( .D(
Sgf_operation_EVEN1_right_N1), .CK(1'b0), .Q(Sgf_operation_Result[1])
);
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_2_ ( .D(
Sgf_operation_EVEN1_right_N2), .CK(1'b0), .Q(Sgf_operation_Result[2])
);
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_3_ ( .D(
Sgf_operation_EVEN1_right_N3), .CK(1'b0), .Q(Sgf_operation_Result[3])
);
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_4_ ( .D(
Sgf_operation_EVEN1_right_N4), .CK(1'b0), .Q(Sgf_operation_Result[4])
);
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_5_ ( .D(
Sgf_operation_EVEN1_right_N5), .CK(1'b0), .Q(Sgf_operation_Result[5])
);
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_6_ ( .D(
Sgf_operation_EVEN1_right_N6), .CK(1'b0), .Q(Sgf_operation_Result[6])
);
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_7_ ( .D(
Sgf_operation_EVEN1_right_N7), .CK(1'b0), .Q(Sgf_operation_Result[7])
);
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_8_ ( .D(
Sgf_operation_EVEN1_right_N8), .CK(1'b0), .Q(Sgf_operation_Result[8])
);
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_9_ ( .D(
Sgf_operation_EVEN1_right_N9), .CK(1'b0), .Q(Sgf_operation_Result[9])
);
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_10_ ( .D(
Sgf_operation_EVEN1_right_N10), .CK(1'b0), .Q(Sgf_operation_Result[10]) );
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_11_ ( .D(
Sgf_operation_EVEN1_right_N11), .CK(1'b0), .Q(Sgf_operation_Result[11]) );
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_12_ ( .D(
Sgf_operation_EVEN1_right_N12), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_right[12]) );
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_13_ ( .D(
Sgf_operation_EVEN1_right_N13), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_right[13]) );
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_14_ ( .D(
Sgf_operation_EVEN1_right_N14), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_right[14]) );
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_15_ ( .D(
Sgf_operation_EVEN1_right_N15), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_right[15]) );
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_16_ ( .D(
Sgf_operation_EVEN1_right_N16), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_right[16]) );
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_17_ ( .D(
Sgf_operation_EVEN1_right_N17), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_right[17]) );
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_18_ ( .D(
Sgf_operation_EVEN1_right_N18), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_right[18]) );
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_19_ ( .D(
Sgf_operation_EVEN1_right_N19), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_right[19]) );
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_20_ ( .D(
Sgf_operation_EVEN1_right_N20), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_right[20]) );
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_21_ ( .D(
Sgf_operation_EVEN1_right_N21), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_right[21]) );
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_22_ ( .D(
Sgf_operation_EVEN1_right_N22), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_right[22]) );
DFFQX1TS Sgf_operation_EVEN1_right_Data_S_o_reg_23_ ( .D(
Sgf_operation_EVEN1_right_N23), .CK(1'b0), .Q(
Sgf_operation_EVEN1_Q_right[23]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n345), .CK(clk), .RN(
n1544), .Q(Op_MX[0]), .QN(n1492) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n263),
.CK(clk), .RN(n1534), .Q(final_result_ieee[31]), .QN(n1490) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n199), .CK(clk),
.RN(n1535), .Q(Sgf_normalized_result[7]), .QN(n1489) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n202), .CK(clk),
.RN(n1535), .Q(Sgf_normalized_result[10]), .QN(n1488) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n198), .CK(clk),
.RN(n1535), .Q(Sgf_normalized_result[6]), .QN(n1486) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n196), .CK(clk),
.RN(n1534), .Q(Sgf_normalized_result[4]), .QN(n1485) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n215), .CK(clk), .RN(n1536), .Q(FSM_selector_C),
.QN(n1484) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n380), .CK(clk), .RN(n1526), .Q(
FS_Module_state_reg[3]), .QN(n1481) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n197), .CK(clk),
.RN(n1534), .Q(Sgf_normalized_result[5]), .QN(n1480) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n201), .CK(clk),
.RN(n1535), .Q(Sgf_normalized_result[9]), .QN(n1478) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n195), .CK(clk),
.RN(n1534), .Q(Sgf_normalized_result[3]), .QN(n1477) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n376), .CK(clk), .RN(n1531), .Q(FSM_selector_A),
.QN(n1487) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n310), .CK(clk), .RN(n1538), .Q(
FSM_selector_B[0]), .QN(n1476) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n357), .CK(clk), .RN(
n1545), .Q(Op_MX[12]), .QN(n1475) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n200), .CK(clk),
.RN(n1535), .Q(Sgf_normalized_result[8]), .QN(n1474) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n378), .CK(clk), .RN(n1548), .Q(
FS_Module_state_reg[1]), .QN(n1483) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n191),
.CK(clk), .RN(n1533), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n190),
.CK(clk), .RN(n1533), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n189),
.CK(clk), .RN(n1533), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n188),
.CK(clk), .RN(n1533), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n187),
.CK(clk), .RN(n1532), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n186),
.CK(clk), .RN(n1532), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n185),
.CK(clk), .RN(n1532), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n184),
.CK(clk), .RN(n1532), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n183),
.CK(clk), .RN(n1532), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n182),
.CK(clk), .RN(n1532), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n181),
.CK(clk), .RN(n1532), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n180),
.CK(clk), .RN(n1532), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n179),
.CK(clk), .RN(n1532), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n178),
.CK(clk), .RN(n1532), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n177),
.CK(clk), .RN(n1531), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n176),
.CK(clk), .RN(n1531), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n175),
.CK(clk), .RN(n1531), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n174),
.CK(clk), .RN(n1531), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n173),
.CK(clk), .RN(n1531), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n172),
.CK(clk), .RN(n1531), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n171),
.CK(clk), .RN(n1531), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n170),
.CK(clk), .RN(n1531), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n168),
.CK(clk), .RN(n1531), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n271),
.CK(clk), .RN(n1534), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n270),
.CK(clk), .RN(n1534), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n269),
.CK(clk), .RN(n1533), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n268),
.CK(clk), .RN(n1533), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n267),
.CK(clk), .RN(n1533), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n266),
.CK(clk), .RN(n1533), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n265),
.CK(clk), .RN(n1533), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n264),
.CK(clk), .RN(n1533), .Q(final_result_ieee[30]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n272), .CK(clk), .RN(n1536), .Q(
Exp_module_Overflow_flag_A) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n273), .CK(clk), .RN(n1534),
.Q(underflow_flag), .QN(n1491) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n282), .CK(clk), .RN(n1537),
.Q(exp_oper_result[8]) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n377), .CK(clk), .RN(n1526), .Q(
FS_Module_state_reg[2]), .QN(n1479) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n309), .CK(clk), .RN(n1537), .Q(
FSM_selector_B[1]), .QN(n1482) );
CMPR32X2TS intadd_47_U26 ( .A(Sgf_operation_Result[0]), .B(intadd_47_B_0_),
.C(Sgf_operation_EVEN1_Q_left[0]), .CO(intadd_47_n25), .S(
intadd_47_SUM_0_) );
CMPR32X2TS intadd_47_U25 ( .A(Sgf_operation_Result[1]), .B(intadd_47_B_1_),
.C(intadd_47_n25), .CO(intadd_47_n24), .S(intadd_47_SUM_1_) );
CMPR32X2TS intadd_47_U24 ( .A(intadd_47_A_2_), .B(intadd_47_B_2_), .C(
intadd_47_n24), .CO(intadd_47_n23), .S(intadd_47_SUM_2_) );
CMPR32X2TS intadd_47_U23 ( .A(intadd_47_A_3_), .B(intadd_47_B_3_), .C(
intadd_47_n23), .CO(intadd_47_n22), .S(intadd_47_SUM_3_) );
CMPR32X2TS intadd_47_U22 ( .A(intadd_47_A_4_), .B(intadd_47_B_4_), .C(
intadd_47_n22), .CO(intadd_47_n21), .S(intadd_47_SUM_4_) );
CMPR32X2TS intadd_47_U21 ( .A(intadd_47_A_5_), .B(intadd_47_B_5_), .C(
intadd_47_n21), .CO(intadd_47_n20), .S(intadd_47_SUM_5_) );
CMPR32X2TS intadd_47_U20 ( .A(intadd_47_A_6_), .B(intadd_47_B_6_), .C(
intadd_47_n20), .CO(intadd_47_n19), .S(intadd_47_SUM_6_) );
CMPR32X2TS intadd_47_U19 ( .A(intadd_47_A_7_), .B(intadd_47_B_7_), .C(
intadd_47_n19), .CO(intadd_47_n18), .S(intadd_47_SUM_7_) );
CMPR32X2TS intadd_47_U18 ( .A(intadd_47_A_8_), .B(intadd_47_B_8_), .C(
intadd_47_n18), .CO(intadd_47_n17), .S(intadd_47_SUM_8_) );
CMPR32X2TS intadd_47_U17 ( .A(intadd_47_A_9_), .B(intadd_47_B_9_), .C(
intadd_47_n17), .CO(intadd_47_n16), .S(intadd_47_SUM_9_) );
CMPR32X2TS intadd_47_U16 ( .A(intadd_47_A_10_), .B(intadd_47_B_10_), .C(
intadd_47_n16), .CO(intadd_47_n15), .S(intadd_47_SUM_10_) );
CMPR32X2TS intadd_47_U15 ( .A(intadd_47_A_11_), .B(intadd_47_B_11_), .C(
intadd_47_n15), .CO(intadd_47_n14), .S(intadd_47_SUM_11_) );
CMPR32X2TS intadd_47_U14 ( .A(intadd_47_A_12_), .B(intadd_47_B_12_), .C(
intadd_47_n14), .CO(intadd_47_n13), .S(intadd_47_SUM_12_) );
CMPR32X2TS intadd_47_U13 ( .A(intadd_47_A_13_), .B(intadd_47_B_13_), .C(
intadd_47_n13), .CO(intadd_47_n12), .S(intadd_47_SUM_13_) );
CMPR32X2TS intadd_47_U12 ( .A(intadd_47_A_14_), .B(intadd_47_B_14_), .C(
intadd_47_n12), .CO(intadd_47_n11), .S(intadd_47_SUM_14_) );
CMPR32X2TS intadd_47_U11 ( .A(intadd_47_A_15_), .B(intadd_47_B_15_), .C(
intadd_47_n11), .CO(intadd_47_n10), .S(intadd_47_SUM_15_) );
CMPR32X2TS intadd_47_U10 ( .A(intadd_47_A_16_), .B(intadd_47_B_16_), .C(
intadd_47_n10), .CO(intadd_47_n9), .S(intadd_47_SUM_16_) );
CMPR32X2TS intadd_47_U9 ( .A(intadd_47_A_17_), .B(intadd_47_B_17_), .C(
intadd_47_n9), .CO(intadd_47_n8), .S(intadd_47_SUM_17_) );
CMPR32X2TS intadd_47_U8 ( .A(intadd_47_A_18_), .B(intadd_47_B_18_), .C(
intadd_47_n8), .CO(intadd_47_n7), .S(intadd_47_SUM_18_) );
CMPR32X2TS intadd_47_U7 ( .A(intadd_47_A_19_), .B(intadd_47_B_19_), .C(
intadd_47_n7), .CO(intadd_47_n6), .S(intadd_47_SUM_19_) );
CMPR32X2TS intadd_47_U6 ( .A(intadd_47_A_20_), .B(intadd_47_B_20_), .C(
intadd_47_n6), .CO(intadd_47_n5), .S(intadd_47_SUM_20_) );
CMPR32X2TS intadd_47_U5 ( .A(intadd_47_A_21_), .B(intadd_47_B_21_), .C(
intadd_47_n5), .CO(intadd_47_n4), .S(intadd_47_SUM_21_) );
CMPR32X2TS intadd_47_U4 ( .A(intadd_47_A_22_), .B(intadd_47_B_22_), .C(
intadd_47_n4), .CO(intadd_47_n3), .S(intadd_47_SUM_22_) );
CMPR32X2TS intadd_47_U3 ( .A(intadd_47_A_23_), .B(intadd_47_B_23_), .C(
intadd_47_n3), .CO(intadd_47_n2), .S(intadd_47_SUM_23_) );
CMPR32X2TS intadd_47_U2 ( .A(intadd_47_A_24_), .B(intadd_47_B_24_), .C(
intadd_47_n2), .CO(intadd_47_n1), .S(intadd_47_SUM_24_) );
CMPR32X2TS intadd_48_U25 ( .A(Sgf_operation_EVEN1_Q_right[13]), .B(
intadd_48_B_0_), .C(intadd_48_CI), .CO(intadd_48_n24), .S(
intadd_48_SUM_0_) );
CMPR32X2TS intadd_48_U24 ( .A(Sgf_operation_EVEN1_Q_right[14]), .B(
intadd_48_B_1_), .C(intadd_48_n24), .CO(intadd_48_n23), .S(
intadd_48_SUM_1_) );
CMPR32X2TS intadd_48_U23 ( .A(Sgf_operation_EVEN1_Q_right[15]), .B(
intadd_48_B_2_), .C(intadd_48_n23), .CO(intadd_48_n22), .S(
intadd_48_SUM_2_) );
CMPR32X2TS intadd_48_U22 ( .A(Sgf_operation_EVEN1_Q_right[16]), .B(
intadd_48_B_3_), .C(intadd_48_n22), .CO(intadd_48_n21), .S(
intadd_48_SUM_3_) );
CMPR32X2TS intadd_48_U21 ( .A(Sgf_operation_EVEN1_Q_right[17]), .B(
intadd_48_B_4_), .C(intadd_48_n21), .CO(intadd_48_n20), .S(
intadd_48_SUM_4_) );
CMPR32X2TS intadd_48_U20 ( .A(Sgf_operation_EVEN1_Q_right[18]), .B(
intadd_48_B_5_), .C(intadd_48_n20), .CO(intadd_48_n19), .S(
intadd_48_SUM_5_) );
CMPR32X2TS intadd_48_U19 ( .A(Sgf_operation_EVEN1_Q_right[19]), .B(
intadd_48_B_6_), .C(intadd_48_n19), .CO(intadd_48_n18), .S(
intadd_48_SUM_6_) );
CMPR32X2TS intadd_48_U18 ( .A(Sgf_operation_EVEN1_Q_right[20]), .B(
intadd_48_B_7_), .C(intadd_48_n18), .CO(intadd_48_n17), .S(
intadd_48_SUM_7_) );
CMPR32X2TS intadd_48_U17 ( .A(Sgf_operation_EVEN1_Q_right[21]), .B(
intadd_48_B_8_), .C(intadd_48_n17), .CO(intadd_48_n16), .S(
intadd_48_SUM_8_) );
CMPR32X2TS intadd_48_U16 ( .A(Sgf_operation_EVEN1_Q_right[22]), .B(
intadd_48_B_9_), .C(intadd_48_n16), .CO(intadd_48_n15), .S(
intadd_48_SUM_9_) );
CMPR32X2TS intadd_48_U15 ( .A(Sgf_operation_EVEN1_Q_right[23]), .B(
intadd_48_B_10_), .C(intadd_48_n15), .CO(intadd_48_n14), .S(
intadd_48_SUM_10_) );
CMPR32X2TS intadd_48_U14 ( .A(Sgf_operation_EVEN1_Q_left[0]), .B(
intadd_48_B_11_), .C(intadd_48_n14), .CO(intadd_48_n13), .S(
intadd_48_SUM_11_) );
CMPR32X2TS intadd_48_U13 ( .A(Sgf_operation_EVEN1_Q_left[1]), .B(
intadd_48_B_12_), .C(intadd_48_n13), .CO(intadd_48_n12), .S(
intadd_48_SUM_12_) );
CMPR32X2TS intadd_48_U12 ( .A(Sgf_operation_EVEN1_Q_left[2]), .B(
intadd_48_B_13_), .C(intadd_48_n12), .CO(intadd_48_n11), .S(
intadd_48_SUM_13_) );
CMPR32X2TS intadd_48_U11 ( .A(Sgf_operation_EVEN1_Q_left[3]), .B(
intadd_48_B_14_), .C(intadd_48_n11), .CO(intadd_48_n10), .S(
intadd_48_SUM_14_) );
CMPR32X2TS intadd_48_U10 ( .A(Sgf_operation_EVEN1_Q_left[4]), .B(
intadd_48_B_15_), .C(intadd_48_n10), .CO(intadd_48_n9), .S(
intadd_48_SUM_15_) );
CMPR32X2TS intadd_48_U9 ( .A(Sgf_operation_EVEN1_Q_left[5]), .B(
intadd_48_B_16_), .C(intadd_48_n9), .CO(intadd_48_n8), .S(
intadd_48_SUM_16_) );
CMPR32X2TS intadd_48_U8 ( .A(Sgf_operation_EVEN1_Q_left[6]), .B(
intadd_48_B_17_), .C(intadd_48_n8), .CO(intadd_48_n7), .S(
intadd_48_SUM_17_) );
CMPR32X2TS intadd_48_U7 ( .A(Sgf_operation_EVEN1_Q_left[7]), .B(
intadd_48_B_18_), .C(intadd_48_n7), .CO(intadd_48_n6), .S(
intadd_48_SUM_18_) );
CMPR32X2TS intadd_48_U6 ( .A(Sgf_operation_EVEN1_Q_left[8]), .B(
intadd_48_B_19_), .C(intadd_48_n6), .CO(intadd_48_n5), .S(
intadd_48_SUM_19_) );
CMPR32X2TS intadd_48_U5 ( .A(Sgf_operation_EVEN1_Q_left[9]), .B(
intadd_48_B_20_), .C(intadd_48_n5), .CO(intadd_48_n4), .S(
intadd_48_SUM_20_) );
CMPR32X2TS intadd_48_U4 ( .A(Sgf_operation_EVEN1_Q_left[10]), .B(
intadd_48_B_21_), .C(intadd_48_n4), .CO(intadd_48_n3), .S(
intadd_48_SUM_21_) );
CMPR32X2TS intadd_48_U3 ( .A(Sgf_operation_EVEN1_Q_left[11]), .B(
intadd_48_B_22_), .C(intadd_48_n3), .CO(intadd_48_n2), .S(
intadd_48_SUM_22_) );
CMPR32X2TS intadd_48_U2 ( .A(Sgf_operation_EVEN1_Q_left[12]), .B(
intadd_48_B_23_), .C(intadd_48_n2), .CO(intadd_48_n1), .S(
intadd_48_SUM_23_) );
CMPR32X2TS intadd_51_U21 ( .A(intadd_51_A_0_), .B(intadd_51_B_0_), .C(
intadd_51_CI), .CO(intadd_51_n20), .S(intadd_51_SUM_0_) );
CMPR32X2TS intadd_51_U20 ( .A(intadd_51_A_1_), .B(intadd_51_B_1_), .C(
intadd_51_n20), .CO(intadd_51_n19), .S(intadd_51_SUM_1_) );
CMPR32X2TS intadd_51_U19 ( .A(intadd_51_A_2_), .B(intadd_51_B_2_), .C(
intadd_51_n19), .CO(intadd_51_n18), .S(intadd_51_SUM_2_) );
CMPR32X2TS intadd_51_U18 ( .A(intadd_51_A_3_), .B(intadd_51_B_3_), .C(
intadd_51_n18), .CO(intadd_51_n17), .S(intadd_51_SUM_3_) );
CMPR32X2TS intadd_51_U17 ( .A(intadd_51_A_4_), .B(intadd_51_B_4_), .C(
intadd_51_n17), .CO(intadd_51_n16), .S(intadd_51_SUM_4_) );
CMPR32X2TS intadd_51_U16 ( .A(intadd_51_A_5_), .B(intadd_51_B_5_), .C(
intadd_51_n16), .CO(intadd_51_n15), .S(intadd_51_SUM_5_) );
CMPR32X2TS intadd_51_U15 ( .A(intadd_51_A_6_), .B(intadd_51_B_6_), .C(
intadd_51_n15), .CO(intadd_51_n14), .S(intadd_51_SUM_6_) );
CMPR32X2TS intadd_51_U14 ( .A(intadd_51_A_7_), .B(intadd_51_B_7_), .C(
intadd_51_n14), .CO(intadd_51_n13), .S(intadd_51_SUM_7_) );
CMPR32X2TS intadd_51_U13 ( .A(intadd_51_A_8_), .B(intadd_51_B_8_), .C(
intadd_51_n13), .CO(intadd_51_n12), .S(intadd_51_SUM_8_) );
CMPR32X2TS intadd_51_U12 ( .A(intadd_51_A_9_), .B(intadd_51_B_9_), .C(
intadd_51_n12), .CO(intadd_51_n11), .S(intadd_51_SUM_9_) );
CMPR32X2TS intadd_51_U11 ( .A(intadd_51_A_10_), .B(intadd_51_B_10_), .C(
intadd_51_n11), .CO(intadd_51_n10), .S(intadd_51_SUM_10_) );
CMPR32X2TS intadd_51_U10 ( .A(intadd_51_A_11_), .B(intadd_51_B_11_), .C(
intadd_51_n10), .CO(intadd_51_n9), .S(intadd_51_SUM_11_) );
CMPR32X2TS intadd_51_U9 ( .A(intadd_51_A_12_), .B(intadd_51_B_12_), .C(
intadd_51_n9), .CO(intadd_51_n8), .S(intadd_51_SUM_12_) );
CMPR32X2TS intadd_51_U8 ( .A(intadd_51_A_13_), .B(intadd_51_B_13_), .C(
intadd_51_n8), .CO(intadd_51_n7), .S(intadd_51_SUM_13_) );
CMPR32X2TS intadd_51_U7 ( .A(intadd_51_A_14_), .B(intadd_51_B_14_), .C(
intadd_51_n7), .CO(intadd_51_n6), .S(intadd_51_SUM_14_) );
CMPR32X2TS intadd_51_U6 ( .A(intadd_51_A_15_), .B(intadd_51_B_15_), .C(
intadd_51_n6), .CO(intadd_51_n5), .S(intadd_51_SUM_15_) );
CMPR32X2TS intadd_51_U5 ( .A(intadd_51_A_16_), .B(intadd_51_B_16_), .C(
intadd_51_n5), .CO(intadd_51_n4), .S(intadd_51_SUM_16_) );
CMPR32X2TS intadd_51_U4 ( .A(intadd_51_A_17_), .B(intadd_51_B_17_), .C(
intadd_51_n4), .CO(intadd_51_n3), .S(intadd_51_SUM_17_) );
CMPR32X2TS intadd_51_U3 ( .A(intadd_51_A_18_), .B(intadd_51_B_18_), .C(
intadd_51_n3), .CO(intadd_51_n2), .S(intadd_51_SUM_18_) );
CMPR32X2TS intadd_51_U2 ( .A(intadd_51_A_19_), .B(intadd_51_B_19_), .C(
intadd_51_n2), .CO(intadd_51_n1), .S(intadd_51_SUM_19_) );
CMPR32X2TS intadd_49_U23 ( .A(intadd_49_A_0_), .B(intadd_49_B_0_), .C(
intadd_49_CI), .CO(intadd_49_n22), .S(intadd_49_SUM_0_) );
CMPR32X2TS intadd_49_U22 ( .A(intadd_49_A_1_), .B(intadd_49_B_1_), .C(
intadd_49_n22), .CO(intadd_49_n21), .S(intadd_49_SUM_1_) );
CMPR32X2TS intadd_49_U21 ( .A(intadd_49_A_2_), .B(intadd_49_B_2_), .C(
intadd_49_n21), .CO(intadd_49_n20), .S(intadd_49_SUM_2_) );
CMPR32X2TS intadd_49_U20 ( .A(intadd_49_A_3_), .B(intadd_49_B_3_), .C(
intadd_49_n20), .CO(intadd_49_n19), .S(intadd_49_SUM_3_) );
CMPR32X2TS intadd_49_U19 ( .A(intadd_49_A_4_), .B(intadd_49_B_4_), .C(
intadd_49_n19), .CO(intadd_49_n18), .S(intadd_49_SUM_4_) );
CMPR32X2TS intadd_49_U18 ( .A(intadd_49_A_5_), .B(intadd_49_B_5_), .C(
intadd_49_n18), .CO(intadd_49_n17), .S(intadd_49_SUM_5_) );
CMPR32X2TS intadd_49_U17 ( .A(intadd_49_A_6_), .B(intadd_49_B_6_), .C(
intadd_49_n17), .CO(intadd_49_n16), .S(intadd_49_SUM_6_) );
CMPR32X2TS intadd_50_U21 ( .A(intadd_50_A_0_), .B(intadd_50_B_0_), .C(
intadd_50_CI), .CO(intadd_50_n20), .S(intadd_50_SUM_0_) );
CMPR32X2TS intadd_50_U20 ( .A(intadd_50_A_1_), .B(intadd_50_B_1_), .C(
intadd_50_n20), .CO(intadd_50_n19), .S(intadd_50_SUM_1_) );
CMPR32X2TS intadd_50_U19 ( .A(intadd_50_A_2_), .B(intadd_50_B_2_), .C(
intadd_50_n19), .CO(intadd_50_n18), .S(intadd_50_SUM_2_) );
CMPR32X2TS intadd_50_U18 ( .A(intadd_50_A_3_), .B(intadd_50_B_3_), .C(
intadd_50_n18), .CO(intadd_50_n17), .S(intadd_50_SUM_3_) );
CMPR32X2TS intadd_50_U17 ( .A(intadd_50_A_4_), .B(intadd_50_B_4_), .C(
intadd_50_n17), .CO(intadd_50_n16), .S(intadd_50_SUM_4_) );
CMPR32X2TS intadd_50_U16 ( .A(intadd_50_A_5_), .B(intadd_50_B_5_), .C(
intadd_50_n16), .CO(intadd_50_n15), .S(intadd_50_SUM_5_) );
CMPR32X2TS intadd_50_U15 ( .A(intadd_50_A_6_), .B(intadd_50_B_6_), .C(
intadd_50_n15), .CO(intadd_50_n14), .S(intadd_50_SUM_6_) );
CMPR32X2TS intadd_50_U14 ( .A(intadd_50_A_7_), .B(intadd_50_B_7_), .C(
intadd_50_n14), .CO(intadd_50_n13), .S(intadd_50_SUM_7_) );
CMPR32X2TS intadd_50_U13 ( .A(intadd_50_A_8_), .B(intadd_50_B_8_), .C(
intadd_50_n13), .CO(intadd_50_n12), .S(intadd_50_SUM_8_) );
CMPR32X2TS intadd_50_U12 ( .A(intadd_50_A_9_), .B(intadd_50_B_9_), .C(
intadd_50_n12), .CO(intadd_50_n11), .S(intadd_50_SUM_9_) );
CMPR32X2TS intadd_50_U11 ( .A(intadd_50_A_10_), .B(intadd_50_B_10_), .C(
intadd_50_n11), .CO(intadd_50_n10), .S(intadd_50_SUM_10_) );
CMPR32X2TS intadd_50_U10 ( .A(intadd_50_A_11_), .B(intadd_50_B_11_), .C(
intadd_50_n10), .CO(intadd_50_n9), .S(intadd_50_SUM_11_) );
CMPR32X2TS intadd_50_U9 ( .A(intadd_50_A_12_), .B(intadd_50_B_12_), .C(
intadd_50_n9), .CO(intadd_50_n8), .S(intadd_50_SUM_12_) );
CMPR32X2TS intadd_50_U8 ( .A(intadd_50_A_13_), .B(intadd_50_B_13_), .C(
intadd_50_n8), .CO(intadd_50_n7), .S(intadd_50_SUM_13_) );
CMPR32X2TS intadd_50_U7 ( .A(intadd_50_A_14_), .B(intadd_50_B_14_), .C(
intadd_50_n7), .CO(intadd_50_n6), .S(intadd_50_SUM_14_) );
CMPR32X2TS intadd_50_U6 ( .A(intadd_50_A_15_), .B(intadd_50_B_15_), .C(
intadd_50_n6), .CO(intadd_50_n5), .S(intadd_50_SUM_15_) );
CMPR32X2TS intadd_50_U5 ( .A(intadd_50_A_16_), .B(intadd_50_B_16_), .C(
intadd_50_n5), .CO(intadd_50_n4), .S(intadd_50_SUM_16_) );
CMPR32X2TS intadd_50_U4 ( .A(intadd_50_A_17_), .B(intadd_50_B_17_), .C(
intadd_50_n4), .CO(intadd_50_n3), .S(intadd_50_SUM_17_) );
CMPR32X2TS intadd_50_U3 ( .A(intadd_50_A_18_), .B(intadd_50_B_18_), .C(
intadd_50_n3), .CO(intadd_50_n2), .S(intadd_50_SUM_18_) );
CMPR32X2TS intadd_50_U2 ( .A(intadd_50_A_19_), .B(intadd_50_B_19_), .C(
intadd_50_n2), .CO(intadd_50_n1), .S(intadd_50_SUM_19_) );
CMPR32X2TS intadd_49_U16 ( .A(intadd_49_A_7_), .B(intadd_49_B_7_), .C(
intadd_49_n16), .CO(intadd_49_n15), .S(intadd_49_SUM_7_) );
CMPR32X2TS intadd_49_U15 ( .A(intadd_49_A_8_), .B(intadd_49_B_8_), .C(
intadd_49_n15), .CO(intadd_49_n14), .S(intadd_49_SUM_8_) );
CMPR32X2TS intadd_49_U14 ( .A(intadd_49_A_9_), .B(intadd_49_B_9_), .C(
intadd_49_n14), .CO(intadd_49_n13), .S(intadd_49_SUM_9_) );
CMPR32X2TS intadd_49_U13 ( .A(intadd_49_A_10_), .B(intadd_49_B_10_), .C(
intadd_49_n13), .CO(intadd_49_n12), .S(intadd_49_SUM_10_) );
CMPR32X2TS intadd_49_U12 ( .A(intadd_49_A_11_), .B(intadd_49_B_11_), .C(
intadd_49_n12), .CO(intadd_49_n11), .S(intadd_49_SUM_11_) );
CMPR32X2TS intadd_49_U11 ( .A(intadd_49_A_12_), .B(intadd_49_B_12_), .C(
intadd_49_n11), .CO(intadd_49_n10), .S(intadd_49_SUM_12_) );
CMPR32X2TS intadd_49_U10 ( .A(intadd_49_A_13_), .B(intadd_49_B_13_), .C(
intadd_49_n10), .CO(intadd_49_n9), .S(intadd_49_SUM_13_) );
CMPR32X2TS intadd_49_U9 ( .A(intadd_49_A_14_), .B(intadd_49_B_14_), .C(
intadd_49_n9), .CO(intadd_49_n8), .S(intadd_49_SUM_14_) );
CMPR32X2TS intadd_49_U8 ( .A(intadd_49_A_15_), .B(intadd_49_B_15_), .C(
intadd_49_n8), .CO(intadd_49_n7), .S(intadd_49_SUM_15_) );
CMPR32X2TS intadd_49_U7 ( .A(intadd_49_A_16_), .B(intadd_49_B_16_), .C(
intadd_49_n7), .CO(intadd_49_n6), .S(intadd_49_SUM_16_) );
CMPR32X2TS intadd_49_U6 ( .A(intadd_49_A_17_), .B(intadd_49_B_17_), .C(
intadd_49_n6), .CO(intadd_49_n5), .S(intadd_49_SUM_17_) );
CMPR32X2TS intadd_49_U5 ( .A(intadd_49_A_18_), .B(intadd_49_B_18_), .C(
intadd_49_n5), .CO(intadd_49_n4), .S(intadd_49_SUM_18_) );
CMPR32X2TS intadd_49_U4 ( .A(intadd_49_A_19_), .B(intadd_49_B_19_), .C(
intadd_49_n4), .CO(intadd_49_n3), .S(intadd_49_SUM_19_) );
CMPR32X2TS intadd_49_U3 ( .A(intadd_49_A_20_), .B(intadd_49_B_20_), .C(
intadd_49_n3), .CO(intadd_49_n2), .S(intadd_49_SUM_20_) );
CMPR32X2TS intadd_49_U2 ( .A(intadd_49_A_21_), .B(intadd_49_B_21_), .C(
intadd_49_n2), .CO(intadd_49_n1), .S(intadd_49_SUM_21_) );
CMPR32X2TS intadd_53_U11 ( .A(n1515), .B(Op_MX[13]), .C(intadd_53_CI), .CO(
intadd_53_n10), .S(intadd_53_SUM_0_) );
CMPR32X2TS intadd_53_U9 ( .A(n1516), .B(Op_MX[15]), .C(intadd_53_n9), .CO(
intadd_53_n8), .S(intadd_53_SUM_2_) );
CMPR32X2TS intadd_53_U7 ( .A(n1517), .B(Op_MX[17]), .C(intadd_53_n7), .CO(
intadd_53_n6), .S(intadd_53_SUM_4_) );
CMPR32X2TS intadd_53_U5 ( .A(n1518), .B(Op_MX[19]), .C(intadd_53_n5), .CO(
intadd_53_n4), .S(intadd_53_SUM_6_) );
CMPR32X2TS DP_OP_36J19_124_9196_U2 ( .A(n578), .B(S_Oper_A_exp[8]), .C(
DP_OP_36J19_124_9196_n2), .CO(DP_OP_36J19_124_9196_n1), .S(
Exp_module_Data_S[8]) );
DFFSX2TS FS_Module_state_reg_reg_0_ ( .D(n629), .CK(clk), .SN(n1548), .Q(
n1547), .QN(FS_Module_state_reg[0]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n363), .CK(clk), .RN(
n1545), .Q(Op_MX[18]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n361), .CK(clk), .RN(
n1545), .Q(Op_MX[16]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n365), .CK(clk), .RN(
n1546), .Q(Op_MX[20]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n353), .CK(clk), .RN(
n1544), .Q(Op_MX[8]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n349), .CK(clk), .RN(
n1544), .Q(Op_MX[4]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n351), .CK(clk), .RN(
n1544), .Q(Op_MX[6]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n359), .CK(clk), .RN(
n1545), .Q(Op_MX[14]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n347), .CK(clk), .RN(
n1544), .Q(Op_MX[2]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n192), .CK(clk),
.RN(n1534), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n367), .CK(clk), .RN(
n1546), .Q(Op_MX[22]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n194), .CK(clk),
.RN(n1534), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n203), .CK(clk),
.RN(n1535), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n205), .CK(clk),
.RN(n1535), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n207), .CK(clk),
.RN(n1535), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n209), .CK(clk),
.RN(n1536), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n211), .CK(clk),
.RN(n1536), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n213), .CK(clk),
.RN(n1536), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n204), .CK(clk),
.RN(n1535), .Q(Sgf_normalized_result[12]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n206), .CK(clk),
.RN(n1535), .Q(Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n208), .CK(clk),
.RN(n1536), .Q(Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n210), .CK(clk),
.RN(n1536), .Q(Sgf_normalized_result[18]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n212), .CK(clk),
.RN(n1536), .Q(Sgf_normalized_result[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n214), .CK(clk),
.RN(n1536), .Q(Sgf_normalized_result[22]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n336), .CK(clk), .RN(
n1540), .Q(Op_MY[23]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n303), .CK(clk), .RN(n1542),
.Q(Add_result[4]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n302), .CK(clk), .RN(n1542),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n301), .CK(clk), .RN(n1542),
.Q(Add_result[6]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n300), .CK(clk), .RN(n1542),
.Q(Add_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n306), .CK(clk), .RN(n1541),
.Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n284), .CK(clk), .RN(n1541),
.Q(Add_result[23]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n341), .CK(clk), .RN(
n1541), .Q(Op_MY[28]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n274), .CK(clk), .RN(n1537),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n275), .CK(clk), .RN(n1537),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n276), .CK(clk), .RN(n1537),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n277), .CK(clk), .RN(n1537),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n278), .CK(clk), .RN(n1537),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n279), .CK(clk), .RN(n1537),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n280), .CK(clk), .RN(n1537),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n281), .CK(clk), .RN(n1537),
.Q(exp_oper_result[0]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n240), .CK(clk), .RN(
n1530), .Q(P_Sgf[24]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n242), .CK(clk), .RN(
n1530), .Q(P_Sgf[26]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(n381), .CK(clk), .RN(
n1526), .Q(P_Sgf[47]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n243), .CK(clk), .RN(
n1528), .Q(P_Sgf[27]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n244), .CK(clk), .RN(
n1528), .Q(P_Sgf[28]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n245), .CK(clk), .RN(
n1528), .Q(P_Sgf[29]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n246), .CK(clk), .RN(
n1527), .Q(P_Sgf[30]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n247), .CK(clk), .RN(
n1527), .Q(P_Sgf[31]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(n248), .CK(clk), .RN(
n1527), .Q(P_Sgf[32]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n249), .CK(clk), .RN(
n1527), .Q(P_Sgf[33]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n368), .CK(clk), .RN(
n1546), .Q(Op_MX[23]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n346), .CK(clk), .RN(
n1544), .Q(Op_MX[1]), .QN(n607) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n193), .CK(clk),
.RN(n1534), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n375), .CK(clk), .RN(
n634), .Q(Op_MX[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n369), .CK(clk), .RN(
n1546), .Q(Op_MX[24]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n373), .CK(clk), .RN(
n1546), .Q(Op_MX[28]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n370), .CK(clk), .RN(
n1546), .Q(Op_MX[25]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n374), .CK(clk), .RN(
n1546), .Q(Op_MX[29]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n371), .CK(clk), .RN(
n1546), .Q(Op_MX[26]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n372), .CK(clk), .RN(
n1546), .Q(Op_MX[27]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n285), .CK(clk), .RN(n1543),
.Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n286), .CK(clk), .RN(n1543),
.Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n287), .CK(clk), .RN(n1543),
.Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n288), .CK(clk), .RN(n1543),
.Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n289), .CK(clk), .RN(n1543),
.Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n290), .CK(clk), .RN(n1543),
.Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n291), .CK(clk), .RN(n1543),
.Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n292), .CK(clk), .RN(n1543),
.Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n293), .CK(clk), .RN(n1543),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n294), .CK(clk), .RN(n1542),
.Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n295), .CK(clk), .RN(n1542),
.Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n296), .CK(clk), .RN(n1542),
.Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n297), .CK(clk), .RN(n1542),
.Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n298), .CK(clk), .RN(n1542),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n299), .CK(clk), .RN(n1542),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n304), .CK(clk), .RN(n1541),
.Q(Add_result[3]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n305), .CK(clk), .RN(n1541),
.Q(Add_result[2]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n343), .CK(clk), .RN(
n1541), .Q(Op_MY[30]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n342), .CK(clk), .RN(
n1541), .Q(Op_MY[29]) );
ADDFX2TS intadd_53_U3 ( .A(n1519), .B(Op_MX[21]), .CI(intadd_53_n3), .CO(
intadd_53_n2), .S(intadd_53_SUM_8_) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(n262), .CK(clk), .RN(
n1526), .Q(P_Sgf[46]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(n255), .CK(clk), .RN(
n1527), .Q(P_Sgf[39]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(n261), .CK(clk), .RN(
n1526), .Q(P_Sgf[45]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(n259), .CK(clk), .RN(
n1526), .Q(P_Sgf[43]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(n257), .CK(clk), .RN(
n1526), .Q(P_Sgf[41]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(n253), .CK(clk), .RN(
n1527), .Q(P_Sgf[37]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(n252), .CK(clk), .RN(
n1527), .Q(P_Sgf[36]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n251), .CK(clk), .RN(
n1527), .Q(P_Sgf[35]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n250), .CK(clk), .RN(
n1527), .Q(P_Sgf[34]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n241), .CK(clk), .RN(
n1528), .Q(P_Sgf[25]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n352), .CK(clk), .RN(
n1544), .Q(Op_MX[7]), .QN(n1499) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n356), .CK(clk), .RN(
n1545), .Q(Op_MX[11]), .QN(n606) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n307), .CK(clk), .RN(n1541),
.Q(Add_result[0]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n330), .CK(clk), .RN(
n1540), .Q(Op_MY[17]), .QN(n616) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n335), .CK(clk), .RN(
n1540), .Q(Op_MY[22]), .QN(n622) );
ADDFX1TS intadd_53_U10 ( .A(Op_MX[2]), .B(Op_MX[14]), .CI(intadd_53_n10),
.CO(intadd_53_n9), .S(intadd_53_SUM_1_) );
ADDFX1TS intadd_53_U8 ( .A(Op_MX[4]), .B(Op_MX[16]), .CI(intadd_53_n8), .CO(
intadd_53_n7), .S(intadd_53_SUM_3_) );
ADDFX1TS intadd_53_U6 ( .A(Op_MX[6]), .B(Op_MX[18]), .CI(intadd_53_n6), .CO(
intadd_53_n5), .S(intadd_53_SUM_5_) );
ADDFX1TS intadd_53_U4 ( .A(Op_MX[8]), .B(Op_MX[20]), .CI(intadd_53_n4), .CO(
intadd_53_n3), .S(intadd_53_SUM_7_) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n326), .CK(clk), .RN(
n1539), .Q(Op_MY[13]), .QN(n394) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n358), .CK(clk), .RN(
n1545), .Q(Op_MX[13]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n360), .CK(clk), .RN(
n1545), .Q(Op_MX[15]), .QN(n1494) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n362), .CK(clk), .RN(
n1545), .Q(Op_MX[17]), .QN(n1496) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n364), .CK(clk), .RN(
n1545), .Q(Op_MX[19]), .QN(n1497) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n366), .CK(clk), .RN(
n1546), .Q(Op_MX[21]), .QN(n1493) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n355), .CK(clk), .RN(
n1545), .Q(Op_MX[10]) );
CMPR32X2TS intadd_53_U2 ( .A(Op_MX[10]), .B(Op_MX[22]), .C(intadd_53_n2),
.CO(intadd_53_n1), .S(intadd_53_SUM_9_) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n317), .CK(clk), .RN(
n1538), .Q(Op_MY[4]), .QN(n393) );
CMPR32X2TS DP_OP_36J19_124_9196_U10 ( .A(S_Oper_A_exp[0]), .B(n578), .C(
DP_OP_36J19_124_9196_n22), .CO(DP_OP_36J19_124_9196_n9), .S(
Exp_module_Data_S[0]) );
XNOR2X1TS U405 ( .A(DP_OP_36J19_124_9196_n1), .B(n1390), .Y(n1313) );
AOI221X4TS U406 ( .A0(n520), .A1(n501), .B0(n498), .B1(n585), .C0(n1072),
.Y(DP_OP_111J19_123_4462_n42) );
CMPR32X2TS U407 ( .A(n558), .B(n547), .C(n1141), .CO(mult_x_23_n42), .S(
mult_x_23_n43) );
CMPR32X2TS U408 ( .A(n874), .B(n806), .C(n805), .CO(n807), .S(n804) );
BUFX3TS U409 ( .A(n631), .Y(n578) );
AOI221X4TS U410 ( .A0(n519), .A1(n499), .B0(n498), .B1(n1364), .C0(n1069),
.Y(n874) );
CMPR32X2TS U411 ( .A(n562), .B(n1145), .C(n1144), .CO(mult_x_23_n98), .S(
mult_x_23_n99) );
OAI221X1TS U412 ( .A0(n517), .A1(n582), .B0(n563), .B1(n639), .C0(n972), .Y(
DP_OP_111J19_123_4462_n210) );
OAI221X1TS U413 ( .A0(n486), .A1(n583), .B0(n522), .B1(n652), .C0(n658), .Y(
DP_OP_111J19_123_4462_n199) );
CMPR32X2TS U414 ( .A(n552), .B(n531), .C(intadd_52_n2), .CO(intadd_52_n1),
.S(intadd_52_SUM_9_) );
CMPR32X2TS U415 ( .A(n518), .B(n1514), .C(intadd_52_n3), .CO(intadd_52_n2),
.S(intadd_52_SUM_8_) );
CMPR32X2TS U416 ( .A(n543), .B(n532), .C(intadd_52_n4), .CO(intadd_52_n3),
.S(intadd_52_SUM_7_) );
CMPR32X2TS U417 ( .A(n541), .B(n1512), .C(intadd_52_n5), .CO(intadd_52_n4),
.S(intadd_52_SUM_6_) );
CMPR32X2TS U418 ( .A(n544), .B(n558), .C(intadd_52_n6), .CO(intadd_52_n5),
.S(intadd_52_SUM_5_) );
CMPR32X2TS U419 ( .A(n523), .B(n521), .C(intadd_52_n7), .CO(intadd_52_n6),
.S(intadd_52_SUM_4_) );
CMPR32X2TS U420 ( .A(n542), .B(n533), .C(intadd_52_n8), .CO(intadd_52_n7),
.S(intadd_52_SUM_3_) );
CMPR32X2TS U421 ( .A(n539), .B(n530), .C(intadd_52_n9), .CO(intadd_52_n8),
.S(intadd_52_SUM_2_) );
CMPR32X2TS U422 ( .A(n529), .B(n525), .C(intadd_52_n10), .CO(intadd_52_n9),
.S(intadd_52_SUM_1_) );
CLKBUFX2TS U423 ( .A(n1509), .Y(n530) );
CMPR32X2TS U424 ( .A(n537), .B(n392), .C(intadd_52_CI), .CO(intadd_52_n10),
.S(intadd_52_SUM_0_) );
INVX2TS U425 ( .A(n548), .Y(n392) );
NOR2XLTS U426 ( .A(n1481), .B(FS_Module_state_reg[2]), .Y(n1032) );
NOR2X4TS U427 ( .A(n1041), .B(FS_Module_state_reg[1]), .Y(n631) );
NOR2XLTS U428 ( .A(n1547), .B(n1481), .Y(n759) );
OAI21XLTS U429 ( .A0(n401), .A1(n1449), .B0(n1054), .Y(n213) );
OAI221X1TS U430 ( .A0(n488), .A1(n583), .B0(n573), .B1(n652), .C0(n1022),
.Y(DP_OP_111J19_123_4462_n198) );
OAI221X1TS U431 ( .A0(intadd_52_SUM_4_), .A1(n582), .B0(n571), .B1(n639),
.C0(n705), .Y(n712) );
CLKBUFX3TS U432 ( .A(n652), .Y(n452) );
CLKINVX3TS U433 ( .A(n478), .Y(n390) );
NAND3BX1TS U434 ( .AN(Exp_module_Data_S[7]), .B(n1437), .C(n1315), .Y(n1316)
);
NAND2X2TS U435 ( .A(n1070), .B(intadd_53_SUM_8_), .Y(n651) );
NAND2X4TS U436 ( .A(n428), .B(intadd_53_n1), .Y(n660) );
CLKBUFX3TS U437 ( .A(n639), .Y(n443) );
OAI21X1TS U438 ( .A0(n401), .A1(n1456), .B0(n1060), .Y(n209) );
OAI21X1TS U439 ( .A0(n401), .A1(n1228), .B0(n1051), .Y(n207) );
OAI21X1TS U440 ( .A0(n1229), .A1(n1456), .B0(n1219), .Y(n1220) );
OAI21X1TS U441 ( .A0(n1229), .A1(n1228), .B0(n1227), .Y(n1230) );
OAI21X1TS U442 ( .A0(n401), .A1(n1453), .B0(n1057), .Y(n211) );
NAND2X2TS U443 ( .A(intadd_53_SUM_6_), .B(n1068), .Y(n640) );
NOR2X4TS U444 ( .A(intadd_53_SUM_6_), .B(n803), .Y(n643) );
OAI21X1TS U445 ( .A0(n1229), .A1(n1449), .B0(n1203), .Y(n1204) );
CLKAND2X2TS U446 ( .A(n1108), .B(n708), .Y(n707) );
OAI21X1TS U447 ( .A0(n1229), .A1(n1453), .B0(n1210), .Y(n1211) );
OAI221X1TS U448 ( .A0(n1500), .A1(n580), .B0(n439), .B1(n762), .C0(n815),
.Y(n817) );
OAI221X1TS U449 ( .A0(n543), .A1(n580), .B0(n1062), .B1(n762), .C0(n912),
.Y(mult_x_55_n216) );
AO22XLTS U450 ( .A0(Sgf_normalized_result[20]), .A1(n1473), .B0(
final_result_ieee[20]), .B1(n1472), .Y(n171) );
AO22XLTS U451 ( .A0(Sgf_normalized_result[21]), .A1(n1473), .B0(
final_result_ieee[21]), .B1(n1472), .Y(n170) );
AO22XLTS U452 ( .A0(Sgf_normalized_result[22]), .A1(n1473), .B0(
final_result_ieee[22]), .B1(n1470), .Y(n168) );
CLKBUFX2TS U453 ( .A(mult_x_55_n208), .Y(n557) );
AO22XLTS U454 ( .A0(Sgf_normalized_result[9]), .A1(n1468), .B0(
final_result_ieee[9]), .B1(n1470), .Y(n182) );
AO22XLTS U455 ( .A0(Sgf_normalized_result[10]), .A1(n1471), .B0(
final_result_ieee[10]), .B1(n1470), .Y(n181) );
NOR2X4TS U456 ( .A(n688), .B(n647), .Y(n648) );
AO22XLTS U457 ( .A0(Sgf_normalized_result[12]), .A1(n1471), .B0(
final_result_ieee[12]), .B1(n1470), .Y(n179) );
AO22XLTS U458 ( .A0(Sgf_normalized_result[11]), .A1(n1471), .B0(
final_result_ieee[11]), .B1(n1470), .Y(n180) );
AO22XLTS U459 ( .A0(Sgf_normalized_result[13]), .A1(n1471), .B0(
final_result_ieee[13]), .B1(n1470), .Y(n178) );
AO22XLTS U460 ( .A0(Sgf_normalized_result[14]), .A1(n1471), .B0(
final_result_ieee[14]), .B1(n1470), .Y(n177) );
AO22XLTS U461 ( .A0(Sgf_normalized_result[15]), .A1(n1471), .B0(
final_result_ieee[15]), .B1(n1470), .Y(n176) );
INVX3TS U462 ( .A(n1464), .Y(n1458) );
AO22XLTS U463 ( .A0(Sgf_normalized_result[16]), .A1(n1471), .B0(
final_result_ieee[16]), .B1(n1470), .Y(n175) );
AO22XLTS U464 ( .A0(Sgf_normalized_result[17]), .A1(n1471), .B0(
final_result_ieee[17]), .B1(n1470), .Y(n174) );
AO22XLTS U465 ( .A0(Sgf_normalized_result[18]), .A1(n1471), .B0(
final_result_ieee[18]), .B1(n1472), .Y(n173) );
AO22XLTS U466 ( .A0(Sgf_normalized_result[19]), .A1(n1471), .B0(
final_result_ieee[19]), .B1(n1472), .Y(n172) );
AO22XLTS U467 ( .A0(n1468), .A1(Sgf_normalized_result[0]), .B0(
final_result_ieee[0]), .B1(n1472), .Y(n191) );
AO22XLTS U468 ( .A0(n1468), .A1(Sgf_normalized_result[1]), .B0(
final_result_ieee[1]), .B1(n1472), .Y(n190) );
AO22XLTS U469 ( .A0(n1468), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n1472), .Y(n189) );
AO22XLTS U470 ( .A0(Sgf_normalized_result[3]), .A1(n1468), .B0(
final_result_ieee[3]), .B1(n1472), .Y(n188) );
OR2X2TS U471 ( .A(n1048), .B(FSM_selector_C), .Y(n401) );
CLKBUFX3TS U472 ( .A(n762), .Y(n432) );
XOR2XLTS U473 ( .A(n1249), .B(n1488), .Y(n1250) );
NOR2X4TS U474 ( .A(n1484), .B(n1048), .Y(n1226) );
XOR2XLTS U475 ( .A(n1255), .B(n1478), .Y(n1256) );
XOR2XLTS U476 ( .A(n1267), .B(n1489), .Y(n1268) );
NAND3X1TS U477 ( .A(n1391), .B(n1390), .C(n1389), .Y(n377) );
CLKBUFX3TS U478 ( .A(n1328), .Y(n566) );
NAND2X2TS U479 ( .A(n1516), .B(n1076), .Y(n763) );
INVX3TS U480 ( .A(n1440), .Y(n1311) );
NOR2X4TS U481 ( .A(n681), .B(n1373), .Y(n682) );
NOR2X4TS U482 ( .A(n1190), .B(n1484), .Y(n1194) );
CLKBUFX3TS U483 ( .A(n775), .Y(n467) );
CLKBUFX3TS U484 ( .A(n685), .Y(n431) );
CLKBUFX3TS U485 ( .A(n774), .Y(n437) );
NOR2X4TS U486 ( .A(n1516), .B(n1116), .Y(n761) );
CLKINVX3TS U487 ( .A(n397), .Y(n391) );
INVX3TS U488 ( .A(n1400), .Y(n1404) );
AND2X2TS U489 ( .A(n1047), .B(FS_Module_state_reg[1]), .Y(n1251) );
CLKBUFX2TS U490 ( .A(n1018), .Y(n559) );
XOR2XLTS U491 ( .A(n1283), .B(Sgf_normalized_result[4]), .Y(n1284) );
XOR2XLTS U492 ( .A(n1289), .B(n1477), .Y(n1291) );
NOR2X4TS U493 ( .A(intadd_53_SUM_0_), .B(n1374), .Y(n680) );
NOR2X4TS U494 ( .A(n1499), .B(n1023), .Y(n782) );
INVX3TS U495 ( .A(n1217), .Y(n1309) );
CLKAND2X2TS U496 ( .A(n1407), .B(n1517), .Y(n666) );
NAND2BX1TS U497 ( .AN(n1046), .B(n1045), .Y(n1047) );
INVX3TS U498 ( .A(n1217), .Y(n1290) );
CLKBUFX3TS U499 ( .A(n1418), .Y(n545) );
CLKBUFX3TS U500 ( .A(n1506), .Y(n543) );
CLKBUFX3TS U501 ( .A(n1504), .Y(n544) );
CLKBUFX3TS U502 ( .A(n1510), .Y(n533) );
XOR2XLTS U503 ( .A(n1295), .B(Sgf_normalized_result[2]), .Y(n1296) );
CLKBUFX3TS U504 ( .A(n1513), .Y(n532) );
CLKBUFX3TS U505 ( .A(n1511), .Y(n558) );
AND2X2TS U506 ( .A(n1046), .B(FSM_add_overflow_flag), .Y(n1043) );
NOR2X1TS U507 ( .A(n1184), .B(n1266), .Y(n1185) );
NAND2X2TS U508 ( .A(Op_MX[13]), .B(n1475), .Y(n779) );
AND2X2TS U509 ( .A(n760), .B(n759), .Y(n1441) );
INVX1TS U510 ( .A(n1046), .Y(n737) );
AND2X2TS U511 ( .A(n1033), .B(n1032), .Y(n1217) );
OR2X2TS U512 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
CLKBUFX3TS U513 ( .A(Op_MX[3]), .Y(n1516) );
CLKBUFX3TS U514 ( .A(Op_MX[5]), .Y(n1517) );
CLKBUFX3TS U515 ( .A(Op_MY[10]), .Y(n721) );
NOR2X1TS U516 ( .A(n1547), .B(n1483), .Y(n1030) );
CLKBUFX3TS U517 ( .A(Op_MX[7]), .Y(n1518) );
CLKMX2X2TS U518 ( .A(n1313), .B(Exp_module_Overflow_flag_A), .S0(n1464), .Y(
n272) );
MX2X1TS U519 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
MX2X1TS U520 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
AOI21X1TS U521 ( .A0(n1186), .A1(n1265), .B0(n1185), .Y(n1247) );
NOR2XLTS U522 ( .A(n1184), .B(n1480), .Y(n1186) );
NAND4XLTS U523 ( .A(n526), .B(mult_x_23_n38), .C(n1423), .D(n418), .Y(n1424)
);
NAND4XLTS U524 ( .A(n1422), .B(n1421), .C(n427), .D(n1420), .Y(n1425) );
NAND4XLTS U525 ( .A(n1419), .B(n565), .C(n495), .D(n561), .Y(n1426) );
MX2X1TS U526 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
MX2X1TS U527 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
OAI21XLTS U528 ( .A0(FSM_selector_B[1]), .A1(n609), .B0(n1180), .Y(n1179) );
MX2X1TS U529 ( .A(Op_MX[30]), .B(exp_oper_result[7]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[7]) );
CLKINVX3TS U530 ( .A(n758), .Y(n1512) );
OAI21X1TS U531 ( .A0(n1295), .A1(n1477), .B0(n1183), .Y(n1265) );
INVX2TS U532 ( .A(n1247), .Y(n1260) );
INVX2TS U533 ( .A(n1265), .Y(n1283) );
NAND3XLTS U534 ( .A(n734), .B(n733), .C(n732), .Y(n736) );
NAND4XLTS U535 ( .A(n1431), .B(n1430), .C(n1429), .D(n1428), .Y(n1432) );
NAND4XLTS U536 ( .A(n1407), .B(n1406), .C(n1405), .D(n606), .Y(n1435) );
MX2X1TS U537 ( .A(n1207), .B(Add_result[19]), .S0(n1214), .Y(n288) );
MX2X1TS U538 ( .A(n1188), .B(Add_result[23]), .S0(n1309), .Y(n284) );
NAND4BXLTS U539 ( .AN(n1314), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n1315) );
NAND4XLTS U540 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n1314) );
AOI221X1TS U541 ( .A0(n430), .A1(n1503), .B0(n507), .B1(n496), .C0(n767),
.Y(n769) );
AOI221X1TS U542 ( .A0(n424), .A1(n1507), .B0(n581), .B1(n570), .C0(n766),
.Y(n770) );
AOI221X1TS U543 ( .A0(n501), .A1(intadd_52_SUM_6_), .B0(n585), .B1(n567),
.C0(n856), .Y(n882) );
AOI221X1TS U544 ( .A0(n501), .A1(intadd_52_SUM_5_), .B0(n585), .B1(n575),
.C0(n852), .Y(n942) );
AOI221X1TS U545 ( .A0(n643), .A1(n390), .B0(n586), .B1(n574), .C0(n851), .Y(
n943) );
AOI221X1TS U546 ( .A0(n501), .A1(intadd_52_SUM_4_), .B0(n585), .B1(n571),
.C0(n859), .Y(n986) );
AOI221X1TS U547 ( .A0(n643), .A1(n480), .B0(n586), .B1(n567), .C0(n858), .Y(
n987) );
AOI221X1TS U548 ( .A0(n499), .A1(intadd_52_SUM_5_), .B0(n586), .B1(n575),
.C0(n847), .Y(n981) );
AOI221X1TS U549 ( .A0(n509), .A1(intadd_52_SUM_7_), .B0(n588), .B1(n574),
.C0(n846), .Y(n982) );
AOI221X1TS U550 ( .A0(n509), .A1(n480), .B0(n588), .B1(n567), .C0(n845), .Y(
n977) );
AOI221X1TS U551 ( .A0(n499), .A1(n490), .B0(n586), .B1(n571), .C0(n844), .Y(
n979) );
NAND2BXLTS U552 ( .AN(n850), .B(n662), .Y(n661) );
AOI221X1TS U553 ( .A0(n509), .A1(n517), .B0(n588), .B1(n563), .C0(n713), .Y(
n790) );
AOI221X1TS U554 ( .A0(n451), .A1(intadd_52_SUM_6_), .B0(n589), .B1(n567),
.C0(n714), .Y(n791) );
AOI221X1TS U555 ( .A0(n577), .A1(n420), .B0(n464), .B1(n422), .C0(n797), .Y(
n799) );
AOI221X1TS U556 ( .A0(n391), .A1(n1397), .B0(n449), .B1(n1423), .C0(n796),
.Y(n800) );
AOI221X1TS U557 ( .A0(n430), .A1(n550), .B0(n507), .B1(n637), .C0(n831), .Y(
n877) );
OAI221X1TS U558 ( .A0(n1506), .A1(n441), .B0(n1062), .B1(n458), .C0(n696),
.Y(mult_x_55_n173) );
AOI221X1TS U559 ( .A0(n426), .A1(n1507), .B0(n584), .B1(n570), .C0(n784),
.Y(n923) );
OAI221X1TS U560 ( .A0(n1507), .A1(n1018), .B0(n570), .B1(n1017), .C0(n861),
.Y(mult_x_55_n186) );
AOI221X1TS U561 ( .A0(n426), .A1(n543), .B0(n584), .B1(n1062), .C0(n919),
.Y(n951) );
OAI221X1TS U562 ( .A0(n1503), .A1(n441), .B0(n496), .B1(n458), .C0(n1028),
.Y(mult_x_55_n176) );
OAI221X1TS U563 ( .A0(n1504), .A1(n1018), .B0(n1341), .B1(n1017), .C0(n1006),
.Y(mult_x_55_n189) );
AOI221X1TS U564 ( .A0(n761), .A1(n544), .B0(n511), .B1(n1341), .C0(n812),
.Y(n887) );
AOI221X1TS U565 ( .A0(n426), .A1(n1502), .B0(n584), .B1(n1419), .C0(n810),
.Y(n889) );
AOI221X1TS U566 ( .A0(n430), .A1(n537), .B0(n507), .B1(n439), .C0(n811), .Y(
n888) );
AOI221X1TS U567 ( .A0(n1071), .A1(n445), .B0(n501), .B1(n399), .C0(n802),
.Y(n806) );
AOI221X1TS U568 ( .A0(n1071), .A1(n483), .B0(n501), .B1(n484), .C0(n873),
.Y(n893) );
INVX2TS U569 ( .A(n874), .Y(n892) );
OAI221X1TS U570 ( .A0(n484), .A1(n583), .B0(n572), .B1(n452), .C0(n902), .Y(
DP_OP_111J19_123_4462_n191) );
OAI221X1TS U571 ( .A0(intadd_52_SUM_9_), .A1(n582), .B0(n483), .B1(n443),
.C0(n1004), .Y(DP_OP_111J19_123_4462_n204) );
OAI221X1TS U572 ( .A0(n490), .A1(n583), .B0(n571), .B1(n452), .C0(n1014),
.Y(DP_OP_111J19_123_4462_n195) );
OAI221X1TS U573 ( .A0(n517), .A1(n583), .B0(n563), .B1(n452), .C0(n1010),
.Y(DP_OP_111J19_123_4462_n196) );
OAI221X1TS U574 ( .A0(intadd_52_SUM_2_), .A1(n583), .B0(n564), .B1(n452),
.C0(n655), .Y(DP_OP_111J19_123_4462_n197) );
OAI221X1TS U575 ( .A0(n390), .A1(n494), .B0(n574), .B1(n1372), .C0(n955),
.Y(DP_OP_111J19_123_4462_n235) );
AOI221X1TS U576 ( .A0(n499), .A1(intadd_52_SUM_1_), .B0(n1364), .B1(n573),
.C0(n792), .Y(n841) );
AOI221X1TS U577 ( .A0(n451), .A1(n492), .B0(n589), .B1(n575), .C0(n794), .Y(
n966) );
AOI221X1TS U578 ( .A0(n509), .A1(intadd_52_SUM_2_), .B0(n588), .B1(n564),
.C0(n793), .Y(n968) );
OAI221X1TS U579 ( .A0(n517), .A1(n494), .B0(n563), .B1(n1372), .C0(n716),
.Y(n717) );
OAI221X1TS U580 ( .A0(n1397), .A1(n471), .B0(n1423), .B1(n604), .C0(n903),
.Y(mult_x_23_n180) );
AOI221X1TS U581 ( .A0(n1147), .A1(n1513), .B0(n469), .B1(mult_x_23_n38),
.C0(n956), .Y(n963) );
OAI221X1TS U582 ( .A0(n420), .A1(n462), .B0(n422), .B1(n598), .C0(n991), .Y(
mult_x_23_n170) );
OAI221X1TS U583 ( .A0(n420), .A1(n471), .B0(n422), .B1(n603), .C0(n904), .Y(
mult_x_23_n184) );
OAI221X1TS U584 ( .A0(n420), .A1(n447), .B0(n422), .B1(n602), .C0(n646), .Y(
mult_x_23_n198) );
AOI221X1TS U585 ( .A0(n1147), .A1(n530), .B0(n469), .B1(n1422), .C0(n835),
.Y(n910) );
AOI221X1TS U586 ( .A0(n434), .A1(n420), .B0(n1142), .B1(n422), .C0(n776),
.Y(n928) );
NAND4XLTS U587 ( .A(n545), .B(n569), .C(mult_x_23_n64), .D(n421), .Y(n1427)
);
NOR3XLTS U588 ( .A(P_Sgf[22]), .B(P_Sgf[2]), .C(P_Sgf[0]), .Y(n730) );
OAI221X1TS U589 ( .A0(n539), .A1(n559), .B0(n538), .B1(n1017), .C0(n1015),
.Y(mult_x_55_n192) );
OAI221X1TS U590 ( .A0(n537), .A1(n559), .B0(n439), .B1(n1017), .C0(n954),
.Y(mult_x_55_n194) );
OAI221X1TS U591 ( .A0(n1503), .A1(n580), .B0(n496), .B1(n432), .C0(n1026),
.Y(mult_x_55_n219) );
OAI221X1TS U592 ( .A0(Op_MY[4]), .A1(n580), .B0(n1025), .B1(n432), .C0(n899),
.Y(mult_x_55_n220) );
AOI221X1TS U593 ( .A0(n424), .A1(n537), .B0(n581), .B1(n439), .C0(n1083),
.Y(n1096) );
AOI221X1TS U594 ( .A0(n761), .A1(n1500), .B0(n511), .B1(n439), .C0(n1090),
.Y(n1098) );
INVX2TS U595 ( .A(n669), .Y(n1515) );
AOI221X1TS U596 ( .A0(n587), .A1(n498), .B0(n503), .B1(n520), .C0(n1359),
.Y(n1079) );
OAI221X1TS U597 ( .A0(n514), .A1(n494), .B0(n564), .B1(n595), .C0(n1012),
.Y(DP_OP_111J19_123_4462_n240) );
AOI221X1TS U598 ( .A0(n451), .A1(n514), .B0(n589), .B1(n564), .C0(n719), .Y(
n1100) );
AOI221X1TS U599 ( .A0(n509), .A1(n1361), .B0(n588), .B1(n535), .C0(n1102),
.Y(n1112) );
AOI221X1TS U600 ( .A0(n451), .A1(n488), .B0(n589), .B1(n573), .C0(n1107),
.Y(n1114) );
OAI221X1TS U601 ( .A0(n1361), .A1(n494), .B0(n535), .B1(n1372), .C0(n684),
.Y(n820) );
OAI221X1TS U602 ( .A0(n1509), .A1(n471), .B0(n1422), .B1(n604), .C0(n995),
.Y(mult_x_23_n186) );
OAI221X1TS U603 ( .A0(n562), .A1(n471), .B0(n527), .B1(n604), .C0(n941), .Y(
mult_x_23_n189) );
NAND4XLTS U604 ( .A(n610), .B(n611), .C(n612), .D(n609), .Y(n1416) );
NOR2X1TS U605 ( .A(n1247), .B(n1187), .Y(n1242) );
MX2X1TS U606 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
OAI21XLTS U607 ( .A0(FSM_selector_B[0]), .A1(n1181), .B0(n1180), .Y(n1182)
);
MX2X1TS U608 ( .A(Op_MX[29]), .B(exp_oper_result[6]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[6]) );
MX2X1TS U609 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
OAI211X1TS U610 ( .A0(n1492), .A1(n536), .B0(n1515), .C0(n545), .Y(n1075) );
INVX2TS U611 ( .A(P_Sgf[42]), .Y(n1453) );
INVX2TS U612 ( .A(P_Sgf[44]), .Y(n1449) );
AO22XLTS U613 ( .A0(n1399), .A1(Op_MY[22]), .B0(n1398), .B1(Data_MY[22]),
.Y(n335) );
AO22XLTS U614 ( .A0(n1399), .A1(Op_MY[17]), .B0(n1401), .B1(Data_MY[17]),
.Y(n330) );
AO22XLTS U615 ( .A0(n1394), .A1(Op_MX[11]), .B0(n1393), .B1(Data_MX[11]),
.Y(n356) );
AO22XLTS U616 ( .A0(n1394), .A1(n1518), .B0(n1403), .B1(Data_MX[7]), .Y(n352) );
AO22XLTS U617 ( .A0(n1387), .A1(P_Sgf[25]), .B0(n756), .B1(intadd_48_SUM_12_), .Y(n241) );
AO22XLTS U618 ( .A0(n1457), .A1(P_Sgf[34]), .B0(n752), .B1(intadd_48_SUM_21_), .Y(n250) );
AO22XLTS U619 ( .A0(n1457), .A1(P_Sgf[35]), .B0(n752), .B1(intadd_48_SUM_22_), .Y(n251) );
AO22XLTS U620 ( .A0(n1457), .A1(P_Sgf[36]), .B0(n752), .B1(intadd_48_SUM_23_), .Y(n252) );
AO22XLTS U621 ( .A0(n1457), .A1(P_Sgf[37]), .B0(n752), .B1(n749), .Y(n253)
);
AO22XLTS U622 ( .A0(n1457), .A1(P_Sgf[41]), .B0(n752), .B1(n744), .Y(n257)
);
AO22XLTS U623 ( .A0(n1457), .A1(P_Sgf[43]), .B0(n752), .B1(n746), .Y(n259)
);
AO22XLTS U624 ( .A0(n1457), .A1(P_Sgf[45]), .B0(n752), .B1(n751), .Y(n261)
);
MX2X1TS U625 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n1404), .Y(n342) );
MX2X1TS U626 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n1404), .Y(n343) );
MX2X1TS U627 ( .A(n1296), .B(Add_result[2]), .S0(n1309), .Y(n305) );
MX2X1TS U628 ( .A(n1291), .B(Add_result[3]), .S0(n1290), .Y(n304) );
INVX2TS U629 ( .A(n1295), .Y(n1288) );
MX2X1TS U630 ( .A(n1261), .B(Add_result[8]), .S0(n1290), .Y(n299) );
MX2X1TS U631 ( .A(n1256), .B(Add_result[9]), .S0(n1290), .Y(n298) );
MX2X1TS U632 ( .A(n1250), .B(Add_result[10]), .S0(n1290), .Y(n297) );
MX2X1TS U633 ( .A(n1243), .B(Add_result[11]), .S0(n1290), .Y(n296) );
MX2X1TS U634 ( .A(n1238), .B(Add_result[12]), .S0(n1290), .Y(n295) );
MX2X1TS U635 ( .A(n1233), .B(Add_result[13]), .S0(n1290), .Y(n294) );
MX2X1TS U636 ( .A(n1225), .B(Add_result[14]), .S0(n1290), .Y(n293) );
MX2X1TS U637 ( .A(n1223), .B(Add_result[15]), .S0(n1290), .Y(n292) );
MX2X1TS U638 ( .A(n1218), .B(Add_result[16]), .S0(n1290), .Y(n291) );
MX2X1TS U639 ( .A(n1215), .B(Add_result[17]), .S0(n1214), .Y(n290) );
MX2X1TS U640 ( .A(n1209), .B(Add_result[18]), .S0(n1214), .Y(n289) );
MX2X1TS U641 ( .A(n1202), .B(Add_result[20]), .S0(n1214), .Y(n287) );
MX2X1TS U642 ( .A(n1200), .B(Add_result[21]), .S0(n1214), .Y(n286) );
MX2X1TS U643 ( .A(n1193), .B(Add_result[22]), .S0(n1214), .Y(n285) );
MX2X1TS U644 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n1311), .Y(n372) );
MX2X1TS U645 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n1311), .Y(n371) );
MX2X1TS U646 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n1311), .Y(n374) );
MX2X1TS U647 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n1311), .Y(n370) );
MX2X1TS U648 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n1311), .Y(n373) );
MX2X1TS U649 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n1311), .Y(n369) );
MX2X1TS U650 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n1311), .Y(n375) );
AO22XLTS U651 ( .A0(n1394), .A1(Op_MX[1]), .B0(n1398), .B1(Data_MX[1]), .Y(
n346) );
MX2X1TS U652 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n1311), .Y(n368) );
AO22XLTS U653 ( .A0(n1457), .A1(P_Sgf[33]), .B0(n752), .B1(intadd_48_SUM_20_), .Y(n249) );
AO22XLTS U654 ( .A0(n1387), .A1(P_Sgf[32]), .B0(n752), .B1(intadd_48_SUM_19_), .Y(n248) );
AO22XLTS U655 ( .A0(n1387), .A1(P_Sgf[31]), .B0(n756), .B1(intadd_48_SUM_18_), .Y(n247) );
AO22XLTS U656 ( .A0(n1387), .A1(P_Sgf[30]), .B0(n756), .B1(intadd_48_SUM_17_), .Y(n246) );
AO22XLTS U657 ( .A0(n1387), .A1(P_Sgf[29]), .B0(n756), .B1(intadd_48_SUM_16_), .Y(n245) );
AO22XLTS U658 ( .A0(n1387), .A1(P_Sgf[28]), .B0(n756), .B1(intadd_48_SUM_15_), .Y(n244) );
AO22XLTS U659 ( .A0(n1387), .A1(P_Sgf[27]), .B0(n756), .B1(intadd_48_SUM_14_), .Y(n243) );
AO22XLTS U660 ( .A0(n1387), .A1(P_Sgf[47]), .B0(n1465), .B1(n1386), .Y(n381)
);
MX2X1TS U661 ( .A(P_Sgf[26]), .B(intadd_48_SUM_13_), .S0(n1458), .Y(n242) );
MX2X1TS U662 ( .A(P_Sgf[24]), .B(intadd_48_SUM_11_), .S0(n1458), .Y(n240) );
MX2X1TS U663 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n1312),
.Y(n281) );
MX2X1TS U664 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n1312),
.Y(n280) );
MX2X1TS U665 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n1312),
.Y(n279) );
MX2X1TS U666 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(n1312),
.Y(n278) );
MX2X1TS U667 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(n1312),
.Y(n277) );
MX2X1TS U668 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(n1312),
.Y(n276) );
MX2X1TS U669 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(n1312),
.Y(n275) );
MX2X1TS U670 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(n1312),
.Y(n274) );
MX2X1TS U671 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n1404), .Y(n341) );
MX2X1TS U672 ( .A(n1300), .B(Add_result[1]), .S0(n1309), .Y(n306) );
MX2X1TS U673 ( .A(n1268), .B(Add_result[7]), .S0(n1309), .Y(n300) );
MX2X1TS U674 ( .A(n1273), .B(Add_result[6]), .S0(n1309), .Y(n301) );
MX2X1TS U675 ( .A(n1278), .B(Add_result[5]), .S0(n1309), .Y(n302) );
MX2X1TS U676 ( .A(n1284), .B(Add_result[4]), .S0(n1309), .Y(n303) );
MX2X1TS U677 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n1404), .Y(n336) );
AO22XLTS U678 ( .A0(n1404), .A1(Op_MX[22]), .B0(n1398), .B1(Data_MX[22]),
.Y(n367) );
AO22XLTS U679 ( .A0(n1440), .A1(Data_MX[2]), .B0(n1439), .B1(Op_MX[2]), .Y(
n347) );
AO22XLTS U680 ( .A0(n1440), .A1(Data_MX[14]), .B0(n1395), .B1(Op_MX[14]),
.Y(n359) );
AO22XLTS U681 ( .A0(n1440), .A1(Data_MX[6]), .B0(n1395), .B1(Op_MX[6]), .Y(
n351) );
AO22XLTS U682 ( .A0(n1440), .A1(Data_MX[4]), .B0(n1395), .B1(Op_MX[4]), .Y(
n349) );
AO22XLTS U683 ( .A0(n1403), .A1(Data_MX[8]), .B0(n1395), .B1(Op_MX[8]), .Y(
n353) );
AO22XLTS U684 ( .A0(n1392), .A1(Data_MX[20]), .B0(n1439), .B1(Op_MX[20]),
.Y(n365) );
AO22XLTS U685 ( .A0(n1440), .A1(Data_MX[16]), .B0(n1395), .B1(Op_MX[16]),
.Y(n361) );
AO22XLTS U686 ( .A0(n1440), .A1(Data_MX[18]), .B0(n1439), .B1(Op_MX[18]),
.Y(n363) );
MX2X1TS U687 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(n1312),
.Y(n282) );
AO22XLTS U688 ( .A0(Sgf_normalized_result[8]), .A1(n1468), .B0(
final_result_ieee[8]), .B1(n1467), .Y(n183) );
AO22XLTS U689 ( .A0(Sgf_normalized_result[7]), .A1(n1468), .B0(
final_result_ieee[7]), .B1(n1467), .Y(n184) );
AO22XLTS U690 ( .A0(Sgf_normalized_result[6]), .A1(n1468), .B0(
final_result_ieee[6]), .B1(n1467), .Y(n185) );
AO22XLTS U691 ( .A0(Sgf_normalized_result[5]), .A1(n1468), .B0(
final_result_ieee[5]), .B1(n1467), .Y(n186) );
AO22XLTS U692 ( .A0(Sgf_normalized_result[4]), .A1(n1468), .B0(
final_result_ieee[4]), .B1(n1467), .Y(n187) );
AO22XLTS U693 ( .A0(n1395), .A1(Op_MX[12]), .B0(n1392), .B1(Data_MX[12]),
.Y(n357) );
OAI211XLTS U694 ( .A0(n1035), .A1(n1476), .B0(n1438), .C0(n1214), .Y(n310)
);
OAI31X1TS U695 ( .A0(FS_Module_state_reg[1]), .A1(n737), .A2(n739), .B0(
n1484), .Y(n215) );
NOR2XLTS U696 ( .A(n1037), .B(underflow_flag), .Y(n1038) );
AO22XLTS U697 ( .A0(n1394), .A1(Op_MX[0]), .B0(n1398), .B1(Data_MX[0]), .Y(
n345) );
AO21XLTS U698 ( .A0(Sgf_normalized_result[23]), .A1(n1304), .B0(n1191), .Y(
n308) );
AO22XLTS U699 ( .A0(n753), .A1(P_Sgf[0]), .B0(n1462), .B1(
Sgf_operation_Result[0]), .Y(n216) );
AO22XLTS U700 ( .A0(n1464), .A1(P_Sgf[1]), .B0(n1458), .B1(
Sgf_operation_Result[1]), .Y(n217) );
AO22XLTS U701 ( .A0(n1463), .A1(P_Sgf[2]), .B0(n1465), .B1(
Sgf_operation_Result[2]), .Y(n218) );
AO22XLTS U702 ( .A0(n1464), .A1(P_Sgf[3]), .B0(n1465), .B1(
Sgf_operation_Result[3]), .Y(n219) );
AO22XLTS U703 ( .A0(n1464), .A1(P_Sgf[4]), .B0(n1465), .B1(
Sgf_operation_Result[4]), .Y(n220) );
AO22XLTS U704 ( .A0(n1463), .A1(P_Sgf[5]), .B0(n1465), .B1(
Sgf_operation_Result[5]), .Y(n221) );
AO22XLTS U705 ( .A0(n1463), .A1(P_Sgf[6]), .B0(n1465), .B1(
Sgf_operation_Result[6]), .Y(n222) );
AO22XLTS U706 ( .A0(n1463), .A1(P_Sgf[7]), .B0(n1465), .B1(
Sgf_operation_Result[7]), .Y(n223) );
AO22XLTS U707 ( .A0(n753), .A1(P_Sgf[8]), .B0(n1465), .B1(
Sgf_operation_Result[8]), .Y(n224) );
AO22XLTS U708 ( .A0(n753), .A1(P_Sgf[9]), .B0(n1465), .B1(
Sgf_operation_Result[9]), .Y(n225) );
AO22XLTS U709 ( .A0(n1464), .A1(P_Sgf[10]), .B0(n1465), .B1(
Sgf_operation_Result[10]), .Y(n226) );
AO22XLTS U710 ( .A0(n1463), .A1(P_Sgf[11]), .B0(n1462), .B1(
Sgf_operation_Result[11]), .Y(n227) );
AO22XLTS U711 ( .A0(n757), .A1(P_Sgf[12]), .B0(n1462), .B1(n755), .Y(n228)
);
AO22XLTS U712 ( .A0(n757), .A1(P_Sgf[13]), .B0(n1462), .B1(intadd_48_SUM_0_),
.Y(n229) );
AO22XLTS U713 ( .A0(n757), .A1(P_Sgf[14]), .B0(n1462), .B1(intadd_48_SUM_1_),
.Y(n230) );
AO22XLTS U714 ( .A0(n757), .A1(P_Sgf[15]), .B0(n1462), .B1(intadd_48_SUM_2_),
.Y(n231) );
AO22XLTS U715 ( .A0(n757), .A1(P_Sgf[16]), .B0(n1462), .B1(intadd_48_SUM_3_),
.Y(n232) );
AO22XLTS U716 ( .A0(n757), .A1(P_Sgf[17]), .B0(n1462), .B1(intadd_48_SUM_4_),
.Y(n233) );
AO22XLTS U717 ( .A0(n757), .A1(P_Sgf[18]), .B0(n1462), .B1(intadd_48_SUM_5_),
.Y(n234) );
AO22XLTS U718 ( .A0(n757), .A1(P_Sgf[19]), .B0(n1462), .B1(intadd_48_SUM_6_),
.Y(n235) );
AO22XLTS U719 ( .A0(n757), .A1(P_Sgf[20]), .B0(n756), .B1(intadd_48_SUM_7_),
.Y(n236) );
AO22XLTS U720 ( .A0(n757), .A1(P_Sgf[21]), .B0(n756), .B1(intadd_48_SUM_8_),
.Y(n237) );
AO22XLTS U721 ( .A0(n1387), .A1(P_Sgf[22]), .B0(n756), .B1(intadd_48_SUM_9_),
.Y(n238) );
AO22XLTS U722 ( .A0(n1387), .A1(P_Sgf[23]), .B0(n756), .B1(intadd_48_SUM_10_), .Y(n239) );
AO22XLTS U723 ( .A0(n1438), .A1(zero_flag), .B0(n1437), .B1(n1436), .Y(n312)
);
NAND4XLTS U724 ( .A(n1415), .B(n1414), .C(n1413), .D(n1412), .Y(n1433) );
NAND4XLTS U725 ( .A(n1411), .B(n1410), .C(n1409), .D(n1408), .Y(n1434) );
AO22XLTS U726 ( .A0(n1404), .A1(Op_MY[0]), .B0(n1393), .B1(Data_MY[0]), .Y(
n313) );
AO22XLTS U727 ( .A0(n1404), .A1(Op_MY[1]), .B0(n1403), .B1(Data_MY[1]), .Y(
n314) );
AO22XLTS U728 ( .A0(n1404), .A1(Op_MY[2]), .B0(n1403), .B1(Data_MY[2]), .Y(
n315) );
AO22XLTS U729 ( .A0(n1402), .A1(Op_MY[3]), .B0(n1403), .B1(Data_MY[3]), .Y(
n316) );
AO22XLTS U730 ( .A0(n1402), .A1(Op_MY[4]), .B0(n1403), .B1(Data_MY[4]), .Y(
n317) );
AO22XLTS U731 ( .A0(n1402), .A1(Op_MY[5]), .B0(n1403), .B1(Data_MY[5]), .Y(
n318) );
AO22XLTS U732 ( .A0(n1402), .A1(Op_MY[6]), .B0(n1403), .B1(Data_MY[6]), .Y(
n319) );
AO22XLTS U733 ( .A0(n1402), .A1(Op_MY[7]), .B0(n1403), .B1(Data_MY[7]), .Y(
n320) );
AO22XLTS U734 ( .A0(n1402), .A1(Op_MY[8]), .B0(n1403), .B1(Data_MY[8]), .Y(
n321) );
AO22XLTS U735 ( .A0(n1402), .A1(Op_MY[9]), .B0(n1401), .B1(Data_MY[9]), .Y(
n322) );
AO22XLTS U736 ( .A0(n1402), .A1(Op_MY[10]), .B0(n1401), .B1(Data_MY[10]),
.Y(n323) );
AO22XLTS U737 ( .A0(n1402), .A1(Op_MY[11]), .B0(n1401), .B1(Data_MY[11]),
.Y(n324) );
AO22XLTS U738 ( .A0(n1402), .A1(Op_MY[12]), .B0(n1401), .B1(Data_MY[12]),
.Y(n325) );
AO22XLTS U739 ( .A0(n1399), .A1(Op_MY[13]), .B0(n1401), .B1(Data_MY[13]),
.Y(n326) );
AO22XLTS U740 ( .A0(n1399), .A1(Op_MY[14]), .B0(n1401), .B1(Data_MY[14]),
.Y(n327) );
AO22XLTS U741 ( .A0(n1399), .A1(Op_MY[15]), .B0(n1401), .B1(Data_MY[15]),
.Y(n328) );
AO22XLTS U742 ( .A0(n1399), .A1(Op_MY[16]), .B0(n1401), .B1(Data_MY[16]),
.Y(n329) );
AO22XLTS U743 ( .A0(n1399), .A1(Op_MY[18]), .B0(n1398), .B1(Data_MY[18]),
.Y(n331) );
AO22XLTS U744 ( .A0(n1399), .A1(Op_MY[19]), .B0(n1393), .B1(Data_MY[19]),
.Y(n332) );
AO22XLTS U745 ( .A0(n1399), .A1(Op_MY[20]), .B0(n1398), .B1(Data_MY[20]),
.Y(n333) );
AO22XLTS U746 ( .A0(n1399), .A1(n1514), .B0(n1398), .B1(Data_MY[21]), .Y(
n334) );
MX2X1TS U747 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n1404), .Y(n337) );
MX2X1TS U748 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n1404), .Y(n338) );
MX2X1TS U749 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n1311), .Y(n339) );
MX2X1TS U750 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n1311), .Y(n340) );
MX2X1TS U751 ( .A(n1310), .B(FSM_add_overflow_flag), .S0(n1309), .Y(n283) );
AO22XLTS U752 ( .A0(n1400), .A1(Data_MX[31]), .B0(n1395), .B1(Op_MX[31]),
.Y(n344) );
AO22XLTS U753 ( .A0(n1394), .A1(n1516), .B0(n1398), .B1(Data_MX[3]), .Y(n348) );
AO22XLTS U754 ( .A0(n1394), .A1(n1517), .B0(n1398), .B1(Data_MX[5]), .Y(n350) );
AO22XLTS U755 ( .A0(n1394), .A1(n1519), .B0(n1398), .B1(Data_MX[9]), .Y(n354) );
AO22XLTS U756 ( .A0(n1394), .A1(Op_MX[10]), .B0(n1400), .B1(Data_MX[10]),
.Y(n355) );
AO22XLTS U757 ( .A0(n1394), .A1(Op_MX[13]), .B0(n1393), .B1(Data_MX[13]),
.Y(n358) );
AO22XLTS U758 ( .A0(n1395), .A1(Op_MX[15]), .B0(n1392), .B1(Data_MX[15]),
.Y(n360) );
AO22XLTS U759 ( .A0(n1395), .A1(Op_MX[17]), .B0(n1393), .B1(Data_MX[17]),
.Y(n362) );
AO22XLTS U760 ( .A0(n1395), .A1(Op_MX[19]), .B0(n1392), .B1(Data_MX[19]),
.Y(n364) );
AO22XLTS U761 ( .A0(n1394), .A1(Op_MX[21]), .B0(n1393), .B1(Data_MX[21]),
.Y(n366) );
AO22XLTS U762 ( .A0(n1440), .A1(Data_MY[31]), .B0(n1439), .B1(Op_MY[31]),
.Y(n311) );
INVX2TS U763 ( .A(n627), .Y(n1506) );
INVX2TS U764 ( .A(n402), .Y(n1504) );
INVX2TS U765 ( .A(n1092), .Y(n1418) );
INVX2TS U766 ( .A(n621), .Y(n1510) );
INVX2TS U767 ( .A(n615), .Y(n1502) );
INVX2TS U768 ( .A(n614), .Y(n1500) );
INVX2TS U769 ( .A(n618), .Y(n1508) );
INVX2TS U770 ( .A(n660), .Y(n973) );
CLKBUFX2TS U771 ( .A(n973), .Y(n1376) );
CLKBUFX2TS U772 ( .A(n773), .Y(n1142) );
OR2X1TS U773 ( .A(n931), .B(n787), .Y(n396) );
OR2X1TS U774 ( .A(Op_MX[17]), .B(n1125), .Y(n397) );
OR2X1TS U775 ( .A(n550), .B(intadd_52_n1), .Y(n398) );
AO21X2TS U776 ( .A0(intadd_52_n1), .A1(n550), .B0(n498), .Y(n399) );
NOR2X4TS U777 ( .A(n1458), .B(n1437), .Y(n1312) );
OR2X1TS U778 ( .A(n1190), .B(FSM_selector_C), .Y(n400) );
INVX2TS U779 ( .A(n608), .Y(n1503) );
INVX2TS U780 ( .A(n620), .Y(n1507) );
INVX2TS U781 ( .A(n628), .Y(n1511) );
INVX2TS U782 ( .A(n624), .Y(n1505) );
INVX2TS U783 ( .A(n623), .Y(n1513) );
INVX2TS U784 ( .A(n626), .Y(n1509) );
INVX2TS U785 ( .A(n617), .Y(n1501) );
INVX2TS U786 ( .A(n1409), .Y(n560) );
OR2X1TS U787 ( .A(intadd_53_SUM_8_), .B(n726), .Y(n404) );
OR2X1TS U788 ( .A(n1496), .B(n1125), .Y(n405) );
OR2X1TS U789 ( .A(Op_MX[15]), .B(n772), .Y(n406) );
OR2X1TS U790 ( .A(n1497), .B(n999), .Y(n407) );
OR2X1TS U791 ( .A(n1493), .B(n777), .Y(n408) );
OR3X1TS U792 ( .A(n1515), .B(Op_MX[2]), .C(n1495), .Y(n409) );
OR3X1TS U793 ( .A(Op_MX[10]), .B(n1519), .C(n659), .Y(n410) );
OR2X1TS U794 ( .A(n1519), .B(n787), .Y(n411) );
OR2X1TS U795 ( .A(n1378), .B(n1377), .Y(n412) );
OR2X1TS U796 ( .A(intadd_53_SUM_4_), .B(n727), .Y(n413) );
OR2X1TS U797 ( .A(intadd_53_SUM_2_), .B(n688), .Y(n414) );
OR2X1TS U798 ( .A(n1518), .B(n1023), .Y(n415) );
OR2X1TS U799 ( .A(n1517), .B(n1093), .Y(n416) );
INVX2TS U800 ( .A(Op_MX[11]), .Y(n659) );
INVX2TS U801 ( .A(n622), .Y(n417) );
INVX2TS U802 ( .A(n417), .Y(n418) );
INVX2TS U803 ( .A(n417), .Y(n419) );
INVX2TS U804 ( .A(n616), .Y(n420) );
INVX2TS U805 ( .A(n420), .Y(n421) );
INVX2TS U806 ( .A(n420), .Y(n422) );
INVX2TS U807 ( .A(n416), .Y(n423) );
INVX2TS U808 ( .A(n416), .Y(n424) );
INVX2TS U809 ( .A(n415), .Y(n425) );
INVX2TS U810 ( .A(n415), .Y(n426) );
INVX2TS U811 ( .A(n392), .Y(n427) );
INVX2TS U812 ( .A(n659), .Y(n428) );
INVX2TS U813 ( .A(n411), .Y(n429) );
INVX2TS U814 ( .A(n411), .Y(n430) );
INVX2TS U815 ( .A(n406), .Y(n433) );
INVX2TS U816 ( .A(n406), .Y(n434) );
INVX2TS U817 ( .A(n1142), .Y(n435) );
INVX2TS U818 ( .A(n435), .Y(n436) );
INVX2TS U819 ( .A(n1417), .Y(n438) );
INVX2TS U820 ( .A(n537), .Y(n439) );
INVX2TS U821 ( .A(n936), .Y(n440) );
INVX2TS U822 ( .A(n936), .Y(n441) );
INVX2TS U823 ( .A(n721), .Y(n442) );
INVX2TS U824 ( .A(n399), .Y(n444) );
INVX2TS U825 ( .A(n399), .Y(n445) );
INVX2TS U826 ( .A(n645), .Y(n446) );
INVX2TS U827 ( .A(n446), .Y(n447) );
INVX2TS U828 ( .A(n405), .Y(n448) );
INVX2TS U829 ( .A(n405), .Y(n449) );
INVX2TS U830 ( .A(n414), .Y(n450) );
INVX2TS U831 ( .A(n414), .Y(n451) );
INVX2TS U832 ( .A(n661), .Y(n453) );
INVX2TS U833 ( .A(n453), .Y(n454) );
INVX2TS U834 ( .A(n453), .Y(n455) );
INVX2TS U835 ( .A(n675), .Y(n456) );
INVX2TS U836 ( .A(n456), .Y(n457) );
INVX2TS U837 ( .A(n456), .Y(n458) );
INVX2TS U838 ( .A(n410), .Y(n459) );
INVX2TS U839 ( .A(n410), .Y(n460) );
INVX2TS U840 ( .A(n700), .Y(n461) );
INVX2TS U841 ( .A(n461), .Y(n462) );
INVX2TS U842 ( .A(n408), .Y(n463) );
INVX2TS U843 ( .A(n408), .Y(n464) );
INVX2TS U844 ( .A(n707), .Y(n465) );
INVX2TS U845 ( .A(n707), .Y(n466) );
INVX2TS U846 ( .A(n407), .Y(n468) );
INVX2TS U847 ( .A(n407), .Y(n469) );
INVX2TS U848 ( .A(n834), .Y(n470) );
INVX2TS U849 ( .A(n470), .Y(n471) );
INVX2TS U850 ( .A(n1194), .Y(n472) );
INVX2TS U851 ( .A(n472), .Y(n473) );
INVX2TS U852 ( .A(n472), .Y(n474) );
INVX2TS U853 ( .A(n1226), .Y(n475) );
INVX2TS U854 ( .A(n475), .Y(n476) );
INVX2TS U855 ( .A(n475), .Y(n477) );
INVX2TS U856 ( .A(intadd_52_SUM_7_), .Y(n478) );
INVX2TS U857 ( .A(intadd_52_SUM_6_), .Y(n479) );
INVX2TS U858 ( .A(n479), .Y(n480) );
INVX2TS U859 ( .A(intadd_52_SUM_8_), .Y(n481) );
INVX2TS U860 ( .A(n481), .Y(n482) );
INVX2TS U861 ( .A(intadd_52_SUM_9_), .Y(n483) );
INVX2TS U862 ( .A(n483), .Y(n484) );
INVX2TS U863 ( .A(intadd_52_SUM_0_), .Y(n485) );
INVX2TS U864 ( .A(n485), .Y(n486) );
INVX2TS U865 ( .A(intadd_52_SUM_1_), .Y(n487) );
INVX2TS U866 ( .A(n487), .Y(n488) );
INVX2TS U867 ( .A(intadd_52_SUM_4_), .Y(n489) );
INVX2TS U868 ( .A(n489), .Y(n490) );
INVX2TS U869 ( .A(intadd_52_SUM_5_), .Y(n491) );
INVX2TS U870 ( .A(n491), .Y(n492) );
INVX2TS U871 ( .A(n1358), .Y(n493) );
INVX2TS U872 ( .A(n1358), .Y(n494) );
INVX2TS U873 ( .A(n1503), .Y(n495) );
CLKINVX3TS U874 ( .A(n523), .Y(n496) );
INVX2TS U875 ( .A(n398), .Y(n497) );
INVX2TS U876 ( .A(n398), .Y(n498) );
CLKBUFX2TS U877 ( .A(n643), .Y(n499) );
INVX2TS U878 ( .A(n404), .Y(n500) );
INVX2TS U879 ( .A(n404), .Y(n501) );
INVX2TS U880 ( .A(n412), .Y(n502) );
INVX2TS U881 ( .A(n412), .Y(n503) );
INVX2TS U882 ( .A(n666), .Y(n504) );
INVX2TS U883 ( .A(n666), .Y(n505) );
INVX2TS U884 ( .A(n396), .Y(n506) );
INVX2TS U885 ( .A(n396), .Y(n507) );
INVX2TS U886 ( .A(n413), .Y(n508) );
INVX2TS U887 ( .A(n413), .Y(n509) );
INVX2TS U888 ( .A(n409), .Y(n510) );
INVX2TS U889 ( .A(n409), .Y(n511) );
INVX2TS U890 ( .A(n1376), .Y(n512) );
INVX2TS U891 ( .A(intadd_52_SUM_2_), .Y(n513) );
INVX2TS U892 ( .A(n513), .Y(n514) );
INVX2TS U893 ( .A(intadd_52_SUM_3_), .Y(n515) );
INVX2TS U894 ( .A(n515), .Y(n516) );
INVX2TS U895 ( .A(n515), .Y(n517) );
INVX2TS U896 ( .A(n569), .Y(n518) );
INVX2TS U897 ( .A(n498), .Y(n519) );
INVX2TS U898 ( .A(n497), .Y(n520) );
INVX2TS U899 ( .A(n421), .Y(n521) );
INVX2TS U900 ( .A(intadd_52_SUM_0_), .Y(n522) );
INVX2TS U901 ( .A(n495), .Y(n523) );
INVX2TS U902 ( .A(n1508), .Y(n524) );
INVX2TS U903 ( .A(n524), .Y(n525) );
INVX2TS U904 ( .A(n1396), .Y(n1514) );
INVX2TS U905 ( .A(n1324), .Y(n526) );
INVX2TS U906 ( .A(n562), .Y(n527) );
INVX2TS U907 ( .A(n1501), .Y(n528) );
INVX2TS U908 ( .A(n528), .Y(n529) );
INVX2TS U909 ( .A(n419), .Y(n531) );
INVX2TS U910 ( .A(n1361), .Y(n534) );
INVX2TS U911 ( .A(n657), .Y(n535) );
INVX2TS U912 ( .A(n1500), .Y(n536) );
INVX2TS U913 ( .A(n536), .Y(n537) );
INVX2TS U914 ( .A(n1502), .Y(n538) );
INVX2TS U915 ( .A(n538), .Y(n539) );
INVX2TS U916 ( .A(n1505), .Y(n540) );
INVX2TS U917 ( .A(n540), .Y(n541) );
INVX2TS U918 ( .A(n393), .Y(n542) );
INVX2TS U919 ( .A(n1512), .Y(n546) );
INVX2TS U920 ( .A(n546), .Y(n547) );
INVX2TS U921 ( .A(Op_MY[13]), .Y(n548) );
INVX2TS U922 ( .A(n549), .Y(n550) );
AOI221X1TS U923 ( .A0(n592), .A1(n550), .B0(n459), .B1(n438), .C0(n1347),
.Y(n1350) );
AOI221X1TS U924 ( .A0(n824), .A1(n1417), .B0(n871), .B1(n438), .C0(n584),
.Y(n868) );
AOI221X1TS U925 ( .A0(n438), .A1(n510), .B0(n1417), .B1(n761), .C0(n1334),
.Y(n934) );
OAI221X1TS U926 ( .A0(n1417), .A1(n580), .B0(n438), .B1(n432), .C0(n900),
.Y(mult_x_55_n213) );
INVX2TS U927 ( .A(n637), .Y(n1417) );
INVX2TS U928 ( .A(n721), .Y(n551) );
INVX2TS U929 ( .A(n551), .Y(n552) );
INVX2TS U930 ( .A(n401), .Y(n553) );
INVX2TS U931 ( .A(n401), .Y(n554) );
INVX2TS U932 ( .A(n400), .Y(n555) );
INVX2TS U933 ( .A(n400), .Y(n556) );
OAI21XLTS U934 ( .A0(FSM_selector_B[1]), .A1(n612), .B0(n1180), .Y(n1178) );
OAI21XLTS U935 ( .A0(FSM_selector_B[1]), .A1(n611), .B0(n1180), .Y(n1177) );
NOR2X1TS U936 ( .A(n417), .B(n1323), .Y(mult_x_23_n151) );
OAI211XLTS U937 ( .A0(n613), .A1(n1390), .B0(n1279), .C0(n1061), .Y(n380) );
OAI221X1TS U938 ( .A0(n539), .A1(n440), .B0(n538), .B1(n457), .C0(n678), .Y(
mult_x_55_n178) );
OAI221X1TS U939 ( .A0(n530), .A1(n462), .B0(n1422), .B1(n598), .C0(n703),
.Y(mult_x_23_n172) );
OAI221X1TS U940 ( .A0(n532), .A1(n462), .B0(mult_x_23_n38), .B1(n597), .C0(
n702), .Y(mult_x_23_n167) );
OAI221X1TS U941 ( .A0(Op_MY[13]), .A1(n447), .B0(n427), .B1(n601), .C0(n699),
.Y(mult_x_23_n202) );
OAI221X1TS U942 ( .A0(n542), .A1(n1343), .B0(n1025), .B1(n431), .C0(n686),
.Y(mult_x_55_n164) );
OAI221X1TS U943 ( .A0(n544), .A1(n590), .B0(n1341), .B1(n431), .C0(n695),
.Y(mult_x_55_n162) );
OAI221X1TS U944 ( .A0(n525), .A1(n462), .B0(n524), .B1(n597), .C0(n704), .Y(
mult_x_23_n173) );
OAI221X1TS U945 ( .A0(n529), .A1(n440), .B0(n565), .B1(n457), .C0(n676), .Y(
mult_x_55_n179) );
OAI221X1TS U946 ( .A0(n486), .A1(n582), .B0(n485), .B1(n443), .C0(n665), .Y(
DP_OP_111J19_123_4462_n213) );
OAI221X1TS U947 ( .A0(n497), .A1(n455), .B0(n519), .B1(n594), .C0(n664), .Y(
DP_OP_111J19_123_4462_n175) );
OAI221X1TS U948 ( .A0(n482), .A1(n493), .B0(n576), .B1(n595), .C0(n649), .Y(
DP_OP_111J19_123_4462_n234) );
OAI221X1TS U949 ( .A0(n523), .A1(n504), .B0(n495), .B1(n599), .C0(n674), .Y(
mult_x_55_n204) );
OAI221X1TS U950 ( .A0(n480), .A1(n493), .B0(n567), .B1(n595), .C0(n656), .Y(
DP_OP_111J19_123_4462_n236) );
OAI221X1TS U951 ( .A0(n721), .A1(n1018), .B0(n442), .B1(n591), .C0(n864),
.Y(mult_x_55_n185) );
OAI221X1TS U952 ( .A0(n552), .A1(n504), .B0(n442), .B1(n599), .C0(n872), .Y(
mult_x_55_n199) );
OAI221X1TS U953 ( .A0(n523), .A1(n1018), .B0(n495), .B1(n591), .C0(n907),
.Y(mult_x_55_n190) );
NOR2X2TS U954 ( .A(n745), .B(n1450), .Y(n1447) );
OAI21X2TS U955 ( .A0(intadd_53_SUM_0_), .A1(intadd_53_SUM_1_), .B0(n855),
.Y(n688) );
OAI221X1TS U956 ( .A0(n531), .A1(n462), .B0(n419), .B1(n598), .C0(n1140),
.Y(n1141) );
OAI221X1TS U957 ( .A0(n531), .A1(n435), .B0(n419), .B1(n1146), .C0(n437),
.Y(mult_x_23_n207) );
OAI221X1TS U958 ( .A0(n531), .A1(n447), .B0(n419), .B1(n601), .C0(n397), .Y(
mult_x_23_n193) );
CLKINVX3TS U959 ( .A(n542), .Y(n1025) );
AOI21X2TS U960 ( .A0(intadd_53_SUM_7_), .A1(intadd_53_SUM_6_), .B0(n650),
.Y(n1070) );
CLKINVX3TS U961 ( .A(n543), .Y(n1062) );
AOI21X2TS U962 ( .A0(intadd_53_SUM_5_), .A1(intadd_53_SUM_4_), .B0(n638),
.Y(n1068) );
CLKINVX3TS U963 ( .A(n544), .Y(n1341) );
CLKINVX3TS U964 ( .A(n530), .Y(n1422) );
OAI221X1TS U965 ( .A0(Op_MY[17]), .A1(n467), .B0(n422), .B1(n437), .C0(n990),
.Y(mult_x_23_n213) );
OAI221X1TS U966 ( .A0(n1092), .A1(n1018), .B0(n545), .B1(n1017), .C0(n958),
.Y(mult_x_55_n195) );
CLKINVX3TS U967 ( .A(n619), .Y(n1092) );
CLKINVX3TS U968 ( .A(n1514), .Y(n1423) );
AOI21X2TS U969 ( .A0(n1492), .A1(n1475), .B0(intadd_53_CI), .Y(n681) );
OAI21X2TS U970 ( .A0(Op_MX[10]), .A1(n1519), .B0(n1354), .Y(n725) );
CLKINVX3TS U971 ( .A(n532), .Y(mult_x_23_n38) );
OAI21XLTS U972 ( .A0(n1459), .A1(Sgf_operation_EVEN1_Q_left[15]), .B0(n1458),
.Y(n1460) );
OAI211XLTS U973 ( .A0(n1444), .A1(Sgf_operation_EVEN1_Q_left[22]), .B0(n1458), .C0(n1443), .Y(n1445) );
CLKINVX3TS U974 ( .A(n533), .Y(mult_x_23_n64) );
OAI21X2TS U975 ( .A0(n428), .A1(intadd_53_n1), .B0(n660), .Y(n1377) );
INVX2TS U976 ( .A(n541), .Y(n561) );
INVX2TS U977 ( .A(n526), .Y(n562) );
NOR3X2TS U978 ( .A(n1518), .B(Op_MX[8]), .C(n931), .Y(n936) );
INVX2TS U979 ( .A(intadd_52_SUM_3_), .Y(n563) );
INVX2TS U980 ( .A(intadd_52_SUM_2_), .Y(n564) );
INVX2TS U981 ( .A(n529), .Y(n565) );
NOR3X2TS U982 ( .A(intadd_53_SUM_1_), .B(n647), .C(intadd_53_SUM_0_), .Y(
n1358) );
INVX2TS U983 ( .A(intadd_52_SUM_6_), .Y(n567) );
INVX2TS U984 ( .A(n445), .Y(n568) );
INVX2TS U985 ( .A(n1507), .Y(n569) );
CLKINVX3TS U986 ( .A(n518), .Y(n570) );
INVX2TS U987 ( .A(intadd_52_SUM_4_), .Y(n571) );
INVX2TS U988 ( .A(intadd_52_SUM_9_), .Y(n572) );
INVX2TS U989 ( .A(intadd_52_SUM_1_), .Y(n573) );
INVX2TS U990 ( .A(intadd_52_SUM_7_), .Y(n574) );
INVX2TS U991 ( .A(intadd_52_SUM_5_), .Y(n575) );
INVX2TS U992 ( .A(intadd_52_SUM_8_), .Y(n576) );
NOR2X2TS U993 ( .A(Sgf_normalized_result[0]), .B(Sgf_normalized_result[1]),
.Y(n1295) );
NOR2X1TS U994 ( .A(Op_MX[13]), .B(n1475), .Y(n778) );
NOR2X1TS U995 ( .A(n1515), .B(n1492), .Y(n670) );
NOR2X1TS U996 ( .A(Op_MX[19]), .B(n999), .Y(n833) );
INVX2TS U997 ( .A(n1140), .Y(n577) );
AOI221X1TS U998 ( .A0(n577), .A1(n531), .B0(n464), .B1(n419), .C0(n822), .Y(
n896) );
AOI221X1TS U999 ( .A0(n577), .A1(Op_MY[13]), .B0(n464), .B1(n548), .C0(n836),
.Y(n909) );
CLKBUFX2TS U1000 ( .A(n701), .Y(n1325) );
CLKBUFX2TS U1001 ( .A(n679), .Y(n579) );
OAI21XLTS U1002 ( .A0(n492), .A1(n579), .B0(n809), .Y(
DP_OP_111J19_123_4462_n252) );
CLKBUFX2TS U1003 ( .A(n679), .Y(n1104) );
CLKBUFX2TS U1004 ( .A(n680), .Y(n1106) );
INVX2TS U1005 ( .A(n1334), .Y(n580) );
OAI221X1TS U1006 ( .A0(n518), .A1(n580), .B0(n570), .B1(n432), .C0(n1024),
.Y(mult_x_55_n215) );
AOI221X1TS U1007 ( .A0(n761), .A1(n529), .B0(n511), .B1(n528), .C0(n1085),
.Y(n1095) );
AOI221X1TS U1008 ( .A0(n761), .A1(n523), .B0(n511), .B1(n496), .C0(n786),
.Y(n948) );
AOI221X1TS U1009 ( .A0(n761), .A1(n518), .B0(n511), .B1(n570), .C0(n764),
.Y(n916) );
CLKBUFX2TS U1010 ( .A(n761), .Y(n1091) );
INVX2TS U1011 ( .A(n1345), .Y(n581) );
CLKBUFX2TS U1012 ( .A(n667), .Y(n1084) );
INVX2TS U1013 ( .A(n1069), .Y(n582) );
OAI221X1TS U1014 ( .A0(intadd_52_SUM_1_), .A1(n582), .B0(n573), .B1(n639),
.C0(n1005), .Y(DP_OP_111J19_123_4462_n212) );
INVX2TS U1015 ( .A(n1072), .Y(n583) );
OAI221X1TS U1016 ( .A0(intadd_52_SUM_8_), .A1(n583), .B0(n576), .B1(n652),
.C0(n1011), .Y(DP_OP_111J19_123_4462_n67) );
CLKBUFX2TS U1017 ( .A(n782), .Y(n584) );
OAI221X1TS U1018 ( .A0(n531), .A1(n467), .B0(n419), .B1(n437), .C0(n1143),
.Y(n1144) );
NOR2X1TS U1019 ( .A(n534), .B(n850), .Y(DP_OP_111J19_123_4462_n187) );
OAI21X2TS U1020 ( .A0(intadd_53_SUM_8_), .A1(intadd_53_SUM_9_), .B0(n1378),
.Y(n850) );
NAND3X2TS U1021 ( .A(n1031), .B(n1547), .C(n1483), .Y(n634) );
NOR2X2TS U1022 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[2]), .Y(
n1031) );
NOR2X2TS U1023 ( .A(n743), .B(n1454), .Y(n1451) );
NOR4X1TS U1024 ( .A(Op_MX[24]), .B(Op_MX[26]), .C(Op_MX[25]), .D(Op_MX[23]),
.Y(n1415) );
NOR2X2TS U1025 ( .A(n750), .B(n1446), .Y(n1444) );
NOR2BX2TS U1026 ( .AN(Sgf_operation_EVEN1_Q_left[14]), .B(n1039), .Y(n1459)
);
AOI222X4TS U1027 ( .A0(Sgf_operation_EVEN1_Q_left[13]), .A1(n747), .B0(
Sgf_operation_EVEN1_Q_left[13]), .B1(intadd_48_n1), .C0(n747), .C1(
intadd_48_n1), .Y(n1039) );
CLKBUFX2TS U1028 ( .A(n1071), .Y(n585) );
CLKBUFX2TS U1029 ( .A(n1364), .Y(n586) );
CLKBUFX2TS U1030 ( .A(n1360), .Y(n587) );
CLKBUFX2TS U1031 ( .A(n1367), .Y(n588) );
INVX2TS U1032 ( .A(n1008), .Y(n589) );
INVX2TS U1033 ( .A(n1347), .Y(n590) );
NOR2X2TS U1034 ( .A(n659), .B(n725), .Y(n1347) );
NOR2XLTS U1035 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n1181) );
INVX2TS U1036 ( .A(n824), .Y(n591) );
OAI221X1TS U1037 ( .A0(n542), .A1(n559), .B0(n1025), .B1(n1017), .C0(n1016),
.Y(mult_x_55_n191) );
NOR2X2TS U1038 ( .A(n783), .B(n1518), .Y(n824) );
CLKBUFX2TS U1039 ( .A(n1348), .Y(n592) );
BUFX3TS U1040 ( .A(n1400), .Y(n1440) );
CLKBUFX2TS U1041 ( .A(n1086), .Y(n593) );
INVX2TS U1042 ( .A(n1359), .Y(n594) );
NOR2X2TS U1043 ( .A(n662), .B(n850), .Y(n1359) );
CLKBUFX2TS U1044 ( .A(n1372), .Y(n595) );
INVX2TS U1045 ( .A(n1109), .Y(n596) );
AOI21X2TS U1046 ( .A0(intadd_53_SUM_3_), .A1(intadd_53_SUM_2_), .B0(n706),
.Y(n1108) );
AND3X1TS U1047 ( .A(Op_MX[20]), .B(Op_MX[19]), .C(n1493), .Y(n1327) );
INVX2TS U1048 ( .A(n1327), .Y(n597) );
INVX2TS U1049 ( .A(n1327), .Y(n598) );
AND3X1TS U1050 ( .A(Op_MX[4]), .B(n1516), .C(n1498), .Y(n1346) );
INVX2TS U1051 ( .A(n1346), .Y(n599) );
INVX2TS U1052 ( .A(n1346), .Y(n600) );
AND3X1TS U1053 ( .A(Op_MX[16]), .B(Op_MX[15]), .C(n1496), .Y(n1119) );
INVX2TS U1054 ( .A(n1119), .Y(n601) );
INVX2TS U1055 ( .A(n1119), .Y(n602) );
AND3X1TS U1056 ( .A(Op_MX[17]), .B(Op_MX[18]), .C(n1497), .Y(n1149) );
INVX2TS U1057 ( .A(n1149), .Y(n603) );
INVX2TS U1058 ( .A(n1149), .Y(n604) );
OAI221X1TS U1059 ( .A0(n532), .A1(n834), .B0(mult_x_23_n38), .B1(n603), .C0(
n1148), .Y(n1150) );
OAI221X4TS U1060 ( .A0(n1510), .A1(n834), .B0(mult_x_23_n64), .B1(n603),
.C0(n994), .Y(mult_x_23_n185) );
OAI221X1TS U1061 ( .A0(n558), .A1(n471), .B0(n1420), .B1(n604), .C0(n992),
.Y(mult_x_23_n183) );
OAI221X4TS U1062 ( .A0(Op_MY[13]), .A1(n834), .B0(n394), .B1(n603), .C0(n945), .Y(mult_x_23_n188) );
OAI221X1TS U1063 ( .A0(n531), .A1(n471), .B0(n419), .B1(n603), .C0(n862),
.Y(mult_x_23_n179) );
NAND2X1TS U1064 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n1183) );
NOR2XLTS U1065 ( .A(n1288), .B(Sgf_normalized_result[2]), .Y(n1289) );
OAI21XLTS U1066 ( .A0(n1309), .A1(Sgf_normalized_result[0]), .B0(n1034), .Y(
n307) );
AOI21X2TS U1067 ( .A0(Op_MX[2]), .A1(n1515), .B0(n1406), .Y(n1076) );
NOR3X1TS U1068 ( .A(Op_MX[13]), .B(Op_MX[14]), .C(n1494), .Y(n773) );
AOI21X2TS U1069 ( .A0(Op_MX[14]), .A1(Op_MX[13]), .B0(n1411), .Y(n1133) );
OAI21X2TS U1070 ( .A0(n1517), .A1(Op_MX[6]), .B0(n783), .Y(n1023) );
NOR3X2TS U1071 ( .A(n1517), .B(Op_MX[6]), .C(n1499), .Y(n871) );
NOR4X1TS U1072 ( .A(Op_MX[0]), .B(n1517), .C(Op_MX[6]), .D(n1518), .Y(n1412)
);
NOR2X2TS U1073 ( .A(n1516), .B(Op_MX[4]), .Y(n1407) );
OAI21X2TS U1074 ( .A0(n1518), .A1(Op_MX[8]), .B0(n1139), .Y(n787) );
NOR2X2TS U1075 ( .A(Op_MX[19]), .B(Op_MX[20]), .Y(n1405) );
NOR2X2TS U1076 ( .A(Op_MX[15]), .B(Op_MX[16]), .Y(n1410) );
NOR2X2TS U1077 ( .A(Op_MX[17]), .B(Op_MX[18]), .Y(n1408) );
AO22XLTS U1078 ( .A0(n392), .A1(n1136), .B0(n1145), .B1(n548), .Y(n605) );
INVX2TS U1079 ( .A(Op_MX[1]), .Y(n669) );
OA22X1TS U1080 ( .A0(n633), .A1(n1388), .B0(P_Sgf[47]), .B1(n1389), .Y(n629)
);
OAI21XLTS U1081 ( .A0(FSM_selector_B[1]), .A1(n610), .B0(n1180), .Y(n1176)
);
INVX2TS U1082 ( .A(mult_x_55_n32), .Y(intadd_50_A_19_) );
INVX2TS U1083 ( .A(mult_x_55_n75), .Y(intadd_50_B_11_) );
INVX2TS U1084 ( .A(mult_x_55_n132), .Y(intadd_50_A_4_) );
INVX2TS U1085 ( .A(DP_OP_111J19_123_4462_n50), .Y(intadd_49_B_16_) );
INVX2TS U1086 ( .A(DP_OP_111J19_123_4462_n113), .Y(intadd_49_A_9_) );
OAI21XLTS U1087 ( .A0(n820), .A1(n819), .B0(intadd_49_A_1_), .Y(
intadd_49_A_0_) );
INVX2TS U1088 ( .A(mult_x_23_n66), .Y(intadd_51_A_13_) );
INVX2TS U1089 ( .A(mult_x_23_n123), .Y(intadd_51_B_5_) );
INVX2TS U1090 ( .A(Op_MY[21]), .Y(n1396) );
OAI21XLTS U1091 ( .A0(n1461), .A1(Sgf_operation_EVEN1_Q_left[16]), .B0(n1454), .Y(n1455) );
NOR2X1TS U1092 ( .A(n1479), .B(FS_Module_state_reg[0]), .Y(n630) );
NAND2X2TS U1093 ( .A(n1481), .B(n630), .Y(n1041) );
CLKBUFX2TS U1094 ( .A(n634), .Y(n636) );
CLKBUFX2TS U1095 ( .A(n636), .Y(n635) );
NAND2X1TS U1096 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n738) );
NOR3X1TS U1097 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[1]), .C(
n738), .Y(ready) );
AOI22X1TS U1098 ( .A0(n578), .A1(n613), .B0(n1547), .B1(n1479), .Y(n633) );
INVX2TS U1099 ( .A(ready), .Y(n632) );
OAI22X2TS U1100 ( .A0(beg_FSM), .A1(n634), .B0(ack_FSM), .B1(n632), .Y(n1388) );
NOR2X1TS U1101 ( .A(FS_Module_state_reg[3]), .B(n1479), .Y(n1044) );
NOR2X2TS U1102 ( .A(n1547), .B(FS_Module_state_reg[1]), .Y(n1033) );
NAND2X1TS U1103 ( .A(n1044), .B(n1033), .Y(n1389) );
INVX2TS U1104 ( .A(rst), .Y(n1548) );
BUFX3TS U1105 ( .A(n1548), .Y(n1529) );
BUFX3TS U1106 ( .A(n1548), .Y(n1530) );
BUFX3TS U1107 ( .A(n1548), .Y(n1528) );
BUFX3TS U1108 ( .A(n634), .Y(n1541) );
BUFX3TS U1109 ( .A(n1548), .Y(n1527) );
BUFX3TS U1110 ( .A(n635), .Y(n1540) );
BUFX3TS U1111 ( .A(n636), .Y(n1537) );
BUFX3TS U1112 ( .A(n635), .Y(n1539) );
BUFX3TS U1113 ( .A(n636), .Y(n1532) );
BUFX3TS U1114 ( .A(n635), .Y(n1546) );
BUFX3TS U1115 ( .A(n636), .Y(n1533) );
BUFX3TS U1116 ( .A(n634), .Y(n1545) );
BUFX3TS U1117 ( .A(n635), .Y(n1538) );
BUFX3TS U1118 ( .A(n634), .Y(n1531) );
BUFX3TS U1119 ( .A(n636), .Y(n1544) );
BUFX3TS U1120 ( .A(n634), .Y(n1543) );
BUFX3TS U1121 ( .A(n1548), .Y(n1526) );
BUFX3TS U1122 ( .A(n635), .Y(n1536) );
BUFX3TS U1123 ( .A(n636), .Y(n1542) );
BUFX3TS U1124 ( .A(n635), .Y(n1534) );
BUFX3TS U1125 ( .A(n636), .Y(n1535) );
INVX1TS U1126 ( .A(Op_MY[11]), .Y(n637) );
NOR2XLTS U1127 ( .A(intadd_53_SUM_4_), .B(intadd_53_SUM_5_), .Y(n638) );
INVX2TS U1128 ( .A(intadd_53_SUM_6_), .Y(n641) );
NAND2X1TS U1129 ( .A(n1068), .B(n641), .Y(n639) );
NOR3XLTS U1130 ( .A(intadd_53_SUM_4_), .B(intadd_53_SUM_5_), .C(n641), .Y(
n642) );
CLKBUFX3TS U1131 ( .A(n642), .Y(n1364) );
NAND2X1TS U1132 ( .A(intadd_53_SUM_4_), .B(intadd_53_SUM_5_), .Y(n803) );
AOI22X1TS U1133 ( .A0(n444), .A1(n1364), .B0(n643), .B1(n568), .Y(n644) );
OAI221XLTS U1134 ( .A0(n498), .A1(n443), .B0(n520), .B1(n582), .C0(n644),
.Y(DP_OP_111J19_123_4462_n202) );
NAND2X1TS U1135 ( .A(n1410), .B(Op_MX[17]), .Y(n645) );
AO21X1TS U1136 ( .A0(Op_MX[16]), .A1(Op_MX[15]), .B0(n1410), .Y(n1125) );
INVX2TS U1137 ( .A(n558), .Y(n1420) );
AOI22X1TS U1138 ( .A0(n1511), .A1(n391), .B0(n448), .B1(n1420), .Y(n646) );
INVX2TS U1139 ( .A(intadd_53_SUM_2_), .Y(n647) );
NAND2X1TS U1140 ( .A(intadd_53_SUM_0_), .B(intadd_53_SUM_1_), .Y(n855) );
OR2X2TS U1141 ( .A(n855), .B(intadd_53_SUM_2_), .Y(n1372) );
AOI22X1TS U1142 ( .A0(n484), .A1(n450), .B0(n648), .B1(n572), .Y(n649) );
NOR2XLTS U1143 ( .A(intadd_53_SUM_6_), .B(intadd_53_SUM_7_), .Y(n650) );
INVX2TS U1144 ( .A(intadd_53_SUM_8_), .Y(n653) );
NAND2X1TS U1145 ( .A(n1070), .B(n653), .Y(n652) );
NAND2X1TS U1146 ( .A(intadd_53_SUM_6_), .B(intadd_53_SUM_7_), .Y(n726) );
NOR3XLTS U1147 ( .A(intadd_53_SUM_6_), .B(intadd_53_SUM_7_), .C(n653), .Y(
n654) );
CLKBUFX3TS U1148 ( .A(n654), .Y(n1071) );
AOI22X1TS U1149 ( .A0(n488), .A1(n500), .B0(n1071), .B1(n487), .Y(n655) );
AOI22X1TS U1150 ( .A0(n390), .A1(n450), .B0(n648), .B1(n574), .Y(n656) );
INVX2TS U1151 ( .A(n625), .Y(n1324) );
NOR2X1TS U1152 ( .A(n1418), .B(n527), .Y(intadd_52_CI) );
AOI21X1TS U1153 ( .A0(n545), .A1(n526), .B0(intadd_52_CI), .Y(n657) );
CLKBUFX3TS U1154 ( .A(n657), .Y(n1361) );
AOI22X1TS U1155 ( .A0(n1361), .A1(n500), .B0(n1071), .B1(n534), .Y(n658) );
NAND2X1TS U1156 ( .A(intadd_53_SUM_8_), .B(intadd_53_SUM_9_), .Y(n1378) );
INVX2TS U1157 ( .A(n1377), .Y(n662) );
INVX2TS U1158 ( .A(n1359), .Y(n1363) );
NOR3XLTS U1159 ( .A(intadd_53_SUM_8_), .B(intadd_53_SUM_9_), .C(n662), .Y(
n663) );
CLKBUFX3TS U1160 ( .A(n663), .Y(n1360) );
AOI22X1TS U1161 ( .A0(n444), .A1(n1360), .B0(n503), .B1(n568), .Y(n664) );
AOI22X1TS U1162 ( .A0(n1361), .A1(n643), .B0(n1364), .B1(n534), .Y(n665) );
AO21X1TS U1163 ( .A0(Op_MX[4]), .A1(n1516), .B0(n1407), .Y(n1093) );
NOR2XLTS U1164 ( .A(n1498), .B(n1093), .Y(n667) );
AOI22X1TS U1165 ( .A0(n529), .A1(n423), .B0(n1084), .B1(n528), .Y(n668) );
OAI221XLTS U1166 ( .A0(n537), .A1(n505), .B0(n536), .B1(n600), .C0(n668),
.Y(mult_x_55_n208) );
NOR2X1TS U1167 ( .A(n1492), .B(n545), .Y(Sgf_operation_EVEN1_right_N0) );
NOR2XLTS U1168 ( .A(Sgf_operation_EVEN1_right_N0), .B(n669), .Y(n673) );
NAND2X2TS U1169 ( .A(Op_MX[0]), .B(n1515), .Y(n1086) );
CLKBUFX3TS U1170 ( .A(n670), .Y(n1089) );
NAND2X1TS U1171 ( .A(n1089), .B(n1500), .Y(n671) );
OAI21XLTS U1172 ( .A0(n1500), .A1(n593), .B0(n671), .Y(n672) );
OA21XLTS U1173 ( .A0(n673), .A1(n672), .B0(n1075), .Y(
Sgf_operation_EVEN1_right_N1) );
AOI22X1TS U1174 ( .A0(n1504), .A1(n423), .B0(n1084), .B1(n1341), .Y(n674) );
INVX2TS U1175 ( .A(DP_OP_111J19_123_4462_n36), .Y(intadd_49_A_20_) );
INVX2TS U1176 ( .A(DP_OP_111J19_123_4462_n37), .Y(intadd_49_B_19_) );
INVX2TS U1177 ( .A(DP_OP_111J19_123_4462_n39), .Y(intadd_49_A_19_) );
INVX2TS U1178 ( .A(DP_OP_111J19_123_4462_n40), .Y(intadd_49_B_18_) );
INVX2TS U1179 ( .A(DP_OP_111J19_123_4462_n44), .Y(intadd_49_A_18_) );
INVX2TS U1180 ( .A(DP_OP_111J19_123_4462_n49), .Y(intadd_49_B_17_) );
INVX2TS U1181 ( .A(DP_OP_111J19_123_4462_n45), .Y(intadd_49_A_17_) );
INVX2TS U1182 ( .A(DP_OP_111J19_123_4462_n56), .Y(intadd_49_A_16_) );
INVX2TS U1183 ( .A(DP_OP_111J19_123_4462_n57), .Y(intadd_49_B_15_) );
INVX2TS U1184 ( .A(DP_OP_111J19_123_4462_n62), .Y(intadd_49_A_15_) );
BUFX3TS U1185 ( .A(Op_MX[9]), .Y(n1519) );
INVX2TS U1186 ( .A(n1519), .Y(n931) );
NAND2X1TS U1187 ( .A(n1518), .B(Op_MX[8]), .Y(n1139) );
NAND2BXLTS U1188 ( .AN(n1139), .B(n931), .Y(n675) );
INVX2TS U1189 ( .A(n539), .Y(n1419) );
AOI22X1TS U1190 ( .A0(n1502), .A1(n429), .B0(n506), .B1(n538), .Y(n676) );
INVX2TS U1191 ( .A(DP_OP_111J19_123_4462_n63), .Y(intadd_49_B_14_) );
INVX2TS U1192 ( .A(DP_OP_111J19_123_4462_n70), .Y(intadd_49_A_14_) );
INVX2TS U1193 ( .A(DP_OP_111J19_123_4462_n71), .Y(intadd_49_B_13_) );
INVX2TS U1194 ( .A(DP_OP_111J19_123_4462_n78), .Y(intadd_49_A_13_) );
INVX2TS U1195 ( .A(DP_OP_111J19_123_4462_n79), .Y(intadd_49_B_12_) );
INVX2TS U1196 ( .A(DP_OP_111J19_123_4462_n88), .Y(intadd_49_A_12_) );
INVX2TS U1197 ( .A(DP_OP_111J19_123_4462_n89), .Y(intadd_49_B_11_) );
INVX2TS U1198 ( .A(DP_OP_111J19_123_4462_n97), .Y(intadd_49_A_11_) );
INVX2TS U1199 ( .A(DP_OP_111J19_123_4462_n98), .Y(intadd_49_B_10_) );
INVX2TS U1200 ( .A(DP_OP_111J19_123_4462_n105), .Y(intadd_49_A_10_) );
AOI22X1TS U1201 ( .A0(Op_MY[4]), .A1(n429), .B0(n506), .B1(n1025), .Y(n678)
);
INVX2TS U1202 ( .A(DP_OP_111J19_123_4462_n106), .Y(intadd_49_B_9_) );
INVX2TS U1203 ( .A(DP_OP_111J19_123_4462_n114), .Y(intadd_49_A_8_) );
INVX2TS U1204 ( .A(DP_OP_111J19_123_4462_n122), .Y(intadd_49_B_7_) );
INVX2TS U1205 ( .A(DP_OP_111J19_123_4462_n127), .Y(intadd_49_A_7_) );
INVX2TS U1206 ( .A(mult_x_55_n133), .Y(intadd_50_A_3_) );
INVX2TS U1207 ( .A(mult_x_55_n128), .Y(intadd_50_B_4_) );
INVX2TS U1208 ( .A(mult_x_55_n123), .Y(intadd_50_B_5_) );
INVX2TS U1209 ( .A(mult_x_55_n127), .Y(intadd_50_A_5_) );
INVX2TS U1210 ( .A(mult_x_55_n116), .Y(intadd_50_B_6_) );
INVX2TS U1211 ( .A(mult_x_55_n122), .Y(intadd_50_A_6_) );
INVX2TS U1212 ( .A(mult_x_55_n110), .Y(intadd_50_B_7_) );
INVX2TS U1213 ( .A(mult_x_55_n115), .Y(intadd_50_A_7_) );
INVX2TS U1214 ( .A(mult_x_55_n102), .Y(intadd_50_B_8_) );
INVX2TS U1215 ( .A(mult_x_55_n109), .Y(intadd_50_A_8_) );
INVX2TS U1216 ( .A(mult_x_55_n94), .Y(intadd_50_B_9_) );
INVX2TS U1217 ( .A(mult_x_55_n101), .Y(intadd_50_A_9_) );
INVX2TS U1218 ( .A(mult_x_55_n85), .Y(intadd_50_B_10_) );
INVX2TS U1219 ( .A(mult_x_55_n93), .Y(intadd_50_A_10_) );
INVX2TS U1220 ( .A(mult_x_55_n84), .Y(intadd_50_A_11_) );
INVX2TS U1221 ( .A(mult_x_55_n67), .Y(intadd_50_B_12_) );
INVX2TS U1222 ( .A(mult_x_55_n74), .Y(intadd_50_A_12_) );
INVX2TS U1223 ( .A(mult_x_55_n59), .Y(intadd_50_B_13_) );
INVX2TS U1224 ( .A(mult_x_55_n66), .Y(intadd_50_A_13_) );
INVX2TS U1225 ( .A(mult_x_55_n53), .Y(intadd_50_B_14_) );
INVX2TS U1226 ( .A(mult_x_55_n58), .Y(intadd_50_A_14_) );
INVX2TS U1227 ( .A(mult_x_55_n46), .Y(intadd_50_B_15_) );
INVX2TS U1228 ( .A(mult_x_55_n52), .Y(intadd_50_A_15_) );
INVX2TS U1229 ( .A(mult_x_55_n45), .Y(intadd_50_B_16_) );
INVX2TS U1230 ( .A(mult_x_55_n41), .Y(intadd_50_A_16_) );
INVX2TS U1231 ( .A(mult_x_55_n40), .Y(intadd_50_B_17_) );
INVX2TS U1232 ( .A(mult_x_55_n36), .Y(intadd_50_A_17_) );
INVX2TS U1233 ( .A(mult_x_55_n35), .Y(intadd_50_B_18_) );
INVX2TS U1234 ( .A(mult_x_55_n33), .Y(intadd_50_A_18_) );
INVX2TS U1235 ( .A(DP_OP_111J19_123_4462_n128), .Y(intadd_49_B_6_) );
INVX2TS U1236 ( .A(DP_OP_111J19_123_4462_n134), .Y(intadd_49_A_6_) );
INVX2TS U1237 ( .A(DP_OP_111J19_123_4462_n135), .Y(intadd_49_B_5_) );
INVX2TS U1238 ( .A(DP_OP_111J19_123_4462_n139), .Y(intadd_49_A_5_) );
INVX2TS U1239 ( .A(DP_OP_111J19_123_4462_n144), .Y(intadd_49_B_4_) );
INVX2TS U1240 ( .A(DP_OP_111J19_123_4462_n140), .Y(intadd_49_A_4_) );
INVX2TS U1241 ( .A(DP_OP_111J19_123_4462_n145), .Y(intadd_49_A_3_) );
NOR2X1TS U1242 ( .A(n1492), .B(n1475), .Y(intadd_53_CI) );
NAND2X1TS U1243 ( .A(n681), .B(intadd_53_SUM_0_), .Y(n679) );
INVX2TS U1244 ( .A(n681), .Y(n1374) );
INVX2TS U1245 ( .A(intadd_53_SUM_0_), .Y(n1373) );
AOI22X1TS U1246 ( .A0(n1106), .A1(intadd_52_SUM_2_), .B0(n682), .B1(n573),
.Y(n683) );
OAI21X1TS U1247 ( .A0(intadd_52_SUM_2_), .A1(n1104), .B0(n683), .Y(n819) );
AOI22X1TS U1248 ( .A0(n486), .A1(n450), .B0(n648), .B1(n485), .Y(n684) );
NAND2X1TS U1249 ( .A(n819), .B(n820), .Y(intadd_49_A_1_) );
NAND2X1TS U1250 ( .A(Op_MX[10]), .B(n1519), .Y(n1354) );
INVX2TS U1251 ( .A(n1347), .Y(n1343) );
NAND2BX1TS U1252 ( .AN(n725), .B(n659), .Y(n685) );
AND3X2TS U1253 ( .A(Op_MX[10]), .B(n659), .C(n1519), .Y(n1348) );
AOI22X1TS U1254 ( .A0(n1502), .A1(n1348), .B0(n459), .B1(n1419), .Y(n686) );
AOI22X1TS U1255 ( .A0(n1106), .A1(intadd_52_SUM_1_), .B0(n682), .B1(n522),
.Y(n687) );
OAI21X1TS U1256 ( .A0(intadd_52_SUM_1_), .A1(n1104), .B0(n687), .Y(n689) );
OAI211X1TS U1257 ( .A0(n1374), .A1(n485), .B0(intadd_53_SUM_0_), .C0(n534),
.Y(n692) );
OAI21X1TS U1258 ( .A0(n534), .A1(n688), .B0(n692), .Y(n690) );
NAND2X1TS U1259 ( .A(n689), .B(n690), .Y(intadd_49_CI) );
OA21XLTS U1260 ( .A0(n690), .A1(n689), .B0(intadd_49_CI), .Y(
Sgf_operation_EVEN1_middle_N2) );
NOR2X1TS U1261 ( .A(n1374), .B(n535), .Y(Sgf_operation_EVEN1_middle_N0) );
NOR2XLTS U1262 ( .A(Sgf_operation_EVEN1_middle_N0), .B(n1373), .Y(n694) );
NAND2X1TS U1263 ( .A(intadd_52_SUM_0_), .B(n680), .Y(n691) );
OAI21XLTS U1264 ( .A0(n486), .A1(n579), .B0(n691), .Y(n693) );
OA21XLTS U1265 ( .A0(n694), .A1(n693), .B0(n692), .Y(
Sgf_operation_EVEN1_middle_N1) );
INVX2TS U1266 ( .A(mult_x_23_n35), .Y(intadd_51_B_18_) );
INVX2TS U1267 ( .A(mult_x_23_n33), .Y(intadd_51_A_18_) );
INVX2TS U1268 ( .A(mult_x_23_n40), .Y(intadd_51_B_17_) );
INVX2TS U1269 ( .A(mult_x_23_n36), .Y(intadd_51_A_17_) );
INVX2TS U1270 ( .A(mult_x_23_n45), .Y(intadd_51_B_16_) );
INVX2TS U1271 ( .A(mult_x_23_n41), .Y(intadd_51_A_16_) );
INVX2TS U1272 ( .A(mult_x_23_n46), .Y(intadd_51_B_15_) );
INVX2TS U1273 ( .A(mult_x_23_n52), .Y(intadd_51_A_15_) );
INVX2TS U1274 ( .A(mult_x_23_n53), .Y(intadd_51_B_14_) );
INVX2TS U1275 ( .A(mult_x_23_n58), .Y(intadd_51_A_14_) );
AOI22X1TS U1276 ( .A0(Op_MY[5]), .A1(n1348), .B0(n459), .B1(n496), .Y(n695)
);
INVX2TS U1277 ( .A(mult_x_23_n59), .Y(intadd_51_B_13_) );
INVX2TS U1278 ( .A(mult_x_23_n67), .Y(intadd_51_B_12_) );
INVX2TS U1279 ( .A(mult_x_23_n74), .Y(intadd_51_A_12_) );
INVX2TS U1280 ( .A(mult_x_23_n75), .Y(intadd_51_B_11_) );
INVX2TS U1281 ( .A(mult_x_23_n84), .Y(intadd_51_A_11_) );
INVX2TS U1282 ( .A(mult_x_23_n85), .Y(intadd_51_B_10_) );
INVX2TS U1283 ( .A(mult_x_23_n93), .Y(intadd_51_A_10_) );
INVX2TS U1284 ( .A(mult_x_23_n94), .Y(intadd_51_B_9_) );
INVX2TS U1285 ( .A(mult_x_23_n101), .Y(intadd_51_A_9_) );
AOI22X1TS U1286 ( .A0(n1507), .A1(n429), .B0(n506), .B1(n570), .Y(n696) );
INVX2TS U1287 ( .A(mult_x_23_n102), .Y(intadd_51_B_8_) );
INVX2TS U1288 ( .A(mult_x_23_n109), .Y(intadd_51_A_8_) );
INVX2TS U1289 ( .A(mult_x_23_n110), .Y(intadd_51_B_7_) );
INVX2TS U1290 ( .A(mult_x_23_n115), .Y(intadd_51_A_7_) );
INVX2TS U1291 ( .A(mult_x_23_n116), .Y(intadd_51_B_6_) );
INVX2TS U1292 ( .A(mult_x_23_n122), .Y(intadd_51_A_6_) );
INVX2TS U1293 ( .A(mult_x_23_n127), .Y(intadd_51_A_5_) );
INVX2TS U1294 ( .A(mult_x_23_n128), .Y(intadd_51_B_4_) );
INVX2TS U1295 ( .A(mult_x_23_n132), .Y(intadd_51_A_4_) );
INVX2TS U1296 ( .A(mult_x_23_n133), .Y(intadd_51_A_3_) );
NAND2X1TS U1297 ( .A(Op_MX[13]), .B(Op_MX[14]), .Y(n772) );
NAND2X1TS U1298 ( .A(Op_MX[15]), .B(n772), .Y(mult_x_23_n205) );
NAND2X1TS U1299 ( .A(Op_MX[19]), .B(Op_MX[20]), .Y(n698) );
NAND2X1TS U1300 ( .A(Op_MX[21]), .B(n698), .Y(mult_x_23_n163) );
INVX2TS U1301 ( .A(n525), .Y(n1421) );
AOI22X1TS U1302 ( .A0(n1508), .A1(n391), .B0(n448), .B1(n1421), .Y(n699) );
NAND2X1TS U1303 ( .A(n1405), .B(Op_MX[21]), .Y(n700) );
AO21X1TS U1304 ( .A0(Op_MX[20]), .A1(Op_MX[19]), .B0(n1405), .Y(n777) );
NOR2XLTS U1305 ( .A(Op_MX[21]), .B(n777), .Y(n701) );
AOI22X1TS U1306 ( .A0(n1397), .A1(n1325), .B0(n463), .B1(n1423), .Y(n702) );
AOI22X1TS U1307 ( .A0(n1510), .A1(n1325), .B0(n463), .B1(mult_x_23_n64), .Y(
n703) );
AOI22X1TS U1308 ( .A0(n1509), .A1(n1325), .B0(n463), .B1(n1422), .Y(n704) );
AOI22X1TS U1309 ( .A0(n516), .A1(n643), .B0(n1364), .B1(n515), .Y(n705) );
NOR2XLTS U1310 ( .A(intadd_53_SUM_2_), .B(intadd_53_SUM_3_), .Y(n706) );
NAND2X2TS U1311 ( .A(n1108), .B(intadd_53_SUM_4_), .Y(n1369) );
INVX2TS U1312 ( .A(intadd_53_SUM_4_), .Y(n708) );
NAND2X1TS U1313 ( .A(intadd_53_SUM_2_), .B(intadd_53_SUM_3_), .Y(n727) );
NOR3XLTS U1314 ( .A(intadd_53_SUM_2_), .B(intadd_53_SUM_3_), .C(n708), .Y(
n709) );
CLKBUFX3TS U1315 ( .A(n709), .Y(n1367) );
AOI22X1TS U1316 ( .A0(n492), .A1(n508), .B0(n1367), .B1(n575), .Y(n710) );
OAI221X1TS U1317 ( .A0(n480), .A1(n1369), .B0(n479), .B1(n465), .C0(n710),
.Y(n711) );
NAND2X1TS U1318 ( .A(n711), .B(n712), .Y(n978) );
OA21XLTS U1319 ( .A0(n712), .A1(n711), .B0(n978), .Y(
DP_OP_111J19_123_4462_n119) );
AOI22X1TS U1320 ( .A0(n490), .A1(n465), .B0(n1369), .B1(n571), .Y(n713) );
AOI22X1TS U1321 ( .A0(n492), .A1(n1372), .B0(n493), .B1(n491), .Y(n714) );
NOR2X1TS U1322 ( .A(n790), .B(n791), .Y(DP_OP_111J19_123_4462_n131) );
AOI22X1TS U1323 ( .A0(n488), .A1(n508), .B0(n1367), .B1(n573), .Y(n715) );
OAI221X1TS U1324 ( .A0(n514), .A1(n1369), .B0(n513), .B1(n465), .C0(n715),
.Y(n718) );
AOI22X1TS U1325 ( .A0(n490), .A1(n450), .B0(n589), .B1(n489), .Y(n716) );
NAND2X1TS U1326 ( .A(n717), .B(n718), .Y(n967) );
OA21XLTS U1327 ( .A0(n718), .A1(n717), .B0(n967), .Y(
DP_OP_111J19_123_4462_n142) );
AOI22X1TS U1328 ( .A0(n488), .A1(n1372), .B0(n493), .B1(n573), .Y(n719) );
INVX2TS U1329 ( .A(n682), .Y(n1103) );
OAI22X1TS U1330 ( .A0(intadd_52_SUM_4_), .A1(n1104), .B0(n516), .B1(n1103),
.Y(n720) );
AOI21X1TS U1331 ( .A0(n680), .A1(intadd_52_SUM_4_), .B0(n720), .Y(n1101) );
NOR2X1TS U1332 ( .A(n1100), .B(n1101), .Y(DP_OP_111J19_123_4462_n148) );
NAND2X1TS U1333 ( .A(n1517), .B(Op_MX[6]), .Y(n783) );
NAND2X1TS U1334 ( .A(n1518), .B(n783), .Y(mult_x_55_n183) );
INVX2TS U1335 ( .A(Op_MX[13]), .Y(mult_x_23_n219) );
NAND2X1TS U1336 ( .A(Op_MX[17]), .B(Op_MX[18]), .Y(n722) );
NAND2X1TS U1337 ( .A(Op_MX[19]), .B(n722), .Y(mult_x_23_n177) );
NAND2X1TS U1338 ( .A(Op_MX[15]), .B(Op_MX[16]), .Y(n723) );
NAND2X1TS U1339 ( .A(Op_MX[17]), .B(n723), .Y(mult_x_23_n191) );
NAND2X1TS U1340 ( .A(n1506), .B(Op_MX[11]), .Y(mult_x_55_n38) );
NAND2X1TS U1341 ( .A(n1516), .B(Op_MX[4]), .Y(n724) );
NAND2X1TS U1342 ( .A(n1517), .B(n724), .Y(mult_x_55_n197) );
NOR2X1TS U1343 ( .A(n1418), .B(n725), .Y(mult_x_55_n168) );
NAND2X1TS U1344 ( .A(n542), .B(Op_MX[11]), .Y(mult_x_55_n64) );
NAND2X1TS U1345 ( .A(intadd_53_SUM_8_), .B(n726), .Y(
DP_OP_111J19_123_4462_n188) );
NAND2X1TS U1346 ( .A(intadd_53_SUM_4_), .B(n727), .Y(
DP_OP_111J19_123_4462_n215) );
AND2X2TS U1347 ( .A(n1033), .B(n1031), .Y(n1393) );
CLKBUFX2TS U1348 ( .A(n1393), .Y(n1392) );
INVX2TS U1349 ( .A(n1392), .Y(n1394) );
INVX2TS U1350 ( .A(n1392), .Y(n1395) );
NOR3X2TS U1351 ( .A(n1481), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[2]), .Y(n1046) );
NOR4X1TS U1352 ( .A(P_Sgf[13]), .B(P_Sgf[17]), .C(P_Sgf[15]), .D(P_Sgf[16]),
.Y(n734) );
NOR4X1TS U1353 ( .A(P_Sgf[20]), .B(P_Sgf[18]), .C(P_Sgf[19]), .D(P_Sgf[21]),
.Y(n733) );
NOR4X1TS U1354 ( .A(P_Sgf[1]), .B(P_Sgf[5]), .C(P_Sgf[3]), .D(P_Sgf[4]), .Y(
n731) );
NOR4X1TS U1355 ( .A(P_Sgf[9]), .B(P_Sgf[10]), .C(P_Sgf[14]), .D(P_Sgf[12]),
.Y(n729) );
NOR4X1TS U1356 ( .A(P_Sgf[8]), .B(P_Sgf[6]), .C(P_Sgf[7]), .D(P_Sgf[11]),
.Y(n728) );
AND4X1TS U1357 ( .A(n731), .B(n730), .C(n729), .D(n728), .Y(n732) );
XOR2X1TS U1358 ( .A(Op_MY[31]), .B(Op_MX[31]), .Y(n1037) );
MXI2X1TS U1359 ( .A(round_mode[0]), .B(round_mode[1]), .S0(n1037), .Y(n735)
);
OAI211X1TS U1360 ( .A0(round_mode[0]), .A1(round_mode[1]), .B0(n736), .C0(
n735), .Y(n739) );
NOR2X1TS U1361 ( .A(n1483), .B(FS_Module_state_reg[2]), .Y(n760) );
AOI22X1TS U1362 ( .A0(n1046), .A1(n739), .B0(n1033), .B1(n738), .Y(n740) );
OAI2BB1X1TS U1363 ( .A0N(n760), .A1N(n1547), .B0(n740), .Y(n378) );
NAND2X1TS U1364 ( .A(n1043), .B(FS_Module_state_reg[1]), .Y(n741) );
NAND2X1TS U1365 ( .A(n741), .B(n1041), .Y(n742) );
INVX2TS U1366 ( .A(n742), .Y(n753) );
INVX2TS U1367 ( .A(n742), .Y(n1463) );
BUFX3TS U1368 ( .A(n1463), .Y(n1464) );
BUFX3TS U1369 ( .A(n1463), .Y(n1457) );
INVX2TS U1370 ( .A(n753), .Y(n752) );
CLKXOR2X2TS U1371 ( .A(Sgf_operation_EVEN1_Q_middle[25]), .B(intadd_47_n1),
.Y(n747) );
CLKAND2X2TS U1372 ( .A(n1459), .B(Sgf_operation_EVEN1_Q_left[15]), .Y(n1461)
);
NAND2X1TS U1373 ( .A(n1461), .B(Sgf_operation_EVEN1_Q_left[16]), .Y(n1454)
);
INVX2TS U1374 ( .A(Sgf_operation_EVEN1_Q_left[17]), .Y(n743) );
AOI21X1TS U1375 ( .A0(n1454), .A1(n743), .B0(n1451), .Y(n744) );
NAND2X1TS U1376 ( .A(n1451), .B(Sgf_operation_EVEN1_Q_left[18]), .Y(n1450)
);
INVX2TS U1377 ( .A(Sgf_operation_EVEN1_Q_left[19]), .Y(n745) );
AOI21X1TS U1378 ( .A0(n1450), .A1(n745), .B0(n1447), .Y(n746) );
XOR2XLTS U1379 ( .A(Sgf_operation_EVEN1_Q_left[13]), .B(n747), .Y(n748) );
XOR2XLTS U1380 ( .A(intadd_48_n1), .B(n748), .Y(n749) );
NAND2X1TS U1381 ( .A(n1447), .B(Sgf_operation_EVEN1_Q_left[20]), .Y(n1446)
);
INVX2TS U1382 ( .A(Sgf_operation_EVEN1_Q_left[21]), .Y(n750) );
AOI21X1TS U1383 ( .A0(n1446), .A1(n750), .B0(n1444), .Y(n751) );
BUFX3TS U1384 ( .A(n753), .Y(n1387) );
INVX2TS U1385 ( .A(n753), .Y(n756) );
BUFX3TS U1386 ( .A(n753), .Y(n757) );
INVX2TS U1387 ( .A(n753), .Y(n1462) );
INVX2TS U1388 ( .A(Sgf_operation_EVEN1_Q_right[12]), .Y(n754) );
NOR2X1TS U1389 ( .A(n754), .B(intadd_47_SUM_0_), .Y(intadd_48_CI) );
AOI21X1TS U1390 ( .A0(intadd_47_SUM_0_), .A1(n754), .B0(intadd_48_CI), .Y(
n755) );
INVX1TS U1391 ( .A(Op_MY[19]), .Y(n758) );
CLKBUFX2TS U1392 ( .A(n1441), .Y(n1466) );
INVX2TS U1393 ( .A(n1466), .Y(n1472) );
OR3X1TS U1394 ( .A(underflow_flag), .B(overflow_flag), .C(n1472), .Y(n1469)
);
BUFX3TS U1395 ( .A(n1469), .Y(n1442) );
INVX2TS U1396 ( .A(n1442), .Y(n1473) );
INVX2TS U1397 ( .A(n1466), .Y(n1470) );
NAND2X1TS U1398 ( .A(n1092), .B(n428), .Y(n917) );
NAND2X1TS U1399 ( .A(n1515), .B(Op_MX[2]), .Y(n1116) );
NOR2X1TS U1400 ( .A(n1515), .B(Op_MX[2]), .Y(n1406) );
NAND2X1TS U1401 ( .A(n1076), .B(n1495), .Y(n762) );
AOI22X1TS U1402 ( .A0(n552), .A1(n432), .B0(n763), .B1(n551), .Y(n764) );
OAI21XLTS U1403 ( .A0(Op_MX[0]), .A1(n637), .B0(n1515), .Y(n915) );
INVX2TS U1404 ( .A(n765), .Y(mult_x_55_n99) );
AOI22X1TS U1405 ( .A0(n1506), .A1(n599), .B0(n505), .B1(n1062), .Y(n766) );
NAND2X1TS U1406 ( .A(Op_MY[1]), .B(n428), .Y(n924) );
INVX2TS U1407 ( .A(n924), .Y(n952) );
AOI22X1TS U1408 ( .A0(Op_MY[4]), .A1(n457), .B0(n440), .B1(n1025), .Y(n767)
);
INVX2TS U1409 ( .A(n768), .Y(mult_x_55_n89) );
CMPR32X2TS U1410 ( .A(n770), .B(n952), .C(n769), .CO(n768), .S(n771) );
INVX2TS U1411 ( .A(n771), .Y(mult_x_55_n90) );
NOR2X1TS U1412 ( .A(Op_MX[13]), .B(Op_MX[14]), .Y(n1411) );
NAND2X1TS U1413 ( .A(n1133), .B(n1494), .Y(n774) );
NAND2X1TS U1414 ( .A(Op_MX[15]), .B(n1133), .Y(n775) );
AOI22X1TS U1415 ( .A0(n1511), .A1(n437), .B0(n467), .B1(n1420), .Y(n776) );
NAND2BXLTS U1416 ( .AN(n777), .B(n562), .Y(n927) );
CLKBUFX3TS U1417 ( .A(n778), .Y(n1136) );
NOR2X2TS U1418 ( .A(n1475), .B(mult_x_23_n219), .Y(n1145) );
INVX2TS U1419 ( .A(n1145), .Y(n1122) );
OAI22X1TS U1420 ( .A0(n1512), .A1(n779), .B0(n1513), .B1(n1122), .Y(n780) );
AOI21X1TS U1421 ( .A0(n1136), .A1(n1513), .B0(n780), .Y(n926) );
INVX2TS U1422 ( .A(n781), .Y(mult_x_23_n125) );
INVX2TS U1423 ( .A(n824), .Y(n1017) );
INVX2TS U1424 ( .A(n871), .Y(n1018) );
AOI22X1TS U1425 ( .A0(Op_MY[8]), .A1(n1017), .B0(n559), .B1(n1062), .Y(n784)
);
NAND2X1TS U1426 ( .A(n1502), .B(n428), .Y(n922) );
INVX2TS U1427 ( .A(n785), .Y(mult_x_55_n72) );
AOI22X1TS U1428 ( .A0(Op_MY[6]), .A1(n432), .B0(n763), .B1(n1341), .Y(n786)
);
NAND2BXLTS U1429 ( .AN(n787), .B(n1092), .Y(n947) );
NOR2X2TS U1430 ( .A(Op_MX[0]), .B(n607), .Y(n1073) );
INVX2TS U1431 ( .A(n1073), .Y(n1087) );
OAI22X1TS U1432 ( .A0(n543), .A1(n1086), .B0(n1505), .B1(n1087), .Y(n788) );
AOI21X1TS U1433 ( .A0(n1089), .A1(n543), .B0(n788), .Y(n946) );
INVX2TS U1434 ( .A(n789), .Y(mult_x_55_n125) );
AO21XLTS U1435 ( .A0(n791), .A1(n790), .B0(DP_OP_111J19_123_4462_n131), .Y(
n842) );
AOI22X1TS U1436 ( .A0(n514), .A1(n443), .B0(n640), .B1(n564), .Y(n792) );
AOI22X1TS U1437 ( .A0(n516), .A1(n466), .B0(n1369), .B1(n563), .Y(n793) );
AOI22X1TS U1438 ( .A0(n490), .A1(n1372), .B0(n493), .B1(n489), .Y(n794) );
INVX2TS U1439 ( .A(n795), .Y(DP_OP_111J19_123_4462_n129) );
AOI22X1TS U1440 ( .A0(Op_MY[20]), .A1(n602), .B0(n447), .B1(mult_x_23_n38),
.Y(n796) );
AOI22X1TS U1441 ( .A0(n1510), .A1(n598), .B0(n462), .B1(mult_x_23_n64), .Y(
n797) );
INVX2TS U1442 ( .A(n798), .Y(mult_x_23_n90) );
CMPR32X2TS U1443 ( .A(Op_MY[13]), .B(n800), .C(n799), .CO(n801), .S(n798) );
INVX2TS U1444 ( .A(n801), .Y(mult_x_23_n89) );
INVX2TS U1445 ( .A(intadd_50_SUM_18_), .Y(Sgf_operation_EVEN1_right_N21) );
INVX2TS U1446 ( .A(intadd_50_SUM_15_), .Y(Sgf_operation_EVEN1_right_N18) );
INVX2TS U1447 ( .A(intadd_50_SUM_16_), .Y(Sgf_operation_EVEN1_right_N19) );
INVX2TS U1448 ( .A(intadd_50_SUM_14_), .Y(Sgf_operation_EVEN1_right_N17) );
INVX2TS U1449 ( .A(intadd_50_SUM_19_), .Y(Sgf_operation_EVEN1_right_N22) );
INVX2TS U1450 ( .A(intadd_50_SUM_13_), .Y(Sgf_operation_EVEN1_right_N16) );
INVX2TS U1451 ( .A(intadd_50_SUM_17_), .Y(Sgf_operation_EVEN1_right_N20) );
INVX2TS U1452 ( .A(n640), .Y(n1069) );
AOI22X1TS U1453 ( .A0(n497), .A1(n651), .B0(n452), .B1(n519), .Y(n802) );
CLKAND2X2TS U1454 ( .A(n803), .B(intadd_53_SUM_6_), .Y(n805) );
INVX2TS U1455 ( .A(n804), .Y(DP_OP_111J19_123_4462_n47) );
INVX2TS U1456 ( .A(intadd_50_SUM_12_), .Y(Sgf_operation_EVEN1_right_N15) );
INVX2TS U1457 ( .A(n807), .Y(DP_OP_111J19_123_4462_n46) );
INVX2TS U1458 ( .A(intadd_50_SUM_11_), .Y(Sgf_operation_EVEN1_right_N14) );
AOI22X1TS U1459 ( .A0(n1106), .A1(n390), .B0(n682), .B1(n479), .Y(n808) );
OAI21XLTS U1460 ( .A0(n390), .A1(n579), .B0(n808), .Y(
DP_OP_111J19_123_4462_n250) );
INVX2TS U1461 ( .A(intadd_50_SUM_10_), .Y(Sgf_operation_EVEN1_right_N13) );
INVX2TS U1462 ( .A(intadd_50_SUM_9_), .Y(Sgf_operation_EVEN1_right_N12) );
INVX2TS U1463 ( .A(intadd_50_SUM_8_), .Y(Sgf_operation_EVEN1_right_N11) );
AOI22X1TS U1464 ( .A0(n1106), .A1(intadd_52_SUM_5_), .B0(n682), .B1(n571),
.Y(n809) );
INVX2TS U1465 ( .A(intadd_50_SUM_7_), .Y(Sgf_operation_EVEN1_right_N10) );
INVX2TS U1466 ( .A(intadd_50_SUM_6_), .Y(Sgf_operation_EVEN1_right_N9) );
INVX2TS U1467 ( .A(intadd_50_SUM_5_), .Y(Sgf_operation_EVEN1_right_N8) );
INVX2TS U1468 ( .A(intadd_50_SUM_4_), .Y(Sgf_operation_EVEN1_right_N7) );
INVX2TS U1469 ( .A(intadd_50_SUM_3_), .Y(Sgf_operation_EVEN1_right_N6) );
INVX2TS U1470 ( .A(intadd_50_SUM_2_), .Y(Sgf_operation_EVEN1_right_N5) );
INVX2TS U1471 ( .A(intadd_50_SUM_1_), .Y(Sgf_operation_EVEN1_right_N4) );
INVX2TS U1472 ( .A(intadd_50_SUM_0_), .Y(Sgf_operation_EVEN1_right_N3) );
AOI22X1TS U1473 ( .A0(n1501), .A1(n1017), .B0(n559), .B1(n528), .Y(n810) );
AOI22X1TS U1474 ( .A0(n1092), .A1(n458), .B0(n441), .B1(n1418), .Y(n811) );
AOI22X1TS U1475 ( .A0(n1505), .A1(n432), .B0(n763), .B1(n540), .Y(n812) );
INVX2TS U1476 ( .A(n813), .Y(mult_x_55_n118) );
INVX2TS U1477 ( .A(intadd_49_SUM_21_), .Y(Sgf_operation_EVEN1_middle_N24) );
INVX2TS U1478 ( .A(intadd_49_SUM_20_), .Y(Sgf_operation_EVEN1_middle_N23) );
INVX2TS U1479 ( .A(intadd_49_SUM_19_), .Y(Sgf_operation_EVEN1_middle_N22) );
INVX2TS U1480 ( .A(intadd_49_SUM_18_), .Y(Sgf_operation_EVEN1_middle_N21) );
INVX2TS U1481 ( .A(intadd_49_SUM_17_), .Y(Sgf_operation_EVEN1_middle_N20) );
INVX2TS U1482 ( .A(intadd_49_SUM_16_), .Y(Sgf_operation_EVEN1_middle_N19) );
INVX2TS U1483 ( .A(intadd_49_SUM_15_), .Y(Sgf_operation_EVEN1_middle_N18) );
INVX2TS U1484 ( .A(intadd_49_SUM_14_), .Y(Sgf_operation_EVEN1_middle_N17) );
INVX2TS U1485 ( .A(intadd_49_SUM_13_), .Y(Sgf_operation_EVEN1_middle_N16) );
INVX2TS U1486 ( .A(intadd_49_SUM_12_), .Y(Sgf_operation_EVEN1_middle_N15) );
INVX2TS U1487 ( .A(intadd_49_SUM_11_), .Y(Sgf_operation_EVEN1_middle_N14) );
INVX2TS U1488 ( .A(intadd_49_SUM_10_), .Y(Sgf_operation_EVEN1_middle_N13) );
INVX2TS U1489 ( .A(intadd_49_SUM_9_), .Y(Sgf_operation_EVEN1_middle_N12) );
INVX2TS U1490 ( .A(intadd_49_SUM_8_), .Y(Sgf_operation_EVEN1_middle_N11) );
INVX2TS U1491 ( .A(intadd_49_SUM_7_), .Y(Sgf_operation_EVEN1_middle_N10) );
AOI22X1TS U1492 ( .A0(n1502), .A1(n1089), .B0(n1073), .B1(n528), .Y(n814) );
OAI21X1TS U1493 ( .A0(n539), .A1(n1086), .B0(n814), .Y(n816) );
AOI22X1TS U1494 ( .A0(n1092), .A1(n1091), .B0(n510), .B1(n545), .Y(n815) );
NAND2X1TS U1495 ( .A(n816), .B(n817), .Y(intadd_50_A_1_) );
OAI21XLTS U1496 ( .A0(n817), .A1(n816), .B0(intadd_50_A_1_), .Y(
intadd_50_A_0_) );
OAI22X1TS U1497 ( .A0(n542), .A1(n1087), .B0(n523), .B1(n1086), .Y(n818) );
AOI21X1TS U1498 ( .A0(n1089), .A1(n523), .B0(n818), .Y(n1081) );
INVX2TS U1499 ( .A(n1084), .Y(n1345) );
OA21XLTS U1500 ( .A0(n1345), .A1(n1092), .B0(n505), .Y(n1082) );
NOR2X1TS U1501 ( .A(n1081), .B(n1082), .Y(mult_x_55_n136) );
INVX2TS U1502 ( .A(intadd_49_SUM_6_), .Y(Sgf_operation_EVEN1_middle_N9) );
INVX2TS U1503 ( .A(intadd_49_SUM_5_), .Y(Sgf_operation_EVEN1_middle_N8) );
INVX2TS U1504 ( .A(intadd_49_SUM_4_), .Y(Sgf_operation_EVEN1_middle_N7) );
INVX2TS U1505 ( .A(intadd_49_SUM_3_), .Y(Sgf_operation_EVEN1_middle_N6) );
INVX2TS U1506 ( .A(intadd_49_SUM_2_), .Y(Sgf_operation_EVEN1_middle_N5) );
INVX2TS U1507 ( .A(intadd_49_SUM_1_), .Y(Sgf_operation_EVEN1_middle_N4) );
INVX2TS U1508 ( .A(intadd_49_SUM_0_), .Y(Sgf_operation_EVEN1_middle_N3) );
INVX2TS U1509 ( .A(intadd_51_SUM_19_), .Y(Sgf_operation_EVEN1_left_N22) );
INVX2TS U1510 ( .A(mult_x_23_n32), .Y(intadd_51_A_19_) );
INVX2TS U1511 ( .A(intadd_51_SUM_18_), .Y(Sgf_operation_EVEN1_left_N21) );
INVX2TS U1512 ( .A(intadd_51_SUM_17_), .Y(Sgf_operation_EVEN1_left_N20) );
INVX2TS U1513 ( .A(intadd_51_SUM_16_), .Y(Sgf_operation_EVEN1_left_N19) );
INVX2TS U1514 ( .A(intadd_51_SUM_15_), .Y(Sgf_operation_EVEN1_left_N18) );
INVX2TS U1515 ( .A(intadd_51_SUM_14_), .Y(Sgf_operation_EVEN1_left_N17) );
INVX2TS U1516 ( .A(intadd_51_SUM_13_), .Y(Sgf_operation_EVEN1_left_N16) );
INVX2TS U1517 ( .A(intadd_51_SUM_12_), .Y(Sgf_operation_EVEN1_left_N15) );
INVX2TS U1518 ( .A(intadd_51_SUM_11_), .Y(Sgf_operation_EVEN1_left_N14) );
INVX2TS U1519 ( .A(intadd_51_SUM_10_), .Y(Sgf_operation_EVEN1_left_N13) );
INVX2TS U1520 ( .A(intadd_51_SUM_9_), .Y(Sgf_operation_EVEN1_left_N12) );
INVX2TS U1521 ( .A(intadd_51_SUM_8_), .Y(Sgf_operation_EVEN1_left_N11) );
INVX2TS U1522 ( .A(intadd_51_SUM_7_), .Y(Sgf_operation_EVEN1_left_N10) );
INVX2TS U1523 ( .A(intadd_51_SUM_6_), .Y(Sgf_operation_EVEN1_left_N9) );
INVX2TS U1524 ( .A(intadd_51_SUM_5_), .Y(Sgf_operation_EVEN1_left_N8) );
INVX2TS U1525 ( .A(intadd_51_SUM_4_), .Y(Sgf_operation_EVEN1_left_N7) );
INVX2TS U1526 ( .A(intadd_51_SUM_3_), .Y(Sgf_operation_EVEN1_left_N6) );
INVX2TS U1527 ( .A(intadd_51_SUM_2_), .Y(Sgf_operation_EVEN1_left_N5) );
OAI22X1TS U1528 ( .A0(n533), .A1(n779), .B0(n521), .B1(n1122), .Y(n821) );
AOI21X1TS U1529 ( .A0(n1136), .A1(n521), .B0(n821), .Y(n1117) );
AOI21X1TS U1530 ( .A0(n449), .A1(n527), .B0(n446), .Y(n1118) );
NOR2X1TS U1531 ( .A(n1117), .B(n1118), .Y(mult_x_23_n136) );
AO21X1TS U1532 ( .A0(Op_MX[18]), .A1(Op_MX[17]), .B0(n1408), .Y(n999) );
NOR2BX1TS U1533 ( .AN(n604), .B(n469), .Y(n897) );
AOI22X1TS U1534 ( .A0(n1397), .A1(n597), .B0(n700), .B1(n1423), .Y(n822) );
INVX2TS U1535 ( .A(n823), .Y(mult_x_23_n47) );
NAND2X1TS U1536 ( .A(n544), .B(n428), .Y(n878) );
INVX2TS U1537 ( .A(n878), .Y(n867) );
AOI22X1TS U1538 ( .A0(n518), .A1(n458), .B0(n441), .B1(n570), .Y(n825) );
AOI221X1TS U1539 ( .A0(n429), .A1(n721), .B0(n506), .B1(n442), .C0(n825),
.Y(n866) );
INVX2TS U1540 ( .A(n826), .Y(mult_x_55_n47) );
INVX2TS U1541 ( .A(intadd_51_SUM_1_), .Y(Sgf_operation_EVEN1_left_N4) );
INVX2TS U1542 ( .A(intadd_51_SUM_0_), .Y(Sgf_operation_EVEN1_left_N3) );
AOI22X1TS U1543 ( .A0(n1509), .A1(n1136), .B0(n1145), .B1(n1422), .Y(n827)
);
OAI21X1TS U1544 ( .A0(Op_MY[14]), .A1(n779), .B0(n827), .Y(n829) );
AOI22X1TS U1545 ( .A0(n562), .A1(n433), .B0(n436), .B1(n527), .Y(n828) );
OAI221X1TS U1546 ( .A0(Op_MY[13]), .A1(n467), .B0(n427), .B1(n437), .C0(n828), .Y(n830) );
NAND2X1TS U1547 ( .A(n829), .B(n830), .Y(intadd_51_A_1_) );
OAI21XLTS U1548 ( .A0(n830), .A1(n829), .B0(intadd_51_A_1_), .Y(
intadd_51_A_0_) );
AOI22X1TS U1549 ( .A0(n721), .A1(n458), .B0(n441), .B1(n551), .Y(n831) );
NAND2X1TS U1550 ( .A(n541), .B(n428), .Y(n876) );
INVX2TS U1551 ( .A(n832), .Y(mult_x_55_n42) );
NOR2X1TS U1552 ( .A(n1475), .B(n526), .Y(Sgf_operation_EVEN1_left_N0) );
CLKBUFX3TS U1553 ( .A(n833), .Y(n1147) );
NAND2X1TS U1554 ( .A(Op_MX[19]), .B(n1408), .Y(n834) );
AOI22X1TS U1555 ( .A0(n1508), .A1(n603), .B0(n471), .B1(n524), .Y(n835) );
AOI22X1TS U1556 ( .A0(n562), .A1(n598), .B0(n700), .B1(n527), .Y(n836) );
AOI22X1TS U1557 ( .A0(n547), .A1(n774), .B0(n467), .B1(n546), .Y(n837) );
AOI221X1TS U1558 ( .A0(n433), .A1(n558), .B0(n436), .B1(n1420), .C0(n837),
.Y(n908) );
INVX2TS U1559 ( .A(n838), .Y(mult_x_23_n118) );
AOI22X1TS U1560 ( .A0(n1106), .A1(n568), .B0(n682), .B1(n572), .Y(n839) );
OAI21X1TS U1561 ( .A0(n1104), .A1(n399), .B0(n839), .Y(
DP_OP_111J19_123_4462_n247) );
CMPR32X2TS U1562 ( .A(n842), .B(n841), .C(n840), .CO(n795), .S(n843) );
INVX2TS U1563 ( .A(n843), .Y(DP_OP_111J19_123_4462_n130) );
AOI22X1TS U1564 ( .A0(n492), .A1(n443), .B0(n640), .B1(n575), .Y(n844) );
AOI22X1TS U1565 ( .A0(n390), .A1(n466), .B0(n596), .B1(n478), .Y(n845) );
AOI22X1TS U1566 ( .A0(n482), .A1(n466), .B0(n596), .B1(n576), .Y(n846) );
AOI22X1TS U1567 ( .A0(n480), .A1(n443), .B0(n640), .B1(n567), .Y(n847) );
INVX2TS U1568 ( .A(n848), .Y(DP_OP_111J19_123_4462_n103) );
AOI22X1TS U1569 ( .A0(n486), .A1(n502), .B0(n1360), .B1(n485), .Y(n849) );
OAI221X1TS U1570 ( .A0(n488), .A1(n1363), .B0(n487), .B1(n454), .C0(n849),
.Y(DP_OP_111J19_123_4462_n185) );
AOI22X1TS U1571 ( .A0(n482), .A1(n443), .B0(n640), .B1(n481), .Y(n851) );
AOI22X1TS U1572 ( .A0(n480), .A1(n452), .B0(n651), .B1(n567), .Y(n852) );
INVX2TS U1573 ( .A(n853), .Y(DP_OP_111J19_123_4462_n84) );
AOI22X1TS U1574 ( .A0(intadd_52_SUM_1_), .A1(n502), .B0(n1360), .B1(n573),
.Y(n854) );
OAI221X1TS U1575 ( .A0(n514), .A1(n1363), .B0(n513), .B1(n454), .C0(n854),
.Y(DP_OP_111J19_123_4462_n184) );
CLKAND2X2TS U1576 ( .A(n855), .B(intadd_53_SUM_2_), .Y(n883) );
AOI22X1TS U1577 ( .A0(n390), .A1(n452), .B0(n651), .B1(n478), .Y(n856) );
INVX2TS U1578 ( .A(n857), .Y(DP_OP_111J19_123_4462_n76) );
AOI22X1TS U1579 ( .A0(intadd_52_SUM_7_), .A1(n443), .B0(n640), .B1(n574),
.Y(n858) );
AOI22X1TS U1580 ( .A0(intadd_52_SUM_5_), .A1(n452), .B0(n651), .B1(n575),
.Y(n859) );
INVX2TS U1581 ( .A(n860), .Y(DP_OP_111J19_123_4462_n94) );
AOI22X1TS U1582 ( .A0(n552), .A1(n425), .B0(n782), .B1(n442), .Y(n861) );
INVX2TS U1583 ( .A(n833), .Y(n862) );
AOI22X1TS U1584 ( .A0(Op_MY[15]), .A1(n391), .B0(n448), .B1(n1422), .Y(n863)
);
OAI221X1TS U1585 ( .A0(n525), .A1(n447), .B0(n524), .B1(n601), .C0(n863),
.Y(mult_x_23_n201) );
AOI22X1TS U1586 ( .A0(n550), .A1(n425), .B0(n782), .B1(n438), .Y(n864) );
NOR2X2TS U1587 ( .A(Op_MX[21]), .B(Op_MX[22]), .Y(n1409) );
INVX2TS U1588 ( .A(n1409), .Y(n1323) );
OAI22X1TS U1589 ( .A0(n547), .A1(n1122), .B0(n1511), .B1(n779), .Y(n865) );
AOI21X1TS U1590 ( .A0(n1136), .A1(n1512), .B0(n865), .Y(n1321) );
AOI21X1TS U1591 ( .A0(n469), .A1(n526), .B0(n470), .Y(n1322) );
NOR2X1TS U1592 ( .A(n1321), .B(n1322), .Y(mult_x_23_n129) );
CMPR32X2TS U1593 ( .A(n868), .B(n867), .C(n866), .CO(n826), .S(n869) );
INVX2TS U1594 ( .A(n869), .Y(mult_x_55_n48) );
OAI22X1TS U1595 ( .A0(n544), .A1(n1087), .B0(n1505), .B1(n1086), .Y(n870) );
AOI21X1TS U1596 ( .A0(n1089), .A1(Op_MY[7]), .B0(n870), .Y(n1339) );
AOI21X1TS U1597 ( .A0(n782), .A1(n545), .B0(n871), .Y(n1340) );
NOR2X1TS U1598 ( .A(n1339), .B(n1340), .Y(mult_x_55_n129) );
AOI22X1TS U1599 ( .A0(n550), .A1(n423), .B0(n1084), .B1(n438), .Y(n872) );
INVX2TS U1600 ( .A(DP_OP_111J19_123_4462_n58), .Y(n894) );
AOI22X1TS U1601 ( .A0(n444), .A1(n651), .B0(n452), .B1(n568), .Y(n873) );
INVX2TS U1602 ( .A(n875), .Y(DP_OP_111J19_123_4462_n51) );
CMPR32X2TS U1603 ( .A(n878), .B(n877), .C(n876), .CO(n832), .S(n879) );
INVX2TS U1604 ( .A(n879), .Y(mult_x_55_n43) );
AOI22X1TS U1605 ( .A0(n1505), .A1(n423), .B0(n1084), .B1(n540), .Y(n880) );
OAI221X1TS U1606 ( .A0(n1504), .A1(n504), .B0(n1341), .B1(n599), .C0(n880),
.Y(mult_x_55_n203) );
AOI22X1TS U1607 ( .A0(n547), .A1(n434), .B0(n1142), .B1(n758), .Y(n881) );
OAI221X1TS U1608 ( .A0(n1513), .A1(n467), .B0(mult_x_23_n38), .B1(n437),
.C0(n881), .Y(mult_x_23_n210) );
CMPR32X2TS U1609 ( .A(intadd_53_SUM_0_), .B(n883), .C(n882), .CO(n884), .S(
n857) );
INVX2TS U1610 ( .A(n884), .Y(DP_OP_111J19_123_4462_n75) );
AOI22X1TS U1611 ( .A0(n518), .A1(n1348), .B0(n459), .B1(n570), .Y(n885) );
OAI221X1TS U1612 ( .A0(n721), .A1(n1343), .B0(n395), .B1(n431), .C0(n885),
.Y(mult_x_55_n158) );
AOI22X1TS U1613 ( .A0(n721), .A1(n423), .B0(n1084), .B1(n442), .Y(n886) );
OAI221X1TS U1614 ( .A0(n518), .A1(n504), .B0(n569), .B1(n600), .C0(n886),
.Y(mult_x_55_n200) );
CMPR32X2TS U1615 ( .A(n889), .B(n888), .C(n887), .CO(n890), .S(n813) );
INVX2TS U1616 ( .A(n890), .Y(mult_x_55_n117) );
AOI22X1TS U1617 ( .A0(n552), .A1(n1348), .B0(n459), .B1(n442), .Y(n891) );
OAI221X1TS U1618 ( .A0(n1417), .A1(n1343), .B0(n438), .B1(n431), .C0(n891),
.Y(mult_x_55_n157) );
CMPR32X2TS U1619 ( .A(n894), .B(n893), .C(n892), .CO(n875), .S(n895) );
INVX2TS U1620 ( .A(n895), .Y(DP_OP_111J19_123_4462_n52) );
CMPR32X2TS U1621 ( .A(n558), .B(n897), .C(n896), .CO(n823), .S(n898) );
INVX2TS U1622 ( .A(n898), .Y(mult_x_23_n48) );
AOI22X1TS U1623 ( .A0(n1502), .A1(n1091), .B0(n510), .B1(n1419), .Y(n899) );
AOI22X1TS U1624 ( .A0(n721), .A1(n1091), .B0(n510), .B1(n442), .Y(n900) );
AOI22X1TS U1625 ( .A0(n1509), .A1(n434), .B0(n436), .B1(n1422), .Y(n901) );
OAI221X1TS U1626 ( .A0(n533), .A1(n467), .B0(mult_x_23_n64), .B1(n437), .C0(
n901), .Y(mult_x_23_n214) );
AOI22X1TS U1627 ( .A0(n482), .A1(n500), .B0(n1071), .B1(n481), .Y(n902) );
AOI22X1TS U1628 ( .A0(n417), .A1(n1147), .B0(n468), .B1(n419), .Y(n903) );
AOI22X1TS U1629 ( .A0(n1511), .A1(n1147), .B0(n468), .B1(n1420), .Y(n904) );
AOI22X1TS U1630 ( .A0(Op_MY[3]), .A1(n424), .B0(n581), .B1(n1419), .Y(n905)
);
OAI221X1TS U1631 ( .A0(n1501), .A1(n504), .B0(n565), .B1(n599), .C0(n905),
.Y(mult_x_55_n207) );
AOI22X1TS U1632 ( .A0(Op_MY[22]), .A1(n391), .B0(n448), .B1(n418), .Y(n906)
);
OAI221X1TS U1633 ( .A0(n1514), .A1(n447), .B0(n1423), .B1(n602), .C0(n906),
.Y(mult_x_23_n194) );
AOI22X1TS U1634 ( .A0(n544), .A1(n425), .B0(n782), .B1(n1341), .Y(n907) );
CMPR32X2TS U1635 ( .A(n910), .B(n909), .C(n908), .CO(n911), .S(n838) );
INVX2TS U1636 ( .A(n911), .Y(mult_x_23_n117) );
AOI22X1TS U1637 ( .A0(n1505), .A1(n1091), .B0(n510), .B1(n561), .Y(n912) );
AOI22X1TS U1638 ( .A0(n1512), .A1(n391), .B0(n448), .B1(n758), .Y(n913) );
OAI221X1TS U1639 ( .A0(n1511), .A1(n447), .B0(n1420), .B1(n602), .C0(n913),
.Y(mult_x_23_n197) );
INVX2TS U1640 ( .A(n433), .Y(n1146) );
AOI22X1TS U1641 ( .A0(n484), .A1(n502), .B0(n1360), .B1(n483), .Y(n914) );
OAI221X1TS U1642 ( .A0(n444), .A1(n455), .B0(n568), .B1(n1363), .C0(n914),
.Y(DP_OP_111J19_123_4462_n176) );
CMPR32X2TS U1643 ( .A(n917), .B(n916), .C(n915), .CO(n918), .S(n765) );
INVX2TS U1644 ( .A(n918), .Y(mult_x_55_n98) );
AOI22X1TS U1645 ( .A0(n541), .A1(n1017), .B0(n559), .B1(n540), .Y(n919) );
NAND2X1TS U1646 ( .A(n1501), .B(n428), .Y(n950) );
INVX2TS U1647 ( .A(n920), .Y(mult_x_55_n79) );
AOI22X1TS U1648 ( .A0(n542), .A1(n1348), .B0(n459), .B1(n1025), .Y(n921) );
OAI221X1TS U1649 ( .A0(n523), .A1(n1343), .B0(n496), .B1(n431), .C0(n921),
.Y(mult_x_55_n163) );
CMPR32X2TS U1650 ( .A(n924), .B(n923), .C(n922), .CO(n925), .S(n785) );
INVX2TS U1651 ( .A(n925), .Y(mult_x_55_n71) );
CMPR32X2TS U1652 ( .A(n928), .B(n927), .C(n926), .CO(n929), .S(n781) );
INVX2TS U1653 ( .A(n929), .Y(mult_x_23_n124) );
AOI22X1TS U1654 ( .A0(Op_MX[10]), .A1(n545), .B0(n659), .B1(n931), .Y(n930)
);
OAI221XLTS U1655 ( .A0(n931), .A1(Op_MX[10]), .B0(n659), .B1(n1418), .C0(
n930), .Y(n932) );
OAI221X1TS U1656 ( .A0(n1500), .A1(n1343), .B0(n439), .B1(n685), .C0(n932),
.Y(mult_x_55_n167) );
OAI22X1TS U1657 ( .A0(n532), .A1(n779), .B0(n1514), .B1(n1122), .Y(n933) );
AOI21X1TS U1658 ( .A0(n1136), .A1(n1397), .B0(n933), .Y(n1319) );
AOI21X1TS U1659 ( .A0(n464), .A1(n527), .B0(n461), .Y(n1320) );
NOR2X1TS U1660 ( .A(n1319), .B(n1320), .Y(mult_x_23_n119) );
INVX2TS U1661 ( .A(n763), .Y(n1334) );
INVX2TS U1662 ( .A(n934), .Y(mult_x_55_n212) );
NOR2X1TS U1663 ( .A(n570), .B(n659), .Y(mult_x_55_n149) );
OAI22X1TS U1664 ( .A0(n1506), .A1(n1087), .B0(n518), .B1(n1086), .Y(n935) );
AOI21X1TS U1665 ( .A0(n1089), .A1(Op_MY[9]), .B0(n935), .Y(n1337) );
AOI21X1TS U1666 ( .A0(n507), .A1(n1418), .B0(n936), .Y(n1338) );
NOR2X1TS U1667 ( .A(n1337), .B(n1338), .Y(mult_x_55_n119) );
INVX2TS U1668 ( .A(n779), .Y(n997) );
AOI22X1TS U1669 ( .A0(n778), .A1(n417), .B0(n997), .B1(n1423), .Y(n937) );
OAI21X1TS U1670 ( .A0(n531), .A1(n1122), .B0(n937), .Y(mult_x_23_n222) );
AOI22X1TS U1671 ( .A0(n1136), .A1(n558), .B0(n997), .B1(n422), .Y(n938) );
OAI21X1TS U1672 ( .A0(n1511), .A1(n1122), .B0(n938), .Y(mult_x_23_n226) );
AOI22X1TS U1673 ( .A0(n1501), .A1(n1348), .B0(n460), .B1(n528), .Y(n939) );
OAI221X1TS U1674 ( .A0(n539), .A1(n1343), .B0(n538), .B1(n431), .C0(n939),
.Y(mult_x_55_n165) );
OAI221X1TS U1675 ( .A0(n1417), .A1(n440), .B0(n438), .B1(n457), .C0(n396),
.Y(mult_x_55_n170) );
AOI22X1TS U1676 ( .A0(n670), .A1(n721), .B0(n1073), .B1(n570), .Y(n940) );
OAI21X1TS U1677 ( .A0(n721), .A1(n593), .B0(n940), .Y(mult_x_55_n228) );
AOI22X1TS U1678 ( .A0(Op_MY[13]), .A1(n1147), .B0(n468), .B1(n548), .Y(n941)
);
CMPR32X2TS U1679 ( .A(n1373), .B(n943), .C(n942), .CO(n944), .S(n853) );
INVX2TS U1680 ( .A(n944), .Y(DP_OP_111J19_123_4462_n83) );
NOR2X1TS U1681 ( .A(n496), .B(n606), .Y(mult_x_55_n151) );
AOI22X1TS U1682 ( .A0(n1508), .A1(n1147), .B0(n468), .B1(n1421), .Y(n945) );
CMPR32X2TS U1683 ( .A(n948), .B(n947), .C(n946), .CO(n949), .S(n789) );
INVX2TS U1684 ( .A(n949), .Y(mult_x_55_n124) );
CMPR32X2TS U1685 ( .A(n952), .B(n951), .C(n950), .CO(n920), .S(n953) );
INVX2TS U1686 ( .A(n953), .Y(mult_x_55_n80) );
AOI22X1TS U1687 ( .A0(n1501), .A1(n425), .B0(n782), .B1(n528), .Y(n954) );
AOI22X1TS U1688 ( .A0(n482), .A1(n450), .B0(n589), .B1(n576), .Y(n955) );
AOI22X1TS U1689 ( .A0(n547), .A1(n604), .B0(n471), .B1(n546), .Y(n956) );
INVX2TS U1690 ( .A(n957), .Y(mult_x_23_n80) );
AOI22X1TS U1691 ( .A0(n1500), .A1(n425), .B0(n782), .B1(n439), .Y(n958) );
AOI22X1TS U1692 ( .A0(n1106), .A1(intadd_52_SUM_8_), .B0(n682), .B1(n574),
.Y(n959) );
OAI21X1TS U1693 ( .A0(n482), .A1(n579), .B0(n959), .Y(
DP_OP_111J19_123_4462_n249) );
AOI22X1TS U1694 ( .A0(n486), .A1(n508), .B0(n1367), .B1(n522), .Y(n960) );
OAI221X1TS U1695 ( .A0(n488), .A1(n1369), .B0(n487), .B1(n465), .C0(n960),
.Y(DP_OP_111J19_123_4462_n227) );
AOI22X1TS U1696 ( .A0(n1089), .A1(n1504), .B0(n1073), .B1(n496), .Y(n961) );
OAI21X1TS U1697 ( .A0(n1504), .A1(n593), .B0(n961), .Y(mult_x_55_n232) );
AOI22X1TS U1698 ( .A0(n680), .A1(intadd_52_SUM_6_), .B0(n682), .B1(n575),
.Y(n962) );
OAI21X1TS U1699 ( .A0(intadd_52_SUM_6_), .A1(n579), .B0(n962), .Y(
DP_OP_111J19_123_4462_n251) );
CMPR32X2TS U1700 ( .A(n1421), .B(n392), .C(n963), .CO(n964), .S(n957) );
INVX2TS U1701 ( .A(n964), .Y(mult_x_23_n79) );
INVX2TS U1702 ( .A(n651), .Y(n1072) );
INVX2TS U1703 ( .A(DP_OP_111J19_123_4462_n42), .Y(DP_OP_111J19_123_4462_n41)
);
AOI22X1TS U1704 ( .A0(intadd_52_SUM_5_), .A1(n502), .B0(n1360), .B1(n575),
.Y(n965) );
OAI221X1TS U1705 ( .A0(n480), .A1(n1363), .B0(n479), .B1(n454), .C0(n965),
.Y(DP_OP_111J19_123_4462_n180) );
CMPR32X2TS U1706 ( .A(n968), .B(n967), .C(n966), .CO(n840), .S(n969) );
INVX2TS U1707 ( .A(n969), .Y(DP_OP_111J19_123_4462_n137) );
AOI22X1TS U1708 ( .A0(n1513), .A1(n1325), .B0(n463), .B1(mult_x_23_n38), .Y(
n970) );
OAI221X1TS U1709 ( .A0(n1512), .A1(n462), .B0(n403), .B1(n597), .C0(n970),
.Y(mult_x_23_n168) );
INVX2TS U1710 ( .A(n1369), .Y(n1109) );
AOI221X1TS U1711 ( .A0(n519), .A1(n508), .B0(n497), .B1(n1367), .C0(n1109),
.Y(n971) );
INVX2TS U1712 ( .A(n971), .Y(DP_OP_111J19_123_4462_n216) );
AOI22X1TS U1713 ( .A0(n514), .A1(n643), .B0(n1364), .B1(n513), .Y(n972) );
NOR2X1TS U1714 ( .A(n973), .B(n535), .Y(DP_OP_111J19_123_4462_n172) );
AOI22X1TS U1715 ( .A0(n680), .A1(intadd_52_SUM_9_), .B0(n682), .B1(n576),
.Y(n974) );
OAI21X1TS U1716 ( .A0(intadd_52_SUM_9_), .A1(n579), .B0(n974), .Y(
DP_OP_111J19_123_4462_n248) );
AOI22X1TS U1717 ( .A0(n390), .A1(n502), .B0(n1360), .B1(n574), .Y(n975) );
OAI221X1TS U1718 ( .A0(n482), .A1(n1363), .B0(n481), .B1(n454), .C0(n975),
.Y(DP_OP_111J19_123_4462_n178) );
AOI22X1TS U1719 ( .A0(n516), .A1(n502), .B0(n1360), .B1(n515), .Y(n976) );
OAI221X1TS U1720 ( .A0(n490), .A1(n1363), .B0(n489), .B1(n454), .C0(n976),
.Y(DP_OP_111J19_123_4462_n182) );
CMPR32X2TS U1721 ( .A(n979), .B(n978), .C(n977), .CO(n983), .S(n980) );
INVX2TS U1722 ( .A(n980), .Y(DP_OP_111J19_123_4462_n111) );
CMPR32X2TS U1723 ( .A(n983), .B(n982), .C(n981), .CO(n984), .S(n848) );
INVX2TS U1724 ( .A(n984), .Y(DP_OP_111J19_123_4462_n102) );
AOI22X1TS U1725 ( .A0(n514), .A1(n503), .B0(n1360), .B1(n564), .Y(n985) );
OAI221X1TS U1726 ( .A0(n516), .A1(n1363), .B0(n515), .B1(n454), .C0(n985),
.Y(DP_OP_111J19_123_4462_n183) );
CMPR32X2TS U1727 ( .A(n1373), .B(n987), .C(n986), .CO(n988), .S(n860) );
INVX2TS U1728 ( .A(n988), .Y(DP_OP_111J19_123_4462_n93) );
AOI22X1TS U1729 ( .A0(n1513), .A1(n391), .B0(n449), .B1(mult_x_23_n38), .Y(
n989) );
OAI221X1TS U1730 ( .A0(n1512), .A1(n447), .B0(n546), .B1(n601), .C0(n989),
.Y(mult_x_23_n196) );
AOI22X1TS U1731 ( .A0(Op_MY[16]), .A1(n434), .B0(n1142), .B1(mult_x_23_n64),
.Y(n990) );
AOI22X1TS U1732 ( .A0(n1511), .A1(n1325), .B0(n463), .B1(n1420), .Y(n991) );
AOI22X1TS U1733 ( .A0(n1512), .A1(n1147), .B0(n468), .B1(n546), .Y(n992) );
AOI22X1TS U1734 ( .A0(n521), .A1(n391), .B0(n449), .B1(n421), .Y(n993) );
OAI221X1TS U1735 ( .A0(n1510), .A1(n645), .B0(mult_x_23_n64), .B1(n602),
.C0(n993), .Y(mult_x_23_n199) );
AOI22X1TS U1736 ( .A0(n521), .A1(n1147), .B0(n468), .B1(n422), .Y(n994) );
INVX2TS U1737 ( .A(mult_x_55_n38), .Y(mult_x_55_n37) );
AOI22X1TS U1738 ( .A0(n1510), .A1(n1147), .B0(n469), .B1(mult_x_23_n64), .Y(
n995) );
AOI22X1TS U1739 ( .A0(n547), .A1(n577), .B0(n463), .B1(n546), .Y(n996) );
OAI221X1TS U1740 ( .A0(Op_MY[18]), .A1(n462), .B0(n1420), .B1(n597), .C0(
n996), .Y(mult_x_23_n169) );
AOI21X1TS U1741 ( .A0(Op_MX[22]), .A1(Op_MX[21]), .B0(n1409), .Y(n998) );
AOI21X1TS U1742 ( .A0(n998), .A1(n527), .B0(n1409), .Y(n1317) );
AOI21X1TS U1743 ( .A0(n997), .A1(n419), .B0(n1136), .Y(n1318) );
NOR2X1TS U1744 ( .A(n1317), .B(n1318), .Y(mult_x_23_n106) );
INVX2TS U1745 ( .A(n998), .Y(n1328) );
NOR2X1TS U1746 ( .A(n526), .B(n566), .Y(mult_x_23_n162) );
NOR2X1TS U1747 ( .A(n526), .B(n999), .Y(mult_x_23_n190) );
AOI22X1TS U1748 ( .A0(n1506), .A1(n1348), .B0(n460), .B1(n1062), .Y(n1000)
);
OAI221X1TS U1749 ( .A0(n518), .A1(n1343), .B0(n569), .B1(n431), .C0(n1000),
.Y(mult_x_55_n159) );
AOI22X1TS U1750 ( .A0(n1513), .A1(n434), .B0(n1142), .B1(mult_x_23_n38), .Y(
n1001) );
OAI221X1TS U1751 ( .A0(n1514), .A1(n467), .B0(n1423), .B1(n437), .C0(n1001),
.Y(mult_x_23_n209) );
AOI22X1TS U1752 ( .A0(n1505), .A1(n1348), .B0(n460), .B1(n540), .Y(n1002) );
OAI221X1TS U1753 ( .A0(n1506), .A1(n1343), .B0(n1062), .B1(n431), .C0(n1002),
.Y(mult_x_55_n160) );
AOI22X1TS U1754 ( .A0(n533), .A1(n391), .B0(n449), .B1(mult_x_23_n64), .Y(
n1003) );
OAI221X1TS U1755 ( .A0(n1509), .A1(n645), .B0(n1422), .B1(n601), .C0(n1003),
.Y(mult_x_23_n200) );
INVX2TS U1756 ( .A(mult_x_55_n64), .Y(mult_x_55_n63) );
AOI22X1TS U1757 ( .A0(intadd_52_SUM_8_), .A1(n643), .B0(n1364), .B1(n576),
.Y(n1004) );
AOI22X1TS U1758 ( .A0(n486), .A1(n643), .B0(n1364), .B1(n522), .Y(n1005) );
AOI22X1TS U1759 ( .A0(n541), .A1(n426), .B0(n782), .B1(n540), .Y(n1006) );
AOI22X1TS U1760 ( .A0(n1505), .A1(n429), .B0(n506), .B1(n540), .Y(n1007) );
OAI221X1TS U1761 ( .A0(n1504), .A1(n440), .B0(n1341), .B1(n457), .C0(n1007),
.Y(mult_x_55_n175) );
INVX2TS U1762 ( .A(n648), .Y(n1008) );
OAI221X1TS U1763 ( .A0(n497), .A1(n1372), .B0(n519), .B1(n493), .C0(n1008),
.Y(DP_OP_111J19_123_4462_n231) );
OAI22X1TS U1764 ( .A0(n552), .A1(n1087), .B0(n1417), .B1(n1086), .Y(n1009)
);
AOI21X1TS U1765 ( .A0(n1089), .A1(n550), .B0(n1009), .Y(n1335) );
AOI21X1TS U1766 ( .A0(n1347), .A1(n545), .B0(n460), .Y(n1336) );
NOR2X1TS U1767 ( .A(n1335), .B(n1336), .Y(mult_x_55_n106) );
AOI22X1TS U1768 ( .A0(intadd_52_SUM_2_), .A1(n500), .B0(n1071), .B1(n564),
.Y(n1010) );
AOI22X1TS U1769 ( .A0(n390), .A1(n500), .B0(n1071), .B1(n574), .Y(n1011) );
INVX2TS U1770 ( .A(DP_OP_111J19_123_4462_n67), .Y(DP_OP_111J19_123_4462_n68)
);
AOI22X1TS U1771 ( .A0(n516), .A1(n450), .B0(n589), .B1(n563), .Y(n1012) );
AOI22X1TS U1772 ( .A0(intadd_52_SUM_8_), .A1(n508), .B0(n1367), .B1(n576),
.Y(n1013) );
OAI221X1TS U1773 ( .A0(n484), .A1(n1369), .B0(n572), .B1(n465), .C0(n1013),
.Y(DP_OP_111J19_123_4462_n219) );
AOI22X1TS U1774 ( .A0(n517), .A1(n500), .B0(n1071), .B1(n563), .Y(n1014) );
AOI22X1TS U1775 ( .A0(Op_MY[4]), .A1(n426), .B0(n782), .B1(n1025), .Y(n1015)
);
AOI22X1TS U1776 ( .A0(n1503), .A1(n426), .B0(n782), .B1(n496), .Y(n1016) );
AOI22X1TS U1777 ( .A0(n523), .A1(n424), .B0(n581), .B1(n496), .Y(n1019) );
OAI221X1TS U1778 ( .A0(Op_MY[4]), .A1(n504), .B0(n1025), .B1(n600), .C0(
n1019), .Y(mult_x_55_n205) );
AOI22X1TS U1779 ( .A0(n680), .A1(n519), .B0(n682), .B1(n445), .Y(n1020) );
OAI21X1TS U1780 ( .A0(n1104), .A1(n520), .B0(n1020), .Y(
DP_OP_111J19_123_4462_n246) );
AOI22X1TS U1781 ( .A0(n542), .A1(n424), .B0(n581), .B1(n1025), .Y(n1021) );
OAI221X1TS U1782 ( .A0(n1502), .A1(n505), .B0(n538), .B1(n599), .C0(n1021),
.Y(mult_x_55_n206) );
AOI22X1TS U1783 ( .A0(intadd_52_SUM_0_), .A1(n501), .B0(n1071), .B1(n522),
.Y(n1022) );
NOR2X1TS U1784 ( .A(n1418), .B(n1023), .Y(mult_x_55_n196) );
AOI22X1TS U1785 ( .A0(n543), .A1(n1091), .B0(n510), .B1(n1062), .Y(n1024) );
AOI22X1TS U1786 ( .A0(Op_MY[4]), .A1(n1091), .B0(n511), .B1(n1025), .Y(n1026) );
AOI22X1TS U1787 ( .A0(n490), .A1(n508), .B0(n1367), .B1(n571), .Y(n1027) );
OAI221X1TS U1788 ( .A0(n492), .A1(n1369), .B0(n491), .B1(n465), .C0(n1027),
.Y(DP_OP_111J19_123_4462_n223) );
AOI22X1TS U1789 ( .A0(n1504), .A1(n430), .B0(n507), .B1(n1341), .Y(n1028) );
AOI22X1TS U1790 ( .A0(n1506), .A1(n424), .B0(n581), .B1(n1062), .Y(n1029) );
OAI221X1TS U1791 ( .A0(n541), .A1(n505), .B0(n561), .B1(n600), .C0(n1029),
.Y(mult_x_55_n202) );
NOR2BX1TS U1792 ( .AN(P_Sgf[47]), .B(n1389), .Y(n1035) );
NAND2X1TS U1793 ( .A(n1031), .B(n1030), .Y(n1438) );
INVX2TS U1794 ( .A(n1217), .Y(n1214) );
NAND2X1TS U1795 ( .A(n1309), .B(Add_result[0]), .Y(n1034) );
INVX2TS U1796 ( .A(n1438), .Y(n1437) );
INVX2TS U1797 ( .A(n1035), .Y(n1036) );
OAI31X1TS U1798 ( .A0(n1217), .A1(n1437), .A2(n1482), .B0(n1036), .Y(n309)
);
OAI32X1TS U1799 ( .A0(n1472), .A1(n1038), .A2(overflow_flag), .B0(n1441),
.B1(n1490), .Y(n263) );
NOR2BX1TS U1800 ( .AN(n1039), .B(Sgf_operation_EVEN1_Q_left[14]), .Y(n1040)
);
INVX2TS U1801 ( .A(P_Sgf[38]), .Y(n1228) );
OAI32X1TS U1802 ( .A0(n1464), .A1(n1459), .A2(n1040), .B0(n1228), .B1(n1458),
.Y(n254) );
INVX2TS U1803 ( .A(intadd_47_SUM_1_), .Y(intadd_48_B_0_) );
INVX2TS U1804 ( .A(intadd_47_SUM_2_), .Y(intadd_48_B_1_) );
INVX2TS U1805 ( .A(intadd_47_SUM_3_), .Y(intadd_48_B_2_) );
INVX2TS U1806 ( .A(intadd_47_SUM_4_), .Y(intadd_48_B_3_) );
INVX2TS U1807 ( .A(intadd_47_SUM_5_), .Y(intadd_48_B_4_) );
INVX2TS U1808 ( .A(intadd_47_SUM_6_), .Y(intadd_48_B_5_) );
INVX2TS U1809 ( .A(intadd_47_SUM_7_), .Y(intadd_48_B_6_) );
INVX2TS U1810 ( .A(intadd_47_SUM_8_), .Y(intadd_48_B_7_) );
INVX2TS U1811 ( .A(intadd_47_SUM_9_), .Y(intadd_48_B_8_) );
INVX2TS U1812 ( .A(intadd_47_SUM_10_), .Y(intadd_48_B_9_) );
INVX2TS U1813 ( .A(intadd_47_SUM_11_), .Y(intadd_48_B_10_) );
INVX2TS U1814 ( .A(intadd_47_SUM_12_), .Y(intadd_48_B_11_) );
INVX2TS U1815 ( .A(intadd_47_SUM_13_), .Y(intadd_48_B_12_) );
INVX2TS U1816 ( .A(intadd_47_SUM_14_), .Y(intadd_48_B_13_) );
INVX2TS U1817 ( .A(intadd_47_SUM_15_), .Y(intadd_48_B_14_) );
INVX2TS U1818 ( .A(intadd_47_SUM_16_), .Y(intadd_48_B_15_) );
INVX2TS U1819 ( .A(intadd_47_SUM_17_), .Y(intadd_48_B_16_) );
INVX2TS U1820 ( .A(intadd_47_SUM_18_), .Y(intadd_48_B_17_) );
INVX2TS U1821 ( .A(intadd_47_SUM_19_), .Y(intadd_48_B_18_) );
INVX2TS U1822 ( .A(intadd_47_SUM_20_), .Y(intadd_48_B_19_) );
INVX2TS U1823 ( .A(intadd_47_SUM_21_), .Y(intadd_48_B_20_) );
INVX2TS U1824 ( .A(intadd_47_SUM_22_), .Y(intadd_48_B_21_) );
INVX2TS U1825 ( .A(intadd_47_SUM_23_), .Y(intadd_48_B_22_) );
INVX2TS U1826 ( .A(intadd_47_SUM_24_), .Y(intadd_48_B_23_) );
INVX2TS U1827 ( .A(Sgf_operation_EVEN1_Q_middle[0]), .Y(intadd_47_B_0_) );
INVX2TS U1828 ( .A(Sgf_operation_EVEN1_Q_left[1]), .Y(n1385) );
NOR2X1TS U1829 ( .A(n1385), .B(Sgf_operation_EVEN1_Q_middle[1]), .Y(
intadd_47_A_2_) );
INVX2TS U1830 ( .A(Sgf_operation_EVEN1_Q_middle[24]), .Y(intadd_47_A_24_) );
INVX2TS U1831 ( .A(n1041), .Y(n1042) );
OAI21X2TS U1832 ( .A0(n1043), .A1(n1042), .B0(FS_Module_state_reg[1]), .Y(
n1190) );
INVX2TS U1833 ( .A(n1044), .Y(n1045) );
NAND2X1TS U1834 ( .A(n1190), .B(n1251), .Y(n1048) );
INVX2TS U1835 ( .A(n1251), .Y(n1279) );
AOI22X1TS U1836 ( .A0(n1195), .A1(Sgf_normalized_result[15]), .B0(
Add_result[15]), .B1(n1226), .Y(n1049) );
OAI2BB1X1TS U1837 ( .A0N(P_Sgf[39]), .A1N(n555), .B0(n1049), .Y(n1050) );
AOI21X1TS U1838 ( .A0(n1194), .A1(Add_result[16]), .B0(n1050), .Y(n1051) );
INVX2TS U1839 ( .A(n1251), .Y(n1195) );
AOI22X1TS U1840 ( .A0(n1195), .A1(Sgf_normalized_result[21]), .B0(
Add_result[21]), .B1(n1226), .Y(n1052) );
OAI2BB1X1TS U1841 ( .A0N(P_Sgf[45]), .A1N(n555), .B0(n1052), .Y(n1053) );
AOI21X1TS U1842 ( .A0(n1194), .A1(Add_result[22]), .B0(n1053), .Y(n1054) );
AOI22X1TS U1843 ( .A0(n1304), .A1(Sgf_normalized_result[19]), .B0(
Add_result[19]), .B1(n1226), .Y(n1055) );
OAI2BB1X1TS U1844 ( .A0N(P_Sgf[43]), .A1N(n555), .B0(n1055), .Y(n1056) );
AOI21X1TS U1845 ( .A0(n1194), .A1(Add_result[20]), .B0(n1056), .Y(n1057) );
INVX2TS U1846 ( .A(P_Sgf[40]), .Y(n1456) );
AOI22X1TS U1847 ( .A0(n1304), .A1(Sgf_normalized_result[17]), .B0(
Add_result[17]), .B1(n1226), .Y(n1058) );
OAI2BB1X1TS U1848 ( .A0N(P_Sgf[41]), .A1N(n556), .B0(n1058), .Y(n1059) );
AOI21X1TS U1849 ( .A0(n1194), .A1(Add_result[18]), .B0(n1059), .Y(n1060) );
INVX2TS U1850 ( .A(n631), .Y(n1390) );
OAI21XLTS U1851 ( .A0(n1479), .A1(n1388), .B0(FS_Module_state_reg[3]), .Y(
n1061) );
AOI22X1TS U1852 ( .A0(n1506), .A1(n430), .B0(n507), .B1(n1062), .Y(n1063) );
OAI221X1TS U1853 ( .A0(n541), .A1(n440), .B0(n561), .B1(n457), .C0(n1063),
.Y(mult_x_55_n174) );
AOI22X1TS U1854 ( .A0(n1500), .A1(n592), .B0(n460), .B1(n439), .Y(n1064) );
OAI221X1TS U1855 ( .A0(n529), .A1(n1343), .B0(n565), .B1(n685), .C0(n1064),
.Y(mult_x_55_n166) );
AOI22X1TS U1856 ( .A0(intadd_52_SUM_6_), .A1(n503), .B0(n1360), .B1(n567),
.Y(n1065) );
OAI221X1TS U1857 ( .A0(n390), .A1(n1363), .B0(n478), .B1(n455), .C0(n1065),
.Y(DP_OP_111J19_123_4462_n179) );
AOI22X1TS U1858 ( .A0(intadd_52_SUM_8_), .A1(n503), .B0(n587), .B1(n576),
.Y(n1066) );
OAI221X1TS U1859 ( .A0(n484), .A1(n1363), .B0(n572), .B1(n455), .C0(n1066),
.Y(DP_OP_111J19_123_4462_n177) );
AOI22X1TS U1860 ( .A0(intadd_52_SUM_4_), .A1(n503), .B0(n587), .B1(n571),
.Y(n1067) );
OAI221X1TS U1861 ( .A0(n492), .A1(n594), .B0(n491), .B1(n455), .C0(n1067),
.Y(DP_OP_111J19_123_4462_n181) );
CLKAND2X2TS U1862 ( .A(n1068), .B(n1361), .Y(DP_OP_111J19_123_4462_n214) );
AO21XLTS U1863 ( .A0(n535), .A1(n1069), .B0(n586), .Y(
DP_OP_111J19_123_4462_n156) );
CLKAND2X2TS U1864 ( .A(n1070), .B(n1361), .Y(DP_OP_111J19_123_4462_n200) );
AO21XLTS U1865 ( .A0(n535), .A1(n1072), .B0(n585), .Y(
DP_OP_111J19_123_4462_n155) );
NAND2BXLTS U1866 ( .AN(n449), .B(n602), .Y(mult_x_23_n192) );
AOI22X1TS U1867 ( .A0(n1089), .A1(Op_MY[2]), .B0(n1073), .B1(n439), .Y(n1074) );
OAI21X1TS U1868 ( .A0(n1501), .A1(n593), .B0(n1074), .Y(n1077) );
OAI2BB1X1TS U1869 ( .A0N(n1076), .A1N(n1092), .B0(n1075), .Y(n1078) );
NAND2X1TS U1870 ( .A(n1077), .B(n1078), .Y(intadd_50_CI) );
OA21XLTS U1871 ( .A0(n1078), .A1(n1077), .B0(intadd_50_CI), .Y(
Sgf_operation_EVEN1_right_N2) );
INVX2TS U1872 ( .A(DP_OP_111J19_123_4462_n35), .Y(n1080) );
AOI22X1TS U1873 ( .A0(n973), .A1(n572), .B0(n445), .B1(n660), .Y(n1375) );
CMPR32X2TS U1874 ( .A(n1080), .B(n1079), .C(n1375), .CO(intadd_49_A_21_),
.S(intadd_49_B_20_) );
AO21XLTS U1875 ( .A0(n1082), .A1(n1081), .B0(mult_x_55_n136), .Y(
intadd_50_B_2_) );
AOI22X1TS U1876 ( .A0(n1092), .A1(n600), .B0(n505), .B1(n1418), .Y(n1083) );
AOI22X1TS U1877 ( .A0(n1502), .A1(n432), .B0(n763), .B1(n538), .Y(n1085) );
OAI22X1TS U1878 ( .A0(n539), .A1(n1087), .B0(Op_MY[4]), .B1(n1086), .Y(n1088) );
AOI21X1TS U1879 ( .A0(n1089), .A1(Op_MY[4]), .B0(n1088), .Y(n1099) );
AOI22X1TS U1880 ( .A0(n1501), .A1(n762), .B0(n763), .B1(n528), .Y(n1090) );
NAND2BXLTS U1881 ( .AN(n1093), .B(n1092), .Y(n1097) );
CMPR32X2TS U1882 ( .A(n1096), .B(n1095), .C(n1094), .CO(intadd_50_B_3_), .S(
intadd_50_A_2_) );
CMPR32X2TS U1883 ( .A(n1099), .B(n1098), .C(n1097), .CO(n1094), .S(
intadd_50_B_1_) );
AO21XLTS U1884 ( .A0(n1101), .A1(n1100), .B0(DP_OP_111J19_123_4462_n148),
.Y(intadd_49_B_2_) );
AOI22X1TS U1885 ( .A0(n486), .A1(n466), .B0(n596), .B1(n522), .Y(n1102) );
OAI22X1TS U1886 ( .A0(n517), .A1(n1104), .B0(n514), .B1(n1103), .Y(n1105) );
AOI21X1TS U1887 ( .A0(n680), .A1(n517), .B0(n1105), .Y(n1115) );
AOI22X1TS U1888 ( .A0(intadd_52_SUM_0_), .A1(n1372), .B0(n494), .B1(n522),
.Y(n1107) );
NAND2X1TS U1889 ( .A(n1361), .B(n1108), .Y(n1113) );
AOI21X1TS U1890 ( .A0(n1109), .A1(n534), .B0(n1367), .Y(n1110) );
CMPR32X2TS U1891 ( .A(n1112), .B(n1111), .C(n1110), .CO(intadd_49_B_3_), .S(
intadd_49_A_2_) );
CMPR32X2TS U1892 ( .A(n1115), .B(n1114), .C(n1113), .CO(n1111), .S(
intadd_49_B_1_) );
NAND2X1TS U1893 ( .A(n1516), .B(n1116), .Y(mult_x_55_n211) );
AO21XLTS U1894 ( .A0(n1118), .A1(n1117), .B0(mult_x_23_n136), .Y(
intadd_51_B_2_) );
AOI22X1TS U1895 ( .A0(n562), .A1(n601), .B0(n447), .B1(n527), .Y(n1120) );
AOI221X1TS U1896 ( .A0(n391), .A1(Op_MY[13]), .B0(n448), .B1(n427), .C0(
n1120), .Y(n1128) );
AOI22X1TS U1897 ( .A0(n530), .A1(n774), .B0(n775), .B1(n1422), .Y(n1121) );
AOI221X1TS U1898 ( .A0(n433), .A1(n1508), .B0(n436), .B1(n524), .C0(n1121),
.Y(n1127) );
OAI22X1TS U1899 ( .A0(n1509), .A1(n779), .B0(n1510), .B1(n1122), .Y(n1123)
);
AOI21X1TS U1900 ( .A0(n1136), .A1(n533), .B0(n1123), .Y(n1131) );
AOI22X1TS U1901 ( .A0(n1508), .A1(n437), .B0(n775), .B1(n1421), .Y(n1124) );
AOI221X1TS U1902 ( .A0(n433), .A1(n392), .B0(n436), .B1(n394), .C0(n1124),
.Y(n1130) );
NAND2BXLTS U1903 ( .AN(n1125), .B(Op_MY[12]), .Y(n1129) );
CMPR32X2TS U1904 ( .A(n1128), .B(n1127), .C(n1126), .CO(intadd_51_B_3_), .S(
intadd_51_A_2_) );
CMPR32X2TS U1905 ( .A(n1131), .B(n1130), .C(n1129), .CO(n1126), .S(
intadd_51_B_1_) );
AOI22X1TS U1906 ( .A0(n1508), .A1(n1136), .B0(n1145), .B1(n524), .Y(n1132)
);
OAI21X1TS U1907 ( .A0(n392), .A1(n779), .B0(n1132), .Y(n1134) );
OAI211X1TS U1908 ( .A0(n1475), .A1(n548), .B0(Op_MX[13]), .C0(n527), .Y(
n1137) );
OAI2BB1X1TS U1909 ( .A0N(n1133), .A1N(n1324), .B0(n1137), .Y(n1135) );
NAND2X1TS U1910 ( .A(n1134), .B(n1135), .Y(intadd_51_CI) );
OA21XLTS U1911 ( .A0(n1135), .A1(n1134), .B0(intadd_51_CI), .Y(
Sgf_operation_EVEN1_left_N2) );
NOR2XLTS U1912 ( .A(Sgf_operation_EVEN1_left_N0), .B(mult_x_23_n219), .Y(
n1138) );
OA21XLTS U1913 ( .A0(n1138), .A1(n605), .B0(n1137), .Y(
Sgf_operation_EVEN1_left_N1) );
NAND2X1TS U1914 ( .A(n1519), .B(n1139), .Y(mult_x_55_n169) );
INVX2TS U1915 ( .A(n1325), .Y(n1140) );
AOI22X1TS U1916 ( .A0(n1397), .A1(n434), .B0(n773), .B1(n1423), .Y(n1143) );
NAND2X1TS U1917 ( .A(n467), .B(n1146), .Y(mult_x_23_n206) );
NAND2BXLTS U1918 ( .AN(n464), .B(n598), .Y(mult_x_23_n164) );
AOI22X1TS U1919 ( .A0(n1397), .A1(n1147), .B0(n469), .B1(n1423), .Y(n1148)
);
CMPR32X2TS U1920 ( .A(n392), .B(n530), .C(n1150), .CO(mult_x_23_n71), .S(
mult_x_23_n72) );
INVX2TS U1921 ( .A(Sgf_operation_EVEN1_Q_middle[2]), .Y(n1151) );
CMPR32X2TS U1922 ( .A(Sgf_operation_Result[2]), .B(n1151), .C(
Sgf_operation_EVEN1_Q_left[2]), .CO(intadd_47_B_3_), .S(intadd_47_B_2_) );
INVX2TS U1923 ( .A(Sgf_operation_EVEN1_Q_middle[3]), .Y(n1152) );
CMPR32X2TS U1924 ( .A(Sgf_operation_Result[3]), .B(n1152), .C(
Sgf_operation_EVEN1_Q_left[3]), .CO(intadd_47_B_4_), .S(intadd_47_A_3_) );
INVX2TS U1925 ( .A(Sgf_operation_EVEN1_Q_middle[4]), .Y(n1153) );
CMPR32X2TS U1926 ( .A(Sgf_operation_Result[4]), .B(n1153), .C(
Sgf_operation_EVEN1_Q_left[4]), .CO(intadd_47_B_5_), .S(intadd_47_A_4_) );
INVX2TS U1927 ( .A(Sgf_operation_EVEN1_Q_middle[5]), .Y(n1154) );
CMPR32X2TS U1928 ( .A(Sgf_operation_Result[5]), .B(n1154), .C(
Sgf_operation_EVEN1_Q_left[5]), .CO(intadd_47_B_6_), .S(intadd_47_A_5_) );
INVX2TS U1929 ( .A(Sgf_operation_EVEN1_Q_middle[6]), .Y(n1155) );
CMPR32X2TS U1930 ( .A(Sgf_operation_Result[6]), .B(n1155), .C(
Sgf_operation_EVEN1_Q_left[6]), .CO(intadd_47_B_7_), .S(intadd_47_A_6_) );
INVX2TS U1931 ( .A(Sgf_operation_EVEN1_Q_middle[7]), .Y(n1156) );
CMPR32X2TS U1932 ( .A(Sgf_operation_Result[7]), .B(n1156), .C(
Sgf_operation_EVEN1_Q_left[7]), .CO(intadd_47_B_8_), .S(intadd_47_A_7_) );
INVX2TS U1933 ( .A(Sgf_operation_EVEN1_Q_middle[8]), .Y(n1157) );
CMPR32X2TS U1934 ( .A(Sgf_operation_Result[8]), .B(n1157), .C(
Sgf_operation_EVEN1_Q_left[8]), .CO(intadd_47_B_9_), .S(intadd_47_A_8_) );
INVX2TS U1935 ( .A(Sgf_operation_EVEN1_Q_middle[9]), .Y(n1158) );
CMPR32X2TS U1936 ( .A(Sgf_operation_Result[9]), .B(n1158), .C(
Sgf_operation_EVEN1_Q_left[9]), .CO(intadd_47_B_10_), .S(
intadd_47_A_9_) );
INVX2TS U1937 ( .A(Sgf_operation_EVEN1_Q_middle[10]), .Y(n1159) );
CMPR32X2TS U1938 ( .A(Sgf_operation_Result[10]), .B(n1159), .C(
Sgf_operation_EVEN1_Q_left[10]), .CO(intadd_47_B_11_), .S(
intadd_47_A_10_) );
INVX2TS U1939 ( .A(Sgf_operation_EVEN1_Q_middle[11]), .Y(n1160) );
CMPR32X2TS U1940 ( .A(Sgf_operation_Result[11]), .B(n1160), .C(
Sgf_operation_EVEN1_Q_left[11]), .CO(intadd_47_B_12_), .S(
intadd_47_A_11_) );
INVX2TS U1941 ( .A(Sgf_operation_EVEN1_Q_middle[12]), .Y(n1161) );
CMPR32X2TS U1942 ( .A(n1161), .B(Sgf_operation_EVEN1_Q_right[12]), .C(
Sgf_operation_EVEN1_Q_left[12]), .CO(intadd_47_B_13_), .S(
intadd_47_A_12_) );
INVX2TS U1943 ( .A(Sgf_operation_EVEN1_Q_middle[13]), .Y(n1162) );
CMPR32X2TS U1944 ( .A(n1162), .B(Sgf_operation_EVEN1_Q_right[13]), .C(
Sgf_operation_EVEN1_Q_left[13]), .CO(intadd_47_B_14_), .S(
intadd_47_A_13_) );
INVX2TS U1945 ( .A(Sgf_operation_EVEN1_Q_middle[14]), .Y(n1163) );
CMPR32X2TS U1946 ( .A(n1163), .B(Sgf_operation_EVEN1_Q_right[14]), .C(
Sgf_operation_EVEN1_Q_left[14]), .CO(intadd_47_B_15_), .S(
intadd_47_A_14_) );
INVX2TS U1947 ( .A(Sgf_operation_EVEN1_Q_middle[15]), .Y(n1164) );
CMPR32X2TS U1948 ( .A(n1164), .B(Sgf_operation_EVEN1_Q_right[15]), .C(
Sgf_operation_EVEN1_Q_left[15]), .CO(intadd_47_B_16_), .S(
intadd_47_A_15_) );
INVX2TS U1949 ( .A(Sgf_operation_EVEN1_Q_middle[16]), .Y(n1165) );
CMPR32X2TS U1950 ( .A(n1165), .B(Sgf_operation_EVEN1_Q_right[16]), .C(
Sgf_operation_EVEN1_Q_left[16]), .CO(intadd_47_B_17_), .S(
intadd_47_A_16_) );
INVX2TS U1951 ( .A(Sgf_operation_EVEN1_Q_middle[17]), .Y(n1166) );
CMPR32X2TS U1952 ( .A(n1166), .B(Sgf_operation_EVEN1_Q_right[17]), .C(
Sgf_operation_EVEN1_Q_left[17]), .CO(intadd_47_B_18_), .S(
intadd_47_A_17_) );
INVX2TS U1953 ( .A(Sgf_operation_EVEN1_Q_middle[18]), .Y(n1167) );
CMPR32X2TS U1954 ( .A(n1167), .B(Sgf_operation_EVEN1_Q_right[18]), .C(
Sgf_operation_EVEN1_Q_left[18]), .CO(intadd_47_B_19_), .S(
intadd_47_A_18_) );
INVX2TS U1955 ( .A(Sgf_operation_EVEN1_Q_middle[19]), .Y(n1168) );
CMPR32X2TS U1956 ( .A(n1168), .B(Sgf_operation_EVEN1_Q_right[19]), .C(
Sgf_operation_EVEN1_Q_left[19]), .CO(intadd_47_B_20_), .S(
intadd_47_A_19_) );
INVX2TS U1957 ( .A(Sgf_operation_EVEN1_Q_middle[20]), .Y(n1169) );
CMPR32X2TS U1958 ( .A(n1169), .B(Sgf_operation_EVEN1_Q_right[20]), .C(
Sgf_operation_EVEN1_Q_left[20]), .CO(intadd_47_B_21_), .S(
intadd_47_A_20_) );
INVX2TS U1959 ( .A(Sgf_operation_EVEN1_Q_middle[21]), .Y(n1170) );
CMPR32X2TS U1960 ( .A(n1170), .B(Sgf_operation_EVEN1_Q_right[21]), .C(
Sgf_operation_EVEN1_Q_left[21]), .CO(intadd_47_B_22_), .S(
intadd_47_A_21_) );
INVX2TS U1961 ( .A(Sgf_operation_EVEN1_Q_middle[22]), .Y(n1171) );
CMPR32X2TS U1962 ( .A(n1171), .B(Sgf_operation_EVEN1_Q_right[22]), .C(
Sgf_operation_EVEN1_Q_left[22]), .CO(intadd_47_B_23_), .S(
intadd_47_A_22_) );
INVX2TS U1963 ( .A(Sgf_operation_EVEN1_Q_middle[23]), .Y(n1172) );
CMPR32X2TS U1964 ( .A(n1172), .B(Sgf_operation_EVEN1_Q_left[23]), .C(
Sgf_operation_EVEN1_Q_right[23]), .CO(intadd_47_B_24_), .S(
intadd_47_A_23_) );
NOR3BX1TS U1965 ( .AN(Op_MY[30]), .B(FSM_selector_B[0]), .C(
FSM_selector_B[1]), .Y(n1173) );
XOR2X1TS U1966 ( .A(n631), .B(n1173), .Y(DP_OP_36J19_124_9196_n15) );
OR2X2TS U1967 ( .A(FSM_selector_B[1]), .B(n1476), .Y(n1180) );
OAI2BB1X1TS U1968 ( .A0N(Op_MY[29]), .A1N(n1482), .B0(n1180), .Y(n1174) );
XOR2X1TS U1969 ( .A(n578), .B(n1174), .Y(DP_OP_36J19_124_9196_n16) );
OAI2BB1X1TS U1970 ( .A0N(Op_MY[28]), .A1N(n1482), .B0(n1180), .Y(n1175) );
XOR2X1TS U1971 ( .A(n631), .B(n1175), .Y(DP_OP_36J19_124_9196_n17) );
XOR2X1TS U1972 ( .A(n578), .B(n1176), .Y(DP_OP_36J19_124_9196_n18) );
XOR2X1TS U1973 ( .A(n631), .B(n1177), .Y(DP_OP_36J19_124_9196_n19) );
XOR2X1TS U1974 ( .A(n578), .B(n1178), .Y(DP_OP_36J19_124_9196_n20) );
XOR2X1TS U1975 ( .A(n631), .B(n1179), .Y(DP_OP_36J19_124_9196_n21) );
XOR2X1TS U1976 ( .A(n631), .B(n1182), .Y(DP_OP_36J19_124_9196_n22) );
NAND2X1TS U1977 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n1184) );
NAND2X1TS U1978 ( .A(Sgf_normalized_result[5]), .B(Sgf_normalized_result[4]),
.Y(n1266) );
NOR2X1TS U1979 ( .A(n1474), .B(n1478), .Y(n1248) );
NAND2X1TS U1980 ( .A(n1248), .B(Sgf_normalized_result[10]), .Y(n1187) );
MXI2X1TS U1981 ( .A(P_Sgf[46]), .B(Add_result[23]), .S0(FSM_selector_C), .Y(
n1189) );
AOI21X1TS U1982 ( .A0(n1190), .A1(n1189), .B0(n1195), .Y(n1191) );
AHHCINX2TS U1983 ( .A(Sgf_normalized_result[22]), .CIN(n1192), .S(n1193),
.CO(n1308) );
AOI22X1TS U1984 ( .A0(n1279), .A1(Sgf_normalized_result[22]), .B0(
Add_result[22]), .B1(n476), .Y(n1196) );
OAI2BB1X1TS U1985 ( .A0N(P_Sgf[46]), .A1N(n556), .B0(n1196), .Y(n1197) );
AOI21X1TS U1986 ( .A0(Add_result[23]), .A1(n473), .B0(n1197), .Y(n1198) );
OAI2BB1X1TS U1987 ( .A0N(n553), .A1N(P_Sgf[45]), .B0(n1198), .Y(n214) );
AHHCONX2TS U1988 ( .A(Sgf_normalized_result[21]), .CI(n1199), .CON(n1192),
.S(n1200) );
AHHCINX2TS U1989 ( .A(Sgf_normalized_result[20]), .CIN(n1201), .S(n1202),
.CO(n1199) );
INVX2TS U1990 ( .A(n555), .Y(n1229) );
AOI22X1TS U1991 ( .A0(n1279), .A1(Sgf_normalized_result[20]), .B0(
Add_result[20]), .B1(n1226), .Y(n1203) );
AOI21X1TS U1992 ( .A0(n474), .A1(Add_result[21]), .B0(n1204), .Y(n1205) );
OAI2BB1X1TS U1993 ( .A0N(n553), .A1N(P_Sgf[43]), .B0(n1205), .Y(n212) );
AHHCONX2TS U1994 ( .A(Sgf_normalized_result[19]), .CI(n1206), .CON(n1201),
.S(n1207) );
AHHCINX2TS U1995 ( .A(Sgf_normalized_result[18]), .CIN(n1208), .S(n1209),
.CO(n1206) );
AOI22X1TS U1996 ( .A0(n1279), .A1(Sgf_normalized_result[18]), .B0(
Add_result[18]), .B1(n1226), .Y(n1210) );
AOI21X1TS U1997 ( .A0(n474), .A1(Add_result[19]), .B0(n1211), .Y(n1212) );
OAI2BB1X1TS U1998 ( .A0N(n554), .A1N(P_Sgf[41]), .B0(n1212), .Y(n210) );
AHHCONX2TS U1999 ( .A(Sgf_normalized_result[17]), .CI(n1213), .CON(n1208),
.S(n1215) );
AHHCINX2TS U2000 ( .A(Sgf_normalized_result[16]), .CIN(n1216), .S(n1218),
.CO(n1213) );
AOI22X1TS U2001 ( .A0(n1279), .A1(Sgf_normalized_result[16]), .B0(
Add_result[16]), .B1(n477), .Y(n1219) );
AOI21X1TS U2002 ( .A0(n474), .A1(Add_result[17]), .B0(n1220), .Y(n1221) );
OAI2BB1X1TS U2003 ( .A0N(n553), .A1N(P_Sgf[39]), .B0(n1221), .Y(n208) );
AHHCONX2TS U2004 ( .A(Sgf_normalized_result[15]), .CI(n1222), .CON(n1216),
.S(n1223) );
AHHCINX2TS U2005 ( .A(Sgf_normalized_result[14]), .CIN(n1224), .S(n1225),
.CO(n1222) );
AOI22X1TS U2006 ( .A0(n1304), .A1(Sgf_normalized_result[14]), .B0(
Add_result[14]), .B1(n476), .Y(n1227) );
AOI21X1TS U2007 ( .A0(n474), .A1(Add_result[15]), .B0(n1230), .Y(n1231) );
OAI2BB1X1TS U2008 ( .A0N(n554), .A1N(P_Sgf[37]), .B0(n1231), .Y(n206) );
AHHCONX2TS U2009 ( .A(Sgf_normalized_result[13]), .CI(n1232), .CON(n1224),
.S(n1233) );
AOI22X1TS U2010 ( .A0(n1279), .A1(Sgf_normalized_result[13]), .B0(
Add_result[13]), .B1(n476), .Y(n1234) );
OAI2BB1X1TS U2011 ( .A0N(P_Sgf[37]), .A1N(n556), .B0(n1234), .Y(n1235) );
AOI21X1TS U2012 ( .A0(n473), .A1(Add_result[14]), .B0(n1235), .Y(n1236) );
OAI2BB1X1TS U2013 ( .A0N(n554), .A1N(P_Sgf[36]), .B0(n1236), .Y(n205) );
AHHCINX2TS U2014 ( .A(Sgf_normalized_result[12]), .CIN(n1237), .S(n1238),
.CO(n1232) );
AOI22X1TS U2015 ( .A0(n1195), .A1(Sgf_normalized_result[12]), .B0(
Add_result[12]), .B1(n477), .Y(n1239) );
OAI2BB1X1TS U2016 ( .A0N(P_Sgf[36]), .A1N(n555), .B0(n1239), .Y(n1240) );
AOI21X1TS U2017 ( .A0(n473), .A1(Add_result[13]), .B0(n1240), .Y(n1241) );
OAI2BB1X1TS U2018 ( .A0N(n554), .A1N(P_Sgf[35]), .B0(n1241), .Y(n204) );
AHHCONX2TS U2019 ( .A(Sgf_normalized_result[11]), .CI(n1242), .CON(n1237),
.S(n1243) );
AOI22X1TS U2020 ( .A0(n1304), .A1(Sgf_normalized_result[11]), .B0(
Add_result[11]), .B1(n477), .Y(n1244) );
OAI2BB1X1TS U2021 ( .A0N(P_Sgf[35]), .A1N(n556), .B0(n1244), .Y(n1245) );
AOI21X1TS U2022 ( .A0(n473), .A1(Add_result[12]), .B0(n1245), .Y(n1246) );
OAI2BB1X1TS U2023 ( .A0N(n554), .A1N(P_Sgf[34]), .B0(n1246), .Y(n203) );
NAND2X1TS U2024 ( .A(n1260), .B(n1248), .Y(n1249) );
INVX2TS U2025 ( .A(n1251), .Y(n1304) );
AOI22X1TS U2026 ( .A0(n1195), .A1(Sgf_normalized_result[10]), .B0(
Add_result[10]), .B1(n477), .Y(n1252) );
OAI2BB1X1TS U2027 ( .A0N(P_Sgf[34]), .A1N(n555), .B0(n1252), .Y(n1253) );
AOI21X1TS U2028 ( .A0(n473), .A1(Add_result[11]), .B0(n1253), .Y(n1254) );
OAI2BB1X1TS U2029 ( .A0N(n554), .A1N(P_Sgf[33]), .B0(n1254), .Y(n202) );
NAND2X1TS U2030 ( .A(n1260), .B(Sgf_normalized_result[8]), .Y(n1255) );
AOI22X1TS U2031 ( .A0(n1304), .A1(Sgf_normalized_result[9]), .B0(
Add_result[9]), .B1(n477), .Y(n1257) );
OAI2BB1X1TS U2032 ( .A0N(P_Sgf[33]), .A1N(n556), .B0(n1257), .Y(n1258) );
AOI21X1TS U2033 ( .A0(n474), .A1(Add_result[10]), .B0(n1258), .Y(n1259) );
OAI2BB1X1TS U2034 ( .A0N(n553), .A1N(P_Sgf[32]), .B0(n1259), .Y(n201) );
XNOR2X1TS U2035 ( .A(n1260), .B(n1474), .Y(n1261) );
AOI22X1TS U2036 ( .A0(n1279), .A1(Sgf_normalized_result[8]), .B0(
Add_result[8]), .B1(n476), .Y(n1262) );
OAI2BB1X1TS U2037 ( .A0N(P_Sgf[32]), .A1N(n555), .B0(n1262), .Y(n1263) );
AOI21X1TS U2038 ( .A0(n473), .A1(Add_result[9]), .B0(n1263), .Y(n1264) );
OAI2BB1X1TS U2039 ( .A0N(n554), .A1N(P_Sgf[31]), .B0(n1264), .Y(n200) );
OAI21X1TS U2040 ( .A0(n1283), .A1(n1480), .B0(n1266), .Y(n1272) );
NAND2X1TS U2041 ( .A(n1272), .B(Sgf_normalized_result[6]), .Y(n1267) );
AOI22X1TS U2042 ( .A0(n1195), .A1(Sgf_normalized_result[7]), .B0(
Add_result[7]), .B1(n477), .Y(n1269) );
OAI2BB1X1TS U2043 ( .A0N(P_Sgf[31]), .A1N(n556), .B0(n1269), .Y(n1270) );
AOI21X1TS U2044 ( .A0(n1194), .A1(Add_result[8]), .B0(n1270), .Y(n1271) );
OAI2BB1X1TS U2045 ( .A0N(n553), .A1N(P_Sgf[30]), .B0(n1271), .Y(n199) );
XNOR2X1TS U2046 ( .A(n1272), .B(n1486), .Y(n1273) );
AOI22X1TS U2047 ( .A0(n1304), .A1(Sgf_normalized_result[6]), .B0(
Add_result[6]), .B1(n477), .Y(n1274) );
OAI2BB1X1TS U2048 ( .A0N(P_Sgf[30]), .A1N(n555), .B0(n1274), .Y(n1275) );
AOI21X1TS U2049 ( .A0(n474), .A1(Add_result[7]), .B0(n1275), .Y(n1276) );
OAI2BB1X1TS U2050 ( .A0N(n554), .A1N(P_Sgf[29]), .B0(n1276), .Y(n198) );
NAND2X1TS U2051 ( .A(n1283), .B(n1485), .Y(n1277) );
XNOR2X1TS U2052 ( .A(n1277), .B(n1480), .Y(n1278) );
AOI22X1TS U2053 ( .A0(n1279), .A1(Sgf_normalized_result[5]), .B0(
Add_result[5]), .B1(n476), .Y(n1280) );
OAI2BB1X1TS U2054 ( .A0N(P_Sgf[29]), .A1N(n556), .B0(n1280), .Y(n1281) );
AOI21X1TS U2055 ( .A0(n473), .A1(Add_result[6]), .B0(n1281), .Y(n1282) );
OAI2BB1X1TS U2056 ( .A0N(n553), .A1N(P_Sgf[28]), .B0(n1282), .Y(n197) );
AOI22X1TS U2057 ( .A0(n1279), .A1(Sgf_normalized_result[4]), .B0(
Add_result[4]), .B1(n476), .Y(n1285) );
OAI2BB1X1TS U2058 ( .A0N(P_Sgf[28]), .A1N(n555), .B0(n1285), .Y(n1286) );
AOI21X1TS U2059 ( .A0(n474), .A1(Add_result[5]), .B0(n1286), .Y(n1287) );
OAI2BB1X1TS U2060 ( .A0N(n554), .A1N(P_Sgf[27]), .B0(n1287), .Y(n196) );
AOI22X1TS U2061 ( .A0(n1195), .A1(Sgf_normalized_result[3]), .B0(
Add_result[3]), .B1(n477), .Y(n1292) );
OAI2BB1X1TS U2062 ( .A0N(P_Sgf[27]), .A1N(n556), .B0(n1292), .Y(n1293) );
AOI21X1TS U2063 ( .A0(n1194), .A1(Add_result[4]), .B0(n1293), .Y(n1294) );
OAI2BB1X1TS U2064 ( .A0N(n553), .A1N(P_Sgf[26]), .B0(n1294), .Y(n195) );
AOI22X1TS U2065 ( .A0(n1195), .A1(Sgf_normalized_result[2]), .B0(n477), .B1(
Add_result[2]), .Y(n1297) );
OAI2BB1X1TS U2066 ( .A0N(P_Sgf[26]), .A1N(n556), .B0(n1297), .Y(n1298) );
AOI21X1TS U2067 ( .A0(n473), .A1(Add_result[3]), .B0(n1298), .Y(n1299) );
OAI2BB1X1TS U2068 ( .A0N(n553), .A1N(P_Sgf[25]), .B0(n1299), .Y(n194) );
XNOR2X1TS U2069 ( .A(Sgf_normalized_result[0]), .B(Sgf_normalized_result[1]),
.Y(n1300) );
AOI22X1TS U2070 ( .A0(n1304), .A1(Sgf_normalized_result[1]), .B0(n476), .B1(
Add_result[1]), .Y(n1301) );
OAI2BB1X1TS U2071 ( .A0N(P_Sgf[25]), .A1N(n555), .B0(n1301), .Y(n1302) );
AOI21X1TS U2072 ( .A0(n474), .A1(Add_result[2]), .B0(n1302), .Y(n1303) );
OAI2BB1X1TS U2073 ( .A0N(n554), .A1N(P_Sgf[24]), .B0(n1303), .Y(n193) );
AOI22X1TS U2074 ( .A0(n1304), .A1(Sgf_normalized_result[0]), .B0(n476), .B1(
Add_result[0]), .Y(n1305) );
OAI2BB1X1TS U2075 ( .A0N(P_Sgf[24]), .A1N(n556), .B0(n1305), .Y(n1306) );
AOI21X1TS U2076 ( .A0(n473), .A1(Add_result[1]), .B0(n1306), .Y(n1307) );
OAI2BB1X1TS U2077 ( .A0N(n553), .A1N(P_Sgf[23]), .B0(n1307), .Y(n192) );
ADDHXLTS U2078 ( .A(Sgf_normalized_result[23]), .B(n1308), .CO(n1310), .S(
n1188) );
CLKBUFX2TS U2079 ( .A(n1393), .Y(n1400) );
NAND2X1TS U2080 ( .A(n1438), .B(n1487), .Y(n376) );
NOR2BX1TS U2081 ( .AN(exp_oper_result[8]), .B(n1487), .Y(S_Oper_A_exp[8]) );
OAI22X1TS U2082 ( .A0(Exp_module_Data_S[8]), .A1(n1316), .B0(n1437), .B1(
n1491), .Y(n273) );
INVX2TS U2083 ( .A(n1469), .Y(n1468) );
OA21XLTS U2084 ( .A0(n775), .A1(n1324), .B0(n435), .Y(intadd_51_B_0_) );
AOI21X1TS U2085 ( .A0(n1318), .A1(n1317), .B0(mult_x_23_n106), .Y(
mult_x_23_n107) );
AOI21X1TS U2086 ( .A0(n1320), .A1(n1319), .B0(mult_x_23_n119), .Y(
mult_x_23_n120) );
AOI21X1TS U2087 ( .A0(n1322), .A1(n1321), .B0(mult_x_23_n129), .Y(
mult_x_23_n130) );
OAI22X1TS U2088 ( .A0(n417), .A1(n566), .B0(n1397), .B1(n560), .Y(
mult_x_23_n152) );
OAI22X1TS U2089 ( .A0(n1397), .A1(n1328), .B0(n1513), .B1(n560), .Y(
mult_x_23_n153) );
OAI22X1TS U2090 ( .A0(n532), .A1(n1328), .B0(n1512), .B1(n1323), .Y(
mult_x_23_n154) );
OAI22X1TS U2091 ( .A0(n1511), .A1(n1323), .B0(n1512), .B1(n566), .Y(
mult_x_23_n155) );
OAI22X1TS U2092 ( .A0(n558), .A1(n1328), .B0(n521), .B1(n560), .Y(
mult_x_23_n156) );
OAI22X1TS U2093 ( .A0(n521), .A1(n1328), .B0(n1510), .B1(n560), .Y(
mult_x_23_n157) );
OAI22X1TS U2094 ( .A0(n1510), .A1(n566), .B0(n1509), .B1(n1323), .Y(
mult_x_23_n158) );
OAI22X1TS U2095 ( .A0(n1508), .A1(n560), .B0(n1509), .B1(n566), .Y(
mult_x_23_n159) );
OAI22X1TS U2096 ( .A0(n392), .A1(n1323), .B0(n1508), .B1(n566), .Y(
mult_x_23_n160) );
OAI22X1TS U2097 ( .A0(Op_MY[13]), .A1(n566), .B0(n562), .B1(n560), .Y(
mult_x_23_n161) );
AOI22X1TS U2098 ( .A0(n525), .A1(n577), .B0(n464), .B1(n1421), .Y(n1326) );
OAI221XLTS U2099 ( .A0(n392), .A1(n700), .B0(n548), .B1(n597), .C0(n1326),
.Y(mult_x_23_n174) );
INVX2TS U2100 ( .A(mult_x_23_n31), .Y(n1329) );
NAND2X1TS U2101 ( .A(Op_MX[21]), .B(Op_MX[22]), .Y(n1332) );
CMPR32X2TS U2102 ( .A(n417), .B(n1329), .C(n1328), .CO(n1330), .S(
intadd_51_B_19_) );
XNOR2X1TS U2103 ( .A(n1330), .B(intadd_51_n1), .Y(n1331) );
XOR2XLTS U2104 ( .A(n1332), .B(n1331), .Y(n1333) );
XNOR2X1TS U2105 ( .A(n531), .B(n1333), .Y(Sgf_operation_EVEN1_left_N23) );
AOI21X1TS U2106 ( .A0(n1334), .A1(n1418), .B0(n511), .Y(intadd_50_B_0_) );
AOI21X1TS U2107 ( .A0(n1336), .A1(n1335), .B0(mult_x_55_n106), .Y(
mult_x_55_n107) );
AOI21X1TS U2108 ( .A0(n1338), .A1(n1337), .B0(mult_x_55_n119), .Y(
mult_x_55_n120) );
AOI21X1TS U2109 ( .A0(n1340), .A1(n1339), .B0(mult_x_55_n129), .Y(
mult_x_55_n130) );
AOI22X1TS U2110 ( .A0(n1504), .A1(n592), .B0(n460), .B1(n1341), .Y(n1342) );
OAI221XLTS U2111 ( .A0(n1505), .A1(n590), .B0(n540), .B1(n431), .C0(n1342),
.Y(mult_x_55_n161) );
AOI22X1TS U2112 ( .A0(n1501), .A1(n430), .B0(n507), .B1(n528), .Y(n1344) );
OAI221XLTS U2113 ( .A0(n1500), .A1(n441), .B0(n536), .B1(n458), .C0(n1344),
.Y(mult_x_55_n180) );
OAI221XLTS U2114 ( .A0(n550), .A1(n505), .B0(n637), .B1(n600), .C0(n1345),
.Y(mult_x_55_n198) );
INVX2TS U2115 ( .A(mult_x_55_n31), .Y(n1351) );
NOR2XLTS U2116 ( .A(n442), .B(n659), .Y(n1349) );
CMPR32X2TS U2117 ( .A(n1351), .B(n1350), .C(n1349), .CO(n1356), .S(
intadd_50_B_19_) );
AOI22X1TS U2118 ( .A0(n552), .A1(n550), .B0(n438), .B1(n442), .Y(n1353) );
OAI21XLTS U2119 ( .A0(n1354), .A1(n1353), .B0(n428), .Y(n1352) );
AOI21X1TS U2120 ( .A0(n1354), .A1(n1353), .B0(n1352), .Y(n1355) );
XOR2XLTS U2121 ( .A(n1356), .B(n1355), .Y(n1357) );
XNOR2X1TS U2122 ( .A(intadd_50_n1), .B(n1357), .Y(
Sgf_operation_EVEN1_right_N23) );
AOI21X1TS U2123 ( .A0(n589), .A1(n535), .B0(n1358), .Y(intadd_49_B_0_) );
AOI21X1TS U2124 ( .A0(n1359), .A1(n535), .B0(n587), .Y(intadd_49_B_8_) );
AOI22X1TS U2125 ( .A0(n973), .A1(n481), .B0(n572), .B1(n512), .Y(
DP_OP_111J19_123_4462_n162) );
AOI22X1TS U2126 ( .A0(n973), .A1(n478), .B0(n481), .B1(n660), .Y(
DP_OP_111J19_123_4462_n163) );
AOI22X1TS U2127 ( .A0(n1376), .A1(n479), .B0(n478), .B1(n512), .Y(
DP_OP_111J19_123_4462_n164) );
AOI22X1TS U2128 ( .A0(n973), .A1(n491), .B0(n479), .B1(n660), .Y(
DP_OP_111J19_123_4462_n165) );
AOI22X1TS U2129 ( .A0(n1376), .A1(n489), .B0(n491), .B1(n512), .Y(
DP_OP_111J19_123_4462_n166) );
AOI22X1TS U2130 ( .A0(n1376), .A1(n515), .B0(n489), .B1(n660), .Y(
DP_OP_111J19_123_4462_n167) );
AOI22X1TS U2131 ( .A0(n973), .A1(n513), .B0(n515), .B1(n512), .Y(
DP_OP_111J19_123_4462_n168) );
AOI22X1TS U2132 ( .A0(n1376), .A1(n487), .B0(n513), .B1(n660), .Y(
DP_OP_111J19_123_4462_n169) );
AOI22X1TS U2133 ( .A0(n973), .A1(n485), .B0(n487), .B1(n660), .Y(
DP_OP_111J19_123_4462_n170) );
AOI22X1TS U2134 ( .A0(n1376), .A1(n534), .B0(n485), .B1(n660), .Y(
DP_OP_111J19_123_4462_n171) );
AOI22X1TS U2135 ( .A0(n1361), .A1(n503), .B0(n587), .B1(n534), .Y(n1362) );
OAI221XLTS U2136 ( .A0(intadd_52_SUM_0_), .A1(n594), .B0(n522), .B1(n455),
.C0(n1362), .Y(DP_OP_111J19_123_4462_n186) );
AOI22X1TS U2137 ( .A0(n484), .A1(n643), .B0(n1364), .B1(n483), .Y(n1365) );
OAI221XLTS U2138 ( .A0(n445), .A1(n443), .B0(n399), .B1(n582), .C0(n1365),
.Y(DP_OP_111J19_123_4462_n203) );
AOI22X1TS U2139 ( .A0(n444), .A1(n1367), .B0(n509), .B1(n399), .Y(n1366) );
OAI221XLTS U2140 ( .A0(n498), .A1(n466), .B0(n520), .B1(n596), .C0(n1366),
.Y(DP_OP_111J19_123_4462_n217) );
AOI22X1TS U2141 ( .A0(intadd_52_SUM_9_), .A1(n509), .B0(n1367), .B1(n483),
.Y(n1368) );
OAI221XLTS U2142 ( .A0(n445), .A1(n466), .B0(n568), .B1(n596), .C0(n1368),
.Y(DP_OP_111J19_123_4462_n218) );
AOI22X1TS U2143 ( .A0(n497), .A1(n648), .B0(n451), .B1(n520), .Y(n1370) );
OAI221XLTS U2144 ( .A0(n445), .A1(n595), .B0(n568), .B1(n494), .C0(n1370),
.Y(DP_OP_111J19_123_4462_n232) );
AOI22X1TS U2145 ( .A0(n444), .A1(n648), .B0(n451), .B1(n399), .Y(n1371) );
OAI221XLTS U2146 ( .A0(intadd_52_SUM_9_), .A1(n494), .B0(n572), .B1(n595),
.C0(n1371), .Y(DP_OP_111J19_123_4462_n233) );
AOI21X1TS U2147 ( .A0(n1374), .A1(n520), .B0(n1373), .Y(
DP_OP_111J19_123_4462_n245) );
INVX2TS U2148 ( .A(n1375), .Y(n1381) );
AOI22X1TS U2149 ( .A0(n973), .A1(n568), .B0(n519), .B1(n512), .Y(n1380) );
CLKAND2X2TS U2150 ( .A(n1378), .B(n1377), .Y(n1379) );
CMPR32X2TS U2151 ( .A(n1381), .B(n1380), .C(n1379), .CO(n1383), .S(
intadd_49_B_21_) );
OAI21XLTS U2152 ( .A0(n498), .A1(n512), .B0(n1383), .Y(n1382) );
OAI31X1TS U2153 ( .A0(n497), .A1(n1383), .A2(n660), .B0(n1382), .Y(n1384) );
XNOR2X1TS U2154 ( .A(intadd_49_n1), .B(n1384), .Y(
Sgf_operation_EVEN1_middle_N25) );
AOI21X1TS U2155 ( .A0(Sgf_operation_EVEN1_Q_middle[1]), .A1(n1385), .B0(
intadd_47_A_2_), .Y(intadd_47_B_1_) );
INVX2TS U2156 ( .A(n1464), .Y(n1465) );
NAND2X1TS U2157 ( .A(n1444), .B(Sgf_operation_EVEN1_Q_left[22]), .Y(n1443)
);
XNOR2X1TS U2158 ( .A(Sgf_operation_EVEN1_Q_left[23]), .B(n1443), .Y(n1386)
);
AOI32X1TS U2159 ( .A0(FS_Module_state_reg[0]), .A1(n1479), .A2(
FS_Module_state_reg[1]), .B0(FS_Module_state_reg[2]), .B1(n1388), .Y(
n1391) );
BUFX3TS U2160 ( .A(n1393), .Y(n1398) );
INVX2TS U2161 ( .A(n1392), .Y(n1439) );
BUFX3TS U2162 ( .A(n1393), .Y(n1401) );
BUFX3TS U2163 ( .A(n1401), .Y(n1403) );
INVX2TS U2164 ( .A(n1400), .Y(n1399) );
INVX2TS U2165 ( .A(n1396), .Y(n1397) );
INVX2TS U2166 ( .A(n1400), .Y(n1402) );
NOR4X1TS U2167 ( .A(Op_MX[30]), .B(Op_MX[29]), .C(Op_MX[28]), .D(Op_MX[27]),
.Y(n1414) );
NOR4X1TS U2168 ( .A(Op_MX[12]), .B(Op_MX[8]), .C(Op_MX[10]), .D(n1519), .Y(
n1413) );
NOR4X1TS U2169 ( .A(n547), .B(Op_MY[29]), .C(Op_MY[28]), .D(n1416), .Y(n1431) );
NOR4X1TS U2170 ( .A(n544), .B(n543), .C(n552), .D(n1417), .Y(n1430) );
NOR4X1TS U2171 ( .A(n537), .B(Op_MY[23]), .C(Op_MY[30]), .D(n542), .Y(n1429)
);
NOR4X1TS U2172 ( .A(n1427), .B(n1426), .C(n1425), .D(n1424), .Y(n1428) );
OAI31X1TS U2173 ( .A0(n1435), .A1(n1434), .A2(n1433), .B0(n1432), .Y(n1436)
);
OA22X1TS U2174 ( .A0(n1466), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n1442), .Y(n271) );
OA22X1TS U2175 ( .A0(n1466), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n1442), .Y(n270) );
OA22X1TS U2176 ( .A0(n1441), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n1442), .Y(n269) );
OA22X1TS U2177 ( .A0(n1441), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n1442), .Y(n268) );
OA22X1TS U2178 ( .A0(n1441), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n1442), .Y(n267) );
OA22X1TS U2179 ( .A0(n1441), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n1442), .Y(n266) );
OA22X1TS U2180 ( .A0(n1441), .A1(final_result_ieee[29]), .B0(
exp_oper_result[6]), .B1(n1442), .Y(n265) );
OA22X1TS U2181 ( .A0(n1466), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n1442), .Y(n264) );
OAI2BB1X1TS U2182 ( .A0N(n1463), .A1N(P_Sgf[46]), .B0(n1445), .Y(n262) );
OAI21XLTS U2183 ( .A0(n1447), .A1(Sgf_operation_EVEN1_Q_left[20]), .B0(n1446), .Y(n1448) );
AOI22X1TS U2184 ( .A0(n1464), .A1(n1449), .B0(n1448), .B1(n1458), .Y(n260)
);
OAI21XLTS U2185 ( .A0(n1451), .A1(Sgf_operation_EVEN1_Q_left[18]), .B0(n1450), .Y(n1452) );
AOI22X1TS U2186 ( .A0(n1457), .A1(n1453), .B0(n1452), .B1(n1458), .Y(n258)
);
AOI22X1TS U2187 ( .A0(n1457), .A1(n1456), .B0(n1455), .B1(n1458), .Y(n256)
);
OAI2BB2XLTS U2188 ( .B0(n1461), .B1(n1460), .A0N(n753), .A1N(P_Sgf[39]), .Y(
n255) );
INVX2TS U2189 ( .A(n1466), .Y(n1467) );
INVX2TS U2190 ( .A(n1469), .Y(n1471) );
initial $sdf_annotate("FPU_Multiplication_Function_KOA_1STAGE_syn.sdf");
endmodule
|
/*
* NAME
* ----
*
* main.v - top most module
*
* DESCRIPTION
* -----------
*
* This module is the top most modules which is used
* to to wire all the different modules together and
* establish a bus.
*
* AUTHOR
* ------
*
* Jeremiah Mahler <[email protected]>
*
*/
`include "decoder.v"
`include "led_ctl.v"
`include "mem_ctl.v"
`include "spi_ctl.v"
`include "switch_ctl.v"
module main(
input sck,
nss,
mosi,
reset_n,
output miso,
output [16:0] mem_address,
inout [7:0] mem_data,
output mem1_ceh_n,
mem1_ce2,
mem1_we_n,
mem1_oe_n,
mem2_ceh_n,
mem2_ce2,
mem2_we_n,
mem2_oe_n,
output [7:0] board_leds,
bar_leds,
input [7:0] switches);
wire [6:0] address;
wire [7:0] data;
GSR GSR_INST(.GSR(reset_n));
wire bar_led_ce_n,
board_led_ce_n,
switch_ce_n,
mem1_ce_n,
mem2_ce_n;
decoder decoder1(address, bar_led_ce_n, board_led_ce_n, switch_ce_n,
mem1_ce_n, mem2_ce_n);
led_ctl board_leds1(read_n, write_n, reset_n, board_led_ce_n,
data, board_leds);
led_ctl bar_leds1(read_n, write_n, reset_n, bar_led_ce_n,
data, bar_leds);
spi_ctl spi1(nss, mosi, sck, miso, address, data, read_n, write_n);
switch_ctl sw1(read_n, switch_ce_n, data, switches);
mem_ctl mem1(read_n, write_n, mem1_ce_n, address, data,
mem_data, mem_address, mem1_ceh_n, mem1_ce2, mem1_we_n,
mem1_oe_n);
mem_ctl mem2(read_n, write_n, mem2_ce_n, address, data,
mem_data, mem_address, mem2_ceh_n, mem2_ce2, mem2_we_n,
mem2_oe_n);
endmodule
|
`define AND 0000
`define OR 4'b0001
`define ADD 4'b0010
`define SUB 4'b0110
`define SLT 4'b0111
`define NOR 4'b1100
`define AND_FUNCT 6'b100100
`define OR_FUNCT 6'b100101
`define ADD_FUNCT 6'b100000
`define SUB_FUNCT 6'b100010
`define SLT_FUNCT 6'b101010
`define NOR_FUNCT 6'b100111
`define SLL_FUNCT 6'b000000
`define LW 3'b000 //lw || sw || addi
`define BEQ 3'b001
`define ORI 3'b100
`define ANDI 3'b011
module alu_control (
input [5:0] funct,
input [2:0] alu_op,
output [3:0] aluctrl );
reg [3:0] funct_val;
reg [3:0] aluctrl_val;
always @(*) begin
case(funct)
`AND_FUNCT : funct_val = `AND;
`OR_FUNCT : funct_val = `OR ;
`ADD_FUNCT : funct_val = `ADD;
`SUB_FUNCT : funct_val = `SUB;
`SLT_FUNCT : funct_val = `SLT;
`NOR_FUNCT : funct_val = `NOR;
default: funct_val= 0;
endcase
end
always @(*) begin
aluctrl_val <= 0;
case (alu_op)
`LW : aluctrl_val <= 4'd2;//lw sw addi
`BEQ : aluctrl_val <= 4'd6;//branch
`ORI : aluctrl_val <= 4'd1;//ori
`ANDI: aluctrl_val <= 4'd0;//andi
3'd2 : aluctrl_val <= funct_val;//r type
default: aluctrl_val <= 0;
endcase
end
assign aluctrl = aluctrl_val;
endmodule
|
module var22_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7
+ R * 9'd7
+ S * 9'd29
+ T * 9'd23
+ U * 9'd24
+ V * 9'd3;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23
+ R * 9'd26
+ S * 9'd1
+ T * 9'd22
+ U * 9'd26
+ V * 9'd15;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30
+ R * 9'd12
+ S * 9'd28
+ T * 9'd13
+ U * 9'd18
+ V * 9'd16;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221OI_4_V
`define SKY130_FD_SC_LS__A221OI_4_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a221oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a221oi_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221OI_4_V
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MEMC
// / / Filename: mcb_traffic_gen.v
// /___/ /\ Date Last Modified: $Date:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Virtex7
//Design Name: s7ven_data_gen
//Purpose: This is top level module of memory traffic generator which can
// generate different CMD_PATTERN and DATA_PATTERN to Virtex 7
// hard memory controller core.
// Supported Data pattern: 0 : Reserved.
// 1 : FIXED_DATA_MODE.
// 2 : ADDR_DATA_MODE
// 3 : HAMMER_DATA_MODE
// 4 : NEIGHBOR_DATA_MODE
// 5 : WALKING1_DATA_MODE
// 6 : WALKING0_DATA_MODE
// 7 : TRUE_PRBS_MODE
//
//
//Reference:
//Revision History: 1.1
//*****************************************************************************
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
module s7ven_data_gen #
( parameter DMODE = "WRITE",
parameter nCK_PER_CLK = 2, // 2: Memc core speed 1/2 of memory clock speed.
// User data bus width = 4 x DQs data width.
// 4: memc core speed 1/4 of memory clock speed.
// User data bus width = 8 x DQs data width.
parameter MEM_TYPE = "DDR3",
parameter TCQ = 100,
parameter BL_WIDTH = 6, // USER_Interface Command Burst Length
parameter FAMILY = "SPARTAN6",
parameter EYE_TEST = "FALSE",
parameter ADDR_WIDTH = 32,
parameter MEM_BURST_LEN = 8,
parameter START_ADDR = 32'h00000000,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 72,
parameter COLUMN_WIDTH = 10,
parameter SEL_VICTIM_LINE = 3 // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
// parameter [287:0] ALL_1 = {288{1'b1}},
// parameter [287:0] ALL_0 = {288{1'b0}}
)
(
input clk_i, //
input rst_i,
input [31:0] prbs_fseed_i,
input mode_load_i,
input mem_init_done_i,
input wr_data_mask_gen_i,
input [3:0] data_mode_i, // "00" = bram;
input data_rdy_i,
input cmd_startA,
input cmd_startB,
input cmd_startC,
input cmd_startD,
input cmd_startE,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern.
input [31:0] fixed_data_i,
input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
input [BL_WIDTH:0] user_burst_cnt, // generated burst length for control the burst data
input fifo_rdy_i, // connect from mcb_wr_full when used as wr_data_gen
// connect from mcb_rd_empty when used as rd_data_gen
// When both data_rdy and data_valid is asserted, the ouput data is valid.
// input [(DWIDTH/8)-1:0] wr_mask_count;
output [(NUM_DQ_PINS*nCK_PER_CLK*2/8)-1:0] data_mask_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o , // generated data pattern
output bram_rd_valid_o
);
//
localparam PRBS_WIDTH = 8;//BL_WIDTH;
localparam TAPS_VALUE = (BL_WIDTH == 8) ? 8'b10001110 :
// (BL_WIDTH == 10) ? 10'b1000000100:
8'b10001110 ;
wire [31:0] prbs_data;
reg [35:0] acounts;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] fdata;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] bdata;
wire [31:0] bram_data;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] adata_tmp;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] adata;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] hammer_data;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w1data;
reg [NUM_DQ_PINS*2-1:0] hdata;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w0data;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data;
reg burst_count_reached2;
reg data_valid;
reg [2:0] walk_cnt;
reg [ADDR_WIDTH-1:0] user_address;
reg [ADDR_WIDTH-1:0] m_addr_r; // generated address used to determine data pattern.
reg sel_w1gen_logic;
//reg [7:0] BLANK;
reg [4*NUM_DQ_PINS -1 :0] sel_victimline_r;
reg data_clk_en,data_clk_en2;
wire [NUM_DQ_PINS*2*nCK_PER_CLK-1:0] full_prbs_data2;
wire [NUM_DQ_PINS*2*nCK_PER_CLK-1:0] psuedo_prbs_data;
reg [2*nCK_PER_CLK-1:0] prbs_mux_data;
reg [NUM_DQ_PINS*4-1:0] h_prbsdata;
wire [PRBS_WIDTH-1:0] prbs_seed;
reg [5:0] prbs_mux_counter;
reg [2*nCK_PER_CLK*16-1:0] prbs_comb_data;
reg prbs_seeded;
reg prbs_comb_data_load;
reg mode_has_loaded;
wire [127:0] prbs_shift_value;
reg next_calib_data;
reg [2*nCK_PER_CLK*NUM_DQ_PINS-1:0 ] calib_data;
wire [2*nCK_PER_CLK*NUM_DQ_PINS/8 -1:0] w1data_group;
wire [31:0] mcb_prbs_data;
wire [NUM_DQ_PINS-1:0] prbsdata_rising_0;
wire [NUM_DQ_PINS-1:0] prbsdata_falling_0;
wire [NUM_DQ_PINS-1:0] prbsdata_rising_1;
wire [NUM_DQ_PINS-1:0] prbsdata_falling_1;
wire [NUM_DQ_PINS-1:0] prbsdata_rising_2;
wire [NUM_DQ_PINS-1:0] prbsdata_falling_2;
wire [NUM_DQ_PINS-1:0] prbsdata_rising_3;
wire [NUM_DQ_PINS-1:0] prbsdata_falling_3 ;
wire [BL_WIDTH-1:0] prbs_o0,prbs_o1,prbs_o2,prbs_o3,prbs_o4,prbs_o5,prbs_o6,prbs_o7;
wire [BL_WIDTH-1:0] prbs_o8,prbs_o9,prbs_o10,prbs_o11,prbs_o12,prbs_o13,prbs_o14,prbs_o15;
wire [3:0] prbs_shift_value0,prbs_shift_value1,prbs_shift_value2,prbs_shift_value3,prbs_shift_value4;
wire [3:0] prbs_shift_value5,prbs_shift_value6,prbs_shift_value7,prbs_shift_value8,prbs_shift_value9;
wire [3:0] prbs_shift_value10,prbs_shift_value11,prbs_shift_value12,prbs_shift_value13,prbs_shift_value14;
wire [3:0] prbs_shift_value15;
wire [3:0] prbs_shift_value16,prbs_shift_value17,prbs_shift_value18,prbs_shift_value19,prbs_shift_value20;
wire [3:0] prbs_shift_value21,prbs_shift_value22,prbs_shift_value23,prbs_shift_value24,prbs_shift_value25;
wire [3:0] prbs_shift_value26,prbs_shift_value27,prbs_shift_value28,prbs_shift_value29,prbs_shift_value30;
wire [3:0] prbs_shift_value31;
//wire [nCK_PER_CLK * 32 -1 :0] prbs_shift_value;
wire [nCK_PER_CLK * 256 -1:0] ReSeedcounter;
reg mode_load_r1,mode_load_r2;
reg [3:0] htstpoint ;
reg data_clk_en2_r;
reg force_load;
reg [NUM_DQ_PINS-1:0] wdatamask_ripplecnt;
//wire [4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] ALL_1 =
reg mode_load_r;
reg user_burst_cnt_larger_1_r;
integer i,j,k;
localparam NUM_WIDTH = 2*nCK_PER_CLK*NUM_DQ_PINS;
localparam USER_BUS_DWIDTH = (nCK_PER_CLK == 2) ? NUM_DQ_PINS*4 : NUM_DQ_PINS*8;
//*********************************************************************************************
localparam BRAM_DATAL_MODE = 4'b0000;
localparam FIXED_DATA_MODE = 4'b0001;
localparam ADDR_DATA_MODE = 4'b0010;
localparam HAMMER_DATA_MODE = 4'b0011;
localparam NEIGHBOR_DATA_MODE = 4'b0100;
localparam WALKING1_DATA_MODE = 4'b0101;
localparam WALKING0_DATA_MODE = 4'b0110;
localparam PRBS_DATA_MODE = 4'b0111;
assign data_o = data;
generate
if (nCK_PER_CLK == 4)
begin: full_prbs_data64
//always @ (prbsdata_falling_3,prbsdata_rising_3,prbsdata_falling_2,prbsdata_rising_2,prbsdata_falling_1,prbsdata_rising_1,prbsdata_falling_0,prbsdata_rising_0)
assign full_prbs_data2 = {prbsdata_falling_3,prbsdata_rising_3,prbsdata_falling_2,prbsdata_rising_2,prbsdata_falling_1,prbsdata_rising_1,prbsdata_falling_0,prbsdata_rising_0};
end
else
begin: full_prbs_data32
assign full_prbs_data2 = {prbsdata_falling_1,prbsdata_rising_1,prbsdata_falling_0,prbsdata_rising_0};
end
endgenerate
generate
genvar p;
for (p = 0; p < NUM_DQ_PINS*nCK_PER_CLK*2/32; p = p+1)
begin
assign psuedo_prbs_data[p*32+31:p*32] = mcb_prbs_data;
end
endgenerate
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w1data_o;
reg [3:0] data_mode_rr_a;
reg [3:0] data_mode_rr_c;
// write data mask generation.
// Only support data pattern = address data mode.
// When wdatamask_ripple_cnt is asserted, the corresponding wr_data word will be jammed with 8'hff.
assign data_mask_o = (wr_data_mask_gen_i == 1'b1 && mem_init_done_i) ? wdatamask_ripplecnt :{ NUM_DQ_PINS*nCK_PER_CLK*2/8{1'b0}};
always @ (posedge clk_i)
begin
if (rst_i || ~wr_data_mask_gen_i || ~mem_init_done_i)
wdatamask_ripplecnt <= 'b0;
else if (cmd_startA)
//wdatamask_ripplecnt <= {15'd0,1'b1};
wdatamask_ripplecnt <= {{NUM_DQ_PINS-1{1'b0}},1'b1};
else if (user_burst_cnt_larger_1_r && data_rdy_i)
wdatamask_ripplecnt <= {wdatamask_ripplecnt[NUM_DQ_PINS-2:0],wdatamask_ripplecnt[NUM_DQ_PINS-1]};
end
generate
genvar n;
for (n = 0; n < NUM_DQ_PINS*nCK_PER_CLK*2/8; n = n+1)
begin
if (MEM_TYPE == "QDR2PLUS")
assign adata = adata_tmp;// QDR not supporting masking
else
assign adata[n*8+7:n*8] = adata_tmp[n*8+7:n*8]| {8{wdatamask_ripplecnt[NUM_DQ_PINS-1]}};
end
endgenerate
always @ (posedge clk_i)
begin
data_mode_rr_a <= #TCQ data_mode_i;
data_mode_rr_c <= #TCQ data_mode_i;
end
assign bdata = {USER_BUS_DWIDTH/32{bram_data[31:0]}};
// selected data pattern go through "data" mux to user data bus.
// 72 pin 1: failed
always @ (bdata,calib_data,hammer_data,adata,data_mode_rr_a,w1data,full_prbs_data2,psuedo_prbs_data)
begin
case(data_mode_rr_a) //
// Simple Data Pattern for bring up
// 0: Reserved
// 1: 32 bits fixed_data from user defined inputs.
// The data from this static pattern is concatenated together multiple times
// to make up the required number of bits as needed.
// 2: 32 bits address as data
// The data from this pattern is concatenated together multiple times
// to make up the required number of bits as needed.
// 4: simple 8data pattern and repeats every 8 words. The pattern is embedded in RAM.
// 5,6: Walkign 1,0 data.
// a Calibration data pattern
// 0,1,2,3,4,9: use bram to implemnt.
4'b0000,4'b0001,4'b0100,4'b1001: data = bdata;
4'b0010: data = adata; // address as data
4'b0011: data = hammer_data;
4'b0101, 4'b110: data = w1data; // walking 1 or walking 0 data
// when vio_instr_mode_value set to 4'hf,the init_mem_pattern_ctr module
// will automatically set the data_mode_o to 0x8
4'b1010: data =calib_data;
// Characterization Mode
// 2: Address as data
// 3: hammer data with option to select VICTIM line which output is always high.
// 7: Hammer PRBS. Only valid in V6,V7 family
// 9: Slow 2 MHz hammer pattern.
4'b0111: data = full_prbs_data2;//{prbs_data,prbs_data,prbs_data,prbs_data}; // "011" = prbs
4'b1000: data = psuedo_prbs_data;//{prbs_data,prbs_data,prbs_data,prbs_data}; // "011" = prbs
default : begin
// for (i=0; i <= 4*NUM_DQ_PINS - 1; i= i+1) begin: neighbor_data
// data = begin
// for (
data = adata;
end
endcase
end
// phy calibration data pattern
//
generate
if (nCK_PER_CLK == 2)
begin: calib_data32
always @ (posedge clk_i)
if (rst_i) begin
next_calib_data <= 1'b0;
calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}};
end
else if (cmd_startA)
begin
calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}};
next_calib_data <=#TCQ 1'b1;
// calib_data <= 'b0;
end
else if (fifo_rdy_i)
begin
next_calib_data <= #TCQ ~next_calib_data;
if (next_calib_data )
calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h66}},{(NUM_DQ_PINS/8){8'h99}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h55}}};
else
calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}};
end
end
else
begin: calib_data64 // when nCK_PER_LK =4 has not verified
always @ (posedge clk_i)
if (rst_i) begin
next_calib_data <= 1'b0;
calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}};
end
else if (cmd_startA)
begin
calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}};
next_calib_data <=#TCQ 1'b1;
// calib_data <= 'b0;
end
else if (fifo_rdy_i)
begin
next_calib_data <= #TCQ ~next_calib_data;
if (next_calib_data )
calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h6666}},{(NUM_DQ_PINS/8){16'h9999}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h5555}}};
else
calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}};
end
end
endgenerate
/*
always @ (posedge clk_i)
begin calib_data <= 'b0;
end
*/
//**************************************************************************
// Pattern bram generates fixed input, hammer, simple 8 repeat data pattern.
//**************************************************************************
function integer logb2;
input [31:0] number;
integer i;
begin
i = number;
for(logb2=1; i>0; logb2=logb2+1)
i = i >> 1;
end
endfunction
vio_init_pattern_bram #
( .MEM_BURST_LEN (MEM_BURST_LEN),
.START_ADDR (START_ADDR),
.NUM_DQ_PINS (NUM_DQ_PINS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE)
)
vio_init_pattern_bram
(
.clk_i (clk_i ),
.rst_i (rst_i ),
// BL8 : least 3 address bits are always zero.
// BL4 " least 2 address bits are always zero.
// for walking 1's or 0's, the least 8 address bits are always zero.
.cmd_addr (addr_i),
.cmd_start (cmd_startB),
.mode_load_i (mode_load_i),
.data_mode_i (data_mode_rr_a),
//.w1data (w1data),
.data0 (simple_data0 ),
.data1 (simple_data1 ),
.data2 (simple_data2 ),
.data3 (simple_data3 ),
.data4 (simple_data4 ),
.data5 (simple_data5 ),
.data6 (simple_data6 ),
.data7 (simple_data7 ),
.data8 (fixed_data_i ),
.bram_rd_valid_o (bram_rd_valid_o),
.bram_rd_rdy_i (user_burst_cnt_larger_1_r & (data_rdy_i | cmd_startB)),
.dout_o (bram_data)
);
//**************************************************************
// Functions to be used byg Walking 1 and Walking 0 circuits.
//**************************************************************
function [2*nCK_PER_CLK*NUM_DQ_PINS-1:0] Data_Gen (input integer i );
integer j;
begin
j = i/2;
Data_Gen = {2*nCK_PER_CLK*NUM_DQ_PINS{1'b0}};
if(i %2 == 1) begin
if (nCK_PER_CLK == 2) begin
Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000;
Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b01000000;
Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00100000;
Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b10000000;
end
else begin
Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000;
Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00100000;
Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b01000000;
Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b10000000;
Data_Gen[(4*NUM_DQ_PINS+j*8)+:8] = 8'b00000001;
Data_Gen[(5*NUM_DQ_PINS+j*8)+:8] = 8'b00000010;
Data_Gen[(6*NUM_DQ_PINS+j*8)+:8] = 8'b00000100;
Data_Gen[(7*NUM_DQ_PINS+j*8)+:8] = 8'b00001000;
end
end else begin
if (nCK_PER_CLK == 2) begin
Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001;
Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000010;
Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000100;
Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00001000;
end
else begin
Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001;
Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000010;
Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000100;
Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00001000;
Data_Gen[(4*NUM_DQ_PINS+j*8)+:8] = 8'b00010000;
Data_Gen[(5*NUM_DQ_PINS+j*8)+:8] = 8'b00100000;
Data_Gen[(6*NUM_DQ_PINS+j*8)+:8] = 8'b01000000;
Data_Gen[(7*NUM_DQ_PINS+j*8)+:8] = 8'b10000000;
end
end
end
endfunction
function [2*nCK_PER_CLK*NUM_DQ_PINS-1:0] Data_GenW0 (input integer i);
integer j;
begin
j = i/2;
Data_GenW0 = {2*nCK_PER_CLK*NUM_DQ_PINS{1'b1}};
if(i %2 == 1) begin
if (nCK_PER_CLK == 2) begin
Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11101111;
Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11011111;
Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b10111111;
Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b01111111;
end
else begin
Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11101111;
Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11011111;
Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b10111111;
Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b01111111;
Data_GenW0[(4*NUM_DQ_PINS+j*8)+:8] = 8'b11111110;
Data_GenW0[(5*NUM_DQ_PINS+j*8)+:8] = 8'b11111101;
Data_GenW0[(6*NUM_DQ_PINS+j*8)+:8] = 8'b11111011;
Data_GenW0[(7*NUM_DQ_PINS+j*8)+:8] = 8'b11110111;
end
end else begin
if (nCK_PER_CLK == 2) begin
Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11111110;
Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111101;
Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111011;
Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11110111;
end
else begin
Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11111110;
Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111101;
Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111011;
Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11110111;
Data_GenW0[(4*NUM_DQ_PINS+j*8)+:8] = 8'b11101111;
Data_GenW0[(5*NUM_DQ_PINS+j*8)+:8] = 8'b11011111;
Data_GenW0[(6*NUM_DQ_PINS+j*8)+:8] = 8'b10111111;
Data_GenW0[(7*NUM_DQ_PINS+j*8)+:8] = 8'b01111111;
end
end
end
endfunction
always @ (posedge clk_i) begin
if (data_mode_rr_c[2:0] == 3'b101 || data_mode_rr_c[2:0] == 3'b100 || data_mode_rr_c[2:0] == 3'b110) // WALKING ONES
sel_w1gen_logic <= #TCQ 1'b1;
else
sel_w1gen_logic <= #TCQ 1'b0;
end
generate
genvar m;
for (m=0; m < (2*nCK_PER_CLK*NUM_DQ_PINS/8) - 1; m= m+1)
begin: w1_gp
assign w1data_group[m] = ( (w1data[(m*8+7):m*8]) != 8'h00);
end
endgenerate
generate
if ((NUM_DQ_PINS == 8 ) &&(DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL"))
begin : WALKING_ONE_8_PATTERN
always @ (posedge clk_i) begin
if( (fifo_rdy_i ) || cmd_startC )
if (cmd_startC ) begin
if (sel_w1gen_logic) begin
if (data_mode_i == 4'b0101)
w1data <= #TCQ Data_Gen(32'b0);
else
w1data <= #TCQ Data_GenW0(32'b0);
end
end
else if ( MEM_BURST_LEN == 8 && fifo_rdy_i ) begin
if ( nCK_PER_CLK == 2)
begin
w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]};
w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]};
w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]};
w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]};
end
else begin
w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS] <= #TCQ w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS ];
w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS] <= #TCQ w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS ];
w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS] <= #TCQ w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS ];
w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS] <= #TCQ w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS ];
w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS ] ;
w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS ];
w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS ] ;
w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS ];
end
end
end
end
//endgenerate
//generate
else if ((NUM_DQ_PINS != 8 ) &&(DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL"))
begin : WALKING_ONE_64_PATTERN
always @ (posedge clk_i) begin
if( (fifo_rdy_i ) || cmd_startC )
if (cmd_startC ) begin
if (sel_w1gen_logic) begin
if (data_mode_i == 4'b0101)
w1data <= #TCQ Data_Gen(32'b0);
else
w1data <= #TCQ Data_GenW0(32'b0);
end
end
else if ( MEM_BURST_LEN == 8 && fifo_rdy_i ) begin
if ( nCK_PER_CLK == 2)
begin
w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]};
w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]};
w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]};
w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]};
end
else begin
w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS] <= #TCQ {w1data[8*NUM_DQ_PINS - 9:7*NUM_DQ_PINS ],w1data[8*NUM_DQ_PINS - 1:8*NUM_DQ_PINS - 8]};
w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS] <= #TCQ {w1data[7*NUM_DQ_PINS - 9:6*NUM_DQ_PINS ],w1data[7*NUM_DQ_PINS - 1:7*NUM_DQ_PINS - 8]};
w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS] <= #TCQ {w1data[6*NUM_DQ_PINS - 9:5*NUM_DQ_PINS ],w1data[6*NUM_DQ_PINS - 1:6*NUM_DQ_PINS - 8]};
w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS] <= #TCQ {w1data[5*NUM_DQ_PINS - 9:4*NUM_DQ_PINS ],w1data[5*NUM_DQ_PINS - 1:5*NUM_DQ_PINS - 8]};
w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 9:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 8]};
w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 9:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 8]};
w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 9:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 8]};
w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 9:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 8]};
end
end
end
end
else
begin: NO_WALKING_PATTERN
always @ (posedge clk_i)
w1data <= 'b0;
end
endgenerate
// HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine
// the position of the pin driving oppsite polarity
// addr_i[6:2] = 5'h0f ; 32 bit data port
// => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111
// => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
// Only generate NUM_DQ_PINS width of hdata and will do concatenation in above level.
always @ (posedge clk_i)
begin
for (i= 0; i <= 2*NUM_DQ_PINS - 1; i= i+1) //begin: hammer_data
if ( i >= NUM_DQ_PINS )
if (SEL_VICTIM_LINE == NUM_DQ_PINS)
hdata[i] <= 1'b0;
else if (
((i == SEL_VICTIM_LINE-1) ||
(i-NUM_DQ_PINS) == SEL_VICTIM_LINE ))//||
hdata[i] <= 1'b1;
else
hdata[i] <= 1'b0;
else
hdata[i] <= 1'b1;
end
generate
if (nCK_PER_CLK == 2)
begin : HAMMER_2
assign hammer_data = {2{hdata[2*NUM_DQ_PINS - 1:0]}};
end
else
begin : HAMMER_4
assign hammer_data = {4{hdata[2*NUM_DQ_PINS - 1:0]}};
end
endgenerate
// ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
// Dataport 32 bit width with starting addr_i = 32'h12345678, burst length 8
// => the 1st data pattern : 32'h12345680
// => the 2nd data pattern : 32'h12345688
// => the 3rd data pattern : 32'h12345690
// => the 4th data pattern : 32'h12345698
generate
reg COut_a;
if (DATA_PATTERN == "DGEN_ADDR" || DATA_PATTERN == "DGEN_ALL")
begin : ADDRESS_PATTERN
always @ (posedge clk_i)
begin
if (cmd_startD)
/// 35:0
acounts <= #TCQ {4'b0000,addr_i} ;
else if (user_burst_cnt_larger_1_r && data_rdy_i ) begin
if (nCK_PER_CLK == 2)
if (FAMILY == "VIRTEX6")
if (MEM_TYPE == "QDR2PLUS")
{COut_a,acounts} <= #TCQ acounts + 1;
else
{COut_a,acounts} <= #TCQ acounts + 4;
else begin // "SPARTAN6"
if (DWIDTH == 32)
{COut_a,acounts} <= #TCQ acounts + 4;
else if (DWIDTH == 64)
{COut_a,acounts} <= #TCQ acounts + 8;
else if (DWIDTH == 64)
{COut_a,acounts} <= #TCQ acounts + 16;
end
else
{COut_a,acounts} <= #TCQ acounts + 8;
end
else
acounts <= #TCQ acounts;
end
assign adata_tmp = {USER_BUS_DWIDTH/32{acounts[31:0]}};
end
else
begin: NO_ADDRESS_PATTERN
assign adata_tmp = 'b0;
end
endgenerate
// PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
// Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
//
always @ (posedge clk_i)
begin
if (user_burst_cnt > 6'd1 || cmd_startE)
user_burst_cnt_larger_1_r <= 1'b1;
else
user_burst_cnt_larger_1_r <= 1'b0;
end
generate
// When doing eye_test, traffic gen only does write and want to
// keep the prbs random and address is fixed at a location.
if (EYE_TEST == "TRUE")
begin : d_clk_en1
always @(data_clk_en)
data_clk_en = 1'b1;//fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end
//endgenerate
//generate
//if (EYE_TEST == "FALSE" || EYE_TEST == "READ_EYE")
else
begin : d_clk_en2
//assign data_clk_en = fifo_rdy_i & data_rdy_i & (user_burst_cnt_larger_1_r > 6'd0);
//assign data_clk_en2 = fifo_rdy_i & data_rdy_i & (user_burst_cnt_larger_1_r > 6'd0);
always @ (fifo_rdy_i, data_rdy_i , user_burst_cnt_larger_1_r)
begin
if (fifo_rdy_i && data_rdy_i && user_burst_cnt_larger_1_r )
data_clk_en <= 1'b1;
else
data_clk_en <= 1'b0;
end
always @ (fifo_rdy_i, data_rdy_i , user_burst_cnt_larger_1_r)
begin
if (fifo_rdy_i && data_rdy_i && user_burst_cnt_larger_1_r )
data_clk_en2 <= 1'b1;
else
data_clk_en2 <= 1'b0;
end
end
endgenerate
generate
if (DATA_PATTERN == "DGEN_PRBS" || DATA_PATTERN == "DGEN_ALL")
begin : PSUEDO_PRBS_PATTERN
// PRBS DATA GENERATION
// xor all the tap positions before feedback to 1st stage.
always @ (posedge clk_i)
m_addr_r <= m_addr_i;
data_prbs_gen #
(
.PRBS_WIDTH (32),
.SEED_WIDTH (32),
.EYE_TEST (EYE_TEST)
)
data_prbs_gen
(
.clk_i (clk_i),
.rst_i (rst_i),
.clk_en (data_clk_en),
.prbs_seed_init (cmd_startE),
.prbs_seed_i (m_addr_i[31:0]),
.prbs_o (mcb_prbs_data)
);
end
else
begin:NO_PSUEDO_PRBS_PATTERN
assign mcb_prbs_data = 'b0;
end
endgenerate
wire [31:0] ReSeedcounter_o;
assign prbs_seed = START_ADDR[BL_WIDTH+1:2];//addr_i[13:2];
always @ (posedge clk_i)
begin
if (rst_i)
prbs_seeded <= 1'b0;
else if (cmd_startE)
if ( data_mode_i == 4'b0111)
prbs_seeded <= 1'b1;
else
prbs_seeded <= 1'b0;
end
//localparam TAPS_VALUE = 12'b100000101001;//10'b1001000000; 256
//localparam TAPS_VALUE = 10'b1000000100;//10'b1001000000; 64
//localparam TAPS_VALUE = 9'b100001000;//9'b1001000000; 64
//localparam TAPS_VALUE = 8'b10001110;//10'b1001000000; repeated in 16 cmd writes
assign prbs_shift_value0 = prbs_shift_value[3:0];
assign prbs_shift_value1 = prbs_shift_value[7:4];
assign prbs_shift_value2 = prbs_shift_value[11:8];
assign prbs_shift_value3 = prbs_shift_value[15:12];
assign prbs_shift_value4 = prbs_shift_value[19:16];
assign prbs_shift_value5 = prbs_shift_value[23:20];
assign prbs_shift_value6 = prbs_shift_value[27:24];
assign prbs_shift_value7 = prbs_shift_value[31:28];
assign prbs_shift_value8 = prbs_shift_value[35:32];
assign prbs_shift_value9 = prbs_shift_value[39:36];
assign prbs_shift_value10 = prbs_shift_value[43:40];
assign prbs_shift_value11 = prbs_shift_value[47:44];
assign prbs_shift_value12 = prbs_shift_value[51:48];
assign prbs_shift_value13 = prbs_shift_value[55:52];
assign prbs_shift_value14 = prbs_shift_value[59:56];
assign prbs_shift_value15 = prbs_shift_value[63:60];
generate
if (nCK_PER_CLK == 4 )
begin
assign prbs_shift_value16 = prbs_shift_value[67:64];
assign prbs_shift_value17 = prbs_shift_value[71:68];
assign prbs_shift_value18 = prbs_shift_value[75:72];
assign prbs_shift_value19 = prbs_shift_value[79:76];
assign prbs_shift_value20 = prbs_shift_value[83:80];
assign prbs_shift_value21 = prbs_shift_value[87:84];
assign prbs_shift_value22 = prbs_shift_value[91:88];
assign prbs_shift_value23 = prbs_shift_value[95:92];
assign prbs_shift_value24 = prbs_shift_value[99:96];
assign prbs_shift_value25 = prbs_shift_value[103:100];
assign prbs_shift_value26 = prbs_shift_value[107:104];
assign prbs_shift_value27 = prbs_shift_value[111:108];
assign prbs_shift_value28 = prbs_shift_value[115:112];
assign prbs_shift_value29 = prbs_shift_value[119:116];
assign prbs_shift_value30 = prbs_shift_value[123:120];
assign prbs_shift_value31 = prbs_shift_value[127:124];
end
else
begin
assign prbs_shift_value16 = 'b0;
assign prbs_shift_value17 = 'b0;
assign prbs_shift_value18 = 'b0;
assign prbs_shift_value19 = 'b0;
assign prbs_shift_value20 = 'b0;
assign prbs_shift_value21 = 'b0;
assign prbs_shift_value22 = 'b0;
assign prbs_shift_value23 = 'b0;
assign prbs_shift_value24 = 'b0;
assign prbs_shift_value25 = 'b0;
assign prbs_shift_value26 = 'b0;
assign prbs_shift_value27 = 'b0;
assign prbs_shift_value28 = 'b0;
assign prbs_shift_value29 = 'b0;
assign prbs_shift_value30 = 'b0;
assign prbs_shift_value31 = 'b0;
end
endgenerate
genvar l;
generate
for (l = 0; l < nCK_PER_CLK*8; l = l + 1)
begin: prbs_modules
tg_prbs_gen #
(
.PRBS_WIDTH (PRBS_WIDTH),
.START_ADDR (START_ADDR),
.PRBS_OFFSET (l*4),
.TAPS (TAPS_VALUE)
)
u_data_prbs_gen
(
.clk_i (clk_i),
.rst (rst_i),
.clk_en (data_clk_en),
// .prbs_seed_init (prbs_seed_init),
.prbs_seed_i (prbs_seed[PRBS_WIDTH-1:0]),//(m_addr_i[31:0]),
.initialize_done (),
.prbs_shift_value (prbs_shift_value[(l+1)*4-1:(l)*4]),
// ADDED, richc 020810: declare ports to avoid warnings
.prbs_o (),
.ReSeedcounter_o (ReSeedcounter[(l+1)*32-1:(l)*32])
);
end endgenerate
// need a mux circuit to mux out prbs_ox to full_prbs bus.
always @ (posedge clk_i)
begin
if (rst_i)
prbs_mux_counter <= 'b0;
else if (data_clk_en )
prbs_mux_counter <= prbs_mux_counter + 1'b1;
end
always @ (posedge clk_i)
begin
if (rst_i)
mode_has_loaded <= 1'b0;
else if ( mode_load_r2 )
mode_has_loaded <= 1'b1;
end
// assert force_load whenever prbs generator has cycle through.
always @ (posedge clk_i)
begin
data_clk_en2_r <= data_clk_en2;
if (ReSeedcounter[31:0] == 0 && data_clk_en2_r && ~data_clk_en2)
force_load <= 1'b1;
else
force_load <= 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i)
prbs_comb_data_load <= 1'b0;
else if (prbs_mux_counter == 63 //&& DMODE == "WRITE" ||
)
prbs_comb_data_load <= 1'b1;
else if (data_clk_en2)
prbs_comb_data_load <= 1'b0;
end
// 16 PRBS generators are running in parallel. Each one is four cycles earlier to its next one.
//
always @ (posedge clk_i)
begin
if ((mode_load_i & ~mode_has_loaded )|| (prbs_comb_data_load && data_clk_en2 && ReSeedcounter[5:0] == 0) || force_load)
prbs_comb_data <= {
prbs_shift_value31,prbs_shift_value30,prbs_shift_value29,prbs_shift_value28,
prbs_shift_value27,prbs_shift_value26,prbs_shift_value25,prbs_shift_value24,
prbs_shift_value23 ,prbs_shift_value22,prbs_shift_value21,prbs_shift_value20,
prbs_shift_value19 ,prbs_shift_value18,prbs_shift_value17,prbs_shift_value16,
prbs_shift_value15,prbs_shift_value14,prbs_shift_value13,prbs_shift_value12,
prbs_shift_value11,prbs_shift_value10,prbs_shift_value9,prbs_shift_value8,
prbs_shift_value7 ,prbs_shift_value6,prbs_shift_value5,prbs_shift_value4,
prbs_shift_value3 ,prbs_shift_value2,prbs_shift_value1,prbs_shift_value0
};
end
always @ (posedge clk_i)
begin
mode_load_r1 <= mode_load_i;
mode_load_r2 <= mode_load_r1;
end
always @ (posedge clk_i)
begin
if ((mode_load_r1 && ~mode_has_loaded) || (ReSeedcounter[31:0] == 0 && ~data_clk_en2 && nCK_PER_CLK == 4) ||
(ReSeedcounter[31:0] == 0 && nCK_PER_CLK == 2 && data_clk_en2))
// needed to preload the previous value in READ mode.
if (nCK_PER_CLK == 4)
prbs_mux_data <= #TCQ {prbs_shift_value1,prbs_shift_value0};
else
prbs_mux_data[3:0] <= #TCQ {prbs_shift_value0};
else if (data_clk_en2 )
begin
case (prbs_mux_counter[3:0])
// 8
0 : if (ReSeedcounter[31:0] == 0)
if (nCK_PER_CLK == 4)
prbs_mux_data <= #TCQ {prbs_shift_value1,prbs_shift_value0};
else
prbs_mux_data[3:0] <= #TCQ {prbs_shift_value0};
else
prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*1 - 1:nCK_PER_CLK*2*0];
1 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*2 - 1:nCK_PER_CLK*2*1 ];
2 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*3 - 1:nCK_PER_CLK*2*2 ];//[23:16];
3 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*4 - 1:nCK_PER_CLK*2*3 ];//[31:24];
4 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*5 - 1:nCK_PER_CLK*2*4 ];//[39:32];
5 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*6 - 1:nCK_PER_CLK*2*5 ];//[47:40];
6 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*7 - 1:nCK_PER_CLK*2*6 ];//[55:48];
7 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*8 - 1:nCK_PER_CLK*2*7 ];//[63:56];
8 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*9 - 1:nCK_PER_CLK*2*8 ];//[71:64];
9 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*10 - 1:nCK_PER_CLK*2*9 ];//[79:72];
10: prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*11 - 1:nCK_PER_CLK*2*10];//[87:80];
11: prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*12 - 1:nCK_PER_CLK*2*11];//[95:88];
12: prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*13 - 1:nCK_PER_CLK*2*12];//[103:96];
13: prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*14 - 1:nCK_PER_CLK*2*13];//[111:104];
14: prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*15 - 1:nCK_PER_CLK*2*14];//[119:112];
15: prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*16 - 1:nCK_PER_CLK*2*15];//[127:120];
default: prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2 - 1:nCK_PER_CLK*2*0 ];//[7:0];
endcase
end
end
assign prbsdata_rising_0 = {NUM_DQ_PINS{prbs_mux_data[3]}};
assign prbsdata_falling_0 = {NUM_DQ_PINS{prbs_mux_data[2]}};
assign prbsdata_rising_1 = {NUM_DQ_PINS{prbs_mux_data[1]}};
assign prbsdata_falling_1 = {NUM_DQ_PINS{prbs_mux_data[0]}};
assign prbsdata_rising_2 = {NUM_DQ_PINS{prbs_mux_data[7]}};
assign prbsdata_falling_2 = {NUM_DQ_PINS{prbs_mux_data[6]}};
assign prbsdata_rising_3 = {NUM_DQ_PINS{prbs_mux_data[5]}};
assign prbsdata_falling_3 = {NUM_DQ_PINS{prbs_mux_data[4]}};
endmodule
|
// #####################################################################################
// # Copyright (C) 1991-2008 Altera Corporation
// # Any megafunction design, and related netlist (encrypted or decrypted),
// # support information, device programming or simulation file, and any other
// # associated documentation or information provided by Altera or a partner
// # under Altera's Megafunction Partnership Program may be used only
// # to program PLD devices (but not masked PLD devices) from Altera. Any
// # other use of such megafunction design, netlist, support information,
// # device programming or simulation file, or any other related documentation
// # or information is prohibited for any other purpose, including, but not
// # limited to modification, reverse engineering, de-compiling, or use with
// # any other silicon devices, unless such use is explicitly licensed under
// # a separate agreement with Altera or a megafunction partner. Title to the
// # intellectual property, including patents, copyrights, trademarks, trade
// # secrets, or maskworks, embodied in any such megafunction design, netlist,
// # support information, device programming or simulation file, or any other
// # related documentation or information provided by Altera or a megafunction
// # partner, remains with Altera, the megafunction partner, or their respective
// # licensors. No other licenses, including any licenses needed under any third
// # party's intellectual property, are provided herein.
// #####################################################################################
// #####################################################################################
// # Loopback module for SOPC system simulation with
// # Altera Triple Speed Ethernet (TSE) Megacore
// #
// # Generated at Tue Mar 5 15:23:15 2013 as a SOPC Builder component
// #
// #####################################################################################
// # This is a module used to provide external loopback on the TSE megacore by supplying
// # necessary clocks and default signal values on the network side interface
// # (GMII/MII/TBI/Serial)
// #
// # - by default this module generate clocks for operation in Gigabit mode that is
// # of 8 ns clock period
// # - no support for forcing collision detection and carrier sense in MII mode
// # the mii_col and mii_crs signal always pulled to zero
// # - you are recomment to set the the MAC operation mode using register access
// # rather than directly pulling the control signals
// #
// #####################################################################################
`timescale 1ns / 1ps
module tse_mac3_loopback (
ref_clk,
txp,
rxp
);
output ref_clk;
input txp;
output rxp;
reg clk_tmp;
initial
clk_tmp <= 1'b0;
always
#4 clk_tmp <= ~clk_tmp;
reg reconfig_clk_tmp;
initial
reconfig_clk_tmp <= 1'b0;
always
#20 reconfig_clk_tmp <= ~reconfig_clk_tmp;
assign ref_clk = clk_tmp;
assign rxp=txp;
endmodule
|
/*
* Copyright (c) 2011-2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
module cpu(
input clk,
input rst,
output mem_re,
output mem_we,
output reg [29:0] memaddr,
input [31:0] rmemdata,
output [31:0] wmemdata,
output [31:0] debugout
);
assign wmemdata = (mem_we && !mem_re) ? reg_c : 32'bz;
assign debugout = pc;
/* next pc */
reg [29:0] pc;
reg [29:0] nextpc;
reg [3:0] control_branch;
`define CONTROL_BRANCH_NOTAKE 4'b1xxx
`define CONTROL_BRANCH_UNCOND 4'b000?
`define CONTROL_BRANCH_COND_Z 4'b0010
`define CONTROL_BRANCH_COND_NZ 4'b0011
`define CONTROL_BRANCH_RA_UNCOND 4'b010?
`define CONTROL_BRANCH_RA_COND_Z 4'b0110
`define CONTROL_BRANCH_RA_COND_NZ 4'b0111
always @(control_branch or reg_c or aluout or reg_a or pc)
begin
casex (control_branch)
`CONTROL_BRANCH_NOTAKE: nextpc = pc;
`CONTROL_BRANCH_COND_Z: nextpc = (reg_c == 32'd0) ? aluout[29:0] : pc;
`CONTROL_BRANCH_COND_NZ: nextpc = (reg_c != 32'd0) ? aluout[29:0] : pc;
`CONTROL_BRANCH_UNCOND: nextpc = aluout[29:0];
`CONTROL_BRANCH_RA_COND_Z: nextpc = (reg_c == 32'd0) ? (reg_a >> 2) : pc;
`CONTROL_BRANCH_RA_COND_NZ: nextpc = (reg_c != 32'd0) ? (reg_a >> 2) : pc;
`CONTROL_BRANCH_RA_UNCOND: nextpc = (reg_a >> 2);
endcase
end
`define STATE_RST 3'd0
`define STATE_FETCH 3'd1
`define STATE_DECODE 3'd2
`define STATE_LOAD 3'd3
`define STATE_STORE 3'd4
reg [2:0] state;
reg control_load;
reg control_store;
/* top level states */
reg [2:0] nextstate;
always @(rst or state or control_load or control_store)
begin
if (rst)
nextstate = `STATE_RST;
else if (state == `STATE_RST || state == `STATE_LOAD || state == `STATE_STORE)
nextstate = `STATE_FETCH;
else if (state == `STATE_FETCH)
nextstate = `STATE_DECODE;
else if (control_load)
nextstate = `STATE_LOAD;
else if (control_store)
nextstate = `STATE_STORE;
else
nextstate = `STATE_FETCH;
end
assign mem_we = (nextstate == `STATE_STORE);
assign mem_re = ((nextstate == `STATE_FETCH) || (nextstate == `STATE_LOAD));
always @(nextstate or pc or nextpc or aluout)
begin
case (nextstate)
`STATE_RST: memaddr = pc;
`STATE_FETCH: memaddr = nextpc;
`STATE_DECODE: memaddr = 30'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
`STATE_LOAD: memaddr = aluout[31:2];
`STATE_STORE: memaddr = aluout[31:2];
default: memaddr = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
endcase
end
always @(posedge clk)
begin
state <= nextstate;
case (nextstate)
`STATE_RST: begin
pc <= 0;
end
`STATE_FETCH: begin
pc <= nextpc;
end
`STATE_DECODE: begin
pc <= aluout[29:0];
ir <= rmemdata;
end
endcase
end
/* alu */
reg [3:0] aluop;
wire [31:0] aluout;
wire [31:0] aluain;
wire [31:0] alubin;
alu alu0(
.op(aluop),
.a(aluain),
.b(alubin),
.res(aluout)
);
/* register file */
reg [3:0] reg_a_sel;
reg [3:0] reg_b_sel;
reg [3:0] reg_w_sel;
wire [31:0] reg_a;
wire [31:0] reg_b;
wire [31:0] reg_c;
wire [31:0] reg_wdata;
reg control_reg_wb;
regfile #(32, 4) regs(
.clk(clk),
.we(control_reg_wb),
.wsel(reg_w_sel),
.wdata(reg_wdata),
.asel(reg_a_sel),
.adata(reg_a),
.bsel(reg_b_sel),
.bdata(reg_b),
.csel(decode_rd),
.cdata(reg_c)
);
/* alu a input mux */
reg alu_a_mux_sel;
`define ALU_A_SEL_DC 1'bx
`define ALU_A_SEL_REG 1'b0
`define ALU_A_SEL_PC 1'b1
mux2 #(32) alu_a_mux(
.sel(alu_a_mux_sel),
.in0(reg_a),
.in1({ 2'b0, pc }),
.out(aluain)
);
/* alu b input mux */
reg [1:0] alu_b_mux_sel;
`define ALU_B_SEL_DC 2'bxx
`define ALU_B_SEL_REG 2'b00
`define ALU_B_SEL_IMM16 2'b01
`define ALU_B_SEL_IMM22 2'b10
`define ALU_B_SEL_ONE 2'b11
mux4 #(32) alu_b_mux(
.sel(alu_b_mux_sel),
.in0(reg_b),
.in1(decode_imm16_signed),
.in2(decode_imm22_signed),
.in3(32'd1),
.out(alubin)
);
/* register file write mux */
reg [1:0] reg_w_mux_sel;
`define REG_W_SEL_DC 2'bxx
`define REG_W_SEL_ALU 2'b00
`define REG_W_SEL_MEM 2'b01
`define REG_W_SEL_PC 2'b10
`define REG_W_SEL_ZERO 2'b11
mux4 #(32) reg_w_mux(
.sel(reg_w_mux_sel),
.in0(aluout),
.in1(rmemdata),
.in2({ pc, 2'b0 }),
.in3(0),
.out(reg_wdata)
);
/* decoder */
reg [31:0] ir;
wire [1:0] decode_form = ir[31:30];
wire [5:0] decode_op = ir[29:24];
wire [3:0] decode_rd = ir[27:24];
wire [3:0] decode_aluop = ir[23:20];
wire [3:0] decode_ra = ir[19:16];
wire [3:0] decode_rb = ir[15:12];
wire [31:0] decode_imm16_signed = (ir[15]) ? { 16'b1111111111111111, ir[15:0] } : { 16'b0000000000000000, ir[15:0] };
wire [31:0] decode_imm22_signed = (ir[21]) ? { 10'b1111111111, ir[21:0] } : { 10'b0000000000, ir[21:0] };
always @(ir or state or decode_form or decode_op or decode_rd or decode_aluop or decode_ra or decode_rb or decode_imm16_signed or decode_imm22_signed)
begin
/* undefined state */
aluop = 4'bxxxx;
control_load = 0;
control_store = 0;
control_branch = `CONTROL_BRANCH_NOTAKE;
control_reg_wb = 0;
reg_a_sel = 4'bxxxx;
reg_b_sel = 4'bxxxx;
reg_w_sel = 4'bxxxx;
alu_a_mux_sel = `ALU_A_SEL_DC;
alu_b_mux_sel = `ALU_B_SEL_DC;
reg_w_mux_sel = `REG_W_SEL_DC;
case (state)
`STATE_FETCH: begin
/* use the alu to calculate the next pc */
aluop = 4'b0000; // add
alu_a_mux_sel = `ALU_A_SEL_PC;
alu_b_mux_sel = `ALU_B_SEL_ONE;
end
`STATE_DECODE: begin
casex (decode_form)
2'b0?: begin /* form 0 and form 1 are very similar */
aluop = decode_aluop;
reg_a_sel = decode_ra;
reg_b_sel = decode_rb;
if (decode_form == 0) begin
$display("form 0");
alu_a_mux_sel = `ALU_A_SEL_REG;
alu_b_mux_sel = `ALU_B_SEL_IMM16;
end else begin
$display("form 1");
alu_a_mux_sel = `ALU_A_SEL_REG;
alu_b_mux_sel = `ALU_B_SEL_REG;
end
casex (decode_op)
default: begin
control_reg_wb = 1;
reg_w_sel = decode_rd;
reg_w_mux_sel = `REG_W_SEL_ALU;
end
/* load */
6'b01????: begin
$display("load");
control_load = 1;
end
/* store */
6'b10????: begin
$display("store");
control_store = 1;
end
endcase
end
2'b10: begin
$display("form 2 - branch");
if (ir[29] == 0) begin
// pc relative branch
aluop = 0; // add
control_branch = { 1'b0, 1'b0, ir[23], ir[22] };
alu_a_mux_sel = `ALU_A_SEL_PC;
alu_b_mux_sel = `ALU_B_SEL_IMM22;
end else begin
// branch to reg
control_branch = { 1'b0, 1'b1, ir[23], ir[22] };
reg_a_sel = decode_ra;
end
// branch and link
if (ir[28]) begin
reg_w_sel = 15; // LR
reg_w_mux_sel = `REG_W_SEL_PC;
control_reg_wb = 1;
end
end
2'b11: begin
$display("form 3 - undefined");
end
endcase
end
`STATE_LOAD: begin
control_reg_wb = 1;
reg_w_sel = decode_rd;
reg_w_mux_sel = `REG_W_SEL_MEM;
end
default: begin
end
endcase
end
endmodule
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=10 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=comm_pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 16.0 cbx_altclkbuf 2016:04:27:18:05:34:SJ cbx_altiobuf_bidir 2016:04:27:18:05:34:SJ cbx_altiobuf_in 2016:04:27:18:05:34:SJ cbx_altiobuf_out 2016:04:27:18:05:34:SJ cbx_altpll 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ VERSION_END
//CBXI_INSTANCE_NAME="DE0_myfirstfpga_comm_pll_comm_pll_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module comm_pll_altpll
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 10,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //comm_pll_altpll
//VALID FILE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_1_V
`define SKY130_FD_SC_LP__A2111OI_1_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111oi_1 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BA_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O21BA_FUNCTIONAL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire nor0_out ;
wire nor1_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X, B1_N, nor0_out );
buf buf0 (X , nor1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BA_FUNCTIONAL_V |
(*
Copyright 2014 Cornell University
This file is part of VPrl (the Verified Nuprl project).
VPrl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VPrl is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VPrl. If not, see <http://www.gnu.org/licenses/>.
Website: http://nuprl.org/html/verification/
Authors: Abhishek Anand & Vincent Rahli
*)
Require Export Eqdep.
Require Export FunctionalExtensionality.
Require Export terms.
(** printing # $\times$ #×# *)
(** printing <=> $\Leftrightarrow$ #⇔# *)
(** printing $ $\times$ #×# *)
(** printing & $\times$ #×# *)
(* begin hide *)
Inductive obool : Type :=
| otrue : obool
| ofalse : obool
| obseq : (nat -> obool) -> obool.
Definition bool2obool (b : bool) : obool :=
if b then otrue else ofalse.
Fixpoint oband (ob1 ob2 : obool) : obool :=
match ob1 with
| otrue => ob2
| ofalse => ob1
| obseq f =>
match ob2 with
| otrue => ob1
| ofalse => ob2
| obseq g => obseq (fun n => oband (f n) (g n))
end
end.
Fixpoint oball (l : list obool) : obool :=
match l with
| [] => otrue
| o :: l => oband o (oball l)
end.
Fixpoint term2otrue {o} (t : @NTerm o) : obool :=
match t with
| vterm _ => otrue
| sterm f => obseq (fun n => term2otrue (f n))
| oterm op bts => oball (map bterm2otrue bts)
end
with bterm2otrue {o} (bt : BTerm) : obool :=
match bt with
| bterm vars t => term2otrue t
end.
Fixpoint no_const {o} (t : @NTerm o) : bool :=
match t with
| vterm _ => true
| sterm _ => true (* what else can we do? *)
| oterm o bs => no_const_o o && ball (map no_const_b bs)
end
with no_const_b {o} (bt : @BTerm o) : bool :=
match bt with
| bterm _ t => no_const t
end.
Fixpoint no_oconst {o} (t : @NTerm o) : obool :=
match t with
| vterm _ => otrue
| sterm f => obseq (fun n => no_oconst (f n))
| oterm o bs => oband (bool2obool (no_const_o o)) (oball (map no_oconst_b bs))
end
with no_oconst_b {o} (bt : @BTerm o) : obool :=
match bt with
| bterm _ t => no_oconst t
end.
Lemma fold_nobnd {p} :
forall t : @NTerm p, bterm [] t = nobnd t.
Proof.
unfold nobnd; auto.
Qed.
Definition mk_ntseq {o} (f : @ntseq o) := sterm f.
Definition mk_integer {p} n : @NTerm p := oterm (Can (Nint n)) [].
Definition mk_nseq {p} f : @NTerm p := oterm (Can (Nseq f)) [].
Definition mk_nat {p} (n : nat) : @NTerm p := mk_integer (Z_of_nat n).
Definition mk_uni {p} n : @NTerm p := oterm (Can (NUni n)) [].
Definition mk_tuni {p} n : @NTerm p := oterm (NCan NTUni) [nobnd n].
Definition mk_minus {p} n : @NTerm p := oterm (NCan NMinus) [nobnd n].
Definition mk_base {p} : @NTerm p := oterm (Can NBase) [].
Definition mk_int {p} : @NTerm p := oterm (Can NInt) [].
Definition mk_axiom {p} : @NTerm p := oterm (Can NAxiom) [].
Definition mk_atom {p} : @NTerm p := oterm (Can NAtom) [].
Definition mk_uatom {p} : @NTerm p := oterm (Can NUAtom) [].
Definition mk_inl {p} (x : @NTerm p) := oterm (Can (NInj NInl)) [nobnd x].
Definition mk_inr {p} (x : @NTerm p) := oterm (Can (NInj NInr)) [nobnd x].
Definition mk_pair {p} (a b : @NTerm p) := oterm (Can NPair) [nobnd a , nobnd b].
Definition mk_sup {p} (a b : @NTerm p) := oterm (Can NSup) [nobnd a , nobnd b].
Definition mk_texc {p} (T1 T2 : @NTerm p) := oterm (Can NTExc) [nobnd T1, nobnd T2].
Definition mk_union {p} (T1 T2 : @NTerm p) := oterm (Can NUnion) [nobnd T1, nobnd T2].
Definition mk_union2 {p} (T1 T2 : @NTerm p) := oterm (Can NUnion2) [nobnd T1, nobnd T2].
Definition mk_approx {p} (a b : @NTerm p) := oterm (Can NApprox) [nobnd a , nobnd b].
Definition mk_cequiv {p} (a b : @NTerm p) := oterm (Can NCequiv) [nobnd a , nobnd b].
Definition mk_compute {p} (a b n : @NTerm p) := oterm (Can NCompute) [nobnd a , nobnd b , nobnd n].
Definition mk_free_from_atom {p} (a b c : @NTerm p) :=
oterm (Can NFreeFromAtom) [nobnd a,nobnd b,nobnd c].
Definition mk_free_from_atoms {p} (T t : @NTerm p) :=
oterm (Can NFreeFromAtoms) [nobnd T, nobnd t].
Definition mk_equality {p} (t1 t2 T : @NTerm p) :=
oterm (Can NEquality) [nobnd t1,nobnd t2,nobnd T].
Definition mk_tequality {p} (t1 t2 : @NTerm p) :=
oterm (Can NTEquality) [nobnd t1,nobnd t2].
Definition mk_can_test {p} test (a b c : @NTerm p) :=
oterm (NCan (NCanTest test)) [nobnd a,nobnd b,nobnd c].
Definition mk_ispair {p} := @mk_can_test p CanIspair.
Definition mk_isint {p} := @mk_can_test p CanIsint.
Definition mk_isinl {p} := @mk_can_test p CanIsinl.
Definition mk_isinr {p} := @mk_can_test p CanIsinr.
Definition mk_isaxiom {p} := @mk_can_test p CanIsaxiom.
Definition mk_islambda {p} := @mk_can_test p CanIslambda.
Definition mk_isatom {p} := @mk_can_test p CanIsatom.
Definition mk_isuatom {p} := @mk_can_test p CanIsuatom.
Definition mk_rec {p} (v : NVar) (T : @NTerm p) :=
oterm (Can NRec) [bterm [v] T].
Definition mk_image {p} (T f : @NTerm p) :=
oterm (Can NImage) [nobnd T, nobnd f].
Definition mk_function {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NFunction) [nobnd T1, bterm [v] T2].
Definition mk_product {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NProduct) [nobnd T1, bterm [v] T2].
Definition mk_set {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NSet) [nobnd T1, bterm [v] T2].
Definition mk_tunion {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NTUnion) [nobnd T1, bterm [v] T2].
Definition mk_quotient {p} (T1 : @NTerm p) (v1 v2 : NVar) (T2 : NTerm) :=
oterm (Can NQuotient) [nobnd T1, bterm [v1,v2] T2].
Definition mk_isect {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NIsect) [nobnd T1, bterm [v] T2].
Definition mk_disect {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NDIsect) [nobnd T1, bterm [v] T2].
Definition mk_eisect {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NEIsect) [nobnd T1, bterm [v] T2].
Definition mk_w {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NW) [nobnd T1, bterm [v] T2].
Definition mk_m {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NM) [nobnd T1, bterm [v] T2].
Definition mk_pw {p}
(P : @NTerm p)
(ap : NVar) (A : NTerm)
(bp : NVar) (ba : NVar) (B : NTerm)
(cp : NVar) (ca : NVar) (cb : NVar) (C : NTerm)
(p : NTerm) :=
oterm (Can NPW)
[ nobnd P,
bterm [ap] A,
bterm [bp; ba] B,
bterm [cp; ca; cb] C,
nobnd p
].
Definition mk_pm {p}
(P : @NTerm p)
(ap : NVar) (A : NTerm)
(bp : NVar) (ba : NVar) (B : NTerm)
(cp : NVar) (ca : NVar) (cb : NVar) (C : NTerm)
(p : NTerm) :=
oterm (Can NPM)
[ nobnd P,
bterm [ap] A,
bterm [bp; ba] B,
bterm [cp; ca; cb] C,
nobnd p
].
Definition mk_spread {p} (t1 : @NTerm p) (u v : NVar) (t2 : NTerm) :=
oterm (NCan NSpread) [nobnd t1, bterm [u, v] t2].
Definition mk_dsup {p} (t1 : @NTerm p) (u v : NVar) (t2 : NTerm) :=
oterm (NCan NDsup) [nobnd t1, bterm [u, v] t2].
Definition mk_decide {p} (t : @NTerm p) (u : NVar) (t1 : NTerm) (v : NVar) (t2 : NTerm) :=
oterm (NCan NDecide) [nobnd t, bterm [u] t1, bterm [v] t2].
Definition mk_cbv {p} (t1 : @NTerm p) (v : NVar) (t2 : NTerm) :=
oterm (NCan NCbv) [nobnd t1, bterm [v] t2].
Definition mk_try {p} (t1 : @NTerm p) (a : @NTerm p) (v : NVar) (t2 : NTerm) :=
oterm (NCan NTryCatch) [nobnd t1, nobnd a, bterm [v] t2].
Definition mk_fresh {p} (v : NVar) (t : @NTerm p) :=
oterm (NCan NFresh) [bterm [v] t].
Definition mk_sleep {p} (t : @NTerm p) := oterm (NCan NSleep) [nobnd t].
Definition mk_pertype {p} (R : @NTerm p) :=
oterm (Can NEPertype) [nobnd R].
Definition mk_ipertype {p} (R : @NTerm p) :=
oterm (Can NIPertype) [nobnd R].
Definition mk_spertype {p} (R : @NTerm p) :=
oterm (Can NSPertype) [nobnd R].
Definition mk_partial {p} (T : @NTerm p) :=
oterm (Can NPartial) [nobnd T].
Definition mk_admiss {p} (T : @NTerm p) :=
oterm (Can NAdmiss) [nobnd T].
Definition mk_mono {p} (T : @NTerm p) :=
oterm (Can NMono) [nobnd T].
Definition mk_less {p} (a b c d : @NTerm p) :=
oterm (NCan (NCompOp CompOpLess)) [nobnd a, nobnd b, nobnd c, nobnd d].
Definition mk_int_eq {p} (a b c d : @NTerm p) :=
oterm (NCan (NCompOp CompOpEq)) [nobnd a, nobnd b, nobnd c, nobnd d].
Definition mk_atom_eq {p} (a b c d : @NTerm p) :=
oterm (NCan (NCompOp CompOpEq)) [nobnd a, nobnd b, nobnd c, nobnd d].
Definition mk_parallel {p} (a b : @NTerm p) := oterm (NCan NParallel) [nobnd a, nobnd b].
Definition mk_add {p} (a b : @NTerm p) := oterm (NCan (NArithOp ArithOpAdd)) [nobnd a, nobnd b].
Definition mk_mul {p} (a b : @NTerm p) := oterm (NCan (NArithOp ArithOpMul)) [nobnd a, nobnd b].
Definition mk_sub {p} (a b : @NTerm p) := oterm (NCan (NArithOp ArithOpSub)) [nobnd a, nobnd b].
Definition mk_div {p} (a b : @NTerm p) := oterm (NCan (NArithOp ArithOpDiv)) [nobnd a, nobnd b].
Definition mk_rem {p} (a b : @NTerm p) := oterm (NCan (NArithOp ArithOpRem)) [nobnd a, nobnd b].
Definition mk_omega {p} : @NTerm p := oterm (Can NOmega) [].
Definition mk_constant_p {p} (x : get_pconstP p) := oterm (Can (NConstP x)) [].
Definition mk_constant_t {p} (x : get_pconstT p) := oterm (Can (NConstT x)) [].
(*
Definition mk_esquash (R : NTerm) :=
oterm (Can NEsquash) [nobnd R].
*)
(* Picks a variable that is not in the set of free variables of a given term *)
Definition newvar {p} (t : @NTerm p) := fresh_var (free_vars t).
Fixpoint free_vars_list {p} (terms : list (@NTerm p)) :=
match terms with
| [] => []
| t :: ts => free_vars t ++ free_vars_list ts
end.
Definition newvarlst {p} (ts : list (@NTerm p)) := fresh_var (free_vars_list ts).
Definition newvars {p} (n : nat) (ts : list (@NTerm p)) :=
fresh_distinct_vars n (free_vars_list ts).
Definition newvars2 {p} (terms : list (@NTerm p)) :=
let v1 := newvarlst terms in
let v2 := newvarlst (terms ++ [mk_var v1]) in
(v1, v2).
Definition newvars3 {p} (terms : list (@NTerm p)) :=
let v1 := newvarlst terms in
let v2 := newvarlst (terms ++ [mk_var v1]) in
let v3 := newvarlst (terms ++ [mk_var v1, mk_var v2]) in
(v1, v2, v3).
Definition newvars4 {p} (terms : list (@NTerm p)) :=
let v1 := newvarlst terms in
let v2 := newvarlst (terms ++ [mk_var v1]) in
let v3 := newvarlst (terms ++ [mk_var v1, mk_var v2]) in
let v4 := newvarlst (terms ++ [mk_var v1, mk_var v2, mk_var v3]) in
(v1, v2, v3, v4).
Definition newvars5 {p} (terms : list (@NTerm p)) :=
let v1 := newvarlst terms in
let v2 := newvarlst (terms ++ [mk_var v1]) in
let v3 := newvarlst (terms ++ [mk_var v1, mk_var v2]) in
let v4 := newvarlst (terms ++ [mk_var v1, mk_var v2, mk_var v3]) in
let v5 := newvarlst (terms ++ [mk_var v1, mk_var v2, mk_var v3, mk_var v4]) in
(v1, v2, v3, v4, v5).
Definition newvars6 {p} (terms : list (@NTerm p)) :=
let v1 := newvarlst terms in
let v2 := newvarlst (terms ++ [mk_var v1]) in
let v3 := newvarlst (terms ++ [mk_var v1, mk_var v2]) in
let v4 := newvarlst (terms ++ [mk_var v1, mk_var v2, mk_var v3]) in
let v5 := newvarlst (terms ++ [mk_var v1, mk_var v2, mk_var v3, mk_var v4]) in
let v6 := newvarlst (terms ++ [mk_var v1, mk_var v2, mk_var v3, mk_var v4, mk_var v5]) in
(v1, v2, v3, v4, v5, v6).
Definition newvars7 {p} (terms : list (@NTerm p)) :=
match newvars6 terms with
| (v1,v2,v3,v4,v5,v6) =>
let v7 := newvarlst (terms ++ [mk_var v1, mk_var v2, mk_var v3, mk_var v4, mk_var v5, mk_var v6]) in
(v1, v2, v3, v4, v5, v6, v7)
end.
(* --- non primitives --- *)
Definition mk_id {p} : @NTerm p := mk_lam nvarx (mk_var nvarx).
Definition mk_bottom {p} : @NTerm p := mk_fix mk_id.
Definition mk_bot {p} : @NTerm p := mk_bottom.
Definition mk_vbot {p} v : @NTerm p := mk_fix (mk_lam v (mk_var v)).
Definition mk_false {p} : @NTerm p := mk_approx mk_axiom mk_bot.
Definition mk_true {p} : @NTerm p := mk_approx mk_axiom mk_axiom.
Definition mk_void {p} : @NTerm p := mk_false.
Definition mk_unit {p} : @NTerm p := mk_true.
Definition mk_btrue {p} : @NTerm p := mk_inl mk_axiom.
Definition mk_bfalse {p} : @NTerm p := mk_inr mk_axiom.
Definition mk_ite {p} (a b c : @NTerm p) :=
mk_decide a (newvar b) b (newvar c) c.
Definition mk_tt {p} : @NTerm p := mk_btrue.
Definition mk_ff {p} : @NTerm p := mk_bfalse.
Definition mk_pi1 {p} (t : @NTerm p) := mk_spread t nvarx nvary (mk_var nvarx).
Definition mk_pi2 {p} (t : @NTerm p) := mk_spread t nvarx nvary (mk_var nvary).
Definition mk_outl {p} (t : @NTerm p) := mk_decide t nvarx (mk_var nvarx) nvary mk_bot.
Definition mk_outr {p} (t : @NTerm p) := mk_decide t nvarx mk_bot nvary (mk_var nvary).
Definition mk_halts {p} (t : @NTerm p) := mk_approx mk_axiom (mk_cbv t nvarx mk_axiom).
Definition mk_uall {p} := @mk_isect p.
Definition mk_all {p} := @mk_function p.
Definition mk_exists {p} := @mk_product p.
Definition mk_top {p} : @NTerm p := mk_isect mk_false nvarx mk_false.
Definition mk_member {p} (t T : @NTerm p) := mk_equality t t T.
Definition mk_type {p} (t : @NTerm p) := mk_tequality t t.
Definition mk_bool {p} : @NTerm p := mk_union mk_unit mk_unit.
Definition mk_apply2 {p} (R x y : @NTerm p) := mk_apply (mk_apply R x) y.
Definition mk_apply3 {p} (f a b c : @NTerm p) :=
mk_apply (mk_apply (mk_apply f a) b) c.
Definition mk_apply4 {p} (f a b c d : @NTerm p) :=
mk_apply (mk_apply (mk_apply (mk_apply f a) b) c) d.
Definition mk_squash {p} (T : @NTerm p) := mk_image T (mk_lam nvarx mk_axiom).
Definition mk_lam3 {p} v1 v2 v3 (b : @NTerm p) := mk_lam v1 (mk_lam v2 (mk_lam v3 b)).
Definition mk_less_than {p} (a b : @NTerm p) := mk_less a b mk_true mk_false.
Definition mk_or {p} (A B : @NTerm p) := mk_union A B.
Definition mk_zero {p} : @NTerm p := mk_nat 0.
Definition mk_one {p} : @NTerm p := mk_nat 1.
Definition mk_two {p} : @NTerm p := mk_nat 2.
(*
Definition mk_fun (T1 : NTerm) (T2 : NTerm) :=
oterm (Can NFunction) [nobnd T1, bterm [v] T2].
Definition mk_product (T1 : NTerm) (v : NVar) (T2 : NTerm) :=
oterm (Can NProduct) [nobnd T1, bterm [v] T2].
*)
(* --- foldings --- *)
Lemma fold_integer {p} :
forall i, oterm (Can (Nint i)) [] = @mk_integer p i.
Proof. sp. Qed.
Lemma fold_nseq {p} :
forall f, oterm (Can (Nseq f)) [] = @mk_nseq p f.
Proof. sp. Qed.
Lemma fold_ntseq {o} :
forall (f : @ntseq o), sterm f = mk_ntseq f.
Proof. sp. Qed.
Lemma fold_token {p} :
forall s, oterm (Can (NTok s)) [] = @mk_token p s.
Proof. sp. Qed.
Lemma fold_utoken {p} :
forall u, oterm (Can (NUTok u)) [] = @mk_utoken p u.
Proof. sp. Qed.
Lemma fold_atom {p} :
oterm (Can NAtom) [] = @mk_atom p.
Proof. sp. Qed.
Lemma fold_uatom {p} :
oterm (Can NUAtom) [] = @mk_uatom p.
Proof. sp. Qed.
Lemma fold_lam {p} :
forall v (b : @NTerm p), oterm (Can NLambda) [bterm [v] b] = mk_lam v b.
Proof. sp. Qed.
Lemma fold_apply {p} :
forall (a b : @NTerm p), oterm (NCan NApply) [ nobnd a, nobnd b ] = mk_apply a b.
Proof. sp. Qed.
Lemma fold_eapply {p} :
forall (a b : @NTerm p), oterm (NCan NEApply) [ nobnd a, nobnd b ] = mk_eapply a b.
Proof. sp. Qed.
Lemma fold_apseq {p} :
forall f (a : @NTerm p), oterm (NCan (NApseq f)) [ nobnd a ] = mk_apseq f a.
Proof. sp. Qed.
Lemma fold_decide {p} :
forall (d : @NTerm p) x f y g,
oterm (NCan NDecide) [nobnd d, bterm [x] f, bterm [y] g]
= mk_decide d x f y g.
Proof. sp. Qed.
Lemma fold_spread {p} :
forall (a : @NTerm p) x y b,
oterm (NCan NSpread) [nobnd a, bterm [x,y] b]
= mk_spread a x y b.
Proof. sp. Qed.
Lemma fold_dsup {p} :
forall (a : @NTerm p) x y b,
oterm (NCan NDsup) [nobnd a, bterm [x,y] b]
= mk_dsup a x y b.
Proof. sp. Qed.
Lemma fold_approx {p} :
forall (a b : @NTerm p), oterm (Can NApprox) [ nobnd a, nobnd b ] = mk_approx a b.
Proof. sp. Qed.
Lemma fold_cequiv {p} :
forall (a b : @NTerm p), oterm (Can NCequiv) [ nobnd a, nobnd b ] = mk_cequiv a b.
Proof. sp. Qed.
Lemma fold_pertype {p} :
forall (a : @NTerm p), oterm (Can NEPertype) [ nobnd a ] = mk_pertype a.
Proof. sp. Qed.
Lemma fold_ipertype {p} :
forall (a : @NTerm p), oterm (Can NIPertype) [ nobnd a ] = mk_ipertype a.
Proof. sp. Qed.
Lemma fold_spertype {p} :
forall (a : @NTerm p), oterm (Can NSPertype) [ nobnd a ] = mk_spertype a.
Proof. sp. Qed.
Lemma fold_tuni {p} :
forall (a : @NTerm p), oterm (NCan NTUni) [ nobnd a ] = mk_tuni a.
Proof. sp. Qed.
Lemma fold_minus {p} :
forall (a : @NTerm p), oterm (NCan NMinus) [ nobnd a ] = mk_minus a.
Proof. sp. Qed.
Lemma fold_admiss {p} :
forall (a : @NTerm p), oterm (Can NAdmiss) [ nobnd a ] = mk_admiss a.
Proof. sp. Qed.
Lemma fold_mono {p} :
forall (a : @NTerm p), oterm (Can NMono) [ nobnd a ] = mk_mono a.
Proof. sp. Qed.
Lemma fold_partial {p} :
forall (a : @NTerm p), oterm (Can NPartial) [ nobnd a ] = mk_partial a.
Proof. sp. Qed.
(*
Lemma fold_esquash :
forall a, oterm (Can NEsquash) [ nobnd a ] = mk_esquash a.
Proof.
sp.
Qed.
*)
Lemma fold_compute {p} :
forall (a b n : @NTerm p),
oterm (Can NCompute) [ nobnd a, nobnd b, nobnd n ]
= mk_compute a b n.
Proof. sp. Qed.
Lemma fold_equality {p} :
forall (a b c : @NTerm p),
oterm (Can NEquality) [ nobnd a, nobnd b, nobnd c ]
= mk_equality a b c.
Proof. sp. Qed.
Lemma fold_free_from_atom {p} :
forall (a b c : @NTerm p),
oterm (Can NFreeFromAtom) [ nobnd a, nobnd b, nobnd c ]
= mk_free_from_atom a b c.
Proof. sp. Qed.
Lemma fold_free_from_atoms {p} :
forall (a b : @NTerm p),
oterm (Can NFreeFromAtoms) [ nobnd a, nobnd b ]
= mk_free_from_atoms a b.
Proof. sp. Qed.
Lemma fold_tequality {p} :
forall (a b : @NTerm p),
oterm (Can NTEquality) [ nobnd a, nobnd b ]
= mk_tequality a b.
Proof. sp. Qed.
Lemma fold_base {p} :
oterm (Can NBase) [] = @mk_base p.
Proof. sp. Qed.
Lemma fold_member {p} :
forall (t T : @NTerm p),
mk_equality t t T = mk_member t T.
Proof. sp. Qed.
Lemma fold_mk_type {p} :
forall (t : @NTerm p),
mk_tequality t t = mk_type t.
Proof. sp. Qed.
Lemma fold_cbv {p} :
forall (t1 : @NTerm p) v t2,
oterm (NCan NCbv) [nobnd t1, bterm [v] t2] = mk_cbv t1 v t2.
Proof. sp. Qed.
Lemma fold_try {p} :
forall (t1 : @NTerm p) a v t2,
oterm (NCan NTryCatch) [nobnd t1, nobnd a, bterm [v] t2] = mk_try t1 a v t2.
Proof. sp. Qed.
Lemma fold_fresh {p} :
forall v (t : @NTerm p),
oterm (NCan NFresh) [bterm [v] t] = mk_fresh v t.
Proof. sp. Qed.
Lemma fold_sleep {p} :
forall (t : @NTerm p), oterm (NCan NSleep) [nobnd t] = mk_sleep t.
Proof. sp. Qed.
Lemma fold_halts {p} :
forall (t : @NTerm p),
mk_approx mk_axiom (mk_cbv t nvarx mk_axiom) = mk_halts t.
Proof. sp. Qed.
Lemma fold_function {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NFunction) [nobnd t1, bterm [v] t2] = mk_function t1 v t2.
Proof. sp. Qed.
Lemma fold_isect {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NIsect) [nobnd t1, bterm [v] t2] = mk_isect t1 v t2.
Proof.
sp.
Qed.
Lemma fold_disect {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NDIsect) [nobnd t1, bterm [v] t2] = mk_disect t1 v t2.
Proof.
sp.
Qed.
Lemma fold_eisect {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NEIsect) [nobnd t1, bterm [v] t2] = mk_eisect t1 v t2.
Proof.
sp.
Qed.
Lemma fold_w {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NW) [nobnd t1, bterm [v] t2] = mk_w t1 v t2.
Proof.
sp.
Qed.
Lemma fold_m {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NM) [nobnd t1, bterm [v] t2] = mk_m t1 v t2.
Proof.
sp.
Qed.
Lemma fold_pw {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
oterm (Can NPW)
[nobnd P,
bterm [ap] A,
bterm [bp,ba] B,
bterm [cp,ca,cb] C,
nobnd p
]
= mk_pw P ap A bp ba B cp ca cb C p.
Proof.
sp.
Qed.
Lemma fold_pm {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
oterm (Can NPM)
[nobnd P,
bterm [ap] A,
bterm [bp,ba] B,
bterm [cp,ca,cb] C,
nobnd p
]
= mk_pm P ap A bp ba B cp ca cb C p.
Proof.
sp.
Qed.
Lemma fold_product {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NProduct) [nobnd t1, bterm [v] t2] = mk_product t1 v t2.
Proof.
sp.
Qed.
Lemma fold_set {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NSet) [nobnd t1, bterm [v] t2] = mk_set t1 v t2.
Proof.
sp.
Qed.
Lemma fold_texc {p} :
forall (t1 t2 : @NTerm p),
oterm (Can NTExc) [nobnd t1, nobnd t2] = mk_texc t1 t2.
Proof.
sp.
Qed.
Lemma fold_union {p} :
forall (t1 : @NTerm p) t2,
oterm (Can NUnion) [nobnd t1, nobnd t2] = mk_union t1 t2.
Proof.
sp.
Qed.
Lemma fold_union2 {p} :
forall (t1 : @NTerm p) t2,
oterm (Can NUnion2) [nobnd t1, nobnd t2] = mk_union2 t1 t2.
Proof.
sp.
Qed.
Lemma fold_tunion {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NTUnion) [nobnd t1, bterm [v] t2] = mk_tunion t1 v t2.
Proof.
sp.
Qed.
Lemma fold_quotient {p} :
forall (t1 : @NTerm p) v1 v2 t2,
oterm (Can NQuotient) [nobnd t1, bterm [v1;v2] t2] = mk_quotient t1 v1 v2 t2.
Proof.
sp.
Qed.
Lemma fold_pair {p} :
forall (a b : @NTerm p), oterm (Can NPair) [ nobnd a, nobnd b ] = mk_pair a b.
Proof.
sp.
Qed.
Lemma fold_ispair {p} :
forall (a b c : @NTerm p),
oterm (NCan (NCanTest CanIspair)) [ nobnd a, nobnd b, nobnd c ]
= mk_ispair a b c.
Proof. sp. Qed.
Lemma fold_isinl {p} :
forall (a b c : @NTerm p),
oterm (NCan (NCanTest CanIsinl)) [ nobnd a, nobnd b, nobnd c ]
= mk_isinl a b c.
Proof. sp. Qed.
Lemma fold_isinr {p} :
forall (a b c : @NTerm p),
oterm (NCan (NCanTest CanIsinr)) [ nobnd a, nobnd b, nobnd c ]
= mk_isinr a b c.
Proof. sp. Qed.
Lemma fold_isaxiom {p} :
forall (a b c : @NTerm p),
oterm (NCan (NCanTest CanIsaxiom)) [ nobnd a, nobnd b, nobnd c ]
= mk_isaxiom a b c.
Proof. sp. Qed.
Lemma fold_isint {p} :
forall (a b c : @NTerm p),
oterm (NCan (NCanTest CanIsint)) [ nobnd a, nobnd b, nobnd c ]
= mk_isint a b c.
Proof. sp. Qed.
Lemma fold_islambda {p} :
forall (a b c : @NTerm p),
oterm (NCan (NCanTest CanIslambda)) [ nobnd a, nobnd b, nobnd c ]
= mk_islambda a b c.
Proof. sp. Qed.
Lemma fold_sup {p} :
forall (a b : @NTerm p), oterm (Can NSup) [ nobnd a, nobnd b ] = mk_sup a b.
Proof. sp. Qed.
Lemma fold_exception {p} :
forall a (e : @NTerm p), oterm Exc [ nobnd a, nobnd e ] = mk_exception a e.
Proof. sp. Qed.
Lemma fold_fix {p} :
forall (f : @NTerm p), oterm (NCan NFix) [ nobnd f ] = mk_fix f.
Proof. sp. Qed.
Lemma fold_parallel {p} :
forall (a b : @NTerm p), oterm (NCan NParallel) [ nobnd a, nobnd b ] = mk_parallel a b.
Proof. sp. Qed.
(* ------ SIMPLE CHECKERS ON TERMS ------ *)
Definition ispair {p} (t : @NTerm p) :=
match t with
| (| a , b |) => true
| _ => false
end.
(* ------ SIMPLE OPERATORS ON TERMS ------ *)
(*
Fixpoint depth (t : NTerm) : nat :=
match t with
| vterm _ => 1
| oterm op bterms => lsum map depth_bterm bterms
end
with depth_bterm (lv : list NVar) (nt : NTerm) :=
match bt with
| bterm lv nt => depth nt
end.
*)
Fixpoint size {p} (t : @NTerm p) : nat :=
match t with
| vterm _ => 1
| sterm _ => 1
| oterm op bterms => S (addl (map size_bterm bterms))
end
with size_bterm {p} (bt: BTerm) :=
match bt with
| bterm lv nt => size nt
end.
(* ------ INDUCTION ON TERMS ------ *)
Lemma size_subterm2 {p} :
forall (o : @Opid p) (lb : list BTerm) (b : BTerm) ,
LIn b lb
-> size_bterm b < size (oterm o lb).
Proof.
simpl. induction lb; intros ? Hin; inverts Hin as; simpl.
- unfold lt. apply le_n_S.
apply le_plus_l.
- intros Hin. apply IHlb in Hin. clear IHlb.
eapply lt_le_trans; eauto.
apply le_n_S. apply le_plus_r.
Defined.
Lemma size_subterm3 {p} :
forall (o : @Opid p) (lb : list BTerm) (nt : NTerm) (lv : list NVar) ,
LIn (bterm lv nt) lb
-> size nt < size (oterm o lb).
Proof.
introv X.
apply (@size_subterm2 p) with (o:=o) in X. auto.
Defined.
(* Some of the ordinal stuff comes from
https://github.com/martijnvermaat/infinitary-rewriting-coq/blob/master/Ordinal.v
*)
Lemma osize_subterm2 {o} :
forall (op : @Opid o) bs b,
LIn b bs -> (osize_bterm b) << (osize (oterm op bs)).
Proof.
simpl.
induction bs; intros ? Hin; inverts Hin as; simpl.
- exists (None : option (opred_type (oadd (osize_bterm b) (oaddl (map osize_bterm bs))))); simpl.
apply ord_le_oadd_l.
- intro Hin.
apply IHbs in Hin; clear IHbs.
exists (None : option (opred_type (oadd (osize_bterm a) (oaddl (map osize_bterm bs))))); simpl.
eapply ord_le_trans;[|apply ord_le_oadd_r].
apply ord_lt_OS_implies in Hin; auto.
Defined.
Lemma osize_subterm3 {o} :
forall (op : @Opid o) bs t vs,
LIn (bterm vs t) bs
-> (osize t) << (osize (oterm op bs)).
Proof.
introv i.
apply (osize_subterm2 op) in i; allsimpl; auto.
Defined.
Lemma NTerm_better_ind2 {p} :
forall P : (@NTerm p) -> Type,
(forall n : NVar, P (vterm n))
-> (forall f, (forall n, P (f n)) -> P (sterm f))
-> (forall (o : Opid) (lbt : list BTerm),
(forall (nt nt': NTerm) (lv: list NVar),
(LIn (bterm lv nt) lbt)
-> (osize nt') <=< (osize nt)
-> P nt'
)
-> P (oterm o lbt)
)
-> forall t : NTerm, P t.
Proof.
intros P Hvar Hseq Hbt.
assert (forall n t, (osize t) =o= n -> P t) as Hass;
[|introv;
apply Hass with (n := osize t);
apply ord_eq_refl].
induction n as [n Hind] using comp_ind_ord.
intros t Hsz.
destruct t as [v|f|op bs].
- clear Hseq Hbt.
apply Hvar.
- clear Hvar Hbt.
apply Hseq; introv; allsimpl; clear Hseq.
pose proof (Hind (osize (f n0))) as h; clear Hind.
autodimp h hyp; [|apply h; apply ord_eq_refl].
eapply ord_lt_eq_trans;[|exact Hsz]; clear Hsz.
apply implies_ord_lt_OS.
eapply implies_ord_le_limit_right.
apply ord_le_refl.
- apply Hbt.
introv Hin Hs; allsimpl.
apply (Hind (osize nt')); auto.
{ eapply ord_lt_eq_trans;[|exact Hsz]; clear Hsz.
apply implies_ord_lt_OS.
eapply ord_le_trans;[exact Hs|]; clear Hs.
pose proof (osize_subterm3 op bs nt lv Hin) as h; allsimpl.
apply ord_lt_OS_implies; auto. }
apply ord_eq_refl.
Defined.
Lemma NTerm_better_ind {p} :
forall P : @NTerm p -> Type,
(forall n : NVar, P (vterm n))
-> (forall f, (forall n, P (f n)) -> P (sterm f))
-> (forall (o : Opid) (lbt : list BTerm),
(forall (nt : NTerm) (lv: list NVar),
(LIn (bterm lv nt) lbt) -> P nt
)
-> P (oterm o lbt)
)
-> forall t : NTerm, P t.
Proof.
introv Hv Hs Hind.
apply NTerm_better_ind2; auto.
introv Hx.
apply Hind.
introv Hin.
eapply Hx in Hin; eauto.
apply ord_le_refl.
Defined.
Fixpoint NTerm_BTerm_mutual_ind {p}
(PN : @NTerm p -> Type) (PB : BTerm -> Type)
(vcase : forall n : NVar, PN (vterm n))
(scase : forall f, (forall n, PN (f n)) -> PN (sterm f))
(bcase: forall (lv : list NVar) (nt : NTerm),
PN nt -> PB (bterm lv nt))
(ocase: forall (o : Opid) (lbt : list BTerm),
(forall (bt : BTerm),
(LIn bt lbt) -> PB bt)
-> PN (oterm o lbt))
(t : NTerm) {struct t} : PN t
with
BTerm_NTerm_mutual_ind {p} (PN : @NTerm p -> Type) (PB : BTerm -> Type)
(vcase : forall n : NVar, PN (vterm n))
(scase : forall f, (forall n, PN (f n)) -> PN (sterm f))
(bcase: forall (lv : list NVar) (nt : NTerm),
PN nt -> PB (bterm lv nt))
(ocase: forall (o : Opid) (lbt : list BTerm),
(forall (bt : BTerm),
(LIn bt lbt) -> PB bt)
-> PN (oterm o lbt))
(bt : BTerm) {struct bt} : PB bt.
Proof.
- destruct t as [?|f|o lbt];[ apply vcase; fail| |].
{ apply scase; auto; introv.
apply NTerm_BTerm_mutual_ind with (PB := PB); auto. }
apply ocase.
introv Hin.
induction lbt as [| btt lbt HBInd];[inverts Hin|].
dorn Hin.
+ rw <- Hin.
apply BTerm_NTerm_mutual_ind with (PN:=PN);
clear BTerm_NTerm_mutual_ind;trivial.
+ clear BTerm_NTerm_mutual_ind;
apply HBInd in Hin. auto.
- clear BTerm_NTerm_mutual_ind.
destruct bt as [lv nt]. apply bcase.
apply NTerm_BTerm_mutual_ind with (PB:=PB);
clear NTerm_BTerm_mutual_ind; trivial.
Defined.
Lemma NBTerm_mutual_ind {p} : forall
(PN : @NTerm p -> Type) (PB : BTerm -> Type)
(vcase : forall n : NVar, PN (vterm n))
(scase : forall f, (forall n, PN (f n)) -> PN (sterm f))
(bcase: forall (lv : list NVar) (nt : NTerm),
PN nt -> PB (bterm lv nt))
(ocase: forall (o : Opid) (lbt : list BTerm),
(forall (bt : BTerm),
(LIn bt lbt) -> PB bt)
-> PN (oterm o lbt)),
((forall nt, PN nt) # (forall bt, PB bt)).
Proof.
intros.
split.
- eapply NTerm_BTerm_mutual_ind; eauto.
- eapply BTerm_NTerm_mutual_ind; eauto.
Defined.
Lemma NTerm_better_ind_direct {p} :
forall P : @NTerm p -> Type,
(forall n : NVar, P (vterm n))
-> (forall f, (forall n, P (f n)) -> P (sterm f))
-> (forall (o : Opid) (lbt : list BTerm),
(forall (nt : NTerm) (lv: list NVar),
(LIn (bterm lv nt) lbt) -> P nt
)
-> P (oterm o lbt)
)
-> forall t : NTerm, P t.
Proof.
introv Hv Hs Hind.
fix 1.
intro t.
destruct t as [|f|o lbt];[apply Hv;fail|apply Hs;auto;fail|].
apply Hind.
introv Hin.
induction lbt as [| bt lbt HBInd];[inverts Hin|].
destruct bt as [blv bnt].
dorn Hin.
- symmetry in Hin. inverts Hin. apply NTerm_better_ind_direct.
- clear NTerm_better_ind_direct.
apply HBInd in Hin. auto.
Defined.
Tactic Notation "nterm_ind" ident(h) ident(c) :=
induction h using NTerm_better_ind;
[ Case_aux c "vterm"
| Case_aux c "sterm"
| Case_aux c "oterm"
].
Tactic Notation "nterm_ind" ident(h) "as" simple_intropattern(I) ident(c) :=
induction h as I using NTerm_better_ind;
[ Case_aux c "vterm"
| Case_aux c "sterm"
| Case_aux c "oterm"
].
Tactic Notation "nterm_ind1" ident(h) "as" simple_intropattern(I) ident(c) :=
induction h as I using NTerm_better_ind;
[ Case_aux c "vterm"
| Case_aux c "sterm"
| Case_aux c "oterm"
].
Tactic Notation "nterm_ind1s" ident(h) "as" simple_intropattern(I) ident(c) :=
induction h as I using NTerm_better_ind2;
[ Case_aux c "vterm"
| Case_aux c "sterm"
| Case_aux c "oterm"
].
Definition IsTypeOpid {p} (opid : @Opid p) : bool :=
match opid with
| Can (NUni _) => true
| Can NEquality => true
| Can NTEquality => true
| Can NInt => true
| Can NAtom => true
| Can NBase => true
| Can NFunction => true
| Can NProduct => true
| Can NSet => true
| Can NQuotient => true
| Can NIsect => true
| Can NDIsect => true
| Can NEIsect => true
| Can NW => true
| Can NEPertype => true
| Can NIPertype => true
| Can NSPertype => true
| Can NPartial => true
| Can NTExc => true
| Can NUnion => true
| Can NUnion2 => true
| Can NTUnion => true
| Can NApprox => true
| Can NCequiv => true
| Can NCompute => true
| Can NRec => true
| Can NImage => true
| _ => false
end.
Definition IsType {p} (t : @NTerm p) : bool :=
match t with
| vterm _ => false
| sterm _ => false
| oterm opid _ => IsTypeOpid opid
end.
Lemma num_bvars_on_bterm {p} :
forall l (n : @NTerm p),
num_bvars (bterm l n) = length l.
Proof.
unfold num_bvars; simpl; sp.
Qed.
Definition no_vars_like {o} (t : @NTerm o) :=
closed t # noutokens t.
Definition no_vars_like_b {o} (t : @NTerm o) : bool :=
nullb (free_vars t) && nullb (get_utokens t).
Fixpoint wft {o} (t : @NTerm o) : obool :=
match t with
| vterm _ => otrue
| sterm f => obseq (fun n => oband (bool2obool (no_vars_like_b (f n))) (wft (f n)))
| oterm op bts =>
oband (bool2obool (beq_list eq_nat_dec (map (num_bvars) bts) (OpBindings op)))
(oball (map wftb bts))
end
with wftb {p} (bt : BTerm) : obool :=
match bt with
| bterm vars t => wft t
end.
Definition wf_term {p} (t : @NTerm p) := wft t = term2otrue t.
Lemma fold_wf_term {o} : forall t : @NTerm o, wft t = term2otrue t <=> wf_term t.
Proof. sp. Qed.
Definition wf_bterm {p} (b : @BTerm p) := wftb b = bterm2otrue b.
Lemma wf_term_proof_irrelevance {p} :
forall (t : @NTerm p),
forall x y : wf_term t,
x = y.
Proof.
intros.
apply UIP.
Qed.
Hint Extern 0 =>
let h := fresh "h" in
match goal with
| [ H1 : wf_term ?t , H2 : wf_term ?t |- _ ] =>
pose proof (wf_term_proof_irrelevance t H2 H1) as h; subst
end : pi.
Definition wf_term_extract {p} :=
fun (t : @NTerm p) (x : wf_term t) =>
match x return (x = match x with
| eq_refl => eq_refl (wft t)
end)
with
| eq_refl => eq_refl eq_refl
end.
(*
Definition wf_term_extract1 :=
fun (t : NTerm) (x : wf_term t) =>
match x in _ = b return match b with
| true => x = eq_refl (wft t)
end
with
| eq_refl => eq_refl eq_refl
end.
Lemma wf_term_extract2 :
forall t : NTerm,
forall x : wf_term t,
x = eq_refl (wft t).
*)
(*Lemma yyy : forall A (x : A) (pf : x = x), pf = eq_refl x.
Lemma xxx : forall t (x : wft t = true), x = eq_refl (wft t).*)
Lemma oball_ofalse :
forall (l : list obool),
oball l = ofalse -> LIn ofalse l.
Proof.
induction l; introv h; allsimpl; ginv.
destruct a; allsimpl; ginv.
remember (oball l) as obl; destruct obl; ginv.
Qed.
Lemma term2otrue_not_ofalse {o} :
forall (t : @NTerm o),
term2otrue t = ofalse -> False.
Proof.
nterm_ind t as [v|f ind|op bs ind] Case; simpl; introv h; ginv.
apply oball_ofalse in h.
rw in_map_iff in h; exrepnd.
destruct a as [l t].
applydup ind in h1; tcsp.
Qed.
Lemma bterm2otrue_not_ofalse {o} :
forall (b : @BTerm o),
bterm2otrue b = ofalse -> False.
Proof.
introv e.
destruct b as [l t]; allsimpl.
apply term2otrue_not_ofalse in e; sp.
Qed.
Lemma wft_otrue_implies_term2otrue_otrue {o} :
forall (t : @NTerm o),
wft t = otrue
-> term2otrue t = otrue.
Proof.
nterm_ind t as [v|f ind|op bs ind] Case; simpl; introv e; ginv.
remember (beq_list eq_nat_dec (map num_bvars bs) (OpBindings op)) as b.
destruct b; allsimpl; ginv.
clear Heqb.
clear op.
induction bs; allsimpl; ginv.
destruct a as [l t]; allsimpl.
autodimp IHbs hyp.
{ introv q h; apply (ind nt lv); auto. }
remember (wft t) as ob1; symmetry in Heqob1; destruct ob1; allsimpl; ginv.
- pose proof (ind t l) as h; repeat (autodimp h hyp).
rw h; simpl; auto.
- remember (oball (map wftb bs)) as ob2; symmetry in Heqob2.
destruct ob2; allsimpl; ginv.
Qed.
Lemma oball_map_bterm2otrue_not_ofalse {o} :
forall (bs : list (@BTerm o)),
oball (map bterm2otrue bs) = ofalse -> False.
Proof.
induction bs; allsimpl; introv e; ginv.
remember (bterm2otrue a) as ob1; symmetry in Heqob1.
destruct ob1; allsimpl; ginv.
- apply bterm2otrue_not_ofalse in Heqob1; sp.
- remember (oball (map bterm2otrue bs)) as ob2; symmetry in Heqob2.
destruct ob2; allsimpl; ginv.
Qed.
Lemma oball_map_wftb_otrue_implies {o} :
forall (bs : list (@BTerm o)),
oball (map wftb bs) = otrue
-> oball (map bterm2otrue bs) = otrue.
Proof.
induction bs; allsimpl; introv e; auto.
destruct a as [l t]; allsimpl.
remember (wft t) as ob; symmetry in Heqob; destruct ob; allsimpl; ginv; tcsp.
- rw @wft_otrue_implies_term2otrue_otrue; auto.
- remember (oball (map wftb bs)) as ob2; symmetry in Heqob2.
destruct ob2; allsimpl; ginv; tcsp.
Qed.
Lemma wft_obseq_implies_term2otrue_obseq {o} :
forall (t : @NTerm o) (f : nat -> obool),
wft t = obseq f
-> {g : nat -> obool & term2otrue t = obseq g}.
Proof.
nterm_ind t as [v|f ind|op bs ind] Case; simpl; introv e; ginv.
- eexists; eauto.
- remember (beq_list eq_nat_dec (map num_bvars bs) (OpBindings op)) as b.
destruct b; allsimpl; ginv.
clear Heqb.
clear op.
revert dependent f.
induction bs; allsimpl; introv e; ginv.
destruct a as [l t]; allsimpl.
autodimp IHbs hyp.
{ introv i; apply (ind nt lv); auto. }
remember (wft t) as ob1; symmetry in Heqob1; destruct ob1; allsimpl; ginv.
+ pose proof (IHbs f) as q; clear IHbs.
autodimp q hyp; exrepnd.
applydup @wft_otrue_implies_term2otrue_otrue in Heqob1; rw Heqob0; simpl.
eexists; eauto.
+ remember (oball (map wftb bs)) as ob2; symmetry in Heqob2.
destruct ob2; allsimpl; ginv.
* clear IHbs.
pose proof (ind t l) as h; clear ind; autodimp h hyp.
pose proof (h f) as q; clear h; autodimp q hyp; exrepnd.
rw q0; simpl.
rw @oball_map_wftb_otrue_implies; auto.
eexists; eauto.
* pose proof (IHbs o1) as q; clear IHbs; autodimp q hyp; exrepnd.
rw q0.
pose proof (ind t l) as h; clear ind; autodimp h hyp.
apply h in Heqob1; exrepnd; clear h.
rw Heqob0; simpl.
eexists; eauto.
Qed.
Lemma oband_of_obseq :
forall s1 s2,
oband (obseq s1) (obseq s2)
= obseq (fun n => oband (s1 n) (s2 n)).
Proof.
sp.
Qed.
Fixpoint isotrue (o : obool) : Prop :=
match o with
| otrue => True
| ofalse => False
| obseq f => forall n, isotrue (f n)
end.
Lemma isotrue_oband :
forall o1 o2, isotrue (oband o1 o2) <=> (isotrue o1 # isotrue o2).
Proof.
induction o1 as [|?|f ind]; introv; split; intro isob; allsimpl; try dands; tcsp.
- introv.
destruct o2; allsimpl; tcsp.
pose proof (isob n) as h.
apply ind in h; sp.
- destruct o2; allsimpl; tcsp.
introv.
pose proof (isob n) as h.
apply ind in h; sp.
- repnd.
destruct o2; allsimpl; tcsp.
introv.
apply ind; dands; auto.
Qed.
Lemma isotrue_oball :
forall l o, isotrue (oball l) -> LIn o l -> isotrue o.
Proof.
induction l; introv ib io; allsimpl; tcsp.
allrw @isotrue_oband; repnd.
repndors; subst; auto.
Qed.
Lemma isotrue_oball_iff :
forall l, isotrue (oball l) <=> (forall o, LIn o l -> isotrue o).
Proof.
induction l; split; introv h; introv; allsimpl; tcsp.
- intro q.
allrw @isotrue_oband; repnd.
repndors; subst; auto.
rw IHl in h.
apply h in q; auto.
- apply isotrue_oband; dands; auto.
apply IHl; introv i.
apply h; sp.
Qed.
Lemma isotrue_oball_map_wftb_implies {o} :
forall (bs : list (@BTerm o)) b,
isotrue (oball (map wftb bs))
-> LIn b bs
-> isotrue (wftb b).
Proof.
introv ibo ib.
eapply isotrue_oball;[exact ibo|].
rw in_map_iff.
eexists; dands; eauto.
Qed.
Lemma isotrue_term2otrue {o} :
forall (t : @NTerm o), isotrue (term2otrue t).
Proof.
nterm_ind t as [v|f inf|op bs ind] Case; allsimpl; auto.
apply isotrue_oball_iff; introv i.
allrw in_map_iff; exrepnd; subst.
destruct a as [l t]; allsimpl.
eapply ind; eauto.
Qed.
Lemma isotrue_oball_map_bterm2otrue {o} :
forall (bs : list (@BTerm o)),
isotrue (oball (map bterm2otrue bs)).
Proof.
introv.
eapply isotrue_oball_iff; introv i.
allrw in_map_iff; exrepnd; subst.
destruct a; simpl.
apply isotrue_term2otrue.
Qed.
Lemma isotrue_bool2obool :
forall b, isotrue (bool2obool b) -> b = true.
Proof.
introv h; destruct b; allsimpl; auto.
Qed.
Lemma isotrue_wft_implies_eq_term2otrue {o} :
forall (t : @NTerm o), isotrue (wft t) -> wft t = term2otrue t.
Proof.
nterm_ind t as [v|f ind|op bs ind] Case; introv iso; allsimpl; auto.
- Case "sterm".
f_equal.
apply functional_extensionality.
introv.
pose proof (iso x) as h.
allrw isotrue_oband; repnd.
apply isotrue_bool2obool in h0; rw h0; simpl.
apply ind; auto.
- Case "oterm".
allrw isotrue_oband; repnd.
apply isotrue_bool2obool in iso0.
rw iso0; simpl.
f_equal.
apply eq_maps; introv i.
destruct x as [l t]; allsimpl.
allrw isotrue_oball_iff.
eapply ind; eauto.
apply iso.
rw in_map_iff; eexists; eauto.
Qed.
Lemma oball_map_wftb_eq_otrue_implies {o} :
forall (bs : list (@BTerm o)) b,
oball (map wftb bs) = oball (map bterm2otrue bs)
-> LIn b bs
-> wftb b = bterm2otrue b.
Proof.
introv e i.
pose proof (isotrue_oball_map_wftb_implies bs b) as h.
repeat (autodimp h hyp);[rw e;apply isotrue_oball_map_bterm2otrue|].
destruct b; allsimpl.
apply isotrue_wft_implies_eq_term2otrue; auto.
Qed.
Lemma no_vars_like_b_true_iff {o} :
forall (t : @NTerm o), no_vars_like_b t = true <=> (closed t # noutokens t).
Proof.
introv; unfold no_vars_like_b, closed, noutokens.
rw @andb_eq_true.
allrw @assert_nullb.
allrw @null_iff_nil; sp.
Qed.
Lemma implies_no_vars_like_b_true {o} :
forall (t : @NTerm o),
closed t
-> noutokens t
-> no_vars_like_b t = true.
Proof.
introv cl nu.
apply no_vars_like_b_true_iff; sp.
Qed.
Lemma nt_wf_eq {p} :
forall (t : @NTerm p),
nt_wf t <=> wf_term t.
Proof.
unfold wf_term.
nterm_ind t as [|f ind|o lbt ind] Case; simpl; intros.
- Case "vterm".
split; sp.
- Case "sterm".
split_iff SCase.
+ SCase "->".
introv wf.
inversion wf as [|g imp|]; subst.
f_equal.
apply functional_extensionality.
introv.
pose proof (imp x) as h; clear imp; repnd.
rw @implies_no_vars_like_b_true; simpl; auto.
apply ind; auto.
+ SCase "<-".
introv wf.
constructor; introv.
inversion wf as [w]; clear wf.
apply equal_f with (x := n) in w.
remember (no_vars_like_b (f n)) as nv; symmetry in Heqnv; destruct nv; allsimpl.
* apply no_vars_like_b_true_iff in Heqnv; repnd; dands; auto.
apply ind in w; dands; auto.
* symmetry in w; apply term2otrue_not_ofalse in w; sp.
- Case "oterm".
split_iff SCase.
+ SCase "->"; intro w.
inversion w as [|?|? ? imp e]; subst.
allrw.
rewrite beq_list_refl; simpl.
f_equal.
apply eq_maps; introv i.
destruct x as [l t]; simpl.
applydup ind in i.
applydup imp in i.
inversion i1 as [? ? ntw]; subst; clear i1.
apply i0 in ntw; auto.
+ SCase "<-".
introv q.
remember (beq_list eq_nat_dec (map num_bvars lbt) (OpBindings o)) as b.
symmetry in Heqb.
destruct b; allsimpl; tcsp;
[|symmetry in q; apply oball_ofalse in q; allrw in_map_iff; exrepnd;
destruct a; allsimpl;
symmetry in q0; apply term2otrue_not_ofalse in q0; sp].
constructor; tcsp.
{ introv i.
destruct l as [l t].
constructor.
applydup ind in i.
apply i0.
eapply oball_map_wftb_eq_otrue_implies in q;[|exact i].
allsimpl; auto. }
apply assert_beq_list in Heqb; auto.
Qed.
Lemma nt_wf_implies {p} :
forall (t : @NTerm p), nt_wf t -> wf_term t.
Proof.
sp; apply nt_wf_eq; sp.
Qed.
Lemma wf_term_eq {p} :
forall (t : @NTerm p), wf_term t <=> nt_wf t.
Proof.
intro; generalize (nt_wf_eq t); sp.
symm; auto.
Qed.
Lemma bt_wf_eq {p} :
forall (bt : @BTerm p), bt_wf bt <=> wf_bterm bt.
Proof.
sp; split; intro w.
inversion w; subst; unfold wf_bterm; simpl.
fold (wf_term nt).
apply wf_term_eq; auto.
destruct bt; allunfold (@wf_bterm p); allsimpl.
fold (wf_term n) in w.
constructor.
apply nt_wf_eq; auto.
Qed.
(*
Inductive nt_wfb (t:NTerm) : bool :=
match t with
| vterm _ => true
| bterm _ rt => nt_wfb rt
| oterm o lnt : (eq map (num_bvars) lnt OpBindings o).
*)
Definition closedb {p} (t : @NTerm p) : bool := nullb (free_vars(t)).
Definition closed_bt {p} (bt : @BTerm p) := free_vars_bterm bt = [].
(* end hide *)
Definition isprogram_bt {p} (bt : @BTerm p) := closed_bt bt # bt_wf bt.
(** Our definition [isprog] below is is logically equivalent to [isprogram],
but unlike [isprogram], it is easy to prove that
for any [t], all members(proofs) of [isprog t] are equal.
An interested reader can look at the lemma
%\coqexternalref{UIP\_dec}
{http://coq.inria.fr/distrib/8.4pl2/stdlib/Coq.Logic.Eqdep\_dec}
{\coqdocdefinition{UIP\_dec}}% from that standard library.
As mentioned before, clicking on the lemma name in
the previous sentence should open
the corresponding webpage of the Coq standard library.
Instead, one can also look at the lemma [isprog_eq] below and
safely ignore these technicalites.
*)
Definition isprog {p} (t : @NTerm p) :=
assert (nullb (free_vars t)) # wf_term t.
(* begin hide *)
Definition isprog_bt {p} (bt : @BTerm p) :=
assert (nullb (free_vars_bterm bt)) # wf_bterm bt.
Definition isprog_vars {p} (vs : list NVar) (t : @NTerm p) :=
assert (sub_vars (free_vars t) vs) # wf_term t.
Lemma closed_nt {p} :
forall (op : @Opid p) bts,
closed (oterm op bts)
<=>
forall bt, LIn bt bts -> closed_bt bt.
Proof.
sp; unfold closed, closed_bt; simpl; trw flat_map_empty; split; sp.
Qed.
Lemma closed_nt0 {p} :
forall (o : @Opid p) nt, closed (oterm o [bterm [] nt]) -> closed nt.
Proof.
intros. unfold closed in H. simpl in H. apply app_eq_nil in H. repnd.
clears_last. rewrite remove_var_nil in H0. auto.
Qed.
Lemma closed_null_free_vars {p} :
forall (t : @NTerm p),
closed t <=> null (free_vars t).
Proof.
unfold closed; sp.
trw null_iff_nil; sp.
Qed.
Lemma isprog_proof_irrelevance {p} :
forall (t : @NTerm p),
forall x y : isprog t,
x = y.
Proof.
intros.
destruct x, y.
f_equal; apply UIP.
Qed.
Hint Extern 0 =>
let h := fresh "h" in
match goal with
| [ H1 : isprog ?t , H2 : isprog ?t |- _ ] =>
pose proof (isprog_proof_irrelevance t H2 H1) as h; subst
end : pi.
Lemma isprog_vars_proof_irrelevance {p} :
forall (t : @NTerm p) vs,
forall x y : isprog_vars vs t,
x = y.
Proof.
intros.
destruct x, y.
f_equal; apply UIP.
Qed.
Hint Extern 0 =>
let h := fresh "h" in
match goal with
| [ H1 : isprog_vars ?vs ?t , H2 : isprog_vars ?vs ?t |- _ ] =>
pose proof (isprog_vars_proof_irrelevance t vs H2 H1) as h; subst
end : pi.
Ltac irr_step :=
match goal with
| [ H1 : isprog ?a, H2 : isprog ?a |- _ ] =>
assert (H2 = H1) by apply isprog_proof_irrelevance; subst
| [ H1 : isprog_vars ?vs ?a, H2 : isprog_vars ?vs ?a |- _ ] =>
assert (H2 = H1) by apply isprog_vars_proof_irrelevance; subst
end.
Ltac irr := repeat irr_step.
Ltac abs_bool2obool n :=
match goal with
| [ H : context[bool2obool ?b] |- _ ] => remember b as n
end.
Lemma assert_true_iff : assert true <=> True.
Proof.
unfold assert; simpl; split; sp.
Qed.
Lemma assert_false_iff : assert false <=> False.
Proof.
unfold assert; simpl; split; sp.
Qed.
Lemma isprogram_eq {p} :
forall (t : @NTerm p),
isprogram t <=> isprog t.
Proof.
unfold isprog, isprogram.
nterm_ind t as [v|f ind|op bs ind] Case; simpl; intros.
- Case "vterm".
rw assert_false_iff.
rw @wf_term_eq.
unfold closed; simpl.
split; intro h; repnd; dands; tcsp.
- Case "sterm".
rw @wf_term_eq.
rw assert_true_iff.
split; intro h; repnd; dands; allsimpl; tcsp.
- Case "oterm".
rw @wf_term_eq.
rw @assert_nullb.
allrw null_iff_nil.
split_iff SCase; tcsp.
Qed.
Lemma isprogram_implies {p} :
forall (t : @NTerm p), isprogram t -> isprog t.
Proof.
sp; apply isprogram_eq; sp.
Qed.
Lemma isprog_implies {p} :
forall t : @NTerm p, isprog t -> isprogram t.
Proof.
sp; apply isprogram_eq; sp.
Qed.
(* end hide *)
Lemma isprog_eq {p} :
forall (t : @NTerm p), isprog t <=> isprogram t.
Proof.
intro; symm; apply isprogram_eq; auto.
Qed.
(* begin hide *)
Lemma isprogram_bt_eq {p} :
forall (bt : @BTerm p),
isprogram_bt bt <=> isprog_bt bt.
Proof.
introv; unfold isprogram_bt, isprog_bt, closed_bt; split; intro h;
repnd; dands; auto.
- allrw; simpl.
apply assert_true_iff; auto.
- apply bt_wf_eq; auto.
- allrw assert_nullb.
allrw null_iff_nil; auto.
- apply bt_wf_eq; auto.
Qed.
Lemma isprog_vars_eq {p} :
forall (t : @NTerm p) vs,
isprog_vars vs t <=> subvars (free_vars t) vs # nt_wf t.
Proof.
unfold isprog_vars; sp.
rw @nt_wf_eq; sp.
Qed.
Lemma isprog_vars_if_isprog {p} :
forall vs (t : @NTerm p), isprog t -> isprog_vars vs t.
Proof.
introv ip.
rw @isprog_vars_eq.
rw @isprog_eq in ip.
destruct ip; sp.
allunfold @closed; allrw; sp.
Qed.
Lemma isprog_vars_app_l {p} :
forall (t : @NTerm p) vs1 vs2,
isprog_vars vs2 t
-> isprog_vars (vs1 ++ vs2) t.
Proof.
sp; alltrewrite (@isprog_vars_eq p); sp.
alltrewrite subvars_eq.
apply subset_app_l; sp.
Qed.
Definition areprograms {p} (ts : list (@NTerm p)) :=
forall t, LIn t ts -> isprogram t.
Lemma areprograms_nil {p} : @areprograms p [].
Proof.
unfold areprograms; simpl; sp.
Qed.
Lemma areprograms_snoc {p} :
forall (t : @NTerm p) ts,
areprograms (snoc ts t) <=> areprograms ts # isprogram t.
Proof.
unfold areprograms; sp; split; sp; try (apply_hyp; rw in_snoc; sp).
alltrewrite in_snoc; sp; subst; sp.
Qed.
Lemma areprograms_cons {p} :
forall (t : @NTerm p) ts, areprograms (t :: ts) <=> isprogram t # areprograms ts.
Proof.
unfold areprograms; sp; simpl; split; sp; subst; sp.
Qed.
Lemma areprograms_app {p} :
forall (ts1 ts2 : list (@NTerm p)),
areprograms (ts1 ++ ts2) <=> areprograms ts1 # areprograms ts2.
Proof.
unfold areprograms; sp; split; sp.
apply_hyp; rw in_app_iff; sp.
apply_hyp; rw in_app_iff; sp.
alltrewrite in_app_iff; sp.
Qed.
Lemma isprogram_vterm {p} :
forall v, @isprogram p (vterm v) <=> False.
Proof.
unfold isprogram, closed; simpl; sp; split; sp.
Qed.
(*
Ltac repnd :=
repeat match goal with
| [ H : _ # _ |- _ ] =>
let name := fresh H in destruct H as [name H]
| [ H : _ # _ |- _ ] =>
let name := fresh H in destruct H as [name H]
end.
*)
Theorem isprogram_ot_iff {p} :
forall (o : @Opid p) bts,
isprogram (oterm o bts)
<=>
(map num_bvars bts = OpBindings o
# forall bt, LIn bt bts -> isprogram_bt bt).
Proof.
intros. sp_iff Case.
- Case "->".
intros Hisp.
unfold isprogram in Hisp. repnd.
inverts Hisp0 as Hflat. inverts Hisp.
split;auto. intros bt Hin.
unfold isprogram_bt.
rw flat_map_empty in Hflat.
apply_in_hyp pp; sp.
- Case "<-".
intros eq; destruct eq as [Hmap Hstclose].
unfold isprogram, closed.
split; try (constructor); auto;
try (simpl; apply flat_map_empty);
intros a ain;
apply Hstclose in ain; inversion ain; sp.
Qed.
Theorem nt_wf_ot_implies {p} :
forall lv (o : @Opid p) nt1 bts,
nt_wf (oterm o bts)
-> LIn (bterm lv nt1) bts
-> nt_wf nt1.
Proof. intros ? ? ? ? Hwf Hin. inverts Hwf as Hwf Hmap.
assert (bt_wf (bterm lv nt1)) as Hbf by (apply Hwf; auto).
inverts Hbf. auto.
Qed.
Lemma newvar_prop {p} :
forall (t : @NTerm p), ! LIn (newvar t) (free_vars t).
Proof.
unfold newvar; sp.
allapply fresh_var_not_in; sp.
Qed.
Lemma newvar_not_in_free_vars {p} :
forall (t : @NTerm p),
! LIn nvarx (free_vars t)
-> newvar t = nvarx.
Proof.
sp.
unfold newvar.
apply fresh_var_nvarx; sp.
Qed.
Lemma newvar_prog {p} :
forall (t : @NTerm p),
isprog t
-> newvar t = nvarx.
Proof.
sp.
unfold newvar.
apply isprog_eq in H.
inversion H.
unfold closed in H0.
rewrite H0; sp.
Qed.
Definition mk_vsubtype {p} (A : @NTerm p) v B := mk_member mk_id (mk_function A v B).
Definition mk_subtype {p} (A : @NTerm p) B := mk_vsubtype A (newvar B) B.
(* non-dependent function type *)
Definition mk_fun {p} (A B : @NTerm p) := mk_function A (newvar B) B.
(* non-dependent uniform function type *)
Definition mk_ufun {p} (A B : @NTerm p) := mk_isect A (newvar B) B.
(* non-dependent extensional uniform function type *)
Definition mk_eufun {p} (A B : @NTerm p) := mk_eisect A (newvar B) B.
(* non-dependent product type *)
Definition mk_prod {p} (A B : @NTerm p) := mk_product A (newvar B) B.
Definition mk_subtype_rel {p} (A B : @NTerm p) := mk_member mk_id (mk_fun A B).
Definition mk_iff {p} (a b : @NTerm p) := mk_prod (mk_fun a b) (mk_fun b a).
Definition mk_not {p} (P : @NTerm p) := mk_fun P mk_void.
Definition mk_le {p} (a b : @NTerm p) := mk_not (mk_less_than b a).
Definition mk_tnat {p} : @NTerm p := mk_set mk_int nvary (mk_le mk_zero (mk_var nvary)).
Definition mk_nat_sub {p} n : @NTerm p :=
mk_set mk_tnat nvarx (mk_less_than (mk_var nvarx) n).
Definition mk_dec {p} (P : @NTerm p) := mk_or P (mk_not P).
Definition mk_plus1 {p} n : @NTerm p := mk_add n mk_one.
(** A value is a program with a canonical operator *)
Inductive isvalue {p} : @NTerm p -> Type :=
| isv_can :
forall t,
isprogram t
-> iscan t
-> isvalue t.
Hint Constructors isvalue.
Inductive isovalue {p} : @NTerm p -> Prop :=
| isovl :
forall t,
nt_wf t
-> iscan t
-> isovalue t.
Hint Constructors isovalue.
Lemma isvalue_closed {p} :
forall (t : @NTerm p), isvalue t -> closed t.
Proof.
introv isv; inversion isv; allunfold @isprogram; sp.
Qed.
Lemma isvalue_program {p} :
forall (t : @NTerm p), isvalue t -> isprogram t.
Proof.
introv isv; inversion isv; sp.
Qed.
Lemma isvalue_mk_lam {p} :
forall v (b : @NTerm p), isprog_vars [v] b -> isvalue (mk_lam v b).
Proof.
intros; repeat constructor; simpl; sp; subst.
rw @isprog_vars_eq in H; sp.
unfold closed; simpl; rewrite app_nil_r.
rw <- null_iff_nil.
rw null_remove_nvars; simpl; sp.
allrw subvars_eq.
allrw subset_singleton_r.
unfold subset in H0; allsimpl.
apply_in_hyp pp; sp.
rw @isprog_vars_eq in H; sp.
Qed.
Lemma isvalue_mk_int {p} : @isvalue p mk_int.
Proof.
repeat constructor; simpl; sp.
Qed.
Theorem isprogram_int {p} : @isprogram p mk_int.
Proof.
repeat constructor; simpl; sp.
Qed.
Theorem isprog_int {p} : @isprog p mk_int.
Proof.
repeat constructor.
Qed.
Theorem wf_int {p} : @wf_term p mk_int.
Proof.
sp.
Qed.
Lemma isprogram_mk_integer {p} : forall n : Z, @isprogram p (mk_integer n).
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isprog_mk_integer' {p} : forall n : Z, @isprog p (mk_integer n).
Proof.
repeat constructor.
Qed.
Definition isprog_mk_integer {p} : forall n : Z, @isprog p (mk_integer n)
:= fun _ => (eq_refl,eq_refl).
Lemma isvalue_mk_integer {p} : forall n : Z, @isvalue p (mk_integer n).
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isovalue_mk_integer {p} : forall n : Z, @isovalue p (mk_integer n).
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma wf_mk_integer' {p} : forall n : Z, @wf_term p (mk_integer n).
Proof.
sp.
Qed.
Definition wf_mk_integer {p} : forall n : Z, @wf_term p (mk_integer n)
:= fun _ => eq_refl.
Lemma isprogram_mk_nat {p} : forall n : nat, @isprogram p (mk_nat n).
Proof.
unfold mk_nat.
intros; apply isprogram_mk_integer.
Qed.
Lemma isprog_mk_nat' {p} : forall n : nat, @isprog p (mk_nat n).
Proof.
unfold mk_nat.
intros; apply isprog_mk_integer.
Qed.
Definition isprog_mk_nat {p} : forall n : nat, @isprog p (mk_nat n)
:= fun _ => (eq_refl,eq_refl).
Lemma isvalue_mk_nat {p} : forall n : nat, @isvalue p (mk_nat n).
Proof.
unfold mk_nat.
intros; apply isvalue_mk_integer.
Qed.
Lemma isovalue_mk_nat {p} : forall n : nat, @isovalue p (mk_nat n).
Proof.
unfold mk_nat.
intros; apply isovalue_mk_integer.
Qed.
Lemma wf_mk_nat' {p} : forall n : nat, @wf_term p (mk_nat n).
Proof.
sp.
Qed.
Definition wf_mk_nat {p} : forall n : nat, @wf_term p (mk_nat n)
:= fun _ => eq_refl.
Lemma isprogram_mk_nseq {p} : forall f : nseq, @isprogram p (mk_nseq f).
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isprog_mk_nseq {p} : forall f : nseq, @isprog p (mk_nseq f).
Proof.
repeat constructor.
Qed.
Lemma isvalue_mk_nseq {p} : forall f : nseq, @isvalue p (mk_nseq f).
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isvalue_token {p} : forall s : String.string, @isvalue p (mk_token s).
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isvalue_utoken {p} : forall u : get_patom_set p, @isvalue p (mk_utoken u).
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isvalue_atom {p} : @isvalue p mk_atom.
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isvalue_uatom {p} : @isvalue p mk_uatom.
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isprogram_mk_uni {p} : forall n : nat, @isprogram p (mk_uni n).
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Lemma isprog_mk_uni {p} : forall n : nat, @isprog p (mk_uni n).
Proof.
repeat constructor.
Qed.
Lemma isvalue_mk_uni {p} : forall n : nat, @isvalue p (mk_uni n).
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Lemma wf_mk_uni {p} : forall n : nat, @wf_term p (mk_uni n).
Proof.
sp.
Qed.
Lemma wf_mk_var {p} : forall v, @wf_term p (mk_var v).
Proof.
sp.
Qed.
Lemma isprogram_axiom {p} : @isprogram p mk_axiom.
Proof.
repeat constructor; simpl; sp.
Qed.
Theorem isprog_axiom {p} : @isprog p mk_axiom.
Proof.
repeat constructor.
Qed.
Theorem isprog_bottom {p} : @isprog p mk_bottom.
Proof.
repeat constructor.
Qed.
Lemma isprogram_bottom {p} : @isprogram p mk_bottom.
Proof.
rw @isprogram_eq. repeat constructor.
Qed.
Theorem isvalue_axiom {p} : @isvalue p mk_axiom.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Theorem wf_axiom {p} : @wf_term p mk_axiom.
Proof.
sp.
Qed.
Theorem isprogram_base {p} : @isprogram p mk_base.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Theorem isprog_base {p} : @isprog p mk_base.
Proof.
repeat constructor.
Qed.
Lemma isvalue_base {p} : @isvalue p mk_base.
Proof.
repeat constructor; simpl; sp.
Qed.
Lemma wf_base {p} : @wf_term p mk_base.
Proof.
sp.
Qed.
Hint Immediate isvalue_mk_int.
Hint Immediate isprogram_int.
Hint Immediate isprog_int.
Hint Immediate wf_int : wf.
Hint Immediate isvalue_axiom.
Hint Immediate isprogram_axiom.
Hint Immediate isprog_axiom.
Hint Immediate isprog_bottom.
Hint Immediate isprogram_bottom.
Hint Immediate wf_axiom : wf.
Hint Immediate isvalue_base.
Hint Immediate isprogram_base.
Hint Immediate isprog_base.
Hint Immediate wf_base : wf.
Theorem wf_pertype {p} :
forall (a : @NTerm p), wf_term a -> wf_term (mk_pertype a).
Proof.
intros.
apply nt_wf_eq; apply nt_wf_eq in H.
intros; inversion H; subst;
constructor; allsimpl; sp;
subst; auto; constructor; auto.
Qed.
Lemma isprogram_pertype {p} :
forall (a : @NTerm p), isprogram a -> isprogram (mk_pertype a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl; sp.
apply nt_wf_eq.
allrw @nt_wf_eq.
apply wf_pertype; sp.
Qed.
Lemma isprogram_pertype_iff {p} :
forall (a : @NTerm p), isprogram a <=> isprogram (mk_pertype a).
Proof.
intros; split; intro i.
apply isprogram_pertype; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
inversion w as [|?|o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Lemma isprog_pertype {p} :
forall (a : @NTerm p), isprog a -> isprog (mk_pertype a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_pertype; auto.
Qed.
Theorem wf_partial {p} :
forall (a : @NTerm p), wf_term a -> wf_term (mk_partial a).
Proof.
intros.
apply nt_wf_eq; apply nt_wf_eq in H.
intros; inversion H; subst;
constructor; allsimpl; sp;
subst; auto; constructor; auto.
Qed.
Theorem isprogram_partial {p} :
forall (a : @NTerm p), isprogram a -> isprogram (mk_partial a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl; sp.
apply nt_wf_eq.
allrw @nt_wf_eq.
apply wf_partial; sp.
Qed.
Lemma isprogram_partial_iff {p} :
forall (a : @NTerm p), isprogram a <=> isprogram (mk_partial a).
Proof.
intros; split; intro i.
apply isprogram_partial; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Theorem isprog_partial {p} :
forall (a : @NTerm p), isprog a -> isprog (mk_partial a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_partial; auto.
Qed.
Theorem isprogram_admiss {p} :
forall (a : @NTerm p), isprogram a -> isprogram (mk_admiss a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl; sp.
apply nt_wf_eq.
allrw @nt_wf_eq.
apply wf_partial; sp.
Qed.
Lemma isprogram_admiss_iff {p} :
forall (a : @NTerm p), isprogram a <=> isprogram (mk_admiss a).
Proof.
intros; split; intro i.
apply isprogram_admiss; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Theorem isprog_admiss {p} :
forall (a : @NTerm p), isprog a -> isprog (mk_admiss a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_admiss; auto.
Qed.
Theorem isprogram_mono {p} :
forall (a : @NTerm p), isprogram a -> isprogram (mk_mono a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl; sp.
apply nt_wf_eq.
allrw @nt_wf_eq.
apply wf_partial; sp.
Qed.
Lemma isprogram_mono_iff {p} :
forall (a : @NTerm p), isprogram a <=> isprogram (mk_mono a).
Proof.
intros; split; intro i.
apply isprogram_mono; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Theorem isprog_mono {p} :
forall (a : @NTerm p), isprog a -> isprog (mk_mono a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_mono; auto.
Qed.
Theorem wf_ipertype {p} :
forall (a : @NTerm p), wf_term a -> wf_term (mk_ipertype a).
Proof.
intros.
apply nt_wf_eq; apply nt_wf_eq in H.
intros; inversion H; subst;
constructor; allsimpl; sp;
subst; auto; constructor; auto.
Qed.
Theorem isprogram_ipertype {p} :
forall (a : @NTerm p), isprogram a -> isprogram (mk_ipertype a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
rewrite X0; simpl.
rewrite remove_nvars_nil_r; sp.
apply nt_wf_eq.
apply nt_wf_eq in X.
apply wf_pertype; sp.
Qed.
Lemma isprogram_ipertype_iff {p} :
forall (a : @NTerm p), isprogram a <=> isprogram (mk_ipertype a).
Proof.
intros; split; intro i.
apply isprogram_ipertype; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Theorem isprog_ipertype {p} :
forall (a : @NTerm p), isprog a -> isprog (mk_ipertype a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_ipertype; auto.
Qed.
Theorem wf_ipertype_iff {p} :
forall (a : @NTerm p), wf_term a <=> wf_term (mk_ipertype a).
Proof.
intros; split; intro i.
apply wf_ipertype; sp.
allrw @wf_term_eq.
inversion i as [|?|o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)); intro j.
repeat (dest_imp j hyp).
inversion j; subst; sp.
Qed.
Lemma isprog_vars_ipertype {p} :
forall (f : @NTerm p) vs,
isprog_vars vs (mk_ipertype f) <=> isprog_vars vs f.
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw @remove_nvars_nil_l).
rw @app_nil_r.
allrw <- @wf_term_eq.
allrw <- @wf_ipertype_iff; split; sp.
Qed.
Theorem wf_spertype {p} :
forall (a : @NTerm p), wf_term a -> wf_term (mk_spertype a).
Proof.
intros.
apply nt_wf_eq; apply nt_wf_eq in H.
intros; inversion H; subst;
constructor; allsimpl; sp;
subst; auto; constructor; auto.
Qed.
Theorem isprogram_spertype {p} :
forall (a : @NTerm p), isprogram a -> isprogram (mk_spertype a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
rewrite X0; simpl.
rewrite remove_nvars_nil_r; sp.
apply nt_wf_eq.
apply nt_wf_eq in X.
apply wf_pertype; sp.
Qed.
Lemma isprogram_spertype_iff {p} :
forall (a : @NTerm p), isprogram a <=> isprogram (mk_spertype a).
Proof.
intros; split; intro i.
apply isprogram_spertype; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Theorem isprog_spertype {p} :
forall (a : @NTerm p), isprog a -> isprog (mk_spertype a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_spertype; auto.
Qed.
Theorem wf_spertype_iff {p} :
forall (a : @NTerm p), wf_term a <=> wf_term (mk_spertype a).
Proof.
intros; split; intro i.
apply wf_spertype; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)); intro j.
repeat (dest_imp j hyp).
inversion j; subst; sp.
Qed.
Lemma isprog_vars_spertype {p} :
forall (f : @NTerm p) vs,
isprog_vars vs (mk_spertype f) <=> isprog_vars vs f.
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw @remove_nvars_nil_l).
rw @app_nil_r.
allrw <- @wf_term_eq.
allrw <- @wf_spertype_iff; split; sp.
Qed.
Lemma wf_tuni {p} :
forall (a : @NTerm p), wf_term a -> wf_term (mk_tuni a).
Proof.
introv h.
apply nt_wf_eq; apply nt_wf_eq in h.
intros; inversion h; subst;
constructor; allsimpl; sp;
subst; auto; simpl; constructor; auto.
Qed.
Lemma isprogram_tuni {p} :
forall (a : @NTerm p), isprogram a -> isprogram (mk_tuni a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl; sp.
apply nt_wf_eq.
allrw @nt_wf_eq.
apply wf_tuni; sp.
Qed.
Lemma isprogram_tuni_iff {p} :
forall (a: @NTerm p), isprogram a <=> isprogram (mk_tuni a).
Proof.
intros; split; intro i.
apply isprogram_tuni; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Lemma isprog_tuni {p} :
forall (a : @NTerm p), isprog a -> isprog (mk_tuni a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_tuni; auto.
Qed.
Theorem wf_tuni_iff {p} :
forall (a : @NTerm p), wf_term a <=> wf_term (mk_tuni a).
Proof.
intros; split; intro i.
apply wf_tuni; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)); intro j.
repeat (dest_imp j hyp).
inversion j; subst; sp.
Qed.
Lemma isprog_vars_tuni {p} :
forall (f : @NTerm p) vs,
isprog_vars vs (mk_tuni f) <=> isprog_vars vs f.
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw @remove_nvars_nil_l).
rw @app_nil_r.
allrw <- @wf_term_eq.
allrw <- @wf_tuni_iff; split; sp.
Qed.
(*
Theorem wf_esquash :
forall a, wf_term a -> wf_term (mk_esquash a).
Proof.
intros.
apply nt_wf_eq; apply nt_wf_eq in H.
intros; inversion H; subst;
constructor; allsimpl; sp;
subst; auto; constructor; auto.
Qed.
Theorem isprogram_esquash :
forall a, isprogram a -> isprogram (mk_esquash a).
Proof.
sp; allunfold isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold closed.
rewrite X0; simpl.
rewrite remove_nvars_nil_r; sp.
apply nt_wf_eq.
apply nt_wf_eq in X.
apply wf_pertype; sp.
Qed.
Theorem isprog_esquash :
forall a, isprog a -> isprog (mk_esquash a).
Proof.
sp.
allrw isprog_eq.
apply isprogram_esquash; auto.
Qed.
*)
Theorem wf_image {p} :
forall (a b : @NTerm p), wf_term a -> wf_term b -> wf_term (mk_image a b).
Proof.
intros a b; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_image_iff {p} :
forall (a b : @NTerm p), (wf_term a # wf_term b) <=> wf_term (mk_image a b).
Proof.
intros; split; intro k.
apply wf_image; sp.
allrw <- @nt_wf_eq.
inversion k as [|?|i j u w]; subst; allsimpl.
generalize (u (nobnd a)) (u (nobnd b)); intros i1 i2.
dest_imp i1 hyp.
dest_imp i2 hyp.
inversion i1; subst; inversion i2; subst; sp.
Qed.
Lemma isprogram_image {p} :
forall (a b : @NTerm p), isprogram a -> isprogram b -> isprogram (mk_image a b).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl.
rewrite remove_nvars_nil_r; sp.
allrw @nt_wf_eq.
apply wf_image; sp.
Qed.
Lemma isprogram_image_iff {p} :
forall (a b : @NTerm p), (isprogram a # isprogram b) <=> isprogram (mk_image a b).
Proof.
sp; split; intro k; try (apply isprogram_image; sp).
inversion k as [c w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repd.
unfold isprogram, closed; allrw.
inversion w as [|?|o lnt i meq ]; subst; allsimpl.
generalize (i (nobnd a)) (i (nobnd b)); intros e1 e2.
dest_imp e1 hyp.
dest_imp e2 hyp.
inversion e1; subst.
inversion e2; subst; sp.
Qed.
Theorem isprog_image {p} :
forall (a b : @NTerm p), isprog a -> isprog b -> isprog (mk_image a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_image; auto.
Qed.
Theorem wf_apply {p} :
forall (a b : @NTerm p), wf_term a -> wf_term b -> wf_term (mk_apply a b).
Proof.
intros a b; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma isprogram_apply {p} :
forall (a b : @NTerm p), isprogram a -> isprogram b -> isprogram (mk_apply a b).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl.
rewrite remove_nvars_nil_r; sp.
allrw @nt_wf_eq.
apply wf_apply; sp.
Qed.
Lemma isprogram_apply_iff {p} :
forall (a b : @NTerm p), (isprogram a # isprogram b) <=> isprogram (mk_apply a b).
Proof.
sp; split; intro k; try (apply isprogram_apply; sp).
inversion k as [c w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repd.
unfold isprogram, closed; allrw.
inversion w as [|?| o lnt i meq ]; subst; allsimpl.
generalize (i (nobnd a)) (i (nobnd b)); intros e1 e2.
dest_imp e1 hyp.
dest_imp e2 hyp.
inversion e1; subst.
inversion e2; subst; sp.
Qed.
Theorem isprog_apply {p} :
forall (a b : @NTerm p), isprog a -> isprog b -> isprog (mk_apply a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_apply; auto.
Qed.
Theorem wf_apply2 {p} :
forall (f a b : @NTerm p),
wf_term f -> wf_term a -> wf_term b -> wf_term (mk_apply2 f a b).
Proof.
unfold mk_apply2; sp.
repeat (apply wf_apply); auto.
Qed.
Theorem isprogram_apply2 {p} :
forall (f a b : @NTerm p),
isprogram f -> isprogram a -> isprogram b -> isprogram (mk_apply2 f a b).
Proof.
unfold mk_apply2; sp.
repeat (apply isprogram_apply); auto.
Qed.
Theorem isprog_apply2 {p} :
forall (f a b : @NTerm p),
isprog f -> isprog a -> isprog b -> isprog (mk_apply2 f a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_apply2; auto.
Qed.
Theorem wf_eapply {p} :
forall (a b : @NTerm p), wf_term a -> wf_term b -> wf_term (mk_eapply a b).
Proof.
intros a b; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma isprogram_eapply {p} :
forall (a b : @NTerm p), isprogram a -> isprogram b -> isprogram (mk_eapply a b).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl.
rewrite remove_nvars_nil_r; sp.
allrw @nt_wf_eq.
apply wf_eapply; sp.
Qed.
Lemma isprogram_eapply_iff {p} :
forall (a b : @NTerm p), (isprogram a # isprogram b) <=> isprogram (mk_eapply a b).
Proof.
sp; split; intro k; try (apply isprogram_eapply; sp).
inversion k as [c w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repd.
unfold isprogram, closed; allrw.
inversion w as [|?| o lnt i meq ]; subst; allsimpl.
generalize (i (nobnd a)) (i (nobnd b)); intros e1 e2.
dest_imp e1 hyp.
dest_imp e2 hyp.
inversion e1; subst.
inversion e2; subst; sp.
Qed.
Theorem isprog_eapply {p} :
forall (a b : @NTerm p), isprog a -> isprog b -> isprog (mk_eapply a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_eapply; auto.
Qed.
Lemma wf_apseq {p} :
forall f (a : @NTerm p), wf_term a -> wf_term (mk_apseq f a).
Proof.
introv w; allrw <- @nt_wf_eq.
constructor; simpl; tcsp; introv k; sp; subst; constructor; auto.
Qed.
Lemma isprogram_apseq {p} :
forall f (a : @NTerm p), isprogram a -> isprogram (mk_apseq f a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl.
rewrite remove_nvars_nil_r; sp.
allrw @nt_wf_eq.
apply wf_apseq; sp.
Qed.
Lemma isprogram_apseq_iff {p} :
forall f (a : @NTerm p), isprogram a <=> isprogram (mk_apseq f a).
Proof.
sp; split; intro k; try (apply isprogram_apseq; sp).
inversion k as [c w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repd.
unfold isprogram, closed; allrw.
inversion w as [|?| o lnt i meq ]; subst; allsimpl.
generalize (i (nobnd a)); intros e1.
dest_imp e1 hyp.
inversion e1; subst; sp.
Qed.
Lemma isprog_apseq {p} :
forall f (a : @NTerm p), isprog a -> isprog (mk_apseq f a).
Proof.
sp; allrw @isprog_eq.
apply isprogram_apseq; auto.
Qed.
(**useful for rewriting in complicated formulae*)
Theorem bt_wf_iff {p} :
forall lv (nt : @NTerm p),
bt_wf (bterm lv nt)
<=> nt_wf nt.
Proof. sp_iff Case; introv H.
Case "->". inverts H as Hwf; auto.
Case "<-". constructor; auto.
Qed.
Theorem wf_parallel {p} :
forall (a b : @NTerm p),
wf_term a
-> wf_term b
-> wf_term (mk_parallel a b).
Proof.
introv wa wb.
repeat (rw <- @nt_wf_eq).
constructor; allsimpl.
- introv i; repndors; tcsp; subst; allrw @bt_wf_iff; allrw @nt_wf_eq; auto.
- unfold num_bvars; simpl; auto.
Qed.
Lemma isprogram_parallel {p} :
forall (a b : @NTerm p),
isprogram a
-> isprogram b
-> isprogram (mk_parallel a b).
Proof.
introv pa pb.
destruct pa as [ca wa].
destruct pb as [cb wb].
constructor.
- unfold closed; simpl; allrw remove_nvars_nil_l; allrw app_nil_r.
rw ca; rw cb; auto.
- rw @nt_wf_eq; apply wf_parallel; rw <- @nt_wf_eq; auto.
Qed.
Lemma isprogram_parallel_iff {p} :
forall (a b : @NTerm p),
isprogram (mk_parallel a b) <=> (isprogram a # isprogram b).
Proof.
introv; split; intro k; try (apply isprogram_parallel; sp).
inversion k as [c w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
apply app_eq_nil_iff in c; repnd.
unfold isprogram; unfold closed; rw c0; rw c.
inversion w as [|?| o lnt i meq ]; subst; allsimpl; clear w.
pose proof (i (nobnd a)) as h1; pose proof (i (nobnd b)) as h2.
autodimp h1 hyp; autodimp h2 hyp.
allrw @bt_wf_iff.
dands; auto.
Qed.
Theorem isprog_parallel {p} :
forall (a b : @NTerm p),
isprog a
-> isprog b
-> isprog (mk_parallel a b).
Proof.
introv pa pb; allrw @isprog_eq.
apply isprogram_parallel; auto.
Qed.
Theorem closed_approx {p} :
forall (a b : @NTerm p), closed a -> closed b -> closed (mk_approx a b).
Proof.
intros.
allunfold @closed; unfold mk_approx; simpl.
allrw; simpl; auto.
Qed.
Theorem closed_cequiv {p} :
forall (a b : @NTerm p), closed a -> closed b -> closed (mk_cequiv a b).
Proof.
intros.
allunfold @closed; unfold mk_cequiv; simpl.
allrw; simpl; auto.
Qed.
Theorem closed_texc {p} :
forall (a b : @NTerm p),
closed a -> closed b -> closed (mk_texc a b).
Proof.
intros.
allunfold @closed; unfold mk_texc; simpl.
allrw; simpl; auto.
Qed.
Theorem closed_union {p} :
forall (a b : @NTerm p), closed a -> closed b -> closed (mk_union a b).
Proof.
intros.
allunfold @closed; unfold mk_union; simpl.
allrw; simpl; auto.
Qed.
Theorem closed_union2 {p} :
forall (a b : @NTerm p), closed a -> closed b -> closed (mk_union2 a b).
Proof.
intros.
allunfold @closed; unfold mk_union2; simpl.
allrw; simpl; auto.
Qed.
Theorem closed_compute {p} :
forall (a b n : @NTerm p),
closed a -> closed b -> closed n -> closed (mk_compute a b n).
Proof.
intros.
allunfold @closed; unfold mk_compute; simpl.
allrw; simpl; sp.
Qed.
Theorem wf_approx {p} :
forall (a b : @NTerm p), wf_term a -> wf_term b -> wf_term (mk_approx a b).
Proof.
intros a b; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem wf_approx_iff {p} :
forall (a b : @NTerm p), (wf_term a # wf_term b) <=> wf_term (mk_approx a b).
Proof.
sp; split; intros k.
apply wf_approx; sp.
allrw @wf_term_eq.
inversion k as [|?| o lnt i meq ]; subst; allsimpl.
generalize (i (nobnd a)); generalize (i (nobnd b)); intros i1 i2.
dest_imp i1 hyp.
dest_imp i2 hyp.
inversion i1; inversion i2; sp.
Qed.
Lemma isprogram_isinl {p} :
forall (a b c : @NTerm p),
isprogram a
-> isprogram b
-> isprogram c
-> isprogram (mk_isinl a b c).
Proof.
introv ipa ipb ipc.
allunfold @isprogram; repnd; allunfold @closed; simpl; allrw; simpl; sp.
constructor; sp; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma isprogram_isinl_iff {p} :
forall (a b c : @NTerm p),
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_isinl a b c).
Proof.
introv; split; intro i; repnd.
apply isprogram_isinl; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Theorem isprog_isinl {p} :
forall (a b c : @NTerm p),
isprog a
-> isprog b
-> isprog c
-> isprog (mk_isinl a b c).
Proof.
sp; allrw @isprog_eq.
apply isprogram_isinl; auto.
Qed.
Lemma isprogram_isinr {p} :
forall (a b c : @NTerm p),
isprogram a
-> isprogram b
-> isprogram c
-> isprogram (mk_isinr a b c).
Proof.
introv ipa ipb ipc.
allunfold @isprogram; repnd; allunfold @closed; simpl; allrw; simpl; sp.
constructor; sp; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma isprogram_isinr_iff {p} :
forall (a b c : @NTerm p),
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_isinr a b c).
Proof.
introv; split; intro i; repnd.
apply isprogram_isinr; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Theorem isprog_isinr {p} :
forall (a b c : @NTerm p),
isprog a
-> isprog b
-> isprog c
-> isprog (mk_isinr a b c).
Proof.
sp; allrw @isprog_eq.
apply isprogram_isinr; auto.
Qed.
Lemma isprogram_isaxiom {p} :
forall (a b c : @NTerm p),
isprogram a
-> isprogram b
-> isprogram c
-> isprogram (mk_isaxiom a b c).
Proof.
introv ipa ipb ipc.
allunfold @isprogram; repnd; allunfold @closed; simpl; allrw; simpl; sp.
constructor; sp; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma isprogram_isaxiom_iff {p} :
forall (a b c : @NTerm p),
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_isaxiom a b c).
Proof.
introv; split; intro i; repnd.
apply isprogram_isaxiom; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Theorem isprog_isaxiom {p} :
forall (a b c : @NTerm p),
isprog a
-> isprog b
-> isprog c
-> isprog (mk_isaxiom a b c).
Proof.
sp; allrw @isprog_eq.
apply isprogram_isaxiom; auto.
Qed.
Lemma isprogram_islambda {p} :
forall (a b c : @NTerm p),
isprogram a
-> isprogram b
-> isprogram c
-> isprogram (mk_islambda a b c).
Proof.
introv ipa ipb ipc.
allunfold @isprogram; repnd; allunfold @closed; simpl; allrw; simpl; sp.
constructor; sp; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma isprogram_islambda_iff {p} :
forall (a b c : @NTerm p),
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_islambda a b c).
Proof.
introv; split; intro i; repnd.
apply isprogram_islambda; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Theorem isprog_islambda {p} :
forall (a b c : @NTerm p),
isprog a
-> isprog b
-> isprog c
-> isprog (mk_islambda a b c).
Proof.
sp; allrw @isprog_eq.
apply isprogram_islambda; auto.
Qed.
Lemma isprogram_can_test {p} :
forall test (a b c : @NTerm p),
isprogram a
-> isprogram b
-> isprogram c
-> isprogram (mk_can_test test a b c).
Proof.
introv ipa ipb ipc.
allunfold @isprogram; repnd; allunfold @closed; simpl; allrw; simpl; sp.
constructor; sp; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma isprogram_ispair {p} :
forall (a b c : @NTerm p),
isprogram a
-> isprogram b
-> isprogram c
-> isprogram (mk_ispair a b c).
Proof.
introv ipa ipb ipc.
allunfold @isprogram; repnd; allunfold @closed; simpl; allrw; simpl; sp.
constructor; sp; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma isprogram_can_test_iff {p} :
forall test (a b c : @NTerm p),
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_can_test test a b c).
Proof.
introv; split; intro i; repnd.
apply isprogram_can_test; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Theorem isprog_can_test {p} :
forall test (a b c : @NTerm p),
isprog a
-> isprog b
-> isprog c
-> isprog (mk_can_test test a b c).
Proof.
sp; allrw @isprog_eq.
apply isprogram_can_test; auto.
Qed.
Lemma isprogram_ispair_iff {p} :
forall (a b c : @NTerm p),
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_ispair a b c).
Proof.
introv; split; intro i; repnd.
apply isprogram_ispair; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Theorem isprog_ispair {p} :
forall (a b c : @NTerm p),
isprog a
-> isprog b
-> isprog c
-> isprog (mk_ispair a b c).
Proof.
sp; allrw @isprog_eq.
apply isprogram_ispair; auto.
Qed.
Lemma isprogram_approx {p} :
forall (a b : @NTerm p),
isprogram a -> isprogram b -> isprogram (mk_approx a b).
Proof.
intros. allunfold @isprogram. repnd. split. apply closed_approx; auto.
constructor; auto. intros ? Hin.
inverts Hin as [Hgarbage | Hin]; subst;
try (constructor;auto).
inversion Hin.
Qed.
Lemma isprogram_approx_iff {p} :
forall (a b : @NTerm p), (isprogram a # isprogram b) <=> isprogram (mk_approx a b).
Proof.
intros; split; intro i.
apply isprogram_approx; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Theorem isprog_approx {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_approx a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_approx; auto.
Qed.
Theorem wf_cequiv {p} :
forall a b : @NTerm p, wf_term a -> wf_term b -> wf_term (mk_cequiv a b).
Proof.
intros a b; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem isprogram_cequiv {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isprogram (mk_cequiv a b).
Proof.
intros. allunfold @isprogram. repnd. split. apply closed_cequiv; auto.
constructor; auto. intros ? Hin.
inverts Hin as [Hgarbage | Hin]; subst;
try (constructor;auto).
inversion Hin.
Qed.
Lemma isprogram_cequiv_iff {p} :
forall a b : @NTerm p, (isprogram a # isprogram b) <=> isprogram (mk_cequiv a b).
Proof.
intros; split; intro i.
apply isprogram_cequiv; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Theorem isprog_cequiv {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_cequiv a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_cequiv; auto.
Qed.
Theorem isprogram_texc {p} :
forall a b : @NTerm p,
isprogram a -> isprogram b -> isprogram (mk_texc a b).
Proof.
intros. allunfold @isprogram. repnd. split. apply closed_texc; auto.
constructor; auto. intros ? Hin.
allsimpl; repndors; tcsp; subst;
try (constructor;auto).
Qed.
Theorem isprog_texc {p} :
forall a b : @NTerm p,
isprog a -> isprog b -> isprog (mk_texc a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_texc; auto.
Qed.
Theorem isprogram_union {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isprogram (mk_union a b).
Proof.
intros. allunfold @isprogram. repnd. split. apply closed_union; auto.
constructor; auto. intros ? Hin.
inverts Hin as [Hgarbage | Hin]; subst;
try (constructor;auto).
inversion Hin.
Qed.
Theorem isprog_union {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_union a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_union; auto.
Qed.
Theorem isprogram_union2 {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isprogram (mk_union2 a b).
Proof.
intros. allunfold @isprogram. repnd. split. apply closed_union2; auto.
constructor; auto. intros ? Hin.
inverts Hin as [Hgarbage | Hin]; subst;
try (constructor;auto).
inversion Hin.
Qed.
Theorem isprog_union2 {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_union2 a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_union2; auto.
Qed.
Theorem isprogram_compute {p} :
forall a b n : @NTerm p,
isprogram a -> isprogram b -> isprogram n -> isprogram (mk_compute a b n).
Proof.
unfold isprogram, closed; sp; simpl; allrw; allsimpl; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Theorem isprog_compute {p} :
forall a b n : @NTerm p,
isprog a -> isprog b -> isprog n -> isprog (mk_compute a b n).
Proof.
sp; allrw @isprog_eq.
apply isprogram_compute; auto.
Qed.
Theorem isvalue_approx {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isvalue (mk_approx a b).
Proof.
intros; constructor; simpl; auto.
fold (mk_approx a b).
apply isprogram_approx; auto.
Qed.
Theorem isovalue_approx {p} :
forall a b : @NTerm p, nt_wf a -> nt_wf b -> isovalue (mk_approx a b).
Proof.
intros; constructor; simpl; auto.
fold (mk_approx a b).
allrw @nt_wf_eq.
apply wf_approx; auto.
Qed.
Theorem isvalue_cequiv {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isvalue (mk_cequiv a b).
Proof.
intros; constructor; simpl; auto.
apply isprogram_cequiv; auto.
Qed.
Theorem isovalue_cequiv {p} :
forall a b : @NTerm p, nt_wf a -> nt_wf b -> isovalue (mk_cequiv a b).
Proof.
intros; constructor; simpl; auto.
allrw @nt_wf_eq.
apply wf_approx; auto.
Qed.
Theorem isvalue_texc {p} :
forall a b : @NTerm p,
isprogram a -> isprogram b -> isvalue (mk_texc a b).
Proof.
intros; constructor; simpl; auto.
apply isprogram_texc; auto.
Qed.
Theorem isvalue_union {p} :
forall a b :@NTerm p, isprogram a -> isprogram b -> isvalue (mk_union a b).
Proof.
intros; constructor; simpl; auto.
apply isprogram_union; auto.
Qed.
Theorem isvalue_union2 {p} :
forall a b :@NTerm p, isprogram a -> isprogram b -> isvalue (mk_union2 a b).
Proof.
intros; constructor; simpl; auto.
apply isprogram_union2; auto.
Qed.
Theorem isvalue_image {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isvalue (mk_image a b).
Proof.
intros; constructor; simpl; auto; apply isprogram_image; auto.
Qed.
Theorem isvalue_pertype {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_pertype a).
Proof.
intros; constructor; simpl; auto; apply isprogram_pertype; auto.
Qed.
Theorem isvalue_partial {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_partial a).
Proof.
intros; constructor; simpl; auto; apply isprogram_partial; auto.
Qed.
Theorem isvalue_ipertype {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_ipertype a).
Proof.
intros; constructor; simpl; auto.
fold (mk_ipertype a).
apply isprogram_ipertype; auto.
Qed.
Theorem isvalue_spertype {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_spertype a).
Proof.
intros; constructor; simpl; auto.
fold (mk_spertype a).
apply isprogram_spertype; auto.
Qed.
(*
Theorem isvalue_tuni :
forall a, isprogram a -> isvalue (mk_tuni a).
Proof.
intros; constructor; apply isprogram_tuni; auto.
Qed.
*)
(*
Theorem isvalue_esquash :
forall a, isprogram a -> isvalue (mk_esquash a).
Proof.
intros. constructor. fold (mk_esquash a).
apply isprogram_esquash; auto.
Qed.
*)
Lemma wf_free_from_atom {p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_free_from_atom a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_free_from_atoms {p} :
forall T t : @NTerm p,
wf_term T -> wf_term t -> wf_term (mk_free_from_atoms T t).
Proof.
introv wT wt; allrw <- @nt_wf_eq.
inversion wT; inversion wt; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma oball_map_wftb_eq_otrue_implies_wf_term {o} :
forall (bs : list (@BTerm o)) t,
oball (map wftb bs) = oball (map bterm2otrue bs)
-> LIn (nobnd t) bs
-> wf_term t.
Proof.
introv e i.
eapply oball_map_wftb_eq_otrue_implies in e;[|exact i].
allsimpl; auto.
Qed.
Lemma wf_free_from_atom_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_free_from_atom a b T).
Proof.
sp; split; introv h; repnd.
- apply wf_free_from_atom; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term;try (exact h); simpl; sp.
Qed.
Lemma wf_free_from_atom_iff2 {p} :
forall a b T : @NTerm p,
wf_term (mk_free_from_atom a b T) <=> (wf_term a # wf_term b # wf_term T).
Proof.
intros; rw @wf_free_from_atom_iff; sp.
Qed.
Lemma wf_free_from_atoms_iff {p} :
forall T t : @NTerm p,
(wf_term T # wf_term t) <=> wf_term (mk_free_from_atoms T t).
Proof.
sp; split; introv h; repnd.
- apply wf_free_from_atoms; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term;try (exact h); simpl; sp.
Qed.
Lemma wf_free_from_atoms_iff2 {p} :
forall T t : @NTerm p,
wf_term (mk_free_from_atoms T t) <=> (wf_term T # wf_term t).
Proof.
intros; rw @wf_free_from_atoms_iff; sp.
Qed.
Lemma wf_equality {p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_equality a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_equality_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_equality a b T).
Proof.
sp; split; introv h; repnd.
- apply wf_equality; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term;try (exact h); simpl; sp.
Qed.
Lemma wf_equality_iff2 {p} :
forall a b T : @NTerm p,
wf_term (mk_equality a b T) <=> (wf_term a # wf_term b # wf_term T).
Proof.
intros; rw @wf_equality_iff; sp.
Qed.
Lemma wf_member {p} :
forall a T : @NTerm p,
wf_term a -> wf_term T -> wf_term (mk_member a T).
Proof.
sp; unfold mk_member; apply wf_equality; sp.
Qed.
Lemma wf_member_iff {p} :
forall a T : @NTerm p, (wf_term a # wf_term T) <=> wf_term (mk_member a T).
Proof.
sp; split; intro i.
apply wf_member; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (nobnd T)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma wf_member_iff2 {p} :
forall a T : @NTerm p, wf_term (mk_member a T) <=> (wf_term a # wf_term T).
Proof.
intros; rw @wf_member_iff; sp.
Qed.
Lemma wf_tequality {p} :
forall a b : @NTerm p, wf_term a -> wf_term b -> wf_term (mk_tequality a b).
Proof.
intros a b; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_tequality_iff {p} :
forall a b : @NTerm p, (wf_term a # wf_term b) <=> wf_term (mk_tequality a b).
Proof.
sp; split; intro h.
- apply wf_tequality; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term;try (exact h); simpl; sp.
Qed.
Lemma wf_tequality_iff2 {p} :
forall a b : @NTerm p, wf_term (mk_tequality a b) <=> (wf_term a # wf_term b).
Proof.
intros; rw @wf_tequality_iff; sp.
Qed.
Lemma wf_type {p} :
forall a : @NTerm p, wf_term a -> wf_term (mk_type a).
Proof.
sp; apply wf_tequality; sp.
Qed.
Lemma wf_type_iff {p} :
forall a : @NTerm p, wf_term a <=> wf_term (mk_type a).
Proof.
sp; split; intro i.
apply wf_type; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
inversion i1; subst; sp.
Qed.
Lemma wf_type_iff2 {p} :
forall a : @NTerm p, wf_term (mk_type a) <=> wf_term a.
Proof.
intros; rw <- @wf_type_iff; sp.
Qed.
Lemma wf_lam {p} :
forall v (b : @NTerm p), wf_term b -> wf_term (mk_lam v b).
Proof.
intros v b; repeat (rw <- @nt_wf_eq).
intros ntb; inversion ntb; subst; constructor; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma wf_lam_iff {p} :
forall v (b : @NTerm p), (wf_term b) <=> wf_term (mk_lam v b).
Proof.
sp; split; intro i; try (apply wf_lam; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (bterm [v] b)); intros j.
dest_imp j hyp; sp.
inversion j; subst; sp.
Qed.
Lemma wf_id {p} : @wf_term p mk_id.
Proof.
apply wf_lam; sp.
Qed.
Hint Immediate wf_id : wf.
Lemma wf_squash {p} :
forall T : @NTerm p, wf_term (mk_squash T) <=> wf_term T.
Proof.
intro; unfold mk_squash; rw <- @wf_image_iff.
rw <- @wf_lam_iff; split; sp.
Qed.
Theorem wf_function {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_function a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem wf_function_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_function a v b).
Proof.
sp; split; intro i; try (apply wf_function; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; try (complete sp).
dest_imp i2 hyp; try (complete sp).
inversion i1; inversion i2; subst; sp.
Qed.
Lemma wf_subtype {p} :
forall a b : @NTerm p, wf_term a -> wf_term b -> wf_term (mk_subtype a b).
Proof.
sp; unfold mk_subtype, mk_vsubtype.
apply wf_member; sp.
apply wf_function; sp.
Qed.
Lemma wf_subtype_iff {p} :
forall a b : @NTerm p, (wf_term a # wf_term b) <=> wf_term (mk_subtype a b).
Proof.
sp; split; intro.
apply wf_subtype; sp.
unfold mk_subtype, mk_vsubtype in H.
allrw <- @wf_member_iff; repd.
allrw <- @wf_function_iff; sp.
Qed.
Lemma wf_halts {p} :
forall a : @NTerm p, wf_term a -> wf_term (mk_halts a).
Proof.
sp; unfold mk_halts.
allrw @wf_term_eq.
constructor; repeat (allsimpl; sp; subst; repeat constructor).
Qed.
Lemma wf_halts_iff {p} :
forall a : @NTerm p, wf_term a <=> wf_term (mk_halts a).
Proof.
sp; split; intro i.
apply wf_halts; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst.
generalize (k (nobnd (mk_cbv a nvarx mk_axiom))); allsimpl; intro j.
dest_imp j hyp.
inversion j as [ lnv nt u ]; subst.
inversion u as [|?| o lnt pp q ]; subst; allsimpl.
generalize (pp (nobnd a)); intro r.
dest_imp r hyp.
inversion r; subst; sp.
Qed.
Lemma isprogram_free_from_atom {p} :
forall a b T : @NTerm p,
isprogram a
-> isprogram b
-> isprogram T
-> isprogram (mk_free_from_atom a b T).
Proof.
repeat constructor.
unfold closed; simpl.
allrw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @isprogram; allunfold @closed.
repeat (rewrite remove_nvars_nil_l); sp.
simpl; sp; allunfold @isprogram; sp; subst; constructor; auto.
Qed.
Lemma isprogram_free_from_atom_iff {p} :
forall a b c : @NTerm p,
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_free_from_atom a b c).
Proof.
intros; split; intro i.
apply isprogram_free_from_atom; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Lemma isprog_free_from_atom {p} :
forall a b T : @NTerm p,
isprog a
-> isprog b
-> isprog T
-> isprog (mk_free_from_atom a b T).
Proof.
sp; allrw @isprog_eq.
apply isprogram_free_from_atom; auto.
Qed.
Lemma isvalue_free_from_atom {p} :
forall a b T : @NTerm p,
isprogram (mk_free_from_atom a b T) -> isvalue (mk_free_from_atom a b T).
Proof. sp; constructor; sp.
Qed.
Lemma isprogram_free_from_atoms {p} :
forall T t : @NTerm p,
isprogram T
-> isprogram t
-> isprogram (mk_free_from_atoms T t).
Proof.
repeat constructor.
unfold closed; simpl.
allrw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @isprogram; allunfold @closed.
repeat (rewrite remove_nvars_nil_l); sp.
simpl; sp; allunfold @isprogram; sp; subst; constructor; auto.
Qed.
Lemma isprogram_free_from_atoms_iff {p} :
forall a b : @NTerm p,
(isprogram a # isprogram b) <=> isprogram (mk_free_from_atoms a b).
Proof.
intros; split; intro i.
apply isprogram_free_from_atoms; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprog_free_from_atoms {p} :
forall a b : @NTerm p,
isprog a
-> isprog b
-> isprog (mk_free_from_atoms a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_free_from_atoms; auto.
Qed.
Lemma isvalue_free_from_atoms {p} :
forall a b : @NTerm p,
isprogram (mk_free_from_atoms a b) -> isvalue (mk_free_from_atoms a b).
Proof. sp; constructor; sp.
Qed.
Lemma isprogram_equality {p} :
forall a b T : @NTerm p,
isprogram a
-> isprogram b
-> isprogram T
-> isprogram (mk_equality a b T).
Proof.
repeat constructor.
unfold closed; simpl.
allrw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @isprogram; allunfold @closed.
repeat (rewrite remove_nvars_nil_l); sp.
simpl; sp; allunfold @isprogram; sp; subst; constructor; auto.
Qed.
Lemma isprogram_equality_iff {p} :
forall a b c : @NTerm p,
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_equality a b c).
Proof.
intros; split; intro i.
apply isprogram_equality; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Lemma isprog_equality {p} :
forall a b T : @NTerm p,
isprog a
-> isprog b
-> isprog T
-> isprog (mk_equality a b T).
Proof.
sp; allrw @isprog_eq.
apply isprogram_equality; auto.
Qed.
Lemma isvalue_equality {p} :
forall a b T : @NTerm p,
isprogram (mk_equality a b T) -> isvalue (mk_equality a b T).
Proof.
intros; constructor; simpl; auto.
Qed.
Lemma isprogram_member {p} :
forall t T : @NTerm p,
isprogram t
-> isprogram T
-> isprogram (mk_member t T).
Proof.
unfold mk_member; sp.
apply isprogram_equality; sp.
Qed.
Lemma isprog_member {p} :
forall t T : @NTerm p,
isprog t
-> isprog T
-> isprog (mk_member t T).
Proof.
unfold mk_member; sp; apply isprog_equality; sp.
Qed.
Lemma isprogram_tequality {p} :
forall a b : @NTerm p,
isprogram a
-> isprogram b
-> isprogram (mk_tequality a b).
Proof.
repeat constructor.
unfold closed; simpl.
allrw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @isprogram; allunfold @closed.
repeat (rewrite remove_nvars_nil_l); sp.
simpl; sp; allunfold @isprogram; sp; subst; constructor; auto.
Qed.
Lemma isprogram_tequality_iff {p} :
forall a b : @NTerm p,
(isprogram a # isprogram b) <=> isprogram (mk_tequality a b).
Proof.
intros; split; intro i.
apply isprogram_tequality; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprog_tequality {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_tequality a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_tequality; auto.
Qed.
Lemma isvalue_tequality {p} :
forall a b : @NTerm p, isprogram (mk_tequality a b) -> isvalue (mk_tequality a b).
Proof.
intros; constructor; simpl; auto.
Qed.
Lemma isprogram_type {p} :
forall t : @NTerm p, isprogram t -> isprogram (mk_type t).
Proof.
unfold mk_type; sp.
apply isprogram_tequality; sp.
Qed.
Lemma isprog_type {p} :
forall t : @NTerm p, isprog t -> isprog (mk_type t).
Proof.
unfold mk_type; sp; apply isprog_tequality; sp.
Qed.
Lemma isprogram_cbv {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_cbv a v b).
Proof.
sp.
repeat constructor; sp.
unfold closed; simpl.
rw remove_nvars_nil_l.
rewrite app_nil_r.
rw app_eq_nil_iff; sp.
allunfold @isprogram; allunfold @closed; sp.
allrw subvars_eq.
rw <- null_iff_nil.
rw null_remove_nvars; simpl; sp.
allsimpl; sp; subst.
constructor; allunfold @isprogram; sp.
constructor; sp.
Qed.
Lemma isprogram_cbv_iff {p} :
forall (a : @NTerm p) v b,
isprogram (mk_cbv a v b)
<=> isprogram a
# subvars (free_vars b) [v]
# nt_wf b.
Proof.
sp; split; intros i.
inversion i as [ cl w ].
inversion w as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); simpl; intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst.
inversion cl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
unfold isprogram, closed.
onerw app_eq_nil_iff; repd; allrw; sp.
allrw <- null_iff_nil.
allrw null_remove_nvars; allsimpl.
rw subvars_eq.
unfold subset; sp; simpl.
try (complete (apply_in_hyp p; sp)).
apply isprogram_cbv; sp.
Qed.
Lemma isprog_cbv {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_cbv a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_cbv; sp.
Qed.
Lemma isprogram_halts {p} :
forall t : @NTerm p,
isprogram t
-> isprogram (mk_halts t).
Proof.
unfold mk_halts; sp.
apply isprogram_approx.
apply isprogram_axiom.
apply isprogram_cbv; sp.
allrw @nt_wf_eq; apply wf_axiom.
Qed.
Lemma isprog_halts {p} :
forall t : @NTerm p,
isprog t
-> isprog (mk_halts t).
Proof.
sp; allrw @isprog_eq.
apply isprogram_halts; sp.
Qed.
Lemma wf_cbv {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_cbv a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_cbv_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_cbv a v b).
Proof.
sp; split; intros i.
apply wf_cbv; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma wf_isect {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_isect a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem wf_isect_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_isect a v b).
Proof.
sp; split; intro i; try (apply wf_isect; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_isect {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_isect a v b).
Proof.
sp.
unfold isprogram, mk_isect, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_isect {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_isect a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_isect; sp.
Qed.
Lemma isprog_isect_iff {p} :
forall (a : @NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_isect a v b).
Proof.
introv; split; intro k; try (apply isprog_isect; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma wf_disect {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_disect a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_disect_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_disect a v b).
Proof.
sp; split; intro i; try (apply wf_disect; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_disect {p} :
forall (a :@NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_disect a v b).
Proof.
sp.
unfold isprogram, mk_disect, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_disect {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_disect a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_disect; sp.
Qed.
Lemma isprog_disect_iff {p} :
forall (a : @NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_disect a v b).
Proof.
introv; split; intro k; try (apply isprog_disect; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma wf_eisect {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_eisect a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem wf_eisect_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_eisect a v b).
Proof.
sp; split; intro i; try (apply wf_eisect; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_eisect {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_eisect a v b).
Proof.
sp.
unfold isprogram, mk_eisect, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_eisect {p} :
forall (a :@NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_eisect a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_eisect; sp.
Qed.
Lemma isprog_eisect_iff {p} :
forall (a : @NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_eisect a v b).
Proof.
introv; split; intro k; try (apply isprog_eisect; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma wf_set {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_set a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem wf_set_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_set a v b).
Proof.
sp; split; intro i; try (apply wf_set; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_set {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_set a v b).
Proof.
sp.
unfold isprogram, mk_set, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_set {p} :
forall (a :@NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_set a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_set; sp.
Qed.
Lemma isprog_set_iff {p} :
forall (a :@NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_set a v b).
Proof.
introv; split; intro k; try (apply isprog_set; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma wf_tunion {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_tunion a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem wf_tunion_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_tunion a v b).
Proof.
sp; split; intro i; try (apply wf_tunion; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_tunion {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_tunion a v b).
Proof.
sp.
unfold isprogram, mk_tunion, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_tunion {p} :
forall (a :@NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_tunion a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_tunion; sp.
Qed.
Lemma isprog_tunion_iff {p} :
forall (a :@NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_tunion a v b).
Proof.
introv; split; intro k; try (apply isprog_tunion; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma wf_quotient {p} :
forall (a : @NTerm p) v1 v2 b,
wf_term a -> wf_term b -> wf_term (mk_quotient a v1 v2 b).
Proof.
intros a v1 v2 B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem wf_quotient_iff {p} :
forall (a : @NTerm p) v1 v2 b,
(wf_term a # wf_term b) <=> wf_term (mk_quotient a v1 v2 b).
Proof.
sp; split; intro i; try (apply wf_quotient; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v1,v2] b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_quotient {p} :
forall (a : @NTerm p) v1 v2 b,
isprogram a
-> subvars (free_vars b) [v1,v2]
-> nt_wf b
-> isprogram (mk_quotient a v1 v2 b).
Proof.
sp.
unfold isprogram, mk_quotient, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp.
allrw subvars_prop; discover; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_quotient {p} :
forall (a : @NTerm p) v1 v2 b,
isprog a
-> isprog_vars [v1,v2] b
-> isprog (mk_quotient a v1 v2 b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_quotient; sp.
Qed.
Lemma isprog_quotient_iff {p} :
forall (a : @NTerm p) v1 v2 b,
(isprog a # isprog_vars [v1,v2] b)
<=> isprog (mk_quotient a v1 v2 b).
Proof.
introv; split; intro k; try (apply isprog_quotient; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v1,v2] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v1 x); destruct (eq_var_dec v2 x); sp.
right; right; right; allsimpl; sp.
Qed.
Lemma wf_w {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_w a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_w_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_w a v b).
Proof.
sp; split; intro i; try (apply wf_w; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; try (complete sp).
dest_imp i2 hyp; try (complete sp).
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_w {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_w a v b).
Proof.
sp.
unfold isprogram, mk_w, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_w {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_w a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_w; sp.
Qed.
Lemma isprog_w_iff {p} :
forall (a : @NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_w a v b).
Proof.
introv; split; intro k; try (apply isprog_w; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma wf_m {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_m a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_m_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_m a v b).
Proof.
sp; split; intro i; try (apply wf_m; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; try (complete sp).
dest_imp i2 hyp; try (complete sp).
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_m {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_m a v b).
Proof.
sp.
unfold isprogram, mk_m, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_m {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_m a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_m; sp.
Qed.
Lemma wf_pw {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
wf_term P
-> wf_term A
-> wf_term B
-> wf_term C
-> wf_term p
-> wf_term (mk_pw P ap A bp ba B cp ca cb C p).
Proof.
introv wP wA wB wC wp; repeat (rw <- @nt_wf_eq).
inversion wP; inversion wA; inversion wB; inversion wC; inversion wp; constructor; sp;
allsimpl; sp; subst; unfold num_bvars; simpl; sp;
constructor; sp; rw @nt_wf_eq; sp.
Qed.
Lemma wf_pw_iff {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C q,
(wf_term P
# wf_term A
# wf_term B
# wf_term C
# wf_term q)
<=> wf_term (mk_pw P ap A bp ba B cp ca cb C q).
Proof.
sp; split; intro i; try (apply wf_pw; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd P))
(k (bterm [ap] A))
(k (bterm [bp,ba] B))
(k (bterm [cp,ca,cb] C))
(k (nobnd q));
intros i1 i2 i3 i4 i5.
dest_imp i1 hyp; try (complete sp).
dest_imp i2 hyp; try (complete sp).
dest_imp i3 hyp; try (complete sp).
dest_imp i4 hyp; try (complete sp).
dest_imp i5 hyp; try (complete sp).
inversion i1; inversion i2; inversion i3; inversion i4; inversion i5; subst; sp.
Qed.
Lemma isprogram_pw {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprogram P
-> subvars (free_vars A) [ap]
-> nt_wf A
-> subvars (free_vars B) [bp, ba]
-> nt_wf B
-> subvars (free_vars C) [cp, ca, cb]
-> nt_wf C
-> isprogram p
-> isprogram (mk_pw P ap A bp ba B cp ca cb C p).
Proof.
sp.
unfold isprogram, mk_pw, closed; simpl; sp.
allrw <- null_iff_nil.
allrw null_app.
allrw remove_nvars_nil_l.
allrw <- @closed_null_free_vars.
allrw null_nil_iff.
allunfold @isprogram; sp;
try (complete (rw null_remove_nvars; simpl; sp;
allrw subvars_prop; allsimpl;
discover; sp)).
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_pw {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprog P
-> isprog_vars [ap] A
-> isprog_vars [bp, ba] B
-> isprog_vars [cp, ca, cb] C
-> isprog p
-> isprog (mk_pw P ap A bp ba B cp ca cb C p).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_pw; sp.
Qed.
Lemma wf_pm {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
wf_term P
-> wf_term A
-> wf_term B
-> wf_term C
-> wf_term p
-> wf_term (mk_pm P ap A bp ba B cp ca cb C p).
Proof.
introv wP wA wB wC wp; repeat (rw <- @nt_wf_eq).
inversion wP; inversion wA; inversion wB; inversion wC; inversion wp; constructor; sp;
allsimpl; sp; subst; unfold num_bvars; simpl; sp;
constructor; sp; rw @nt_wf_eq; sp.
Qed.
Lemma wf_pm_iff {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C q,
(wf_term P
# wf_term A
# wf_term B
# wf_term C
# wf_term q)
<=> wf_term (mk_pm P ap A bp ba B cp ca cb C q).
Proof.
sp; split; intro i; try (apply wf_pm; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd P))
(k (bterm [ap] A))
(k (bterm [bp,ba] B))
(k (bterm [cp,ca,cb] C))
(k (nobnd q));
intros i1 i2 i3 i4 i5.
dest_imp i1 hyp; try (complete sp).
dest_imp i2 hyp; try (complete sp).
dest_imp i3 hyp; try (complete sp).
dest_imp i4 hyp; try (complete sp).
dest_imp i5 hyp; try (complete sp).
inversion i1; inversion i2; inversion i3; inversion i4; inversion i5; subst; sp.
Qed.
Lemma isprogram_pm {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprogram P
-> subvars (free_vars A) [ap]
-> nt_wf A
-> subvars (free_vars B) [bp, ba]
-> nt_wf B
-> subvars (free_vars C) [cp, ca, cb]
-> nt_wf C
-> isprogram p
-> isprogram (mk_pm P ap A bp ba B cp ca cb C p).
Proof.
sp.
unfold isprogram, mk_pw, closed; simpl; sp.
allrw <- null_iff_nil.
allrw null_app.
allrw remove_nvars_nil_l.
allrw <- @closed_null_free_vars.
allrw null_nil_iff.
allunfold @isprogram; sp;
try (complete (rw null_remove_nvars; simpl; sp;
allrw subvars_prop; allsimpl;
discover; sp)).
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_pm {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprog P
-> isprog_vars [ap] A
-> isprog_vars [bp, ba] B
-> isprog_vars [cp, ca, cb] C
-> isprog p
-> isprog (mk_pm P ap A bp ba B cp ca cb C p).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_pm; sp.
Qed.
Lemma isprogram_function {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_function a v b).
Proof.
sp.
unfold isprogram, mk_function, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_function {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_function a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_function; sp.
Qed.
Lemma isprog_function_iff {p} :
forall (a : @NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_function a v b).
Proof.
introv; split; intro k; try (apply isprog_function; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma isprogram_product {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_product a v b).
Proof.
sp.
unfold isprogram, mk_product, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_product {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_product a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_product; sp.
Qed.
Lemma isprog_product_iff {p} :
forall (a : @NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_product a v b).
Proof.
introv; split; intro k; try (apply isprog_product; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (autodimp i1 hyp).
repeat (autodimp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma isprogram_lam {p} :
forall v (b : @NTerm p),
isprog_vars [v] b
-> isprogram (mk_lam v b).
Proof.
sp.
allrw @isprog_vars_eq; sp.
constructor.
unfold closed; simpl.
rw app_nil_r.
rw <- null_iff_nil.
rw null_remove_nvars; simpl; sp.
allrw subvars_eq.
allrw subset_singleton_r.
apply_in_hyp pp; sp.
constructor; allsimpl; sp; subst.
constructor; sp.
Qed.
Lemma isprog_lam {p} :
forall v (b : @NTerm p),
isprog_vars [v] b
-> isprog (mk_lam v b).
Proof.
sp; allrw @isprog_eq; apply isprogram_lam; sp.
Qed.
Lemma isprog_vars_var {p} :
forall v, @isprog_vars p [v] (mk_var v).
Proof.
sp.
rw @isprog_vars_eq; simpl; sp.
Qed.
Lemma isprog_vars_var_if {p} :
forall v vs, LIn v vs -> @isprog_vars p vs (mk_var v).
Proof.
sp.
rw @isprog_vars_eq; simpl; sp.
rw subvars_singleton_l; sp.
Qed.
Lemma isprog_vars_var_if2 {p} :
forall v vs, LIn v vs -> @isprog_vars p vs (mk_var v) <=> True.
Proof.
sp.
rw @isprog_vars_eq; simpl; sp.
rw subvars_singleton_l; sp.
Qed.
Lemma isprog_vars_var_iff {p} :
forall v vs, LIn v vs <=> @isprog_vars p vs (mk_var v).
Proof.
sp.
rw @isprog_vars_eq; simpl; sp.
rw subvars_singleton_l; sp; split; sp.
Qed.
Lemma isprog_id {p} :
@isprog p mk_id.
Proof.
unfold mk_id; sp; apply isprog_lam.
apply isprog_vars_var.
Qed.
Hint Immediate isprog_id.
Lemma isprog_vsubtype {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog b
-> isprog (mk_vsubtype a v b).
Proof.
unfold mk_vsubtype; sp.
apply isprog_member; sp.
apply isprog_function; sp.
allrw @isprog_eq.
inversion H0.
allunfold @closed.
allrw @isprog_vars_eq; simpl.
allrw; sp.
Qed.
Lemma isprog_subtype {p} :
forall a b : @NTerm p,
isprog a
-> isprog b
-> isprog (mk_subtype a b).
Proof.
unfold mk_subtype; sp.
apply isprog_member.
apply isprog_lam.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp; simpl.
apply isprog_function; sp.
allrw @isprog_eq.
inversion H0.
allunfold @closed.
rw @isprog_vars_eq; sp.
allrw; sp.
Qed.
Lemma isprog_fun {p} :
forall a b : @NTerm p,
isprog a
-> isprog b
-> isprog (mk_fun a b).
Proof.
unfold mk_fun; introv ipa ipb.
apply isprog_function; sp.
allrw @isprog_vars_eq; sp; simpl.
allrw @isprog_eq.
inversion ipb.
allunfold @closed.
allrw; sp.
allrw @isprog_eq; allunfold @isprogram; sp.
Qed.
Lemma isprog_ufun {p} :
forall a b : @NTerm p,
isprog a
-> isprog b
-> isprog (mk_ufun a b).
Proof.
unfold mk_fun; introv ipa ipb.
apply isprog_isect; sp.
allrw @isprog_vars_eq; sp; simpl.
allrw @isprog_eq.
inversion ipb.
allunfold @closed.
allrw; sp.
allrw @isprog_eq; allunfold @isprogram; sp.
Qed.
Lemma isprog_eufun {p} :
forall a b : @NTerm p,
isprog a
-> isprog b
-> isprog (mk_eufun a b).
Proof.
unfold mk_fun; introv ipa ipb.
apply isprog_eisect; sp.
allrw @isprog_vars_eq; sp; simpl.
allrw @isprog_eq.
inversion ipb.
allunfold @closed.
allrw; sp.
allrw @isprog_eq; allunfold @isprogram; sp.
Qed.
Lemma isprog_prod {p} :
forall a b : @NTerm p,
isprog a
-> isprog b
-> isprog (mk_prod a b).
Proof.
unfold mk_fun; introv ipa ipb.
apply isprog_product; sp.
allrw @isprog_vars_eq; sp; simpl.
allrw @isprog_eq.
inversion ipb.
allunfold @closed.
allrw; sp.
allrw @isprog_eq; allunfold @isprogram; sp.
Qed.
Lemma wf_rec {p} :
forall v (a : @NTerm p), wf_term a -> wf_term (mk_rec v a).
Proof.
intros v a; repeat (rw <- @nt_wf_eq).
intros nta; inversion nta; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma isprogram_rec {p} :
forall v (a : @NTerm p),
subvars (free_vars a) [v]
-> nt_wf a
-> isprogram (mk_rec v a).
Proof.
sp.
unfold isprogram, mk_rec, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
rw null_nil_iff.
allrw subvars_prop; allsimpl; sp.
rw null_remove_nvars; simpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_rec {p} :
forall v (a : @NTerm p),
isprog_vars [v] a
-> isprog (mk_rec v a).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_rec; sp.
Qed.
Theorem wf_product {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_product a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma isprogram_integer {p} :
forall i, @isprogram p (mk_integer i).
Proof.
introv.
repeat constructor; simpl; sp.
Qed.
Hint Immediate isprogram_integer.
Lemma isprogram_int_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (Can NInt) bterms)
-> bterms = [].
Proof.
introv isp; inversion isp as [ cl w ].
inversion w as [|?| o lnt k e]; subst; allsimpl.
allrw <- null_iff_nil; allsimpl.
allrw null_map.
allrw null_iff_nil; auto.
Qed.
Lemma isprogram_nat_implies {p} :
forall (bterms : list (@BTerm p)) n,
isprogram (oterm (Can (Nint n)) bterms)
-> bterms = [].
Proof.
introv isp; inversion isp as [cl w].
inversion w as [|?| o lnt k e]; subst; allsimpl.
allrw <- null_iff_nil.
allrw null_map.
allrw null_iff_nil; auto.
Qed.
Lemma isprogram_nseq_implies {p} :
forall (bterms : list (@BTerm p)) f,
isprogram (oterm (Can (Nseq f)) bterms)
-> bterms = [].
Proof.
introv isp; inversion isp as [cl w].
inversion w as [|?| o lnt k e]; subst; allsimpl.
allrw <- null_iff_nil.
allrw null_map.
allrw null_iff_nil; auto.
Qed.
Lemma isprogram_integer_implies {p} :
forall (bterms : list (@BTerm p)) z,
isprogram (oterm (Can (Nint z)) bterms)
-> bterms = [].
Proof.
exact isprogram_nat_implies.
Qed.
Lemma isprogram_base_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (Can NBase) bterms)
-> bterms = [].
Proof.
introv isp; inversion isp as [cl w].
inversion w as [|?| o lnt k e]; subst; allsimpl.
allrw <- null_iff_nil.
allrw null_map.
allrw null_iff_nil; auto.
Qed.
Lemma isprogram_approx_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (Can NApprox) bterms)
-> {a, b : NTerm $
bterms = [nobnd a, nobnd b]}.
Proof.
introv isp; inversion isp as [cl w].
inversion w as [|?|o lnt k e]; subst; allsimpl.
destruct bterms; allsimpl; sp.
destruct bterms; allsimpl; sp.
destruct bterms; allsimpl; sp.
destruct b; destruct b0; allunfold @num_bvars; allsimpl.
inversion e as [len].
rewrite len in H.
repeat (allrw length0; subst; allsimpl).
unfold nobnd.
exists n n0; auto.
Qed.
(* ------ programs ------ *)
Definition WTerm {p} := { t : @NTerm p | wf_term t }.
Definition WBTerm {p} := { bt : @BTerm p | wf_bterm bt }.
(* end hide *)
(*
(* first of all, isprog is NOT a boolean. also, the reader will
be left wondering what UIP_dec is*)
where [isprog] is the Boolean version of [isprogram]
(using a Boolean version of [isprogram] makes it easy to prove that
closed terms are equal by proving that the underlying [NTerm]s are
equals using [UIP_dec]).
*)
(**
The [CTerm] type below is useful in compactly stating definitions
that are only meaningful for closed terms. A [CTerm] is a pair
of an [NTerm] [t] and a proof that [t] is closed.
This [CTerm] type will be handy in compactly
defining the Nuprl type system where types are defined as partial
equivalence relations on closed terms.
*)
Definition CTerm {p} := { t : @NTerm p | isprog t }.
Definition get_cterm {p} (t : @CTerm p) := let (a,_) := t in a.
(* begin hide *)
Definition BCTerm {p} := { bt : @BTerm p | isprog_bt bt }.
(* end hide *)
(**
We also define a type of terms that specifies what are the possible
free variables of its inhabitants. A term is a [(CVTerm vs)] term
if the set of its free variables is a subset of [vs]. This type is
also useful to define the Nuprl type system. For example, to define
a closed family of types such as a closed function type of the form
$\NUPRLfunction{x}{A}{\NUPRLsuba{B}{z}{x}}$, $A$ has to be closed
and the free variables of $B$ can only be $z$.
*)
Definition CVTerm {p} (vs : list NVar) := { t : @NTerm p | isprog_vars vs t }.
(* begin hide *)
Definition CVTerm3 {p} := forall a b c, @CVTerm p [a;b;c].
Definition mk_cvterm {p} (vs : list NVar) (t : @NTerm p) (p : isprog_vars vs t) :=
exist (isprog_vars vs) t p.
Ltac destruct_cterms :=
repeat match goal with
| [ H : CTerm |- _ ] => destruct H
| [ H : CVTerm _ |- _ ] => destruct H
end.
Ltac dest_cterm H :=
let t := type of H in
match goal with
| [ x : CTerm |- _ ] =>
match t with
| context[x] => destruct x
end
| [ x : CVTerm _ |- _ ] =>
match t with
| context[x] => destruct x
end
end.
(** A faster version of destruct_cterms. We avoid destructing all of them. *)
Ltac dest_cterms H := repeat (dest_cterm H).
Definition get_wterm {p} (t : @WTerm p) := let (a,_) := t in a.
Definition get_cvterm {p} (vs : list NVar) (t : @CVTerm p vs) := let (a,_) := t in a.
Definition get_bcterm {p} (bt : @BCTerm p) := let (a,_) := bt in a.
Lemma cterm_eq {p} :
forall t u : @CTerm p,
get_cterm t = get_cterm u
-> t = u.
Proof.
introv; destruct_cterms; simpl; sp; subst.
eauto with pi.
Qed.
Lemma cvterm_eq {p} :
forall vs (t u : @CVTerm p vs),
get_cvterm vs t = get_cvterm vs u
-> t = u.
Proof.
introv; destruct_cterms; simpl; sp; subst.
eauto with pi.
Qed.
Lemma wf_cterm {p} :
forall t, @wf_term p (get_cterm t).
Proof.
introv; destruct_cterms; simpl.
allrw @isprog_eq; allunfold @isprogram; repnd; allrw @nt_wf_eq; sp.
Qed.
Hint Immediate wf_cterm : wf.
Lemma free_vars_cterm {p} :
forall t : @CTerm p, free_vars (get_cterm t) = [].
Proof.
introv; destruct_cterms; simpl.
allrw @isprog_eq; allunfold @isprogram; repnd; allrw; sp.
Qed.
Definition mk_cterm {p} (t : @NTerm p) (p : isprogram t) : CTerm :=
exist isprog t (isprogram_implies t p).
Definition mk_ct {p} (t : @NTerm p) (p : isprog t) : CTerm := exist isprog t p.
Definition mk_wterm {p} (t : @NTerm p) (p : wf_term t) := exist wf_term t p.
Definition mk_wterm' {p} (t : @NTerm p) (p : nt_wf t) :=
exist wf_term t (nt_wf_implies t p).
Definition iscvalue {p} (t : @CTerm p) : Type :=
isvalue (get_cterm t).
Lemma mk_cv_pf {p} :
forall vs t,
@isprog_vars p vs (get_cterm t).
Proof.
destruct t; simpl.
rw @isprog_eq in i; destruct i.
rw @isprog_vars_eq; simpl; sp.
allunfold @closed.
allrw; sp.
Qed.
(** From a closed term, we can always make a term whose variables
* are contained in vs: *)
Definition mk_cv {p} (vs : list NVar) (t : @CTerm p) : CVTerm vs :=
exist (isprog_vars vs) (get_cterm t) (mk_cv_pf vs t).
Ltac clear_deps h :=
repeat match goal with
| [ H : context[h] |- _ ] => clear H
end.
Lemma programs_bt_to_program {p} :
forall bts : list (@BCTerm p),
forall op,
map (fun bt => num_bvars (get_bcterm bt)) bts = OpBindings op
-> isprogram (oterm op (map get_bcterm bts)).
Proof.
sp; unfold isprogram; sp.
allrw @closed_nt; sp.
allrw in_map_iff; sp; subst.
destruct a; destruct x; allsimpl.
clear_deps i.
rw <- @isprogram_bt_eq in i.
inversion i; sp.
constructor; sp.
allrw in_map_iff; sp; subst.
destruct a; destruct x; allsimpl.
clear_deps i.
rw <- @isprogram_bt_eq in i.
inversion i; sp.
rewrite <- H.
rewrite map_map; unfold compose; sp.
Qed.
Definition mkc_int {p} : @CTerm p :=
exist isprog mk_int isprog_int.
Definition mkw_int {p} : @WTerm p :=
exist wf_term mk_int wf_int.
Definition mkc_integer {p} (n : Z) : @CTerm p :=
exist isprog (mk_integer n) (isprog_mk_integer n).
Definition mkw_integer {p} (n : Z) : @WTerm p :=
exist wf_term (mk_integer n) (wf_mk_integer n).
Lemma mkc_integer_eq {p} :
forall a b,
@mkc_integer p a = mkc_integer b
-> a = b.
Proof.
unfold mkc_integer; sp.
inversion H; sp.
Qed.
Definition mkc_nseq {p} (f : nseq) : @CTerm p :=
exist isprog (mk_nseq f) (isprog_mk_nseq f).
Lemma mkc_nseq_eq {p} :
forall f g,
@mkc_nseq p f = mkc_nseq g
-> f = g.
Proof.
unfold mkc_nseq; sp.
inversion H; sp.
Qed.
Lemma isvalue_implies {p} :
forall t, @isvalue p t -> (iscan t # isprogram t).
Proof.
introv isv.
inversion isv; subst; simpl; dands; auto.
Qed.
Lemma isvalue_iff {p} :
forall t : @NTerm p, isvalue t <=> (iscan t # isprogram t).
Proof.
introv; split; intro k.
- apply isvalue_implies; auto.
- repnd; destruct t; allsimpl; tcsp.
Qed.
Definition isprog_nout {p} (t : @NTerm p) :=
assert (no_vars_like_b t) # wf_term t.
Definition isprog_ntseq {o} (f : @ntseq o) :=
forall n, isprog_nout (f n).
Lemma isprogram_mk_ntseq {o} :
forall f : @ntseq o,
isprog_ntseq f
-> isprogram (mk_ntseq f).
Proof.
introv imp.
repeat constructor; pose proof (imp n) as h;
unfold isprog_nout in h; repnd;
apply @no_vars_like_b_true_iff in h0; repnd; auto.
apply nt_wf_eq; auto.
Qed.
Lemma isprog_mk_ntseq {o} :
forall f : @ntseq o,
isprog_ntseq f
-> isprog (mk_ntseq f).
Proof.
introv imp.
apply isprog_eq.
apply isprogram_mk_ntseq; auto.
Qed.
Lemma isvalue_mk_ntseq {o} :
forall f : @ntseq o,
isprog_ntseq f
-> isvalue (mk_ntseq f).
Proof.
introv imp.
apply isvalue_iff; simpl; dands; auto.
apply isprogram_mk_ntseq; auto.
Qed.
Definition mkc_ntseq {o}
(f : @ntseq o)
(p : isprog_ntseq f) : CTerm :=
exist isprog (mk_ntseq f) (isprog_mk_ntseq f p).
Lemma mkc_ntseq_eq {o} :
forall (f g : @ntseq o) pf pg,
mkc_ntseq f pf = mkc_ntseq g pg
-> f = g.
Proof.
unfold mkc_ntseq; introv h.
inversion h; sp.
Qed.
Lemma isprog_nout_proof_irrelevance {p} :
forall (t : @NTerm p),
forall x y : isprog_nout t,
x = y.
Proof.
intros.
destruct x, y.
f_equal; apply UIP.
Qed.
Hint Extern 0 =>
let h := fresh "h" in
match goal with
| [ H1 : isprog_nout ?t , H2 : isprog_nout ?t |- _ ] =>
pose proof (isprog_nout_proof_irrelevance t H2 H1) as h; subst
end : pi.
Lemma isprog_ntseq_proof_irrelevance {o} :
forall (f : @ntseq o) (p1 p2 : isprog_ntseq f),
p1 = p2.
Proof.
introv.
allunfold @isprog_ntseq.
apply functional_extensionality_dep.
introv.
remember (p1 x) as i1.
remember (p2 x) as i2.
eauto with pi.
Qed.
Definition isprog_atom {p} : @isprog p mk_atom := (eq_refl,eq_refl).
Definition isprog_uatom {p} : @isprog p mk_uatom := (eq_refl,eq_refl).
Definition isprog_token {p} :
forall s : String.string, @isprog p (mk_token s) := fun _ => (eq_refl,eq_refl).
Definition isprog_utoken {p} :
forall u : get_patom_set p, @isprog p (mk_utoken u) := fun _ => (eq_refl,eq_refl).
Definition mkc_atom {p} : @CTerm p :=
exist isprog mk_atom isprog_atom.
Definition mkc_token {p} (s : String.string) : @CTerm p :=
exist isprog (mk_token s) (isprog_token s).
Lemma mkc_token_eq {p} :
forall a b,
@mkc_token p a = mkc_token b
-> a = b.
Proof.
introv k; inversion k; sp.
Qed.
Definition mkc_uatom {p} : @CTerm p :=
exist isprog mk_uatom isprog_uatom.
Definition mkc_utoken {p} (u : get_patom_set p) : @CTerm p :=
exist isprog (mk_utoken u) (isprog_utoken u).
Lemma mkc_utoken_eq {p} :
forall a b : get_patom_set p,
@mkc_utoken p a = mkc_utoken b
-> a = b.
Proof.
introv k; inversion k; sp.
Qed.
Definition mkc_nat {p} (n : nat) : @CTerm p :=
exist isprog (mk_nat n) (isprog_mk_nat n).
Definition mkw_nat {p} (n : nat) : @WTerm p :=
exist wf_term (mk_nat n) (wf_mk_nat n).
Definition mkc_uni {p} (i : nat) : @CTerm p :=
exist isprog (mk_uni i) (isprog_mk_uni i).
Definition mkw_uni {p} (i : nat) : @WTerm p :=
exist wf_term (mk_uni i) (wf_mk_uni i).
Lemma mkc_uni_eq {p} :
forall a b,
@mkc_uni p a = mkc_uni b
-> a = b.
Proof.
unfold mkc_uni; sp.
inversion H; sp.
Qed.
Definition mkc_base {p} : @CTerm p :=
exist isprog mk_base isprog_base.
Definition mkw_base {p} : @WTerm p :=
exist wf_term mk_base wf_base.
Definition mkc_axiom {p} : @CTerm p :=
exist isprog mk_axiom isprog_axiom.
Definition mkw_axiom {p} : @WTerm p :=
exist wf_term mk_axiom wf_axiom.
Definition mkc_bottom {p} : @CTerm p :=
exist isprog mk_bottom isprog_bottom.
Lemma isprogram_pair {p} :
forall (a b : @NTerm p),
isprogram a
-> isprogram b
-> isprogram (mk_pair a b).
Proof.
introv pa pb.
inversion pa; inversion pb.
constructor; simpl.
unfold closed; simpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allunfold @closed; allrw; simpl; sp.
constructor; simpl; sp; subst; sp; constructor; sp.
Qed.
Lemma isprog_pair {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_pair a b).
Proof.
sp; allrw @isprog_eq; apply isprogram_pair; sp.
Qed.
Definition mkc_pair {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_pair a b) (isprog_pair a b x y).
Theorem wf_sup {p} :
forall a b : @NTerm p, wf_term a -> wf_term b -> wf_term (mk_sup a b).
Proof.
intros a b; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma isprogram_sup {p} :
forall a b : @NTerm p,
isprogram a
-> isprogram b
-> isprogram (mk_sup a b).
Proof.
introv pa pb.
inversion pa; inversion pb.
constructor; simpl.
unfold closed; simpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allunfold @closed; allrw; simpl; sp.
constructor; simpl; sp; subst; sp; constructor; sp.
Qed.
Lemma isprogram_sup_iff {p} :
forall a b : @NTerm p, (isprogram a # isprogram b) <=> isprogram (mk_sup a b).
Proof.
intros; split; intro i.
apply isprogram_sup; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprog_sup {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_sup a b).
Proof.
sp; allrw @isprog_eq; apply isprogram_sup; sp.
Qed.
Definition mkc_sup {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_sup a b) (isprog_sup a b x y).
Lemma mkc_sup_eq {p} :
forall a b c d : @CTerm p,
mkc_sup a b = mkc_sup c d
-> a = c # b = d.
Proof.
intros.
destruct a, b, c, d.
allunfold @mkc_sup.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_pair_eq {p} :
forall a b c d : @CTerm p,
mkc_pair a b = mkc_pair c d
-> a = c # b = d.
Proof.
intros.
destruct a, b, c, d.
allunfold @mkc_pair.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_texc {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_texc a b) (isprog_texc a b x y).
Lemma mkc_texc_eq {p} :
forall A1 A2 B1 B2 : @CTerm p,
mkc_texc A1 A2 = mkc_texc B1 B2
-> A1 = B1 # A2 = B2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
dands; eauto with pi.
Qed.
Definition mkc_union {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_union a b) (isprog_union a b x y).
Lemma mkc_union_eq {p} :
forall A1 A2 B1 B2 : @CTerm p,
mkc_union A1 A2 = mkc_union B1 B2
-> A1 = B1 # A2 = B2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_union2 {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_union2 a b) (isprog_union2 a b x y).
Lemma mkc_union2_eq {p} :
forall A1 A2 B1 B2 : @CTerm p,
mkc_union2 A1 A2 = mkc_union2 B1 B2
-> A1 = B1 # A2 = B2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Lemma isprog_unit {p} : @isprog p mk_unit.
Proof.
unfold isprog; simpl.
rw assert_true_iff; dands; sp.
Qed.
Hint Immediate isprog_unit.
Definition mkc_bool {p} : @CTerm p :=
exist isprog mk_bool (isprog_union mk_unit mk_unit isprog_unit isprog_unit).
Lemma isprogram_inl {p} :
forall a : @NTerm p, isprogram a -> isprogram (mk_inl a).
Proof.
introv pa.
inversion pa.
constructor; simpl.
unfold closed; simpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allunfold @closed; allrw; simpl; sp.
constructor; simpl; sp; subst; sp; constructor; sp.
Qed.
Lemma isprog_inl {p} :
forall a : @NTerm p, isprog a -> isprog (mk_inl a).
Proof.
sp; allrw @isprog_eq; apply isprogram_inl; sp.
Qed.
Definition mkc_inl {p} (t : @CTerm p) : CTerm :=
let (a,x) := t in exist isprog (mk_inl a) (isprog_inl a x).
Lemma isprogram_inr {p} :
forall a : @NTerm p, isprogram a -> isprogram (mk_inr a).
Proof.
introv pa.
inversion pa.
constructor; simpl.
unfold closed; simpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allunfold @closed; allrw; simpl; sp.
constructor; simpl; sp; subst; sp; constructor; sp.
Qed.
Lemma isprog_inr {p} :
forall a : @NTerm p, isprog a -> isprog (mk_inr a).
Proof.
sp; allrw @isprog_eq; apply isprogram_inr; sp.
Qed.
Definition mkc_inr {p} (t : @CTerm p) : CTerm :=
let (a,x) := t in exist isprog (mk_inr a) (isprog_inr a x).
Lemma mkc_inl_eq {p} :
forall a b : @CTerm p,
mkc_inl a = mkc_inl b
-> a = b.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_inr_eq {p} :
forall a b : @CTerm p,
mkc_inr a = mkc_inr b
-> a = b.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_pertype {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_pertype a) (isprog_pertype a x).
Definition mkw_pertype {p} (R : @WTerm p) : WTerm :=
let (a,x) := R in
exist wf_term (mk_pertype a) (wf_pertype a x).
Lemma mkc_pertype_eq {p} :
forall R1 R2 : @CTerm p, mkc_pertype R1 = mkc_pertype R2 -> R1 = R2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_partial {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_partial a) (isprog_partial a x).
Definition mkw_partial {p} (R : @WTerm p) : WTerm :=
let (a,x) := R in
exist wf_term (mk_partial a) (wf_partial a x).
Lemma mkc_partial_eq {p} :
forall R1 R2 : @CTerm p, mkc_partial R1 = mkc_partial R2 -> R1 = R2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_ipertype {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_ipertype a) (isprog_ipertype a x).
Definition mkw_ipertype {p} (R : @WTerm p) : WTerm :=
let (a,x) := R in
exist wf_term (mk_ipertype a) (wf_ipertype a x).
Lemma mkc_ipertype_eq {p} :
forall R1 R2 : @CTerm p, mkc_ipertype R1 = mkc_ipertype R2 -> R1 = R2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_spertype {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_spertype a) (isprog_spertype a x).
Definition mkw_spertype {p} (R : @WTerm p) : WTerm :=
let (a,x) := R in
exist wf_term (mk_spertype a) (wf_spertype a x).
Lemma mkc_spertype_eq {p} :
forall R1 R2 : @CTerm p, mkc_spertype R1 = mkc_spertype R2 -> R1 = R2.
Proof.
introv h.
destruct_cterms; allsimpl.
inversion h; subst.
eauto with pi.
Qed.
Definition mkc_tuni {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_tuni a) (isprog_tuni a x).
Lemma mkc_tuni_eq {p} :
forall R1 R2 : @CTerm p, mkc_tuni R1 = mkc_tuni R2 -> R1 = R2.
Proof.
introv h.
destruct_cterms; allsimpl.
inversion h; subst.
eauto with pi.
Qed.
Lemma wf_sleep {p} :
forall a : @NTerm p, wf_term a -> wf_term (mk_sleep a).
Proof.
introv h.
apply nt_wf_eq; apply nt_wf_eq in h.
intros; inversion h; subst;
constructor; allsimpl; sp;
subst; auto; simpl; constructor; auto.
Qed.
Lemma isprogram_sleep {p} :
forall a : @NTerm p, isprogram a -> isprogram (mk_sleep a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl; sp.
apply nt_wf_eq.
allrw @nt_wf_eq.
apply wf_sleep; sp.
Qed.
Lemma isprogram_sleep_iff {p} :
forall a : @NTerm p, isprogram a <=> isprogram (mk_sleep a).
Proof.
intros; split; intro i.
apply isprogram_sleep; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Lemma isprog_sleep {p} :
forall a : @NTerm p, isprog a -> isprog (mk_sleep a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_sleep; auto.
Qed.
Definition mkc_sleep {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_sleep a) (isprog_sleep a x).
Lemma mkc_sleep_eq {p} :
forall a b : @CTerm p, mkc_sleep a = mkc_sleep b -> a = b.
Proof.
introv h.
destruct_cterms; allsimpl.
inversion h; subst.
eauto with pi.
Qed.
Lemma wf_exception {p} :
forall a (e : @NTerm p),
wf_term a
-> wf_term e
-> wf_term (mk_exception a e).
Proof.
introv h1 h2.
allrw <- @nt_wf_eq.
intros; inversion h1; inversion h2; subst;
constructor; allsimpl; sp;
subst; auto; simpl; constructor; auto.
Qed.
Lemma isprogram_exception {p} :
forall a (e : @NTerm p),
isprogram a
-> isprogram e
-> isprogram (mk_exception a e).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl; sp.
apply nt_wf_eq.
allrw @nt_wf_eq.
apply wf_exception; sp.
Qed.
Lemma isprogram_exception_iff {p} :
forall a (e : @NTerm p),
isprogram (mk_exception a e) <=> (isprogram a # isprogram e).
Proof.
intros; split; intro i.
- inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd e)); intros i1 i2.
dest_imp i1 hyp.
dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
inversion i2; subst; sp.
- apply isprogram_exception; sp.
Qed.
Lemma isprog_exception {p} :
forall a (e : @NTerm p),
isprog a
-> isprog e
-> isprog (mk_exception a e).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_exception; auto.
Qed.
Definition mkc_exception {p} (a e : @CTerm p) : CTerm :=
let (u,y) := a in
let (t,x) := e in
exist isprog (mk_exception u t) (isprog_exception u t y x).
Lemma mkc_exception_eq {p} :
forall a b (t u : @CTerm p),
mkc_exception a t = mkc_exception b u
-> (a = b # t = u).
Proof.
introv h.
destruct_cterms; allsimpl.
inversion h; subst.
dands; eauto with pi.
Qed.
Lemma wf_try {p} :
forall (a : @NTerm p) x v b,
wf_term a
-> wf_term x
-> wf_term b
-> wf_term (mk_try a x v b).
Proof.
introv; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_try_iff {p} :
forall (a : @NTerm p) x v b,
(wf_term a # wf_term x # wf_term b) <=> wf_term (mk_try a x v b).
Proof.
sp; split; intros i.
apply wf_try; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst.
generalize (k (nobnd a)) (k (nobnd x)) (k (bterm [v] b)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Lemma isprogram_try {p} :
forall (a : @NTerm p) x v b,
isprogram a
-> isprogram x
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_try a x v b).
Proof.
sp.
repeat constructor; sp.
- unfold closed; simpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; sp.
+ allunfold @isprogram; allunfold @closed; sp.
+ allunfold @isprogram; allunfold @closed; sp.
+ allrw subvars_eq.
rw <- null_iff_nil.
rw null_remove_nvars; simpl; sp.
- allsimpl; sp; subst.
+ constructor; allunfold @isprogram; sp.
+ constructor; allunfold @isprogram; sp.
+ constructor; sp.
Qed.
Lemma isprogram_try_iff {p} :
forall (a : @NTerm p) x v b,
isprogram (mk_try a x v b)
<=> isprogram a
# isprogram x
# subvars (free_vars b) [v]
# nt_wf b.
Proof.
sp; split; intros i.
- inversion i as [ cl w ].
inversion w as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (nobnd x)) (k (bterm [v] b)); simpl; intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
inversion i1; inversion i2; inversion i3; subst.
inversion cl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
unfold isprogram, closed.
onerw app_eq_nil_iff; repd; allrw; sp;
onerw app_eq_nil_iff; repd; allrw; sp.
allrw <- null_iff_nil.
allrw null_remove_nvars; allsimpl.
rw subvars_eq.
unfold subset; sp; simpl.
- apply isprogram_try; sp.
Qed.
Lemma isprogram_try_iff2 {p} :
forall (a : @NTerm p) x v b,
isprogram (mk_try a x v b)
<=> isprogram a # isprogram x # isprogram_bt (bterm [v] b).
Proof.
introv.
rw @isprogram_try_iff.
unfold isprogram_bt; simpl.
unfold closed_bt; simpl.
rw <- null_iff_nil.
rw null_remove_nvars.
rw subvars_prop.
split; intro k; repnd; dands; auto.
inversion k; sp.
Qed.
Lemma isprog_try {p} :
forall (a : @NTerm p) x v b,
isprog a
-> isprog x
-> isprog_vars [v] b
-> isprog (mk_try a x v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_try; sp.
Qed.
Definition mkc_try {p} (t1 : @CTerm p) (n : @CTerm p) (v : NVar) (t2 : CVTerm [v]) : CTerm :=
let (a,x) := t1 in
let (c,z) := n in
let (b,y) := t2 in
exist isprog (mk_try a c v b) (isprog_try a c v b x z y).
(*
Definition mkc_esquash (R : CTerm) : CTerm :=
let (a,x) := R in
exist isprog (mk_esquash a) (isprog_esquash a x).
Definition mkw_esquash (R : WTerm) : WTerm :=
let (a,x) := R in
exist wf_term (mk_esquash a) (wf_esquash a x).
Lemma mkc_esquash_eq :
forall R1 R2, mkc_esquash R1 = mkc_esquash R2 -> R1 = R2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
assert (i = i0) by apply isprog_proof_irrelevance; subst; sp.
Qed.
*)
Definition mkc_isinl {p} (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_isinl a b c) (isprog_isinl a b c x y z).
Lemma mkc_isinl_eq {p} :
forall a b c d e f : @CTerm p,
mkc_isinl a b c = mkc_isinl d e f
-> a = d # b = e # c = f.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto 6 with pi.
Qed.
Definition mkc_isinr {p} (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_isinr a b c) (isprog_isinr a b c x y z).
Lemma mkc_isinr_eq {p} :
forall a b c d e f : @CTerm p,
mkc_isinr a b c = mkc_isinr d e f
-> a = d # b = e # c = f.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto 6 with pi.
Qed.
Definition mkc_ispair {p} (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_ispair a b c) (isprog_ispair a b c x y z).
Lemma mkc_ispair_eq {p} :
forall a b c d e f : @CTerm p,
mkc_ispair a b c = mkc_ispair d e f
-> a = d # b = e # c = f.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto 6 with pi.
Qed.
Definition mkc_isaxiom {p} (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_isaxiom a b c) (isprog_isaxiom a b c x y z).
Lemma mkc_isaxiom_eq {p} :
forall a b c d e f : @CTerm p,
mkc_isinl a b c = mkc_isaxiom d e f
-> a = d # b = e # c = f.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
Qed.
Definition mkc_islambda {p} (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_islambda a b c) (isprog_islambda a b c x y z).
Lemma mkc_islambda_eq {p} :
forall a b c d e f : @CTerm p,
mkc_isinl a b c = mkc_islambda d e f
-> a = d # b = e # c = f.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
Qed.
Definition mkc_can_test {p} (test: CanonicalTest) (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_can_test test a b c) (isprog_can_test test a b c x y z).
Definition mk_approx_c {p} (t1 t2 : @CTerm p) : NTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
mk_approx a b.
Definition mkc_approx {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_approx a b) (isprog_approx a b x y).
Definition mkw_approx {p} (t1 t2 : @WTerm p) : WTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist wf_term (mk_approx a b) (wf_approx a b x y).
Lemma mkw_approx_eq {p} :
forall a b c d : @WTerm p,
mkw_approx a b = mkw_approx c d
-> a = c # b = d.
Proof.
intros.
destruct a, b, c, d.
allunfold @mkw_approx.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_approx_eq {p} :
forall a b c d : @CTerm p,
mkc_approx a b = mkc_approx c d
-> a = c # b = d.
Proof.
intros.
destruct a, b, c, d.
allunfold @mkc_approx.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_cequiv {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_cequiv a b) (isprog_cequiv a b x y).
Definition mkw_cequiv {p} (t1 t2 : @WTerm p) : WTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist wf_term (mk_cequiv a b) (wf_cequiv a b x y).
Lemma mkw_cequiv_eq {p} :
forall a b c d : @WTerm p,
mkw_cequiv a b = mkw_cequiv c d
-> a = c # b = d.
Proof.
intros.
destruct a, b, c, d.
allunfold @mkw_cequiv.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_cequiv_eq {p} :
forall a b c d : @CTerm p,
mkc_cequiv a b = mkc_cequiv c d
-> a = c # b = d.
Proof.
intros.
destruct a, b, c, d.
allunfold @mkc_cequiv.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_compute {p} (t1 t2 n : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := n in
exist isprog (mk_compute a b c) (isprog_compute a b c x y z).
Lemma mkc_compute_eq {p} :
forall a b c d n m : @CTerm p,
mkc_compute a b n = mkc_compute c d m
-> a = c # b = d # n = m.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto 6 with pi.
Qed.
Definition mkc_image {p} (T F : @CTerm p) : CTerm :=
let (t,x) := T in
let (f,y) := F in
exist isprog (mk_image t f) (isprog_image t f x y).
Lemma mkc_image_eq {p} :
forall A1 A2 f1 f2 : @CTerm p,
mkc_image A1 f1 = mkc_image A2 f2
-> A1 = A2 # f1 = f2.
Proof.
introv e.
destruct_cterms; allsimpl.
inversion e; subst; irr; sp.
Qed.
(* end hide *)
(**
Using the [CVTerm] and [CTerm] types we can define useful
abstraction to build closed versions of the various terms of our
computation system. For example, given a variable [v] and a term in
[CVTerm [v]], we can build a closed lambda abstraction. As an other
example, given two closed terms, we can build a closed application
term.
*)
Definition mkc_lam {p} (v : NVar) (b : @CVTerm p [v]) : CTerm :=
let (t,x) := b in
exist isprog (mk_lam v t) (isprog_lam v t x).
Definition mkc_apply {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_apply a b) (isprog_apply a b x y).
(* begin hide *)
Lemma mkc_apply_eq {p} :
forall t1 t2 t3 t4 : @CTerm p,
mkc_apply t1 t2 = mkc_apply t3 t4 -> t1 = t3 # t2 = t4.
Proof.
introv e; destruct_cterms; allsimpl.
inversion e; subst.
irr; sp.
Qed.
Definition mkw_apply {p} (t1 t2 : @WTerm p) : WTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist wf_term (mk_apply a b) (wf_apply a b x y).
Definition mkc_apply2 {p} (t0 t1 t2 : @CTerm p) : CTerm :=
let (f,z) := t0 in
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_apply2 f a b) (isprog_apply2 f a b z x y).
Lemma mkc_apply2_eq {p} :
forall t0 t1 t2 : @CTerm p,
mkc_apply2 t0 t1 t2 = mkc_apply (mkc_apply t0 t1) t2.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Theorem wf_apply3 {p} :
forall f a b c : @NTerm p,
wf_term f
-> wf_term a
-> wf_term b
-> wf_term c
-> wf_term (mk_apply3 f a b c).
Proof.
unfold mk_apply3; sp.
repeat (apply wf_apply); auto.
Qed.
Theorem isprogram_apply3 {p} :
forall f a b c : @NTerm p,
isprogram f
-> isprogram a
-> isprogram b
-> isprogram c
-> isprogram (mk_apply3 f a b c).
Proof.
unfold mk_apply3; sp.
repeat (apply isprogram_apply); auto.
Qed.
Theorem isprog_apply3 {p} :
forall f a b c : @NTerm p,
isprog f
-> isprog a
-> isprog b
-> isprog c
-> isprog (mk_apply3 f a b c).
Proof.
sp; allrw @isprog_eq.
apply isprogram_apply3; auto.
Qed.
Definition mkc_apply3 {p} (t0 t1 t2 t3 : @CTerm p) : CTerm :=
let (f,u) := t0 in
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_apply3 f a b c) (isprog_apply3 f a b c u x y z).
Lemma mkc_apply3_eq {p} :
forall t0 t1 t2 t3 : @CTerm p,
mkc_apply3 t0 t1 t2 t3 = mkc_apply (mkc_apply (mkc_apply t0 t1) t2) t3.
Proof.
intros; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_eapply {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_eapply a b) (isprog_eapply a b x y).
Lemma mkc_eapply_eq {p} :
forall t1 t2 t3 t4 : @CTerm p,
mkc_eapply t1 t2 = mkc_eapply t3 t4 -> t1 = t3 # t2 = t4.
Proof.
introv e; destruct_cterms; allsimpl.
inversion e; subst.
irr; sp.
Qed.
Definition mkc_apseq {p} f (t : @CTerm p) : CTerm :=
let (a,x) := t in
exist isprog (mk_apseq f a) (isprog_apseq f a x).
Lemma mkc_apseq_eq {p} :
forall f1 f2 (t1 t2 : @CTerm p),
mkc_apseq f1 t1 = mkc_apseq f2 t2 -> f1 = f2 # t1 = t2.
Proof.
introv e; destruct_cterms; allsimpl.
inversion e; subst.
irr; sp.
Qed.
(*Definition mkw_apply2 (t0 t1 t2 : WTerm) : WTerm :=
let (f,z) := t0 in
let (a,x) := t1 in
let (b,y) := t2 in
exist wf_term (mk_apply2 f a b) (wf_apply2 f a b z x y).*)
Definition mkc_free_from_atom {p} (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_free_from_atom a b c) (isprog_free_from_atom a b c x y z).
Lemma mkc_free_from_atom_eq {p} :
forall a b c d e f : @CTerm p,
mkc_free_from_atom a b c = mkc_free_from_atom d e f
-> a = d # b = e # c = f.
Proof.
introv h.
destruct_cterms; allsimpl.
inversion h; subst.
eauto 6 with pi.
Qed.
Definition mkc_free_from_atoms {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_free_from_atoms a b) (isprog_free_from_atoms a b x y).
Lemma mkc_free_from_atoms_eq {p} :
forall a b c d : @CTerm p,
mkc_free_from_atoms a b = mkc_free_from_atoms c d
-> a = c # b = d.
Proof.
introv h.
destruct_cterms; allsimpl.
inversion h; subst.
eauto 6 with pi.
Qed.
Definition mkc_equality {p} (t1 t2 T : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := T in
exist isprog (mk_equality a b c) (isprog_equality a b c x y z).
Definition mkw_equality {p} (t1 t2 T : @WTerm p) : WTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := T in
exist wf_term (mk_equality a b c) (wf_equality a b c x y z).
Lemma mkw_equality_eq {p} :
forall a b c d T U : @WTerm p,
mkw_equality a b T = mkw_equality c d U
-> a = c # b = d # T = U.
Proof.
intros.
destruct a, b, c, d, T, U.
allunfold @mkw_equality.
inversion H; subst.
eauto 6 with pi.
Qed.
Lemma mkc_equality_eq {p} :
forall a b c d T U : @CTerm p,
mkc_equality a b T = mkc_equality c d U
-> a = c # b = d # T = U.
Proof.
intros.
destruct a, b, c, d, T, U.
allunfold @mkc_equality.
inversion H; subst.
eauto 6 with pi.
Qed.
Definition mkc_member {p} (t T : @CTerm p) : CTerm :=
let (a,x) := t in
let (b,y) := T in
exist isprog (mk_member a b) (isprog_member a b x y).
Lemma fold_mkc_member {p} :
forall t T : @CTerm p,
mkc_equality t t T = mkc_member t T.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_tequality {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_tequality a b) (isprog_tequality a b x y).
Lemma mkc_tequality_eq {p} :
forall a b c d : @CTerm p,
mkc_tequality a b = mkc_tequality c d
-> a = c # b = d.
Proof.
intros.
destruct_cterms.
allunfold @mkc_tequality.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_type {p} (t : @CTerm p) : CTerm :=
let (a,x) := t in exist isprog (mk_type a) (isprog_type a x).
Lemma fold_mkc_type {p} :
forall t : @CTerm p, mkc_tequality t t = mkc_type t.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_cbv {p} (t1 : @CTerm p) (v : NVar) (t2 : CVTerm [v]) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_cbv a v b) (isprog_cbv a v b x y).
Definition mkc_halts {p} (t : @CTerm p) : CTerm :=
let (a,x) := t in
exist isprog (mk_halts a) (isprog_halts a x).
Lemma isprog_vars_axiom {p} :
forall v,
@isprog_vars p [v] mk_axiom.
Proof.
unfold isprog_vars; sp.
Qed.
Definition mkcv_axiom {p} (v : NVar) : @CVTerm p [v] :=
exist (isprog_vars [v]) mk_axiom (isprog_vars_axiom v).
Lemma fold_mkc_halts {p} :
forall t : @CTerm p,
mkc_approx mkc_axiom (mkc_cbv t nvarx (mkcv_axiom nvarx)) = mkc_halts t.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Lemma isprogram_spread {p} :
forall (a : @NTerm p) v1 v2 b,
isprogram a
-> subvars (free_vars b) [v1,v2]
-> nt_wf b
-> isprogram (mk_spread a v1 v2 b).
Proof.
unfold isprogram, closed; introv ipa sv ntb; repnd; simpl.
allrw; simpl.
allrw subvars_prop; allsimpl.
allrw app_nil_r.
rw <- null_iff_nil; rw null_remove_nvars.
dands.
introv i.
apply sv in i; sp.
constructor; simpl.
introv e; repdors; subst; try (complete sp).
constructor; sp.
constructor.
Qed.
Lemma isprog_spread {p} :
forall (a : @NTerm p) v1 v2 b,
isprog a
-> isprog_vars [v1,v2] b
-> isprog (mk_spread a v1 v2 b).
Proof.
introv ipa ipb.
allrw @isprog_eq.
allrw @isprog_vars_eq.
apply isprogram_spread; sp.
Qed.
Definition mkc_spread {p}
(t1 : @CTerm p)
(v1 v2 : NVar)
(t2 : CVTerm [v1,v2]) : CTerm :=
let (a,x1) := t1 in
let (b,x2) := t2 in
exist isprog (mk_spread a v1 v2 b) (isprog_spread a v1 v2 b x1 x2).
Lemma mkc_spread_eq1 {p} :
forall (a1 : @CTerm p) x1 y1 b1 a2 x2 y2 b2,
mkc_spread a1 x1 y1 b1 = mkc_spread a2 x2 y2 b2
-> a1 = a2 # x1 = x2 # y1 = y2.
Proof.
introv e.
destruct a1, a2, b1, b2.
allunfold @mkc_spread.
inversion e; subst.
eauto with pi.
Qed.
Lemma mkc_spread_eq2 {p} :
forall (a : @CTerm p) x y b1 b2,
mkc_spread a x y b1 = mkc_spread a x y b2
-> b1 = b2.
Proof.
introv e.
destruct a, b1, b2.
allunfold @mkc_spread.
inversion e; subst.
eauto with pi.
Qed.
Lemma isprogram_dsup {p} :
forall (a : @NTerm p) v1 v2 b,
isprogram a
-> subvars (free_vars b) [v1,v2]
-> nt_wf b
-> isprogram (mk_dsup a v1 v2 b).
Proof.
unfold isprogram, closed; introv ipa sv ntb; repnd; simpl.
allrw; simpl.
allrw subvars_prop; allsimpl.
allrw app_nil_r.
rw <- null_iff_nil; rw null_remove_nvars.
dands.
introv i.
apply sv in i; sp.
constructor; simpl.
introv e; repdors; subst; try (complete sp).
constructor; sp.
constructor.
Qed.
Lemma isprog_dsup {p} :
forall (a : @NTerm p) v1 v2 b,
isprog a
-> isprog_vars [v1,v2] b
-> isprog (mk_dsup a v1 v2 b).
Proof.
introv ipa ipb.
allrw @isprog_eq.
allrw @isprog_vars_eq.
apply isprogram_dsup; sp.
Qed.
Definition mkc_dsup {p}
(t1 : @CTerm p)
(v1 v2 : NVar)
(t2 : CVTerm [v1,v2]) : CTerm :=
let (a,x1) := t1 in
let (b,x2) := t2 in
exist isprog (mk_dsup a v1 v2 b) (isprog_dsup a v1 v2 b x1 x2).
Lemma isprogram_decide {p} :
forall (a : @NTerm p) v1 a1 v2 a2,
isprogram a
-> subvars (free_vars a1) [v1]
-> nt_wf a1
-> subvars (free_vars a2) [v2]
-> nt_wf a2
-> isprogram (mk_decide a v1 a1 v2 a2).
Proof.
unfold isprogram, closed; introv ipa sv1 nt1 sv2 nt2; repnd; simpl.
allrw; simpl.
allrw subvars_eq.
unfold subset in sv1, sv2; sp.
assert (remove_nvars [v1] (free_vars a1) = []) as eq1.
rw <- null_iff_nil; rw null_remove_nvars; introv ia1.
apply sv1 in ia1; sp.
assert (remove_nvars [v2] (free_vars a2) = []) as eq2.
rw <- null_iff_nil; rw null_remove_nvars; introv ia2.
apply sv2 in ia2; sp.
rw eq1; rw eq2; sp.
repeat (constructor; simpl; sp; subst).
Qed.
Lemma isprog_decide {p} :
forall (a : @NTerm p) v1 a1 v2 a2,
isprog a
-> isprog_vars [v1] a1
-> isprog_vars [v2] a2
-> isprog (mk_decide a v1 a1 v2 a2).
Proof.
introv ipa ipa1 ipa2.
allrw @isprog_eq.
allrw @isprog_vars_eq.
apply isprogram_decide; sp.
Qed.
Definition mkc_decide {p}
(t : @CTerm p)
(v1 : NVar)
(t1 : CVTerm [v1])
(v2 : NVar)
(t2 : CVTerm [v2]) : CTerm :=
let (a,x) := t in
let (a1,x1) := t1 in
let (a2,x2) := t2 in
exist isprog (mk_decide a v1 a1 v2 a2) (isprog_decide a v1 a1 v2 a2 x x1 x2).
Definition mkc_ite {p} (a b c : @CTerm p) :=
let (t1,x1) := a in
let (t2,x2) := b in
let (t3,x3) := c in
exist isprog
(mk_decide t1 nvarx t2 nvarx t3)
(isprog_decide t1 nvarx t2 nvarx t3
x1
(isprog_vars_if_isprog [nvarx] t2 x2)
(isprog_vars_if_isprog [nvarx] t3 x3)).
Lemma mkc_ite_eq_mkc_decide {p} :
forall a b c : @CTerm p,
mkc_ite a b c = mkc_decide a nvarx (mk_cv [nvarx] b) nvarx (mk_cv [nvarx] c).
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_isect {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_isect a v b) (isprog_isect a v b x y).
Definition mkw_isect {p} (T1 : @WTerm p) (v : NVar) (T2 : WTerm) : WTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist wf_term (mk_isect a v b) (wf_isect a v b x y).
Lemma mkw_isect_eq {p} :
forall (a1 : @WTerm p) v1 b1 a2 v2 b2,
mkw_isect a1 v1 b1 = mkw_isect a2 v2 b2
-> a1 = a2 # v1 = v2 # b1 = b2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkw_isect.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_isect_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_isect a1 v1 b1 = mkc_isect a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_isect.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_isect_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_isect a v b1 = mkc_isect a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_isect.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_uall {p} := @mkc_isect p.
Definition mkc_eisect {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_eisect a v b) (isprog_eisect a v b x y).
Lemma mkc_eisect_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_eisect a1 v1 b1 = mkc_eisect a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_eisect.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_eisect_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_eisect a v b1 = mkc_eisect a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_eisect.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_disect {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_disect a v b) (isprog_disect a v b x y).
Definition mkw_disect {p} (T1 : @WTerm p) (v : NVar) (T2 : WTerm) : WTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist wf_term (mk_disect a v b) (wf_disect a v b x y).
Lemma mkw_disect_eq {p} :
forall (a1 : @WTerm p) v1 b1 a2 v2 b2,
mkw_disect a1 v1 b1 = mkw_disect a2 v2 b2
-> a1 = a2 # v1 = v2 # b1 = b2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkw_disect.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_disect_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_disect a1 v1 b1 = mkc_disect a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_disect.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_disect_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_disect a v b1 = mkc_disect a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_disect.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_set {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_set a v b) (isprog_set a v b x y).
Lemma mkc_set_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_set a1 v1 b1 = mkc_set a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_set.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_set_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_set a v b1 = mkc_set a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_set.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_tunion {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_tunion a v b) (isprog_tunion a v b x y).
Lemma mkc_tunion_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_tunion a1 v1 b1 = mkc_tunion a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_tunion.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_tunion_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_tunion a v b1 = mkc_tunion a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_tunion.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_quotient {p} (T1 : @CTerm p) (v1 v2 : NVar) (T2 : CVTerm [v1,v2]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_quotient a v1 v2 b) (isprog_quotient a v1 v2 b x y).
Lemma mkc_quotient_eq1 {p} :
forall (a1 : @CTerm p) v1 u1 b1 a2 v2 u2 b2,
mkc_quotient a1 v1 u1 b1 = mkc_quotient a2 v2 u2 b2
-> a1 = a2 # v1 = v2 # u1 = u2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_quotient.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_quotient_eq2 {p} :
forall (a : @CTerm p) v1 v2 b1 b2,
mkc_quotient a v1 v2 b1 = mkc_quotient a v1 v2 b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_quotient.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_w {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_w a v b) (isprog_w a v b x y).
Definition mkw_w {p} (T1 : @WTerm p) (v : NVar) (T2 : WTerm) : WTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist wf_term (mk_w a v b) (wf_w a v b x y).
Lemma mkw_w_eq {p} :
forall (a1 : @WTerm p) v1 b1 a2 v2 b2,
mkw_w a1 v1 b1 = mkw_w a2 v2 b2
-> a1 = a2 # v1 = v2 # b1 = b2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkw_w.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_w_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_w a1 v1 b1 = mkc_w a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_w.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_w_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_w a v b1 = mkc_w a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_w.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_m {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_m a v b) (isprog_m a v b x y).
Definition mkw_m {p} (T1 : @WTerm p) (v : NVar) (T2 : WTerm) : WTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist wf_term (mk_m a v b) (wf_w a v b x y).
Lemma mkw_m_eq {p} :
forall (a1 : @WTerm p) v1 b1 a2 v2 b2,
mkw_m a1 v1 b1 = mkw_m a2 v2 b2
-> a1 = a2 # v1 = v2 # b1 = b2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkw_m.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_m_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_m a1 v1 b1 = mkc_m a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_w.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_m_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_m a v b1 = mkc_m a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_w.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_pw {p}
(P : @CTerm p)
(ap : NVar) (A : CVTerm [ap])
(bp : NVar) (ba : NVar) (B : CVTerm [bp, ba])
(cp : NVar) (ca : NVar) (cb : NVar) (C : CVTerm [cp, ca, cb])
(p : CTerm) : CTerm :=
let (tP,wP) := P in
let (tA,wA) := A in
let (tB,wB) := B in
let (tC,wC) := C in
let (tp,wp) := p in
exist isprog
(mk_pw tP ap tA bp ba tB cp ca cb tC tp)
(isprog_pw tP ap tA bp ba tB cp ca cb tC tp wP wA wB wC wp).
Lemma mkc_pw_eq1 {p} :
forall (P1 : @CTerm p) ap1 A1 bp1 ba1 B1 cp1 ca1 cb1 C1 p1
P2 ap2 A2 bp2 ba2 B2 cp2 ca2 cb2 C2 p2,
mkc_pw P1 ap1 A1 bp1 ba1 B1 cp1 ca1 cb1 C1 p1
= mkc_pw P2 ap2 A2 bp2 ba2 B2 cp2 ca2 cb2 C2 p2
-> P1 = P2
# p1 = p2
# ap1 = ap2
# bp1 = bp2
# ba1 = ba2
# cp1 = cp2
# ca1 = ca2
# cb1 = cb2.
Proof.
introv e.
destruct_cterms; allsimpl.
inversion e; subst; irr; sp.
Qed.
Lemma mkc_pw_eq2 {p} :
forall (P : @CTerm p) ap bp ba cp ca cb p A1 B1 C1 A2 B2 C2,
mkc_pw P ap A1 bp ba B1 cp ca cb C1 p
= mkc_pw P ap A2 bp ba B2 cp ca cb C2 p
-> A1 = A2 # B1 = B2 # C1 = C2.
Proof.
introv e.
destruct_cterms; allsimpl.
inversion e; subst; irr; sp.
Qed.
Lemma isprog_vars_pw {p} :
forall vs (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprog P
-> isprog_vars [ap] A
-> isprog_vars [bp, ba] B
-> isprog_vars [cp, ca, cb] C
-> isprog_vars vs p
-> isprog_vars vs (mk_pw P ap A bp ba B cp ca cb C p).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
simpl.
allunfold @isprogram; repnd.
allrw subvars_app_l; allrw remove_nvars_nil_l; allrw; sp;
allrw subvars_prop; introv i; allrw in_remove_nvars; allrw in_single_iff;
repnd; discover; allrw in_single_iff; sp.
constructor; simpl; sp; subst; constructor; sp.
allunfold @isprogram; sp.
Qed.
Definition mkc_pw_vs {p}
(vs : list NVar)
(P : @CTerm p)
(ap : NVar) (A : CVTerm [ap])
(bp : NVar) (ba : NVar) (B : CVTerm [bp, ba])
(cp : NVar) (ca : NVar) (cb : NVar) (C : CVTerm [cp, ca, cb])
(p : CVTerm vs) : CVTerm vs :=
let (tP,wP) := P in
let (tA,wA) := A in
let (tB,wB) := B in
let (tC,wC) := C in
let (tp,wp) := p in
exist (isprog_vars vs)
(mk_pw tP ap tA bp ba tB cp ca cb tC tp)
(isprog_vars_pw vs tP ap tA bp ba tB cp ca cb tC tp wP wA wB wC wp).
Definition mkc_pm {p}
(P : @CTerm p)
(ap : NVar) (A : CVTerm [ap])
(bp : NVar) (ba : NVar) (B : CVTerm [bp, ba])
(cp : NVar) (ca : NVar) (cb : NVar) (C : CVTerm [cp, ca, cb])
(p : CTerm) : CTerm :=
let (tP,wP) := P in
let (tA,wA) := A in
let (tB,wB) := B in
let (tC,wC) := C in
let (tp,wp) := p in
exist isprog
(mk_pm tP ap tA bp ba tB cp ca cb tC tp)
(isprog_pm tP ap tA bp ba tB cp ca cb tC tp wP wA wB wC wp).
Lemma mkc_pm_eq1 {p} :
forall (P1 : @CTerm p) ap1 A1 bp1 ba1 B1 cp1 ca1 cb1 C1 p1
P2 ap2 A2 bp2 ba2 B2 cp2 ca2 cb2 C2 p2,
mkc_pm P1 ap1 A1 bp1 ba1 B1 cp1 ca1 cb1 C1 p1
= mkc_pm P2 ap2 A2 bp2 ba2 B2 cp2 ca2 cb2 C2 p2
-> P1 = P2
# p1 = p2
# ap1 = ap2
# bp1 = bp2
# ba1 = ba2
# cp1 = cp2
# ca1 = ca2
# cb1 = cb2.
Proof.
introv e.
destruct_cterms; allsimpl.
inversion e; subst; irr; sp.
Qed.
Lemma mkc_pm_eq2 {p} :
forall (P : @CTerm p) ap bp ba cp ca cb p A1 B1 C1 A2 B2 C2,
mkc_pm P ap A1 bp ba B1 cp ca cb C1 p
= mkc_pm P ap A2 bp ba B2 cp ca cb C2 p
-> A1 = A2 # B1 = B2 # C1 = C2.
Proof.
introv e.
destruct_cterms; allsimpl.
inversion e; subst; irr; sp.
Qed.
Definition mkc_function {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_function a v b) (isprog_function a v b x y).
Definition mkw_function {p} (T1 : @WTerm p) (v : NVar) (T2 : WTerm) :=
let (a,x) := T1 in
let (b,y) := T2 in
exist wf_term (mk_function a v b) (wf_function a v b x y).
Lemma mkc_function_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_function a1 v1 b1 = mkc_function a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_function.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_function_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_function a v b1 = mkc_function a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_function.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_product {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_product a v b) (isprog_product a v b x y).
Definition mkw_product {p} (T1 : @WTerm p) (v : NVar) (T2 : WTerm) :=
let (a,x) := T1 in
let (b,y) := T2 in
exist wf_term (mk_product a v b) (wf_product a v b x y).
Lemma mkc_product_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_product a1 v1 b1 = mkc_product a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_product.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_product_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_product a v b1 = mkc_product a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_product.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_var {p} (v : NVar) : @CVTerm p [v] :=
exist (isprog_vars [v]) (mk_var v) (isprog_vars_var v).
Definition mkc_vsubtype {p} (T1 : @CTerm p) (v : NVar) (T2 : CTerm) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_vsubtype a v b) (isprog_vsubtype a v b x y).
Definition mkc_subtype {p} (T1 : @CTerm p) (T2 : CTerm) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_subtype a b) (isprog_subtype a b x y).
(** newvar on closed terms *)
Definition cnewvar {p} (t : @CTerm p) := newvar (projT1 t).
Lemma cnewvar_eq {p} :
forall t : @CTerm p, cnewvar t = nvarx.
Proof.
destruct t; unfold cnewvar, newvar; simpl.
rw @isprog_eq in i.
inversion i.
unfold closed in H.
rewrite H.
unfold fresh_var; sp.
Qed.
Lemma isprog_vars_cvterm_var {p} :
forall v : NVar,
forall t : @CTerm p,
isprog_vars [v] (projT1 t).
Proof.
destruct t; unfold cnewvar.
rw @isprog_vars_eq; simpl.
rw @isprog_eq in i.
inversion i; sp.
unfold closed in H.
rewrite H; sp.
Qed.
Lemma isprog_vars_cvterm_newvar {p} :
forall t : @CTerm p,
isprog_vars [cnewvar t] (projT1 t).
Proof.
sp; apply isprog_vars_cvterm_var.
Qed.
(** Builds, from a closed term t, a term that has at most one free variable,
* namely v, which we know not to be in t.
* The term is the same. Only the proof of closeness changes. *)
Definition cvterm_var {p} (v : NVar) (t : @CTerm p) : CVTerm [v] :=
exist (isprog_vars [v])
(projT1 t)
(isprog_vars_cvterm_var v t).
Definition cvterm_newvar {p} (t : @CTerm p) : CVTerm [cnewvar t] :=
cvterm_var (cnewvar t) t.
Lemma mk_cv_as_cvterm_var {p} :
forall v (t : @CTerm p), mk_cv [v] t = cvterm_var v t.
Proof.
intros.
destruct_cterms.
apply cvterm_eq; simpl; auto.
Qed.
Definition mkc_fun {p} (A B : @CTerm p) : CTerm :=
let (a,x) := A in
let (b,y) := B in
exist isprog (mk_fun a b) (isprog_fun a b x y).
Lemma fold_mkc_fun {p} :
forall (A B : @CTerm p),
mkc_function A (cnewvar B) (mk_cv [cnewvar B] B)
= mkc_fun A B.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_ufun {p} (A B : @CTerm p) : CTerm :=
let (a,x) := A in
let (b,y) := B in
exist isprog (mk_ufun a b) (isprog_ufun a b x y).
Lemma fold_mkc_ufun {p} :
forall (A B : @CTerm p),
mkc_isect A (cnewvar B) (mk_cv [cnewvar B] B)
= mkc_ufun A B.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_eufun {p} (A B : @CTerm p) : CTerm :=
let (a,x) := A in
let (b,y) := B in
exist isprog (mk_eufun a b) (isprog_eufun a b x y).
Lemma fold_mkc_eufun {p} :
forall (A B : @CTerm p),
mkc_eisect A (cnewvar B) (mk_cv [cnewvar B] B)
= mkc_eufun A B.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_prod {p} (A B : @CTerm p) : CTerm :=
let (a,x) := A in
let (b,y) := B in
exist isprog (mk_prod a b) (isprog_prod a b x y).
Lemma fold_mkc_prod {p} :
forall (A B : @CTerm p),
mkc_product A (cnewvar B) (mk_cv [cnewvar B] B)
= mkc_prod A B.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_iff {p} (a b : @CTerm p) := mkc_prod (mkc_fun a b) (mkc_fun b a).
Definition mkc_id {p} : @CTerm p := mkc_lam nvarx (mkc_var nvarx).
Definition mkc_squash {p} (T : @CTerm p) :=
mkc_image T (mkc_lam nvarx (mk_cv [nvarx] mkc_axiom)).
Lemma get_cterm_mkc_squash {p} :
forall T : @CTerm p, get_cterm (mkc_squash T) = mk_squash (get_cterm T).
Proof.
intro; destruct_cterms; sp.
Qed.
Lemma isprogram_fix {p} :
forall t : @NTerm p, isprogram t -> isprogram (mk_fix t).
Proof.
introv isp.
repeat constructor; simpl; sp; subst.
unfold closed; simpl.
rewrite remove_nvars_nil_l.
rewrite app_nil_r.
inversion isp as [cl w]; sp.
inversion isp; sp.
Qed.
Lemma isprogram_fix_iff {p} :
forall a : @NTerm p, isprogram a <=> isprogram (mk_fix a).
Proof.
intros; split; intro i.
apply isprogram_fix; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Lemma isprog_fix {p} :
forall t : @NTerm p, isprog t -> isprog (mk_fix t).
Proof.
intro; repeat (rw @isprog_eq); sp.
apply isprogram_fix; sp.
Qed.
Lemma wf_fix {p} : forall t : @NTerm p, wf_term t -> wf_term (mk_fix t).
Proof.
introv wt.
allrw @wf_term_eq.
constructor; simpl; sp; subst.
constructor; auto.
Qed.
Lemma wf_bot {p} : @wf_term p mk_bot.
Proof.
unfold mk_bot, mk_bottom.
apply wf_fix.
apply wf_id.
Qed.
Hint Immediate wf_bot : wf.
Lemma isprogram_bot {p} : @isprogram p mk_bot.
Proof.
unfold mk_bot, mk_bottom.
apply isprogram_fix.
apply isprogram_lam; simpl.
apply isprog_vars_var.
Qed.
Hint Immediate isprogram_bot.
Lemma isprogram_mk_bot {p} : @isprogram p mk_bot.
Proof.
apply isprogram_bot.
Qed.
Hint Immediate isprogram_mk_bot.
Lemma isprog_bot {p} : @isprog p mk_bot.
Proof.
rw @isprog_eq.
apply isprogram_bot.
Qed.
Hint Immediate isprog_bot.
Lemma wf_vbot {p} : forall v, @wf_term p (mk_vbot v).
Proof.
introv.
unfold mk_vbot.
apply wf_fix.
apply wf_lam; sp.
Qed.
Hint Immediate wf_vbot : wf.
Lemma isprogram_vbot {p} : forall v, @isprogram p (mk_vbot v).
Proof.
introv.
unfold mk_vbot.
apply isprogram_fix.
apply isprogram_lam; simpl.
apply isprog_vars_var.
Qed.
Hint Immediate isprogram_vbot.
Lemma isprog_vbot {p} : forall v, @isprog p (mk_vbot v).
Proof.
introv.
rw @isprog_eq.
apply isprogram_vbot.
Qed.
Hint Immediate isprog_vbot.
Lemma isprogram_mk_false {p} :
@isprogram p mk_false.
Proof.
unfold mk_false.
apply isprogram_approx.
apply isprogram_axiom.
apply isprogram_bot.
Qed.
Hint Immediate isprogram_mk_false.
Lemma isprog_mk_false {p} :
@isprog p mk_false.
Proof.
rw @isprog_eq.
apply isprogram_mk_false.
Qed.
Lemma wf_mk_false {p} :
@wf_term p mk_false.
Proof.
sp.
Qed.
Definition mkc_false {p} : @CTerm p :=
exist isprog mk_false isprog_mk_false.
Definition mkc_bot {p} : @CTerm p :=
exist isprog mk_bot isprog_bot.
Definition mkc_fix {p} (t : @CTerm p) :=
let (a,x) := t in
exist isprog (mk_fix a) (isprog_fix a x).
Lemma mkc_bot_eq {p} :
@mkc_bot p = mkc_fix mkc_id.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Lemma mkc_false_eq {p} :
@mkc_false p = mkc_approx mkc_axiom mkc_bot.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Theorem isprogram_void {p} : @isprogram p mk_void.
Proof.
unfold mk_void; apply isprogram_mk_false.
Qed.
Theorem isprog_void {p} : @isprog p mk_void.
Proof.
unfold mk_void; apply isprog_mk_false.
Qed.
Theorem wf_void {p} : @wf_term p mk_void.
Proof.
sp.
Qed.
Definition mkc_void {p} : @CTerm p := exist isprog mk_void isprog_void.
Definition mkc_unit {p} : @CTerm p := exist isprog mk_unit isprog_unit.
Lemma mkc_unit_eq {p} : @mkc_unit p = mkc_approx mkc_axiom mkc_axiom.
Proof.
apply cterm_eq; auto.
Qed.
(*
Lemma isprogram_void_implies :
forall bterms,
isprogram (oterm (Can NVoid) bterms)
-> bterms = [].
Proof.
sp; allunfold isprogram; sp.
inversion X; subst; allsimpl.
allrw <- null_iff_nil; allsimpl.
allrw null_map; sp.
Qed.
*)
Lemma fold_mkc_vsubtype {p} :
forall (A : @CTerm p) v B,
mkc_member mkc_id (mkc_function A v (cvterm_var v B))
= mkc_vsubtype A v B.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Lemma fold_mkc_subtype {p} :
forall (A B : @CTerm p),
mkc_member mkc_id (mkc_function A (cnewvar B) (cvterm_newvar B))
= mkc_subtype A B.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_rec {p} (v : NVar) (t : @CVTerm p [v]) :=
let (a,x) := t in
exist isprog (mk_rec v a) (isprog_rec v a x).
Definition mkw_rec {p} (v : NVar) (t : @WTerm p) :=
let (a,x) := t in
exist wf_term (mk_rec v a) (wf_rec v a x).
Definition isvalue_wft {p} (t : @WTerm p) :=
let (a,_) := t in isvalue a.
Definition isovalue_wft {p} (t : @WTerm p) :=
let (a,_) := t in isovalue a.
Lemma isvalue_wft_mkw_approx {p} :
forall t : @WTerm p, isvalue_wft (mkw_approx t t).
Proof.
unfold isvalue_wft, mkw_approx; sp.
destruct t; simpl.
apply isvalue_approx.
Abort.
Lemma iscvalue_mkc_nat {p} : forall n : nat, @iscvalue p (mkc_nat n).
Proof.
repeat constructor; sp; allsimpl; sp.
Qed.
Theorem iscvalue_mkc_uni {p} : forall i : nat, @iscvalue p (mkc_uni i).
Proof.
repeat constructor; sp; allsimpl; sp.
Qed.
Lemma isvalue_wft_mkw_int {p} : @isvalue_wft p mkw_int.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Lemma isovalue_wft_mkw_int {p} : @isovalue_wft p mkw_int.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Lemma iscvalue_mkc_int {p} : @iscvalue p mkc_int.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Lemma isovalue_wft_mkw_axiom {p} : @isovalue_wft p mkw_axiom.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Theorem iscvalue_mkc_axiom {p} : @iscvalue p mkc_axiom.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Theorem iscvalue_mkc_base {p} : @iscvalue p mkc_base.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Hint Immediate iscvalue_mkc_nat.
Hint Immediate iscvalue_mkc_uni.
Hint Immediate iscvalue_mkc_int.
Hint Immediate iscvalue_mkc_axiom.
Hint Immediate iscvalue_mkc_base.
Lemma isovalue_wft_mkw_approx {p} :
forall t1 t2 : @WTerm p, isovalue_wft (mkw_approx t1 t2).
Proof.
intro; destruct t1; destruct t2; simpl.
apply isovalue_approx; allrw @nt_wf_eq; auto.
Qed.
Lemma iscvalue_mkc_approx {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_approx t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_approx; allrw @isprog_eq; auto.
Qed.
Lemma isovalue_wft_mkw_cequiv {p} :
forall t1 t2 : @WTerm p, isovalue_wft (mkw_cequiv t1 t2).
Proof.
intro; destruct t1; destruct t2; simpl.
apply isovalue_cequiv; allrw @nt_wf_eq; auto.
Qed.
Lemma iscvalue_mkc_cequiv {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_cequiv t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_cequiv; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_texc {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_texc t1 t2).
Proof.
introv; destruct_cterms; unfold iscvalue; simpl.
apply isvalue_texc; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_union {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_union t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_union; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_union2 {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_union2 t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_union2; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_image {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_image t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_image; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_pertype {p} :
forall t : @CTerm p, iscvalue (mkc_pertype t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_pertype; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_partial {p} :
forall t : @CTerm p, iscvalue (mkc_partial t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_partial; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_ipertype {p} :
forall t : @CTerm p, iscvalue (mkc_ipertype t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_ipertype; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_spertype {p} :
forall t : @CTerm p, iscvalue (mkc_spertype t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_spertype; allrw @isprog_eq; auto.
Qed.
(*
Lemma iscvalue_mkc_tuni :
forall t, iscvalue (mkc_tuni t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_tuni; allrw isprog_eq; auto.
Qed.
*)
(*
Lemma iscvalue_mkc_esquash :
forall t, iscvalue (mkc_esquash t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_esquash; allrw isprog_eq; auto.
Qed.
*)
Lemma mkw_integer_eq_nat {p} :
forall n,
@mkw_integer p (Z.of_nat n) = mkw_nat n.
Proof.
sp.
Qed.
Lemma iscvalue_mkc_equality {p} :
forall t1 t2 T : @CTerm p, iscvalue (mkc_equality t1 t2 T).
Proof.
intro; destruct t1; destruct t2; destruct T; unfold iscvalue; simpl.
apply isvalue_equality; allrw @isprog_eq; auto.
apply isprogram_equality; sp.
Qed.
Lemma isvalue_function {p} :
forall (a : @NTerm p) v b, isprogram (mk_function a v b) -> isvalue (mk_function a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_product {p} :
forall (a : @NTerm p) v b, isprogram (mk_product a v b) -> isvalue (mk_product a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_isect {p} :
forall (a : @NTerm p) v b, isprogram (mk_isect a v b) -> isvalue (mk_isect a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_eisect {p} :
forall (a : @NTerm p) v b, isprogram (mk_eisect a v b) -> isvalue (mk_eisect a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_disect {p} :
forall (a : @NTerm p) v b, isprogram (mk_disect a v b) -> isvalue (mk_disect a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_set {p} :
forall (a : @NTerm p) v b, isprogram (mk_set a v b) -> isvalue (mk_set a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_tunion {p} :
forall (a : @NTerm p) v b, isprogram (mk_tunion a v b) -> isvalue (mk_tunion a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_w {p} :
forall (a : @NTerm p) v b, isprogram (mk_w a v b) -> isvalue (mk_w a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_m {p} :
forall (a : @NTerm p) v b, isprogram (mk_m a v b) -> isvalue (mk_m a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_pw {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprogram (mk_pw P ap A bp ba B cp ca cb C p)
-> isvalue (mk_pw P ap A bp ba B cp ca cb C p).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_pm {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprogram (mk_pm P ap A bp ba B cp ca cb C p)
-> isvalue (mk_pm P ap A bp ba B cp ca cb C p).
Proof.
sp; constructor; sp.
Qed.
Lemma implies_isvalue_function {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_function a v b).
Proof.
sp.
apply isvalue_function.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_function; sp.
Qed.
Lemma implies_isvalue_product {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_product a v b).
Proof.
sp.
apply isvalue_product.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_product; sp.
Qed.
Lemma implies_isvalue_isect {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_isect a v b).
Proof.
sp.
apply isvalue_isect.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_isect; sp.
Qed.
Lemma implies_isvalue_eisect {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_eisect a v b).
Proof.
sp.
apply isvalue_eisect.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_eisect; sp.
Qed.
Lemma implies_isvalue_disect {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_disect a v b).
Proof.
sp.
apply isvalue_disect.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_disect; sp.
Qed.
Lemma implies_isvalue_set {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_set a v b).
Proof.
sp.
apply isvalue_set.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_set; sp.
Qed.
Lemma implies_isvalue_tunion {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_tunion a v b).
Proof.
sp.
apply isvalue_tunion.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_tunion; sp.
Qed.
Lemma implies_isvalue_w {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_w a v b).
Proof.
sp.
apply isvalue_w.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_w; sp.
Qed.
Lemma implies_isvalue_m {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_m a v b).
Proof.
sp.
apply isvalue_m.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_m; sp.
Qed.
Lemma implies_isvalue_pw {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprog P
-> isprog_vars [ap] A
-> isprog_vars [bp,ba] B
-> isprog_vars [cp,ca,cb] C
-> isprog p
-> isvalue (mk_pw P ap A bp ba B cp ca cb C p).
Proof.
sp.
apply isvalue_pw.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_pw; sp.
Qed.
Lemma implies_isvalue_pm {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprog P
-> isprog_vars [ap] A
-> isprog_vars [bp,ba] B
-> isprog_vars [cp,ca,cb] C
-> isprog p
-> isvalue (mk_pm P ap A bp ba B cp ca cb C p).
Proof.
sp.
apply isvalue_pm.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_pm; sp.
Qed.
Lemma iscvalue_mkc_function {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_function a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_function; sp.
Qed.
Hint Immediate iscvalue_mkc_function.
Lemma iscvalue_mkc_product {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_product a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_product; sp.
Qed.
Hint Immediate iscvalue_mkc_product.
Lemma iscvalue_mkc_isect {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_isect a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_isect; sp.
Qed.
Hint Immediate iscvalue_mkc_isect.
Lemma iscvalue_mkc_eisect {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_eisect a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_eisect; sp.
Qed.
Hint Immediate iscvalue_mkc_eisect.
Lemma iscvalue_mkc_disect {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_disect a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_disect; sp.
Qed.
Hint Immediate iscvalue_mkc_disect.
Lemma iscvalue_mkc_set {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_set a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_set; sp.
Qed.
Hint Immediate iscvalue_mkc_set.
Lemma iscvalue_mkc_tunion {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_tunion a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_tunion; sp.
Qed.
Hint Immediate iscvalue_mkc_tunion.
Lemma iscvalue_mkc_w {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_w a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_w; sp.
Qed.
Hint Immediate iscvalue_mkc_w.
Lemma iscvalue_mkc_m {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_m a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_m; sp.
Qed.
Hint Immediate iscvalue_mkc_m.
Lemma iscvalue_mkc_pw {p} :
forall (P : @CTerm p) ap A bp ba B cp ca cb C p,
iscvalue (mkc_pw P ap A bp ba B cp ca cb C p).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_pw; sp.
Qed.
Hint Immediate iscvalue_mkc_pw.
Lemma iscvalue_mkc_pm {p} :
forall (P : @CTerm p) ap A bp ba B cp ca cb C p,
iscvalue (mkc_pm P ap A bp ba B cp ca cb C p).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_pm; sp.
Qed.
Hint Immediate iscvalue_mkc_pm.
(* ---------------------------------------------------- *)
Definition list_rel {A} {B} (R : A -> B -> Prop) (ll : list A) (lr : list B) :=
(length ll = length lr)
#
forall p1 p2 , LIn (p1, p2) (combine ll lr)
-> R p1 p2.
Definition default_nterm {o} : @NTerm o := mk_axiom.
Definition default_bt {o} : @BTerm o := bterm [] mk_axiom.
Definition bin_rel_nterm {o} := binrel_list (@default_nterm o).
Definition bin_rel_bterm {o} := binrel_list (@default_bt o).
(** gets the nth element of a list of bterms. if n is out of range, it returns the variable x
*)
Definition selectbt {p} (bts: list BTerm) (n:nat) : @BTerm p :=
nth n bts default_bt.
(* Howe defines T(L) as B_0(L) (no bterm constructor)
and T_0(L) as closed terms of T(L)
so, a term T_0(L) cannot have the vterm constructor
at the root
This a superset of T_0(L)
*)
Inductive not_vbterm {p} : @NTerm p -> Type :=
| nvbo : forall op bs, not_vbterm (oterm op bs)
| nvbs : forall f, not_vbterm (sterm f).
Hint Constructors not_vbterm.
(** this should not be required anymore. a closed NTerm is automatically not_vbterm. Proof below*)
Definition not_vbtermb {p} (t : @NTerm p) : bool :=
match t with
| vterm _ => false
| _ => true
end.
Theorem closed_notvb {p} : forall t: @NTerm p , closed t -> not_vbterm t.
Proof.
intros ? Hclose.
destruct t; allsimpl; auto.
unfold closed in Hclose. simpl in Hclose; ginv.
Qed.
Theorem selectbt_in {p} :
forall n (bts : list (@BTerm p)),
n < length bts -> LIn (selectbt bts n) bts.
Proof.
intros. unfold selectbt.
apply nth_in; auto.
Qed.
Lemma selectbt_cons {p} :
forall (bt : @BTerm p) bts n,
selectbt (bt :: bts) n = if beq_nat n 0 then bt else selectbt bts (n - 1).
Proof.
unfold selectbt; simpl; sp.
destruct n; simpl; sp.
destruct n; simpl; sp.
Qed.
(*
Theorem isprogram_bt_iff : forall (bt:BTerm ) , (isprogram_bt bt) <=>
forall (lnt : list NTerm) ,
(forall nt: NTerm, (LIn nt lnt) -> isprogram nt)
-> isprogram (apply_bterm bt lnt ).
intros. destruct bt as [lv nt].
induction nt as [v| c bts] using NTerm_better_ind;
[ Case_aux Case "vterm"
| Case_aux Case "oterm"
].
remember (memberb eq_var_dec v lv) as vinlv.
destruct vinlv. fold assert () in Heqvinlv.
sp_iff SCase.
SCase "->".
intros Hisp ? Hin.
*)
Lemma isvalue_wf {p} :
forall c (bts : list (@BTerm p)),
isvalue (oterm (Can c) bts)
-> map num_bvars bts = OpBindings (Can c).
Proof. intros ? ? Hval.
inverts Hval as Hpr. inverts Hpr as Hclose Hwf.
inverts Hwf; auto.
Qed.
Lemma isvalue_wf2 {p} : forall c (bts : list (@BTerm p)),
(isvalue (oterm (Can c) bts))
-> length bts= length(OpBindings (Can c)).
Proof. intros ? ? Hval. apply isvalue_wf in Hval.
(* fequalhyp H length. why does this fail*)
assert (length (map num_bvars bts) = length (OpBindings (Can c)))
as Hlen by (rewrite Hval; reflexivity) .
rewrite map_length in Hlen. auto.
Qed.
Lemma isprogram_wf3 {p} : forall o (bts : list (@BTerm p)),
(isprogram (oterm o bts))
-> forall n, (n<length bts) -> (num_bvars (selectbt bts n))= nth n (OpBindings o) 0.
Proof.
intros ? ? Hprog. apply isprogram_ot_iff in Hprog. repnd.
intros ? Hlt.
assert(nth n (map num_bvars bts) 0= nth n (OpBindings o) 0)
as Hnth by (rewrite Hprog0; reflexivity).
unfold selectbt.
instlemma (@map_nth
BTerm nat num_bvars
bts default_bt) as Hmapn.
assert((@num_bvars p default_bt) = 0) as h by sp.
rewrite h in Hmapn.
rewrite Hmapn in Hnth. auto.
Qed.
Lemma isvalue_wf3 {p} : forall o (bts : list (@BTerm p)),
(isvalue (oterm o bts))
-> forall n, (n<length bts) -> (num_bvars (selectbt bts n))= nth n (OpBindings o) 0.
Proof.
intros ? ? Hval ? Hlt.
inverts Hval as Hprog; apply @isprogram_wf3 with (n:=n) in Hprog; auto.
Qed.
Theorem var_not_prog {p} : forall v, @isprogram p (vterm v) -> void.
Proof.
unfold not. intros v Hpr.
inversion Hpr as [Hclose ?].
unfold closed in Hclose. simpl in Hclose. inversion Hclose.
Qed.
Lemma implies_isprogram_bt {p} :
forall bts : list (@BTerm p),
(forall l : BTerm, LIn l bts -> bt_wf l)
-> flat_map free_vars_bterm bts = []
-> forall bt : BTerm, LIn bt bts -> isprogram_bt bt.
Proof.
intros bts Hbf Hflat ? Hin.
unfold isprogram_bt, closed_bt; split; auto.
rw flat_map_empty in Hflat. apply Hflat; auto.
Qed.
Theorem ntbf_wf {p} :
forall nt : @NTerm p, (bt_wf (bterm [] nt)) -> nt_wf nt.
Proof.
introv Hin. inverts Hin. auto.
Qed.
Lemma implies_isprogram_bt0 {p} :
forall t : @NTerm p,
isprogram t
-> isprogram_bt (bterm [] t).
Proof.
unfold isprogram_bt, closed_bt, isprogram, closed; simpl; sp.
Qed.
Theorem is_program_ot_bts0 {p} :
forall o (nt : @NTerm p),
isprogram nt
-> OpBindings o = [0]
-> isprogram (oterm o [bterm [] nt]).
Proof.
introv Hpr Hop. allunfold @isprogram. repnd. split;auto. unfold closed. simpl.
rewrite app_nil_r. rewrite remove_var_nil. sp.
constructor; sp; allsimpl; sp; subst; sp.
Qed.
Theorem is_program_ot_nth_nobnd {p} :
forall o (nt1 : @NTerm p) bts,
isprogram (oterm o bts)
-> LIn (bterm [] nt1) bts
-> isprogram nt1.
Proof. intros ? ? ? Hisp Hin. apply isprogram_ot_iff in Hisp. repnd.
apply Hisp in Hin. inverts Hin as Hclose Hbf. inverts Hbf.
unfold closed_bt in Hclose. simpl in Hclose.
rewrite remove_var_nil in Hclose. split; auto.
Qed.
Theorem is_program_ot_fst_nobnd {p} :
forall o (nt1 : @NTerm p) bts,
isprogram (oterm o ((bterm [] nt1):: bts))
-> isprogram nt1.
Proof.
intros ? ? ? Hisp.
apply @is_program_ot_nth_nobnd with (nt1:=nt1) in Hisp; sp.
Qed.
Theorem is_program_ot_snd_nobnd {p} :
forall o bt1 (nt2 : @NTerm p) bts,
isprogram (oterm o ((bt1)::(bterm [] nt2):: bts))
-> isprogram nt2.
Proof. intros ? ? ? ? Hisp.
apply is_program_ot_nth_nobnd with (nt1:=nt2) in Hisp; simpl; sp.
Qed.
Theorem is_program_ot_subst1 {p} :
forall o (nt1 : @NTerm p) bts nt1r,
isprogram (oterm o ((bterm [] nt1):: bts))
-> isprogram nt1r
-> isprogram (oterm o ((bterm [] nt1r):: bts)).
Proof. intros ? ? ? ? Hisp Hispst. unfold isprogram.
unfold closed. simpl.
inverts Hisp as Hclos Hisp. unfold closed in Hclos. simpl in Hclos.
apply app_eq_nil in Hclos. repnd. rewrite remove_var_nil in Hclos0.
inverts Hispst as Hclosst Hispst. unfold closed in Hclosst.
rewrite remove_var_nil. rewrite Hclosst. rewrite Hclos. split;auto.
invertsn Hisp. constructor;auto.
intros ? Hin. inverts Hin. constructor; auto.
apply Hisp. right; auto.
Qed.
Theorem is_program_ot_subst2 {p} :
forall o bt1 (nt2 : @NTerm p) bts nt2r,
isprogram (oterm o (bt1::(bterm [] nt2):: bts))
-> isprogram nt2r
-> isprogram (oterm o (bt1::(bterm [] nt2r):: bts)).
Proof. intros ? ? ? ? ? Hisp Hispst. unfold isprogram.
unfold closed. simpl.
inverts Hisp as Hclos Hisp. inverts Hispst as Hclosst Hwfst.
allunfold @closed. simpl.
unfold closed in Hclos. allsimpl.
simpl_vlist. rewrite Hclosst. rewrite Hclos0.
simpl. split;auto.
inverts Hisp as Hisp Hm. constructor;simpl; auto.
intros ? Hin. dorn Hin;subst;auto. apply Hisp; auto.
left; auto.
dorn Hin; subst; auto.
apply Hisp. right;right;auto.
Qed.
Theorem is_program_ot_nth_wf {p} :
forall lv o (nt1 : @NTerm p) bts,
isprogram (oterm o bts)
-> LIn (bterm lv nt1) bts
-> nt_wf nt1.
Proof. intros ? ? ? ? Hisp Hin. apply isprogram_ot_iff in Hisp. repnd.
assert (isprogram_bt (bterm lv nt1)) as Hass by (apply Hisp; auto).
inverts Hass as Hass Hbt. inversion Hbt; auto.
Qed.
Lemma combine_vars_map_sp {p} :
forall vars,
combine vars (map vterm vars) = map (fun v => (v, @vterm p v)) vars.
Proof.
induction vars; simpl; sp.
rewrite IHvars; sp.
Qed.
Lemma combine_vars_map :
forall A,
forall f : NVar -> A,
forall vars,
combine vars (map f vars) = map (fun v => (v, f v)) vars.
Proof.
induction vars; simpl; sp.
rewrite IHvars; sp.
Qed.
Theorem in_selectbt {p} :
forall (bt : @BTerm p) bts,
LIn bt bts ->
{n : nat $ n < length bts # selectbt bts n = bt}.
Proof.
intros ? ? Hin. induction bts. inverts Hin.
invertsn Hin.
- exists 0. split; simpl; auto. omega.
- destruct IHbts; auto. exists (S x). repnd.
split; simpl; try omega. auto.
Qed.
(**useful for rewriting in complicated formulae*)
Theorem ntot_wf_iff {p} :
forall o (bts : list (@BTerm p)),
nt_wf (oterm o bts)
<=> map num_bvars bts = OpBindings o
# forall n : nat,
n < length bts -> bt_wf (selectbt bts n).
Proof. introv. sp_iff Case; introv H.
Case "->". inverts H as Hbf Hmap. split; auto.
introv Hlt. apply Hbf. apply selectbt_in; auto.
Case "<-". repnd. constructor; auto.
introv Hin. apply in_selectbt in Hin.
exrepnd. rw <- Hin0;auto.
Qed.
Definition nvarxbt {p} : @BTerm p := bterm [] (vterm nvarx) .
Lemma wf_cvterm {p} :
forall vs : list NVar,
forall t : @CVTerm p vs,
wf_term (get_cvterm vs t).
Proof.
destruct t; simpl.
rw @isprog_vars_eq in i; sp.
rw @wf_term_eq; sp.
Qed.
Lemma isprogram_get_cterm {p} :
forall a : @CTerm p, isprogram (get_cterm a).
Proof.
destruct a; sp; simpl.
rw @isprogram_eq; sp.
Qed.
Hint Immediate isprogram_get_cterm.
Lemma oterm_eq {p} :
forall (o1 o2 : @Opid p) l1 l2,
o1 = o2
-> l1 = l2
-> oterm o1 l1 = oterm o2 l2.
Proof.
sp; allrw; sp.
Qed.
Lemma bterm_eq {p} :
forall l1 l2 (n1 n2 : @NTerm p),
l1 = l2
-> n1 = n2
-> bterm l1 n1 = bterm l2 n2.
Proof.
sp; allrw; sp.
Qed.
Theorem selectbt_map {p} :
forall lbt n (f: @BTerm p -> @BTerm p),
n<length lbt
-> selectbt (map f lbt) n = f (selectbt lbt n).
Proof.
induction lbt; introv Hlt. inverts Hlt.
simpl. destruct n; subst. reflexivity.
allunfold @selectbt. allsimpl.
assert (n < (length lbt)) by omega.
auto.
Qed.
Theorem eq_maps_bt {p} :
forall (B : Type) (f : BTerm -> B)
(g : BTerm -> B) (la lc : list (@BTerm p)),
length la = length lc
-> (forall n : nat, n < length la
-> f (selectbt la n) = g (selectbt lc n))
-> map f la = map g lc.
Proof. unfold selectbt. introv H2 H3. apply eq_maps2 in H3; auto.
Qed.
Lemma vterm_inj {p} : injective_fun (@vterm p).
Proof.
introv Hf. inverts Hf. auto.
Qed.
Lemma map_eq_lift_vterm {p} :
forall lvi lvo,
map (@vterm p) lvi = map vterm lvo -> lvi = lvo.
Proof.
intros.
apply map_eq_injective with (f:=@vterm p); auto.
exact vterm_inj.
Qed.
Fixpoint no_seq {o} (t : @NTerm o) : bool :=
match t with
| vterm _ => true
| sterm f => false
| oterm op bs => no_seq_o op && ball (map no_seq_b bs)
end
with no_seq_b {o} (b : @BTerm o) : bool :=
match b with
| bterm _ t => no_seq t
end.
Lemma lin_lift_vterm {p} :
forall v lv,
LIn v lv <=> LIn (@vterm p v) (map vterm lv).
Proof.
induction lv; [sp | ]. simpl.
rw <- IHlv; split; intros hp; try (dorn hp); sp; subst; sp.
inverts hp. sp.
Qed.
Definition all_vars_bt {p} (bt : @BTerm p) :=
free_vars_bterm bt ++ bound_vars_bterm bt.
Lemma all_vars_ot {p} : forall (o : @Opid p) lbt, all_vars (oterm o lbt) =
flat_map all_vars_bt lbt.
Proof.
intros. unfold all_vars. simpl. unfold all_vars_bt.
Abort. (** they are only equal as bags*)
Theorem nil_remove_nvars_iff :
forall l1 l2 : list NVar,
(remove_nvars l1 l2) = [] <=> (forall x : NVar, LIn x l2 -> LIn x l1).
Proof.
intros. rw <- null_iff_nil. apply null_remove_nvars.
Qed.
Theorem nil_rv_single_iff: forall lv v ,
(remove_nvars lv [v]) = [] <=> (LIn v lv).
Proof.
intros. rw <- null_iff_nil. rw null_remove_nvars.
split; intro Hyp.
apply Hyp. left. auto.
introv Hin. apply in_list1 in Hin; subst; auto.
Qed.
Theorem selectbt_eq_in {p} :
forall lv (nt : @NTerm p) lbt n,
bterm lv nt = selectbt lbt n
-> n < length lbt
-> LIn (bterm lv nt) lbt.
Proof.
introv Heq Hlt. rw Heq.
apply selectbt_in; trivial.
Qed.
Lemma flat_map_closed_terms {p} :
forall lnt : list (@NTerm p), lforall closed lnt
-> flat_map free_vars lnt = [].
Proof.
unfold lforall, closed. introv Hfr.
apply flat_map_empty. trivial.
Qed.
Lemma flat_map_progs {p} :
forall lnt : list (@NTerm p), lforall isprogram lnt
-> flat_map free_vars lnt = [].
Proof.
unfold lforall, closed. introv Hfr.
apply flat_map_empty. introv Hin.
apply Hfr in Hin. inverts Hin. auto.
Qed.
Theorem disjoint_lbt_bt {p} :
forall vs lbt lv (nt : @NTerm p),
disjoint vs (flat_map bound_vars_bterm lbt)
-> LIn (bterm lv nt) lbt
-> disjoint vs lv.
Proof.
introv Hink1 Hin.
apply disjoint_sym in Hink1; rw disjoint_flat_map_l in Hink1.
apply Hink1 in Hin.
simpl in Hin. rw disjoint_app_l in Hin.
repnd; apply disjoint_sym. trivial.
Qed.
Tactic Notation "disjoint_reasoningv" :=
(allunfold all_vars); repeat( progress disjoint_reasoning).
Lemma isprog_vars_top {p} :
forall vs, @isprog_vars p vs mk_top.
Proof.
intro; rw @isprog_vars_eq; simpl.
repeat (rw remove_nvars_nil_l); repeat (rw app_nil_r); sp.
rw @nt_wf_eq; sp.
Qed.
Hint Immediate isprog_vars_top.
Lemma isprog_vars_mk_false {p} :
forall vs, @isprog_vars p vs mk_false.
Proof.
intro; rw @isprog_vars_eq; simpl.
repeat (rw remove_nvars_nil_l); repeat (rw app_nil_r); sp.
rw @nt_wf_eq; sp.
Qed.
Hint Immediate isprog_vars_mk_false.
Definition selectnt {p} (n:nat) (lnt : list NTerm): @NTerm p :=
nth n lnt (vterm nvarx).
Inductive nt_wf2 {p} : @NTerm p -> [univ] :=
| wfvt2 : forall nv : NVar, nt_wf2 (vterm nv)
| wfst2: forall f,
(forall n, nt_wf2 (f n) # closed (f n) # noutokens (f n))
-> nt_wf2 (sterm f)
| wfot2 : forall (o : Opid) (lnt : list BTerm),
length lnt = length (OpBindings o)
-> (forall n, n < (length lnt) ->
num_bvars (selectbt lnt n) = nth n (OpBindings o) 0
# bt_wf2 (selectbt lnt n))
-> nt_wf2 (oterm o lnt)
with bt_wf2 {p} : @BTerm p -> [univ] :=
wfbt2 : forall (lnv : list NVar) (nt : NTerm),
nt_wf2 nt -> bt_wf2 (bterm lnv nt).
Hint Constructors nt_wf2.
(** mainly for convenience in proofs *)
Theorem selectbt_in2 {p} :
forall (n : nat) (bts : list (@BTerm p)),
n < length bts -> { bt : BTerm & (LIn bt bts # (selectbt bts n)=bt) }.
Proof.
intros. exists (selectbt bts n).
split;auto. apply selectbt_in; trivial.
Defined.
Lemma nt_wf_nt_wf2 {p} : forall t : @NTerm p, (nt_wf t) <=> (nt_wf2 t).
Proof.
assert (0= num_bvars (bterm [] (@mk_axiom p))) as XX by auto.
nterm_ind1 t as [|f ind| o lbt Hind] Case; split; introv Hyp; auto.
- Case "sterm".
inversion Hyp as [|? imp|]; subst.
constructor; introv.
pose proof (imp n) as h; repnd; dands; auto.
apply ind; auto.
- Case "sterm".
inversion Hyp as [|? imp|]; subst.
constructor; introv.
pose proof (imp n) as h; repnd; dands; auto.
apply ind; auto.
- Case "oterm".
inverts Hyp as Hl Hyp. constructor. apply_length Hyp;sp.
introv hlt. unfold selectbt. rw <- Hyp.
rw XX.
rw map_nth; sp;[].
fold (selectbt lbt n).
pose proof (selectbt_in2 n lbt hlt) as Hbt.
exrepnd. destruct bt as [lv nt].
applydup Hind in Hbt1.
rw Hbt0. constructor.
apply Hl in Hbt1. inverts Hbt1.
sp3.
- inverts Hyp as Hl Hyp. constructor.
+ introv Hin. apply in_selectbt in Hin; auto;[].
exrepnd. applydup Hyp in Hin1.
rw Hin0 in Hin2. destruct l as [lv nt].
constructor. exrepnd. invertsn Hin2.
applysym @selectbt_in in Hin1. rw Hin0 in Hin1.
apply Hind in Hin1. sp3.
+ eapply (tiff_snd (eq_list2 _ 0 _ _)). rw map_length.
split; auto;[]. introv Hlt. apply Hyp in Hlt.
repnd. rw <- Hlt0.
rw XX. rw map_nth. sp.
Qed.
Lemma isprog_vars_decide {p} :
forall vs (a : @NTerm p) v1 a1 v2 a2,
isprog_vars vs a
-> isprog_vars (v1 :: vs) a1
-> isprog_vars (v2 :: vs) a2
-> isprog_vars vs (mk_decide a v1 a1 v2 a2).
Proof.
introv ipa ipa1 ipa2.
allrw @isprog_vars_eq; allsimpl.
allrw subvars_eq.
unfold subset in ipa, ipa1, ipa2; exrepd; sp.
unfold subset; introv i.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff;
allsimpl; sp;
discover; sp; subst; sp.
repeat (constructor; simpl; sp; subst).
Qed.
Lemma isprog_vars_spread {p} :
forall vs (a : @NTerm p) v1 v2 b,
isprog_vars vs a
-> isprog_vars (v1 :: v2 :: vs) b
-> isprog_vars vs (mk_spread a v1 v2 b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allsimpl.
allrw subvars_prop; repnd.
allrw remove_nvars_nil_l.
allrw app_nil_r.
dands.
introv i.
allrw in_app_iff.
allrw in_remove_nvars; allsimpl.
repdors; sp.
allrw not_over_or; repnd.
discover; sp.
constructor; simpl; try (constructor).
sp; subst; sp; constructor; sp.
Qed.
Lemma isprog_vars_dsup {p} :
forall vs (a : @NTerm p) v1 v2 b,
isprog_vars vs a
-> isprog_vars (v1 :: v2 :: vs) b
-> isprog_vars vs (mk_dsup a v1 v2 b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allsimpl.
allrw subvars_prop; repnd.
allrw remove_nvars_nil_l.
allrw app_nil_r.
dands.
introv i.
allrw in_app_iff.
allrw in_remove_nvars; allsimpl.
repdors; sp.
allrw not_over_or; repnd.
discover; sp.
constructor; simpl; try (constructor).
sp; subst; sp; constructor; sp.
Qed.
Lemma isprog_vars_cons {p} :
forall v vs (t : @NTerm p), isprog_vars vs t -> isprog_vars (v :: vs) t.
Proof.
introv ip.
allrw @isprog_vars_eq.
allrw subvars_eq; sp.
Qed.
Definition mkc_ite_vars {p} (vs : list NVar) (a b c : @CVTerm p vs) :=
let (t1,x1) := a in
let (t2,x2) := b in
let (t3,x3) := c in
exist (isprog_vars vs)
(mk_decide t1 nvarx t2 nvarx t3)
(isprog_vars_decide
vs
t1 nvarx t2 nvarx t3
x1
(isprog_vars_cons nvarx vs t2 x2)
(isprog_vars_cons nvarx vs t3 x3)).
Definition mkc_lamc {p} v (t :@CTerm p) := mkc_lam v (mk_cv [v] t).
Theorem isvalue_inl {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_inl a).
Proof.
intros; constructor; simpl; auto.
fold (mk_inl a).
apply isprogram_inl; auto.
Qed.
Lemma iscvalue_mkc_inl {p} :
forall t : @CTerm p, iscvalue (mkc_inl t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_inl; allrw @isprog_eq; auto.
Qed.
Theorem isvalue_inr {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_inr a).
Proof.
intros; constructor; simpl; auto. fold (mk_inr a).
apply isprogram_inr; auto.
Qed.
Lemma iscvalue_mkc_inr {p} :
forall t : @CTerm p, iscvalue (mkc_inr t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_inr; allrw @isprog_eq; auto.
Qed.
Theorem isvalue_sup {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isvalue (mk_sup a b).
Proof.
intros; constructor; simpl; auto. fold (mk_sup a b).
apply isprogram_sup; auto.
Qed.
Lemma iscvalue_mkc_sup {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_sup t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_sup; allrw @isprog_eq; auto.
Qed.
Definition is_inl {p} (t : @CTerm p) :=
match get_cterm t with
| vterm _ => false
| sterm _ => false
| oterm (Can (NInj NInl)) _ => true
| oterm _ _ => false
end.
Definition is_inr {p} (t : @CTerm p) :=
match get_cterm t with
| vterm _ => false
| sterm _ => false
| oterm (Can (NInj NInr)) _ => true
| oterm _ _ => false
end.
Lemma get_cterm_mkc_void {p} :
get_cterm mkc_void = @mk_void p.
Proof.
unfold mkc_void; simpl; sp.
Qed.
Lemma isvalue_mk_void {p} :
@isvalue p mk_void.
Proof.
apply isvalue_approx; sp.
Qed.
Hint Immediate isvalue_mk_void.
Definition mkc_idv {p} v : @CTerm p := mkc_lam v (mkc_var v).
Definition mkc_botv {p} v : @CTerm p := mkc_fix (mkc_idv v).
Definition mkc_voidv {p} v : @CTerm p := mkc_approx mkc_axiom (mkc_botv v).
Lemma wf_apply_iff {p} :
forall a b : @NTerm p, (wf_term a # wf_term b) <=> wf_term (mk_apply a b).
Proof.
introv; split; intro i.
apply wf_apply; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (nobnd b)); intros k1 k2.
repeat (dest_imp k1 hyp).
repeat (dest_imp k2 hyp).
inversion k1; subst.
inversion k2; subst; sp.
Qed.
Lemma wf_apply2_iff {p} :
forall a b c : @NTerm p,
(wf_term a # wf_term b # wf_term c) <=> wf_term (mk_apply2 a b c).
Proof.
introv.
unfold mk_apply2.
allrw <- @wf_apply_iff; split; sp.
Qed.
Lemma isprog_vars_apply {p} :
forall (f a : @NTerm p) vs,
isprog_vars vs (mk_apply f a) <=> (isprog_vars vs f # isprog_vars vs a).
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw @remove_nvars_nil_l).
rw @app_nil_r.
rw subvars_app_l.
allrw <- @wf_term_eq.
allrw <- @wf_apply_iff; split; sp.
Qed.
Lemma isprog_vars_apply2 {p} :
forall (f a b :@NTerm p) vs,
isprog_vars vs (mk_apply2 f a b)
<=>
(isprog_vars vs f # isprog_vars vs a # isprog_vars vs b).
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw remove_nvars_nil_l).
repeat (rw app_nil_r).
repeat (rw subvars_app_l).
allrw <- @wf_term_eq.
allrw <- @wf_apply2_iff; split; sp.
Qed.
Lemma wf_eapply_iff {p} :
forall a b : @NTerm p, (wf_term a # wf_term b) <=> wf_term (mk_eapply a b).
Proof.
introv; split; intro i.
apply wf_eapply; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (nobnd b)); intros k1 k2.
repeat (dest_imp k1 hyp).
repeat (dest_imp k2 hyp).
inversion k1; subst.
inversion k2; subst; sp.
Qed.
Lemma isprog_vars_eapply {p} :
forall (f a : @NTerm p) vs,
isprog_vars vs (mk_eapply f a) <=> (isprog_vars vs f # isprog_vars vs a).
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw @remove_nvars_nil_l).
rw @app_nil_r.
rw subvars_app_l.
allrw <- @wf_term_eq.
allrw <- @wf_eapply_iff; split; sp.
Qed.
Lemma wf_apseq_iff {p} :
forall f (a : @NTerm p), wf_term a <=> wf_term (mk_apseq f a).
Proof.
introv; split; intro i.
apply wf_apseq; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)); intros k1.
repeat (dest_imp k1 hyp).
inversion k1; subst; sp.
Qed.
Lemma isprog_vars_apseq {p} :
forall f (a : @NTerm p) vs,
isprog_vars vs (mk_apseq f a) <=> isprog_vars vs a.
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw @remove_nvars_nil_l).
rw @app_nil_r.
allrw <- @wf_term_eq.
allrw <- @wf_apseq_iff; split; sp.
Qed.
Lemma wf_parallel_iff {p} :
forall (a b : @NTerm p),
wf_term (mk_parallel a b) <=> (wf_term a # wf_term b).
Proof.
introv; split; intro i; repnd; try (apply wf_parallel; complete sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl; clear i.
pose proof (k (nobnd a)) as h1; autodimp h1 hyp.
pose proof (k (nobnd b)) as h2; autodimp h2 hyp.
allrw @bt_wf_iff; dands; auto.
Qed.
Lemma isprog_vars_parallel {p} :
forall (a b : @NTerm p) vs,
isprog_vars vs (mk_parallel a b)
<=> (isprog_vars vs a # isprog_vars vs b).
Proof.
introv.
allrw @isprog_vars_eq; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l.
allrw @nt_wf_eq.
allrw @wf_parallel_iff.
split; sp.
Qed.
Definition mkc_parallel {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_parallel a b) (isprog_parallel a b x y).
Lemma mkc_parallel_eq {p} :
forall t1 t2 t3 t4 : @CTerm p,
mkc_parallel t1 t2 = mkc_parallel t3 t4 -> t1 = t3 # t2 = t4.
Proof.
introv e; destruct_cterms; allsimpl.
inversion e; subst.
irr; sp.
Qed.
Theorem wf_pertype_iff {p} :
forall a : @NTerm p, wf_term a <=> wf_term (mk_pertype a).
Proof.
intros; split; intro i.
apply wf_pertype; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)); intro j.
repeat (dest_imp j hyp).
inversion j; subst; sp.
Qed.
Lemma isprog_vars_pertype {p} :
forall (f : @NTerm p) vs,
isprog_vars vs (mk_pertype f) <=> isprog_vars vs f.
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
allrw <- @wf_term_eq.
allrw <- @wf_pertype_iff; split; sp.
Qed.
Theorem wf_partial_iff {p} :
forall a : @NTerm p, wf_term a <=> wf_term (mk_partial a).
Proof.
intros; split; intro i.
apply wf_partial; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)); intro j.
repeat (dest_imp j hyp).
inversion j; subst; sp.
Qed.
Lemma isprog_vars_partial {p} :
forall (f : @NTerm p) vs,
isprog_vars vs (mk_partial f) <=> isprog_vars vs f.
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
allrw <- @wf_term_eq.
allrw <- @wf_partial_iff; split; sp.
Qed.
Lemma isprog_vars_weak_l {p} :
forall vs v (t : @NTerm p),
isprog_vars vs t -> isprog_vars (snoc vs v) t.
Proof.
introv i.
allrw @isprog_vars_eq; sp.
apply subvars_snoc_weak; sp.
Qed.
Lemma isprog_vars_weak_r {p} :
forall vs v,
isprog_vars (snoc vs v) (@mk_var p v).
Proof.
introv.
allrw @isprog_vars_eq; sp; allsimpl.
rw subvars_singleton_l; rw in_snoc; sp.
Qed.
Hint Immediate isprog_vars_weak_r.
Lemma subset_snoc_swap_r :
forall T vs vs1 vs2 (v : T),
subset vs (snoc vs1 v ++ vs2)
<=>
subset vs (snoc (vs1 ++ vs2) v).
Proof.
introv; unfold subset; split; intro s; introv i;
apply s in i; allrw in_snoc; allrw in_app_iff; allrw in_snoc; sp.
Qed.
Lemma subvars_snoc_swap_r :
forall vs vs1 vs2 v,
subvars vs (snoc vs1 v ++ vs2)
<=>
subvars vs (snoc (vs1 ++ vs2) v).
Proof.
introv.
allrw subvars_eq.
apply subset_snoc_swap_r; sp.
Qed.
Lemma isprog_vars_snoc_swap {p} :
forall vs1 vs2 v (t : @NTerm p),
isprog_vars (snoc vs1 v ++ vs2) t
<=>
isprog_vars (snoc (vs1 ++ vs2) v) t.
Proof.
introv.
allrw @isprog_vars_eq; split; intro i; repnd; sp.
apply subvars_snoc_swap_r; sp.
apply subvars_snoc_swap_r; sp.
Qed.
Lemma isprog_vars_lam {p} :
forall vs v (b : @NTerm p),
isprog_vars (v :: vs) b
-> isprog_vars vs (mk_lam v b).
Proof.
introv ipv.
allrw @isprog_vars_eq; simpl.
rw app_nil_r.
allrw subvars_prop; sp.
allrw in_remove_nvars; allrw in_single_iff; allsimpl; sp.
apply_in_hyp pp; sp.
constructor; simpl; sp; subst.
constructor; sp.
Qed.
Lemma isprog_vars_isect {p} :
forall vs (a : @NTerm p) v b,
isprog_vars vs a
-> isprog_vars (v :: vs) b
-> isprog_vars vs (mk_isect a v b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allrw subvars_prop; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r; sp.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
discover; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_eisect {p} :
forall vs (a : @NTerm p) v b,
isprog_vars vs a
-> isprog_vars (v :: vs) b
-> isprog_vars vs (mk_eisect a v b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allrw subvars_prop; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r; sp.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
discover; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_base {p} :
forall vs, @isprog_vars p vs mk_base.
Proof.
intros.
rw @isprog_vars_eq; simpl; sp.
constructor; simpl; sp.
Qed.
Hint Immediate isprog_vars_base.
Lemma isprog_vars_free_from_atom {p} :
forall vs (a b T : @NTerm p),
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs T
-> isprog_vars vs (mk_free_from_atom a b T).
Proof.
introv ipa ipb ipt.
allrw @isprog_vars_eq; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_free_from_atoms {p} :
forall vs (a b : @NTerm p),
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs (mk_free_from_atoms a b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_equality {p} :
forall vs (a b T : @NTerm p),
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs T
-> isprog_vars vs (mk_equality a b T).
Proof.
introv ipa ipb ipt.
allrw @isprog_vars_eq; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_tequality {p} :
forall vs (a b : @NTerm p),
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs (mk_tequality a b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_mk_var {p} :
forall vs v, LIn v vs -> isprog_vars vs (@mk_var p v).
Proof.
intros.
rw @isprog_vars_eq; simpl; rw subvars_singleton_l; sp.
Qed.
Lemma isvalue_mk_unit {p} :
@isvalue p mk_unit.
Proof.
apply isvalue_approx; sp; apply isprogram_axiom.
Qed.
Hint Immediate isvalue_mk_unit.
Lemma mkc_void_eq_mkc_false {p} :
@mkc_void p = mkc_false.
Proof.
apply cterm_eq; auto.
Qed.
Lemma iscvalue_mkc_false {p} :
@iscvalue p mkc_false.
Proof.
unfold iscvalue, mkc_false; simpl; sp.
Qed.
Hint Immediate iscvalue_mkc_false.
Lemma isprogram_mk_true {p} :
@isprogram p mk_true.
Proof.
unfold mk_true.
apply isprogram_approx.
apply isprogram_axiom.
apply isprogram_axiom.
Qed.
Hint Immediate isprogram_mk_true.
Lemma isprog_mk_true {p} :
@isprog p mk_true.
Proof.
rw @isprog_eq.
apply isprogram_mk_true.
Qed.
Hint Immediate isprog_mk_true.
Definition mkc_true {p} : @CTerm p := exist isprog mk_true isprog_mk_true.
Lemma iscvalue_mkc_true {p} :
@iscvalue p mkc_true.
Proof.
unfold iscvalue, mkc_true; simpl; sp.
Qed.
Hint Immediate iscvalue_mkc_false.
Definition mkc_top {p} : @CTerm p :=
mkc_isect mkc_false nvarx (mk_cv [nvarx] mkc_false).
Lemma get_cterm_mkc_top {p} :
get_cterm mkc_top = @mk_top p.
Proof. sp. Qed.
Lemma mkc_true_eq {p} :
@mkc_true p = mkc_approx mkc_axiom mkc_axiom.
Proof.
apply cterm_eq; auto.
Qed.
Ltac rwselectbt :=
match goal with
|[ H1: bterm ?lv ?nt = selectbt ?lbt ?n , H2 : context [selectbt ?lbt ?n] |- _ ] => rewrite <- H1 in H2
|[ H1: selectbt ?lbt ?n = bterm ?lv ?nt , H2 : context [selectbt ?lbt ?n] |- _ ] => rewrite H1 in H2
|[ H1: bterm ?lv ?nt = selectbt ?lbt ?n |- context [selectbt ?lbt ?n] ] => rewrite <- H1
|[ H1: selectbt ?lbt ?n = bterm ?lv ?nt |- context [selectbt ?lbt ?n] ] => rewrite H1
end.
Lemma bin_rel_nterm_if_combine {o} :
forall (ts1 ts2 : list (@NTerm o)) R,
(forall t1 t2, LIn (t1,t2) (combine ts1 ts2) -> R t1 t2)
-> length ts1 = length ts2
-> bin_rel_nterm R ts1 ts2.
Proof.
unfold bin_rel_nterm, binrel_list; introv h e; dands; auto.
introv k.
apply h.
rw <- combine_nth; auto.
apply nth_in; auto.
rw combine_length; rw <- e.
rw Min.min_idempotent; auto.
Qed.
Theorem isprogram_ot_implies_eauto2 {p} :
forall (o : @Opid p) bts,
isprogram (oterm o bts)
-> (forall n, n< length bts -> isprogram_bt (selectbt bts n)).
Proof.
introv Hp Hlt. apply isprogram_ot_iff in Hp.
apply selectbt_in in Hlt. exrepnd.
eauto with slow.
Qed.
Lemma isprogram_bt_nobnd {p} :
forall (t : @NTerm p),
isprogram_bt (bterm [] t)
-> isprogram (t).
Proof.
unfold isprogram_bt, closed_bt, isprogram, closed; introns Hxx; spc; allsimpl.
inverts Hxx;sp.
Qed.
Lemma mkc_unit_eq_mkc_true {p} :
@mkc_unit p = mkc_true.
Proof.
apply cterm_eq; auto.
Qed.
Lemma free_vars_list_app {p} :
forall (ts1 ts2 : list (@NTerm p)),
free_vars_list (ts1 ++ ts2)
= free_vars_list ts1 ++ free_vars_list ts2.
Proof.
induction ts1; simpl; sp.
rw IHts1; simpl.
rw app_assoc; sp.
Qed.
Tactic Notation "ntermd" ident(h) "as" simple_intropattern(I) ident(c) :=
destruct h as I;
[ Case_aux c "vterm"
| Case_aux c "sterm"
| Case_aux c "oterm"
].
Ltac prove_or :=
try (left;cpx;fail);
try (right;cpx;fail);
try (left;left;cpx;fail);
try (left;right;cpx;fail);
try (right;left;cpx;fail);
try (right;right;cpx;fail).
Ltac fold_selectbt :=
match goal with
| [ |- context [nth ?n ?lbt (bterm [] mk_axiom)] ] => fold (selectbt lbt n)
| [ |- context [nth ?n ?lbt default_bt] ] => fold (selectbt lbt n)
end.
Hint Resolve nt_wf_implies : slow.
Hint Resolve nt_wf_eq: slow.
Hint Resolve is_program_ot_nth_nobnd : slow.
Lemma isprog_ntwf_eauto {p} : forall t : @NTerm p, isprogram t -> nt_wf t.
Proof. unfold isprogram. spc.
Qed.
Hint Resolve isprog_ntwf_eauto : slow.
Theorem isprogram_ot_if_eauto {p} :
forall (o : @Opid p) bts,
map num_bvars bts = OpBindings o
-> (forall bt, LIn bt bts -> isprogram_bt bt)
-> isprogram (oterm o bts).
Proof.
intros. apply isprogram_ot_iff;spc.
Qed.
Lemma isprogramd {p} :
forall v,
@isprogram p v
-> {f : ntseq & v = sterm f}
[+] {o : Opid $ {lbt : list BTerm $ v = oterm o lbt}}.
Proof.
introv Hpr.
invertsn Hpr.
destruct v; inverts Hpr.
- left; eexists; eauto.
- right; eexists; eexists; eauto.
Qed.
Lemma isprogram_noncan {p} :
forall v,
@isprogram p v
-> (isvalue v [+] isnoncan v [+] isexc v [+] isabs v [+] isseq v).
Proof.
introv Hp.
applydup @isprogramd in Hp.
repndors; exrepnd; subst; cpx.
destruct o; cpx.
Qed.
(*
Ltac d_isnoncan H :=
match type of H with
isnoncan ?t => let tlbt := fresh t "lbt" in let tnc := fresh t "nc" in
let tt := fresh "temp" in
destruct t as [tt|tt tlbt];[inverts H as H; fail|];
destruct tt as [tt|tnc]; [inverts H as H; fail|]
end.
*)
Hint Resolve isprogram_fix : slow.
Lemma fold_combine : forall {A B} (v:A) (t:B),
[(v,t)] = (combine [v] [t]).
Proof.
intros. simpl. auto.
Qed.
Lemma nvarx_nvary : nvarx <> nvary.
Proof.
allunfold nvarx.
allunfold nvary.
introv Hinc.
inverts Hinc.
Qed.
Hint Immediate nvarx_nvary : slow.
Lemma noncan_not_value {p} :
forall e : @NTerm p,
isnoncan e
-> isvalue e
-> False.
Proof.
introv Hisnc Hisv.
destruct e as [|?|o lbt]; allsimpl; cpx.
destruct o; cpx.
inverts Hisv; allsimpl; tcsp.
Qed.
Theorem isprogram_ot_if_eauto2 {p} :
forall (o : @Opid p) bts,
map num_bvars bts = OpBindings o
-> (forall n, n< length bts -> isprogram_bt (selectbt bts n))
-> isprogram (oterm o bts).
Proof.
introv Hn Hp. apply isprogram_ot_iff; dands; spcf.
introv Hin. apply in_selectbt in Hin. exrepnd.
eauto with slow.
rw <- Hin0.
eauto with slow.
Qed.
Hint Resolve isprogram_ot_if_eauto : slow.
Lemma newvars5_prop {p} :
forall v1 v2 v3 v4 v5 (terms : list (@NTerm p)),
(v1, v2, v3, v4, v5) = newvars5 terms
-> !LIn v1 (free_vars_list terms)
# !LIn v2 (free_vars_list terms ++ [v1])
# !LIn v3 (free_vars_list terms ++ [v1, v2])
# !LIn v4 (free_vars_list terms ++ [v1, v2, v3])
# !LIn v5 (free_vars_list terms ++ [v1, v2, v3, v4]).
Proof.
introv eq.
unfold newvars5 in eq; cpx.
unfold newvarlst; simpl; allrw @free_vars_list_app; simpl.
dands; apply fresh_var_not_in.
Qed.
Lemma newvars5_prop2 {p} :
forall v1 v2 v3 v4 v5 (terms : list (@NTerm p)),
(v1, v2, v3, v4, v5) = newvars5 terms
-> !LIn v1 (free_vars_list terms)
# !LIn v2 (free_vars_list terms)
# !LIn v3 (free_vars_list terms)
# !LIn v4 (free_vars_list terms)
# !LIn v5 (free_vars_list terms)
# !v1 = v2
# !v1 = v3
# !v1 = v4
# !v1 = v5
# !v2 = v3
# !v2 = v4
# !v2 = v5
# !v3 = v4
# !v3 = v5
# !v4 = v5.
Proof.
introv eq.
apply newvars5_prop in eq; repnd.
allrw in_app_iff; allsimpl.
repeat (apply not_over_or in eq; repnd).
repeat (apply not_over_or in eq1; repnd).
repeat (apply not_over_or in eq2; repnd).
repeat (apply not_over_or in eq3; repnd).
sp.
Qed.
Lemma newvars2_prop {p} :
forall v1 v2 (terms : list (@NTerm p)),
(v1, v2) = newvars2 terms
-> !LIn v1 (free_vars_list terms)
# !LIn v2 (free_vars_list terms ++ [v1]).
Proof.
introv eq.
unfold newvars2 in eq; cpx.
unfold newvarlst; simpl; allrw @free_vars_list_app; simpl.
dands; apply fresh_var_not_in.
Qed.
Lemma newvars2_prop2 {p} :
forall v1 v2 (terms : list (@NTerm p)),
(v1, v2) = newvars2 terms
-> !LIn v1 (free_vars_list terms)
# !LIn v2 (free_vars_list terms)
# !v1 = v2.
Proof.
introv eq.
apply newvars2_prop in eq; repnd.
allrw in_app_iff; allsimpl.
repeat (apply not_over_or in eq; repnd).
sp.
Qed.
Lemma newvars6_prop {p} :
forall v1 v2 v3 v4 v5 v6 (terms : list (@NTerm p)),
(v1, v2, v3, v4, v5, v6) = newvars6 terms
-> !LIn v1 (free_vars_list terms)
# !LIn v2 (free_vars_list terms ++ [v1])
# !LIn v3 (free_vars_list terms ++ [v1, v2])
# !LIn v4 (free_vars_list terms ++ [v1, v2, v3])
# !LIn v5 (free_vars_list terms ++ [v1, v2, v3, v4])
# !LIn v6 (free_vars_list terms ++ [v1, v2, v3, v4, v5]).
Proof.
introv eq.
unfold newvars6 in eq; cpx.
unfold newvarlst; simpl; allrw @free_vars_list_app; simpl.
dands; try (apply fresh_var_not_in).
Qed.
Lemma newvars6_prop2 {p} :
forall v1 v2 v3 v4 v5 v6 (terms : list (@NTerm p)),
(v1, v2, v3, v4, v5, v6) = newvars6 terms
-> !LIn v1 (free_vars_list terms)
# !LIn v2 (free_vars_list terms)
# !LIn v3 (free_vars_list terms)
# !LIn v4 (free_vars_list terms)
# !LIn v5 (free_vars_list terms)
# !LIn v6 (free_vars_list terms)
# !v1 = v2
# !v1 = v3
# !v1 = v4
# !v1 = v5
# !v1 = v6
# !v2 = v3
# !v2 = v4
# !v2 = v5
# !v2 = v6
# !v3 = v4
# !v3 = v5
# !v3 = v6
# !v4 = v5
# !v4 = v6
# !v5 = v6.
Proof.
introv eq.
apply newvars6_prop in eq; repnd.
allrw in_app_iff; allsimpl.
repeat (apply not_over_or in eq; repnd).
repeat (apply not_over_or in eq1; repnd).
repeat (apply not_over_or in eq2; repnd).
repeat (apply not_over_or in eq3; repnd).
repeat (apply not_over_or in eq4; repnd).
tcsp.
Qed.
Lemma newvarlst_prop {p} :
forall (ts : list (@NTerm p)), ! LIn (newvarlst ts) (free_vars_list ts).
Proof.
unfold newvarlst; sp.
allapply fresh_var_not_in; sp.
Qed.
Lemma newvars7_prop {o} :
forall (terms : list (@NTerm o)),
{v1 : NVar
& {v2 : NVar
& {v3 : NVar
& {v4 : NVar
& {v5 : NVar
& {v6 : NVar
& {v7 : NVar
& (v1,v2,v3,v4,v5,v6,v7) = newvars7 terms
# !LIn v1 (free_vars_list terms)
# !LIn v2 (free_vars_list terms)
# !LIn v3 (free_vars_list terms)
# !LIn v4 (free_vars_list terms)
# !LIn v5 (free_vars_list terms)
# !LIn v6 (free_vars_list terms)
# !LIn v7 (free_vars_list terms)
# !v1 = v2
# !v1 = v3
# !v1 = v4
# !v1 = v5
# !v1 = v6
# !v1 = v7
# !v2 = v3
# !v2 = v4
# !v2 = v5
# !v2 = v6
# !v2 = v7
# !v3 = v4
# !v3 = v5
# !v3 = v6
# !v3 = v7
# !v4 = v5
# !v4 = v6
# !v4 = v7
# !v5 = v6
# !v5 = v7
# !v6 = v7}}}}}}}.
Proof.
introv.
remember (newvars7 terms) as nv; sp.
sp.
unfold newvars7 in Heqnv.
remember (newvars6 terms) as nv'; sp.
apply newvars6_prop2 in Heqnv'; repnd.
ginv.
pose proof (newvarlst_prop
(terms ++
[mk_var nv'4, mk_var nv'3,
mk_var nv'2, mk_var nv'1,
mk_var nv'0, mk_var nv'])) as h.
remember (newvarlst
(terms ++
[mk_var nv'4, mk_var nv'3,
mk_var nv'2, mk_var nv'1,
mk_var nv'0, mk_var nv'])) as n.
clear Heqn.
allrw @free_vars_list_app; allsimpl.
allrw in_app_iff; allsimpl.
allrw not_over_or; repnd; GC.
eexists; eexists; eexists; eexists; eexists; eexists; eexists.
dands; eauto.
Qed.
Lemma mkc_inl_inr_eq {p} :
forall a b : @CTerm p, mkc_inl a = mkc_inr b -> False.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H.
Qed.
Lemma mkc_inr_inl_eq {p} :
forall a b : @CTerm p, mkc_inr a = mkc_inl b -> False.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H.
Qed.
Lemma closed_implies {p} :
forall t : @NTerm p,
closed t -> (forall x, !LIn x (free_vars t)).
Proof.
introv cl i; rw cl in i; sp.
Qed.
Lemma closed_iff {p} :
forall t : @NTerm p,
closed t <=> (forall x, !LIn x (free_vars t)).
Proof.
introv; split; intro k.
- apply closed_implies; auto.
- unfold closed.
apply subvars_nil_r.
rw subvars_prop; introv i.
apply k in i; sp.
Qed.
Lemma isprog_lam_iff {p} :
forall v (b : @NTerm p),
isprog_vars [v] b <=> isprog (mk_lam v b).
Proof.
introv; split; intro k.
apply isprog_lam; sp.
allrw @isprog_eq.
rw @isprog_vars_eq.
unfold isprogram in k; repnd.
inversion k as [|?| o lnt j meq ]; allsimpl; subst.
generalize (j (bterm [v] b)); intro u; dest_imp u hyp.
inversion u; subst; sp.
generalize (closed_implies (mk_lam v b) k0); intro i.
rw subvars_prop; introv y.
allsimpl.
destruct (eq_var_dec v x); sp.
allrw app_nil_r.
generalize (i x); intro pp.
allrw in_remove_nvars; allrw in_single_iff.
provefalse.
apply pp; sp.
Qed.
Lemma isprog_vars_lam_iff {p} :
forall v (b : @NTerm p) vs,
isprog_vars vs (mk_lam v b) <=> isprog_vars (vs ++ [v]) b.
Proof.
introv; split; intro k; allrw @isprog_vars_eq; allrw @nt_wf_eq; repnd; dands;
allrw <- @wf_lam_iff; try (complete sp); allsimpl; allrw app_nil_r; allrw subvars_prop;
introv i.
rw in_app_iff; rw in_single_iff.
destruct (eq_var_dec v x); sp.
generalize (k0 x).
rw in_remove_nvars; rw in_single_iff; intro j.
dest_imp j hyp.
rw in_remove_nvars in i; rw in_single_iff in i; repnd.
generalize (k0 x); intro j; dest_imp j hyp.
rw in_app_iff in j; rw in_single_iff in j; sp.
Qed.
Lemma isprog_vars_isect_iff {p} :
forall vs (a : @NTerm p) v b,
(isprog_vars vs a # isprog_vars (v :: vs) b)
<=> isprog_vars vs (mk_isect a v b).
Proof.
introv; split; intro k.
apply isprog_vars_isect; sp.
allrw @isprog_vars_eq; allrw @nt_wf_eq.
allrw <- @wf_isect_iff; repnd.
allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; sp.
provesv; allrw in_app_iff; allsimpl; sp.
Qed.
Lemma isprog_vars_eisect_iff {p} :
forall vs (a : @NTerm p) v b,
(isprog_vars vs a # isprog_vars (v :: vs) b)
<=> isprog_vars vs (mk_eisect a v b).
Proof.
introv; split; intro k.
apply isprog_vars_eisect; sp.
allrw @isprog_vars_eq; allrw @nt_wf_eq.
allrw <- @wf_eisect_iff; repnd.
allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; sp.
provesv; allrw in_app_iff; allsimpl; sp.
Qed.
Lemma isprog_vars_free_from_atom_iff {p} :
forall vs (a b T : @NTerm p),
(isprog_vars vs a # isprog_vars vs b # isprog_vars vs T)
<=> isprog_vars vs (mk_free_from_atom a b T).
Proof.
introv; split; intro k.
- apply isprog_vars_free_from_atom; sp.
- allrw @isprog_vars_eq; allsimpl; allrw @nt_wf_eq.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw <- @wf_free_from_atom_iff.
allrw subvars_app_l; sp.
Qed.
Lemma isprog_vars_free_from_atoms_iff {p} :
forall vs (a b : @NTerm p),
(isprog_vars vs a # isprog_vars vs b)
<=> isprog_vars vs (mk_free_from_atoms a b).
Proof.
introv; split; intro k.
- apply isprog_vars_free_from_atoms; sp.
- allrw @isprog_vars_eq; allsimpl; allrw @nt_wf_eq.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw <- @wf_free_from_atoms_iff.
allrw subvars_app_l; sp.
Qed.
Lemma isprog_vars_equality_iff {p} :
forall vs (a b T : @NTerm p),
(isprog_vars vs a # isprog_vars vs b # isprog_vars vs T)
<=> isprog_vars vs (mk_equality a b T).
Proof.
introv; split; intro k.
apply isprog_vars_equality; sp.
allrw @isprog_vars_eq; allsimpl; allrw @nt_wf_eq.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw <- @wf_equality_iff.
allrw subvars_app_l; sp.
Qed.
Lemma isprog_vars_tequality_iff {p} :
forall vs (a b : @NTerm p),
(isprog_vars vs a # isprog_vars vs b)
<=> isprog_vars vs (mk_tequality a b).
Proof.
introv; split; intro k.
apply isprog_vars_tequality; sp.
allrw @isprog_vars_eq; allsimpl; allrw @nt_wf_eq.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw <- @wf_tequality_iff.
allrw subvars_app_l; sp.
Qed.
Theorem isprog_pertype_iff {p} :
forall a : @NTerm p, isprog a <=> isprog (mk_pertype a).
Proof.
introv; split; intro k.
apply isprog_pertype; sp.
allrw @isprog_eq; allunfold @isprogram; allrw @nt_wf_eq.
allrw <- @wf_pertype_iff; sp.
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r; sp.
Qed.
Lemma isprog_vars_base_iff {p} :
forall vs, @isprog_vars p vs mk_base <=> True.
Proof.
intros.
rw @isprog_vars_eq; simpl; sp; split; sp.
constructor; simpl; sp.
Qed.
Lemma isprog_vars_app1 {p} :
forall (t : @NTerm p) vs1 vs2,
isprog_vars vs1 t
-> isprog_vars (vs1 ++ vs2) t.
Proof.
sp; alltrewrite @isprog_vars_eq; sp.
alltrewrite subvars_eq.
apply subset_app_r; sp.
Qed.
Lemma isprog_vars_cons_if2 {p} :
forall v vs (t : @NTerm p),
isprog_vars (v :: vs) t
-> !LIn v (free_vars t)
-> isprog_vars vs t.
Proof.
introv ip ni.
allrw @isprog_vars_eq.
allrw subvars_prop; sp.
discover; allsimpl; sp; subst; sp.
Qed.
Lemma isprog_vars_cons_app1 {p} :
forall vs1 vs2 (t : @NTerm p),
isprog_vars (vs1 ++ vs2) t
-> (forall v, LIn v vs2 -> !LIn v (free_vars t))
-> isprog_vars vs1 t.
Proof.
introv ip ni.
allrw @isprog_vars_eq.
allrw subvars_prop; sp.
discover.
allrw in_app_iff; sp.
discover; sp.
Qed.
Ltac unfold_all_mk :=
allunfold mk_apply
;allunfold mk_eapply
;allunfold mk_apseq
;allunfold mk_parallel
;allunfold mk_bottom
;allunfold mk_fix
;allunfold mk_id
;allunfold mk_lam
;allunfold mk_var
;allunfold mk_sup
;allunfold mk_free_from_atom
;allunfold mk_free_from_atoms
;allunfold mk_equality
;allunfold mk_tequality
;allunfold mk_cequiv
;allunfold mk_inl
;allunfold mk_inr
;allunfold mk_pair
;allunfold mk_sup
;allunfold mk_int
;allunfold mk_uni
;allunfold mk_base
;allunfold mk_fun
;allunfold mk_set
;allunfold mk_texc
;allunfold mk_tunion
;allunfold mk_quotient
;allunfold mk_isect
;allunfold mk_disect
;allunfold mk_w
;allunfold mk_m
;allunfold mk_pw
;allunfold mk_pm
;allunfold mk_pertype
;allunfold mk_ipertype
;allunfold mk_spertype
;allunfold mk_tuni
;allunfold mk_partial
;allunfold mk_union
;allunfold mk_union2
;allunfold mk_approx
;allunfold mk_cequiv
;allunfold mk_compute
;allunfold mk_rec
;allunfold mk_image
;allunfold mk_admiss
;allunfold mk_mono
;allunfold nobnd.
Lemma isprogram_inl_iff {p} :
forall a : @NTerm p, isprogram a <=> isprogram (mk_inl a).
Proof.
intros; split; intro i.
apply isprogram_inl; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Lemma isprogram_inr_iff {p} :
forall a : @NTerm p, isprogram a <=> isprogram (mk_inr a).
Proof.
intros; split; intro i.
apply isprogram_inr; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Lemma isprogram_texc_iff {p} :
forall a b : @NTerm p,
(isprogram a # isprogram b) <=> isprogram (mk_texc a b).
Proof.
intros; split; intro i.
apply isprogram_texc; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_union_iff {p} :
forall a b : @NTerm p, (isprogram a # isprogram b) <=> isprogram (mk_union a b).
Proof.
intros; split; intro i.
apply isprogram_union; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_union2_iff {p} :
forall a b : @NTerm p, (isprogram a # isprogram b) <=> isprogram (mk_union2 a b).
Proof.
intros; split; intro i.
apply isprogram_union2; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprog_m_iff {p} :
forall (a : @NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_m a v b).
Proof.
introv; split; intro k; try (apply isprog_m; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma isprogram_pair_iff {p} :
forall a b : @NTerm p, (isprogram a # isprogram b) <=> isprogram (mk_pair a b).
Proof.
intros; split; intro i.
apply isprogram_pair; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Definition mkc_admiss {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_admiss a) (isprog_admiss a x).
Theorem isvalue_admiss {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_admiss a).
Proof.
intros; constructor; simpl; auto; apply isprogram_admiss; auto.
Qed.
Lemma iscvalue_mkc_admiss {p} :
forall t : @CTerm p, iscvalue (mkc_admiss t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_admiss; allrw @isprog_eq; auto.
Qed.
Definition mkc_mono {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_mono a) (isprog_mono a x).
Theorem isvalue_mono {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_mono a).
Proof.
intros; constructor; simpl; auto; apply isprogram_mono; auto.
Qed.
Lemma iscvalue_mkc_mono {p} :
forall t : @CTerm p, iscvalue (mkc_mono t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_mono; allrw @isprog_eq; auto.
Qed.
Lemma wf_cequiv_iff {p} :
forall a b : @NTerm p, (wf_term a # wf_term b) <=> wf_term (mk_cequiv a b).
Proof.
sp; split; intros k.
apply wf_cequiv; sp.
allrw @wf_term_eq.
inversion k as [|?| o lnt i meq ]; subst; allsimpl.
generalize (i (nobnd a)); generalize (i (nobnd b)); intros i1 i2.
dest_imp i1 hyp.
dest_imp i2 hyp.
inversion i1; inversion i2; sp.
Qed.
Definition mkc_or {p} (A B : @CTerm p) := mkc_union A B.
Definition mkc_not {p} (P : @CTerm p) := mkc_fun P mkc_void.
Lemma wf_fun {p} :
forall A B : @NTerm p, wf_term (mk_fun A B) <=> (wf_term A # wf_term B).
Proof.
introv.
split; intro w.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e ]; subst.
generalize (bw (nobnd A)) (bw (bterm [newvar B] B)); intros bw1 bw2; clear bw.
dest_imp bw1 hyp.
dest_imp bw2 hyp.
inversion bw1; subst.
inversion bw2; subst.
allrw @nt_wf_eq; sp.
rw <- @nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_ufun {p} :
forall A B : @NTerm p, wf_term (mk_ufun A B) <=> (wf_term A # wf_term B).
Proof.
introv.
split; intro w.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e ]; subst.
generalize (bw (nobnd A)) (bw (bterm [newvar B] B)); intros bw1 bw2; clear bw.
dest_imp bw1 hyp.
dest_imp bw2 hyp.
inversion bw1; subst.
inversion bw2; subst.
allrw @nt_wf_eq; sp.
rw <- @nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_eufun {p} :
forall A B : @NTerm p, wf_term (mk_eufun A B) <=> (wf_term A # wf_term B).
Proof.
introv.
split; intro w.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e ]; subst.
generalize (bw (nobnd A)) (bw (bterm [newvar B] B)); intros bw1 bw2; clear bw.
dest_imp bw1 hyp.
dest_imp bw2 hyp.
inversion bw1; subst.
inversion bw2; subst.
allrw @nt_wf_eq; sp.
rw <- @nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_prod {p} :
forall A B : @NTerm p, wf_term (mk_prod A B) <=> (wf_term A # wf_term B).
Proof.
introv.
split; intro w.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e ]; subst.
generalize (bw (nobnd A)) (bw (bterm [newvar B] B)); intros bw1 bw2; clear bw.
dest_imp bw1 hyp.
dest_imp bw2 hyp.
inversion bw1; subst.
inversion bw2; subst.
allrw @nt_wf_eq; sp.
rw <- @nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_not {p} :
forall A : @NTerm p, wf_term (mk_not A) <=> wf_term A.
Proof.
introv.
rw @wf_fun; split; sp.
Qed.
Lemma wf_subtype_rel {p} :
forall a b : @NTerm p,
wf_term a
-> wf_term b
-> wf_term (mk_subtype_rel a b).
Proof.
sp; unfold mk_subtype_rel.
apply wf_member; sp.
apply wf_fun; sp.
Qed.
Lemma wf_fun_iff {p} :
forall (a b : @NTerm p),
wf_term (mk_fun a b) <=> (wf_term a # wf_term b).
Proof.
introv.
unfold mk_fun.
rw <- @wf_function_iff; sp.
Qed.
Lemma wf_subtype_rel_iff {p} :
forall a b : @NTerm p,
wf_term (mk_subtype_rel a b) <=> (wf_term a # wf_term b).
Proof.
sp; split; intro.
- unfold mk_subtype_rel in H.
allrw <- @wf_member_iff; repd.
allrw @wf_fun_iff; sp.
- apply wf_subtype_rel; sp.
Qed.
Lemma isprog_subtype_rel {p} :
forall a b : @NTerm p,
isprog a
-> isprog b
-> isprog (mk_subtype_rel a b).
Proof.
unfold mk_subtype_rel; introv ispa ispb.
apply isprog_member; auto.
apply isprog_fun; auto.
Qed.
Definition mkc_subtype_rel {p} (T1 T2 : @CTerm p) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_subtype_rel a b) (isprog_subtype_rel a b x y).
Ltac destruct_bterms :=
repeat match goal with
[bt : BTerm |- _] =>
let btlv := fresh bt "lv" in
let btnt := fresh bt "nt" in
destruct bt as [btlv btnt]
end.
Lemma mkc_admiss_eq {p} :
forall T1 T2 : @CTerm p, mkc_admiss T1 = mkc_admiss T2 -> T1 = T2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_mono_eq {p} :
forall T1 T2 : @CTerm p, mkc_mono T1 = mkc_mono T2 -> T1 = T2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Lemma wf_less {p} :
forall a b c d : @NTerm p,
wf_term a
-> wf_term b
-> wf_term c
-> wf_term d
-> wf_term (mk_less a b c d).
Proof.
introv; repeat (rw <- @nt_wf_eq).
intros nta ntb ntc ntd; inversion nta; inversion ntb; inversion ntc; inversion ntd; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_less_iff {p} :
forall a b c d : @NTerm p,
(wf_term a # wf_term b # wf_term c # wf_term d) <=> wf_term (mk_less a b c d).
Proof.
introv; split; intro i.
apply wf_less; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)) (k (nobnd d)); intros k1 k2 k3 k4.
repeat (dest_imp k1 hyp).
repeat (dest_imp k2 hyp).
repeat (dest_imp k3 hyp).
repeat (dest_imp k4 hyp).
inversion k1; subst.
inversion k2; subst.
inversion k3; subst.
inversion k4; subst; sp.
Qed.
Lemma isprog_vars_less {p} :
forall (a b c d : @NTerm p) vs,
isprog_vars vs (mk_less a b c d)
<=> (isprog_vars vs a
# isprog_vars vs b
# isprog_vars vs c
# isprog_vars vs d).
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw remove_nvars_nil_l).
repeat (rw app_nil_r).
repeat (rw subvars_app_l).
repeat (rw <- @wf_term_eq).
allrw <- @wf_less_iff; split; sp.
Qed.
Lemma isprog_vars_function {p} :
forall vs (a : @NTerm p) v b,
isprog_vars vs a
-> isprog_vars (v :: vs) b
-> isprog_vars vs (mk_function a v b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allrw subvars_prop; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r; sp.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
discover; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_function_iff {p} :
forall vs (a : @NTerm p) v b,
(isprog_vars vs a # isprog_vars (v :: vs) b)
<=> isprog_vars vs (mk_function a v b).
Proof.
introv; split; intro k.
apply isprog_vars_function; sp.
allrw @isprog_vars_eq; allrw @nt_wf_eq.
allrw <- @wf_function_iff; repnd.
allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; sp.
provesv; allrw in_app_iff; allsimpl; sp.
Qed.
Lemma isprog_vars_cons_newvar {p} :
forall (b : @NTerm p) vs,
isprog_vars (newvar b :: vs) b <=> isprog_vars vs b.
Proof.
introv; split; intro k.
allrw @isprog_vars_eq.
allrw subvars_prop; repnd; dands; auto.
introv i.
applydup k0 in i; simpl in i0; repdors; subst; auto.
apply newvar_prop in i; sp.
apply isprog_vars_cons; sp.
Qed.
Lemma isprog_vars_fun {p} :
forall vs (a b : @NTerm p),
(isprog_vars vs a # isprog_vars vs b)
<=> isprog_vars vs (mk_fun a b).
Proof.
introv.
rw <- @isprog_vars_function_iff.
rw @isprog_vars_cons_newvar; sp.
Qed.
Lemma isprog_vars_ufun {p} :
forall vs (a b : @NTerm p),
(isprog_vars vs a # isprog_vars vs b)
<=> isprog_vars vs (mk_ufun a b).
Proof.
introv.
rw <- @isprog_vars_isect_iff.
rw @isprog_vars_cons_newvar; sp.
Qed.
Lemma isprog_vars_eufun {p} :
forall vs (a b : @NTerm p),
(isprog_vars vs a # isprog_vars vs b)
<=> isprog_vars vs (mk_eufun a b).
Proof.
introv.
rw <- @isprog_vars_eisect_iff.
rw @isprog_vars_cons_newvar; sp.
Qed.
Lemma isprog_vars_product {p} :
forall vs (a : @NTerm p) v b,
isprog_vars vs a
-> isprog_vars (v :: vs) b
-> isprog_vars vs (mk_product a v b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allrw subvars_prop; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r; sp.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
discover; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Theorem wf_product_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_product a v b).
Proof.
sp; split; intro i; try (apply wf_product; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; try (complete sp).
dest_imp i2 hyp; try (complete sp).
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprog_vars_product_iff {p} :
forall vs (a : @NTerm p) v b,
(isprog_vars vs a # isprog_vars (v :: vs) b)
<=> isprog_vars vs (mk_product a v b).
Proof.
introv; split; intro k.
apply isprog_vars_product; sp.
allrw @isprog_vars_eq; allrw @nt_wf_eq.
allrw <- @wf_product_iff; repnd.
allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; sp.
provesv; allrw in_app_iff; allsimpl; sp.
Qed.
Lemma isprog_vars_prod {p} :
forall vs (a b : @NTerm p),
(isprog_vars vs a # isprog_vars vs b)
<=> isprog_vars vs (mk_prod a b).
Proof.
introv.
rw <- @isprog_vars_product_iff.
rw @isprog_vars_cons_newvar; sp.
Qed.
Lemma isprog_vars_set {p} :
forall vs (a : @NTerm p) v b,
isprog_vars vs a
-> isprog_vars (v :: vs) b
-> isprog_vars vs (mk_set a v b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allrw subvars_prop; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r; sp.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
discover; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_set_iff {p} :
forall vs (a : @NTerm p) v b,
(isprog_vars vs a # isprog_vars (v :: vs) b)
<=> isprog_vars vs (mk_set a v b).
Proof.
introv; split; intro k.
apply isprog_vars_set; sp.
allrw @isprog_vars_eq; allrw @nt_wf_eq.
allrw <- @wf_set_iff; repnd.
allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; sp.
provesv; allrw in_app_iff; allsimpl; sp.
Qed.
Lemma isprog_vars_tunion {p} :
forall vs (a : @NTerm p) v b,
isprog_vars vs a
-> isprog_vars (v :: vs) b
-> isprog_vars vs (mk_tunion a v b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allrw subvars_prop; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r; sp.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
discover; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_tunion_iff {p} :
forall vs (a : @NTerm p) v b,
(isprog_vars vs a # isprog_vars (v :: vs) b)
<=> isprog_vars vs (mk_tunion a v b).
Proof.
introv; split; intro k.
apply isprog_vars_tunion; sp.
allrw @isprog_vars_eq; allrw @nt_wf_eq.
allrw <- @wf_tunion_iff; repnd.
allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; sp.
provesv; allrw in_app_iff; allsimpl; sp.
Qed.
Lemma isprog_vars_void_iff {p} :
forall vs, @isprog_vars p vs mk_void <=> True.
Proof.
introv; split; intro k; auto.
Qed.
Lemma isprog_vars_true_iff {p} :
forall vs, @isprog_vars p vs mk_true <=> True.
Proof.
introv; split; intro k; auto.
rw @isprog_vars_eq; sp.
constructor; sp.
allsimpl; sp; subst; repeat constructor; simpl; sp.
Qed.
Lemma isprog_vars_false_iff {p} :
forall vs, @isprog_vars p vs mk_false <=> True.
Proof.
introv; split; intro k; auto.
Qed.
Lemma isprog_vars_le {p} :
forall (a b : @NTerm p) vs,
isprog_vars vs (mk_le a b) <=> (isprog_vars vs a # isprog_vars vs b).
Proof.
introv; unfold mk_le.
rw <- @isprog_vars_fun.
rw @isprog_vars_void_iff.
rw @isprog_vars_less.
rw @isprog_vars_false_iff.
rw @isprog_vars_true_iff.
split; sp.
Qed.
Lemma isprog_vars_zero {p} :
forall vs,
@isprog_vars p vs mk_zero.
Proof.
introv.
apply isprog_vars_eq; simpl; dands; tcsp.
constructor; simpl; tcsp.
Qed.
Hint Resolve isprog_vars_zero : slow.
Lemma isprog_tnat {p} : @isprog p mk_tnat.
Proof.
rw <- @isprog_set_iff.
dands; auto.
rw @isprog_vars_le; dands; eauto 3 with slow.
apply isprog_vars_var.
Qed.
Definition mkc_tnat {p} : @CTerm p := exist isprog mk_tnat isprog_tnat.
Lemma free_vars_fun {p} :
forall a b : @NTerm p, free_vars (mk_fun a b) = free_vars a ++ free_vars b.
Proof.
introv; simpl.
rw remove_nvars_nil_l.
rw app_nil_r.
assert (disjoint (free_vars b) [newvar b]) as disj.
apply disjoint_sym.
rw disjoint_singleton_l.
apply newvar_prop.
rw remove_nvars_unchanged in disj.
rw disj; auto.
Qed.
Lemma free_vars_ufun {p} :
forall a b : @NTerm p, free_vars (mk_ufun a b) = free_vars a ++ free_vars b.
Proof.
introv; simpl.
rw remove_nvars_nil_l.
rw app_nil_r.
assert (disjoint (free_vars b) [newvar b]) as disj.
apply disjoint_sym.
rw disjoint_singleton_l.
apply newvar_prop.
rw remove_nvars_unchanged in disj.
rw disj; auto.
Qed.
Lemma free_vars_eufun {p} :
forall a b : @NTerm p, free_vars (mk_eufun a b) = free_vars a ++ free_vars b.
Proof.
introv; simpl.
rw remove_nvars_nil_l.
rw app_nil_r.
assert (disjoint (free_vars b) [newvar b]) as disj.
apply disjoint_sym.
rw disjoint_singleton_l.
apply newvar_prop.
rw remove_nvars_unchanged in disj.
rw disj; auto.
Qed.
Lemma isprogram_mk_zero {p} :
@isprogram p mk_zero.
Proof.
repeat constructor; simpl; sp.
Qed.
Hint Immediate isprogram_mk_zero.
Lemma isprogram_mk_one {p} :
@isprogram p mk_one.
Proof.
repeat constructor; simpl; sp.
Qed.
Hint Immediate isprogram_mk_one.
Lemma isprog_mk_zero {p} :
@isprog p mk_zero.
Proof.
rw @isprog_eq.
apply isprogram_mk_zero.
Qed.
Hint Immediate isprog_mk_zero.
Definition mkc_zero {p} : @CTerm p := exist isprog mk_zero isprog_mk_zero.
Definition mk_eta_pair {p} (t : @NTerm p) := mk_pair (mk_pi1 t) (mk_pi2 t).
Definition mk_eta_inl {p} (t : @NTerm p) := mk_inl (mk_outl t).
Definition mk_eta_inr {p} (t : @NTerm p) := mk_inr (mk_outr t).
Lemma free_vars_mk_pertype {p} :
forall A : @NTerm p,
free_vars (mk_pertype A) = free_vars A.
Proof.
introv.
simpl.
rw remove_nvars_nil_l.
rw app_nil_r; auto.
Qed.
Lemma free_vars_mk_ipertype {p} :
forall A : @NTerm p,
free_vars (mk_ipertype A) = free_vars A.
Proof.
introv.
simpl.
rw remove_nvars_nil_l.
rw app_nil_r; auto.
Qed.
Lemma free_vars_mk_spertype {p} :
forall A : @NTerm p,
free_vars (mk_spertype A) = free_vars A.
Proof.
introv.
simpl.
rw remove_nvars_nil_l.
rw app_nil_r; auto.
Qed.
Lemma free_vars_mk_tuni {p} :
forall A : @NTerm p,
free_vars (mk_tuni A) = free_vars A.
Proof.
introv.
simpl.
rw remove_nvars_nil_l.
rw app_nil_r; auto.
Qed.
Lemma wf_isaxiom {p} :
forall a b c : @NTerm p,
wf_term (mk_isaxiom a b c) <=> (wf_term a # wf_term b # wf_term c).
Proof.
sp; split; intro k.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term; try (exact k); simpl; sp.
- repnd.
unfold wf_term; simpl.
rw k0; rw k1; rw k; auto.
Qed.
Lemma nt_wf_isaxiom {p} :
forall a b c : @NTerm p,
nt_wf (mk_isaxiom a b c) <=> (nt_wf a # nt_wf b # nt_wf c).
Proof.
introv.
allrw @nt_wf_eq.
apply wf_isaxiom.
Qed.
Lemma isprog_vars_isaxiom {p} :
forall vs (a b c : @NTerm p),
isprog_vars vs (mk_isaxiom a b c)
<=>
(isprog_vars vs a
# isprog_vars vs b
# isprog_vars vs c).
Proof.
introv; split; intro k; repnd; allrw @isprog_vars_eq; allsimpl;
allrw remove_nvars_nil_l; allrw app_nil_r;
allrw subvars_app_l; allrw @nt_wf_isaxiom; sp.
Qed.
Lemma isprog_vars_halts {p} :
forall vs (a : @NTerm p), isprog_vars vs (mk_halts a) <=> isprog_vars vs a.
Proof.
introv.
allrw @isprog_vars_eq; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw @nt_wf_eq.
allrw <- @wf_halts_iff; sp.
Qed.
Lemma isprog_ipertype_iff {p} :
forall a : @NTerm p, isprog a <=> isprog (mk_ipertype a).
Proof.
introv; split; intro k.
apply isprog_ipertype; sp.
allrw @isprog_eq; allunfold @isprogram; allrw @nt_wf_eq.
allrw <- @wf_ipertype_iff; sp.
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r; sp.
Qed.
Lemma isprog_spertype_iff {p} :
forall a : @NTerm p, isprog a <=> isprog (mk_spertype a).
Proof.
introv; split; intro k.
apply isprog_spertype; sp.
allrw @isprog_eq; allunfold @isprogram; allrw @nt_wf_eq.
allrw <- @wf_spertype_iff; sp.
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r; sp.
Qed.
Lemma isprog_tuni_iff {p} :
forall a : @NTerm p, isprog a <=> isprog (mk_tuni a).
Proof.
introv; split; intro k.
apply isprog_tuni; sp.
allrw @isprog_eq; allunfold @isprogram; allrw @nt_wf_eq.
allrw <- @wf_tuni_iff; sp.
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r; sp.
Qed.
Lemma wf_pair {p} :
forall a b : @NTerm p, wf_term (mk_pair a b) <=> (wf_term a # wf_term b).
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e]; subst.
generalize (bw (nobnd a)) (bw (nobnd b)); simpl; intros bw1 bw2.
autodimp bw1 hyp.
autodimp bw2 hyp.
inversion bw1; subst.
inversion bw2; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_spread {p} :
forall (a : @NTerm p) v1 v2 b,
wf_term (mk_spread a v1 v2 b) <=> (wf_term a # wf_term b).
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bwf e ]; subst.
generalize (bwf (nobnd a)) (bwf (bterm [v1,v2] b)); clear bwf; intros bwf1 bwf2.
autodimp bwf1 hyp; autodimp bwf2 hyp; try (complete (simpl; sp)).
inversion bwf1; subst.
inversion bwf2; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; sp.
allsimpl; sp; subst; constructor; allrw @nt_wf_eq; sp.
Qed.
Lemma wf_ispair {p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_ispair a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_ispair_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_ispair a b T).
Proof.
sp; split; introv k.
- apply wf_ispair; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term; try (exact k); simpl; sp.
Qed.
Lemma wf_isinl {p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_isinl a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_isinl_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_isinl a b T).
Proof.
introv; split; intro k.
- apply wf_isinl; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term; try (exact k); simpl; sp.
Qed.
Lemma wf_isinr {p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_isinr a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_isinr_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_isinr a b T).
Proof.
introv; split; intro k.
- apply wf_isinl; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term; try (exact k); simpl; sp.
Qed.
Lemma wf_islambda {p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_islambda a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_islambda_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_isinr a b T).
Proof.
introv; split; intro k.
- apply wf_islambda; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term; try (exact k); simpl; sp.
Qed.
Lemma wf_isaxiom_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_isinr a b T).
Proof.
introv; split; intro k.
- apply wf_isaxiom; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term; try (exact k); simpl; sp.
Qed.
Lemma wf_isint{p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_isint a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_isint_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_isint a b T).
Proof.
introv; split; intro k.
- apply wf_isint; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term; try (exact k); simpl; sp.
Qed.
Lemma isprog_pi1 {p} :
forall t : @NTerm p, isprog t -> isprog (mk_pi1 t).
Proof.
introv ip.
apply isprog_spread; sp.
apply isprog_vars_var_iff; simpl; sp.
Qed.
Lemma isprog_pi2 {p} :
forall t : @NTerm p, isprog t -> isprog (mk_pi2 t).
Proof.
introv ip.
apply isprog_spread; sp.
apply isprog_vars_var_iff; simpl; sp.
Qed.
Lemma isprog_eta_pair {p} :
forall t : @NTerm p, isprog t -> isprog (mk_eta_pair t).
Proof.
introv ip.
unfold mk_eta_pair.
apply isprog_pair.
apply isprog_pi1; auto.
apply isprog_pi2; auto.
Qed.
Definition mkc_eta_pair {p} (t : @CTerm p) :=
let (a,p) := t in exist isprog (mk_eta_pair a) (isprog_eta_pair a p).
Lemma isprog_outl {p} :
forall t : @NTerm p, isprog t -> isprog (mk_outl t).
Proof.
introv ip.
apply isprog_decide; tcsp.
- apply isprog_vars_mk_var; tcsp.
- unfold isprog_vars; simpl; dands; tcsp.
Qed.
Lemma isprog_outr {p} :
forall t : @NTerm p, isprog t -> isprog (mk_outr t).
Proof.
introv ip.
apply isprog_decide; sp.
- unfold isprog_vars; simpl; dands; tcsp.
- apply isprog_vars_mk_var; tcsp.
Qed.
Lemma isprog_eta_inl {p} :
forall t : @NTerm p, isprog t -> isprog (mk_eta_inl t).
Proof.
introv ip.
unfold mk_eta_inl.
apply isprog_inl.
apply isprog_outl; auto.
Qed.
Lemma isprog_eta_inr {p} :
forall t : @NTerm p, isprog t -> isprog (mk_eta_inr t).
Proof.
introv ip.
unfold mk_eta_inr.
apply isprog_inr.
apply isprog_outl; auto.
Qed.
Definition mkc_eta_inl {p} (t : @CTerm p) :=
let (a,p) := t in exist isprog (mk_eta_inl a) (isprog_eta_inl a p).
Definition mkc_eta_inr {p} (t : @CTerm p) :=
let (a,p) := t in exist isprog (mk_eta_inr a) (isprog_eta_inr a p).
Lemma fold_pi1 {p} :
forall t : @NTerm p, mk_spread t nvarx nvary (mk_var nvarx) = mk_pi1 t.
Proof. sp. Qed.
Lemma fold_pi2 {p} :
forall t : @NTerm p, mk_spread t nvarx nvary (mk_var nvary) = mk_pi2 t.
Proof. sp. Qed.
Lemma fold_eta_pair {p} :
forall t : @NTerm p, mk_pair (mk_pi1 t) (mk_pi2 t) = mk_eta_pair t.
Proof. sp. Qed.
Lemma wf_pi1 {p} :
forall t : @NTerm p, wf_term (mk_pi1 t) <=> wf_term t.
Proof.
introv.
rw @wf_spread; split; sp.
Qed.
Lemma wf_pi2 {p} :
forall t : @NTerm p, wf_term (mk_pi2 t) <=> wf_term t.
Proof.
introv.
rw @wf_spread; split; sp.
Qed.
Lemma wf_eta_pair {p} :
forall t : @NTerm p, wf_term (mk_eta_pair t) <=> wf_term t.
Proof.
introv.
unfold mk_eta_pair.
rw @wf_pair.
rw @wf_pi1.
rw @wf_pi2.
split; sp.
Qed.
Lemma isprogram_spread_iff {p} :
forall (a : @NTerm p) v1 v2 b,
(isprogram a
# subvars (free_vars b) [v1,v2]
# nt_wf b)
<=> isprogram (mk_spread a v1 v2 b).
Proof.
introv; split; intro isp; repnd.
apply isprogram_spread; auto.
inversion isp as [cl wf].
inversion wf as [|?| o l bwf e ]; subst.
generalize (bwf (nobnd a)) (bwf (bterm [v1,v2] b)); clear bwf; intros bwf1 bwf2.
autodimp bwf1 hyp; autodimp bwf2 hyp; try (complete (simpl; sp)).
inversion bwf1; subst.
inversion bwf2; subst.
unfold closed in cl; simpl in cl; rw remove_nvars_nil_l in cl; rw app_nil_r in cl.
apply app_eq_nil in cl; repnd.
allfold (closed a).
dands; auto.
constructor; sp.
rw subvars_prop; introv i.
rw nil_remove_nvars_iff in cl.
apply cl in i; sp.
Qed.
Lemma isprogram_spread_iff2 {p} :
forall (a : @NTerm p) v1 v2 b,
isprogram (mk_spread a v1 v2 b)
<=> isprogram a # isprogram_bt (bterm [v1, v2] b).
Proof.
introv.
rw <- @isprogram_spread_iff.
unfold isprogram_bt; simpl.
unfold closed_bt; simpl.
rw <- null_iff_nil.
rw null_remove_nvars.
rw subvars_prop.
split; intro k; repnd; dands; auto.
inversion k; sp.
Qed.
Lemma isprogram_dsup_iff {p} :
forall (a : @NTerm p) v1 v2 b,
(isprogram a
# subvars (free_vars b) [v1,v2]
# nt_wf b)
<=> isprogram (mk_dsup a v1 v2 b).
Proof.
introv; split; intro isp; repnd.
apply isprogram_dsup; auto.
inversion isp as [cl wf].
inversion wf as [|?| o l bwf e ]; subst.
generalize (bwf (nobnd a)) (bwf (bterm [v1,v2] b)); clear bwf; intros bwf1 bwf2.
autodimp bwf1 hyp; autodimp bwf2 hyp; try (complete (simpl; sp)).
inversion bwf1; subst.
inversion bwf2; subst.
unfold closed in cl; simpl in cl; rw remove_nvars_nil_l in cl; rw app_nil_r in cl.
apply app_eq_nil in cl; repnd.
allfold (closed a).
dands; auto.
constructor; sp.
rw subvars_prop; introv i.
rw nil_remove_nvars_iff in cl.
apply cl in i; sp.
Qed.
Lemma isprogram_dsup_iff2 {p} :
forall (a : @NTerm p) v1 v2 b,
isprogram (mk_dsup a v1 v2 b)
<=> isprogram a # isprogram_bt (bterm [v1, v2] b).
Proof.
introv.
rw <- @isprogram_dsup_iff.
unfold isprogram_bt; simpl.
unfold closed_bt; simpl.
rw <- null_iff_nil.
rw null_remove_nvars.
rw subvars_prop.
split; intro k; repnd; dands; auto.
inversion k; sp.
Qed.
Lemma isprogram_decide_iff {p} :
forall (a : @NTerm p) v1 b1 v2 b2,
(isprogram a
# subvars (free_vars b1) [v1]
# subvars (free_vars b2) [v2]
# nt_wf b1
# nt_wf b2)
<=> isprogram (mk_decide a v1 b1 v2 b2).
Proof.
introv; split; intro isp; repnd.
apply isprogram_decide; auto.
inversion isp as [cl wf].
inversion wf as [|?| o l bwf e ]; subst.
generalize (bwf (nobnd a)) (bwf (bterm [v1] b1)) (bwf (bterm [v2] b2)); clear bwf; intros bwf1 bwf2 bwf3.
autodimp bwf1 hyp; autodimp bwf2 hyp; autodimp bwf3 hyp; try (complete (simpl; sp)).
inversion bwf1; subst.
inversion bwf2; subst.
inversion bwf3; subst.
unfold closed in cl; simpl in cl; rw remove_nvars_nil_l in cl; rw app_nil_r in cl.
apply app_eq_nil in cl; repnd.
allfold (closed a).
apply app_eq_nil_iff in cl; repnd.
rw nil_remove_nvars_iff in cl1.
rw nil_remove_nvars_iff in cl.
dands; auto.
constructor; sp.
rw subvars_prop; sp.
rw subvars_prop; sp.
Qed.
Lemma isprogram_decide_iff2 {p} :
forall (a : @NTerm p) v1 b1 v2 b2,
isprogram (mk_decide a v1 b1 v2 b2)
<=> isprogram a # isprogram_bt (bterm [v1] b1) # isprogram_bt (bterm [v2] b2).
Proof.
introv.
rw <- @isprogram_decide_iff.
unfold isprogram_bt; simpl.
unfold closed_bt; simpl.
repeat (rw <- null_iff_nil).
repeat (rw null_remove_nvars).
repeat (rw subvars_prop).
split; intro k; repnd; dands; auto.
inversion k1; sp.
inversion k; sp.
Qed.
Lemma isprogram_outl {p} :
forall t : @NTerm p, isprogram (mk_outl t) <=> isprogram t.
Proof.
introv.
rw <- @isprogram_decide_iff; simpl; split; intro i; repnd; auto.
dands; auto.
pose proof (@isprogram_bot p) as X.
destruct X. auto.
Qed.
Lemma isprogram_outr {p} :
forall t : @NTerm p, isprogram (mk_outr t) <=> isprogram t.
Proof.
introv.
rw <- @isprogram_decide_iff; simpl; split; intro i; repnd; auto.
dands; auto.
pose proof (@isprogram_bot p) as X.
destruct X. auto.
Qed.
Lemma isprogram_pi1 {p} :
forall t : @NTerm p, isprogram (mk_pi1 t) <=> isprogram t.
Proof.
introv.
rw <- @isprogram_spread_iff; simpl; split; intro i; repnd; auto.
dands; auto.
rw subvars_cons_l; sp.
Qed.
Lemma isprogram_pi2 {p} :
forall t : @NTerm p, isprogram (mk_pi2 t) <=> isprogram t.
Proof.
introv.
rw <- @isprogram_spread_iff; simpl; split; intro i; repnd; auto.
dands; auto.
rw subvars_cons_l; sp.
Qed.
Lemma isprogram_eta_pair {p} :
forall t : @NTerm p, isprogram (mk_eta_pair t) <=> isprogram t.
Proof.
introv.
rw <- @isprogram_pair_iff.
rw @isprogram_pi1.
rw @isprogram_pi2.
split; sp.
Qed.
Lemma iscvalue_mkc_tequality {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_tequality t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_tequality; allrw @isprog_eq; auto.
apply isprogram_tequality; sp.
Qed.
Lemma isprog_pw_iff {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C q,
isprog (mk_pw P ap A bp ba B cp ca cb C q)
<=> (isprog P
# isprog_vars [ap] A
# isprog_vars [bp, ba] B
# isprog_vars [cp, ca, cb] C
# isprog q).
Proof.
introv; split; intro isp.
rw @isprog_eq in isp.
inversion isp as [ cl wf ].
inversion wf as [|?| o lnt j e ]; subst.
generalize (j (nobnd P))
(j (bterm [ap] A))
(j (bterm [bp,ba] B))
(j (bterm [cp,ca,cb] C))
(j (nobnd q)); clear j;
intros i1 i2 i3 i4 i5; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
repeat (dest_imp i3 hyp).
repeat (dest_imp i4 hyp).
repeat (dest_imp i5 hyp).
inversion i1; inversion i2; inversion i3; inversion i4; inversion i5; subst.
unfold closed in cl; simpl in cl; allrw remove_nvars_nil_l; allrw app_nil_r.
rw <- null_iff_nil in cl.
allrw null_app; repnd.
allrw null_remove_nvars_subvars.
allrw null_iff_nil.
dands.
rw @isprog_eq; constructor; sp.
rw @isprog_vars_eq; sp.
rw @isprog_vars_eq; sp.
rw @isprog_vars_eq; sp.
rw @isprog_eq; constructor; sp.
apply isprog_pw; sp.
Qed.
Lemma isprog_pm_iff {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C q,
isprog (mk_pm P ap A bp ba B cp ca cb C q)
<=> (isprog P
# isprog_vars [ap] A
# isprog_vars [bp, ba] B
# isprog_vars [cp, ca, cb] C
# isprog q).
Proof.
introv; split; intro isp.
rw @isprog_eq in isp.
inversion isp as [ cl wf ].
inversion wf as [|?| o lnt j e ]; subst.
generalize (j (nobnd P))
(j (bterm [ap] A))
(j (bterm [bp,ba] B))
(j (bterm [cp,ca,cb] C))
(j (nobnd q)); clear j;
intros i1 i2 i3 i4 i5; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
repeat (dest_imp i3 hyp).
repeat (dest_imp i4 hyp).
repeat (dest_imp i5 hyp).
inversion i1; inversion i2; inversion i3; inversion i4; inversion i5; subst.
unfold closed in cl; simpl in cl; allrw remove_nvars_nil_l; allrw app_nil_r.
rw <- null_iff_nil in cl.
allrw null_app; repnd.
allrw null_remove_nvars_subvars.
allrw null_iff_nil.
dands.
rw @isprog_eq; constructor; sp.
rw @isprog_vars_eq; sp.
rw @isprog_vars_eq; sp.
rw @isprog_vars_eq; sp.
rw @isprog_eq; constructor; sp.
apply isprog_pm; sp.
Qed.
Lemma isprogram_exception_implies {p} :
forall (bterms : list (@BTerm p)),
isprogram (oterm Exc bterms)
-> {a : NTerm
$ {t : NTerm
$ bterms = [bterm [] a, bterm [] t]
# isprogram a
# isprogram t}}.
Proof.
introv isp.
inversion isp as [c w].
inversion w as [|?|o lnt bw m]; subst; allsimpl.
repeat (destruct bterms; ginv).
allsimpl; ginv.
destruct b as [l1 t1]; destruct b0 as [l2 t2].
destruct l1; destruct l2; ginv.
allunfold @num_bvars; allsimpl; GC.
unfold closed in c; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw app_eq_nil_iff.
pose proof (bw (bterm [] t1)) as w1.
pose proof (bw (bterm [] t2)) as w2.
repeat (autodimp w1 hyp); repeat (autodimp w2 hyp).
inversion w1; inversion w2; subst.
exists t1 t2; dands; auto; constructor; sp.
Qed.
Lemma iscan_implies {p} :
forall t : @NTerm p,
iscan t
-> {c : CanonicalOp
& {bterms : list BTerm
& t = oterm (Can c) bterms}}
[+] {f : ntseq & t = sterm f}.
Proof.
introv isc.
destruct t as [v|f|op bs]; try (complete (inversion isc)).
- right.
eexists; eauto.
- destruct op; try (complete (inversion isc)).
left; exists c bs; sp.
Qed.
Lemma isexc_implies {p} :
forall t : @NTerm p,
isexc t
-> isprogram t
-> {a : NTerm & {e : NTerm & t = mk_exception a e}}.
Proof.
introv isc isp.
destruct t; try (complete (inversion isc)).
destruct o; try (complete (inversion isc)).
apply isprogram_exception_implies in isp; sp; subst.
eexists; eexists; reflexivity.
Qed.
Lemma isexc_implies2 {p} :
forall t : @NTerm p,
isexc t
-> {l : list BTerm & t = oterm Exc l}.
Proof.
introv isc.
destruct t; try (complete (inversion isc)).
destruct o; try (complete (inversion isc)).
eexists; eexists; sp.
Qed.
Lemma isprogram_trycatch_implies {p} :
forall (bterms : list (@BTerm p)),
isprogram (oterm (NCan NTryCatch) bterms)
-> {t : NTerm
$ {a : NTerm
$ {v : NVar
$ {b : NTerm
$ bterms = [bterm [] t, bterm [] a, bterm [v] b]
# isprogram t
# isprogram a
# isprogram_bt (bterm [v] b)}}}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b as [l1 t1]; allsimpl; cpx.
destruct b0 as [l2 t2]; allsimpl; cpx.
destruct b1 as [l3 t3]; allsimpl; cpx.
destruct l1; allsimpl; cpx.
destruct l2; allsimpl; cpx.
repeat (destruct l3; allsimpl; cpx).
generalize (isp (bterm [] t1)) (isp (bterm [] t2)) (isp (bterm [n] t3)); intros isp1 isp2 isp3.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
repeat (autodimp isp3 hyp).
apply isprogram_bt_nobnd in isp1.
apply isprogram_bt_nobnd in isp2.
exists t1 t2 n t3; sp.
Qed.
Lemma isprogram_fresh_implies {p} :
forall (bterms : list (@BTerm p)),
isprogram (oterm (NCan NFresh) bterms)
-> {v : NVar
$ {b : NTerm
$ bterms = [bterm [v] b]
# isprogram_bt (bterm [v] b)}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [n0] n)); intros isp1.
repeat (autodimp isp1 hyp).
exists n0 n; sp.
Qed.
Lemma isprogram_cbv_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NCbv) bterms)
-> {t : NTerm
$ {v : NVar
$ {b : NTerm
$ bterms = [bterm [] t, bterm [v] b]
# isprogram t
# isprogram_bt (bterm [v] b)}}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [n1] n0)); intros isp1 isp2.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
apply isprogram_bt_nobnd in isp1.
exists n n1 n0; sp.
Qed.
Lemma isprogram_apply_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NApply) bterms)
-> {f : NTerm
$ {a : NTerm
$ bterms = [bterm [] f, bterm [] a]
# isprogram f
# isprogram a}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [] n0)); intros isp1 isp2.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
apply isprogram_bt_nobnd in isp1.
apply isprogram_bt_nobnd in isp2.
exists n n0; sp.
Qed.
Lemma isprogram_eapply_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NEApply) bterms)
-> {f : NTerm
$ {a : NTerm
$ bterms = [bterm [] f, bterm [] a]
# isprogram f
# isprogram a}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [] n0)); intros isp1 isp2.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
apply isprogram_bt_nobnd in isp1.
apply isprogram_bt_nobnd in isp2.
exists n n0; sp.
Qed.
Lemma isprogram_apseq_implies {p} :
forall f (bterms : list (@BTerm p)),
isprogram (oterm (NCan (NApseq f)) bterms)
-> {a : NTerm
$ bterms = [bterm [] a]
# isprogram a}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)); intros isp1.
repeat (autodimp isp1 hyp).
apply isprogram_bt_nobnd in isp1.
exists n; sp.
Qed.
Lemma isprogram_parallel_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NParallel) bterms)
-> {a : NTerm
$ {b : NTerm
$ bterms = [bterm [] a, bterm [] b]
# isprogram a
# isprogram b}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [] n0)); intros isp1 isp2.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
apply isprogram_bt_nobnd in isp1.
apply isprogram_bt_nobnd in isp2.
exists n n0; sp.
Qed.
Lemma isprogram_fix_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NFix) bterms)
-> {f : NTerm
$ bterms = [bterm [] f]
# isprogram f}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
generalize (isp (bterm [] n)); intros isp1.
repeat (autodimp isp1 hyp).
apply isprogram_bt_nobnd in isp1.
exists n; sp.
Qed.
Lemma isprogram_sleep_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NSleep) bterms)
-> {t : NTerm
$ bterms = [bterm [] t]
# isprogram t}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
generalize (isp (bterm [] n)); intros isp1.
repeat (autodimp isp1 hyp).
apply isprogram_bt_nobnd in isp1.
exists n; sp.
Qed.
Lemma isprogram_tuni_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NTUni) bterms)
-> {t : NTerm
$ bterms = [bterm [] t]
# isprogram t}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
generalize (isp (bterm [] n)); intros isp1.
repeat (autodimp isp1 hyp).
apply isprogram_bt_nobnd in isp1.
exists n; sp.
Qed.
Lemma isprogram_minus_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NMinus) bterms)
-> {t : NTerm
$ bterms = [bterm [] t]
# isprogram t}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
generalize (isp (bterm [] n)); intros isp1.
repeat (autodimp isp1 hyp).
apply isprogram_bt_nobnd in isp1.
exists n; sp.
Qed.
Lemma isprogram_spread_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NSpread) bterms)
-> {t : NTerm
$ {v1 : NVar
$ {v2 : NVar
$ {b : NTerm
$ bterms = [bterm [] t, bterm [v1,v2] b]
# isprogram t
# isprogram_bt (bterm [v1,v2] b)}}}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [n1,n2] n0)); intros isp1 isp2.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
apply isprogram_bt_nobnd in isp1.
exists n n1 n2 n0; sp.
Qed.
Lemma isprogram_dsup_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NDsup) bterms)
-> {t : NTerm
$ {v1 : NVar
$ {v2 : NVar
$ {b : NTerm
$ bterms = [bterm [] t, bterm [v1,v2] b]
# isprogram t
# isprogram_bt (bterm [v1,v2] b)}}}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [n1,n2] n0)); intros isp1 isp2.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
apply isprogram_bt_nobnd in isp1.
exists n n1 n2 n0; sp.
Qed.
Lemma isprogram_decide_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NDecide) bterms)
-> {t : NTerm
$ {v1 : NVar
$ {b1 : NTerm
$ {v2 : NVar
$ {b2 : NTerm
$ bterms = [bterm [] t, bterm [v1] b1, bterm [v2] b2]
# isprogram t
# isprogram_bt (bterm [v1] b1)
# isprogram_bt (bterm [v2] b2)}}}}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
destruct b1; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [n1] n0)) (isp (bterm [n3] n2));
intros isp1 isp2 isp3.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
repeat (autodimp isp3 hyp).
apply isprogram_bt_nobnd in isp1.
exists n n1 n0 n3 n2; sp.
Qed.
Lemma isprogram_arithop_implies {p} :
forall o (bterms : list (@BTerm p)),
isprogram (oterm (NCan (NArithOp o)) bterms)
-> {a : NTerm
$ {b : NTerm
$ bterms = [bterm [] a, bterm [] b]
# isprogram a
# isprogram b}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [] n0)); intros isp1 isp2.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
apply isprogram_bt_nobnd in isp1.
apply isprogram_bt_nobnd in isp2.
exists n n0; sp.
Qed.
Lemma isprogram_arithop_iff {p} :
forall o (bterms : list (@BTerm p)),
isprogram (oterm (NCan (NArithOp o)) bterms)
<=> {a : NTerm
$ {b : NTerm
$ bterms = [bterm [] a, bterm [] b]
# isprogram a
# isprogram b}}.
Proof.
introv; split; intro k.
apply isprogram_arithop_implies in k; auto.
exrepnd; subst.
apply isprogram_ot_iff; simpl.
unfold num_bvars; simpl; dands; sp; subst;
apply implies_isprogram_bt0; auto.
Qed.
Lemma isprogram_compop_implies {p} :
forall o (bterms : list (@BTerm p)),
isprogram (oterm (NCan (NCompOp o)) bterms)
-> {a : NTerm
$ {b : NTerm
$ {c : NTerm
$ {d : NTerm
$ bterms = [bterm [] a, bterm [] b, bterm [] c, bterm [] d]
# isprogram a
# isprogram b
# isprogram c
# isprogram d}}}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
destruct b1; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct l0; allsimpl; cpx.
destruct b2; allsimpl; cpx.
destruct l; allsimpl; cpx.
generalize
(isp (bterm [] n))
(isp (bterm [] n0))
(isp (bterm [] n1))
(isp (bterm [] n2));
intros isp1 isp2 isp3 isp4.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
repeat (autodimp isp3 hyp).
repeat (autodimp isp4 hyp).
allapply @isprogram_bt_nobnd.
exists n n0 n1 n2; sp.
Qed.
Lemma isprogram_compop_iff {p} :
forall o (bterms : list (@BTerm p)),
isprogram (oterm (NCan (NCompOp o)) bterms)
<=> {a : NTerm
$ {b : NTerm
$ {c : NTerm
$ {d : NTerm
$ bterms = [bterm [] a, bterm [] b, bterm [] c, bterm [] d]
# isprogram a
# isprogram b
# isprogram c
# isprogram d}}}}.
Proof.
introv; split; intro k.
apply isprogram_compop_implies in k; auto.
exrepnd; subst.
apply isprogram_ot_iff; unfold num_bvars; simpl; sp; subst;
apply implies_isprogram_bt0; auto.
Qed.
Lemma isprogram_cantest_implies {p} :
forall o (bterms : list (@BTerm p)),
isprogram (oterm (NCan (NCanTest o)) bterms)
-> {a : NTerm
$ {b : NTerm
$ {c : NTerm
$ bterms = [bterm [] a, bterm [] b, bterm [] c]
# isprogram a
# isprogram b
# isprogram c}}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
destruct b1; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct l0; allsimpl; cpx.
generalize
(isp (bterm [] n))
(isp (bterm [] n0))
(isp (bterm [] n1));
intros isp1 isp2 isp3.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
repeat (autodimp isp3 hyp).
allapply @isprogram_bt_nobnd.
exists n n0 n1; sp.
Qed.
Lemma isprogram_cantest_iff {p} :
forall o (bterms : list (@BTerm p)),
isprogram (oterm (NCan (NCanTest o)) bterms)
<=> {a : NTerm
$ {b : NTerm
$ {c : NTerm
$ bterms = [bterm [] a, bterm [] b, bterm [] c]
# isprogram a
# isprogram b
# isprogram c}}}.
Proof.
introv; split; intro k.
apply isprogram_cantest_implies in k; auto.
exrepnd; subst.
apply isprogram_ot_iff; unfold num_bvars; simpl; sp; subst;
apply implies_isprogram_bt0; auto.
Qed.
Lemma isprog_vars_btrue {o} :
forall vs, @isprog_vars o vs mk_btrue.
Proof.
introv.
rw @isprog_vars_eq; simpl; dands; auto.
constructor; simpl; tcsp.
introv i; repndors; subst; tcsp.
constructor; eauto with slow.
Qed.
Lemma isprog_vars_bfalse {o} :
forall vs, @isprog_vars o vs mk_bfalse.
Proof.
introv.
rw @isprog_vars_eq; simpl; dands; auto.
constructor; simpl; tcsp.
introv i; repndors; subst; tcsp.
constructor; eauto with slow.
Qed.
Lemma isprog_vars_le_implies {o} :
forall (a b : @NTerm o) vs,
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs (mk_le a b).
Proof.
introv u v.
apply isprog_vars_le; sp.
Qed.
Lemma isprog_vars_less_than {o} :
forall (a b : @NTerm o) vs,
isprog_vars vs (mk_less_than a b) <=> (isprog_vars vs a # isprog_vars vs b).
Proof.
introv; unfold mk_less_than.
rw @isprog_vars_less; split; sp.
apply isprog_vars_true_iff; sp.
Qed.
Lemma isprog_implies_isprog_vars_nil {o} :
forall t, @isprog o t -> isprog_vars [] t.
Proof.
introv isp.
apply isprog_eq in isp.
apply isprog_vars_eq.
rw subvars_nil_r; auto.
Qed.
Lemma isprog_vars_nil_implies_isprog {o} :
forall t, isprog_vars [] t -> @isprog o t.
Proof.
introv isp.
apply isprog_eq.
apply isprog_vars_eq in isp; repnd.
apply subvars_nil_r in isp0.
unfold isprogram; auto.
Qed.
Lemma isprog_vars_nil_iff_isprog {o} :
forall t, @isprog o t <=> isprog_vars [] t.
Proof.
introv; split; intro k.
apply isprog_implies_isprog_vars_nil; auto.
apply isprog_vars_nil_implies_isprog; auto.
Qed.
Lemma isprog_less_than {o} :
forall a b : @NTerm o,
isprog (mk_less_than a b) <=> (isprog a # isprog b).
Proof.
introv.
allrw @isprog_vars_nil_iff_isprog.
apply isprog_vars_less_than.
Qed.
Lemma isprog_less_than_implies {o} :
forall a b : @NTerm o,
isprog a
-> isprog b
-> isprog (mk_less_than a b).
Proof.
introv x y.
apply isprog_less_than; sp.
Qed.
Lemma isprog_vars_prod_implies {p} :
forall vs (a b : @NTerm p),
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs (mk_prod a b).
Proof.
introv ispa ispb.
apply isprog_vars_prod; sp.
Qed.
Lemma isprog_vars_less_than_implies {o} :
forall (a b : @NTerm o) vs,
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs (mk_less_than a b).
Proof.
introv u v.
apply isprog_vars_less_than; sp.
Qed.
Lemma isprog_ot_iff {p} :
forall (o : @Opid p) (bts : list BTerm),
isprog (oterm o bts)
<=>
map num_bvars bts = OpBindings o
# (forall bt : BTerm, LIn bt bts -> isprog_bt bt).
Proof.
introv.
rw @isprog_eq.
rw @isprogram_ot_iff; split; intro k; repnd; dands; auto;
introv i; apply isprogram_bt_eq; auto.
Qed.
Lemma isprog_decide_iff {o} :
forall (a : @NTerm o) (v1 : NVar) (a1 : NTerm) (v2 : NVar) (a2 : NTerm),
isprog (mk_decide a v1 a1 v2 a2)
<=> (isprog a # isprog_vars [v1] a1 # isprog_vars [v2] a2).
Proof.
introv.
split; intro k; repnd; try (apply isprog_decide; auto).
unfold mk_decide in k.
rw @isprog_ot_iff in k; repnd; allsimpl; clear k0.
pose proof (k (nobnd a)) as h1; autodimp h1 hyp.
pose proof (k (bterm [v1] a1)) as h2; autodimp h2 hyp.
pose proof (k (bterm [v2] a2)) as h3; autodimp h3 hyp.
Qed.
Lemma isprog_vars_not {o} :
forall vs (t : @NTerm o),
isprog_vars vs (mk_not t) <=> isprog_vars vs t.
Proof.
introv.
unfold mk_not.
rw <- @isprog_vars_fun.
rw @isprog_vars_void_iff.
split; sp.
Qed.
Lemma implies_isprog_vars_not {o} :
forall vs (t : @NTerm o),
isprog_vars vs t -> isprog_vars vs (mk_not t).
Proof.
introv isp.
apply isprog_vars_not; auto.
Qed.
Lemma isprog_vars_disjoint_implies_isprog {o} :
forall vs (t : @NTerm o),
isprog_vars vs t
-> disjoint vs (free_vars t)
-> isprog t.
Proof.
introv isp disj.
allrw @isprog_vars_eq; repnd.
rw @isprog_eq.
constructor; auto.
unfold closed.
apply null_iff_nil.
introv i.
rw subvars_prop in isp0.
applydup isp0 in i.
apply disj in i0; sp.
Qed.
(* end hide *)
(**
We say that a term [t] is covered by a list of variables [vs] if the
free variables of [t] are all in [vs].
*)
Definition covered {p} (t : @NTerm p) (vs : list NVar) :=
subvars (free_vars t) vs.
(* begin hide *)
Lemma covered_proof_irrelevance {p} :
forall t vs,
forall x y : @covered p t vs,
x = y.
Proof.
intros.
apply UIP_dec.
apply bool_dec.
Qed.
Hint Extern 0 =>
let h := fresh "h" in
match goal with
| [ H1 : covered ?t ?vs , H2 : covered ?t ?vs |- _ ] =>
pose proof (covered_proof_irrelevance t vs H2 H1) as h; subst
end : pi.
Lemma isprog_vars_implies_covered {o} :
forall (t : @NTerm o) vs,
isprog_vars vs t -> covered t vs.
Proof.
introv isp.
unfold covered.
allrw @isprog_vars_eq; sp.
Qed.
Hint Resolve isprog_vars_implies_covered : slow.
(* --- isprog hints --- *)
Hint Resolve isprog_lam : isprog.
Hint Resolve isprog_vars_lam : isprog.
Hint Resolve isprog_vars_isect : isprog.
Hint Resolve isprog_vars_base : isprog.
Hint Resolve isprog_vars_equality : isprog.
Hint Resolve isprog_vars_var_if : isprog.
Hint Resolve isprog_vars_if_isprog : isprog.
Hint Extern 100 (LIn _ _) => complete (simpl; sp) : isprog.
Hint Resolve isprog_implies : isprog.
Hint Resolve isprog_vars_btrue : slow.
Hint Resolve isprog_vars_bfalse : slow.
Hint Resolve isprog_vars_le_implies : slow.
Hint Resolve isprog_vars_less_than_implies : slow.
Hint Resolve isprog_vars_prod_implies : slow.
Hint Resolve wf_function : slow.
Hint Resolve wf_product : slow.
Lemma ispexc_exception {p} :
forall a e : @NTerm p,
isprogram a -> isprogram e -> ispexc (mk_exception a e).
Proof.
introv isp1 isp2.
split.
constructor.
apply isprogram_exception; auto.
Qed.
Hint Resolve ispexc_exception.
Lemma isp_can_or_exc_exception {p} :
forall a e : @NTerm p,
isprogram a
-> isprogram e
-> isp_can_or_exc (mk_exception a e).
Proof.
introv isp1 isp2.
split; auto.
apply isprogram_exception; auto.
right; sp.
Qed.
Hint Resolve isp_can_or_exc_exception.
Lemma free_vars_list_nil {p} :
forall ts : list (@NTerm p),
(forall t, LIn t ts -> isprog t)
-> free_vars_list ts = [].
Proof.
induction ts; introv h; allsimpl; auto.
allrw IHts; sp.
pose proof (h a) as k; autodimp k hyp.
apply isprog_eq in k.
inversion k.
allunfold @closed.
allrw; sp.
Qed.
Lemma newvarlst_prog {p} :
forall ts : list (@NTerm p),
(forall t, LIn t ts -> isprog t)
-> newvarlst ts = nvarx.
Proof.
introv h.
unfold newvarlst.
rw @free_vars_list_nil; auto.
Qed.
Lemma nt_wf_oterm_iff {p} :
forall o (bts : list (@BTerm p)),
nt_wf (oterm o bts)
<=> map num_bvars bts = OpBindings o
# forall b, LIn b bts -> bt_wf b.
Proof.
introv. sp_iff Case; introv h; repnd.
- Case "->".
inverts h as Hbf Hmap. split; auto.
- Case "<-".
constructor; auto.
Qed.
Lemma isprog_vars_ot_iff {p} :
forall (vs : list NVar) (o : @Opid p) (bts : list BTerm),
isprog_vars vs (oterm o bts)
<=>
map num_bvars bts = OpBindings o
# (forall l t, LIn (bterm l t) bts -> isprog_vars (vs ++ l) t).
Proof.
introv.
rw @isprog_vars_eq; simpl.
rw @nt_wf_oterm_iff.
rw subvars_flat_map.
split; intro k; repnd; dands; auto; introv i.
- apply isprog_vars_eq; dands.
apply k0 in i; simpl in i.
rw subvars_remove_nvars in i; auto.
apply k in i; inversion i; subst; auto.
- destruct x; simpl.
rw subvars_remove_nvars.
apply k in i.
apply isprog_vars_eq in i; repnd; auto.
- destruct b.
apply k in i.
apply isprog_vars_eq in i; repnd; auto.
Qed.
Lemma nt_wf_bottom {o} : nt_wf (@mk_bottom o).
Proof.
repeat constructor; simpl; introv i; dorn i; cpx; subst.
repeat constructor; simpl; introv i; dorn i; cpx; subst.
repeat constructor; simpl; introv i; dorn i; cpx; subst.
Qed.
Lemma closed_if_program {o} :
forall t : @NTerm o, isprogram t -> closed t.
Proof.
introv isp; destruct isp; auto.
Qed.
Hint Resolve closed_if_program : slow.
Definition mk_compop {p} x (a b c d : @NTerm p) :=
oterm (NCan (NCompOp x)) [nobnd a, nobnd b, nobnd c, nobnd d].
Lemma wf_compop {p} :
forall x (a b c d : @NTerm p),
wf_term a -> wf_term b -> wf_term c -> wf_term d
-> wf_term (mk_compop x a b c d).
Proof.
introv wa wb wc wd; allrw <- @nt_wf_eq.
constructor; simpl; tcsp.
introv k; repndors; subst; tcsp; constructor; auto.
Qed.
Lemma wf_compop_iff {p} :
forall x (a b c d : @NTerm p),
wf_term (mk_compop x a b c d) <=> (wf_term a # wf_term b # wf_term c # wf_term d).
Proof.
introv; split; intro k.
- allrw @wf_term_eq.
inversion k as [|?|? ? i e]; subst; allsimpl.
pose proof (i (nobnd a)) as ha.
pose proof (i (nobnd b)) as hb.
pose proof (i (nobnd c)) as hc.
pose proof (i (nobnd d)) as hd.
repeat (autodimp ha hyp).
repeat (autodimp hb hyp).
repeat (autodimp hc hyp).
repeat (autodimp hd hyp).
inversion ha; subst.
inversion hb; subst.
inversion hc; subst.
inversion hd; subst; sp.
- apply wf_compop; sp.
Qed.
Definition mk_arithop {p} x (a b : @NTerm p) :=
oterm (NCan (NArithOp x)) [nobnd a, nobnd b].
Lemma wf_arithop {p} :
forall x (a b : @NTerm p),
wf_term a -> wf_term b
-> wf_term (mk_arithop x a b).
Proof.
introv wa wb; allrw <- @nt_wf_eq.
constructor; simpl; tcsp.
introv k; repndors; subst; tcsp; constructor; auto.
Qed.
Lemma wf_arithop_iff {p} :
forall x (a b : @NTerm p),
wf_term (mk_arithop x a b) <=> (wf_term a # wf_term b).
Proof.
introv; split; intro k.
- allrw @wf_term_eq.
inversion k as [|?|? ? i e]; subst; allsimpl.
pose proof (i (nobnd a)) as ha.
pose proof (i (nobnd b)) as hb.
repeat (autodimp ha hyp).
repeat (autodimp hb hyp).
inversion ha; subst.
inversion hb; subst; sp.
- apply wf_arithop; sp.
Qed.
Lemma isprog_arithop {p} :
forall (op: ArithOp) (a b : @NTerm p), isprog a -> isprog b -> isprog (mk_arithop op a b).
Proof.
sp; allrw @isprog_eq; intros; apply isprogram_arithop_iff; sp.
exists a b; auto.
Qed.
Definition mkc_arithop {p} (op: ArithOp) (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_arithop op a b) (isprog_arithop op a b x y).
Lemma wf_can_test {p} :
forall x (a b c : @NTerm p),
wf_term a -> wf_term b -> wf_term c
-> wf_term (mk_can_test x a b c).
Proof.
introv wa wb wc; allrw <- @nt_wf_eq.
constructor; simpl; tcsp.
introv k; repndors; subst; tcsp; constructor; auto.
Qed.
Lemma wf_can_test_iff {p} :
forall x (a b c : @NTerm p),
wf_term (mk_can_test x a b c) <=> (wf_term a # wf_term b # wf_term c).
Proof.
introv; split; intro k.
- allrw @wf_term_eq.
inversion k as [|?|? ? i e]; subst; allsimpl.
pose proof (i (nobnd a)) as ha.
pose proof (i (nobnd b)) as hb.
pose proof (i (nobnd c)) as hc.
repeat (autodimp ha hyp).
repeat (autodimp hb hyp).
repeat (autodimp hc hyp).
inversion ha; subst.
inversion hb; subst.
inversion hc; subst; sp.
- apply wf_can_test; sp.
Qed.
Lemma wf_dsup {p} :
forall (a : @NTerm p) v1 v2 b,
wf_term (mk_dsup a v1 v2 b) <=> (wf_term a # wf_term b).
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bwf e ]; subst.
generalize (bwf (nobnd a)) (bwf (bterm [v1,v2] b)); clear bwf; intros bwf1 bwf2.
autodimp bwf1 hyp; autodimp bwf2 hyp; try (complete (simpl; sp)).
inversion bwf1; subst.
inversion bwf2; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; sp.
allsimpl; sp; subst; constructor; allrw @nt_wf_eq; sp.
Qed.
Lemma wf_sup_iff {p} :
forall a b : @NTerm p, wf_term (mk_sup a b) <=> (wf_term a # wf_term b).
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e]; subst.
generalize (bw (nobnd a)) (bw (nobnd b)); simpl; intros bw1 bw2.
autodimp bw1 hyp.
autodimp bw2 hyp.
inversion bw1; subst.
inversion bw2; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_inl {p} :
forall a : @NTerm p, wf_term (mk_inl a) <=> wf_term a.
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e]; subst.
generalize (bw (nobnd a)); simpl; intros bw1.
autodimp bw1 hyp.
inversion bw1; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_inr {p} :
forall a : @NTerm p, wf_term (mk_inr a) <=> wf_term a.
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e]; subst.
generalize (bw (nobnd a)); simpl; intros bw1.
autodimp bw1 hyp.
inversion bw1; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_decide {p} :
forall (a : @NTerm p) v1 b1 v2 b2,
wf_term (mk_decide a v1 b1 v2 b2) <=> (wf_term a # wf_term b1 # wf_term b2).
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bwf e ]; subst.
generalize (bwf (nobnd a)) (bwf (bterm [v1] b1)) (bwf (bterm [v2] b2));
clear bwf; intros bwf1 bwf2 bwf3.
autodimp bwf1 hyp; autodimp bwf2 hyp; autodimp bwf3 hyp; try (complete (simpl; sp)).
inversion bwf1; subst.
inversion bwf2; subst.
inversion bwf3; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; sp.
allsimpl; sp; subst; constructor; allrw @nt_wf_eq; sp.
Qed.
Lemma wf_fix_iff {p} :
forall t : @NTerm p,
wf_term (mk_fix t) <=> wf_term t.
Proof.
introv; split; intro k.
- allrw @wf_term_eq.
inversion k as [|?|? ? i]; allsimpl; subst; ginv.
pose proof (i (bterm [] t)) as h; autodimp h hyp.
inversion h; subst; auto.
- apply wf_fix; auto.
Qed.
Lemma closed_bt_bterm {o} :
forall vs (t : @NTerm o),
closed_bt (bterm vs t)
<=> subvars (free_vars t) vs.
Proof.
introv.
unfold closed_bt; simpl.
rw nil_remove_nvars_iff.
rw subvars_prop; sp.
Qed.
Lemma wf_fresh {p} :
forall v (b : @NTerm p), wf_term b -> wf_term (mk_fresh v b).
Proof.
intros v b; repeat (rw <- @nt_wf_eq).
intros ntb; inversion ntb; subst; constructor; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma wf_fresh_iff {p} :
forall v (b : @NTerm p), wf_term (mk_fresh v b) <=> wf_term b.
Proof.
introv; split; intro i; try (apply wf_fresh; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (bterm [v] b)); intros j.
dest_imp j hyp; sp.
inversion j; subst; sp.
Qed.
Lemma isprog_vars_subvars {o} :
forall (t : @NTerm o) vs1 vs2,
subvars vs1 vs2
-> isprog_vars vs1 t
-> isprog_vars vs2 t.
Proof.
introv sv isp.
allrw @isprog_vars_eq; repnd; dands; auto.
eapply subvars_trans; eauto.
Qed.
Hint Resolve isprog_vars_subvars : slow.
Lemma nt_wf_eapply_iff {p} :
forall (bs : list (@BTerm p)),
nt_wf (oterm (NCan NEApply) bs)
<=> {a : NTerm
$ {b : NTerm
$ bs = [bterm [] a, bterm [] b]
# nt_wf a
# nt_wf b}}.
Proof.
introv; split; intro k.
- inversion k as [|?|? ? imp e]; clear k; subst.
allsimpl.
repeat (destruct bs; allsimpl; ginv).
destruct b as [l1 t1].
destruct b0 as [l2 t2].
allunfold @num_bvars; allsimpl.
destruct l1; ginv.
destruct l2; ginv.
pose proof (imp (bterm [] t1)) as h1.
autodimp h1 hyp.
pose proof (imp (bterm [] t2)) as h2.
autodimp h2 hyp.
allrw @bt_wf_iff.
exists t1 t2; dands; auto.
- exrepnd; subst.
repeat constructor.
introv i; allsimpl; repndors; subst; tcsp.
Qed.
(* end hide *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21AI_TB_V
`define SKY130_FD_SC_LP__O21AI_TB_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_lp__o21ai dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21AI_TB_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016
// Date : Thu May 4 16:19:46 2017
// Host : david-desktop-arch running 64-bit unknown
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ init_config_rom_stub.v
// Design : init_config_rom
// Purpose : Stub declaration of top-level module interface
// Device : xc7a200tfbg484-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_4,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[9:0],douta[31:0]" */;
input clka;
input [9:0]addra;
output [31:0]douta;
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module kernel_clock_0_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else
data_in_d1 <= data_in;
end
assign data_out = data_in ^ data_in_d1;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module kernel_clock_0_slave_FSM (
// inputs:
master_read_done_token,
master_write_done_token,
slave_clk,
slave_read,
slave_reset_n,
slave_write,
// outputs:
slave_read_request,
slave_waitrequest,
slave_write_request
)
;
output slave_read_request;
output slave_waitrequest;
output slave_write_request;
input master_read_done_token;
input master_write_done_token;
input slave_clk;
input slave_read;
input slave_reset_n;
input slave_write;
reg next_slave_read_request;
reg [ 2: 0] next_slave_state;
reg next_slave_write_request;
reg slave_read_request;
reg [ 2: 0] slave_state;
reg slave_waitrequest;
reg slave_write_request;
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_read_request <= 0;
else if (1)
slave_read_request <= next_slave_read_request;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_write_request <= 0;
else if (1)
slave_write_request <= next_slave_write_request;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_state <= 3'b001;
else if (1)
slave_state <= next_slave_state;
end
always @(master_read_done_token or master_write_done_token or slave_read or slave_read_request or slave_state or slave_write or slave_write_request)
begin
case (slave_state) // synthesis parallel_case
3'b001: begin
//read request: go from IDLE state to READ_WAIT state
if (slave_read)
begin
next_slave_state = 3'b010;
slave_waitrequest = 1;
next_slave_read_request = !slave_read_request;
next_slave_write_request = slave_write_request;
end
else if (slave_write)
begin
next_slave_state = 3'b100;
slave_waitrequest = 1;
next_slave_read_request = slave_read_request;
next_slave_write_request = !slave_write_request;
end
else
begin
next_slave_state = slave_state;
slave_waitrequest = 0;
next_slave_read_request = slave_read_request;
next_slave_write_request = slave_write_request;
end
end // 3'b001
3'b010: begin
//stay in READ_WAIT state until master passes read done token
if (master_read_done_token)
begin
next_slave_state = 3'b001;
slave_waitrequest = 0;
end
else
begin
next_slave_state = 3'b010;
slave_waitrequest = 1;
end
next_slave_read_request = slave_read_request;
next_slave_write_request = slave_write_request;
end // 3'b010
3'b100: begin
//stay in WRITE_WAIT state until master passes write done token
if (master_write_done_token)
begin
next_slave_state = 3'b001;
slave_waitrequest = 0;
end
else
begin
next_slave_state = 3'b100;
slave_waitrequest = 1;
end
next_slave_read_request = slave_read_request;
next_slave_write_request = slave_write_request;
end // 3'b100
default: begin
next_slave_state = 3'b001;
slave_waitrequest = 0;
next_slave_read_request = slave_read_request;
next_slave_write_request = slave_write_request;
end // default
endcase // slave_state
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module kernel_clock_0_master_FSM (
// inputs:
master_clk,
master_reset_n,
master_waitrequest,
slave_read_request_token,
slave_write_request_token,
// outputs:
master_read,
master_read_done,
master_write,
master_write_done
)
;
output master_read;
output master_read_done;
output master_write;
output master_write_done;
input master_clk;
input master_reset_n;
input master_waitrequest;
input slave_read_request_token;
input slave_write_request_token;
reg master_read;
reg master_read_done;
reg [ 2: 0] master_state;
reg master_write;
reg master_write_done;
reg next_master_read;
reg next_master_read_done;
reg [ 2: 0] next_master_state;
reg next_master_write;
reg next_master_write_done;
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_read_done <= 0;
else if (1)
master_read_done <= next_master_read_done;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_write_done <= 0;
else if (1)
master_write_done <= next_master_write_done;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_read <= 0;
else if (1)
master_read <= next_master_read;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_write <= 0;
else if (1)
master_write <= next_master_write;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_state <= 3'b001;
else if (1)
master_state <= next_master_state;
end
always @(master_read or master_read_done or master_state or master_waitrequest or master_write or master_write_done or slave_read_request_token or slave_write_request_token)
begin
case (master_state) // synthesis parallel_case
3'b001: begin
//if read request token from slave then goto READ_WAIT state
if (slave_read_request_token)
begin
next_master_state = 3'b010;
next_master_read = 1;
next_master_write = 0;
end
else if (slave_write_request_token)
begin
next_master_state = 3'b100;
next_master_read = 0;
next_master_write = 1;
end
else
begin
next_master_state = master_state;
next_master_read = 0;
next_master_write = 0;
end
next_master_read_done = master_read_done;
next_master_write_done = master_write_done;
end // 3'b001
3'b010: begin
//stay in READ_WAIT state until master wait is deasserted
if (!master_waitrequest)
begin
next_master_state = 3'b001;
next_master_read_done = !master_read_done;
next_master_read = 0;
end
else
begin
next_master_state = 3'b010;
next_master_read_done = master_read_done;
next_master_read = master_read;
end
next_master_write_done = master_write_done;
next_master_write = 0;
end // 3'b010
3'b100: begin
//stay in WRITE_WAIT state until slave wait is deasserted
if (!master_waitrequest)
begin
next_master_state = 3'b001;
next_master_write = 0;
next_master_write_done = !master_write_done;
end
else
begin
next_master_state = 3'b100;
next_master_write = master_write;
next_master_write_done = master_write_done;
end
next_master_read_done = master_read_done;
next_master_read = 0;
end // 3'b100
default: begin
next_master_state = 3'b001;
next_master_write = 0;
next_master_write_done = master_write_done;
next_master_read = 0;
next_master_read_done = master_read_done;
end // default
endcase // master_state
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module kernel_clock_0_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
)
;
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk1 or negedge reset_clk1_n)
begin
if (reset_clk1_n == 0)
data_in_d1 <= 0;
else
data_in_d1 <= data_in;
end
always @(posedge clk2 or negedge reset_clk2_n)
begin
if (reset_clk2_n == 0)
data_out <= 0;
else
data_out <= data_in_d1;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//Clock Domain Crossing Adapterkernel_clock_0
module kernel_clock_0 (
// inputs:
master_clk,
master_endofpacket,
master_readdata,
master_reset_n,
master_waitrequest,
slave_address,
slave_byteenable,
slave_clk,
slave_nativeaddress,
slave_read,
slave_reset_n,
slave_write,
slave_writedata,
// outputs:
master_address,
master_byteenable,
master_nativeaddress,
master_read,
master_write,
master_writedata,
slave_endofpacket,
slave_readdata,
slave_waitrequest
)
;
output [ 19: 0] master_address;
output [ 1: 0] master_byteenable;
output [ 18: 0] master_nativeaddress;
output master_read;
output master_write;
output [ 15: 0] master_writedata;
output slave_endofpacket;
output [ 15: 0] slave_readdata;
output slave_waitrequest;
input master_clk;
input master_endofpacket;
input [ 15: 0] master_readdata;
input master_reset_n;
input master_waitrequest;
input [ 19: 0] slave_address;
input [ 1: 0] slave_byteenable;
input slave_clk;
input [ 18: 0] slave_nativeaddress;
input slave_read;
input slave_reset_n;
input slave_write;
input [ 15: 0] slave_writedata;
reg [ 19: 0] master_address /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
reg [ 1: 0] master_byteenable /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
reg [ 18: 0] master_nativeaddress /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
wire master_read;
wire master_read_done;
wire master_read_done_sync;
wire master_read_done_token;
wire master_write;
wire master_write_done;
wire master_write_done_sync;
wire master_write_done_token;
reg [ 15: 0] master_writedata /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
reg [ 19: 0] slave_address_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
reg [ 1: 0] slave_byteenable_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
wire slave_endofpacket;
reg [ 18: 0] slave_nativeaddress_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
wire slave_read_request;
wire slave_read_request_sync;
wire slave_read_request_token;
reg [ 15: 0] slave_readdata /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON" */;
reg [ 15: 0] slave_readdata_p1;
wire slave_waitrequest;
wire slave_write_request;
wire slave_write_request_sync;
wire slave_write_request_token;
reg [ 15: 0] slave_writedata_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
//in, which is an e_avalon_slave
//out, which is an e_avalon_master
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (slave_clk),
.din (master_read_done),
.dout (master_read_done_sync),
.reset_n (slave_reset_n)
);
defparam the_altera_std_synchronizer.depth = 2;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (slave_clk),
.din (master_write_done),
.dout (master_write_done_sync),
.reset_n (slave_reset_n)
);
defparam the_altera_std_synchronizer1.depth = 2;
//read_done_edge_to_pulse, which is an e_instance
kernel_clock_0_edge_to_pulse read_done_edge_to_pulse
(
.clock (slave_clk),
.data_in (master_read_done_sync),
.data_out (master_read_done_token),
.reset_n (slave_reset_n)
);
//write_done_edge_to_pulse, which is an e_instance
kernel_clock_0_edge_to_pulse write_done_edge_to_pulse
(
.clock (slave_clk),
.data_in (master_write_done_sync),
.data_out (master_write_done_token),
.reset_n (slave_reset_n)
);
//slave_FSM, which is an e_instance
kernel_clock_0_slave_FSM slave_FSM
(
.master_read_done_token (master_read_done_token),
.master_write_done_token (master_write_done_token),
.slave_clk (slave_clk),
.slave_read (slave_read),
.slave_read_request (slave_read_request),
.slave_reset_n (slave_reset_n),
.slave_waitrequest (slave_waitrequest),
.slave_write (slave_write),
.slave_write_request (slave_write_request)
);
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (master_clk),
.din (slave_read_request),
.dout (slave_read_request_sync),
.reset_n (master_reset_n)
);
defparam the_altera_std_synchronizer2.depth = 2;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (master_clk),
.din (slave_write_request),
.dout (slave_write_request_sync),
.reset_n (master_reset_n)
);
defparam the_altera_std_synchronizer3.depth = 2;
//read_request_edge_to_pulse, which is an e_instance
kernel_clock_0_edge_to_pulse read_request_edge_to_pulse
(
.clock (master_clk),
.data_in (slave_read_request_sync),
.data_out (slave_read_request_token),
.reset_n (master_reset_n)
);
//write_request_edge_to_pulse, which is an e_instance
kernel_clock_0_edge_to_pulse write_request_edge_to_pulse
(
.clock (master_clk),
.data_in (slave_write_request_sync),
.data_out (slave_write_request_token),
.reset_n (master_reset_n)
);
//master_FSM, which is an e_instance
kernel_clock_0_master_FSM master_FSM
(
.master_clk (master_clk),
.master_read (master_read),
.master_read_done (master_read_done),
.master_reset_n (master_reset_n),
.master_waitrequest (master_waitrequest),
.master_write (master_write),
.master_write_done (master_write_done),
.slave_read_request_token (slave_read_request_token),
.slave_write_request_token (slave_write_request_token)
);
//endofpacket_bit_pipe, which is an e_instance
kernel_clock_0_bit_pipe endofpacket_bit_pipe
(
.clk1 (slave_clk),
.clk2 (master_clk),
.data_in (master_endofpacket),
.data_out (slave_endofpacket),
.reset_clk1_n (slave_reset_n),
.reset_clk2_n (master_reset_n)
);
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
slave_readdata_p1 <= 0;
else if (master_read & ~master_waitrequest)
slave_readdata_p1 <= master_readdata;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_readdata <= 0;
else
slave_readdata <= slave_readdata_p1;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_writedata_d1 <= 0;
else
slave_writedata_d1 <= slave_writedata;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_writedata <= 0;
else
master_writedata <= slave_writedata_d1;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_address_d1 <= 0;
else
slave_address_d1 <= slave_address;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_address <= 0;
else
master_address <= slave_address_d1;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_nativeaddress_d1 <= 0;
else
slave_nativeaddress_d1 <= slave_nativeaddress;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_nativeaddress <= 0;
else
master_nativeaddress <= slave_nativeaddress_d1;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_byteenable_d1 <= 0;
else
slave_byteenable_d1 <= slave_byteenable;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_byteenable <= 0;
else
master_byteenable <= slave_byteenable_d1;
end
endmodule
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module spw_babasu_AUTOSTART (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/*
This SDRAM controller is for the Mojo's SDRAM shield which uses
a 48LC32M8A2-7E SDRAM chip. This module was designed under the
assumption that the click rate is 100MHz. Timing values would
need to be re-evaluated under different clock rates.
This controller features two baisc improvements over the most
basic of controllers. It does burst reads and writes of 4 bytes,
and it only closes a row when it has to.
*/
module sdram (
input clk,
input rst,
// these signals go directly to the IO pins
output sdram_clk,
output sdram_cle,
output sdram_cs,
output sdram_cas,
output sdram_ras,
output sdram_we,
output sdram_dqm,
output [1:0] sdram_ba,
output [12:0] sdram_a,
inout [7:0] sdram_dq,
// User interface
input [22:0] addr, // address to read/write
input rw, // 1 = write, 0 = read
input [31:0] data_in, // data from a read
output [31:0] data_out, // data for a write
output busy, // controller is busy when high
input in_valid, // pulse high to initiate a read/write
output out_valid // pulses high when data from read is valid
);
// Commands for the SDRAM
localparam CMD_UNSELECTED = 4'b1000;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE_REG = 4'b0000;
localparam STATE_SIZE = 4;
localparam INIT = 0,
WAIT = 1,
PRECHARGE_INIT = 2,
REFRESH_INIT_1 = 3,
REFRESH_INIT_2 = 4,
LOAD_MODE_REG = 5,
IDLE = 6,
REFRESH = 7,
ACTIVATE = 8,
READ = 9,
READ_RES = 10,
WRITE = 11,
PRECHARGE = 12;
wire sdram_clk_ddr;
// This is used to drive the SDRAM clock
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR2_inst (
.Q(sdram_clk_ddr), // 1-bit DDR output data
.C0(clk), // 1-bit clock input
.C1(~clk), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b0), // 1-bit data input (associated with C0)
.D1(1'b1), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
IODELAY2 #(
.IDELAY_VALUE(0),
.IDELAY_MODE("NORMAL"),
.ODELAY_VALUE(50), // value of 100 seems to work at 100MHz
.IDELAY_TYPE("FIXED"),
.DELAY_SRC("ODATAIN"),
.DATA_RATE("SDR")
) IODELAY_inst (
.IDATAIN(1'b0),
.T(1'b0),
.ODATAIN(sdram_clk_ddr),
.CAL(1'b0),
.IOCLK0(1'b0),
.IOCLK1(1'b0),
.CLK(1'b0),
.INC(1'b0),
.CE(1'b0),
.RST(1'b0),
.BUSY(),
.DATAOUT(),
.DATAOUT2(),
.TOUT(),
.DOUT(sdram_clk)
);
// registers for SDRAM signals
reg cle_d, dqm_d;
reg [3:0] cmd_d;
reg [1:0] ba_d;
reg [12:0] a_d;
reg [7:0] dq_d;
reg [7:0] dqi_d;
// We want the output/input registers to be embedded in the
// IO buffers so we set IOB to "TRUE". This is to ensure all
// the signals are sent and received at the same time.
(* IOB = "TRUE" *)
reg cle_q, dqm_q;
(* IOB = "TRUE" *)
reg [3:0] cmd_q;
(* IOB = "TRUE" *)
reg [1:0] ba_q;
(* IOB = "TRUE" *)
reg [12:0] a_q;
(* IOB = "TRUE" *)
reg [7:0] dq_q;
(* IOB = "TRUE" *)
reg [7:0] dqi_q;
reg dq_en_d, dq_en_q;
// Output assignments
assign sdram_cle = cle_q;
assign sdram_cs = cmd_q[3];
assign sdram_ras = cmd_q[2];
assign sdram_cas = cmd_q[1];
assign sdram_we = cmd_q[0];
assign sdram_dqm = dqm_q;
assign sdram_ba = ba_q;
assign sdram_a = a_q;
assign sdram_dq = dq_en_q ? dq_q : 8'hZZ; // only drive when dq_en_q is 1
reg [STATE_SIZE-1:0] state_d, state_q = INIT;
reg [STATE_SIZE-1:0] next_state_d, next_state_q;
reg [22:0] addr_d, addr_q;
reg [31:0] data_d, data_q;
reg out_valid_d, out_valid_q;
assign data_out = data_q;
assign busy = !ready_q;
assign out_valid = out_valid_q;
reg [15:0] delay_ctr_d, delay_ctr_q;
reg [1:0] byte_ctr_d, byte_ctr_q;
reg [9:0] refresh_ctr_d, refresh_ctr_q;
reg refresh_flag_d, refresh_flag_q;
reg ready_d, ready_q;
reg saved_rw_d, saved_rw_q;
reg [22:0] saved_addr_d, saved_addr_q;
reg [31:0] saved_data_d, saved_data_q;
reg rw_op_d, rw_op_q;
reg [3:0] row_open_d, row_open_q;
reg [12:0] row_addr_d[3:0], row_addr_q[3:0];
reg [2:0] precharge_bank_d, precharge_bank_q;
integer i;
always @* begin
// Default values
dq_d = dq_q;
dqi_d = sdram_dq;
dq_en_d = 1'b0; // normally keep the bus in high-Z
cle_d = cle_q;
cmd_d = CMD_NOP; // default to NOP
dqm_d = 1'b0;
ba_d = 2'd0;
a_d = 25'd0;
state_d = state_q;
next_state_d = next_state_q;
delay_ctr_d = delay_ctr_q;
addr_d = addr_q;
data_d = data_q;
out_valid_d = 1'b0;
precharge_bank_d = precharge_bank_q;
rw_op_d = rw_op_q;
byte_ctr_d = 2'd0;
row_open_d = row_open_q;
// row_addr is a 2d array and must be coppied this way
for (i = 0; i < 4; i = i + 1)
row_addr_d[i] = row_addr_q[i];
// The data in the SDRAM must be refreshed periodically.
// This conter ensures that the data remains intact.
refresh_flag_d = refresh_flag_q;
refresh_ctr_d = refresh_ctr_q + 1'b1;
if (refresh_ctr_q > 10'd750) begin
refresh_ctr_d = 10'd0;
refresh_flag_d = 1'b1;
end
saved_rw_d = saved_rw_q;
saved_data_d = saved_data_q;
saved_addr_d = saved_addr_q;
ready_d = ready_q;
// This is a queue of 1 for read/write operations.
// When the queue is empty we aren't busy and can
// accept another request.
if (ready_q && in_valid) begin
saved_rw_d = rw;
saved_data_d = data_in;
saved_addr_d = addr;
ready_d = 1'b0;
end
case (state_q)
///// INITALIZATION /////
INIT: begin
ready_d = 1'b0;
row_open_d = 4'b0;
out_valid_d = 1'b0;
a_d = 13'b0;
ba_d = 2'b0;
cle_d = 1'b1;
state_d = WAIT;
delay_ctr_d = 16'd10100; // wait for 101us
next_state_d = PRECHARGE_INIT;
dq_en_d = 1'b0;
end
WAIT: begin
delay_ctr_d = delay_ctr_q - 1'b1;
if (delay_ctr_q == 13'd0) begin
state_d = next_state_q;
if (next_state_q == WRITE) begin
dq_en_d = 1'b1; // enable the bus early
dq_d = data_q[7:0];
end
end
end
PRECHARGE_INIT: begin
cmd_d = CMD_PRECHARGE;
a_d[10] = 1'b1; // all banks
ba_d = 2'd0;
state_d = WAIT;
next_state_d = REFRESH_INIT_1;
delay_ctr_d = 13'd0;
end
REFRESH_INIT_1: begin
cmd_d = CMD_REFRESH;
state_d = WAIT;
delay_ctr_d = 13'd7;
next_state_d = REFRESH_INIT_2;
end
REFRESH_INIT_2: begin
cmd_d = CMD_REFRESH;
state_d = WAIT;
delay_ctr_d = 13'd7;
next_state_d = LOAD_MODE_REG;
end
LOAD_MODE_REG: begin
cmd_d = CMD_LOAD_MODE_REG;
ba_d = 2'b0;
// Reserved, Burst Access, Standard Op, CAS = 2, Sequential, Burst = 4
a_d = {3'b000, 1'b0, 2'b00, 3'b010, 1'b0, 3'b010}; //010
state_d = WAIT;
delay_ctr_d = 13'd1;
next_state_d = IDLE;
refresh_flag_d = 1'b0;
refresh_ctr_d = 10'b1;
ready_d = 1'b1;
end
///// IDLE STATE /////
IDLE: begin
if (refresh_flag_q) begin // we need to do a refresh
state_d = PRECHARGE;
next_state_d = REFRESH;
precharge_bank_d = 3'b100; // all banks
refresh_flag_d = 1'b0; // clear the refresh flag
end else if (!ready_q) begin // operation waiting
ready_d = 1'b1; // clear the queue
rw_op_d = saved_rw_q; // save the values we'll need later
addr_d = saved_addr_q;
if (saved_rw_q) // Write
data_d = saved_data_q;
// if the row is open we don't have to activate it
if (row_open_q[saved_addr_q[9:8]]) begin
if (row_addr_q[saved_addr_q[9:8]] == saved_addr_q[22:10]) begin
// Row is already open
if (saved_rw_q)
state_d = WRITE;
else
state_d = READ;
end else begin
// A different row in the bank is open
state_d = PRECHARGE; // precharge open row
precharge_bank_d = {1'b0, saved_addr_q[9:8]};
next_state_d = ACTIVATE; // open current row
end
end else begin
// no rows open
state_d = ACTIVATE; // open the row
end
end
end
///// REFRESH /////
REFRESH: begin
cmd_d = CMD_REFRESH;
state_d = WAIT;
delay_ctr_d = 13'd6; // gotta wait 7 clocks (66ns)
next_state_d = IDLE;
end
///// ACTIVATE /////
ACTIVATE: begin
cmd_d = CMD_ACTIVE;
a_d = addr_q[22:10];
ba_d = addr_q[9:8];
delay_ctr_d = 13'd0;
state_d = WAIT;
if (rw_op_q)
next_state_d = WRITE;
else
next_state_d = READ;
row_open_d[addr_q[9:8]] = 1'b1; // row is now open
row_addr_d[addr_q[9:8]] = addr_q[22:10];
end
///// READ /////
READ: begin
cmd_d = CMD_READ;
a_d = {2'b0, 1'b0, addr_q[7:0], 2'b0};
ba_d = addr_q[9:8];
state_d = WAIT;
delay_ctr_d = 13'd2; // wait for the data to show up
next_state_d = READ_RES;
end
READ_RES: begin
byte_ctr_d = byte_ctr_q + 1'b1; // we need to read in 4 bytes
data_d = {dqi_q, data_q[31:8]}; // shift the data in
if (byte_ctr_q == 2'd3) begin
out_valid_d = 1'b1;
state_d = IDLE;
end
end
///// WRITE /////
WRITE: begin
byte_ctr_d = byte_ctr_q + 1'b1; // send out 4 bytes
if (byte_ctr_q == 2'd0) // first byte send write command
cmd_d = CMD_WRITE;
dq_d = data_q[7:0];
data_d = {8'h00, data_q[31:8]}; // shift the data out
dq_en_d = 1'b1; // enable out bus
a_d = {2'b0, 1'b0, addr_q[7:0], 2'b00};
ba_d = addr_q[9:8];
if (byte_ctr_q == 2'd3) begin
state_d = IDLE;
end
end
///// PRECHARGE /////
PRECHARGE: begin
cmd_d = CMD_PRECHARGE;
a_d[10] = precharge_bank_q[2]; // all banks
ba_d = precharge_bank_q[1:0];
state_d = WAIT;
delay_ctr_d = 13'd0;
if (precharge_bank_q[2]) begin
row_open_d = 4'b0000; // closed all rows
end else begin
row_open_d[precharge_bank_q[1:0]] = 1'b0; // closed one row
end
end
default: state_d = INIT;
endcase
end
always @(posedge clk) begin
if(rst) begin
cle_q <= 1'b0;
dq_en_q <= 1'b0;
state_q <= INIT;
ready_q <= 1'b0;
end else begin
cle_q <= cle_d;
dq_en_q <= dq_en_d;
state_q <= state_d;
ready_q <= ready_d;
end
saved_rw_q <= saved_rw_d;
saved_data_q <= saved_data_d;
saved_addr_q <= saved_addr_d;
cmd_q <= cmd_d;
dqm_q <= dqm_d;
ba_q <= ba_d;
a_q <= a_d;
dq_q <= dq_d;
dqi_q <= dqi_d;
next_state_q <= next_state_d;
refresh_flag_q <= refresh_flag_d;
refresh_ctr_q <= refresh_ctr_d;
data_q <= data_d;
addr_q <= addr_d;
out_valid_q <= out_valid_d;
row_open_q <= row_open_d;
for (i = 0; i < 4; i = i + 1)
row_addr_q[i] <= row_addr_d[i];
precharge_bank_q <= precharge_bank_d;
rw_op_q <= rw_op_d;
byte_ctr_q <= byte_ctr_d;
delay_ctr_q <= delay_ctr_d;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFBUF_PP_SYMBOL_V
`define SKY130_FD_SC_HD__BUFBUF_PP_SYMBOL_V
/**
* bufbuf: Double buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__bufbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFBUF_PP_SYMBOL_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "block" *) module Loop_loop_height_dEe_rom (
addr0, ce0, q0, addr1, ce1, q1, addr2, ce2, q2, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input[AWIDTH-1:0] addr2;
input ce2;
output reg[DWIDTH-1:0] q2;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_dEe_rom.dat", ram0);
$readmemh("./Loop_loop_height_dEe_rom.dat", ram1);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram0[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram0[addr1];
end
end
always @(posedge clk)
begin
if (ce2)
begin
q2 <= ram1[addr2];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_dEe(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
input[AddressWidth - 1:0] address2;
input ce2;
output[DataWidth - 1:0] q2;
Loop_loop_height_dEe_rom Loop_loop_height_dEe_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ),
.addr2( address2 ),
.ce2( ce2 ),
.q2( q2 ));
endmodule
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs.
As of Coq 8.4 [admit] is in the standard library, but we include
it here for backwards compatibility.
*)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
mathematics: If a procedure or method has no side effects, then
pretty much all you need to understand about it is how it maps
inputs to outputs -- that is, you can think of its behavior as
just computing a mathematical function. This is one reason for
the word "functional" in "functional programming." This direct
connection between programs and simple mathematical objects
supports both sound informal reasoning and formal proofs of
correctness.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful idioms, as we will see.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code.
To see how this works, let's start with a very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second through eighth lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters.
More information can also be found in the Coq'Art book by Bertot
and Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] will automatically perform
simplification.) *)
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
match b1 with
| false => true
| true => negb b2
end.
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
match (b1, b2, b3) with
| (true, true, true) => true
| (_, _, _) => false
end.
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => S O
| S n' => mult n (factorial n')
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Optional Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition blt_nat (n m : nat) : bool :=
match (ble_nat n m) with
| false => false
| true => negb (beq_nat n m)
end.
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** Step through these proofs in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o.
intros H1.
intros H2.
rewrite -> H1.
rewrite <- H2.
reflexivity.
Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m.
intros H1.
simpl.
rewrite <- H1.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n.
destruct n.
reflexivity.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f Hf b.
rewrite -> Hf.
rewrite -> Hf.
reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f Hf b.
rewrite -> Hf.
rewrite -> Hf.
rewrite -> negb_involutive.
reflexivity.
Qed.
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Lemma andb_eq_true_r:
forall (a b : bool),
(andb a b = true) ->
b = true.
Proof.
intros a b.
destruct a.
simpl. intros H1. rewrite -> H1. reflexivity.
simpl. intros H2. destruct b. reflexivity. rewrite -> H2. reflexivity.
Qed.
Lemma andb_eq_true_l:
forall (a b : bool),
(andb a b = true) ->
a = true.
Proof.
intros a b.
destruct a.
reflexivity.
simpl. intros H1. rewrite -> H1. reflexivity.
Qed.
Lemma orb_eq_false_l:
forall (a b : bool),
(orb a b = false) ->
a = false.
Proof.
intros a b.
destruct a.
simpl. intros H. rewrite -> H. reflexivity.
reflexivity.
Qed.
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c.
destruct b.
simpl. intros H1. rewrite -> H1. reflexivity.
simpl. intros H2. rewrite -> H2. reflexivity.
Qed.
Lemma orb_true_eq_true_r:
forall (a : bool),
orb a true = true.
Proof.
intros a. destruct a. reflexivity. reflexivity. Qed.
Lemma orb_true_eq_true_l:
forall (b : bool),
orb true b = true.
Proof.
reflexivity. Qed.
Lemma andb_false_eq_false_r:
forall (a : bool),
andb a false = false.
Proof.
intros a. destruct a. reflexivity. reflexivity. Qed.
Lemma andb_false_eq_false_l:
forall (b : bool),
andb false b = false.
Proof.
reflexivity. Qed.
Theorem andb_eq_orb2 :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c.
destruct c.
rewrite -> orb_true_eq_true_r. destruct b. reflexivity. simpl. intro H. rewrite -> H. reflexivity.
rewrite -> andb_false_eq_false_r. destruct b. simpl. intro H. rewrite -> H. reflexivity. reflexivity.
Qed.
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Write some unit tests for your increment and binary-to-unary
functions. Notice that incrementing a binary number and
then converting it to unary should yield the same result as first
converting it to unary and then incrementing.
*)
Inductive bin : Type :=
| O : bin
| D : bin -> bin
| DS : bin -> bin.
Fixpoint bincr (b : bin) : bin :=
match b with
| O => DS O
| D b' => DS b'
| DS b' => D (bincr b')
end.
Fixpoint bin_to_nat (b : bin) : nat :=
match b with
| O => 0
| D b' => mult 2 (bin_to_nat b')
| DS b' => 1 + (mult 2 (bin_to_nat b'))
end.
Example test_bin_to_nat1: bin_to_nat O = 0.
Proof. reflexivity. Qed.
Example test_bin_to_nat2: bin_to_nat (bincr O) = 1.
Proof. reflexivity. Qed.
Example test_bin_to_nat3: bin_to_nat (bincr (bincr O)) = 2.
Proof. reflexivity. Qed.
Example test_bin_to_nat4: bin_to_nat (bincr (bincr (bincr O))) = 3.
Proof. reflexivity. Qed.
Example test_bin_to_nat5: bin_to_nat (bincr (bincr (bincr (bincr O)))) = 4.
Proof. reflexivity. Qed.
Example test_bin_to_nat6: bin_to_nat (bincr (bincr (bincr (bincr (bincr O))))) = 5.
Proof. reflexivity. Qed.
Fixpoint nat_to_bin (n : nat) : bin :=
match n with
| 0 => O
| S n' => bincr (nat_to_bin n')
end.
Example test_nat_to_bin1: bin_to_nat (nat_to_bin 9) = 9.
Proof. reflexivity. Qed.
Example test_nat_to_bin2: bin_to_nat (nat_to_bin 631) = 631.
Proof. reflexivity. Qed.
Example test_bin_to_nat7: bin_to_nat (bincr (nat_to_bin 783)) = 784.
Proof. reflexivity. Qed.
(* Theorem bincr_eq_nat_plus_1:
forall (b : bin),
forall (n : nat),
bin_to_nat b = n ->
(bin_to_nat (bincr b) = 1 + n).
Proof.
intros b n.
destruct b.
simpl. intros H. rewrite -> H. reflexivity.
simpl. intros H. rewrite -> H. reflexivity.
admit. *)
(* I think I haven't learnt enough tools to prove yet! *)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * Optional Material *)
(** ** More on Notation *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** ** [Fixpoint]s and Structural Recursion *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| 0 => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
Fixpoint nat_even (n : nat) : bool :=
match n with
| 0 => true
| S n' => negb (nat_even n')
end.
Example test_nat_even1: nat_even 131 = false.
Proof. reflexivity. Qed.
Example test_nat_even2: nat_even 8 = true.
Proof. reflexivity. Qed.
(* function doesn't really make sense but it doesn't pass the coq
coq reucrsion check as on one branch we recurse small when the
nat is even, on the other we make it even and then recurse.
This relies on a more semantic understanding on nat (or at least
bringing in the definition of nat_even) which is beyond the simple
check. *)
(* Fixpoint nat_bad_fix (n : nat) : nat :=
match (nat_even n, n) with
| (_, 0) => 0
| (true, S n') => nat_bad_fix n'
| (false, S n') => nat_bad_fix (S (S n'))
end. *)
(** [] *)
(* $Date: 2013-12-03 07:45:41 -0500 (Tue, 03 Dec 2013) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_TB_V
`define SKY130_FD_SC_HD__NOR4B_TB_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor4b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hd__nor4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_TB_V
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module neo_i0(
// OR, AND gate and sync inverter are kept in neogeo.v
input nRESET,
input nCOUNTOUT,
input [3:1] M68K_ADDR,
input M68K_ADDR_7,
output reg COUNTER1,
output reg COUNTER2,
output reg LOCKOUT1,
output reg LOCKOUT2,
input [15:0] PBUS,
input PCK2B,
output reg [15:0] G
);
always @(posedge PCK2B)
G <= {PBUS[11:0], PBUS[15:12]};
// A7=Counter/lockout data
// A1=1/2
// A2=Counter/lockout
always @(nCOUNTOUT, nRESET)
begin
if (!nRESET)
begin
COUNTER1 <= 1'b0;
COUNTER2 <= 1'b0;
LOCKOUT1 <= 1'b0;
LOCKOUT2 <= 1'b0;
end
else
begin
if (!nCOUNTOUT)
begin
// DEBUG
if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b0000)
$display("COIN COUNTER 1 RESET");
else if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b0001)
$display("COIN COUNTER 2 RESET");
else if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b0010)
$display("COIN LOCKOUT 1 RESET");
else if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b0011)
$display("COIN LOCKOUT 2 RESET");
else if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b1000)
$display("COIN COUNTER 1 SET");
else if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b1001)
$display("COIN COUNTER 2 SET");
else if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b1010)
$display("COIN LOCKOUT 1 SET");
else if ({M68K_ADDR_7, M68K_ADDR[3:1]} == 4'b1011)
$display("COIN LOCKOUT 2 SET");
if (M68K_ADDR[3:1] == 3'b000) COUNTER1 <= M68K_ADDR_7;
if (M68K_ADDR[3:1] == 3'b001) COUNTER2 <= M68K_ADDR_7;
if (M68K_ADDR[3:1] == 3'b010) LOCKOUT1 <= M68K_ADDR_7;
if (M68K_ADDR[3:1] == 3'b011) LOCKOUT2 <= M68K_ADDR_7;
end
end
end
endmodule
|
`timescale 1 ps / 1 ps
module alt_mem_ddrx_controller #
( parameter
// Local interface parameters
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_LOCAL_DATA_WIDTH = 80, // Maximum DQ width of 40
CFG_LOCAL_ID_WIDTH = 8,
CFG_LOCAL_IF_TYPE = "AVALON",
// Memory interface parameters
CFG_MEM_IF_CHIP = 2,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 15,
CFG_MEM_IF_COL_WIDTH = 12,
CFG_MEM_IF_ADDR_WIDTH = 15,
CFG_MEM_IF_CKE_WIDTH = 2,
CFG_MEM_IF_ODT_WIDTH = 2,
CFG_MEM_IF_CLK_PAIR_COUNT = 2,
CFG_MEM_IF_DQ_WIDTH = 40,
CFG_MEM_IF_DQS_WIDTH = 5,
CFG_MEM_IF_DM_WIDTH = 5,
// Controller parameters
CFG_DWIDTH_RATIO = 2,
CFG_ODT_ENABLED = 1, // NOTICE: required?
CFG_OUTPUT_REGD = 0, // NOTICE: un-used and will be removed
CFG_CTL_TBP_NUM = 4,
CFG_LPDDR2_ENABLED = 0,
CFG_DATA_REORDERING_TYPE = "INTER_BANK",
CFG_ECC_MULTIPLES_16_24_40_72 = 1,
// Data path buffer & fifo parameters
CFG_WRBUFFER_ADDR_WIDTH = 6,
CFG_RDBUFFER_ADDR_WIDTH = 10,
CFG_MAX_PENDING_RD_CMD = 16,
CFG_MAX_PENDING_WR_CMD = 8,
// MMR port width
// cfg: general
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_DEVICE_WIDTH = 4,
CFG_PORT_WIDTH_OUTPUT_REGD = 2,
// cfg: address mapping signals
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 3,
// cfg: timing parameters
CFG_PORT_WIDTH_CAS_WR_LAT = 4, // max will be 8 in DDR3
CFG_PORT_WIDTH_ADD_LAT = 3, // max will be 10 in DDR3
CFG_PORT_WIDTH_TCL = 4, // max will be 11 in DDR3
CFG_PORT_WIDTH_TRRD = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TFAW = 6, // 6 - 32 enough?
CFG_PORT_WIDTH_TRFC = 8, // 12-140 enough?
CFG_PORT_WIDTH_TREFI = 13, // 780 - 6240 enough?
CFG_PORT_WIDTH_TRCD = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TRP = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TWR = 4, // 2 - 12 enough?
CFG_PORT_WIDTH_TWTR = 4, // 1 - 10 enough?
CFG_PORT_WIDTH_TRTP = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TRAS = 5, // 4 - 29 enough?
CFG_PORT_WIDTH_TRC = 6, // 8 - 40 enough?
CFG_PORT_WIDTH_TCCD = 4, // max will be 8 in DDR3
CFG_PORT_WIDTH_TMRD = 3, // 4 - ? enough?
CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10, // max will be 512 in DDR3
CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4, // 3 - ? enough?
CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16, // enough?
CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES = 4, // enough?
CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES = 4, // enough?
// cfg: extra timing parameters
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 4,
// cfg: control signals
CFG_PORT_WIDTH_REORDER_DATA = 1,
CFG_PORT_WIDTH_STARVE_LIMIT = 6,
CFG_PORT_WIDTH_USER_RFSH = 1,
CFG_PORT_WIDTH_SELF_RFSH = 1,
CFG_PORT_WIDTH_REGDIMM_ENABLE = 1,
CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT = 1,
CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE = 1,
CFG_ENABLE_CMD_SPLIT = 1'b1, // disable this (set to 0) when using the controller with hard MPFE
CFG_ENABLE_WDATA_PATH_LATENCY = 0,
// cfg: ecc signals
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
CFG_PORT_WIDTH_GEN_SBE = 1,
CFG_PORT_WIDTH_GEN_DBE = 1,
CFG_PORT_WIDTH_ENABLE_INTR = 1,
CFG_PORT_WIDTH_MASK_SBE_INTR = 1,
CFG_PORT_WIDTH_MASK_DBE_INTR = 1,
CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1,
CFG_PORT_WIDTH_CLR_INTR = 1,
CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES = 1,
CFG_PORT_WIDTH_ENABLE_NO_DM = 1,
CFG_ECC_DECODER_REG = 1,
// cfg: odt
CFG_PORT_WIDTH_WRITE_ODT_CHIP = 4,
CFG_PORT_WIDTH_READ_ODT_CHIP = 4,
// cfg: ecc signals
STS_PORT_WIDTH_SBE_ERROR = 1,
STS_PORT_WIDTH_DBE_ERROR = 1,
STS_PORT_WIDTH_CORR_DROP_ERROR = 1,
STS_PORT_WIDTH_SBE_COUNT = 8,
STS_PORT_WIDTH_DBE_COUNT = 8,
STS_PORT_WIDTH_CORR_DROP_COUNT = 8,
// PHY parameters
CFG_WLAT_BUS_WIDTH = 4,
CFG_RRANK_BUS_WIDTH = 1,
CFG_WRANK_BUS_WIDTH = 1,
CFG_USE_SHADOW_REGS = 0,
// controller read data return mode
CFG_RDATA_RETURN_MODE = "PASSTHROUGH",
CFG_ERRCMD_FIFO_REG = 0,
CFG_ENABLE_BURST_MERGE = 0
)
(
// Clock and reset
ctl_clk,
ctl_reset_n,
// Command channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// Write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// Read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
itf_rd_data_id_early, // only valid when CFG_RDATA_RETURN_MODE == PASSTHROUGH
itf_rd_data_id_early_valid, // only valid when CFG_RDATA_RETURN_MODE == PASSTHROUGH
// Sideband signals
local_refresh_req,
local_refresh_chip,
local_zqcal_req,
local_zqcal_chip,
local_deep_powerdn_chip,
local_deep_powerdn_req,
local_self_rfsh_req,
local_self_rfsh_chip,
local_refresh_ack,
local_deep_powerdn_ack,
local_power_down_ack,
local_self_rfsh_ack,
local_init_done,
// Controller commands to the AFI interface
afi_rst_n,
afi_ba,
afi_addr,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_odt,
// Controller read and write data to the AFI interface
afi_wlat,
afi_dqs_burst,
afi_dm,
afi_wdata,
afi_wdata_valid,
afi_rdata_en,
afi_rdata_en_full,
afi_rrank,
afi_wrank,
afi_rdata,
afi_rdata_valid,
// Status and control signal to the AFI interface
ctl_cal_success,
ctl_cal_fail,
ctl_cal_req,
ctl_init_req,
ctl_mem_clk_disable,
ctl_cal_byte_lane_sel_n,
// cfg: general
cfg_type,
cfg_interface_width, // not sure where this signal is used
cfg_burst_length,
cfg_device_width, // not sure where this signal is used
cfg_output_regd,
// cfg: address mapping signals
cfg_addr_order,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width,
// cfg: timing parameters
cfg_cas_wr_lat,
cfg_add_lat,
cfg_tcl,
cfg_trrd,
cfg_tfaw,
cfg_trfc,
cfg_trefi,
cfg_trcd,
cfg_trp,
cfg_twr,
cfg_twtr,
cfg_trtp,
cfg_tras,
cfg_trc,
cfg_tccd,
cfg_auto_pd_cycles,
cfg_self_rfsh_exit_cycles,
cfg_pdn_exit_cycles,
cfg_power_saving_exit_cycles,
cfg_mem_clk_entry_cycles,
cfg_tmrd,
// cfg: extra timing parameters
cfg_extra_ctl_clk_act_to_rdwr,
cfg_extra_ctl_clk_act_to_pch,
cfg_extra_ctl_clk_act_to_act,
cfg_extra_ctl_clk_rd_to_rd,
cfg_extra_ctl_clk_rd_to_rd_diff_chip,
cfg_extra_ctl_clk_rd_to_wr,
cfg_extra_ctl_clk_rd_to_wr_bc,
cfg_extra_ctl_clk_rd_to_wr_diff_chip,
cfg_extra_ctl_clk_rd_to_pch,
cfg_extra_ctl_clk_rd_ap_to_valid,
cfg_extra_ctl_clk_wr_to_wr,
cfg_extra_ctl_clk_wr_to_wr_diff_chip,
cfg_extra_ctl_clk_wr_to_rd,
cfg_extra_ctl_clk_wr_to_rd_bc,
cfg_extra_ctl_clk_wr_to_rd_diff_chip,
cfg_extra_ctl_clk_wr_to_pch,
cfg_extra_ctl_clk_wr_ap_to_valid,
cfg_extra_ctl_clk_pch_to_valid,
cfg_extra_ctl_clk_pch_all_to_valid,
cfg_extra_ctl_clk_act_to_act_diff_bank,
cfg_extra_ctl_clk_four_act_to_act,
cfg_extra_ctl_clk_arf_to_valid,
cfg_extra_ctl_clk_pdn_to_valid,
cfg_extra_ctl_clk_srf_to_valid,
cfg_extra_ctl_clk_srf_to_zq_cal,
cfg_extra_ctl_clk_arf_period,
cfg_extra_ctl_clk_pdn_period,
// cfg: control signals
cfg_reorder_data, // enable data reordering
cfg_starve_limit, // starvation counter limit
cfg_user_rfsh,
cfg_regdimm_enable,
cfg_enable_burst_interrupt,
cfg_enable_burst_terminate,
// cfg: ecc signals
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_ecc_code_overwrites,
cfg_enable_no_dm,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
// cfg: odt
cfg_write_odt_chip,
cfg_read_odt_chip,
// sts: ecc signals
ecc_interrupt,
sts_sbe_error,
sts_dbe_error,
sts_corr_dropped,
sts_sbe_count,
sts_dbe_count,
sts_corr_dropped_count,
sts_err_addr,
sts_corr_dropped_addr,
//calibration
cfg_cal_req,
sts_cal_fail,
sts_cal_success,
// DQS enable tracking
cfg_enable_dqs_tracking, //enable DQS enable tracking support in controller
afi_ctl_refresh_done, // Controller asserts this after tRFC is done, also acts as stall ack to phy
afi_seq_busy, // Sequencer busy signal to controller, also acts as stall request to ctlr
afi_ctl_long_idle, // Controller asserts this after long period of no refresh, protocol is the same as rfsh_done
// Refresh controller
tbp_empty,
cmd_gen_busy,
sideband_in_refresh
);
// General parameters
localparam CFG_ECC_BE_ALLLOW_RMW = 0;
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_INT_SIZE_WIDTH = (CFG_DWIDTH_RATIO == 2) ? 4 : ((CFG_DWIDTH_RATIO == 4) ? 3 : ((CFG_DWIDTH_RATIO == 8) ? 2 : 4));
localparam CFG_CTL_QUEUE_DEPTH = 8;
localparam CFG_ENABLE_QUEUE = 0;
//localparam CFG_ENABLE_BURST_MERGE = 0;
localparam CFG_CMD_GEN_OUTPUT_REG = 1; // only in effect when CFG_ENABLE_QUEUE is set to '0'
localparam CFG_CTL_ARBITER_TYPE = "ROWCOL";
localparam CFG_AFI_INTF_PHASE_NUM = 2;
localparam CFG_ECC_DATA_WIDTH = CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO;
localparam CFG_ECC_DM_WIDTH = CFG_ECC_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_ECC_CODE_WIDTH = 8;
localparam CFG_ECC_MULTIPLES = CFG_DWIDTH_RATIO * CFG_ECC_MULTIPLES_16_24_40_72;
localparam CFG_PARTIAL_BE_PER_WORD_ENABLE = 1;
localparam CFG_ENABLE_BURST_GEN_OUTPUT_REG = 1;
localparam CFG_DISABLE_PRIORITY = 1;
localparam CFG_REG_GRANT = (CFG_DWIDTH_RATIO == 8) ? 0 : 1; // disable grant register for better efficiency in quarter rate
localparam CFG_REG_REQ = 0;
localparam CFG_RANK_TIMER_OUTPUT_REG = 1;
localparam CFG_ECC_DEC_REG = 1;
localparam CFG_ECC_RDATA_REG = 1;
localparam CFG_ECC_ENC_REG = 1;
localparam CFG_WDATA_REG = CFG_ENABLE_WDATA_PATH_LATENCY;
localparam CFG_DISABLE_READ_REODERING = 0;
localparam CFG_ENABLE_SHADOW_TBP = 0;
localparam CFG_CTL_SHADOW_TBP_NUM = CFG_CTL_TBP_NUM; // similar to TBP number
// Datapath buffer & fifo size calculation
localparam CFG_MAX_PENDING_ERR_CMD = 8; // temporary
localparam CFG_MAX_PENDING_RD_CMD_WIDTH = log2(CFG_MAX_PENDING_RD_CMD);
localparam CFG_WRDATA_ID_WIDTH = log2(CFG_MAX_PENDING_WR_CMD);
localparam CFG_ERRCMD_FIFO_ADDR_WIDTH = log2(CFG_MAX_PENDING_ERR_CMD);
localparam CFG_RDDATA_ID_WIDTH = CFG_RDBUFFER_ADDR_WIDTH - CFG_INT_SIZE_WIDTH;
localparam CFG_DATA_ID_WIDTH = (CFG_WRDATA_ID_WIDTH >= CFG_RDDATA_ID_WIDTH) ? CFG_WRDATA_ID_WIDTH : CFG_RDDATA_ID_WIDTH;
// to avoid -1
localparam integer CFG_DATA_ID_REMAINDER = (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH) ? 0 : 2**(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH);
localparam CFG_WRDATA_VEC_ID_WIDTH = CFG_MAX_PENDING_WR_CMD;
// AFI
localparam CFG_ADDR_RATE_RATIO = (CFG_LPDDR2_ENABLED == 1) ? 2 : 1;
localparam CFG_AFI_IF_FR_ADDR_WIDTH = CFG_ADDR_RATE_RATIO * CFG_MEM_IF_ADDR_WIDTH;
localparam CFG_DRAM_WLAT_GROUP = (CFG_WLAT_BUS_WIDTH <= 6) ? 1 : CFG_MEM_IF_DQS_WIDTH; // Supports single / multiple DQS group of afi_wlat
localparam CFG_LOCAL_WLAT_GROUP = (CFG_WLAT_BUS_WIDTH <= 6) ? 1 : (((CFG_LOCAL_DATA_WIDTH / CFG_DWIDTH_RATIO) == CFG_MEM_IF_DQ_WIDTH) ? CFG_MEM_IF_DQS_WIDTH : CFG_MEM_IF_DQS_WIDTH - CFG_ECC_MULTIPLES_16_24_40_72); // Determine the wlat group for local data width (without ECC code)
// Derived timing parameters width
localparam T_PARAM_ACT_TO_RDWR_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 3 : (CFG_DWIDTH_RATIO == 4) ? 3 : 4; //case:234203
localparam T_PARAM_ACT_TO_PCH_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_ACT_TO_ACT_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_RD_TO_RD_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_RD_TO_WR_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_RD_TO_WR_BC_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_RD_TO_PCH_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_RD_AP_TO_VALID_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_WR_TO_WR_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_WR_TO_RD_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_WR_TO_RD_BC_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_WR_TO_PCH_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_WR_AP_TO_VALID_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_PCH_TO_VALID_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 3 : (CFG_DWIDTH_RATIO == 4) ? 3 : 4; //case:234203
localparam T_PARAM_PCH_ALL_TO_VALID_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 3 : (CFG_DWIDTH_RATIO == 4) ? 3 : 4; //case:234203
localparam T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 2 : (CFG_DWIDTH_RATIO == 4) ? 3 : 4;
localparam T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 2 : (CFG_DWIDTH_RATIO == 4) ? 3 : 4;
localparam T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_FOUR_ACT_TO_ACT_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 4 : (CFG_DWIDTH_RATIO == 4) ? 5 : 6;
localparam T_PARAM_ARF_TO_VALID_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 7 : (CFG_DWIDTH_RATIO == 4) ? 8 : 9;
localparam T_PARAM_PDN_TO_VALID_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 3 : (CFG_DWIDTH_RATIO == 4) ? 3 : 4; //case:234203
localparam T_PARAM_SRF_TO_VALID_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 8 : (CFG_DWIDTH_RATIO == 4) ? 9 : 10;
localparam T_PARAM_SRF_TO_ZQ_CAL_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 7 : (CFG_DWIDTH_RATIO == 4) ? 8 : 9;
localparam T_PARAM_ARF_PERIOD_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 12 : (CFG_DWIDTH_RATIO == 4) ? 12 : 13; //case:234203
localparam T_PARAM_PDN_PERIOD_WIDTH = 17; //case:234203
localparam T_PARAM_POWER_SAVING_EXIT_WIDTH = (CFG_DWIDTH_RATIO == 8) ? 3 : (CFG_DWIDTH_RATIO == 4) ? 2 : 3; //case:234203
localparam T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH = (CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES > 6) ? CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES : 5; //case:234203
localparam integer CFG_DATAID_ARRAY_DEPTH = 2**CFG_DATA_ID_WIDTH;
localparam integer CFG_WRDATA_ID_WIDTH_SQRD = 2**CFG_WRDATA_ID_WIDTH;
// Clock and reset
input ctl_clk;
input ctl_reset_n;
// Command channel
output itf_cmd_ready;
input itf_cmd_valid;
input itf_cmd;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] itf_cmd_address;
input [CFG_LOCAL_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
// Write data channel
output itf_wr_data_ready;
input itf_wr_data_valid;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_wr_data;
input [CFG_LOCAL_DATA_WIDTH / 8 - 1 : 0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_wr_data_id;
// Read data channel
input itf_rd_data_ready;
output itf_rd_data_valid;
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id_early;
output itf_rd_data_id_early_valid;
// Sideband signals
input local_refresh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_refresh_chip;
input local_zqcal_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_zqcal_chip;
input local_deep_powerdn_req;
input [CFG_MEM_IF_CHIP-1:0] local_deep_powerdn_chip;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_self_rfsh_chip;
output local_refresh_ack;
output local_deep_powerdn_ack;
output local_power_down_ack;
output local_self_rfsh_ack;
output local_init_done;
// Controller commands to the AFI interface
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rst_n;
output [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_ba;
output [(CFG_AFI_IF_FR_ADDR_WIDTH*(CFG_DWIDTH_RATIO / 2))- 1 : 0] afi_addr;
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cke;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cs_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_ras_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_cas_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_we_n;
output [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_odt;
// Controller read and write data to the AFI interface
input [CFG_WLAT_BUS_WIDTH - 1 : 0] afi_wlat;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_dqs_burst;
output [CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_dm;
output [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_wdata;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_wdata_valid;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en_full;
output [CFG_RRANK_BUS_WIDTH - 1 : 0] afi_rrank;
output [CFG_WRANK_BUS_WIDTH - 1 : 0] afi_wrank;
input [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_rdata;
input [CFG_DWIDTH_RATIO / 2 - 1 : 0] afi_rdata_valid;
// Status and control signal to the AFI interface
input ctl_cal_success;
input ctl_cal_fail;
output ctl_cal_req;
output ctl_init_req;
output [CFG_MEM_IF_DQS_WIDTH * CFG_MEM_IF_CHIP - 1 : 0] ctl_cal_byte_lane_sel_n ;
output [CFG_MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_mem_clk_disable;
// cfg: general
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] cfg_device_width;
input [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd;
// cfg: address mapping signals
input [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
// cfg: timing parameters
input [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
input [CFG_PORT_WIDTH_TRRD - 1 : 0] cfg_trrd;
input [CFG_PORT_WIDTH_TFAW - 1 : 0] cfg_tfaw;
input [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc;
input [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi;
input [CFG_PORT_WIDTH_TRCD - 1 : 0] cfg_trcd;
input [CFG_PORT_WIDTH_TRP - 1 : 0] cfg_trp;
input [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr;
input [CFG_PORT_WIDTH_TWTR - 1 : 0] cfg_twtr;
input [CFG_PORT_WIDTH_TRTP - 1 : 0] cfg_trtp;
input [CFG_PORT_WIDTH_TRAS - 1 : 0] cfg_tras;
input [CFG_PORT_WIDTH_TRC - 1 : 0] cfg_trc;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] cfg_auto_pd_cycles;
input [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES - 1 : 0] cfg_self_rfsh_exit_cycles;
input [CFG_PORT_WIDTH_PDN_EXIT_CYCLES - 1 : 0] cfg_pdn_exit_cycles;
input [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES - 1 : 0] cfg_power_saving_exit_cycles;
input [CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES - 1 : 0] cfg_mem_clk_entry_cycles;
input [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd;
// cfg: extra timing parameters
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD - 1 : 0] cfg_extra_ctl_clk_arf_period;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD - 1 : 0] cfg_extra_ctl_clk_pdn_period;
// cfg: control signals
input [CFG_PORT_WIDTH_REORDER_DATA - 1 : 0] cfg_reorder_data;
input [CFG_PORT_WIDTH_STARVE_LIMIT - 1 : 0] cfg_starve_limit;
input [CFG_PORT_WIDTH_USER_RFSH - 1 : 0] cfg_user_rfsh;
input [CFG_PORT_WIDTH_REGDIMM_ENABLE - 1 : 0] cfg_regdimm_enable;
input [CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT - 1 : 0] cfg_enable_burst_interrupt;
input [CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE - 1 : 0] cfg_enable_burst_terminate;
// cfg: ecc signals
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
input [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
input [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] cfg_gen_sbe;
input [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] cfg_gen_dbe;
input [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] cfg_enable_intr;
input [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] cfg_mask_sbe_intr;
input [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] cfg_mask_dbe_intr;
input [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] cfg_mask_corr_dropped_intr;
input [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] cfg_clr_intr;
input [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites;
// cfg: odt
input [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip;
input [CFG_PORT_WIDTH_READ_ODT_CHIP - 1 : 0] cfg_read_odt_chip;
// sts: ecc signals
output ecc_interrupt;
output [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
output [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
output [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
output [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
output [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
output [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
// calibration signals
input cfg_cal_req;
output sts_cal_fail;
output sts_cal_success;
// DQS enable tracking
input cfg_enable_dqs_tracking;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP - 1 : 0] afi_seq_busy;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
output tbp_empty;
output cmd_gen_busy;
output sideband_in_refresh;
//==============================================================================
//
// Wires
//
//==============================================================================
// alt_mem_ddrx_input_if
wire itf_cmd_ready;
wire itf_wr_data_ready;
wire itf_rd_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
wire itf_rd_data_error;
wire itf_rd_data_begin;
wire itf_rd_data_last;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id_early;
wire itf_rd_data_id_early_valid;
wire cmd_valid;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] cmd_address;
wire cmd_write;
wire cmd_read;
wire cmd_multicast;
wire [CFG_LOCAL_SIZE_WIDTH - 1 : 0] cmd_size;
wire cmd_priority;
wire cmd_autoprecharge;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] cmd_id;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] write_data;
wire [CFG_LOCAL_DATA_WIDTH / 8 - 1 : 0] byte_en;
wire write_data_valid;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] write_data_id;
wire local_refresh_ack;
wire local_deep_powerdn_ack;
wire local_power_down_ack;
wire local_self_rfsh_ack;
wire local_init_done;
wire rfsh_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] rfsh_chip;
wire zqcal_req;
wire deep_powerdn_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] deep_powerdn_chip;
wire self_rfsh_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] self_rfsh_chip;
// alt_mem_ddrx_cmd_gen
wire cmd_gen_load;
wire cmd_gen_waiting_to_load;
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] cmd_gen_chipsel;
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] cmd_gen_bank;
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] cmd_gen_row;
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] cmd_gen_col;
wire cmd_gen_write;
wire cmd_gen_read;
wire cmd_gen_multicast;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] cmd_gen_size;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] cmd_gen_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] cmd_gen_dataid;
wire cmd_gen_priority;
wire cmd_gen_rmw_correct;
wire cmd_gen_rmw_partial;
wire cmd_gen_autopch;
wire cmd_gen_complete;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_bank_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_row_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_col_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_read_cmd;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_write_cmd;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_chipsel_addr;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_bank_addr;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_row_addr;
wire cmd_gen_full;
// alt_mem_ddrx_tbp
wire tbp_full;
wire tbp_empty;
wire [CFG_CTL_TBP_NUM - 1 : 0] row_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] act_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] pch_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] col_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] rd_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] wr_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_read;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_write;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_precharge;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_activate;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_bank;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_row;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] tbp_col;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_shadow_chipsel;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_shadow_bank;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_shadow_row;
wire [(CFG_CTL_TBP_NUM * CFG_INT_SIZE_WIDTH) - 1 : 0] tbp_size;
wire [(CFG_CTL_TBP_NUM * CFG_LOCAL_ID_WIDTH) - 1 : 0] tbp_localid;
wire [(CFG_CTL_TBP_NUM * CFG_DATA_ID_WIDTH) - 1 : 0] tbp_dataid;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_ap;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_burst_chop;
wire [(CFG_CTL_TBP_NUM * CFG_CTL_TBP_NUM) - 1 : 0] tbp_age;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_priority;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_correct;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_partial;
wire [CFG_MEM_IF_CHIP - 1 : 0] tbp_bank_closed;
wire [CFG_MEM_IF_CHIP - 1 : 0] tbp_timer_ready;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_load_index;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_load;
wire data_rmw_fetch;
// alt_mem_ddrx_arbiter
wire [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
wire or_row_grant;
wire or_col_grant;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// alt_mem_ddrx_burst_gen
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
wire bg_interrupt_ready_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
wire bg_do_lmr_read = 0;
wire bg_do_refresh_1bank = 0;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
wire bg_doing_write;
wire bg_doing_read;
wire bg_rdwr_data_valid;
wire bg_interrupt_ready;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
wire [CFG_RDDATA_ID_WIDTH - 1 : 0] bg_rddataid;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
wire [ 2 : 0] bg_to_lmr = 0;
// alt_mem_ddrx_addr_cmd_wrap
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cs_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_ras_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_cas_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_we_n;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_ba;
wire [(CFG_AFI_IF_FR_ADDR_WIDTH*(CFG_DWIDTH_RATIO / 2))- 1 : 0] afi_addr;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rst_n;
wire [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_odt;
wire [CFG_AFI_IF_FR_ADDR_WIDTH - 1 : 0] lmr_opcode = 0;
// alt_mem_ddrx_rdwr_data_tmg
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en_full;
wire [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd_for_afi_output;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_read;
wire [CFG_DRAM_WLAT_GROUP * CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid;
wire [CFG_DRAM_WLAT_GROUP * CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_rmw_correct;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_rmw_partial;
wire ecc_wdata_fifo_read_first;
wire [CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid_first;
wire [CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector_first;
wire ecc_wdata_fifo_rmw_correct_first;
wire ecc_wdata_fifo_rmw_partial_first;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_first_vector;
wire ecc_wdata_fifo_read_last;
wire [CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid_last;
wire [CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector_last;
wire ecc_wdata_fifo_rmw_correct_last;
wire ecc_wdata_fifo_rmw_partial_last;
wire [CFG_DRAM_WLAT_GROUP * CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid;
wire [CFG_DRAM_WLAT_GROUP * CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid_first;
wire [CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector_first;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid_last;
wire [CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector_last;
wire [CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2) * CFG_MEM_IF_DQS_WIDTH - 1 : 0] int_afi_rrank;
wire [CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2) * CFG_MEM_IF_DQS_WIDTH - 1 : 0] int_afi_wrank;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_dqs_burst;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_wdata_valid;
wire [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_wdata;
wire [CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_dm;
// alt_mem_ddrx_wdata_path
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
wire wdatap_free_id_valid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] wdatap_free_id_dataid;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] wdatap_free_id_wrdataid;
wire wr_data_mem_full;
wire [CFG_CTL_TBP_NUM - 1 : 0] data_complete;
wire data_rmw_complete;
wire data_partial_be;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_data;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_partial_data;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_correct_data;
wire wdatap_rmw_partial;
wire wdatap_rmw_correct;
wire [(CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS) - 1 : 0] wdatap_dm;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
wire [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// alt_mem_ddrx_rdata_path
wire rdatap_free_id_valid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] rdatap_free_id_dataid;
wire [CFG_RDDATA_ID_WIDTH - 1 : 0] rdatap_free_id_rddataid;
wire read_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] read_data;
wire read_data_error;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] read_data_localid;
wire errcmd_ready;
wire errcmd_valid;
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] errcmd_chipsel;
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] errcmd_bank;
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] errcmd_row;
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] errcmd_column;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] errcmd_size;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] errcmd_localid;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] rdatap_rcvd_addr;
wire rdatap_rcvd_cmd;
wire rdatap_rcvd_corr_dropped;
wire rmwfifo_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] rmwfifo_data;
wire [CFG_ECC_MULTIPLES - 1 : 0] rmwfifo_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// alt_mem_ddrx_ecc_encoder_decoder_wrapper
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
wire ecc_rdata_valid;
wire [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
wire [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
wire [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
wire ecc_interrupt;
wire [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
wire [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
wire [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
wire [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
wire [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
wire [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
// alt_mem_ddrx_sideband
wire rfsh_ack;
wire self_rfsh_ack;
wire deep_powerdn_ack;
wire power_down_ack;
wire stall_row_arbiter;
wire stall_col_arbiter;
wire [CFG_MEM_IF_CHIP - 1 : 0] stall_chip;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_precharge_all;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_refresh;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_self_refresh;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_power_down;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_deep_pdown;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_zq_cal;
wire [CFG_CTL_TBP_NUM - 1 : 0] sb_tbp_precharge_all;
wire [CFG_MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_sb_mem_clk_disable;
wire ctl_sb_cal_req;
wire ctl_sb_init_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
wire [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
// alt_mem_ddrx_rank_timer
wire [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_read;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_write;
// alt_mem_ddrx_timing_param
wire [T_PARAM_ACT_TO_RDWR_WIDTH - 1 : 0] t_param_act_to_rdwr;
wire [T_PARAM_ACT_TO_PCH_WIDTH - 1 : 0] t_param_act_to_pch;
wire [T_PARAM_ACT_TO_ACT_WIDTH - 1 : 0] t_param_act_to_act;
wire [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
wire [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
wire [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
wire [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
wire [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
wire [T_PARAM_RD_TO_PCH_WIDTH - 1 : 0] t_param_rd_to_pch;
wire [T_PARAM_RD_AP_TO_VALID_WIDTH - 1 : 0] t_param_rd_ap_to_valid;
wire [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
wire [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
wire [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
wire [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
wire [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
wire [T_PARAM_WR_TO_PCH_WIDTH - 1 : 0] t_param_wr_to_pch;
wire [T_PARAM_WR_AP_TO_VALID_WIDTH - 1 : 0] t_param_wr_ap_to_valid;
wire [T_PARAM_PCH_TO_VALID_WIDTH - 1 : 0] t_param_pch_to_valid;
wire [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
wire [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
wire [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
wire [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
wire [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
wire [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
wire [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
wire [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
wire [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
wire [T_PARAM_POWER_SAVING_EXIT_WIDTH - 1 : 0] t_param_power_saving_exit;
wire [T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH - 1 : 0] t_param_mem_clk_entry_cycles;
// General
wire init_done = ctl_cal_success;
wire sts_cal_success = ctl_cal_success;
wire sts_cal_fail = ctl_cal_fail;
wire ctl_cal_req = cfg_cal_req | ctl_sb_cal_req;
wire ctl_init_req = ctl_sb_init_req;
wire [CFG_MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_mem_clk_disable = ctl_sb_mem_clk_disable;
wire [CFG_MEM_IF_DQS_WIDTH*CFG_MEM_IF_CHIP - 1 : 0] ctl_cal_byte_lane_sel_n = 0;
wire [CFG_RRANK_BUS_WIDTH - 1 : 0] afi_rrank = CFG_USE_SHADOW_REGS ? int_afi_rrank[CFG_RRANK_BUS_WIDTH - 1:0] : {CFG_RRANK_BUS_WIDTH{1'b0}};
wire [CFG_WRANK_BUS_WIDTH - 1 : 0] afi_wrank = CFG_USE_SHADOW_REGS ? int_afi_wrank[CFG_WRANK_BUS_WIDTH - 1:0] : {CFG_RRANK_BUS_WIDTH{1'b0}};
// Log 2 function
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
// register init_done signal
reg init_done_reg;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
init_done_reg <= 0;
end
else
begin
init_done_reg <= init_done;
end
end
//==============================================================================
// alt_mem_ddrx_input_if
//------------------------------------------------------------------------------
//
// Input interface block
//
// Info: Includes cmd channel, and both read and write channels
// * Optional half-rate bridge logic
//
//==============================================================================
alt_mem_ddrx_input_if #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_SIZE_WIDTH (CFG_LOCAL_SIZE_WIDTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE )
)
input_if_inst
(
.itf_cmd_ready (itf_cmd_ready ),
.itf_cmd_valid (itf_cmd_valid ),
.itf_cmd (itf_cmd ),
.itf_cmd_address (itf_cmd_address ),
.itf_cmd_burstlen (itf_cmd_burstlen ),
.itf_cmd_id (itf_cmd_id ),
.itf_cmd_priority (itf_cmd_priority ),
.itf_cmd_autopercharge (itf_cmd_autopercharge ),
.itf_cmd_multicast (itf_cmd_multicast ),
.itf_wr_data_ready (itf_wr_data_ready ),
.itf_wr_data_valid (itf_wr_data_valid ),
.itf_wr_data (itf_wr_data ),
.itf_wr_data_byte_en (itf_wr_data_byte_en ),
.itf_wr_data_begin (itf_wr_data_begin ),
.itf_wr_data_last (itf_wr_data_last ),
.itf_wr_data_id (itf_wr_data_id ),
.itf_rd_data_ready (itf_rd_data_ready ),
.itf_rd_data_valid (itf_rd_data_valid ),
.itf_rd_data (itf_rd_data ),
.itf_rd_data_error (itf_rd_data_error ),
.itf_rd_data_begin (itf_rd_data_begin ),
.itf_rd_data_last (itf_rd_data_last ),
.itf_rd_data_id (itf_rd_data_id ),
.itf_rd_data_id_early (itf_rd_data_id_early ),
.itf_rd_data_id_early_valid(itf_rd_data_id_early_valid ),
.cmd_gen_full (cmd_gen_full ),
.cmd_valid (cmd_valid ),
.cmd_address (cmd_address ),
.cmd_write (cmd_write ),
.cmd_read (cmd_read ),
.cmd_multicast (cmd_multicast ),
.cmd_size (cmd_size ),
.cmd_priority (cmd_priority ),
.cmd_autoprecharge (cmd_autoprecharge ),
.cmd_id (cmd_id ),
.write_data (write_data ),
.wr_data_mem_full (wr_data_mem_full ),
.write_data_id (write_data_id ),
.byte_en (byte_en ),
.write_data_valid (write_data_valid ),
.read_data (read_data ),
.read_data_valid (read_data_valid ),
.read_data_error (read_data_error ),
.read_data_localid (read_data_localid ),
.read_data_begin ( ), // NOTICE: not connected?
.read_data_last ( ), // NOTICE: not connected?
.bg_do_read (bg_do_read ),
.bg_localid (bg_localid ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.local_refresh_req (local_refresh_req ),
.local_refresh_chip (local_refresh_chip ),
.local_zqcal_req (local_zqcal_req ),
// .local_zqcal_chip (local_zqcal_chip ),
.local_deep_powerdn_req (local_deep_powerdn_req ),
.local_deep_powerdn_chip (local_deep_powerdn_chip ),
.local_self_rfsh_req (local_self_rfsh_req ),
.local_self_rfsh_chip (local_self_rfsh_chip ),
.local_refresh_ack (local_refresh_ack ),
.local_deep_powerdn_ack (local_deep_powerdn_ack ),
.local_power_down_ack (local_power_down_ack ),
.local_self_rfsh_ack (local_self_rfsh_ack ),
.local_init_done (local_init_done ),
.rfsh_req (rfsh_req ),
.rfsh_chip (rfsh_chip ),
.zqcal_req (zqcal_req ),
.deep_powerdn_req (deep_powerdn_req ),
.deep_powerdn_chip (deep_powerdn_chip ),
.self_rfsh_req (self_rfsh_req ),
.self_rfsh_chip (self_rfsh_chip ),
.rfsh_ack (rfsh_ack ),
.deep_powerdn_ack (deep_powerdn_ack ),
.power_down_ack (power_down_ack ),
.self_rfsh_ack (self_rfsh_ack ),
.init_done (init_done_reg )
);
//==============================================================================
// alt_mem_ddrx_cmd_gen
//------------------------------------------------------------------------------
//
// Command generator block
//
// Info: * generates cmd from local and internal ECC block
// * splitting and merging of all commands
// * optional queue for latency reduction purpose when no merging is required
//
//==============================================================================
alt_mem_ddrx_cmd_gen #
(
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_SIZE_WIDTH (CFG_LOCAL_SIZE_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_PORT_WIDTH_COL_ADDR_WIDTH (CFG_PORT_WIDTH_COL_ADDR_WIDTH ),
.CFG_PORT_WIDTH_ROW_ADDR_WIDTH (CFG_PORT_WIDTH_ROW_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BANK_ADDR_WIDTH (CFG_PORT_WIDTH_BANK_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH (CFG_PORT_WIDTH_CS_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ADDR_ORDER (CFG_PORT_WIDTH_ADDR_ORDER ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_QUEUE_DEPTH (CFG_CTL_QUEUE_DEPTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_ENABLE_QUEUE (CFG_ENABLE_QUEUE ),
.CFG_ENABLE_BURST_MERGE (CFG_ENABLE_BURST_MERGE ),
.CFG_CMD_GEN_OUTPUT_REG (CFG_CMD_GEN_OUTPUT_REG ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_SHADOW_TBP_NUM (CFG_CTL_SHADOW_TBP_NUM )
)
cmd_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.tbp_full (tbp_full ),
.tbp_load (tbp_load ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_shadow_chipsel (tbp_shadow_chipsel ),
.tbp_shadow_bank (tbp_shadow_bank ),
.tbp_shadow_row (tbp_shadow_row ),
.cmd_gen_load (cmd_gen_load ),
.cmd_gen_waiting_to_load (cmd_gen_waiting_to_load ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.cmd_gen_bank (cmd_gen_bank ),
.cmd_gen_row (cmd_gen_row ),
.cmd_gen_col (cmd_gen_col ),
.cmd_gen_write (cmd_gen_write ),
.cmd_gen_read (cmd_gen_read ),
.cmd_gen_multicast (cmd_gen_multicast ),
.cmd_gen_size (cmd_gen_size ),
.cmd_gen_localid (cmd_gen_localid ),
.cmd_gen_dataid (cmd_gen_dataid ),
.cmd_gen_priority (cmd_gen_priority ),
.cmd_gen_rmw_correct (cmd_gen_rmw_correct ),
.cmd_gen_rmw_partial (cmd_gen_rmw_partial ),
.cmd_gen_autopch (cmd_gen_autopch ),
.cmd_gen_complete (cmd_gen_complete ),
.cmd_gen_same_chipsel_addr (cmd_gen_same_chipsel_addr ),
.cmd_gen_same_bank_addr (cmd_gen_same_bank_addr ),
.cmd_gen_same_row_addr (cmd_gen_same_row_addr ),
.cmd_gen_same_col_addr (cmd_gen_same_col_addr ),
.cmd_gen_same_read_cmd (cmd_gen_same_read_cmd ),
.cmd_gen_same_write_cmd (cmd_gen_same_write_cmd ),
.cmd_gen_same_shadow_chipsel_addr (cmd_gen_same_shadow_chipsel_addr ),
.cmd_gen_same_shadow_bank_addr (cmd_gen_same_shadow_bank_addr ),
.cmd_gen_same_shadow_row_addr (cmd_gen_same_shadow_row_addr ),
.cmd_gen_busy (cmd_gen_busy ),
.cmd_gen_full (cmd_gen_full ),
.cmd_valid (cmd_valid ),
.cmd_address (cmd_address ),
.cmd_write (cmd_write ),
.cmd_read (cmd_read ),
.cmd_id (cmd_id ),
.cmd_multicast (cmd_multicast ),
.cmd_size (cmd_size ),
.cmd_priority (cmd_priority ),
.cmd_autoprecharge (cmd_autoprecharge ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_write (proc_write ),
.proc_read (proc_read ),
.proc_size (proc_size ),
.proc_localid (proc_localid ),
.wdatap_free_id_valid (wdatap_free_id_valid ),
.wdatap_free_id_dataid (wdatap_free_id_dataid ),
.rdatap_free_id_valid (rdatap_free_id_valid ),
.rdatap_free_id_dataid (rdatap_free_id_dataid ),
.tbp_load_index (tbp_load_index ),
.data_complete (data_complete ),
.data_rmw_complete (data_rmw_complete ),
.errcmd_ready (errcmd_ready ),
.errcmd_valid (errcmd_valid ),
.errcmd_chipsel (errcmd_chipsel ),
.errcmd_bank (errcmd_bank ),
.errcmd_row (errcmd_row ),
.errcmd_column (errcmd_column ),
.errcmd_size (errcmd_size ),
.errcmd_localid (errcmd_localid ),
.data_partial_be (data_partial_be ),
.cfg_enable_cmd_split (CFG_ENABLE_CMD_SPLIT ),
.cfg_burst_length (cfg_burst_length ),
.cfg_addr_order (cfg_addr_order ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_col_addr_width (cfg_col_addr_width ),
.cfg_row_addr_width (cfg_row_addr_width ),
.cfg_bank_addr_width (cfg_bank_addr_width ),
.cfg_cs_addr_width (cfg_cs_addr_width )
);
//==============================================================================
// alt_mem_ddrx_tbp
//------------------------------------------------------------------------------
//
// Timing bank pool block
//
// Info: * parallel queue in which a cmd is present
// * tracks timer and bank status information of the command it hold
// * monitor other TBPs content to update status bit in itself such
// as the autoprecharge bit
// * pass timer value to another TBP if need arises
//
//==============================================================================
alt_mem_ddrx_tbp #
(
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_SHADOW_TBP_NUM (CFG_CTL_SHADOW_TBP_NUM ),
.CFG_ENABLE_SHADOW_TBP (CFG_ENABLE_SHADOW_TBP ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_PORT_WIDTH_STARVE_LIMIT (CFG_PORT_WIDTH_STARVE_LIMIT ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_REORDER_DATA (CFG_PORT_WIDTH_REORDER_DATA ),
.CFG_REG_REQ (CFG_REG_REQ ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_DATA_REORDERING_TYPE (CFG_DATA_REORDERING_TYPE ),
.CFG_DISABLE_READ_REODERING (CFG_DISABLE_READ_REODERING ),
.CFG_DISABLE_PRIORITY (CFG_DISABLE_PRIORITY ),
.T_PARAM_ACT_TO_RDWR_WIDTH (T_PARAM_ACT_TO_RDWR_WIDTH ),
.T_PARAM_ACT_TO_ACT_WIDTH (T_PARAM_ACT_TO_ACT_WIDTH ),
.T_PARAM_ACT_TO_PCH_WIDTH (T_PARAM_ACT_TO_PCH_WIDTH ),
.T_PARAM_RD_TO_PCH_WIDTH (T_PARAM_RD_TO_PCH_WIDTH ),
.T_PARAM_WR_TO_PCH_WIDTH (T_PARAM_WR_TO_PCH_WIDTH ),
.T_PARAM_PCH_TO_VALID_WIDTH (T_PARAM_PCH_TO_VALID_WIDTH ),
.T_PARAM_RD_AP_TO_VALID_WIDTH (T_PARAM_RD_AP_TO_VALID_WIDTH ),
.T_PARAM_WR_AP_TO_VALID_WIDTH (T_PARAM_WR_AP_TO_VALID_WIDTH )
)
tbp_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.tbp_full (tbp_full ),
.tbp_empty (tbp_empty ),
.cmd_gen_load (cmd_gen_load ),
.cmd_gen_waiting_to_load (cmd_gen_waiting_to_load ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.cmd_gen_bank (cmd_gen_bank ),
.cmd_gen_row (cmd_gen_row ),
.cmd_gen_col (cmd_gen_col ),
.cmd_gen_write (cmd_gen_write ),
.cmd_gen_read (cmd_gen_read ),
.cmd_gen_size (cmd_gen_size ),
.cmd_gen_localid (cmd_gen_localid ),
.cmd_gen_dataid (cmd_gen_dataid ),
.cmd_gen_priority (cmd_gen_priority ),
.cmd_gen_rmw_correct (cmd_gen_rmw_correct ),
.cmd_gen_rmw_partial (cmd_gen_rmw_partial ),
.cmd_gen_autopch (cmd_gen_autopch ),
.cmd_gen_complete (cmd_gen_complete ),
.cmd_gen_same_chipsel_addr (cmd_gen_same_chipsel_addr ),
.cmd_gen_same_bank_addr (cmd_gen_same_bank_addr ),
.cmd_gen_same_row_addr (cmd_gen_same_row_addr ),
.cmd_gen_same_col_addr (cmd_gen_same_col_addr ),
.cmd_gen_same_read_cmd (cmd_gen_same_read_cmd ),
.cmd_gen_same_write_cmd (cmd_gen_same_write_cmd ),
.cmd_gen_same_shadow_chipsel_addr (cmd_gen_same_shadow_chipsel_addr ),
.cmd_gen_same_shadow_bank_addr (cmd_gen_same_shadow_bank_addr ),
.cmd_gen_same_shadow_row_addr (cmd_gen_same_shadow_row_addr ),
.row_req (row_req ),
.act_req (act_req ),
.pch_req (pch_req ),
.col_req (col_req ),
.rd_req (rd_req ),
.wr_req (wr_req ),
.row_grant (row_grant ),
.col_grant (col_grant ),
.act_grant (act_grant ),
.pch_grant (pch_grant ),
.rd_grant (rd_grant ),
.wr_grant (wr_grant ),
.log2_row_grant (log2_row_grant ),
.log2_col_grant (log2_col_grant ),
.log2_act_grant (log2_act_grant ),
.log2_pch_grant (log2_pch_grant ),
.log2_rd_grant (log2_rd_grant ),
.log2_wr_grant (log2_wr_grant ),
.or_row_grant (or_row_grant ),
.or_col_grant (or_col_grant ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_precharge (tbp_precharge ),
.tbp_activate (tbp_activate ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_shadow_chipsel (tbp_shadow_chipsel ),
.tbp_shadow_bank (tbp_shadow_bank ),
.tbp_shadow_row (tbp_shadow_row ),
.tbp_size (tbp_size ),
.tbp_localid (tbp_localid ),
.tbp_dataid (tbp_dataid ),
.tbp_ap (tbp_ap ),
.tbp_burst_chop (tbp_burst_chop ),
.tbp_age (tbp_age ),
.tbp_priority (tbp_priority ),
.tbp_rmw_correct (tbp_rmw_correct ),
.tbp_rmw_partial (tbp_rmw_partial ),
.sb_tbp_precharge_all (sb_tbp_precharge_all ),
.sb_do_precharge_all (sb_do_precharge_all ),
.t_param_act_to_rdwr (t_param_act_to_rdwr ),
.t_param_act_to_act (t_param_act_to_act ),
.t_param_act_to_pch (t_param_act_to_pch ),
.t_param_rd_to_pch (t_param_rd_to_pch ),
.t_param_wr_to_pch (t_param_wr_to_pch ),
.t_param_pch_to_valid (t_param_pch_to_valid ),
.t_param_rd_ap_to_valid (t_param_rd_ap_to_valid ),
.t_param_wr_ap_to_valid (t_param_wr_ap_to_valid ),
.tbp_bank_closed (tbp_bank_closed ),
.tbp_timer_ready (tbp_timer_ready ),
.cfg_reorder_data (cfg_reorder_data ),
.tbp_load (tbp_load ),
.data_complete (data_complete ),
.data_rmw_complete (data_rmw_complete ),
.data_rmw_fetch (data_rmw_fetch ),
.cfg_starve_limit (cfg_starve_limit ),
.cfg_type (cfg_type ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_no_dm (cfg_enable_no_dm )
);
//==============================================================================
// alt_mem_ddrx_arbiter
//------------------------------------------------------------------------------
//
// Arbiter block
//
// Info: Priority command-aging arbiter, it will grant command with priority
// first, during tie-break situation, oldest command will be granted.
// Read comment in arbiter code for more information
//
//==============================================================================
alt_mem_ddrx_arbiter #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_REG_REQ (CFG_REG_REQ ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_DISABLE_PRIORITY (CFG_DISABLE_PRIORITY )
)
arbiter_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.stall_row_arbiter (stall_row_arbiter ),
.stall_col_arbiter (stall_col_arbiter ),
.sb_do_precharge_all (sb_do_precharge_all ),
.sb_do_refresh (sb_do_refresh ),
.sb_do_self_refresh (sb_do_self_refresh ),
.sb_do_power_down (sb_do_power_down ),
.sb_do_deep_pdown (sb_do_deep_pdown ),
.sb_do_zq_cal (sb_do_zq_cal ),
.row_req (row_req ),
.col_req (col_req ),
.act_req (act_req ),
.pch_req (pch_req ),
.rd_req (rd_req ),
.wr_req (wr_req ),
.row_grant (row_grant ),
.col_grant (col_grant ),
.act_grant (act_grant ),
.pch_grant (pch_grant ),
.rd_grant (rd_grant ),
.wr_grant (wr_grant ),
.log2_row_grant (log2_row_grant ),
.log2_col_grant (log2_col_grant ),
.log2_act_grant (log2_act_grant ),
.log2_pch_grant (log2_pch_grant ),
.log2_rd_grant (log2_rd_grant ),
.log2_wr_grant (log2_wr_grant ),
.or_row_grant (or_row_grant ),
.or_col_grant (or_col_grant ),
.tbp_activate (tbp_activate ),
.tbp_precharge (tbp_precharge ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_size (tbp_size ),
.tbp_localid (tbp_localid ),
.tbp_dataid (tbp_dataid ),
.tbp_ap (tbp_ap ),
.tbp_burst_chop (tbp_burst_chop ),
.tbp_rmw_correct (tbp_rmw_correct ),
.tbp_rmw_partial (tbp_rmw_partial ),
.tbp_age (tbp_age ),
.tbp_priority (tbp_priority ),
.can_activate (can_activate ),
.can_precharge (can_precharge ),
.can_write (can_write ),
.can_read (can_read ),
.arb_do_write (arb_do_write ),
.arb_do_read (arb_do_read ),
.arb_do_burst_chop (arb_do_burst_chop ),
.arb_do_burst_terminate (arb_do_burst_terminate ),
.arb_do_auto_precharge (arb_do_auto_precharge ),
.arb_do_rmw_correct (arb_do_rmw_correct ),
.arb_do_rmw_partial (arb_do_rmw_partial ),
.arb_do_activate (arb_do_activate ),
.arb_do_precharge (arb_do_precharge ),
.arb_do_precharge_all (arb_do_precharge_all ),
.arb_do_refresh (arb_do_refresh ),
.arb_do_self_refresh (arb_do_self_refresh ),
.arb_do_power_down (arb_do_power_down ),
.arb_do_deep_pdown (arb_do_deep_pdown ),
.arb_do_zq_cal (arb_do_zq_cal ),
.arb_do_lmr (arb_do_lmr ),
.arb_to_chipsel (arb_to_chipsel ),
.arb_to_chip (arb_to_chip ),
.arb_to_bank (arb_to_bank ),
.arb_to_row (arb_to_row ),
.arb_to_col (arb_to_col ),
.arb_localid (arb_localid ),
.arb_dataid (arb_dataid ),
.arb_size (arb_size )
);
//==============================================================================
// alt_mem_ddrx_burst_gen
//------------------------------------------------------------------------------
//
// Burst generation block
//
// Info: Create DQ/DQS burst information for AFI block
//
//==============================================================================
alt_mem_ddrx_burst_gen #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_TCCD (CFG_PORT_WIDTH_TCCD ),
.CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT (CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT ),
.CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE (CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE ),
.CFG_ENABLE_BURST_GEN_OUTPUT_REG (CFG_ENABLE_BURST_GEN_OUTPUT_REG )
)
burst_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_burst_length (cfg_burst_length ),
.cfg_tccd (cfg_tccd ),
.cfg_enable_burst_interrupt (cfg_enable_burst_interrupt ),
.cfg_enable_burst_terminate (cfg_enable_burst_terminate ),
.arb_do_write (arb_do_write ),
.arb_do_read (arb_do_read ),
.arb_do_burst_chop (arb_do_burst_chop ),
.arb_do_burst_terminate (arb_do_burst_terminate ),
.arb_do_auto_precharge (arb_do_auto_precharge ),
.arb_do_rmw_correct (arb_do_rmw_correct ),
.arb_do_rmw_partial (arb_do_rmw_partial ),
.arb_do_activate (arb_do_activate ),
.arb_do_precharge (arb_do_precharge ),
.arb_do_precharge_all (arb_do_precharge_all ),
.arb_do_refresh (arb_do_refresh ),
.arb_do_self_refresh (arb_do_self_refresh ),
.arb_do_power_down (arb_do_power_down ),
.arb_do_deep_pdown (arb_do_deep_pdown ),
.arb_do_zq_cal (arb_do_zq_cal ),
.arb_do_lmr (arb_do_lmr ),
.arb_to_chipsel (arb_to_chipsel ),
.arb_to_chip (arb_to_chip ),
.arb_to_bank (arb_to_bank ),
.arb_to_row (arb_to_row ),
.arb_to_col (arb_to_col ),
.arb_localid (arb_localid ),
.arb_dataid (arb_dataid ),
.arb_size (arb_size ),
.bg_do_write_combi (bg_do_write_combi ),
.bg_do_read_combi (bg_do_read_combi ),
.bg_do_burst_chop_combi (bg_do_burst_chop_combi ),
.bg_do_burst_terminate_combi (bg_do_burst_terminate_combi ),
.bg_do_activate_combi (bg_do_activate_combi ),
.bg_do_precharge_combi (bg_do_precharge_combi ),
.bg_to_chip_combi (bg_to_chip_combi ),
.bg_effective_size_combi (bg_effective_size_combi ),
.bg_interrupt_ready_combi (bg_interrupt_ready_combi ),
.bg_do_write (bg_do_write ),
.bg_do_read (bg_do_read ),
.bg_do_burst_chop (bg_do_burst_chop ),
.bg_do_burst_terminate (bg_do_burst_terminate ),
.bg_do_auto_precharge (bg_do_auto_precharge ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.bg_do_activate (bg_do_activate ),
.bg_do_precharge (bg_do_precharge ),
.bg_do_precharge_all (bg_do_precharge_all ),
.bg_do_refresh (bg_do_refresh ),
.bg_do_self_refresh (bg_do_self_refresh ),
.bg_do_power_down (bg_do_power_down ),
.bg_do_deep_pdown (bg_do_deep_pdown ),
.bg_do_zq_cal (bg_do_zq_cal ),
.bg_do_lmr (bg_do_lmr ),
.bg_to_chipsel (bg_to_chipsel ),
.bg_to_chip (bg_to_chip ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_col (bg_to_col ),
.bg_doing_write (bg_doing_write ),
.bg_doing_read (bg_doing_read ),
.bg_rdwr_data_valid (bg_rdwr_data_valid ),
.bg_interrupt_ready (bg_interrupt_ready ),
.bg_localid (bg_localid ),
.bg_dataid (bg_dataid ),
.bg_size (bg_size ),
.bg_effective_size (bg_effective_size )
);
//==============================================================================
// alt_mem_ddrx_addr_cmd_wrap
//------------------------------------------------------------------------------
//
// Address and command decoder block
//
// Info: Trasalate controller internal command into AFI command
//
//==============================================================================
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_to_chip = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0] | bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP ];
// wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] temp_to_bank = bg_to_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0] | bg_to_bank [2 * CFG_MEM_IF_BA_WIDTH - 1 : CFG_MEM_IF_BA_WIDTH ];
// wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] temp_to_row = bg_to_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0] | bg_to_row [2 * CFG_MEM_IF_ROW_WIDTH - 1 : CFG_MEM_IF_ROW_WIDTH];
// wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] temp_to_col = bg_to_col [CFG_MEM_IF_COL_WIDTH - 1 : 0] | bg_to_col [2 * CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_COL_WIDTH];
//
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_refresh = bg_do_refresh [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_refresh [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_power_down = bg_do_power_down [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_power_down [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_self_refresh = bg_do_self_refresh [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_self_refresh [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_precharge_all = bg_do_precharge_all [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_precharge_all [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_deep_pdown = bg_do_deep_pdown [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_deep_pdown [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_zq_cal = bg_do_zq_cal [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_zq_cal [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
alt_mem_ddrx_addr_cmd_wrap #
(
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH (CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH (CFG_AFI_IF_FR_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_LPDDR2_ENABLED (CFG_LPDDR2_ENABLED ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
.CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP (CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP (CFG_PORT_WIDTH_READ_ODT_CHIP ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD )
)
addr_cmd_wrap_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.ctl_cal_success (ctl_cal_success ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_write_odt_chip (cfg_write_odt_chip ),
.cfg_read_odt_chip (cfg_read_odt_chip ),
.cfg_burst_length (cfg_burst_length ),
.cfg_output_regd_for_afi_output (cfg_output_regd_for_afi_output ),
.bg_do_write (bg_do_write ),
.bg_do_read (bg_do_read ),
.bg_do_auto_precharge (bg_do_auto_precharge ),
.bg_do_burst_chop (bg_do_burst_chop ),
.bg_do_activate (bg_do_activate ),
.bg_do_precharge (bg_do_precharge ),
.bg_do_refresh (bg_do_refresh ),
.bg_do_power_down (bg_do_power_down ),
.bg_do_self_refresh (bg_do_self_refresh ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.bg_do_lmr (bg_do_lmr ),
.bg_do_precharge_all (bg_do_precharge_all ),
.bg_do_zq_cal (bg_do_zq_cal ),
.bg_do_lmr_read (bg_do_lmr_read ),
.bg_do_refresh_1bank (bg_do_refresh_1bank ),
.bg_do_burst_terminate (bg_do_burst_terminate ),
.bg_do_deep_pdown (bg_do_deep_pdown ),
.bg_to_chip (bg_to_chip ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_col (bg_to_col ),
.bg_to_lmr (bg_to_lmr ),
.bg_dataid (bg_dataid ),
.bg_localid (bg_localid ),
.bg_size (bg_size ),
.lmr_opcode (lmr_opcode ),
.afi_cke (afi_cke ),
.afi_cs_n (afi_cs_n ),
.afi_ras_n (afi_ras_n ),
.afi_cas_n (afi_cas_n ),
.afi_we_n (afi_we_n ),
.afi_ba (afi_ba ),
.afi_addr (afi_addr ),
.afi_rst_n (afi_rst_n ),
.afi_odt (afi_odt )
);
//==============================================================================
// alt_mem_ddrx_odt_gen
//------------------------------------------------------------------------------
//
// ODT generation block
//
// Info: Generate ODT information based on user configuration
//
//==============================================================================
// alt_mem_ddrx_odt_gen #
// (
// .CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
// .CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
// .CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
// .CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
// .CFG_OUTPUT_REGD (CFG_OUTPUT_REGD ),
// .CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
// .CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
// .CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
// .CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE )
// )
// odt_gen_inst
// (
// .ctl_clk (ctl_clk ),
// .ctl_reset_n (ctl_reset_n ),
// .cfg_type (cfg_type ),
// .cfg_tcl (cfg_tcl ),
// .cfg_cas_wr_lat (cfg_cas_wr_lat ),
// .cfg_add_lat (cfg_add_lat ),
// .cfg_write_odt_chip (cfg_write_odt_chip ),
// .cfg_read_odt_chip (cfg_read_odt_chip ),
// .cfg_burst_length (cfg_burst_length ),
// .bg_do_read (bg_do_read ),
// .bg_do_write (bg_do_write ),
// .bg_to_chip (bg_to_chip ),
// .afi_odt (afi_odt )
// );
//==============================================================================
// alt_mem_ddrx_rdwr_data_tmg
//------------------------------------------------------------------------------
//
// Read / write data timing block
//
// Info: Adjust read and write data timing based on AFI information
//
//==============================================================================
alt_mem_ddrx_rdwr_data_tmg #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_MEM_IF_DM_WIDTH (CFG_MEM_IF_DM_WIDTH ),
.CFG_WLAT_BUS_WIDTH (CFG_WLAT_BUS_WIDTH ),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_WDATA_REG (CFG_WDATA_REG ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_USE_SHADOW_REGS (CFG_USE_SHADOW_REGS )
)
rdwr_data_tmg_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_output_regd (cfg_output_regd ),
.cfg_output_regd_for_afi_output (cfg_output_regd_for_afi_output ),
.bg_do_read (bg_do_read ),
.bg_do_write (bg_do_write ),
.bg_doing_read (bg_doing_read ),
.bg_doing_write (bg_doing_write ),
.bg_rdwr_data_valid (bg_rdwr_data_valid ),
.dataid (bg_dataid ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.bg_to_chip (bg_to_chip ),
.ecc_wdata (ecc_wdata ),
.ecc_dm (ecc_dm ),
.afi_wlat (afi_wlat ),
.afi_doing_read (afi_rdata_en ),
.afi_doing_read_full (afi_rdata_en_full ),
.ecc_wdata_fifo_read (ecc_wdata_fifo_read ),
.ecc_wdata_fifo_dataid (ecc_wdata_fifo_dataid ),
.ecc_wdata_fifo_dataid_vector (ecc_wdata_fifo_dataid_vector ),
.ecc_wdata_fifo_rmw_correct (ecc_wdata_fifo_rmw_correct ),
.ecc_wdata_fifo_rmw_partial (ecc_wdata_fifo_rmw_partial ),
.ecc_wdata_fifo_read_first (ecc_wdata_fifo_read_first ),
.ecc_wdata_fifo_dataid_first (ecc_wdata_fifo_dataid_first ),
.ecc_wdata_fifo_dataid_vector_first (ecc_wdata_fifo_dataid_vector_first ),
.ecc_wdata_fifo_rmw_correct_first (ecc_wdata_fifo_rmw_correct_first ),
.ecc_wdata_fifo_rmw_partial_first (ecc_wdata_fifo_rmw_partial_first ),
.ecc_wdata_fifo_first_vector (ecc_wdata_fifo_first_vector ),
.ecc_wdata_fifo_read_last (ecc_wdata_fifo_read_last ),
.ecc_wdata_fifo_dataid_last (ecc_wdata_fifo_dataid_last ),
.ecc_wdata_fifo_dataid_vector_last (ecc_wdata_fifo_dataid_vector_last ),
.ecc_wdata_fifo_rmw_correct_last (ecc_wdata_fifo_rmw_correct_last ),
.ecc_wdata_fifo_rmw_partial_last (ecc_wdata_fifo_rmw_partial_last ),
.afi_rrank (int_afi_rrank ),
.afi_wrank (int_afi_wrank ),
.afi_dqs_burst (afi_dqs_burst ),
.afi_wdata_valid (afi_wdata_valid ),
.afi_wdata (afi_wdata ),
.afi_dm (afi_dm )
);
//==============================================================================
// alt_mem_ddrx_wdata_path
//------------------------------------------------------------------------------
//
// Write data path block
//
// Info: Handles write data processing
//
//==============================================================================
// match datapath id width, with command path id width
generate
begin : gen_resolve_datap_id
genvar i;
for (i = 0;i < CFG_DRAM_WLAT_GROUP;i = i + 1)
begin : write_dataid_per_dqs_group
if (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign ecc_wdata_wrdataid [(i + 1) * CFG_WRDATA_ID_WIDTH - 1 : i * CFG_WRDATA_ID_WIDTH ] = ecc_wdata_fifo_dataid [(i * CFG_DATA_ID_WIDTH ) + CFG_WRDATA_ID_WIDTH - 1 : i * CFG_DATA_ID_WIDTH ];
assign ecc_wdata_wrdataid_vector [(i + 1) * CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_WRDATA_VEC_ID_WIDTH] = ecc_wdata_fifo_dataid_vector [(i * CFG_DATAID_ARRAY_DEPTH) + CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_DATAID_ARRAY_DEPTH];
end
else // (CFG_WRDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
begin
assign ecc_wdata_wrdataid [(i + 1) * CFG_WRDATA_ID_WIDTH - 1 : i * CFG_WRDATA_ID_WIDTH ] = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid [(i * CFG_DATA_ID_WIDTH ) + CFG_WRDATA_ID_WIDTH - 1 : i * CFG_DATA_ID_WIDTH ]};
assign ecc_wdata_wrdataid_vector [(i + 1) * CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_WRDATA_VEC_ID_WIDTH] = {{CFG_DATA_ID_REMAINDER {1'b0}},ecc_wdata_fifo_dataid_vector [(i * CFG_DATAID_ARRAY_DEPTH) + CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_DATAID_ARRAY_DEPTH]};
end
end
if (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign wdatap_free_id_dataid = {{(CFG_DATA_ID_WIDTH-CFG_WRDATA_ID_WIDTH){1'b0}},wdatap_free_id_wrdataid};
assign ecc_wdata_wrdataid_first = ecc_wdata_fifo_dataid_first [CFG_WRDATA_ID_WIDTH - 1 : 0];
assign ecc_wdata_wrdataid_vector_first = ecc_wdata_fifo_dataid_vector_first [CFG_WRDATA_ID_WIDTH_SQRD -1 : 0];
assign ecc_wdata_wrdataid_last = ecc_wdata_fifo_dataid_last [CFG_WRDATA_ID_WIDTH - 1 : 0];
assign ecc_wdata_wrdataid_vector_last = ecc_wdata_fifo_dataid_vector_last [CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0];
end
else // (CFG_WRDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
begin
assign wdatap_free_id_dataid = wdatap_free_id_wrdataid[CFG_DATA_ID_WIDTH-1:0];
assign ecc_wdata_wrdataid_first = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid_first};
assign ecc_wdata_wrdataid_vector_first = {{CFG_DATA_ID_REMAINDER{1'b0}},ecc_wdata_fifo_dataid_vector_first};
assign ecc_wdata_wrdataid_last = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid_last};
assign ecc_wdata_wrdataid_vector_last = {{CFG_DATA_ID_REMAINDER{1'b0}},ecc_wdata_fifo_dataid_vector_last};
end
if (CFG_RDDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign rdatap_free_id_dataid = {{(CFG_DATA_ID_WIDTH-CFG_RDDATA_ID_WIDTH){1'b0}},rdatap_free_id_rddataid};
assign bg_rddataid = bg_dataid[CFG_RDDATA_ID_WIDTH-1:0];
end
else if(CFG_RDDATA_ID_WIDTH > CFG_DATA_ID_WIDTH)
begin
assign rdatap_free_id_dataid = rdatap_free_id_rddataid[CFG_DATA_ID_WIDTH-1:0];
assign bg_rddataid = {{(CFG_RDDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},bg_dataid};
end
else // CFG_RDDATA_ID_WIDTH == CFG_DATA_ID_WIDTH
begin
assign rdatap_free_id_dataid = rdatap_free_id_rddataid[CFG_DATA_ID_WIDTH-1:0];
assign bg_rddataid = bg_dataid;
end
end
endgenerate
alt_mem_ddrx_wdata_path #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_WRDATA_ID_WIDTH ),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP ),
.CFG_LOCAL_WLAT_GROUP (CFG_LOCAL_WLAT_GROUP ),
.CFG_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_BUFFER_ADDR_WIDTH (CFG_WRBUFFER_ADDR_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_WDATA_REG (CFG_WDATA_REG ),
.CFG_PARTIAL_BE_PER_WORD_ENABLE (CFG_PARTIAL_BE_PER_WORD_ENABLE ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_ENABLE_AUTO_CORR (CFG_PORT_WIDTH_ENABLE_AUTO_CORR),
.CFG_PORT_WIDTH_ENABLE_NO_DM (CFG_PORT_WIDTH_ENABLE_NO_DM ),
.CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES (CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES),
.CFG_PORT_WIDTH_INTERFACE_WIDTH (CFG_PORT_WIDTH_INTERFACE_WIDTH ),
.CFG_ECC_BE_ALLLOW_RMW (CFG_ECC_BE_ALLLOW_RMW)
)
wdata_path_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_auto_corr (cfg_enable_auto_corr ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_enable_ecc_code_overwrites (cfg_enable_ecc_code_overwrites ),
.cfg_interface_width (cfg_interface_width ),
.wdatap_free_id_valid (wdatap_free_id_valid ),
.wdatap_free_id_dataid (wdatap_free_id_wrdataid ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_write (proc_write ),
.tbp_load_index (tbp_load_index ),
.proc_size (proc_size ),
.wr_data_mem_full (wr_data_mem_full ),
.write_data_en (write_data_valid ),
.write_data (write_data ),
.byte_en (byte_en ),
.data_complete (data_complete ),
.data_rmw_complete (data_rmw_complete ),
.data_rmw_fetch (data_rmw_fetch ),
.data_partial_be (data_partial_be ),
.doing_write (ecc_wdata_fifo_read ),
.dataid (ecc_wdata_wrdataid ),
.dataid_vector (ecc_wdata_wrdataid_vector ),
.rdwr_data_valid (ecc_wdata_fifo_read ),
.rmw_correct (ecc_wdata_fifo_rmw_correct ),
.rmw_partial (ecc_wdata_fifo_rmw_partial ),
.doing_write_first (ecc_wdata_fifo_read_first ),
.dataid_first (ecc_wdata_wrdataid_first ),
.dataid_vector_first (ecc_wdata_wrdataid_vector_first ),
.rdwr_data_valid_first (ecc_wdata_fifo_read_first ),
.rmw_correct_first (ecc_wdata_fifo_rmw_correct_first ),
.rmw_partial_first (ecc_wdata_fifo_rmw_partial_first ),
.doing_write_first_vector (ecc_wdata_fifo_first_vector ),
.rdwr_data_valid_first_vector (ecc_wdata_fifo_first_vector ),
.doing_write_last (ecc_wdata_fifo_read_last ),
.dataid_last (ecc_wdata_wrdataid_last ),
.dataid_vector_last (ecc_wdata_wrdataid_vector_last ),
.rdwr_data_valid_last (ecc_wdata_fifo_read_last ),
.rmw_correct_last (ecc_wdata_fifo_rmw_correct_last ),
.rmw_partial_last (ecc_wdata_fifo_rmw_partial_last ),
.wdatap_data (wdatap_data ),
.wdatap_rmw_partial_data (wdatap_rmw_partial_data ),
.wdatap_rmw_correct_data (wdatap_rmw_correct_data ),
.wdatap_rmw_partial (wdatap_rmw_partial ),
.wdatap_rmw_correct (wdatap_rmw_correct ),
.wdatap_dm (wdatap_dm ),
.wdatap_ecc_code (wdatap_ecc_code ),
.wdatap_ecc_code_overwrite (wdatap_ecc_code_overwrite ),
.rmwfifo_data_valid (rmwfifo_data_valid ),
.rmwfifo_data (rmwfifo_data ),
.rmwfifo_ecc_dbe (rmwfifo_ecc_dbe ),
.rmwfifo_ecc_code (rmwfifo_ecc_code )
);
//==============================================================================
// alt_mem_ddrx_rdata_path
//------------------------------------------------------------------------------
//
// Read data path block
//
// Info: Handles read data processing
//
//==============================================================================
alt_mem_ddrx_rdata_path #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_RDDATA_ID_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_BUFFER_ADDR_WIDTH (CFG_RDBUFFER_ADDR_WIDTH ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MAX_READ_CMD_NUM_WIDTH (CFG_MAX_PENDING_RD_CMD_WIDTH ),
.CFG_RDATA_RETURN_MODE (CFG_RDATA_RETURN_MODE ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_ERRCMD_FIFO_ADDR_WIDTH (CFG_ERRCMD_FIFO_ADDR_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_ENABLE_AUTO_CORR (CFG_PORT_WIDTH_ENABLE_AUTO_CORR ),
.CFG_PORT_WIDTH_ENABLE_NO_DM (CFG_PORT_WIDTH_ENABLE_NO_DM ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ADDR_ORDER (CFG_PORT_WIDTH_ADDR_ORDER ),
.CFG_PORT_WIDTH_COL_ADDR_WIDTH (CFG_PORT_WIDTH_COL_ADDR_WIDTH ),
.CFG_PORT_WIDTH_ROW_ADDR_WIDTH (CFG_PORT_WIDTH_ROW_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BANK_ADDR_WIDTH (CFG_PORT_WIDTH_BANK_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH (CFG_PORT_WIDTH_CS_ADDR_WIDTH ),
.CFG_ERRCMD_FIFO_REG (CFG_ERRCMD_FIFO_REG )
)
rdata_path_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_auto_corr (cfg_enable_auto_corr ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_burst_length (cfg_burst_length ),
.cfg_addr_order (cfg_addr_order ),
.cfg_col_addr_width (cfg_col_addr_width ),
.cfg_row_addr_width (cfg_row_addr_width ),
.cfg_bank_addr_width (cfg_bank_addr_width ),
.cfg_cs_addr_width (cfg_cs_addr_width ),
.rdatap_free_id_valid (rdatap_free_id_valid ),
.rdatap_free_id_dataid (rdatap_free_id_rddataid ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_read (proc_read ),
.proc_size (proc_size ),
.proc_localid (proc_localid ),
.read_data_valid (read_data_valid ),
.read_data (read_data ),
.read_data_error (read_data_error ),
.read_data_localid (read_data_localid ),
.bg_do_read (bg_do_read ),
.bg_to_chipsel (bg_to_chipsel ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_column (bg_to_col ),
.bg_dataid (bg_rddataid ),
.bg_localid (bg_localid ),
.bg_size (bg_size ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.ecc_rdata (ecc_rdata ),
.ecc_rdatav (ecc_rdata_valid ),
.ecc_sbe (ecc_sbe ),
.ecc_dbe (ecc_dbe ),
.ecc_code (ecc_code ),
.errcmd_ready (errcmd_ready ),
.errcmd_valid (errcmd_valid ),
.errcmd_chipsel (errcmd_chipsel ),
.errcmd_bank (errcmd_bank ),
.errcmd_row (errcmd_row ),
.errcmd_column (errcmd_column ),
.errcmd_size (errcmd_size ),
.errcmd_localid (errcmd_localid ),
.rdatap_rcvd_addr (rdatap_rcvd_addr ),
.rdatap_rcvd_cmd (rdatap_rcvd_cmd ),
.rdatap_rcvd_corr_dropped (rdatap_rcvd_corr_dropped ),
.rmwfifo_data_valid (rmwfifo_data_valid ),
.rmwfifo_data (rmwfifo_data ),
.rmwfifo_ecc_dbe (rmwfifo_ecc_dbe ),
.rmwfifo_ecc_code (rmwfifo_ecc_code )
);
//==============================================================================
// alt_mem_ddrx_ecc_encoder_decoder_wrapper
//------------------------------------------------------------------------------
//
// ECC encoder/decoder block
//
// Info: Encode write data and decode read data, correct single bit error
// and detect double bit errors
//
//==============================================================================
alt_mem_ddrx_ecc_encoder_decoder_wrapper #
(
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_ECC_DEC_REG (CFG_ECC_DEC_REG ),
.CFG_ECC_DECODER_REG (CFG_ECC_DECODER_REG ),
.CFG_ECC_RDATA_REG (CFG_ECC_RDATA_REG ),
.CFG_PORT_WIDTH_INTERFACE_WIDTH (CFG_PORT_WIDTH_INTERFACE_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_GEN_SBE (CFG_PORT_WIDTH_GEN_SBE ),
.CFG_PORT_WIDTH_GEN_DBE (CFG_PORT_WIDTH_GEN_DBE ),
.CFG_PORT_WIDTH_ENABLE_INTR (CFG_PORT_WIDTH_ENABLE_INTR ),
.CFG_PORT_WIDTH_MASK_SBE_INTR (CFG_PORT_WIDTH_MASK_SBE_INTR ),
.CFG_PORT_WIDTH_MASK_DBE_INTR (CFG_PORT_WIDTH_MASK_DBE_INTR ),
.CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR (CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR),
.CFG_PORT_WIDTH_CLR_INTR (CFG_PORT_WIDTH_CLR_INTR ),
.STS_PORT_WIDTH_SBE_ERROR (STS_PORT_WIDTH_SBE_ERROR ),
.STS_PORT_WIDTH_DBE_ERROR (STS_PORT_WIDTH_DBE_ERROR ),
.STS_PORT_WIDTH_SBE_COUNT (STS_PORT_WIDTH_SBE_COUNT ),
.STS_PORT_WIDTH_DBE_COUNT (STS_PORT_WIDTH_DBE_COUNT ),
.STS_PORT_WIDTH_CORR_DROP_ERROR (STS_PORT_WIDTH_CORR_DROP_ERROR ),
.STS_PORT_WIDTH_CORR_DROP_COUNT (STS_PORT_WIDTH_CORR_DROP_COUNT )
)
ecc_encoder_decoder_wrapper_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_interface_width (cfg_interface_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_gen_sbe (cfg_gen_sbe ),
.cfg_gen_dbe (cfg_gen_dbe ),
.cfg_enable_intr (cfg_enable_intr ),
.cfg_mask_sbe_intr (cfg_mask_sbe_intr ),
.cfg_mask_dbe_intr (cfg_mask_dbe_intr ),
.cfg_mask_corr_dropped_intr (cfg_mask_corr_dropped_intr ),
.cfg_clr_intr (cfg_clr_intr ),
.wdatap_dm (wdatap_dm ),
.wdatap_data (wdatap_data ),
.wdatap_rmw_partial_data (wdatap_rmw_partial_data ),
.wdatap_rmw_correct_data (wdatap_rmw_correct_data ),
.wdatap_rmw_partial (wdatap_rmw_partial ),
.wdatap_rmw_correct (wdatap_rmw_correct ),
.wdatap_ecc_code (wdatap_ecc_code ),
.wdatap_ecc_code_overwrite (wdatap_ecc_code_overwrite ),
.rdatap_rcvd_addr (rdatap_rcvd_addr ),
.rdatap_rcvd_cmd (rdatap_rcvd_cmd ),
.rdatap_rcvd_corr_dropped (rdatap_rcvd_corr_dropped ),
.afi_rdata (afi_rdata ),
.afi_rdata_valid (afi_rdata_valid ),
.ecc_rdata (ecc_rdata ),
.ecc_rdata_valid (ecc_rdata_valid ),
.ecc_dm (ecc_dm ),
.ecc_wdata (ecc_wdata ),
.ecc_sbe (ecc_sbe ),
.ecc_dbe (ecc_dbe ),
.ecc_code (ecc_code ),
.ecc_interrupt (ecc_interrupt ),
.sts_sbe_error (sts_sbe_error ),
.sts_dbe_error (sts_dbe_error ),
.sts_sbe_count (sts_sbe_count ),
.sts_dbe_count (sts_dbe_count ),
.sts_err_addr (sts_err_addr ),
.sts_corr_dropped (sts_corr_dropped ),
.sts_corr_dropped_count (sts_corr_dropped_count ),
.sts_corr_dropped_addr (sts_corr_dropped_addr )
);
//==============================================================================
// alt_mem_ddrx_sideband
//------------------------------------------------------------------------------
//
// Sideband block
//
// Info: Monitor and issue sideband specific commands such as user/auto
// refresh, self refresh, power down, deep power down,
// precharge all and zq calibration commands
//
//==============================================================================
alt_mem_ddrx_sideband #
(
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH (CFG_PORT_WIDTH_CS_ADDR_WIDTH ),
.CFG_MEM_IF_CLK_PAIR_COUNT (CFG_MEM_IF_CLK_PAIR_COUNT ),
.CFG_RANK_TIMER_OUTPUT_REG (CFG_RANK_TIMER_OUTPUT_REG ),
.T_PARAM_ARF_TO_VALID_WIDTH (T_PARAM_ARF_TO_VALID_WIDTH ),
.T_PARAM_ARF_PERIOD_WIDTH (T_PARAM_ARF_PERIOD_WIDTH ),
.T_PARAM_PCH_ALL_TO_VALID_WIDTH (T_PARAM_PCH_ALL_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_VALID_WIDTH (T_PARAM_SRF_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_ZQ_CAL_WIDTH (T_PARAM_SRF_TO_ZQ_CAL_WIDTH ),
.T_PARAM_PDN_TO_VALID_WIDTH (T_PARAM_PDN_TO_VALID_WIDTH ),
.T_PARAM_PDN_PERIOD_WIDTH (T_PARAM_PDN_PERIOD_WIDTH ),
.T_PARAM_POWER_SAVING_EXIT_WIDTH (T_PARAM_POWER_SAVING_EXIT_WIDTH ),
.T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH (T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH )
)
sideband_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.rfsh_req (rfsh_req ),
.rfsh_chip (rfsh_chip ),
.rfsh_ack (rfsh_ack ),
.zqcal_req (zqcal_req ),
.self_rfsh_req (self_rfsh_req ),
.self_rfsh_chip (self_rfsh_chip ),
.self_rfsh_ack (self_rfsh_ack ),
.deep_powerdn_req (deep_powerdn_req ),
.deep_powerdn_chip (deep_powerdn_chip ),
.deep_powerdn_ack (deep_powerdn_ack ),
.power_down_ack (power_down_ack ),
.stall_row_arbiter (stall_row_arbiter ),
.stall_col_arbiter (stall_col_arbiter ),
.stall_chip (stall_chip ),
.sb_do_precharge_all (sb_do_precharge_all ),
.sb_do_refresh (sb_do_refresh ),
.sb_do_self_refresh (sb_do_self_refresh ),
.sb_do_power_down (sb_do_power_down ),
.sb_do_deep_pdown (sb_do_deep_pdown ),
.sb_do_zq_cal (sb_do_zq_cal ),
.sb_tbp_precharge_all (sb_tbp_precharge_all ),
.ctl_mem_clk_disable (ctl_sb_mem_clk_disable ),
.ctl_cal_req (ctl_sb_cal_req ),
.ctl_init_req (ctl_sb_init_req ),
.ctl_cal_success (ctl_cal_success ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.tbp_chipsel (tbp_chipsel ),
.tbp_load (tbp_load ),
.t_param_arf_to_valid (t_param_arf_to_valid ),
.t_param_arf_period (t_param_arf_period ),
.t_param_pch_all_to_valid (t_param_pch_all_to_valid ),
.t_param_srf_to_valid (t_param_srf_to_valid ),
.t_param_srf_to_zq_cal (t_param_srf_to_zq_cal ),
.t_param_pdn_to_valid (t_param_pdn_to_valid ),
.t_param_pdn_period (t_param_pdn_period ),
.t_param_power_saving_exit (t_param_power_saving_exit ),
.t_param_mem_clk_entry_cycles (t_param_mem_clk_entry_cycles ),
.tbp_empty (tbp_empty ),
.tbp_bank_closed (tbp_bank_closed ),
.tbp_timer_ready (tbp_timer_ready ),
.row_grant (or_row_grant ),
.col_grant (or_col_grant ),
.afi_ctl_refresh_done (afi_ctl_refresh_done ),
.afi_seq_busy (afi_seq_busy ),
.afi_ctl_long_idle (afi_ctl_long_idle ),
.cfg_cs_addr_width (cfg_cs_addr_width ),
.cfg_enable_dqs_tracking (cfg_enable_dqs_tracking ),
.cfg_user_rfsh (cfg_user_rfsh ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_regdimm_enable (cfg_regdimm_enable ),
.sideband_in_refresh (sideband_in_refresh )
);
//==============================================================================
// alt_mem_ddrx_rank_timer
//------------------------------------------------------------------------------
//
// Rank timer block
//
// Info: Monitor rank specific timing parameter for activate, precharge,
// read and write commands
//
//==============================================================================
alt_mem_ddrx_rank_timer #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_RANK_TIMER_OUTPUT_REG (CFG_RANK_TIMER_OUTPUT_REG ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.T_PARAM_FOUR_ACT_TO_ACT_WIDTH (T_PARAM_FOUR_ACT_TO_ACT_WIDTH ),
.T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH (T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH ),
.T_PARAM_WR_TO_WR_WIDTH (T_PARAM_WR_TO_WR_WIDTH ),
.T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_RD_WIDTH (T_PARAM_WR_TO_RD_WIDTH ),
.T_PARAM_WR_TO_RD_BC_WIDTH (T_PARAM_WR_TO_RD_BC_WIDTH ),
.T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_RD_WIDTH (T_PARAM_RD_TO_RD_WIDTH ),
.T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_WR_WIDTH (T_PARAM_RD_TO_WR_WIDTH ),
.T_PARAM_RD_TO_WR_BC_WIDTH (T_PARAM_RD_TO_WR_BC_WIDTH ),
.T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH )
)
rank_timer_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.t_param_four_act_to_act (t_param_four_act_to_act ),
.t_param_act_to_act_diff_bank (t_param_act_to_act_diff_bank ),
.t_param_wr_to_wr (t_param_wr_to_wr ),
.t_param_wr_to_wr_diff_chip (t_param_wr_to_wr_diff_chip ),
.t_param_wr_to_rd (t_param_wr_to_rd ),
.t_param_wr_to_rd_bc (t_param_wr_to_rd_bc ),
.t_param_wr_to_rd_diff_chip (t_param_wr_to_rd_diff_chip ),
.t_param_rd_to_rd (t_param_rd_to_rd ),
.t_param_rd_to_rd_diff_chip (t_param_rd_to_rd_diff_chip ),
.t_param_rd_to_wr (t_param_rd_to_wr ),
.t_param_rd_to_wr_bc (t_param_rd_to_wr_bc ),
.t_param_rd_to_wr_diff_chip (t_param_rd_to_wr_diff_chip ),
.bg_do_write (bg_do_write_combi ),
.bg_do_read (bg_do_read_combi ),
.bg_do_burst_chop (bg_do_burst_chop_combi ),
.bg_do_burst_terminate (bg_do_burst_terminate_combi ),
.bg_do_activate (bg_do_activate_combi ),
.bg_do_precharge (bg_do_precharge_combi ),
.bg_to_chip (bg_to_chip_combi ),
.bg_effective_size (bg_effective_size_combi ),
.bg_interrupt_ready (bg_interrupt_ready_combi ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.tbp_chipsel (tbp_chipsel ),
.tbp_load (tbp_load ),
.stall_chip (stall_chip ),
.can_activate (can_activate ),
.can_precharge (can_precharge ),
.can_read (can_read ),
.can_write (can_write )
);
//==============================================================================
// alt_mem_ddrx_timing_param
//------------------------------------------------------------------------------
//
// Timing parameter block
//
// Info: Pre-calculate required timing parameters for each memory commands
// based on memory type
//
//==============================================================================
alt_mem_ddrx_timing_param #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_TRRD (CFG_PORT_WIDTH_TRRD ),
.CFG_PORT_WIDTH_TFAW (CFG_PORT_WIDTH_TFAW ),
.CFG_PORT_WIDTH_TRFC (CFG_PORT_WIDTH_TRFC ),
.CFG_PORT_WIDTH_TREFI (CFG_PORT_WIDTH_TREFI ),
.CFG_PORT_WIDTH_TRCD (CFG_PORT_WIDTH_TRCD ),
.CFG_PORT_WIDTH_TRP (CFG_PORT_WIDTH_TRP ),
.CFG_PORT_WIDTH_TWR (CFG_PORT_WIDTH_TWR ),
.CFG_PORT_WIDTH_TWTR (CFG_PORT_WIDTH_TWTR ),
.CFG_PORT_WIDTH_TRTP (CFG_PORT_WIDTH_TRTP ),
.CFG_PORT_WIDTH_TRAS (CFG_PORT_WIDTH_TRAS ),
.CFG_PORT_WIDTH_TRC (CFG_PORT_WIDTH_TRC ),
.CFG_PORT_WIDTH_TCCD (CFG_PORT_WIDTH_TCCD ),
.CFG_PORT_WIDTH_TMRD (CFG_PORT_WIDTH_TMRD ),
.CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES (CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES ),
.CFG_PORT_WIDTH_PDN_EXIT_CYCLES (CFG_PORT_WIDTH_PDN_EXIT_CYCLES ),
.CFG_PORT_WIDTH_AUTO_PD_CYCLES (CFG_PORT_WIDTH_AUTO_PD_CYCLES ),
.CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES (CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES ),
.CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES (CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD ),
.T_PARAM_ACT_TO_RDWR_WIDTH (T_PARAM_ACT_TO_RDWR_WIDTH ),
.T_PARAM_ACT_TO_PCH_WIDTH (T_PARAM_ACT_TO_PCH_WIDTH ),
.T_PARAM_ACT_TO_ACT_WIDTH (T_PARAM_ACT_TO_ACT_WIDTH ),
.T_PARAM_RD_TO_RD_WIDTH (T_PARAM_RD_TO_RD_WIDTH ),
.T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_WR_WIDTH (T_PARAM_RD_TO_WR_WIDTH ),
.T_PARAM_RD_TO_WR_BC_WIDTH (T_PARAM_RD_TO_WR_BC_WIDTH ),
.T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_PCH_WIDTH (T_PARAM_RD_TO_PCH_WIDTH ),
.T_PARAM_RD_AP_TO_VALID_WIDTH (T_PARAM_RD_AP_TO_VALID_WIDTH ),
.T_PARAM_WR_TO_WR_WIDTH (T_PARAM_WR_TO_WR_WIDTH ),
.T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_RD_WIDTH (T_PARAM_WR_TO_RD_WIDTH ),
.T_PARAM_WR_TO_RD_BC_WIDTH (T_PARAM_WR_TO_RD_BC_WIDTH ),
.T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_PCH_WIDTH (T_PARAM_WR_TO_PCH_WIDTH ),
.T_PARAM_WR_AP_TO_VALID_WIDTH (T_PARAM_WR_AP_TO_VALID_WIDTH ),
.T_PARAM_PCH_TO_VALID_WIDTH (T_PARAM_PCH_TO_VALID_WIDTH ),
.T_PARAM_PCH_ALL_TO_VALID_WIDTH (T_PARAM_PCH_ALL_TO_VALID_WIDTH ),
.T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH (T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH ),
.T_PARAM_FOUR_ACT_TO_ACT_WIDTH (T_PARAM_FOUR_ACT_TO_ACT_WIDTH ),
.T_PARAM_ARF_TO_VALID_WIDTH (T_PARAM_ARF_TO_VALID_WIDTH ),
.T_PARAM_PDN_TO_VALID_WIDTH (T_PARAM_PDN_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_VALID_WIDTH (T_PARAM_SRF_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_ZQ_CAL_WIDTH (T_PARAM_SRF_TO_ZQ_CAL_WIDTH ),
.T_PARAM_ARF_PERIOD_WIDTH (T_PARAM_ARF_PERIOD_WIDTH ),
.T_PARAM_PDN_PERIOD_WIDTH (T_PARAM_PDN_PERIOD_WIDTH ),
.T_PARAM_POWER_SAVING_EXIT_WIDTH (T_PARAM_POWER_SAVING_EXIT_WIDTH ),
.T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH (T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH )
)
timing_param_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.cfg_type (cfg_type ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_tcl (cfg_tcl ),
.cfg_trrd (cfg_trrd ),
.cfg_tfaw (cfg_tfaw ),
.cfg_trfc (cfg_trfc ),
.cfg_trefi (cfg_trefi ),
.cfg_trcd (cfg_trcd ),
.cfg_trp (cfg_trp ),
.cfg_twr (cfg_twr ),
.cfg_twtr (cfg_twtr ),
.cfg_trtp (cfg_trtp ),
.cfg_tras (cfg_tras ),
.cfg_trc (cfg_trc ),
.cfg_tccd (cfg_tccd ),
.cfg_tmrd (cfg_tmrd ),
.cfg_self_rfsh_exit_cycles (cfg_self_rfsh_exit_cycles ),
.cfg_pdn_exit_cycles (cfg_pdn_exit_cycles ),
.cfg_auto_pd_cycles (cfg_auto_pd_cycles ),
.cfg_power_saving_exit_cycles (cfg_power_saving_exit_cycles ),
.cfg_mem_clk_entry_cycles (cfg_mem_clk_entry_cycles ),
.cfg_extra_ctl_clk_act_to_rdwr (cfg_extra_ctl_clk_act_to_rdwr ),
.cfg_extra_ctl_clk_act_to_pch (cfg_extra_ctl_clk_act_to_pch ),
.cfg_extra_ctl_clk_act_to_act (cfg_extra_ctl_clk_act_to_act ),
.cfg_extra_ctl_clk_rd_to_rd (cfg_extra_ctl_clk_rd_to_rd ),
.cfg_extra_ctl_clk_rd_to_rd_diff_chip (cfg_extra_ctl_clk_rd_to_rd_diff_chip ),
.cfg_extra_ctl_clk_rd_to_wr (cfg_extra_ctl_clk_rd_to_wr ),
.cfg_extra_ctl_clk_rd_to_wr_bc (cfg_extra_ctl_clk_rd_to_wr_bc ),
.cfg_extra_ctl_clk_rd_to_wr_diff_chip (cfg_extra_ctl_clk_rd_to_wr_diff_chip ),
.cfg_extra_ctl_clk_rd_to_pch (cfg_extra_ctl_clk_rd_to_pch ),
.cfg_extra_ctl_clk_rd_ap_to_valid (cfg_extra_ctl_clk_rd_ap_to_valid ),
.cfg_extra_ctl_clk_wr_to_wr (cfg_extra_ctl_clk_wr_to_wr ),
.cfg_extra_ctl_clk_wr_to_wr_diff_chip (cfg_extra_ctl_clk_wr_to_wr_diff_chip ),
.cfg_extra_ctl_clk_wr_to_rd (cfg_extra_ctl_clk_wr_to_rd ),
.cfg_extra_ctl_clk_wr_to_rd_bc (cfg_extra_ctl_clk_wr_to_rd_bc ),
.cfg_extra_ctl_clk_wr_to_rd_diff_chip (cfg_extra_ctl_clk_wr_to_rd_diff_chip ),
.cfg_extra_ctl_clk_wr_to_pch (cfg_extra_ctl_clk_wr_to_pch ),
.cfg_extra_ctl_clk_wr_ap_to_valid (cfg_extra_ctl_clk_wr_ap_to_valid ),
.cfg_extra_ctl_clk_pch_to_valid (cfg_extra_ctl_clk_pch_to_valid ),
.cfg_extra_ctl_clk_pch_all_to_valid (cfg_extra_ctl_clk_pch_all_to_valid ),
.cfg_extra_ctl_clk_act_to_act_diff_bank (cfg_extra_ctl_clk_act_to_act_diff_bank ),
.cfg_extra_ctl_clk_four_act_to_act (cfg_extra_ctl_clk_four_act_to_act ),
.cfg_extra_ctl_clk_arf_to_valid (cfg_extra_ctl_clk_arf_to_valid ),
.cfg_extra_ctl_clk_pdn_to_valid (cfg_extra_ctl_clk_pdn_to_valid ),
.cfg_extra_ctl_clk_srf_to_valid (cfg_extra_ctl_clk_srf_to_valid ),
.cfg_extra_ctl_clk_srf_to_zq_cal (cfg_extra_ctl_clk_srf_to_zq_cal ),
.cfg_extra_ctl_clk_arf_period (cfg_extra_ctl_clk_arf_period ),
.cfg_extra_ctl_clk_pdn_period (cfg_extra_ctl_clk_pdn_period ),
.t_param_act_to_rdwr (t_param_act_to_rdwr ),
.t_param_act_to_pch (t_param_act_to_pch ),
.t_param_act_to_act (t_param_act_to_act ),
.t_param_rd_to_rd (t_param_rd_to_rd ),
.t_param_rd_to_rd_diff_chip (t_param_rd_to_rd_diff_chip ),
.t_param_rd_to_wr (t_param_rd_to_wr ),
.t_param_rd_to_wr_bc (t_param_rd_to_wr_bc ),
.t_param_rd_to_wr_diff_chip (t_param_rd_to_wr_diff_chip ),
.t_param_rd_to_pch (t_param_rd_to_pch ),
.t_param_rd_ap_to_valid (t_param_rd_ap_to_valid ),
.t_param_wr_to_wr (t_param_wr_to_wr ),
.t_param_wr_to_wr_diff_chip (t_param_wr_to_wr_diff_chip ),
.t_param_wr_to_rd (t_param_wr_to_rd ),
.t_param_wr_to_rd_bc (t_param_wr_to_rd_bc ),
.t_param_wr_to_rd_diff_chip (t_param_wr_to_rd_diff_chip ),
.t_param_wr_to_pch (t_param_wr_to_pch ),
.t_param_wr_ap_to_valid (t_param_wr_ap_to_valid ),
.t_param_pch_to_valid (t_param_pch_to_valid ),
.t_param_pch_all_to_valid (t_param_pch_all_to_valid ),
.t_param_act_to_act_diff_bank (t_param_act_to_act_diff_bank ),
.t_param_four_act_to_act (t_param_four_act_to_act ),
.t_param_arf_to_valid (t_param_arf_to_valid ),
.t_param_pdn_to_valid (t_param_pdn_to_valid ),
.t_param_srf_to_valid (t_param_srf_to_valid ),
.t_param_srf_to_zq_cal (t_param_srf_to_zq_cal ),
.t_param_arf_period (t_param_arf_period ),
.t_param_pdn_period (t_param_pdn_period ),
.t_param_power_saving_exit (t_param_power_saving_exit ),
.t_param_mem_clk_entry_cycles (t_param_mem_clk_entry_cycles )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A31OI_BEHAVIORAL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a31oi (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_BEHAVIORAL_V |
module project (input wrEnable, input [4:0] wrReg, input [4:0] rdReg1, input [4:0] rdReg2, input clk, input [3:0] opCode, input [4:0] shiftAmt, output signed [31:0] result, input selCh, input [31:0] selData);
wire [31:0] selected;
wire signed [31:0] rdData1;
wire signed [31:0] rdData2;
registerFile regFile1 (wrEnable, wrReg, selected, rdReg1, rdData1, rdReg2, rdData2, clk);
alu alu1 (rdData1, rdData2, opCode, shiftAmt, result);
mux m1 (selCh, selData, result, selected);
endmodule
module project_tb;
reg wrEnable;
reg [4:0] wrReg;
reg [4:0] rdReg1;
reg [4:0] rdReg2;
reg clk;
reg [3:0] opCode;
reg [4:0] shiftAmt;
wire signed [31:0] result;
reg selCh;
reg [31:0] selData;
always begin #5 clk = ~clk; end
initial begin
$monitor ("Your result = %d", result);
clk = 0; selCh = 0;
#10 $display ("Register file's 1st register = 1."); wrEnable = 1; wrReg = 0; selData = 1;
#10 $display ("Register file's 2nd register = 7."); wrReg = 1; selData = 7; #10 wrEnable = 0;
#10 $display ("Choosing register file's 1st and 2nd registers as it's outputs, and adding both."); rdReg1 = 0; rdReg2 = 1; opCode = 0;
#10 $display ("Subtracting both."); opCode = 1;
#10 $display ("Changing 2nd register = 0 and subtrcating both again."); wrEnable = 1; selData = 0; #10 wrEnable = 0;
#10 $display ("Putting both registers at the terminals of an AND gate."); opCode = 2;
#10 $display ("Putting both registers at the terminals of an OR gate."); opCode = 3;
#10 $display ("Shifting 1st register's binary value 3 digits to the left."); shiftAmt = 3; opCode = 4;
#10 $display ("Register file's 1st register = last operation's answer, and shifting it's binary value 3 digits to the left."); wrEnable = 1; wrReg = 0; selCh = 1; #10 wrEnable = 0;
#10 $display ("Shifting 1st register's binary value 2 digits to the right logicaly."); shiftAmt = 2; opCode = 5;
#10 $display ("Changing 1st register = -9 and shifting it's binary value 2 digits to the right logicaly."); wrEnable = 1; wrReg = 0; selCh = 0; selData = -9; #10 wrEnable = 0; // It'll give an unrelated answer because of the negative number.
#10 $display ("Shifting 1st register's binary value 1 digits to the right arithmeticaly."); shiftAmt = 1; opCode = 6;
#10 $display ("Is 1st register's value greater than 2nd register's value?"); opCode = 7;
#10 $display ("Is 1st register's value less than 2nd register's value?"); opCode = 8;
end
project p1 (wrEnable, wrReg, rdReg1, rdReg2, clk, opCode, shiftAmt, result, selCh, selData);
endmodule
|
//==========================================
// Function : Asynchronous FIFO (w/ 2 asynchronous clocks).
// Coder : Alex Claros F.
// Date : 15/May/2005.
// Notes : This implementation is based on the article
// 'Asynchronous FIFO in Virtex-II FPGAs'
// writen by Peter Alfke. This TechXclusive
// article can be downloaded from the
// Xilinx website. It has some minor modifications.
//=========================================
`timescale 1ns/1ps
module aFifo_256x8
#(parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 8,
FIFO_DEPTH = (1 << ADDRESS_WIDTH))
//Reading port
(output reg [DATA_WIDTH-1:0] Data_out,
output reg Empty_out,
input wire ReadEn_in,
input wire RClk,
//Writing port.
input wire [DATA_WIDTH-1:0] Data_in,
output reg Full_out,
input wire WriteEn_in,
input wire WClk,
input wire Clear_in);
/////Internal connections & variables//////
reg [DATA_WIDTH-1:0] Mem [FIFO_DEPTH-1:0];
wire [ADDRESS_WIDTH-1:0] pNextWordToWrite, pNextWordToRead;
wire EqualAddresses;
wire NextWriteAddressEn, NextReadAddressEn;
wire Set_Status, Rst_Status;
reg Status;
wire PresetFull, PresetEmpty;
//////////////Code///////////////
//Data ports logic:
//(Uses a dual-port RAM).
//'Data_out' logic:
/* Begin Comment
always @ (posedge RClk)
if (ReadEn_in & !Empty_out)
Data_out <= Mem[pNextWordToRead];
//'Data_in' logic:
always @ (posedge WClk)
if (WriteEn_in & !Full_out)
Mem[pNextWordToWrite] <= Data_in;
End Comment */
// Synopsys SRAM memory usage A1: ReadPort , A2 : WritePort
wire [DATA_WIDTH-1:0] temp;
wire [DATA_WIDTH-1:0] Lsb_Data_out;
wire [DATA_WIDTH-1:0] Msb_Data_out;
wire read_LsbEn , read_MsbEn, write_MsbEn, write_Lsben;
assign read_LsbEn = ~pNextWordToRead[7];
assign read_MsbEn = pNextWordToRead[7];
assign write_LsbEn = ~pNextWordToWrite[7];
assign write_MsbEn = pNextWordToWrite[7];
assign Data_out = (read_LsbEn ? Lsb_Data_out : Msb_Data_out);
SRAM2RW128x8 INST_LSB_SRAM2RW128x8 (.A1(pNextWordToRead[6:0]),
.A2(pNextWordToWrite[6:0]),
.CE1(RClk & read_LsbEn),
.CE2(WClk & write_LsbEn),
.WEB1(ReadEn_in),
.WEB2(~WriteEn_in),
.OEB1(1'b0),
.OEB2(1'b1),
.CSB1(~ReadEn_in),
.CSB2(~WriteEn_in),
.I1(8'h00),
.I2(Data_in),
.O1(Lsb_Data_out),
.O2(temp));
SRAM2RW128x8 INST_MSB_SRAM2RW128x8 (.A1(pNextWordToRead[6:0]),
.A2(pNextWordToWrite[6:0]),
.CE1(RClk & read_MsbEn),
.CE2(WClk & write_MsbEn),
.WEB1(ReadEn_in),
.WEB2(~WriteEn_in),
.OEB1(1'b1),
.OEB2(1'b0),
.CSB1(~ReadEn_in),
.CSB2(~WriteEn_in),
.I1(8'h00),
.I2(Data_in),
.O1(Msb_Data_out),
.O2(temp));
//Fifo addresses support logic:
//'Next Addresses' enable logic:
assign NextWriteAddressEn = WriteEn_in & ~Full_out;
assign NextReadAddressEn = ReadEn_in & ~Empty_out;
//Addreses (Gray counters) logic:
GrayCounter #(ADDRESS_WIDTH) GrayCounter_pWr
(.GrayCount_out(pNextWordToWrite),
.Enable_in(NextWriteAddressEn),
.Clear_in(Clear_in),
.Clk(WClk)
);
GrayCounter #(ADDRESS_WIDTH) GrayCounter_pRd
(.GrayCount_out(pNextWordToRead),
.Enable_in(NextReadAddressEn),
.Clear_in(Clear_in),
.Clk(RClk)
);
//'EqualAddresses' logic:
assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
//'Quadrant selectors' logic:
assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ^ pNextWordToRead[ADDRESS_WIDTH-2]);
assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
//'Status' latch logic:
always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.
if (Rst_Status | Clear_in)
Status = 0; //Going 'Empty'.
else if (Set_Status)
Status = 1; //Going 'Full'.
//'Full_out' logic for the writing port:
assign PresetFull = Status & EqualAddresses; //'Full' Fifo.
always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.
if (PresetFull)
Full_out <= 1;
else
Full_out <= 0;
//'Empty_out' logic for the reading port:
assign PresetEmpty = ~Status & EqualAddresses; //'Empty' Fifo.
always @ (posedge RClk, posedge PresetEmpty) //D Flip-Flop w/ Asynchronous Preset.
if (PresetEmpty)
Empty_out <= 1;
else
Empty_out <= 0;
endmodule
|
(** * IndProp: Inductively Defined Propositions *)
Set Warnings "-notation-overridden,-parsing".
From LF Require Export Logic.
From Coq Require Export Lia.
(* ################################################################# *)
(** * Inductively Defined Propositions *)
(** In the [Logic] chapter, we looked at several ways of writing
propositions, including conjunction, disjunction, and existential
quantification. In this chapter, we bring yet another new tool
into the mix: _inductive definitions_.
_Note_: For the sake of simplicity, most of this chapter uses an
inductive definition of "evenness" as a running example. You may
find this confusing, since we already have a perfectly good way of
defining evenness as a proposition ([n] is even if it is equal to
the result of doubling some number); if so, rest assured that we
will see many more compelling examples of inductively defined
propositions toward the end of this chapter and in future
chapters. *)
(** In past chapters, we have seen two ways of stating that a number
[n] is even: We can say
(1) [evenb n = true], or
(2) [exists k, n = double k].
Yet another possibility is to say that [n] is even if we can
establish its evenness from the following rules:
- Rule [ev_0]: The number [0] is even.
- Rule [ev_SS]: If [n] is even, then [S (S n)] is even. *)
(** To illustrate how this new definition of evenness works,
let's imagine using it to show that [4] is even. By rule [ev_SS],
it suffices to show that [2] is even. This, in turn, is again
guaranteed by rule [ev_SS], as long as we can show that [0] is
even. But this last fact follows directly from the [ev_0] rule. *)
(** We will see many definitions like this one during the rest
of the course. For purposes of informal discussions, it is
helpful to have a lightweight notation that makes them easy to
read and write. _Inference rules_ are one such notation. (We'll
use [ev] for the name of this property, since [even] is already
used.)
------------ (ev_0)
ev 0
ev n
---------------- (ev_SS)
ev (S (S n))
*)
(** Each of the textual rules that we started with is
reformatted here as an inference rule; the intended reading is
that, if the _premises_ above the line all hold, then the
_conclusion_ below the line follows. For example, the rule
[ev_SS] says that, if [n] satisfies [ev], then [S (S n)] also
does. If a rule has no premises above the line, then its
conclusion holds unconditionally.
We can represent a proof using these rules by combining rule
applications into a _proof tree_. Here's how we might transcribe
the above proof that [4] is even:
-------- (ev_0)
ev 0
-------- (ev_SS)
ev 2
-------- (ev_SS)
ev 4
*)
(** (Why call this a "tree", rather than a "stack", for example?
Because, in general, inference rules can have multiple premises.
We will see examples of this shortly.) *)
(* ================================================================= *)
(** ** Inductive Definition of Evenness *)
(** Putting all of this together, we can translate the definition of
evenness into a formal Coq definition using an [Inductive]
declaration, where each constructor corresponds to an inference
rule: *)
Inductive ev : nat -> Prop :=
| ev_0 : ev 0
| ev_SS (n : nat) (H : ev n) : ev (S (S n)).
(** This definition is interestingly different from previous uses of
[Inductive]. For one thing, we are defining not a [Type] (like
[nat]) or a function yielding a [Type] (like [list]), but rather a
function from [nat] to [Prop] -- that is, a property of numbers.
But what is really new is that, because the [nat] argument of
[ev] appears to the _right_ of the colon on the first line, it
is allowed to take different values in the types of different
constructors: [0] in the type of [ev_0] and [S (S n)] in the type
of [ev_SS]. Accordingly, the type of each constructor must be
specified explicitly (after a colon), and each constructor's type
must have the form [ev n] for some natural number [n].
In contrast, recall the definition of [list]:
Inductive list (X:Type) : Type :=
| nil
| cons (x : X) (l : list X).
This definition introduces the [X] parameter _globally_, to the
_left_ of the colon, forcing the result of [nil] and [cons] to be
the same (i.e., [list X]). Had we tried to bring [nat] to the left
of the colon in defining [ev], we would have seen an error: *)
Fail Inductive wrong_ev (n : nat) : Prop :=
| wrong_ev_0 : wrong_ev 0
| wrong_ev_SS (H: wrong_ev n) : wrong_ev (S (S n)).
(* ===> Error: Last occurrence of "[wrong_ev]" must have "[n]"
as 1st argument in "[wrong_ev 0]". *)
(** In an [Inductive] definition, an argument to the type constructor
on the left of the colon is called a "parameter", whereas an
argument on the right is called an "index" or "annotation."
For example, in [Inductive list (X : Type) := ...], the [X] is a
parameter; in [Inductive ev : nat -> Prop := ...], the unnamed
[nat] argument is an index. *)
(** We can think of the definition of [ev] as defining a Coq
property [ev : nat -> Prop], together with "evidence constructors"
[ev_0 : ev 0] and [ev_SS : forall n, ev n -> ev (S (S n))]. *)
(** Such "evidence constructors" have the same status as proven
theorems. In particular, we can use Coq's [apply] tactic with the
rule names to prove [ev] for particular numbers... *)
Theorem ev_4 : ev 4.
Proof. apply ev_SS. apply ev_SS. apply ev_0. Qed.
(** ... or we can use function application syntax: *)
Theorem ev_4' : ev 4.
Proof. apply (ev_SS 2 (ev_SS 0 ev_0)). Qed.
(** We can also prove theorems that have hypotheses involving [ev]. *)
Theorem ev_plus4 : forall n, ev n -> ev (4 + n).
Proof.
intros n. simpl. intros Hn.
apply ev_SS. apply ev_SS. apply Hn.
Qed.
(** **** Exercise: 1 star, standard (ev_double) *)
Theorem ev_double : forall n,
ev (double n).
Proof.
intros.
induction n.
- simpl. apply ev_0.
- simpl. apply ev_SS. apply IHn.
Qed.
(** [] *)
(* ################################################################# *)
(** * Using Evidence in Proofs *)
(** Besides _constructing_ evidence that numbers are even, we can also
_destruct_ such evidence, which amounts to reasoning about how it
could have been built.
Introducing [ev] with an [Inductive] declaration tells Coq not
only that the constructors [ev_0] and [ev_SS] are valid ways to
build evidence that some number is [ev], but also that these two
constructors are the _only_ ways to build evidence that numbers
are [ev]. *)
(** In other words, if someone gives us evidence [E] for the assertion
[ev n], then we know that [E] must be one of two things:
- [E] is [ev_0] (and [n] is [O]), or
- [E] is [ev_SS n' E'] (and [n] is [S (S n')], where [E'] is
evidence for [ev n']). *)
(** This suggests that it should be possible to analyze a
hypothesis of the form [ev n] much as we do inductively defined
data structures; in particular, it should be possible to argue by
_induction_ and _case analysis_ on such evidence. Let's look at a
few examples to see what this means in practice. *)
(* ================================================================= *)
(** ** Inversion on Evidence *)
(** Suppose we are proving some fact involving a number [n], and
we are given [ev n] as a hypothesis. We already know how to
perform case analysis on [n] using [destruct] or [induction],
generating separate subgoals for the case where [n = O] and the
case where [n = S n'] for some [n']. But for some proofs we may
instead want to analyze the evidence that [ev n] _directly_. As
a tool, we can prove our characterization of evidence for
[ev n], using [destruct]. *)
Theorem ev_inversion :
forall (n : nat), ev n ->
(n = 0) \/ (exists n', n = S (S n') /\ ev n').
Proof.
intros n E.
destruct E as [ | n' E'] eqn:EE.
- (* E = ev_0 : ev 0 *)
left. reflexivity.
- (* E = ev_SS n' E' : ev (S (S n')) *)
right. exists n'. split. reflexivity. apply E'.
Qed.
(** The following theorem can easily be proved using [destruct] on
evidence. *)
Theorem ev_minus2 : forall n,
ev n -> ev (pred (pred n)).
Proof.
intros n E.
destruct E as [| n' E'] eqn:EE.
- (* E = ev_0 *) simpl. apply ev_0.
- (* E = ev_SS n' E' *) simpl. apply E'.
Qed.
(** However, this variation cannot easily be handled with just
[destruct]. *)
Theorem evSS_ev : forall n,
ev (S (S n)) -> ev n.
(** Intuitively, we know that evidence for the hypothesis cannot
consist just of the [ev_0] constructor, since [O] and [S] are
different constructors of the type [nat]; hence, [ev_SS] is the
only case that applies. Unfortunately, [destruct] is not smart
enough to realize this, and it still generates two subgoals. Even
worse, in doing so, it keeps the final goal unchanged, failing to
provide any useful information for completing the proof. *)
Proof.
intros n E.
destruct E as [| n' E'] eqn:EE.
- (* E = ev_0. *)
(* We must prove that [n] is even from no assumptions! *)
Abort.
(* I guess It should be provable by induction on n?? *)
Theorem evSS_ev_my_take : forall n,
ev (S (S n)) -> ev n.
Proof.
intros n.
induction n.
- intros E. apply ev_0.
- intros.
(*
n : nat
IHn : ev (S (S n)) -> ev n
H : ev (S (S (S n)))
============================
ev (S n)
Nope.. I'm stuck in this case *)
Admitted.
(** What happened, exactly? Calling [destruct] has the effect of
replacing all occurrences of the property argument by the values
that correspond to each constructor. This is enough in the case
of [ev_minus2] because that argument [n] is mentioned directly
in the final goal. However, it doesn't help in the case of
[evSS_ev] since the term that gets replaced ([S (S n)]) is not
mentioned anywhere. *)
(** If we [remember] that term [S (S n)], the proof goes
through. (We'll discuss [remember] in more detail below.) *)
Theorem evSS_ev_remember : forall n,
ev (S (S n)) -> ev n.
Proof.
intros n E. remember (S (S n)) as k eqn:Hk. destruct E as [|n' E'] eqn:EE.
- (* E = ev_0 *)
(* Now we do have an assumption, in which [k = S (S n)] has been
rewritten as [0 = S (S n)] by [destruct]. That assumption
gives us a contradiction. *)
discriminate Hk.
- (* E = ev_S n' E' *)
(* This time [k = S (S n)] has been rewritten as [S (S n') = S (S n)]. *)
injection Hk as Heq. rewrite <- Heq. apply E'.
Qed.
(** Alternatively, the proof is straightforward using our inversion
lemma. *)
Theorem evSS_ev : forall n, ev (S (S n)) -> ev n.
Proof.
intros n H. apply ev_inversion in H.
destruct H as [H0|H1].
- discriminate H0.
- destruct H1 as [n' [Hnm Hev]]. injection Hnm as Heq.
rewrite Heq. apply Hev.
Qed.
(** Note how both proofs produce two subgoals, which correspond
to the two ways of proving [ev]. The first subgoal is a
contradiction that is discharged with [discriminate]. The second
subgoal makes use of [injection] and [rewrite]. Coq provides a
handy tactic called [inversion] that factors out that common
pattern.
The [inversion] tactic can detect (1) that the first case ([n =
0]) does not apply and (2) that the [n'] that appears in the
[ev_SS] case must be the same as [n]. It has an "[as]" variant
similar to [destruct], allowing us to assign names rather than
have Coq choose them. *)
Theorem evSS_ev' : forall n,
ev (S (S n)) -> ev n.
Proof.
intros n E.
inversion E as [| n' E' Heq].
(* We are in the [E = ev_SS n' E'] case now. *)
apply E'.
Qed.
(** The [inversion] tactic can apply the principle of explosion to
"obviously contradictory" hypotheses involving inductively defined
properties, something that takes a bit more work using our
inversion lemma. For example: *)
Theorem one_not_even : ~ ev 1.
Proof.
intros H. apply ev_inversion in H.
destruct H as [ | [m [Hm _]]].
- discriminate H.
- discriminate Hm.
Qed.
Theorem one_not_even' : ~ ev 1.
intros H. inversion H. Qed.
(** **** Exercise: 1 star, standard (inversion_practice)
Prove the following result using [inversion]. (For extra practice,
you can also prove it using the inversion lemma.) *)
Theorem SSSSev__even : forall n,
ev (S (S (S (S n)))) -> ev n.
Proof.
intros.
inversion H as [|n' HH Heq].
inversion HH as [|n'' HHH HHeq].
apply HHH.
Qed.
Theorem SSSSev__even_with_inversion_lemma : forall n,
ev (S (S (S (S n)))) -> ev n.
Proof.
intros.
apply ev_inversion in H. destruct H. discriminate H.
destruct H. destruct H.
injection H as H.
apply ev_inversion in H0. destruct H0. rewrite H0 in H. discriminate H.
destruct H0. destruct H0.
rewrite <- H in H0. injection H0 as H0. rewrite H0. apply H1.
Qed.
(** [] *)
(** **** Exercise: 1 star, standard (ev5_nonsense)
Prove the following result using [inversion]. *)
Theorem ev5_nonsense :
ev 5 -> 2 + 2 = 9.
Proof.
intros.
inversion H.
inversion H1.
inversion H3.
Qed.
(** [] *)
(** The [inversion] tactic does quite a bit of work. For
example, when applied to an equality assumption, it does the work
of both [discriminate] and [injection]. In addition, it carries
out the [intros] and [rewrite]s that are typically necessary in
the case of [injection]. It can also be applied, more generally,
to analyze evidence for inductively defined propositions. As
examples, we'll use it to reprove some theorems from chapter
[Tactics]. (Here we are being a bit lazy by omitting the [as]
clause from [inversion], thereby asking Coq to choose names for
the variables and hypotheses that it introduces.) *)
Theorem inversion_ex1 : forall (n m o : nat),
[n; m] = [o; o] ->
[n] = [m].
Proof.
intros n m o H. inversion H. reflexivity. Qed.
Theorem inversion_ex2 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
(** Here's how [inversion] works in general. Suppose the name
[H] refers to an assumption [P] in the current context, where [P]
has been defined by an [Inductive] declaration. Then, for each of
the constructors of [P], [inversion H] generates a subgoal in which
[H] has been replaced by the exact, specific conditions under
which this constructor could have been used to prove [P]. Some of
these subgoals will be self-contradictory; [inversion] throws
these away. The ones that are left represent the cases that must
be proved to establish the original goal. For those, [inversion]
adds all equations into the proof context that must hold of the
arguments given to [P] (e.g., [S (S n') = n] in the proof of
[evSS_ev]). *)
(** The [ev_double] exercise above shows that our new notion of
evenness is implied by the two earlier ones (since, by
[even_bool_prop] in chapter [Logic], we already know that
those are equivalent to each other). To show that all three
coincide, we just need the following lemma. *)
Lemma ev_even_firsttry : forall n,
ev n -> even n.
Proof.
(* WORKED IN CLASS *)
(** We could try to proceed by case analysis or induction on [n]. But
since [ev] is mentioned in a premise, this strategy would
probably lead to a dead end, because (as we've noted before) the
induction hypothesis will talk about n-1 (which is _not_ even!).
Thus, it seems better to first try [inversion] on the evidence for
[ev]. Indeed, the first case can be solved trivially. And we can
seemingly make progress on the second case with a helper lemma. *)
intros n E. inversion E as [EQ' | n' E' EQ'].
- (* E = ev_0 *)
exists 0. reflexivity.
- (* E = ev_SS n' E' *) simpl.
(** Unfortunately, the second case is harder. We need to show [exists
k, S (S n') = double k], but the only available assumption is
[E'], which states that [ev n'] holds. Since this isn't
directly useful, it seems that we are stuck and that performing
case analysis on [E] was a waste of time.
If we look more closely at our second goal, however, we can see
that something interesting happened: By performing case analysis
on [E], we were able to reduce the original result to a similar
one that involves a _different_ piece of evidence for [ev]:
namely [E']. More formally, we can finish our proof by showing
that
exists k', n' = double k',
which is the same as the original statement, but with [n'] instead
of [n]. Indeed, it is not difficult to convince Coq that this
intermediate result suffices. *)
(** Unforunately, now we are stuck. To make that apparent, let's move
[E'] back into the goal from the hypotheses. *)
generalize dependent E'.
(** Now it is clear we are trying to prove another instance of the
same theorem we set out to prove. This instance is with [n'],
instead of [n], where [n'] is a smaller natural number than [n]. *)
Abort.
(* ================================================================= *)
(** ** Induction on Evidence *)
(** If this looks familiar, it is no coincidence: We've encountered
similar problems in the [Induction] chapter, when trying to
use case analysis to prove results that required induction. And
once again the solution is... induction! *)
(** The behavior of [induction] on evidence is the same as its
behavior on data: It causes Coq to generate one subgoal for each
constructor that could have used to build that evidence, while
providing an induction hypothesis for each recursive occurrence of
the property in question.
To prove a property of [n] holds for all numbers for which [ev
n] holds, we can use induction on [ev n]. This requires us to
prove two things, corresponding to the two ways in which [ev n]
could have been constructed. If it was constructed by [ev_0], then
[n=0], and the property must hold of [0]. If it was constructed by
[ev_SS], then the evidence of [ev n] is of the form [ev_SS n'
E'], where [n = S (S n')] and [E'] is evidence for [ev n']. In
this case, the inductive hypothesis says that the property we are
trying to prove holds for [n']. *)
(** Let's try our current lemma again: *)
Lemma ev_even : forall n,
ev n -> even n.
Proof.
intros n E.
induction E as [|n' E' IH].
- (* E = ev_0 *)
exists 0. reflexivity.
- (* E = ev_SS n' E'
with IH : even E' *)
unfold even in IH.
destruct IH as [k Hk].
rewrite Hk. exists (S k). simpl. reflexivity.
Qed.
(** Here, we can see that Coq produced an [IH] that corresponds
to [E'], the single recursive occurrence of [ev] in its own
definition. Since [E'] mentions [n'], the induction hypothesis
talks about [n'], as opposed to [n] or some other number. *)
(** The equivalence between the second and third definitions of
evenness now follows. *)
Theorem ev_even_iff : forall n,
ev n <-> even n.
Proof.
intros n. split.
- (* -> *) apply ev_even.
- (* <- *) unfold even. intros [k Hk]. rewrite Hk. apply ev_double.
Qed.
(** As we will see in later chapters, induction on evidence is a
recurring technique across many areas, and in particular when
formalizing the semantics of programming languages, where many
properties of interest are defined inductively. *)
(** The following exercises provide simple examples of this
technique, to help you familiarize yourself with it. *)
(** **** Exercise: 2 stars, standard (ev_sum) *)
Theorem ev_sum : forall n m, ev n -> ev m -> ev (n + m).
Proof.
intros.
inversion H.
- (* n=0 *)
simpl. apply H0.
- (* n=SS n0 *)
simpl. apply ev_SS.
induction H0.
+ (* m = 0 *)
rewrite <- plus_n_O.
apply H1.
+ (* m = S S m0 *)
rewrite <- plus_n_Sm. rewrite <- plus_n_Sm.
apply ev_SS. apply IHev.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced, optional (ev'_ev)
In general, there may be multiple ways of defining a
property inductively. For example, here's a (slightly contrived)
alternative definition for [ev]: *)
Inductive ev' : nat -> Prop :=
| ev'_0 : ev' 0
| ev'_2 : ev' 2
| ev'_sum n m (Hn : ev' n) (Hm : ev' m) : ev' (n + m).
(** Prove that this definition is logically equivalent to the old one.
To streamline the proof, use the technique (from [Logic]) of
applying theorems to arguments, and note that the same technique
works with constructors of inductively defined propositions. *)
Theorem ev'_ev : forall n, ev' n <-> ev n.
Proof.
intros. split.
- (* -> *)
intro.
induction H as [| | n m IHevn' IHevn IHevm' IHevm].
+ (* 0 *) apply ev_0.
+ (* 2 *) apply ev_SS. apply ev_0.
+ (* n + m *) apply ev_sum. apply IHevn. apply IHevm.
- (* <- *)
intro.
induction H as [| n IHSSn].
+ (* 0 *) apply ev'_0.
+ (* 2 *) assert (S(S(n)) = 2 + n).
{ reflexivity. }
rewrite H.
apply ev'_sum.
* (* ev' 2 *)
apply ev'_2.
* (* ev' n *)
apply IHIHSSn.
Qed.
(** [] *)
Theorem plus_n_m_zero : forall n m, n + m = 0 <-> m = 0 /\ n = 0.
Proof.
split.
- (* -> *)
induction n.
+ simpl. intros. split. apply H. reflexivity.
+ simpl. intros. discriminate H.
- (* <- *)
intros. destruct H. rewrite H. rewrite H0. reflexivity.
Qed.
(** **** Exercise: 3 stars, advanced, especially useful (ev_ev__ev)
There are two pieces of evidence you could attempt to induct upon
here. If one doesn't work, try the other. *)
Theorem ev_ev__ev : forall n m,
ev (n+m) -> ev n -> ev m.
Proof.
intros.
induction H0.
- simpl in H. apply H.
- simpl in H.
+ inversion H.
apply IHev.
apply H2.
Qed.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (ev_plus_plus)
This exercise can be completed without induction or case analysis.
But, you will need a clever assertion and some tedious rewriting.
Hint: is [(n+m) + (n+p)] even? *)
Theorem ev_plus_plus : forall n m p,
ev (n+m) -> ev (n+p) -> ev (m+p).
Proof.
intros.
assert (ev ((n+n) + (m+p))).
{
(* the "tedious rewriting" part lol *)
rewrite plus_assoc.
rewrite (plus_comm _ m).
rewrite plus_assoc.
rewrite (plus_comm m n).
rewrite <- plus_assoc.
(* above rewriting converts "(n+n) + (m+p)" to "(n+m) + (n+p)" *)
apply ev_sum.
- apply H.
- apply H0.
}
apply (ev_ev__ev (n+n)) in H1.
- apply H1.
- rewrite <- double_plus. apply ev_double.
Qed.
(** [] *)
(* ################################################################# *)
(** * Inductive Relations *)
(** A proposition parameterized by a number (such as [ev])
can be thought of as a _property_ -- i.e., it defines
a subset of [nat], namely those numbers for which the proposition
is provable. In the same way, a two-argument proposition can be
thought of as a _relation_ -- i.e., it defines a set of pairs for
which the proposition is provable. *)
Module Playground.
(** Just like properties, relations can be defined inductively. One
useful example is the "less than or equal to" relation on
numbers. *)
(** The following definition should be fairly intuitive. It
says that there are two ways to give evidence that one number is
less than or equal to another: either observe that they are the
same number, or give evidence that the first is less than or equal
to the predecessor of the second. *)
Inductive le : nat -> nat -> Prop :=
| le_n (n : nat) : le n n
| le_S (n m : nat) (H : le n m) : le n (S m).
Notation "n <= m" := (le n m).
(** Proofs of facts about [<=] using the constructors [le_n] and
[le_S] follow the same patterns as proofs about properties, like
[ev] above. We can [apply] the constructors to prove [<=]
goals (e.g., to show that [3<=3] or [3<=6]), and we can use
tactics like [inversion] to extract information from [<=]
hypotheses in the context (e.g., to prove that [(2 <= 1) ->
2+2=5].) *)
(** Here are some sanity checks on the definition. (Notice that,
although these are the same kind of simple "unit tests" as we gave
for the testing functions we wrote in the first few lectures, we
must construct their proofs explicitly -- [simpl] and
[reflexivity] don't do the job, because the proofs aren't just a
matter of simplifying computations.) *)
Theorem test_le1 :
3 <= 3.
Proof.
(* WORKED IN CLASS *)
apply le_n. Qed.
Theorem test_le2 :
3 <= 6.
Proof.
(* WORKED IN CLASS *)
apply le_S. apply le_S. apply le_S. apply le_n. Qed.
Theorem test_le3 :
(2 <= 1) -> 2 + 2 = 5.
Proof.
(* WORKED IN CLASS *)
intros H. inversion H. inversion H2. Qed.
(** The "strictly less than" relation [n < m] can now be defined
in terms of [le]. *)
Definition lt (n m:nat) := le (S n) m.
Notation "m < n" := (lt m n).
End Playground.
(** Here are a few more simple relations on numbers: *)
Inductive square_of : nat -> nat -> Prop :=
| sq n : square_of n (n * n).
Inductive next_nat : nat -> nat -> Prop :=
| nn n : next_nat n (S n).
Inductive next_ev : nat -> nat -> Prop :=
| ne_1 n (H: ev (S n)) : next_ev n (S n)
| ne_2 n (H: ev (S (S n))) : next_ev n (S (S n)).
(** **** Exercise: 2 stars, standard, optional (total_relation)
Define an inductive binary relation [total_relation] that holds
between every pair of natural numbers. *)
Inductive total_relation : nat -> nat -> Prop :=
| total n m : total_relation n m.
(* [] *)
Goal total_relation 1 3.
apply total.
Qed.
(** **** Exercise: 2 stars, standard, optional (empty_relation)
Define an inductive binary relation [empty_relation] (on numbers)
that never holds. *)
Inductive empty_relation : nat -> nat -> Prop :=.
(* [] *)
(** From the definition of [le], we can sketch the behaviors of
[destruct], [inversion], and [induction] on a hypothesis [H]
providing evidence of the form [le e1 e2]. Doing [destruct H]
will generate two cases. In the first case, [e1 = e2], and it
will replace instances of [e2] with [e1] in the goal and context.
In the second case, [e2 = S n'] for some [n'] for which [le e1 n']
holds, and it will replace instances of [e2] with [S n'].
Doing [inversion H] will remove impossible cases and add generated
equalities to the context for further use. Doing [induction H]
will, in the second case, add the induction hypothesis that the
goal holds when [e2] is replaced with [n']. *)
(** **** Exercise: 3 stars, standard, optional (le_exercises)
Here are a number of facts about the [<=] and [<] relations that
we are going to need later in the course. The proofs make good
practice exercises. *)
Lemma le_trans : forall m n o, m <= n -> n <= o -> m <= o.
Proof.
intros.
induction H0.
- apply H.
- apply le_S. apply IHle.
Qed.
Theorem O_le_n : forall n,
0 <= n.
Proof.
induction n.
- apply le_n.
- apply le_S. apply IHn.
Qed.
Theorem n_le_m__Sn_le_Sm : forall n m,
n <= m -> S n <= S m.
Proof.
intros.
induction H.
- apply le_n.
- apply le_S. apply IHle.
Qed.
Theorem Sn_le_Sm__n_le_m : forall n m,
S n <= S m -> n <= m.
Proof.
intros.
inversion H.
- apply le_n.
- inversion H1.
+ apply le_S.
apply le_n.
+ apply le_S.
apply (le_trans _ (S n) _).
* apply le_S.
apply le_n.
* apply H2.
Qed.
Theorem le_plus_l : forall a b,
a <= a + b.
Proof.
intros.
induction b.
- rewrite <- plus_n_O.
reflexivity.
- rewrite <- plus_n_Sm.
apply le_S.
apply IHb.
Qed.
Lemma plus_le_left : forall n1 n2 m,
n1 + n2 <= m -> n1 <= m.
Proof.
intros.
induction n2.
+ rewrite <- plus_n_O in H.
apply H.
+ rewrite <- plus_n_Sm in H.
apply le_S in H.
apply Sn_le_Sm__n_le_m in H.
apply IHn2 in H. apply H.
Qed.
Lemma plus_le_right : forall n1 n2 m,
n1 + n2 <= m -> n2 <= m.
Proof.
intros.
rewrite plus_comm in H.
apply plus_le_left in H.
apply H.
Qed.
Theorem plus_le : forall n1 n2 m,
n1 + n2 <= m ->
n1 <= m /\ n2 <= m.
Proof.
intros.
split.
- (* n1 <= m *)
apply (plus_le_left _ n2).
apply H.
- (* n2 <= m *)
apply (plus_le_right n1 _).
apply H.
Qed.
(** Hint: the next one may be easiest to prove by induction on [n]. *)
Theorem add_le_cases : forall n m p q,
n + m <= p + q -> n <= p \/ m <= q.
Proof.
intros.
generalize dependent m.
generalize dependent p.
generalize dependent q.
induction n.
- (* n := 0 *)
intros.
simpl in H. left. apply O_le_n.
- (* n := S n *)
intros.
destruct p.
+ right. apply (plus_le_left _ (S n) _).
rewrite plus_comm. simpl. simpl in H. apply H.
+ simpl in H. apply Sn_le_Sm__n_le_m in H. apply IHn in H. destruct H.
* left. apply n_le_m__Sn_le_Sm. apply H.
* right. apply H.
Qed.
Theorem lt_S : forall n m,
n < m ->
n < S m.
Proof.
intros.
destruct H.
- apply le_S. apply le_n.
- apply le_S. apply le_S. apply H.
Qed.
Theorem plus_lt : forall n1 n2 m,
n1 + n2 < m ->
n1 < m /\ n2 < m.
Proof.
unfold lt.
intros.
split.
replace (S (n1 + n2)) with (S n1 + n2) in H.
- apply plus_le_left in H.
apply H.
- simpl. reflexivity.
- rewrite plus_n_Sm in H.
apply plus_le_right in H.
apply H.
Qed.
Theorem leb_complete : forall n m,
n <=? m = true -> n <= m.
Proof.
induction n.
- (* n := 0 *)
intros.
apply O_le_n.
- (* n := S n *)
intros.
destruct m.
+ (* m : = 0 *)
unfold leb in H. discriminate H.
+ (* m := S m*)
simpl leb in H. apply n_le_m__Sn_le_Sm. apply IHn. apply H.
Qed.
(** Hint: The next one may be easiest to prove by induction on [m]. *)
Theorem leb_correct : forall n m,
n <= m ->
n <=? m = true.
Proof.
induction n.
intros.
- (* n := 0 *)
simpl. reflexivity.
- (* n := S n *)
destruct m.
+ (* m := 0 *)
intros. inversion H.
+ (* m := S m *)
intros. apply Sn_le_Sm__n_le_m in H. simpl. apply IHn. apply H.
Qed.
(** Hint: The next one can easily be proved without using [induction]. *)
Theorem leb_true_trans : forall n m o,
n <=? m = true -> m <=? o = true -> n <=? o = true.
Proof.
intros.
apply leb_complete in H.
apply leb_complete in H0.
apply leb_correct.
apply (le_trans _ m _).
apply H.
apply H0.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (leb_iff) *)
Theorem leb_iff : forall n m,
n <=? m = true <-> n <= m.
Proof.
intros.
split.
- (* -> direction *)
intros.
apply leb_complete.
apply H.
- (* <- direction *)
intros.
apply leb_correct.
apply H.
Qed.
(** [] *)
Module R.
(** **** Exercise: 3 stars, standard, especially useful (R_provability)
We can define three-place relations, four-place relations,
etc., in just the same way as binary relations. For example,
consider the following three-place relation on numbers: *)
Inductive R : nat -> nat -> nat -> Prop :=
| c1 : R 0 0 0
| c2 m n o (H : R m n o) : R (S m) n (S o)
| c3 m n o (H : R m n o) : R m (S n) (S o)
| c4 m n o (H : R (S m) (S n) (S (S o))) : R m n o
| c5 m n o (H : R m n o) : R n m o.
(* I figured out this relation encodes the notion of plus.
Namely, R a b c <-> plus a b = c
*)
(** - Which of the following propositions are provable?
- [R 1 1 2]
- [R 2 2 6]
- If we dropped constructor [c5] from the definition of [R],
would the set of provable propositions change? Briefly (1
sentence) explain your answer.
- If we dropped constructor [c4] from the definition of [R],
would the set of provable propositions change? Briefly (1
sentence) explain your answer. *)
(* R 1 1 2 is provable because 1 + 1 = 2 *)
(* R 2 2 6 is not provable because 2 + 2 <> 6 *)
(* Do not modify the following line: *)
Definition manual_grade_for_R_provability : option (nat*string) := None.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (R_fact)
The relation [R] above actually encodes a familiar function.
Figure out which function; then state and prove this equivalence
in Coq? *)
Definition fR : nat -> nat -> nat := plus.
Theorem R_equiv_fR : forall m n o, R m n o <-> fR m n = o.
Proof.
unfold fR.
intros.
split.
- (* -> direction *)
intro.
induction H.
+ reflexivity.
+ simpl. rewrite IHR. reflexivity.
+ rewrite <- plus_n_Sm. rewrite IHR. reflexivity.
+ simpl in IHR. rewrite <- plus_n_Sm in IHR. injection IHR as IHR. apply IHR.
+ rewrite plus_comm. apply IHR.
- (* <- direction *)
intro.
generalize dependent o.
induction m.
+ (* m := 0 *)
intros.
generalize dependent o.
induction n.
* (* n := 0 *) intros. destruct o. constructor. inversion H.
* (* n := S n *) intros. destruct o. simpl in H. inversion H.
constructor. apply IHn. simpl in H. simpl. injection H as H. apply H.
+ (* m := S m *)
intros. destruct o. simpl in H. inversion H.
constructor. apply IHm. simpl in H. inversion H. reflexivity.
Qed.
(** [] *)
End R.
(** **** Exercise: 2 stars, advanced (subsequence)
A list is a _subsequence_ of another list if all of the elements
in the first list occur in the same order in the second list,
possibly with some extra elements in between. For example,
[1;2;3]
is a subsequence of each of the lists
[1;2;3]
[1;1;1;2;2;3]
[1;2;7;3]
[5;6;1;9;9;2;7;3;8]
but it is _not_ a subsequence of any of the lists
[1;2]
[1;3]
[5;6;2;1;7;3;8].
- Define an inductive proposition [subseq] on [list nat] that
captures what it means to be a subsequence. (Hint: You'll need
three cases.)
- Prove [subseq_refl] that subsequence is reflexive, that is,
any list is a subsequence of itself.
- Prove [subseq_app] that for any lists [l1], [l2], and [l3],
if [l1] is a subsequence of [l2], then [l1] is also a subsequence
of [l2 ++ l3].
- (Optional, harder) Prove [subseq_trans] that subsequence is
transitive -- that is, if [l1] is a subsequence of [l2] and [l2]
is a subsequence of [l3], then [l1] is a subsequence of [l3].
Hint: choose your induction carefully! *)
Inductive subseq : list nat -> list nat -> Prop :=
| ss0 xs : subseq [] xs
| ss_init x xs ys (H : subseq xs ys) : subseq (x::xs) (x::ys)
| ss_rest x y xs ys (H : subseq (x::xs) ys) : subseq (x::xs) (y::ys)
.
Theorem subseq_refl : forall (l : list nat), subseq l l.
Proof.
intros.
induction l.
- (* subseq [] [] *)
constructor.
- (* subseq (x::l) (x::l) *)
constructor. apply IHl.
Qed.
Theorem subseq_app : forall (l1 l2 l3 : list nat),
subseq l1 l2 ->
subseq l1 (l2 ++ l3).
Proof.
intros l1.
destruct l1.
- (* l1 := [] *)
intros. constructor.
- (* l1 := S l1 *)
intros.
induction H.
+ (* (x::xs) [] *)
constructor.
+ (* (x::xs) (x::ys) *)
simpl. constructor. apply IHsubseq.
+ (* (x::xs) (y::ys) *)
simpl. constructor. apply IHsubseq.
Qed.
Theorem subseq_trans : forall (l1 l2 l3 : list nat),
subseq l1 l2 ->
subseq l2 l3 ->
subseq l1 l3.
Proof.
intros l1 l2 l3.
intro.
generalize dependent l3.
induction H.
- (* [] _ l3 *)
intros. constructor.
- (* x::xs x::ys l3 *)
intros.
remember (x::ys) as l2.
induction H0.
+ (* x::xs x::ys=[] l3 *)
inversion Heql2.
+ (* x::xs x::ys x::ys0 *)
injection Heql2. intros. clear Heql2. subst xs0 x0.
constructor. apply IHsubseq. apply H0.
+ (* x::xs x::ys y::ys0 *)
injection Heql2. intros. clear Heql2. subst xs0 x0.
constructor. apply IHsubseq0. reflexivity.
- (* x::xs y::ys l3 *)
intros.
remember (y::ys) as l2.
induction H0.
+ (* x::xs y::ys=[] l3 *)
inversion Heql2.
+ (* x::xs y::ys y::ys0 *)
injection Heql2. intros. clear Heql2. subst xs0 x0.
constructor. apply IHsubseq. apply H0.
+ (* x::xs y::ys y0::ys0 *)
injection Heql2. intros. clear Heql2. subst xs0 x0.
constructor. apply IHsubseq0. reflexivity.
Qed.
(** **** Exercise: 2 stars, standard, optional (R_provability2)
Suppose we give Coq the following definition:
Inductive R : nat -> list nat -> Prop :=
| c1 : R 0 []
| c2 n l (H: R n l) : R (S n) (n :: l)
| c3 n l (H: R (S n) l) : R n l.
Which of the following propositions are provable?
- [R 2 [1;0]]
- [R 1 [1;2;1;0]]
- [R 6 [3;2;1;0]] *)
(* `R n l` encodes a seemingly complex relation.
Here's a listing of valid relations:
(+) denotes c2
(-) denotes c3
R 0 []
+ R 1 [0]
+ R 2 [1; 0]
+ R 3 [2; 1; 0]
+ R 4 [3; 2; 1; 0]
- R 2 [2; 1; 0]
- R 1 [2; 1; 0]
+ R 2 [1; 2; 1; 0]
- R 0 [2; 1; 0]
+ R 1 [0; 2; 1; 0]
- R 1 [1; 0]
+ R 2 [1; 1; 0]
+ R 3 [2; 1; 1; 0]
- R 1 [1; 1; 0]
- R 0 [1; 0]
- R 0 [0]
+ R 1 [0; 0]
+ R 2 [1; 0; 0]
- R 1 [0; 0]
- R 0 [0; 0]
some observations:
- last elements must be 0
- for two adjacent elements, l=[...;n;m;...], n <= S m
- n <= length l
- n <= S(hd(l))
I'm not sure if these four properties are strong enough to be equivalent to R.
*)
Module R'.
Inductive R : nat -> list nat -> Prop :=
| c1 : R 0 []
| c2 n l (H: R n l) : R (S n) (n :: l)
| c3 n l (H: R (S n) l) : R n l.
Example R_ex_1: R 2 [1; 0].
Proof. apply c2. apply c2. apply c1. Qed.
Example R_ex_2: R 1 [1; 2; 1].
Proof. apply c3. apply c2. apply c3. apply c3. apply c2. apply c2. Admitted.
Example R_ex_3: R 6 [3; 2; 1; 0].
Proof. Admitted.
Example R_ex_2': R 1 [1; 2; 1; 0].
Proof. apply c3. apply c2. apply c3. apply c3. apply c2. apply c2. apply c2.
apply c1.
Qed.
End R'.
(* [] *)
(* ################################################################# *)
(** * Case Study: Regular Expressions *)
(** The [ev] property provides a simple example for
illustrating inductive definitions and the basic techniques for
reasoning about them, but it is not terribly exciting -- after
all, it is equivalent to the two non-inductive definitions of
evenness that we had already seen, and does not seem to offer any
concrete benefit over them.
To give a better sense of the power of inductive definitions, we
now show how to use them to model a classic concept in computer
science: _regular expressions_. *)
(** Regular expressions are a simple language for describing sets of
strings. Their syntax is defined as follows: *)
Inductive reg_exp (T : Type) : Type :=
| EmptySet
| EmptyStr
| Char (t : T)
| App (r1 r2 : reg_exp T)
| Union (r1 r2 : reg_exp T)
| Star (r : reg_exp T).
Arguments EmptySet {T}.
Arguments EmptyStr {T}.
Arguments Char {T} _.
Arguments App {T} _ _.
Arguments Union {T} _ _.
Arguments Star {T} _.
(** Note that this definition is _polymorphic_: Regular
expressions in [reg_exp T] describe strings with characters drawn
from [T] -- that is, lists of elements of [T].
(We depart slightly from standard practice in that we do not
require the type [T] to be finite. This results in a somewhat
different theory of regular expressions, but the difference is not
significant for our purposes.) *)
(** We connect regular expressions and strings via the following
rules, which define when a regular expression _matches_ some
string:
- The expression [EmptySet] does not match any string.
- The expression [EmptyStr] matches the empty string [[]].
- The expression [Char x] matches the one-character string [[x]].
- If [re1] matches [s1], and [re2] matches [s2],
then [App re1 re2] matches [s1 ++ s2].
- If at least one of [re1] and [re2] matches [s],
then [Union re1 re2] matches [s].
- Finally, if we can write some string [s] as the concatenation
of a sequence of strings [s = s_1 ++ ... ++ s_k], and the
expression [re] matches each one of the strings [s_i],
then [Star re] matches [s].
In particular, the sequence of strings may be empty, so
[Star re] always matches the empty string [[]] no matter what
[re] is. *)
(** We can easily translate this informal definition into an
[Inductive] one as follows. We use the notation [s =~ re] in
place of [exp_match s re]; by "reserving" the notation before
defining the [Inductive], we can use it in the definition! *)
Reserved Notation "s =~ re" (at level 80).
Inductive exp_match {T} : list T -> reg_exp T -> Prop :=
| MEmpty : [] =~ EmptyStr
| MChar x : [x] =~ (Char x)
| MApp s1 re1 s2 re2
(H1 : s1 =~ re1)
(H2 : s2 =~ re2)
: (s1 ++ s2) =~ (App re1 re2)
| MUnionL s1 re1 re2
(H1 : s1 =~ re1)
: s1 =~ (Union re1 re2)
| MUnionR re1 s2 re2
(H2 : s2 =~ re2)
: s2 =~ (Union re1 re2)
| MStar0 re : [] =~ (Star re)
| MStarApp s1 s2 re
(H1 : s1 =~ re)
(H2 : s2 =~ (Star re))
: (s1 ++ s2) =~ (Star re)
where "s =~ re" := (exp_match s re).
Lemma quiz : forall T (s:list T), ~(s =~ EmptySet).
Proof. intros T s Hc. inversion Hc. Qed.
(** Again, for readability, we display this definition using
inference-rule notation. *)
(**
---------------- (MEmpty)
[] =~ EmptyStr
--------------- (MChar)
[x] =~ Char x
s1 =~ re1 s2 =~ re2
------------------------- (MApp)
s1 ++ s2 =~ App re1 re2
s1 =~ re1
--------------------- (MUnionL)
s1 =~ Union re1 re2
s2 =~ re2
--------------------- (MUnionR)
s2 =~ Union re1 re2
--------------- (MStar0)
[] =~ Star re
s1 =~ re s2 =~ Star re
--------------------------- (MStarApp)
s1 ++ s2 =~ Star re
*)
(** Notice that these rules are not _quite_ the same as the
informal ones that we gave at the beginning of the section.
First, we don't need to include a rule explicitly stating that no
string matches [EmptySet]; we just don't happen to include any
rule that would have the effect of some string matching
[EmptySet]. (Indeed, the syntax of inductive definitions doesn't
even _allow_ us to give such a "negative rule.")
Second, the informal rules for [Union] and [Star] correspond
to two constructors each: [MUnionL] / [MUnionR], and [MStar0] /
[MStarApp]. The result is logically equivalent to the original
rules but more convenient to use in Coq, since the recursive
occurrences of [exp_match] are given as direct arguments to the
constructors, making it easier to perform induction on evidence.
(The [exp_match_ex1] and [exp_match_ex2] exercises below ask you
to prove that the constructors given in the inductive declaration
and the ones that would arise from a more literal transcription of
the informal rules are indeed equivalent.)
Let's illustrate these rules with a few examples. *)
Example reg_exp_ex1 : [1] =~ Char 1.
Proof.
apply MChar.
Qed.
Example reg_exp_ex2 : [1; 2] =~ App (Char 1) (Char 2).
Proof.
apply (MApp [1]).
- apply MChar.
- apply MChar.
Qed.
(** (Notice how the last example applies [MApp] to the string
[[1]] directly. Since the goal mentions [[1; 2]] instead of
[[1] ++ [2]], Coq wouldn't be able to figure out how to split
the string on its own.)
Using [inversion], we can also show that certain strings do _not_
match a regular expression: *)
Example reg_exp_ex3 : ~ ([1; 2] =~ Char 1).
Proof.
intros H. inversion H.
Qed.
(** We can define helper functions for writing down regular
expressions. The [reg_exp_of_list] function constructs a regular
expression that matches exactly the list that it receives as an
argument: *)
Fixpoint reg_exp_of_list {T} (l : list T) :=
match l with
| [] => EmptyStr
| x :: l' => App (Char x) (reg_exp_of_list l')
end.
Example reg_exp_ex4 : [1; 2; 3] =~ reg_exp_of_list [1; 2; 3].
Proof.
simpl. apply (MApp [1]).
{ apply MChar. }
apply (MApp [2]).
{ apply MChar. }
apply (MApp [3]).
{ apply MChar. }
apply MEmpty.
Qed.
(** We can also prove general facts about [exp_match]. For instance,
the following lemma shows that every string [s] that matches [re]
also matches [Star re]. *)
Lemma MStar1 :
forall T s (re : reg_exp T) ,
s =~ re ->
s =~ Star re.
Proof.
intros T s re H.
rewrite <- (app_nil_r _ s).
apply MStarApp.
- apply H.
- apply MStar0.
Qed.
(** (Note the use of [app_nil_r] to change the goal of the theorem to
exactly the same shape expected by [MStarApp].) *)
(** **** Exercise: 3 stars, standard (exp_match_ex1)
The following lemmas show that the informal matching rules given
at the beginning of the chapter can be obtained from the formal
inductive definition. *)
Lemma empty_is_empty : forall T (s : list T),
~ (s =~ EmptySet).
Proof.
intros. intro.
inversion H.
Qed.
Lemma MUnion' : forall T (s : list T) (re1 re2 : reg_exp T),
s =~ re1 \/ s =~ re2 ->
s =~ Union re1 re2.
Proof.
intros.
destruct H.
- apply MUnionL. apply H.
- apply MUnionR. apply H.
Qed.
(** The next lemma is stated in terms of the [fold] function from the
[Poly] chapter: If [ss : list (list T)] represents a sequence of
strings [s1, ..., sn], then [fold app ss []] is the result of
concatenating them all together. *)
Lemma MStar' : forall T (ss : list (list T)) (re : reg_exp T),
(forall s, In s ss -> s =~ re) ->
fold app ss [] =~ Star re.
Proof.
intros.
induction ss.
- simpl. apply MStar0.
- simpl. apply MStarApp.
+ apply H. simpl. left. reflexivity.
+ apply IHss. intros. apply H. simpl. right. apply H0.
Qed.
(** [] *)
(** **** Exercise: 4 stars, standard, optional (reg_exp_of_list_spec)
Prove that [reg_exp_of_list] satisfies the following
specification: *)
Lemma reg_exp_of_list_spec : forall T (s1 s2 : list T),
s1 =~ reg_exp_of_list s2 <-> s1 = s2.
Proof.
split; intros.
- (* -> *)
generalize dependent s1.
induction s2.
+ (* s2 := [], show s1 = [] *)
intros. inversion H. reflexivity.
+ (* s2 := x:l, show s1 = x:l *)
intros. simpl in H. inversion H. subst s1 re1 re2.
(* H3: s0 ~ Char x *)
inversion H3. subst x0 s0. simpl. f_equal. apply IHs2. apply H4.
- (* <- *)
generalize dependent s1.
induction s2; intros.
+ (* s2 := [], show s1 =~ reg_exp_of_list s2 *)
simpl. rewrite H. apply MEmpty.
+ (* s2 := x::s2, show s1 =~ reg_exp_of_list (x :: s2) *)
simpl. rewrite H. apply (MApp [x]).
* (* prove [x] =~ Char x *)
apply MChar.
* (* prove s2 =~ reg_exp_of_list s2 *)
apply IHs2. reflexivity.
Qed.
(** [] *)
(** Since the definition of [exp_match] has a recursive
structure, we might expect that proofs involving regular
expressions will often require induction on evidence. *)
(** For example, suppose that we wanted to prove the following
intuitive result: If a regular expression [re] matches some string
[s], then all elements of [s] must occur as character literals
somewhere in [re].
To state this theorem, we first define a function [re_chars] that
lists all characters that occur in a regular expression: *)
Fixpoint re_chars {T} (re : reg_exp T) : list T :=
match re with
| EmptySet => []
| EmptyStr => []
| Char x => [x]
| App re1 re2 => re_chars re1 ++ re_chars re2
| Union re1 re2 => re_chars re1 ++ re_chars re2
| Star re => re_chars re
end.
(** We can then phrase our theorem as follows: *)
Theorem in_re_match : forall T (s : list T) (re : reg_exp T) (x : T),
s =~ re ->
In x s ->
In x (re_chars re).
Proof.
intros T s re x Hmatch Hin.
induction Hmatch
as [| x'
| s1 re1 s2 re2 Hmatch1 IH1 Hmatch2 IH2
| s1 re1 re2 Hmatch IH | re1 s2 re2 Hmatch IH
| re | s1 s2 re Hmatch1 IH1 Hmatch2 IH2].
(* WORKED IN CLASS *)
- (* MEmpty *)
simpl in Hin. destruct Hin.
- (* MChar *)
simpl. simpl in Hin.
apply Hin.
- (* MApp *)
simpl.
(** Something interesting happens in the [MApp] case. We obtain
_two_ induction hypotheses: One that applies when [x] occurs in
[s1] (which matches [re1]), and a second one that applies when [x]
occurs in [s2] (which matches [re2]). *)
simpl. rewrite In_app_iff in *.
destruct Hin as [Hin | Hin].
+ (* In x s1 *)
left. apply (IH1 Hin).
+ (* In x s2 *)
right. apply (IH2 Hin).
- (* MUnionL *)
simpl. rewrite In_app_iff.
left. apply (IH Hin).
- (* MUnionR *)
simpl. rewrite In_app_iff.
right. apply (IH Hin).
- (* MStar0 *)
destruct Hin.
- (* MStarApp *)
simpl.
(** Here again we get two induction hypotheses, and they illustrate
why we need induction on evidence for [exp_match], rather than
induction on the regular expression [re]: The latter would only
provide an induction hypothesis for strings that match [re], which
would not allow us to reason about the case [In x s2]. *)
rewrite In_app_iff in Hin.
destruct Hin as [Hin | Hin].
+ (* In x s1 *)
apply (IH1 Hin).
+ (* In x s2 *)
apply (IH2 Hin).
Qed.
(** **** Exercise: 4 stars, standard (re_not_empty)
Write a recursive function [re_not_empty] that tests whether a
regular expression matches some string. Prove that your function
is correct. *)
Fixpoint re_not_empty {T : Type} (re : reg_exp T) : bool :=
match re with
| EmptySet => false
| EmptyStr => true
| Char _ => true
| App re1 re2 => re_not_empty re1 && re_not_empty re2
| Union re1 re2 => re_not_empty re1 || re_not_empty re2
| Star _ => true
end.
Lemma re_not_empty_correct : forall T (re : reg_exp T),
(exists s, s =~ re) <-> re_not_empty re = true.
Proof.
split.
- (* -> *)
intros. destruct H.
induction H.
+ (* MEmptyStr *)
reflexivity.
+ (* MChar *)
reflexivity.
+ (* MApp *)
simpl. rewrite IHexp_match1. rewrite IHexp_match2. reflexivity.
+ (* MUnionL *)
simpl. rewrite IHexp_match. reflexivity.
+ (* MUnionR *)
simpl. rewrite IHexp_match. apply orb_true_iff. right. reflexivity.
+ (* MStar0 *)
reflexivity.
+ (* MStarApp *)
reflexivity.
- (* <- *)
intros.
induction re.
+ (* EmptySet *)
inversion H.
+ (* EmptyStr *)
exists []. apply MEmpty.
+ (* Char *)
exists [t]. apply MChar.
+ (* App *)
inversion H.
apply andb_true_iff in H1.
destruct H1.
apply IHre1 in H0. destruct H0 as [x0].
apply IHre2 in H1. destruct H1 as [x1].
exists (x0 ++ x1). apply MApp. apply H0. apply H1.
+ (* Union *)
simpl in H. apply orb_true_iff in H. destruct H.
* apply IHre1 in H. destruct H. exists x. apply MUnionL. apply H.
* apply IHre2 in H. destruct H. exists x. apply MUnionR. apply H.
+ (* Star *)
exists []. apply MStar0.
Qed.
(** [] *)
(* ================================================================= *)
(** ** The [remember] Tactic *)
(** One potentially confusing feature of the [induction] tactic is
that it will let you try to perform an induction over a term that
isn't sufficiently general. The effect of this is to lose
information (much as [destruct] without an [eqn:] clause can do),
and leave you unable to complete the proof. Here's an example: *)
Lemma star_app: forall T (s1 s2 : list T) (re : reg_exp T),
s1 =~ Star re ->
s2 =~ Star re ->
s1 ++ s2 =~ Star re.
Proof.
intros T s1 s2 re H1.
(** Just doing an [inversion] on [H1] won't get us very far in
the recursive cases. (Try it!). So we need induction (on
evidence!). Here is a naive first attempt: *)
generalize dependent s2.
induction H1
as [|x'|s1 re1 s2' re2 Hmatch1 IH1 Hmatch2 IH2
|s1 re1 re2 Hmatch IH|re1 s2' re2 Hmatch IH
|re''|s1 s2' re'' Hmatch1 IH1 Hmatch2 IH2].
(** But now, although we get seven cases (as we would expect from the
definition of [exp_match]), we have lost a very important bit of
information from [H1]: the fact that [s1] matched something of the
form [Star re]. This means that we have to give proofs for _all_
seven constructors of this definition, even though all but two of
them ([MStar0] and [MStarApp]) are contradictory. We can still
get the proof to go through for a few constructors, such as
[MEmpty]... *)
- (* MEmpty *)
simpl. intros s2 H. apply H.
(** ... but most cases get stuck. For [MChar], for instance, we
must show that
s2 =~ Char x' -> x' :: s2 =~ Char x',
which is clearly impossible. *)
- (* MChar. *) intros s2 H. simpl. (* Stuck... *)
Abort.
(** The problem is that [induction] over a Prop hypothesis only works
properly with hypotheses that are completely general, i.e., ones
in which all the arguments are variables, as opposed to more
complex expressions, such as [Star re].
(In this respect, [induction] on evidence behaves more like
[destruct]-without-[eqn:] than like [inversion].)
An awkward way to solve this problem is "manually generalizing"
over the problematic expressions by adding explicit equality
hypotheses to the lemma: *)
Lemma star_app: forall T (s1 s2 : list T) (re re' : reg_exp T),
re' = Star re ->
s1 =~ re' ->
s2 =~ Star re ->
s1 ++ s2 =~ Star re.
(** We can now proceed by performing induction over evidence directly,
because the argument to the first hypothesis is sufficiently
general, which means that we can discharge most cases by inverting
the [re' = Star re] equality in the context.
This idiom is so common that Coq provides a tactic to
automatically generate such equations for us, avoiding thus the
need for changing the statements of our theorems. *)
Abort.
(** The tactic [remember e as x] causes Coq to (1) replace all
occurrences of the expression [e] by the variable [x], and (2) add
an equation [x = e] to the context. Here's how we can use it to
show the above result: *)
Lemma star_app: forall T (s1 s2 : list T) (re : reg_exp T),
s1 =~ Star re ->
s2 =~ Star re ->
s1 ++ s2 =~ Star re.
Proof.
intros T s1 s2 re H1.
remember (Star re) as re'.
(** We now have [Heqre' : re' = Star re]. *)
generalize dependent s2.
induction H1
as [|x'|s1 re1 s2' re2 Hmatch1 IH1 Hmatch2 IH2
|s1 re1 re2 Hmatch IH|re1 s2' re2 Hmatch IH
|re''|s1 s2' re'' Hmatch1 IH1 Hmatch2 IH2].
(** The [Heqre'] is contradictory in most cases, allowing us to
conclude immediately. *)
- (* MEmpty *) discriminate.
- (* MChar *) discriminate.
- (* MApp *) discriminate.
- (* MUnionL *) discriminate.
- (* MUnionR *) discriminate.
(** The interesting cases are those that correspond to [Star]. Note
that the induction hypothesis [IH2] on the [MStarApp] case
mentions an additional premise [Star re'' = Star re], which
results from the equality generated by [remember]. *)
- (* MStar0 *)
injection Heqre' as Heqre''. intros s H. apply H.
- (* MStarApp *)
injection Heqre' as Heqre''.
intros s2 H1. rewrite <- app_assoc.
apply MStarApp.
+ apply Hmatch1.
+ apply IH2.
* rewrite Heqre''. reflexivity.
* apply H1.
Qed.
(** **** Exercise: 4 stars, standard, optional (exp_match_ex2) *)
(** The [MStar''] lemma below (combined with its converse, the
[MStar'] exercise above), shows that our definition of [exp_match]
for [Star] is equivalent to the informal one given previously. *)
Lemma MStar'' : forall T (s : list T) (re : reg_exp T),
s =~ Star re ->
exists ss : list (list T),
s = fold app ss []
/\ forall s', In s' ss -> s' =~ re.
Proof.
intros.
remember (Star re) as re'.
induction H; try discriminate.
- (* MStar0 *)
injection Heqre' as Heqre'.
exists []. split.
+ reflexivity.
+ intros. inversion H.
- (* MStarApp *)
injection Heqre' as Heqre'. subst re0.
assert (Star re = Star re). reflexivity.
apply IHexp_match2 in H1. clear IHexp_match2. destruct H1. destruct H1.
exists (s1::x). split.
+ (* show that (s1 :: x) = fold app (s1 :: x) *)
simpl. rewrite <- H1. reflexivity.
+ (* show that s1 =~ re and forall s' in x, s' =~ re *)
simpl. intros.
destruct H3.
* subst s1. apply H.
* apply H2 in H3. apply H3.
Qed.
(** [] *)
(** **** Exercise: 5 stars, advanced (weak_pumping)
One of the first really interesting theorems in the theory of
regular expressions is the so-called _pumping lemma_, which
states, informally, that any sufficiently long string [s] matching
a regular expression [re] can be "pumped" by repeating some middle
section of [s] an arbitrary number of times to produce a new
string also matching [re]. (For the sake of simplicity in this
exercise, we consider a slightly weaker theorem than is usually
stated in courses on automata theory.)
To get started, we need to define "sufficiently long." Since we
are working in a constructive logic, we actually need to be able
to calculate, for each regular expression [re], the minimum length
for strings [s] to guarantee "pumpability." *)
Module Pumping.
Fixpoint pumping_constant {T} (re : reg_exp T) : nat :=
match re with
| EmptySet => 1
| EmptyStr => 1
| Char _ => 2
| App re1 re2 =>
pumping_constant re1 + pumping_constant re2
| Union re1 re2 =>
pumping_constant re1 + pumping_constant re2
| Star r => pumping_constant r
end.
(** You may find these lemmas about the pumping constant useful when
proving the pumping lemma below. *)
Lemma pumping_constant_ge_1 :
forall T (re : reg_exp T),
pumping_constant re >= 1.
Proof.
intros T re. induction re.
- (* Emptyset *)
apply le_n.
- (* EmptyStr *)
apply le_n.
- (* Char *)
apply le_S. apply le_n.
- (* App *)
simpl.
apply le_trans with (n:=pumping_constant re1).
apply IHre1. apply le_plus_l.
- (* Union *)
simpl.
apply le_trans with (n:=pumping_constant re1).
apply IHre1. apply le_plus_l.
- (* Star *)
simpl. apply IHre.
Qed.
Lemma pumping_constant_0_false :
forall T (re : reg_exp T),
pumping_constant re = 0 -> False.
Proof.
intros T re H.
assert (Hp1 : pumping_constant re >= 1).
{ apply pumping_constant_ge_1. }
inversion Hp1 as [Hp1'| p Hp1' Hp1''].
- rewrite H in Hp1'. discriminate Hp1'.
- rewrite H in Hp1''. discriminate Hp1''.
Qed.
(** Next, it is useful to define an auxiliary function that repeats a
string (appends it to itself) some number of times. *)
Fixpoint napp {T} (n : nat) (l : list T) : list T :=
match n with
| 0 => []
| S n' => l ++ napp n' l
end.
(** This auxiliary lemma might also be useful in your proof of the
pumping lemma. *)
Lemma napp_plus: forall T (n m : nat) (l : list T),
napp (n + m) l = napp n l ++ napp m l.
Proof.
intros T n m l.
induction n as [|n IHn].
- reflexivity.
- simpl. rewrite IHn, app_assoc. reflexivity.
Qed.
Lemma napp_star :
forall T m s1 s2 (re : reg_exp T),
s1 =~ re -> s2 =~ Star re ->
napp m s1 ++ s2 =~ Star re.
Proof.
intros T m s1 s2 re Hs1 Hs2.
induction m.
- simpl. apply Hs2.
- simpl. rewrite <- app_assoc.
apply MStarApp.
+ apply Hs1.
+ apply IHm.
Qed.
Lemma napp_empty : forall T m, @napp T m [] = [].
Proof.
intros.
induction m.
reflexivity.
simpl. apply IHm.
Qed.
Lemma nil_eq_app_nil_nil : forall T (l1 l2 : list T),
l1 ++ l2 = [] -> l1 = [] /\ l2 = [].
Proof.
intros.
destruct l1; destruct l2.
- split; reflexivity.
- inversion H.
- inversion H.
- inversion H.
Qed.
Lemma napp_any_star :
forall T m s (re : reg_exp T),
s =~ Star re -> napp m s =~ Star re.
Proof.
intros.
induction m.
- simpl. apply MStar0.
- simpl. apply star_app. apply H. apply IHm.
Qed.
Lemma napp_any_star_one :
forall T m s (re : reg_exp T),
s =~ re -> napp m s =~ Star re.
Proof.
intros.
induction m.
- simpl. apply MStar0.
- simpl. apply star_app.
+ replace s with (s ++ []). apply MStarApp. apply H. apply MStar0.
apply app_nil_r.
+ apply IHm.
Qed.
Lemma napp_star_right :
forall T m s1 s2 (re : reg_exp T),
s1 =~ re -> s2 =~ Star re ->
s1 ++ napp m s2 =~ Star re.
Proof.
intros T m s1 s2 re Hs1 Hs2.
remember (Star re) as re'.
induction Hs2; try inversion Heqre'; try subst.
- rewrite napp_empty.
apply MStarApp. apply Hs1. apply MStar0.
- subst. apply MStarApp. apply Hs1.
clear Heqre'.
induction m.
+ simpl. apply MStar0.
+ simpl. apply star_app. apply MStarApp. apply Hs2_1. apply Hs2_2.
apply IHm. intro. apply MStarApp. apply Hs1. apply napp_any_star. apply Hs2_2.
intro. rewrite Heqre'. apply MStarApp. apply Hs1.
apply napp_any_star_one. apply Hs2_1.
(* Sorry for this really long and unstructured proof. This one alone
is difficult (4 star level I think).
Basically the idea goes like this. Divide the conditions into 3 cases.
- s2 = []
- s2 = (s0 ++ s3), m = 0
- s2 = (S0 ++ s3), m := S m
The first two are easy to prove. The last one is equivalent to proving
(s0 ++ s2) ++ (s0 ++ s2)^n =~ re*
subject to:
- s0 =~ re
- s2 =~ re*
It then requires some divide and conquer, and using some new lemmas
related to napp and and Star. Overall the idea is quite clear,
although the manipulation here is a bit dirty.
*)
Qed.
(** The (weak) pumping lemma itself says that, if [s =~ re] and if the
length of [s] is at least the pumping constant of [re], then [s]
can be split into three substrings [s1 ++ s2 ++ s3] in such a way
that [s2] can be repeated any number of times and the result, when
combined with [s1] and [s3] will still match [re]. Since [s2] is
also guaranteed not to be the empty string, this gives us
a (constructive!) way to generate strings matching [re] that are
as long as we like. *)
Lemma weak_pumping : forall T (re : reg_exp T) s,
s =~ re ->
pumping_constant re <= length s ->
exists s1 s2 s3,
s = s1 ++ s2 ++ s3 /\
s2 <> [] /\
forall m, s1 ++ napp m s2 ++ s3 =~ re.
(** You are to fill in the proof. Several of the lemmas about
[le] that were in an optional exercise earlier in this chapter
may be useful. *)
Proof.
intros T re s Hmatch.
induction Hmatch
as [ | x | s1 re1 s2 re2 Hmatch1 IH1 Hmatch2 IH2
| s1 re1 re2 Hmatch IH | re1 s2 re2 Hmatch IH
| re | s1 s2 re Hmatch1 IH1 Hmatch2 IH2 ].
- (* MEmpty *)
simpl. intros contra. inversion contra.
- (* MChar *)
simpl. intro contra. inversion contra. inversion H0.
- (* MApp *)
simpl. intro. rewrite app_length in H. apply add_le_cases in H.
destruct H.
+ (* pumping_const re1 <= len s1 *)
apply IH1 in H.
destruct H as [l1].
destruct H as [l2].
destruct H as [l3].
destruct H as [Happ H].
destruct H as [Hnonempty Hpump].
exists l1. exists l2. exists (l3 ++ s2).
split; try split.
* (* sum *)
rewrite Happ. rewrite <- app_assoc. rewrite <- app_assoc. reflexivity.
* (* l2 <> [] *)
apply Hnonempty.
* (* pumping *)
intro.
rewrite app_assoc. rewrite app_assoc.
rewrite <- (app_assoc _ l1).
apply (MApp (l1 ++ napp m l2 ++ l3)).
-- apply Hpump.
-- apply Hmatch2.
+ (* pumping_const re2 <= len s2 *)
apply IH2 in H.
destruct H as [l1].
destruct H as [l2].
destruct H as [l3].
destruct H as [Happ H].
destruct H as [Hnonempty Hpump].
exists (s1 ++ l1). exists l2. exists l3.
split; try split.
* (* sum *)
rewrite Happ. rewrite <- app_assoc. reflexivity.
* (* l2 <> [] *)
apply Hnonempty.
* (* pumping *)
intro.
rewrite <- app_assoc.
apply (MApp s1).
-- apply Hmatch1.
-- apply Hpump.
- (* MUnionL *)
simpl. intros. apply plus_le_left in H.
apply IH in H.
destruct H as [l1]. destruct H as [l2]. destruct H as [l3].
destruct H as [Happ H]. destruct H as [Hnonempty Hpump].
exists l1. exists l2. exists l3. split; try split.
+ (* sum *) apply Happ.
+ (* nonempty *) apply Hnonempty.
+ (* pumping *) intros. apply MUnionL. apply Hpump.
- (* MUnionR *)
simpl. intros. apply plus_le_right in H.
apply IH in H.
destruct H as [l1]. destruct H as [l2]. destruct H as [l3].
destruct H as [Happ H]. destruct H as [Hnonempty Hpump].
exists l1. exists l2. exists l3. split; try split.
+ (* sum *) apply Happ.
+ (* nonempty *) apply Hnonempty.
+ (* pumping *) intros. apply MUnionR. apply Hpump.
- (* MStar0 *)
simpl. intro. inversion H. apply pumping_constant_0_false in H1. destruct H1.
- (* MStarApp *)
simpl. rewrite app_length. intro.
assert (Hl: 1 <= length s1 + length s2).
{ apply (le_trans _ (pumping_constant re) _).
apply pumping_constant_ge_1.
apply H.
}
assert (Hcase: 1 <= length s1 \/ 1 <= length s2).
{ destruct (length s1).
+ simpl in Hl. right. apply Hl.
+ left. apply n_le_m__Sn_le_Sm. apply le_0_n.
}
assert (Hlen_ge_one: forall X (l: list X), 1 <= length l -> l <> []).
{ intros. destruct l. intro. simpl in H0.
apply PeanoNat.Nat.nle_succ_0 in H0. (* ~(S n <= 0) *)
inversion H0. simpl in H0. intro. inversion H1.
}
destruct Hcase as [Hlen|Hlen].
+ (* 1 <= length s1 *)
exists []. exists s1. exists s2. split; try split.
(* "sum" case is simply proved *)
* (* nonempty *) apply Hlen_ge_one. apply Hlen.
* (* pumping *) intro. simpl. apply napp_star. apply Hmatch1. apply Hmatch2.
+ (* 1 <= length s2 *)
exists s1. exists s2. exists []. split; try split.
* (* sum *) rewrite app_nil_r. reflexivity.
* (* nonempty *) apply Hlen_ge_one. apply Hlen.
* (* pumping *) intro. rewrite app_nil_r. apply napp_star_right.
apply Hmatch1. apply Hmatch2.
Qed.
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (pumping)
Now here is the usual version of the pumping lemma. In addition to
requiring that [s2 <> []], it also requires that [length s1 +
length s2 <= pumping_constant re]. *)
Theorem add_le_cases_reverse : forall n m p q,
n <= p /\ m <= q -> n + m <= p + q.
Proof.
intros.
generalize dependent m.
generalize dependent p.
generalize dependent q.
induction n.
- (* n := 0 *)
intros.
simpl in H. simpl. destruct H. apply (le_trans _ q). apply H0.
rewrite plus_comm. apply le_plus_l.
- (* n := S n *)
intros.
simpl. destruct H. destruct p. inversion H.
apply Sn_le_Sm__n_le_m in H. simpl. apply n_le_m__Sn_le_Sm.
apply IHn. split. apply H. apply H0.
Qed.
Theorem add_le_cases_stronger : forall n m p q,
n + m <= p + q -> n <= p \/ (~(n <= p) /\ m <= q).
Proof.
intros.
generalize dependent m.
generalize dependent p.
generalize dependent q.
induction n.
- (* n := 0 *)
intros.
simpl in H. left. apply O_le_n.
- (* n := S n *)
intros.
destruct p.
+ right. split.
* intro. inversion H0.
* apply (plus_le_left _ (S n) _).
rewrite plus_comm. simpl. simpl in H. apply H.
+ simpl in H. apply Sn_le_Sm__n_le_m in H. apply IHn in H. destruct H.
* left. apply n_le_m__Sn_le_Sm. apply H.
* right. destruct H. split.
-- intro. apply Sn_le_Sm__n_le_m in H1. apply H in H1. apply H1.
-- apply H0.
Qed.
Theorem not_le : forall n m,
~(n <= m) -> S m <= n.
Proof.
intro.
induction n.
- intros. exfalso. apply H. apply O_le_n.
- intros. destruct m.
+ apply n_le_m__Sn_le_Sm. apply O_le_n.
+ apply n_le_m__Sn_le_Sm. apply IHn. intro.
apply H. apply n_le_m__Sn_le_Sm. apply H0.
Qed.
Lemma match_empty : forall T (s : list T), s =~ EmptyStr -> s = [].
Proof.
intros.
induction s.
- reflexivity.
- inversion H.
Qed.
Lemma star_empty : forall T (s : list T), s =~ Star EmptyStr -> s = [].
Proof.
intros.
remember (Star EmptyStr) as re.
induction H; try inversion Heqre.
+ reflexivity.
+ subst. simpl in *. clear Heqre.
assert (@Star T EmptyStr = Star EmptyStr).
{ reflexivity. }
apply IHexp_match2 in H1. subst. apply match_empty in H. subst.
reflexivity.
Qed.
Lemma match_app_empty : forall T (re1 re2 : reg_exp T),
[ ] =~ App re1 re2 -> [] =~ re1 /\ [] =~ re2.
Proof.
intros.
inversion H.
subst. apply nil_eq_app_nil_nil in H1. destruct H1. subst. simpl.
split; assumption.
Qed.
Lemma len_ge_one: forall X (l: list X), 1 <= length l -> l <> [].
Proof.
intros. destruct l.
- simpl in H. inversion H.
- intro. inversion H0.
Qed.
Lemma app_not_nil: forall X (l1 l2: list X),
l1 ++ l2 <> [] <-> l1 <> [] \/ l2 <> [].
Proof.
intros.
split; intros.
- (* -> *)
destruct l1.
+ simpl in H. right. apply H.
+ left. intro. inversion H0.
- destruct H.
+ intro. apply nil_eq_app_nil_nil in H0.
destruct H0. subst. apply H. reflexivity.
+ intro. apply nil_eq_app_nil_nil in H0.
destruct H0. subst. apply H. reflexivity.
Qed.
Lemma star_nonempty : forall T (re : reg_exp T) (s : list T),
s =~ Star re ->
s <> [] ->
exists s1 s2, s = s1 ++ s2 /\ s1 <> [] /\ s1 =~ re /\ s2 =~ Star re.
Proof.
intros.
remember (Star re).
induction H; try inversion Heqr. subst.
- exfalso. apply H0. reflexivity.
- subst. apply app_not_nil in H0. destruct H0.
+ (* s1 <> [] *)
exists s1. exists s2. repeat split.
* apply H0.
* apply H.
* apply H1.
+ (* s2 <> [] *)
apply IHexp_match2 in Heqr.
destruct Heqr as [s21]. destruct H2 as [s22]. destruct H2. destruct H3. destruct H4.
destruct s1.
* (* s1 = [] *) subst.
exists s21. exists s22. repeat split.
-- apply H3.
-- apply H4.
-- apply H5.
* (* s1 <> [] *) subst.
exists (x::s1). exists (s21 ++ s22). repeat split.
-- intro. inversion H2.
-- apply H.
-- apply H1.
* apply H0.
Qed.
Lemma pumping : forall T (re : reg_exp T) s,
s =~ re ->
pumping_constant re <= length s ->
exists s1 s2 s3,
s = s1 ++ s2 ++ s3 /\
s2 <> [] /\
length s1 + length s2 <= pumping_constant re /\
forall m, s1 ++ napp m s2 ++ s3 =~ re.
(** You may want to copy your proof of weak_pumping below. *)
Proof.
intros T re s Hmatch.
induction Hmatch
as [ | x | s1 re1 s2 re2 Hmatch1 IH1 Hmatch2 IH2
| s1 re1 re2 Hmatch IH | re1 s2 re2 Hmatch IH
| re | s1 s2 re Hmatch1 IH1 Hmatch2 IH2 ].
- (* MEmpty *)
simpl. intros contra. inversion contra.
- (* MChar *)
simpl. intro contra. inversion contra. inversion H0.
- (* MApp *)
simpl. intro. rewrite app_length in H.
apply add_le_cases_stronger in H.
destruct H.
+ (* pumping_const re1 <= len s1 *)
apply IH1 in H.
destruct H as [l1].
destruct H as [l2].
destruct H as [l3].
destruct H as [Happ H].
destruct H as [Hnonempty H].
destruct H as [Hlen Hpump].
exists l1. exists l2. exists (l3 ++ s2).
split; try split; try split.
* (* sum *)
rewrite Happ. rewrite <- app_assoc. rewrite <- app_assoc. reflexivity.
* (* l2 <> [] *)
apply Hnonempty.
* (* len *)
apply (le_trans _ (pumping_constant re1)). apply Hlen.
apply le_plus_l.
* (* pumping *)
intro.
rewrite app_assoc. rewrite app_assoc.
rewrite <- (app_assoc _ l1).
apply (MApp (l1 ++ napp m l2 ++ l3)).
-- apply Hpump.
-- apply Hmatch2.
+ (* pumping_const re2 <= len s2 *)
destruct H as [Hlenre1 H].
apply IH2 in H.
destruct H as [l1].
destruct H as [l2].
destruct H as [l3].
destruct H as [Happ H].
destruct H as [Hnonempty H].
destruct H as [Hlen Hpump].
exists (s1 ++ l1). exists l2. exists l3.
split; try split; try split.
* (* sum *)
rewrite Happ. rewrite <- app_assoc. reflexivity.
* (* l2 <> [] *)
apply Hnonempty.
* (* len *)
rewrite app_length.
rewrite <- plus_assoc.
apply add_le_cases_reverse. split.
-- apply not_le in Hlenre1.
apply (le_trans _ (S (length s1))). apply le_S. apply le_n.
apply Hlenre1.
-- apply Hlen.
* (* pumping *)
intro.
rewrite <- app_assoc.
apply (MApp s1).
-- apply Hmatch1.
-- apply Hpump.
- (* MUnionL *)
simpl. intros. apply plus_le_left in H.
apply IH in H.
destruct H as [l1]. destruct H as [l2]. destruct H as [l3].
destruct H as [Happ H].
destruct H as [Hnonempty H].
destruct H as [Hlen Hpump].
exists l1. exists l2. exists l3. split; try split; try split.
+ (* sum *) apply Happ.
+ (* nonempty *) apply Hnonempty.
+ (* len *) apply (le_trans _ (pumping_constant re1)).
apply Hlen. apply le_plus_l.
+ (* pumping *) intros. apply MUnionL. apply Hpump.
- (* MUnionR *)
simpl. intros. apply plus_le_right in H.
apply IH in H.
destruct H as [l1]. destruct H as [l2]. destruct H as [l3].
destruct H as [Happ H].
destruct H as [Hnonempty H].
destruct H as [Hlen Hpump].
exists l1. exists l2. exists l3. split; try split; try split.
+ (* sum *) apply Happ.
+ (* nonempty *) apply Hnonempty.
+ (* len *) apply (le_trans _ (pumping_constant re2)).
apply Hlen. rewrite plus_comm. apply le_plus_l.
+ (* pumping *) intros. apply MUnionR. apply Hpump.
- (* MStar0 *)
simpl. intro. inversion H. apply pumping_constant_0_false in H1. destruct H1.
- (* MStarApp *)
simpl. rewrite app_length. intro.
destruct s1.
+ (* s1 = [] *)
apply star_nonempty in Hmatch2.
destruct Hmatch2 as
[s21 [s22 [Hs2sum [Hs21nonempty [Hs21match Hs22match]]]]].
subst. simpl in *. apply IH2 in H.
destruct H as [l1 [l2 [l3 [Happ [Hl2nonempty [Hl12len Hpump]]]]]].
exists l1. exists l2. exists l3.
repeat split.
* apply Happ.
* apply Hl2nonempty.
* apply Hl12len.
* apply Hpump.
* simpl in H. apply len_ge_one.
apply (le_trans _ (pumping_constant re)).
apply pumping_constant_ge_1.
apply H.
+ (* s1 <> [] *)
remember (x::s1) as s1_orig. simpl in *.
assert (pumping_constant re <= length s1_orig \/
length s1_orig <= pumping_constant re).
{ apply PeanoNat.Nat.le_ge_cases. }
destruct H0.
-- (* pumping_const re <= |s1_orig| *)
apply IH1 in H0.
destruct H0 as [l1 [l2 [l3 [Happ [Hl2nonempty [Hl12len Hpump]]]]]].
exists l1. exists l2. exists (l3 ++ s2). simpl in *. repeat split.
++ rewrite Happ.
rewrite (app_assoc _ _ _ s2).
rewrite (app_assoc _ _ _ s2).
reflexivity.
++ apply Hl2nonempty.
++ apply Hl12len.
++ intro.
rewrite (app_assoc _ _ _ s2).
rewrite (app_assoc _ _ _ s2).
apply MStarApp. apply Hpump.
apply Hmatch2.
-- (* pumping_const re >= |s1_orig| *)
exists []. exists s1_orig. exists s2. simpl in *. repeat split.
++ intro. subst. inversion H1.
++ apply H0.
++ intro.
apply napp_star.
apply Hmatch1.
apply Hmatch2.
Qed.
End Pumping.
(** [] *)
(* ################################################################# *)
(** * Case Study: Improving Reflection *)
(** We've seen in the [Logic] chapter that we often need to
relate boolean computations to statements in [Prop]. But
performing this conversion as we did it there can result in
tedious proof scripts. Consider the proof of the following
theorem: *)
Theorem filter_not_empty_In : forall n l,
filter (fun x => n =? x) l <> [] ->
In n l.
Proof.
intros n l. induction l as [|m l' IHl'].
- (* l = [] *)
simpl. intros H. apply H. reflexivity.
- (* l = m :: l' *)
simpl. destruct (n =? m) eqn:H.
+ (* n =? m = true *)
intros _. rewrite eqb_eq in H. rewrite H.
left. reflexivity.
+ (* n =? m = false *)
intros H'. right. apply IHl'. apply H'.
Qed.
(** In the first branch after [destruct], we explicitly apply
the [eqb_eq] lemma to the equation generated by
destructing [n =? m], to convert the assumption [n =? m
= true] into the assumption [n = m]; then we had to [rewrite]
using this assumption to complete the case. *)
(** We can streamline this by defining an inductive proposition that
yields a better case-analysis principle for [n =? m].
Instead of generating an equation such as [(n =? m) = true],
which is generally not directly useful, this principle gives us
right away the assumption we really need: [n = m]. *)
Inductive reflect (P : Prop) : bool -> Prop :=
| ReflectT (H : P) : reflect P true
| ReflectF (H : ~ P) : reflect P false.
(** The [reflect] property takes two arguments: a proposition
[P] and a boolean [b]. Intuitively, it states that the property
[P] is _reflected_ in (i.e., equivalent to) the boolean [b]: that
is, [P] holds if and only if [b = true]. To see this, notice
that, by definition, the only way we can produce evidence for
[reflect P true] is by showing [P] and then using the [ReflectT]
constructor. If we invert this statement, this means that it
should be possible to extract evidence for [P] from a proof of
[reflect P true]. Similarly, the only way to show [reflect P
false] is by combining evidence for [~ P] with the [ReflectF]
constructor.
It is easy to formalize this intuition and show that the
statements [P <-> b = true] and [reflect P b] are indeed
equivalent. First, the left-to-right implication: *)
Theorem iff_reflect : forall P b, (P <-> b = true) -> reflect P b.
Proof.
(* WORKED IN CLASS *)
intros P b H. destruct b.
- apply ReflectT. rewrite H. reflexivity.
- apply ReflectF. rewrite H. intros H'. discriminate.
Qed.
(** Now you prove the right-to-left implication: *)
(** **** Exercise: 2 stars, standard, especially useful (reflect_iff) *)
Theorem reflect_iff : forall P b, reflect P b -> (P <-> b = true).
Proof.
intros.
inversion H.
- (* p <-> true = true *)
split.
+ intro. reflexivity.
+ intro. apply H0.
- (* p <-> false = true *)
split.
+ intro. exfalso. apply H0. apply H2.
+ intro. discriminate H2.
Qed.
(** [] *)
(** The advantage of [reflect] over the normal "if and only if"
connective is that, by destructing a hypothesis or lemma of the
form [reflect P b], we can perform case analysis on [b] while at
the same time generating appropriate hypothesis in the two
branches ([P] in the first subgoal and [~ P] in the second). *)
Lemma eqbP : forall n m, reflect (n = m) (n =? m).
Proof.
intros n m. apply iff_reflect. rewrite eqb_eq. reflexivity.
Qed.
(** A smoother proof of [filter_not_empty_In] now goes as follows.
Notice how the calls to [destruct] and [rewrite] are combined into a
single call to [destruct]. *)
(** (To see this clearly, look at the two proofs of
[filter_not_empty_In] with Coq and observe the differences in
proof state at the beginning of the first case of the
[destruct].) *)
Theorem filter_not_empty_In' : forall n l,
filter (fun x => n =? x) l <> [] ->
In n l.
Proof.
intros n l. induction l as [|m l' IHl'].
- (* l = [] *)
simpl. intros H. apply H. reflexivity.
- (* l = m :: l' *)
simpl. destruct (eqbP n m) as [H | H].
+ (* n = m *)
intros _. rewrite H. left. reflexivity.
+ (* n <> m *)
intros H'. right. apply IHl'. apply H'.
Qed.
(** **** Exercise: 3 stars, standard, especially useful (eqbP_practice)
Use [eqbP] as above to prove the following: *)
Fixpoint count n l :=
match l with
| [] => 0
| m :: l' => (if n =? m then 1 else 0) + count n l'
end.
Theorem eqbP_practice : forall n l,
count n l = 0 -> ~(In n l).
Proof.
intros.
induction l.
- simpl. intro. apply H0.
- simpl in *. destruct (eqbP n x).
+ subst. simpl in H. inversion H.
+ intro. apply H0. destruct H1.
* symmetry. apply H1.
* simpl in *. apply IHl in H. apply H in H1. inversion H1.
Qed.
(** [] *)
(** This small example shows how reflection gives us a small gain in
convenience; in larger developments, using [reflect] consistently
can often lead to noticeably shorter and clearer proof scripts.
We'll see many more examples in later chapters and in _Programming
Language Foundations_.
The use of the [reflect] property has been popularized by
_SSReflect_, a Coq library that has been used to formalize
important results in mathematics, including as the 4-color theorem
and the Feit-Thompson theorem. The name SSReflect stands for
_small-scale reflection_, i.e., the pervasive use of reflection to
simplify small proof steps with boolean computations. *)
(* ################################################################# *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars, standard, especially useful (nostutter_defn)
Formulating inductive definitions of properties is an important
skill you'll need in this course. Try to solve this exercise
without any help at all.
We say that a list "stutters" if it repeats the same element
consecutively. (This is different from not containing duplicates:
the sequence [[1;4;1]] repeats the element [1] but does not
stutter.) The property "[nostutter mylist]" means that [mylist]
does not stutter. Formulate an inductive definition for
[nostutter]. *)
Inductive nostutter {X:Type} : list X -> Prop :=
| NoSt0 : nostutter []
| NoSt1 (x : X) : nostutter [x]
| NoStN (x y : X) (Hneq : x <> y)
(l : list X)
(H : nostutter (y :: l))
: nostutter (x :: y :: l)
.
(** Make sure each of these tests succeeds, but feel free to change
the suggested proof (in comments) if the given one doesn't work
for you. Your definition might be different from ours and still
be correct, in which case the examples might need a different
proof. (You'll notice that the suggested proofs use a number of
tactics we haven't talked about, to make them more robust to
different possible ways of defining [nostutter]. You can probably
just uncomment and use them as-is, but you can also prove each
example with more basic tactics.) *)
Example test_nostutter_1: nostutter [3;1;4;1;5;6].
Proof. repeat constructor; apply eqb_neq; auto. Qed.
Example test_nostutter_2: nostutter (@nil nat).
Proof. repeat constructor; apply eqb_neq; auto. Qed.
Example test_nostutter_3: nostutter [5].
Proof. repeat constructor; auto. Qed.
Example test_nostutter_4: not (nostutter [3;1;1;4]).
Proof.
intro.
repeat match goal with
h: nostutter _ |- _ =>
inversion h; clear h; subst
end.
contradiction; auto. Qed.
(* Do not modify the following line: *)
Definition manual_grade_for_nostutter : option (nat*string) := None.
(** [] *)
(** **** Exercise: 4 stars, advanced (filter_challenge)
Let's prove that our definition of [filter] from the [Poly]
chapter matches an abstract specification. Here is the
specification, written out informally in English:
A list [l] is an "in-order merge" of [l1] and [l2] if it contains
all the same elements as [l1] and [l2], in the same order as [l1]
and [l2], but possibly interleaved. For example,
[1;4;6;2;3]
is an in-order merge of
[1;6;2]
and
[4;3].
Now, suppose we have a set [X], a function [test: X->bool], and a
list [l] of type [list X]. Suppose further that [l] is an
in-order merge of two lists, [l1] and [l2], such that every item
in [l1] satisfies [test] and no item in [l2] satisfies test. Then
[filter test l = l1].
Translate this specification into a Coq theorem and prove
it. (You'll need to begin by defining what it means for one list
to be a merge of two others. Do this with an inductive relation,
not a [Fixpoint].) *)
Inductive in_order_merge {X : Type} : list X -> list X -> list X -> Prop :=
| IOM_Nil_L (l1 : list X) : in_order_merge l1 [] l1
| IOM_Nil_R (l2 : list X) : in_order_merge [] l2 l2
| IOM_L (x : X) (l1 l2 l : list X)
(H : in_order_merge l1 l2 l)
: in_order_merge (x :: l1) l2 (x :: l)
| IOM_R (x : X) (l1 l2 l : list X)
(H : in_order_merge l1 l2 l)
: in_order_merge l1 (x :: l2) (x :: l).
Theorem filter_in_order_merge : forall (X : Type) (l1 l2 l : list X) (test : X -> bool),
in_order_merge l1 l2 l ->
(forall x, In x l1 -> test x = true) ->
(forall x, In x l2 -> test x = false) ->
filter test l = l1.
Proof.
intros.
induction H.
- (* IMO_Nil_L *)
induction l1.
+ reflexivity.
+ simpl in *. rewrite H0. rewrite IHl1.
* reflexivity.
* intros. apply H0. right. apply H.
* left. reflexivity.
- (* IMO_Nil_R *)
induction l2.
+ reflexivity.
+ simpl in *. rewrite H1. rewrite IHl2.
* reflexivity.
* intros. apply H1. right. apply H.
* left. reflexivity.
- (* IMO_L *)
simpl in *.
rewrite H0. rewrite IHin_order_merge.
+ reflexivity.
+ intros. apply H0. right. apply H2.
+ intros. apply H1. apply H2.
+ left. reflexivity.
- (* IMO_R *)
simpl in *.
rewrite H1. rewrite IHin_order_merge.
+ reflexivity.
+ intros. apply H0. apply H2.
+ intros. apply H1. right. apply H2.
+ left. reflexivity.
Qed.
(* Do not modify the following line: *)
Definition manual_grade_for_filter_challenge : option (nat*string) := None.
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (filter_challenge_2)
A different way to characterize the behavior of [filter] goes like
this: Among all subsequences of [l] with the property that [test]
evaluates to [true] on all their members, [filter test l] is the
longest. Formalize this claim and prove it. *)
Inductive subseq' {X : Type} : list X -> list X -> Prop :=
| SS_Nil (l : list X) : subseq' [] l
| SS_Head (x : X) (sl l : list X) (H : subseq' sl l) : subseq' (x :: sl) (x :: l)
| SS_Skip (x : X) (sl l : list X) (H : subseq' sl l) : subseq' sl (x :: l)
.
Example subseq_ex1 : subseq' [1;2;3] [1;4;2;3;4].
Proof. repeat constructor. Qed.
Theorem filter_longest_subseq : forall (X : Type) (sl l fl : list X) (test : X -> bool),
fl = filter test l ->
subseq' sl l ->
(forall x, In x sl -> test x = true) ->
length sl <= length fl.
Proof.
intros.
generalize dependent fl.
induction H0.
- (* SS_Nil *)
intros. simpl. apply O_le_n.
- (* SS_Head *)
intros.
simpl in *.
destruct (test x) eqn:Htestx.
+ (* test x = true *)
subst. simpl in *. apply n_le_m__Sn_le_Sm.
apply IHsubseq'.
* intros. apply H1. right. apply H.
* reflexivity.
+ (* test x = false *)
subst. simpl in *.
assert (test x = true).
{ apply H1. left. reflexivity. }
rewrite H in Htestx. inversion Htestx.
- (* SS_Skip *)
intros.
simpl in *.
destruct (test x) eqn:Htestx.
+ (* test x = true *)
rewrite H. simpl.
apply le_S.
apply IHsubseq'.
* intros. apply H1. apply H2.
* subst. reflexivity.
+ (* test x = false *)
apply IHsubseq'.
intros. apply H1. apply H2. apply H.
Qed.
(* [] *)
(** **** Exercise: 4 stars, standard, optional (palindromes)
A palindrome is a sequence that reads the same backwards as
forwards.
- Define an inductive proposition [pal] on [list X] that
captures what it means to be a palindrome. (Hint: You'll need
three cases. Your definition should be based on the structure
of the list; just having a single constructor like
c : forall l, l = rev l -> pal l
may seem obvious, but will not work very well.)
- Prove ([pal_app_rev]) that
forall l, pal (l ++ rev l).
- Prove ([pal_rev] that)
forall l, pal l -> l = rev l.
*)
Inductive pal {X}: list X -> Prop :=
| Pal_Nil : pal []
| Pal_One (x : X) : pal [x]
| Pal_X (x : X) (l : list X) (H : pal l) : pal (x :: l ++ [x])
.
Theorem cons_app_assoc : forall X (x : X) (l1 l2 : list X),
x :: l1 ++ l2 = (x :: l1) ++ l2.
Proof. intros. reflexivity. Qed.
Theorem pal_app_rev : forall X (l : list X), pal (l ++ (rev l)).
Proof.
intros.
induction l as [|x l'].
- (* l = [] *)
simpl. apply Pal_Nil.
- (* l = x :: l' *)
simpl. rewrite app_assoc.
apply Pal_X. apply IHl'.
Qed.
Theorem pal_rev : forall X (l : list X), pal l -> l = rev l.
Proof.
intros.
induction H.
- (* Pal_Nil *)
reflexivity.
- (* Pal_One *)
reflexivity.
- (* Pal_X *)
simpl.
rewrite rev_l_x. simpl. rewrite <- IHpal.
reflexivity.
Qed.
(* Do not modify the following line: *)
Definition manual_grade_for_pal_pal_app_rev_pal_rev : option (nat*string) := None.
(** [] *)
(** **** Exercise: 5 stars, standard, optional (palindrome_converse)
Again, the converse direction is significantly more difficult, due
to the lack of evidence. Using your definition of [pal] from the
previous exercise, prove that
forall l, l = rev l -> pal l.
*)
(* [] *)
Lemma rev_head_tail : forall X (x : X) (l : list X),
(x :: l) = rev (x :: l) ->
l <> [] ->
exists l', l' = rev l' /\ l = l' ++ [x].
Proof.
simpl.
intros.
induction (rev l) eqn:revl.
- exists []. simpl. split.
+ reflexivity.
+ simpl in H. inversion H. exfalso. apply H0. apply H2.
- exists l0. simpl in *. injection H as Hx. split.
+ (* init l = rev (init l) *)
subst.
rewrite rev_app_distr in revl. simpl in revl. injection revl.
intro. symmetry. apply H.
+ (* init l ++ [x] = l *)
rewrite H. reflexivity.
Qed.
Lemma list_length_0 : forall X (l : list X), length l = 0 -> l = [].
Proof.
destruct l.
- reflexivity.
- intro. inversion H.
Qed.
Lemma list_length_1 : forall X (l : list X), length l = 1 -> exists x, l = [x].
Proof.
destruct l.
- intro. inversion H.
- intro. destruct l.
+ exists x. reflexivity.
+ simpl in H. inversion H.
Qed.
(* ev equivalent for odd numbers *)
Inductive od : nat -> Prop :=
| Od_One : od 1
| Od_SS n (H: od n) : od (S (S n)).
Lemma od_not_ev_iff: forall n, od n <-> ~(ev n).
Proof.
intro. split.
- (* -> *)
intro. induction H.
+ intro. inversion H.
+ intro. inversion H0. apply IHod. apply H2.
- (* <- *)
intro. destruct (evenb n) eqn:Hevenb.
+ apply even_bool_prop in Hevenb. apply ev_even_iff in Hevenb.
exfalso. apply H. apply Hevenb.
+ destruct (evenb_double_conv n).
rewrite Hevenb in H0.
assert (ev (double x)).
{ apply ev_double. }
generalize dependent n.
induction H1.
* intros. subst. apply Od_One.
* intros. subst. apply Od_SS.
apply IHev.
-- intro. apply H. apply ev_SS. apply H0.
-- simpl in Hevenb. simpl. apply Hevenb.
-- reflexivity.
Qed.
Lemma even_bool_prop_false : forall n, evenb n = false <-> ~(ev n).
Proof.
intros n. split.
- intros H. destruct (evenb_double_conv n) as [k Hk].
rewrite H in Hk.
generalize dependent n.
induction k.
+ intros. simpl in *. subst. intro. inversion H0.
+ intros. simpl in *. subst.
assert (evenb (S (double k)) = false).
{ simpl. simpl in H. apply H. }
apply IHk in H0.
intro. apply H0. apply evSS_ev. apply H1. reflexivity.
- intros.
destruct (evenb n) eqn:Hevn.
+ apply even_bool_prop in Hevn. apply ev_even_iff in Hevn.
exfalso. apply H. apply Hevn.
+ reflexivity.
Qed.
Lemma pal_converse_even : forall X (l : list X), ev (length l) -> l = rev l -> pal l.
Proof.
intros.
remember (length l) as n.
generalize dependent l.
induction H.
- intros.
symmetry in Heqn.
apply list_length_0 in Heqn. rewrite Heqn.
apply Pal_Nil.
- intros.
destruct l.
+ apply Pal_Nil.
+ destruct l.
* apply Pal_One.
* apply rev_head_tail in H0.
destruct H0 as [initl' [Hinitl'rev Hinitl'eq]].
rewrite Hinitl'eq.
apply Pal_X. apply IHev.
assert (length (x0 :: l) = length (initl' ++ [x])).
{ rewrite Hinitl'eq. reflexivity. }
assert (length l = length initl').
{ rewrite app_length in H0. simpl in H0.
rewrite <- plus_n_Sm in H0. rewrite <- plus_n_O in H0.
injection H0 as H0. apply H0.
}
rewrite <- H1.
simpl in Heqn. repeat injection Heqn as Heqn. apply Heqn.
apply Hinitl'rev.
intro. inversion H1.
Qed.
Lemma pal_converse_odd : forall X (l : list X), ~ev (length l) -> l = rev l -> pal l.
Proof.
intros.
remember (length l) as n.
generalize dependent l.
apply od_not_ev_iff in H.
induction H.
- intros.
symmetry in Heqn.
apply list_length_1 in Heqn. destruct Heqn. rewrite H.
apply Pal_One.
- intros.
destruct l.
+ apply Pal_Nil.
+ destruct l.
* apply Pal_One.
* apply rev_head_tail in H0.
destruct H0 as [initl' [Hinitl'rev Hinitl'eq]].
rewrite Hinitl'eq.
apply Pal_X. apply IHod.
assert (length (x0 :: l) = length (initl' ++ [x])).
{ rewrite Hinitl'eq. reflexivity. }
assert (length l = length initl').
{ rewrite app_length in H0. simpl in H0.
rewrite <- plus_n_Sm in H0. rewrite <- plus_n_O in H0.
injection H0 as H0. apply H0.
}
rewrite <- H1.
simpl in Heqn. repeat injection Heqn as Heqn. apply Heqn.
apply Hinitl'rev.
intro. inversion H1.
Qed.
Theorem pal_converse : forall X (l : list X), l = rev l -> pal l.
Proof.
intros.
remember (length l).
generalize dependent l.
destruct (evenb n) eqn:Hevn.
- (* even case *)
apply even_bool_prop in Hevn.
apply ev_even_iff in Hevn.
intros.
apply pal_converse_even. subst. apply Hevn. apply H.
- (* odd case *)
apply even_bool_prop_false in Hevn.
intros.
apply pal_converse_odd. subst. apply Hevn. apply H.
Qed.
(** **** Exercise: 4 stars, advanced, optional (NoDup)
Recall the definition of the [In] property from the [Logic]
chapter, which asserts that a value [x] appears at least once in a
list [l]: *)
(* Fixpoint In (A : Type) (x : A) (l : list A) : Prop :=
match l with
| [] => False
| x' :: l' => x' = x \/ In A x l'
end *)
(** Your first task is to use [In] to define a proposition [disjoint X
l1 l2], which should be provable exactly when [l1] and [l2] are
lists (with elements of type X) that have no elements in
common. *)
Definition disjoint {X} (l1 l2 : list X) :=
(forall x, In x l1 -> ~(In x l2)) /\ (forall x, In x l2 -> ~(In x l1)).
(** Next, use [In] to define an inductive proposition [NoDup X
l], which should be provable exactly when [l] is a list (with
elements of type [X]) where every member is different from every
other. For example, [NoDup nat [1;2;3;4]] and [NoDup
bool []] should be provable, while [NoDup nat [1;2;1]] and
[NoDup bool [true;true]] should not be. *)
Inductive no_dup {X} : list X -> Prop :=
| NoDup_Nil : no_dup []
| NoDup_Cons (x : X) (l : list X)
(Hno_dup : no_dup l)
(Hnot_in : ~(In x l)) :
no_dup (x :: l)
.
(** Finally, state and prove one or more interesting theorems relating
[disjoint], [NoDup] and [++] (list append). *)
Theorem disjoint_app_no_dup : forall X (l1 l2 : list X),
no_dup (l1 ++ l2) -> disjoint l1 l2.
Proof.
intros.
remember (l1 ++ l2).
generalize dependent l1.
generalize dependent l2.
induction H.
- (* [] = l1 ++ l2 *)
intros.
symmetry in Heql.
apply Pumping.nil_eq_app_nil_nil in Heql. destruct Heql.
split; subst.
+ intros. inversion H.
+ intros. inversion H.
- (* x :: l = l1 ++ l2 *)
intros.
unfold disjoint in *.
split; intros.
+ (* x0 in l1 -> ~ (x0 in l2) *)
destruct l1.
* simpl in *. inversion H0.
* simpl in *. inversion Heql. inversion Heql.
apply IHno_dup in H3. destruct H3.
destruct H0.
-- subst. intro. apply Hnot_in.
apply In_app_iff. right. apply H0.
-- apply H1 in H0. apply H0.
+ (* x0 in l2 -> ~ (x0 in l1) *)
destruct l1.
* simpl in *. intro. inversion H1.
* simpl in *. inversion Heql. inversion Heql.
apply IHno_dup in H3. destruct H3.
intro. destruct H6.
-- (* prove that x0 in l2 -> x0 <> x1 *)
apply Hnot_in.
rewrite H5. apply In_app_iff. right. subst. apply H0.
-- (* prove that x0 in l2 -> x0 not in l1 *)
subst. clear H4.
apply (H3 x0). apply H0. apply H6.
Qed.
(* Note that the converse may not be true. Here's an counter example
l1 = [1; 1]
l2 = [2]
l1 ++ l2 = [1; 1; 2]
Then disjoint l1 l2 holds, but no_dup (l1 ++ l2) doesn't hold.
*)
(* Do not modify the following line: *)
Definition manual_grade_for_NoDup_disjoint_etc : option (nat*string) := None.
(** [] *)
(** **** Exercise: 4 stars, advanced, optional (pigeonhole_principle)
The _pigeonhole principle_ states a basic fact about counting: if
we distribute more than [n] items into [n] pigeonholes, some
pigeonhole must contain at least two items. As often happens, this
apparently trivial fact about numbers requires non-trivial
machinery to prove, but we now have enough... *)
(** First prove an easy useful lemma. *)
Lemma in_split : forall (X:Type) (x:X) (l:list X),
In x l ->
exists l1 l2, l = l1 ++ x :: l2.
Proof.
intros.
induction l.
- inversion H.
- simpl in *.
destruct H.
+ exists []. exists l. subst. simpl. reflexivity.
+ apply IHl in H. destruct H as [l1 [l2]].
exists (x0 :: l1). exists l2. subst. simpl. reflexivity.
Qed.
(** Now define a property [repeats] such that [repeats X l] asserts
that [l] contains at least one repeated element (of type [X]). *)
Inductive repeats {X:Type} : list X -> Prop :=
| Rep_Rep (x : X) (l : list X) (H : In x l) : repeats (x :: l)
| Rep_Add (x : X) (l : list X) (H : repeats l) : repeats (x :: l)
.
(* Do not modify the following line: *)
Definition manual_grade_for_check_repeats : option (nat*string) := None.
(** Now, here's a way to formalize the pigeonhole principle. Suppose
list [l2] represents a list of pigeonhole labels, and list [l1]
represents the labels assigned to a list of items. If there are
more items than labels, at least two items must have the same
label -- i.e., list [l1] must contain repeats.
This proof is much easier if you use the [excluded_middle]
hypothesis to show that [In] is decidable, i.e., [forall x l, (In x
l) \/ ~ (In x l)]. However, it is also possible to make the proof
go through _without_ assuming that [In] is decidable; if you
manage to do this, you will not need the [excluded_middle]
hypothesis. *)
Theorem pigeonhole_principle: forall (X:Type) (l1 l2:list X),
excluded_middle ->
(forall x, In x l1 -> In x l2) ->
length l2 < length l1 ->
repeats l1.
Proof.
intros X l1 l2 Hem.
generalize dependent l2.
induction l1 as [|x l1' IHl1'].
- (* l1 = [] *)
intros. inversion H0.
- (* l1 = x :: l1' *)
simpl. intros.
assert ((In x l1') \/ ~(In x l1')).
{ apply Hem. }
destruct H1.
+ (* x in l1' -> l1 repeats *)
apply Rep_Rep. apply H1.
+ (* x not in l1' -> l1' repeats *)
apply Rep_Add.
assert (In x l2).
{ apply H. left. reflexivity. }
apply in_split in H2. destruct H2 as [l21 [l22]].
apply (IHl1' (l21 ++ l22)).
* (* show that forall k, k in l1' -> k in (l21 ++ l22) *)
intro k. intros.
assert (x <> k).
{ intro. subst. apply H1. apply H3. }
assert (In k l2).
{ apply H. right. apply H3. }
rewrite H2 in H5.
rewrite In_app_iff in H5. simpl in H5.
rewrite In_app_iff.
destruct H5; try destruct H5.
-- (* k in l21 *)
left. apply H5.
-- (* k = x, contradiction *)
exfalso. apply H4. apply H5.
-- (* k in l22 *)
right. apply H5.
* (* show that len(l21 + l22) < len(l1') *)
rewrite H2 in H0. rewrite app_length in H0.
simpl in H0. rewrite <- plus_n_Sm in H0.
apply Sn_le_Sm__n_le_m in H0.
rewrite app_length. unfold lt.
apply H0.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Extended Exercise: A Verified Regular-Expression Matcher *)
(** We have now defined a match relation over regular expressions and
polymorphic lists. We can use such a definition to manually prove that
a given regex matches a given string, but it does not give us a
program that we can run to determine a match autmatically.
It would be reasonable to hope that we can translate the definitions
of the inductive rules for constructing evidence of the match relation
into cases of a recursive function that reflects the relation by recursing
on a given regex. However, it does not seem straightforward to define
such a function in which the given regex is a recursion variable
recognized by Coq. As a result, Coq will not accept that the function
always terminates.
Heavily-optimized regex matchers match a regex by translating a given
regex into a state machine and determining if the state machine
accepts a given string. However, regex matching can also be
implemented using an algorithm that operates purely on strings and
regexes without defining and maintaining additional datatypes, such as
state machines. We'll implemement such an algorithm, and verify that
its value reflects the match relation. *)
(** We will implement a regex matcher that matches strings represented
as lists of ASCII characters: *)
Require Import Coq.Strings.Ascii.
Definition string := list ascii.
(** The Coq standard library contains a distinct inductive definition
of strings of ASCII characters. However, we will use the above
definition of strings as lists as ASCII characters in order to apply
the existing definition of the match relation.
We could also define a regex matcher over polymorphic lists, not lists
of ASCII characters specifically. The matching algorithm that we will
implement needs to be able to test equality of elements in a given
list, and thus needs to be given an equality-testing
function. Generalizing the definitions, theorems, and proofs that we
define for such a setting is a bit tedious, but workable. *)
(** The proof of correctness of the regex matcher will combine
properties of the regex-matching function with properties of the
[match] relation that do not depend on the matching function. We'll go
ahead and prove the latter class of properties now. Most of them have
straightforward proofs, which have been given to you, although there
are a few key lemmas that are left for you to prove. *)
(** Each provable [Prop] is equivalent to [True]. *)
Lemma provable_equiv_true : forall (P : Prop), P -> (P <-> True).
Proof.
intros.
split.
- intros. constructor.
- intros _. apply H.
Qed.
(** Each [Prop] whose negation is provable is equivalent to [False]. *)
Lemma not_equiv_false : forall (P : Prop), ~P -> (P <-> False).
Proof.
intros.
split.
- apply H.
- intros. destruct H0.
Qed.
(** [EmptySet] matches no string. *)
Lemma null_matches_none : forall (s : string), (s =~ EmptySet) <-> False.
Proof.
intros.
apply not_equiv_false.
unfold not. intros. inversion H.
Qed.
(** [EmptyStr] only matches the empty string. *)
Lemma empty_matches_eps : forall (s : string), s =~ EmptyStr <-> s = [ ].
Proof.
split.
- intros. inversion H. reflexivity.
- intros. rewrite H. apply MEmpty.
Qed.
(** [EmptyStr] matches no non-empty string. *)
Lemma empty_nomatch_ne : forall (a : ascii) s, (a :: s =~ EmptyStr) <-> False.
Proof.
intros.
apply not_equiv_false.
unfold not. intros. inversion H.
Qed.
(** [Char a] matches no string that starts with a non-[a] character. *)
Lemma char_nomatch_char :
forall (a b : ascii) s, b <> a -> (b :: s =~ Char a <-> False).
Proof.
intros.
apply not_equiv_false.
unfold not.
intros.
apply H.
inversion H0.
reflexivity.
Qed.
(** If [Char a] matches a non-empty string, then the string's tail is empty. *)
Lemma char_eps_suffix : forall (a : ascii) s, a :: s =~ Char a <-> s = [ ].
Proof.
split.
- intros. inversion H. reflexivity.
- intros. rewrite H. apply MChar.
Qed.
(** [App re0 re1] matches string [s] iff [s = s0 ++ s1], where [s0]
matches [re0] and [s1] matches [re1]. *)
Lemma app_exists : forall (s : string) re0 re1,
s =~ App re0 re1 <->
exists s0 s1, s = s0 ++ s1 /\ s0 =~ re0 /\ s1 =~ re1.
Proof.
intros.
split.
- intros. inversion H. exists s1, s2. split.
* reflexivity.
* split. apply H3. apply H4.
- intros [ s0 [ s1 [ Happ [ Hmat0 Hmat1 ] ] ] ].
rewrite Happ. apply (MApp s0 _ s1 _ Hmat0 Hmat1).
Qed.
(** **** Exercise: 3 stars, standard, optional (app_ne)
[App re0 re1] matches [a::s] iff [re0] matches the empty string
and [a::s] matches [re1] or [s=s0++s1], where [a::s0] matches [re0]
and [s1] matches [re1].
Even though this is a property of purely the match relation, it is a
critical observation behind the design of our regex matcher. So (1)
take time to understand it, (2) prove it, and (3) look for how you'll
use it later. *)
Lemma app_ne : forall (a : ascii) s re0 re1,
a :: s =~ (App re0 re1) <->
([ ] =~ re0 /\ a :: s =~ re1) \/
exists s0 s1, s = s0 ++ s1 /\ a :: s0 =~ re0 /\ s1 =~ re1.
Proof.
intros. split.
- (* -> *)
intros.
inversion H. subst.
destruct s1 as [|x s1'].
+ (* s1 = [] *)
left. split. apply H3. simpl. apply H4.
+ (* s1 = x :: s1' *)
right. exists s1'. exists s2. simpl in *. injection H1 as Heq H2. subst.
split.
* (* s = s0 ++ s1 *)
reflexivity.
* (* a::s0 =~ re0 /\ s1 =~ re1 *)
split. apply H3. apply H4.
- (* <- *)
intros. destruct H.
+ (* [] =~ re0 /\ ... case *)
destruct H. apply (MApp []). apply H. apply H0.
+ (* exists ... case *)
destruct H as [s0 [s1 [Hs [Hm1 Hm2]]]].
subst.
apply (MApp (a::s0)). apply Hm1. apply Hm2.
Qed.
(** [] *)
(** [s] matches [Union re0 re1] iff [s] matches [re0] or [s] matches [re1]. *)
Lemma union_disj : forall (s : string) re0 re1,
s =~ Union re0 re1 <-> s =~ re0 \/ s =~ re1.
Proof.
intros. split.
- intros. inversion H.
+ left. apply H2.
+ right. apply H1.
- intros [ H | H ].
+ apply MUnionL. apply H.
+ apply MUnionR. apply H.
Qed.
(** **** Exercise: 3 stars, standard, optional (star_ne)
[a::s] matches [Star re] iff [s = s0 ++ s1], where [a::s0] matches
[re] and [s1] matches [Star re]. Like [app_ne], this observation is
critical, so understand it, prove it, and keep it in mind.
Hint: you'll need to perform induction. There are quite a few
reasonable candidates for [Prop]'s to prove by induction. The only one
that will work is splitting the [iff] into two implications and
proving one by induction on the evidence for [a :: s =~ Star re]. The
other implication can be proved without induction.
In order to prove the right property by induction, you'll need to
rephrase [a :: s =~ Star re] to be a [Prop] over general variables,
using the [remember] tactic. *)
Lemma star_ne : forall (a : ascii) s re,
a :: s =~ Star re <->
exists s0 s1, s = s0 ++ s1 /\ a :: s0 =~ re /\ s1 =~ Star re.
Proof.
intros.
split.
- (* -> *)
intros.
(* this part is almost the same as the "star_nonempty"
lemma I proved for pumping lemma. So I'll just use the result. *)
intros.
apply (Pumping.star_nonempty ascii re (a :: s)) in H.
destruct H as [s1 [s2 [Hsum [Hnonempty [Hm1 Hm2]]]]].
destruct s1.
+ exfalso. apply Hnonempty. reflexivity.
+ simpl in *. injection Hsum. intros. subst.
exists s1. exists s2. split; try split.
* apply Hm1.
* apply Hm2.
+ intro. inversion H0.
- intros.
destruct H as [s1 [s2 [Hsum [Hm1 Hm2]]]].
subst.
apply (MStarApp (a::s1)).
apply Hm1.
apply Hm2.
Qed.
(** [] *)
(** The definition of our regex matcher will include two fixpoint
functions. The first function, given regex [re], will evaluate to a
value that reflects whether [re] matches the empty string. The
function will satisfy the following property: *)
Definition refl_matches_eps m :=
forall re : reg_exp ascii, reflect ([ ] =~ re) (m re).
(** **** Exercise: 2 stars, standard, optional (match_eps)
Complete the definition of [match_eps] so that it tests if a given
regex matches the empty string: *)
Fixpoint match_eps (re: reg_exp ascii) : bool :=
match re with
| EmptyStr => true
| Star _ => true
| App re1 re2 => match_eps re1 && match_eps re2
| Union re1 re2 => match_eps re1 || match_eps re2
| _ => false
end.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (match_eps_refl)
Now, prove that [match_eps] indeed tests if a given regex matches
the empty string. (Hint: You'll want to use the reflection lemmas
[ReflectT] and [ReflectF].) *)
Lemma match_eps_refl : refl_matches_eps match_eps.
Proof.
unfold refl_matches_eps.
intros.
induction re.
- (* EmptySet *)
apply ReflectF. intro. inversion H.
- (* EmptyStr *)
apply ReflectT. apply MEmpty.
- (* Char (t : T) *)
apply ReflectF. intro. inversion H.
- (* App (r1 r2 : reg_exp T) *)
destruct (match_eps re1) eqn:Hre1;
destruct (match_eps re2) eqn:Hre2;
simpl;
rewrite Hre1;
rewrite Hre2;
simpl;
try apply ReflectT;
try apply ReflectF;
inversion IHre1;
inversion IHre2.
+ apply (MApp [] re1 [] re2). apply H. apply H0.
+ intro. apply H0. inversion H1. subst.
apply Pumping.nil_eq_app_nil_nil in H2. destruct H2. subst.
simpl in *. apply H6.
+ intro. apply H. inversion H1. subst.
apply Pumping.nil_eq_app_nil_nil in H2. destruct H2. subst.
simpl in *. apply H5.
+ intro. apply H. inversion H1. subst.
apply Pumping.nil_eq_app_nil_nil in H2. destruct H2. subst.
simpl in *. apply H5.
- (* Union (r1 r2 : reg_exp T) *)
destruct (match_eps re1) eqn:Hre1;
destruct (match_eps re2) eqn:Hre2;
simpl;
rewrite Hre1;
rewrite Hre2;
simpl;
try apply ReflectT;
try apply ReflectF;
inversion IHre1;
inversion IHre2.
+ apply MUnionL. apply H.
+ apply MUnionL. apply H.
+ apply MUnionR. apply H0.
+ intro. inversion H1.
* subst. apply H. apply H4.
* subst. apply H0. apply H4.
- (* Star (r : reg_exp T). *)
simpl. apply ReflectT. apply MStar0.
Qed.
(** [] *)
(** We'll define other functions that use [match_eps]. However, the
only property of [match_eps] that you'll need to use in all proofs
over these functions is [match_eps_refl]. *)
(** The key operation that will be performed by our regex matcher will
be to iteratively construct a sequence of regex derivatives. For each
character [a] and regex [re], the derivative of [re] on [a] is a regex
that matches all suffixes of strings matched by [re] that start with
[a]. I.e., [re'] is a derivative of [re] on [a] if they satisfy the
following relation: *)
Definition is_der re (a : ascii) re' :=
forall s, a :: s =~ re <-> s =~ re'.
(** A function [d] derives strings if, given character [a] and regex
[re], it evaluates to the derivative of [re] on [a]. I.e., [d]
satisfies the following property: *)
Definition derives d := forall a re, is_der re a (d a re).
(** **** Exercise: 3 stars, standard, optional (derive)
Define [derive] so that it derives strings. One natural
implementation uses [match_eps] in some cases to determine if key
regex's match the empty string. *)
Fixpoint derive (a : ascii) (re : reg_exp ascii) : reg_exp ascii :=
match re with
| EmptySet => EmptySet
| EmptyStr => EmptySet
| Char t => (if eqb t a then EmptyStr else EmptySet)
| App r1 r2 => if match_eps r1
then Union (App (derive a r1) r2)
(derive a r2)
else App (derive a r1) r2
| Union r1 r2 => Union (derive a r1) (derive a r2)
| Star r => App (derive a r) (Star r)
end.
(** [] *)
(** The [derive] function should pass the following tests. Each test
establishes an equality between an expression that will be
evaluated by our regex matcher and the final value that must be
returned by the regex matcher. Each test is annotated with the
match fact that it reflects. *)
Example c := ascii_of_nat 99.
Example d := ascii_of_nat 100.
(** "c" =~ EmptySet: *)
Example test_der0 : match_eps (derive c (EmptySet)) = false.
Proof. reflexivity. Qed.
(** "c" =~ Char c: *)
Example test_der1 : match_eps (derive c (Char c)) = true.
Proof. reflexivity. Qed.
(** "c" =~ Char d: *)
Example test_der2 : match_eps (derive c (Char d)) = false.
Proof. reflexivity. Qed.
(** "c" =~ App (Char c) EmptyStr: *)
Example test_der3 : match_eps (derive c (App (Char c) EmptyStr)) = true.
Proof. reflexivity. Qed.
(** "c" =~ App EmptyStr (Char c): *)
Example test_der4 : match_eps (derive c (App EmptyStr (Char c))) = true.
Proof. reflexivity. Qed.
(** "c" =~ Star c: *)
Example test_der5 : match_eps (derive c (Star (Char c))) = true.
Proof. reflexivity. Qed.
(** "cd" =~ App (Char c) (Char d): *)
Example test_der6 :
match_eps (derive d (derive c (App (Char c) (Char d)))) = true.
Proof. reflexivity. Qed.
(** "cd" =~ App (Char d) (Char c): *)
Example test_der7 :
match_eps (derive d (derive c (App (Char d) (Char c)))) = false.
Proof. reflexivity. Qed.
(* added a few more verifier to validate my implementation *)
(* "cd" =~ (cd)* *)
Example test_der8 :
match_eps (derive d (derive c (Star (App (Char c) (Char d))))) = true.
Proof. simpl. reflexivity. Qed.
(* "c" =~ (c|d)* *)
Example test_der9 :
match_eps (derive d (derive c (Star (Union (Char c) (Char d))))) = true.
Proof. simpl. reflexivity. Qed.
(* "cc" =~ c* *)
Example test_der10 :
match_eps (derive c (derive c (Star (Char c)))) = true.
Proof. simpl. reflexivity. Qed.
(** **** Exercise: 4 stars, standard, optional (derive_corr)
Prove that [derive] in fact always derives strings.
Hint: one proof performs induction on [re], although you'll need
to carefully choose the property that you prove by induction by
generalizing the appropriate terms.
Hint: if your definition of [derive] applies [match_eps] to a
particular regex [re], then a natural proof will apply
[match_eps_refl] to [re] and destruct the result to generate cases
with assumptions that the [re] does or does not match the empty
string.
Hint: You can save quite a bit of work by using lemmas proved
above. In particular, to prove many cases of the induction, you
can rewrite a [Prop] over a complicated regex (e.g., [s =~ Union
re0 re1]) to a Boolean combination of [Prop]'s over simple
regex's (e.g., [s =~ re0 \/ s =~ re1]) using lemmas given above
that are logical equivalences. You can then reason about these
[Prop]'s naturally using [intro] and [destruct]. *)
Lemma derive_corr : derives derive.
Proof.
unfold derives. intros.
induction re; simpl; unfold is_der; intros.
- (* EmptySet *)
split.
+ intros. inversion H.
+ intros. inversion H.
- (* EmptyStr *)
split.
+ intros. inversion H.
+ intros. inversion H.
- (* Char (t : T) *)
destruct (eqb_spec t a); subst.
+ split.
* intros. inversion H. subst. apply MEmpty.
* intros. inversion H. apply MChar.
+ assert (Hneq: (t <> a)).
{ apply n. }
apply eqb_neq in n.
split.
* intros. inversion H. subst. exfalso. apply Hneq. reflexivity.
* intros. inversion H.
- (* App (r1 r2 : reg_exp T) *)
destruct (match_eps_refl re1).
+ (* match_eps re1 = true *)
split.
* (* a :: s =~ re1 re2 -> ... *)
intros. inversion H0. subst.
destruct s1 eqn:Hs1; simpl in *.
-- apply MUnionR. apply IHre2. subst. apply H5.
-- apply MUnionL. inversion H1. subst.
apply MApp. apply IHre1. apply H4. apply H5.
* (* ... -> a :: s =~ re1 re2 *)
intros. inversion H0. inversion H3. subst.
-- apply (MApp (a :: s0)). apply IHre1. apply H8. apply H9.
-- apply (MApp []). apply H. apply IHre2. apply H3.
+ (* match_eps re1 = false *)
split.
* (* a::s =~ s1 s2 -> s =~ (derive a re1) re2 *)
intros. inversion H0. subst. destruct s1.
-- (* s1 = [], contra *) exfalso. apply H. apply H4.
-- simpl in *. inversion H1. subst. apply MApp.
apply IHre1. apply H4. apply H5.
* (* s =~ (derive a re1) re2 -> a::s =~ s1 s2 *)
intros. inversion H0. subst. apply (MApp (a::s1)).
apply IHre1. apply H4. apply H5.
- (* Union (r1 r2 : reg_exp T) *)
split.
+ (* a :: s =~ Union re1 re2 -> s =~ Union (dervie a re1) (derive a re2) *)
intros. inversion H; subst.
* apply MUnionL. apply IHre1. apply H2.
* apply MUnionR. apply IHre2. apply H1.
+ (* s =~ Union (derive a re1) (derive a re2) -> a :: s =~ Union re1 re2 *)
intros. inversion H; subst.
* apply MUnionL. apply IHre1. apply H2.
* apply MUnionR. apply IHre2. apply H1.
- (* Star (r : reg_exp T). *)
split.
+ (* a :: s =~ Star re -> s =~ App (derive a re) (Star re) *)
intros. apply star_ne in H.
destruct H as [s0 [s1 [Heq [Hm1 Hm2]]]].
subst.
apply (MApp s0).
* apply IHre. apply Hm1.
* apply Hm2.
+ (* s =~ App (derive a re) (Star re) -> a :: s =~ Star re *)
intros. inversion H. subst.
apply (MStarApp (a::s1)).
* apply IHre. apply H3.
* apply H4.
Qed.
(** [] *)
(** We'll define the regex matcher using [derive]. However, the only
property of [derive] that you'll need to use in all proofs of
properties of the matcher is [derive_corr]. *)
(** A function [m] matches regexes if, given string [s] and regex [re],
it evaluates to a value that reflects whether [s] is matched by
[re]. I.e., [m] holds the following property: *)
Definition matches_regex m : Prop :=
forall (s : string) re, reflect (s =~ re) (m s re).
(** **** Exercise: 2 stars, standard, optional (regex_match)
Complete the definition of [regex_match] so that it matches
regexes. *)
Fixpoint regex_match (s : string) (re : reg_exp ascii) : bool :=
match s with
| [] => match_eps re
| (a::s') => regex_match s' (derive a re)
end.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (regex_refl)
Finally, prove that [regex_match] in fact matches regexes.
Hint: if your definition of [regex_match] applies [match_eps] to
regex [re], then a natural proof applies [match_eps_refl] to [re]
and destructs the result to generate cases in which you may assume
that [re] does or does not match the empty string.
Hint: if your definition of [regex_match] applies [derive] to
character [x] and regex [re], then a natural proof applies
[derive_corr] to [x] and [re] to prove that [x :: s =~ re] given
[s =~ derive x re], and vice versa. *)
Theorem regex_refl : matches_regex regex_match.
Proof.
unfold matches_regex. intros. apply iff_reflect.
split.
- generalize dependent re. induction s.
+ intros. simpl. destruct (match_eps_refl re).
* reflexivity.
* exfalso. apply H0. apply H.
+ intros. simpl. apply IHs. apply derive_corr. apply H.
- generalize dependent re. induction s.
+ intros. simpl in H. destruct (match_eps_refl re).
* apply H0.
* inversion H.
+ simpl. intros. apply derive_corr. apply IHs. apply H.
Qed.
(** [] *)
(* 2020-09-09 20:51 *)
|
//////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE SD Card Controller IP Core ////
//// ////
//// sdc_controller.v ////
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Top level entity. ////
//// This core is based on the "sd card controller" project from ////
//// http://opencores.org/project,sdcard_mass_storage_controller ////
//// but has been largely rewritten. A lot of effort has been ////
//// made to make the core more generic and easily usable ////
//// with OSs like Linux. ////
//// - data transfer commands are not fixed ////
//// - data transfer block size is configurable ////
//// - multiple block transfer support ////
//// - R2 responses (136 bit) support ////
//// ////
//// Author(s): ////
//// - Marek Czerski, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson ([email protected]) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sdc_controller(
// WISHBONE common
wb_clk_i,
wb_rst_i,
// WISHBONE slave
wb_dat_i,
wb_dat_o,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_cyc_i,
wb_stb_i,
wb_ack_o,
// WISHBONE master
m_wb_dat_o,
m_wb_dat_i,
m_wb_adr_o,
m_wb_sel_o,
m_wb_we_o,
m_wb_cyc_o,
m_wb_stb_o,
m_wb_ack_i,
m_wb_cti_o,
m_wb_bte_o,
//SD BUS
sd_cmd_dat_i,
sd_cmd_out_o,
sd_cmd_oe_o,
//card_detect,
sd_dat_dat_i,
sd_dat_out_o,
sd_dat_oe_o,
sd_clk_o_pad,
sd_clk_i_pad,
int_cmd,
int_data
);
input wb_clk_i;
input wb_rst_i;
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
//input card_detect;
input [7:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
output [2:0] m_wb_cti_o;
output [1:0] m_wb_bte_o;
input wire [3:0] sd_dat_dat_i;
output wire [3:0] sd_dat_out_o;
output wire sd_dat_oe_o;
input wire sd_cmd_dat_i;
output wire sd_cmd_out_o;
output wire sd_cmd_oe_o;
output sd_clk_o_pad;
input wire sd_clk_i_pad;
output int_cmd, int_data;
//SD clock
wire sd_clk_o; //Sd_clk used in the system
wire [3:0] wr_wbm_sel;
wire [`BLKSIZE_W+`BLKCNT_W-1:0] xfersize;
wire [31:0] wbm_adr;
wire go_idle;
wire cmd_start_wb_clk;
wire cmd_start_sd_clk;
wire cmd_start;
wire [1:0] cmd_setting;
wire cmd_start_tx;
wire [39:0] cmd;
wire [119:0] cmd_response;
wire cmd_crc_ok;
wire cmd_index_ok;
wire cmd_finish;
wire d_write;
wire d_read;
wire [31:0] data_in_rx_fifo;
wire [31:0] data_out_tx_fifo;
wire start_tx_fifo;
wire start_rx_fifo;
wire tx_fifo_empty;
wire tx_fifo_full;
wire rx_fifo_full;
wire sd_data_busy;
wire data_busy;
wire data_crc_ok;
wire rd_fifo;
wire we_fifo;
wire data_start_rx;
wire data_start_tx;
wire cmd_int_rst_wb_clk;
wire cmd_int_rst_sd_clk;
wire cmd_int_rst;
wire data_int_rst_wb_clk;
wire data_int_rst_sd_clk;
wire data_int_rst;
//wb accessible registers
wire [31:0] argument_reg_wb_clk;
wire [`CMD_REG_SIZE-1:0] command_reg_wb_clk;
wire [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg_wb_clk;
wire [`DATA_TIMEOUT_W-1:0] data_timeout_reg_wb_clk;
wire [0:0] software_reset_reg_wb_clk;
wire [31:0] response_0_reg_wb_clk;
wire [31:0] response_1_reg_wb_clk;
wire [31:0] response_2_reg_wb_clk;
wire [31:0] response_3_reg_wb_clk;
wire [`BLKSIZE_W-1:0] block_size_reg_wb_clk;
wire [0:0] controll_setting_reg_wb_clk;
wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg_wb_clk;
wire [`INT_DATA_SIZE-1:0] data_int_status_reg_wb_clk;
wire [`INT_CMD_SIZE-1:0] cmd_int_enable_reg_wb_clk;
wire [`INT_DATA_SIZE-1:0] data_int_enable_reg_wb_clk;
wire [`BLKCNT_W-1:0] block_count_reg_wb_clk;
wire [31:0] dma_addr_reg_wb_clk;
wire [7:0] clock_divider_reg_wb_clk;
wire [31:0] argument_reg_sd_clk;
wire [`CMD_REG_SIZE-1:0] command_reg_sd_clk;
wire [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg_sd_clk;
wire [`DATA_TIMEOUT_W-1:0] data_timeout_reg_sd_clk;
wire [0:0] software_reset_reg_sd_clk;
wire [31:0] response_0_reg_sd_clk;
wire [31:0] response_1_reg_sd_clk;
wire [31:0] response_2_reg_sd_clk;
wire [31:0] response_3_reg_sd_clk;
wire [`BLKSIZE_W-1:0] block_size_reg_sd_clk;
wire [0:0] controll_setting_reg_sd_clk;
wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg_sd_clk;
wire [`INT_DATA_SIZE-1:0] data_int_status_reg_sd_clk;
wire [`BLKCNT_W-1:0] block_count_reg_sd_clk;
wire [1:0] dma_addr_reg_sd_clk;
wire [7:0] clock_divider_reg_sd_clk;
sd_clock_divider clock_divider0(
.CLK (sd_clk_i_pad),
.DIVIDER (clock_divider_reg_sd_clk),
.RST (wb_rst_i),
.SD_CLK (sd_clk_o)
);
assign sd_clk_o_pad = sd_clk_o ;
sd_cmd_master sd_cmd_master0(
.sd_clk (sd_clk_o),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.start_i (cmd_start_sd_clk),
.int_status_rst_i(cmd_int_rst_sd_clk),
.setting_o (cmd_setting),
.start_xfr_o (cmd_start_tx),
.go_idle_o (go_idle),
.cmd_o (cmd),
.response_i (cmd_response),
.crc_ok_i (cmd_crc_ok),
.index_ok_i (cmd_index_ok),
.busy_i (sd_data_busy),
.finish_i (cmd_finish),
.argument_i (argument_reg_sd_clk),
.command_i (command_reg_sd_clk),
.timeout_i (cmd_timeout_reg_sd_clk),
.int_status_o (cmd_int_status_reg_sd_clk),
.response_0_o (response_0_reg_sd_clk),
.response_1_o (response_1_reg_sd_clk),
.response_2_o (response_2_reg_sd_clk),
.response_3_o (response_3_reg_sd_clk)
);
sd_cmd_serial_host cmd_serial_host0(
.sd_clk (sd_clk_o),
.rst (wb_rst_i |
software_reset_reg_sd_clk[0] |
go_idle),
.setting_i (cmd_setting),
.cmd_i (cmd),
.start_i (cmd_start_tx),
.finish_o (cmd_finish),
.response_o (cmd_response),
.crc_ok_o (cmd_crc_ok),
.index_ok_o (cmd_index_ok),
.cmd_dat_i (sd_cmd_dat_i),
.cmd_out_o (sd_cmd_out_o),
.cmd_oe_o (sd_cmd_oe_o)
);
sd_data_master sd_data_master0(
.sd_clk (sd_clk_o),
.rst (wb_rst_i |
software_reset_reg_sd_clk[0]),
.start_tx_i (data_start_tx),
.start_rx_i (data_start_rx),
.timeout_i (data_timeout_reg_sd_clk),
.d_write_o (d_write),
.d_read_o (d_read),
.start_tx_fifo_o (start_tx_fifo),
.start_rx_fifo_o (start_rx_fifo),
.tx_fifo_empty_i (tx_fifo_empty),
.tx_fifo_full_i (tx_fifo_full),
.rx_fifo_full_i (rx_fifo_full),
.xfr_complete_i (!data_busy),
.crc_ok_i (data_crc_ok),
.int_status_o (data_int_status_reg_sd_clk),
.int_status_rst_i (data_int_rst_sd_clk)
);
sd_data_serial_host sd_data_serial_host0(
.sd_clk (sd_clk_o),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.data_in (data_out_tx_fifo),
.rd (rd_fifo),
.data_out (data_in_rx_fifo),
.we (we_fifo),
.DAT_oe_o (sd_dat_oe_o),
.DAT_dat_o (sd_dat_out_o),
.DAT_dat_i (sd_dat_dat_i),
.blksize (block_size_reg_sd_clk),
.bus_4bit (controll_setting_reg_sd_clk[0]),
.blkcnt (block_count_reg_sd_clk),
.start ({d_read, d_write}),
.byte_alignment (dma_addr_reg_sd_clk),
.sd_data_busy (sd_data_busy),
.busy (data_busy),
.crc_ok (data_crc_ok)
);
sd_fifo_filler sd_fifo_filler0(
.wb_clk (wb_clk_i),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.wbm_adr_o (wbm_adr),
.wbm_we_o (m_wb_we_o),
.wbm_dat_o (m_wb_dat_o),
.wbm_dat_i (m_wb_dat_i),
.wbm_cyc_o (m_wb_cyc_o),
.wbm_stb_o (m_wb_stb_o),
.wbm_ack_i (m_wb_ack_i),
.en_rx_i (start_rx_fifo),
.en_tx_i (start_tx_fifo),
.adr_i (dma_addr_reg_wb_clk),
.sd_clk (sd_clk_o),
.dat_i (data_in_rx_fifo),
.dat_o (data_out_tx_fifo),
.wr_i (we_fifo),
.rd_i (rd_fifo),
.sd_empty_o (tx_fifo_empty),
.sd_full_o (rx_fifo_full),
.wb_empty_o (),
.wb_full_o (tx_fifo_full)
);
assign xfersize = (block_size_reg_wb_clk + 1'b1) * (block_count_reg_wb_clk + 1'b1);
sd_wb_sel_ctrl sd_wb_sel_ctrl0(
.wb_clk (wb_clk_i),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.ena (start_rx_fifo),
.base_adr_i (dma_addr_reg_wb_clk),
.wbm_adr_i (wbm_adr),
.xfersize (xfersize),
.wbm_sel_o (wr_wbm_sel)
);
sd_data_xfer_trig sd_data_xfer_trig0 (
.sd_clk (sd_clk_o),
.rst (wb_rst_i | software_reset_reg_sd_clk[0]),
.cmd_with_data_start_i (cmd_start_sd_clk &
(command_reg_sd_clk[`CMD_WITH_DATA] !=
2'b00)),
.r_w_i (command_reg_sd_clk[`CMD_WITH_DATA] ==
2'b01),
.cmd_int_status_i (cmd_int_status_reg_sd_clk),
.start_tx_o (data_start_tx),
.start_rx_o (data_start_rx)
);
sd_controller_wb sd_controller_wb0(
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_adr_i (wb_adr_i),
.wb_sel_i (wb_sel_i),
.wb_we_i (wb_we_i),
.wb_stb_i (wb_stb_i),
.wb_cyc_i (wb_cyc_i),
.wb_ack_o (wb_ack_o),
.cmd_start (cmd_start),
.data_int_rst (data_int_rst),
.cmd_int_rst (cmd_int_rst),
.argument_reg (argument_reg_wb_clk),
.command_reg (command_reg_wb_clk),
.response_0_reg (response_0_reg_wb_clk),
.response_1_reg (response_1_reg_wb_clk),
.response_2_reg (response_2_reg_wb_clk),
.response_3_reg (response_3_reg_wb_clk),
.software_reset_reg (software_reset_reg_wb_clk),
.cmd_timeout_reg (cmd_timeout_reg_wb_clk),
.data_timeout_reg (data_timeout_reg_wb_clk),
.block_size_reg (block_size_reg_wb_clk),
.controll_setting_reg (controll_setting_reg_wb_clk),
.cmd_int_status_reg (cmd_int_status_reg_wb_clk),
.cmd_int_enable_reg (cmd_int_enable_reg_wb_clk),
.clock_divider_reg (clock_divider_reg_wb_clk),
.block_count_reg (block_count_reg_wb_clk),
.dma_addr_reg (dma_addr_reg_wb_clk),
.data_int_status_reg (data_int_status_reg_wb_clk),
.data_int_enable_reg (data_int_enable_reg_wb_clk)
);
//clock domain crossing regiters
//assign cmd_start_sd_clk = cmd_start_wb_clk;
//assign data_int_rst_sd_clk = data_int_rst_wb_clk;
//assign cmd_int_rst_sd_clk = cmd_int_rst_wb_clk;
//assign argument_reg_sd_clk = argument_reg_wb_clk;
//assign command_reg_sd_clk = command_reg_wb_clk;
//assign response_0_reg_wb_clk = response_0_reg_sd_clk;
//assign response_1_reg_wb_clk = response_1_reg_sd_clk;
//assign response_2_reg_wb_clk = response_2_reg_sd_clk;
//assign response_3_reg_wb_clk = response_3_reg_sd_clk;
//assign software_reset_reg_sd_clk = software_reset_reg_wb_clk;
//assign timeout_reg_sd_clk = timeout_reg_wb_clk;
//assign block_size_reg_sd_clk = block_size_reg_wb_clk;
//assign controll_setting_reg_sd_clk = controll_setting_reg_wb_clk;
//assign cmd_int_status_reg_wb_clk = cmd_int_status_reg_sd_clk;
//assign clock_divider_reg_sd_clk = clock_divider_reg_wb_clk;
//assign block_count_reg_sd_clk = block_count_reg_wb_clk;
//assign dma_addr_reg_sd_clk = dma_addr_reg_wb_clk;
//assign data_int_status_reg_wb_clk = data_int_status_reg_sd_clk;
edge_detect cmd_start_edge(.rst(wb_rst_i), .clk(wb_clk_i), .sig(cmd_start), .rise(cmd_start_wb_clk), .fall());
edge_detect data_int_rst_edge(.rst(wb_rst_i), .clk(wb_clk_i), .sig(data_int_rst), .rise(data_int_rst_wb_clk), .fall());
edge_detect cmd_int_rst_edge(.rst(wb_rst_i), .clk(wb_clk_i), .sig(cmd_int_rst), .rise(cmd_int_rst_wb_clk), .fall());
monostable_domain_cross cmd_start_cross(wb_rst_i, wb_clk_i, cmd_start_wb_clk, sd_clk_o, cmd_start_sd_clk);
monostable_domain_cross data_int_rst_cross(wb_rst_i, wb_clk_i, data_int_rst_wb_clk, sd_clk_o, data_int_rst_sd_clk);
monostable_domain_cross cmd_int_rst_cross(wb_rst_i, wb_clk_i, cmd_int_rst_wb_clk, sd_clk_o, cmd_int_rst_sd_clk);
bistable_domain_cross #(32) argument_reg_cross(wb_rst_i, wb_clk_i, argument_reg_wb_clk, sd_clk_o, argument_reg_sd_clk);
bistable_domain_cross #(`CMD_REG_SIZE) command_reg_cross(wb_rst_i, wb_clk_i, command_reg_wb_clk, sd_clk_o, command_reg_sd_clk);
bistable_domain_cross #(32) response_0_reg_cross(wb_rst_i, sd_clk_o, response_0_reg_sd_clk, wb_clk_i, response_0_reg_wb_clk);
bistable_domain_cross #(32) response_1_reg_cross(wb_rst_i, sd_clk_o, response_1_reg_sd_clk, wb_clk_i, response_1_reg_wb_clk);
bistable_domain_cross #(32) response_2_reg_cross(wb_rst_i, sd_clk_o, response_2_reg_sd_clk, wb_clk_i, response_2_reg_wb_clk);
bistable_domain_cross #(32) response_3_reg_cross(wb_rst_i, sd_clk_o, response_3_reg_sd_clk, wb_clk_i, response_3_reg_wb_clk);
bistable_domain_cross software_reset_reg_cross(wb_rst_i, wb_clk_i, software_reset_reg_wb_clk, sd_clk_o, software_reset_reg_sd_clk);
bistable_domain_cross #(`CMD_TIMEOUT_W) cmd_timeout_reg_cross(wb_rst_i, wb_clk_i, cmd_timeout_reg_wb_clk, sd_clk_o, cmd_timeout_reg_sd_clk);
bistable_domain_cross #(`DATA_TIMEOUT_W) data_timeout_reg_cross(wb_rst_i, wb_clk_i, data_timeout_reg_wb_clk, sd_clk_o, data_timeout_reg_sd_clk);
bistable_domain_cross #(`BLKSIZE_W) block_size_reg_cross(wb_rst_i, wb_clk_i, block_size_reg_wb_clk, sd_clk_o, block_size_reg_sd_clk);
bistable_domain_cross #(1) controll_setting_reg_cross(wb_rst_i, wb_clk_i, controll_setting_reg_wb_clk, sd_clk_o, controll_setting_reg_sd_clk);
bistable_domain_cross #(`INT_CMD_SIZE) cmd_int_status_reg_cross(wb_rst_i, sd_clk_o, cmd_int_status_reg_sd_clk, wb_clk_i, cmd_int_status_reg_wb_clk);
bistable_domain_cross #(8) clock_divider_reg_cross(wb_rst_i, wb_clk_i, clock_divider_reg_wb_clk, sd_clk_i_pad, clock_divider_reg_sd_clk);
bistable_domain_cross #(`BLKCNT_W) block_count_reg_cross(wb_rst_i, wb_clk_i, block_count_reg_wb_clk, sd_clk_o, block_count_reg_sd_clk);
bistable_domain_cross #(2) dma_addr_reg_cross(wb_rst_i, wb_clk_i, dma_addr_reg_wb_clk[1:0], sd_clk_o, dma_addr_reg_sd_clk);
bistable_domain_cross #(`INT_DATA_SIZE) data_int_status_reg_cross(wb_rst_i, sd_clk_o, data_int_status_reg_sd_clk, wb_clk_i, data_int_status_reg_wb_clk);
assign m_wb_cti_o = 3'b000;
assign m_wb_bte_o = 2'b00;
assign int_cmd = |(cmd_int_status_reg_wb_clk & cmd_int_enable_reg_wb_clk);
assign int_data = |(data_int_status_reg_wb_clk & data_int_enable_reg_wb_clk);
assign m_wb_sel_o = m_wb_cyc_o & m_wb_we_o ? wr_wbm_sel : 4'b1111;
assign m_wb_adr_o = {wbm_adr[31:2], 2'b00};
endmodule
|
//-----------------------------------------------------
// Design Name : hw2_A
// File Name : hw2_A.v
// Function : This program designs an One-Pulse Generator.
// Coder : hydai
//-----------------------------------------------------
`timescale 1 ns/1 ns
module hw2_A (
input in,
input clk,
input rst_n,
output reg out
);
parameter S0 = 0;
parameter S1 = 1;
reg state, nextState;
reg tmp_out;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= S0;
end else begin
state <= nextState;
end // end of if-else block
end // end of always
// next state
always @(*) begin
case (state)
S0: begin // previous input is 0
if (in == 0) begin // 0 -> 0 => 0
nextState <= 0;
end else begin // 0 -> 1 => 1
nextState <= 1;
end
end
S1: begin // previous input is 1
if (in == 0) begin // 1 -> 0 => 0
nextState <= 0;
end else begin // 1 -> 1 => 0;
nextState <= 1;
end
end
endcase
end
// output
always @(*) begin
case (state)
S0: begin // previous input is 0
if (in == 0) begin // 0 -> 0 => 0
tmp_out <= 0;
end else begin // 0 -> 1 => 1
tmp_out <= 1;
end
end
S1: begin // previous input is 1
tmp_out <= 0;
end
endcase
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
out <= 0;
end else begin
out <= tmp_out;
end
end
endmodule // endmodule of hw2_A
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOBUFSRC_FUNCTIONAL_V
`define SKY130_FD_SC_LP__ISOBUFSRC_FUNCTIONAL_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__isobufsrc (
X ,
SLEEP,
A
);
// Module ports
output X ;
input SLEEP;
input A ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X, not0_out, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOBUFSRC_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.02.2016 16:25:28
// Design Name:
// Module Name: SPI
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI#
(
parameter integer m = 15, // Data packet size
parameter integer Tbit = 100 // Clocks for 1 bit
)
(
// External interfaces
output reg [127:0] str0 = " ",
output reg [127:0] str1 = " ",
output reg [127:0] str2 = " ",
output reg [127:0] str3 = " ",
input wire GCLK,
input wire RST,
input wire [7:0] SW,
// Transmission start switch
input wire st,
// SPI Master bus
input wire MASTER_MISO,
output wire MASTER_MOSI,
output wire MASTER_SS,
output wire MASTER_SCLK,
// SPI Slave bus
input wire SLAVE_MOSI,
output wire SLAVE_MISO,
input wire SLAVE_SS,
input wire SLAVE_SCLK
);
// I/O buffers
wire [m-1:0] MASTER_RX;
reg [m-1:0] MASTER_TX = 15'b010110000110110;
wire [m-1:0] SLAVE_RX;
reg [m-1:0] SLAVE_TX = 15'b110101100110110;
wire clk_Tbit; // Clock for bit timing
SPI_MASTER #(.m(m)) spi_master
(
.clk(GCLK),
.ce(clk_Tbit),
.st(st),
.SCLK(MASTER_SCLK),
.MISO(MASTER_MISO),
.MOSI(MASTER_MOSI),
.LOAD(MASTER_SS),
.TX_MD(MASTER_TX),
.RX_SD(MASTER_RX),
.RST(RST),
.LEFT(1'b1),
.R(1'b1)
);
SPI_SLAVE #(.m(m)) spi_slave
(
.GCLK(GCLK),
.RST(RST),
.SCLK(SLAVE_SCLK),
.MISO(SLAVE_MISO),
.MOSI(SLAVE_MOSI),
.SS(SLAVE_SS),
.DIN(SLAVE_TX),
.DOUT(SLAVE_RX)
);
CLK_DIV clk_div
(
.GCLK(GCLK),
.out(clk_Tbit),
.T(Tbit)
);
// Display
wire [127:0] str_m_tx;
wire [127:0] str_s_tx;
wire [127:0] str_m_rx;
wire [127:0] str_s_rx;
always @(posedge clk_Tbit) begin
if (SW[6] == 1'b1) begin
str0 <= "SPI Interface ";
str1 <= SW[7] ? " M-R TX/SLAVE RX" : " SLAVE TX/M-R RX";
str2 <= SW[7] ? str_m_tx : str_s_tx;
str3 <= SW[7] ? str_s_rx : str_m_rx;
end
end
D2STR_B #(.len(m)) oled_d2b_0
(
.str(str_m_tx),
.d(MASTER_TX)
);
D2STR_B #(.len(m)) oled_d2b_1
(
.str(str_s_tx),
.d(SLAVE_TX)
);
D2STR_B #(.len(m)) oled_d2b_2
(
.str(str_m_rx),
.d(MASTER_RX)
);
D2STR_B #(.len(m)) oled_d2b_3
(
.str(str_s_rx),
.d(SLAVE_RX)
);
endmodule |
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