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`include "fpga_registers.v"
// Name: WcaAdc.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaAdc
(
input clock_sample,
input clock_rf_data,
input reset,
input enable,
//DMA Interface .
input wire [13:0] dmaCtrl, //DMA address and control lines { addr[9:0], nAddrStrobe, nReadStrobe, nWriteStrobe, cpuclock }
inout wire [15:0] dmaData, //Tri-state I/O data.
//RF Chip Interface. 2 Receive channels, 1 transmit.
input wire rx1_iqsel,
input wire [11:0] rx1_data,
input wire rx2_iqsel,
input wire [11:0] rx2_data,
output reg [11:0] tx1_data,
output wire tx1_iqsel,
output wire rf1_rxen,
output wire rf1_txen,
output wire rf2_rxen,
output wire rf_rxclk, //Lime receive ADC clock.
output wire rf_txclk, //Lime transmit ADC clock.
//DAC Output dma_data
input wire [11:0] tx_i,
input wire [11:0] tx_q,
//Buffer ADC input dma_data.
output reg [11:0] rx0_i,
output reg [11:0] rx0_q,
output reg [11:0] rx1_i,
output reg [11:0] rx1_q
);
//RF Interface. (WRITE)
// bit# | Description
//-------|----------------------------------------------------------
// 0-1 RX Input Mode
// 0 = txd Loopback (counter in UT version)
// 1 = rf1_rx input.
// 2 = rf2_rx input.
// 3 = Fixed Test Pattern DSP0 i = AA0, q = BB1; DSP2 (if available) i=CC0, q=DD1;
//
// 2 "rf1_rxen" output line - set to 1 to enable, 0 to disable. Enables disables the
// Lime chip #1 receive ADC function. If RF Interfane not enabled in FR_MCTRL_0,
// this is disabled.
//
// 3 "rf1_txen" output pin state - set to 1 to enable, 0 to disable Enables / disables the
// Lime chip #1 transmit DAC function. If RF interface not enabled in FR_MCTRL_0,
// this is disabled.
//
// 4 "rf2_rxen" output pin state - set to 1 to enable, 0 to disable. Enables / disables the
// Lime chip #2 receive ADC function. If RF interface not enabled in FR_MCTRL_0,
// this is disabled.
//
// 5 "rf_rxclk" enable (1) / (0). If enabled the rf_rxclk pin will turn on and provide clock
// signals to the receive functions of the Lime chips. If disabled, clock output will be low.
// If RF interface not enabled in FR_MCTRL_0, clock output is disabled.
//
// 6 "rf_txclk" enable (1) / (0). If enabled the tx_rxclk pin will turn on and provide clock
// signals to the transmit functions of Lime chip #1. If disabled, clock output will be low.
// If RF interface not enabled in FR_MCTRL_0, clock output is disabled.
//
// 7-15 Reserved.
//
wire [15:0] rf_ctrl;
WcaWriteWordReg #(`FR_RF_CTRL) sr_rf_ctrl
(.reset(reset), .out( rf_ctrl), .dmaCtrl(dmaCtrl), .dmaData(dmaData) );
//------------------------------------------------------------
// Lime chip control.
//------------------------------------------------------------
assign rf1_rxen = enable & rf_ctrl[2];
assign rf1_txen = enable & rf_ctrl[3];
assign rf2_rxen = enable & rf_ctrl[4];
assign rf_rxclk = (enable & rf_ctrl[5]) ? clock_rf_data : 1'b0;
assign rf_txclk = (enable & rf_ctrl[6]) ? clock_rf_data : 1'b0;
assign tx1_iqsel = (rf1_txen) ? clock_sample : 1'b0;
//------------------------------------------------------------
// Rx1 and Rx2 Interface.Selector.
//------------------------------------------------------------
//Break out receive dma_data into separate I/Q paths
//so we can process in dsp.
always @(posedge clock_rf_data)
begin
case( { enable, rf_ctrl[1:0]} )
3'b100 : // 0 is loop back.tx back on to rx.
begin
if( clock_sample )
begin
rx0_i <= #1 tx_i[11:0];
rx1_i <= #1 tx_i[11:0];
end
else
begin
rx0_q <= #1 tx_q[11:0];
rx1_q <= #1 tx_q[11:0];
end
end
3'b101 : //1 is rx 1.
begin
if( rx1_iqsel )
rx0_i <= #1 rx1_data;
else
rx0_q <= #1 rx1_data;
if( rx2_iqsel )
rx1_i <= #1 rx2_data;
else
rx1_q <= #1 rx2_data;
end
3'b110 : // 2 is rx 2.
begin
if( rx2_iqsel )
rx0_i <= #1 rx2_data;
else
rx0_q <= #1 rx2_data;
if( rx1_iqsel )
rx1_i <= #1 rx1_data;
else
rx1_q <= #1 rx1_data;
end
3'b111 : //3 is test pattern.
begin
rx0_i <= #1 12'd256;
rx0_q <= #1 -12'd256;
rx1_i <= #1 12'd256;
rx1_q <= #1 -12'd256;
end
default: //Default is nothing.
begin
rx0_i <= #1 12'd0;
rx0_q <= #2 12'd0;
rx1_i <= #2 12'd0;
rx1_q <= #2 12'd0;
end
endcase
end
//------------------------------------------------------------
// RSSI Implementation
//------------------------------------------------------------
wire [7:0] rssi_q0;
wire [7:0] rssi_i0;
//Construct Inphase RSSI function
rssi RssiInphase(
.clock(clock_sample), .reset(reset), .enable(enable),
.adc(rx0_i),
.rssi(rssi_i0)
);
//RSSI Quadrature Function
rssi RssiQuadrature(
.clock(clock_sample), .reset(reset), .enable(enable),
.adc(rx0_q),
.rssi(rssi_q0)
);
WcaReadWordReg #(`FR_ADC_RSSI) AdcRssiReadRegister
( .reset(reset), .clockIn(clock_sample), .enableIn(1'b1), .in( {rssi_q0, rssi_i0} ),.dmaCtrl(dmaCtrl), .dmaData(dmaData));
//------------------------------------------------------------
// DC Bias Detection.
//------------------------------------------------------------
rx_dcoffset #(`FR_ADC_IBIAS) OffsetInphase(
.clock(clock_sample), .enable(enable), .reset(reset),
.adc_in(rx0_i),
.dmaCtrl(dmaCtrl), .dmaData(dmaData)
);
rx_dcoffset #(`FR_ADC_QBIAS) OffsetQuadrature(
.clock(clock_sample), .enable(enable), .reset(reset),
.adc_in(rx0_q),
.dmaCtrl(dmaCtrl), .dmaData(dmaData)
);
//------------------------------------------------------------
// Tx1 Data Output.
//------------------------------------------------------------
always @(posedge clock_rf_data)
begin
if( rf1_txen)
begin
if( clock_sample )
tx1_data <= #1 tx_i[11:0];
else
tx1_data <= #1 tx_q[11:0];
end
else
tx1_data <= #1 15'd0;
end
endmodule // adc_interface |
module tb_spi_i2s_ipi_clk_div();
localparam TB_PARAM_CNT_WIDTH = 8;
localparam TB_PARAM_STAGE_NUM = 3;
function integer clogb2;
input [31:0] value;
reg div2;
begin
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
value = value >> 1;
end
endfunction
wire clkd_clk_out_o;
wire clkd_time_base_o;
reg [clogb2(TB_PARAM_CNT_WIDTH) - 1 : 0] clkd_clk_div_sel_i;
reg clkd_enable_i;
reg clkd_clk;
reg clkd_rst_n;
integer i;
spi_i2s_ipi_clk_div
#(
.PARAM_CNT_WIDTH ( TB_PARAM_CNT_WIDTH ),
.PARAM_STAGE_WIDTH ( TB_PARAM_STAGE_NUM )
)
CLK_DIV
(
.clkd_clk_out_o ( clkd_clk_out_o ),
.clkd_time_base_o ( clkd_time_base_o ),
.clkd_clk_div_sel_i ( clkd_clk_div_sel_i),
.clkd_enable_i ( clkd_enable_i ),
.clkd_clk ( clkd_clk ),
.clkd_rst_n ( clkd_rst_n )
);
initial
begin
clkd_clk = 0;
clkd_rst_n = 0;
clkd_enable_i = 0;
clkd_clk_div_sel_i = 0;
@(posedge clkd_clk);
@(posedge clkd_clk);
clkd_rst_n = 1;
clkd_enable_i = 1;
for(i = 0; i < 8; i = i + 1)
begin
repeat(10*2**i)
@(posedge clkd_clk);
if(i != 0)
@(posedge clkd_time_base_o);
clkd_enable_i = 0;
clkd_clk_div_sel_i = i + 1;
@(posedge clkd_clk);
clkd_enable_i = 1;
end
$stop;
end
always #10
clkd_clk = !clkd_clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_MUX_2TO1_N_TB_V
`define SKY130_FD_SC_LP__UDP_MUX_2TO1_N_TB_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_mux_2to1_n.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 A0 = 1'b1;
#100 A1 = 1'b1;
#120 S = 1'b1;
#140 A0 = 1'b0;
#160 A1 = 1'b0;
#180 S = 1'b0;
#200 S = 1'b1;
#220 A1 = 1'b1;
#240 A0 = 1'b1;
#260 S = 1'bx;
#280 A1 = 1'bx;
#300 A0 = 1'bx;
end
sky130_fd_sc_lp__udp_mux_2to1_N dut (.A0(A0), .A1(A1), .S(S), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_MUX_2TO1_N_TB_V
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_64x64.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram_64x64 (
byteena_a,
clock,
data,
rdaddress,
wraddress,
wren,
q);
input [7:0] byteena_a;
input clock;
input [63:0] data;
input [5:0] rdaddress;
input [5:0] wraddress;
input wren;
output [63:0] q;
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena_a),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({64{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 64,
altsyncram_component.numwords_b = 64,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 6,
altsyncram_component.widthad_b = 6,
altsyncram_component.width_a = 64,
altsyncram_component.width_b = 64,
altsyncram_component.width_byteena_a = 8;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "8"
// Retrieval info: USED_PORT: byteena_a 0 0 8 0 INPUT VCC byteena_a[7..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL rdaddress[5..0]
// Retrieval info: USED_PORT: wraddress 0 0 6 0 INPUT NODEFVAL wraddress[5..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
// Retrieval info: CONNECT: @address_a 0 0 6 0 wraddress 0 0 6 0
// Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0
// Retrieval info: CONNECT: @byteena_a 0 0 8 0 byteena_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x64.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x64_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x64_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x64_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pad_misc.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module pad_misc(io_tdo_en ,bscan_hiz_l_in ,bscan_update_dr_in ,tdi ,
spare_misc_pad ,spare_misc_pad_to_core ,spare_misc_pindata ,
spare_misc_pin ,burnin ,io_burnin ,spare_misc_paddata ,
spare_misc_padoe ,vreg_selbg_l ,io_pmi ,tck2 ,pad_misc_bsi ,
pad_misc_se ,pad_misc_si ,pad_misc_so ,bscan_clock_dr_in ,ssi_miso
,ssi_mosi ,temp_trig ,jbus_arst_l ,jbus_adbginit_l ,ext_int_l ,
vdd_sense ,jbus_gdbginit_l ,bscan_shift_dr_out ,bscan_update_dr_out
,bscan_clock_dr_out ,bscan_mode_ctl_out ,pmi ,io_ext_int_l ,
pll_char_in ,jbus_grst_l ,jbus_gclk ,vss_sense ,clk_stretch ,
pwron_rst_l ,test_mode ,vddo ,io_trigin ,pmo ,pgrm_en ,io_test_mode
,clk_misc_cken ,hstl_vref ,tms ,pcm_misc_oe ,io_pwron_rst_l ,
io_tms ,io_pmo ,io_pgrm_en ,io_pll_char_in ,io_tdo ,jbi_io_ssi_sck
,jbi_io_ssi_mosi ,io_trst_l ,io_tck ,io_tdi ,io_temp_trig ,
spare_misc_pin_to_core ,io_jbi_ssi_miso ,tck ,tdo ,trst_l ,ssi_sck
,bscan_mode_ctl_in ,bscan_shift_dr_in ,bscan_hiz_l_out ,
pad_misc_bso ,io_tck2 ,spare_misc_pinoe ,io_vreg_selbg_l ,
io_clk_stretch ,trigin );
output [2:0] spare_misc_pad_to_core ;
input [2:0] spare_misc_paddata ;
input [2:0] spare_misc_padoe ;
inout [2:0] spare_misc_pad ;
output io_burnin ;
output io_pmi ;
output pad_misc_so ;
output bscan_shift_dr_out ;
output bscan_update_dr_out ;
output bscan_clock_dr_out ;
output bscan_mode_ctl_out ;
output io_ext_int_l ;
output io_trigin ;
output io_test_mode ;
output io_pwron_rst_l ;
output io_tms ;
output io_pgrm_en ;
output io_pll_char_in ;
output io_trst_l ;
output io_tck ;
output io_tdi ;
output io_temp_trig ;
output spare_misc_pin_to_core ;
output io_jbi_ssi_miso ;
output bscan_hiz_l_out ;
output pad_misc_bso ;
output io_tck2 ;
output io_vreg_selbg_l ;
output io_clk_stretch ;
input io_tdo_en ;
input bscan_hiz_l_in ;
input bscan_update_dr_in ;
input spare_misc_pindata ;
input pad_misc_bsi ;
input pad_misc_se ;
input pad_misc_si ;
input bscan_clock_dr_in ;
input jbus_arst_l ;
input jbus_adbginit_l ;
input jbus_gdbginit_l ;
input jbus_grst_l ;
input jbus_gclk ;
input vddo ;
input clk_misc_cken ;
input pcm_misc_oe ;
input io_pmo ;
input io_tdo ;
input jbi_io_ssi_sck ;
input jbi_io_ssi_mosi ;
input bscan_mode_ctl_in ;
input bscan_shift_dr_in ;
input spare_misc_pinoe ;
inout tdi ;
inout spare_misc_pin ;
inout burnin ;
inout vreg_selbg_l ;
inout tck2 ;
inout ssi_miso ;
inout ssi_mosi ;
inout temp_trig ;
inout ext_int_l ;
inout vdd_sense ;
inout pmi ;
inout pll_char_in ;
inout vss_sense ;
inout clk_stretch ;
inout pwron_rst_l ;
inout test_mode ;
inout pmo ;
inout pgrm_en ;
inout hstl_vref ;
inout tms ;
inout tck ;
inout tdo ;
inout trst_l ;
inout ssi_sck ;
inout trigin ;
supply1 vdd ;
supply0 vss ;
wire net282 ;
wire net300 ;
wire net283 ;
wire net301 ;
wire net284 ;
wire net302 ;
wire net285 ;
wire net286 ;
wire net287 ;
wire net288 ;
wire net305 ;
wire chunk1_so ;
wire chunk5_so ;
wire net296 ;
wire net297 ;
wire net412 ;
wire net298 ;
wire net413 ;
wire net299 ;
wire chunk2_bso ;
wire net0251 ;
wire chunk1_bso ;
wire net0254 ;
wire net324 ;
wire net0257 ;
wire net325 ;
wire net326 ;
wire net327 ;
wire net328 ;
wire net329 ;
wire reset_l ;
wire net330 ;
wire net338 ;
wire net339 ;
wire net340 ;
wire net341 ;
wire net342 ;
wire net343 ;
wire net344 ;
wire net346 ;
wire chunk3_bso ;
wire rclk ;
wire misc_si_1 ;
wire misc_si_2 ;
wire header_si ;
wire chunk2_so ;
wire net273 ;
bw_u1_minbuf_4x I141 (
.z (header_si ),
.a (misc_si_2 ) );
bw_clk_cl_misc_jbus pad_misc_header (
.arst_l (jbus_arst_l ),
.adbginit_l (jbus_adbginit_l ),
.se (pad_misc_se ),
.si (pad_misc_si ),
.cluster_grst_l (reset_l ),
.so (misc_si_1 ),
.dbginit_l (net273 ),
.rclk (rclk ),
.gclk (jbus_gclk ),
.cluster_cken (clk_misc_cken ),
.grst_l (jbus_grst_l ),
.gdbginit_l (jbus_gdbginit_l ) );
bw_u1_ckbuf_1p5x so_ckbuf (
.clk (net0251 ),
.rclk (rclk ) );
bw_u1_scanl_2x lockup_bso (
.so (net0254 ),
.sd (chunk1_bso ),
.ck (net341 ) );
bw_u1_minbuf_1x si_minbuf1 (
.z (misc_si_2 ),
.a (misc_si_1 ) );
bw_io_misc_rpt rpt0 (
.in2 (bscan_mode_ctl_in ),
.out2 (net343 ),
.out3 (net342 ),
.out4 (net341 ),
.out5 (net340 ),
.out6 (net339 ),
.out7 (net338 ),
.in3 (bscan_shift_dr_in ),
.in4 (bscan_clock_dr_in ),
.in5 (bscan_update_dr_in ),
.in6 (reset_l ),
.in7 (pad_misc_se ),
.in1 (bscan_hiz_l_in ),
.out1 (net344 ) );
bw_io_misc_rpt rpt1 (
.in2 (net343 ),
.out2 (net329 ),
.out3 (net328 ),
.out4 (net327 ),
.out5 (net326 ),
.out6 (net325 ),
.out7 (net324 ),
.in3 (net342 ),
.in4 (net341 ),
.in5 (net340 ),
.in6 (net339 ),
.in7 (net338 ),
.in1 (net344 ),
.out1 (net330 ) );
bw_io_misc_rpt rpt2 (
.in2 (net329 ),
.out2 (net287 ),
.out3 (net286 ),
.out4 (net285 ),
.out5 (net284 ),
.out6 (net283 ),
.out7 (net282 ),
.in3 (net328 ),
.in4 (net327 ),
.in5 (net326 ),
.in6 (net325 ),
.in7 (net324 ),
.in1 (net330 ),
.out1 (net288 ) );
bw_io_misc_rpt rpt3 (
.in2 (net287 ),
.out2 (net301 ),
.out3 (net300 ),
.out4 (net299 ),
.out5 (net298 ),
.out6 (net297 ),
.out7 (net296 ),
.in3 (net286 ),
.in4 (net285 ),
.in5 (net284 ),
.in6 (net283 ),
.in7 (net282 ),
.in1 (net288 ),
.out1 (net302 ) );
bw_io_misc_rpt rpt4 (
.in2 (net301 ),
.out2 (bscan_mode_ctl_out ),
.out3 (bscan_shift_dr_out ),
.out4 (bscan_clock_dr_out ),
.out5 (bscan_update_dr_out ),
.out6 (net346 ),
.out7 (net305 ),
.in3 (net300 ),
.in4 (net299 ),
.in5 (net298 ),
.in6 (vss ),
.in7 (vss ),
.in1 (net302 ),
.out1 (bscan_hiz_l_out ) );
bw_u1_buf_20x so_buf (
.z (pad_misc_so ),
.a (net0257 ) );
bw_u1_scanl_2x lockup_so (
.so (net0257 ),
.sd (chunk5_so ),
.ck (net0251 ) );
bw_io_hstl_drv hstl_vref_dummy (
.cbu ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.cbd ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.pad (hstl_vref ),
.sel_data_n (vss ),
.pad_up (vss ),
.pad_dn_l (vdd ),
.por (vss ),
.bsr_up (vss ),
.bsr_dn_l (vdd ),
.vddo (vddo ) );
bw_io_misc_chunk1 chunk1 (
.obsel ({vss ,vss } ),
.io_ext_int_l (io_ext_int_l ),
.spare_misc_pinoe (spare_misc_pinoe ),
.sel_bypass (vss ),
.vss_sense (vss_sense ),
.vdd_sense (vdd_sense ),
.test_mode (test_mode ),
.ext_int_l (ext_int_l ),
.temp_trig (temp_trig ),
.spare_misc_pindata (spare_misc_pindata ),
.ckd (vss ),
.vref (hstl_vref ),
.vddo (vddo ),
.clk_stretch (clk_stretch ),
.hiz_l (net344 ),
.rst_val_dn (vdd ),
.rst_val_up (vdd ),
.reset_l (net339 ),
.mode_ctl (net343 ),
.update_dr (net340 ),
.io_test_mode (io_test_mode ),
.shift_dr (net342 ),
.clock_dr (net341 ),
.io_clk_stretch (io_clk_stretch ),
.por_l (vdd ),
.rst_io_l (vdd ),
.bsi (chunk2_bso ),
.se (net338 ),
.si (header_si ),
.so (chunk1_so ),
.bso (chunk1_bso ),
.clk (rclk ),
.io_pgrm_en (io_pgrm_en ),
.io_burnin (io_burnin ),
.burnin (burnin ),
.pgrm_en (pgrm_en ),
.io_temp_trig (io_temp_trig ),
.pwron_rst_l (pwron_rst_l ),
.io_pwron_rst_l (io_pwron_rst_l ),
.spare_misc_pin (spare_misc_pin ),
.spare_misc_pin_to_core (spare_misc_pin_to_core ) );
bw_io_misc_chunk2 chunk2 (
.obsel ({vss ,vss } ),
.io_pll_char_in (io_pll_char_in ),
.sel_bypass (vss ),
.tck2 (tck2 ),
.io_tck2 (io_tck2 ),
.pll_char_in (pll_char_in ),
.ssi_mosi (ssi_mosi ),
.jbi_io_ssi_mosi (jbi_io_ssi_mosi ),
.ssi_miso (ssi_miso ),
.io_jbi_ssi_miso (io_jbi_ssi_miso ),
.vddo (vddo ),
.vref (hstl_vref ),
.ckd (vss ),
.so (chunk2_so ),
.bso (chunk2_bso ),
.rst_val_up (vdd ),
.rst_val_dn (vdd ),
.reset_l (net325 ),
.si (chunk1_so ),
.se (net324 ),
.bsi (chunk3_bso ),
.rst_io_l (vdd ),
.hiz_l (net330 ),
.shift_dr (net328 ),
.update_dr (net326 ),
.clock_dr (net327 ),
.mode_ctl (net329 ),
.clk (rclk ),
.por_l (vdd ) );
bw_io_misc_chunk3 chunk3 (
.spare_misc_pad ({spare_misc_pad[0] } ),
.spare_misc_paddata ({spare_misc_paddata[0] } ),
.spare_misc_pad_to_core ({spare_misc_pad_to_core[0] } ),
.obsel ({vss ,vss } ),
.spare_misc_padoe ({spare_misc_padoe[0] } ),
.ssi_sck (ssi_sck ),
.jbi_io_ssi_sck (jbi_io_ssi_sck ),
.trigin (trigin ),
.io_trigin (io_trigin ),
.io_tms (io_tms ),
.io_vreg_selbg_l (io_vreg_selbg_l ),
.clk (rclk ),
.ckd (vss ),
.vref (hstl_vref ),
.vddo (vddo ),
.rst_val_up (vdd ),
.tms (tms ),
.sel_bypass (vss ),
.mode_ctl (net287 ),
.rst_val_dn (vdd ),
.bsi (net412 ),
.clock_dr (net285 ),
.shift_dr (net286 ),
.hiz_l (net288 ),
.update_dr (net284 ),
.rst_io_l (vdd ),
.por_l (vdd ),
.se (net282 ),
.si (chunk2_so ),
.reset_l (net283 ),
.so (net413 ),
.bso (chunk3_bso ),
.hstl_vref (hstl_vref ),
.vreg_selbg_l (vreg_selbg_l ) );
bw_u1_buf_30x bso_buf (
.z (pad_misc_bso ),
.a (net0254 ) );
bw_io_misc_chunk5 chunk5 (
.spare_misc_pad ({spare_misc_pad[2:1] } ),
.spare_misc_paddata ({spare_misc_paddata[2:1] } ),
.obsel ({vss ,vss } ),
.spare_misc_padoe ({spare_misc_padoe[2:1] } ),
.spare_misc_pad_to_core ({spare_misc_pad_to_core[2:1] } ),
.clk (rclk ),
.sel_bypass (vss ),
.io_tdo_en (io_tdo_en ),
.ckd (vss ),
.vref (hstl_vref ),
.vddo (vddo ),
.io_tdo (io_tdo ),
.rst_val_up (vdd ),
.io_tdi (io_tdi ),
.mode_ctl (net301 ),
.rst_val_dn (vdd ),
.io_trst_l (io_trst_l ),
.bsi (pad_misc_bsi ),
.io_tck (io_tck ),
.clock_dr (net299 ),
.tck (tck ),
.shift_dr (net300 ),
.trst_l (trst_l ),
.hiz_l (net302 ),
.tdi (tdi ),
.update_dr (net298 ),
.rst_io_l (vdd ),
.por_l (vdd ),
.tdo (tdo ),
.se (net296 ),
.si (net413 ),
.reset_l (net297 ),
.so (chunk5_so ),
.bso (net412 ) );
bw_io_misc_chunk6 chunk6 (
.io_pmi (io_pmi ),
.pcm_misc_oe (pcm_misc_oe ),
.vddo (vddo ),
.pmo (pmo ),
.io_pmo (io_pmo ),
.por_l (vdd ),
.pmi (pmi ) );
endmodule
|
(** * ProofObjects: The Curry-Howard Correspondence *)
Set Warnings "-notation-overridden,-parsing,-deprecated-hint-without-locality".
From LF Require Export IndProp.
(** "Algorithms are the computational content of proofs."
(Robert Harper) *)
(** We have seen that Coq has mechanisms both for _programming_,
using inductive data types like [nat] or [list] and functions over
these types, and for _proving_ properties of these programs, using
inductive propositions (like [ev]), implication, universal
quantification, and the like. So far, we have mostly treated
these mechanisms as if they were quite separate, and for many
purposes this is a good way to think. But we have also seen hints
that Coq's programming and proving facilities are closely related.
For example, the keyword [Inductive] is used to declare both data
types and propositions, and [->] is used both to describe the type
of functions on data and logical implication. This is not just a
syntactic accident! In fact, programs and proofs in Coq are
almost the same thing. In this chapter we will study how this
works.
We have already seen the fundamental idea: provability in Coq is
represented by concrete _evidence_. When we construct the proof
of a basic proposition, we are actually building a tree of
evidence, which can be thought of as a data structure.
If the proposition is an implication like [A -> B], then its proof
will be an evidence _transformer_: a recipe for converting
evidence for A into evidence for B. So at a fundamental level,
proofs are simply programs that manipulate evidence. *)
(** Question: If evidence is data, what are propositions themselves?
Answer: They are types! *)
(** Look again at the formal definition of the [ev] property. *)
Print ev.
(* ==>
Inductive ev : nat -> Prop :=
| ev_0 : ev 0
| ev_SS : forall n, ev n -> ev (S (S n)).
*)
(** Suppose we introduce an alternative pronunciation of "[:]".
Instead of "has type," we can say "is a proof of." For example,
the second line in the definition of [ev] declares that [ev_0 : ev
0]. Instead of "[ev_0] has type [ev 0]," we can say that "[ev_0]
is a proof of [ev 0]." *)
(** This pun between types and propositions -- between [:] as "has type"
and [:] as "is a proof of" or "is evidence for" -- is called the
_Curry-Howard correspondence_. It proposes a deep connection
between the world of logic and the world of computation:
propositions ~ types
proofs ~ data values
See [Wadler 2015] (in Bib.v) for a brief history and up-to-date
exposition. *)
(** Many useful insights follow from this connection. To begin with,
it gives us a natural interpretation of the type of the [ev_SS]
constructor: *)
Check ev_SS
: forall n,
ev n ->
ev (S (S n)).
(** This can be read "[ev_SS] is a constructor that takes two
arguments -- a number [n] and evidence for the proposition [ev
n] -- and yields evidence for the proposition [ev (S (S n))]." *)
(** Now let's look again at a previous proof involving [ev]. *)
Theorem ev_4 : ev 4.
Proof.
apply ev_SS. apply ev_SS. apply ev_0. Qed.
(** As with ordinary data values and functions, we can use the [Print]
command to see the _proof object_ that results from this proof
script. *)
Print ev_4.
(* ===> ev_4 = ev_SS 2 (ev_SS 0 ev_0)
: ev 4 *)
(** Indeed, we can also write down this proof object directly,
without the need for a separate proof script: *)
Check (ev_SS 2 (ev_SS 0 ev_0))
: ev 4.
(** The expression [ev_SS 2 (ev_SS 0 ev_0)] can be thought of as
instantiating the parameterized constructor [ev_SS] with the
specific arguments [2] and [0] plus the corresponding proof
objects for its premises [ev 2] and [ev 0]. Alternatively, we can
think of [ev_SS] as a primitive "evidence constructor" that, when
applied to a particular number, wants to be further applied to
evidence that this number is even; its type,
forall n, ev n -> ev (S (S n)),
expresses this functionality, in the same way that the polymorphic
type [forall X, list X] expresses the fact that the constructor
[nil] can be thought of as a function from types to empty lists
with elements of that type. *)
(** We saw in the [Logic] chapter that we can use function
application syntax to instantiate universally quantified variables
in lemmas, as well as to supply evidence for assumptions that
these lemmas impose. For instance: *)
Theorem ev_4': ev 4.
Proof.
apply (ev_SS 2 (ev_SS 0 ev_0)).
Qed.
(* ################################################################# *)
(** * Proof Scripts *)
(** The _proof objects_ we've been discussing lie at the core of how
Coq operates. When Coq is following a proof script, what is
happening internally is that it is gradually constructing a proof
object -- a term whose type is the proposition being proved. The
tactics between [Proof] and [Qed] tell it how to build up a term
of the required type. To see this process in action, let's use
the [Show Proof] command to display the current state of the proof
tree at various points in the following tactic proof. *)
Theorem ev_4'' : ev 4.
Proof.
Show Proof.
apply ev_SS.
Show Proof.
apply ev_SS.
Show Proof.
apply ev_0.
Show Proof.
Qed.
(** At any given moment, Coq has constructed a term with a
"hole" (indicated by [?Goal] here, and so on), and it knows what
type of evidence is needed to fill this hole.
Each hole corresponds to a subgoal, and the proof is
finished when there are no more subgoals. At this point, the
evidence we've built is stored in the global context under the name
given in the [Theorem] command. *)
(** Tactic proofs are useful and convenient, but they are not
essential: in principle, we can always construct the required
evidence by hand, as shown above. Then we can use [Definition]
(rather than [Theorem]) to give a global name directly to this
evidence. *)
Definition ev_4''' : ev 4 :=
ev_SS 2 (ev_SS 0 ev_0).
(** All these different ways of building the proof lead to exactly the
same evidence being saved in the global environment. *)
Print ev_4.
(* ===> ev_4 = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
Print ev_4'.
(* ===> ev_4' = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
Print ev_4''.
(* ===> ev_4'' = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
Print ev_4'''.
(* ===> ev_4''' = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
(** **** Exercise: 2 stars, standard (eight_is_even)
Give a tactic proof and a proof object showing that [ev 8]. *)
Theorem ev_8 : ev 8.
Proof.
(* FILL IN HERE *) Admitted.
Definition ev_8' : ev 8
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** [] *)
(* ################################################################# *)
(** * Quantifiers, Implications, Functions *)
(** In Coq's computational universe (where data structures and
programs live), there are two sorts of values that have arrows in
their types: _constructors_ introduced by [Inductive]ly defined
data types, and _functions_.
Similarly, in Coq's logical universe (where we carry out proofs),
there are two ways of giving evidence for an implication:
constructors introduced by [Inductive]ly defined propositions,
and... functions! *)
(** For example, consider this statement: *)
Theorem ev_plus4 : forall n, ev n -> ev (4 + n).
Proof.
intros n H. simpl.
apply ev_SS.
apply ev_SS.
apply H.
Qed.
(** What is the proof object corresponding to [ev_plus4]?
We're looking for an expression whose _type_ is [forall n, ev n ->
ev (4 + n)] -- that is, a _function_ that takes two arguments (one
number and a piece of evidence) and returns a piece of evidence!
Here it is: *)
Definition ev_plus4' : forall n, ev n -> ev (4 + n) :=
fun (n : nat) => fun (H : ev n) =>
ev_SS (S (S n)) (ev_SS n H).
(** Recall that [fun n => blah] means "the function that, given [n],
yields [blah]," and that Coq treats [4 + n] and [S (S (S (S n)))]
as synonyms. Another equivalent way to write this definition is: *)
Definition ev_plus4'' (n : nat) (H : ev n)
: ev (4 + n) :=
ev_SS (S (S n)) (ev_SS n H).
Check ev_plus4''
: forall n : nat,
ev n ->
ev (4 + n).
(** When we view the proposition being proved by [ev_plus4] as a
function type, one interesting point becomes apparent: The second
argument's type, [ev n], mentions the _value_ of the first
argument, [n].
While such _dependent types_ are not found in conventional
programming languages, they can be useful in programming too, as
the recent flurry of activity in the functional programming
community demonstrates. *)
(** Notice that both implication ([->]) and quantification ([forall])
correspond to functions on evidence. In fact, they are really the
same thing: [->] is just a shorthand for a degenerate use of
[forall] where there is no dependency, i.e., no need to give a
name to the type on the left-hand side of the arrow:
forall (x:nat), nat
= forall (_:nat), nat
= nat -> nat
*)
(** For example, consider this proposition: *)
Definition ev_plus2 : Prop :=
forall n, forall (E : ev n), ev (n + 2).
(** A proof term inhabiting this proposition would be a function
with two arguments: a number [n] and some evidence [E] that [n] is
even. But the name [E] for this evidence is not used in the rest
of the statement of [ev_plus2], so it's a bit silly to bother
making up a name for it. We could write it like this instead,
using the dummy identifier [_] in place of a real name: *)
Definition ev_plus2' : Prop :=
forall n, forall (_ : ev n), ev (n + 2).
(** Or, equivalently, we can write it in a more familiar way: *)
Definition ev_plus2'' : Prop :=
forall n, ev n -> ev (n + 2).
(** In general, "[P -> Q]" is just syntactic sugar for
"[forall (_:P), Q]". *)
(* ################################################################# *)
(** * Programming with Tactics *)
(** If we can build proofs by giving explicit terms rather than
executing tactic scripts, you may be wondering whether we can
build _programs_ using _tactics_ rather than explicit terms.
Naturally, the answer is yes! *)
Definition add1 : nat -> nat.
intro n.
Show Proof.
apply S.
Show Proof.
apply n. Defined.
Print add1.
(* ==>
add1 = fun n : nat => S n
: nat -> nat
*)
Compute add1 2.
(* ==> 3 : nat *)
(** Notice that we terminate the [Definition] with a [.] rather than
with [:=] followed by a term. This tells Coq to enter _proof
scripting mode_ to build an object of type [nat -> nat]. Also, we
terminate the proof with [Defined] rather than [Qed]; this makes
the definition _transparent_ so that it can be used in computation
like a normally-defined function. ([Qed]-defined objects are
opaque during computation.)
This feature is mainly useful for writing functions with dependent
types, which we won't explore much further in this book. But it
does illustrate the uniformity and orthogonality of the basic
ideas in Coq. *)
(* ################################################################# *)
(** * Logical Connectives as Inductive Types *)
(** Inductive definitions are powerful enough to express most of the
connectives we have seen so far. Indeed, only universal
quantification (with implication as a special case) is built into
Coq; all the others are defined inductively. We'll see these
definitions in this section. *)
Module Props.
(* ================================================================= *)
(** ** Conjunction *)
(** To prove that [P /\ Q] holds, we must present evidence for both
[P] and [Q]. Thus, it makes sense to define a proof object for [P
/\ Q] as consisting of a pair of two proofs: one for [P] and
another one for [Q]. This leads to the following definition. *)
Module And.
Inductive and (P Q : Prop) : Prop :=
| conj : P -> Q -> and P Q.
Arguments conj [P] [Q].
Notation "P /\ Q" := (and P Q) : type_scope.
(** Notice the similarity with the definition of the [prod] type,
given in chapter [Poly]; the only difference is that [prod] takes
[Type] arguments, whereas [and] takes [Prop] arguments. *)
Print prod.
(* ===>
Inductive prod (X Y : Type) : Type :=
| pair : X -> Y -> X * Y. *)
(** This similarity should clarify why [destruct] and [intros]
patterns can be used on a conjunctive hypothesis. Case analysis
allows us to consider all possible ways in which [P /\ Q] was
proved -- here just one (the [conj] constructor). *)
Theorem proj1' : forall P Q,
P /\ Q -> P.
Proof.
intros P Q HPQ. destruct HPQ as [HP HQ]. apply HP.
Show Proof.
Qed.
(** Similarly, the [split] tactic actually works for any inductively
defined proposition with exactly one constructor. In particular,
it works for [and]: *)
Lemma and_comm : forall P Q : Prop, P /\ Q <-> Q /\ P.
Proof.
intros P Q. split.
- intros [HP HQ]. split.
+ apply HQ.
+ apply HP.
- intros [HQ HP]. split.
+ apply HP.
+ apply HQ.
Qed.
End And.
(** This shows why the inductive definition of [and] can be
manipulated by tactics as we've been doing. We can also use it to
build proofs directly, using pattern-matching. For instance: *)
Definition and_comm'_aux P Q (H : P /\ Q) : Q /\ P :=
match H with
| conj HP HQ => conj HQ HP
end.
Definition and_comm' P Q : P /\ Q <-> Q /\ P :=
conj (and_comm'_aux P Q) (and_comm'_aux Q P).
(** **** Exercise: 2 stars, standard (conj_fact)
Construct a proof object for the following proposition. *)
Definition conj_fact : forall P Q R, P /\ Q -> Q /\ R -> P /\ R
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** [] *)
(* ================================================================= *)
(** ** Disjunction *)
(** The inductive definition of disjunction uses two constructors, one
for each side of the disjunct: *)
Module Or.
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
Arguments or_introl [P] [Q].
Arguments or_intror [P] [Q].
Notation "P \/ Q" := (or P Q) : type_scope.
(** This declaration explains the behavior of the [destruct] tactic on
a disjunctive hypothesis, since the generated subgoals match the
shape of the [or_introl] and [or_intror] constructors. *)
(** Once again, we can also directly write proof objects for theorems
involving [or], without resorting to tactics. *)
Definition inj_l : forall (P Q : Prop), P -> P \/ Q :=
fun P Q HP => or_introl HP.
Theorem inj_l' : forall (P Q : Prop), P -> P \/ Q.
Proof.
intros P Q HP. left. apply HP.
Qed.
Definition or_elim : forall (P Q R : Prop), (P \/ Q) -> (P -> R) -> (Q -> R) -> R :=
fun P Q R HPQ HPR HQR =>
match HPQ with
| or_introl HP => HPR HP
| or_intror HQ => HQR HQ
end.
Theorem or_elim' : forall (P Q R : Prop), (P \/ Q) -> (P -> R) -> (Q -> R) -> R.
Proof.
intros P Q R HPQ HPR HQR.
destruct HPQ as [HP | HQ].
- apply HPR. apply HP.
- apply HQR. apply HQ.
Qed.
End Or.
(** **** Exercise: 2 stars, standard (or_commut')
Construct a proof object for the following proposition. *)
Definition or_commut' : forall P Q, P \/ Q -> Q \/ P
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** [] *)
(* ================================================================= *)
(** ** Existential Quantification *)
(** To give evidence for an existential quantifier, we package a
witness [x] together with a proof that [x] satisfies the property
[P]: *)
Module Ex.
Inductive ex {A : Type} (P : A -> Prop) : Prop :=
| ex_intro : forall x : A, P x -> ex P.
Notation "'exists' x , p" :=
(ex (fun x => p))
(at level 200, right associativity) : type_scope.
End Ex.
(** This may benefit from a little unpacking. The core definition is
for a type former [ex] that can be used to build propositions of
the form [ex P], where [P] itself is a _function_ from witness
values in the type [A] to propositions. The [ex_intro]
constructor then offers a way of constructing evidence for [ex P],
given a witness [x] and a proof of [P x].
The notation in the standard library is a slight variant of
the above, enabling syntactic forms such as [exists x y, P x y]. *)
(** The more familiar form [exists x, P x] desugars to an expression
involving [ex]: *)
Check ex (fun n => ev n) : Prop.
(** Here's how to define an explicit proof object involving [ex]: *)
Definition some_nat_is_even : exists n, ev n :=
ex_intro ev 4 (ev_SS 2 (ev_SS 0 ev_0)).
(** **** Exercise: 2 stars, standard (ex_ev_Sn)
Construct a proof object for the following proposition. *)
Definition ex_ev_Sn : ex (fun n => ev (S n))
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** [] *)
(* ================================================================= *)
(** ** [True] and [False] *)
(** The inductive definition of the [True] proposition is simple: *)
Inductive True : Prop :=
| I : True.
(** It has one constructor (so every proof of [True] is the same, so
being given a proof of [True] is not informative.) *)
(** **** Exercise: 1 star, standard (p_implies_true)
Construct a proof object for the following proposition. *)
Definition p_implies_true : forall P, P -> True
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** [] *)
(** [False] is equally simple -- indeed, so simple it may look
syntactically wrong at first glance! *)
Inductive False : Prop := .
(** That is, [False] is an inductive type with _no_ constructors --
i.e., no way to build evidence for it. For example, there is
no way to complete the following definition such that it
succeeds (rather than fails). *)
Fail Definition contra : False :=
0 = 1.
(** But it is possible to destruct [False] by pattern matching. There can
be no patterns that match it, since it has no constructors. So
the pattern match also is so simple it may look syntactically
wrong at first glance. *)
Definition false_implies_zero_eq_one : False -> 0 = 1 :=
fun contra => match contra with end.
(** Since there are no branches to evaluate, the [match] expression
can be considered to have any type we want, including [0 = 1].
Indeed, it's impossible to ever cause the [match] to be evaluated,
because we can never construct a value of type [False] to pass to
the function. *)
(** **** Exercise: 1 star, standard (ex_falso_quodlibet')
Construct a proof object for the following proposition. *)
Definition ex_falso_quodlibet' : forall P, False -> P
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** [] *)
End Props.
(* ################################################################# *)
(** * Equality *)
(** Even Coq's equality relation is not built in. We can define
it ourselves: *)
Module MyEquality.
Inductive eq {X:Type} : X -> X -> Prop :=
| eq_refl : forall x, eq x x.
Notation "x == y" := (eq x y)
(at level 70, no associativity)
: type_scope.
(** The way to think about this definition (which is just a slight
variant of the standard library's) is that, given a set [X], it
defines a _family_ of propositions "[x] is equal to [y]," indexed
by pairs of values ([x] and [y]) from [X]. There is just one way
of constructing evidence for members of this family: applying the
constructor [eq_refl] to a type [X] and a single value [x : X],
which yields evidence that [x] is equal to [x].
Other types of the form [eq x y] where [x] and [y] are not the
same are thus uninhabited. *)
(** We can use [eq_refl] to construct evidence that, for example, [2 =
2]. Can we also use it to construct evidence that [1 + 1 = 2]?
Yes, we can. Indeed, it is the very same piece of evidence!
The reason is that Coq treats as "the same" any two terms that are
_convertible_ according to a simple set of computation rules.
These rules, which are similar to those used by [Compute], include
evaluation of function application, inlining of definitions, and
simplification of [match]es. *)
Lemma four: 2 + 2 == 1 + 3.
Proof.
apply eq_refl.
Qed.
(** The [reflexivity] tactic that we have used to prove
equalities up to now is essentially just shorthand for [apply
eq_refl].
In tactic-based proofs of equality, the conversion rules are
normally hidden in uses of [simpl] (either explicit or implicit in
other tactics such as [reflexivity]).
But you can see them directly at work in the following explicit
proof objects: *)
Definition four' : 2 + 2 == 1 + 3 :=
eq_refl 4.
Definition singleton : forall (X:Type) (x:X), []++[x] == x::[] :=
fun (X:Type) (x:X) => eq_refl [x].
(** **** Exercise: 2 stars, standard (equality__leibniz_equality)
The inductive definition of equality implies _Leibniz equality_:
what we mean when we say "[x] and [y] are equal" is that every
property on [P] that is true of [x] is also true of [y]. *)
Lemma equality__leibniz_equality : forall (X : Type) (x y: X),
x == y -> forall P:X->Prop, P x -> P y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (leibniz_equality__equality)
Show that, in fact, the inductive definition of equality is
_equivalent_ to Leibniz equality. Hint: the proof is quite short;
about all you need to do is to invent a clever property [P] to
instantiate the antecedent.*)
Lemma leibniz_equality__equality : forall (X : Type) (x y: X),
(forall P:X->Prop, P x -> P y) -> x == y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End MyEquality.
(* ================================================================= *)
(** ** Inversion, Again *)
(** We've seen [inversion] used with both equality hypotheses and
hypotheses about inductively defined propositions. Now that we've
seen that these are actually the same thing, we're in a position
to take a closer look at how [inversion] behaves.
In general, the [inversion] tactic...
- takes a hypothesis [H] whose type [P] is inductively defined,
and
- for each constructor [C] in [P]'s definition,
- generates a new subgoal in which we assume [H] was
built with [C],
- adds the arguments (premises) of [C] to the context of
the subgoal as extra hypotheses,
- matches the conclusion (result type) of [C] against the
current goal and calculates a set of equalities that must
hold in order for [C] to be applicable,
- adds these equalities to the context (and, for convenience,
rewrites them in the goal), and
- if the equalities are not satisfiable (e.g., they involve
things like [S n = O]), immediately solves the subgoal. *)
(** _Example_: If we invert a hypothesis built with [or], there are
two constructors, so two subgoals get generated. The
conclusion (result type) of the constructor ([P \/ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal. *)
(** _Example_: If we invert a hypothesis built with [and], there is
only one constructor, so only one subgoal gets generated. Again,
the conclusion (result type) of the constructor ([P /\ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal. The
constructor does have two arguments, though, and these can be seen
in the context in the subgoal. *)
(** _Example_: If we invert a hypothesis built with [eq], there is
again only one constructor, so only one subgoal gets generated.
Now, though, the form of the [eq_refl] constructor does give us
some extra information: it tells us that the two arguments to [eq]
must be the same! The [inversion] tactic adds this fact to the
context. *)
(* ################################################################# *)
(** * The Coq Trusted Computing Base *)
(** One issue that arises with any automated proof assistant is
"why trust it?": what if there is a bug in the implementation that
renders all its reasoning suspect?
While it is impossible to allay such concerns completely, the fact
that Coq is based on the Curry-Howard correspondence gives it a
strong foundation. Because propositions are just types and proofs
are just terms, checking that an alleged proof of a proposition is
valid just amounts to _type-checking_ the term. Type checkers are
relatively small and straightforward programs, so the "trusted
computing base" for Coq -- the part of the code that we have to
believe is operating correctly -- is small too.
What must a typechecker do? Its primary job is to make sure that
in each function application the expected and actual argument
types match, that the arms of a [match] expression are constructor
patterns belonging to the inductive type being matched over and
all arms of the [match] return the same type, and so on. *)
(** There are a few additional wrinkles:
First, since Coq types can themselves be expressions, the checker
must normalize these (by using the computation rules) before
comparing them.
Second, the checker must make sure that [match] expressions are
_exhaustive_. That is, there must be an arm for every possible
constructor. To see why, consider the following alleged proof
object: *)
Fail Definition or_bogus : forall P Q, P \/ Q -> P :=
fun (P Q : Prop) (A : P \/ Q) =>
match A with
| or_introl H => H
end.
(** All the types here match correctly, but the [match] only
considers one of the possible constructors for [or]. Coq's
exhaustiveness check will reject this definition.
Third, the checker must make sure that each recursive function
terminates. It does this using a syntactic check to make sure
that each recursive call is on a subexpression of the original
argument. To see why this is essential, consider this alleged
proof: *)
Fail Fixpoint infinite_loop {X : Type} (n : nat) {struct n} : X :=
infinite_loop n.
Fail Definition falso : False := infinite_loop 0.
(** Recursive function [infinite_loop] purports to return a
value of any type [X] that you would like. (The [struct]
annotation on the function tells Coq that it recurses on argument
[n], not [X].) Were Coq to allow [infinite_loop], then [falso]
would be definable, thus giving evidence for [False]. So Coq rejects
[infinite_loop]. *)
(** Note that the soundness of Coq depends only on the
correctness of this typechecking engine, not on the tactic
machinery. If there is a bug in a tactic implementation (and this
certainly does happen!), that tactic might construct an invalid
proof term. But when you type [Qed], Coq checks the term for
validity from scratch. Only theorems whose proofs pass the
type-checker can be used in further proof developments. *)
(* 2021-08-11 15:08 *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3B_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NOR3B_PP_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3B_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_PP_BLACKBOX_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_PP_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sc_0_1_dbg_rptr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sc_0_1_dbg_rptr(/*AUTOARG*/
// Outputs
l2_dbgbus_out, enable_01, so,
// Inputs
dbgbus_b0, dbgbus_b1, rclk, si, se
);
output [39:0] l2_dbgbus_out ;
output enable_01;
input [40:0] dbgbus_b0;
input [40:0] dbgbus_b1;
input rclk;
input si, se;
output so;
wire [39:0] l2_dbgbus_out_prev ;
wire enable_01_prev;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
// Row0
mux2ds #(20) mux_dbgmuxb01_row0 (.dout (l2_dbgbus_out_prev[19:0]),
.in0(dbgbus_b0[19:0]),
.in1(dbgbus_b1[19:0]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row0 (.q(l2_dbgbus_out[19:0]),
.din(l2_dbgbus_out_prev[19:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
// Row1
mux2ds #(20) mux_dbgmuxb01_row1 (.dout (l2_dbgbus_out_prev[39:20]),
.in0(dbgbus_b0[39:20]),
.in1(dbgbus_b1[39:20]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row1 (.q(l2_dbgbus_out[39:20]),
.din(l2_dbgbus_out_prev[39:20]),
.clk(rclk), .se(1'b0), .si(), .so() );
assign enable_01_prev = dbgbus_b0[40] | dbgbus_b1[40] ;
dff_s #(1) ff_valid (.q(enable_01),
.din(enable_01_prev),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
`include "senior_defines.vh"
`default_nettype none
module alu
#(parameter nat_w = `SENIOR_NATIVE_WIDTH,
parameter ctrl_w = `ALU_CTRL_WIDTH,
parameter mac_flags_w = `MAC_NUM_FLAGS,
parameter alu_flags_w = `ALU_NUM_FLAGS,
parameter spr_dat_w = `SPR_DATA_BUS_WIDTH,
parameter spr_adr_w = `SPR_ADR_BUS_WIDTH
)
(
input wire clk_i,
input wire reset_i,
input wire [ctrl_w-1:0] ctrl_i,
input wire [nat_w-1:0] opa_i,
input wire [nat_w-1:0] opb_i,
input wire condition_check_i,
input wire [mac_flags_w-1:0] mac_flags_i,
output wire [alu_flags_w-1:0] flags_o,
output wire [mac_flags_w-1:0] masked_mac_flags_o,
output reg [nat_w-1:0] result_o,
output reg [nat_w-1:0] result_unr_o,
input wire [spr_dat_w-1:0] spr_dat_i,
input wire [spr_adr_w-1:0] spr_adr_i,
input wire spr_wren_i,
output reg [spr_dat_w-1:0] spr_dat_o
);
`include "std_messages.vh"
// Internal Declarations
reg [1:0] opa_sel_sig;
reg [nat_w-1:0] opa_sig;
reg [nat_w-1:0] opb_sig;
wire [(nat_w-1):0] add_sig;
wire add_carry;
reg max_sig;
reg [nat_w-1:0] mxmn_sig;
reg cin_sig;
reg [nat_w-1:0] add_sat_sig;
reg led_cnt_sig;
reg [nat_w-1:0] led_sig;
reg [nat_w-1:0] logic_sig;
reg [(nat_w-1)+1:0] shift_sig;
reg [(mac_flags_w+alu_flags_w)-1:0] aox_flag_sig;
reg [alu_flags_w-1:0] flags_reg;
reg [alu_flags_w-1:0] flags_sig;
wire mx_minmax;
wire mx_opa_inv;
wire [1:0] mx_ci;
min_max_ctrl min_max_ctrl
(
// Outputs
.mx_minmax_o (mx_minmax),
// Inputs
.function_i (ctrl_i`ALU_FUNCTION),
.opb_sign_i (opb_i[nat_w-1]),
.opa_sign_i (opa_i[nat_w-1]),
.carry_i (add_carry)
);
adder_ctrl adder_ctrl
(
// Outputs
.mx_opa_inv_o (mx_opa_inv),
.mx_ci_o (mx_ci),
// Inputs
.function_i (ctrl_i`ALU_FUNCTION),
.opa_sign_i (opa_i[nat_w-1])
);
assign flags_o = flags_reg;
assign masked_mac_flags_o[`MAC_FLAG_MZ]=aox_flag_sig[4];
assign masked_mac_flags_o[`MAC_FLAG_MN]=aox_flag_sig[5];
assign masked_mac_flags_o[`MAC_FLAG_MS]=aox_flag_sig[6];
assign masked_mac_flags_o[`MAC_FLAG_MV]=aox_flag_sig[7];
// Compute Adder
assign {add_carry,add_sig}=opa_sig+opb_sig+cin_sig;
wire add_pos_overflow;
wire add_neg_overflow;
wire abs_overflow;
assign add_pos_overflow = ~opa_sig[nat_w-1] & ~opb_sig[nat_w-1] & add_sig[nat_w-1];
assign add_neg_overflow = opa_sig[nat_w-1] & opb_sig[nat_w-1] & ~add_sig[nat_w-1];
assign abs_overflow = opa_i[nat_w-1] & add_sig[nat_w-1];
// Mux to select mux signal for Operand A
always @(*) begin
case (ctrl_i`ALU_OPA)
2'b00: opa_sel_sig=2'b00;
2'b01: opa_sel_sig=2'b01;
2'b10: opa_sel_sig={1'b0,opa_i[15]};
2'b11: opa_sel_sig=2'b11;
endcase
end
//Mux to select Operand A
always@* begin
case(mx_opa_inv)
1'b0: opa_sig=opa_i;
1'b1: opa_sig=~(opa_i);
endcase // case(mx_opa_inv)
end
//Mux to select Operand B
always@(*) begin
casex(ctrl_i`ALU_OPB)
2'b00: opb_sig=opb_i;
2'b01: opb_sig=0;
2'b1x: opb_sig=opb_i;
endcase
end
//Mux to select Carry for adder
always@* begin
case(mx_ci)
2'b00: cin_sig = 0;
2'b01: cin_sig = 1;
2'b10: cin_sig = flags_reg[`ALU_FLAG_AC];
default: begin
cin_sig=0;
if(defined_but_illegal(mx_ci,2,"mx_ci")) begin
$stop;
end
end
endcase // case(mx_ci_o)
end
always@* begin
case (mx_minmax)
1'b0: mxmn_sig=opa_i;
1'b1: mxmn_sig=opb_i;
endcase
end
reg sat_carry;
//Check Saturation
always@(*) begin
sat_carry = 0;
casex ({ctrl_i`ALU_ABS_SAT,add_neg_overflow,add_pos_overflow})
3'b000: add_sat_sig=add_sig;
3'b001: begin
add_sat_sig=16'b0111111111111111;
sat_carry = 1;
end
3'b010: begin
add_sat_sig=16'b1000000000000000;
sat_carry = 1;
end
3'b011: begin
add_sat_sig=add_sig;
$display("illagal to be here");
$stop;
end
3'b1xx: begin
add_sat_sig=abs_overflow ? 16'h7fff : add_sig;
end
endcase
end
//Mux to select the Leading bit to be counted
always@(*) begin
case (ctrl_i`ALU_LED)
2'b00: led_cnt_sig=1'b0;
2'b01: led_cnt_sig=1'b1;
2'b10: led_cnt_sig=opa_i[15];
2'b11: led_cnt_sig=flags_reg[`ALU_FLAG_AC];
endcase
end
// compute leading x
always@(*) begin
if(led_cnt_sig) begin
casex(opa_i)
16'b0xxxxxxxxxxxxxxx: led_sig = 16'd0;
16'b1111111111111111: led_sig = 16'd16;
16'b111111111111111x: led_sig = 16'd15;
16'b11111111111111xx: led_sig = 16'd14;
16'b1111111111111xxx: led_sig = 16'd13;
16'b111111111111xxxx: led_sig = 16'd12;
16'b11111111111xxxxx: led_sig = 16'd11;
16'b1111111111xxxxxx: led_sig = 16'd10;
16'b111111111xxxxxxx: led_sig = 16'd9;
16'b11111111xxxxxxxx: led_sig = 16'd8;
16'b1111111xxxxxxxxx: led_sig = 16'd7;
16'b111111xxxxxxxxxx: led_sig = 16'd6;
16'b11111xxxxxxxxxxx: led_sig = 16'd5;
16'b1111xxxxxxxxxxxx: led_sig = 16'd4;
16'b111xxxxxxxxxxxxx: led_sig = 16'd3;
16'b11xxxxxxxxxxxxxx: led_sig = 16'd2;
16'b1xxxxxxxxxxxxxxx: led_sig = 16'd1;
endcase // casex(opa_i)
end
else begin
casex(opa_i)
16'b1xxxxxxxxxxxxxxx: led_sig = 16'd0;
16'b0000000000000000: led_sig = 16'd16;
16'b000000000000000x: led_sig = 16'd15;
16'b00000000000000xx: led_sig = 16'd14;
16'b0000000000000xxx: led_sig = 16'd13;
16'b000000000000xxxx: led_sig = 16'd12;
16'b00000000000xxxxx: led_sig = 16'd11;
16'b0000000000xxxxxx: led_sig = 16'd10;
16'b000000000xxxxxxx: led_sig = 16'd9;
16'b00000000xxxxxxxx: led_sig = 16'd8;
16'b0000000xxxxxxxxx: led_sig = 16'd7;
16'b000000xxxxxxxxxx: led_sig = 16'd6;
16'b00000xxxxxxxxxxx: led_sig = 16'd5;
16'b0000xxxxxxxxxxxx: led_sig = 16'd4;
16'b000xxxxxxxxxxxxx: led_sig = 16'd3;
16'b00xxxxxxxxxxxxxx: led_sig = 16'd2;
16'b0xxxxxxxxxxxxxxx: led_sig = 16'd1;
endcase // casex(opa_i)
end // else: !if(led_cnt_sig)
end // always@ (*)
//Mux and logic to select the logic operation
always@(*) begin
case (ctrl_i`ALU_LOGIC)
2'b00: logic_sig=opa_i & opb_i;
2'b01: logic_sig=opa_i | opb_i;
2'b10: logic_sig=opa_i ^ opb_i;
default: begin
logic_sig=0;
if(defined_but_illegal(ctrl_i`ALU_LOGIC,2,"ctrl_i`ALU_LOGIC")) begin
$stop;
end
end
endcase
end
wire signed [17:0] shift_vector;
reg right_shift_carry;
assign shift_vector = {opa_i[15], opa_i, 1'b0};
// Mux and logic for selecting shift type
always@(*) begin
right_shift_carry = 0;
case (ctrl_i`ALU_SHIFT)
//arithmetic right shift
3'b000: begin
{shift_sig,right_shift_carry} = shift_vector >>> opb_i[4:0];
end
// logical right shift
3'b010: begin
{shift_sig,right_shift_carry} = {1'b0, opa_i, 1'b0} >> opb_i[4:0];
end
3'b001: // arithmetic left shift
begin
shift_sig = {1'b0, opa_i} << opb_i[4:0];
end
3'b011: // logical left shift
begin
shift_sig = {1'b0, opa_i} << opb_i[4:0];
end
3'b100: // right rotation without carry
begin
shift_sig[16] = 0;
case(opb_i[3:0])
0: shift_sig[15:0]=opa_i;
1: shift_sig[15:0]={opa_i[0],opa_i[15:1]};
2: shift_sig[15:0]={opa_i[1:0],opa_i[15:2]};
3: shift_sig[15:0]={opa_i[2:0],opa_i[15:3]};
4: shift_sig[15:0]={opa_i[3:0],opa_i[15:4]};
5: shift_sig[15:0]={opa_i[4:0],opa_i[15:5]};
6: shift_sig[15:0]={opa_i[5:0],opa_i[15:6]};
7: shift_sig[15:0]={opa_i[6:0],opa_i[15:7]};
8: shift_sig[15:0]={opa_i[7:0],opa_i[15:8]};
9: shift_sig[15:0]={opa_i[8:0],opa_i[15:9]};
10: shift_sig[15:0]={opa_i[9:0],opa_i[15:10]};
11: shift_sig[15:0]={opa_i[10:0],opa_i[15:11]};
12: shift_sig[15:0]={opa_i[11:0],opa_i[15:12]};
13: shift_sig[15:0]={opa_i[12:0],opa_i[15:13]};
14: shift_sig[15:0]={opa_i[13:0],opa_i[15:14]};
15: shift_sig[15:0]={opa_i[14:0],opa_i[15]};
endcase
end
// left rotation without carry
3'b101: begin
shift_sig[16] = 0;
case(opb_i[3:0])
0: shift_sig[15:0]=opa_i;
1: shift_sig[15:0]={opa_i[14:0],opa_i[15]};
2: shift_sig[15:0]={opa_i[13:0],opa_i[15:14]};
3: shift_sig[15:0]={opa_i[12:0],opa_i[15:13]};
4: shift_sig[15:0]={opa_i[11:0],opa_i[15:12]};
5: shift_sig[15:0]={opa_i[10:0],opa_i[15:11]};
6: shift_sig[15:0]={opa_i[9:0],opa_i[15:10]};
7: shift_sig[15:0]={opa_i[8:0],opa_i[15:9]};
8: shift_sig[15:0]={opa_i[7:0],opa_i[15:8]};
9: shift_sig[15:0]={opa_i[6:0],opa_i[15:7]};
10: shift_sig[15:0]={opa_i[5:0],opa_i[15:6]};
11: shift_sig[15:0]={opa_i[4:0],opa_i[15:5]};
12: shift_sig[15:0]={opa_i[3:0],opa_i[15:4]};
13: shift_sig[15:0]={opa_i[2:0],opa_i[15:3]};
14: shift_sig[15:0]={opa_i[1:0],opa_i[15:2]};
15: shift_sig[15:0]={opa_i[0],opa_i[15:1]};
endcase
end
//right rotation with carry
3'b110: begin
case(opb_i[4:0])
0: shift_sig={flags_reg[`ALU_FLAG_AC],opa_i};
1: shift_sig={opa_i[0],flags_reg[`ALU_FLAG_AC],opa_i[15:1]};
2: shift_sig={opa_i[1:0],flags_reg[`ALU_FLAG_AC],opa_i[15:2]};
3: shift_sig={opa_i[2:0],flags_reg[`ALU_FLAG_AC],opa_i[15:3]};
4: shift_sig={opa_i[3:0],flags_reg[`ALU_FLAG_AC],opa_i[15:4]};
5: shift_sig={opa_i[4:0],flags_reg[`ALU_FLAG_AC],opa_i[15:5]};
6: shift_sig={opa_i[5:0],flags_reg[`ALU_FLAG_AC],opa_i[15:6]};
7: shift_sig={opa_i[6:0],flags_reg[`ALU_FLAG_AC],opa_i[15:7]};
8: shift_sig={opa_i[7:0],flags_reg[`ALU_FLAG_AC],opa_i[15:8]};
9: shift_sig={opa_i[8:0],flags_reg[`ALU_FLAG_AC],opa_i[15:9]};
10: shift_sig={opa_i[9:0],flags_reg[`ALU_FLAG_AC],opa_i[15:10]};
11: shift_sig={opa_i[10:0],flags_reg[`ALU_FLAG_AC],opa_i[15:11]};
12: shift_sig={opa_i[11:0],flags_reg[`ALU_FLAG_AC],opa_i[15:12]};
13: shift_sig={opa_i[12:0],flags_reg[`ALU_FLAG_AC],opa_i[15:13]};
14: shift_sig={opa_i[13:0],flags_reg[`ALU_FLAG_AC],opa_i[15:14]};
15: shift_sig={opa_i[14:0],flags_reg[`ALU_FLAG_AC],opa_i[15]};
16: shift_sig={opa_i[15:0],flags_reg[`ALU_FLAG_AC]};
default: begin
shift_sig={opa_i[15:0],flags_reg[`ALU_FLAG_AC]};
$display("Warning: undefined value (%h) used for right rotation with carry on opa_i[4:0] in %m", opa_i[4:0]);
end
endcase
end
3'b111: // left rotation with carry
begin
case(opb_i[4:0])
0: shift_sig={flags_reg[`ALU_FLAG_AC],opa_i[15:0]};
1: shift_sig={opa_i[15:0],flags_reg[`ALU_FLAG_AC]};
2: shift_sig={opa_i[14:0],flags_reg[`ALU_FLAG_AC],opa_i[15]};
3: shift_sig={opa_i[13:0],flags_reg[`ALU_FLAG_AC],opa_i[15:14]};
4: shift_sig={opa_i[12:0],flags_reg[`ALU_FLAG_AC],opa_i[15:13]};
5: shift_sig={opa_i[11:0],flags_reg[`ALU_FLAG_AC],opa_i[15:12]};
6: shift_sig={opa_i[10:0],flags_reg[`ALU_FLAG_AC],opa_i[15:11]};
7: shift_sig={opa_i[9:0],flags_reg[`ALU_FLAG_AC],opa_i[15:10]};
8: shift_sig={opa_i[8:0],flags_reg[`ALU_FLAG_AC],opa_i[15:9]};
9: shift_sig={opa_i[7:0],flags_reg[`ALU_FLAG_AC],opa_i[15:8]};
10: shift_sig={opa_i[6:0],flags_reg[`ALU_FLAG_AC],opa_i[15:7]};
11: shift_sig={opa_i[5:0],flags_reg[`ALU_FLAG_AC],opa_i[15:6]};
12: shift_sig={opa_i[4:0],flags_reg[`ALU_FLAG_AC],opa_i[15:5]};
13: shift_sig={opa_i[3:0],flags_reg[`ALU_FLAG_AC],opa_i[15:4]};
14: shift_sig={opa_i[2:0],flags_reg[`ALU_FLAG_AC],opa_i[15:3]};
15: shift_sig={opa_i[1:0],flags_reg[`ALU_FLAG_AC],opa_i[15:2]};
16: shift_sig={opa_i[0],flags_reg[`ALU_FLAG_AC],opa_i[15:1]};
default: begin
shift_sig=0;
$display("Warning: undefined value (%h) used for left rotation with carry on opa_i[4:0] in %m", opa_i[4:0]);
end
endcase
end
endcase
end
reg [nat_w-1:0] result;
// Mux for selecting the output operation
always@* begin
case (ctrl_i`ALU_OUT)
3'b000: result=led_sig;
3'b001: result=shift_sig[15:0];
3'b010: result=logic_sig;
3'b011: result=mxmn_sig;
3'b100: result=add_sig;
3'b101: result=add_sat_sig;
3'b110: result={8'b0, //Reserved
aox_flag_sig[7], //MV
aox_flag_sig[6], //MS
aox_flag_sig[5], //MN
aox_flag_sig[4], //MZ
flags_reg[`ALU_FLAG_AV],
flags_reg[`ALU_FLAG_AC],
flags_reg[`ALU_FLAG_AN],
flags_reg[`ALU_FLAG_AZ]};
default: begin
result=add_sat_sig;
if(defined_but_illegal(ctrl_i`ALU_OUT,3,"ctrl_i`ALU_OUT")) begin
$stop;
end
end
endcase
end
always @(*) begin
result_unr_o = result;
end
always@(posedge clk_i) begin
result_o <= result;
end
// and or xor flags
always@(*) begin
case (ctrl_i`ALU_AOX)
2'b00:
begin
aox_flag_sig[0] = flags_reg[`ALU_FLAG_AZ] & opa_i[0];
aox_flag_sig[1] = flags_reg[`ALU_FLAG_AN] & opa_i[1];
aox_flag_sig[2] = flags_reg[`ALU_FLAG_AC] & opa_i[2];
aox_flag_sig[3] = flags_reg[`ALU_FLAG_AV] & opa_i[3];
aox_flag_sig[4] = mac_flags_i[`MAC_FLAG_MZ] & opa_i[4];
aox_flag_sig[5] = mac_flags_i[`MAC_FLAG_MN] & opa_i[5];
aox_flag_sig[6] = mac_flags_i[`MAC_FLAG_MS] & opa_i[6];
aox_flag_sig[7] = mac_flags_i[`MAC_FLAG_MV] & opa_i[7];
end
2'b10:
begin
aox_flag_sig[0] = flags_reg[`ALU_FLAG_AZ] ^ opa_i[0];
aox_flag_sig[1] = flags_reg[`ALU_FLAG_AN] ^ opa_i[1];
aox_flag_sig[2] = flags_reg[`ALU_FLAG_AC] ^ opa_i[2];
aox_flag_sig[3] = flags_reg[`ALU_FLAG_AV] ^ opa_i[3];
aox_flag_sig[4] = mac_flags_i[`MAC_FLAG_MZ] ^ opa_i[4];
aox_flag_sig[5] = mac_flags_i[`MAC_FLAG_MN] ^ opa_i[5];
aox_flag_sig[6] = mac_flags_i[`MAC_FLAG_MS] ^ opa_i[6];
aox_flag_sig[7] = mac_flags_i[`MAC_FLAG_MV] ^ opa_i[7];
end
2'b01:
begin
aox_flag_sig[0] = flags_reg[`ALU_FLAG_AZ] | opa_i[0];
aox_flag_sig[1] = flags_reg[`ALU_FLAG_AN] | opa_i[1];
aox_flag_sig[2] = flags_reg[`ALU_FLAG_AC] | opa_i[2];
aox_flag_sig[3] = flags_reg[`ALU_FLAG_AV] | opa_i[3];
aox_flag_sig[4] = mac_flags_i[`MAC_FLAG_MZ] | opa_i[4];
aox_flag_sig[5] = mac_flags_i[`MAC_FLAG_MN] | opa_i[5];
aox_flag_sig[6] = mac_flags_i[`MAC_FLAG_MS] | opa_i[6];
aox_flag_sig[7] = mac_flags_i[`MAC_FLAG_MV] | opa_i[7];
end
default: begin
aox_flag_sig = 0;
if(defined_but_illegal(ctrl_i`ALU_AOX,2,"ctrl_i`ALU_AOX")) begin
$stop;
end
end
endcase
end
// zero flag
always@(*) begin
case (ctrl_i`ALU_AZ)
2'b01: flags_sig[`ALU_FLAG_AZ]=~(|result);
2'b10: flags_sig[`ALU_FLAG_AZ]=aox_flag_sig[0];
default: flags_sig[`ALU_FLAG_AZ]=flags_reg[`ALU_FLAG_AZ];
endcase
end
// negative flag
always@(*) begin
case (ctrl_i`ALU_AN)
2'b01: flags_sig[`ALU_FLAG_AN]=result[15];
2'b10: flags_sig[`ALU_FLAG_AN]=aox_flag_sig[1];
default: flags_sig[`ALU_FLAG_AN]=flags_reg[`ALU_FLAG_AN];
endcase
end
// saturate/carry flag
always@(*) begin
case (ctrl_i`ALU_AC)
3'b000: flags_sig[`ALU_FLAG_AC]=flags_reg[`ALU_FLAG_AC];
3'b001: begin
flags_sig[`ALU_FLAG_AC]=opa_i[15];
$stop;
end
3'b010: begin
case(ctrl_i`ALU_SHIFT)
3'b000: flags_sig[`ALU_FLAG_AC]=right_shift_carry;
3'b001: flags_sig[`ALU_FLAG_AC]=shift_sig[16];
3'b010: flags_sig[`ALU_FLAG_AC]=right_shift_carry;
3'b011: flags_sig[`ALU_FLAG_AC]=shift_sig[16];
3'b100: flags_sig[`ALU_FLAG_AC]=shift_sig[15];
3'b101: flags_sig[`ALU_FLAG_AC]=shift_sig[0];
3'b110: flags_sig[`ALU_FLAG_AC]=shift_sig[16];
3'b111: flags_sig[`ALU_FLAG_AC]=shift_sig[16];
endcase // casex(ctrl_i`ALU_shift)
end
3'b011: flags_sig[`ALU_FLAG_AC]=add_carry;
3'b100: flags_sig[`ALU_FLAG_AC]=aox_flag_sig[2];
3'b101: flags_sig[`ALU_FLAG_AC]=add_carry;
3'b110: flags_sig[`ALU_FLAG_AC]=sat_carry;
3'b111: flags_sig[`ALU_FLAG_AC]=0;
endcase
end
//overflow flag
always@(*) begin
case (ctrl_i`ALU_AV)
2'b00: flags_sig[`ALU_FLAG_AV]=flags_reg[`ALU_FLAG_AV];
2'b01: flags_sig[`ALU_FLAG_AV]=add_pos_overflow | add_neg_overflow ;
2'b10: flags_sig[`ALU_FLAG_AV]=aox_flag_sig[3];
2'b11: flags_sig[`ALU_FLAG_AV]=0;
default: begin
flags_sig[`ALU_FLAG_AV]=flags_reg[`ALU_FLAG_AV];
if(defined_but_illegal(ctrl_i`ALU_AV,2,"ctrl_i`ALU_AV")) begin
$stop;
end
end
endcase
end
reg spr_write_flags;
reg [spr_dat_w-1:`MAC_NUM_FLAGS+`ALU_NUM_FLAGS] spr_fl0_extra_store;
always@* begin
spr_dat_o = 0;
case(spr_adr_i)
(`SPR_CP_GROUP+`SPR_STATUS_FLAGS): begin
spr_write_flags = spr_wren_i;
spr_dat_o = {spr_fl0_extra_store,`MAC_NUM_FLAGS'b0,flags_reg};
end
default: spr_write_flags = 0;
endcase // case(spr_adr_i)
end
// register flags
always @(posedge clk_i) begin
if (!reset_i) begin
flags_reg<=0;
spr_fl0_extra_store <= 0;
end
else begin
if (spr_write_flags) begin
spr_fl0_extra_store <= spr_dat_i[spr_dat_w-1:`MAC_NUM_FLAGS+`ALU_NUM_FLAGS];
flags_reg <= spr_dat_i[3:0];
end
else if (condition_check_i) begin
flags_reg<=flags_sig;
end
end // else: !if(!reset_i)
end // always @ (posedge clk_i)
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR3_SYMBOL_V
`define SKY130_FD_SC_HDLL__XNOR3_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__xnor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR3_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SDFRTP_BLACKBOX_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:52:04 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_ov7670_controller_1_0 -prefix
// system_ov7670_controller_1_0_ system_ov7670_controller_0_0_stub.v
// Design : system_ov7670_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_controller,Vivado 2016.4" *)
module system_ov7670_controller_1_0(clk, resend, config_finished, sioc, siod, reset,
pwdn, xclk)
/* synthesis syn_black_box black_box_pad_pin="clk,resend,config_finished,sioc,siod,reset,pwdn,xclk" */;
input clk;
input resend;
output config_finished;
output sioc;
inout siod;
output reset;
output pwdn;
output xclk;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: flop_rptrs_xc5.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module flop_rptrs_xc5(/*AUTOARG*/
// Outputs
sparc_out, so, jbussync2_out, jbussync1_out, grst_out,
gdbginit_out, ddrsync2_out, ddrsync1_out, cken_out,
// Inputs
spare_in, se, sd, jbussync2_in, jbussync1_in, grst_in,
gdbginit_in, gclk, ddrsync2_in, ddrsync1_in, cken_in, agrst_l,
adbginit_l
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [25:0] cken_out; // From cken_ff_25_ of bw_u1_soffasr_2x.v, ...
output ddrsync1_out; // From ddrsync1_ff of bw_u1_soffasr_2x.v
output ddrsync2_out; // From ddrsync2_ff of bw_u1_soffasr_2x.v
output gdbginit_out; // From gdbginit_ff of bw_u1_soffasr_2x.v
output grst_out; // From gclk_ff of bw_u1_soffasr_2x.v
output jbussync1_out; // From jbussync1_ff of bw_u1_soffasr_2x.v
output jbussync2_out; // From jbussync2_ff of bw_u1_soffasr_2x.v
output so; // From scanout_latch of bw_u1_scanlg_2x.v
output [5:0] sparc_out; // From spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To gdbginit_ff of bw_u1_soffasr_2x.v
input agrst_l; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [25:0] cken_in; // To cken_ff_25_ of bw_u1_soffasr_2x.v, ...
input ddrsync1_in; // To ddrsync1_ff of bw_u1_soffasr_2x.v
input ddrsync2_in; // To ddrsync2_ff of bw_u1_soffasr_2x.v
input gclk; // To I73 of bw_u1_ckbuf_33x.v
input gdbginit_in; // To gdbginit_ff of bw_u1_soffasr_2x.v
input grst_in; // To gclk_ff of bw_u1_soffasr_2x.v
input jbussync1_in; // To jbussync1_ff of bw_u1_soffasr_2x.v
input jbussync2_in; // To jbussync2_ff of bw_u1_soffasr_2x.v
input sd; // To spare_ff_5_ of bw_u1_soffasr_2x.v
input se; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [5:0] spare_in; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire clk; // From I73 of bw_u1_ckbuf_33x.v
wire scan_data_0; // From spare_ff_5_ of bw_u1_soffasr_2x.v
wire scan_data_1; // From spare_ff_4_ of bw_u1_soffasr_2x.v
wire scan_data_10; // From gdbginit_ff of bw_u1_soffasr_2x.v
wire scan_data_11; // From gclk_ff of bw_u1_soffasr_2x.v
wire scan_data_2; // From spare_ff_3_ of bw_u1_soffasr_2x.v
wire scan_data_3; // From spare_ff_2_ of bw_u1_soffasr_2x.v
wire scan_data_4; // From spare_ff_1_ of bw_u1_soffasr_2x.v
wire scan_data_5; // From spare_ff_0_ of bw_u1_soffasr_2x.v
wire scan_data_6; // From jbussync2_ff of bw_u1_soffasr_2x.v
wire scan_data_7; // From jbussync1_ff of bw_u1_soffasr_2x.v
wire scan_data_8; // From ddrsync2_ff of bw_u1_soffasr_2x.v
wire scan_data_9; // From ddrsync1_ff of bw_u1_soffasr_2x.v
// End of automatics
/* bw_u1_ckbuf_33x AUTO_TEMPLATE (
.clk (clk ),
.rclk (gclk ) ); */
bw_u1_ckbuf_33x I73
(/*AUTOINST*/
// Outputs
.clk (clk ), // Templated
// Inputs
.rclk (gclk )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (sparc_out[@]),
.d (spare_in[@]),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.sd (scan_data_@"(- 4 @)" ),
.so (scan_data_@"(- 5 @)" ),
); */
bw_u1_soffasr_2x spare_ff_5_
(
// Inputs
.sd (sd ),
/*AUTOINST*/
// Outputs
.q (sparc_out[5]), // Templated
.so (scan_data_0 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[5]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se));
bw_u1_soffasr_2x spare_ff_4_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[4]), // Templated
.so (scan_data_1 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[4]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_0 )); // Templated
bw_u1_soffasr_2x spare_ff_3_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[3]), // Templated
.so (scan_data_2 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[3]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_1 )); // Templated
bw_u1_soffasr_2x spare_ff_2_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[2]), // Templated
.so (scan_data_3 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[2]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_2 )); // Templated
bw_u1_soffasr_2x spare_ff_1_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[1]), // Templated
.so (scan_data_4 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[1]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_3 )); // Templated
bw_u1_soffasr_2x spare_ff_0_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[0]), // Templated
.so (scan_data_5 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[0]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_4 )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (cken_out[@] ),
.d (cken_in[@] ),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (1'b0),
.sd (1'b0),
.so (),
); */
bw_u1_soffasr_2x cken_ff_25_
( /*AUTOINST*/
// Outputs
.q (cken_out[25] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[25] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_24_
( /*AUTOINST*/
// Outputs
.q (cken_out[24] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[24] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_23_
( /*AUTOINST*/
// Outputs
.q (cken_out[23] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[23] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_22_
( /*AUTOINST*/
// Outputs
.q (cken_out[22] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[22] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_21_
( /*AUTOINST*/
// Outputs
.q (cken_out[21] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[21] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_20_
( /*AUTOINST*/
// Outputs
.q (cken_out[20] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[20] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_19_
( /*AUTOINST*/
// Outputs
.q (cken_out[19] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[19] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_18_
( /*AUTOINST*/
// Outputs
.q (cken_out[18] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[18] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_17_
( /*AUTOINST*/
// Outputs
.q (cken_out[17] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[17] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_16_
( /*AUTOINST*/
// Outputs
.q (cken_out[16] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[16] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_15_
( /*AUTOINST*/
// Outputs
.q (cken_out[15] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[15] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_14_
( /*AUTOINST*/
// Outputs
.q (cken_out[14] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[14] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_13_
( /*AUTOINST*/
// Outputs
.q (cken_out[13] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[13] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_12_
( /*AUTOINST*/
// Outputs
.q (cken_out[12] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[12] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_11_
( /*AUTOINST*/
// Outputs
.q (cken_out[11] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[11] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_10_
( /*AUTOINST*/
// Outputs
.q (cken_out[10] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[10] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_9_
( /*AUTOINST*/
// Outputs
.q (cken_out[9] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[9] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_8_
( /*AUTOINST*/
// Outputs
.q (cken_out[8] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[8] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_7_
( /*AUTOINST*/
// Outputs
.q (cken_out[7] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[7] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_6_
( /*AUTOINST*/
// Outputs
.q (cken_out[6] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[6] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_5_
( /*AUTOINST*/
// Outputs
.q (cken_out[5] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[5] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_4_
( /*AUTOINST*/
// Outputs
.q (cken_out[4] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[4] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_3_
( /*AUTOINST*/
// Outputs
.q (cken_out[3] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[3] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_2_
( /*AUTOINST*/
// Outputs
.q (cken_out[2] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[2] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_1_
( /*AUTOINST*/
// Outputs
.q (cken_out[1] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[1] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_0_
( /*AUTOINST*/
// Outputs
.q (cken_out[0] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[0] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (se ),
); */
bw_u1_soffasr_2x ddrsync1_ff
(
// Outputs
.q (ddrsync1_out ),
.so (scan_data_9 ),
// Inputs
.d (ddrsync1_in ),
.sd (scan_data_8 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x ddrsync2_ff
(
// Outputs
.q (ddrsync2_out ),
.so (scan_data_8 ),
// Inputs
.d (ddrsync2_in ),
.sd (scan_data_7 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync1_ff
(
// Outputs
.q (jbussync1_out ),
.so (scan_data_7 ),
// Inputs
.d (jbussync1_in ),
.sd (scan_data_6 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync2_ff
(
// Outputs
.q (jbussync2_out ),
.so (scan_data_6 ),
// Inputs
.d (jbussync2_in ),
.sd (scan_data_5 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gdbginit_ff
(
// Outputs
.q (gdbginit_out ),
.so (scan_data_10 ),
// Inputs
.d (gdbginit_in ),
.sd (scan_data_9 ),
.r_l (adbginit_l),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gclk_ff
(
// Outputs
.q (grst_out ),
.so (scan_data_11 ),
// Inputs
.d (grst_in ),
.sd (scan_data_10 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
/* bw_u1_scanlg_2x AUTO_TEMPLATE (
.sd (scan_data_11 ),
.ck (clk ),
); */
bw_u1_scanlg_2x scanout_latch
( /*AUTOINST*/
// Outputs
.so (so),
// Inputs
.sd (scan_data_11 ), // Templated
.ck (clk ), // Templated
.se (1'b1));
endmodule
// Local Variables:
// verilog-library-files:("../../../common/rtl/u1.behV" )
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2OI_BLACKBOX_V
`define SKY130_FD_SC_MS__A2BB2OI_BLACKBOX_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2OI_BLACKBOX_V
|
//File Name: lab6phase2I2C.v
//Author: Jianjian Song
//Date: October 27, 2015
//ECE333 Fall 2015
//ChipSelect is the lower 3-bit address of TM101
//Read one of TMP101 temperature sensor
//send first byte to I2C bus with slave address
//Receive first byte from I2C bus as temperature
//Display the 8-bit temperatue in Celsius on LEDs LD7-0
//Display 2-digit temperature in Fahrenheit and 2-digit in Celsius
//on 4-digit 7-segment display
module lab6phase2I2C(ChipSelect,Start,Mode,ReceivedData,SCL,SDA,Reset,SystemClock,ClockLocked,DONE,Display,Transistors);
input Reset, Mode, SystemClock, Start;
input [2:0] ChipSelect;
output SCL, ClockLocked, DONE;
inout SDA;
output [7:0] ReceivedData;
output [3:0] Transistors;
output [7:0] Display;
parameter BaudRate=20'd40000, ClockFrequency=30'd65000000;
wire clock;
//simulation parameter
//parameter BaudRate=2, ClockFrequency=12;
Clock65MHz SystemClockUnit(SystemClock,clock,ClockLocked);
ClockedPositiveOneShot StartOneShot(Start, StartReading, Reset, clock) ;
wire [7:0] Chip;
wire WriteLoad, ReadorWrite, ShiftorHold, Select, BaudEnable, StartStopAck;
//module ReadTempI2C2015fall(Start, Address, ReceivedData, Done, SCL, SDA,
//BaudRate, ClockFrequency, Reset, clock);
assign Chip = {4'b1001,ChipSelect,1'b1};
ReadTempI2C2015fall ReadUnit(StartReading||Mode, 8'b10010011, ReceivedData, DONE, SCL, SDA,
BaudRate, ClockFrequency, Reset, clock);
wire [3:0] First1, First0, Second1, Second0;
wire [7:0] F1code,F0code,S1code,S0code;
reg [7:0] Temperature;
always@(posedge clock)
if(DONE==1) Temperature<=ReceivedData;
else Temperature<=Temperature;
OneTemperatureConverter ConvertUnit(Temperature, First1, First0, Second1, Second0);
BCDto7Segment F1Unit(First1,F1code);
BCDto7Segment F0Unit(First0,F0code);
BCDto7Segment C1Unit(Second1, S1code);
BCDto7Segment C0Unit(Second0,S0code);
//7-segment display
//module SevenSegDriver(D3, D2, D1, D0, Display, Reset, Clock, Select);
SevenSegDriver DisplayUnit(F1code,F0code,S1code,S0code,Display,Reset,clock,Transistors);
endmodule |
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module mult_16x16 (
input wire [15:0] A,
input wire [15:0] B,
output wire [31:0] Z
);
assign Z = A * B;
endmodule
module mult_20x18 (
input wire [19:0] A,
input wire [17:0] B,
output wire [37:0] Z
);
assign Z = A * B;
endmodule
module mult_8x8 (
input wire [ 7:0] A,
input wire [ 7:0] B,
output wire [15:0] Z
);
assign Z = A * B;
endmodule
module mult_10x9 (
input wire [ 9:0] A,
input wire [ 8:0] B,
output wire [18:0] Z
);
assign Z = A * B;
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench (
// inputs:
A_cmp_result,
A_ctrl_ld_non_bypass,
A_en,
A_exc_active_no_break_no_crst,
A_exc_allowed,
A_exc_any_active,
A_exc_hbreak_pri1,
A_exc_highest_pri_exc_id,
A_exc_inst_fetch,
A_exc_norm_intr_pri5,
A_st_data,
A_valid,
A_wr_data_unfiltered,
A_wr_dst_reg,
E_add_br_to_taken_history_unfiltered,
M_bht_ptr_unfiltered,
M_bht_wr_data_unfiltered,
M_bht_wr_en_unfiltered,
M_mem_baddr,
M_target_pcb,
M_valid,
W_badaddr_reg,
W_bstatus_reg,
W_dst_regnum,
W_dst_regset,
W_estatus_reg,
W_exception_reg,
W_iw,
W_iw_op,
W_iw_opx,
W_pcb,
W_status_reg,
W_valid,
W_vinst,
W_wr_dst_reg,
clk,
d_address,
d_byteenable,
d_read,
d_readdatavalid,
d_write,
i_address,
i_read,
i_readdatavalid,
reset_n,
// outputs:
A_wr_data_filtered,
E_add_br_to_taken_history_filtered,
M_bht_ptr_filtered,
M_bht_wr_data_filtered,
M_bht_wr_en_filtered,
test_has_ended
)
;
output [ 31: 0] A_wr_data_filtered;
output E_add_br_to_taken_history_filtered;
output [ 7: 0] M_bht_ptr_filtered;
output [ 1: 0] M_bht_wr_data_filtered;
output M_bht_wr_en_filtered;
output test_has_ended;
input A_cmp_result;
input A_ctrl_ld_non_bypass;
input A_en;
input A_exc_active_no_break_no_crst;
input A_exc_allowed;
input A_exc_any_active;
input A_exc_hbreak_pri1;
input [ 31: 0] A_exc_highest_pri_exc_id;
input A_exc_inst_fetch;
input A_exc_norm_intr_pri5;
input [ 31: 0] A_st_data;
input A_valid;
input [ 31: 0] A_wr_data_unfiltered;
input A_wr_dst_reg;
input E_add_br_to_taken_history_unfiltered;
input [ 7: 0] M_bht_ptr_unfiltered;
input [ 1: 0] M_bht_wr_data_unfiltered;
input M_bht_wr_en_unfiltered;
input [ 24: 0] M_mem_baddr;
input [ 24: 0] M_target_pcb;
input M_valid;
input [ 31: 0] W_badaddr_reg;
input [ 31: 0] W_bstatus_reg;
input [ 4: 0] W_dst_regnum;
input [ 5: 0] W_dst_regset;
input [ 31: 0] W_estatus_reg;
input [ 31: 0] W_exception_reg;
input [ 31: 0] W_iw;
input [ 5: 0] W_iw_op;
input [ 5: 0] W_iw_opx;
input [ 24: 0] W_pcb;
input [ 31: 0] W_status_reg;
input W_valid;
input [ 71: 0] W_vinst;
input W_wr_dst_reg;
input clk;
input [ 24: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_readdatavalid;
input d_write;
input [ 24: 0] i_address;
input i_read;
input i_readdatavalid;
input reset_n;
wire A_iw_invalid;
reg [ 24: 0] A_mem_baddr;
reg [ 24: 0] A_target_pcb;
wire [ 31: 0] A_wr_data_filtered;
wire A_wr_data_unfiltered_0_is_x;
wire A_wr_data_unfiltered_10_is_x;
wire A_wr_data_unfiltered_11_is_x;
wire A_wr_data_unfiltered_12_is_x;
wire A_wr_data_unfiltered_13_is_x;
wire A_wr_data_unfiltered_14_is_x;
wire A_wr_data_unfiltered_15_is_x;
wire A_wr_data_unfiltered_16_is_x;
wire A_wr_data_unfiltered_17_is_x;
wire A_wr_data_unfiltered_18_is_x;
wire A_wr_data_unfiltered_19_is_x;
wire A_wr_data_unfiltered_1_is_x;
wire A_wr_data_unfiltered_20_is_x;
wire A_wr_data_unfiltered_21_is_x;
wire A_wr_data_unfiltered_22_is_x;
wire A_wr_data_unfiltered_23_is_x;
wire A_wr_data_unfiltered_24_is_x;
wire A_wr_data_unfiltered_25_is_x;
wire A_wr_data_unfiltered_26_is_x;
wire A_wr_data_unfiltered_27_is_x;
wire A_wr_data_unfiltered_28_is_x;
wire A_wr_data_unfiltered_29_is_x;
wire A_wr_data_unfiltered_2_is_x;
wire A_wr_data_unfiltered_30_is_x;
wire A_wr_data_unfiltered_31_is_x;
wire A_wr_data_unfiltered_3_is_x;
wire A_wr_data_unfiltered_4_is_x;
wire A_wr_data_unfiltered_5_is_x;
wire A_wr_data_unfiltered_6_is_x;
wire A_wr_data_unfiltered_7_is_x;
wire A_wr_data_unfiltered_8_is_x;
wire A_wr_data_unfiltered_9_is_x;
wire E_add_br_to_taken_history_filtered;
wire E_add_br_to_taken_history_unfiltered_is_x;
wire [ 7: 0] M_bht_ptr_filtered;
wire M_bht_ptr_unfiltered_0_is_x;
wire M_bht_ptr_unfiltered_1_is_x;
wire M_bht_ptr_unfiltered_2_is_x;
wire M_bht_ptr_unfiltered_3_is_x;
wire M_bht_ptr_unfiltered_4_is_x;
wire M_bht_ptr_unfiltered_5_is_x;
wire M_bht_ptr_unfiltered_6_is_x;
wire M_bht_ptr_unfiltered_7_is_x;
wire [ 1: 0] M_bht_wr_data_filtered;
wire M_bht_wr_data_unfiltered_0_is_x;
wire M_bht_wr_data_unfiltered_1_is_x;
wire M_bht_wr_en_filtered;
wire M_bht_wr_en_unfiltered_is_x;
reg W_cmp_result;
reg W_exc_any_active;
reg [ 31: 0] W_exc_highest_pri_exc_id;
wire W_is_opx_inst;
reg W_iw_invalid;
wire W_op_add;
wire W_op_addi;
wire W_op_and;
wire W_op_andhi;
wire W_op_andi;
wire W_op_beq;
wire W_op_bge;
wire W_op_bgeu;
wire W_op_blt;
wire W_op_bltu;
wire W_op_bne;
wire W_op_br;
wire W_op_break;
wire W_op_bret;
wire W_op_call;
wire W_op_callr;
wire W_op_cmpeq;
wire W_op_cmpeqi;
wire W_op_cmpge;
wire W_op_cmpgei;
wire W_op_cmpgeu;
wire W_op_cmpgeui;
wire W_op_cmplt;
wire W_op_cmplti;
wire W_op_cmpltu;
wire W_op_cmpltui;
wire W_op_cmpne;
wire W_op_cmpnei;
wire W_op_crst;
wire W_op_custom;
wire W_op_div;
wire W_op_divu;
wire W_op_eret;
wire W_op_flushd;
wire W_op_flushda;
wire W_op_flushi;
wire W_op_flushp;
wire W_op_hbreak;
wire W_op_initd;
wire W_op_initda;
wire W_op_initi;
wire W_op_intr;
wire W_op_jmp;
wire W_op_jmpi;
wire W_op_ldb;
wire W_op_ldbio;
wire W_op_ldbu;
wire W_op_ldbuio;
wire W_op_ldh;
wire W_op_ldhio;
wire W_op_ldhu;
wire W_op_ldhuio;
wire W_op_ldl;
wire W_op_ldw;
wire W_op_ldwio;
wire W_op_mul;
wire W_op_muli;
wire W_op_mulxss;
wire W_op_mulxsu;
wire W_op_mulxuu;
wire W_op_nextpc;
wire W_op_nor;
wire W_op_op_rsv02;
wire W_op_op_rsv09;
wire W_op_op_rsv10;
wire W_op_op_rsv17;
wire W_op_op_rsv18;
wire W_op_op_rsv25;
wire W_op_op_rsv26;
wire W_op_op_rsv33;
wire W_op_op_rsv34;
wire W_op_op_rsv41;
wire W_op_op_rsv42;
wire W_op_op_rsv49;
wire W_op_op_rsv57;
wire W_op_op_rsv61;
wire W_op_op_rsv62;
wire W_op_op_rsv63;
wire W_op_opx_rsv00;
wire W_op_opx_rsv10;
wire W_op_opx_rsv15;
wire W_op_opx_rsv17;
wire W_op_opx_rsv21;
wire W_op_opx_rsv25;
wire W_op_opx_rsv33;
wire W_op_opx_rsv34;
wire W_op_opx_rsv35;
wire W_op_opx_rsv42;
wire W_op_opx_rsv43;
wire W_op_opx_rsv44;
wire W_op_opx_rsv47;
wire W_op_opx_rsv50;
wire W_op_opx_rsv51;
wire W_op_opx_rsv55;
wire W_op_opx_rsv56;
wire W_op_opx_rsv60;
wire W_op_opx_rsv63;
wire W_op_or;
wire W_op_orhi;
wire W_op_ori;
wire W_op_rdctl;
wire W_op_rdprs;
wire W_op_ret;
wire W_op_rol;
wire W_op_roli;
wire W_op_ror;
wire W_op_sll;
wire W_op_slli;
wire W_op_sra;
wire W_op_srai;
wire W_op_srl;
wire W_op_srli;
wire W_op_stb;
wire W_op_stbio;
wire W_op_stc;
wire W_op_sth;
wire W_op_sthio;
wire W_op_stw;
wire W_op_stwio;
wire W_op_sub;
wire W_op_sync;
wire W_op_trap;
wire W_op_wrctl;
wire W_op_wrprs;
wire W_op_xor;
wire W_op_xorhi;
wire W_op_xori;
reg [ 31: 0] W_st_data;
reg [ 24: 0] W_target_pcb;
reg W_valid_crst;
reg W_valid_hbreak;
reg W_valid_intr;
reg [ 31: 0] W_wr_data_filtered;
wire test_has_ended;
assign W_op_call = W_iw_op == 0;
assign W_op_jmpi = W_iw_op == 1;
assign W_op_op_rsv02 = W_iw_op == 2;
assign W_op_ldbu = W_iw_op == 3;
assign W_op_addi = W_iw_op == 4;
assign W_op_stb = W_iw_op == 5;
assign W_op_br = W_iw_op == 6;
assign W_op_ldb = W_iw_op == 7;
assign W_op_cmpgei = W_iw_op == 8;
assign W_op_op_rsv09 = W_iw_op == 9;
assign W_op_op_rsv10 = W_iw_op == 10;
assign W_op_ldhu = W_iw_op == 11;
assign W_op_andi = W_iw_op == 12;
assign W_op_sth = W_iw_op == 13;
assign W_op_bge = W_iw_op == 14;
assign W_op_ldh = W_iw_op == 15;
assign W_op_cmplti = W_iw_op == 16;
assign W_op_op_rsv17 = W_iw_op == 17;
assign W_op_op_rsv18 = W_iw_op == 18;
assign W_op_initda = W_iw_op == 19;
assign W_op_ori = W_iw_op == 20;
assign W_op_stw = W_iw_op == 21;
assign W_op_blt = W_iw_op == 22;
assign W_op_ldw = W_iw_op == 23;
assign W_op_cmpnei = W_iw_op == 24;
assign W_op_op_rsv25 = W_iw_op == 25;
assign W_op_op_rsv26 = W_iw_op == 26;
assign W_op_flushda = W_iw_op == 27;
assign W_op_xori = W_iw_op == 28;
assign W_op_stc = W_iw_op == 29;
assign W_op_bne = W_iw_op == 30;
assign W_op_ldl = W_iw_op == 31;
assign W_op_cmpeqi = W_iw_op == 32;
assign W_op_op_rsv33 = W_iw_op == 33;
assign W_op_op_rsv34 = W_iw_op == 34;
assign W_op_ldbuio = W_iw_op == 35;
assign W_op_muli = W_iw_op == 36;
assign W_op_stbio = W_iw_op == 37;
assign W_op_beq = W_iw_op == 38;
assign W_op_ldbio = W_iw_op == 39;
assign W_op_cmpgeui = W_iw_op == 40;
assign W_op_op_rsv41 = W_iw_op == 41;
assign W_op_op_rsv42 = W_iw_op == 42;
assign W_op_ldhuio = W_iw_op == 43;
assign W_op_andhi = W_iw_op == 44;
assign W_op_sthio = W_iw_op == 45;
assign W_op_bgeu = W_iw_op == 46;
assign W_op_ldhio = W_iw_op == 47;
assign W_op_cmpltui = W_iw_op == 48;
assign W_op_op_rsv49 = W_iw_op == 49;
assign W_op_custom = W_iw_op == 50;
assign W_op_initd = W_iw_op == 51;
assign W_op_orhi = W_iw_op == 52;
assign W_op_stwio = W_iw_op == 53;
assign W_op_bltu = W_iw_op == 54;
assign W_op_ldwio = W_iw_op == 55;
assign W_op_rdprs = W_iw_op == 56;
assign W_op_op_rsv57 = W_iw_op == 57;
assign W_op_flushd = W_iw_op == 59;
assign W_op_xorhi = W_iw_op == 60;
assign W_op_op_rsv61 = W_iw_op == 61;
assign W_op_op_rsv62 = W_iw_op == 62;
assign W_op_op_rsv63 = W_iw_op == 63;
assign W_op_opx_rsv00 = (W_iw_opx == 0) & W_is_opx_inst;
assign W_op_eret = (W_iw_opx == 1) & W_is_opx_inst;
assign W_op_roli = (W_iw_opx == 2) & W_is_opx_inst;
assign W_op_rol = (W_iw_opx == 3) & W_is_opx_inst;
assign W_op_flushp = (W_iw_opx == 4) & W_is_opx_inst;
assign W_op_ret = (W_iw_opx == 5) & W_is_opx_inst;
assign W_op_nor = (W_iw_opx == 6) & W_is_opx_inst;
assign W_op_mulxuu = (W_iw_opx == 7) & W_is_opx_inst;
assign W_op_cmpge = (W_iw_opx == 8) & W_is_opx_inst;
assign W_op_bret = (W_iw_opx == 9) & W_is_opx_inst;
assign W_op_opx_rsv10 = (W_iw_opx == 10) & W_is_opx_inst;
assign W_op_ror = (W_iw_opx == 11) & W_is_opx_inst;
assign W_op_flushi = (W_iw_opx == 12) & W_is_opx_inst;
assign W_op_jmp = (W_iw_opx == 13) & W_is_opx_inst;
assign W_op_and = (W_iw_opx == 14) & W_is_opx_inst;
assign W_op_opx_rsv15 = (W_iw_opx == 15) & W_is_opx_inst;
assign W_op_cmplt = (W_iw_opx == 16) & W_is_opx_inst;
assign W_op_opx_rsv17 = (W_iw_opx == 17) & W_is_opx_inst;
assign W_op_slli = (W_iw_opx == 18) & W_is_opx_inst;
assign W_op_sll = (W_iw_opx == 19) & W_is_opx_inst;
assign W_op_wrprs = (W_iw_opx == 20) & W_is_opx_inst;
assign W_op_opx_rsv21 = (W_iw_opx == 21) & W_is_opx_inst;
assign W_op_or = (W_iw_opx == 22) & W_is_opx_inst;
assign W_op_mulxsu = (W_iw_opx == 23) & W_is_opx_inst;
assign W_op_cmpne = (W_iw_opx == 24) & W_is_opx_inst;
assign W_op_opx_rsv25 = (W_iw_opx == 25) & W_is_opx_inst;
assign W_op_srli = (W_iw_opx == 26) & W_is_opx_inst;
assign W_op_srl = (W_iw_opx == 27) & W_is_opx_inst;
assign W_op_nextpc = (W_iw_opx == 28) & W_is_opx_inst;
assign W_op_callr = (W_iw_opx == 29) & W_is_opx_inst;
assign W_op_xor = (W_iw_opx == 30) & W_is_opx_inst;
assign W_op_mulxss = (W_iw_opx == 31) & W_is_opx_inst;
assign W_op_cmpeq = (W_iw_opx == 32) & W_is_opx_inst;
assign W_op_opx_rsv33 = (W_iw_opx == 33) & W_is_opx_inst;
assign W_op_opx_rsv34 = (W_iw_opx == 34) & W_is_opx_inst;
assign W_op_opx_rsv35 = (W_iw_opx == 35) & W_is_opx_inst;
assign W_op_divu = (W_iw_opx == 36) & W_is_opx_inst;
assign W_op_div = (W_iw_opx == 37) & W_is_opx_inst;
assign W_op_rdctl = (W_iw_opx == 38) & W_is_opx_inst;
assign W_op_mul = (W_iw_opx == 39) & W_is_opx_inst;
assign W_op_cmpgeu = (W_iw_opx == 40) & W_is_opx_inst;
assign W_op_initi = (W_iw_opx == 41) & W_is_opx_inst;
assign W_op_opx_rsv42 = (W_iw_opx == 42) & W_is_opx_inst;
assign W_op_opx_rsv43 = (W_iw_opx == 43) & W_is_opx_inst;
assign W_op_opx_rsv44 = (W_iw_opx == 44) & W_is_opx_inst;
assign W_op_trap = (W_iw_opx == 45) & W_is_opx_inst;
assign W_op_wrctl = (W_iw_opx == 46) & W_is_opx_inst;
assign W_op_opx_rsv47 = (W_iw_opx == 47) & W_is_opx_inst;
assign W_op_cmpltu = (W_iw_opx == 48) & W_is_opx_inst;
assign W_op_add = (W_iw_opx == 49) & W_is_opx_inst;
assign W_op_opx_rsv50 = (W_iw_opx == 50) & W_is_opx_inst;
assign W_op_opx_rsv51 = (W_iw_opx == 51) & W_is_opx_inst;
assign W_op_break = (W_iw_opx == 52) & W_is_opx_inst;
assign W_op_hbreak = (W_iw_opx == 53) & W_is_opx_inst;
assign W_op_sync = (W_iw_opx == 54) & W_is_opx_inst;
assign W_op_opx_rsv55 = (W_iw_opx == 55) & W_is_opx_inst;
assign W_op_opx_rsv56 = (W_iw_opx == 56) & W_is_opx_inst;
assign W_op_sub = (W_iw_opx == 57) & W_is_opx_inst;
assign W_op_srai = (W_iw_opx == 58) & W_is_opx_inst;
assign W_op_sra = (W_iw_opx == 59) & W_is_opx_inst;
assign W_op_opx_rsv60 = (W_iw_opx == 60) & W_is_opx_inst;
assign W_op_intr = (W_iw_opx == 61) & W_is_opx_inst;
assign W_op_crst = (W_iw_opx == 62) & W_is_opx_inst;
assign W_op_opx_rsv63 = (W_iw_opx == 63) & W_is_opx_inst;
assign W_is_opx_inst = W_iw_op == 58;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_target_pcb <= 0;
else if (A_en)
A_target_pcb <= M_target_pcb;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_mem_baddr <= 0;
else if (A_en)
A_mem_baddr <= M_mem_baddr;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_wr_data_filtered <= 0;
else
W_wr_data_filtered <= A_wr_data_filtered;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_st_data <= 0;
else
W_st_data <= A_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= A_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_target_pcb <= 0;
else
W_target_pcb <= A_target_pcb;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid_hbreak <= 0;
else
W_valid_hbreak <= A_exc_allowed & A_exc_hbreak_pri1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid_crst <= 0;
else
W_valid_crst <= A_exc_allowed & 0;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid_intr <= 0;
else
W_valid_intr <= A_exc_allowed & A_exc_norm_intr_pri5;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_exc_any_active <= 0;
else
W_exc_any_active <= A_exc_any_active;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_exc_highest_pri_exc_id <= 0;
else
W_exc_highest_pri_exc_id <= A_exc_highest_pri_exc_id;
end
assign A_iw_invalid = A_exc_inst_fetch & A_exc_active_no_break_no_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_iw_invalid <= 0;
else
W_iw_invalid <= A_iw_invalid;
end
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign A_wr_data_unfiltered_0_is_x = ^(A_wr_data_unfiltered[0]) === 1'bx;
assign A_wr_data_filtered[0] = (A_wr_data_unfiltered_0_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[0];
assign A_wr_data_unfiltered_1_is_x = ^(A_wr_data_unfiltered[1]) === 1'bx;
assign A_wr_data_filtered[1] = (A_wr_data_unfiltered_1_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[1];
assign A_wr_data_unfiltered_2_is_x = ^(A_wr_data_unfiltered[2]) === 1'bx;
assign A_wr_data_filtered[2] = (A_wr_data_unfiltered_2_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[2];
assign A_wr_data_unfiltered_3_is_x = ^(A_wr_data_unfiltered[3]) === 1'bx;
assign A_wr_data_filtered[3] = (A_wr_data_unfiltered_3_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[3];
assign A_wr_data_unfiltered_4_is_x = ^(A_wr_data_unfiltered[4]) === 1'bx;
assign A_wr_data_filtered[4] = (A_wr_data_unfiltered_4_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[4];
assign A_wr_data_unfiltered_5_is_x = ^(A_wr_data_unfiltered[5]) === 1'bx;
assign A_wr_data_filtered[5] = (A_wr_data_unfiltered_5_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[5];
assign A_wr_data_unfiltered_6_is_x = ^(A_wr_data_unfiltered[6]) === 1'bx;
assign A_wr_data_filtered[6] = (A_wr_data_unfiltered_6_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[6];
assign A_wr_data_unfiltered_7_is_x = ^(A_wr_data_unfiltered[7]) === 1'bx;
assign A_wr_data_filtered[7] = (A_wr_data_unfiltered_7_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[7];
assign A_wr_data_unfiltered_8_is_x = ^(A_wr_data_unfiltered[8]) === 1'bx;
assign A_wr_data_filtered[8] = (A_wr_data_unfiltered_8_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[8];
assign A_wr_data_unfiltered_9_is_x = ^(A_wr_data_unfiltered[9]) === 1'bx;
assign A_wr_data_filtered[9] = (A_wr_data_unfiltered_9_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[9];
assign A_wr_data_unfiltered_10_is_x = ^(A_wr_data_unfiltered[10]) === 1'bx;
assign A_wr_data_filtered[10] = (A_wr_data_unfiltered_10_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[10];
assign A_wr_data_unfiltered_11_is_x = ^(A_wr_data_unfiltered[11]) === 1'bx;
assign A_wr_data_filtered[11] = (A_wr_data_unfiltered_11_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[11];
assign A_wr_data_unfiltered_12_is_x = ^(A_wr_data_unfiltered[12]) === 1'bx;
assign A_wr_data_filtered[12] = (A_wr_data_unfiltered_12_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[12];
assign A_wr_data_unfiltered_13_is_x = ^(A_wr_data_unfiltered[13]) === 1'bx;
assign A_wr_data_filtered[13] = (A_wr_data_unfiltered_13_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[13];
assign A_wr_data_unfiltered_14_is_x = ^(A_wr_data_unfiltered[14]) === 1'bx;
assign A_wr_data_filtered[14] = (A_wr_data_unfiltered_14_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[14];
assign A_wr_data_unfiltered_15_is_x = ^(A_wr_data_unfiltered[15]) === 1'bx;
assign A_wr_data_filtered[15] = (A_wr_data_unfiltered_15_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[15];
assign A_wr_data_unfiltered_16_is_x = ^(A_wr_data_unfiltered[16]) === 1'bx;
assign A_wr_data_filtered[16] = (A_wr_data_unfiltered_16_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[16];
assign A_wr_data_unfiltered_17_is_x = ^(A_wr_data_unfiltered[17]) === 1'bx;
assign A_wr_data_filtered[17] = (A_wr_data_unfiltered_17_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[17];
assign A_wr_data_unfiltered_18_is_x = ^(A_wr_data_unfiltered[18]) === 1'bx;
assign A_wr_data_filtered[18] = (A_wr_data_unfiltered_18_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[18];
assign A_wr_data_unfiltered_19_is_x = ^(A_wr_data_unfiltered[19]) === 1'bx;
assign A_wr_data_filtered[19] = (A_wr_data_unfiltered_19_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[19];
assign A_wr_data_unfiltered_20_is_x = ^(A_wr_data_unfiltered[20]) === 1'bx;
assign A_wr_data_filtered[20] = (A_wr_data_unfiltered_20_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[20];
assign A_wr_data_unfiltered_21_is_x = ^(A_wr_data_unfiltered[21]) === 1'bx;
assign A_wr_data_filtered[21] = (A_wr_data_unfiltered_21_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[21];
assign A_wr_data_unfiltered_22_is_x = ^(A_wr_data_unfiltered[22]) === 1'bx;
assign A_wr_data_filtered[22] = (A_wr_data_unfiltered_22_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[22];
assign A_wr_data_unfiltered_23_is_x = ^(A_wr_data_unfiltered[23]) === 1'bx;
assign A_wr_data_filtered[23] = (A_wr_data_unfiltered_23_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[23];
assign A_wr_data_unfiltered_24_is_x = ^(A_wr_data_unfiltered[24]) === 1'bx;
assign A_wr_data_filtered[24] = (A_wr_data_unfiltered_24_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[24];
assign A_wr_data_unfiltered_25_is_x = ^(A_wr_data_unfiltered[25]) === 1'bx;
assign A_wr_data_filtered[25] = (A_wr_data_unfiltered_25_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[25];
assign A_wr_data_unfiltered_26_is_x = ^(A_wr_data_unfiltered[26]) === 1'bx;
assign A_wr_data_filtered[26] = (A_wr_data_unfiltered_26_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[26];
assign A_wr_data_unfiltered_27_is_x = ^(A_wr_data_unfiltered[27]) === 1'bx;
assign A_wr_data_filtered[27] = (A_wr_data_unfiltered_27_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[27];
assign A_wr_data_unfiltered_28_is_x = ^(A_wr_data_unfiltered[28]) === 1'bx;
assign A_wr_data_filtered[28] = (A_wr_data_unfiltered_28_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[28];
assign A_wr_data_unfiltered_29_is_x = ^(A_wr_data_unfiltered[29]) === 1'bx;
assign A_wr_data_filtered[29] = (A_wr_data_unfiltered_29_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[29];
assign A_wr_data_unfiltered_30_is_x = ^(A_wr_data_unfiltered[30]) === 1'bx;
assign A_wr_data_filtered[30] = (A_wr_data_unfiltered_30_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[30];
assign A_wr_data_unfiltered_31_is_x = ^(A_wr_data_unfiltered[31]) === 1'bx;
assign A_wr_data_filtered[31] = (A_wr_data_unfiltered_31_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[31];
//Clearing 'X' data bits
assign E_add_br_to_taken_history_unfiltered_is_x = ^(E_add_br_to_taken_history_unfiltered) === 1'bx;
assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered_is_x ? 1'b0 : E_add_br_to_taken_history_unfiltered;
//Clearing 'X' data bits
assign M_bht_wr_en_unfiltered_is_x = ^(M_bht_wr_en_unfiltered) === 1'bx;
assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered_is_x ? 1'b0 : M_bht_wr_en_unfiltered;
//Clearing 'X' data bits
assign M_bht_wr_data_unfiltered_0_is_x = ^(M_bht_wr_data_unfiltered[0]) === 1'bx;
assign M_bht_wr_data_filtered[0] = M_bht_wr_data_unfiltered_0_is_x ? 1'b0 : M_bht_wr_data_unfiltered[0];
assign M_bht_wr_data_unfiltered_1_is_x = ^(M_bht_wr_data_unfiltered[1]) === 1'bx;
assign M_bht_wr_data_filtered[1] = M_bht_wr_data_unfiltered_1_is_x ? 1'b0 : M_bht_wr_data_unfiltered[1];
//Clearing 'X' data bits
assign M_bht_ptr_unfiltered_0_is_x = ^(M_bht_ptr_unfiltered[0]) === 1'bx;
assign M_bht_ptr_filtered[0] = M_bht_ptr_unfiltered_0_is_x ? 1'b0 : M_bht_ptr_unfiltered[0];
assign M_bht_ptr_unfiltered_1_is_x = ^(M_bht_ptr_unfiltered[1]) === 1'bx;
assign M_bht_ptr_filtered[1] = M_bht_ptr_unfiltered_1_is_x ? 1'b0 : M_bht_ptr_unfiltered[1];
assign M_bht_ptr_unfiltered_2_is_x = ^(M_bht_ptr_unfiltered[2]) === 1'bx;
assign M_bht_ptr_filtered[2] = M_bht_ptr_unfiltered_2_is_x ? 1'b0 : M_bht_ptr_unfiltered[2];
assign M_bht_ptr_unfiltered_3_is_x = ^(M_bht_ptr_unfiltered[3]) === 1'bx;
assign M_bht_ptr_filtered[3] = M_bht_ptr_unfiltered_3_is_x ? 1'b0 : M_bht_ptr_unfiltered[3];
assign M_bht_ptr_unfiltered_4_is_x = ^(M_bht_ptr_unfiltered[4]) === 1'bx;
assign M_bht_ptr_filtered[4] = M_bht_ptr_unfiltered_4_is_x ? 1'b0 : M_bht_ptr_unfiltered[4];
assign M_bht_ptr_unfiltered_5_is_x = ^(M_bht_ptr_unfiltered[5]) === 1'bx;
assign M_bht_ptr_filtered[5] = M_bht_ptr_unfiltered_5_is_x ? 1'b0 : M_bht_ptr_unfiltered[5];
assign M_bht_ptr_unfiltered_6_is_x = ^(M_bht_ptr_unfiltered[6]) === 1'bx;
assign M_bht_ptr_filtered[6] = M_bht_ptr_unfiltered_6_is_x ? 1'b0 : M_bht_ptr_unfiltered[6];
assign M_bht_ptr_unfiltered_7_is_x = ^(M_bht_ptr_unfiltered[7]) === 1'bx;
assign M_bht_ptr_filtered[7] = M_bht_ptr_unfiltered_7_is_x ? 1'b0 : M_bht_ptr_unfiltered[7];
always @(posedge clk)
begin
if (reset_n)
if (^(W_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_pcb) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_pcb is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_iw) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_iw is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_en) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/A_en is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_dst_regset) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_dst_regset is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(M_valid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/M_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_valid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/A_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (A_valid & A_en & A_wr_dst_reg)
if (^(A_wr_data_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/A_wr_data_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_status_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_status_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_estatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_estatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_bstatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_bstatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_exception_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_exception_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_badaddr_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_badaddr_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_exc_any_active) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/A_exc_any_active is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_readdatavalid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/i_readdatavalid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_readdatavalid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_readdatavalid is 'x'\n", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign A_wr_data_filtered = A_wr_data_unfiltered;
//
//
// assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered;
//
//
// assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered;
//
//
// assign M_bht_wr_data_filtered = M_bht_wr_data_unfiltered;
//
//
// assign M_bht_ptr_filtered = M_bht_ptr_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
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(* DowngradeIPIdentifiedWarnings="yes" *)
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
(* CHECK_LICENSE_TYPE = "ila_0,ila,{}" *)
(* CORE_GENERATION_INFO = "ila_0,ila,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VERILOG,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=kintex7,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=21,C_DATA_DEPTH=2048,C_MAJOR_VERSION=2016,C_MINOR_VERSION=3,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=2000000,C_PROBE0_WIDTH=64,C_PROBE1_WIDTH=64,C_PROBE2_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE7_WIDTH=64,C_PROBE8_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE12_WIDTH=64,C_PROBE13_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE18_WIDTH=8,C_PROBE19_WIDTH=8,C_PROBE20_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=1,C_PROBE25_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,\
C_PROBE54_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE70_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE81_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE153_WIDTH=1,\
C_PROBE154_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE187_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE236_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE240_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE253_WIDTH=1,\
C_PROBE254_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE266_WIDTH=1,C_PROBE267_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE289_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE292_WIDTH=1,C_PROBE293_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE315_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE319_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE345_WIDTH=1,C_PROBE346_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE353_WIDTH=1,\
C_PROBE354_WIDTH=1,C_PROBE355_WIDTH=1,C_PROBE356_WIDTH=1,C_PROBE357_WIDTH=1,C_PROBE358_WIDTH=1,C_PROBE359_WIDTH=1,C_PROBE360_WIDTH=1,C_PROBE361_WIDTH=1,C_PROBE362_WIDTH=1,C_PROBE363_WIDTH=1,C_PROBE364_WIDTH=1,C_PROBE365_WIDTH=1,C_PROBE366_WIDTH=1,C_PROBE367_WIDTH=1,C_PROBE368_WIDTH=1,C_PROBE369_WIDTH=1,C_PROBE370_WIDTH=1,C_PROBE371_WIDTH=1,C_PROBE372_WIDTH=1,C_PROBE373_WIDTH=1,C_PROBE374_WIDTH=1,C_PROBE375_WIDTH=1,C_PROBE376_WIDTH=1,C_PROBE377_WIDTH=1,C_PROBE378_WIDTH=1,C_PROBE379_WIDTH=1,C_PROBE380_WIDTH=1,C_PROBE381_WIDTH=1,C_PROBE382_WIDTH=1,C_PROBE383_WIDTH=1,C_PROBE384_WIDTH=1,C_PROBE385_WIDTH=1,C_PROBE386_WIDTH=1,C_PROBE387_WIDTH=1,C_PROBE388_WIDTH=1,C_PROBE389_WIDTH=1,C_PROBE390_WIDTH=1,C_PROBE391_WIDTH=1,C_PROBE392_WIDTH=1,C_PROBE393_WIDTH=1,C_PROBE394_WIDTH=1,C_PROBE395_WIDTH=1,C_PROBE396_WIDTH=1,C_PROBE397_WIDTH=1,C_PROBE398_WIDTH=1,C_PROBE399_WIDTH=1,C_PROBE400_WIDTH=1,C_PROBE401_WIDTH=1,C_PROBE402_WIDTH=1,C_PROBE403_WIDTH=1,C_PROBE404_WIDTH=1,C_PROBE405_WIDTH=1,C_PROBE406_WIDTH=1,C_PROBE407_WIDTH=1,C_PROBE408_WIDTH=1,C_PROBE409_WIDTH=1,C_PROBE410_WIDTH=1,C_PROBE411_WIDTH=1,C_PROBE412_WIDTH=1,C_PROBE413_WIDTH=1,C_PROBE414_WIDTH=1,C_PROBE415_WIDTH=1,C_PROBE416_WIDTH=1,C_PROBE417_WIDTH=1,C_PROBE418_WIDTH=1,C_PROBE419_WIDTH=1,C_PROBE420_WIDTH=1,C_PROBE421_WIDTH=1,C_PROBE422_WIDTH=1,C_PROBE423_WIDTH=1,C_PROBE424_WIDTH=1,C_PROBE425_WIDTH=1,C_PROBE426_WIDTH=1,C_PROBE427_WIDTH=1,C_PROBE428_WIDTH=1,C_PROBE429_WIDTH=1,C_PROBE430_WIDTH=1,C_PROBE431_WIDTH=1,C_PROBE432_WIDTH=1,C_PROBE433_WIDTH=1,C_PROBE434_WIDTH=1,C_PROBE435_WIDTH=1,C_PROBE436_WIDTH=1,C_PROBE437_WIDTH=1,C_PROBE438_WIDTH=1,C_PROBE439_WIDTH=1,C_PROBE440_WIDTH=1,C_PROBE441_WIDTH=1,C_PROBE442_WIDTH=1,C_PROBE443_WIDTH=1,C_PROBE444_WIDTH=1,C_PROBE445_WIDTH=1,C_PROBE446_WIDTH=1,C_PROBE447_WIDTH=1,C_PROBE448_WIDTH=1,C_PROBE449_WIDTH=1,C_PROBE450_WIDTH=1,C_PROBE451_WIDTH=1,C_PROBE452_WIDTH=1,C_PROBE453_WIDTH=1,\
C_PROBE454_WIDTH=1,C_PROBE455_WIDTH=1,C_PROBE456_WIDTH=1,C_PROBE457_WIDTH=1,C_PROBE458_WIDTH=1,C_PROBE459_WIDTH=1,C_PROBE460_WIDTH=1,C_PROBE461_WIDTH=1,C_PROBE462_WIDTH=1,C_PROBE463_WIDTH=1,C_PROBE464_WIDTH=1,C_PROBE465_WIDTH=1,C_PROBE466_WIDTH=1,C_PROBE467_WIDTH=1,C_PROBE468_WIDTH=1,C_PROBE469_WIDTH=1,C_PROBE470_WIDTH=1,C_PROBE471_WIDTH=1,C_PROBE472_WIDTH=1,C_PROBE473_WIDTH=1,C_PROBE474_WIDTH=1,C_PROBE475_WIDTH=1,C_PROBE476_WIDTH=1,C_PROBE477_WIDTH=1,C_PROBE478_WIDTH=1,C_PROBE479_WIDTH=1,C_PROBE480_WIDTH=1,C_PROBE481_WIDTH=1,C_PROBE482_WIDTH=1,C_PROBE483_WIDTH=1,C_PROBE484_WIDTH=1,C_PROBE485_WIDTH=1,C_PROBE486_WIDTH=1,C_PROBE487_WIDTH=1,C_PROBE488_WIDTH=1,C_PROBE489_WIDTH=1,C_PROBE490_WIDTH=1,C_PROBE491_WIDTH=1,C_PROBE492_WIDTH=1,C_PROBE493_WIDTH=1,C_PROBE494_WIDTH=1,C_PROBE495_WIDTH=1,C_PROBE496_WIDTH=1,C_PROBE497_WIDTH=1,C_PROBE498_WIDTH=1,C_PROBE499_WIDTH=1,C_PROBE500_WIDTH=1,C_PROBE501_WIDTH=1,C_PROBE502_WIDTH=1,C_PROBE503_WIDTH=1,C_PROBE504_WIDTH=1,C_PROBE505_WIDTH=1,C_PROBE506_WIDTH=1,C_PROBE507_WIDTH=1,C_PROBE508_WIDTH=1,C_PROBE509_WIDTH=1,C_PROBE510_WIDTH=1,C_PROBE511_WIDTH=1,C_PROBE512_WIDTH=1,C_PROBE513_WIDTH=1,C_PROBE514_WIDTH=1,C_PROBE515_WIDTH=1,C_PROBE516_WIDTH=1,C_PROBE517_WIDTH=1,C_PROBE518_WIDTH=1,C_PROBE519_WIDTH=1,C_PROBE520_WIDTH=1,C_PROBE521_WIDTH=1,C_PROBE522_WIDTH=1,C_PROBE523_WIDTH=1,C_PROBE524_WIDTH=1,C_PROBE525_WIDTH=1,C_PROBE526_WIDTH=1,C_PROBE527_WIDTH=1,C_PROBE528_WIDTH=1,C_PROBE529_WIDTH=1,C_PROBE530_WIDTH=1,C_PROBE531_WIDTH=1,C_PROBE532_WIDTH=1,C_PROBE533_WIDTH=1,C_PROBE534_WIDTH=1,C_PROBE535_WIDTH=1,C_PROBE536_WIDTH=1,C_PROBE537_WIDTH=1,C_PROBE538_WIDTH=1,C_PROBE539_WIDTH=1,C_PROBE540_WIDTH=1,C_PROBE541_WIDTH=1,C_PROBE542_WIDTH=1,C_PROBE543_WIDTH=1,C_PROBE544_WIDTH=1,C_PROBE545_WIDTH=1,C_PROBE546_WIDTH=1,C_PROBE547_WIDTH=1,C_PROBE548_WIDTH=1,C_PROBE549_WIDTH=1,C_PROBE550_WIDTH=1,C_PROBE551_WIDTH=1,C_PROBE552_WIDTH=1,C_PROBE553_WIDTH=1,\
C_PROBE554_WIDTH=1,C_PROBE555_WIDTH=1,C_PROBE556_WIDTH=1,C_PROBE557_WIDTH=1,C_PROBE558_WIDTH=1,C_PROBE559_WIDTH=1,C_PROBE560_WIDTH=1,C_PROBE561_WIDTH=1,C_PROBE562_WIDTH=1,C_PROBE563_WIDTH=1,C_PROBE564_WIDTH=1,C_PROBE565_WIDTH=1,C_PROBE566_WIDTH=1,C_PROBE567_WIDTH=1,C_PROBE568_WIDTH=1,C_PROBE569_WIDTH=1,C_PROBE570_WIDTH=1,C_PROBE571_WIDTH=1,C_PROBE572_WIDTH=1,C_PROBE573_WIDTH=1,C_PROBE574_WIDTH=1,C_PROBE575_WIDTH=1,C_PROBE576_WIDTH=1,C_PROBE577_WIDTH=1,C_PROBE578_WIDTH=1,C_PROBE579_WIDTH=1,C_PROBE580_WIDTH=1,C_PROBE581_WIDTH=1,C_PROBE582_WIDTH=1,C_PROBE583_WIDTH=1,C_PROBE584_WIDTH=1,C_PROBE585_WIDTH=1,C_PROBE586_WIDTH=1,C_PROBE587_WIDTH=1,C_PROBE588_WIDTH=1,C_PROBE589_WIDTH=1,C_PROBE590_WIDTH=1,C_PROBE591_WIDTH=1,C_PROBE592_WIDTH=1,C_PROBE593_WIDTH=1,C_PROBE594_WIDTH=1,C_PROBE595_WIDTH=1,C_PROBE596_WIDTH=1,C_PROBE597_WIDTH=1,C_PROBE598_WIDTH=1,C_PROBE599_WIDTH=1,C_PROBE600_WIDTH=1,C_PROBE601_WIDTH=1,C_PROBE602_WIDTH=1,C_PROBE603_WIDTH=1,C_PROBE604_WIDTH=1,C_PROBE605_WIDTH=1,C_PROBE606_WIDTH=1,C_PROBE607_WIDTH=1,C_PROBE608_WIDTH=1,C_PROBE609_WIDTH=1,C_PROBE610_WIDTH=1,C_PROBE611_WIDTH=1,C_PROBE612_WIDTH=1,C_PROBE613_WIDTH=1,C_PROBE614_WIDTH=1,C_PROBE615_WIDTH=1,C_PROBE616_WIDTH=1,C_PROBE617_WIDTH=1,C_PROBE618_WIDTH=1,C_PROBE619_WIDTH=1,C_PROBE620_WIDTH=1,C_PROBE621_WIDTH=1,C_PROBE622_WIDTH=1,C_PROBE623_WIDTH=1,C_PROBE624_WIDTH=1,C_PROBE625_WIDTH=1,C_PROBE626_WIDTH=1,C_PROBE627_WIDTH=1,C_PROBE628_WIDTH=1,C_PROBE629_WIDTH=1,C_PROBE630_WIDTH=1,C_PROBE631_WIDTH=1,C_PROBE632_WIDTH=1,C_PROBE633_WIDTH=1,C_PROBE634_WIDTH=1,C_PROBE635_WIDTH=1,C_PROBE636_WIDTH=1,C_PROBE637_WIDTH=1,C_PROBE638_WIDTH=1,C_PROBE639_WIDTH=1,C_PROBE640_WIDTH=1,C_PROBE641_WIDTH=1,C_PROBE642_WIDTH=1,C_PROBE643_WIDTH=1,C_PROBE644_WIDTH=1,C_PROBE645_WIDTH=1,C_PROBE646_WIDTH=1,C_PROBE647_WIDTH=1,C_PROBE648_WIDTH=1,C_PROBE649_WIDTH=1,C_PROBE650_WIDTH=1,C_PROBE651_WIDTH=1,C_PROBE652_WIDTH=1,C_PROBE653_WIDTH=1,\
C_PROBE654_WIDTH=1,C_PROBE655_WIDTH=1,C_PROBE656_WIDTH=1,C_PROBE657_WIDTH=1,C_PROBE658_WIDTH=1,C_PROBE659_WIDTH=1,C_PROBE660_WIDTH=1,C_PROBE661_WIDTH=1,C_PROBE662_WIDTH=1,C_PROBE663_WIDTH=1,C_PROBE664_WIDTH=1,C_PROBE665_WIDTH=1,C_PROBE666_WIDTH=1,C_PROBE667_WIDTH=1,C_PROBE668_WIDTH=1,C_PROBE669_WIDTH=1,C_PROBE670_WIDTH=1,C_PROBE671_WIDTH=1,C_PROBE672_WIDTH=1,C_PROBE673_WIDTH=1,C_PROBE674_WIDTH=1,C_PROBE675_WIDTH=1,C_PROBE676_WIDTH=1,C_PROBE677_WIDTH=1,C_PROBE678_WIDTH=1,C_PROBE679_WIDTH=1,C_PROBE680_WIDTH=1,C_PROBE681_WIDTH=1,C_PROBE682_WIDTH=1,C_PROBE683_WIDTH=1,C_PROBE684_WIDTH=1,C_PROBE685_WIDTH=1,C_PROBE686_WIDTH=1,C_PROBE687_WIDTH=1,C_PROBE688_WIDTH=1,C_PROBE689_WIDTH=1,C_PROBE690_WIDTH=1,C_PROBE691_WIDTH=1,C_PROBE692_WIDTH=1,C_PROBE693_WIDTH=1,C_PROBE694_WIDTH=1,C_PROBE695_WIDTH=1,C_PROBE696_WIDTH=1,C_PROBE697_WIDTH=1,C_PROBE698_WIDTH=1,C_PROBE699_WIDTH=1,C_PROBE700_WIDTH=1,C_PROBE701_WIDTH=1,C_PROBE702_WIDTH=1,C_PROBE703_WIDTH=1,C_PROBE704_WIDTH=1,C_PROBE705_WIDTH=1,C_PROBE706_WIDTH=1,C_PROBE707_WIDTH=1,C_PROBE708_WIDTH=1,C_PROBE709_WIDTH=1,C_PROBE710_WIDTH=1,C_PROBE711_WIDTH=1,C_PROBE712_WIDTH=1,C_PROBE713_WIDTH=1,C_PROBE714_WIDTH=1,C_PROBE715_WIDTH=1,C_PROBE716_WIDTH=1,C_PROBE717_WIDTH=1,C_PROBE718_WIDTH=1,C_PROBE719_WIDTH=1,C_PROBE720_WIDTH=1,C_PROBE721_WIDTH=1,C_PROBE722_WIDTH=1,C_PROBE723_WIDTH=1,C_PROBE724_WIDTH=1,C_PROBE725_WIDTH=1,C_PROBE726_WIDTH=1,C_PROBE727_WIDTH=1,C_PROBE728_WIDTH=1,C_PROBE729_WIDTH=1,C_PROBE730_WIDTH=1,C_PROBE731_WIDTH=1,C_PROBE732_WIDTH=1,C_PROBE733_WIDTH=1,C_PROBE734_WIDTH=1,C_PROBE735_WIDTH=1,C_PROBE736_WIDTH=1,C_PROBE737_WIDTH=1,C_PROBE738_WIDTH=1,C_PROBE739_WIDTH=1,C_PROBE740_WIDTH=1,C_PROBE741_WIDTH=1,C_PROBE742_WIDTH=1,C_PROBE743_WIDTH=1,C_PROBE744_WIDTH=1,C_PROBE745_WIDTH=1,C_PROBE746_WIDTH=1,C_PROBE747_WIDTH=1,C_PROBE748_WIDTH=1,C_PROBE749_WIDTH=1,C_PROBE750_WIDTH=1,C_PROBE751_WIDTH=1,C_PROBE752_WIDTH=1,C_PROBE753_WIDTH=1,\
C_PROBE754_WIDTH=1,C_PROBE755_WIDTH=1,C_PROBE756_WIDTH=1,C_PROBE757_WIDTH=1,C_PROBE758_WIDTH=1,C_PROBE759_WIDTH=1,C_PROBE760_WIDTH=1,C_PROBE761_WIDTH=1,C_PROBE762_WIDTH=1,C_PROBE763_WIDTH=1,C_PROBE764_WIDTH=1,C_PROBE765_WIDTH=1,C_PROBE766_WIDTH=1,C_PROBE767_WIDTH=1,C_PROBE768_WIDTH=1,C_PROBE769_WIDTH=1,C_PROBE770_WIDTH=1,C_PROBE771_WIDTH=1,C_PROBE772_WIDTH=1,C_PROBE773_WIDTH=1,C_PROBE774_WIDTH=1,C_PROBE775_WIDTH=1,C_PROBE776_WIDTH=1,C_PROBE777_WIDTH=1,C_PROBE778_WIDTH=1,C_PROBE779_WIDTH=1,C_PROBE780_WIDTH=1,C_PROBE781_WIDTH=1,C_PROBE782_WIDTH=1,C_PROBE783_WIDTH=1,C_PROBE784_WIDTH=1,C_PROBE785_WIDTH=1,C_PROBE786_WIDTH=1,C_PROBE787_WIDTH=1,C_PROBE788_WIDTH=1,C_PROBE789_WIDTH=1,C_PROBE790_WIDTH=1,C_PROBE791_WIDTH=1,C_PROBE792_WIDTH=1,C_PROBE793_WIDTH=1,C_PROBE794_WIDTH=1,C_PROBE795_WIDTH=1,C_PROBE796_WIDTH=1,C_PROBE797_WIDTH=1,C_PROBE798_WIDTH=1,C_PROBE799_WIDTH=1,C_PROBE800_WIDTH=1,C_PROBE801_WIDTH=1,C_PROBE802_WIDTH=1,C_PROBE803_WIDTH=1,C_PROBE804_WIDTH=1,C_PROBE805_WIDTH=1,C_PROBE806_WIDTH=1,C_PROBE807_WIDTH=1,C_PROBE808_WIDTH=1,C_PROBE809_WIDTH=1,C_PROBE810_WIDTH=1,C_PROBE811_WIDTH=1,C_PROBE812_WIDTH=1,C_PROBE813_WIDTH=1,C_PROBE814_WIDTH=1,C_PROBE815_WIDTH=1,C_PROBE816_WIDTH=1,C_PROBE817_WIDTH=1,C_PROBE818_WIDTH=1,C_PROBE819_WIDTH=1,C_PROBE820_WIDTH=1,C_PROBE821_WIDTH=1,C_PROBE822_WIDTH=1,C_PROBE823_WIDTH=1,C_PROBE824_WIDTH=1,C_PROBE825_WIDTH=1,C_PROBE826_WIDTH=1,C_PROBE827_WIDTH=1,C_PROBE828_WIDTH=1,C_PROBE829_WIDTH=1,C_PROBE830_WIDTH=1,C_PROBE831_WIDTH=1,C_PROBE832_WIDTH=1,C_PROBE833_WIDTH=1,C_PROBE834_WIDTH=1,C_PROBE835_WIDTH=1,C_PROBE836_WIDTH=1,C_PROBE837_WIDTH=1,C_PROBE838_WIDTH=1,C_PROBE839_WIDTH=1,C_PROBE840_WIDTH=1,C_PROBE841_WIDTH=1,C_PROBE842_WIDTH=1,C_PROBE843_WIDTH=1,C_PROBE844_WIDTH=1,C_PROBE845_WIDTH=1,C_PROBE846_WIDTH=1,C_PROBE847_WIDTH=1,C_PROBE848_WIDTH=1,C_PROBE849_WIDTH=1,C_PROBE850_WIDTH=1,C_PROBE851_WIDTH=1,C_PROBE852_WIDTH=1,C_PROBE853_WIDTH=1,\
C_PROBE854_WIDTH=1,C_PROBE855_WIDTH=1,C_PROBE856_WIDTH=1,C_PROBE857_WIDTH=1,C_PROBE858_WIDTH=1,C_PROBE859_WIDTH=1,C_PROBE860_WIDTH=1,C_PROBE861_WIDTH=1,C_PROBE862_WIDTH=1,C_PROBE863_WIDTH=1,C_PROBE864_WIDTH=1,C_PROBE865_WIDTH=1,C_PROBE866_WIDTH=1,C_PROBE867_WIDTH=1,C_PROBE868_WIDTH=1,C_PROBE869_WIDTH=1,C_PROBE870_WIDTH=1,C_PROBE871_WIDTH=1,C_PROBE872_WIDTH=1,C_PROBE873_WIDTH=1,C_PROBE874_WIDTH=1,C_PROBE875_WIDTH=1,C_PROBE876_WIDTH=1,C_PROBE877_WIDTH=1,C_PROBE878_WIDTH=1,C_PROBE879_WIDTH=1,C_PROBE880_WIDTH=1,C_PROBE881_WIDTH=1,C_PROBE882_WIDTH=1,C_PROBE883_WIDTH=1,C_PROBE884_WIDTH=1,C_PROBE885_WIDTH=1,C_PROBE886_WIDTH=1,C_PROBE887_WIDTH=1,C_PROBE888_WIDTH=1,C_PROBE889_WIDTH=1,C_PROBE890_WIDTH=1,C_PROBE891_WIDTH=1,C_PROBE892_WIDTH=1,C_PROBE893_WIDTH=1,C_PROBE894_WIDTH=1,C_PROBE895_WIDTH=1,C_PROBE896_WIDTH=1,C_PROBE897_WIDTH=1,C_PROBE898_WIDTH=1,C_PROBE899_WIDTH=1,C_PROBE900_WIDTH=1,C_PROBE901_WIDTH=1,C_PROBE902_WIDTH=1,C_PROBE903_WIDTH=1,C_PROBE904_WIDTH=1,C_PROBE905_WIDTH=1,C_PROBE906_WIDTH=1,C_PROBE907_WIDTH=1,C_PROBE908_WIDTH=1,C_PROBE909_WIDTH=1,C_PROBE910_WIDTH=1,C_PROBE911_WIDTH=1,C_PROBE912_WIDTH=1,C_PROBE913_WIDTH=1,C_PROBE914_WIDTH=1,C_PROBE915_WIDTH=1,C_PROBE916_WIDTH=1,C_PROBE917_WIDTH=1,C_PROBE918_WIDTH=1,C_PROBE919_WIDTH=1,C_PROBE920_WIDTH=1,C_PROBE921_WIDTH=1,C_PROBE922_WIDTH=1,C_PROBE923_WIDTH=1,C_PROBE924_WIDTH=1,C_PROBE925_WIDTH=1,C_PROBE926_WIDTH=1,C_PROBE927_WIDTH=1,C_PROBE928_WIDTH=1,C_PROBE929_WIDTH=1,C_PROBE930_WIDTH=1,C_PROBE931_WIDTH=1,C_PROBE932_WIDTH=1,C_PROBE933_WIDTH=1,C_PROBE934_WIDTH=1,C_PROBE935_WIDTH=1,C_PROBE936_WIDTH=1,C_PROBE937_WIDTH=1,C_PROBE938_WIDTH=1,C_PROBE939_WIDTH=1,C_PROBE940_WIDTH=1,C_PROBE941_WIDTH=1,C_PROBE942_WIDTH=1,C_PROBE943_WIDTH=1,C_PROBE944_WIDTH=1,C_PROBE945_WIDTH=1,C_PROBE946_WIDTH=1,C_PROBE947_WIDTH=1,C_PROBE948_WIDTH=1,C_PROBE949_WIDTH=1,C_PROBE950_WIDTH=1,C_PROBE951_WIDTH=1,C_PROBE952_WIDTH=1,C_PROBE953_WIDTH=1,\
C_PROBE954_WIDTH=1,C_PROBE955_WIDTH=1,C_PROBE956_WIDTH=1,C_PROBE957_WIDTH=1,C_PROBE958_WIDTH=1,C_PROBE959_WIDTH=1,C_PROBE960_WIDTH=1,C_PROBE961_WIDTH=1,C_PROBE962_WIDTH=1,C_PROBE963_WIDTH=1,C_PROBE964_WIDTH=1,C_PROBE965_WIDTH=1,C_PROBE966_WIDTH=1,C_PROBE967_WIDTH=1,C_PROBE968_WIDTH=1,C_PROBE969_WIDTH=1,C_PROBE970_WIDTH=1,C_PROBE971_WIDTH=1,C_PROBE972_WIDTH=1,C_PROBE973_WIDTH=1,C_PROBE974_WIDTH=1,C_PROBE975_WIDTH=1,C_PROBE976_WIDTH=1,C_PROBE977_WIDTH=1,C_PROBE978_WIDTH=1,C_PROBE979_WIDTH=1,C_PROBE980_WIDTH=1,C_PROBE981_WIDTH=1,C_PROBE982_WIDTH=1,C_PROBE983_WIDTH=1,C_PROBE984_WIDTH=1,C_PROBE985_WIDTH=1,C_PROBE986_WIDTH=1,C_PROBE987_WIDTH=1,C_PROBE988_WIDTH=1,C_PROBE989_WIDTH=1,C_PROBE990_WIDTH=1,C_PROBE991_WIDTH=1,C_PROBE992_WIDTH=1,C_PROBE993_WIDTH=1,C_PROBE994_WIDTH=1,C_PROBE995_WIDTH=1,C_PROBE996_WIDTH=1,C_PROBE997_WIDTH=1,C_PROBE998_WIDTH=1,C_PROBE999_WIDTH=1,C_PROBE1000_WIDTH=1,C_PROBE1001_WIDTH=1,C_PROBE1002_WIDTH=1,C_PROBE1003_WIDTH=1,C_PROBE1004_WIDTH=1,C_PROBE1005_WIDTH=1,C_PROBE1006_WIDTH=1,C_PROBE1007_WIDTH=1,C_PROBE1008_WIDTH=1,C_PROBE1009_WIDTH=1,C_PROBE1010_WIDTH=1,C_PROBE1011_WIDTH=1,C_PROBE1012_WIDTH=1,C_PROBE1013_WIDTH=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,\
C_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,\
C_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,\
C_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,\
C_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,\
C_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,\
C_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,\
C_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,\
C_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,\
C_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,\
C_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=0,C_PROBE2_TYPE=0,C_PROBE3_TYPE=0,C_PROBE4_TYPE=0,C_PROBE5_TYPE=0,\
C_PROBE6_TYPE=0,C_PROBE7_TYPE=0,C_PROBE8_TYPE=0,C_PROBE9_TYPE=0,C_PROBE10_TYPE=0,C_PROBE11_TYPE=0,C_PROBE12_TYPE=0,C_PROBE13_TYPE=0,C_PROBE14_TYPE=0,C_PROBE15_TYPE=0,C_PROBE16_TYPE=0,C_PROBE17_TYPE=0,C_PROBE18_TYPE=0,C_PROBE19_TYPE=0,C_PROBE20_TYPE=0,C_PROBE21_TYPE=1,C_PROBE22_TYPE=1,C_PROBE23_TYPE=1,C_PROBE24_TYPE=1,C_PROBE25_TYPE=1,C_PROBE26_TYPE=1,C_PROBE27_TYPE=1,C_PROBE28_TYPE=1,C_PROBE29_TYPE=1,C_PROBE30_TYPE=1,C_PROBE31_TYPE=1,C_PROBE32_TYPE=1,C_PROBE33_TYPE=1,C_PROBE34_TYPE=1,C_PROBE35_TYPE=1,C_PROBE36_TYPE=1,C_PROBE37_TYPE=1,C_PROBE38_TYPE=1,C_PROBE39_TYPE=1,C_PROBE40_TYPE=1,C_PROBE41_TYPE=1,C_PROBE42_TYPE=1,C_PROBE43_TYPE=1,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,\
C_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,\
C_PROBE206_TYPE=1,C_PROBE207_TYPE=1,C_PROBE208_TYPE=1,C_PROBE209_TYPE=1,C_PROBE210_TYPE=1,C_PROBE211_TYPE=1,C_PROBE212_TYPE=1,C_PROBE213_TYPE=1,C_PROBE214_TYPE=1,C_PROBE215_TYPE=1,C_PROBE216_TYPE=1,C_PROBE217_TYPE=1,C_PROBE218_TYPE=1,C_PROBE219_TYPE=1,C_PROBE220_TYPE=1,C_PROBE221_TYPE=1,C_PROBE222_TYPE=1,C_PROBE223_TYPE=1,C_PROBE224_TYPE=1,C_PROBE225_TYPE=1,C_PROBE226_TYPE=1,C_PROBE227_TYPE=1,C_PROBE228_TYPE=1,C_PROBE229_TYPE=1,C_PROBE230_TYPE=1,C_PROBE231_TYPE=1,C_PROBE232_TYPE=1,C_PROBE233_TYPE=1,C_PROBE234_TYPE=1,C_PROBE235_TYPE=1,C_PROBE236_TYPE=1,C_PROBE237_TYPE=1,C_PROBE238_TYPE=1,C_PROBE239_TYPE=1,C_PROBE240_TYPE=1,C_PROBE241_TYPE=1,C_PROBE242_TYPE=1,C_PROBE243_TYPE=1,C_PROBE244_TYPE=1,C_PROBE245_TYPE=1,C_PROBE246_TYPE=1,C_PROBE247_TYPE=1,C_PROBE248_TYPE=1,C_PROBE249_TYPE=1,C_PROBE250_TYPE=1,C_PROBE251_TYPE=1,C_PROBE252_TYPE=1,C_PROBE253_TYPE=1,C_PROBE254_TYPE=1,C_PROBE255_TYPE=1,C_PROBE256_TYPE=1,C_PROBE257_TYPE=1,C_PROBE258_TYPE=1,C_PROBE259_TYPE=1,C_PROBE260_TYPE=1,C_PROBE261_TYPE=1,C_PROBE262_TYPE=1,C_PROBE263_TYPE=1,C_PROBE264_TYPE=1,C_PROBE265_TYPE=1,C_PROBE266_TYPE=1,C_PROBE267_TYPE=1,C_PROBE268_TYPE=1,C_PROBE269_TYPE=1,C_PROBE270_TYPE=1,C_PROBE271_TYPE=1,C_PROBE272_TYPE=1,C_PROBE273_TYPE=1,C_PROBE274_TYPE=1,C_PROBE275_TYPE=1,C_PROBE276_TYPE=1,C_PROBE277_TYPE=1,C_PROBE278_TYPE=1,C_PROBE279_TYPE=1,C_PROBE280_TYPE=1,C_PROBE281_TYPE=1,C_PROBE282_TYPE=1,C_PROBE283_TYPE=1,C_PROBE284_TYPE=1,C_PROBE285_TYPE=1,C_PROBE286_TYPE=1,C_PROBE287_TYPE=1,C_PROBE288_TYPE=1,C_PROBE289_TYPE=1,C_PROBE290_TYPE=1,C_PROBE291_TYPE=1,C_PROBE292_TYPE=1,C_PROBE293_TYPE=1,C_PROBE294_TYPE=1,C_PROBE295_TYPE=1,C_PROBE296_TYPE=1,C_PROBE297_TYPE=1,C_PROBE298_TYPE=1,C_PROBE299_TYPE=1,C_PROBE300_TYPE=1,C_PROBE301_TYPE=1,C_PROBE302_TYPE=1,C_PROBE303_TYPE=1,C_PROBE304_TYPE=1,C_PROBE305_TYPE=1,\
C_PROBE306_TYPE=1,C_PROBE307_TYPE=1,C_PROBE308_TYPE=1,C_PROBE309_TYPE=1,C_PROBE310_TYPE=1,C_PROBE311_TYPE=1,C_PROBE312_TYPE=1,C_PROBE313_TYPE=1,C_PROBE314_TYPE=1,C_PROBE315_TYPE=1,C_PROBE316_TYPE=1,C_PROBE317_TYPE=1,C_PROBE318_TYPE=1,C_PROBE319_TYPE=1,C_PROBE320_TYPE=1,C_PROBE321_TYPE=1,C_PROBE322_TYPE=1,C_PROBE323_TYPE=1,C_PROBE324_TYPE=1,C_PROBE325_TYPE=1,C_PROBE326_TYPE=1,C_PROBE327_TYPE=1,C_PROBE328_TYPE=1,C_PROBE329_TYPE=1,C_PROBE330_TYPE=1,C_PROBE331_TYPE=1,C_PROBE332_TYPE=1,C_PROBE333_TYPE=1,C_PROBE334_TYPE=1,C_PROBE335_TYPE=1,C_PROBE336_TYPE=1,C_PROBE337_TYPE=1,C_PROBE338_TYPE=1,C_PROBE339_TYPE=1,C_PROBE340_TYPE=1,C_PROBE341_TYPE=1,C_PROBE342_TYPE=1,C_PROBE343_TYPE=1,C_PROBE344_TYPE=1,C_PROBE345_TYPE=1,C_PROBE346_TYPE=1,C_PROBE347_TYPE=1,C_PROBE348_TYPE=1,C_PROBE349_TYPE=1,C_PROBE350_TYPE=1,C_PROBE351_TYPE=1,C_PROBE352_TYPE=1,C_PROBE353_TYPE=1,C_PROBE354_TYPE=1,C_PROBE355_TYPE=1,C_PROBE356_TYPE=1,C_PROBE357_TYPE=1,C_PROBE358_TYPE=1,C_PROBE359_TYPE=1,C_PROBE360_TYPE=1,C_PROBE361_TYPE=1,C_PROBE362_TYPE=1,C_PROBE363_TYPE=1,C_PROBE364_TYPE=1,C_PROBE365_TYPE=1,C_PROBE366_TYPE=1,C_PROBE367_TYPE=1,C_PROBE368_TYPE=1,C_PROBE369_TYPE=1,C_PROBE370_TYPE=1,C_PROBE371_TYPE=1,C_PROBE372_TYPE=1,C_PROBE373_TYPE=1,C_PROBE374_TYPE=1,C_PROBE375_TYPE=1,C_PROBE376_TYPE=1,C_PROBE377_TYPE=1,C_PROBE378_TYPE=1,C_PROBE379_TYPE=1,C_PROBE380_TYPE=1,C_PROBE381_TYPE=1,C_PROBE382_TYPE=1,C_PROBE383_TYPE=1,C_PROBE384_TYPE=1,C_PROBE385_TYPE=1,C_PROBE386_TYPE=1,C_PROBE387_TYPE=1,C_PROBE388_TYPE=1,C_PROBE389_TYPE=1,C_PROBE390_TYPE=1,C_PROBE391_TYPE=1,C_PROBE392_TYPE=1,C_PROBE393_TYPE=1,C_PROBE394_TYPE=1,C_PROBE395_TYPE=1,C_PROBE396_TYPE=1,C_PROBE397_TYPE=1,C_PROBE398_TYPE=1,C_PROBE399_TYPE=1,C_PROBE400_TYPE=1,C_PROBE401_TYPE=1,C_PROBE402_TYPE=1,C_PROBE403_TYPE=1,C_PROBE404_TYPE=1,C_PROBE405_TYPE=1,\
C_PROBE406_TYPE=1,C_PROBE407_TYPE=1,C_PROBE408_TYPE=1,C_PROBE409_TYPE=1,C_PROBE410_TYPE=1,C_PROBE411_TYPE=1,C_PROBE412_TYPE=1,C_PROBE413_TYPE=1,C_PROBE414_TYPE=1,C_PROBE415_TYPE=1,C_PROBE416_TYPE=1,C_PROBE417_TYPE=1,C_PROBE418_TYPE=1,C_PROBE419_TYPE=1,C_PROBE420_TYPE=1,C_PROBE421_TYPE=1,C_PROBE422_TYPE=1,C_PROBE423_TYPE=1,C_PROBE424_TYPE=1,C_PROBE425_TYPE=1,C_PROBE426_TYPE=1,C_PROBE427_TYPE=1,C_PROBE428_TYPE=1,C_PROBE429_TYPE=1,C_PROBE430_TYPE=1,C_PROBE431_TYPE=1,C_PROBE432_TYPE=1,C_PROBE433_TYPE=1,C_PROBE434_TYPE=1,C_PROBE435_TYPE=1,C_PROBE436_TYPE=1,C_PROBE437_TYPE=1,C_PROBE438_TYPE=1,C_PROBE439_TYPE=1,C_PROBE440_TYPE=1,C_PROBE441_TYPE=1,C_PROBE442_TYPE=1,C_PROBE443_TYPE=1,C_PROBE444_TYPE=1,C_PROBE445_TYPE=1,C_PROBE446_TYPE=1,C_PROBE447_TYPE=1,C_PROBE448_TYPE=1,C_PROBE449_TYPE=1,C_PROBE450_TYPE=1,C_PROBE451_TYPE=1,C_PROBE452_TYPE=1,C_PROBE453_TYPE=1,C_PROBE454_TYPE=1,C_PROBE455_TYPE=1,C_PROBE456_TYPE=1,C_PROBE457_TYPE=1,C_PROBE458_TYPE=1,C_PROBE459_TYPE=1,C_PROBE460_TYPE=1,C_PROBE461_TYPE=1,C_PROBE462_TYPE=1,C_PROBE463_TYPE=1,C_PROBE464_TYPE=1,C_PROBE465_TYPE=1,C_PROBE466_TYPE=1,C_PROBE467_TYPE=1,C_PROBE468_TYPE=1,C_PROBE469_TYPE=1,C_PROBE470_TYPE=1,C_PROBE471_TYPE=1,C_PROBE472_TYPE=1,C_PROBE473_TYPE=1,C_PROBE474_TYPE=1,C_PROBE475_TYPE=1,C_PROBE476_TYPE=1,C_PROBE477_TYPE=1,C_PROBE478_TYPE=1,C_PROBE479_TYPE=1,C_PROBE480_TYPE=1,C_PROBE481_TYPE=1,C_PROBE482_TYPE=1,C_PROBE483_TYPE=1,C_PROBE484_TYPE=1,C_PROBE485_TYPE=1,C_PROBE486_TYPE=1,C_PROBE487_TYPE=1,C_PROBE488_TYPE=1,C_PROBE489_TYPE=1,C_PROBE490_TYPE=1,C_PROBE491_TYPE=1,C_PROBE492_TYPE=1,C_PROBE493_TYPE=1,C_PROBE494_TYPE=1,C_PROBE495_TYPE=1,C_PROBE496_TYPE=1,C_PROBE497_TYPE=1,C_PROBE498_TYPE=1,C_PROBE499_TYPE=1,C_PROBE500_TYPE=1,C_PROBE501_TYPE=1,C_PROBE502_TYPE=1,C_PROBE503_TYPE=1,C_PROBE504_TYPE=1,C_PROBE505_TYPE=1,\
C_PROBE506_TYPE=1,C_PROBE507_TYPE=1,C_PROBE508_TYPE=1,C_PROBE509_TYPE=1,C_PROBE510_TYPE=1,C_PROBE511_TYPE=1,C_PROBE512_TYPE=1,C_PROBE513_TYPE=1,C_PROBE514_TYPE=1,C_PROBE515_TYPE=1,C_PROBE516_TYPE=1,C_PROBE517_TYPE=1,C_PROBE518_TYPE=1,C_PROBE519_TYPE=1,C_PROBE520_TYPE=1,C_PROBE521_TYPE=1,C_PROBE522_TYPE=1,C_PROBE523_TYPE=1,C_PROBE524_TYPE=1,C_PROBE525_TYPE=1,C_PROBE526_TYPE=1,C_PROBE527_TYPE=1,C_PROBE528_TYPE=1,C_PROBE529_TYPE=1,C_PROBE530_TYPE=1,C_PROBE531_TYPE=1,C_PROBE532_TYPE=1,C_PROBE533_TYPE=1,C_PROBE534_TYPE=1,C_PROBE535_TYPE=1,C_PROBE536_TYPE=1,C_PROBE537_TYPE=1,C_PROBE538_TYPE=1,C_PROBE539_TYPE=1,C_PROBE540_TYPE=1,C_PROBE541_TYPE=1,C_PROBE542_TYPE=1,C_PROBE543_TYPE=1,C_PROBE544_TYPE=1,C_PROBE545_TYPE=1,C_PROBE546_TYPE=1,C_PROBE547_TYPE=1,C_PROBE548_TYPE=1,C_PROBE549_TYPE=1,C_PROBE550_TYPE=1,C_PROBE551_TYPE=1,C_PROBE552_TYPE=1,C_PROBE553_TYPE=1,C_PROBE554_TYPE=1,C_PROBE555_TYPE=1,C_PROBE556_TYPE=1,C_PROBE557_TYPE=1,C_PROBE558_TYPE=1,C_PROBE559_TYPE=1,C_PROBE560_TYPE=1,C_PROBE561_TYPE=1,C_PROBE562_TYPE=1,C_PROBE563_TYPE=1,C_PROBE564_TYPE=1,C_PROBE565_TYPE=1,C_PROBE566_TYPE=1,C_PROBE567_TYPE=1,C_PROBE568_TYPE=1,C_PROBE569_TYPE=1,C_PROBE570_TYPE=1,C_PROBE571_TYPE=1,C_PROBE572_TYPE=1,C_PROBE573_TYPE=1,C_PROBE574_TYPE=1,C_PROBE575_TYPE=1,C_PROBE576_TYPE=1,C_PROBE577_TYPE=1,C_PROBE578_TYPE=1,C_PROBE579_TYPE=1,C_PROBE580_TYPE=1,C_PROBE581_TYPE=1,C_PROBE582_TYPE=1,C_PROBE583_TYPE=1,C_PROBE584_TYPE=1,C_PROBE585_TYPE=1,C_PROBE586_TYPE=1,C_PROBE587_TYPE=1,C_PROBE588_TYPE=1,C_PROBE589_TYPE=1,C_PROBE590_TYPE=1,C_PROBE591_TYPE=1,C_PROBE592_TYPE=1,C_PROBE593_TYPE=1,C_PROBE594_TYPE=1,C_PROBE595_TYPE=1,C_PROBE596_TYPE=1,C_PROBE597_TYPE=1,C_PROBE598_TYPE=1,C_PROBE599_TYPE=1,C_PROBE600_TYPE=1,C_PROBE601_TYPE=1,C_PROBE602_TYPE=1,C_PROBE603_TYPE=1,C_PROBE604_TYPE=1,C_PROBE605_TYPE=1,\
C_PROBE606_TYPE=1,C_PROBE607_TYPE=1,C_PROBE608_TYPE=1,C_PROBE609_TYPE=1,C_PROBE610_TYPE=1,C_PROBE611_TYPE=1,C_PROBE612_TYPE=1,C_PROBE613_TYPE=1,C_PROBE614_TYPE=1,C_PROBE615_TYPE=1,C_PROBE616_TYPE=1,C_PROBE617_TYPE=1,C_PROBE618_TYPE=1,C_PROBE619_TYPE=1,C_PROBE620_TYPE=1,C_PROBE621_TYPE=1,C_PROBE622_TYPE=1,C_PROBE623_TYPE=1,C_PROBE624_TYPE=1,C_PROBE625_TYPE=1,C_PROBE626_TYPE=1,C_PROBE627_TYPE=1,C_PROBE628_TYPE=1,C_PROBE629_TYPE=1,C_PROBE630_TYPE=1,C_PROBE631_TYPE=1,C_PROBE632_TYPE=1,C_PROBE633_TYPE=1,C_PROBE634_TYPE=1,C_PROBE635_TYPE=1,C_PROBE636_TYPE=1,C_PROBE637_TYPE=1,C_PROBE638_TYPE=1,C_PROBE639_TYPE=1,C_PROBE640_TYPE=1,C_PROBE641_TYPE=1,C_PROBE642_TYPE=1,C_PROBE643_TYPE=1,C_PROBE644_TYPE=1,C_PROBE645_TYPE=1,C_PROBE646_TYPE=1,C_PROBE647_TYPE=1,C_PROBE648_TYPE=1,C_PROBE649_TYPE=1,C_PROBE650_TYPE=1,C_PROBE651_TYPE=1,C_PROBE652_TYPE=1,C_PROBE653_TYPE=1,C_PROBE654_TYPE=1,C_PROBE655_TYPE=1,C_PROBE656_TYPE=1,C_PROBE657_TYPE=1,C_PROBE658_TYPE=1,C_PROBE659_TYPE=1,C_PROBE660_TYPE=1,C_PROBE661_TYPE=1,C_PROBE662_TYPE=1,C_PROBE663_TYPE=1,C_PROBE664_TYPE=1,C_PROBE665_TYPE=1,C_PROBE666_TYPE=1,C_PROBE667_TYPE=1,C_PROBE668_TYPE=1,C_PROBE669_TYPE=1,C_PROBE670_TYPE=1,C_PROBE671_TYPE=1,C_PROBE672_TYPE=1,C_PROBE673_TYPE=1,C_PROBE674_TYPE=1,C_PROBE675_TYPE=1,C_PROBE676_TYPE=1,C_PROBE677_TYPE=1,C_PROBE678_TYPE=1,C_PROBE679_TYPE=1,C_PROBE680_TYPE=1,C_PROBE681_TYPE=1,C_PROBE682_TYPE=1,C_PROBE683_TYPE=1,C_PROBE684_TYPE=1,C_PROBE685_TYPE=1,C_PROBE686_TYPE=1,C_PROBE687_TYPE=1,C_PROBE688_TYPE=1,C_PROBE689_TYPE=1,C_PROBE690_TYPE=1,C_PROBE691_TYPE=1,C_PROBE692_TYPE=1,C_PROBE693_TYPE=1,C_PROBE694_TYPE=1,C_PROBE695_TYPE=1,C_PROBE696_TYPE=1,C_PROBE697_TYPE=1,C_PROBE698_TYPE=1,C_PROBE699_TYPE=1,C_PROBE700_TYPE=1,C_PROBE701_TYPE=1,C_PROBE702_TYPE=1,C_PROBE703_TYPE=1,C_PROBE704_TYPE=1,C_PROBE705_TYPE=1,\
C_PROBE706_TYPE=1,C_PROBE707_TYPE=1,C_PROBE708_TYPE=1,C_PROBE709_TYPE=1,C_PROBE710_TYPE=1,C_PROBE711_TYPE=1,C_PROBE712_TYPE=1,C_PROBE713_TYPE=1,C_PROBE714_TYPE=1,C_PROBE715_TYPE=1,C_PROBE716_TYPE=1,C_PROBE717_TYPE=1,C_PROBE718_TYPE=1,C_PROBE719_TYPE=1,C_PROBE720_TYPE=1,C_PROBE721_TYPE=1,C_PROBE722_TYPE=1,C_PROBE723_TYPE=1,C_PROBE724_TYPE=1,C_PROBE725_TYPE=1,C_PROBE726_TYPE=1,C_PROBE727_TYPE=1,C_PROBE728_TYPE=1,C_PROBE729_TYPE=1,C_PROBE730_TYPE=1,C_PROBE731_TYPE=1,C_PROBE732_TYPE=1,C_PROBE733_TYPE=1,C_PROBE734_TYPE=1,C_PROBE735_TYPE=1,C_PROBE736_TYPE=1,C_PROBE737_TYPE=1,C_PROBE738_TYPE=1,C_PROBE739_TYPE=1,C_PROBE740_TYPE=1,C_PROBE741_TYPE=1,C_PROBE742_TYPE=1,C_PROBE743_TYPE=1,C_PROBE744_TYPE=1,C_PROBE745_TYPE=1,C_PROBE746_TYPE=1,C_PROBE747_TYPE=1,C_PROBE748_TYPE=1,C_PROBE749_TYPE=1,C_PROBE750_TYPE=1,C_PROBE751_TYPE=1,C_PROBE752_TYPE=1,C_PROBE753_TYPE=1,C_PROBE754_TYPE=1,C_PROBE755_TYPE=1,C_PROBE756_TYPE=1,C_PROBE757_TYPE=1,C_PROBE758_TYPE=1,C_PROBE759_TYPE=1,C_PROBE760_TYPE=1,C_PROBE761_TYPE=1,C_PROBE762_TYPE=1,C_PROBE763_TYPE=1,C_PROBE764_TYPE=1,C_PROBE765_TYPE=1,C_PROBE766_TYPE=1,C_PROBE767_TYPE=1,C_PROBE768_TYPE=1,C_PROBE769_TYPE=1,C_PROBE770_TYPE=1,C_PROBE771_TYPE=1,C_PROBE772_TYPE=1,C_PROBE773_TYPE=1,C_PROBE774_TYPE=1,C_PROBE775_TYPE=1,C_PROBE776_TYPE=1,C_PROBE777_TYPE=1,C_PROBE778_TYPE=1,C_PROBE779_TYPE=1,C_PROBE780_TYPE=1,C_PROBE781_TYPE=1,C_PROBE782_TYPE=1,C_PROBE783_TYPE=1,C_PROBE784_TYPE=1,C_PROBE785_TYPE=1,C_PROBE786_TYPE=1,C_PROBE787_TYPE=1,C_PROBE788_TYPE=1,C_PROBE789_TYPE=1,C_PROBE790_TYPE=1,C_PROBE791_TYPE=1,C_PROBE792_TYPE=1,C_PROBE793_TYPE=1,C_PROBE794_TYPE=1,C_PROBE795_TYPE=1,C_PROBE796_TYPE=1,C_PROBE797_TYPE=1,C_PROBE798_TYPE=1,C_PROBE799_TYPE=1,C_PROBE800_TYPE=1,C_PROBE801_TYPE=1,C_PROBE802_TYPE=1,C_PROBE803_TYPE=1,C_PROBE804_TYPE=1,C_PROBE805_TYPE=1,\
C_PROBE806_TYPE=1,C_PROBE807_TYPE=1,C_PROBE808_TYPE=1,C_PROBE809_TYPE=1,C_PROBE810_TYPE=1,C_PROBE811_TYPE=1,C_PROBE812_TYPE=1,C_PROBE813_TYPE=1,C_PROBE814_TYPE=1,C_PROBE815_TYPE=1,C_PROBE816_TYPE=1,C_PROBE817_TYPE=1,C_PROBE818_TYPE=1,C_PROBE819_TYPE=1,C_PROBE820_TYPE=1,C_PROBE821_TYPE=1,C_PROBE822_TYPE=1,C_PROBE823_TYPE=1,C_PROBE824_TYPE=1,C_PROBE825_TYPE=1,C_PROBE826_TYPE=1,C_PROBE827_TYPE=1,C_PROBE828_TYPE=1,C_PROBE829_TYPE=1,C_PROBE830_TYPE=1,C_PROBE831_TYPE=1,C_PROBE832_TYPE=1,C_PROBE833_TYPE=1,C_PROBE834_TYPE=1,C_PROBE835_TYPE=1,C_PROBE836_TYPE=1,C_PROBE837_TYPE=1,C_PROBE838_TYPE=1,C_PROBE839_TYPE=1,C_PROBE840_TYPE=1,C_PROBE841_TYPE=1,C_PROBE842_TYPE=1,C_PROBE843_TYPE=1,C_PROBE844_TYPE=1,C_PROBE845_TYPE=1,C_PROBE846_TYPE=1,C_PROBE847_TYPE=1,C_PROBE848_TYPE=1,C_PROBE849_TYPE=1,C_PROBE850_TYPE=1,C_PROBE851_TYPE=1,C_PROBE852_TYPE=1,C_PROBE853_TYPE=1,C_PROBE854_TYPE=1,C_PROBE855_TYPE=1,C_PROBE856_TYPE=1,C_PROBE857_TYPE=1,C_PROBE858_TYPE=1,C_PROBE859_TYPE=1,C_PROBE860_TYPE=1,C_PROBE861_TYPE=1,C_PROBE862_TYPE=1,C_PROBE863_TYPE=1,C_PROBE864_TYPE=1,C_PROBE865_TYPE=1,C_PROBE866_TYPE=1,C_PROBE867_TYPE=1,C_PROBE868_TYPE=1,C_PROBE869_TYPE=1,C_PROBE870_TYPE=1,C_PROBE871_TYPE=1,C_PROBE872_TYPE=1,C_PROBE873_TYPE=1,C_PROBE874_TYPE=1,C_PROBE875_TYPE=1,C_PROBE876_TYPE=1,C_PROBE877_TYPE=1,C_PROBE878_TYPE=1,C_PROBE879_TYPE=1,C_PROBE880_TYPE=1,C_PROBE881_TYPE=1,C_PROBE882_TYPE=1,C_PROBE883_TYPE=1,C_PROBE884_TYPE=1,C_PROBE885_TYPE=1,C_PROBE886_TYPE=1,C_PROBE887_TYPE=1,C_PROBE888_TYPE=1,C_PROBE889_TYPE=1,C_PROBE890_TYPE=1,C_PROBE891_TYPE=1,C_PROBE892_TYPE=1,C_PROBE893_TYPE=1,C_PROBE894_TYPE=1,C_PROBE895_TYPE=1,C_PROBE896_TYPE=1,C_PROBE897_TYPE=1,C_PROBE898_TYPE=1,C_PROBE899_TYPE=1,C_PROBE900_TYPE=1,C_PROBE901_TYPE=1,C_PROBE902_TYPE=1,C_PROBE903_TYPE=1,C_PROBE904_TYPE=1,C_PROBE905_TYPE=1,\
C_PROBE906_TYPE=1,C_PROBE907_TYPE=1,C_PROBE908_TYPE=1,C_PROBE909_TYPE=1,C_PROBE910_TYPE=1,C_PROBE911_TYPE=1,C_PROBE912_TYPE=1,C_PROBE913_TYPE=1,C_PROBE914_TYPE=1,C_PROBE915_TYPE=1,C_PROBE916_TYPE=1,C_PROBE917_TYPE=1,C_PROBE918_TYPE=1,C_PROBE919_TYPE=1,C_PROBE920_TYPE=1,C_PROBE921_TYPE=1,C_PROBE922_TYPE=1,C_PROBE923_TYPE=1,C_PROBE924_TYPE=1,C_PROBE925_TYPE=1,C_PROBE926_TYPE=1,C_PROBE927_TYPE=1,C_PROBE928_TYPE=1,C_PROBE929_TYPE=1,C_PROBE930_TYPE=1,C_PROBE931_TYPE=1,C_PROBE932_TYPE=1,C_PROBE933_TYPE=1,C_PROBE934_TYPE=1,C_PROBE935_TYPE=1,C_PROBE936_TYPE=1,C_PROBE937_TYPE=1,C_PROBE938_TYPE=1,C_PROBE939_TYPE=1,C_PROBE940_TYPE=1,C_PROBE941_TYPE=1,C_PROBE942_TYPE=1,C_PROBE943_TYPE=1,C_PROBE944_TYPE=1,C_PROBE945_TYPE=1,C_PROBE946_TYPE=1,C_PROBE947_TYPE=1,C_PROBE948_TYPE=1,C_PROBE949_TYPE=1,C_PROBE950_TYPE=1,C_PROBE951_TYPE=1,C_PROBE952_TYPE=1,C_PROBE953_TYPE=1,C_PROBE954_TYPE=1,C_PROBE955_TYPE=1,C_PROBE956_TYPE=1,C_PROBE957_TYPE=1,C_PROBE958_TYPE=1,C_PROBE959_TYPE=1,C_PROBE960_TYPE=1,C_PROBE961_TYPE=1,C_PROBE962_TYPE=1,C_PROBE963_TYPE=1,C_PROBE964_TYPE=1,C_PROBE965_TYPE=1,C_PROBE966_TYPE=1,C_PROBE967_TYPE=1,C_PROBE968_TYPE=1,C_PROBE969_TYPE=1,C_PROBE970_TYPE=1,C_PROBE971_TYPE=1,C_PROBE972_TYPE=1,C_PROBE973_TYPE=1,C_PROBE974_TYPE=1,C_PROBE975_TYPE=1,C_PROBE976_TYPE=1,C_PROBE977_TYPE=1,C_PROBE978_TYPE=1,C_PROBE979_TYPE=1,C_PROBE980_TYPE=1,C_PROBE981_TYPE=1,C_PROBE982_TYPE=1,C_PROBE983_TYPE=1,C_PROBE984_TYPE=1,C_PROBE985_TYPE=1,C_PROBE986_TYPE=1,C_PROBE987_TYPE=1,C_PROBE988_TYPE=1,C_PROBE989_TYPE=1,C_PROBE990_TYPE=1,C_PROBE991_TYPE=1,C_PROBE992_TYPE=1,C_PROBE993_TYPE=1,C_PROBE994_TYPE=1,C_PROBE995_TYPE=1,C_PROBE996_TYPE=1,C_PROBE997_TYPE=1,C_PROBE998_TYPE=1,C_PROBE999_TYPE=1,C_PROBE1000_TYPE=1,C_PROBE1001_TYPE=1,C_PROBE1002_TYPE=1,C_PROBE1003_TYPE=1,C_PROBE1004_TYPE=1,C_PROBE1005_TYPE=1,\
C_PROBE1006_TYPE=1,C_PROBE1007_TYPE=1,C_PROBE1008_TYPE=1,C_PROBE1009_TYPE=1,C_PROBE1010_TYPE=1,C_PROBE1011_TYPE=1,C_PROBE1012_TYPE=1,C_PROBE1013_TYPE=1,C_PROBE1014_TYPE=1,C_PROBE1015_TYPE=1,C_PROBE1016_TYPE=1,C_PROBE1017_TYPE=1,C_PROBE1018_TYPE=1,C_PROBE1019_TYPE=1,C_PROBE1020_TYPE=1,C_PROBE1021_TYPE=1,C_PROBE1022_TYPE=1,C_PROBE1023_TYPE=1}" *)
module ila_0 (
clk,
probe0,
probe1,
probe2,
probe3,
probe4,
probe5,
probe6,
probe7,
probe8,
probe9,
probe10,
probe11,
probe12,
probe13,
probe14,
probe15,
probe16,
probe17,
probe18,
probe19,
probe20
);
input clk;
input [63 : 0] probe0;
input [63 : 0] probe1;
input [0 : 0] probe2;
input [0 : 0] probe3;
input [0 : 0] probe4;
input [0 : 0] probe5;
input [0 : 0] probe6;
input [63 : 0] probe7;
input [0 : 0] probe8;
input [0 : 0] probe9;
input [0 : 0] probe10;
input [0 : 0] probe11;
input [63 : 0] probe12;
input [0 : 0] probe13;
input [0 : 0] probe14;
input [0 : 0] probe15;
input [0 : 0] probe16;
input [0 : 0] probe17;
input [7 : 0] probe18;
input [7 : 0] probe19;
input [0 : 0] probe20;
wire [16:0] sl_oport0;
wire [36:0] sl_iport0;
ila_v6_2_0_ila #(
.C_XLNX_HW_PROBE_INFO("DEFAULT"),
.C_XDEVICEFAMILY("kintex7"),
.C_CORE_TYPE(1),
.C_CORE_INFO1(0),
.C_CORE_INFO2(0),
.C_CAPTURE_TYPE(0),
.C_MU_TYPE(0),
.C_TC_TYPE(0),
.C_NUM_OF_PROBES(21),
.C_DATA_DEPTH(2048),
.C_MAJOR_VERSION(2016),
.C_MINOR_VERSION(3),
.C_BUILD_REVISION(0),
.C_CORE_MAJOR_VER(6),
.C_CORE_MINOR_VER(2),
.C_XSDB_SLAVE_TYPE(17),
.C_NEXT_SLAVE(0),
.C_CSE_DRV_VER(2),
.C_USE_TEST_REG(1),
.C_PIPE_IFACE(1),
.C_RAM_STYLE("SUBCORE"),
.C_TRIGOUT_EN(0),
.C_TRIGIN_EN(0),
.C_ADV_TRIGGER(0),
.C_EN_DDR_ILA(0),
.C_DDR_CLK_GEN(0),
.C_CLK_FREQ(200),
.C_CLK_PERIOD(5.0),
.C_CLKFBOUT_MULT_F(10),
.C_DIVCLK_DIVIDE(3),
.C_CLKOUT0_DIVIDE_F(10),
.C_EN_STRG_QUAL(0),
.C_INPUT_PIPE_STAGES(0),
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.C_PROBE985_WIDTH(1),
.C_PROBE986_WIDTH(1),
.C_PROBE987_WIDTH(1),
.C_PROBE988_WIDTH(1),
.C_PROBE989_WIDTH(1),
.C_PROBE990_WIDTH(1),
.C_PROBE991_WIDTH(1),
.C_PROBE992_WIDTH(1),
.C_PROBE993_WIDTH(1),
.C_PROBE994_WIDTH(1),
.C_PROBE995_WIDTH(1),
.C_PROBE996_WIDTH(1),
.C_PROBE997_WIDTH(1),
.C_PROBE998_WIDTH(1),
.C_PROBE999_WIDTH(1),
.C_PROBE1000_WIDTH(1),
.C_PROBE1001_WIDTH(1),
.C_PROBE1002_WIDTH(1),
.C_PROBE1003_WIDTH(1),
.C_PROBE1004_WIDTH(1),
.C_PROBE1005_WIDTH(1),
.C_PROBE1006_WIDTH(1),
.C_PROBE1007_WIDTH(1),
.C_PROBE1008_WIDTH(1),
.C_PROBE1009_WIDTH(1),
.C_PROBE1010_WIDTH(1),
.C_PROBE1011_WIDTH(1),
.C_PROBE1012_WIDTH(1),
.C_PROBE1013_WIDTH(1),
.C_PROBE1014_WIDTH(1),
.C_PROBE1015_WIDTH(1),
.C_PROBE1016_WIDTH(1),
.C_PROBE1017_WIDTH(1),
.C_PROBE1018_WIDTH(1),
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.C_PROBE1020_WIDTH(1),
.C_PROBE1021_WIDTH(1),
.C_PROBE1022_WIDTH(1),
.C_PROBE1023_WIDTH(1),
.C_PROBE0_MU_CNT(1),
.C_PROBE1_MU_CNT(1),
.C_PROBE2_MU_CNT(1),
.C_PROBE3_MU_CNT(1),
.C_PROBE4_MU_CNT(1),
.C_PROBE5_MU_CNT(1),
.C_PROBE6_MU_CNT(1),
.C_PROBE7_MU_CNT(1),
.C_PROBE8_MU_CNT(1),
.C_PROBE9_MU_CNT(1),
.C_PROBE10_MU_CNT(1),
.C_PROBE11_MU_CNT(1),
.C_PROBE12_MU_CNT(1),
.C_PROBE13_MU_CNT(1),
.C_PROBE14_MU_CNT(1),
.C_PROBE15_MU_CNT(1),
.C_PROBE16_MU_CNT(1),
.C_PROBE17_MU_CNT(1),
.C_PROBE18_MU_CNT(1),
.C_PROBE19_MU_CNT(1),
.C_PROBE20_MU_CNT(1),
.C_PROBE21_MU_CNT(1),
.C_PROBE22_MU_CNT(1),
.C_PROBE23_MU_CNT(1),
.C_PROBE24_MU_CNT(1),
.C_PROBE25_MU_CNT(1),
.C_PROBE26_MU_CNT(1),
.C_PROBE27_MU_CNT(1),
.C_PROBE28_MU_CNT(1),
.C_PROBE29_MU_CNT(1),
.C_PROBE30_MU_CNT(1),
.C_PROBE31_MU_CNT(1),
.C_PROBE32_MU_CNT(1),
.C_PROBE33_MU_CNT(1),
.C_PROBE34_MU_CNT(1),
.C_PROBE35_MU_CNT(1),
.C_PROBE36_MU_CNT(1),
.C_PROBE37_MU_CNT(1),
.C_PROBE38_MU_CNT(1),
.C_PROBE39_MU_CNT(1),
.C_PROBE40_MU_CNT(1),
.C_PROBE41_MU_CNT(1),
.C_PROBE42_MU_CNT(1),
.C_PROBE43_MU_CNT(1),
.C_PROBE44_MU_CNT(1),
.C_PROBE45_MU_CNT(1),
.C_PROBE46_MU_CNT(1),
.C_PROBE47_MU_CNT(1),
.C_PROBE48_MU_CNT(1),
.C_PROBE49_MU_CNT(1),
.C_PROBE50_MU_CNT(1),
.C_PROBE51_MU_CNT(1),
.C_PROBE52_MU_CNT(1),
.C_PROBE53_MU_CNT(1),
.C_PROBE54_MU_CNT(1),
.C_PROBE55_MU_CNT(1),
.C_PROBE56_MU_CNT(1),
.C_PROBE57_MU_CNT(1),
.C_PROBE58_MU_CNT(1),
.C_PROBE59_MU_CNT(1),
.C_PROBE60_MU_CNT(1),
.C_PROBE61_MU_CNT(1),
.C_PROBE62_MU_CNT(1),
.C_PROBE63_MU_CNT(1),
.C_PROBE64_MU_CNT(1),
.C_PROBE65_MU_CNT(1),
.C_PROBE66_MU_CNT(1),
.C_PROBE67_MU_CNT(1),
.C_PROBE68_MU_CNT(1),
.C_PROBE69_MU_CNT(1),
.C_PROBE70_MU_CNT(1),
.C_PROBE71_MU_CNT(1),
.C_PROBE72_MU_CNT(1),
.C_PROBE73_MU_CNT(1),
.C_PROBE74_MU_CNT(1),
.C_PROBE75_MU_CNT(1),
.C_PROBE76_MU_CNT(1),
.C_PROBE77_MU_CNT(1),
.C_PROBE78_MU_CNT(1),
.C_PROBE79_MU_CNT(1),
.C_PROBE80_MU_CNT(1),
.C_PROBE81_MU_CNT(1),
.C_PROBE82_MU_CNT(1),
.C_PROBE83_MU_CNT(1),
.C_PROBE84_MU_CNT(1),
.C_PROBE85_MU_CNT(1),
.C_PROBE86_MU_CNT(1),
.C_PROBE87_MU_CNT(1),
.C_PROBE88_MU_CNT(1),
.C_PROBE89_MU_CNT(1),
.C_PROBE90_MU_CNT(1),
.C_PROBE91_MU_CNT(1),
.C_PROBE92_MU_CNT(1),
.C_PROBE93_MU_CNT(1),
.C_PROBE94_MU_CNT(1),
.C_PROBE95_MU_CNT(1),
.C_PROBE96_MU_CNT(1),
.C_PROBE97_MU_CNT(1),
.C_PROBE98_MU_CNT(1),
.C_PROBE99_MU_CNT(1),
.C_PROBE100_MU_CNT(1),
.C_PROBE101_MU_CNT(1),
.C_PROBE102_MU_CNT(1),
.C_PROBE103_MU_CNT(1),
.C_PROBE104_MU_CNT(1),
.C_PROBE105_MU_CNT(1),
.C_PROBE106_MU_CNT(1),
.C_PROBE107_MU_CNT(1),
.C_PROBE108_MU_CNT(1),
.C_PROBE109_MU_CNT(1),
.C_PROBE110_MU_CNT(1),
.C_PROBE111_MU_CNT(1),
.C_PROBE112_MU_CNT(1),
.C_PROBE113_MU_CNT(1),
.C_PROBE114_MU_CNT(1),
.C_PROBE115_MU_CNT(1),
.C_PROBE116_MU_CNT(1),
.C_PROBE117_MU_CNT(1),
.C_PROBE118_MU_CNT(1),
.C_PROBE119_MU_CNT(1),
.C_PROBE120_MU_CNT(1),
.C_PROBE121_MU_CNT(1),
.C_PROBE122_MU_CNT(1),
.C_PROBE123_MU_CNT(1),
.C_PROBE124_MU_CNT(1),
.C_PROBE125_MU_CNT(1),
.C_PROBE126_MU_CNT(1),
.C_PROBE127_MU_CNT(1),
.C_PROBE128_MU_CNT(1),
.C_PROBE129_MU_CNT(1),
.C_PROBE130_MU_CNT(1),
.C_PROBE131_MU_CNT(1),
.C_PROBE132_MU_CNT(1),
.C_PROBE133_MU_CNT(1),
.C_PROBE134_MU_CNT(1),
.C_PROBE135_MU_CNT(1),
.C_PROBE136_MU_CNT(1),
.C_PROBE137_MU_CNT(1),
.C_PROBE138_MU_CNT(1),
.C_PROBE139_MU_CNT(1),
.C_PROBE140_MU_CNT(1),
.C_PROBE141_MU_CNT(1),
.C_PROBE142_MU_CNT(1),
.C_PROBE143_MU_CNT(1),
.C_PROBE144_MU_CNT(1),
.C_PROBE145_MU_CNT(1),
.C_PROBE146_MU_CNT(1),
.C_PROBE147_MU_CNT(1),
.C_PROBE148_MU_CNT(1),
.C_PROBE149_MU_CNT(1),
.C_PROBE150_MU_CNT(1),
.C_PROBE151_MU_CNT(1),
.C_PROBE152_MU_CNT(1),
.C_PROBE153_MU_CNT(1),
.C_PROBE154_MU_CNT(1),
.C_PROBE155_MU_CNT(1),
.C_PROBE156_MU_CNT(1),
.C_PROBE157_MU_CNT(1),
.C_PROBE158_MU_CNT(1),
.C_PROBE159_MU_CNT(1),
.C_PROBE160_MU_CNT(1),
.C_PROBE161_MU_CNT(1),
.C_PROBE162_MU_CNT(1),
.C_PROBE163_MU_CNT(1),
.C_PROBE164_MU_CNT(1),
.C_PROBE165_MU_CNT(1),
.C_PROBE166_MU_CNT(1),
.C_PROBE167_MU_CNT(1),
.C_PROBE168_MU_CNT(1),
.C_PROBE169_MU_CNT(1),
.C_PROBE170_MU_CNT(1),
.C_PROBE171_MU_CNT(1),
.C_PROBE172_MU_CNT(1),
.C_PROBE173_MU_CNT(1),
.C_PROBE174_MU_CNT(1),
.C_PROBE175_MU_CNT(1),
.C_PROBE176_MU_CNT(1),
.C_PROBE177_MU_CNT(1),
.C_PROBE178_MU_CNT(1),
.C_PROBE179_MU_CNT(1),
.C_PROBE180_MU_CNT(1),
.C_PROBE181_MU_CNT(1),
.C_PROBE182_MU_CNT(1),
.C_PROBE183_MU_CNT(1),
.C_PROBE184_MU_CNT(1),
.C_PROBE185_MU_CNT(1),
.C_PROBE186_MU_CNT(1),
.C_PROBE187_MU_CNT(1),
.C_PROBE188_MU_CNT(1),
.C_PROBE189_MU_CNT(1),
.C_PROBE190_MU_CNT(1),
.C_PROBE191_MU_CNT(1),
.C_PROBE192_MU_CNT(1),
.C_PROBE193_MU_CNT(1),
.C_PROBE194_MU_CNT(1),
.C_PROBE195_MU_CNT(1),
.C_PROBE196_MU_CNT(1),
.C_PROBE197_MU_CNT(1),
.C_PROBE198_MU_CNT(1),
.C_PROBE199_MU_CNT(1),
.C_PROBE200_MU_CNT(1),
.C_PROBE201_MU_CNT(1),
.C_PROBE202_MU_CNT(1),
.C_PROBE203_MU_CNT(1),
.C_PROBE204_MU_CNT(1),
.C_PROBE205_MU_CNT(1),
.C_PROBE206_MU_CNT(1),
.C_PROBE207_MU_CNT(1),
.C_PROBE208_MU_CNT(1),
.C_PROBE209_MU_CNT(1),
.C_PROBE210_MU_CNT(1),
.C_PROBE211_MU_CNT(1),
.C_PROBE212_MU_CNT(1),
.C_PROBE213_MU_CNT(1),
.C_PROBE214_MU_CNT(1),
.C_PROBE215_MU_CNT(1),
.C_PROBE216_MU_CNT(1),
.C_PROBE217_MU_CNT(1),
.C_PROBE218_MU_CNT(1),
.C_PROBE219_MU_CNT(1),
.C_PROBE220_MU_CNT(1),
.C_PROBE221_MU_CNT(1),
.C_PROBE222_MU_CNT(1),
.C_PROBE223_MU_CNT(1),
.C_PROBE224_MU_CNT(1),
.C_PROBE225_MU_CNT(1),
.C_PROBE226_MU_CNT(1),
.C_PROBE227_MU_CNT(1),
.C_PROBE228_MU_CNT(1),
.C_PROBE229_MU_CNT(1),
.C_PROBE230_MU_CNT(1),
.C_PROBE231_MU_CNT(1),
.C_PROBE232_MU_CNT(1),
.C_PROBE233_MU_CNT(1),
.C_PROBE234_MU_CNT(1),
.C_PROBE235_MU_CNT(1),
.C_PROBE236_MU_CNT(1),
.C_PROBE237_MU_CNT(1),
.C_PROBE238_MU_CNT(1),
.C_PROBE239_MU_CNT(1),
.C_PROBE240_MU_CNT(1),
.C_PROBE241_MU_CNT(1),
.C_PROBE242_MU_CNT(1),
.C_PROBE243_MU_CNT(1),
.C_PROBE244_MU_CNT(1),
.C_PROBE245_MU_CNT(1),
.C_PROBE246_MU_CNT(1),
.C_PROBE247_MU_CNT(1),
.C_PROBE248_MU_CNT(1),
.C_PROBE249_MU_CNT(1),
.C_PROBE250_MU_CNT(1),
.C_PROBE251_MU_CNT(1),
.C_PROBE252_MU_CNT(1),
.C_PROBE253_MU_CNT(1),
.C_PROBE254_MU_CNT(1),
.C_PROBE255_MU_CNT(1),
.C_PROBE256_MU_CNT(1),
.C_PROBE257_MU_CNT(1),
.C_PROBE258_MU_CNT(1),
.C_PROBE259_MU_CNT(1),
.C_PROBE260_MU_CNT(1),
.C_PROBE261_MU_CNT(1),
.C_PROBE262_MU_CNT(1),
.C_PROBE263_MU_CNT(1),
.C_PROBE264_MU_CNT(1),
.C_PROBE265_MU_CNT(1),
.C_PROBE266_MU_CNT(1),
.C_PROBE267_MU_CNT(1),
.C_PROBE268_MU_CNT(1),
.C_PROBE269_MU_CNT(1),
.C_PROBE270_MU_CNT(1),
.C_PROBE271_MU_CNT(1),
.C_PROBE272_MU_CNT(1),
.C_PROBE273_MU_CNT(1),
.C_PROBE274_MU_CNT(1),
.C_PROBE275_MU_CNT(1),
.C_PROBE276_MU_CNT(1),
.C_PROBE277_MU_CNT(1),
.C_PROBE278_MU_CNT(1),
.C_PROBE279_MU_CNT(1),
.C_PROBE280_MU_CNT(1),
.C_PROBE281_MU_CNT(1),
.C_PROBE282_MU_CNT(1),
.C_PROBE283_MU_CNT(1),
.C_PROBE284_MU_CNT(1),
.C_PROBE285_MU_CNT(1),
.C_PROBE286_MU_CNT(1),
.C_PROBE287_MU_CNT(1),
.C_PROBE288_MU_CNT(1),
.C_PROBE289_MU_CNT(1),
.C_PROBE290_MU_CNT(1),
.C_PROBE291_MU_CNT(1),
.C_PROBE292_MU_CNT(1),
.C_PROBE293_MU_CNT(1),
.C_PROBE294_MU_CNT(1),
.C_PROBE295_MU_CNT(1),
.C_PROBE296_MU_CNT(1),
.C_PROBE297_MU_CNT(1),
.C_PROBE298_MU_CNT(1),
.C_PROBE299_MU_CNT(1),
.C_PROBE300_MU_CNT(1),
.C_PROBE301_MU_CNT(1),
.C_PROBE302_MU_CNT(1),
.C_PROBE303_MU_CNT(1),
.C_PROBE304_MU_CNT(1),
.C_PROBE305_MU_CNT(1),
.C_PROBE306_MU_CNT(1),
.C_PROBE307_MU_CNT(1),
.C_PROBE308_MU_CNT(1),
.C_PROBE309_MU_CNT(1),
.C_PROBE310_MU_CNT(1),
.C_PROBE311_MU_CNT(1),
.C_PROBE312_MU_CNT(1),
.C_PROBE313_MU_CNT(1),
.C_PROBE314_MU_CNT(1),
.C_PROBE315_MU_CNT(1),
.C_PROBE316_MU_CNT(1),
.C_PROBE317_MU_CNT(1),
.C_PROBE318_MU_CNT(1),
.C_PROBE319_MU_CNT(1),
.C_PROBE320_MU_CNT(1),
.C_PROBE321_MU_CNT(1),
.C_PROBE322_MU_CNT(1),
.C_PROBE323_MU_CNT(1),
.C_PROBE324_MU_CNT(1),
.C_PROBE325_MU_CNT(1),
.C_PROBE326_MU_CNT(1),
.C_PROBE327_MU_CNT(1),
.C_PROBE328_MU_CNT(1),
.C_PROBE329_MU_CNT(1),
.C_PROBE330_MU_CNT(1),
.C_PROBE331_MU_CNT(1),
.C_PROBE332_MU_CNT(1),
.C_PROBE333_MU_CNT(1),
.C_PROBE334_MU_CNT(1),
.C_PROBE335_MU_CNT(1),
.C_PROBE336_MU_CNT(1),
.C_PROBE337_MU_CNT(1),
.C_PROBE338_MU_CNT(1),
.C_PROBE339_MU_CNT(1),
.C_PROBE340_MU_CNT(1),
.C_PROBE341_MU_CNT(1),
.C_PROBE342_MU_CNT(1),
.C_PROBE343_MU_CNT(1),
.C_PROBE344_MU_CNT(1),
.C_PROBE345_MU_CNT(1),
.C_PROBE346_MU_CNT(1),
.C_PROBE347_MU_CNT(1),
.C_PROBE348_MU_CNT(1),
.C_PROBE349_MU_CNT(1),
.C_PROBE350_MU_CNT(1),
.C_PROBE351_MU_CNT(1),
.C_PROBE352_MU_CNT(1),
.C_PROBE353_MU_CNT(1),
.C_PROBE354_MU_CNT(1),
.C_PROBE355_MU_CNT(1),
.C_PROBE356_MU_CNT(1),
.C_PROBE357_MU_CNT(1),
.C_PROBE358_MU_CNT(1),
.C_PROBE359_MU_CNT(1),
.C_PROBE360_MU_CNT(1),
.C_PROBE361_MU_CNT(1),
.C_PROBE362_MU_CNT(1),
.C_PROBE363_MU_CNT(1),
.C_PROBE364_MU_CNT(1),
.C_PROBE365_MU_CNT(1),
.C_PROBE366_MU_CNT(1),
.C_PROBE367_MU_CNT(1),
.C_PROBE368_MU_CNT(1),
.C_PROBE369_MU_CNT(1),
.C_PROBE370_MU_CNT(1),
.C_PROBE371_MU_CNT(1),
.C_PROBE372_MU_CNT(1),
.C_PROBE373_MU_CNT(1),
.C_PROBE374_MU_CNT(1),
.C_PROBE375_MU_CNT(1),
.C_PROBE376_MU_CNT(1),
.C_PROBE377_MU_CNT(1),
.C_PROBE378_MU_CNT(1),
.C_PROBE379_MU_CNT(1),
.C_PROBE380_MU_CNT(1),
.C_PROBE381_MU_CNT(1),
.C_PROBE382_MU_CNT(1),
.C_PROBE383_MU_CNT(1),
.C_PROBE384_MU_CNT(1),
.C_PROBE385_MU_CNT(1),
.C_PROBE386_MU_CNT(1),
.C_PROBE387_MU_CNT(1),
.C_PROBE388_MU_CNT(1),
.C_PROBE389_MU_CNT(1),
.C_PROBE390_MU_CNT(1),
.C_PROBE391_MU_CNT(1),
.C_PROBE392_MU_CNT(1),
.C_PROBE393_MU_CNT(1),
.C_PROBE394_MU_CNT(1),
.C_PROBE395_MU_CNT(1),
.C_PROBE396_MU_CNT(1),
.C_PROBE397_MU_CNT(1),
.C_PROBE398_MU_CNT(1),
.C_PROBE399_MU_CNT(1),
.C_PROBE400_MU_CNT(1),
.C_PROBE401_MU_CNT(1),
.C_PROBE402_MU_CNT(1),
.C_PROBE403_MU_CNT(1),
.C_PROBE404_MU_CNT(1),
.C_PROBE405_MU_CNT(1),
.C_PROBE406_MU_CNT(1),
.C_PROBE407_MU_CNT(1),
.C_PROBE408_MU_CNT(1),
.C_PROBE409_MU_CNT(1),
.C_PROBE410_MU_CNT(1),
.C_PROBE411_MU_CNT(1),
.C_PROBE412_MU_CNT(1),
.C_PROBE413_MU_CNT(1),
.C_PROBE414_MU_CNT(1),
.C_PROBE415_MU_CNT(1),
.C_PROBE416_MU_CNT(1),
.C_PROBE417_MU_CNT(1),
.C_PROBE418_MU_CNT(1),
.C_PROBE419_MU_CNT(1),
.C_PROBE420_MU_CNT(1),
.C_PROBE421_MU_CNT(1),
.C_PROBE422_MU_CNT(1),
.C_PROBE423_MU_CNT(1),
.C_PROBE424_MU_CNT(1),
.C_PROBE425_MU_CNT(1),
.C_PROBE426_MU_CNT(1),
.C_PROBE427_MU_CNT(1),
.C_PROBE428_MU_CNT(1),
.C_PROBE429_MU_CNT(1),
.C_PROBE430_MU_CNT(1),
.C_PROBE431_MU_CNT(1),
.C_PROBE432_MU_CNT(1),
.C_PROBE433_MU_CNT(1),
.C_PROBE434_MU_CNT(1),
.C_PROBE435_MU_CNT(1),
.C_PROBE436_MU_CNT(1),
.C_PROBE437_MU_CNT(1),
.C_PROBE438_MU_CNT(1),
.C_PROBE439_MU_CNT(1),
.C_PROBE440_MU_CNT(1),
.C_PROBE441_MU_CNT(1),
.C_PROBE442_MU_CNT(1),
.C_PROBE443_MU_CNT(1),
.C_PROBE444_MU_CNT(1),
.C_PROBE445_MU_CNT(1),
.C_PROBE446_MU_CNT(1),
.C_PROBE447_MU_CNT(1),
.C_PROBE448_MU_CNT(1),
.C_PROBE449_MU_CNT(1),
.C_PROBE450_MU_CNT(1),
.C_PROBE451_MU_CNT(1),
.C_PROBE452_MU_CNT(1),
.C_PROBE453_MU_CNT(1),
.C_PROBE454_MU_CNT(1),
.C_PROBE455_MU_CNT(1),
.C_PROBE456_MU_CNT(1),
.C_PROBE457_MU_CNT(1),
.C_PROBE458_MU_CNT(1),
.C_PROBE459_MU_CNT(1),
.C_PROBE460_MU_CNT(1),
.C_PROBE461_MU_CNT(1),
.C_PROBE462_MU_CNT(1),
.C_PROBE463_MU_CNT(1),
.C_PROBE464_MU_CNT(1),
.C_PROBE465_MU_CNT(1),
.C_PROBE466_MU_CNT(1),
.C_PROBE467_MU_CNT(1),
.C_PROBE468_MU_CNT(1),
.C_PROBE469_MU_CNT(1),
.C_PROBE470_MU_CNT(1),
.C_PROBE471_MU_CNT(1),
.C_PROBE472_MU_CNT(1),
.C_PROBE473_MU_CNT(1),
.C_PROBE474_MU_CNT(1),
.C_PROBE475_MU_CNT(1),
.C_PROBE476_MU_CNT(1),
.C_PROBE477_MU_CNT(1),
.C_PROBE478_MU_CNT(1),
.C_PROBE479_MU_CNT(1),
.C_PROBE480_MU_CNT(1),
.C_PROBE481_MU_CNT(1),
.C_PROBE482_MU_CNT(1),
.C_PROBE483_MU_CNT(1),
.C_PROBE484_MU_CNT(1),
.C_PROBE485_MU_CNT(1),
.C_PROBE486_MU_CNT(1),
.C_PROBE487_MU_CNT(1),
.C_PROBE488_MU_CNT(1),
.C_PROBE489_MU_CNT(1),
.C_PROBE490_MU_CNT(1),
.C_PROBE491_MU_CNT(1),
.C_PROBE492_MU_CNT(1),
.C_PROBE493_MU_CNT(1),
.C_PROBE494_MU_CNT(1),
.C_PROBE495_MU_CNT(1),
.C_PROBE496_MU_CNT(1),
.C_PROBE497_MU_CNT(1),
.C_PROBE498_MU_CNT(1),
.C_PROBE499_MU_CNT(1),
.C_PROBE500_MU_CNT(1),
.C_PROBE501_MU_CNT(1),
.C_PROBE502_MU_CNT(1),
.C_PROBE503_MU_CNT(1),
.C_PROBE504_MU_CNT(1),
.C_PROBE505_MU_CNT(1),
.C_PROBE506_MU_CNT(1),
.C_PROBE507_MU_CNT(1),
.C_PROBE508_MU_CNT(1),
.C_PROBE509_MU_CNT(1),
.C_PROBE510_MU_CNT(1),
.C_PROBE511_MU_CNT(1),
.C_PROBE512_MU_CNT(1),
.C_PROBE513_MU_CNT(1),
.C_PROBE514_MU_CNT(1),
.C_PROBE515_MU_CNT(1),
.C_PROBE516_MU_CNT(1),
.C_PROBE517_MU_CNT(1),
.C_PROBE518_MU_CNT(1),
.C_PROBE519_MU_CNT(1),
.C_PROBE520_MU_CNT(1),
.C_PROBE521_MU_CNT(1),
.C_PROBE522_MU_CNT(1),
.C_PROBE523_MU_CNT(1),
.C_PROBE524_MU_CNT(1),
.C_PROBE525_MU_CNT(1),
.C_PROBE526_MU_CNT(1),
.C_PROBE527_MU_CNT(1),
.C_PROBE528_MU_CNT(1),
.C_PROBE529_MU_CNT(1),
.C_PROBE530_MU_CNT(1),
.C_PROBE531_MU_CNT(1),
.C_PROBE532_MU_CNT(1),
.C_PROBE533_MU_CNT(1),
.C_PROBE534_MU_CNT(1),
.C_PROBE535_MU_CNT(1),
.C_PROBE536_MU_CNT(1),
.C_PROBE537_MU_CNT(1),
.C_PROBE538_MU_CNT(1),
.C_PROBE539_MU_CNT(1),
.C_PROBE540_MU_CNT(1),
.C_PROBE541_MU_CNT(1),
.C_PROBE542_MU_CNT(1),
.C_PROBE543_MU_CNT(1),
.C_PROBE544_MU_CNT(1),
.C_PROBE545_MU_CNT(1),
.C_PROBE546_MU_CNT(1),
.C_PROBE547_MU_CNT(1),
.C_PROBE548_MU_CNT(1),
.C_PROBE549_MU_CNT(1),
.C_PROBE550_MU_CNT(1),
.C_PROBE551_MU_CNT(1),
.C_PROBE552_MU_CNT(1),
.C_PROBE553_MU_CNT(1),
.C_PROBE554_MU_CNT(1),
.C_PROBE555_MU_CNT(1),
.C_PROBE556_MU_CNT(1),
.C_PROBE557_MU_CNT(1),
.C_PROBE558_MU_CNT(1),
.C_PROBE559_MU_CNT(1),
.C_PROBE560_MU_CNT(1),
.C_PROBE561_MU_CNT(1),
.C_PROBE562_MU_CNT(1),
.C_PROBE563_MU_CNT(1),
.C_PROBE564_MU_CNT(1),
.C_PROBE565_MU_CNT(1),
.C_PROBE566_MU_CNT(1),
.C_PROBE567_MU_CNT(1),
.C_PROBE568_MU_CNT(1),
.C_PROBE569_MU_CNT(1),
.C_PROBE570_MU_CNT(1),
.C_PROBE571_MU_CNT(1),
.C_PROBE572_MU_CNT(1),
.C_PROBE573_MU_CNT(1),
.C_PROBE574_MU_CNT(1),
.C_PROBE575_MU_CNT(1),
.C_PROBE576_MU_CNT(1),
.C_PROBE577_MU_CNT(1),
.C_PROBE578_MU_CNT(1),
.C_PROBE579_MU_CNT(1),
.C_PROBE580_MU_CNT(1),
.C_PROBE581_MU_CNT(1),
.C_PROBE582_MU_CNT(1),
.C_PROBE583_MU_CNT(1),
.C_PROBE584_MU_CNT(1),
.C_PROBE585_MU_CNT(1),
.C_PROBE586_MU_CNT(1),
.C_PROBE587_MU_CNT(1),
.C_PROBE588_MU_CNT(1),
.C_PROBE589_MU_CNT(1),
.C_PROBE590_MU_CNT(1),
.C_PROBE591_MU_CNT(1),
.C_PROBE592_MU_CNT(1),
.C_PROBE593_MU_CNT(1),
.C_PROBE594_MU_CNT(1),
.C_PROBE595_MU_CNT(1),
.C_PROBE596_MU_CNT(1),
.C_PROBE597_MU_CNT(1),
.C_PROBE598_MU_CNT(1),
.C_PROBE599_MU_CNT(1),
.C_PROBE600_MU_CNT(1),
.C_PROBE601_MU_CNT(1),
.C_PROBE602_MU_CNT(1),
.C_PROBE603_MU_CNT(1),
.C_PROBE604_MU_CNT(1),
.C_PROBE605_MU_CNT(1),
.C_PROBE606_MU_CNT(1),
.C_PROBE607_MU_CNT(1),
.C_PROBE608_MU_CNT(1),
.C_PROBE609_MU_CNT(1),
.C_PROBE610_MU_CNT(1),
.C_PROBE611_MU_CNT(1),
.C_PROBE612_MU_CNT(1),
.C_PROBE613_MU_CNT(1),
.C_PROBE614_MU_CNT(1),
.C_PROBE615_MU_CNT(1),
.C_PROBE616_MU_CNT(1),
.C_PROBE617_MU_CNT(1),
.C_PROBE618_MU_CNT(1),
.C_PROBE619_MU_CNT(1),
.C_PROBE620_MU_CNT(1),
.C_PROBE621_MU_CNT(1),
.C_PROBE622_MU_CNT(1),
.C_PROBE623_MU_CNT(1),
.C_PROBE624_MU_CNT(1),
.C_PROBE625_MU_CNT(1),
.C_PROBE626_MU_CNT(1),
.C_PROBE627_MU_CNT(1),
.C_PROBE628_MU_CNT(1),
.C_PROBE629_MU_CNT(1),
.C_PROBE630_MU_CNT(1),
.C_PROBE631_MU_CNT(1),
.C_PROBE632_MU_CNT(1),
.C_PROBE633_MU_CNT(1),
.C_PROBE634_MU_CNT(1),
.C_PROBE635_MU_CNT(1),
.C_PROBE636_MU_CNT(1),
.C_PROBE637_MU_CNT(1),
.C_PROBE638_MU_CNT(1),
.C_PROBE639_MU_CNT(1),
.C_PROBE640_MU_CNT(1),
.C_PROBE641_MU_CNT(1),
.C_PROBE642_MU_CNT(1),
.C_PROBE643_MU_CNT(1),
.C_PROBE644_MU_CNT(1),
.C_PROBE645_MU_CNT(1),
.C_PROBE646_MU_CNT(1),
.C_PROBE647_MU_CNT(1),
.C_PROBE648_MU_CNT(1),
.C_PROBE649_MU_CNT(1),
.C_PROBE650_MU_CNT(1),
.C_PROBE651_MU_CNT(1),
.C_PROBE652_MU_CNT(1),
.C_PROBE653_MU_CNT(1),
.C_PROBE654_MU_CNT(1),
.C_PROBE655_MU_CNT(1),
.C_PROBE656_MU_CNT(1),
.C_PROBE657_MU_CNT(1),
.C_PROBE658_MU_CNT(1),
.C_PROBE659_MU_CNT(1),
.C_PROBE660_MU_CNT(1),
.C_PROBE661_MU_CNT(1),
.C_PROBE662_MU_CNT(1),
.C_PROBE663_MU_CNT(1),
.C_PROBE664_MU_CNT(1),
.C_PROBE665_MU_CNT(1),
.C_PROBE666_MU_CNT(1),
.C_PROBE667_MU_CNT(1),
.C_PROBE668_MU_CNT(1),
.C_PROBE669_MU_CNT(1),
.C_PROBE670_MU_CNT(1),
.C_PROBE671_MU_CNT(1),
.C_PROBE672_MU_CNT(1),
.C_PROBE673_MU_CNT(1),
.C_PROBE674_MU_CNT(1),
.C_PROBE675_MU_CNT(1),
.C_PROBE676_MU_CNT(1),
.C_PROBE677_MU_CNT(1),
.C_PROBE678_MU_CNT(1),
.C_PROBE679_MU_CNT(1),
.C_PROBE680_MU_CNT(1),
.C_PROBE681_MU_CNT(1),
.C_PROBE682_MU_CNT(1),
.C_PROBE683_MU_CNT(1),
.C_PROBE684_MU_CNT(1),
.C_PROBE685_MU_CNT(1),
.C_PROBE686_MU_CNT(1),
.C_PROBE687_MU_CNT(1),
.C_PROBE688_MU_CNT(1),
.C_PROBE689_MU_CNT(1),
.C_PROBE690_MU_CNT(1),
.C_PROBE691_MU_CNT(1),
.C_PROBE692_MU_CNT(1),
.C_PROBE693_MU_CNT(1),
.C_PROBE694_MU_CNT(1),
.C_PROBE695_MU_CNT(1),
.C_PROBE696_MU_CNT(1),
.C_PROBE697_MU_CNT(1),
.C_PROBE698_MU_CNT(1),
.C_PROBE699_MU_CNT(1),
.C_PROBE700_MU_CNT(1),
.C_PROBE701_MU_CNT(1),
.C_PROBE702_MU_CNT(1),
.C_PROBE703_MU_CNT(1),
.C_PROBE704_MU_CNT(1),
.C_PROBE705_MU_CNT(1),
.C_PROBE706_MU_CNT(1),
.C_PROBE707_MU_CNT(1),
.C_PROBE708_MU_CNT(1),
.C_PROBE709_MU_CNT(1),
.C_PROBE710_MU_CNT(1),
.C_PROBE711_MU_CNT(1),
.C_PROBE712_MU_CNT(1),
.C_PROBE713_MU_CNT(1),
.C_PROBE714_MU_CNT(1),
.C_PROBE715_MU_CNT(1),
.C_PROBE716_MU_CNT(1),
.C_PROBE717_MU_CNT(1),
.C_PROBE718_MU_CNT(1),
.C_PROBE719_MU_CNT(1),
.C_PROBE720_MU_CNT(1),
.C_PROBE721_MU_CNT(1),
.C_PROBE722_MU_CNT(1),
.C_PROBE723_MU_CNT(1),
.C_PROBE724_MU_CNT(1),
.C_PROBE725_MU_CNT(1),
.C_PROBE726_MU_CNT(1),
.C_PROBE727_MU_CNT(1),
.C_PROBE728_MU_CNT(1),
.C_PROBE729_MU_CNT(1),
.C_PROBE730_MU_CNT(1),
.C_PROBE731_MU_CNT(1),
.C_PROBE732_MU_CNT(1),
.C_PROBE733_MU_CNT(1),
.C_PROBE734_MU_CNT(1),
.C_PROBE735_MU_CNT(1),
.C_PROBE736_MU_CNT(1),
.C_PROBE737_MU_CNT(1),
.C_PROBE738_MU_CNT(1),
.C_PROBE739_MU_CNT(1),
.C_PROBE740_MU_CNT(1),
.C_PROBE741_MU_CNT(1),
.C_PROBE742_MU_CNT(1),
.C_PROBE743_MU_CNT(1),
.C_PROBE744_MU_CNT(1),
.C_PROBE745_MU_CNT(1),
.C_PROBE746_MU_CNT(1),
.C_PROBE747_MU_CNT(1),
.C_PROBE748_MU_CNT(1),
.C_PROBE749_MU_CNT(1),
.C_PROBE750_MU_CNT(1),
.C_PROBE751_MU_CNT(1),
.C_PROBE752_MU_CNT(1),
.C_PROBE753_MU_CNT(1),
.C_PROBE754_MU_CNT(1),
.C_PROBE755_MU_CNT(1),
.C_PROBE756_MU_CNT(1),
.C_PROBE757_MU_CNT(1),
.C_PROBE758_MU_CNT(1),
.C_PROBE759_MU_CNT(1),
.C_PROBE760_MU_CNT(1),
.C_PROBE761_MU_CNT(1),
.C_PROBE762_MU_CNT(1),
.C_PROBE763_MU_CNT(1),
.C_PROBE764_MU_CNT(1),
.C_PROBE765_MU_CNT(1),
.C_PROBE766_MU_CNT(1),
.C_PROBE767_MU_CNT(1),
.C_PROBE768_MU_CNT(1),
.C_PROBE769_MU_CNT(1),
.C_PROBE770_MU_CNT(1),
.C_PROBE771_MU_CNT(1),
.C_PROBE772_MU_CNT(1),
.C_PROBE773_MU_CNT(1),
.C_PROBE774_MU_CNT(1),
.C_PROBE775_MU_CNT(1),
.C_PROBE776_MU_CNT(1),
.C_PROBE777_MU_CNT(1),
.C_PROBE778_MU_CNT(1),
.C_PROBE779_MU_CNT(1),
.C_PROBE780_MU_CNT(1),
.C_PROBE781_MU_CNT(1),
.C_PROBE782_MU_CNT(1),
.C_PROBE783_MU_CNT(1),
.C_PROBE784_MU_CNT(1),
.C_PROBE785_MU_CNT(1),
.C_PROBE786_MU_CNT(1),
.C_PROBE787_MU_CNT(1),
.C_PROBE788_MU_CNT(1),
.C_PROBE789_MU_CNT(1),
.C_PROBE790_MU_CNT(1),
.C_PROBE791_MU_CNT(1),
.C_PROBE792_MU_CNT(1),
.C_PROBE793_MU_CNT(1),
.C_PROBE794_MU_CNT(1),
.C_PROBE795_MU_CNT(1),
.C_PROBE796_MU_CNT(1),
.C_PROBE797_MU_CNT(1),
.C_PROBE798_MU_CNT(1),
.C_PROBE799_MU_CNT(1),
.C_PROBE800_MU_CNT(1),
.C_PROBE801_MU_CNT(1),
.C_PROBE802_MU_CNT(1),
.C_PROBE803_MU_CNT(1),
.C_PROBE804_MU_CNT(1),
.C_PROBE805_MU_CNT(1),
.C_PROBE806_MU_CNT(1),
.C_PROBE807_MU_CNT(1),
.C_PROBE808_MU_CNT(1),
.C_PROBE809_MU_CNT(1),
.C_PROBE810_MU_CNT(1),
.C_PROBE811_MU_CNT(1),
.C_PROBE812_MU_CNT(1),
.C_PROBE813_MU_CNT(1),
.C_PROBE814_MU_CNT(1),
.C_PROBE815_MU_CNT(1),
.C_PROBE816_MU_CNT(1),
.C_PROBE817_MU_CNT(1),
.C_PROBE818_MU_CNT(1),
.C_PROBE819_MU_CNT(1),
.C_PROBE820_MU_CNT(1),
.C_PROBE821_MU_CNT(1),
.C_PROBE822_MU_CNT(1),
.C_PROBE823_MU_CNT(1),
.C_PROBE824_MU_CNT(1),
.C_PROBE825_MU_CNT(1),
.C_PROBE826_MU_CNT(1),
.C_PROBE827_MU_CNT(1),
.C_PROBE828_MU_CNT(1),
.C_PROBE829_MU_CNT(1),
.C_PROBE830_MU_CNT(1),
.C_PROBE831_MU_CNT(1),
.C_PROBE832_MU_CNT(1),
.C_PROBE833_MU_CNT(1),
.C_PROBE834_MU_CNT(1),
.C_PROBE835_MU_CNT(1),
.C_PROBE836_MU_CNT(1),
.C_PROBE837_MU_CNT(1),
.C_PROBE838_MU_CNT(1),
.C_PROBE839_MU_CNT(1),
.C_PROBE840_MU_CNT(1),
.C_PROBE841_MU_CNT(1),
.C_PROBE842_MU_CNT(1),
.C_PROBE843_MU_CNT(1),
.C_PROBE844_MU_CNT(1),
.C_PROBE845_MU_CNT(1),
.C_PROBE846_MU_CNT(1),
.C_PROBE847_MU_CNT(1),
.C_PROBE848_MU_CNT(1),
.C_PROBE849_MU_CNT(1),
.C_PROBE850_MU_CNT(1),
.C_PROBE851_MU_CNT(1),
.C_PROBE852_MU_CNT(1),
.C_PROBE853_MU_CNT(1),
.C_PROBE854_MU_CNT(1),
.C_PROBE855_MU_CNT(1),
.C_PROBE856_MU_CNT(1),
.C_PROBE857_MU_CNT(1),
.C_PROBE858_MU_CNT(1),
.C_PROBE859_MU_CNT(1),
.C_PROBE860_MU_CNT(1),
.C_PROBE861_MU_CNT(1),
.C_PROBE862_MU_CNT(1),
.C_PROBE863_MU_CNT(1),
.C_PROBE864_MU_CNT(1),
.C_PROBE865_MU_CNT(1),
.C_PROBE866_MU_CNT(1),
.C_PROBE867_MU_CNT(1),
.C_PROBE868_MU_CNT(1),
.C_PROBE869_MU_CNT(1),
.C_PROBE870_MU_CNT(1),
.C_PROBE871_MU_CNT(1),
.C_PROBE872_MU_CNT(1),
.C_PROBE873_MU_CNT(1),
.C_PROBE874_MU_CNT(1),
.C_PROBE875_MU_CNT(1),
.C_PROBE876_MU_CNT(1),
.C_PROBE877_MU_CNT(1),
.C_PROBE878_MU_CNT(1),
.C_PROBE879_MU_CNT(1),
.C_PROBE880_MU_CNT(1),
.C_PROBE881_MU_CNT(1),
.C_PROBE882_MU_CNT(1),
.C_PROBE883_MU_CNT(1),
.C_PROBE884_MU_CNT(1),
.C_PROBE885_MU_CNT(1),
.C_PROBE886_MU_CNT(1),
.C_PROBE887_MU_CNT(1),
.C_PROBE888_MU_CNT(1),
.C_PROBE889_MU_CNT(1),
.C_PROBE890_MU_CNT(1),
.C_PROBE891_MU_CNT(1),
.C_PROBE892_MU_CNT(1),
.C_PROBE893_MU_CNT(1),
.C_PROBE894_MU_CNT(1),
.C_PROBE895_MU_CNT(1),
.C_PROBE896_MU_CNT(1),
.C_PROBE897_MU_CNT(1),
.C_PROBE898_MU_CNT(1),
.C_PROBE899_MU_CNT(1),
.C_PROBE900_MU_CNT(1),
.C_PROBE901_MU_CNT(1),
.C_PROBE902_MU_CNT(1),
.C_PROBE903_MU_CNT(1),
.C_PROBE904_MU_CNT(1),
.C_PROBE905_MU_CNT(1),
.C_PROBE906_MU_CNT(1),
.C_PROBE907_MU_CNT(1),
.C_PROBE908_MU_CNT(1),
.C_PROBE909_MU_CNT(1),
.C_PROBE910_MU_CNT(1),
.C_PROBE911_MU_CNT(1),
.C_PROBE912_MU_CNT(1),
.C_PROBE913_MU_CNT(1),
.C_PROBE914_MU_CNT(1),
.C_PROBE915_MU_CNT(1),
.C_PROBE916_MU_CNT(1),
.C_PROBE917_MU_CNT(1),
.C_PROBE918_MU_CNT(1),
.C_PROBE919_MU_CNT(1),
.C_PROBE920_MU_CNT(1),
.C_PROBE921_MU_CNT(1),
.C_PROBE922_MU_CNT(1),
.C_PROBE923_MU_CNT(1),
.C_PROBE924_MU_CNT(1),
.C_PROBE925_MU_CNT(1),
.C_PROBE926_MU_CNT(1),
.C_PROBE927_MU_CNT(1),
.C_PROBE928_MU_CNT(1),
.C_PROBE929_MU_CNT(1),
.C_PROBE930_MU_CNT(1),
.C_PROBE931_MU_CNT(1),
.C_PROBE932_MU_CNT(1),
.C_PROBE933_MU_CNT(1),
.C_PROBE934_MU_CNT(1),
.C_PROBE935_MU_CNT(1),
.C_PROBE936_MU_CNT(1),
.C_PROBE937_MU_CNT(1),
.C_PROBE938_MU_CNT(1),
.C_PROBE939_MU_CNT(1),
.C_PROBE940_MU_CNT(1),
.C_PROBE941_MU_CNT(1),
.C_PROBE942_MU_CNT(1),
.C_PROBE943_MU_CNT(1),
.C_PROBE944_MU_CNT(1),
.C_PROBE945_MU_CNT(1),
.C_PROBE946_MU_CNT(1),
.C_PROBE947_MU_CNT(1),
.C_PROBE948_MU_CNT(1),
.C_PROBE949_MU_CNT(1),
.C_PROBE950_MU_CNT(1),
.C_PROBE951_MU_CNT(1),
.C_PROBE952_MU_CNT(1),
.C_PROBE953_MU_CNT(1),
.C_PROBE954_MU_CNT(1),
.C_PROBE955_MU_CNT(1),
.C_PROBE956_MU_CNT(1),
.C_PROBE957_MU_CNT(1),
.C_PROBE958_MU_CNT(1),
.C_PROBE959_MU_CNT(1),
.C_PROBE960_MU_CNT(1),
.C_PROBE961_MU_CNT(1),
.C_PROBE962_MU_CNT(1),
.C_PROBE963_MU_CNT(1),
.C_PROBE964_MU_CNT(1),
.C_PROBE965_MU_CNT(1),
.C_PROBE966_MU_CNT(1),
.C_PROBE967_MU_CNT(1),
.C_PROBE968_MU_CNT(1),
.C_PROBE969_MU_CNT(1),
.C_PROBE970_MU_CNT(1),
.C_PROBE971_MU_CNT(1),
.C_PROBE972_MU_CNT(1),
.C_PROBE973_MU_CNT(1),
.C_PROBE974_MU_CNT(1),
.C_PROBE975_MU_CNT(1),
.C_PROBE976_MU_CNT(1),
.C_PROBE977_MU_CNT(1),
.C_PROBE978_MU_CNT(1),
.C_PROBE979_MU_CNT(1),
.C_PROBE980_MU_CNT(1),
.C_PROBE981_MU_CNT(1),
.C_PROBE982_MU_CNT(1),
.C_PROBE983_MU_CNT(1),
.C_PROBE984_MU_CNT(1),
.C_PROBE985_MU_CNT(1),
.C_PROBE986_MU_CNT(1),
.C_PROBE987_MU_CNT(1),
.C_PROBE988_MU_CNT(1),
.C_PROBE989_MU_CNT(1),
.C_PROBE990_MU_CNT(1),
.C_PROBE991_MU_CNT(1),
.C_PROBE992_MU_CNT(1),
.C_PROBE993_MU_CNT(1),
.C_PROBE994_MU_CNT(1),
.C_PROBE995_MU_CNT(1),
.C_PROBE996_MU_CNT(1),
.C_PROBE997_MU_CNT(1),
.C_PROBE998_MU_CNT(1),
.C_PROBE999_MU_CNT(1),
.C_PROBE1000_MU_CNT(1),
.C_PROBE1001_MU_CNT(1),
.C_PROBE1002_MU_CNT(1),
.C_PROBE1003_MU_CNT(1),
.C_PROBE1004_MU_CNT(1),
.C_PROBE1005_MU_CNT(1),
.C_PROBE1006_MU_CNT(1),
.C_PROBE1007_MU_CNT(1),
.C_PROBE1008_MU_CNT(1),
.C_PROBE1009_MU_CNT(1),
.C_PROBE1010_MU_CNT(1),
.C_PROBE1011_MU_CNT(1),
.C_PROBE1012_MU_CNT(1),
.C_PROBE1013_MU_CNT(1),
.C_PROBE1014_MU_CNT(1),
.C_PROBE1015_MU_CNT(1),
.C_PROBE1016_MU_CNT(1),
.C_PROBE1017_MU_CNT(1),
.C_PROBE1018_MU_CNT(1),
.C_PROBE1019_MU_CNT(1),
.C_PROBE1020_MU_CNT(1),
.C_PROBE1021_MU_CNT(1),
.C_PROBE1022_MU_CNT(1),
.C_PROBE1023_MU_CNT(1),
.C_PROBE0_TYPE(0),
.C_PROBE1_TYPE(0),
.C_PROBE2_TYPE(0),
.C_PROBE3_TYPE(0),
.C_PROBE4_TYPE(0),
.C_PROBE5_TYPE(0),
.C_PROBE6_TYPE(0),
.C_PROBE7_TYPE(0),
.C_PROBE8_TYPE(0),
.C_PROBE9_TYPE(0),
.C_PROBE10_TYPE(0),
.C_PROBE11_TYPE(0),
.C_PROBE12_TYPE(0),
.C_PROBE13_TYPE(0),
.C_PROBE14_TYPE(0),
.C_PROBE15_TYPE(0),
.C_PROBE16_TYPE(0),
.C_PROBE17_TYPE(0),
.C_PROBE18_TYPE(0),
.C_PROBE19_TYPE(0),
.C_PROBE20_TYPE(0),
.C_PROBE21_TYPE(1),
.C_PROBE22_TYPE(1),
.C_PROBE23_TYPE(1),
.C_PROBE24_TYPE(1),
.C_PROBE25_TYPE(1),
.C_PROBE26_TYPE(1),
.C_PROBE27_TYPE(1),
.C_PROBE28_TYPE(1),
.C_PROBE29_TYPE(1),
.C_PROBE30_TYPE(1),
.C_PROBE31_TYPE(1),
.C_PROBE32_TYPE(1),
.C_PROBE33_TYPE(1),
.C_PROBE34_TYPE(1),
.C_PROBE35_TYPE(1),
.C_PROBE36_TYPE(1),
.C_PROBE37_TYPE(1),
.C_PROBE38_TYPE(1),
.C_PROBE39_TYPE(1),
.C_PROBE40_TYPE(1),
.C_PROBE41_TYPE(1),
.C_PROBE42_TYPE(1),
.C_PROBE43_TYPE(1),
.C_PROBE44_TYPE(1),
.C_PROBE45_TYPE(1),
.C_PROBE46_TYPE(1),
.C_PROBE47_TYPE(1),
.C_PROBE48_TYPE(1),
.C_PROBE49_TYPE(1),
.C_PROBE50_TYPE(1),
.C_PROBE51_TYPE(1),
.C_PROBE52_TYPE(1),
.C_PROBE53_TYPE(1),
.C_PROBE54_TYPE(1),
.C_PROBE55_TYPE(1),
.C_PROBE56_TYPE(1),
.C_PROBE57_TYPE(1),
.C_PROBE58_TYPE(1),
.C_PROBE59_TYPE(1),
.C_PROBE60_TYPE(1),
.C_PROBE61_TYPE(1),
.C_PROBE62_TYPE(1),
.C_PROBE63_TYPE(1),
.C_PROBE64_TYPE(1),
.C_PROBE65_TYPE(1),
.C_PROBE66_TYPE(1),
.C_PROBE67_TYPE(1),
.C_PROBE68_TYPE(1),
.C_PROBE69_TYPE(1),
.C_PROBE70_TYPE(1),
.C_PROBE71_TYPE(1),
.C_PROBE72_TYPE(1),
.C_PROBE73_TYPE(1),
.C_PROBE74_TYPE(1),
.C_PROBE75_TYPE(1),
.C_PROBE76_TYPE(1),
.C_PROBE77_TYPE(1),
.C_PROBE78_TYPE(1),
.C_PROBE79_TYPE(1),
.C_PROBE80_TYPE(1),
.C_PROBE81_TYPE(1),
.C_PROBE82_TYPE(1),
.C_PROBE83_TYPE(1),
.C_PROBE84_TYPE(1),
.C_PROBE85_TYPE(1),
.C_PROBE86_TYPE(1),
.C_PROBE87_TYPE(1),
.C_PROBE88_TYPE(1),
.C_PROBE89_TYPE(1),
.C_PROBE90_TYPE(1),
.C_PROBE91_TYPE(1),
.C_PROBE92_TYPE(1),
.C_PROBE93_TYPE(1),
.C_PROBE94_TYPE(1),
.C_PROBE95_TYPE(1),
.C_PROBE96_TYPE(1),
.C_PROBE97_TYPE(1),
.C_PROBE98_TYPE(1),
.C_PROBE99_TYPE(1),
.C_PROBE100_TYPE(1),
.C_PROBE101_TYPE(1),
.C_PROBE102_TYPE(1),
.C_PROBE103_TYPE(1),
.C_PROBE104_TYPE(1),
.C_PROBE105_TYPE(1),
.C_PROBE106_TYPE(1),
.C_PROBE107_TYPE(1),
.C_PROBE108_TYPE(1),
.C_PROBE109_TYPE(1),
.C_PROBE110_TYPE(1),
.C_PROBE111_TYPE(1),
.C_PROBE112_TYPE(1),
.C_PROBE113_TYPE(1),
.C_PROBE114_TYPE(1),
.C_PROBE115_TYPE(1),
.C_PROBE116_TYPE(1),
.C_PROBE117_TYPE(1),
.C_PROBE118_TYPE(1),
.C_PROBE119_TYPE(1),
.C_PROBE120_TYPE(1),
.C_PROBE121_TYPE(1),
.C_PROBE122_TYPE(1),
.C_PROBE123_TYPE(1),
.C_PROBE124_TYPE(1),
.C_PROBE125_TYPE(1),
.C_PROBE126_TYPE(1),
.C_PROBE127_TYPE(1),
.C_PROBE128_TYPE(1),
.C_PROBE129_TYPE(1),
.C_PROBE130_TYPE(1),
.C_PROBE131_TYPE(1),
.C_PROBE132_TYPE(1),
.C_PROBE133_TYPE(1),
.C_PROBE134_TYPE(1),
.C_PROBE135_TYPE(1),
.C_PROBE136_TYPE(1),
.C_PROBE137_TYPE(1),
.C_PROBE138_TYPE(1),
.C_PROBE139_TYPE(1),
.C_PROBE140_TYPE(1),
.C_PROBE141_TYPE(1),
.C_PROBE142_TYPE(1),
.C_PROBE143_TYPE(1),
.C_PROBE144_TYPE(1),
.C_PROBE145_TYPE(1),
.C_PROBE146_TYPE(1),
.C_PROBE147_TYPE(1),
.C_PROBE148_TYPE(1),
.C_PROBE149_TYPE(1),
.C_PROBE150_TYPE(1),
.C_PROBE151_TYPE(1),
.C_PROBE152_TYPE(1),
.C_PROBE153_TYPE(1),
.C_PROBE154_TYPE(1),
.C_PROBE155_TYPE(1),
.C_PROBE156_TYPE(1),
.C_PROBE157_TYPE(1),
.C_PROBE158_TYPE(1),
.C_PROBE159_TYPE(1),
.C_PROBE160_TYPE(1),
.C_PROBE161_TYPE(1),
.C_PROBE162_TYPE(1),
.C_PROBE163_TYPE(1),
.C_PROBE164_TYPE(1),
.C_PROBE165_TYPE(1),
.C_PROBE166_TYPE(1),
.C_PROBE167_TYPE(1),
.C_PROBE168_TYPE(1),
.C_PROBE169_TYPE(1),
.C_PROBE170_TYPE(1),
.C_PROBE171_TYPE(1),
.C_PROBE172_TYPE(1),
.C_PROBE173_TYPE(1),
.C_PROBE174_TYPE(1),
.C_PROBE175_TYPE(1),
.C_PROBE176_TYPE(1),
.C_PROBE177_TYPE(1),
.C_PROBE178_TYPE(1),
.C_PROBE179_TYPE(1),
.C_PROBE180_TYPE(1),
.C_PROBE181_TYPE(1),
.C_PROBE182_TYPE(1),
.C_PROBE183_TYPE(1),
.C_PROBE184_TYPE(1),
.C_PROBE185_TYPE(1),
.C_PROBE186_TYPE(1),
.C_PROBE187_TYPE(1),
.C_PROBE188_TYPE(1),
.C_PROBE189_TYPE(1),
.C_PROBE190_TYPE(1),
.C_PROBE191_TYPE(1),
.C_PROBE192_TYPE(1),
.C_PROBE193_TYPE(1),
.C_PROBE194_TYPE(1),
.C_PROBE195_TYPE(1),
.C_PROBE196_TYPE(1),
.C_PROBE197_TYPE(1),
.C_PROBE198_TYPE(1),
.C_PROBE199_TYPE(1),
.C_PROBE200_TYPE(1),
.C_PROBE201_TYPE(1),
.C_PROBE202_TYPE(1),
.C_PROBE203_TYPE(1),
.C_PROBE204_TYPE(1),
.C_PROBE205_TYPE(1),
.C_PROBE206_TYPE(1),
.C_PROBE207_TYPE(1),
.C_PROBE208_TYPE(1),
.C_PROBE209_TYPE(1),
.C_PROBE210_TYPE(1),
.C_PROBE211_TYPE(1),
.C_PROBE212_TYPE(1),
.C_PROBE213_TYPE(1),
.C_PROBE214_TYPE(1),
.C_PROBE215_TYPE(1),
.C_PROBE216_TYPE(1),
.C_PROBE217_TYPE(1),
.C_PROBE218_TYPE(1),
.C_PROBE219_TYPE(1),
.C_PROBE220_TYPE(1),
.C_PROBE221_TYPE(1),
.C_PROBE222_TYPE(1),
.C_PROBE223_TYPE(1),
.C_PROBE224_TYPE(1),
.C_PROBE225_TYPE(1),
.C_PROBE226_TYPE(1),
.C_PROBE227_TYPE(1),
.C_PROBE228_TYPE(1),
.C_PROBE229_TYPE(1),
.C_PROBE230_TYPE(1),
.C_PROBE231_TYPE(1),
.C_PROBE232_TYPE(1),
.C_PROBE233_TYPE(1),
.C_PROBE234_TYPE(1),
.C_PROBE235_TYPE(1),
.C_PROBE236_TYPE(1),
.C_PROBE237_TYPE(1),
.C_PROBE238_TYPE(1),
.C_PROBE239_TYPE(1),
.C_PROBE240_TYPE(1),
.C_PROBE241_TYPE(1),
.C_PROBE242_TYPE(1),
.C_PROBE243_TYPE(1),
.C_PROBE244_TYPE(1),
.C_PROBE245_TYPE(1),
.C_PROBE246_TYPE(1),
.C_PROBE247_TYPE(1),
.C_PROBE248_TYPE(1),
.C_PROBE249_TYPE(1),
.C_PROBE250_TYPE(1),
.C_PROBE251_TYPE(1),
.C_PROBE252_TYPE(1),
.C_PROBE253_TYPE(1),
.C_PROBE254_TYPE(1),
.C_PROBE255_TYPE(1),
.C_PROBE256_TYPE(1),
.C_PROBE257_TYPE(1),
.C_PROBE258_TYPE(1),
.C_PROBE259_TYPE(1),
.C_PROBE260_TYPE(1),
.C_PROBE261_TYPE(1),
.C_PROBE262_TYPE(1),
.C_PROBE263_TYPE(1),
.C_PROBE264_TYPE(1),
.C_PROBE265_TYPE(1),
.C_PROBE266_TYPE(1),
.C_PROBE267_TYPE(1),
.C_PROBE268_TYPE(1),
.C_PROBE269_TYPE(1),
.C_PROBE270_TYPE(1),
.C_PROBE271_TYPE(1),
.C_PROBE272_TYPE(1),
.C_PROBE273_TYPE(1),
.C_PROBE274_TYPE(1),
.C_PROBE275_TYPE(1),
.C_PROBE276_TYPE(1),
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.C_PROBE901_TYPE(1),
.C_PROBE902_TYPE(1),
.C_PROBE903_TYPE(1),
.C_PROBE904_TYPE(1),
.C_PROBE905_TYPE(1),
.C_PROBE906_TYPE(1),
.C_PROBE907_TYPE(1),
.C_PROBE908_TYPE(1),
.C_PROBE909_TYPE(1),
.C_PROBE910_TYPE(1),
.C_PROBE911_TYPE(1),
.C_PROBE912_TYPE(1),
.C_PROBE913_TYPE(1),
.C_PROBE914_TYPE(1),
.C_PROBE915_TYPE(1),
.C_PROBE916_TYPE(1),
.C_PROBE917_TYPE(1),
.C_PROBE918_TYPE(1),
.C_PROBE919_TYPE(1),
.C_PROBE920_TYPE(1),
.C_PROBE921_TYPE(1),
.C_PROBE922_TYPE(1),
.C_PROBE923_TYPE(1),
.C_PROBE924_TYPE(1),
.C_PROBE925_TYPE(1),
.C_PROBE926_TYPE(1),
.C_PROBE927_TYPE(1),
.C_PROBE928_TYPE(1),
.C_PROBE929_TYPE(1),
.C_PROBE930_TYPE(1),
.C_PROBE931_TYPE(1),
.C_PROBE932_TYPE(1),
.C_PROBE933_TYPE(1),
.C_PROBE934_TYPE(1),
.C_PROBE935_TYPE(1),
.C_PROBE936_TYPE(1),
.C_PROBE937_TYPE(1),
.C_PROBE938_TYPE(1),
.C_PROBE939_TYPE(1),
.C_PROBE940_TYPE(1),
.C_PROBE941_TYPE(1),
.C_PROBE942_TYPE(1),
.C_PROBE943_TYPE(1),
.C_PROBE944_TYPE(1),
.C_PROBE945_TYPE(1),
.C_PROBE946_TYPE(1),
.C_PROBE947_TYPE(1),
.C_PROBE948_TYPE(1),
.C_PROBE949_TYPE(1),
.C_PROBE950_TYPE(1),
.C_PROBE951_TYPE(1),
.C_PROBE952_TYPE(1),
.C_PROBE953_TYPE(1),
.C_PROBE954_TYPE(1),
.C_PROBE955_TYPE(1),
.C_PROBE956_TYPE(1),
.C_PROBE957_TYPE(1),
.C_PROBE958_TYPE(1),
.C_PROBE959_TYPE(1),
.C_PROBE960_TYPE(1),
.C_PROBE961_TYPE(1),
.C_PROBE962_TYPE(1),
.C_PROBE963_TYPE(1),
.C_PROBE964_TYPE(1),
.C_PROBE965_TYPE(1),
.C_PROBE966_TYPE(1),
.C_PROBE967_TYPE(1),
.C_PROBE968_TYPE(1),
.C_PROBE969_TYPE(1),
.C_PROBE970_TYPE(1),
.C_PROBE971_TYPE(1),
.C_PROBE972_TYPE(1),
.C_PROBE973_TYPE(1),
.C_PROBE974_TYPE(1),
.C_PROBE975_TYPE(1),
.C_PROBE976_TYPE(1),
.C_PROBE977_TYPE(1),
.C_PROBE978_TYPE(1),
.C_PROBE979_TYPE(1),
.C_PROBE980_TYPE(1),
.C_PROBE981_TYPE(1),
.C_PROBE982_TYPE(1),
.C_PROBE983_TYPE(1),
.C_PROBE984_TYPE(1),
.C_PROBE985_TYPE(1),
.C_PROBE986_TYPE(1),
.C_PROBE987_TYPE(1),
.C_PROBE988_TYPE(1),
.C_PROBE989_TYPE(1),
.C_PROBE990_TYPE(1),
.C_PROBE991_TYPE(1),
.C_PROBE992_TYPE(1),
.C_PROBE993_TYPE(1),
.C_PROBE994_TYPE(1),
.C_PROBE995_TYPE(1),
.C_PROBE996_TYPE(1),
.C_PROBE997_TYPE(1),
.C_PROBE998_TYPE(1),
.C_PROBE999_TYPE(1),
.C_PROBE1000_TYPE(1),
.C_PROBE1001_TYPE(1),
.C_PROBE1002_TYPE(1),
.C_PROBE1003_TYPE(1),
.C_PROBE1004_TYPE(1),
.C_PROBE1005_TYPE(1),
.C_PROBE1006_TYPE(1),
.C_PROBE1007_TYPE(1),
.C_PROBE1008_TYPE(1),
.C_PROBE1009_TYPE(1),
.C_PROBE1010_TYPE(1),
.C_PROBE1011_TYPE(1),
.C_PROBE1012_TYPE(1),
.C_PROBE1013_TYPE(1),
.C_PROBE1014_TYPE(1),
.C_PROBE1015_TYPE(1),
.C_PROBE1016_TYPE(1),
.C_PROBE1017_TYPE(1),
.C_PROBE1018_TYPE(1),
.C_PROBE1019_TYPE(1),
.C_PROBE1020_TYPE(1),
.C_PROBE1021_TYPE(1),
.C_PROBE1022_TYPE(1),
.C_PROBE1023_TYPE(1)
) inst (
.clk(clk),
.sl_iport0(sl_iport0),
.sl_oport0(sl_oport0),
.probe0(probe0),
.probe1(probe1),
.probe2(probe2),
.probe3(probe3),
.probe4(probe4),
.probe5(probe5),
.probe6(probe6),
.probe7(probe7),
.probe8(probe8),
.probe9(probe9),
.probe10(probe10),
.probe11(probe11),
.probe12(probe12),
.probe13(probe13),
.probe14(probe14),
.probe15(probe15),
.probe16(probe16),
.probe17(probe17),
.probe18(probe18),
.probe19(probe19),
.probe20(probe20),
.probe21(0),
.probe22(0),
.probe23(0),
.probe24(0),
.probe25(0),
.probe26(0),
.probe27(0),
.probe28(0),
.probe29(0),
.probe30(0),
.probe31(0),
.probe32(0),
.probe33(0),
.probe34(0),
.probe35(0),
.probe36(0),
.probe37(0),
.probe38(0),
.probe39(0),
.probe40(0),
.probe41(0),
.probe42(0),
.probe43(0),
.probe44(0),
.probe45(0),
.probe46(0),
.probe47(0),
.probe48(0),
.probe49(0),
.probe50(0),
.probe51(0),
.probe52(0),
.probe53(0),
.probe54(0),
.probe55(0),
.probe56(0),
.probe57(0),
.probe58(0),
.probe59(0),
.probe60(0),
.probe61(0),
.probe62(0),
.probe63(0),
.probe64(0),
.probe65(0),
.probe66(0),
.probe67(0),
.probe68(0),
.probe69(0),
.probe70(0),
.probe71(0),
.probe72(0),
.probe73(0),
.probe74(0),
.probe75(0),
.probe76(0),
.probe77(0),
.probe78(0),
.probe79(0),
.probe80(0),
.probe81(0),
.probe82(0),
.probe83(0),
.probe84(0),
.probe85(0),
.probe86(0),
.probe87(0),
.probe88(0),
.probe89(0),
.probe90(0),
.probe91(0),
.probe92(0),
.probe93(0),
.probe94(0),
.probe95(0),
.probe96(0),
.probe97(0),
.probe98(0),
.probe99(0),
.probe100(0),
.probe101(0),
.probe102(0),
.probe103(0),
.probe104(0),
.probe105(0),
.probe106(0),
.probe107(0),
.probe108(0),
.probe109(0),
.probe110(0),
.probe111(0),
.probe112(0),
.probe113(0),
.probe114(0),
.probe115(0),
.probe116(0),
.probe117(0),
.probe118(0),
.probe119(0),
.probe120(0),
.probe121(0),
.probe122(0),
.probe123(0),
.probe124(0),
.probe125(0),
.probe126(0),
.probe127(0),
.probe128(0),
.probe129(0),
.probe130(0),
.probe131(0),
.probe132(0),
.probe133(0),
.probe134(0),
.probe135(0),
.probe136(0),
.probe137(0),
.probe138(0),
.probe139(0),
.probe140(0),
.probe141(0),
.probe142(0),
.probe143(0),
.probe144(0),
.probe145(0),
.probe146(0),
.probe147(0),
.probe148(0),
.probe149(0),
.probe150(0),
.probe151(0),
.probe152(0),
.probe153(0),
.probe154(0),
.probe155(0),
.probe156(0),
.probe157(0),
.probe158(0),
.probe159(0),
.probe160(0),
.probe161(0),
.probe162(0),
.probe163(0),
.probe164(0),
.probe165(0),
.probe166(0),
.probe167(0),
.probe168(0),
.probe169(0),
.probe170(0),
.probe171(0),
.probe172(0),
.probe173(0),
.probe174(0),
.probe175(0),
.probe176(0),
.probe177(0),
.probe178(0),
.probe179(0),
.probe180(0),
.probe181(0),
.probe182(0),
.probe183(0),
.probe184(0),
.probe185(0),
.probe186(0),
.probe187(0),
.probe188(0),
.probe189(0),
.probe190(0),
.probe191(0),
.probe192(0),
.probe193(0),
.probe194(0),
.probe195(0),
.probe196(0),
.probe197(0),
.probe198(0),
.probe199(0),
.probe200(0),
.probe201(0),
.probe202(0),
.probe203(0),
.probe204(0),
.probe205(0),
.probe206(0),
.probe207(0),
.probe208(0),
.probe209(0),
.probe210(0),
.probe211(0),
.probe212(0),
.probe213(0),
.probe214(0),
.probe215(0),
.probe216(0),
.probe217(0),
.probe218(0),
.probe219(0),
.probe220(0),
.probe221(0),
.probe222(0),
.probe223(0),
.probe224(0),
.probe225(0),
.probe226(0),
.probe227(0),
.probe228(0),
.probe229(0),
.probe230(0),
.probe231(0),
.probe232(0),
.probe233(0),
.probe234(0),
.probe235(0),
.probe236(0),
.probe237(0),
.probe238(0),
.probe239(0),
.probe240(0),
.probe241(0),
.probe242(0),
.probe243(0),
.probe244(0),
.probe245(0),
.probe246(0),
.probe247(0),
.probe248(0),
.probe249(0),
.probe250(0),
.probe251(0),
.probe252(0),
.probe253(0),
.probe254(0),
.probe255(0),
.probe256(0),
.probe257(0),
.probe258(0),
.probe259(0),
.probe260(0),
.probe261(0),
.probe262(0),
.probe263(0),
.probe264(0),
.probe265(0),
.probe266(0),
.probe267(0),
.probe268(0),
.probe269(0),
.probe270(0),
.probe271(0),
.probe272(0),
.probe273(0),
.probe274(0),
.probe275(0),
.probe276(0),
.probe277(0),
.probe278(0),
.probe279(0),
.probe280(0),
.probe281(0),
.probe282(0),
.probe283(0),
.probe284(0),
.probe285(0),
.probe286(0),
.probe287(0),
.probe288(0),
.probe289(0),
.probe290(0),
.probe291(0),
.probe292(0),
.probe293(0),
.probe294(0),
.probe295(0),
.probe296(0),
.probe297(0),
.probe298(0),
.probe299(0),
.probe300(0),
.probe301(0),
.probe302(0),
.probe303(0),
.probe304(0),
.probe305(0),
.probe306(0),
.probe307(0),
.probe308(0),
.probe309(0),
.probe310(0),
.probe311(0),
.probe312(0),
.probe313(0),
.probe314(0),
.probe315(0),
.probe316(0),
.probe317(0),
.probe318(0),
.probe319(0),
.probe320(0),
.probe321(0),
.probe322(0),
.probe323(0),
.probe324(0),
.probe325(0),
.probe326(0),
.probe327(0),
.probe328(0),
.probe329(0),
.probe330(0),
.probe331(0),
.probe332(0),
.probe333(0),
.probe334(0),
.probe335(0),
.probe336(0),
.probe337(0),
.probe338(0),
.probe339(0),
.probe340(0),
.probe341(0),
.probe342(0),
.probe343(0),
.probe344(0),
.probe345(0),
.probe346(0),
.probe347(0),
.probe348(0),
.probe349(0),
.probe350(0),
.probe351(0),
.probe352(0),
.probe353(0),
.probe354(0),
.probe355(0),
.probe356(0),
.probe357(0),
.probe358(0),
.probe359(0),
.probe360(0),
.probe361(0),
.probe362(0),
.probe363(0),
.probe364(0),
.probe365(0),
.probe366(0),
.probe367(0),
.probe368(0),
.probe369(0),
.probe370(0),
.probe371(0),
.probe372(0),
.probe373(0),
.probe374(0),
.probe375(0),
.probe376(0),
.probe377(0),
.probe378(0),
.probe379(0),
.probe380(0),
.probe381(0),
.probe382(0),
.probe383(0),
.probe384(0),
.probe385(0),
.probe386(0),
.probe387(0),
.probe388(0),
.probe389(0),
.probe390(0),
.probe391(0),
.probe392(0),
.probe393(0),
.probe394(0),
.probe395(0),
.probe396(0),
.probe397(0),
.probe398(0),
.probe399(0),
.probe400(0),
.probe401(0),
.probe402(0),
.probe403(0),
.probe404(0),
.probe405(0),
.probe406(0),
.probe407(0),
.probe408(0),
.probe409(0),
.probe410(0),
.probe411(0),
.probe412(0),
.probe413(0),
.probe414(0),
.probe415(0),
.probe416(0),
.probe417(0),
.probe418(0),
.probe419(0),
.probe420(0),
.probe421(0),
.probe422(0),
.probe423(0),
.probe424(0),
.probe425(0),
.probe426(0),
.probe427(0),
.probe428(0),
.probe429(0),
.probe430(0),
.probe431(0),
.probe432(0),
.probe433(0),
.probe434(0),
.probe435(0),
.probe436(0),
.probe437(0),
.probe438(0),
.probe439(0),
.probe440(0),
.probe441(0),
.probe442(0),
.probe443(0),
.probe444(0),
.probe445(0),
.probe446(0),
.probe447(0),
.probe448(0),
.probe449(0),
.probe450(0),
.probe451(0),
.probe452(0),
.probe453(0),
.probe454(0),
.probe455(0),
.probe456(0),
.probe457(0),
.probe458(0),
.probe459(0),
.probe460(0),
.probe461(0),
.probe462(0),
.probe463(0),
.probe464(0),
.probe465(0),
.probe466(0),
.probe467(0),
.probe468(0),
.probe469(0),
.probe470(0),
.probe471(0),
.probe472(0),
.probe473(0),
.probe474(0),
.probe475(0),
.probe476(0),
.probe477(0),
.probe478(0),
.probe479(0),
.probe480(0),
.probe481(0),
.probe482(0),
.probe483(0),
.probe484(0),
.probe485(0),
.probe486(0),
.probe487(0),
.probe488(0),
.probe489(0),
.probe490(0),
.probe491(0),
.probe492(0),
.probe493(0),
.probe494(0),
.probe495(0),
.probe496(0),
.probe497(0),
.probe498(0),
.probe499(0),
.probe500(0),
.probe501(0),
.probe502(0),
.probe503(0),
.probe504(0),
.probe505(0),
.probe506(0),
.probe507(0),
.probe508(0),
.probe509(0),
.probe510(0),
.probe511(0),
.probe512(0),
.probe513(0),
.probe514(0),
.probe515(0),
.probe516(0),
.probe517(0),
.probe518(0),
.probe519(0),
.probe520(0),
.probe521(0),
.probe522(0),
.probe523(0),
.probe524(0),
.probe525(0),
.probe526(0),
.probe527(0),
.probe528(0),
.probe529(0),
.probe530(0),
.probe531(0),
.probe532(0),
.probe533(0),
.probe534(0),
.probe535(0),
.probe536(0),
.probe537(0),
.probe538(0),
.probe539(0),
.probe540(0),
.probe541(0),
.probe542(0),
.probe543(0),
.probe544(0),
.probe545(0),
.probe546(0),
.probe547(0),
.probe548(0),
.probe549(0),
.probe550(0),
.probe551(0),
.probe552(0),
.probe553(0),
.probe554(0),
.probe555(0),
.probe556(0),
.probe557(0),
.probe558(0),
.probe559(0),
.probe560(0),
.probe561(0),
.probe562(0),
.probe563(0),
.probe564(0),
.probe565(0),
.probe566(0),
.probe567(0),
.probe568(0),
.probe569(0),
.probe570(0),
.probe571(0),
.probe572(0),
.probe573(0),
.probe574(0),
.probe575(0),
.probe576(0),
.probe577(0),
.probe578(0),
.probe579(0),
.probe580(0),
.probe581(0),
.probe582(0),
.probe583(0),
.probe584(0),
.probe585(0),
.probe586(0),
.probe587(0),
.probe588(0),
.probe589(0),
.probe590(0),
.probe591(0),
.probe592(0),
.probe593(0),
.probe594(0),
.probe595(0),
.probe596(0),
.probe597(0),
.probe598(0),
.probe599(0),
.probe600(0),
.probe601(0),
.probe602(0),
.probe603(0),
.probe604(0),
.probe605(0),
.probe606(0),
.probe607(0),
.probe608(0),
.probe609(0),
.probe610(0),
.probe611(0),
.probe612(0),
.probe613(0),
.probe614(0),
.probe615(0),
.probe616(0),
.probe617(0),
.probe618(0),
.probe619(0),
.probe620(0),
.probe621(0),
.probe622(0),
.probe623(0),
.probe624(0),
.probe625(0),
.probe626(0),
.probe627(0),
.probe628(0),
.probe629(0),
.probe630(0),
.probe631(0),
.probe632(0),
.probe633(0),
.probe634(0),
.probe635(0),
.probe636(0),
.probe637(0),
.probe638(0),
.probe639(0),
.probe640(0),
.probe641(0),
.probe642(0),
.probe643(0),
.probe644(0),
.probe645(0),
.probe646(0),
.probe647(0),
.probe648(0),
.probe649(0),
.probe650(0),
.probe651(0),
.probe652(0),
.probe653(0),
.probe654(0),
.probe655(0),
.probe656(0),
.probe657(0),
.probe658(0),
.probe659(0),
.probe660(0),
.probe661(0),
.probe662(0),
.probe663(0),
.probe664(0),
.probe665(0),
.probe666(0),
.probe667(0),
.probe668(0),
.probe669(0),
.probe670(0),
.probe671(0),
.probe672(0),
.probe673(0),
.probe674(0),
.probe675(0),
.probe676(0),
.probe677(0),
.probe678(0),
.probe679(0),
.probe680(0),
.probe681(0),
.probe682(0),
.probe683(0),
.probe684(0),
.probe685(0),
.probe686(0),
.probe687(0),
.probe688(0),
.probe689(0),
.probe690(0),
.probe691(0),
.probe692(0),
.probe693(0),
.probe694(0),
.probe695(0),
.probe696(0),
.probe697(0),
.probe698(0),
.probe699(0),
.probe700(0),
.probe701(0),
.probe702(0),
.probe703(0),
.probe704(0),
.probe705(0),
.probe706(0),
.probe707(0),
.probe708(0),
.probe709(0),
.probe710(0),
.probe711(0),
.probe712(0),
.probe713(0),
.probe714(0),
.probe715(0),
.probe716(0),
.probe717(0),
.probe718(0),
.probe719(0),
.probe720(0),
.probe721(0),
.probe722(0),
.probe723(0),
.probe724(0),
.probe725(0),
.probe726(0),
.probe727(0),
.probe728(0),
.probe729(0),
.probe730(0),
.probe731(0),
.probe732(0),
.probe733(0),
.probe734(0),
.probe735(0),
.probe736(0),
.probe737(0),
.probe738(0),
.probe739(0),
.probe740(0),
.probe741(0),
.probe742(0),
.probe743(0),
.probe744(0),
.probe745(0),
.probe746(0),
.probe747(0),
.probe748(0),
.probe749(0),
.probe750(0),
.probe751(0),
.probe752(0),
.probe753(0),
.probe754(0),
.probe755(0),
.probe756(0),
.probe757(0),
.probe758(0),
.probe759(0),
.probe760(0),
.probe761(0),
.probe762(0),
.probe763(0),
.probe764(0),
.probe765(0),
.probe766(0),
.probe767(0),
.probe768(0),
.probe769(0),
.probe770(0),
.probe771(0),
.probe772(0),
.probe773(0),
.probe774(0),
.probe775(0),
.probe776(0),
.probe777(0),
.probe778(0),
.probe779(0),
.probe780(0),
.probe781(0),
.probe782(0),
.probe783(0),
.probe784(0),
.probe785(0),
.probe786(0),
.probe787(0),
.probe788(0),
.probe789(0),
.probe790(0),
.probe791(0),
.probe792(0),
.probe793(0),
.probe794(0),
.probe795(0),
.probe796(0),
.probe797(0),
.probe798(0),
.probe799(0),
.probe800(0),
.probe801(0),
.probe802(0),
.probe803(0),
.probe804(0),
.probe805(0),
.probe806(0),
.probe807(0),
.probe808(0),
.probe809(0),
.probe810(0),
.probe811(0),
.probe812(0),
.probe813(0),
.probe814(0),
.probe815(0),
.probe816(0),
.probe817(0),
.probe818(0),
.probe819(0),
.probe820(0),
.probe821(0),
.probe822(0),
.probe823(0),
.probe824(0),
.probe825(0),
.probe826(0),
.probe827(0),
.probe828(0),
.probe829(0),
.probe830(0),
.probe831(0),
.probe832(0),
.probe833(0),
.probe834(0),
.probe835(0),
.probe836(0),
.probe837(0),
.probe838(0),
.probe839(0),
.probe840(0),
.probe841(0),
.probe842(0),
.probe843(0),
.probe844(0),
.probe845(0),
.probe846(0),
.probe847(0),
.probe848(0),
.probe849(0),
.probe850(0),
.probe851(0),
.probe852(0),
.probe853(0),
.probe854(0),
.probe855(0),
.probe856(0),
.probe857(0),
.probe858(0),
.probe859(0),
.probe860(0),
.probe861(0),
.probe862(0),
.probe863(0),
.probe864(0),
.probe865(0),
.probe866(0),
.probe867(0),
.probe868(0),
.probe869(0),
.probe870(0),
.probe871(0),
.probe872(0),
.probe873(0),
.probe874(0),
.probe875(0),
.probe876(0),
.probe877(0),
.probe878(0),
.probe879(0),
.probe880(0),
.probe881(0),
.probe882(0),
.probe883(0),
.probe884(0),
.probe885(0),
.probe886(0),
.probe887(0),
.probe888(0),
.probe889(0),
.probe890(0),
.probe891(0),
.probe892(0),
.probe893(0),
.probe894(0),
.probe895(0),
.probe896(0),
.probe897(0),
.probe898(0),
.probe899(0),
.probe900(0),
.probe901(0),
.probe902(0),
.probe903(0),
.probe904(0),
.probe905(0),
.probe906(0),
.probe907(0),
.probe908(0),
.probe909(0),
.probe910(0),
.probe911(0),
.probe912(0),
.probe913(0),
.probe914(0),
.probe915(0),
.probe916(0),
.probe917(0),
.probe918(0),
.probe919(0),
.probe920(0),
.probe921(0),
.probe922(0),
.probe923(0),
.probe924(0),
.probe925(0),
.probe926(0),
.probe927(0),
.probe928(0),
.probe929(0),
.probe930(0),
.probe931(0),
.probe932(0),
.probe933(0),
.probe934(0),
.probe935(0),
.probe936(0),
.probe937(0),
.probe938(0),
.probe939(0),
.probe940(0),
.probe941(0),
.probe942(0),
.probe943(0),
.probe944(0),
.probe945(0),
.probe946(0),
.probe947(0),
.probe948(0),
.probe949(0),
.probe950(0),
.probe951(0),
.probe952(0),
.probe953(0),
.probe954(0),
.probe955(0),
.probe956(0),
.probe957(0),
.probe958(0),
.probe959(0),
.probe960(0),
.probe961(0),
.probe962(0),
.probe963(0),
.probe964(0),
.probe965(0),
.probe966(0),
.probe967(0),
.probe968(0),
.probe969(0),
.probe970(0),
.probe971(0),
.probe972(0),
.probe973(0),
.probe974(0),
.probe975(0),
.probe976(0),
.probe977(0),
.probe978(0),
.probe979(0),
.probe980(0),
.probe981(0),
.probe982(0),
.probe983(0),
.probe984(0),
.probe985(0),
.probe986(0),
.probe987(0),
.probe988(0),
.probe989(0),
.probe990(0),
.probe991(0),
.probe992(0),
.probe993(0),
.probe994(0),
.probe995(0),
.probe996(0),
.probe997(0),
.probe998(0),
.probe999(0),
.probe1000(0),
.probe1001(0),
.probe1002(0),
.probe1003(0),
.probe1004(0),
.probe1005(0),
.probe1006(0),
.probe1007(0),
.probe1008(0),
.probe1009(0),
.probe1010(0),
.probe1011(0),
.probe1012(0),
.probe1013(0),
.probe1014(0),
.probe1015(0),
.probe1016(0),
.probe1017(0),
.probe1018(0),
.probe1019(0),
.probe1020(0),
.probe1021(0),
.probe1022(0),
.probe1023(0)
)/* synthesis syn_noprune=1 */;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BAI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O21BAI_PP_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BAI_PP_BLACKBOX_V
|
/*
* The MIT License (MIT)
*
* Copyright (c) 2015 Stefan Wendler
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/**
* Testbench for rcswitch_send.
*
* I use this with iverilog and gtkwave:
*
* iverilog -o rcswitch.vvp clockdiv.v rcswitch.v rcswitch_send_tb.v
* ./rcswitch_send.vvp
* gtkwace rcswitch_send.vcd
*/
module rcswitch_test;
reg [39:0] addr;
reg [39:0] chan;
reg [15:0] stat;
reg send;
initial begin
#0 addr = 40'b10001000_10001000_10001000_10001000_10001000; // 11111
#0 chan = 40'b10001000_10001110_10001110_10001110_10001110; // 0FFFF = A
#0 stat = 16'b10001110_10001000; // F0 = ON
#2 send = 1;
#100 send = 0;
#300 $finish;
end
// clock
reg clk = 0;
always #1 clk = !clk;
wire ready;
wire out;
rcswitch_send rcswitch_send_inst (
.clk(clk),
.rst(1'b0),
.send(send),
.addr(addr),
.chan(chan),
.stat(stat),
.ready(ready),
.out(out)
);
initial
begin
$dumpfile("rcswitch_send.vcd");
$dumpvars(0, rcswitch_send_inst);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:57:50 08/25/2009
// Design Name:
// Module Name: mcu_cmd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
output reg mcu_rrq = 0,
output mcu_write,
output reg mcu_wrq = 0,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [10:0] SD_DMA_PARTIAL_START,
output [10:0] SD_DMA_PARTIAL_END,
output reg SD_DMA_START_MID_BLOCK,
output reg SD_DMA_END_MID_BLOCK,
// DAC
output [10:0] dac_addr_out,
input DAC_STATUS,
output reg dac_play_out = 0,
output reg dac_reset_out = 0,
output reg [2:0] dac_vol_select_out = 3'b000,
output reg dac_palmode_out = 0,
output reg [8:0] dac_ptr_out = 0,
// MSU data
output [13:0] msu_addr_out,
input [7:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
// BS-X
output [7:0] bsx_regs_reset_out,
output [7:0] bsx_regs_set_out,
output bsx_regs_reset_we,
// generic RTC
output [55:0] rtc_data_out,
output rtc_pgm_we,
// S-RTC
output srtc_reset,
// uPD77C25
output reg [23:0] dspx_pgm_data_out,
output reg [10:0] dspx_pgm_addr_out,
output reg dspx_pgm_we_out,
output reg [15:0] dspx_dat_data_out,
output reg [10:0] dspx_dat_addr_out,
output reg dspx_dat_we_out,
output reg dspx_reset_out,
// feature enable
output reg [7:0] featurebits_out,
output reg region_out,
// SNES sync/clk
input snes_sysclk,
// snes cmd interface
input [7:0] snescmd_data_in,
output reg [7:0] snescmd_data_out,
output reg [8:0] snescmd_addr_out,
output reg snescmd_we_out,
// cheat configuration
output reg [7:0] cheat_pgm_idx_out,
output reg [31:0] cheat_pgm_data_out,
output reg cheat_pgm_we_out,
// DSP core features
output reg [15:0] dsp_feat_out = 16'h0000
);
initial begin
dspx_pgm_addr_out = 11'b00000000000;
dspx_dat_addr_out = 10'b0000000000;
dspx_reset_out = 1'b1;
region_out = 0;
SD_DMA_START_MID_BLOCK = 0;
SD_DMA_END_MID_BLOCK = 0;
end
wire [31:0] snes_sysclk_freq;
clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
reg [2:0] MAPPER_BUF;
reg [23:0] ADDR_OUT_BUF;
reg [10:0] DAC_ADDR_OUT_BUF;
reg [7:0] DAC_VOL_OUT_BUF;
reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
reg msu_status_reset_we_buf = 0;
reg MSU_RESET_OUT_BUF;
reg [7:0] bsx_regs_set_out_buf;
reg [7:0] bsx_regs_reset_out_buf;
reg bsx_regs_reset_we_buf;
reg [55:0] rtc_data_out_buf;
reg rtc_pgm_we_buf;
reg srtc_reset_buf;
initial srtc_reset_buf = 0;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
reg [7:0] MCU_DATA_OUT_BUF;
reg [7:0] MCU_DATA_IN_BUF;
reg [2:0] mcu_nextaddr_buf;
reg [7:0] dsp_feat_tmp;
wire mcu_nextaddr;
reg DAC_STATUSr;
reg SD_DMA_STATUSr;
reg [7:0] MSU_STATUSr;
always @(posedge clk) begin
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
end
reg SD_DMA_PARTIALr;
assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
reg SD_DMA_ENr;
assign SD_DMA_EN = SD_DMA_ENr;
reg [1:0] SD_DMA_TGTr;
assign SD_DMA_TGT = SD_DMA_TGTr;
reg [10:0] SD_DMA_PARTIAL_STARTr;
reg [10:0] SD_DMA_PARTIAL_ENDr;
assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
reg [23:0] SAVERAM_MASK;
reg [23:0] ROM_MASK;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
SD_DMA_ENr = 0;
MAPPER_BUF = 1;
SD_DMA_PARTIALr = 0;
end
// command interpretation
always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
dac_reset_out <= 1'b0;
MSU_RESET_OUT_BUF <= 1'b0;
if (cmd_ready) begin
case (cmd_data[7:4])
4'h3: // select mapper
MAPPER_BUF <= cmd_data[2:0];
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= 2'b00; // cmd_data[1:0]; // not implemented
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
8'h6x:
case (spi_byte_cnt)
32'h2: begin
SD_DMA_START_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
end
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4: begin
SD_DMA_END_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
end
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'hd0:
case (spi_byte_cnt)
32'h2:
snescmd_addr_out[7:0] <= param_data;
32'h3:
snescmd_addr_out[8] <= param_data[0];
endcase
8'hd1:
snescmd_addr_out <= snescmd_addr_out + 1;
8'hd2: begin
case (spi_byte_cnt)
32'h2:
snescmd_we_out <= 1'b1;
32'h3:
snescmd_addr_out <= snescmd_addr_out + 1;
endcase
snescmd_data_out <= param_data;
end
8'hd3: begin
case (spi_byte_cnt)
32'h2:
cheat_pgm_idx_out <= param_data[2:0];
32'h3:
cheat_pgm_data_out[31:24] <= param_data;
32'h4:
cheat_pgm_data_out[23:16] <= param_data;
32'h5:
cheat_pgm_data_out[15:8] <= param_data;
32'h6: begin
cheat_pgm_data_out[7:0] <= param_data;
cheat_pgm_we_out <= 1'b1;
end
endcase
end
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
8'he1: // pause DAC
dac_play_out <= 1'b0;
8'he2: // resume DAC
dac_play_out <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
case (spi_byte_cnt)
32'h2:
dac_ptr_out[8] <= param_data[0];
32'h3: begin
dac_ptr_out[7:0] <= param_data;
dac_reset_out <= 1'b1; // reset by default value, see above
end
endcase
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
endcase
8'he5:
case (spi_byte_cnt)
32'h2:
rtc_data_out_buf[55:48] <= param_data;
32'h3:
rtc_data_out_buf[47:40] <= param_data;
32'h4:
rtc_data_out_buf[39:32] <= param_data;
32'h5:
rtc_data_out_buf[31:24] <= param_data;
32'h6:
rtc_data_out_buf[23:16] <= param_data;
32'h7:
rtc_data_out_buf[15:8] <= param_data;
32'h8: begin
rtc_data_out_buf[7:0] <= param_data;
rtc_pgm_we_buf <= 1'b1;
end
32'h9:
rtc_pgm_we_buf <= 1'b0;
endcase
8'he6:
case (spi_byte_cnt)
32'h2: begin
bsx_regs_set_out_buf <= param_data[7:0];
end
32'h3: begin
bsx_regs_reset_out_buf <= param_data[7:0];
bsx_regs_reset_we_buf <= 1'b1;
end
32'h4:
bsx_regs_reset_we_buf <= 1'b0;
endcase
8'he7:
case (spi_byte_cnt)
32'h2: begin
srtc_reset_buf <= 1'b1;
end
32'h3: begin
srtc_reset_buf <= 1'b0;
end
endcase
8'he8: begin// reset DSPx PGM+DAT address
case (spi_byte_cnt)
32'h2: begin
dspx_pgm_addr_out <= 11'b00000000000;
dspx_dat_addr_out <= 10'b0000000000;
end
endcase
end
8'he9:// write DSPx PGM w/ increment
case (spi_byte_cnt)
32'h2: dspx_pgm_data_out[23:16] <= param_data[7:0];
32'h3: dspx_pgm_data_out[15:8] <= param_data[7:0];
32'h4: dspx_pgm_data_out[7:0] <= param_data[7:0];
32'h5: dspx_pgm_we_out <= 1'b1;
32'h6: begin
dspx_pgm_we_out <= 1'b0;
dspx_pgm_addr_out <= dspx_pgm_addr_out + 1;
end
endcase
8'hea:// write DSPx DAT w/ increment
case (spi_byte_cnt)
32'h2: dspx_dat_data_out[15:8] <= param_data[7:0];
32'h3: dspx_dat_data_out[7:0] <= param_data[7:0];
32'h4: dspx_dat_we_out <= 1'b1;
32'h5: begin
dspx_dat_we_out <= 1'b0;
dspx_dat_addr_out <= dspx_dat_addr_out + 1;
end
endcase
8'heb: // control DSPx reset
dspx_reset_out <= param_data[0];
8'hec:
begin // set DAC properties
dac_vol_select_out <= param_data[2:0];
dac_palmode_out <= param_data[7];
end
8'hed:
featurebits_out <= param_data;
8'hee:
region_out <= param_data[0];
8'hef:
case (spi_byte_cnt)
32'h2: dsp_feat_tmp <= param_data[7:0];
32'h3: begin
dsp_feat_out <= {dsp_feat_tmp, param_data[7:0]};
end
endcase
endcase
end
end
always @(posedge clk) begin
if(param_ready && cmd_data[7:4] == 4'h0) begin
case (cmd_data[1:0])
2'b01: begin
case (spi_byte_cnt)
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
2'b10: begin
case (spi_byte_cnt)
32'h2: begin
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
MSU_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
) begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
endcase
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
MCU_DATA_IN_BUF <= mcu_data_in;
else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
if (cmd_data[7:4] == 4'hA)
MCU_DATA_IN_BUF <= snescmd_data_in;
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[7], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {1'b0, MSU_STATUSr[6:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:0] == 8'hD1)
MCU_DATA_IN_BUF <= snescmd_data_in;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
always @(posedge clk) begin
mcu_rrq <= 1'b0;
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
mcu_rrq <= 1'b1;
end
end
always @(posedge clk) begin
mcu_wrq <= 1'b0;
if(param_ready && cmd_data[7:4] == 4'h9) begin
mcu_wrq <= 1'b1;
end
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_write = SD_DMA_STATUS
?(SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
: 1'b1
)
: 1'b1;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;
assign msu_status_reset_we = msu_status_reset_we_buf;
assign msu_status_reset_out = msu_status_reset_out_buf;
assign msu_status_set_out = msu_status_set_out_buf;
assign msu_reset_out = MSU_RESET_OUT_BUF;
assign msu_ptr_out = MSU_PTR_OUT_BUF;
assign bsx_regs_reset_we = bsx_regs_reset_we_buf;
assign bsx_regs_reset_out = bsx_regs_reset_out_buf;
assign bsx_regs_set_out = bsx_regs_set_out_buf;
assign rtc_data_out = rtc_data_out_buf;
assign rtc_pgm_we = rtc_pgm_we_buf;
assign srtc_reset = srtc_reset_buf;
assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
assign mcu_mapper = MAPPER_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
assign DBG_mcu_nextaddr = mcu_nextaddr;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD3_BEHAVIORAL_PP_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd3 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD3_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
///////////////// ** trim_dac_ctrl ** ////////////////////////////////////////
//
// Logic to control the LTC2624-1 trim DACs
//
// The 9 12-bit DAC outputs are stored in a LUT. Note the LUT is nominally 16 lots of
// 14-bit values: ignore the higher addresses and the MS 2 bits of each entry
//
// The LUT is loaded via the uart_decoder in the same way as the FB gain luts
//
// The FONT 5 board has 3 trim DAC chips each with 4 DACs (A,B,C,D) each.
// The chips are in series, and are loaded by transmitting serial data.
// DAC A is loaded on all chips first, then DAC B, then DAC C. D is unused
//
// Chip 1 is connected to channels 1-3, 2 to 4-5 and 3 to 7-9
//
// When the ld_dacs strobe goes high synchronous to clk (40MHz), 3x 32-bit shift regs
// are loaded with the following pattern:
//
// X X C A D D D X [Each character is 4-bits]
//
// Where: X = Don't care (4'b0000)
// C = Command (always 4'b0011, which writes to and updates specified DAC)
// A = Currenct DAC addr (A = 0000, B = 0001, C = 0010, D = 0011)
// D = 12 data bits from LUT
//
// The shift regs are in series and the three bit patterns are transmitted to the DAC
// chain. Once all three DAC A's have been updated, then the shift regs are reloaded
// and all DAC B's are updated, then all DAC C's
module trim_dac_ctrl (
input clk40,
input rst,
input [6:0] lut_in,
input [4:0] lut_addr,
input lut_we,
input load_dacs,
output serial_out,
output clk_out,
output enable_out
);
/*input clk40;
input rst;
input [6:0] lut_in;
input [4:0] lut_addr;
input lut_we;
input load_dacs;
output serial_out;
output clk_out;
output enable_out;
*/
// Instantiate LUT
wire [13:0] lut_out;
reg [3:0] lut_out_addr;
dp_lut_7x5_14x4 trim_lut (
.clk(clk40),
.din_a(lut_in),
.we_a(lut_we),
.addr_a(lut_addr),
.dout_b(lut_out),
.addr_b(lut_out_addr)
);
reg clk20A, clk20B;
// Instantiate the 3 shift registers
reg [3:0] dac_addr;
reg shift_en;
reg shreg1_ld_en, shreg2_ld_en, shreg3_ld_en;
wire [31:0] shreg_pin;
wire shreg1_out, shreg2_out;
shift_reg_32 shreg1(
.clk(clk20A),
.p_load(shreg1_ld_en),
.p_data(shreg_pin),
.s_in(1'b0),
.s_out(shreg1_out),
.shift_en(shift_en)
);
shift_reg_32 shreg2(
.clk(clk20A),
.p_load(shreg2_ld_en),
.p_data(shreg_pin),
.s_in(shreg1_out),
.s_out(shreg2_out),
.shift_en(shift_en)
);
shift_reg_32 shreg3(
.clk(clk20A),
.p_load(shreg3_ld_en),
.p_data(shreg_pin),
.s_in(shreg2_out),
.s_out(serial_out),
.shift_en(shift_en)
);
// Form shift reg parallel input
assign shreg_pin = {8'b0, 4'b0011, dac_addr, lut_out[11:0], 4'b0};
// Assign DAC chip clock. 180 deg. phase shift so rising edge is in the middle
// of serial out data bits. Only output when DAC chips enabled
reg clk_mask;
assign clk_out = (clk_mask & ~clk20A);
// The DAC chip enable is active low. Require it to stay active one cycle longer
// than the shift enable, and also activate one earlier, so use extra cycle regs
reg early_cycle, late_cycle;
assign enable_out = ~(shift_en | early_cycle | late_cycle);
//Divide te 40MHz and generate two clocks in quadrature
//One phase A clock shregs and, inverted, clocks DAC chips
//Other phase generates enables to avoid edge transitions
always @(posedge clk40) begin
if (rst) begin
clk20A <= 0;
end else begin
clk20A <= ~clk20A;
end
end
always @(negedge clk40) begin
if (rst) begin
clk20B <= 0;
end else begin
clk20B <= ~clk20B;
end
end
// Create mask to stop DAC chip clock
always @(posedge clk20A) begin
if (rst) begin
clk_mask <= 0;
end else begin
if (shift_en | early_cycle) begin
clk_mask <= 1;
end else begin
clk_mask <= 0;
end
end
end
// Extend synchronous trigger in order to ensure the divided clock spots it
reg trig_a, trig_b;
wire long_trig;
always @(posedge clk40) begin
trig_a <= load_dacs;
trig_b <= trig_a;
end
assign long_trig = trig_a | trig_b;
// Wait for load_dacs synchronous trigger, then begin to step through a state machine
// The machine first loads the 3 shregs with DAC A values for each chip, i.e channels
// 1, 4 & 7
reg [8:0] state_count;
always @(negedge clk20B) begin
if (rst) begin
shift_en <= 0;
state_count <= 0;
shreg1_ld_en <= 0;
shreg2_ld_en <= 0;
shreg3_ld_en <= 0;
early_cycle <= 0;
late_cycle <= 0;
end else begin
early_cycle <= 0;
late_cycle <= 0;
if (long_trig) begin
//Start state machine
state_count <= 9'd1;
end else begin
state_count <= state_count + 1;
case (state_count)
9'd0: state_count <= 0;
9'd1: begin
//Specify address of dac A for all chips
dac_addr <= 4'b0000;
//Load shreg1 with ch7 dac code
lut_out_addr <= 4'd0;
shreg1_ld_en <= 1;
end
9'd2: begin
//Load shreg2 with ch4 dac code
shreg1_ld_en <= 0;
lut_out_addr <= 4'd1;
shreg2_ld_en <= 1;
end
9'd3: begin
//Load shreg3 with ch1 dac code
shreg2_ld_en <= 0;
lut_out_addr <= 4'd2;
shreg3_ld_en <= 1;
end
9'd4: begin
//shregs loaded
shreg3_ld_en <= 0;
//Begin enabling DAC chips
early_cycle <= 1;
end
9'd5: begin
//Enable shift register data to be shifted out onto DAC chips
shift_en <= 1;
end
9'd100: begin
//All data shifted out of shregs onto DAC chips
shift_en <= 0; // [updates dacs]
late_cycle <= 1;
end
9'd101: begin
//Specify address of dac B for all chips
dac_addr <= 4'b0001;
//Load shreg1 with ch8 dac code
lut_out_addr <= 4'd3;
shreg1_ld_en <= 1;
end
9'd102: begin
//Load shreg2 with ch5 dac code
shreg1_ld_en <= 0;
lut_out_addr <= 4'd4;
shreg2_ld_en <= 1;
end
9'd103: begin
//Load shreg3 with ch2 dac code
shreg2_ld_en <= 0;
lut_out_addr <= 4'd5;
shreg3_ld_en <= 1;
end
9'd104: begin
//shregs loaded
shreg3_ld_en <= 0;
//Begin enabling DAC chips
early_cycle <= 1;
end
9'd105: begin
//Enable shift register data to be shifted out onto DAC chips
shift_en <= 1;
end
9'd200: begin
//All data shifted out of shregs onto DAC chips
shift_en <= 0; // [updates dacs]
late_cycle <= 1;
end
9'd201: begin
//Specify address of dac C for all chips
dac_addr <= 4'b0010;
//Load shreg1 with ch9 dac code
lut_out_addr <= 4'd6;
shreg1_ld_en <= 1;
end
9'd202: begin
//Load shreg2 with ch6 dac code
shreg1_ld_en <= 0;
lut_out_addr <= 4'd7;
shreg2_ld_en <= 1;
end
9'd203: begin
//Load shreg3 with ch3 dac code
shreg2_ld_en <= 0;
lut_out_addr <= 4'd8;
shreg3_ld_en <= 1;
end
9'd204: begin
//shregs loaded
shreg3_ld_en <= 0;
//Begin enabling DAC chips
early_cycle <= 1;
end
9'd205: begin
//Enable shift register data to be shifted out onto DAC chips
shift_en <= 1;
end
9'd300: begin
//All data shifted out of shregs onto DAC chips
shift_en <= 0; // [updates dacs]
late_cycle <= 1;
state_count <= 0;
end
endcase
end
end
end
endmodule
///////////////// ** dp_lut_7x5_14x4 ** ////////////////////////////////////////
//
// Simple dual port LUT. Takes 32 7-bit values input and outputs 16 14-bit values
// Port A takes in 7-bit values addr 0-31
// Port B outputs 14-bit values, for example B(0) = {A(1), A(0)}
module dp_lut_7x5_14x4 (
clk,
din_a,
we_a,
addr_a,
dout_b,
addr_b
);
input clk;
input we_a;
input [4:0] addr_a;
input [6:0] din_a;
input [3:0] addr_b;
output [13:0] dout_b;
reg [6:0] lut [0:31];
//Write routine
always @(posedge clk) begin
if (we_a) begin
lut[addr_a] <= din_a;
end
end
//Output
assign dout_b = {lut[2*addr_b + 1], lut[2*addr_b]};
endmodule
///////////////// ** shift_reg_32 ** //////////////////////////////////////////
//
// 32 bit parallel-loadable shift register
//
module shift_reg_32 (
clk,
p_load,
p_data,
s_in,
s_out,
shift_en
);
input clk;
input s_in;
input p_load;
input [31:0] p_data;
input shift_en;
output s_out;
reg [31:0] shreg;
always @(posedge clk) begin
if (p_load) begin
shreg = p_data;
end else begin
if (shift_en) begin
shreg = {shreg[30:0], s_in};
end
end
end
assign s_out = shreg[31];
endmodule
|
// system_acl_iface_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.28.12:23:11
`timescale 1 ps / 1 ps
module system_acl_iface_mm_interconnect_0 (
input wire [11:0] hps_h2f_lw_axi_master_awid, // hps_h2f_lw_axi_master.awid
input wire [20:0] hps_h2f_lw_axi_master_awaddr, // .awaddr
input wire [3:0] hps_h2f_lw_axi_master_awlen, // .awlen
input wire [2:0] hps_h2f_lw_axi_master_awsize, // .awsize
input wire [1:0] hps_h2f_lw_axi_master_awburst, // .awburst
input wire [1:0] hps_h2f_lw_axi_master_awlock, // .awlock
input wire [3:0] hps_h2f_lw_axi_master_awcache, // .awcache
input wire [2:0] hps_h2f_lw_axi_master_awprot, // .awprot
input wire hps_h2f_lw_axi_master_awvalid, // .awvalid
output wire hps_h2f_lw_axi_master_awready, // .awready
input wire [11:0] hps_h2f_lw_axi_master_wid, // .wid
input wire [31:0] hps_h2f_lw_axi_master_wdata, // .wdata
input wire [3:0] hps_h2f_lw_axi_master_wstrb, // .wstrb
input wire hps_h2f_lw_axi_master_wlast, // .wlast
input wire hps_h2f_lw_axi_master_wvalid, // .wvalid
output wire hps_h2f_lw_axi_master_wready, // .wready
output wire [11:0] hps_h2f_lw_axi_master_bid, // .bid
output wire [1:0] hps_h2f_lw_axi_master_bresp, // .bresp
output wire hps_h2f_lw_axi_master_bvalid, // .bvalid
input wire hps_h2f_lw_axi_master_bready, // .bready
input wire [11:0] hps_h2f_lw_axi_master_arid, // .arid
input wire [20:0] hps_h2f_lw_axi_master_araddr, // .araddr
input wire [3:0] hps_h2f_lw_axi_master_arlen, // .arlen
input wire [2:0] hps_h2f_lw_axi_master_arsize, // .arsize
input wire [1:0] hps_h2f_lw_axi_master_arburst, // .arburst
input wire [1:0] hps_h2f_lw_axi_master_arlock, // .arlock
input wire [3:0] hps_h2f_lw_axi_master_arcache, // .arcache
input wire [2:0] hps_h2f_lw_axi_master_arprot, // .arprot
input wire hps_h2f_lw_axi_master_arvalid, // .arvalid
output wire hps_h2f_lw_axi_master_arready, // .arready
output wire [11:0] hps_h2f_lw_axi_master_rid, // .rid
output wire [31:0] hps_h2f_lw_axi_master_rdata, // .rdata
output wire [1:0] hps_h2f_lw_axi_master_rresp, // .rresp
output wire hps_h2f_lw_axi_master_rlast, // .rlast
output wire hps_h2f_lw_axi_master_rvalid, // .rvalid
input wire hps_h2f_lw_axi_master_rready, // .rready
input wire config_clk_out_clk_clk, // config_clk_out_clk.clk
input wire hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
input wire version_id_clk_reset_reset_bridge_in_reset_reset, // version_id_clk_reset_reset_bridge_in_reset.reset
output wire [10:0] acl_kernel_clk_ctrl_address, // acl_kernel_clk_ctrl.address
output wire acl_kernel_clk_ctrl_write, // .write
output wire acl_kernel_clk_ctrl_read, // .read
input wire [31:0] acl_kernel_clk_ctrl_readdata, // .readdata
output wire [31:0] acl_kernel_clk_ctrl_writedata, // .writedata
output wire [0:0] acl_kernel_clk_ctrl_burstcount, // .burstcount
output wire [3:0] acl_kernel_clk_ctrl_byteenable, // .byteenable
input wire acl_kernel_clk_ctrl_readdatavalid, // .readdatavalid
input wire acl_kernel_clk_ctrl_waitrequest, // .waitrequest
output wire acl_kernel_clk_ctrl_debugaccess, // .debugaccess
output wire [13:0] acl_kernel_interface_kernel_cntrl_address, // acl_kernel_interface_kernel_cntrl.address
output wire acl_kernel_interface_kernel_cntrl_write, // .write
output wire acl_kernel_interface_kernel_cntrl_read, // .read
input wire [31:0] acl_kernel_interface_kernel_cntrl_readdata, // .readdata
output wire [31:0] acl_kernel_interface_kernel_cntrl_writedata, // .writedata
output wire [0:0] acl_kernel_interface_kernel_cntrl_burstcount, // .burstcount
output wire [3:0] acl_kernel_interface_kernel_cntrl_byteenable, // .byteenable
input wire acl_kernel_interface_kernel_cntrl_readdatavalid, // .readdatavalid
input wire acl_kernel_interface_kernel_cntrl_waitrequest, // .waitrequest
output wire acl_kernel_interface_kernel_cntrl_debugaccess, // .debugaccess
output wire version_id_s_read, // version_id_s.read
input wire [31:0] version_id_s_readdata // .readdata
);
wire version_id_s_agent_m0_waitrequest; // version_id_s_translator:uav_waitrequest -> version_id_s_agent:m0_waitrequest
wire [2:0] version_id_s_agent_m0_burstcount; // version_id_s_agent:m0_burstcount -> version_id_s_translator:uav_burstcount
wire [31:0] version_id_s_agent_m0_writedata; // version_id_s_agent:m0_writedata -> version_id_s_translator:uav_writedata
wire [20:0] version_id_s_agent_m0_address; // version_id_s_agent:m0_address -> version_id_s_translator:uav_address
wire version_id_s_agent_m0_write; // version_id_s_agent:m0_write -> version_id_s_translator:uav_write
wire version_id_s_agent_m0_lock; // version_id_s_agent:m0_lock -> version_id_s_translator:uav_lock
wire version_id_s_agent_m0_read; // version_id_s_agent:m0_read -> version_id_s_translator:uav_read
wire [31:0] version_id_s_agent_m0_readdata; // version_id_s_translator:uav_readdata -> version_id_s_agent:m0_readdata
wire version_id_s_agent_m0_readdatavalid; // version_id_s_translator:uav_readdatavalid -> version_id_s_agent:m0_readdatavalid
wire version_id_s_agent_m0_debugaccess; // version_id_s_agent:m0_debugaccess -> version_id_s_translator:uav_debugaccess
wire [3:0] version_id_s_agent_m0_byteenable; // version_id_s_agent:m0_byteenable -> version_id_s_translator:uav_byteenable
wire version_id_s_agent_rf_source_endofpacket; // version_id_s_agent:rf_source_endofpacket -> version_id_s_agent_rsp_fifo:in_endofpacket
wire version_id_s_agent_rf_source_valid; // version_id_s_agent:rf_source_valid -> version_id_s_agent_rsp_fifo:in_valid
wire version_id_s_agent_rf_source_startofpacket; // version_id_s_agent:rf_source_startofpacket -> version_id_s_agent_rsp_fifo:in_startofpacket
wire [114:0] version_id_s_agent_rf_source_data; // version_id_s_agent:rf_source_data -> version_id_s_agent_rsp_fifo:in_data
wire version_id_s_agent_rf_source_ready; // version_id_s_agent_rsp_fifo:in_ready -> version_id_s_agent:rf_source_ready
wire version_id_s_agent_rsp_fifo_out_endofpacket; // version_id_s_agent_rsp_fifo:out_endofpacket -> version_id_s_agent:rf_sink_endofpacket
wire version_id_s_agent_rsp_fifo_out_valid; // version_id_s_agent_rsp_fifo:out_valid -> version_id_s_agent:rf_sink_valid
wire version_id_s_agent_rsp_fifo_out_startofpacket; // version_id_s_agent_rsp_fifo:out_startofpacket -> version_id_s_agent:rf_sink_startofpacket
wire [114:0] version_id_s_agent_rsp_fifo_out_data; // version_id_s_agent_rsp_fifo:out_data -> version_id_s_agent:rf_sink_data
wire version_id_s_agent_rsp_fifo_out_ready; // version_id_s_agent:rf_sink_ready -> version_id_s_agent_rsp_fifo:out_ready
wire version_id_s_agent_rdata_fifo_src_valid; // version_id_s_agent:rdata_fifo_src_valid -> version_id_s_agent_rdata_fifo:in_valid
wire [33:0] version_id_s_agent_rdata_fifo_src_data; // version_id_s_agent:rdata_fifo_src_data -> version_id_s_agent_rdata_fifo:in_data
wire version_id_s_agent_rdata_fifo_src_ready; // version_id_s_agent_rdata_fifo:in_ready -> version_id_s_agent:rdata_fifo_src_ready
wire version_id_s_agent_rdata_fifo_out_valid; // version_id_s_agent_rdata_fifo:out_valid -> version_id_s_agent:rdata_fifo_sink_valid
wire [33:0] version_id_s_agent_rdata_fifo_out_data; // version_id_s_agent_rdata_fifo:out_data -> version_id_s_agent:rdata_fifo_sink_data
wire version_id_s_agent_rdata_fifo_out_ready; // version_id_s_agent:rdata_fifo_sink_ready -> version_id_s_agent_rdata_fifo:out_ready
wire acl_kernel_interface_kernel_cntrl_agent_m0_waitrequest; // acl_kernel_interface_kernel_cntrl_translator:uav_waitrequest -> acl_kernel_interface_kernel_cntrl_agent:m0_waitrequest
wire [2:0] acl_kernel_interface_kernel_cntrl_agent_m0_burstcount; // acl_kernel_interface_kernel_cntrl_agent:m0_burstcount -> acl_kernel_interface_kernel_cntrl_translator:uav_burstcount
wire [31:0] acl_kernel_interface_kernel_cntrl_agent_m0_writedata; // acl_kernel_interface_kernel_cntrl_agent:m0_writedata -> acl_kernel_interface_kernel_cntrl_translator:uav_writedata
wire [20:0] acl_kernel_interface_kernel_cntrl_agent_m0_address; // acl_kernel_interface_kernel_cntrl_agent:m0_address -> acl_kernel_interface_kernel_cntrl_translator:uav_address
wire acl_kernel_interface_kernel_cntrl_agent_m0_write; // acl_kernel_interface_kernel_cntrl_agent:m0_write -> acl_kernel_interface_kernel_cntrl_translator:uav_write
wire acl_kernel_interface_kernel_cntrl_agent_m0_lock; // acl_kernel_interface_kernel_cntrl_agent:m0_lock -> acl_kernel_interface_kernel_cntrl_translator:uav_lock
wire acl_kernel_interface_kernel_cntrl_agent_m0_read; // acl_kernel_interface_kernel_cntrl_agent:m0_read -> acl_kernel_interface_kernel_cntrl_translator:uav_read
wire [31:0] acl_kernel_interface_kernel_cntrl_agent_m0_readdata; // acl_kernel_interface_kernel_cntrl_translator:uav_readdata -> acl_kernel_interface_kernel_cntrl_agent:m0_readdata
wire acl_kernel_interface_kernel_cntrl_agent_m0_readdatavalid; // acl_kernel_interface_kernel_cntrl_translator:uav_readdatavalid -> acl_kernel_interface_kernel_cntrl_agent:m0_readdatavalid
wire acl_kernel_interface_kernel_cntrl_agent_m0_debugaccess; // acl_kernel_interface_kernel_cntrl_agent:m0_debugaccess -> acl_kernel_interface_kernel_cntrl_translator:uav_debugaccess
wire [3:0] acl_kernel_interface_kernel_cntrl_agent_m0_byteenable; // acl_kernel_interface_kernel_cntrl_agent:m0_byteenable -> acl_kernel_interface_kernel_cntrl_translator:uav_byteenable
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_endofpacket; // acl_kernel_interface_kernel_cntrl_agent:rf_source_endofpacket -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_endofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_valid; // acl_kernel_interface_kernel_cntrl_agent:rf_source_valid -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_valid
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_startofpacket; // acl_kernel_interface_kernel_cntrl_agent:rf_source_startofpacket -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_startofpacket
wire [114:0] acl_kernel_interface_kernel_cntrl_agent_rf_source_data; // acl_kernel_interface_kernel_cntrl_agent:rf_source_data -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_data
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_ready; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_ready -> acl_kernel_interface_kernel_cntrl_agent:rf_source_ready
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_endofpacket; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_endofpacket -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_endofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_valid; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_valid -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_valid
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_startofpacket; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_startofpacket -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_startofpacket
wire [114:0] acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_data; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_data -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_data
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_ready; // acl_kernel_interface_kernel_cntrl_agent:rf_sink_ready -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_ready
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_valid; // acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_src_valid -> acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:in_valid
wire [33:0] acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_data; // acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_src_data -> acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:in_data
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_ready; // acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:in_ready -> acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_src_ready
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_valid; // acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:out_valid -> acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_sink_valid
wire [33:0] acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_data; // acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:out_data -> acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_sink_data
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_ready; // acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_sink_ready -> acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:out_ready
wire acl_kernel_clk_ctrl_agent_m0_waitrequest; // acl_kernel_clk_ctrl_translator:uav_waitrequest -> acl_kernel_clk_ctrl_agent:m0_waitrequest
wire [2:0] acl_kernel_clk_ctrl_agent_m0_burstcount; // acl_kernel_clk_ctrl_agent:m0_burstcount -> acl_kernel_clk_ctrl_translator:uav_burstcount
wire [31:0] acl_kernel_clk_ctrl_agent_m0_writedata; // acl_kernel_clk_ctrl_agent:m0_writedata -> acl_kernel_clk_ctrl_translator:uav_writedata
wire [20:0] acl_kernel_clk_ctrl_agent_m0_address; // acl_kernel_clk_ctrl_agent:m0_address -> acl_kernel_clk_ctrl_translator:uav_address
wire acl_kernel_clk_ctrl_agent_m0_write; // acl_kernel_clk_ctrl_agent:m0_write -> acl_kernel_clk_ctrl_translator:uav_write
wire acl_kernel_clk_ctrl_agent_m0_lock; // acl_kernel_clk_ctrl_agent:m0_lock -> acl_kernel_clk_ctrl_translator:uav_lock
wire acl_kernel_clk_ctrl_agent_m0_read; // acl_kernel_clk_ctrl_agent:m0_read -> acl_kernel_clk_ctrl_translator:uav_read
wire [31:0] acl_kernel_clk_ctrl_agent_m0_readdata; // acl_kernel_clk_ctrl_translator:uav_readdata -> acl_kernel_clk_ctrl_agent:m0_readdata
wire acl_kernel_clk_ctrl_agent_m0_readdatavalid; // acl_kernel_clk_ctrl_translator:uav_readdatavalid -> acl_kernel_clk_ctrl_agent:m0_readdatavalid
wire acl_kernel_clk_ctrl_agent_m0_debugaccess; // acl_kernel_clk_ctrl_agent:m0_debugaccess -> acl_kernel_clk_ctrl_translator:uav_debugaccess
wire [3:0] acl_kernel_clk_ctrl_agent_m0_byteenable; // acl_kernel_clk_ctrl_agent:m0_byteenable -> acl_kernel_clk_ctrl_translator:uav_byteenable
wire acl_kernel_clk_ctrl_agent_rf_source_endofpacket; // acl_kernel_clk_ctrl_agent:rf_source_endofpacket -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_endofpacket
wire acl_kernel_clk_ctrl_agent_rf_source_valid; // acl_kernel_clk_ctrl_agent:rf_source_valid -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_valid
wire acl_kernel_clk_ctrl_agent_rf_source_startofpacket; // acl_kernel_clk_ctrl_agent:rf_source_startofpacket -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_startofpacket
wire [114:0] acl_kernel_clk_ctrl_agent_rf_source_data; // acl_kernel_clk_ctrl_agent:rf_source_data -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_data
wire acl_kernel_clk_ctrl_agent_rf_source_ready; // acl_kernel_clk_ctrl_agent_rsp_fifo:in_ready -> acl_kernel_clk_ctrl_agent:rf_source_ready
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_endofpacket; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_endofpacket -> acl_kernel_clk_ctrl_agent:rf_sink_endofpacket
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_valid; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_valid -> acl_kernel_clk_ctrl_agent:rf_sink_valid
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_startofpacket; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_startofpacket -> acl_kernel_clk_ctrl_agent:rf_sink_startofpacket
wire [114:0] acl_kernel_clk_ctrl_agent_rsp_fifo_out_data; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_data -> acl_kernel_clk_ctrl_agent:rf_sink_data
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_ready; // acl_kernel_clk_ctrl_agent:rf_sink_ready -> acl_kernel_clk_ctrl_agent_rsp_fifo:out_ready
wire acl_kernel_clk_ctrl_agent_rdata_fifo_src_valid; // acl_kernel_clk_ctrl_agent:rdata_fifo_src_valid -> acl_kernel_clk_ctrl_agent_rdata_fifo:in_valid
wire [33:0] acl_kernel_clk_ctrl_agent_rdata_fifo_src_data; // acl_kernel_clk_ctrl_agent:rdata_fifo_src_data -> acl_kernel_clk_ctrl_agent_rdata_fifo:in_data
wire acl_kernel_clk_ctrl_agent_rdata_fifo_src_ready; // acl_kernel_clk_ctrl_agent_rdata_fifo:in_ready -> acl_kernel_clk_ctrl_agent:rdata_fifo_src_ready
wire acl_kernel_clk_ctrl_agent_rdata_fifo_out_valid; // acl_kernel_clk_ctrl_agent_rdata_fifo:out_valid -> acl_kernel_clk_ctrl_agent:rdata_fifo_sink_valid
wire [33:0] acl_kernel_clk_ctrl_agent_rdata_fifo_out_data; // acl_kernel_clk_ctrl_agent_rdata_fifo:out_data -> acl_kernel_clk_ctrl_agent:rdata_fifo_sink_data
wire acl_kernel_clk_ctrl_agent_rdata_fifo_out_ready; // acl_kernel_clk_ctrl_agent:rdata_fifo_sink_ready -> acl_kernel_clk_ctrl_agent_rdata_fifo:out_ready
wire hps_h2f_lw_axi_master_agent_write_cp_endofpacket; // hps_h2f_lw_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
wire hps_h2f_lw_axi_master_agent_write_cp_valid; // hps_h2f_lw_axi_master_agent:write_cp_valid -> router:sink_valid
wire hps_h2f_lw_axi_master_agent_write_cp_startofpacket; // hps_h2f_lw_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
wire [113:0] hps_h2f_lw_axi_master_agent_write_cp_data; // hps_h2f_lw_axi_master_agent:write_cp_data -> router:sink_data
wire hps_h2f_lw_axi_master_agent_write_cp_ready; // router:sink_ready -> hps_h2f_lw_axi_master_agent:write_cp_ready
wire hps_h2f_lw_axi_master_agent_read_cp_endofpacket; // hps_h2f_lw_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
wire hps_h2f_lw_axi_master_agent_read_cp_valid; // hps_h2f_lw_axi_master_agent:read_cp_valid -> router_001:sink_valid
wire hps_h2f_lw_axi_master_agent_read_cp_startofpacket; // hps_h2f_lw_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
wire [113:0] hps_h2f_lw_axi_master_agent_read_cp_data; // hps_h2f_lw_axi_master_agent:read_cp_data -> router_001:sink_data
wire hps_h2f_lw_axi_master_agent_read_cp_ready; // router_001:sink_ready -> hps_h2f_lw_axi_master_agent:read_cp_ready
wire version_id_s_agent_rp_endofpacket; // version_id_s_agent:rp_endofpacket -> router_002:sink_endofpacket
wire version_id_s_agent_rp_valid; // version_id_s_agent:rp_valid -> router_002:sink_valid
wire version_id_s_agent_rp_startofpacket; // version_id_s_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [113:0] version_id_s_agent_rp_data; // version_id_s_agent:rp_data -> router_002:sink_data
wire version_id_s_agent_rp_ready; // router_002:sink_ready -> version_id_s_agent:rp_ready
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire [113:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire [2:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire acl_kernel_interface_kernel_cntrl_agent_rp_endofpacket; // acl_kernel_interface_kernel_cntrl_agent:rp_endofpacket -> router_003:sink_endofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rp_valid; // acl_kernel_interface_kernel_cntrl_agent:rp_valid -> router_003:sink_valid
wire acl_kernel_interface_kernel_cntrl_agent_rp_startofpacket; // acl_kernel_interface_kernel_cntrl_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [113:0] acl_kernel_interface_kernel_cntrl_agent_rp_data; // acl_kernel_interface_kernel_cntrl_agent:rp_data -> router_003:sink_data
wire acl_kernel_interface_kernel_cntrl_agent_rp_ready; // router_003:sink_ready -> acl_kernel_interface_kernel_cntrl_agent:rp_ready
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire [113:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire [2:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire acl_kernel_clk_ctrl_agent_rp_endofpacket; // acl_kernel_clk_ctrl_agent:rp_endofpacket -> router_004:sink_endofpacket
wire acl_kernel_clk_ctrl_agent_rp_valid; // acl_kernel_clk_ctrl_agent:rp_valid -> router_004:sink_valid
wire acl_kernel_clk_ctrl_agent_rp_startofpacket; // acl_kernel_clk_ctrl_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [113:0] acl_kernel_clk_ctrl_agent_rp_data; // acl_kernel_clk_ctrl_agent:rp_data -> router_004:sink_data
wire acl_kernel_clk_ctrl_agent_rp_ready; // router_004:sink_ready -> acl_kernel_clk_ctrl_agent:rp_ready
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire [113:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire [2:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire router_src_endofpacket; // router:src_endofpacket -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_endofpacket
wire router_src_valid; // router:src_valid -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_startofpacket
wire [113:0] router_src_data; // router:src_data -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_data
wire [2:0] router_src_channel; // router:src_channel -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_channel
wire router_src_ready; // hps_h2f_lw_axi_master_wr_limiter:cmd_sink_ready -> router:src_ready
wire hps_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire hps_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire [113:0] hps_h2f_lw_axi_master_wr_limiter_cmd_src_data; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_data -> cmd_demux:sink_data
wire [2:0] hps_h2f_lw_axi_master_wr_limiter_cmd_src_channel; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire hps_h2f_lw_axi_master_wr_limiter_cmd_src_ready; // cmd_demux:sink_ready -> hps_h2f_lw_axi_master_wr_limiter:cmd_src_ready
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_startofpacket
wire [113:0] rsp_mux_src_data; // rsp_mux:src_data -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_data
wire [2:0] rsp_mux_src_channel; // rsp_mux:src_channel -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_channel
wire rsp_mux_src_ready; // hps_h2f_lw_axi_master_wr_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_endofpacket -> hps_h2f_lw_axi_master_agent:write_rp_endofpacket
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_valid; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_valid -> hps_h2f_lw_axi_master_agent:write_rp_valid
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_startofpacket -> hps_h2f_lw_axi_master_agent:write_rp_startofpacket
wire [113:0] hps_h2f_lw_axi_master_wr_limiter_rsp_src_data; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_data -> hps_h2f_lw_axi_master_agent:write_rp_data
wire [2:0] hps_h2f_lw_axi_master_wr_limiter_rsp_src_channel; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_channel -> hps_h2f_lw_axi_master_agent:write_rp_channel
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_ready; // hps_h2f_lw_axi_master_agent:write_rp_ready -> hps_h2f_lw_axi_master_wr_limiter:rsp_src_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_startofpacket
wire [113:0] router_001_src_data; // router_001:src_data -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_data
wire [2:0] router_001_src_channel; // router_001:src_channel -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_channel
wire router_001_src_ready; // hps_h2f_lw_axi_master_rd_limiter:cmd_sink_ready -> router_001:src_ready
wire hps_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire hps_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire [113:0] hps_h2f_lw_axi_master_rd_limiter_cmd_src_data; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire [2:0] hps_h2f_lw_axi_master_rd_limiter_cmd_src_channel; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire hps_h2f_lw_axi_master_rd_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> hps_h2f_lw_axi_master_rd_limiter:cmd_src_ready
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_valid
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_startofpacket
wire [113:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_data
wire [2:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_channel
wire rsp_mux_001_src_ready; // hps_h2f_lw_axi_master_rd_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_endofpacket -> hps_h2f_lw_axi_master_agent:read_rp_endofpacket
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_valid; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_valid -> hps_h2f_lw_axi_master_agent:read_rp_valid
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_startofpacket -> hps_h2f_lw_axi_master_agent:read_rp_startofpacket
wire [113:0] hps_h2f_lw_axi_master_rd_limiter_rsp_src_data; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_data -> hps_h2f_lw_axi_master_agent:read_rp_data
wire [2:0] hps_h2f_lw_axi_master_rd_limiter_rsp_src_channel; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_channel -> hps_h2f_lw_axi_master_agent:read_rp_channel
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_ready; // hps_h2f_lw_axi_master_agent:read_rp_ready -> hps_h2f_lw_axi_master_rd_limiter:rsp_src_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> version_id_s_burst_adapter:sink0_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> version_id_s_burst_adapter:sink0_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> version_id_s_burst_adapter:sink0_startofpacket
wire [113:0] cmd_mux_src_data; // cmd_mux:src_data -> version_id_s_burst_adapter:sink0_data
wire [2:0] cmd_mux_src_channel; // cmd_mux:src_channel -> version_id_s_burst_adapter:sink0_channel
wire cmd_mux_src_ready; // version_id_s_burst_adapter:sink0_ready -> cmd_mux:src_ready
wire version_id_s_burst_adapter_source0_endofpacket; // version_id_s_burst_adapter:source0_endofpacket -> version_id_s_agent:cp_endofpacket
wire version_id_s_burst_adapter_source0_valid; // version_id_s_burst_adapter:source0_valid -> version_id_s_agent:cp_valid
wire version_id_s_burst_adapter_source0_startofpacket; // version_id_s_burst_adapter:source0_startofpacket -> version_id_s_agent:cp_startofpacket
wire [113:0] version_id_s_burst_adapter_source0_data; // version_id_s_burst_adapter:source0_data -> version_id_s_agent:cp_data
wire version_id_s_burst_adapter_source0_ready; // version_id_s_agent:cp_ready -> version_id_s_burst_adapter:source0_ready
wire [2:0] version_id_s_burst_adapter_source0_channel; // version_id_s_burst_adapter:source0_channel -> version_id_s_agent:cp_channel
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_startofpacket
wire [113:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_data
wire [2:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_channel
wire cmd_mux_001_src_ready; // acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_endofpacket; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_endofpacket -> acl_kernel_interface_kernel_cntrl_agent:cp_endofpacket
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_valid; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_valid -> acl_kernel_interface_kernel_cntrl_agent:cp_valid
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_startofpacket; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_startofpacket -> acl_kernel_interface_kernel_cntrl_agent:cp_startofpacket
wire [113:0] acl_kernel_interface_kernel_cntrl_burst_adapter_source0_data; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_data -> acl_kernel_interface_kernel_cntrl_agent:cp_data
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_ready; // acl_kernel_interface_kernel_cntrl_agent:cp_ready -> acl_kernel_interface_kernel_cntrl_burst_adapter:source0_ready
wire [2:0] acl_kernel_interface_kernel_cntrl_burst_adapter_source0_channel; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_channel -> acl_kernel_interface_kernel_cntrl_agent:cp_channel
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> acl_kernel_clk_ctrl_burst_adapter:sink0_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> acl_kernel_clk_ctrl_burst_adapter:sink0_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> acl_kernel_clk_ctrl_burst_adapter:sink0_startofpacket
wire [113:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> acl_kernel_clk_ctrl_burst_adapter:sink0_data
wire [2:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> acl_kernel_clk_ctrl_burst_adapter:sink0_channel
wire cmd_mux_002_src_ready; // acl_kernel_clk_ctrl_burst_adapter:sink0_ready -> cmd_mux_002:src_ready
wire acl_kernel_clk_ctrl_burst_adapter_source0_endofpacket; // acl_kernel_clk_ctrl_burst_adapter:source0_endofpacket -> acl_kernel_clk_ctrl_agent:cp_endofpacket
wire acl_kernel_clk_ctrl_burst_adapter_source0_valid; // acl_kernel_clk_ctrl_burst_adapter:source0_valid -> acl_kernel_clk_ctrl_agent:cp_valid
wire acl_kernel_clk_ctrl_burst_adapter_source0_startofpacket; // acl_kernel_clk_ctrl_burst_adapter:source0_startofpacket -> acl_kernel_clk_ctrl_agent:cp_startofpacket
wire [113:0] acl_kernel_clk_ctrl_burst_adapter_source0_data; // acl_kernel_clk_ctrl_burst_adapter:source0_data -> acl_kernel_clk_ctrl_agent:cp_data
wire acl_kernel_clk_ctrl_burst_adapter_source0_ready; // acl_kernel_clk_ctrl_agent:cp_ready -> acl_kernel_clk_ctrl_burst_adapter:source0_ready
wire [2:0] acl_kernel_clk_ctrl_burst_adapter_source0_channel; // acl_kernel_clk_ctrl_burst_adapter:source0_channel -> acl_kernel_clk_ctrl_agent:cp_channel
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [113:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [2:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [113:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire [2:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [113:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire [2:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire [113:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire [2:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire [113:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
wire [2:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink1_valid
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
wire [113:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink1_data
wire [2:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src2_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [113:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [2:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire [113:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire [2:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire [113:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire [2:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire [113:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
wire [2:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire [113:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire [2:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink2_valid
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
wire [113:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink2_data
wire [2:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src1_ready
wire [2:0] hps_h2f_lw_axi_master_wr_limiter_cmd_valid_data; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire [2:0] hps_h2f_lw_axi_master_rd_limiter_cmd_valid_data; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) version_id_s_translator (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (version_id_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (version_id_s_agent_m0_burstcount), // .burstcount
.uav_read (version_id_s_agent_m0_read), // .read
.uav_write (version_id_s_agent_m0_write), // .write
.uav_waitrequest (version_id_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (version_id_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (version_id_s_agent_m0_byteenable), // .byteenable
.uav_readdata (version_id_s_agent_m0_readdata), // .readdata
.uav_writedata (version_id_s_agent_m0_writedata), // .writedata
.uav_lock (version_id_s_agent_m0_lock), // .lock
.uav_debugaccess (version_id_s_agent_m0_debugaccess), // .debugaccess
.av_read (version_id_s_read), // avalon_anti_slave_0.read
.av_readdata (version_id_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) acl_kernel_interface_kernel_cntrl_translator (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (acl_kernel_interface_kernel_cntrl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (acl_kernel_interface_kernel_cntrl_agent_m0_burstcount), // .burstcount
.uav_read (acl_kernel_interface_kernel_cntrl_agent_m0_read), // .read
.uav_write (acl_kernel_interface_kernel_cntrl_agent_m0_write), // .write
.uav_waitrequest (acl_kernel_interface_kernel_cntrl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (acl_kernel_interface_kernel_cntrl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (acl_kernel_interface_kernel_cntrl_agent_m0_byteenable), // .byteenable
.uav_readdata (acl_kernel_interface_kernel_cntrl_agent_m0_readdata), // .readdata
.uav_writedata (acl_kernel_interface_kernel_cntrl_agent_m0_writedata), // .writedata
.uav_lock (acl_kernel_interface_kernel_cntrl_agent_m0_lock), // .lock
.uav_debugaccess (acl_kernel_interface_kernel_cntrl_agent_m0_debugaccess), // .debugaccess
.av_address (acl_kernel_interface_kernel_cntrl_address), // avalon_anti_slave_0.address
.av_write (acl_kernel_interface_kernel_cntrl_write), // .write
.av_read (acl_kernel_interface_kernel_cntrl_read), // .read
.av_readdata (acl_kernel_interface_kernel_cntrl_readdata), // .readdata
.av_writedata (acl_kernel_interface_kernel_cntrl_writedata), // .writedata
.av_burstcount (acl_kernel_interface_kernel_cntrl_burstcount), // .burstcount
.av_byteenable (acl_kernel_interface_kernel_cntrl_byteenable), // .byteenable
.av_readdatavalid (acl_kernel_interface_kernel_cntrl_readdatavalid), // .readdatavalid
.av_waitrequest (acl_kernel_interface_kernel_cntrl_waitrequest), // .waitrequest
.av_debugaccess (acl_kernel_interface_kernel_cntrl_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (11),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) acl_kernel_clk_ctrl_translator (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (acl_kernel_clk_ctrl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (acl_kernel_clk_ctrl_agent_m0_burstcount), // .burstcount
.uav_read (acl_kernel_clk_ctrl_agent_m0_read), // .read
.uav_write (acl_kernel_clk_ctrl_agent_m0_write), // .write
.uav_waitrequest (acl_kernel_clk_ctrl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (acl_kernel_clk_ctrl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (acl_kernel_clk_ctrl_agent_m0_byteenable), // .byteenable
.uav_readdata (acl_kernel_clk_ctrl_agent_m0_readdata), // .readdata
.uav_writedata (acl_kernel_clk_ctrl_agent_m0_writedata), // .writedata
.uav_lock (acl_kernel_clk_ctrl_agent_m0_lock), // .lock
.uav_debugaccess (acl_kernel_clk_ctrl_agent_m0_debugaccess), // .debugaccess
.av_address (acl_kernel_clk_ctrl_address), // avalon_anti_slave_0.address
.av_write (acl_kernel_clk_ctrl_write), // .write
.av_read (acl_kernel_clk_ctrl_read), // .read
.av_readdata (acl_kernel_clk_ctrl_readdata), // .readdata
.av_writedata (acl_kernel_clk_ctrl_writedata), // .writedata
.av_burstcount (acl_kernel_clk_ctrl_burstcount), // .burstcount
.av_byteenable (acl_kernel_clk_ctrl_byteenable), // .byteenable
.av_readdatavalid (acl_kernel_clk_ctrl_readdatavalid), // .readdatavalid
.av_waitrequest (acl_kernel_clk_ctrl_waitrequest), // .waitrequest
.av_debugaccess (acl_kernel_clk_ctrl_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (21),
.RDATA_WIDTH (32),
.WDATA_WIDTH (32),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (84),
.PKT_CACHE_H (108),
.PKT_CACHE_L (105),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_RESPONSE_STATUS_L (109),
.PKT_RESPONSE_STATUS_H (110),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_EXCLUSIVE (62),
.PKT_TRANS_LOCK (61),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_THREAD_ID_H (101),
.PKT_THREAD_ID_L (90),
.PKT_QOS_L (85),
.PKT_QOS_H (85),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_ORI_BURST_SIZE_H (113),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.ID (0)
) hps_h2f_lw_axi_master_agent (
.aclk (config_clk_out_clk_clk), // clk.clk
.aresetn (~hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (hps_h2f_lw_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (hps_h2f_lw_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (hps_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (hps_h2f_lw_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (hps_h2f_lw_axi_master_wr_limiter_rsp_src_valid), // write_rp.valid
.write_rp_data (hps_h2f_lw_axi_master_wr_limiter_rsp_src_data), // .data
.write_rp_channel (hps_h2f_lw_axi_master_wr_limiter_rsp_src_channel), // .channel
.write_rp_startofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
.write_rp_endofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
.write_rp_ready (hps_h2f_lw_axi_master_wr_limiter_rsp_src_ready), // .ready
.read_cp_valid (hps_h2f_lw_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (hps_h2f_lw_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (hps_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (hps_h2f_lw_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (hps_h2f_lw_axi_master_rd_limiter_rsp_src_valid), // read_rp.valid
.read_rp_data (hps_h2f_lw_axi_master_rd_limiter_rsp_src_data), // .data
.read_rp_channel (hps_h2f_lw_axi_master_rd_limiter_rsp_src_channel), // .channel
.read_rp_startofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
.read_rp_endofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
.read_rp_ready (hps_h2f_lw_axi_master_rd_limiter_rsp_src_ready), // .ready
.awid (hps_h2f_lw_axi_master_awid), // altera_axi_slave.awid
.awaddr (hps_h2f_lw_axi_master_awaddr), // .awaddr
.awlen (hps_h2f_lw_axi_master_awlen), // .awlen
.awsize (hps_h2f_lw_axi_master_awsize), // .awsize
.awburst (hps_h2f_lw_axi_master_awburst), // .awburst
.awlock (hps_h2f_lw_axi_master_awlock), // .awlock
.awcache (hps_h2f_lw_axi_master_awcache), // .awcache
.awprot (hps_h2f_lw_axi_master_awprot), // .awprot
.awvalid (hps_h2f_lw_axi_master_awvalid), // .awvalid
.awready (hps_h2f_lw_axi_master_awready), // .awready
.wid (hps_h2f_lw_axi_master_wid), // .wid
.wdata (hps_h2f_lw_axi_master_wdata), // .wdata
.wstrb (hps_h2f_lw_axi_master_wstrb), // .wstrb
.wlast (hps_h2f_lw_axi_master_wlast), // .wlast
.wvalid (hps_h2f_lw_axi_master_wvalid), // .wvalid
.wready (hps_h2f_lw_axi_master_wready), // .wready
.bid (hps_h2f_lw_axi_master_bid), // .bid
.bresp (hps_h2f_lw_axi_master_bresp), // .bresp
.bvalid (hps_h2f_lw_axi_master_bvalid), // .bvalid
.bready (hps_h2f_lw_axi_master_bready), // .bready
.arid (hps_h2f_lw_axi_master_arid), // .arid
.araddr (hps_h2f_lw_axi_master_araddr), // .araddr
.arlen (hps_h2f_lw_axi_master_arlen), // .arlen
.arsize (hps_h2f_lw_axi_master_arsize), // .arsize
.arburst (hps_h2f_lw_axi_master_arburst), // .arburst
.arlock (hps_h2f_lw_axi_master_arlock), // .arlock
.arcache (hps_h2f_lw_axi_master_arcache), // .arcache
.arprot (hps_h2f_lw_axi_master_arprot), // .arprot
.arvalid (hps_h2f_lw_axi_master_arvalid), // .arvalid
.arready (hps_h2f_lw_axi_master_arready), // .arready
.rid (hps_h2f_lw_axi_master_rid), // .rid
.rdata (hps_h2f_lw_axi_master_rdata), // .rdata
.rresp (hps_h2f_lw_axi_master_rresp), // .rresp
.rlast (hps_h2f_lw_axi_master_rlast), // .rlast
.rvalid (hps_h2f_lw_axi_master_rvalid), // .rvalid
.rready (hps_h2f_lw_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (1'b0), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_TRANS_LOCK (61),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_ORI_BURST_SIZE_H (113),
.ST_CHANNEL_W (3),
.ST_DATA_W (114),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) version_id_s_agent (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (version_id_s_agent_m0_address), // m0.address
.m0_burstcount (version_id_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (version_id_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (version_id_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (version_id_s_agent_m0_lock), // .lock
.m0_readdata (version_id_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (version_id_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (version_id_s_agent_m0_read), // .read
.m0_waitrequest (version_id_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (version_id_s_agent_m0_writedata), // .writedata
.m0_write (version_id_s_agent_m0_write), // .write
.rp_endofpacket (version_id_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (version_id_s_agent_rp_ready), // .ready
.rp_valid (version_id_s_agent_rp_valid), // .valid
.rp_data (version_id_s_agent_rp_data), // .data
.rp_startofpacket (version_id_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (version_id_s_burst_adapter_source0_ready), // cp.ready
.cp_valid (version_id_s_burst_adapter_source0_valid), // .valid
.cp_data (version_id_s_burst_adapter_source0_data), // .data
.cp_startofpacket (version_id_s_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (version_id_s_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (version_id_s_burst_adapter_source0_channel), // .channel
.rf_sink_ready (version_id_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (version_id_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (version_id_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (version_id_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (version_id_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (version_id_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (version_id_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (version_id_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (version_id_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (version_id_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (version_id_s_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (version_id_s_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (version_id_s_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (version_id_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (version_id_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (version_id_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (115),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_s_agent_rsp_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_s_agent_rf_source_data), // in.data
.in_valid (version_id_s_agent_rf_source_valid), // .valid
.in_ready (version_id_s_agent_rf_source_ready), // .ready
.in_startofpacket (version_id_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (version_id_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (version_id_s_agent_rsp_fifo_out_data), // out.data
.out_valid (version_id_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (version_id_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (version_id_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (version_id_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_s_agent_rdata_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_s_agent_rdata_fifo_src_data), // in.data
.in_valid (version_id_s_agent_rdata_fifo_src_valid), // .valid
.in_ready (version_id_s_agent_rdata_fifo_src_ready), // .ready
.out_data (version_id_s_agent_rdata_fifo_out_data), // out.data
.out_valid (version_id_s_agent_rdata_fifo_out_valid), // .valid
.out_ready (version_id_s_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_TRANS_LOCK (61),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_ORI_BURST_SIZE_H (113),
.ST_CHANNEL_W (3),
.ST_DATA_W (114),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) acl_kernel_interface_kernel_cntrl_agent (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (acl_kernel_interface_kernel_cntrl_agent_m0_address), // m0.address
.m0_burstcount (acl_kernel_interface_kernel_cntrl_agent_m0_burstcount), // .burstcount
.m0_byteenable (acl_kernel_interface_kernel_cntrl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (acl_kernel_interface_kernel_cntrl_agent_m0_debugaccess), // .debugaccess
.m0_lock (acl_kernel_interface_kernel_cntrl_agent_m0_lock), // .lock
.m0_readdata (acl_kernel_interface_kernel_cntrl_agent_m0_readdata), // .readdata
.m0_readdatavalid (acl_kernel_interface_kernel_cntrl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (acl_kernel_interface_kernel_cntrl_agent_m0_read), // .read
.m0_waitrequest (acl_kernel_interface_kernel_cntrl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (acl_kernel_interface_kernel_cntrl_agent_m0_writedata), // .writedata
.m0_write (acl_kernel_interface_kernel_cntrl_agent_m0_write), // .write
.rp_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (acl_kernel_interface_kernel_cntrl_agent_rp_ready), // .ready
.rp_valid (acl_kernel_interface_kernel_cntrl_agent_rp_valid), // .valid
.rp_data (acl_kernel_interface_kernel_cntrl_agent_rp_data), // .data
.rp_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_startofpacket), // .startofpacket
.cp_ready (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_ready), // cp.ready
.cp_valid (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_valid), // .valid
.cp_data (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_data), // .data
.cp_startofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_channel), // .channel
.rf_sink_ready (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (acl_kernel_interface_kernel_cntrl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (acl_kernel_interface_kernel_cntrl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (acl_kernel_interface_kernel_cntrl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (115),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_interface_kernel_cntrl_agent_rsp_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_interface_kernel_cntrl_agent_rf_source_data), // in.data
.in_valid (acl_kernel_interface_kernel_cntrl_agent_rf_source_valid), // .valid
.in_ready (acl_kernel_interface_kernel_cntrl_agent_rf_source_ready), // .ready
.in_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_endofpacket), // .endofpacket
.out_data (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_data), // out.data
.out_valid (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_valid), // .valid
.out_ready (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_interface_kernel_cntrl_agent_rdata_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_data), // in.data
.in_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_valid), // .valid
.in_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_ready), // .ready
.out_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_data), // out.data
.out_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_valid), // .valid
.out_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_TRANS_LOCK (61),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_ORI_BURST_SIZE_H (113),
.ST_CHANNEL_W (3),
.ST_DATA_W (114),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) acl_kernel_clk_ctrl_agent (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (acl_kernel_clk_ctrl_agent_m0_address), // m0.address
.m0_burstcount (acl_kernel_clk_ctrl_agent_m0_burstcount), // .burstcount
.m0_byteenable (acl_kernel_clk_ctrl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (acl_kernel_clk_ctrl_agent_m0_debugaccess), // .debugaccess
.m0_lock (acl_kernel_clk_ctrl_agent_m0_lock), // .lock
.m0_readdata (acl_kernel_clk_ctrl_agent_m0_readdata), // .readdata
.m0_readdatavalid (acl_kernel_clk_ctrl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (acl_kernel_clk_ctrl_agent_m0_read), // .read
.m0_waitrequest (acl_kernel_clk_ctrl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (acl_kernel_clk_ctrl_agent_m0_writedata), // .writedata
.m0_write (acl_kernel_clk_ctrl_agent_m0_write), // .write
.rp_endofpacket (acl_kernel_clk_ctrl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (acl_kernel_clk_ctrl_agent_rp_ready), // .ready
.rp_valid (acl_kernel_clk_ctrl_agent_rp_valid), // .valid
.rp_data (acl_kernel_clk_ctrl_agent_rp_data), // .data
.rp_startofpacket (acl_kernel_clk_ctrl_agent_rp_startofpacket), // .startofpacket
.cp_ready (acl_kernel_clk_ctrl_burst_adapter_source0_ready), // cp.ready
.cp_valid (acl_kernel_clk_ctrl_burst_adapter_source0_valid), // .valid
.cp_data (acl_kernel_clk_ctrl_burst_adapter_source0_data), // .data
.cp_startofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (acl_kernel_clk_ctrl_burst_adapter_source0_channel), // .channel
.rf_sink_ready (acl_kernel_clk_ctrl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (acl_kernel_clk_ctrl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (acl_kernel_clk_ctrl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (acl_kernel_clk_ctrl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (acl_kernel_clk_ctrl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (acl_kernel_clk_ctrl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (acl_kernel_clk_ctrl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (acl_kernel_clk_ctrl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (acl_kernel_clk_ctrl_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (acl_kernel_clk_ctrl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (115),
.FIFO_DEPTH (5),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_clk_ctrl_agent_rsp_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_clk_ctrl_agent_rf_source_data), // in.data
.in_valid (acl_kernel_clk_ctrl_agent_rf_source_valid), // .valid
.in_ready (acl_kernel_clk_ctrl_agent_rf_source_ready), // .ready
.in_startofpacket (acl_kernel_clk_ctrl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (acl_kernel_clk_ctrl_agent_rf_source_endofpacket), // .endofpacket
.out_data (acl_kernel_clk_ctrl_agent_rsp_fifo_out_data), // out.data
.out_valid (acl_kernel_clk_ctrl_agent_rsp_fifo_out_valid), // .valid
.out_ready (acl_kernel_clk_ctrl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_clk_ctrl_agent_rdata_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_clk_ctrl_agent_rdata_fifo_src_data), // in.data
.in_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_src_valid), // .valid
.in_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_src_ready), // .ready
.out_data (acl_kernel_clk_ctrl_agent_rdata_fifo_out_data), // out.data
.out_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_out_valid), // .valid
.out_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_mm_interconnect_0_router router (
.sink_ready (hps_h2f_lw_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (hps_h2f_lw_axi_master_agent_write_cp_valid), // .valid
.sink_data (hps_h2f_lw_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router router_001 (
.sink_ready (hps_h2f_lw_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (hps_h2f_lw_axi_master_agent_read_cp_valid), // .valid
.sink_data (hps_h2f_lw_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router_002 router_002 (
.sink_ready (version_id_s_agent_rp_ready), // sink.ready
.sink_valid (version_id_s_agent_rp_valid), // .valid
.sink_data (version_id_s_agent_rp_data), // .data
.sink_startofpacket (version_id_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (version_id_s_agent_rp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router_002 router_003 (
.sink_ready (acl_kernel_interface_kernel_cntrl_agent_rp_ready), // sink.ready
.sink_valid (acl_kernel_interface_kernel_cntrl_agent_rp_valid), // .valid
.sink_data (acl_kernel_interface_kernel_cntrl_agent_rp_data), // .data
.sink_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router_002 router_004 (
.sink_ready (acl_kernel_clk_ctrl_agent_rp_ready), // sink.ready
.sink_valid (acl_kernel_clk_ctrl_agent_rp_valid), // .valid
.sink_data (acl_kernel_clk_ctrl_agent_rp_data), // .data
.sink_startofpacket (acl_kernel_clk_ctrl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (acl_kernel_clk_ctrl_agent_rp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.MAX_OUTSTANDING_RESPONSES (6),
.PIPELINED (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.VALID_WIDTH (3),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) hps_h2f_lw_axi_master_wr_limiter (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_h2f_lw_axi_master_wr_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_h2f_lw_axi_master_wr_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_h2f_lw_axi_master_wr_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_h2f_lw_axi_master_wr_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_h2f_lw_axi_master_wr_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_h2f_lw_axi_master_wr_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_h2f_lw_axi_master_wr_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_h2f_lw_axi_master_wr_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.MAX_OUTSTANDING_RESPONSES (6),
.PIPELINED (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.VALID_WIDTH (3),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) hps_h2f_lw_axi_master_rd_limiter (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_h2f_lw_axi_master_rd_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_h2f_lw_axi_master_rd_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_h2f_lw_axi_master_rd_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_h2f_lw_axi_master_rd_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_h2f_lw_axi_master_rd_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_h2f_lw_axi_master_rd_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_h2f_lw_axi_master_rd_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_h2f_lw_axi_master_rd_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) version_id_s_burst_adapter (
.clk (config_clk_out_clk_clk), // cr0.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_src_valid), // sink0.valid
.sink0_data (cmd_mux_src_data), // .data
.sink0_channel (cmd_mux_src_channel), // .channel
.sink0_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_src_ready), // .ready
.source0_valid (version_id_s_burst_adapter_source0_valid), // source0.valid
.source0_data (version_id_s_burst_adapter_source0_data), // .data
.source0_channel (version_id_s_burst_adapter_source0_channel), // .channel
.source0_startofpacket (version_id_s_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (version_id_s_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (version_id_s_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) acl_kernel_interface_kernel_cntrl_burst_adapter (
.clk (config_clk_out_clk_clk), // cr0.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_001_src_valid), // sink0.valid
.sink0_data (cmd_mux_001_src_data), // .data
.sink0_channel (cmd_mux_001_src_channel), // .channel
.sink0_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_001_src_ready), // .ready
.source0_valid (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_valid), // source0.valid
.source0_data (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_data), // .data
.source0_channel (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_channel), // .channel
.source0_startofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) acl_kernel_clk_ctrl_burst_adapter (
.clk (config_clk_out_clk_clk), // cr0.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_002_src_valid), // sink0.valid
.sink0_data (cmd_mux_002_src_data), // .data
.sink0_channel (cmd_mux_002_src_channel), // .channel
.sink0_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_002_src_ready), // .ready
.source0_valid (acl_kernel_clk_ctrl_burst_adapter_source0_valid), // source0.valid
.source0_data (acl_kernel_clk_ctrl_burst_adapter_source0_data), // .data
.source0_channel (acl_kernel_clk_ctrl_burst_adapter_source0_channel), // .channel
.source0_startofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (acl_kernel_clk_ctrl_burst_adapter_source0_ready) // .ready
);
system_acl_iface_mm_interconnect_0_cmd_demux cmd_demux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_h2f_lw_axi_master_wr_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_h2f_lw_axi_master_wr_limiter_cmd_src_channel), // .channel
.sink_data (hps_h2f_lw_axi_master_wr_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_h2f_lw_axi_master_wr_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_demux cmd_demux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_h2f_lw_axi_master_rd_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_h2f_lw_axi_master_rd_limiter_cmd_src_channel), // .channel
.sink_data (hps_h2f_lw_axi_master_rd_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_h2f_lw_axi_master_rd_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_mux cmd_mux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_mux cmd_mux_002 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src2_valid), // .valid
.sink1_channel (cmd_demux_001_src2_channel), // .channel
.sink1_data (cmd_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_demux rsp_demux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_demux rsp_demux_002 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_mux rsp_mux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_mux rsp_mux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src1_valid), // .valid
.sink2_channel (rsp_demux_002_src1_channel), // .channel
.sink2_data (rsp_demux_002_src1_data), // .data
.sink2_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
endmodule
|
`default_nettype none
module dps_utim64(
//System
input wire iCLOCK, //Global Clock
input wire inRESET,
//Timer Clock
input wire iTIMER_CLOCK,
//Counter
input wire iREQ_VALID,
output wire oREQ_BUSY,
input wire iREQ_RW,
input wire [4:0] iREQ_ADDR,
input wire [31:0] iREQ_DATA,
output wire oREQ_VALID,
output wire [31:0] oREQ_DATA,
//Interrupt
output wire oIRQ_VALID,
input wire iIRQ_ACK
);
wire [3:0] utim64a_irq;
wire [3:0] utim64b_irq;
reg [1:0] b_irq_state;
reg [7:0] b_irq_flags;
reg b_flag_buffer_valid;
reg [7:0] b_flag_buffer_flags;
wire utim64a_busy;
wire utim64b_busy;
wire utim64a_req_cc;
wire utim64b_req_cc;
wire utim64_flags_cc;
assign utim64a_req_cc = !utim64a_busy && !utim64b_busy && iREQ_VALID && (iREQ_ADDR >= 5'h0 && iREQ_ADDR <= 5'he);
assign utim64b_req_cc = !utim64a_busy && !utim64b_busy && iREQ_VALID && (iREQ_ADDR >= 5'h10 && iREQ_ADDR <= 5'h1e);
assign utim64_flags_cc = !utim64a_busy && !utim64b_busy && iREQ_VALID && !iREQ_RW && (iREQ_ADDR == 5'h1f);
wire utim64a_out_valid;
wire utim64b_out_valid;
wire [31:0] utim64a_out_data;
wire [31:0] utim64b_out_data;
/************************************
Module Select State
************************************/
parameter L_PARAM_MAIN_STT_IDLE = 1'h0;
parameter L_PARAM_MAIN_STT_RD_WAIT = 1'h1;
reg [1:0] b_modsel; //0:UTIM64A | 1:UTIM64B | 2:FLAGS
reg b_state;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= L_PARAM_MAIN_STT_IDLE;
b_modsel <= 2'b00;
end
else begin
case(b_state)
L_PARAM_MAIN_STT_IDLE:
begin
if(!iREQ_RW)begin
if(utim64a_req_cc)begin
b_state <= L_PARAM_MAIN_STT_RD_WAIT;
b_modsel <= 2'b00;
end
else if(utim64b_req_cc)begin
b_state <= L_PARAM_MAIN_STT_RD_WAIT;
b_modsel <= 2'b01;
end
else if(utim64_flags_cc)begin
b_state <= L_PARAM_MAIN_STT_RD_WAIT;
b_modsel <= 2'b10;
end
end
end
L_PARAM_MAIN_STT_RD_WAIT:
begin
if(utim64a_out_valid || utim64b_out_valid || b_flag_buffer_valid)begin
b_state <= L_PARAM_MAIN_STT_IDLE;
end
end
endcase
end
end
/************************************
Timer Module
************************************/
dps_utim64_module UTIM64A(
//System
.iIF_CLOCK(iCLOCK),
.iTIMER_CLOCK(iTIMER_CLOCK),
.inRESET(inRESET),
//Counter
.iREQ_VALID(utim64a_req_cc),
.oREQ_BUSY(utim64a_busy),
.iREQ_RW(iREQ_RW),
.iREQ_ADDR(iREQ_ADDR[3:0]),
.iREQ_DATA(iREQ_DATA),
.oREQ_VALID(utim64a_out_valid),
.oREQ_DATA(utim64a_out_data),
//Interrupt
.oIRQ_IRQ(utim64a_irq)
);
dps_utim64_module UTIM64B(
//System
.iIF_CLOCK(iCLOCK),
.iTIMER_CLOCK(iTIMER_CLOCK),
.inRESET(inRESET),
//Counter
.iREQ_VALID(utim64b_req_cc),
.oREQ_BUSY(utim64b_busy),
.iREQ_RW(iREQ_RW),
.iREQ_ADDR({1'b0, iREQ_ADDR[2:0]}),
.iREQ_DATA(iREQ_DATA),
.oREQ_VALID(utim64b_out_valid),
.oREQ_DATA(utim64b_out_data),
//Interrupt
.oIRQ_IRQ(utim64b_irq)
);
/************************************
IRQ Flags
************************************/
parameter L_PARAM_IRQ_STT_IDLE = 2'h0;
parameter L_PARAM_IRQ_STT_IRQ = 2'h1;
parameter L_PARAM_IRQ_STT_FLAG = 2'h2;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_irq_state <= L_PARAM_IRQ_STT_IDLE;
b_irq_flags <= 8'h0;
end
else begin
case(b_irq_state)
L_PARAM_IRQ_STT_IDLE:
begin
if(|{utim64a_irq, utim64b_irq})begin
b_irq_state <= L_PARAM_IRQ_STT_IRQ;
b_irq_flags <= b_irq_flags | {utim64b_irq, utim64a_irq};
end
begin
b_irq_flags <= b_irq_flags | {utim64b_irq, utim64a_irq};
end
/*
if(|{utim64a_irq, utim64b_irq})begin
b_irq_state <= L_PARAM_IRQ_STT_IRQ;
if(utim64_flags_cc)begin
b_irq_flags <= {utim64a_irq, utim64b_irq};
end
else begin
b_irq_flags <= b_irq_flags | {utim64a_irq, utim64b_irq};
end
end
else begin
if(utim64_flags_cc)begin
b_irq_flags <= 8'h00;
end
else begin
b_irq_flags <= b_irq_flags;
end
end
*/
end
L_PARAM_IRQ_STT_IRQ:
begin
if(iIRQ_ACK)begin
b_irq_state <= L_PARAM_IRQ_STT_FLAG;
end
b_irq_flags <= b_irq_flags | {utim64b_irq, utim64a_irq};
/*
if(iIRQ_ACK)begin
if(utim64_flags_cc)begin
//Flag Load Condition
b_irq_state <= (utim64a_irq || utim64b_irq)? L_PARAM_IRQ_STT_IRQ : L_PARAM_IRQ_STT_IDLE;
b_irq_flags <= (utim64a_irq || utim64b_irq)? {utim64a_irq, utim64b_irq} : 8'h00;
end
else begin
//Not Flag Load Condition
b_irq_state <= (utim64a_irq || utim64b_irq)? L_PARAM_IRQ_STT_IRQ : L_PARAM_IRQ_STT_IDLE;
b_irq_flags <= (utim64a_irq || utim64b_irq)? (b_irq_flags | {utim64a_irq, utim64b_irq}) : b_irq_flags;
end
end
else begin
if(utim64_flags_cc)begin
//Flag Load Condition
b_irq_state <= L_PARAM_IRQ_STT_IRQ;
b_irq_flags <= (utim64a_irq || utim64b_irq)? {utim64a_irq, utim64b_irq} : 8'h00;
end
else begin
//Not Flag Load Condition
b_irq_state <= L_PARAM_IRQ_STT_IRQ;
b_irq_flags <= (utim64a_irq || utim64b_irq)? (b_irq_flags | {utim64a_irq, utim64b_irq}) : b_irq_flags;
end
end
*/
end
L_PARAM_IRQ_STT_FLAG:
begin
if(utim64_flags_cc)begin
//Flag Load Condition
b_irq_state <= L_PARAM_IRQ_STT_IDLE;
b_irq_flags <= {utim64b_irq, utim64a_irq};
end
else begin
//Not Flag Load Condition
b_irq_flags <= b_irq_flags | {utim64b_irq, utim64a_irq};
end
end
default:
begin
b_irq_state <= L_PARAM_IRQ_STT_IDLE;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_flag_buffer_valid <= 1'b0;
b_flag_buffer_flags <= 8'h0;
end
else begin
b_flag_buffer_valid <= utim64_flags_cc;//utim64_flags_cc && (b_irq_state == L_PARAM_IRQ_STT_IRQ);
b_flag_buffer_flags <= b_irq_flags;
end
end
/************************************
Assign
************************************/
assign oIRQ_VALID = (b_irq_state == L_PARAM_IRQ_STT_IRQ)? 1'b1 : 1'b0;
assign oREQ_BUSY = (b_state != L_PARAM_MAIN_STT_IDLE) || utim64a_busy || utim64b_busy;
assign oREQ_VALID = utim64a_out_valid || utim64b_out_valid || b_flag_buffer_valid;
assign oREQ_DATA = (b_modsel == 2'h0)? utim64a_out_data : (
(b_modsel == 2'h1)? utim64b_out_data : b_flag_buffer_flags
);
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2_BEHAVIORAL_V
`define SKY130_FD_SC_MS__AND2_BEHAVIORAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DECAP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DECAP_BEHAVIORAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__decap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DECAP_BEHAVIORAL_V |
`default_nettype none
`include "core.h"
`include "irq.h"
`include "common.h"
module execute(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Event CTRL
input wire iEVENT_HOLD,
input wire iEVENT_START,
input wire iEVENT_IRQ_FRONT2BACK,
input wire iEVENT_IRQ_BACK2FRONT,
input wire iEVENT_END,
//Lock
output wire oEXCEPTION_LOCK,
//System Register
input wire [31:0] iSYSREG_PFLAGR,
output wire [31:0] oSYSREG_FLAGR,
//Pipeline
input wire iPREVIOUS_VALID,
input wire iPREVIOUS_FAULT_PAGEFAULT,
input wire iPREVIOUS_FAULT_PRIVILEGE_ERROR,
input wire iPREVIOUS_FAULT_INVALID_INST,
input wire iPREVIOUS_PAGING_ENA,
input wire iPREVIOUS_KERNEL_ACCESS,
input wire iPREVIOUS_BRANCH_PREDICT,
input wire [31:0] iPREVIOUS_BRANCH_PREDICT_ADDR,
input wire [31:0] iPREVIOUS_SYSREG_PSR,
input wire [63:0] iPREVIOUS_SYSREG_FRCR,
input wire [31:0] iPREVIOUS_SYSREG_TIDR,
input wire [31:0] iPREVIOUS_SYSREG_PDTR,
input wire [31:0] iPREVIOUS_SYSREG_KPDTR,
input wire iPREVIOUS_DESTINATION_SYSREG,
input wire [4:0] iPREVIOUS_DESTINATION,
input wire iPREVIOUS_WRITEBACK,
input wire iPREVIOUS_FLAGS_WRITEBACK,
input wire [4:0] iPREVIOUS_CMD,
input wire [3:0] iPREVIOUS_CC_AFE,
input wire [31:0] iPREVIOUS_SPR,
input wire [31:0] iPREVIOUS_SOURCE0,
input wire [31:0] iPREVIOUS_SOURCE1,
input wire [5:0] iPREVIOUS_ADV_DATA,
input wire [4:0] iPREVIOUS_SOURCE0_POINTER,
input wire [4:0] iPREVIOUS_SOURCE1_POINTER,
input wire iPREVIOUS_SOURCE0_SYSREG,
input wire iPREVIOUS_SOURCE1_SYSREG,
input wire iPREVIOUS_SOURCE1_IMM,
input wire iPREVIOUS_SOURCE0_FLAGS,
input wire iPREVIOUS_ADV_ACTIVE,
input wire iPREVIOUS_EX_SYS_REG,
input wire iPREVIOUS_EX_SYS_LDST,
input wire iPREVIOUS_EX_LOGIC,
input wire iPREVIOUS_EX_SHIFT,
input wire iPREVIOUS_EX_ADDER,
input wire iPREVIOUS_EX_MUL,
input wire iPREVIOUS_EX_SDIV,
input wire iPREVIOUS_EX_UDIV,
input wire iPREVIOUS_EX_LDST,
input wire iPREVIOUS_EX_BRANCH,
input wire [31:0] iPREVIOUS_PC,
output wire oPREVIOUS_LOCK,
//Load Store Pipe
output wire oDATAIO_REQ,
input wire iDATAIO_BUSY,
output wire [1:0] oDATAIO_ORDER, //00=Byte Order 01=2Byte Order 10= Word Order 11= None
output wire [3:0] oDATAIO_MASK, //[0]=Byte0, [1]=Byte1...
output wire oDATAIO_RW, //0=Read 1=Write
output wire [13:0] oDATAIO_ASID,
output wire [1:0] oDATAIO_MMUMOD,
output wire [2:0] oDATAIO_MMUPS,
output wire [31:0] oDATAIO_PDT,
output wire [31:0] oDATAIO_ADDR,
output wire [31:0] oDATAIO_DATA,
input wire iDATAIO_REQ,
input wire [11:0] iDATAIO_MMU_FLAGS,
input wire [31:0] iDATAIO_DATA,
//Writeback
output wire oNEXT_VALID,
output wire [31:0] oNEXT_DATA,
output wire [4:0] oNEXT_DESTINATION,
output wire oNEXT_DESTINATION_SYSREG,
output wire oNEXT_WRITEBACK,
output wire oNEXT_SPR_WRITEBACK,
output wire [31:0] oNEXT_SPR,
output wire [63:0] oNEXT_FRCR,
output wire [31:0] oNEXT_PC,
//System Register Write
output wire oPDTR_WRITEBACK,
//Branch
output wire [31:0] oBRANCH_ADDR,
output wire oJUMP_VALID,
output wire oINTR_VALID,
output wire oIDTSET_VALID,
output wire oPDTSET_VALID,
output wire oPSRSET_VALID,
output wire oFAULT_VALID,
output wire [6:0] oFAULT_NUM,
output wire [31:0] oFAULT_FI0R,
output wire [31:0] oFAULT_FI1R,
//Branch Predictor
output wire oBPREDICT_JUMP_INST,
output wire oBPREDICT_PREDICT, //Branch Guess
output wire oBPREDICT_HIT, //Guess Hit!
output wire oBPREDICT_JUMP, //Branch Active
output wire [31:0] oBPREDICT_JUMP_ADDR, //Branch Address
output wire [31:0] oBPREDICT_INST_ADDR, //Branch Instruction Memory Address
//Debug
input wire iDEBUG_CTRL_REQ,
input wire iDEBUG_CTRL_STOP,
input wire iDEBUG_CTRL_START,
output wire oDEBUG_CTRL_ACK,
output wire [31:0] oDEBUG_REG_OUT_FLAGR
);
/*********************************************************************************************************
Wire
*********************************************************************************************************/
localparam L_PARAM_STT_NORMAL = 3'h0;
localparam L_PARAM_STT_DIV_WAIT = 3'h1;
localparam L_PARAM_STT_LOAD = 3'h2;
localparam L_PARAM_STT_STORE = 3'h3;
localparam L_PARAM_STT_BRANCH = 3'h4;
localparam L_PARAM_STT_RELOAD = 3'h5;
localparam L_PARAM_STT_EXCEPTION = 3'h6;
localparam L_PARAM_STT_HALT = 3'h7;
reg b_valid;
reg [31:0] b_sysreg_psr;
reg [31:0] b_sysreg_tidr;
reg [31:0] b_sysreg_pdt;
reg [2:0] b_state;
reg b_load_store;
reg b_writeback;
reg b_destination_sysreg;
reg [4:0] b_destination;
reg [3:0] b_afe;
reg [31:0] b_r_data;
reg b_spr_writeback;
reg [31:0] b_r_spr;
reg [31:0] b_pc;
reg [63:0] b_frcr;
wire div_wait;
wire debugger_pipeline_stop;
wire lock_condition = (b_state != L_PARAM_STT_NORMAL) || div_wait || debugger_pipeline_stop;// || iDATAIO_BUSY;
wire io_lock_condition = iDATAIO_BUSY;
assign oPREVIOUS_LOCK = lock_condition || iEVENT_HOLD || iEVENT_HOLD;
wire [31:0] ex_module_source0;
wire [31:0] ex_module_source1;
wire forwarding_reg_gr_valid;
wire [31:0] forwarding_reg_gr_data;
wire [4:0] forwarding_reg_gr_dest;
wire forwarding_reg_gr_dest_sysreg;
wire forwarding_reg_spr_valid;
wire [31:0] forwarding_reg_spr_data;
wire forwarding_reg_frcr_valid;
wire [63:0] forwarding_reg_frcr_data;
wire [31:0] ex_module_spr;// = forwarding_reg_spr_data;
wire [31:0] ex_module_pdtr;
wire [31:0] ex_module_kpdtr;
wire [31:0] ex_module_tidr;
wire [31:0] ex_module_psr;
//System Register
wire sys_reg_sf = 1'b0;
wire sys_reg_of = 1'b0;
wire sys_reg_cf = 1'b0;
wire sys_reg_pf = 1'b0;
wire sys_reg_zf = 1'b0;
wire [4:0] sys_reg_flags = {sys_reg_sf, sys_reg_of, sys_reg_cf, sys_reg_pf, sys_reg_zf};
wire [31:0] sys_reg_data;
//Logic
wire logic_sf;
wire logic_of;
wire logic_cf;
wire logic_pf;
wire logic_zf;
wire [31:0] logic_data;
wire [4:0] logic_flags = {logic_sf, logic_of, logic_cf, logic_pf, logic_zf};
//Shift
wire shift_sf, shift_of, shift_cf, shift_pf, shift_zf;
wire [31:0] shift_data;
wire [4:0] shift_flags = {shift_sf, shift_of, shift_cf, shift_pf, shift_zf};
//Adder
wire [31:0] adder_data;
wire adder_sf, adder_of, adder_cf, adder_pf, adder_zf;
wire [4:0] adder_flags = {adder_sf, adder_of, adder_cf, adder_pf, adder_zf};
//Mul
wire [4:0] mul_flags;
wire [31:0] mul_data;
//Div
wire [31:0] div_out_data;
wire div_out_valid;
/*
//Load Store
wire ldst_spr_valid;
wire [31:0] ldst_spr;
wire ldst_pipe_rw;
wire [31:0] ldst_pipe_addr;
wire [31:0] ldst_pipe_pdt;
wire [31:0] ldst_pipe_data;
wire [1:0] ldst_pipe_order;
wire [1:0] load_pipe_shift;
wire [3:0] ldst_pipe_mask;
*/
//Branch
wire [31:0] branch_branch_addr;
wire branch_jump_valid;
wire branch_not_jump_valid;
wire branch_ib_valid;
wire branch_halt_valid;
//AFE
wire [31:0] result_data_with_afe;
//Flag
wire [4:0] sysreg_flags_register;
/*********************************************************************************************************
Debug Module
*********************************************************************************************************/
execute_debugger DEBUGGER(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Debugger Port
.iDEBUG_CTRL_REQ(iDEBUG_CTRL_REQ),
.iDEBUG_CTRL_STOP(iDEBUG_CTRL_STOP),
.iDEBUG_CTRL_START(iDEBUG_CTRL_START),
.oDEBUG_CTRL_ACK(oDEBUG_CTRL_ACK),
.oDEBUG_REG_OUT_FLAGR(oDEBUG_REG_OUT_FLAGR),
//Pipeline
.oPIPELINE_STOP(debugger_pipeline_stop),
//Registers
.iREGISTER_FLAGR(sysreg_flags_register),
//Busy
.iBUSY(lock_condition)
);
/*********************************************************************************************************
Forwarding
*********************************************************************************************************/
execute_forwarding_register FORWARDING_REGISTER(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iEVENT_HOLD || iEVENT_START || iRESET_SYNC),
//Writeback - General Register
.iWB_GR_VALID(b_valid && b_writeback),
.iWB_GR_DATA(result_data_with_afe),
.iWB_GR_DEST(b_destination),
.iWB_GR_DEST_SYSREG(b_destination_sysreg),
//Writeback - Stack Point Register
.iWB_SPR_VALID(b_valid && b_spr_writeback),
.iWB_SPR_DATA(b_r_spr),
//Writeback Auto - Stack Point Register
.iWB_AUTO_SPR_VALID(b_valid && b_destination_sysreg && b_writeback && b_destination == `SYSREG_SPR),
.iWB_AUTO_SPR_DATA(result_data_with_afe),
//Current -Stak Point Register
.iCUUR_SPR_DATA(iPREVIOUS_SPR),
//Writeback - FRCR
.iWB_FRCR_VALID(b_valid),
.iWB_FRCR_DATA(b_frcr),
//Current - FRCR
.iCUUR_FRCR_DATA(iPREVIOUS_SYSREG_FRCR),
//Fowerding Register Output
.oFDR_GR_VALID(forwarding_reg_gr_valid),
.oFDR_GR_DATA(forwarding_reg_gr_data),
.oFDR_GR_DEST(forwarding_reg_gr_dest),
.oFDR_GR_DEST_SYSREG(forwarding_reg_gr_dest_sysreg),
//Fowerding Register Output
.oFDR_SPR_VALID(forwarding_reg_spr_valid),
.oFDR_SPR_DATA(forwarding_reg_spr_data),
//Forwerding Register Output
.oFDR_FRCR_VALID(forwarding_reg_frcr_valid),
.oFDR_FRCR_DATA(forwarding_reg_frcr_data)
);
execute_forwarding FORWARDING_RS0(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iEVENT_HOLD || iEVENT_START || iRESET_SYNC),
//Writeback - General Register
.iWB_GR_VALID(b_valid && b_writeback),
.iWB_GR_DATA(result_data_with_afe),
.iWB_GR_DEST(b_destination),
.iWB_GR_DEST_SYSREG(b_destination_sysreg),
//Writeback - Stack Point Register
.iWB_SPR_VALID(b_valid && b_spr_writeback),
.iWB_SPR_DATA(b_r_spr),
//Writeback - FRCR
.iWR_FRCR_VALID(b_valid),
.iWR_FRCR_DATA(b_frcr),
//Previous Writeback - General Register
.iPREV_WB_GR_VALID(forwarding_reg_gr_valid),
.iPREV_WB_GR_DATA(forwarding_reg_gr_data),
.iPREV_WB_GR_DEST(forwarding_reg_gr_dest),
.iPREV_WB_GR_DEST_SYSREG(forwarding_reg_gr_dest_sysreg),
//Previous Writeback - Stack Point Register
.iPREV_WB_SPR_VALID(forwarding_reg_spr_valid),
.iPREV_WB_SPR_DATA(forwarding_reg_spr_data),
//Previous Writeback - FRCR
.iPREV_WB_FRCR_VALID(forwarding_reg_frcr_valid),
.iPREV_WB_FRCR_DATA(forwarding_reg_frcr_data),
//Source
.iPREVIOUS_SOURCE_SYSREG(iPREVIOUS_SOURCE0_SYSREG),
.iPREVIOUS_SOURCE_POINTER(iPREVIOUS_SOURCE0_POINTER),
.iPREVIOUS_SOURCE_IMM(1'b0/*iPREVIOUS_SOURCE0_IMM*/),
.iPREVIOUS_SOURCE_DATA(iPREVIOUS_SOURCE0),
.iPREVIOUS_SOURCE_PDTR(iPREVIOUS_SYSREG_PDTR),
.iPREVIOUS_SOURCE_KPDTR(iPREVIOUS_SYSREG_KPDTR),
.iPREVIOUS_SOURCE_TIDR(iPREVIOUS_SYSREG_TIDR),
.iPREVIOUS_SOURCE_PSR(iPREVIOUS_SYSREG_PSR),
//Output
.oNEXT_SOURCE_DATA(ex_module_source0),
.oNEXT_SOURCE_SPR(ex_module_spr),
.oNEXT_SOURCE_PDTR(ex_module_pdtr),
.oNEXT_SOURCE_KPDTR(ex_module_kpdtr),
.oNEXT_SOURCE_TIDR(ex_module_tidr),
.oNEXT_SOURCE_PSR(ex_module_psr)
);
/*
assign ex_module_pdtr = iPREVIOUS_SYSREG_PDTR;
assign ex_module_tidr = iPREVIOUS_SYSREG_TIDR;
assign ex_module_psr = iPREVIOUS_SYSREG_PSR;
*/
execute_forwarding FORWARDING_RS1(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iEVENT_HOLD || iEVENT_START || iRESET_SYNC),
//Writeback - General Register
.iWB_GR_VALID(b_valid && b_writeback),
.iWB_GR_DATA(result_data_with_afe),
.iWB_GR_DEST(b_destination),
.iWB_GR_DEST_SYSREG(b_destination_sysreg),
//Writeback - Stack Point Register
.iWB_SPR_VALID(b_valid && b_spr_writeback),
.iWB_SPR_DATA(b_r_spr),
//Writeback - FRCR
.iWR_FRCR_VALID(b_valid),
.iWR_FRCR_DATA(b_frcr),
//Previous Writeback - General Register
.iPREV_WB_GR_VALID(forwarding_reg_gr_valid),
.iPREV_WB_GR_DATA(forwarding_reg_gr_data),
.iPREV_WB_GR_DEST(forwarding_reg_gr_dest),
.iPREV_WB_GR_DEST_SYSREG(forwarding_reg_gr_dest_sysreg),
//Previous Writeback - Stack Point Register
.iPREV_WB_SPR_VALID(forwarding_reg_spr_valid),
.iPREV_WB_SPR_DATA(forwarding_reg_spr_data),
//Previous Writeback - FRCR
.iPREV_WB_FRCR_VALID(forwarding_reg_frcr_valid),
.iPREV_WB_FRCR_DATA(forwarding_reg_frcr_data),
//Source
.iPREVIOUS_SOURCE_SYSREG(iPREVIOUS_SOURCE1_SYSREG),
.iPREVIOUS_SOURCE_POINTER(iPREVIOUS_SOURCE1_POINTER),
.iPREVIOUS_SOURCE_IMM(iPREVIOUS_SOURCE1_IMM),
.iPREVIOUS_SOURCE_DATA(iPREVIOUS_SOURCE1),
.iPREVIOUS_SOURCE_PDTR(iPREVIOUS_SYSREG_PDTR),
.iPREVIOUS_SOURCE_KPDTR(iPREVIOUS_SYSREG_KPDTR),
.iPREVIOUS_SOURCE_TIDR(iPREVIOUS_SYSREG_TIDR),
.iPREVIOUS_SOURCE_PSR(iPREVIOUS_SYSREG_PSR),
//Output
.oNEXT_SOURCE_DATA(ex_module_source1),
.oNEXT_SOURCE_SPR(),
.oNEXT_SOURCE_PDTR(),
.oNEXT_SOURCE_KPDTR(),
.oNEXT_SOURCE_TIDR(),
.oNEXT_SOURCE_PSR()
);
/****************************************
Flag Register
****************************************/
execute_flag_register REG_FLAG(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Control
.iCTRL_HOLD(iEVENT_HOLD || iEVENT_HOLD || iEVENT_START),
//PFLAGR
.iPFLAGR_VALID(iEVENT_IRQ_BACK2FRONT),
.iPFLAGR(iSYSREG_PFLAGR[4:0]),
//Prev
.iPREV_INST_VALID(iPREVIOUS_VALID),
.iPREV_BUSY(lock_condition),
.iPREV_FLAG_WRITE(iPREVIOUS_FLAGS_WRITEBACK),
//Shift
.iSHIFT_VALID(iPREVIOUS_EX_SHIFT),
.iSHIFT_FLAG(shift_flags),
//Adder
.iADDER_VALID(iPREVIOUS_EX_ADDER),
.iADDER_FLAG(adder_flags),
//Mul
.iMUL_VALID(iPREVIOUS_EX_MUL),
.iMUL_FLAG(mul_flags),
//Logic
.iLOGIC_VALID(iPREVIOUS_EX_LOGIC),
.iLOGIC_FLAG(logic_flags),
//oUTPUT
.oFLAG(sysreg_flags_register)
);
/*********************************************************************************************************
Execute
*********************************************************************************************************/
/****************************************
Logic
****************************************/
wire [4:0] logic_cmd;
execute_logic_decode EXE_LOGIC_DECODER(
.iPREV_INST(iPREVIOUS_CMD),
.oNEXT_INST(logic_cmd)
);
execute_logic #(32) EXE_LOGIC(
.iCONTROL_CMD(logic_cmd),
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.oDATA(logic_data),
.oSF(logic_sf),
.oOF(logic_of),
.oCF(logic_cf),
.oPF(logic_pf),
.oZF(logic_zf)
);
/****************************************
Shift
****************************************/
wire [2:0] shift_cmd;
execute_shift_decode EXE_SHIFT_DECODER(
.iPREV_INST(iPREVIOUS_CMD),
.oNEXT_INST(shift_cmd)
);
execute_shift #(32) EXE_SHIFT(
.iCONTROL_MODE(shift_cmd),
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.oDATA(shift_data),
.oSF(shift_sf),
.oOF(shift_of),
.oCF(shift_cf),
.oPF(shift_pf),
.oZF(shift_zf)
);
/****************************************
Adder
****************************************/
execute_adder #(32) EXE_ADDER(
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.iADDER_CMD(iPREVIOUS_CMD),
.oDATA(adder_data),
.oSF(adder_sf),
.oOF(adder_of),
.oCF(adder_cf),
.oPF(adder_pf),
.oZF(adder_zf)
);
/****************************************
Mul
****************************************/
execute_mul EXE_MUL(
.iCMD(iPREVIOUS_CMD),
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.oDATA(mul_data),
.oFLAGS(mul_flags)
);
/*
wire [4:0] mul_flags = (iPREVIOUS_CMD == `EXE_MUL_MULH)? {mul_sf_h, mul_of_h, mul_cf_h, mul_pf_h, mul_zf_h} : {mul_sf_l, mul_of_l, mul_cf_l, mul_pf_l, mul_zf_l};
wire [31:0] mul_data = (iPREVIOUS_CMD == `EXE_MUL_MULH)? mul_tmp[63:32] : mul_tmp[31:0];
execute_mul_booth32 EXE_MUL_BOOTH(
//iDATA
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
//oDATA
.oDATA(mul_tmp),
.oHSF(mul_sf_h),
.oHCF(mul_cf_h),
.oHOF(mul_of_h),
.oHPF(mul_pf_h),
.oHZF(mul_zf_h),
.oLSF(mul_sf_l),
.oLCF(mul_cf_l),
.oLOF(mul_of_l),
.oLPF(mul_pf_l),
.oLZF(mul_zf_l)
);
*/
/****************************************
Div
****************************************/
execute_div EXE_DIV(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iEVENT_HOLD || iEVENT_START || iRESET_SYNC),
//FLAG
.oFLAG_WAITING_DIV(div_wait),
//Prev
.iPREV_VALID(iPREVIOUS_VALID),
.iPREV_UDIV(iPREVIOUS_EX_UDIV),
.iPREV_SDIV(iPREVIOUS_EX_SDIV),
.iCMD(iPREVIOUS_CMD),
//iDATA
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
//oDATA
.iBUSY(lock_condition),
.oDATA_VALID(div_out_valid),
.oDATA(div_out_data)
);
/****************************************
Address calculate(Load Store)
****************************************/
//Load Store
wire ldst_spr_valid;
wire [31:0] ldst_spr;
wire ldst_pipe_rw;
wire [31:0] ldst_pipe_pdt;
wire [31:0] ldst_pipe_addr;
wire [31:0] ldst_pipe_data;
wire [1:0] ldst_pipe_order;
wire [1:0] load_pipe_shift;
wire [3:0] ldst_pipe_mask;
execute_adder_calc LDST_CALC_ADDR(
//Prev
.iCMD(iPREVIOUS_CMD),
.iLOADSTORE_MODE(iPREVIOUS_EX_LDST),
.iSOURCE0(ex_module_source0),
.iSOURCE1(ex_module_source1),
.iADV_ACTIVE(iPREVIOUS_ADV_ACTIVE),
//.iADV_DATA({26'h0, iPREVIOUS_ADV_DATA}),
.iADV_DATA({{26{iPREVIOUS_ADV_DATA[5]}}, iPREVIOUS_ADV_DATA}),
.iSPR(ex_module_spr),
.iPSR(ex_module_psr),
.iPDTR(ex_module_pdtr),
.iKPDTR(ex_module_kpdtr),
.iPC(iPREVIOUS_PC - 32'h4),
//Output - Writeback
.oOUT_SPR_VALID(ldst_spr_valid),
.oOUT_SPR(ldst_spr),
.oOUT_DATA(),
//Output - LDST Pipe
.oLDST_RW(ldst_pipe_rw),
.oLDST_PDT(ldst_pipe_pdt),
.oLDST_ADDR(ldst_pipe_addr),
.oLDST_DATA(ldst_pipe_data),
.oLDST_ORDER(ldst_pipe_order),
.oLDST_MASK(ldst_pipe_mask),
.oLOAD_SHIFT(load_pipe_shift)
);
//Load Store
wire [1:0] load_shift;
wire [3:0] load_mask;
execute_load_store STAGE_LDST(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Event CTRL
.iEVENT_HOLD(iEVENT_HOLD),
.iEVENT_START(iEVENT_START),
.iEVENT_IRQ_FRONT2BACK(iEVENT_IRQ_FRONT2BACK),
.iEVENT_IRQ_BACK2FRONT(iEVENT_IRQ_BACK2FRONT),
.iEVENT_END(iEVENT_END),
//State
.iSTATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
.iSTATE_LOAD(b_state == L_PARAM_STT_LOAD),
.iSTATE_STORE(b_state == L_PARAM_STT_STORE),
/*************************************
Previous
*************************************/
//Previous - PREDICT
.iPREV_VALID(iPREVIOUS_VALID),
.iPREV_EX_LDST(iPREVIOUS_EX_LDST),
//System Register
.iPREV_PSR(ex_module_psr),
.iPREV_TIDR(ex_module_tidr),
//Writeback
.iPREV_SPR_VALID(ldst_spr_valid),
.iPREV_SPR(ldst_spr),
//Output - LDST Pipe
.iPREV_LDST_RW(ldst_pipe_rw),
.iPREV_LDST_PDT(ldst_pipe_pdt),
.iPREV_LDST_ADDR(ldst_pipe_addr),
.iPREV_LDST_DATA(ldst_pipe_data),
.iPREV_LDST_ORDER(ldst_pipe_order),
.iPREV_LDST_MASK(ldst_pipe_mask),
.iPREV_LOAD_SHIFT(load_pipe_shift),
/*************************************
MA
*************************************/
//Output - LDST Pipe
.oLDST_REQ(oDATAIO_REQ),
.iLDST_BUSY(iEVENT_HOLD || io_lock_condition),
.oLDST_RW(oDATAIO_RW),
.oLDST_PDT(oDATAIO_PDT),
.oLDST_ADDR(oDATAIO_ADDR),
.oLDST_DATA(oDATAIO_DATA),
.oLDST_ORDER(oDATAIO_ORDER),
.oLDST_MASK(oDATAIO_MASK),
.oLDST_ASID(oDATAIO_ASID),
.oLDST_MMUMOD(oDATAIO_MMUMOD),
.oLDST_MMUPS(oDATAIO_MMUPS),
.iLDST_VALID(iDATAIO_REQ),
/*************************************
Next
*************************************/
//Next
.iNEXT_BUSY(lock_condition),
.oNEXT_VALID(),
.oNEXT_SPR_VALID(),
.oNEXT_SPR(),
.oNEXT_SHIFT(load_shift), //It's for after load data sigals
.oNEXT_MASK(load_mask) //It's for after load data sigals
);
//Load Data Mask and Shft
wire [31:0] load_data;
execute_load_data LOAD_MASK(
.iMASK(load_mask),
.iSHIFT(load_shift),
.iDATA(iDATAIO_DATA),
.oDATA(load_data)
);
/****************************************
System Register
****************************************/
wire sysreg_ctrl_idt_valid;
wire sysreg_ctrl_pdt_valid;
wire sysreg_ctrl_psr_valid;
wire [31:0] sysreg_reload_addr;
execute_sys_reg EXE_SYS_REG(
.iCMD(iPREVIOUS_CMD),
.iPC(iPREVIOUS_PC),
.iSOURCE0(ex_module_source0),
.iSOURCE1(ex_module_source1),
.oOUT(sys_reg_data),
.oCTRL_IDT_VALID(sysreg_ctrl_idt_valid),
.oCTRL_PDT_VALID(sysreg_ctrl_pdt_valid),
.oCTRL_PSR_VALID(sysreg_ctrl_psr_valid),
.oCTRL_RELOAD_ADDR(sysreg_reload_addr)
);
/****************************************
Jump
****************************************/
//Branch
execute_branch EXE_BRANCH(
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.iPC(iPREVIOUS_PC - 32'h4),
.iFLAG(sysreg_flags_register),
.iCC(iPREVIOUS_CC_AFE),
.iCMD(iPREVIOUS_CMD),
.oBRANCH_ADDR(branch_branch_addr),
.oJUMP_VALID(branch_jump_valid),
.oNOT_JUMP_VALID(branch_not_jump_valid),
.oIB_VALID(branch_ib_valid),
.oHALT_VALID(branch_halt_valid)
);
//Branch Predict
wire branch_with_predict_predict_ena;
wire branch_with_predict_predict_hit;
wire branch_with_predict_branch_valid;
wire branch_with_predict_ib_valid;
wire [31:0] branch_with_predict_jump_addr;
//Branch Predicter
execute_branch_predict EXE_BRANCH_PREDICT(
//State
.iSTATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
//Previous - PREDICT
.iPREV_VALID(iPREVIOUS_VALID),
.iPREV_EX_BRANCH(iPREVIOUS_EX_BRANCH),
.iPREV_BRANCH_PREDICT_ENA(iPREVIOUS_BRANCH_PREDICT),
.iPREV_BRANCH_PREDICT_ADDR(iPREVIOUS_BRANCH_PREDICT_ADDR),
//BRANCH
.iPREV_BRANCH_VALID(branch_jump_valid),
.iPREV_BRANCH_IB_VALID(branch_ib_valid),
.iPREV_JUMP_ADDR(branch_branch_addr),
//Next
.iNEXT_BUSY(lock_condition),
.oNEXT_PREDICT_HIT(branch_with_predict_predict_hit)
);
wire branch_valid_with_predict_miss = branch_not_jump_valid && iPREVIOUS_BRANCH_PREDICT; //not need jump, but predict jump
wire branch_valid_with_predict_addr_miss = branch_jump_valid && !(iPREVIOUS_BRANCH_PREDICT && branch_with_predict_predict_hit); //need jump, but predict addr is diffelent (predict address diffelent)
wire branch_valid_with_predict = branch_valid_with_predict_miss || branch_valid_with_predict_addr_miss;
//Jump
wire jump_stage_predict_ena;
wire jump_stage_predict_hit;
wire jump_stage_jump_valid;
wire [31:0] jump_stage_jump_addr;
wire jump_normal_jump_inst;
wire jump_stage_branch_valid;
wire jump_stage_branch_ib_valid;
wire jump_stage_sysreg_idt_valid;
wire jump_stage_sysreg_pdt_valid;
wire jump_stage_sysreg_psr_valid;
execute_jump STAGE_JUMP(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Event CTRL
.iEVENT_HOLD(iEVENT_HOLD),
.iEVENT_START(iEVENT_START),
.iEVENT_IRQ_FRONT2BACK(iEVENT_IRQ_FRONT2BACK),
.iEVENT_IRQ_BACK2FRONT(iEVENT_IRQ_BACK2FRONT),
.iEVENT_END(iEVENT_END),
//State
.iSTATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
//Previous - PREDICT
.iPREV_VALID(iPREVIOUS_VALID),
.iPREV_EX_BRANCH(iPREVIOUS_EX_BRANCH),
.iPREV_EX_SYS_REG(iPREVIOUS_EX_SYS_REG),
.iPREV_PC(iPREVIOUS_PC),
.iPREV_BRANCH_PREDICT_ENA(iPREVIOUS_BRANCH_PREDICT),
.iPREV_BRANCH_PREDICT_HIT(branch_with_predict_predict_hit),
.iPREV_BRANCH_NORMAL_JUMP_INST(branch_jump_valid || branch_not_jump_valid), //ignore branch predict result
//BRANCH
.iPREV_BRANCH_PREDICT_MISS_VALID(branch_valid_with_predict_miss),
.iPREV_BRANCH_PREDICT_ADDR_MISS_VALID(branch_valid_with_predict_addr_miss),
.iPREV_BRANCH_IB_VALID(branch_ib_valid),
.iPREV_BRANCH_ADDR(branch_branch_addr),
//SYSREG JUMP
.iPREV_SYSREG_IDT_VALID(sysreg_ctrl_idt_valid),
.iPREV_SYSREG_PDT_VALID(sysreg_ctrl_pdt_valid),
.iPREV_SYSREG_PSR_VALID(sysreg_ctrl_psr_valid),
.iPREV_SYSREG_ADDR(sysreg_reload_addr),
/*************************************
Next
*************************************/
//Next
.iNEXT_BUSY(lock_condition),
.oNEXT_PREDICT_ENA(jump_stage_predict_ena),
.oNEXT_PREDICT_HIT(jump_stage_predict_hit),
.oNEXT_JUMP_VALID(jump_stage_jump_valid),
.oNEXT_JUMP_ADDR(jump_stage_jump_addr),
//for Branch Predictor
.oNEXT_NORMAL_JUMP_INST(jump_normal_jump_inst), //ignore branch predict result
//Kaind of Jump
.oNEXT_TYPE_BRANCH_VALID(jump_stage_branch_valid),
.oNEXT_TYPE_BRANCH_IB_VALID(jump_stage_branch_ib_valid),
.oNEXT_TYPE_SYSREG_IDT_VALID(jump_stage_sysreg_idt_valid),
.oNEXT_TYPE_SYSREG_PDT_VALID(jump_stage_sysreg_pdt_valid),
.oNEXT_TYPE_SYSREG_PSR_VALID(jump_stage_sysreg_psr_valid)
);
/*********************************************************************************************************
Exception
*********************************************************************************************************/
wire except_inst_valid;
wire [6:0] except_inst_num;
wire except_ldst_valid;
wire [6:0] except_ldst_num;
execute_exception_check_inst EXE_EXCEPTION_INST(
//Execute Module State
.iPREV_STATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
//Previous Instruxtion
.iPREV_FAULT_PAGEFAULT(iPREVIOUS_FAULT_PAGEFAULT),
.iPREV_FAULT_PRIVILEGE_ERROR(iPREVIOUS_FAULT_PRIVILEGE_ERROR),
.iPREV_FAULT_INVALID_INST(iPREVIOUS_FAULT_INVALID_INST),
.iPREV_FAULT_DIVIDE_ZERO((iPREVIOUS_EX_SDIV || iPREVIOUS_EX_UDIV) && (ex_module_source1 == 32'h0)),
//Output Exception
.oEXCEPT_VALID(except_inst_valid),
.oEXCEPT_NUM(except_inst_num)
);
execute_exception_check_ldst EXE_EXCEPTION_LDST(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Event CTRL
.iEVENT_HOLD(iEVENT_HOLD),
.iEVENT_START(iEVENT_START),
.iEVENT_IRQ_FRONT2BACK(iEVENT_IRQ_FRONT2BACK),
.iEVENT_IRQ_BACK2FRONT(iEVENT_IRQ_BACK2FRONT),
.iEVENT_END(iEVENT_END),
//Execute Module State
.iPREV_STATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
.iPREV_STATE_LDST(b_state == L_PARAM_STT_LOAD),
//Previous Instruxtion
.iPREV_VALID(b_state == L_PARAM_STT_NORMAL && iPREVIOUS_VALID && !lock_condition),
.iPREV_KERNEL_ACCESS(iPREVIOUS_KERNEL_ACCESS),
.iPREV_PAGING_ENA(iPREVIOUS_PAGING_ENA),
.iPREV_LDST_RW(ldst_pipe_rw),
//Load Store
.iLDST_VALID(iDATAIO_REQ),
.iLDST_MMU_FLAG(iDATAIO_MMU_FLAGS),
//Output Exception
.oEXCEPT_VALID(except_ldst_valid),
.oEXCEPT_NUM(except_ldst_num)
);
wire exception_valid;
wire [6:0] exception_num;
wire [31:0] exception_fi0r;
wire [31:0] exception_fi1r;
execute_exception STAGE_EXCEPTION(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Event CTRL
.iEVENT_HOLD(iEVENT_HOLD),
.iEVENT_START(iEVENT_START),
.iEVENT_IRQ_FRONT2BACK(iEVENT_IRQ_FRONT2BACK),
.iEVENT_IRQ_BACK2FRONT(iEVENT_IRQ_BACK2FRONT),
.iEVENT_END(iEVENT_END),
//Execute Module State
.iPREV_STATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
.iPREV_STATE_LDST(b_state == L_PARAM_STT_LOAD),
//Previous Instruxtion
.iPREV_VALID(b_state == L_PARAM_STT_NORMAL && iPREVIOUS_VALID && !lock_condition),
.iPREV_KERNEL_ACCESS(iPREVIOUS_KERNEL_ACCESS),
.iPREV_PC(iPREVIOUS_PC),
//Instruction Exception
.iEXCEPT_INST_VALID(except_inst_valid),
.iEXCEPT_INST_NUM(except_inst_num),
//Load Store Exception
.iEXCEPT_LDST_VALID(except_ldst_valid),
.iEXCEPT_LDST_NUM(except_ldst_num),
//Output Exception
.oEXCEPT_VALID(exception_valid),
.oEXCEPT_NUM(exception_num),
.oEXCEPT_FI0R(exception_fi0r),
.oEXCEPT_FI1R(exception_fi1r)
);
/*********************************************************************************************************
Pipelined Register
*********************************************************************************************************/
/****************************************
State
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= L_PARAM_STT_NORMAL;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_state <= L_PARAM_STT_NORMAL;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_VALID && !lock_condition)begin
//Fault Check
if(except_inst_valid)begin
b_state <= L_PARAM_STT_EXCEPTION;
end
//Execute
else begin
//Div instruction
if(iPREVIOUS_EX_SDIV || iPREVIOUS_EX_UDIV)begin
b_state <= L_PARAM_STT_DIV_WAIT;
end
//Load Store
else if(iPREVIOUS_EX_LDST)begin
if(!ldst_pipe_rw)begin
b_state <= L_PARAM_STT_LOAD;
end
else begin
b_state <= L_PARAM_STT_STORE;
end
end
//Branch
else if(iPREVIOUS_EX_BRANCH)begin
//Halt
if(branch_halt_valid)begin
b_state <= L_PARAM_STT_HALT;
end
//Interrupt Return Branch
else if(branch_ib_valid)begin
b_state <= L_PARAM_STT_BRANCH;
end
//Branch(with Branch predict)
else if(branch_valid_with_predict)begin
b_state <= L_PARAM_STT_BRANCH;
end
end
//System Register(for need re-load instructions)
if(iPREVIOUS_EX_SYS_REG)begin
if(sysreg_ctrl_idt_valid || sysreg_ctrl_pdt_valid || sysreg_ctrl_psr_valid)begin
b_state <= L_PARAM_STT_RELOAD;
end
end
end
end
end
L_PARAM_STT_DIV_WAIT:
begin
if(div_out_valid)begin
b_state <= L_PARAM_STT_NORMAL;
end
end
L_PARAM_STT_LOAD:
begin
if(iDATAIO_REQ)begin
//Pagefault || Exception Check(Load)
if(except_ldst_valid)begin
b_state <= L_PARAM_STT_EXCEPTION;
end
//Non Error
else begin
b_state <= L_PARAM_STT_NORMAL;
end
end
end
L_PARAM_STT_STORE:
begin
if(iDATAIO_REQ)begin
//Pagefault
//Exception Check(Load)
if(except_ldst_valid)begin
b_state <= L_PARAM_STT_EXCEPTION;
end
//Non Error
else begin
b_state <= L_PARAM_STT_NORMAL;
end
end
end
L_PARAM_STT_BRANCH:
begin
//Branch Wait
b_state <= L_PARAM_STT_BRANCH;
end
L_PARAM_STT_RELOAD:
begin
//Branch Wait
b_state <= L_PARAM_STT_RELOAD;
end
L_PARAM_STT_EXCEPTION:
begin
b_state <= L_PARAM_STT_EXCEPTION;
end
L_PARAM_STT_HALT:
begin
b_state <= L_PARAM_STT_HALT;
end
endcase
end
end //state always
/****************************************
For PC
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_pc <= 32'h0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_pc <= 32'h0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_VALID && !lock_condition)begin
b_pc <= iPREVIOUS_PC;
end
end
default:
begin
b_pc <= b_pc;
end
endcase
end
end
/****************************************
For FRCR
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_frcr <= 64'h0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_frcr <= 64'h0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_VALID && !lock_condition)begin
b_frcr <= iPREVIOUS_SYSREG_FRCR;
end
end
default:
begin
b_frcr <= b_frcr;
end
endcase
end
end
/****************************************
Result Data
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_r_data <= 32'h0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_r_data <= 32'h0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_VALID && !lock_condition)begin
//SPR Read Store
if(iPREVIOUS_EX_SYS_LDST)begin
b_r_data <= ldst_spr;
end
//System Register
else if(iPREVIOUS_EX_SYS_REG)begin
b_r_data <= sys_reg_data;
end
//Logic
else if(iPREVIOUS_EX_LOGIC)begin
b_r_data <= logic_data;
end
//SHIFT
else if(iPREVIOUS_EX_SHIFT)begin
b_r_data <= shift_data;
end
//ADDER
else if(iPREVIOUS_EX_ADDER)begin
b_r_data <= adder_data;
end
//MUL
else if(iPREVIOUS_EX_MUL)begin
b_r_data <= mul_data;
end
//Error
else begin
b_r_data <= 32'h0;
end
end
end
L_PARAM_STT_DIV_WAIT:
begin
if(div_out_valid)begin
b_r_data <= div_out_data;
end
else begin
b_r_data <= 32'h0;
end
end
L_PARAM_STT_LOAD:
begin
if(iDATAIO_REQ)begin
b_r_data <= load_data;
end
end
default:
begin
b_r_data <= 32'h0;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_r_spr <= 32'h0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_r_spr <= 32'h0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_EX_LDST || iPREVIOUS_EX_SYS_LDST)begin
b_r_spr <= ldst_spr;
end
end
default:
begin
b_r_spr <= b_r_spr;
end
endcase
end
end
/****************************************
Execute Category
****************************************/
reg b_ex_category_ldst;
reg b_ex_category_branch;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_ex_category_ldst <= 1'b0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_ex_category_ldst <= 1'b0;
end
else begin
if(b_state == L_PARAM_STT_NORMAL && iPREVIOUS_VALID && !lock_condition)begin
b_ex_category_ldst <= iPREVIOUS_EX_LDST;
b_ex_category_branch <= iPREVIOUS_EX_BRANCH;
end
end
end
/****************************************
Pass Line
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_writeback <= 1'b0;
b_destination_sysreg <= 1'b0;
b_destination <= 5'h0;
b_afe <= 4'h0;
b_spr_writeback <= 1'b0;
end
else if(iEVENT_HOLD || iRESET_SYNC || iEVENT_START)begin
b_writeback <= 1'b0;
b_destination_sysreg <= 1'b0;
b_destination <= 5'h0;
b_afe <= 4'h0;
b_spr_writeback <= 1'b0;
end
else if(b_state == L_PARAM_STT_NORMAL)begin
if(iPREVIOUS_VALID && !lock_condition)begin
if(iPREVIOUS_EX_SDIV || iPREVIOUS_EX_UDIV || iPREVIOUS_EX_LDST || iPREVIOUS_EX_SYS_LDST || iPREVIOUS_EX_SYS_REG || iPREVIOUS_EX_LOGIC || iPREVIOUS_EX_SHIFT || iPREVIOUS_EX_ADDER || iPREVIOUS_EX_MUL)begin
b_writeback <= iPREVIOUS_WRITEBACK && (!except_inst_valid);
b_destination_sysreg <= iPREVIOUS_DESTINATION_SYSREG;
b_destination <= iPREVIOUS_DESTINATION;
b_afe <= iPREVIOUS_CC_AFE;
b_spr_writeback <= (iPREVIOUS_EX_LDST || iPREVIOUS_EX_SYS_LDST) && ldst_spr_valid;
end
else if(iPREVIOUS_EX_BRANCH)begin
b_writeback <= 1'b0;
b_destination_sysreg <= iPREVIOUS_DESTINATION_SYSREG;
b_destination <= iPREVIOUS_DESTINATION;
b_afe <= iPREVIOUS_CC_AFE;
b_spr_writeback <= 1'b0;
end
end
end
end
/****************************************
Valid
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_valid <= 1'b0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_valid <= 1'b0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
//Fault Check
if(iPREVIOUS_VALID && !lock_condition && except_inst_valid)begin
b_valid <= 1'b1;
end
else if(iPREVIOUS_VALID && !lock_condition && (iPREVIOUS_EX_SDIV || iPREVIOUS_EX_UDIV || (iPREVIOUS_EX_LDST && !ldst_pipe_rw)))begin
b_valid <= 1'b0;
end
else if(iPREVIOUS_VALID && !lock_condition && iPREVIOUS_EX_BRANCH)begin
//Halt
if(branch_halt_valid)begin
b_valid <= 1'b1;
end
//Interrupt Return Branch
else if(branch_ib_valid)begin
b_valid <= 1'b1;
end
//Branch(with Branch predict) - True
else if(branch_valid_with_predict)begin
b_valid <= 1'b1;
end
else if(branch_with_predict_predict_hit)begin
b_valid <= 1'b1;
end
else begin
//b_valid <= 1'b0;
b_valid <= 1'b1;
end
end
else begin
b_valid <= iPREVIOUS_VALID && !lock_condition;
end
end
L_PARAM_STT_DIV_WAIT:
begin
if(div_out_valid)begin
b_valid <= 1'b1;
end
end
L_PARAM_STT_LOAD:
begin
if(iDATAIO_REQ)begin
//not error
if(!except_ldst_valid)begin
b_valid <= 1'b1;
end
end
end
L_PARAM_STT_STORE:
begin
if(iDATAIO_REQ)begin
//not error
if(!except_ldst_valid)begin
b_valid <= 1'b1;
end
end
end
default:
begin
b_valid <= 1'b0;
end
endcase
end
end
/*********************************************************************************************************
AFE
*********************************************************************************************************/
/****************************************
AFE - for Load Store
****************************************/
wire [31:0] afe_ldst_data_result;
execute_afe_load_store AFE_LDST(
//AFE-Conrtol
.iAFE_CODE(b_afe),
//Data-In/Out
.iDATA(b_r_data),
.oDATA(afe_ldst_data_result)
);
/****************************************
AFE - Select
****************************************/
execute_afe AFE_SELECT(
.iAFE_LDST(b_ex_category_ldst),
.iAFE_LDST_DATA(afe_ldst_data_result),
.iRAW_DATA(b_r_data),
.oDATA(result_data_with_afe)
);
/*********************************************************************************************************
Assign
*********************************************************************************************************/
//Fault
assign oFAULT_VALID = exception_valid;
assign oFAULT_NUM = exception_num;
assign oFAULT_FI0R = exception_fi0r;
assign oFAULT_FI1R = exception_fi1r;
//Branch Predict
assign oBPREDICT_JUMP_INST = jump_normal_jump_inst; //Is normal jump Instruction?
assign oBPREDICT_PREDICT = jump_stage_predict_ena;
assign oBPREDICT_HIT = b_ex_category_branch && (jump_stage_predict_hit);
assign oBPREDICT_JUMP = jump_stage_jump_valid; //it same of Unhit
assign oBPREDICT_JUMP_ADDR = jump_stage_jump_addr;
assign oBPREDICT_INST_ADDR = b_pc - 32'h00000004;
//Branch - Controller
assign oBRANCH_ADDR = jump_stage_jump_addr;
assign oJUMP_VALID = jump_stage_jump_valid;
assign oINTR_VALID = jump_stage_branch_ib_valid;
assign oIDTSET_VALID = jump_stage_sysreg_idt_valid;
assign oPDTSET_VALID = jump_stage_sysreg_pdt_valid;
assign oPSRSET_VALID = jump_stage_sysreg_psr_valid;
//Writeback
assign oNEXT_VALID = b_valid && !iEVENT_HOLD;
assign oNEXT_DATA = result_data_with_afe;
assign oNEXT_DESTINATION = b_destination;
assign oNEXT_DESTINATION_SYSREG = b_destination_sysreg;
assign oNEXT_WRITEBACK = b_writeback && !except_ldst_valid && (b_state != L_PARAM_STT_BRANCH);
assign oNEXT_SPR_WRITEBACK = b_spr_writeback && !except_ldst_valid && (b_state != L_PARAM_STT_BRANCH);
assign oNEXT_SPR = b_r_spr;
assign oNEXT_FRCR = b_frcr;
assign oNEXT_PC = b_pc;
//System Register Writeback
assign oPDTR_WRITEBACK = b_destination_sysreg && b_writeback && (b_destination == `SYSREG_PDTR);
assign oEXCEPTION_LOCK = (b_state == L_PARAM_STT_DIV_WAIT) || (b_state == L_PARAM_STT_LOAD) || (b_state == L_PARAM_STT_STORE) || (b_state == L_PARAM_STT_RELOAD);
assign oSYSREG_FLAGR = {27'h0, sysreg_flags_register};
/*********************************************************************************************************
Assertion
*********************************************************************************************************/
/*************************************************
Assertion - SVA
*************************************************/
//synthesis translate_off
`ifdef MIST1032ISA_SVA_ASSERTION
property PRO_DATAPIPE_REQ_ACK;
@(posedge iCLOCK) disable iff (!inRESET || iEVENT_START || iRESET_SYNC) (oDATAIO_REQ |-> ##[1:50] iDATAIO_REQ);
endproperty
assert property(PRO_DATAPIPE_REQ_ACK);
`endif
//synthesis translate_on
/*************************************************
Verilog Assertion
*************************************************/
//synthesis translate_off
function [31:0] func_assert_write_data;
input [4:0] func_mask;
input [31:0] func_data;
begin
if(func_mask == 4'hf)begin
func_assert_write_data = func_data;
end
else if(func_mask == 4'b0011)begin
func_assert_write_data = {16'h0, func_data[15:0]};
end
else if(func_mask == 4'b1100)begin
func_assert_write_data = {16'h0, func_data[31:16]};
end
else if(func_mask == 4'b1000)begin
func_assert_write_data = {24'h0, func_data[31:24]};
end
else if(func_mask == 4'b0100)begin
func_assert_write_data = {24'h0, func_data[23:16]};
end
else if(func_mask == 4'b0010)begin
func_assert_write_data = {24'h0, func_data[15:8]};
end
else if(func_mask == 4'b0001)begin
func_assert_write_data = {24'h0, func_data[7:0]};
end
else begin
func_assert_write_data = 32'h0;
end
end
endfunction
//`ifdef MIST1032ISA_VLG_ASSERTION
localparam time_ena = 0;
/*
integer F_HANDLE;
initial F_HANDLE = $fopen("ldst_time_dump.log");
*/
wire [31:0] for_assertion_store_real_data = func_assert_write_data(oDATAIO_MASK, oDATAIO_DATA);
//synthesis translate_on
/*
--------------------------------
[S], "PC", "spr", "addr", "data"
[L], "PC", "spr", "addr", "data"
--------------------------------
*/
endmodule
`default_nettype wire |
`timescale 1 ns / 1 ps
module hapara_axis_id_dispatcher_v1_0 #
(
// Users to add parameters here
parameter integer NUM_SLAVES = 1,
parameter integer DATA_WIDTH = 32
// User parameters ends
)
(
// Users to add ports here
input wire [NUM_SLAVES-1: 0] priority_sel,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXIS
input wire s00_axis_aclk,
input wire s00_axis_aresetn,
output wire s00_axis_tready,
input wire [DATA_WIDTH-1 : 0] s00_axis_tdata,
input wire s00_axis_tlast,
input wire s00_axis_tvalid,
// Ports of Axi Master Bus Interface M00_AXIS
input wire m00_axis_aclk,
input wire m00_axis_aresetn,
output wire m00_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m00_axis_tdata,
output wire m00_axis_tlast,
input wire m00_axis_tready,
// Ports of Axi Master Bus Interface M01_AXIS
input wire m01_axis_aclk,
input wire m01_axis_aresetn,
output wire m01_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m01_axis_tdata,
output wire m01_axis_tlast,
input wire m01_axis_tready,
// Ports of Axi Master Bus Interface M02_AXIS
input wire m02_axis_aclk,
input wire m02_axis_aresetn,
output wire m02_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m02_axis_tdata,
output wire m02_axis_tlast,
input wire m02_axis_tready,
// Ports of Axi Master Bus Interface M03_AXIS
input wire m03_axis_aclk,
input wire m03_axis_aresetn,
output wire m03_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m03_axis_tdata,
output wire m03_axis_tlast,
input wire m03_axis_tready,
// Ports of Axi Master Bus Interface M04_AXIS
input wire m04_axis_aclk,
input wire m04_axis_aresetn,
output wire m04_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m04_axis_tdata,
output wire m04_axis_tlast,
input wire m04_axis_tready,
// Ports of Axi Master Bus Interface M05_AXIS
input wire m05_axis_aclk,
input wire m05_axis_aresetn,
output wire m05_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m05_axis_tdata,
output wire m05_axis_tlast,
input wire m05_axis_tready,
// Ports of Axi Master Bus Interface M06_AXIS
input wire m06_axis_aclk,
input wire m06_axis_aresetn,
output wire m06_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m06_axis_tdata,
output wire m06_axis_tlast,
input wire m06_axis_tready,
// Ports of Axi Master Bus Interface M07_AXIS
input wire m07_axis_aclk,
input wire m07_axis_aresetn,
output wire m07_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m07_axis_tdata,
output wire m07_axis_tlast,
input wire m07_axis_tready
);
localparam dispatch = 4'b0001;
localparam waitslave = 4'b0010;
localparam terminate = 4'b0100;
localparam waitdata = 4'b1000;
reg [3 : 0] curr_state;
reg [3 : 0] next_state;
// Logic for curr_state
always @(posedge s00_axis_aclk) begin
if (!s00_axis_aresetn) begin
// reset
curr_state <= dispatch;
end
else begin
curr_state <= next_state;
end
end
wire slaves_ready;
// Logic for next_state
always @(s00_axis_tdata or slaves_ready or curr_state) begin
case (curr_state)
dispatch:
if (s00_axis_tdata == {DATA_WIDTH{1'b1}}) begin
next_state = waitslave;
end
else begin
next_state = dispatch;
end
waitslave:
if (slaves_ready) begin
next_state = terminate;
end
else begin
next_state = waitslave;
end
terminate:
next_state = waitdata;
waitdata:
if (s00_axis_tdata != {DATA_WIDTH{1'b1}}) begin
next_state = dispatch;
end
else begin
next_state = waitdata;
end
default:
next_state = 3'bxxx;
endcase
end
assign m00_axis_tdata = s00_axis_tdata;
assign m00_axis_tlast = s00_axis_tlast;
assign m01_axis_tdata = s00_axis_tdata;
assign m01_axis_tlast = s00_axis_tlast;
assign m02_axis_tdata = s00_axis_tdata;
assign m02_axis_tlast = s00_axis_tlast;
assign m03_axis_tdata = s00_axis_tdata;
assign m03_axis_tlast = s00_axis_tlast;
assign m04_axis_tdata = s00_axis_tdata;
assign m04_axis_tlast = s00_axis_tlast;
assign m05_axis_tdata = s00_axis_tdata;
assign m05_axis_tlast = s00_axis_tlast;
assign m06_axis_tdata = s00_axis_tdata;
assign m06_axis_tlast = s00_axis_tlast;
assign m07_axis_tdata = s00_axis_tdata;
assign m07_axis_tlast = s00_axis_tlast;
// Add user logic here
generate if (NUM_SLAVES == 1)
begin: NUM_SLAVES_1
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
m00_axis_tready;
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[0]);
assign slaves_ready = m00_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 2)
begin: NUM_SLAVES_2
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[1]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 3)
begin: NUM_SLAVES_3
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
s00_axis_tvalid &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[2]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 4)
begin: NUM_SLAVES_4
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[3]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 5)
begin: NUM_SLAVES_5
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready ||
m04_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[4] &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[4] &&
priority_sel[3]);
assign m04_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[4]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready &
m04_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 6)
begin: NUM_SLAVES_6
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready ||
m04_axis_tready ||
m05_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
~priority_sel[4] &&
priority_sel[3]);
assign m04_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
priority_sel[4]);
assign m05_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[5]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready &
m04_axis_tready &
m05_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 7)
begin: NUM_SLAVES_7
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready ||
m04_axis_tready ||
m05_axis_tready ||
m06_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
priority_sel[3]);
assign m04_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
priority_sel[4]);
assign m05_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
priority_sel[5]);
assign m06_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[6]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready &
m04_axis_tready &
m05_axis_tready &
m06_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 8)
begin: NUM_SLAVES_8
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready ||
m04_axis_tready ||
m05_axis_tready ||
m06_axis_tready ||
m07_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
priority_sel[3]);
assign m04_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
priority_sel[4]);
assign m05_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
priority_sel[5]);
assign m06_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
priority_sel[6]);
assign m07_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[7]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready &
m04_axis_tready &
m05_axis_tready &
m06_axis_tready &
m07_axis_tready;
end
endgenerate
// User logic ends
endmodule
|
/***********************************************
Module Name: CORDIC_Element_test
Feature: Testbench for CORDIC_Element
An example for the GEM Projects
Coder: Garfield
Organization: XXXX Group, Department of Architecture
------------------------------------------------------
Variables:
clk: clock for processing
reset: reset flag
cntr: counter for the EN and CLRinput
------------------------------------------------------
History:
06-20-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
`define WIDTH 15
//Bit Width
`define ORDER 12
//Insert the modules
module CORDIC_Element_test;
//defination for Variables
reg clk;
reg reset;
reg[(`WIDTH-1):0] test_vector_x[(`ORDER+1):0];
reg[(`WIDTH-1):0] test_vector_y[(`ORDER+1):0];
reg[(`WIDTH-1):0] test_vector_z[(`ORDER+1):0];
//Test Vector Value
wire[(`WIDTH-1):0] x[(`ORDER+1):0];
wire[(`WIDTH-1):0] y[(`ORDER+1):0];
wire[(`WIDTH-1):0] z[(`ORDER+1):0];
//middle signals
reg[(`WIDTH-1):0] comp_x[(`ORDER+1):0];
reg[(`WIDTH-1):0] comp_y[(`ORDER+1):0];
reg[(`WIDTH-1):0] comp_z[(`ORDER+1):0];
//Results right? Comparision results
reg[3:0] loop;
//Connection to the modules
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h3243), .ORDER(0) )
CE0 ( .CLK(clk), .RESET_n(reset),
.x_k(x[0]), .y_k(y[0]), .z_k(z[0]),
.x_k1(x[1]), .y_k1(y[1]), .z_k1(z[1]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h1DAC), .ORDER(1) )
CE1 ( .CLK(clk), .RESET_n(reset),
.x_k(x[1]), .y_k(y[1]), .z_k(z[1]),
.x_k1(x[2]), .y_k1(y[2]), .z_k1(z[2]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h0FAD), .ORDER(2) )
CE2 ( .CLK(clk), .RESET_n(reset),
.x_k(x[2]), .y_k(y[2]), .z_k(z[2]),
.x_k1(x[3]), .y_k1(y[3]), .z_k1(z[3]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h07F5), .ORDER(3) )
CE3 ( .CLK(clk), .RESET_n(reset),
.x_k(x[3]), .y_k(y[3]), .z_k(z[3]),
.x_k1(x[4]), .y_k1(y[4]), .z_k1(z[4]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h03FE), .ORDER(4) )
CE4 ( .CLK(clk), .RESET_n(reset),
.x_k(x[4]), .y_k(y[4]), .z_k(z[4]),
.x_k1(x[5]), .y_k1(y[5]), .z_k1(z[5]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h01FF), .ORDER(5) )
CE5 ( .CLK(clk), .RESET_n(reset),
.x_k(x[5]), .y_k(y[5]), .z_k(z[5]),
.x_k1(x[6]), .y_k1(y[6]), .z_k1(z[6]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h00FF), .ORDER(6) )
CE6 ( .CLK(clk), .RESET_n(reset),
.x_k(x[6]), .y_k(y[6]), .z_k(z[6]),
.x_k1(x[7]), .y_k1(y[7]), .z_k1(z[7]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h007F), .ORDER(7) )
CE7 ( .CLK(clk), .RESET_n(reset),
.x_k(x[7]), .y_k(y[7]), .z_k(z[7]),
.x_k1(x[8]), .y_k1(y[8]), .z_k1(z[8]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h003F), .ORDER(8) )
CE8 ( .CLK(clk), .RESET_n(reset),
.x_k(x[8]), .y_k(y[8]), .z_k(z[8]),
.x_k1(x[9]), .y_k1(y[9]), .z_k1(z[9]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h001F), .ORDER(9) )
CE9 ( .CLK(clk), .RESET_n(reset),
.x_k(x[9]), .y_k(y[9]), .z_k(z[9]),
.x_k1(x[10]), .y_k1(y[10]), .z_k1(z[10]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h000F), .ORDER(10) )
CE10 ( .CLK(clk), .RESET_n(reset),
.x_k(x[10]), .y_k(y[10]), .z_k(z[10]),
.x_k1(x[11]), .y_k1(y[11]), .z_k1(z[11]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h0007), .ORDER(11) )
CE11 ( .CLK(clk), .RESET_n(reset),
.x_k(x[11]), .y_k(y[11]), .z_k(z[11]),
.x_k1(x[12]), .y_k1(y[12]), .z_k1(z[12]) );
CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h0003), .ORDER(12) )
CE12 ( .CLK(clk), .RESET_n(reset),
.x_k(x[12]), .y_k(y[12]), .z_k(z[12]),
.x_k1(x[13]), .y_k1(y[13]), .z_k1(z[13]) );
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Load the test vectors
initial
begin
$readmemh("triangle_x_test_vector.txt", test_vector_x);
$readmemh("triangle_y_test_vector.txt", test_vector_y);
$readmemh("triangle_z_test_vector.txt", test_vector_z);
end
//Load the input of 0 order element
//assign x[0] = test_vector_x[0];
//assign y[0] = test_vector_y[0];
//assign z[0] = test_vector_z[0];
assign x[0] = test_vector_x[0];
assign y[0] = test_vector_y[0];
assign z[0] = 0;
//Comparision
always @(posedge clk)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
for (loop = 0; loop <= (`ORDER+1); loop = loop + 1)
begin
comp_x[loop] <= 1'b0;
comp_y[loop] <= 1'b0;
comp_z[loop] <= 1'b0;
end
end
else
begin
for (loop = 0; loop <= (`ORDER+1); loop = loop + 1)
begin
comp_x[loop] <= (x[loop]>>>1 - test_vector_x[loop]);
comp_y[loop] <= (y[loop]>>>1 - test_vector_y[loop]);
comp_z[loop] <= (z[loop]>>>1 - test_vector_z[loop]);
end
end
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__OR4_BEHAVIORAL_PP_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or4 (
VPWR,
VGND,
X ,
A ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C ;
input D ;
// Local signals
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , D, C, B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__XNOR3_FUNCTIONAL_PP_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR3_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__NAND4BB_BEHAVIORAL_PP_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4BB_BEHAVIORAL_PP_V |
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
// Date : Tue Dec 22 18:36:47 2015
// Host : jon-GA-MA770T-ES3 running 64-bit Linux Mint 17.2 Rafaela
// Command : write_verilog -force ./cpu_impl_netlist.v -mode timesim -sdf_anno true
// Design : BSP
// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or
// synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING
module BRAM
(DOBDO,
ETH_CLK_OBUF,
ADDRBWRADDR,
pwropt);
output [3:0]DOBDO;
input ETH_CLK_OBUF;
input [12:0]ADDRBWRADDR;
input pwropt;
wire [12:0]ADDRBWRADDR;
wire [3:0]DOBDO;
wire ETH_CLK_OBUF;
wire pwropt;
wire NLW_MEMORY_reg_0_CASCADEOUTA_UNCONNECTED;
wire NLW_MEMORY_reg_0_CASCADEOUTB_UNCONNECTED;
wire NLW_MEMORY_reg_0_DBITERR_UNCONNECTED;
wire NLW_MEMORY_reg_0_INJECTDBITERR_UNCONNECTED;
wire NLW_MEMORY_reg_0_INJECTSBITERR_UNCONNECTED;
wire NLW_MEMORY_reg_0_REGCEAREGCE_UNCONNECTED;
wire NLW_MEMORY_reg_0_REGCEB_UNCONNECTED;
wire NLW_MEMORY_reg_0_SBITERR_UNCONNECTED;
wire [31:0]NLW_MEMORY_reg_0_DOADO_UNCONNECTED;
wire [31:4]NLW_MEMORY_reg_0_DOBDO_UNCONNECTED;
wire [3:0]NLW_MEMORY_reg_0_DOPADOP_UNCONNECTED;
wire [3:0]NLW_MEMORY_reg_0_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_MEMORY_reg_0_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_MEMORY_reg_0_RDADDRECC_UNCONNECTED;
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENBWREN=NEW" *)
(* RTL_RAM_BITS = "60000" *)
(* RTL_RAM_NAME = "MEMORY" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "3" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.IS_ENBWREN_INVERTED(1'b1),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
MEMORY_reg_0
(.ADDRARDADDR({1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b1),
.CASCADEOUTA(NLW_MEMORY_reg_0_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_MEMORY_reg_0_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(ETH_CLK_OBUF),
.DBITERR(NLW_MEMORY_reg_0_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(NLW_MEMORY_reg_0_DOADO_UNCONNECTED[31:0]),
.DOBDO({NLW_MEMORY_reg_0_DOBDO_UNCONNECTED[31:4],DOBDO}),
.DOPADOP(NLW_MEMORY_reg_0_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_MEMORY_reg_0_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_MEMORY_reg_0_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(1'b1),
.ENBWREN(pwropt),
.INJECTDBITERR(NLW_MEMORY_reg_0_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_MEMORY_reg_0_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_MEMORY_reg_0_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_MEMORY_reg_0_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_MEMORY_reg_0_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_MEMORY_reg_0_SBITERR_UNCONNECTED),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ECO_CHECKSUM = "9f08b84e" *) (* POWER_OPT_BRAM_CDC = "0" *) (* POWER_OPT_BRAM_SR_ADDR = "0" *)
(* POWER_OPT_LOOPED_NET_PERCENTAGE = "0" *)
(* NotValidForBitStream *)
module BSP
(CLK_IN,
RST,
ETH_CLK,
PHY_RESET_N,
RXDV,
RXER,
RXD,
TXD,
TXEN,
JC,
SDA,
SCL,
KD,
KC,
AUDIO,
AUDIO_EN,
VGA_R,
VGA_G,
VGA_B,
HSYNCH,
VSYNCH,
GPIO_LEDS,
GPIO_SWITCHES,
GPIO_BUTTONS,
LED_R_PWM,
LED_G_PWM,
LED_B_PWM,
SEVEN_SEGMENT_CATHODE,
SEVEN_SEGMENT_ANNODE,
RS232_RX,
RS232_TX);
input CLK_IN;
input RST;
output ETH_CLK;
output PHY_RESET_N;
input RXDV;
input RXER;
input [1:0]RXD;
output [1:0]TXD;
output TXEN;
inout [7:0]JC;
inout SDA;
inout SCL;
input KD;
input KC;
output AUDIO;
output AUDIO_EN;
output [3:0]VGA_R;
output [3:0]VGA_G;
output [3:0]VGA_B;
output HSYNCH;
output VSYNCH;
output [15:0]GPIO_LEDS;
input [15:0]GPIO_SWITCHES;
input [4:0]GPIO_BUTTONS;
output LED_R_PWM;
output LED_G_PWM;
output LED_B_PWM;
output [6:0]SEVEN_SEGMENT_CATHODE;
output [7:0]SEVEN_SEGMENT_ANNODE;
input RS232_RX;
output RS232_TX;
wire AUDIO;
wire AUDIO_EN;
wire CLKFB;
wire CLKIN;
(* IBUF_LOW_PWR *) wire CLK_IN;
wire ETH_CLK;
wire ETH_CLK_OBUF;
wire \GPIO_BUTTONS[0] ;
wire \GPIO_BUTTONS[0]_IBUF ;
wire \GPIO_BUTTONS[1] ;
wire \GPIO_BUTTONS[1]_IBUF ;
wire \GPIO_BUTTONS[2] ;
wire \GPIO_BUTTONS[2]_IBUF ;
wire \GPIO_BUTTONS[3] ;
wire \GPIO_BUTTONS[3]_IBUF ;
wire \GPIO_BUTTONS[4] ;
wire \GPIO_BUTTONS[4]_IBUF ;
wire [15:0]GPIO_LEDS;
wire \GPIO_SWITCHES[0] ;
wire \GPIO_SWITCHES[0]_IBUF ;
wire \GPIO_SWITCHES[10] ;
wire \GPIO_SWITCHES[10]_IBUF ;
wire \GPIO_SWITCHES[11] ;
wire \GPIO_SWITCHES[11]_IBUF ;
wire \GPIO_SWITCHES[12] ;
wire \GPIO_SWITCHES[12]_IBUF ;
wire \GPIO_SWITCHES[13] ;
wire \GPIO_SWITCHES[13]_IBUF ;
wire \GPIO_SWITCHES[14] ;
wire \GPIO_SWITCHES[14]_IBUF ;
wire \GPIO_SWITCHES[15] ;
wire \GPIO_SWITCHES[15]_IBUF ;
wire \GPIO_SWITCHES[1] ;
wire \GPIO_SWITCHES[1]_IBUF ;
wire \GPIO_SWITCHES[2] ;
wire \GPIO_SWITCHES[2]_IBUF ;
wire \GPIO_SWITCHES[3] ;
wire \GPIO_SWITCHES[3]_IBUF ;
wire \GPIO_SWITCHES[4] ;
wire \GPIO_SWITCHES[4]_IBUF ;
wire \GPIO_SWITCHES[5] ;
wire \GPIO_SWITCHES[5]_IBUF ;
wire \GPIO_SWITCHES[6] ;
wire \GPIO_SWITCHES[6]_IBUF ;
wire \GPIO_SWITCHES[7] ;
wire \GPIO_SWITCHES[7]_IBUF ;
wire \GPIO_SWITCHES[8] ;
wire \GPIO_SWITCHES[8]_IBUF ;
wire \GPIO_SWITCHES[9] ;
wire \GPIO_SWITCHES[9]_IBUF ;
wire HSYNCH;
wire HSYNCH_OBUF;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg_n_0;
wire [7:0]JC;
wire [1:1]JC_IBUF;
wire KC;
wire KC_IBUF;
wire KD;
wire KD_IBUF;
wire LED_B_PWM;
wire LED_B_PWM_OBUF;
wire LED_G_PWM;
wire LED_G_PWM_OBUF;
wire LED_R_PWM;
wire LED_R_PWM_OBUF;
wire NOT_LOCKED;
wire NOT_LOCKED_i_1_n_0;
wire PHY_RESET_N;
wire PHY_RESET_N_OBUF;
wire RS232_RX;
wire RS232_RX_IBUF;
wire RS232_TX;
wire RS232_TX_OBUF;
wire RST;
wire RST_IBUF;
wire RXDV;
wire RXDV_IBUF;
wire \RXD[0] ;
wire \RXD[0]_IBUF ;
wire \RXD[1] ;
wire \RXD[1]_IBUF ;
wire RXER;
wire RXER_IBUF;
(* DRIVE = "12" *) (* IBUF_LOW_PWR *) (* SLEW = "SLOW" *) wire SCL;
wire SCL_IBUF;
wire SCL_TRI;
wire SDA;
wire SDA_IBUF;
wire SDA_TRI;
wire [7:0]SEVEN_SEGMENT_ANNODE;
wire [6:0]SEVEN_SEGMENT_CATHODE;
wire [1:0]TXD;
wire [1:0]TXD_OBUF;
wire TXEN;
wire TXEN_OBUF;
wire USER_DESIGN_INST_1_n_1;
wire USER_DESIGN_INST_1_n_2;
wire USER_DESIGN_INST_1_n_3;
wire USER_DESIGN_INST_1_n_4;
wire USER_DESIGN_INST_1_n_5;
wire USER_DESIGN_INST_1_n_6;
wire USER_DESIGN_INST_1_n_7;
wire USER_DESIGN_INST_1_n_8;
wire [3:0]VGA_B;
wire [0:0]VGA_B_OBUF;
wire [3:0]VGA_G;
wire [3:0]VGA_R;
wire VSYNCH;
wire VSYNCH_OBUF;
wire clk0;
wire clkdv;
wire locked_internal;
wire NLW_dcm_sp_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT0_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT0B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT1_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT1B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT2_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT2B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT3_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT3B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT5_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT6_UNCONNECTED;
wire NLW_dcm_sp_inst_DRDY_UNCONNECTED;
wire NLW_dcm_sp_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_dcm_sp_inst_DO_UNCONNECTED;
wire NLW_ethernet_inst_1_RXDV_IBUF_UNCONNECTED;
wire NLW_ethernet_inst_1_RXER_IBUF_UNCONNECTED;
wire [1:0]NLW_ethernet_inst_1_D_UNCONNECTED;
PULLUP pullup_KC
(.O(KC));
PULLUP pullup_KD
(.O(KD));
initial begin
$sdf_annotate("cpu_impl_netlist.sdf",,,,"tool_control");
end
assign \GPIO_BUTTONS[0] = GPIO_BUTTONS[0];
assign \GPIO_BUTTONS[1] = GPIO_BUTTONS[1];
assign \GPIO_BUTTONS[2] = GPIO_BUTTONS[2];
assign \GPIO_BUTTONS[3] = GPIO_BUTTONS[3];
assign \GPIO_BUTTONS[4] = GPIO_BUTTONS[4];
assign \GPIO_SWITCHES[0] = GPIO_SWITCHES[0];
assign \GPIO_SWITCHES[10] = GPIO_SWITCHES[10];
assign \GPIO_SWITCHES[11] = GPIO_SWITCHES[11];
assign \GPIO_SWITCHES[12] = GPIO_SWITCHES[12];
assign \GPIO_SWITCHES[13] = GPIO_SWITCHES[13];
assign \GPIO_SWITCHES[14] = GPIO_SWITCHES[14];
assign \GPIO_SWITCHES[15] = GPIO_SWITCHES[15];
assign \GPIO_SWITCHES[1] = GPIO_SWITCHES[1];
assign \GPIO_SWITCHES[2] = GPIO_SWITCHES[2];
assign \GPIO_SWITCHES[3] = GPIO_SWITCHES[3];
assign \GPIO_SWITCHES[4] = GPIO_SWITCHES[4];
assign \GPIO_SWITCHES[5] = GPIO_SWITCHES[5];
assign \GPIO_SWITCHES[6] = GPIO_SWITCHES[6];
assign \GPIO_SWITCHES[7] = GPIO_SWITCHES[7];
assign \GPIO_SWITCHES[8] = GPIO_SWITCHES[8];
assign \GPIO_SWITCHES[9] = GPIO_SWITCHES[9];
assign \RXD[0] = RXD[0];
assign \RXD[1] = RXD[1];
OBUF AUDIO_EN_OBUF_inst
(.I(1'b1),
.O(AUDIO_EN));
OBUF AUDIO_OBUF_inst
(.I(1'b0),
.O(AUDIO));
(* box_type = "PRIMITIVE" *)
BUFG BUFG_INST1
(.I(clkdv),
.O(ETH_CLK_OBUF));
(* box_type = "PRIMITIVE" *)
BUFG BUFG_INST2
(.I(clk0),
.O(CLKFB));
CHARSVGA CHARSVGA_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.HSYNCH(HSYNCH_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.VGA_B_OBUF(VGA_B_OBUF),
.VSYNCH(VSYNCH_OBUF));
OBUF ETH_CLK_OBUF_inst
(.I(ETH_CLK_OBUF),
.O(ETH_CLK));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[0]_IBUF_inst
(.I(\GPIO_BUTTONS[0] ),
.O(\GPIO_BUTTONS[0]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[1]_IBUF_inst
(.I(\GPIO_BUTTONS[1] ),
.O(\GPIO_BUTTONS[1]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[2]_IBUF_inst
(.I(\GPIO_BUTTONS[2] ),
.O(\GPIO_BUTTONS[2]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[3]_IBUF_inst
(.I(\GPIO_BUTTONS[3] ),
.O(\GPIO_BUTTONS[3]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[4]_IBUF_inst
(.I(\GPIO_BUTTONS[4] ),
.O(\GPIO_BUTTONS[4]_IBUF ));
OBUF \GPIO_LEDS_OBUF[0]_inst
(.I(1'b0),
.O(GPIO_LEDS[0]));
OBUF \GPIO_LEDS_OBUF[10]_inst
(.I(1'b0),
.O(GPIO_LEDS[10]));
OBUF \GPIO_LEDS_OBUF[11]_inst
(.I(1'b0),
.O(GPIO_LEDS[11]));
OBUF \GPIO_LEDS_OBUF[12]_inst
(.I(1'b0),
.O(GPIO_LEDS[12]));
OBUF \GPIO_LEDS_OBUF[13]_inst
(.I(1'b0),
.O(GPIO_LEDS[13]));
OBUF \GPIO_LEDS_OBUF[14]_inst
(.I(1'b0),
.O(GPIO_LEDS[14]));
OBUF \GPIO_LEDS_OBUF[15]_inst
(.I(1'b0),
.O(GPIO_LEDS[15]));
OBUF \GPIO_LEDS_OBUF[1]_inst
(.I(1'b0),
.O(GPIO_LEDS[1]));
OBUF \GPIO_LEDS_OBUF[2]_inst
(.I(1'b0),
.O(GPIO_LEDS[2]));
OBUF \GPIO_LEDS_OBUF[3]_inst
(.I(1'b0),
.O(GPIO_LEDS[3]));
OBUF \GPIO_LEDS_OBUF[4]_inst
(.I(1'b0),
.O(GPIO_LEDS[4]));
OBUF \GPIO_LEDS_OBUF[5]_inst
(.I(1'b0),
.O(GPIO_LEDS[5]));
OBUF \GPIO_LEDS_OBUF[6]_inst
(.I(1'b0),
.O(GPIO_LEDS[6]));
OBUF \GPIO_LEDS_OBUF[7]_inst
(.I(1'b0),
.O(GPIO_LEDS[7]));
OBUF \GPIO_LEDS_OBUF[8]_inst
(.I(1'b0),
.O(GPIO_LEDS[8]));
OBUF \GPIO_LEDS_OBUF[9]_inst
(.I(1'b0),
.O(GPIO_LEDS[9]));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[0]_IBUF_inst
(.I(\GPIO_SWITCHES[0] ),
.O(\GPIO_SWITCHES[0]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[10]_IBUF_inst
(.I(\GPIO_SWITCHES[10] ),
.O(\GPIO_SWITCHES[10]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[11]_IBUF_inst
(.I(\GPIO_SWITCHES[11] ),
.O(\GPIO_SWITCHES[11]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[12]_IBUF_inst
(.I(\GPIO_SWITCHES[12] ),
.O(\GPIO_SWITCHES[12]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[13]_IBUF_inst
(.I(\GPIO_SWITCHES[13] ),
.O(\GPIO_SWITCHES[13]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[14]_IBUF_inst
(.I(\GPIO_SWITCHES[14] ),
.O(\GPIO_SWITCHES[14]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[15]_IBUF_inst
(.I(\GPIO_SWITCHES[15] ),
.O(\GPIO_SWITCHES[15]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[1]_IBUF_inst
(.I(\GPIO_SWITCHES[1] ),
.O(\GPIO_SWITCHES[1]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[2]_IBUF_inst
(.I(\GPIO_SWITCHES[2] ),
.O(\GPIO_SWITCHES[2]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[3]_IBUF_inst
(.I(\GPIO_SWITCHES[3] ),
.O(\GPIO_SWITCHES[3]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[4]_IBUF_inst
(.I(\GPIO_SWITCHES[4] ),
.O(\GPIO_SWITCHES[4]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[5]_IBUF_inst
(.I(\GPIO_SWITCHES[5] ),
.O(\GPIO_SWITCHES[5]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[6]_IBUF_inst
(.I(\GPIO_SWITCHES[6] ),
.O(\GPIO_SWITCHES[6]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[7]_IBUF_inst
(.I(\GPIO_SWITCHES[7] ),
.O(\GPIO_SWITCHES[7]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[8]_IBUF_inst
(.I(\GPIO_SWITCHES[8] ),
.O(\GPIO_SWITCHES[8]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[9]_IBUF_inst
(.I(\GPIO_SWITCHES[9] ),
.O(\GPIO_SWITCHES[9]_IBUF ));
OBUF HSYNCH_OBUF_inst
(.I(HSYNCH_OBUF),
.O(HSYNCH));
I2C I2C_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.SCL_IBUF(SCL_IBUF),
.SCL_TRI(SCL_TRI),
.SDA_IBUF(SDA_IBUF),
.SDA_TRI(SDA_TRI));
FDRE INTERNAL_RST_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(NOT_LOCKED),
.Q(INTERNAL_RST_reg_n_0),
.R(1'b0));
OBUF \JC_OBUF[0]_inst
(.I(1'b1),
.O(JC[0]));
OBUF \JC_OBUF[1]_inst
(.I(JC_IBUF),
.O(JC[1]));
(* OPT_INSERTED *)
IBUF KC_IBUF_inst
(.I(KC),
.O(KC_IBUF));
(* OPT_INSERTED *)
IBUF KD_IBUF_inst
(.I(KD),
.O(KD_IBUF));
OBUF LED_B_PWM_OBUF_inst
(.I(LED_B_PWM_OBUF),
.O(LED_B_PWM));
OBUF LED_G_PWM_OBUF_inst
(.I(LED_G_PWM_OBUF),
.O(LED_G_PWM));
OBUF LED_R_PWM_OBUF_inst
(.I(LED_R_PWM_OBUF),
.O(LED_R_PWM));
LUT1 #(
.INIT(2'h1))
NOT_LOCKED_i_1
(.I0(locked_internal),
.O(NOT_LOCKED_i_1_n_0));
FDRE NOT_LOCKED_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(NOT_LOCKED_i_1_n_0),
.Q(NOT_LOCKED),
.R(1'b0));
OBUF PHY_RESET_N_OBUF_inst
(.I(PHY_RESET_N_OBUF),
.O(PHY_RESET_N));
LUT1 #(
.INIT(2'h1))
PHY_RESET_N_OBUF_inst_i_1
(.I0(INTERNAL_RST_reg_n_0),
.O(PHY_RESET_N_OBUF));
PWM PWM_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.LED_R_PWM_OBUF(LED_R_PWM_OBUF));
PWM_0 PWM_INST_2
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.LED_G_PWM_OBUF(LED_G_PWM_OBUF));
PWM_1 PWM_INST_3
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.LED_B_PWM_OBUF(LED_B_PWM_OBUF));
(* OPT_INSERTED *)
IBUF RS232_RX_IBUF_inst
(.I(RS232_RX),
.O(RS232_RX_IBUF));
OBUF RS232_TX_OBUF_inst
(.I(RS232_TX_OBUF),
.O(RS232_TX));
IBUF RST_IBUF_inst
(.I(RST),
.O(RST_IBUF));
(* OPT_INSERTED *)
IBUF RXDV_IBUF_inst
(.I(RXDV),
.O(RXDV_IBUF));
(* OPT_INSERTED *)
IBUF \RXD[0]_IBUF_inst
(.I(\RXD[0] ),
.O(\RXD[0]_IBUF ));
(* OPT_INSERTED *)
IBUF \RXD[1]_IBUF_inst
(.I(\RXD[1] ),
.O(\RXD[1]_IBUF ));
(* OPT_INSERTED *)
IBUF RXER_IBUF_inst
(.I(RXER),
.O(RXER_IBUF));
IOBUF_HD3 SCL_IOBUF_inst
(.I(1'b0),
.IO(SCL),
.O(SCL_IBUF),
.T(SCL_TRI));
IOBUF_UNIQ_BASE_ SDA_IOBUF_inst
(.I(1'b0),
.IO(SDA),
.O(SDA_IBUF),
.T(SDA_TRI));
serial_output SERIAL_OUTPUT_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.IN1_ACK(IN1_ACK),
.IN1_STB(IN1_STB),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.Q({USER_DESIGN_INST_1_n_1,USER_DESIGN_INST_1_n_2,USER_DESIGN_INST_1_n_3,USER_DESIGN_INST_1_n_4,USER_DESIGN_INST_1_n_5,USER_DESIGN_INST_1_n_6,USER_DESIGN_INST_1_n_7,USER_DESIGN_INST_1_n_8}),
.RS232_TX_OBUF(RS232_TX_OBUF));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[0]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[0]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[1]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[1]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[2]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[2]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[3]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[3]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[4]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[4]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[5]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[5]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[6]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[6]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[7]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[7]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[0]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[0]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[1]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[1]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[2]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[2]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[3]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[3]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[4]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[4]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[5]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[5]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[6]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[6]));
OBUF \TXD_OBUF[0]_inst
(.I(TXD_OBUF[0]),
.O(TXD[0]));
OBUF \TXD_OBUF[1]_inst
(.I(TXD_OBUF[1]),
.O(TXD[1]));
OBUF TXEN_OBUF_inst
(.I(TXEN_OBUF),
.O(TXEN));
user_design USER_DESIGN_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.IN1_ACK(IN1_ACK),
.IN1_STB(IN1_STB),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.output_rs232_tx({USER_DESIGN_INST_1_n_1,USER_DESIGN_INST_1_n_2,USER_DESIGN_INST_1_n_3,USER_DESIGN_INST_1_n_4,USER_DESIGN_INST_1_n_5,USER_DESIGN_INST_1_n_6,USER_DESIGN_INST_1_n_7,USER_DESIGN_INST_1_n_8}));
OBUF \VGA_B_OBUF[0]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[0]));
OBUF \VGA_B_OBUF[1]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[1]));
OBUF \VGA_B_OBUF[2]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[2]));
OBUF \VGA_B_OBUF[3]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[3]));
OBUF \VGA_G_OBUF[0]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[0]));
OBUF \VGA_G_OBUF[1]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[1]));
OBUF \VGA_G_OBUF[2]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[2]));
OBUF \VGA_G_OBUF[3]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[3]));
OBUF \VGA_R_OBUF[0]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[0]));
OBUF \VGA_R_OBUF[1]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[1]));
OBUF \VGA_R_OBUF[2]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[2]));
OBUF \VGA_R_OBUF[3]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[3]));
OBUF VSYNCH_OBUF_inst
(.I(VSYNCH_OBUF),
.O(VSYNCH));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* XILINX_LEGACY_PRIM = "IBUFG" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_buf
(.I(CLK_IN),
.O(CLKIN));
(* XILINX_LEGACY_PRIM = "DCM_SP" *)
(* XILINX_TRANSFORM_PINMAP = "STATUS[7]:DO[7] STATUS[6]:DO[6] STATUS[5]:DO[5] STATUS[4]:DO[4] STATUS[3]:DO[3] STATUS[2]:DO[2] STATUS[1]:DO[1] STATUS[0]:DO[0] CLKIN:CLKIN1 CLKFX:CLKOUT0 CLKFX180:CLKOUT0B CLK2X:CLKOUT1 CLK2X180:CLKOUT1B CLK90:CLKOUT2 CLK270:CLKOUT2B CLKDV:CLKOUT4 CLK0:CLKFBOUT CLK180:CLKFBOUTB CLKFB:CLKFBIN" *)
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(8.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(2.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(4),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(8),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(90.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(8),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(16),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_PSINCDEC_INVERTED(1'b1),
.IS_RST_INVERTED(1'b1),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.STARTUP_WAIT("FALSE"))
dcm_sp_inst
(.CLKFBIN(CLKFB),
.CLKFBOUT(clk0),
.CLKFBOUTB(NLW_dcm_sp_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_dcm_sp_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(CLKIN),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_dcm_sp_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(NLW_dcm_sp_inst_CLKOUT0_UNCONNECTED),
.CLKOUT0B(NLW_dcm_sp_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_dcm_sp_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_dcm_sp_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_dcm_sp_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_dcm_sp_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_dcm_sp_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_dcm_sp_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(clkdv),
.CLKOUT5(NLW_dcm_sp_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_dcm_sp_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_dcm_sp_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_dcm_sp_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked_internal),
.PSCLK(1'b0),
.PSDONE(NLW_dcm_sp_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(RST_IBUF));
rmii_ethernet ethernet_inst_1
(.D(NLW_ethernet_inst_1_D_UNCONNECTED[1:0]),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.RXDV_IBUF(NLW_ethernet_inst_1_RXDV_IBUF_UNCONNECTED),
.RXER_IBUF(NLW_ethernet_inst_1_RXER_IBUF_UNCONNECTED),
.TXD_OBUF(TXD_OBUF),
.TXEN_OBUF(TXEN_OBUF));
pwm_audio pwm_audio_inst_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.JC_IBUF(JC_IBUF));
endmodule
module CHARSVGA
(HSYNCH,
VSYNCH,
VGA_B_OBUF,
ETH_CLK_OBUF,
INTERNAL_RST_reg);
output HSYNCH;
output VSYNCH;
output [0:0]VGA_B_OBUF;
input ETH_CLK_OBUF;
input INTERNAL_RST_reg;
wire [12:1]AOUT;
wire BLANK;
wire BLANK_DEL;
wire BLANK_DEL_DEL;
wire [3:0]DOUT;
wire ETH_CLK_OBUF;
wire HSYNCH;
wire HSYNCH_DEL;
wire INTERNAL_RST_reg;
wire [2:0]PIXCOL_DEL;
wire \PIXCOL_DEL_DEL_reg_n_0_[0] ;
wire \PIXCOL_DEL_DEL_reg_n_0_[1] ;
wire \PIXCOL_DEL_DEL_reg_n_0_[2] ;
wire [7:0]PIXELS_reg__0;
wire TIMEING1_n_0;
wire TIMEING1_n_1;
wire TIMEING1_n_15;
wire TIMEING1_n_16;
wire TIMEING1_n_17;
wire TIMEING1_n_18;
wire TIMEING1_n_19;
wire TIMEING1_n_2;
wire TIMEING1_n_20;
wire [0:0]VGA_B_OBUF;
wire \VGA_R_OBUF[3]_inst_i_2_n_0 ;
wire \VGA_R_OBUF[3]_inst_i_3_n_0 ;
wire VSYNCH;
wire VSYNCH_DEL;
wire [2:0]sel;
wire NLW_PIXELS_reg_REGCEAREGCE_UNCONNECTED;
wire NLW_PIXELS_reg_REGCEB_UNCONNECTED;
wire [15:8]NLW_PIXELS_reg_DOADO_UNCONNECTED;
wire [15:0]NLW_PIXELS_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_PIXELS_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_PIXELS_reg_DOPBDOP_UNCONNECTED;
FDRE BLANK_DEL_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BLANK_DEL),
.Q(BLANK_DEL_DEL),
.R(1'b0));
FDRE BLANK_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BLANK),
.Q(BLANK_DEL),
.R(1'b0));
BRAM BRAM_INST_1
(.ADDRBWRADDR({AOUT,TIMEING1_n_15}),
.DOBDO(DOUT),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.pwropt(BLANK));
FDRE HSYNCH_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_19),
.Q(HSYNCH_DEL),
.R(1'b0));
FDRE HSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HSYNCH_DEL),
.Q(HSYNCH),
.R(1'b0));
FDRE \PIXCOL_DEL_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(PIXCOL_DEL[0]),
.Q(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
.R(1'b0));
FDRE \PIXCOL_DEL_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(PIXCOL_DEL[1]),
.Q(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
.R(1'b0));
FDRE \PIXCOL_DEL_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(PIXCOL_DEL[2]),
.Q(\PIXCOL_DEL_DEL_reg_n_0_[2] ),
.R(1'b0));
FDRE \PIXCOL_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_0),
.Q(PIXCOL_DEL[0]),
.R(1'b0));
FDRE \PIXCOL_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_1),
.Q(PIXCOL_DEL[1]),
.R(1'b0));
FDRE \PIXCOL_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_2),
.Q(PIXCOL_DEL[2]),
.R(1'b0));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "16384" *)
(* RTL_RAM_NAME = "PIXELS" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "2047" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "17" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000143E143E1400000000000000141400000800080808080000000000000000),
.INIT_09(256'h0000000000000808006C12320C12120C00E2A4E8102E4A8E00081E281C0A3C08),
.INIT_0A(256'h00101010FE1010100000000022143E0800081020202010080008040202020408),
.INIT_0B(256'h00000204081020400000080000000000000000003E0000000008080000000000),
.INIT_0C(256'h00001C222010221C00003E040810221C00003E0808080C0800001C262A2A321C),
.INIT_0D(256'h000008081020223E00001C221E02221C00001C22203E023E00003C103E121418),
.INIT_0E(256'h0008080000000800000008000000080000001C22203C221C00001C22221C221C),
.INIT_0F(256'h000008000818221C000204081008040200003E00003E00000010080402040810),
.INIT_10(256'h00001C220202221C00001E22221E221E00002222223E221C006CA2BAAABA827C),
.INIT_11(256'h00001C223A02221C00000202021E023E00003E02021E023E00001E222222221E),
.INIT_12(256'h000022120A060A1200000C121010103800003E080808083E00002222223E2222),
.INIT_13(256'h00001C222222221C000022322A262222000022222A2A362200003E0202020202),
.INIT_14(256'h00001E20201C023C000022120A1E221E00681C222222221C000002021E22221E),
.INIT_15(256'h0000142A2A222222000008141422222200001C2222222222000008080808083E),
.INIT_16(256'h001808080808081800003E020408103E00000808081C22220000221408081422),
.INIT_17(256'h00FF000000000000000000000022140800181010101010180000402010080402),
.INIT_18(256'h00001C2202021C0000001E22261A020200005C223C201C000000000000001008),
.INIT_19(256'h001C203C22223C00000002020E02221C00001C023E221C0000003C22322C2020),
.INIT_1A(256'h000022120E0A1202000C12101018001000001C08080C000800002222261A0202),
.INIT_1B(256'h00001C2222221C000000242424241A0000002A2A2A2A160000003E080808080C),
.INIT_1C(256'h00001E201C023C000000040404241A000020203C22322C000002021E22221E00),
.INIT_1D(256'h0000142A2A222200000008141422220000002C121212120000001C22020E0202),
.INIT_1E(256'h001008080408081000003E0408103E00001C203C222222000000221408142200),
.INIT_1F(256'h000000000000000000000060920C000000040808100808040008080808080808),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000143E143E1400000000000000141400000800080808080000000000000000),
.INIT_29(256'h0000000000000808006C12320C12120C00E2A4E8102E4A8E00081E281C0A3C08),
.INIT_2A(256'h00101010FE1010100000000022143E0800081020202010080008040202020408),
.INIT_2B(256'h00000204081020400000080000000000000000003E0000000008080000000000),
.INIT_2C(256'h00001C222010221C00003E040810221C00003E0808080C0800001C262A2A321C),
.INIT_2D(256'h000008081020223E00001C221E02221C00001C22203E023E00003C103E121418),
.INIT_2E(256'h0008080000000800000008000000080000001C22203C221C00001C22221C221C),
.INIT_2F(256'h000008000818221C000204081008040200003E00003E00000010080402040810),
.INIT_30(256'h00001C220202221C00001E22221E221E00002222223E221C006CA2BAAABA827C),
.INIT_31(256'h00001C223A02221C00000202021E023E00003E02021E023E00001E222222221E),
.INIT_32(256'h000022120A060A1200000C121010103800003E080808083E00002222223E2222),
.INIT_33(256'h00001C222222221C000022322A262222000022222A2A362200003E0202020202),
.INIT_34(256'h00001E20201C023C000022120A1E221E00681C222222221C000002021E22221E),
.INIT_35(256'h0000142A2A222222000008141422222200001C2222222222000008080808083E),
.INIT_36(256'h001808080808081800003E020408103E00000808081C22220000221408081422),
.INIT_37(256'h00FF000000000000000000000022140800181010101010180000402010080402),
.INIT_38(256'h00001C2202021C0000001E22261A020200005C223C201C000000000000001008),
.INIT_39(256'h001C203C22223C00000002020E02221C00001C023E221C0000003C22322C2020),
.INIT_3A(256'h000022120E0A1202000C12101018001000001C08080C000800002222261A0202),
.INIT_3B(256'h00001C2222221C000000242424241A0000002A2A2A2A160000003E080808080C),
.INIT_3C(256'h00001E201C023C000000040404241A000020203C22322C000002021E22221E00),
.INIT_3D(256'h0000142A2A222200000008141422220000002C121212120000001C22020E0202),
.INIT_3E(256'h001008080408081000003E0408103E00001C203C222222000000221408142200),
.INIT_3F(256'h000000000000000000000060920C000000040808100808040008080808080808),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.IS_ENARDEN_INVERTED(1'b1),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(0))
PIXELS_reg
(.ADDRARDADDR({DOUT,DOUT,sel,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO({NLW_PIXELS_reg_DOADO_UNCONNECTED[15:8],PIXELS_reg__0}),
.DOBDO(NLW_PIXELS_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_PIXELS_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_PIXELS_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(BLANK_DEL),
.ENBWREN(1'b0),
.REGCEAREGCE(NLW_PIXELS_reg_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_PIXELS_reg_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
FDRE \PIXROW_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_16),
.Q(sel[0]),
.R(1'b0));
FDRE \PIXROW_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_17),
.Q(sel[1]),
.R(1'b0));
FDRE \PIXROW_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_18),
.Q(sel[2]),
.R(1'b0));
VIDEO_TIME_GEN TIMEING1
(.ADDRBWRADDR({AOUT,TIMEING1_n_15}),
.BLANK(BLANK),
.D(TIMEING1_n_18),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.HSYNCH_DEL_reg(TIMEING1_n_19),
.INTERNAL_RST_reg(INTERNAL_RST_reg),
.\PIXCOL_DEL_reg[0] (TIMEING1_n_0),
.\PIXCOL_DEL_reg[1] (TIMEING1_n_1),
.\PIXCOL_DEL_reg[2] (TIMEING1_n_2),
.\PIXROW_DEL_reg[0] (TIMEING1_n_16),
.\PIXROW_DEL_reg[1] (TIMEING1_n_17),
.VSYNCH_DEL_reg(TIMEING1_n_20));
LUT4 #(
.INIT(16'h00E2))
\VGA_R_OBUF[3]_inst_i_1
(.I0(\VGA_R_OBUF[3]_inst_i_2_n_0 ),
.I1(\PIXCOL_DEL_DEL_reg_n_0_[2] ),
.I2(\VGA_R_OBUF[3]_inst_i_3_n_0 ),
.I3(BLANK_DEL_DEL),
.O(VGA_B_OBUF));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\VGA_R_OBUF[3]_inst_i_2
(.I0(PIXELS_reg__0[3]),
.I1(PIXELS_reg__0[2]),
.I2(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
.I3(PIXELS_reg__0[1]),
.I4(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
.I5(PIXELS_reg__0[0]),
.O(\VGA_R_OBUF[3]_inst_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\VGA_R_OBUF[3]_inst_i_3
(.I0(PIXELS_reg__0[7]),
.I1(PIXELS_reg__0[6]),
.I2(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
.I3(PIXELS_reg__0[5]),
.I4(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
.I5(PIXELS_reg__0[4]),
.O(\VGA_R_OBUF[3]_inst_i_3_n_0 ));
FDRE VSYNCH_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_20),
.Q(VSYNCH_DEL),
.R(1'b0));
FDRE VSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(VSYNCH_DEL),
.Q(VSYNCH),
.R(1'b0));
endmodule
module I2C
(SDA_TRI,
SCL_TRI,
ETH_CLK_OBUF,
SCL_IBUF,
INTERNAL_RST_reg,
SDA_IBUF);
output SDA_TRI;
output SCL_TRI;
input ETH_CLK_OBUF;
input SCL_IBUF;
input INTERNAL_RST_reg;
input SDA_IBUF;
wire BIT_i_1_n_0;
wire BIT_i_2_n_0;
wire BIT_i_3_n_0;
wire BIT_reg_n_0;
wire [2:0]COUNT;
wire \COUNT[0]_i_1__0_n_0 ;
wire \COUNT[1]_i_1__0_n_0 ;
wire \COUNT[2]_i_1_n_0 ;
wire \COUNT[2]_i_2_n_0 ;
wire ETH_CLK_OBUF;
wire [3:0]GET_BIT_RETURN;
wire \GET_BIT_RETURN[0]_i_1_n_0 ;
wire \GET_BIT_RETURN[3]_i_1_n_0 ;
wire INTERNAL_RST_reg;
wire SCL_IBUF;
wire SCL_I_D;
wire SCL_I_SYNCH;
wire SCL_O_i_1_n_0;
wire SCL_O_i_2_n_0;
wire SCL_O_i_3_n_0;
wire SCL_O_i_4_n_0;
wire SCL_TRI;
wire SDA_IBUF;
wire SDA_I_D;
wire SDA_I_SYNCH;
wire SDA_O_i_1_n_0;
wire SDA_O_i_2_n_0;
wire SDA_TRI;
wire [3:0]SEND_BIT_RETURN;
wire \SEND_BIT_RETURN[0]_i_1_n_0 ;
wire \SEND_BIT_RETURN[3]_i_1_n_0 ;
wire STARTED;
wire STARTED_i_1_n_0;
wire STARTED_i_2_n_0;
wire \STATE[0]_i_2_n_0 ;
wire \STATE[0]_i_3_n_0 ;
wire \STATE[1]_i_1_n_0 ;
wire \STATE[1]_i_2_n_0 ;
wire \STATE[1]_i_3_n_0 ;
wire \STATE[1]_i_4_n_0 ;
wire \STATE[2]_i_1_n_0 ;
wire \STATE[3]_i_2_n_0 ;
wire \STATE[3]_i_3_n_0 ;
wire \STATE[4]_i_1_n_0 ;
wire \STATE[4]_i_2_n_0 ;
wire \STATE[4]_i_3_n_0 ;
wire \STATE[4]_i_4_n_0 ;
wire \STATE[4]_i_5_n_0 ;
wire \STATE[4]_i_6_n_0 ;
wire \STATE_reg[0]_i_1_n_0 ;
wire \STATE_reg[3]_i_1_n_0 ;
wire \STATE_reg_n_0_[0] ;
wire \STATE_reg_n_0_[1] ;
wire \STATE_reg_n_0_[2] ;
wire \STATE_reg_n_0_[3] ;
wire \STATE_reg_n_0_[4] ;
wire S_I2C_IN_ACK_i_1_n_0;
wire S_I2C_IN_ACK_reg_n_0;
wire S_I2C_OUT_STB_i_1_n_0;
wire S_I2C_OUT_STB_reg_n_0;
wire \TIMER[0]_i_1_n_0 ;
wire \TIMER[0]_i_2_n_0 ;
wire \TIMER[0]_i_3_n_0 ;
wire \TIMER[10]_i_1_n_0 ;
wire \TIMER[10]_i_2_n_0 ;
wire \TIMER[10]_i_3_n_0 ;
wire \TIMER[10]_i_5_n_0 ;
wire \TIMER[10]_i_6_n_0 ;
wire \TIMER[10]_i_7_n_0 ;
wire \TIMER[11]_i_1_n_0 ;
wire \TIMER[1]_i_1__2_n_0 ;
wire \TIMER[2]_i_1_n_0 ;
wire \TIMER[3]_i_1__2_n_0 ;
wire \TIMER[4]_i_1__2_n_0 ;
wire \TIMER[4]_i_3_n_0 ;
wire \TIMER[4]_i_4_n_0 ;
wire \TIMER[4]_i_5_n_0 ;
wire \TIMER[4]_i_6_n_0 ;
wire \TIMER[5]_i_1__2_n_0 ;
wire \TIMER[5]_i_3_n_0 ;
wire \TIMER[5]_i_4_n_0 ;
wire \TIMER[5]_i_5_n_0 ;
wire \TIMER[5]_i_6_n_0 ;
wire \TIMER[6]_i_1_n_0 ;
wire \TIMER[7]_i_1_n_0 ;
wire \TIMER[8]_i_1_n_0 ;
wire \TIMER[9]_i_1__2_n_0 ;
wire \TIMER_reg[10]_i_4_n_5 ;
wire \TIMER_reg[10]_i_4_n_6 ;
wire \TIMER_reg[10]_i_4_n_7 ;
wire \TIMER_reg[4]_i_2_n_0 ;
wire \TIMER_reg[4]_i_2_n_4 ;
wire \TIMER_reg[4]_i_2_n_5 ;
wire \TIMER_reg[4]_i_2_n_6 ;
wire \TIMER_reg[4]_i_2_n_7 ;
wire \TIMER_reg[5]_i_2_n_0 ;
wire \TIMER_reg[5]_i_2_n_4 ;
wire \TIMER_reg[5]_i_2_n_5 ;
wire \TIMER_reg[5]_i_2_n_6 ;
wire \TIMER_reg[5]_i_2_n_7 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[10] ;
wire \TIMER_reg_n_0_[11] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire g0_b0_n_0;
wire [3:0]\NLW_TIMER_reg[10]_i_4_CO_UNCONNECTED ;
wire [3:3]\NLW_TIMER_reg[10]_i_4_O_UNCONNECTED ;
wire [2:0]\NLW_TIMER_reg[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_TIMER_reg[5]_i_2_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'hFFF0FA3300000A00))
BIT_i_1
(.I0(SDA_I_SYNCH),
.I1(BIT_i_2_n_0),
.I2(BIT_i_3_n_0),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(BIT_reg_n_0),
.O(BIT_i_1_n_0));
LUT3 #(
.INIT(8'h40))
BIT_i_2
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[3] ),
.O(BIT_i_2_n_0));
LUT3 #(
.INIT(8'hEF))
BIT_i_3
(.I0(\STATE_reg_n_0_[0] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[1] ),
.O(BIT_i_3_n_0));
FDRE BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BIT_i_1_n_0),
.Q(BIT_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h1FF0))
\COUNT[0]_i_1__0
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\COUNT[2]_i_2_n_0 ),
.I3(COUNT[0]),
.O(\COUNT[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'hF1FF1F00))
\COUNT[1]_i_1__0
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[2] ),
.I2(COUNT[0]),
.I3(\COUNT[2]_i_2_n_0 ),
.I4(COUNT[1]),
.O(\COUNT[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFF1FFFF111F0000))
\COUNT[2]_i_1
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(COUNT[0]),
.I3(COUNT[1]),
.I4(\COUNT[2]_i_2_n_0 ),
.I5(COUNT[2]),
.O(\COUNT[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00100401))
\COUNT[2]_i_2
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[0] ),
.O(\COUNT[2]_i_2_n_0 ));
FDRE \COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[0]_i_1__0_n_0 ),
.Q(COUNT[0]),
.R(1'b0));
FDRE \COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[1]_i_1__0_n_0 ),
.Q(COUNT[1]),
.R(1'b0));
FDRE \COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[2]_i_1_n_0 ),
.Q(COUNT[2]),
.R(1'b0));
LUT6 #(
.INIT(64'hFBFFFFFF00000010))
\GET_BIT_RETURN[0]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(GET_BIT_RETURN[0]),
.O(\GET_BIT_RETURN[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF04000000))
\GET_BIT_RETURN[3]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(GET_BIT_RETURN[3]),
.O(\GET_BIT_RETURN[3]_i_1_n_0 ));
FDRE \GET_BIT_RETURN_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\GET_BIT_RETURN[0]_i_1_n_0 ),
.Q(GET_BIT_RETURN[0]),
.R(1'b0));
FDRE \GET_BIT_RETURN_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\GET_BIT_RETURN[3]_i_1_n_0 ),
.Q(GET_BIT_RETURN[3]),
.R(1'b0));
FDRE SCL_I_D_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SCL_IBUF),
.Q(SCL_I_D),
.R(1'b0));
FDRE SCL_I_SYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SCL_I_D),
.Q(SCL_I_SYNCH),
.R(1'b0));
LUT6 #(
.INIT(64'h403FFFFF403F0000))
SCL_O_i_1
(.I0(\STATE_reg_n_0_[0] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(SCL_O_i_2_n_0),
.I5(SCL_TRI),
.O(SCL_O_i_1_n_0));
LUT6 #(
.INIT(64'hFFFFFFFF01000000))
SCL_O_i_2
(.I0(\TIMER[0]_i_2_n_0 ),
.I1(SCL_O_i_3_n_0),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(SCL_O_i_4_n_0),
.O(SCL_O_i_2_n_0));
LUT2 #(
.INIT(4'h1))
SCL_O_i_3
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.O(SCL_O_i_3_n_0));
LUT6 #(
.INIT(64'h3C0C0C2C3C000000))
SCL_O_i_4
(.I0(\TIMER[10]_i_3_n_0 ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(\STATE_reg_n_0_[3] ),
.I5(\STATE_reg_n_0_[4] ),
.O(SCL_O_i_4_n_0));
FDSE SCL_O_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SCL_O_i_1_n_0),
.Q(SCL_TRI),
.S(INTERNAL_RST_reg));
FDRE SDA_I_D_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SDA_IBUF),
.Q(SDA_I_D),
.R(1'b0));
FDRE SDA_I_SYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SDA_I_D),
.Q(SDA_I_SYNCH),
.R(1'b0));
LUT6 #(
.INIT(64'hADA5FFFFADA50000))
SDA_O_i_1
(.I0(\STATE_reg_n_0_[3] ),
.I1(BIT_reg_n_0),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(SDA_O_i_2_n_0),
.I5(SDA_TRI),
.O(SDA_O_i_1_n_0));
LUT6 #(
.INIT(64'h9098803080988030))
SDA_O_i_2
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[4] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[3] ),
.I5(\TIMER[10]_i_3_n_0 ),
.O(SDA_O_i_2_n_0));
FDSE SDA_O_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SDA_O_i_1_n_0),
.Q(SDA_TRI),
.S(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFFFFBF01000000))
\SEND_BIT_RETURN[0]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(SEND_BIT_RETURN[0]),
.O(\SEND_BIT_RETURN[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFEFFFFFF00000040))
\SEND_BIT_RETURN[3]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(SEND_BIT_RETURN[3]),
.O(\SEND_BIT_RETURN[3]_i_1_n_0 ));
FDRE \SEND_BIT_RETURN_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\SEND_BIT_RETURN[0]_i_1_n_0 ),
.Q(SEND_BIT_RETURN[0]),
.R(1'b0));
FDRE \SEND_BIT_RETURN_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\SEND_BIT_RETURN[3]_i_1_n_0 ),
.Q(SEND_BIT_RETURN[3]),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFDFFFD08000000))
STARTED_i_1
(.I0(STARTED_i_2_n_0),
.I1(\STATE_reg_n_0_[4] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(\TIMER[10]_i_3_n_0 ),
.I5(STARTED),
.O(STARTED_i_1_n_0));
LUT4 #(
.INIT(16'hEAAB))
STARTED_i_2
(.I0(\STATE_reg_n_0_[3] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[0] ),
.O(STARTED_i_2_n_0));
FDRE STARTED_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(STARTED_i_1_n_0),
.Q(STARTED),
.R(1'b0));
LUT5 #(
.INIT(32'hB0FC3CCF))
\STATE[0]_i_2
(.I0(SEND_BIT_RETURN[0]),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[0] ),
.I4(\STATE_reg_n_0_[2] ),
.O(\STATE[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h040004005F5F5A5F))
\STATE[0]_i_3
(.I0(\STATE_reg_n_0_[3] ),
.I1(STARTED),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(GET_BIT_RETURN[0]),
.I5(\STATE_reg_n_0_[0] ),
.O(\STATE[0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h2))
\STATE[1]_i_1
(.I0(\STATE[1]_i_2_n_0 ),
.I1(\STATE[1]_i_3_n_0 ),
.O(\STATE[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h12781258FFFFFFFF))
\STATE[1]_i_2
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[2] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(STARTED),
.I5(\STATE_reg_n_0_[4] ),
.O(\STATE[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0005010555155055))
\STATE[1]_i_3
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE[1]_i_4_n_0 ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[0] ),
.I4(\STATE_reg_n_0_[1] ),
.I5(\STATE_reg_n_0_[2] ),
.O(\STATE[1]_i_3_n_0 ));
LUT3 #(
.INIT(8'h01))
\STATE[1]_i_4
(.I0(COUNT[2]),
.I1(COUNT[1]),
.I2(COUNT[0]),
.O(\STATE[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'h406EB828406E3828))
\STATE[2]_i_1
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.I5(SEND_BIT_RETURN[0]),
.O(\STATE[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8F00F5F0))
\STATE[3]_i_2
(.I0(\STATE_reg_n_0_[2] ),
.I1(SEND_BIT_RETURN[3]),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[0] ),
.O(\STATE[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0F0F0200))
\STATE[3]_i_3
(.I0(GET_BIT_RETURN[3]),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[3] ),
.O(\STATE[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFF4F4F0FF))
\STATE[4]_i_1
(.I0(\STATE[4]_i_3_n_0 ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE[4]_i_4_n_0 ),
.I3(\STATE[4]_i_5_n_0 ),
.I4(\STATE_reg_n_0_[1] ),
.I5(\STATE[4]_i_6_n_0 ),
.O(\STATE[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'h1301FD80))
\STATE[4]_i_2
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[2] ),
.O(\STATE[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hEEEEEE0FEE00EE0F))
\STATE[4]_i_3
(.I0(\TIMER_reg_n_0_[0] ),
.I1(\TIMER[0]_i_2_n_0 ),
.I2(S_I2C_OUT_STB_reg_n_0),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.I5(\STATE_reg_n_0_[2] ),
.O(\STATE[4]_i_3_n_0 ));
LUT5 #(
.INIT(32'h80AA8000))
\STATE[4]_i_4
(.I0(\TIMER[10]_i_3_n_0 ),
.I1(\STATE_reg_n_0_[2] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[0] ),
.I4(\STATE_reg_n_0_[4] ),
.O(\STATE[4]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFC0C0CDCFCFCDCDC))
\STATE[4]_i_5
(.I0(S_I2C_IN_ACK_reg_n_0),
.I1(\STATE_reg_n_0_[4] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(SCL_I_SYNCH),
.O(\STATE[4]_i_5_n_0 ));
LUT5 #(
.INIT(32'h004075BB))
\STATE[4]_i_6
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[0] ),
.I2(SCL_I_SYNCH),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.O(\STATE[4]_i_6_n_0 ));
FDRE \STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE_reg[0]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
MUXF7 \STATE_reg[0]_i_1
(.I0(\STATE[0]_i_2_n_0 ),
.I1(\STATE[0]_i_3_n_0 ),
.O(\STATE_reg[0]_i_1_n_0 ),
.S(\STATE_reg_n_0_[4] ));
FDRE \STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE[1]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \STATE_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE[2]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \STATE_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE_reg[3]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
MUXF7 \STATE_reg[3]_i_1
(.I0(\STATE[3]_i_2_n_0 ),
.I1(\STATE[3]_i_3_n_0 ),
.O(\STATE_reg[3]_i_1_n_0 ),
.S(\STATE_reg_n_0_[4] ));
FDRE \STATE_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE[4]_i_2_n_0 ),
.Q(\STATE_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFEFFFF00010000))
S_I2C_IN_ACK_i_1
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(S_I2C_IN_ACK_reg_n_0),
.O(S_I2C_IN_ACK_i_1_n_0));
FDRE S_I2C_IN_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_I2C_IN_ACK_i_1_n_0),
.Q(S_I2C_IN_ACK_reg_n_0),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFDFFFF00020000))
S_I2C_OUT_STB_i_1
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[2] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(S_I2C_OUT_STB_reg_n_0),
.O(S_I2C_OUT_STB_i_1_n_0));
FDRE S_I2C_OUT_STB_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_I2C_OUT_STB_i_1_n_0),
.Q(S_I2C_OUT_STB_reg_n_0),
.R(INTERNAL_RST_reg));
LUT5 #(
.INIT(32'h00FFA800))
\TIMER[0]_i_1
(.I0(\TIMER[0]_i_2_n_0 ),
.I1(\STATE_reg_n_0_[4] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(g0_b0_n_0),
.I4(\TIMER_reg_n_0_[0] ),
.O(\TIMER[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\TIMER[0]_i_2
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[11] ),
.I2(\TIMER_reg_n_0_[7] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[1] ),
.I5(\TIMER[0]_i_3_n_0 ),
.O(\TIMER[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\TIMER[0]_i_3
(.I0(\TIMER_reg_n_0_[6] ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[9] ),
.I3(\TIMER_reg_n_0_[10] ),
.I4(\TIMER_reg_n_0_[5] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(\TIMER[0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\TIMER[10]_i_1
(.I0(\TIMER[10]_i_3_n_0 ),
.I1(g0_b0_n_0),
.O(\TIMER[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[10]_i_2
(.I0(\TIMER_reg[10]_i_4_n_6 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[10]_i_2_n_0 ));
LUT2 #(
.INIT(4'h1))
\TIMER[10]_i_3
(.I0(\TIMER_reg_n_0_[0] ),
.I1(\TIMER[0]_i_2_n_0 ),
.O(\TIMER[10]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[10]_i_5
(.I0(\TIMER_reg_n_0_[11] ),
.O(\TIMER[10]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[10]_i_6
(.I0(\TIMER_reg_n_0_[10] ),
.O(\TIMER[10]_i_6_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[10]_i_7
(.I0(\TIMER_reg_n_0_[9] ),
.O(\TIMER[10]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[11]_i_1
(.I0(\TIMER_reg[10]_i_4_n_5 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[1]_i_1__2
(.I0(\TIMER_reg[4]_i_2_n_7 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[2]_i_1
(.I0(\TIMER_reg[4]_i_2_n_6 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[3]_i_1__2
(.I0(\TIMER_reg[4]_i_2_n_5 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[4]_i_1__2
(.I0(\TIMER_reg[4]_i_2_n_4 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[4]_i_1__2_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_3
(.I0(\TIMER_reg_n_0_[4] ),
.O(\TIMER[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_4
(.I0(\TIMER_reg_n_0_[3] ),
.O(\TIMER[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_5
(.I0(\TIMER_reg_n_0_[2] ),
.O(\TIMER[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_6
(.I0(\TIMER_reg_n_0_[1] ),
.O(\TIMER[4]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[5]_i_1__2
(.I0(\TIMER_reg[5]_i_2_n_7 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[5]_i_1__2_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_3
(.I0(\TIMER_reg_n_0_[8] ),
.O(\TIMER[5]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_4
(.I0(\TIMER_reg_n_0_[7] ),
.O(\TIMER[5]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_5
(.I0(\TIMER_reg_n_0_[6] ),
.O(\TIMER[5]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_6
(.I0(\TIMER_reg_n_0_[5] ),
.O(\TIMER[5]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[6]_i_1
(.I0(\TIMER_reg[5]_i_2_n_6 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAB))
\TIMER[7]_i_1
(.I0(\TIMER_reg[5]_i_2_n_5 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[8]_i_1
(.I0(\TIMER_reg[5]_i_2_n_4 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[9]_i_1__2
(.I0(\TIMER_reg[10]_i_4_n_7 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[9]_i_1__2_n_0 ));
FDRE \TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TIMER[0]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE \TIMER_reg[10]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[10]_i_2_n_0 ),
.Q(\TIMER_reg_n_0_[10] ),
.R(\TIMER[10]_i_1_n_0 ));
CARRY4 \TIMER_reg[10]_i_4
(.CI(\TIMER_reg[5]_i_2_n_0 ),
.CO(\NLW_TIMER_reg[10]_i_4_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\TIMER_reg_n_0_[10] ,\TIMER_reg_n_0_[9] }),
.O({\NLW_TIMER_reg[10]_i_4_O_UNCONNECTED [3],\TIMER_reg[10]_i_4_n_5 ,\TIMER_reg[10]_i_4_n_6 ,\TIMER_reg[10]_i_4_n_7 }),
.S({1'b0,\TIMER[10]_i_5_n_0 ,\TIMER[10]_i_6_n_0 ,\TIMER[10]_i_7_n_0 }));
FDSE \TIMER_reg[11]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[11]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[11] ),
.S(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[1]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[1] ),
.R(\TIMER[10]_i_1_n_0 ));
FDSE \TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[2]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[2] ),
.S(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[3]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[3] ),
.R(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[4]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[4] ),
.R(\TIMER[10]_i_1_n_0 ));
CARRY4 \TIMER_reg[4]_i_2
(.CI(1'b0),
.CO({\TIMER_reg[4]_i_2_n_0 ,\NLW_TIMER_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(\TIMER_reg_n_0_[0] ),
.DI({\TIMER_reg_n_0_[4] ,\TIMER_reg_n_0_[3] ,\TIMER_reg_n_0_[2] ,\TIMER_reg_n_0_[1] }),
.O({\TIMER_reg[4]_i_2_n_4 ,\TIMER_reg[4]_i_2_n_5 ,\TIMER_reg[4]_i_2_n_6 ,\TIMER_reg[4]_i_2_n_7 }),
.S({\TIMER[4]_i_3_n_0 ,\TIMER[4]_i_4_n_0 ,\TIMER[4]_i_5_n_0 ,\TIMER[4]_i_6_n_0 }));
FDRE \TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[5]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[5] ),
.R(\TIMER[10]_i_1_n_0 ));
CARRY4 \TIMER_reg[5]_i_2
(.CI(\TIMER_reg[4]_i_2_n_0 ),
.CO({\TIMER_reg[5]_i_2_n_0 ,\NLW_TIMER_reg[5]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\TIMER_reg_n_0_[8] ,\TIMER_reg_n_0_[7] ,\TIMER_reg_n_0_[6] ,\TIMER_reg_n_0_[5] }),
.O({\TIMER_reg[5]_i_2_n_4 ,\TIMER_reg[5]_i_2_n_5 ,\TIMER_reg[5]_i_2_n_6 ,\TIMER_reg[5]_i_2_n_7 }),
.S({\TIMER[5]_i_3_n_0 ,\TIMER[5]_i_4_n_0 ,\TIMER[5]_i_5_n_0 ,\TIMER[5]_i_6_n_0 }));
FDSE \TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[6]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[6] ),
.S(\TIMER[10]_i_1_n_0 ));
FDSE \TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[7]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[7] ),
.S(\TIMER[10]_i_1_n_0 ));
FDSE \TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[8]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[8] ),
.S(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[9]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[9] ),
.R(\TIMER[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'h1DD5A001))
g0_b0
(.I0(\STATE_reg_n_0_[0] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.O(g0_b0_n_0));
endmodule
module IOBUF_UNIQ_BASE_
(IO,
O,
I,
T);
inout IO;
output O;
input I;
input T;
wire I;
wire IO;
wire O;
wire T;
IBUF IBUF
(.I(IO),
.O(O));
OBUFT OBUFT
(.I(I),
.O(IO),
.T(T));
endmodule
(* ORIG_REF_NAME = "IOBUF" *)
module IOBUF_HD3
(IO,
O,
I,
T);
inout IO;
output O;
input I;
input T;
wire I;
wire IO;
wire O;
wire T;
IBUF #(
.IOSTANDARD("DEFAULT"))
IBUF
(.I(IO),
.O(O));
OBUFT #(
.IOSTANDARD("DEFAULT"))
OBUFT
(.I(I),
.O(IO),
.T(T));
endmodule
module PWM
(LED_R_PWM_OBUF,
ETH_CLK_OBUF);
output LED_R_PWM_OBUF;
input ETH_CLK_OBUF;
wire \COUNT[0]_i_1__1_n_0 ;
wire \COUNT[1]_i_1__1_n_0 ;
wire \COUNT[1]_i_2_n_0 ;
wire \COUNT[2]_i_1__0_n_0 ;
wire \COUNT[3]_i_1_n_0 ;
wire \COUNT[3]_i_2_n_0 ;
wire \COUNT[4]_i_1_n_0 ;
wire \COUNT[5]_i_1_n_0 ;
wire \COUNT[6]_i_1_n_0 ;
wire \COUNT[7]_i_1_n_0 ;
wire \COUNT[7]_i_2_n_0 ;
wire \COUNT[7]_i_3_n_0 ;
wire \COUNT_reg_n_0_[0] ;
wire \COUNT_reg_n_0_[1] ;
wire \COUNT_reg_n_0_[2] ;
wire \COUNT_reg_n_0_[3] ;
wire \COUNT_reg_n_0_[4] ;
wire \COUNT_reg_n_0_[5] ;
wire \COUNT_reg_n_0_[6] ;
wire \COUNT_reg_n_0_[7] ;
wire ETH_CLK_OBUF;
wire LED_R_PWM_OBUF;
wire OUT_BIT_i_10_n_0;
wire OUT_BIT_i_1_n_0;
wire OUT_BIT_i_3_n_0;
wire OUT_BIT_i_4_n_0;
wire OUT_BIT_i_5_n_0;
wire OUT_BIT_i_6_n_0;
wire OUT_BIT_i_7_n_0;
wire OUT_BIT_i_8_n_0;
wire OUT_BIT_i_9_n_0;
wire [9:0]TIMER;
wire \TIMER[4]_i_2_n_0 ;
wire \TIMER[9]_i_2_n_0 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire p_0_in;
wire [2:0]NLW_OUT_BIT_reg_i_2_CO_UNCONNECTED;
wire [3:0]NLW_OUT_BIT_reg_i_2_O_UNCONNECTED;
LUT6 #(
.INIT(64'h2333333333333333))
\COUNT[0]_i_1__1
(.I0(\COUNT[7]_i_3_n_0 ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT_reg_n_0_[4] ),
.I4(\COUNT_reg_n_0_[7] ),
.I5(\COUNT_reg_n_0_[6] ),
.O(\COUNT[0]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'h00FFBF00))
\COUNT[1]_i_1__1
(.I0(\COUNT[1]_i_2_n_0 ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(\COUNT_reg_n_0_[2] ),
.I3(\COUNT_reg_n_0_[1] ),
.I4(\COUNT_reg_n_0_[0] ),
.O(\COUNT[1]_i_1__1_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\COUNT[1]_i_2
(.I0(\COUNT_reg_n_0_[5] ),
.I1(\COUNT_reg_n_0_[4] ),
.I2(\COUNT_reg_n_0_[7] ),
.I3(\COUNT_reg_n_0_[6] ),
.O(\COUNT[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT5 #(
.INIT(32'hFFC011C0))
\COUNT[2]_i_1__0
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[1] ),
.I3(\COUNT_reg_n_0_[2] ),
.I4(\COUNT[3]_i_2_n_0 ),
.O(\COUNT[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT5 #(
.INIT(32'hFF805580))
\COUNT[3]_i_1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[1] ),
.I2(\COUNT_reg_n_0_[0] ),
.I3(\COUNT_reg_n_0_[3] ),
.I4(\COUNT[3]_i_2_n_0 ),
.O(\COUNT[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h15555555FFFFFFFF))
\COUNT[3]_i_2
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT_reg_n_0_[4] ),
.I3(\COUNT_reg_n_0_[7] ),
.I4(\COUNT_reg_n_0_[6] ),
.I5(\COUNT_reg_n_0_[1] ),
.O(\COUNT[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF00FF7F00FF0000))
\COUNT[4]_i_1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[6] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT[7]_i_3_n_0 ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAABFFFFF55000000))
\COUNT[5]_i_1
(.I0(\COUNT[7]_i_3_n_0 ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT_reg_n_0_[0] ),
.I4(\COUNT_reg_n_0_[4] ),
.I5(\COUNT_reg_n_0_[5] ),
.O(\COUNT[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF01CF0F0F0F0F0F0))
\COUNT[6]_i_1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT[7]_i_3_n_0 ),
.I4(\COUNT_reg_n_0_[5] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\COUNT[7]_i_1
(.I0(\TIMER_reg_n_0_[9] ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.I5(\TIMER[9]_i_2_n_0 ),
.O(\COUNT[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF7FFF7FF08000000))
\COUNT[7]_i_2
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT[7]_i_3_n_0 ),
.I3(\COUNT_reg_n_0_[6] ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[7] ),
.O(\COUNT[7]_i_2_n_0 ));
LUT3 #(
.INIT(8'h7F))
\COUNT[7]_i_3
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[2] ),
.I2(\COUNT_reg_n_0_[1] ),
.O(\COUNT[7]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[0]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[1]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[2]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[3]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[4]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[5]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[6]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[7]_i_2_n_0 ),
.Q(\COUNT_reg_n_0_[7] ),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
OUT_BIT_i_1
(.I0(p_0_in),
.O(OUT_BIT_i_1_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_10
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_10_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_3
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_3_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_4
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_4_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_5
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_5_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_6
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_6_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_7
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_7_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_8
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_8_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_9
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_9_n_0));
FDRE OUT_BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(OUT_BIT_i_1_n_0),
.Q(LED_R_PWM_OBUF),
.R(1'b0));
CARRY4 OUT_BIT_reg_i_2
(.CI(1'b0),
.CO({p_0_in,NLW_OUT_BIT_reg_i_2_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({OUT_BIT_i_3_n_0,OUT_BIT_i_4_n_0,OUT_BIT_i_5_n_0,OUT_BIT_i_6_n_0}),
.O(NLW_OUT_BIT_reg_i_2_O_UNCONNECTED[3:0]),
.S({OUT_BIT_i_7_n_0,OUT_BIT_i_8_n_0,OUT_BIT_i_9_n_0,OUT_BIT_i_10_n_0}));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT1 #(
.INIT(2'h1))
\TIMER[0]_i_1__0
(.I0(\TIMER_reg_n_0_[0] ),
.O(TIMER[0]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT2 #(
.INIT(4'h9))
\TIMER[1]_i_1
(.I0(\TIMER_reg_n_0_[1] ),
.I1(\TIMER_reg_n_0_[0] ),
.O(TIMER[1]));
LUT3 #(
.INIT(8'hA9))
\TIMER[2]_i_1__0
(.I0(\TIMER_reg_n_0_[2] ),
.I1(\TIMER_reg_n_0_[0] ),
.I2(\TIMER_reg_n_0_[1] ),
.O(TIMER[2]));
LUT6 #(
.INIT(64'hF0F0F0F0F0F0F00E))
\TIMER[3]_i_1
(.I0(\TIMER[4]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[4] ),
.I2(\TIMER_reg_n_0_[3] ),
.I3(\TIMER_reg_n_0_[1] ),
.I4(\TIMER_reg_n_0_[0] ),
.I5(\TIMER_reg_n_0_[2] ),
.O(TIMER[3]));
LUT6 #(
.INIT(64'hFFFE0001FFFE0000))
\TIMER[4]_i_1
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.I5(\TIMER[4]_i_2_n_0 ),
.O(TIMER[4]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[4]_i_2
(.I0(\TIMER_reg_n_0_[8] ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.I4(\TIMER_reg_n_0_[9] ),
.O(\TIMER[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\TIMER[5]_i_1
(.I0(\TIMER_reg_n_0_[5] ),
.I1(\TIMER_reg_n_0_[3] ),
.I2(\TIMER_reg_n_0_[1] ),
.I3(\TIMER_reg_n_0_[0] ),
.I4(\TIMER_reg_n_0_[2] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(TIMER[5]));
LUT3 #(
.INIT(8'hE1))
\TIMER[6]_i_1__0
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[5] ),
.I2(\TIMER_reg_n_0_[6] ),
.O(TIMER[6]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT4 #(
.INIT(16'hFE01))
\TIMER[7]_i_1__0
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.O(TIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT5 #(
.INIT(32'hFFFE0001))
\TIMER[8]_i_1__0
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.O(TIMER[8]));
LUT6 #(
.INIT(64'hFFFFFFFE00000001))
\TIMER[9]_i_1
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[6] ),
.I3(\TIMER_reg_n_0_[5] ),
.I4(\TIMER_reg_n_0_[7] ),
.I5(\TIMER_reg_n_0_[9] ),
.O(TIMER[9]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[9]_i_2
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.O(\TIMER[9]_i_2_n_0 ));
FDRE #(
.INIT(1'b1))
\TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[0]),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[1]),
.Q(\TIMER_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[2]),
.Q(\TIMER_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[3]),
.Q(\TIMER_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[4]),
.Q(\TIMER_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[5]),
.Q(\TIMER_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[6]),
.Q(\TIMER_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[7]),
.Q(\TIMER_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[8]),
.Q(\TIMER_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[9]),
.Q(\TIMER_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "PWM" *)
module PWM_0
(LED_G_PWM_OBUF,
ETH_CLK_OBUF);
output LED_G_PWM_OBUF;
input ETH_CLK_OBUF;
wire \COUNT[0]_i_1__2_n_0 ;
wire \COUNT[1]_i_1__2_n_0 ;
wire \COUNT[1]_i_2__0_n_0 ;
wire \COUNT[2]_i_1__1_n_0 ;
wire \COUNT[3]_i_1__0_n_0 ;
wire \COUNT[3]_i_2__0_n_0 ;
wire \COUNT[4]_i_1__0_n_0 ;
wire \COUNT[5]_i_1__0_n_0 ;
wire \COUNT[6]_i_1__0_n_0 ;
wire \COUNT[7]_i_1__0_n_0 ;
wire \COUNT[7]_i_2__0_n_0 ;
wire \COUNT[7]_i_3__0_n_0 ;
wire \COUNT_reg_n_0_[0] ;
wire \COUNT_reg_n_0_[1] ;
wire \COUNT_reg_n_0_[2] ;
wire \COUNT_reg_n_0_[3] ;
wire \COUNT_reg_n_0_[4] ;
wire \COUNT_reg_n_0_[5] ;
wire \COUNT_reg_n_0_[6] ;
wire \COUNT_reg_n_0_[7] ;
wire ETH_CLK_OBUF;
wire LED_G_PWM_OBUF;
wire OUT_BIT_i_10__0_n_0;
wire OUT_BIT_i_1__0_n_0;
wire OUT_BIT_i_3__0_n_0;
wire OUT_BIT_i_4__0_n_0;
wire OUT_BIT_i_5__0_n_0;
wire OUT_BIT_i_6__0_n_0;
wire OUT_BIT_i_7__0_n_0;
wire OUT_BIT_i_8__0_n_0;
wire OUT_BIT_i_9__0_n_0;
wire [9:0]TIMER;
wire \TIMER[4]_i_2__0_n_0 ;
wire \TIMER[9]_i_2__0_n_0 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire p_0_in;
wire [2:0]NLW_OUT_BIT_reg_i_2__0_CO_UNCONNECTED;
wire [3:0]NLW_OUT_BIT_reg_i_2__0_O_UNCONNECTED;
LUT6 #(
.INIT(64'h2333333333333333))
\COUNT[0]_i_1__2
(.I0(\COUNT[7]_i_3__0_n_0 ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT_reg_n_0_[4] ),
.I4(\COUNT_reg_n_0_[7] ),
.I5(\COUNT_reg_n_0_[6] ),
.O(\COUNT[0]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'h00FFBF00))
\COUNT[1]_i_1__2
(.I0(\COUNT[1]_i_2__0_n_0 ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(\COUNT_reg_n_0_[2] ),
.I3(\COUNT_reg_n_0_[1] ),
.I4(\COUNT_reg_n_0_[0] ),
.O(\COUNT[1]_i_1__2_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\COUNT[1]_i_2__0
(.I0(\COUNT_reg_n_0_[5] ),
.I1(\COUNT_reg_n_0_[4] ),
.I2(\COUNT_reg_n_0_[7] ),
.I3(\COUNT_reg_n_0_[6] ),
.O(\COUNT[1]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'hFFC011C0))
\COUNT[2]_i_1__1
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[1] ),
.I3(\COUNT_reg_n_0_[2] ),
.I4(\COUNT[3]_i_2__0_n_0 ),
.O(\COUNT[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'hFF805580))
\COUNT[3]_i_1__0
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[1] ),
.I2(\COUNT_reg_n_0_[0] ),
.I3(\COUNT_reg_n_0_[3] ),
.I4(\COUNT[3]_i_2__0_n_0 ),
.O(\COUNT[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h15555555FFFFFFFF))
\COUNT[3]_i_2__0
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT_reg_n_0_[4] ),
.I3(\COUNT_reg_n_0_[7] ),
.I4(\COUNT_reg_n_0_[6] ),
.I5(\COUNT_reg_n_0_[1] ),
.O(\COUNT[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFF00FF7F00FF0000))
\COUNT[4]_i_1__0
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[6] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT[7]_i_3__0_n_0 ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[4]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAABFFFFF55000000))
\COUNT[5]_i_1__0
(.I0(\COUNT[7]_i_3__0_n_0 ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT_reg_n_0_[0] ),
.I4(\COUNT_reg_n_0_[4] ),
.I5(\COUNT_reg_n_0_[5] ),
.O(\COUNT[5]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF01CF0F0F0F0F0F0))
\COUNT[6]_i_1__0
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT[7]_i_3__0_n_0 ),
.I4(\COUNT_reg_n_0_[5] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[6]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\COUNT[7]_i_1__0
(.I0(\TIMER_reg_n_0_[9] ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.I5(\TIMER[9]_i_2__0_n_0 ),
.O(\COUNT[7]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF7FFF7FF08000000))
\COUNT[7]_i_2__0
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT[7]_i_3__0_n_0 ),
.I3(\COUNT_reg_n_0_[6] ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[7] ),
.O(\COUNT[7]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'h7F))
\COUNT[7]_i_3__0
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[2] ),
.I2(\COUNT_reg_n_0_[1] ),
.O(\COUNT[7]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[0]_i_1__2_n_0 ),
.Q(\COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[1]_i_1__2_n_0 ),
.Q(\COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[2]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[3]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[4]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[5]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[6]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[7]_i_2__0_n_0 ),
.Q(\COUNT_reg_n_0_[7] ),
.R(1'b0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_10__0
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_10__0_n_0));
LUT1 #(
.INIT(2'h1))
OUT_BIT_i_1__0
(.I0(p_0_in),
.O(OUT_BIT_i_1__0_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_3__0
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_3__0_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_4__0
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_4__0_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_5__0
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_5__0_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_6__0
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_6__0_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_7__0
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_7__0_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_8__0
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_8__0_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_9__0
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_9__0_n_0));
FDRE OUT_BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(OUT_BIT_i_1__0_n_0),
.Q(LED_G_PWM_OBUF),
.R(1'b0));
CARRY4 OUT_BIT_reg_i_2__0
(.CI(1'b0),
.CO({p_0_in,NLW_OUT_BIT_reg_i_2__0_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({OUT_BIT_i_3__0_n_0,OUT_BIT_i_4__0_n_0,OUT_BIT_i_5__0_n_0,OUT_BIT_i_6__0_n_0}),
.O(NLW_OUT_BIT_reg_i_2__0_O_UNCONNECTED[3:0]),
.S({OUT_BIT_i_7__0_n_0,OUT_BIT_i_8__0_n_0,OUT_BIT_i_9__0_n_0,OUT_BIT_i_10__0_n_0}));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT1 #(
.INIT(2'h1))
\TIMER[0]_i_1__1
(.I0(\TIMER_reg_n_0_[0] ),
.O(TIMER[0]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT2 #(
.INIT(4'h9))
\TIMER[1]_i_1__0
(.I0(\TIMER_reg_n_0_[1] ),
.I1(\TIMER_reg_n_0_[0] ),
.O(TIMER[1]));
LUT3 #(
.INIT(8'hA9))
\TIMER[2]_i_1__1
(.I0(\TIMER_reg_n_0_[2] ),
.I1(\TIMER_reg_n_0_[0] ),
.I2(\TIMER_reg_n_0_[1] ),
.O(TIMER[2]));
LUT6 #(
.INIT(64'hF0F0F0F0F0F0F00E))
\TIMER[3]_i_1__0
(.I0(\TIMER[4]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[4] ),
.I2(\TIMER_reg_n_0_[3] ),
.I3(\TIMER_reg_n_0_[1] ),
.I4(\TIMER_reg_n_0_[0] ),
.I5(\TIMER_reg_n_0_[2] ),
.O(TIMER[3]));
LUT6 #(
.INIT(64'hFFFE0001FFFE0000))
\TIMER[4]_i_1__0
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.I5(\TIMER[4]_i_2__0_n_0 ),
.O(TIMER[4]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[4]_i_2__0
(.I0(\TIMER_reg_n_0_[8] ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.I4(\TIMER_reg_n_0_[9] ),
.O(\TIMER[4]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\TIMER[5]_i_1__0
(.I0(\TIMER_reg_n_0_[5] ),
.I1(\TIMER_reg_n_0_[3] ),
.I2(\TIMER_reg_n_0_[1] ),
.I3(\TIMER_reg_n_0_[0] ),
.I4(\TIMER_reg_n_0_[2] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(TIMER[5]));
LUT3 #(
.INIT(8'hE1))
\TIMER[6]_i_1__1
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[5] ),
.I2(\TIMER_reg_n_0_[6] ),
.O(TIMER[6]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT4 #(
.INIT(16'hFE01))
\TIMER[7]_i_1__1
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.O(TIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT5 #(
.INIT(32'hFFFE0001))
\TIMER[8]_i_1__1
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.O(TIMER[8]));
LUT6 #(
.INIT(64'hFFFFFFFE00000001))
\TIMER[9]_i_1__0
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[6] ),
.I3(\TIMER_reg_n_0_[5] ),
.I4(\TIMER_reg_n_0_[7] ),
.I5(\TIMER_reg_n_0_[9] ),
.O(TIMER[9]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[9]_i_2__0
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.O(\TIMER[9]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b1))
\TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[0]),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[1]),
.Q(\TIMER_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[2]),
.Q(\TIMER_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[3]),
.Q(\TIMER_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[4]),
.Q(\TIMER_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[5]),
.Q(\TIMER_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[6]),
.Q(\TIMER_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[7]),
.Q(\TIMER_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[8]),
.Q(\TIMER_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[9]),
.Q(\TIMER_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "PWM" *)
module PWM_1
(LED_B_PWM_OBUF,
ETH_CLK_OBUF);
output LED_B_PWM_OBUF;
input ETH_CLK_OBUF;
wire \COUNT[0]_i_1__3_n_0 ;
wire \COUNT[1]_i_1__3_n_0 ;
wire \COUNT[1]_i_2__1_n_0 ;
wire \COUNT[2]_i_1__2_n_0 ;
wire \COUNT[3]_i_1__1_n_0 ;
wire \COUNT[3]_i_2__1_n_0 ;
wire \COUNT[4]_i_1__1_n_0 ;
wire \COUNT[5]_i_1__1_n_0 ;
wire \COUNT[6]_i_1__1_n_0 ;
wire \COUNT[7]_i_1__1_n_0 ;
wire \COUNT[7]_i_2__1_n_0 ;
wire \COUNT[7]_i_3__1_n_0 ;
wire \COUNT_reg_n_0_[0] ;
wire \COUNT_reg_n_0_[1] ;
wire \COUNT_reg_n_0_[2] ;
wire \COUNT_reg_n_0_[3] ;
wire \COUNT_reg_n_0_[4] ;
wire \COUNT_reg_n_0_[5] ;
wire \COUNT_reg_n_0_[6] ;
wire \COUNT_reg_n_0_[7] ;
wire ETH_CLK_OBUF;
wire LED_B_PWM_OBUF;
wire OUT_BIT_i_10__1_n_0;
wire OUT_BIT_i_1__1_n_0;
wire OUT_BIT_i_3__1_n_0;
wire OUT_BIT_i_4__1_n_0;
wire OUT_BIT_i_5__1_n_0;
wire OUT_BIT_i_6__1_n_0;
wire OUT_BIT_i_7__1_n_0;
wire OUT_BIT_i_8__1_n_0;
wire OUT_BIT_i_9__1_n_0;
wire [9:0]TIMER;
wire \TIMER[4]_i_2__1_n_0 ;
wire \TIMER[9]_i_2__1_n_0 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire p_0_in;
wire [2:0]NLW_OUT_BIT_reg_i_2__1_CO_UNCONNECTED;
wire [3:0]NLW_OUT_BIT_reg_i_2__1_O_UNCONNECTED;
LUT6 #(
.INIT(64'h2333333333333333))
\COUNT[0]_i_1__3
(.I0(\COUNT[7]_i_3__1_n_0 ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT_reg_n_0_[4] ),
.I4(\COUNT_reg_n_0_[7] ),
.I5(\COUNT_reg_n_0_[6] ),
.O(\COUNT[0]_i_1__3_n_0 ));
LUT5 #(
.INIT(32'h00FFBF00))
\COUNT[1]_i_1__3
(.I0(\COUNT[1]_i_2__1_n_0 ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(\COUNT_reg_n_0_[2] ),
.I3(\COUNT_reg_n_0_[1] ),
.I4(\COUNT_reg_n_0_[0] ),
.O(\COUNT[1]_i_1__3_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\COUNT[1]_i_2__1
(.I0(\COUNT_reg_n_0_[5] ),
.I1(\COUNT_reg_n_0_[4] ),
.I2(\COUNT_reg_n_0_[7] ),
.I3(\COUNT_reg_n_0_[6] ),
.O(\COUNT[1]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hFFC011C0))
\COUNT[2]_i_1__2
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[1] ),
.I3(\COUNT_reg_n_0_[2] ),
.I4(\COUNT[3]_i_2__1_n_0 ),
.O(\COUNT[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hFF805580))
\COUNT[3]_i_1__1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[1] ),
.I2(\COUNT_reg_n_0_[0] ),
.I3(\COUNT_reg_n_0_[3] ),
.I4(\COUNT[3]_i_2__1_n_0 ),
.O(\COUNT[3]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h15555555FFFFFFFF))
\COUNT[3]_i_2__1
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT_reg_n_0_[4] ),
.I3(\COUNT_reg_n_0_[7] ),
.I4(\COUNT_reg_n_0_[6] ),
.I5(\COUNT_reg_n_0_[1] ),
.O(\COUNT[3]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'hFF00FF7F00FF0000))
\COUNT[4]_i_1__1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[6] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT[7]_i_3__1_n_0 ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[4]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAABFFFFF55000000))
\COUNT[5]_i_1__1
(.I0(\COUNT[7]_i_3__1_n_0 ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT_reg_n_0_[0] ),
.I4(\COUNT_reg_n_0_[4] ),
.I5(\COUNT_reg_n_0_[5] ),
.O(\COUNT[5]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hF01CF0F0F0F0F0F0))
\COUNT[6]_i_1__1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT[7]_i_3__1_n_0 ),
.I4(\COUNT_reg_n_0_[5] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[6]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\COUNT[7]_i_1__1
(.I0(\TIMER_reg_n_0_[9] ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.I5(\TIMER[9]_i_2__1_n_0 ),
.O(\COUNT[7]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hF7FFF7FF08000000))
\COUNT[7]_i_2__1
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT[7]_i_3__1_n_0 ),
.I3(\COUNT_reg_n_0_[6] ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[7] ),
.O(\COUNT[7]_i_2__1_n_0 ));
LUT3 #(
.INIT(8'h7F))
\COUNT[7]_i_3__1
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[2] ),
.I2(\COUNT_reg_n_0_[1] ),
.O(\COUNT[7]_i_3__1_n_0 ));
FDRE #(
.INIT(1'b0))
\COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[0]_i_1__3_n_0 ),
.Q(\COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[1]_i_1__3_n_0 ),
.Q(\COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[2]_i_1__2_n_0 ),
.Q(\COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[3]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[4]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[5]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[6]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[7]_i_2__1_n_0 ),
.Q(\COUNT_reg_n_0_[7] ),
.R(1'b0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_10__1
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_10__1_n_0));
LUT1 #(
.INIT(2'h1))
OUT_BIT_i_1__1
(.I0(p_0_in),
.O(OUT_BIT_i_1__1_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_3__1
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_3__1_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_4__1
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_4__1_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_5__1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_5__1_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_6__1
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_6__1_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_7__1
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_7__1_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_8__1
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_8__1_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_9__1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_9__1_n_0));
FDRE OUT_BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(OUT_BIT_i_1__1_n_0),
.Q(LED_B_PWM_OBUF),
.R(1'b0));
CARRY4 OUT_BIT_reg_i_2__1
(.CI(1'b0),
.CO({p_0_in,NLW_OUT_BIT_reg_i_2__1_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({OUT_BIT_i_3__1_n_0,OUT_BIT_i_4__1_n_0,OUT_BIT_i_5__1_n_0,OUT_BIT_i_6__1_n_0}),
.O(NLW_OUT_BIT_reg_i_2__1_O_UNCONNECTED[3:0]),
.S({OUT_BIT_i_7__1_n_0,OUT_BIT_i_8__1_n_0,OUT_BIT_i_9__1_n_0,OUT_BIT_i_10__1_n_0}));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT1 #(
.INIT(2'h1))
\TIMER[0]_i_1__2
(.I0(\TIMER_reg_n_0_[0] ),
.O(TIMER[0]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT2 #(
.INIT(4'h9))
\TIMER[1]_i_1__1
(.I0(\TIMER_reg_n_0_[1] ),
.I1(\TIMER_reg_n_0_[0] ),
.O(TIMER[1]));
LUT3 #(
.INIT(8'hA9))
\TIMER[2]_i_1__2
(.I0(\TIMER_reg_n_0_[2] ),
.I1(\TIMER_reg_n_0_[0] ),
.I2(\TIMER_reg_n_0_[1] ),
.O(TIMER[2]));
LUT6 #(
.INIT(64'hF0F0F0F0F0F0F00E))
\TIMER[3]_i_1__1
(.I0(\TIMER[4]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[4] ),
.I2(\TIMER_reg_n_0_[3] ),
.I3(\TIMER_reg_n_0_[1] ),
.I4(\TIMER_reg_n_0_[0] ),
.I5(\TIMER_reg_n_0_[2] ),
.O(TIMER[3]));
LUT6 #(
.INIT(64'hFFFE0001FFFE0000))
\TIMER[4]_i_1__1
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.I5(\TIMER[4]_i_2__1_n_0 ),
.O(TIMER[4]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[4]_i_2__1
(.I0(\TIMER_reg_n_0_[8] ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.I4(\TIMER_reg_n_0_[9] ),
.O(\TIMER[4]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\TIMER[5]_i_1__1
(.I0(\TIMER_reg_n_0_[5] ),
.I1(\TIMER_reg_n_0_[3] ),
.I2(\TIMER_reg_n_0_[1] ),
.I3(\TIMER_reg_n_0_[0] ),
.I4(\TIMER_reg_n_0_[2] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(TIMER[5]));
LUT3 #(
.INIT(8'hE1))
\TIMER[6]_i_1__2
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[5] ),
.I2(\TIMER_reg_n_0_[6] ),
.O(TIMER[6]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT4 #(
.INIT(16'hFE01))
\TIMER[7]_i_1__2
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.O(TIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hFFFE0001))
\TIMER[8]_i_1__2
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.O(TIMER[8]));
LUT6 #(
.INIT(64'hFFFFFFFE00000001))
\TIMER[9]_i_1__1
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[6] ),
.I3(\TIMER_reg_n_0_[5] ),
.I4(\TIMER_reg_n_0_[7] ),
.I5(\TIMER_reg_n_0_[9] ),
.O(TIMER[9]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[9]_i_2__1
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.O(\TIMER[9]_i_2__1_n_0 ));
FDRE #(
.INIT(1'b1))
\TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[0]),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[1]),
.Q(\TIMER_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[2]),
.Q(\TIMER_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[3]),
.Q(\TIMER_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[4]),
.Q(\TIMER_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[5]),
.Q(\TIMER_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[6]),
.Q(\TIMER_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[7]),
.Q(\TIMER_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[8]),
.Q(\TIMER_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[9]),
.Q(\TIMER_reg_n_0_[9] ),
.R(1'b0));
endmodule
module RAM32M_UNIQ_BASE_
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD10
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD11
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD12
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD13
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD14
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD4
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD5
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD6
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD7
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD8
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD9
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
module VIDEO_TIME_GEN
(\PIXCOL_DEL_reg[0] ,
\PIXCOL_DEL_reg[1] ,
\PIXCOL_DEL_reg[2] ,
ADDRBWRADDR,
\PIXROW_DEL_reg[0] ,
\PIXROW_DEL_reg[1] ,
D,
HSYNCH_DEL_reg,
VSYNCH_DEL_reg,
BLANK,
ETH_CLK_OBUF,
INTERNAL_RST_reg);
output \PIXCOL_DEL_reg[0] ;
output \PIXCOL_DEL_reg[1] ;
output \PIXCOL_DEL_reg[2] ;
output [12:0]ADDRBWRADDR;
output \PIXROW_DEL_reg[0] ;
output \PIXROW_DEL_reg[1] ;
output [0:0]D;
output HSYNCH_DEL_reg;
output VSYNCH_DEL_reg;
output BLANK;
input ETH_CLK_OBUF;
input INTERNAL_RST_reg;
wire [12:0]ADDRBWRADDR;
wire BLANK;
wire \COL_ADDRESS[0]_i_1_n_0 ;
wire \COL_ADDRESS[1]_i_1_n_0 ;
wire \COL_ADDRESS[2]_i_1_n_0 ;
wire \COL_ADDRESS[3]_i_1_n_0 ;
wire \COL_ADDRESS[4]_i_1_n_0 ;
wire \COL_ADDRESS[5]_i_1_n_0 ;
wire \COL_ADDRESS[6]_i_1_n_0 ;
wire \COL_ADDRESS[6]_i_2_n_0 ;
wire \COL_ADDRESS[6]_i_3_n_0 ;
wire \COL_ADDRESS_reg_n_0_[1] ;
wire \COL_ADDRESS_reg_n_0_[2] ;
wire \COL_ADDRESS_reg_n_0_[3] ;
wire \COL_ADDRESS_reg_n_0_[4] ;
wire \COL_ADDRESS_reg_n_0_[5] ;
wire \COL_ADDRESS_reg_n_0_[6] ;
wire [0:0]D;
wire ETH_CLK_OBUF;
wire HBLANK_i_1_n_0;
wire HBLANK_i_2_n_0;
wire HBLANK_i_3_n_0;
wire HBLANK_i_4_n_0;
wire HBLANK_i_5_n_0;
wire HBLANK_i_6_n_0;
wire HBLANK_reg_n_0;
wire HSYNCH_DEL_reg;
wire [10:0]HTIMER;
wire \HTIMER[0]_i_2_n_0 ;
wire \HTIMER[0]_i_3_n_0 ;
wire \HTIMER[10]_i_2_n_0 ;
wire \HTIMER[10]_i_3_n_0 ;
wire \HTIMER[10]_i_4_n_0 ;
wire \HTIMER[2]_i_1_n_0 ;
wire \HTIMER[4]_i_2_n_0 ;
wire \HTIMER[5]_i_1_n_0 ;
wire \HTIMER[6]_i_1_n_0 ;
wire \HTIMER[9]_i_2_n_0 ;
wire INTERNAL_RST_reg;
wire INTHSYNCH_i_1_n_0;
wire INTVSYNCH2_out;
wire INTVSYNCH_i_1_n_0;
wire INTVSYNCH_i_3_n_0;
wire MEMORY_reg_0_i_11_n_0;
wire MEMORY_reg_0_i_12_n_0;
wire MEMORY_reg_0_i_13_n_0;
wire MEMORY_reg_0_i_14_n_0;
wire MEMORY_reg_0_i_15_n_0;
wire MEMORY_reg_0_i_16_n_0;
wire MEMORY_reg_0_i_2_n_0;
wire MEMORY_reg_0_i_3_n_0;
wire \PIXCOL_DEL_reg[0] ;
wire \PIXCOL_DEL_reg[1] ;
wire \PIXCOL_DEL_reg[2] ;
wire \PIXROW_DEL_reg[0] ;
wire \PIXROW_DEL_reg[1] ;
wire \PIX_COL_ADDRESS[0]_i_1_n_0 ;
wire \PIX_COL_ADDRESS[1]_i_1_n_0 ;
wire \PIX_COL_ADDRESS[2]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[0]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[1]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[2]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[2]_i_2_n_0 ;
wire \PIX_ROW_ADDRESS[2]_i_3_n_0 ;
wire [12:1]ROW_ADDRESS;
wire \ROW_ADDRESS[12]_i_1_n_0 ;
wire \ROW_ADDRESS[12]_i_3_n_0 ;
wire \ROW_ADDRESS[12]_i_4_n_0 ;
wire \ROW_ADDRESS[4]_i_5_n_0 ;
wire \ROW_ADDRESS[8]_i_5_n_0 ;
wire \ROW_ADDRESS[8]_i_6_n_0 ;
wire [12:1]ROW_ADDRESS_0;
wire \ROW_ADDRESS_reg[12]_i_5_n_4 ;
wire \ROW_ADDRESS_reg[12]_i_5_n_5 ;
wire \ROW_ADDRESS_reg[12]_i_5_n_6 ;
wire \ROW_ADDRESS_reg[12]_i_5_n_7 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_0 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_4 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_5 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_6 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_7 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_0 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_4 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_5 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_6 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_7 ;
wire VBLANK_i_1_n_0;
wire VBLANK_i_2_n_0;
wire VBLANK_i_3_n_0;
wire VBLANK_i_4_n_0;
wire VBLANK_i_5_n_0;
wire VBLANK_i_6_n_0;
wire VBLANK_i_7_n_0;
wire VBLANK_reg_n_0;
wire VSYNCH_DEL_reg;
wire [9:0]VTIMER;
wire \VTIMER[0]_i_1_n_0 ;
wire \VTIMER[2]_i_2_n_0 ;
wire \VTIMER[2]_i_3_n_0 ;
wire \VTIMER[5]_i_1_n_0 ;
wire \VTIMER[9]_i_2_n_0 ;
wire \VTIMER[9]_i_3_n_0 ;
wire \VTIMER[9]_i_4_n_0 ;
wire \VTIMER[9]_i_5_n_0 ;
wire [9:1]VTIMER_1;
wire VTIMER_EN;
wire VTIMER_EN_i_1_n_0;
wire [10:0]sel0;
wire [3:0]NLW_MEMORY_reg_0_i_1_CO_UNCONNECTED;
wire [2:0]NLW_MEMORY_reg_0_i_2_CO_UNCONNECTED;
wire [2:0]NLW_MEMORY_reg_0_i_3_CO_UNCONNECTED;
wire [0:0]NLW_MEMORY_reg_0_i_3_O_UNCONNECTED;
wire [3:0]\NLW_ROW_ADDRESS_reg[12]_i_5_CO_UNCONNECTED ;
wire [2:0]\NLW_ROW_ADDRESS_reg[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_ROW_ADDRESS_reg[8]_i_2_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'hE))
BLANK_DEL_i_1
(.I0(VBLANK_reg_n_0),
.I1(HBLANK_reg_n_0),
.O(BLANK));
LUT1 #(
.INIT(2'h1))
\COL_ADDRESS[0]_i_1
(.I0(ADDRBWRADDR[0]),
.O(\COL_ADDRESS[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\COL_ADDRESS[1]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[1] ),
.I1(ADDRBWRADDR[0]),
.O(\COL_ADDRESS[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF00000000EFFF))
\COL_ADDRESS[2]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[4] ),
.I1(\COL_ADDRESS_reg_n_0_[3] ),
.I2(\COL_ADDRESS_reg_n_0_[6] ),
.I3(\COL_ADDRESS_reg_n_0_[5] ),
.I4(\COL_ADDRESS[6]_i_3_n_0 ),
.I5(\COL_ADDRESS_reg_n_0_[2] ),
.O(\COL_ADDRESS[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h6AAA))
\COL_ADDRESS[3]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[3] ),
.I1(\COL_ADDRESS_reg_n_0_[1] ),
.I2(ADDRBWRADDR[0]),
.I3(\COL_ADDRESS_reg_n_0_[2] ),
.O(\COL_ADDRESS[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\COL_ADDRESS[4]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[4] ),
.I1(\COL_ADDRESS_reg_n_0_[2] ),
.I2(ADDRBWRADDR[0]),
.I3(\COL_ADDRESS_reg_n_0_[1] ),
.I4(\COL_ADDRESS_reg_n_0_[3] ),
.O(\COL_ADDRESS[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF3FFFFD00C00000))
\COL_ADDRESS[5]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[6] ),
.I1(\COL_ADDRESS_reg_n_0_[4] ),
.I2(\COL_ADDRESS_reg_n_0_[2] ),
.I3(\COL_ADDRESS[6]_i_3_n_0 ),
.I4(\COL_ADDRESS_reg_n_0_[3] ),
.I5(\COL_ADDRESS_reg_n_0_[5] ),
.O(\COL_ADDRESS[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000080))
\COL_ADDRESS[6]_i_1
(.I0(\PIXCOL_DEL_reg[0] ),
.I1(\PIXCOL_DEL_reg[1] ),
.I2(\PIXCOL_DEL_reg[2] ),
.I3(HBLANK_reg_n_0),
.I4(VBLANK_reg_n_0),
.O(\COL_ADDRESS[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hDFFEFFFF20000000))
\COL_ADDRESS[6]_i_2
(.I0(\COL_ADDRESS_reg_n_0_[3] ),
.I1(\COL_ADDRESS[6]_i_3_n_0 ),
.I2(\COL_ADDRESS_reg_n_0_[2] ),
.I3(\COL_ADDRESS_reg_n_0_[4] ),
.I4(\COL_ADDRESS_reg_n_0_[5] ),
.I5(\COL_ADDRESS_reg_n_0_[6] ),
.O(\COL_ADDRESS[6]_i_2_n_0 ));
LUT2 #(
.INIT(4'h7))
\COL_ADDRESS[6]_i_3
(.I0(\COL_ADDRESS_reg_n_0_[1] ),
.I1(ADDRBWRADDR[0]),
.O(\COL_ADDRESS[6]_i_3_n_0 ));
FDRE \COL_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[0]_i_1_n_0 ),
.Q(ADDRBWRADDR[0]),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[1]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[2]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[3]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[4]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[5]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[5] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[6]_i_2_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[6] ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFFFFFFFFF70000))
HBLANK_i_1
(.I0(HBLANK_i_2_n_0),
.I1(sel0[7]),
.I2(sel0[8]),
.I3(sel0[6]),
.I4(HBLANK_reg_n_0),
.I5(HBLANK_i_3_n_0),
.O(HBLANK_i_1_n_0));
LUT6 #(
.INIT(64'h0000000010000000))
HBLANK_i_2
(.I0(sel0[9]),
.I1(sel0[10]),
.I2(sel0[5]),
.I3(sel0[4]),
.I4(sel0[3]),
.I5(HBLANK_i_4_n_0),
.O(HBLANK_i_2_n_0));
LUT6 #(
.INIT(64'hAAAAABAAAAAAAAAA))
HBLANK_i_3
(.I0(INTERNAL_RST_reg),
.I1(HBLANK_i_5_n_0),
.I2(sel0[0]),
.I3(sel0[3]),
.I4(HBLANK_i_6_n_0),
.I5(\HTIMER[0]_i_3_n_0 ),
.O(HBLANK_i_3_n_0));
LUT3 #(
.INIT(8'hFE))
HBLANK_i_4
(.I0(sel0[2]),
.I1(sel0[1]),
.I2(sel0[0]),
.O(HBLANK_i_4_n_0));
LUT3 #(
.INIT(8'hBF))
HBLANK_i_5
(.I0(sel0[10]),
.I1(sel0[8]),
.I2(sel0[9]),
.O(HBLANK_i_5_n_0));
LUT2 #(
.INIT(4'h7))
HBLANK_i_6
(.I0(sel0[7]),
.I1(sel0[6]),
.O(HBLANK_i_6_n_0));
FDRE HBLANK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HBLANK_i_1_n_0),
.Q(HBLANK_reg_n_0),
.R(1'b0));
LUT5 #(
.INIT(32'h0000FDFF))
\HTIMER[0]_i_1
(.I0(\HTIMER[0]_i_2_n_0 ),
.I1(sel0[6]),
.I2(sel0[3]),
.I3(\HTIMER[0]_i_3_n_0 ),
.I4(sel0[0]),
.O(HTIMER[0]));
LUT4 #(
.INIT(16'h0010))
\HTIMER[0]_i_2
(.I0(sel0[8]),
.I1(sel0[7]),
.I2(sel0[10]),
.I3(sel0[9]),
.O(\HTIMER[0]_i_2_n_0 ));
LUT4 #(
.INIT(16'h0010))
\HTIMER[0]_i_3
(.I0(sel0[2]),
.I1(sel0[1]),
.I2(sel0[4]),
.I3(sel0[5]),
.O(\HTIMER[0]_i_3_n_0 ));
LUT5 #(
.INIT(32'h3AAAAAAA))
\HTIMER[10]_i_1
(.I0(\HTIMER[10]_i_2_n_0 ),
.I1(sel0[10]),
.I2(sel0[8]),
.I3(sel0[9]),
.I4(\HTIMER[10]_i_3_n_0 ),
.O(HTIMER[10]));
LUT6 #(
.INIT(64'hAAAAAAA8AAAAAAAA))
\HTIMER[10]_i_2
(.I0(sel0[10]),
.I1(sel0[8]),
.I2(sel0[6]),
.I3(sel0[9]),
.I4(sel0[7]),
.I5(\HTIMER[10]_i_4_n_0 ),
.O(\HTIMER[10]_i_2_n_0 ));
LUT3 #(
.INIT(8'h40))
\HTIMER[10]_i_3
(.I0(\HTIMER[9]_i_2_n_0 ),
.I1(sel0[6]),
.I2(sel0[7]),
.O(\HTIMER[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000010))
\HTIMER[10]_i_4
(.I0(sel0[5]),
.I1(sel0[3]),
.I2(sel0[4]),
.I3(sel0[2]),
.I4(sel0[1]),
.I5(sel0[0]),
.O(\HTIMER[10]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\HTIMER[1]_i_1
(.I0(sel0[0]),
.I1(sel0[1]),
.O(HTIMER[1]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h6A))
\HTIMER[2]_i_1
(.I0(sel0[2]),
.I1(sel0[1]),
.I2(sel0[0]),
.O(\HTIMER[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h6AAA))
\HTIMER[3]_i_1
(.I0(sel0[3]),
.I1(sel0[1]),
.I2(sel0[0]),
.I3(sel0[2]),
.O(HTIMER[3]));
LUT6 #(
.INIT(64'h1555555540000000))
\HTIMER[4]_i_1
(.I0(\HTIMER[4]_i_2_n_0 ),
.I1(sel0[2]),
.I2(sel0[0]),
.I3(sel0[1]),
.I4(sel0[3]),
.I5(sel0[4]),
.O(HTIMER[4]));
LUT6 #(
.INIT(64'h0000000000000200))
\HTIMER[4]_i_2
(.I0(\HTIMER[10]_i_4_n_0 ),
.I1(sel0[8]),
.I2(sel0[7]),
.I3(sel0[10]),
.I4(sel0[9]),
.I5(sel0[6]),
.O(\HTIMER[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\HTIMER[5]_i_1
(.I0(sel0[5]),
.I1(sel0[4]),
.I2(sel0[3]),
.I3(sel0[1]),
.I4(sel0[0]),
.I5(sel0[2]),
.O(\HTIMER[5]_i_1_n_0 ));
LUT2 #(
.INIT(4'h9))
\HTIMER[6]_i_1
(.I0(sel0[6]),
.I1(\HTIMER[9]_i_2_n_0 ),
.O(\HTIMER[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'h9A))
\HTIMER[7]_i_1
(.I0(sel0[7]),
.I1(\HTIMER[9]_i_2_n_0 ),
.I2(sel0[6]),
.O(HTIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hAA6A))
\HTIMER[8]_i_1
(.I0(sel0[8]),
.I1(sel0[7]),
.I2(sel0[6]),
.I3(\HTIMER[9]_i_2_n_0 ),
.O(HTIMER[8]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h9AAAAAAA))
\HTIMER[9]_i_1
(.I0(sel0[9]),
.I1(\HTIMER[9]_i_2_n_0 ),
.I2(sel0[6]),
.I3(sel0[7]),
.I4(sel0[8]),
.O(HTIMER[9]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\HTIMER[9]_i_2
(.I0(sel0[4]),
.I1(sel0[3]),
.I2(sel0[1]),
.I3(sel0[0]),
.I4(sel0[2]),
.I5(sel0[5]),
.O(\HTIMER[9]_i_2_n_0 ));
FDRE \HTIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[0]),
.Q(sel0[0]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[10]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[10]),
.Q(sel0[10]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[1]),
.Q(sel0[1]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\HTIMER[2]_i_1_n_0 ),
.Q(sel0[2]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[3]),
.Q(sel0[3]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[4]),
.Q(sel0[4]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\HTIMER[5]_i_1_n_0 ),
.Q(sel0[5]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\HTIMER[6]_i_1_n_0 ),
.Q(sel0[6]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[7]),
.Q(sel0[7]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[8]),
.Q(sel0[8]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[9]),
.Q(sel0[9]),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h00000000AAAEAAAA))
INTHSYNCH_i_1
(.I0(HSYNCH_DEL_reg),
.I1(HBLANK_i_2_n_0),
.I2(sel0[7]),
.I3(sel0[8]),
.I4(sel0[6]),
.I5(VTIMER_EN_i_1_n_0),
.O(INTHSYNCH_i_1_n_0));
FDRE INTHSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(INTHSYNCH_i_1_n_0),
.Q(HSYNCH_DEL_reg),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000EEEE0EEE))
INTVSYNCH_i_1
(.I0(VSYNCH_DEL_reg),
.I1(INTVSYNCH2_out),
.I2(\VTIMER[2]_i_2_n_0 ),
.I3(VTIMER_EN),
.I4(VTIMER[0]),
.I5(INTERNAL_RST_reg),
.O(INTVSYNCH_i_1_n_0));
LUT6 #(
.INIT(64'h0000000000000002))
INTVSYNCH_i_2
(.I0(VBLANK_i_2_n_0),
.I1(VTIMER[0]),
.I2(INTVSYNCH_i_3_n_0),
.I3(VTIMER[3]),
.I4(VTIMER[5]),
.I5(VTIMER[4]),
.O(INTVSYNCH2_out));
LUT2 #(
.INIT(4'h7))
INTVSYNCH_i_3
(.I0(VTIMER[1]),
.I1(VTIMER[2]),
.O(INTVSYNCH_i_3_n_0));
FDRE INTVSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(INTVSYNCH_i_1_n_0),
.Q(VSYNCH_DEL_reg),
.R(1'b0));
CARRY4 MEMORY_reg_0_i_1
(.CI(MEMORY_reg_0_i_2_n_0),
.CO(NLW_MEMORY_reg_0_i_1_CO_UNCONNECTED[3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(ADDRBWRADDR[12:9]),
.S(ROW_ADDRESS[12:9]));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_11
(.I0(ROW_ADDRESS[6]),
.I1(\COL_ADDRESS_reg_n_0_[6] ),
.O(MEMORY_reg_0_i_11_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_12
(.I0(ROW_ADDRESS[5]),
.I1(\COL_ADDRESS_reg_n_0_[5] ),
.O(MEMORY_reg_0_i_12_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_13
(.I0(ROW_ADDRESS[4]),
.I1(\COL_ADDRESS_reg_n_0_[4] ),
.O(MEMORY_reg_0_i_13_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_14
(.I0(ROW_ADDRESS[3]),
.I1(\COL_ADDRESS_reg_n_0_[3] ),
.O(MEMORY_reg_0_i_14_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_15
(.I0(ROW_ADDRESS[2]),
.I1(\COL_ADDRESS_reg_n_0_[2] ),
.O(MEMORY_reg_0_i_15_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_16
(.I0(ROW_ADDRESS[1]),
.I1(\COL_ADDRESS_reg_n_0_[1] ),
.O(MEMORY_reg_0_i_16_n_0));
CARRY4 MEMORY_reg_0_i_2
(.CI(MEMORY_reg_0_i_3_n_0),
.CO({MEMORY_reg_0_i_2_n_0,NLW_MEMORY_reg_0_i_2_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,ROW_ADDRESS[6:5]}),
.O(ADDRBWRADDR[8:5]),
.S({ROW_ADDRESS[8:7],MEMORY_reg_0_i_11_n_0,MEMORY_reg_0_i_12_n_0}));
CARRY4 MEMORY_reg_0_i_3
(.CI(1'b0),
.CO({MEMORY_reg_0_i_3_n_0,NLW_MEMORY_reg_0_i_3_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(ROW_ADDRESS[4:1]),
.O({ADDRBWRADDR[4:2],NLW_MEMORY_reg_0_i_3_O_UNCONNECTED[0]}),
.S({MEMORY_reg_0_i_13_n_0,MEMORY_reg_0_i_14_n_0,MEMORY_reg_0_i_15_n_0,MEMORY_reg_0_i_16_n_0}));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_4
(.I0(ROW_ADDRESS[1]),
.I1(\COL_ADDRESS_reg_n_0_[1] ),
.O(ADDRBWRADDR[1]));
LUT3 #(
.INIT(8'hE1))
\PIX_COL_ADDRESS[0]_i_1
(.I0(VBLANK_reg_n_0),
.I1(HBLANK_reg_n_0),
.I2(\PIXCOL_DEL_reg[0] ),
.O(\PIX_COL_ADDRESS[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hFD02))
\PIX_COL_ADDRESS[1]_i_1
(.I0(\PIXCOL_DEL_reg[0] ),
.I1(HBLANK_reg_n_0),
.I2(VBLANK_reg_n_0),
.I3(\PIXCOL_DEL_reg[1] ),
.O(\PIX_COL_ADDRESS[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hFFF70008))
\PIX_COL_ADDRESS[2]_i_1
(.I0(\PIXCOL_DEL_reg[0] ),
.I1(\PIXCOL_DEL_reg[1] ),
.I2(HBLANK_reg_n_0),
.I3(VBLANK_reg_n_0),
.I4(\PIXCOL_DEL_reg[2] ),
.O(\PIX_COL_ADDRESS[2]_i_1_n_0 ));
FDRE \PIX_COL_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_COL_ADDRESS[0]_i_1_n_0 ),
.Q(\PIXCOL_DEL_reg[0] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_COL_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_COL_ADDRESS[1]_i_1_n_0 ),
.Q(\PIXCOL_DEL_reg[1] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_COL_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_COL_ADDRESS[2]_i_1_n_0 ),
.Q(\PIXCOL_DEL_reg[2] ),
.R(INTERNAL_RST_reg));
LUT2 #(
.INIT(4'h6))
\PIX_ROW_ADDRESS[0]_i_1
(.I0(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I1(\PIXROW_DEL_reg[0] ),
.O(\PIX_ROW_ADDRESS[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h78))
\PIX_ROW_ADDRESS[1]_i_1
(.I0(\PIXROW_DEL_reg[0] ),
.I1(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I2(\PIXROW_DEL_reg[1] ),
.O(\PIX_ROW_ADDRESS[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\PIX_ROW_ADDRESS[2]_i_1
(.I0(\PIXROW_DEL_reg[0] ),
.I1(\PIXROW_DEL_reg[1] ),
.I2(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I3(D),
.O(\PIX_ROW_ADDRESS[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000010000000))
\PIX_ROW_ADDRESS[2]_i_2
(.I0(VBLANK_reg_n_0),
.I1(HBLANK_reg_n_0),
.I2(\PIXCOL_DEL_reg[2] ),
.I3(\PIXCOL_DEL_reg[1] ),
.I4(\PIXCOL_DEL_reg[0] ),
.I5(\PIX_ROW_ADDRESS[2]_i_3_n_0 ),
.O(\PIX_ROW_ADDRESS[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF7))
\PIX_ROW_ADDRESS[2]_i_3
(.I0(\COL_ADDRESS_reg_n_0_[5] ),
.I1(\COL_ADDRESS_reg_n_0_[6] ),
.I2(\COL_ADDRESS_reg_n_0_[2] ),
.I3(\COL_ADDRESS_reg_n_0_[3] ),
.I4(\COL_ADDRESS_reg_n_0_[4] ),
.I5(\COL_ADDRESS[6]_i_3_n_0 ),
.O(\PIX_ROW_ADDRESS[2]_i_3_n_0 ));
FDRE \PIX_ROW_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_ROW_ADDRESS[0]_i_1_n_0 ),
.Q(\PIXROW_DEL_reg[0] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_ROW_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_ROW_ADDRESS[1]_i_1_n_0 ),
.Q(\PIXROW_DEL_reg[1] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_ROW_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_ROW_ADDRESS[2]_i_1_n_0 ),
.Q(D),
.R(INTERNAL_RST_reg));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[10]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_6 ),
.O(ROW_ADDRESS_0[10]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[11]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_5 ),
.O(ROW_ADDRESS_0[11]));
LUT4 #(
.INIT(16'h8000))
\ROW_ADDRESS[12]_i_1
(.I0(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I1(D),
.I2(\PIXROW_DEL_reg[0] ),
.I3(\PIXROW_DEL_reg[1] ),
.O(\ROW_ADDRESS[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[12]_i_2
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_4 ),
.O(ROW_ADDRESS_0[12]));
LUT6 #(
.INIT(64'h0040000000000000))
\ROW_ADDRESS[12]_i_3
(.I0(ROW_ADDRESS[9]),
.I1(ROW_ADDRESS[10]),
.I2(ROW_ADDRESS[7]),
.I3(ROW_ADDRESS[8]),
.I4(ROW_ADDRESS[11]),
.I5(ROW_ADDRESS[12]),
.O(\ROW_ADDRESS[12]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000080))
\ROW_ADDRESS[12]_i_4
(.I0(ROW_ADDRESS[6]),
.I1(ROW_ADDRESS[5]),
.I2(ROW_ADDRESS[3]),
.I3(ROW_ADDRESS[4]),
.I4(ROW_ADDRESS[1]),
.I5(ROW_ADDRESS[2]),
.O(\ROW_ADDRESS[12]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[1]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_7 ),
.O(ROW_ADDRESS_0[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[2]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_6 ),
.O(ROW_ADDRESS_0[2]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[3]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_5 ),
.O(ROW_ADDRESS_0[3]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[4]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_4 ),
.O(ROW_ADDRESS_0[4]));
LUT1 #(
.INIT(2'h1))
\ROW_ADDRESS[4]_i_5
(.I0(ROW_ADDRESS[2]),
.O(\ROW_ADDRESS[4]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[5]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_7 ),
.O(ROW_ADDRESS_0[5]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[6]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_6 ),
.O(ROW_ADDRESS_0[6]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[7]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_5 ),
.O(ROW_ADDRESS_0[7]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[8]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_4 ),
.O(ROW_ADDRESS_0[8]));
LUT1 #(
.INIT(2'h1))
\ROW_ADDRESS[8]_i_5
(.I0(ROW_ADDRESS[6]),
.O(\ROW_ADDRESS[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\ROW_ADDRESS[8]_i_6
(.I0(ROW_ADDRESS[5]),
.O(\ROW_ADDRESS[8]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[9]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_7 ),
.O(ROW_ADDRESS_0[9]));
FDRE \ROW_ADDRESS_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[10]),
.Q(ROW_ADDRESS[10]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[11]),
.Q(ROW_ADDRESS[11]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[12]),
.Q(ROW_ADDRESS[12]),
.R(INTERNAL_RST_reg));
CARRY4 \ROW_ADDRESS_reg[12]_i_5
(.CI(\ROW_ADDRESS_reg[8]_i_2_n_0 ),
.CO(\NLW_ROW_ADDRESS_reg[12]_i_5_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\ROW_ADDRESS_reg[12]_i_5_n_4 ,\ROW_ADDRESS_reg[12]_i_5_n_5 ,\ROW_ADDRESS_reg[12]_i_5_n_6 ,\ROW_ADDRESS_reg[12]_i_5_n_7 }),
.S(ROW_ADDRESS[12:9]));
FDRE \ROW_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[1]),
.Q(ROW_ADDRESS[1]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[2]),
.Q(ROW_ADDRESS[2]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[3]),
.Q(ROW_ADDRESS[3]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[4]),
.Q(ROW_ADDRESS[4]),
.R(INTERNAL_RST_reg));
CARRY4 \ROW_ADDRESS_reg[4]_i_2
(.CI(1'b0),
.CO({\ROW_ADDRESS_reg[4]_i_2_n_0 ,\NLW_ROW_ADDRESS_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,ROW_ADDRESS[2],1'b0}),
.O({\ROW_ADDRESS_reg[4]_i_2_n_4 ,\ROW_ADDRESS_reg[4]_i_2_n_5 ,\ROW_ADDRESS_reg[4]_i_2_n_6 ,\ROW_ADDRESS_reg[4]_i_2_n_7 }),
.S({ROW_ADDRESS[4:3],\ROW_ADDRESS[4]_i_5_n_0 ,ROW_ADDRESS[1]}));
FDRE \ROW_ADDRESS_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[5]),
.Q(ROW_ADDRESS[5]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[6]),
.Q(ROW_ADDRESS[6]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[7]),
.Q(ROW_ADDRESS[7]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[8]),
.Q(ROW_ADDRESS[8]),
.R(INTERNAL_RST_reg));
CARRY4 \ROW_ADDRESS_reg[8]_i_2
(.CI(\ROW_ADDRESS_reg[4]_i_2_n_0 ),
.CO({\ROW_ADDRESS_reg[8]_i_2_n_0 ,\NLW_ROW_ADDRESS_reg[8]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,ROW_ADDRESS[6:5]}),
.O({\ROW_ADDRESS_reg[8]_i_2_n_4 ,\ROW_ADDRESS_reg[8]_i_2_n_5 ,\ROW_ADDRESS_reg[8]_i_2_n_6 ,\ROW_ADDRESS_reg[8]_i_2_n_7 }),
.S({ROW_ADDRESS[8:7],\ROW_ADDRESS[8]_i_5_n_0 ,\ROW_ADDRESS[8]_i_6_n_0 }));
FDRE \ROW_ADDRESS_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[9]),
.Q(ROW_ADDRESS[9]),
.R(INTERNAL_RST_reg));
LUT4 #(
.INIT(16'hFFD0))
VBLANK_i_1
(.I0(VBLANK_i_2_n_0),
.I1(VBLANK_i_3_n_0),
.I2(VBLANK_reg_n_0),
.I3(VBLANK_i_4_n_0),
.O(VBLANK_i_1_n_0));
LUT5 #(
.INIT(32'h00000004))
VBLANK_i_2
(.I0(VTIMER[7]),
.I1(VTIMER_EN),
.I2(VTIMER[8]),
.I3(VTIMER[9]),
.I4(VTIMER[6]),
.O(VBLANK_i_2_n_0));
LUT6 #(
.INIT(64'hFFFFFBFFFFFFFFFF))
VBLANK_i_3
(.I0(VTIMER[2]),
.I1(VTIMER[0]),
.I2(VTIMER[1]),
.I3(VTIMER[5]),
.I4(VTIMER[4]),
.I5(VTIMER[3]),
.O(VBLANK_i_3_n_0));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAABA))
VBLANK_i_4
(.I0(INTERNAL_RST_reg),
.I1(VBLANK_i_5_n_0),
.I2(VTIMER_EN),
.I3(VBLANK_i_6_n_0),
.I4(VTIMER[6]),
.I5(VBLANK_i_7_n_0),
.O(VBLANK_i_4_n_0));
LUT3 #(
.INIT(8'hFE))
VBLANK_i_5
(.I0(VTIMER[3]),
.I1(VTIMER[5]),
.I2(VTIMER[4]),
.O(VBLANK_i_5_n_0));
LUT3 #(
.INIT(8'hFB))
VBLANK_i_6
(.I0(VTIMER[1]),
.I1(VTIMER[0]),
.I2(VTIMER[2]),
.O(VBLANK_i_6_n_0));
LUT3 #(
.INIT(8'hDF))
VBLANK_i_7
(.I0(VTIMER[9]),
.I1(VTIMER[8]),
.I2(VTIMER[7]),
.O(VBLANK_i_7_n_0));
FDRE VBLANK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(VBLANK_i_1_n_0),
.Q(VBLANK_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h1))
\VTIMER[0]_i_1
(.I0(VTIMER[0]),
.I1(\VTIMER[2]_i_2_n_0 ),
.O(\VTIMER[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h06))
\VTIMER[1]_i_1
(.I0(VTIMER[0]),
.I1(VTIMER[1]),
.I2(\VTIMER[2]_i_2_n_0 ),
.O(VTIMER_1[1]));
LUT4 #(
.INIT(16'h0078))
\VTIMER[2]_i_1
(.I0(VTIMER[1]),
.I1(VTIMER[0]),
.I2(VTIMER[2]),
.I3(\VTIMER[2]_i_2_n_0 ),
.O(VTIMER_1[2]));
LUT6 #(
.INIT(64'h0222000000000000))
\VTIMER[2]_i_2
(.I0(\VTIMER[2]_i_3_n_0 ),
.I1(VTIMER[5]),
.I2(VTIMER[3]),
.I3(VTIMER[4]),
.I4(VTIMER[1]),
.I5(VTIMER[2]),
.O(\VTIMER[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000400000))
\VTIMER[2]_i_3
(.I0(VTIMER[8]),
.I1(VTIMER[9]),
.I2(VTIMER[4]),
.I3(VTIMER[5]),
.I4(VTIMER[7]),
.I5(VTIMER[6]),
.O(\VTIMER[2]_i_3_n_0 ));
LUT4 #(
.INIT(16'h6AAA))
\VTIMER[3]_i_1
(.I0(VTIMER[3]),
.I1(VTIMER[2]),
.I2(VTIMER[1]),
.I3(VTIMER[0]),
.O(VTIMER_1[3]));
LUT6 #(
.INIT(64'h000000007FFF8000))
\VTIMER[4]_i_1
(.I0(VTIMER[0]),
.I1(VTIMER[1]),
.I2(VTIMER[2]),
.I3(VTIMER[3]),
.I4(VTIMER[4]),
.I5(\VTIMER[9]_i_3_n_0 ),
.O(VTIMER_1[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\VTIMER[5]_i_1
(.I0(VTIMER[5]),
.I1(VTIMER[4]),
.I2(VTIMER[0]),
.I3(VTIMER[1]),
.I4(VTIMER[2]),
.I5(VTIMER[3]),
.O(\VTIMER[5]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\VTIMER[6]_i_1
(.I0(VTIMER[6]),
.I1(\VTIMER[9]_i_2_n_0 ),
.O(VTIMER_1[6]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h1540))
\VTIMER[7]_i_1
(.I0(\VTIMER[9]_i_3_n_0 ),
.I1(\VTIMER[9]_i_2_n_0 ),
.I2(VTIMER[6]),
.I3(VTIMER[7]),
.O(VTIMER_1[7]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h6AAA))
\VTIMER[8]_i_1
(.I0(VTIMER[8]),
.I1(VTIMER[7]),
.I2(VTIMER[6]),
.I3(\VTIMER[9]_i_2_n_0 ),
.O(VTIMER_1[8]));
LUT6 #(
.INIT(64'h000000006AAAAAAA))
\VTIMER[9]_i_1
(.I0(VTIMER[9]),
.I1(\VTIMER[9]_i_2_n_0 ),
.I2(VTIMER[6]),
.I3(VTIMER[7]),
.I4(VTIMER[8]),
.I5(\VTIMER[9]_i_3_n_0 ),
.O(VTIMER_1[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\VTIMER[9]_i_2
(.I0(VTIMER[5]),
.I1(VTIMER[4]),
.I2(VTIMER[0]),
.I3(VTIMER[1]),
.I4(VTIMER[2]),
.I5(VTIMER[3]),
.O(\VTIMER[9]_i_2_n_0 ));
LUT5 #(
.INIT(32'h00000020))
\VTIMER[9]_i_3
(.I0(VTIMER[7]),
.I1(\VTIMER[9]_i_4_n_0 ),
.I2(VTIMER[9]),
.I3(VTIMER[8]),
.I4(\VTIMER[9]_i_5_n_0 ),
.O(\VTIMER[9]_i_3_n_0 ));
LUT4 #(
.INIT(16'hF8FF))
\VTIMER[9]_i_4
(.I0(VTIMER[6]),
.I1(VTIMER[7]),
.I2(VTIMER[5]),
.I3(VTIMER[4]),
.O(\VTIMER[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFF7F7F7))
\VTIMER[9]_i_5
(.I0(VTIMER[1]),
.I1(VTIMER[2]),
.I2(VTIMER[0]),
.I3(VTIMER[4]),
.I4(VTIMER[3]),
.I5(VTIMER[5]),
.O(\VTIMER[9]_i_5_n_0 ));
LUT2 #(
.INIT(4'hE))
VTIMER_EN_i_1
(.I0(INTERNAL_RST_reg),
.I1(\HTIMER[4]_i_2_n_0 ),
.O(VTIMER_EN_i_1_n_0));
FDRE VTIMER_EN_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(VTIMER_EN_i_1_n_0),
.Q(VTIMER_EN),
.R(1'b0));
FDRE \VTIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(\VTIMER[0]_i_1_n_0 ),
.Q(VTIMER[0]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[1]),
.Q(VTIMER[1]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[2]),
.Q(VTIMER[2]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[3]),
.Q(VTIMER[3]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[4]),
.Q(VTIMER[4]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(\VTIMER[5]_i_1_n_0 ),
.Q(VTIMER[5]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[6]),
.Q(VTIMER[6]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[7]),
.Q(VTIMER[7]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[8]),
.Q(VTIMER[8]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[9]),
.Q(VTIMER[9]),
.R(INTERNAL_RST_reg));
endmodule
module main_0
(IN1_STB,
output_rs232_tx,
IN1_ACK,
ETH_CLK_OBUF,
INTERNAL_RST_reg);
output IN1_STB;
output [7:0]output_rs232_tx;
input IN1_ACK;
input ETH_CLK_OBUF;
input INTERNAL_RST_reg;
wire ETH_CLK_OBUF;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg;
wire [3:0]address_a;
wire [3:0]address_a_2;
wire [3:0]address_b_2;
wire [3:0]address_z;
wire [3:0]address_z_2;
wire [3:0]address_z_3;
wire \address_z_3[3]_i_1_n_0 ;
wire [15:1]data1;
wire [16:1]data2;
wire [31:0]data3;
wire instruction0;
wire \instruction[0]_i_4_n_0 ;
wire \instruction[0]_i_5_n_0 ;
wire \instruction[0]_i_6_n_0 ;
wire \instruction[0]_i_7_n_0 ;
wire \instruction[15]_i_2_n_0 ;
wire \instruction[15]_i_3_n_0 ;
wire \instruction[15]_i_4_n_0 ;
wire \instruction[15]_i_5_n_0 ;
wire \instruction[15]_i_6_n_0 ;
wire \instruction[15]_i_7_n_0 ;
wire \instruction[16]_i_4_n_0 ;
wire \instruction[16]_i_5_n_0 ;
wire \instruction[16]_i_6_n_0 ;
wire \instruction[16]_i_7_n_0 ;
wire \instruction[17]_i_4_n_0 ;
wire \instruction[17]_i_5_n_0 ;
wire \instruction[17]_i_6_n_0 ;
wire \instruction[17]_i_7_n_0 ;
wire \instruction[18]_i_4_n_0 ;
wire \instruction[18]_i_5_n_0 ;
wire \instruction[18]_i_6_n_0 ;
wire \instruction[18]_i_7_n_0 ;
wire \instruction[19]_i_4_n_0 ;
wire \instruction[19]_i_5_n_0 ;
wire \instruction[19]_i_6_n_0 ;
wire \instruction[19]_i_7_n_0 ;
wire \instruction[1]_i_4_n_0 ;
wire \instruction[1]_i_5_n_0 ;
wire \instruction[1]_i_6_n_0 ;
wire \instruction[1]_i_7_n_0 ;
wire \instruction[20]_i_4_n_0 ;
wire \instruction[20]_i_5_n_0 ;
wire \instruction[20]_i_6_n_0 ;
wire \instruction[20]_i_7_n_0 ;
wire \instruction[21]_i_4_n_0 ;
wire \instruction[21]_i_5_n_0 ;
wire \instruction[21]_i_6_n_0 ;
wire \instruction[21]_i_7_n_0 ;
wire \instruction[22]_i_4_n_0 ;
wire \instruction[22]_i_5_n_0 ;
wire \instruction[22]_i_6_n_0 ;
wire \instruction[22]_i_7_n_0 ;
wire \instruction[23]_i_4_n_0 ;
wire \instruction[23]_i_5_n_0 ;
wire \instruction[23]_i_6_n_0 ;
wire \instruction[23]_i_7_n_0 ;
wire \instruction[24]_i_4_n_0 ;
wire \instruction[24]_i_5_n_0 ;
wire \instruction[24]_i_6_n_0 ;
wire \instruction[24]_i_7_n_0 ;
wire \instruction[25]_i_4_n_0 ;
wire \instruction[25]_i_5_n_0 ;
wire \instruction[25]_i_6_n_0 ;
wire \instruction[25]_i_7_n_0 ;
wire \instruction[26]_i_4_n_0 ;
wire \instruction[26]_i_5_n_0 ;
wire \instruction[26]_i_6_n_0 ;
wire \instruction[26]_i_7_n_0 ;
wire \instruction[27]_i_2_n_0 ;
wire \instruction[27]_i_3_n_0 ;
wire \instruction[27]_i_4_n_0 ;
wire \instruction[27]_i_5_n_0 ;
wire \instruction[27]_i_6_n_0 ;
wire \instruction[2]_i_4_n_0 ;
wire \instruction[2]_i_5_n_0 ;
wire \instruction[2]_i_6_n_0 ;
wire \instruction[2]_i_7_n_0 ;
wire \instruction[3]_i_4_n_0 ;
wire \instruction[3]_i_5_n_0 ;
wire \instruction[3]_i_6_n_0 ;
wire \instruction[3]_i_7_n_0 ;
wire \instruction[4]_i_1_n_0 ;
wire \instruction[4]_i_3_n_0 ;
wire \instruction[4]_i_4_n_0 ;
wire \instruction[4]_i_5_n_0 ;
wire \instruction[4]_i_6_n_0 ;
wire \instruction[5]_i_4_n_0 ;
wire \instruction[5]_i_5_n_0 ;
wire \instruction[5]_i_6_n_0 ;
wire \instruction[5]_i_7_n_0 ;
wire \instruction[6]_i_4_n_0 ;
wire \instruction[6]_i_5_n_0 ;
wire \instruction[6]_i_6_n_0 ;
wire \instruction[6]_i_7_n_0 ;
wire \instruction[7]_i_4_n_0 ;
wire \instruction[7]_i_5_n_0 ;
wire \instruction[7]_i_6_n_0 ;
wire \instruction[7]_i_7_n_0 ;
wire \instruction_reg[0]_i_1_n_0 ;
wire \instruction_reg[0]_i_2_n_0 ;
wire \instruction_reg[0]_i_3_n_0 ;
wire \instruction_reg[15]_i_1_n_0 ;
wire \instruction_reg[16]_i_1_n_0 ;
wire \instruction_reg[16]_i_2_n_0 ;
wire \instruction_reg[16]_i_3_n_0 ;
wire \instruction_reg[17]_i_1_n_0 ;
wire \instruction_reg[17]_i_2_n_0 ;
wire \instruction_reg[17]_i_3_n_0 ;
wire \instruction_reg[18]_i_1_n_0 ;
wire \instruction_reg[18]_i_2_n_0 ;
wire \instruction_reg[18]_i_3_n_0 ;
wire \instruction_reg[19]_i_1_n_0 ;
wire \instruction_reg[19]_i_2_n_0 ;
wire \instruction_reg[19]_i_3_n_0 ;
wire \instruction_reg[1]_i_1_n_0 ;
wire \instruction_reg[1]_i_2_n_0 ;
wire \instruction_reg[1]_i_3_n_0 ;
wire \instruction_reg[20]_i_1_n_0 ;
wire \instruction_reg[20]_i_2_n_0 ;
wire \instruction_reg[20]_i_3_n_0 ;
wire \instruction_reg[21]_i_1_n_0 ;
wire \instruction_reg[21]_i_2_n_0 ;
wire \instruction_reg[21]_i_3_n_0 ;
wire \instruction_reg[22]_i_1_n_0 ;
wire \instruction_reg[22]_i_2_n_0 ;
wire \instruction_reg[22]_i_3_n_0 ;
wire \instruction_reg[23]_i_1_n_0 ;
wire \instruction_reg[23]_i_2_n_0 ;
wire \instruction_reg[23]_i_3_n_0 ;
wire \instruction_reg[24]_i_1_n_0 ;
wire \instruction_reg[24]_i_2_n_0 ;
wire \instruction_reg[24]_i_3_n_0 ;
wire \instruction_reg[25]_i_1_n_0 ;
wire \instruction_reg[25]_i_2_n_0 ;
wire \instruction_reg[25]_i_3_n_0 ;
wire \instruction_reg[26]_i_1_n_0 ;
wire \instruction_reg[26]_i_2_n_0 ;
wire \instruction_reg[26]_i_3_n_0 ;
wire \instruction_reg[27]_i_1_n_0 ;
wire \instruction_reg[2]_i_1_n_0 ;
wire \instruction_reg[2]_i_2_n_0 ;
wire \instruction_reg[2]_i_3_n_0 ;
wire \instruction_reg[3]_i_1_n_0 ;
wire \instruction_reg[3]_i_2_n_0 ;
wire \instruction_reg[3]_i_3_n_0 ;
wire \instruction_reg[4]_i_2_n_0 ;
wire \instruction_reg[5]_i_1_n_0 ;
wire \instruction_reg[5]_i_2_n_0 ;
wire \instruction_reg[5]_i_3_n_0 ;
wire \instruction_reg[6]_i_1_n_0 ;
wire \instruction_reg[6]_i_2_n_0 ;
wire \instruction_reg[6]_i_3_n_0 ;
wire \instruction_reg[7]_i_1_n_0 ;
wire \instruction_reg[7]_i_2_n_0 ;
wire \instruction_reg[7]_i_3_n_0 ;
wire \instruction_reg_n_0_[0] ;
wire \instruction_reg_n_0_[15] ;
wire \instruction_reg_n_0_[1] ;
wire \instruction_reg_n_0_[2] ;
wire \instruction_reg_n_0_[3] ;
wire \instruction_reg_n_0_[4] ;
wire \instruction_reg_n_0_[5] ;
wire \instruction_reg_n_0_[6] ;
wire \instruction_reg_n_0_[7] ;
wire [15:4]literal_2;
wire [31:0]load_data;
wire memory_reg_1_ENARDEN_cooolgate_en_sig_1;
wire memory_reg_2_ENARDEN_cooolgate_en_sig_2;
wire memory_reg_3_ENARDEN_cooolgate_en_sig_3;
wire memory_reg_4_ENARDEN_cooolgate_en_sig_4;
wire memory_reg_5_ENARDEN_cooolgate_en_sig_5;
wire memory_reg_6_ENARDEN_cooolgate_en_sig_6;
wire memory_reg_7_ENARDEN_cooolgate_en_sig_7;
wire [3:0]opcode;
wire [3:0]opcode_2;
wire opcode_20;
wire operand_a1;
wire operand_b1;
wire [7:0]output_rs232_tx;
wire p_0_in;
wire \program_counter[10]_i_1_n_0 ;
wire \program_counter[11]_i_1_n_0 ;
wire \program_counter[12]_i_1_n_0 ;
wire \program_counter[13]_i_1_n_0 ;
wire \program_counter[14]_i_1_n_0 ;
wire \program_counter[14]_i_2_n_0 ;
wire \program_counter[14]_i_3_n_0 ;
wire \program_counter[15]_i_1_n_0 ;
wire \program_counter[15]_i_3_n_0 ;
wire \program_counter[8]_i_1_n_0 ;
wire \program_counter[9]_i_1_n_0 ;
wire [15:0]program_counter_1;
wire [15:0]program_counter_2;
wire \program_counter_reg[12]_i_2_n_0 ;
wire \program_counter_reg_n_0_[0] ;
wire \program_counter_reg_n_0_[10] ;
wire \program_counter_reg_n_0_[11] ;
wire \program_counter_reg_n_0_[12] ;
wire \program_counter_reg_n_0_[13] ;
wire \program_counter_reg_n_0_[14] ;
wire \program_counter_reg_n_0_[15] ;
wire \program_counter_reg_n_0_[1] ;
wire \program_counter_reg_n_0_[2] ;
wire \program_counter_reg_n_0_[3] ;
wire \program_counter_reg_n_0_[4] ;
wire \program_counter_reg_n_0_[5] ;
wire \program_counter_reg_n_0_[6] ;
wire \program_counter_reg_n_0_[7] ;
wire \program_counter_reg_n_0_[8] ;
wire \program_counter_reg_n_0_[9] ;
wire \program_counter_reg_rep[4]_i_2_n_0 ;
wire \program_counter_reg_rep[7]_i_4_n_0 ;
wire \program_counter_reg_rep_n_0_[0] ;
wire \program_counter_reg_rep_n_0_[1] ;
wire \program_counter_reg_rep_n_0_[2] ;
wire \program_counter_reg_rep_n_0_[3] ;
wire \program_counter_reg_rep_n_0_[4] ;
wire \program_counter_reg_rep_n_0_[5] ;
wire \program_counter_reg_rep_n_0_[6] ;
wire \program_counter_reg_rep_n_0_[7] ;
wire \program_counter_rep[0]_i_1_n_0 ;
wire \program_counter_rep[0]_i_2_n_0 ;
wire \program_counter_rep[1]_i_1_n_0 ;
wire \program_counter_rep[1]_i_2_n_0 ;
wire \program_counter_rep[2]_i_1_n_0 ;
wire \program_counter_rep[2]_i_2_n_0 ;
wire \program_counter_rep[3]_i_1_n_0 ;
wire \program_counter_rep[3]_i_2_n_0 ;
wire \program_counter_rep[4]_i_1_n_0 ;
wire \program_counter_rep[4]_i_3_n_0 ;
wire \program_counter_rep[5]_i_1_n_0 ;
wire \program_counter_rep[5]_i_2_n_0 ;
wire \program_counter_rep[6]_i_1_n_0 ;
wire \program_counter_rep[6]_i_2_n_0 ;
wire \program_counter_rep[7]_i_10_n_0 ;
wire \program_counter_rep[7]_i_15_n_0 ;
wire \program_counter_rep[7]_i_16_n_0 ;
wire \program_counter_rep[7]_i_17_n_0 ;
wire \program_counter_rep[7]_i_18_n_0 ;
wire \program_counter_rep[7]_i_19_n_0 ;
wire \program_counter_rep[7]_i_20_n_0 ;
wire \program_counter_rep[7]_i_21_n_0 ;
wire \program_counter_rep[7]_i_22_n_0 ;
wire \program_counter_rep[7]_i_23_n_0 ;
wire \program_counter_rep[7]_i_24_n_0 ;
wire \program_counter_rep[7]_i_25_n_0 ;
wire \program_counter_rep[7]_i_26_n_0 ;
wire \program_counter_rep[7]_i_2_n_0 ;
wire \program_counter_rep[7]_i_3_n_0 ;
wire \program_counter_rep[7]_i_5_n_0 ;
wire \program_counter_rep[7]_i_6_n_0 ;
wire \program_counter_rep[7]_i_7_n_0 ;
wire \program_counter_rep[7]_i_8_n_0 ;
wire \program_counter_rep[7]_i_9_n_0 ;
wire [31:0]register_a;
wire [31:0]register_b;
wire [31:0]result;
wire \result[0]_i_1_n_0 ;
wire \result[0]_i_2_n_0 ;
wire \result[10]_i_1_n_0 ;
wire \result[10]_i_2_n_0 ;
wire \result[11]_i_10_n_0 ;
wire \result[11]_i_11_n_0 ;
wire \result[11]_i_12_n_0 ;
wire \result[11]_i_1_n_0 ;
wire \result[11]_i_2_n_0 ;
wire \result[11]_i_5_n_0 ;
wire \result[11]_i_6_n_0 ;
wire \result[11]_i_7_n_0 ;
wire \result[11]_i_8_n_0 ;
wire \result[11]_i_9_n_0 ;
wire \result[12]_i_1_n_0 ;
wire \result[12]_i_2_n_0 ;
wire \result[13]_i_1_n_0 ;
wire \result[13]_i_2_n_0 ;
wire \result[14]_i_1_n_0 ;
wire \result[14]_i_2_n_0 ;
wire \result[15]_i_10_n_0 ;
wire \result[15]_i_11_n_0 ;
wire \result[15]_i_12_n_0 ;
wire \result[15]_i_1_n_0 ;
wire \result[15]_i_2_n_0 ;
wire \result[15]_i_5_n_0 ;
wire \result[15]_i_6_n_0 ;
wire \result[15]_i_7_n_0 ;
wire \result[15]_i_8_n_0 ;
wire \result[15]_i_9_n_0 ;
wire \result[16]_i_1_n_0 ;
wire \result[16]_i_2_n_0 ;
wire \result[16]_i_4_n_0 ;
wire \result[17]_i_1_n_0 ;
wire \result[17]_i_2_n_0 ;
wire \result[18]_i_1_n_0 ;
wire \result[18]_i_2_n_0 ;
wire \result[19]_i_10_n_0 ;
wire \result[19]_i_11_n_0 ;
wire \result[19]_i_12_n_0 ;
wire \result[19]_i_1_n_0 ;
wire \result[19]_i_2_n_0 ;
wire \result[19]_i_5_n_0 ;
wire \result[19]_i_6_n_0 ;
wire \result[19]_i_7_n_0 ;
wire \result[19]_i_8_n_0 ;
wire \result[19]_i_9_n_0 ;
wire \result[1]_i_1_n_0 ;
wire \result[1]_i_2_n_0 ;
wire \result[20]_i_1_n_0 ;
wire \result[20]_i_2_n_0 ;
wire \result[21]_i_1_n_0 ;
wire \result[21]_i_2_n_0 ;
wire \result[22]_i_1_n_0 ;
wire \result[22]_i_2_n_0 ;
wire \result[23]_i_10_n_0 ;
wire \result[23]_i_11_n_0 ;
wire \result[23]_i_12_n_0 ;
wire \result[23]_i_1_n_0 ;
wire \result[23]_i_2_n_0 ;
wire \result[23]_i_5_n_0 ;
wire \result[23]_i_6_n_0 ;
wire \result[23]_i_7_n_0 ;
wire \result[23]_i_8_n_0 ;
wire \result[23]_i_9_n_0 ;
wire \result[24]_i_1_n_0 ;
wire \result[24]_i_2_n_0 ;
wire \result[25]_i_1_n_0 ;
wire \result[25]_i_2_n_0 ;
wire \result[26]_i_1_n_0 ;
wire \result[26]_i_2_n_0 ;
wire \result[27]_i_10_n_0 ;
wire \result[27]_i_11_n_0 ;
wire \result[27]_i_12_n_0 ;
wire \result[27]_i_1_n_0 ;
wire \result[27]_i_2_n_0 ;
wire \result[27]_i_5_n_0 ;
wire \result[27]_i_6_n_0 ;
wire \result[27]_i_7_n_0 ;
wire \result[27]_i_8_n_0 ;
wire \result[27]_i_9_n_0 ;
wire \result[28]_i_1_n_0 ;
wire \result[28]_i_2_n_0 ;
wire \result[29]_i_1_n_0 ;
wire \result[29]_i_2_n_0 ;
wire \result[2]_i_1_n_0 ;
wire \result[2]_i_2_n_0 ;
wire \result[30]_i_1_n_0 ;
wire \result[30]_i_2_n_0 ;
wire \result[31]_i_10_n_0 ;
wire \result[31]_i_11_n_0 ;
wire \result[31]_i_12_n_0 ;
wire \result[31]_i_13_n_0 ;
wire \result[31]_i_14_n_0 ;
wire \result[31]_i_15_n_0 ;
wire \result[31]_i_1_n_0 ;
wire \result[31]_i_2_n_0 ;
wire \result[31]_i_3_n_0 ;
wire \result[31]_i_4_n_0 ;
wire \result[31]_i_5_n_0 ;
wire \result[31]_i_8_n_0 ;
wire \result[31]_i_9_n_0 ;
wire \result[3]_i_10_n_0 ;
wire \result[3]_i_11_n_0 ;
wire \result[3]_i_12_n_0 ;
wire \result[3]_i_13_n_0 ;
wire \result[3]_i_14_n_0 ;
wire \result[3]_i_15_n_0 ;
wire \result[3]_i_16_n_0 ;
wire \result[3]_i_1_n_0 ;
wire \result[3]_i_2_n_0 ;
wire \result[3]_i_5_n_0 ;
wire \result[3]_i_6_n_0 ;
wire \result[3]_i_7_n_0 ;
wire \result[3]_i_8_n_0 ;
wire \result[3]_i_9_n_0 ;
wire \result[4]_i_1_n_0 ;
wire \result[4]_i_2_n_0 ;
wire \result[5]_i_1_n_0 ;
wire \result[5]_i_2_n_0 ;
wire \result[6]_i_1_n_0 ;
wire \result[6]_i_2_n_0 ;
wire \result[7]_i_10_n_0 ;
wire \result[7]_i_11_n_0 ;
wire \result[7]_i_12_n_0 ;
wire \result[7]_i_1_n_0 ;
wire \result[7]_i_2_n_0 ;
wire \result[7]_i_5_n_0 ;
wire \result[7]_i_6_n_0 ;
wire \result[7]_i_7_n_0 ;
wire \result[7]_i_8_n_0 ;
wire \result[7]_i_9_n_0 ;
wire \result[8]_i_1_n_0 ;
wire \result[8]_i_2_n_0 ;
wire \result[9]_i_1_n_0 ;
wire \result[9]_i_2_n_0 ;
wire \result_reg[11]_i_3_n_0 ;
wire \result_reg[11]_i_3_n_4 ;
wire \result_reg[11]_i_3_n_5 ;
wire \result_reg[11]_i_3_n_6 ;
wire \result_reg[11]_i_3_n_7 ;
wire \result_reg[11]_i_4_n_0 ;
wire \result_reg[12]_i_3_n_0 ;
wire \result_reg[15]_i_3_n_0 ;
wire \result_reg[15]_i_3_n_4 ;
wire \result_reg[15]_i_3_n_5 ;
wire \result_reg[15]_i_3_n_6 ;
wire \result_reg[15]_i_3_n_7 ;
wire \result_reg[15]_i_4_n_0 ;
wire \result_reg[19]_i_3_n_0 ;
wire \result_reg[19]_i_3_n_4 ;
wire \result_reg[19]_i_3_n_5 ;
wire \result_reg[19]_i_3_n_6 ;
wire \result_reg[19]_i_3_n_7 ;
wire \result_reg[19]_i_4_n_0 ;
wire \result_reg[23]_i_3_n_0 ;
wire \result_reg[23]_i_3_n_4 ;
wire \result_reg[23]_i_3_n_5 ;
wire \result_reg[23]_i_3_n_6 ;
wire \result_reg[23]_i_3_n_7 ;
wire \result_reg[23]_i_4_n_0 ;
wire \result_reg[27]_i_3_n_0 ;
wire \result_reg[27]_i_3_n_4 ;
wire \result_reg[27]_i_3_n_5 ;
wire \result_reg[27]_i_3_n_6 ;
wire \result_reg[27]_i_3_n_7 ;
wire \result_reg[27]_i_4_n_0 ;
wire \result_reg[31]_i_6_n_4 ;
wire \result_reg[31]_i_6_n_5 ;
wire \result_reg[31]_i_6_n_6 ;
wire \result_reg[31]_i_6_n_7 ;
wire \result_reg[3]_i_3_n_0 ;
wire \result_reg[3]_i_3_n_4 ;
wire \result_reg[3]_i_3_n_5 ;
wire \result_reg[3]_i_3_n_6 ;
wire \result_reg[3]_i_3_n_7 ;
wire \result_reg[3]_i_4_n_0 ;
wire \result_reg[4]_i_3_n_0 ;
wire \result_reg[7]_i_3_n_0 ;
wire \result_reg[7]_i_3_n_4 ;
wire \result_reg[7]_i_3_n_5 ;
wire \result_reg[7]_i_3_n_6 ;
wire \result_reg[7]_i_3_n_7 ;
wire \result_reg[7]_i_4_n_0 ;
wire \result_reg[8]_i_3_n_0 ;
wire \s_output_rs232_tx[7]_i_1_n_0 ;
wire \s_output_rs232_tx[7]_i_2_n_0 ;
wire \s_output_rs232_tx[7]_i_3_n_0 ;
wire \s_output_rs232_tx[7]_i_4_n_0 ;
wire \s_output_rs232_tx[7]_i_5_n_0 ;
wire \s_output_rs232_tx[7]_i_6_n_0 ;
wire \s_output_rs232_tx[7]_i_7_n_0 ;
wire \s_output_rs232_tx[7]_i_8_n_0 ;
wire \s_output_rs232_tx_stb[0]_i_1_n_0 ;
wire \state[0]_i_1_n_0 ;
wire \state[1]_i_1_n_0 ;
wire \state[2]_i_10_n_0 ;
wire \state[2]_i_11_n_0 ;
wire \state[2]_i_12_n_0 ;
wire \state[2]_i_1_n_0 ;
wire \state[2]_i_2_n_0 ;
wire \state[2]_i_3_n_0 ;
wire \state[2]_i_4_n_0 ;
wire \state[2]_i_5_n_0 ;
wire \state[2]_i_6_n_0 ;
wire \state[2]_i_7_n_0 ;
wire \state[2]_i_8_n_0 ;
wire \state[2]_i_9_n_0 ;
wire \state_reg_n_0_[0] ;
wire \state_reg_n_0_[1] ;
wire \state_reg_n_0_[2] ;
wire [31:0]store_data;
wire write_enable;
wire [31:0]write_output;
wire \write_output[0]_i_1_n_0 ;
wire \write_output[10]_i_1_n_0 ;
wire \write_output[11]_i_1_n_0 ;
wire \write_output[12]_i_1_n_0 ;
wire \write_output[13]_i_1_n_0 ;
wire \write_output[14]_i_1_n_0 ;
wire \write_output[15]_i_1_n_0 ;
wire \write_output[16]_i_1_n_0 ;
wire \write_output[17]_i_1_n_0 ;
wire \write_output[18]_i_1_n_0 ;
wire \write_output[19]_i_1_n_0 ;
wire \write_output[1]_i_1_n_0 ;
wire \write_output[20]_i_1_n_0 ;
wire \write_output[21]_i_1_n_0 ;
wire \write_output[22]_i_1_n_0 ;
wire \write_output[23]_i_1_n_0 ;
wire \write_output[24]_i_1_n_0 ;
wire \write_output[25]_i_1_n_0 ;
wire \write_output[26]_i_1_n_0 ;
wire \write_output[27]_i_1_n_0 ;
wire \write_output[28]_i_1_n_0 ;
wire \write_output[29]_i_1_n_0 ;
wire \write_output[2]_i_1_n_0 ;
wire \write_output[30]_i_1_n_0 ;
wire \write_output[31]_i_1_n_0 ;
wire \write_output[31]_i_2_n_0 ;
wire \write_output[31]_i_3_n_0 ;
wire \write_output[31]_i_4_n_0 ;
wire \write_output[3]_i_1_n_0 ;
wire \write_output[4]_i_1_n_0 ;
wire \write_output[5]_i_1_n_0 ;
wire \write_output[6]_i_1_n_0 ;
wire \write_output[7]_i_1_n_0 ;
wire \write_output[8]_i_1_n_0 ;
wire \write_output[9]_i_1_n_0 ;
wire [7:0]write_value;
wire \write_value[7]_i_3_n_0 ;
wire NLW_memory_reg_0_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_0_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_0_DBITERR_UNCONNECTED;
wire NLW_memory_reg_0_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_0_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_0_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_0_REGCEB_UNCONNECTED;
wire NLW_memory_reg_0_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_0_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_0_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_0_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_0_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_0_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_0_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_1_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_1_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_1_DBITERR_UNCONNECTED;
wire NLW_memory_reg_1_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_1_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_1_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_1_REGCEB_UNCONNECTED;
wire NLW_memory_reg_1_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_1_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_1_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_1_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_1_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_1_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_1_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_2_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_2_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_2_DBITERR_UNCONNECTED;
wire NLW_memory_reg_2_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_2_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_2_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_2_REGCEB_UNCONNECTED;
wire NLW_memory_reg_2_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_2_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_2_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_2_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_2_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_2_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_2_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_3_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_3_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_3_DBITERR_UNCONNECTED;
wire NLW_memory_reg_3_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_3_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_3_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_3_REGCEB_UNCONNECTED;
wire NLW_memory_reg_3_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_3_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_3_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_3_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_3_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_3_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_3_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_4_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_4_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_4_DBITERR_UNCONNECTED;
wire NLW_memory_reg_4_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_4_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_4_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_4_REGCEB_UNCONNECTED;
wire NLW_memory_reg_4_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_4_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_4_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_4_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_4_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_4_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_4_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_5_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_5_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_5_DBITERR_UNCONNECTED;
wire NLW_memory_reg_5_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_5_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_5_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_5_REGCEB_UNCONNECTED;
wire NLW_memory_reg_5_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_5_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_5_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_5_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_5_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_5_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_5_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_6_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_6_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_6_DBITERR_UNCONNECTED;
wire NLW_memory_reg_6_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_6_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_6_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_6_REGCEB_UNCONNECTED;
wire NLW_memory_reg_6_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_6_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_6_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_6_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_6_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_6_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_6_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_7_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_7_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_7_DBITERR_UNCONNECTED;
wire NLW_memory_reg_7_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_7_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_7_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_7_REGCEB_UNCONNECTED;
wire NLW_memory_reg_7_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_7_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_7_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_7_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_7_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_7_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_7_RDADDRECC_UNCONNECTED;
wire [2:0]\NLW_program_counter_reg[12]_i_2_CO_UNCONNECTED ;
wire [3:0]\NLW_program_counter_reg[15]_i_2_CO_UNCONNECTED ;
wire [3:3]\NLW_program_counter_reg[15]_i_2_O_UNCONNECTED ;
wire [2:0]\NLW_program_counter_reg_rep[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_program_counter_reg_rep[7]_i_4_CO_UNCONNECTED ;
wire [1:0]NLW_registers_reg_r1_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOB_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOC_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_6_11_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOB_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOC_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_6_11_DOD_UNCONNECTED;
wire [2:0]\NLW_result_reg[11]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[11]_i_4_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[12]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[15]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[15]_i_4_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[16]_i_3_CO_UNCONNECTED ;
wire [3:3]\NLW_result_reg[16]_i_3_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[19]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[19]_i_4_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[23]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[23]_i_4_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[27]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[27]_i_4_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[31]_i_6_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[31]_i_7_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[3]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[3]_i_4_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[4]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[7]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[7]_i_4_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[8]_i_3_CO_UNCONNECTED ;
FDRE \address_a_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[0]),
.Q(address_a_2[0]),
.R(1'b0));
FDRE \address_a_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[1]),
.Q(address_a_2[1]),
.R(1'b0));
FDRE \address_a_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[2]),
.Q(address_a_2[2]),
.R(1'b0));
FDRE \address_a_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[3]),
.Q(address_a_2[3]),
.R(1'b0));
FDRE \address_b_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[0] ),
.Q(address_b_2[0]),
.R(1'b0));
FDRE \address_b_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[1] ),
.Q(address_b_2[1]),
.R(1'b0));
FDRE \address_b_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[2] ),
.Q(address_b_2[2]),
.R(1'b0));
FDRE \address_b_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[3] ),
.Q(address_b_2[3]),
.R(1'b0));
FDRE \address_z_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[0]),
.Q(address_z_2[0]),
.R(1'b0));
FDRE \address_z_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[1]),
.Q(address_z_2[1]),
.R(1'b0));
FDRE \address_z_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[2]),
.Q(address_z_2[2]),
.R(1'b0));
FDRE \address_z_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[3]),
.Q(address_z_2[3]),
.R(1'b0));
LUT3 #(
.INIT(8'h40))
\address_z_3[3]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(\state_reg_n_0_[0] ),
.O(\address_z_3[3]_i_1_n_0 ));
FDRE \address_z_3_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[0]),
.Q(address_z_3[0]),
.R(INTERNAL_RST_reg));
FDRE \address_z_3_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[1]),
.Q(address_z_3[1]),
.R(INTERNAL_RST_reg));
FDRE \address_z_3_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[2]),
.Q(address_z_3[2]),
.R(INTERNAL_RST_reg));
FDRE \address_z_3_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[3]),
.Q(address_z_3[3]),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hF001000000F05200))
\instruction[0]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h03A0A8E454A04452))
\instruction[0]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'h050F55AA004622FC))
\instruction[0]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'h05EE010002452252))
\instruction[0]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'h8888B888))
\instruction[15]_i_2
(.I0(\instruction[15]_i_4_n_0 ),
.I1(\program_counter_reg_rep_n_0_[1] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\instruction[15]_i_5_n_0 ),
.I4(\program_counter_reg_rep_n_0_[2] ),
.O(\instruction[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0008FFFF00080000))
\instruction[15]_i_3
(.I0(\program_counter_reg_rep_n_0_[6] ),
.I1(\instruction[15]_i_6_n_0 ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[2] ),
.I4(\program_counter_reg_rep_n_0_[1] ),
.I5(\instruction[15]_i_7_n_0 ),
.O(\instruction[15]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0A50500508444000))
\instruction[15]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[15]_i_4_n_0 ));
LUT3 #(
.INIT(8'h94))
\instruction[15]_i_5
(.I0(\program_counter_reg_rep_n_0_[3] ),
.I1(\program_counter_reg_rep_n_0_[4] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[15]_i_5_n_0 ));
LUT2 #(
.INIT(4'h1))
\instruction[15]_i_6
(.I0(\program_counter_reg_rep_n_0_[5] ),
.I1(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[15]_i_6_n_0 ));
LUT6 #(
.INIT(64'hC3000044C0000040))
\instruction[15]_i_7
(.I0(\program_counter_reg_rep_n_0_[5] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[15]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAD8850A08AF8A8F4))
\instruction[16]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[16]_i_4_n_0 ));
LUT6 #(
.INIT(64'h8FD8EC44A8F8E4F9))
\instruction[16]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[16]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0FA0F4F80050CCEC))
\instruction[16]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[16]_i_6_n_0 ));
LUT6 #(
.INIT(64'hDD00F8F45A0050F0))
\instruction[16]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[16]_i_7_n_0 ));
LUT6 #(
.INIT(64'h21CE54EEAAF921FC))
\instruction[17]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[17]_i_4_n_0 ));
LUT6 #(
.INIT(64'hDF7564BAED5476B9))
\instruction[17]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[17]_i_5_n_0 ));
LUT6 #(
.INIT(64'hCF98FDB8FECDFCEE))
\instruction[17]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[17]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFD12B8B246017530))
\instruction[17]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[17]_i_7_n_0 ));
LUT6 #(
.INIT(64'hBB838C3888808800))
\instruction[18]_i_4
(.I0(\program_counter_reg_rep_n_0_[7] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[18]_i_4_n_0 ));
LUT6 #(
.INIT(64'h88D858D488880884))
\instruction[18]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[18]_i_5_n_0 ));
LUT6 #(
.INIT(64'hC8808C3888008800))
\instruction[18]_i_6
(.I0(\program_counter_reg_rep_n_0_[7] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[18]_i_6_n_0 ));
LUT6 #(
.INIT(64'hCEEC0000CDDC0000))
\instruction[18]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[18]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0F0000000C004040))
\instruction[19]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[19]_i_4_n_0 ));
LUT5 #(
.INIT(32'h80200000))
\instruction[19]_i_5
(.I0(\program_counter_reg_rep_n_0_[6] ),
.I1(\program_counter_reg_rep_n_0_[3] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[2] ),
.O(\instruction[19]_i_5_n_0 ));
LUT6 #(
.INIT(64'h3000C30000008000))
\instruction[19]_i_6
(.I0(\program_counter_reg_rep_n_0_[7] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[19]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0A0050004848C88C))
\instruction[19]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[19]_i_7_n_0 ));
LUT6 #(
.INIT(64'h5251424061405040))
\instruction[1]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[6] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'hCD54A80256456510))
\instruction[1]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[1]_i_5_n_0 ));
LUT6 #(
.INIT(64'h64476522444602B8))
\instruction[1]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[1]_i_6_n_0 ));
LUT6 #(
.INIT(64'h4445000202000298))
\instruction[1]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[1]_i_7_n_0 ));
LUT6 #(
.INIT(64'hA00000500050A0A1))
\instruction[20]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[20]_i_4_n_0 ));
LUT6 #(
.INIT(64'h8AE4F84454F04451))
\instruction[20]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[20]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0500F4A8000008AC))
\instruction[20]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[20]_i_6_n_0 ));
LUT6 #(
.INIT(64'h00FFEC0005CCFF00))
\instruction[20]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[6] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[20]_i_7_n_0 ));
LUT6 #(
.INIT(64'h20551010AA5421A3))
\instruction[21]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[21]_i_4_n_0 ));
LUT6 #(
.INIT(64'hEEFC5466EE45B9F9))
\instruction[21]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[21]_i_5_n_0 ));
LUT6 #(
.INIT(64'h55AFF5D80052AAFC))
\instruction[21]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[21]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0FA25F8955F854F6))
\instruction[21]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[21]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAA80AA000080280C))
\instruction[22]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[6] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[22]_i_4_n_0 ));
LUT6 #(
.INIT(64'h8888300488880000))
\instruction[22]_i_5
(.I0(\program_counter_reg_rep_n_0_[7] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[22]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000200000152001))
\instruction[22]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[3] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[6] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[22]_i_6_n_0 ));
LUT5 #(
.INIT(32'h20C01000))
\instruction[22]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[6] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[22]_i_7_n_0 ));
LUT6 #(
.INIT(64'h56E54554A0020208))
\instruction[23]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[23]_i_4_n_0 ));
LUT6 #(
.INIT(64'h54A0550046190846))
\instruction[23]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[23]_i_5_n_0 ));
LUT6 #(
.INIT(64'h2010002202010500))
\instruction[23]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[23]_i_6_n_0 ));
LUT6 #(
.INIT(64'h62400A2840D20A49))
\instruction[23]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[23]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFDFCEC4C8C8))
\instruction[24]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[24]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFEFCFCCCFCF8FCFD))
\instruction[24]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[24]_i_5_n_0 ));
LUT6 #(
.INIT(64'hF588F4FCFA50D8FC))
\instruction[24]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[24]_i_6_n_0 ));
LUT6 #(
.INIT(64'hEDFFFAC8FDCCFFCC))
\instruction[24]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[6] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[24]_i_7_n_0 ));
LUT6 #(
.INIT(64'h45EC308A46452144))
\instruction[25]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[25]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0189010000463200))
\instruction[25]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[25]_i_5_n_0 ));
LUT6 #(
.INIT(64'hCECEFDEC0A050052))
\instruction[25]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[25]_i_6_n_0 ));
LUT6 #(
.INIT(64'hD88804128A890108))
\instruction[25]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[25]_i_7_n_0 ));
LUT6 #(
.INIT(64'h20FF910020009000))
\instruction[26]_i_4
(.I0(\program_counter_reg_rep_n_0_[5] ),
.I1(\program_counter_reg_rep_n_0_[3] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[2] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[26]_i_4_n_0 ));
LUT6 #(
.INIT(64'h5405A58A4400A088))
\instruction[26]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[26]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0077000020201000))
\instruction[26]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[4] ),
.I2(\program_counter_reg_rep_n_0_[7] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[26]_i_6_n_0 ));
LUT6 #(
.INIT(64'hE5EA080840C00848))
\instruction[26]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[26]_i_7_n_0 ));
LUT6 #(
.INIT(64'h4000434000000000))
\instruction[27]_i_2
(.I0(\program_counter_reg_rep_n_0_[1] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[27]_i_2_n_0 ));
LUT6 #(
.INIT(64'hC0A0C0A00F000000))
\instruction[27]_i_3
(.I0(\instruction[27]_i_4_n_0 ),
.I1(\instruction[27]_i_5_n_0 ),
.I2(\program_counter_reg_rep_n_0_[1] ),
.I3(\program_counter_reg_rep_n_0_[7] ),
.I4(\instruction[27]_i_6_n_0 ),
.I5(\program_counter_reg_rep_n_0_[2] ),
.O(\instruction[27]_i_3_n_0 ));
LUT4 #(
.INIT(16'h4000))
\instruction[27]_i_4
(.I0(\program_counter_reg_rep_n_0_[3] ),
.I1(\program_counter_reg_rep_n_0_[5] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[27]_i_4_n_0 ));
LUT2 #(
.INIT(4'h2))
\instruction[27]_i_5
(.I0(\program_counter_reg_rep_n_0_[5] ),
.I1(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[27]_i_5_n_0 ));
LUT3 #(
.INIT(8'h04))
\instruction[27]_i_6
(.I0(\program_counter_reg_rep_n_0_[4] ),
.I1(\program_counter_reg_rep_n_0_[5] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[27]_i_6_n_0 ));
LUT6 #(
.INIT(64'h55000550A151A200))
\instruction[2]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'h055EAAE410000212))
\instruction[2]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'h888800AA0045CD28))
\instruction[2]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[4] ),
.I2(\program_counter_reg_rep_n_0_[7] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[2]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000A050000010210))
\instruction[2]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[2]_i_7_n_0 ));
LUT6 #(
.INIT(64'h1088139A8B518B44))
\instruction[3]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00565547AB460010))
\instruction[3]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[3]_i_5_n_0 ));
LUT6 #(
.INIT(64'hEEEE465570510B2A))
\instruction[3]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[6] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'h5041426200013331))
\instruction[3]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[6] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[3]_i_7_n_0 ));
LUT6 #(
.INIT(64'hB888B888B8BBB888))
\instruction[4]_i_1
(.I0(\instruction_reg[4]_i_2_n_0 ),
.I1(\program_counter_reg_rep_n_0_[0] ),
.I2(\instruction[4]_i_3_n_0 ),
.I3(\program_counter_reg_rep_n_0_[1] ),
.I4(\instruction[4]_i_4_n_0 ),
.I5(\program_counter_reg_rep_n_0_[2] ),
.O(\instruction[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0054A84410000011))
\instruction[4]_i_3
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[4]_i_3_n_0 ));
LUT4 #(
.INIT(16'h8600))
\instruction[4]_i_4
(.I0(\program_counter_reg_rep_n_0_[5] ),
.I1(\program_counter_reg_rep_n_0_[4] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[4]_i_4_n_0 ));
LUT6 #(
.INIT(64'hCF000050C0300040))
\instruction[4]_i_5
(.I0(\program_counter_reg_rep_n_0_[5] ),
.I1(\program_counter_reg_rep_n_0_[6] ),
.I2(\program_counter_reg_rep_n_0_[2] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[4]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000001000004))
\instruction[4]_i_6
(.I0(\program_counter_reg_rep_n_0_[7] ),
.I1(\program_counter_reg_rep_n_0_[6] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[2] ),
.O(\instruction[4]_i_6_n_0 ));
LUT6 #(
.INIT(64'h54A1440244105600))
\instruction[5]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[5]_i_4_n_0 ));
LUT6 #(
.INIT(64'h44545544AA414412))
\instruction[5]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[5] ),
.O(\instruction[5]_i_5_n_0 ));
LUT6 #(
.INIT(64'hA0A0000A0041A508))
\instruction[5]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[5]_i_6_n_0 ));
LUT6 #(
.INIT(64'h2000000020010048))
\instruction[5]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[3] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[6] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[5]_i_7_n_0 ));
LUT6 #(
.INIT(64'h10A1000200501000))
\instruction[6]_i_4
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[3] ),
.O(\instruction[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'hCAD4D0C5CAC4C0C2))
\instruction[6]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'hE000A402000101F8))
\instruction[6]_i_6
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[6]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000010000000251))
\instruction[6]_i_7
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[6] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[5] ),
.I5(\program_counter_reg_rep_n_0_[4] ),
.O(\instruction[6]_i_7_n_0 ));
LUT6 #(
.INIT(64'h00000000FF208220))
\instruction[7]_i_4
(.I0(\program_counter_reg_rep_n_0_[6] ),
.I1(\program_counter_reg_rep_n_0_[3] ),
.I2(\program_counter_reg_rep_n_0_[4] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[7] ),
.I5(\program_counter_reg_rep_n_0_[2] ),
.O(\instruction[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0A54500508440000))
\instruction[7]_i_5
(.I0(\program_counter_reg_rep_n_0_[2] ),
.I1(\program_counter_reg_rep_n_0_[7] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[4] ),
.I4(\program_counter_reg_rep_n_0_[3] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[7]_i_5_n_0 ));
LUT6 #(
.INIT(64'hBB30303C88000008))
\instruction[7]_i_6
(.I0(\program_counter_reg_rep_n_0_[6] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[5] ),
.I3(\program_counter_reg_rep_n_0_[3] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[7] ),
.O(\instruction[7]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0C00000308000000))
\instruction[7]_i_7
(.I0(\program_counter_reg_rep_n_0_[7] ),
.I1(\program_counter_reg_rep_n_0_[2] ),
.I2(\program_counter_reg_rep_n_0_[3] ),
.I3(\program_counter_reg_rep_n_0_[5] ),
.I4(\program_counter_reg_rep_n_0_[4] ),
.I5(\program_counter_reg_rep_n_0_[6] ),
.O(\instruction[7]_i_7_n_0 ));
FDRE \instruction_reg[0]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[0]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[0] ),
.R(1'b0));
MUXF8 \instruction_reg[0]_i_1
(.I0(\instruction_reg[0]_i_2_n_0 ),
.I1(\instruction_reg[0]_i_3_n_0 ),
.O(\instruction_reg[0]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[0]_i_2
(.I0(\instruction[0]_i_4_n_0 ),
.I1(\instruction[0]_i_5_n_0 ),
.O(\instruction_reg[0]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[0]_i_3
(.I0(\instruction[0]_i_6_n_0 ),
.I1(\instruction[0]_i_7_n_0 ),
.O(\instruction_reg[0]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[15]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[15]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[15] ),
.R(1'b0));
MUXF7 \instruction_reg[15]_i_1
(.I0(\instruction[15]_i_2_n_0 ),
.I1(\instruction[15]_i_3_n_0 ),
.O(\instruction_reg[15]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
FDRE \instruction_reg[16]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[16]_i_1_n_0 ),
.Q(address_a[0]),
.R(1'b0));
MUXF8 \instruction_reg[16]_i_1
(.I0(\instruction_reg[16]_i_2_n_0 ),
.I1(\instruction_reg[16]_i_3_n_0 ),
.O(\instruction_reg[16]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[16]_i_2
(.I0(\instruction[16]_i_4_n_0 ),
.I1(\instruction[16]_i_5_n_0 ),
.O(\instruction_reg[16]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[16]_i_3
(.I0(\instruction[16]_i_6_n_0 ),
.I1(\instruction[16]_i_7_n_0 ),
.O(\instruction_reg[16]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[17]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[17]_i_1_n_0 ),
.Q(address_a[1]),
.R(1'b0));
MUXF8 \instruction_reg[17]_i_1
(.I0(\instruction_reg[17]_i_2_n_0 ),
.I1(\instruction_reg[17]_i_3_n_0 ),
.O(\instruction_reg[17]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[17]_i_2
(.I0(\instruction[17]_i_4_n_0 ),
.I1(\instruction[17]_i_5_n_0 ),
.O(\instruction_reg[17]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[17]_i_3
(.I0(\instruction[17]_i_6_n_0 ),
.I1(\instruction[17]_i_7_n_0 ),
.O(\instruction_reg[17]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[18]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[18]_i_1_n_0 ),
.Q(address_a[2]),
.R(1'b0));
MUXF8 \instruction_reg[18]_i_1
(.I0(\instruction_reg[18]_i_2_n_0 ),
.I1(\instruction_reg[18]_i_3_n_0 ),
.O(\instruction_reg[18]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[18]_i_2
(.I0(\instruction[18]_i_4_n_0 ),
.I1(\instruction[18]_i_5_n_0 ),
.O(\instruction_reg[18]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[18]_i_3
(.I0(\instruction[18]_i_6_n_0 ),
.I1(\instruction[18]_i_7_n_0 ),
.O(\instruction_reg[18]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[19]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[19]_i_1_n_0 ),
.Q(address_a[3]),
.R(1'b0));
MUXF8 \instruction_reg[19]_i_1
(.I0(\instruction_reg[19]_i_2_n_0 ),
.I1(\instruction_reg[19]_i_3_n_0 ),
.O(\instruction_reg[19]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[19]_i_2
(.I0(\instruction[19]_i_4_n_0 ),
.I1(\instruction[19]_i_5_n_0 ),
.O(\instruction_reg[19]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[19]_i_3
(.I0(\instruction[19]_i_6_n_0 ),
.I1(\instruction[19]_i_7_n_0 ),
.O(\instruction_reg[19]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[1]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[1]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[1] ),
.R(1'b0));
MUXF8 \instruction_reg[1]_i_1
(.I0(\instruction_reg[1]_i_2_n_0 ),
.I1(\instruction_reg[1]_i_3_n_0 ),
.O(\instruction_reg[1]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[1]_i_2
(.I0(\instruction[1]_i_4_n_0 ),
.I1(\instruction[1]_i_5_n_0 ),
.O(\instruction_reg[1]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[1]_i_3
(.I0(\instruction[1]_i_6_n_0 ),
.I1(\instruction[1]_i_7_n_0 ),
.O(\instruction_reg[1]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[20]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[20]_i_1_n_0 ),
.Q(address_z[0]),
.R(1'b0));
MUXF8 \instruction_reg[20]_i_1
(.I0(\instruction_reg[20]_i_2_n_0 ),
.I1(\instruction_reg[20]_i_3_n_0 ),
.O(\instruction_reg[20]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[20]_i_2
(.I0(\instruction[20]_i_4_n_0 ),
.I1(\instruction[20]_i_5_n_0 ),
.O(\instruction_reg[20]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[20]_i_3
(.I0(\instruction[20]_i_6_n_0 ),
.I1(\instruction[20]_i_7_n_0 ),
.O(\instruction_reg[20]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[21]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[21]_i_1_n_0 ),
.Q(address_z[1]),
.R(1'b0));
MUXF8 \instruction_reg[21]_i_1
(.I0(\instruction_reg[21]_i_2_n_0 ),
.I1(\instruction_reg[21]_i_3_n_0 ),
.O(\instruction_reg[21]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[21]_i_2
(.I0(\instruction[21]_i_4_n_0 ),
.I1(\instruction[21]_i_5_n_0 ),
.O(\instruction_reg[21]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[21]_i_3
(.I0(\instruction[21]_i_6_n_0 ),
.I1(\instruction[21]_i_7_n_0 ),
.O(\instruction_reg[21]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[22]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[22]_i_1_n_0 ),
.Q(address_z[2]),
.R(1'b0));
MUXF8 \instruction_reg[22]_i_1
(.I0(\instruction_reg[22]_i_2_n_0 ),
.I1(\instruction_reg[22]_i_3_n_0 ),
.O(\instruction_reg[22]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[22]_i_2
(.I0(\instruction[22]_i_4_n_0 ),
.I1(\instruction[22]_i_5_n_0 ),
.O(\instruction_reg[22]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[22]_i_3
(.I0(\instruction[22]_i_6_n_0 ),
.I1(\instruction[22]_i_7_n_0 ),
.O(\instruction_reg[22]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[23]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[23]_i_1_n_0 ),
.Q(address_z[3]),
.R(1'b0));
MUXF8 \instruction_reg[23]_i_1
(.I0(\instruction_reg[23]_i_2_n_0 ),
.I1(\instruction_reg[23]_i_3_n_0 ),
.O(\instruction_reg[23]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[23]_i_2
(.I0(\instruction[23]_i_4_n_0 ),
.I1(\instruction[23]_i_5_n_0 ),
.O(\instruction_reg[23]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[23]_i_3
(.I0(\instruction[23]_i_6_n_0 ),
.I1(\instruction[23]_i_7_n_0 ),
.O(\instruction_reg[23]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[24]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[24]_i_1_n_0 ),
.Q(opcode[0]),
.R(1'b0));
MUXF8 \instruction_reg[24]_i_1
(.I0(\instruction_reg[24]_i_2_n_0 ),
.I1(\instruction_reg[24]_i_3_n_0 ),
.O(\instruction_reg[24]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[24]_i_2
(.I0(\instruction[24]_i_4_n_0 ),
.I1(\instruction[24]_i_5_n_0 ),
.O(\instruction_reg[24]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[24]_i_3
(.I0(\instruction[24]_i_6_n_0 ),
.I1(\instruction[24]_i_7_n_0 ),
.O(\instruction_reg[24]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[25]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[25]_i_1_n_0 ),
.Q(opcode[1]),
.R(1'b0));
MUXF8 \instruction_reg[25]_i_1
(.I0(\instruction_reg[25]_i_2_n_0 ),
.I1(\instruction_reg[25]_i_3_n_0 ),
.O(\instruction_reg[25]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[25]_i_2
(.I0(\instruction[25]_i_4_n_0 ),
.I1(\instruction[25]_i_5_n_0 ),
.O(\instruction_reg[25]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[25]_i_3
(.I0(\instruction[25]_i_6_n_0 ),
.I1(\instruction[25]_i_7_n_0 ),
.O(\instruction_reg[25]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[26]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[26]_i_1_n_0 ),
.Q(opcode[2]),
.R(1'b0));
MUXF8 \instruction_reg[26]_i_1
(.I0(\instruction_reg[26]_i_2_n_0 ),
.I1(\instruction_reg[26]_i_3_n_0 ),
.O(\instruction_reg[26]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[26]_i_2
(.I0(\instruction[26]_i_4_n_0 ),
.I1(\instruction[26]_i_5_n_0 ),
.O(\instruction_reg[26]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[26]_i_3
(.I0(\instruction[26]_i_6_n_0 ),
.I1(\instruction[26]_i_7_n_0 ),
.O(\instruction_reg[26]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[27]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[27]_i_1_n_0 ),
.Q(opcode[3]),
.R(1'b0));
MUXF7 \instruction_reg[27]_i_1
(.I0(\instruction[27]_i_2_n_0 ),
.I1(\instruction[27]_i_3_n_0 ),
.O(\instruction_reg[27]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
FDRE \instruction_reg[2]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[2]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[2] ),
.R(1'b0));
MUXF8 \instruction_reg[2]_i_1
(.I0(\instruction_reg[2]_i_2_n_0 ),
.I1(\instruction_reg[2]_i_3_n_0 ),
.O(\instruction_reg[2]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[2]_i_2
(.I0(\instruction[2]_i_4_n_0 ),
.I1(\instruction[2]_i_5_n_0 ),
.O(\instruction_reg[2]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[2]_i_3
(.I0(\instruction[2]_i_6_n_0 ),
.I1(\instruction[2]_i_7_n_0 ),
.O(\instruction_reg[2]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[3]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[3]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[3] ),
.R(1'b0));
MUXF8 \instruction_reg[3]_i_1
(.I0(\instruction_reg[3]_i_2_n_0 ),
.I1(\instruction_reg[3]_i_3_n_0 ),
.O(\instruction_reg[3]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[3]_i_2
(.I0(\instruction[3]_i_4_n_0 ),
.I1(\instruction[3]_i_5_n_0 ),
.O(\instruction_reg[3]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[3]_i_3
(.I0(\instruction[3]_i_6_n_0 ),
.I1(\instruction[3]_i_7_n_0 ),
.O(\instruction_reg[3]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[4]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction[4]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[4] ),
.R(1'b0));
MUXF7 \instruction_reg[4]_i_2
(.I0(\instruction[4]_i_5_n_0 ),
.I1(\instruction[4]_i_6_n_0 ),
.O(\instruction_reg[4]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[5]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[5]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[5] ),
.R(1'b0));
MUXF8 \instruction_reg[5]_i_1
(.I0(\instruction_reg[5]_i_2_n_0 ),
.I1(\instruction_reg[5]_i_3_n_0 ),
.O(\instruction_reg[5]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[5]_i_2
(.I0(\instruction[5]_i_4_n_0 ),
.I1(\instruction[5]_i_5_n_0 ),
.O(\instruction_reg[5]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[5]_i_3
(.I0(\instruction[5]_i_6_n_0 ),
.I1(\instruction[5]_i_7_n_0 ),
.O(\instruction_reg[5]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[6]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[6]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[6] ),
.R(1'b0));
MUXF8 \instruction_reg[6]_i_1
(.I0(\instruction_reg[6]_i_2_n_0 ),
.I1(\instruction_reg[6]_i_3_n_0 ),
.O(\instruction_reg[6]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[6]_i_2
(.I0(\instruction[6]_i_4_n_0 ),
.I1(\instruction[6]_i_5_n_0 ),
.O(\instruction_reg[6]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[6]_i_3
(.I0(\instruction[6]_i_6_n_0 ),
.I1(\instruction[6]_i_7_n_0 ),
.O(\instruction_reg[6]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \instruction_reg[7]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\instruction_reg[7]_i_1_n_0 ),
.Q(\instruction_reg_n_0_[7] ),
.R(1'b0));
MUXF8 \instruction_reg[7]_i_1
(.I0(\instruction_reg[7]_i_2_n_0 ),
.I1(\instruction_reg[7]_i_3_n_0 ),
.O(\instruction_reg[7]_i_1_n_0 ),
.S(\program_counter_reg_rep_n_0_[0] ));
MUXF7 \instruction_reg[7]_i_2
(.I0(\instruction[7]_i_4_n_0 ),
.I1(\instruction[7]_i_5_n_0 ),
.O(\instruction_reg[7]_i_2_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
MUXF7 \instruction_reg[7]_i_3
(.I0(\instruction[7]_i_6_n_0 ),
.I1(\instruction[7]_i_7_n_0 ),
.O(\instruction_reg[7]_i_3_n_0 ),
.S(\program_counter_reg_rep_n_0_[1] ));
FDRE \literal_2_reg[15]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[15] ),
.Q(literal_2[15]),
.R(1'b0));
FDRE \literal_2_reg[4]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[4] ),
.Q(literal_2[4]),
.R(1'b0));
FDRE \literal_2_reg[5]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[5] ),
.Q(literal_2[5]),
.R(1'b0));
FDRE \literal_2_reg[6]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[6] ),
.Q(literal_2[6]),
.R(1'b0));
FDRE \literal_2_reg[7]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(\instruction_reg_n_0_[7] ),
.Q(literal_2[7]),
.R(1'b0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "3" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_0
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_0_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_0_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_0_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[3:0]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_0_DOADO_UNCONNECTED[31:4],load_data[3:0]}),
.DOBDO(NLW_memory_reg_0_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_0_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_0_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_0_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_0_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_0_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_0_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_0_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_0_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_0_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000000000800))
memory_reg_0_i_1
(.I0(\state_reg_n_0_[0] ),
.I1(opcode_20),
.I2(opcode_2[3]),
.I3(opcode_2[1]),
.I4(opcode_2[2]),
.I5(opcode_2[0]),
.O(p_0_in));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "4" *)
(* bram_slice_end = "7" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_1
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_1_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_1_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_1_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[7:4]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_1_DOADO_UNCONNECTED[31:4],load_data[7:4]}),
.DOBDO(NLW_memory_reg_1_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_1_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_1_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_1_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_1_ENARDEN_cooolgate_en_sig_1),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_1_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_1_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_1_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_1_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_1_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_1_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff01))
memory_reg_1_ENARDEN_cooolgate_en_gate_1
(.I0(\state[1]_i_1_n_0 ),
.I1(\state[0]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_1_ENARDEN_cooolgate_en_sig_1));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "8" *)
(* bram_slice_end = "11" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_2
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_2_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_2_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_2_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[11:8]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_2_DOADO_UNCONNECTED[31:4],load_data[11:8]}),
.DOBDO(NLW_memory_reg_2_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_2_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_2_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_2_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_2_ENARDEN_cooolgate_en_sig_2),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_2_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_2_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_2_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_2_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_2_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_2_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff01))
memory_reg_2_ENARDEN_cooolgate_en_gate_3
(.I0(\state[1]_i_1_n_0 ),
.I1(\state[0]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_2_ENARDEN_cooolgate_en_sig_2));
LUT3 #(
.INIT(8'hB8))
memory_reg_2_i_1
(.I0(result[11]),
.I1(operand_b1),
.I2(register_b[11]),
.O(store_data[11]));
LUT3 #(
.INIT(8'hB8))
memory_reg_2_i_2
(.I0(result[10]),
.I1(operand_b1),
.I2(register_b[10]),
.O(store_data[10]));
LUT3 #(
.INIT(8'hB8))
memory_reg_2_i_3
(.I0(result[9]),
.I1(operand_b1),
.I2(register_b[9]),
.O(store_data[9]));
LUT3 #(
.INIT(8'hB8))
memory_reg_2_i_4
(.I0(result[8]),
.I1(operand_b1),
.I2(register_b[8]),
.O(store_data[8]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "12" *)
(* bram_slice_end = "15" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_3
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_3_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_3_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_3_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[15:12]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_3_DOADO_UNCONNECTED[31:4],load_data[15:12]}),
.DOBDO(NLW_memory_reg_3_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_3_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_3_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_3_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_3_ENARDEN_cooolgate_en_sig_3),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_3_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_3_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_3_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_3_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_3_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_3_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff01))
memory_reg_3_ENARDEN_cooolgate_en_gate_5
(.I0(\state[1]_i_1_n_0 ),
.I1(\state[0]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_3_ENARDEN_cooolgate_en_sig_3));
LUT3 #(
.INIT(8'hB8))
memory_reg_3_i_1
(.I0(result[15]),
.I1(operand_b1),
.I2(register_b[15]),
.O(store_data[15]));
LUT3 #(
.INIT(8'hB8))
memory_reg_3_i_2
(.I0(result[14]),
.I1(operand_b1),
.I2(register_b[14]),
.O(store_data[14]));
LUT3 #(
.INIT(8'hB8))
memory_reg_3_i_3
(.I0(result[13]),
.I1(operand_b1),
.I2(register_b[13]),
.O(store_data[13]));
LUT3 #(
.INIT(8'hB8))
memory_reg_3_i_4
(.I0(result[12]),
.I1(operand_b1),
.I2(register_b[12]),
.O(store_data[12]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "16" *)
(* bram_slice_end = "19" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_4
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_4_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_4_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_4_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[19:16]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_4_DOADO_UNCONNECTED[31:4],load_data[19:16]}),
.DOBDO(NLW_memory_reg_4_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_4_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_4_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_4_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_4_ENARDEN_cooolgate_en_sig_4),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_4_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_4_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_4_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_4_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_4_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_4_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff01))
memory_reg_4_ENARDEN_cooolgate_en_gate_7
(.I0(\state[1]_i_1_n_0 ),
.I1(\state[0]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_4_ENARDEN_cooolgate_en_sig_4));
LUT3 #(
.INIT(8'hB8))
memory_reg_4_i_1
(.I0(result[19]),
.I1(operand_b1),
.I2(register_b[19]),
.O(store_data[19]));
LUT3 #(
.INIT(8'hB8))
memory_reg_4_i_2
(.I0(result[18]),
.I1(operand_b1),
.I2(register_b[18]),
.O(store_data[18]));
LUT3 #(
.INIT(8'hB8))
memory_reg_4_i_3
(.I0(result[17]),
.I1(operand_b1),
.I2(register_b[17]),
.O(store_data[17]));
LUT3 #(
.INIT(8'hB8))
memory_reg_4_i_4
(.I0(result[16]),
.I1(operand_b1),
.I2(register_b[16]),
.O(store_data[16]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "20" *)
(* bram_slice_end = "23" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_5
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_5_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_5_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_5_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[23:20]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_5_DOADO_UNCONNECTED[31:4],load_data[23:20]}),
.DOBDO(NLW_memory_reg_5_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_5_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_5_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_5_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_5_ENARDEN_cooolgate_en_sig_5),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_5_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_5_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_5_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_5_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_5_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_5_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff01))
memory_reg_5_ENARDEN_cooolgate_en_gate_9
(.I0(\state[1]_i_1_n_0 ),
.I1(\state[0]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_5_ENARDEN_cooolgate_en_sig_5));
LUT3 #(
.INIT(8'hB8))
memory_reg_5_i_1
(.I0(result[23]),
.I1(operand_b1),
.I2(register_b[23]),
.O(store_data[23]));
LUT3 #(
.INIT(8'hB8))
memory_reg_5_i_2
(.I0(result[22]),
.I1(operand_b1),
.I2(register_b[22]),
.O(store_data[22]));
LUT3 #(
.INIT(8'hB8))
memory_reg_5_i_3
(.I0(result[21]),
.I1(operand_b1),
.I2(register_b[21]),
.O(store_data[21]));
LUT3 #(
.INIT(8'hB8))
memory_reg_5_i_4
(.I0(result[20]),
.I1(operand_b1),
.I2(register_b[20]),
.O(store_data[20]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "24" *)
(* bram_slice_end = "27" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_6
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_6_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_6_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_6_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[27:24]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_6_DOADO_UNCONNECTED[31:4],load_data[27:24]}),
.DOBDO(NLW_memory_reg_6_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_6_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_6_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_6_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_6_ENARDEN_cooolgate_en_sig_6),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_6_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_6_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_6_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_6_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_6_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_6_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff01))
memory_reg_6_ENARDEN_cooolgate_en_gate_11
(.I0(\state[1]_i_1_n_0 ),
.I1(\state[0]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_6_ENARDEN_cooolgate_en_sig_6));
LUT3 #(
.INIT(8'hB8))
memory_reg_6_i_1
(.I0(result[27]),
.I1(operand_b1),
.I2(register_b[27]),
.O(store_data[27]));
LUT3 #(
.INIT(8'hB8))
memory_reg_6_i_2
(.I0(result[26]),
.I1(operand_b1),
.I2(register_b[26]),
.O(store_data[26]));
LUT3 #(
.INIT(8'hB8))
memory_reg_6_i_3
(.I0(result[25]),
.I1(operand_b1),
.I2(register_b[25]),
.O(store_data[25]));
LUT3 #(
.INIT(8'hB8))
memory_reg_6_i_4
(.I0(result[24]),
.I1(operand_b1),
.I2(register_b[24]),
.O(store_data[24]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "28" *)
(* bram_slice_end = "31" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_7
(.ADDRARDADDR({1'b1,\write_output[12]_i_1_n_0 ,\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 ,\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 ,\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\write_output[1]_i_1_n_0 ,\write_output[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_7_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_7_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_7_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[31:28]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_7_DOADO_UNCONNECTED[31:4],load_data[31:28]}),
.DOBDO(NLW_memory_reg_7_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_7_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_7_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_7_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_7_ENARDEN_cooolgate_en_sig_7),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_7_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_7_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_7_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_7_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_7_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_7_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff01))
memory_reg_7_ENARDEN_cooolgate_en_gate_13
(.I0(\state[1]_i_1_n_0 ),
.I1(\state[0]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_7_ENARDEN_cooolgate_en_sig_7));
LUT3 #(
.INIT(8'hB8))
memory_reg_7_i_1
(.I0(result[31]),
.I1(operand_b1),
.I2(register_b[31]),
.O(store_data[31]));
LUT3 #(
.INIT(8'hB8))
memory_reg_7_i_2
(.I0(result[30]),
.I1(operand_b1),
.I2(register_b[30]),
.O(store_data[30]));
LUT3 #(
.INIT(8'hB8))
memory_reg_7_i_3
(.I0(result[29]),
.I1(operand_b1),
.I2(register_b[29]),
.O(store_data[29]));
LUT3 #(
.INIT(8'hB8))
memory_reg_7_i_4
(.I0(result[28]),
.I1(operand_b1),
.I2(register_b[28]),
.O(store_data[28]));
LUT2 #(
.INIT(4'h2))
\opcode_2[3]_i_1
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[2] ),
.O(opcode_20));
FDRE \opcode_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[0]),
.Q(opcode_2[0]),
.R(1'b0));
FDRE \opcode_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[1]),
.Q(opcode_2[1]),
.R(1'b0));
FDRE \opcode_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[2]),
.Q(opcode_2[2]),
.R(1'b0));
FDRE \opcode_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[3]),
.Q(opcode_2[3]),
.R(1'b0));
LUT5 #(
.INIT(32'hFF4F4444))
\program_counter[10]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[10]),
.I2(opcode_2[2]),
.I3(\write_output[10]_i_1_n_0 ),
.I4(\program_counter[14]_i_2_n_0 ),
.O(\program_counter[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFF4F4444))
\program_counter[11]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[11]),
.I2(opcode_2[2]),
.I3(\write_output[11]_i_1_n_0 ),
.I4(\program_counter[14]_i_2_n_0 ),
.O(\program_counter[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFF4F4444))
\program_counter[12]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[12]),
.I2(opcode_2[2]),
.I3(\write_output[12]_i_1_n_0 ),
.I4(\program_counter[14]_i_2_n_0 ),
.O(\program_counter[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFF4F4444))
\program_counter[13]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[13]),
.I2(opcode_2[2]),
.I3(\write_output[13]_i_1_n_0 ),
.I4(\program_counter[14]_i_2_n_0 ),
.O(\program_counter[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFF4F4444))
\program_counter[14]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[14]),
.I2(opcode_2[2]),
.I3(\write_output[14]_i_1_n_0 ),
.I4(\program_counter[14]_i_2_n_0 ),
.O(\program_counter[14]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAA80808088))
\program_counter[14]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(literal_2[15]),
.I2(opcode_2[1]),
.I3(\program_counter_rep[7]_i_10_n_0 ),
.I4(\program_counter[14]_i_3_n_0 ),
.I5(opcode_2[2]),
.O(\program_counter[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter[14]_i_3
(.I0(\state[2]_i_12_n_0 ),
.I1(\state[2]_i_11_n_0 ),
.I2(\program_counter_rep[7]_i_25_n_0 ),
.I3(\program_counter_rep[7]_i_24_n_0 ),
.I4(\program_counter_rep[7]_i_23_n_0 ),
.I5(\state[2]_i_9_n_0 ),
.O(\program_counter[14]_i_3_n_0 ));
LUT6 #(
.INIT(64'hE2AAE2AAF3AAC0AA))
\program_counter[15]_i_1
(.I0(data1[15]),
.I1(opcode_2[2]),
.I2(\write_output[15]_i_1_n_0 ),
.I3(\program_counter[15]_i_3_n_0 ),
.I4(literal_2[15]),
.I5(\program_counter_rep[7]_i_5_n_0 ),
.O(\program_counter[15]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0008000808800000))
\program_counter[15]_i_3
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[0]),
.I3(opcode_2[2]),
.I4(opcode_2[1]),
.I5(opcode_2[3]),
.O(\program_counter[15]_i_3_n_0 ));
LUT5 #(
.INIT(32'hFF4F4444))
\program_counter[8]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[8]),
.I2(opcode_2[2]),
.I3(\write_output[8]_i_1_n_0 ),
.I4(\program_counter[14]_i_2_n_0 ),
.O(\program_counter[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFF4F4444))
\program_counter[9]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[9]),
.I2(opcode_2[2]),
.I3(\write_output[9]_i_1_n_0 ),
.I4(\program_counter[14]_i_2_n_0 ),
.O(\program_counter[9]_i_1_n_0 ));
FDRE \program_counter_1_reg[0]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[0] ),
.Q(program_counter_1[0]),
.R(1'b0));
FDRE \program_counter_1_reg[10]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[10] ),
.Q(program_counter_1[10]),
.R(1'b0));
FDRE \program_counter_1_reg[11]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[11] ),
.Q(program_counter_1[11]),
.R(1'b0));
FDRE \program_counter_1_reg[12]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[12] ),
.Q(program_counter_1[12]),
.R(1'b0));
FDRE \program_counter_1_reg[13]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[13] ),
.Q(program_counter_1[13]),
.R(1'b0));
FDRE \program_counter_1_reg[14]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[14] ),
.Q(program_counter_1[14]),
.R(1'b0));
FDRE \program_counter_1_reg[15]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[15] ),
.Q(program_counter_1[15]),
.R(1'b0));
FDRE \program_counter_1_reg[1]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[1] ),
.Q(program_counter_1[1]),
.R(1'b0));
FDRE \program_counter_1_reg[2]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[2] ),
.Q(program_counter_1[2]),
.R(1'b0));
FDRE \program_counter_1_reg[3]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[3] ),
.Q(program_counter_1[3]),
.R(1'b0));
FDRE \program_counter_1_reg[4]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[4] ),
.Q(program_counter_1[4]),
.R(1'b0));
FDRE \program_counter_1_reg[5]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[5] ),
.Q(program_counter_1[5]),
.R(1'b0));
FDRE \program_counter_1_reg[6]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[6] ),
.Q(program_counter_1[6]),
.R(1'b0));
FDRE \program_counter_1_reg[7]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[7] ),
.Q(program_counter_1[7]),
.R(1'b0));
FDRE \program_counter_1_reg[8]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[8] ),
.Q(program_counter_1[8]),
.R(1'b0));
FDRE \program_counter_1_reg[9]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[9] ),
.Q(program_counter_1[9]),
.R(1'b0));
FDRE \program_counter_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[0]),
.Q(program_counter_2[0]),
.R(1'b0));
FDRE \program_counter_2_reg[10]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[10]),
.Q(program_counter_2[10]),
.R(1'b0));
FDRE \program_counter_2_reg[11]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[11]),
.Q(program_counter_2[11]),
.R(1'b0));
FDRE \program_counter_2_reg[12]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[12]),
.Q(program_counter_2[12]),
.R(1'b0));
FDRE \program_counter_2_reg[13]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[13]),
.Q(program_counter_2[13]),
.R(1'b0));
FDRE \program_counter_2_reg[14]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[14]),
.Q(program_counter_2[14]),
.R(1'b0));
FDRE \program_counter_2_reg[15]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[15]),
.Q(program_counter_2[15]),
.R(1'b0));
FDRE \program_counter_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[1]),
.Q(program_counter_2[1]),
.R(1'b0));
FDRE \program_counter_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[2]),
.Q(program_counter_2[2]),
.R(1'b0));
FDRE \program_counter_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[3]),
.Q(program_counter_2[3]),
.R(1'b0));
FDRE \program_counter_2_reg[4]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[4]),
.Q(program_counter_2[4]),
.R(1'b0));
FDRE \program_counter_2_reg[5]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[5]),
.Q(program_counter_2[5]),
.R(1'b0));
FDRE \program_counter_2_reg[6]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[6]),
.Q(program_counter_2[6]),
.R(1'b0));
FDRE \program_counter_2_reg[7]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[7]),
.Q(program_counter_2[7]),
.R(1'b0));
FDRE \program_counter_2_reg[8]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[8]),
.Q(program_counter_2[8]),
.R(1'b0));
FDRE \program_counter_2_reg[9]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[9]),
.Q(program_counter_2[9]),
.R(1'b0));
FDRE \program_counter_reg[0]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[0]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[10]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[10]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[10] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[11]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[11]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[11] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[12]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[12]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[12] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg[12]_i_2
(.CI(\program_counter_reg_rep[7]_i_4_n_0 ),
.CO({\program_counter_reg[12]_i_2_n_0 ,\NLW_program_counter_reg[12]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data1[12:9]),
.S({\program_counter_reg_n_0_[12] ,\program_counter_reg_n_0_[11] ,\program_counter_reg_n_0_[10] ,\program_counter_reg_n_0_[9] }));
FDRE \program_counter_reg[13]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[13]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[13] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[14]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[14]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[14] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[15]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[15]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[15] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg[15]_i_2
(.CI(\program_counter_reg[12]_i_2_n_0 ),
.CO(\NLW_program_counter_reg[15]_i_2_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_program_counter_reg[15]_i_2_O_UNCONNECTED [3],data1[15:13]}),
.S({1'b0,\program_counter_reg_n_0_[15] ,\program_counter_reg_n_0_[14] ,\program_counter_reg_n_0_[13] }));
FDRE \program_counter_reg[1]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[1]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[2]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[2]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[3]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[3]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[4]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[4]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[5]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[5]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[5] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[6]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[6]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[6] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[7]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[7]_i_2_n_0 ),
.Q(\program_counter_reg_n_0_[7] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[8]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[8]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[8] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[9]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter[9]_i_1_n_0 ),
.Q(\program_counter_reg_n_0_[9] ),
.R(INTERNAL_RST_reg));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[0]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[0]_i_1_n_0 ),
.Q(\program_counter_reg_rep_n_0_[0] ),
.R(INTERNAL_RST_reg));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[1]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[1]_i_1_n_0 ),
.Q(\program_counter_reg_rep_n_0_[1] ),
.R(INTERNAL_RST_reg));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[2]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[2]_i_1_n_0 ),
.Q(\program_counter_reg_rep_n_0_[2] ),
.R(INTERNAL_RST_reg));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[3]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[3]_i_1_n_0 ),
.Q(\program_counter_reg_rep_n_0_[3] ),
.R(INTERNAL_RST_reg));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[4]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[4]_i_1_n_0 ),
.Q(\program_counter_reg_rep_n_0_[4] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg_rep[4]_i_2
(.CI(1'b0),
.CO({\program_counter_reg_rep[4]_i_2_n_0 ,\NLW_program_counter_reg_rep[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(\program_counter_reg_n_0_[0] ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data1[4:1]),
.S({\program_counter_reg_n_0_[4] ,\program_counter_reg_n_0_[3] ,\program_counter_reg_n_0_[2] ,\program_counter_reg_n_0_[1] }));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[5]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[5]_i_1_n_0 ),
.Q(\program_counter_reg_rep_n_0_[5] ),
.R(INTERNAL_RST_reg));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[6]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[6]_i_1_n_0 ),
.Q(\program_counter_reg_rep_n_0_[6] ),
.R(INTERNAL_RST_reg));
(* equivalent_register_removal = "no" *)
FDRE \program_counter_reg_rep[7]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_rep[7]_i_2_n_0 ),
.Q(\program_counter_reg_rep_n_0_[7] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg_rep[7]_i_4
(.CI(\program_counter_reg_rep[4]_i_2_n_0 ),
.CO({\program_counter_reg_rep[7]_i_4_n_0 ,\NLW_program_counter_reg_rep[7]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data1[8:5]),
.S({\program_counter_reg_n_0_[8] ,\program_counter_reg_n_0_[7] ,\program_counter_reg_n_0_[6] ,\program_counter_reg_n_0_[5] }));
LUT6 #(
.INIT(64'hF1FFF1F111111111))
\program_counter_rep[0]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(\program_counter_reg_n_0_[0] ),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(address_b_2[0]),
.I5(\program_counter_rep[0]_i_2_n_0 ),
.O(\program_counter_rep[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[0]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[0]),
.I2(operand_a1),
.I3(register_a[0]),
.I4(opcode_2[2]),
.O(\program_counter_rep[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4F444444444))
\program_counter_rep[1]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[1]),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(address_b_2[1]),
.I5(\program_counter_rep[1]_i_2_n_0 ),
.O(\program_counter_rep[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[1]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[1]),
.I2(operand_a1),
.I3(register_a[1]),
.I4(opcode_2[2]),
.O(\program_counter_rep[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4F444444444))
\program_counter_rep[2]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[2]),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(address_b_2[2]),
.I5(\program_counter_rep[2]_i_2_n_0 ),
.O(\program_counter_rep[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[2]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[2]),
.I2(operand_a1),
.I3(register_a[2]),
.I4(opcode_2[2]),
.O(\program_counter_rep[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4F444444444))
\program_counter_rep[3]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[3]),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(address_b_2[3]),
.I5(\program_counter_rep[3]_i_2_n_0 ),
.O(\program_counter_rep[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[3]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[3]),
.I2(operand_a1),
.I3(register_a[3]),
.I4(opcode_2[2]),
.O(\program_counter_rep[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4F444444444))
\program_counter_rep[4]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[4]),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(literal_2[4]),
.I5(\program_counter_rep[4]_i_3_n_0 ),
.O(\program_counter_rep[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[4]_i_3
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[4]),
.I2(operand_a1),
.I3(register_a[4]),
.I4(opcode_2[2]),
.O(\program_counter_rep[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4F444444444))
\program_counter_rep[5]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[5]),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(literal_2[5]),
.I5(\program_counter_rep[5]_i_2_n_0 ),
.O(\program_counter_rep[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[5]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[5]),
.I2(operand_a1),
.I3(register_a[5]),
.I4(opcode_2[2]),
.O(\program_counter_rep[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4F444444444))
\program_counter_rep[6]_i_1
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[6]),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(literal_2[6]),
.I5(\program_counter_rep[6]_i_2_n_0 ),
.O(\program_counter_rep[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[6]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[6]),
.I2(operand_a1),
.I3(register_a[6]),
.I4(opcode_2[2]),
.O(\program_counter_rep[6]_i_2_n_0 ));
LUT3 #(
.INIT(8'h32))
\program_counter_rep[7]_i_1
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[0] ),
.O(instruction0));
LUT5 #(
.INIT(32'hFFFFFFFE))
\program_counter_rep[7]_i_10
(.I0(\write_output[1]_i_1_n_0 ),
.I1(\write_output[0]_i_1_n_0 ),
.I2(\program_counter_rep[7]_i_26_n_0 ),
.I3(\write_output[2]_i_1_n_0 ),
.I4(\write_output[3]_i_1_n_0 ),
.O(\program_counter_rep[7]_i_10_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter_rep[7]_i_15
(.I0(\write_output[3]_i_1_n_0 ),
.I1(\write_output[2]_i_1_n_0 ),
.I2(\write_output[6]_i_1_n_0 ),
.I3(\write_output[7]_i_1_n_0 ),
.I4(\write_output[4]_i_1_n_0 ),
.I5(\write_output[5]_i_1_n_0 ),
.O(\program_counter_rep[7]_i_15_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEFFFEEE))
\program_counter_rep[7]_i_16
(.I0(\write_output[11]_i_1_n_0 ),
.I1(\write_output[10]_i_1_n_0 ),
.I2(result[13]),
.I3(operand_a1),
.I4(register_a[13]),
.I5(\write_output[12]_i_1_n_0 ),
.O(\program_counter_rep[7]_i_16_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_17
(.I0(register_a[16]),
.I1(result[16]),
.I2(register_a[17]),
.I3(operand_a1),
.I4(result[17]),
.O(\program_counter_rep[7]_i_17_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_18
(.I0(register_a[18]),
.I1(result[18]),
.I2(register_a[19]),
.I3(operand_a1),
.I4(result[19]),
.O(\program_counter_rep[7]_i_18_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_19
(.I0(register_a[14]),
.I1(result[14]),
.I2(register_a[15]),
.I3(operand_a1),
.I4(result[15]),
.O(\program_counter_rep[7]_i_19_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4F444444444))
\program_counter_rep[7]_i_2
(.I0(\program_counter_rep[7]_i_3_n_0 ),
.I1(data1[7]),
.I2(opcode_2[2]),
.I3(\program_counter_rep[7]_i_5_n_0 ),
.I4(literal_2[7]),
.I5(\program_counter_rep[7]_i_6_n_0 ),
.O(\program_counter_rep[7]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_20
(.I0(register_a[22]),
.I1(result[22]),
.I2(register_a[23]),
.I3(operand_a1),
.I4(result[23]),
.O(\program_counter_rep[7]_i_20_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_21
(.I0(register_a[24]),
.I1(result[24]),
.I2(register_a[25]),
.I3(operand_a1),
.I4(result[25]),
.O(\program_counter_rep[7]_i_21_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_22
(.I0(register_a[20]),
.I1(result[20]),
.I2(register_a[21]),
.I3(operand_a1),
.I4(result[21]),
.O(\program_counter_rep[7]_i_22_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_23
(.I0(register_a[28]),
.I1(result[28]),
.I2(register_a[29]),
.I3(operand_a1),
.I4(result[29]),
.O(\program_counter_rep[7]_i_23_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_24
(.I0(register_a[30]),
.I1(result[30]),
.I2(register_a[31]),
.I3(operand_a1),
.I4(result[31]),
.O(\program_counter_rep[7]_i_24_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter_rep[7]_i_25
(.I0(register_a[26]),
.I1(result[26]),
.I2(register_a[27]),
.I3(operand_a1),
.I4(result[27]),
.O(\program_counter_rep[7]_i_25_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEFEA))
\program_counter_rep[7]_i_26
(.I0(\write_output[5]_i_1_n_0 ),
.I1(result[4]),
.I2(operand_a1),
.I3(register_a[4]),
.I4(\write_output[7]_i_1_n_0 ),
.I5(\write_output[6]_i_1_n_0 ),
.O(\program_counter_rep[7]_i_26_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAA8888888A))
\program_counter_rep[7]_i_3
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_rep[7]_i_7_n_0 ),
.I2(\program_counter_rep[7]_i_8_n_0 ),
.I3(\program_counter_rep[7]_i_9_n_0 ),
.I4(\program_counter_rep[7]_i_10_n_0 ),
.I5(opcode_2[1]),
.O(\program_counter_rep[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFFFFFE))
\program_counter_rep[7]_i_5
(.I0(\program_counter_rep[7]_i_8_n_0 ),
.I1(\program_counter_rep[7]_i_9_n_0 ),
.I2(\write_output[1]_i_1_n_0 ),
.I3(\write_output[0]_i_1_n_0 ),
.I4(\program_counter_rep[7]_i_15_n_0 ),
.I5(opcode_2[1]),
.O(\program_counter_rep[7]_i_5_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\program_counter_rep[7]_i_6
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(result[7]),
.I2(operand_a1),
.I3(register_a[7]),
.I4(opcode_2[2]),
.O(\program_counter_rep[7]_i_6_n_0 ));
LUT4 #(
.INIT(16'h02A2))
\program_counter_rep[7]_i_7
(.I0(opcode_2[2]),
.I1(register_a[15]),
.I2(operand_a1),
.I3(result[15]),
.O(\program_counter_rep[7]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter_rep[7]_i_8
(.I0(\program_counter_rep[7]_i_16_n_0 ),
.I1(\write_output[8]_i_1_n_0 ),
.I2(\write_output[9]_i_1_n_0 ),
.I3(\program_counter_rep[7]_i_17_n_0 ),
.I4(\program_counter_rep[7]_i_18_n_0 ),
.I5(\program_counter_rep[7]_i_19_n_0 ),
.O(\program_counter_rep[7]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter_rep[7]_i_9
(.I0(\program_counter_rep[7]_i_20_n_0 ),
.I1(\program_counter_rep[7]_i_21_n_0 ),
.I2(\program_counter_rep[7]_i_22_n_0 ),
.I3(\program_counter_rep[7]_i_23_n_0 ),
.I4(\program_counter_rep[7]_i_24_n_0 ),
.I5(\program_counter_rep[7]_i_25_n_0 ),
.O(\program_counter_rep[7]_i_9_n_0 ));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_UNIQ_BASE_ registers_reg_r1_0_15_0_5
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[1:0]),
.DIB(result[3:2]),
.DIC(result[5:4]),
.DID({1'b0,1'b0}),
.DOA(register_b[1:0]),
.DOB(register_b[3:2]),
.DOC(register_b[5:4]),
.DOD(NLW_registers_reg_r1_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD5 registers_reg_r1_0_15_12_17
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[13:12]),
.DIB(result[15:14]),
.DIC(result[17:16]),
.DID({1'b0,1'b0}),
.DOA(register_b[13:12]),
.DOB(register_b[15:14]),
.DOC(register_b[17:16]),
.DOD(NLW_registers_reg_r1_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD6 registers_reg_r1_0_15_18_23
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[19:18]),
.DIB(result[21:20]),
.DIC(result[23:22]),
.DID({1'b0,1'b0}),
.DOA(register_b[19:18]),
.DOB(register_b[21:20]),
.DOC(register_b[23:22]),
.DOD(NLW_registers_reg_r1_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD7 registers_reg_r1_0_15_24_29
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[25:24]),
.DIB(result[27:26]),
.DIC(result[29:28]),
.DID({1'b0,1'b0}),
.DOA(register_b[25:24]),
.DOB(register_b[27:26]),
.DOC(register_b[29:28]),
.DOD(NLW_registers_reg_r1_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD8 registers_reg_r1_0_15_30_31
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[31:30]),
.DIB({1'b0,1'b0}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA(register_b[31:30]),
.DOB(NLW_registers_reg_r1_0_15_30_31_DOB_UNCONNECTED[1:0]),
.DOC(NLW_registers_reg_r1_0_15_30_31_DOC_UNCONNECTED[1:0]),
.DOD(NLW_registers_reg_r1_0_15_30_31_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD4 registers_reg_r1_0_15_6_11
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[7:6]),
.DIB(result[9:8]),
.DIC(result[11:10]),
.DID({1'b0,1'b0}),
.DOA(register_b[7:6]),
.DOB(register_b[9:8]),
.DOC(register_b[11:10]),
.DOD(NLW_registers_reg_r1_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD9 registers_reg_r2_0_15_0_5
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[1:0]),
.DIB(result[3:2]),
.DIC(result[5:4]),
.DID({1'b0,1'b0}),
.DOA(register_a[1:0]),
.DOB(register_a[3:2]),
.DOC(register_a[5:4]),
.DOD(NLW_registers_reg_r2_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD11 registers_reg_r2_0_15_12_17
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[13:12]),
.DIB(result[15:14]),
.DIC(result[17:16]),
.DID({1'b0,1'b0}),
.DOA(register_a[13:12]),
.DOB(register_a[15:14]),
.DOC(register_a[17:16]),
.DOD(NLW_registers_reg_r2_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD12 registers_reg_r2_0_15_18_23
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[19:18]),
.DIB(result[21:20]),
.DIC(result[23:22]),
.DID({1'b0,1'b0}),
.DOA(register_a[19:18]),
.DOB(register_a[21:20]),
.DOC(register_a[23:22]),
.DOD(NLW_registers_reg_r2_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD13 registers_reg_r2_0_15_24_29
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[25:24]),
.DIB(result[27:26]),
.DIC(result[29:28]),
.DID({1'b0,1'b0}),
.DOA(register_a[25:24]),
.DOB(register_a[27:26]),
.DOC(register_a[29:28]),
.DOD(NLW_registers_reg_r2_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD14 registers_reg_r2_0_15_30_31
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[31:30]),
.DIB({1'b0,1'b0}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA(register_a[31:30]),
.DOB(NLW_registers_reg_r2_0_15_30_31_DOB_UNCONNECTED[1:0]),
.DOC(NLW_registers_reg_r2_0_15_30_31_DOC_UNCONNECTED[1:0]),
.DOD(NLW_registers_reg_r2_0_15_30_31_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD10 registers_reg_r2_0_15_6_11
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[7:6]),
.DIB(result[9:8]),
.DIC(result[11:10]),
.DID({1'b0,1'b0}),
.DOA(register_a[7:6]),
.DOB(register_a[9:8]),
.DOC(register_a[11:10]),
.DOD(NLW_registers_reg_r2_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\result[0]_i_1
(.I0(\result[0]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[0]),
.O(\result[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hA0A0AFAFCFC0CFC0))
\result[0]_i_2
(.I0(address_b_2[0]),
.I1(\result_reg[3]_i_3_n_7 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data3[0]),
.I4(program_counter_2[0]),
.I5(\result[16]_i_4_n_0 ),
.O(\result[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\result[10]_i_1
(.I0(\result[10]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[10]),
.O(\result[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[10]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[11]_i_3_n_5 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[10]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[10]),
.O(\result[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\result[11]_i_1
(.I0(\result[11]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[11]),
.O(\result[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[11]_i_10
(.I0(register_a[10]),
.I1(operand_a1),
.I2(register_b[10]),
.I3(operand_b1),
.I4(result[10]),
.O(\result[11]_i_10_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[11]_i_11
(.I0(register_a[9]),
.I1(operand_a1),
.I2(register_b[9]),
.I3(operand_b1),
.I4(result[9]),
.O(\result[11]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[11]_i_12
(.I0(register_a[8]),
.I1(operand_a1),
.I2(register_b[8]),
.I3(operand_b1),
.I4(result[8]),
.O(\result[11]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[11]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[11]_i_3_n_4 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[11]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[11]),
.O(\result[11]_i_2_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_5
(.I0(register_a[11]),
.I1(operand_a1),
.I2(result[11]),
.I3(literal_2[15]),
.O(\result[11]_i_5_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_6
(.I0(register_a[10]),
.I1(operand_a1),
.I2(result[10]),
.I3(literal_2[15]),
.O(\result[11]_i_6_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_7
(.I0(register_a[9]),
.I1(operand_a1),
.I2(result[9]),
.I3(literal_2[15]),
.O(\result[11]_i_7_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_8
(.I0(register_a[8]),
.I1(operand_a1),
.I2(result[8]),
.I3(literal_2[15]),
.O(\result[11]_i_8_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[11]_i_9
(.I0(register_a[11]),
.I1(operand_a1),
.I2(register_b[11]),
.I3(operand_b1),
.I4(result[11]),
.O(\result[11]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\result[12]_i_1
(.I0(\result[12]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[12]),
.O(\result[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[12]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[15]_i_3_n_7 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[12]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[12]),
.O(\result[12]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\result[13]_i_1
(.I0(\result[13]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[13]),
.O(\result[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[13]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[15]_i_3_n_6 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[13]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[13]),
.O(\result[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\result[14]_i_1
(.I0(\result[14]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[14]),
.O(\result[14]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[14]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[15]_i_3_n_5 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[14]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[14]),
.O(\result[14]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\result[15]_i_1
(.I0(\result[15]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[15]),
.O(\result[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[15]_i_10
(.I0(register_a[14]),
.I1(operand_a1),
.I2(register_b[14]),
.I3(operand_b1),
.I4(result[14]),
.O(\result[15]_i_10_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[15]_i_11
(.I0(register_a[13]),
.I1(operand_a1),
.I2(register_b[13]),
.I3(operand_b1),
.I4(result[13]),
.O(\result[15]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[15]_i_12
(.I0(register_a[12]),
.I1(operand_a1),
.I2(register_b[12]),
.I3(operand_b1),
.I4(result[12]),
.O(\result[15]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[15]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[15]_i_3_n_4 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[15]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[15]),
.O(\result[15]_i_2_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_5
(.I0(register_a[15]),
.I1(operand_a1),
.I2(result[15]),
.I3(literal_2[15]),
.O(\result[15]_i_5_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_6
(.I0(register_a[14]),
.I1(operand_a1),
.I2(result[14]),
.I3(literal_2[15]),
.O(\result[15]_i_6_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_7
(.I0(register_a[13]),
.I1(operand_a1),
.I2(result[13]),
.I3(literal_2[15]),
.O(\result[15]_i_7_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_8
(.I0(register_a[12]),
.I1(operand_a1),
.I2(result[12]),
.I3(literal_2[15]),
.O(\result[15]_i_8_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[15]_i_9
(.I0(register_a[15]),
.I1(operand_a1),
.I2(register_b[15]),
.I3(operand_b1),
.I4(result[15]),
.O(\result[15]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\result[16]_i_1
(.I0(\result[16]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[16]),
.O(\result[16]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[16]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[19]_i_3_n_7 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[16]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[16]),
.O(\result[16]_i_2_n_0 ));
LUT3 #(
.INIT(8'h45))
\result[16]_i_4
(.I0(opcode_2[2]),
.I1(opcode_2[1]),
.I2(opcode_2[0]),
.O(\result[16]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\result[17]_i_1
(.I0(\result[17]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[17]),
.O(\result[17]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[17]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[19]_i_3_n_6 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[17]),
.I5(opcode_2[0]),
.O(\result[17]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\result[18]_i_1
(.I0(\result[18]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[18]),
.O(\result[18]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[18]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[19]_i_3_n_5 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[18]),
.I5(opcode_2[0]),
.O(\result[18]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\result[19]_i_1
(.I0(\result[19]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[19]),
.O(\result[19]_i_1_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_10
(.I0(register_a[18]),
.I1(operand_a1),
.I2(register_b[18]),
.I3(operand_b1),
.I4(result[18]),
.O(\result[19]_i_10_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_11
(.I0(register_a[17]),
.I1(operand_a1),
.I2(register_b[17]),
.I3(operand_b1),
.I4(result[17]),
.O(\result[19]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_12
(.I0(register_a[16]),
.I1(operand_a1),
.I2(register_b[16]),
.I3(operand_b1),
.I4(result[16]),
.O(\result[19]_i_12_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[19]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[19]_i_3_n_4 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[19]),
.I5(opcode_2[0]),
.O(\result[19]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_5
(.I0(result[19]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[19]),
.O(\result[19]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_6
(.I0(result[18]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[18]),
.O(\result[19]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_7
(.I0(result[17]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[17]),
.O(\result[19]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_8
(.I0(result[16]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[16]),
.O(\result[19]_i_8_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_9
(.I0(register_a[19]),
.I1(operand_a1),
.I2(register_b[19]),
.I3(operand_b1),
.I4(result[19]),
.O(\result[19]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\result[1]_i_1
(.I0(\result[1]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[1]),
.O(\result[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[1]_i_2
(.I0(address_b_2[1]),
.I1(\result_reg[3]_i_3_n_6 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[1]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[1]),
.O(\result[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\result[20]_i_1
(.I0(\result[20]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[20]),
.O(\result[20]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[20]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[23]_i_3_n_7 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[20]),
.I5(opcode_2[0]),
.O(\result[20]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\result[21]_i_1
(.I0(\result[21]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[21]),
.O(\result[21]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[21]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[23]_i_3_n_6 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[21]),
.I5(opcode_2[0]),
.O(\result[21]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\result[22]_i_1
(.I0(\result[22]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[22]),
.O(\result[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[22]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[23]_i_3_n_5 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[22]),
.I5(opcode_2[0]),
.O(\result[22]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\result[23]_i_1
(.I0(\result[23]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[23]),
.O(\result[23]_i_1_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[23]_i_10
(.I0(register_a[22]),
.I1(operand_a1),
.I2(register_b[22]),
.I3(operand_b1),
.I4(result[22]),
.O(\result[23]_i_10_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[23]_i_11
(.I0(register_a[21]),
.I1(operand_a1),
.I2(register_b[21]),
.I3(operand_b1),
.I4(result[21]),
.O(\result[23]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[23]_i_12
(.I0(register_a[20]),
.I1(operand_a1),
.I2(register_b[20]),
.I3(operand_b1),
.I4(result[20]),
.O(\result[23]_i_12_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[23]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[23]_i_3_n_4 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[23]),
.I5(opcode_2[0]),
.O(\result[23]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_5
(.I0(result[23]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[23]),
.O(\result[23]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_6
(.I0(result[22]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[22]),
.O(\result[23]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_7
(.I0(result[21]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[21]),
.O(\result[23]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_8
(.I0(result[20]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[20]),
.O(\result[23]_i_8_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[23]_i_9
(.I0(register_a[23]),
.I1(operand_a1),
.I2(register_b[23]),
.I3(operand_b1),
.I4(result[23]),
.O(\result[23]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\result[24]_i_1
(.I0(\result[24]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[24]),
.O(\result[24]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[24]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[27]_i_3_n_7 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[24]),
.I5(opcode_2[0]),
.O(\result[24]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\result[25]_i_1
(.I0(\result[25]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[25]),
.O(\result[25]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[25]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[27]_i_3_n_6 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[25]),
.I5(opcode_2[0]),
.O(\result[25]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\result[26]_i_1
(.I0(\result[26]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[26]),
.O(\result[26]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[26]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[27]_i_3_n_5 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[26]),
.I5(opcode_2[0]),
.O(\result[26]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\result[27]_i_1
(.I0(\result[27]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[27]),
.O(\result[27]_i_1_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[27]_i_10
(.I0(register_a[26]),
.I1(operand_a1),
.I2(register_b[26]),
.I3(operand_b1),
.I4(result[26]),
.O(\result[27]_i_10_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[27]_i_11
(.I0(register_a[25]),
.I1(operand_a1),
.I2(register_b[25]),
.I3(operand_b1),
.I4(result[25]),
.O(\result[27]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[27]_i_12
(.I0(register_a[24]),
.I1(operand_a1),
.I2(register_b[24]),
.I3(operand_b1),
.I4(result[24]),
.O(\result[27]_i_12_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[27]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[27]_i_3_n_4 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[27]),
.I5(opcode_2[0]),
.O(\result[27]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[27]_i_5
(.I0(result[27]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[27]),
.O(\result[27]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[27]_i_6
(.I0(result[26]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[26]),
.O(\result[27]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[27]_i_7
(.I0(result[25]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[25]),
.O(\result[27]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[27]_i_8
(.I0(result[24]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[24]),
.O(\result[27]_i_8_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[27]_i_9
(.I0(register_a[27]),
.I1(operand_a1),
.I2(register_b[27]),
.I3(operand_b1),
.I4(result[27]),
.O(\result[27]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\result[28]_i_1
(.I0(\result[28]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[28]),
.O(\result[28]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[28]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[31]_i_6_n_7 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[28]),
.I5(opcode_2[0]),
.O(\result[28]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\result[29]_i_1
(.I0(\result[29]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[29]),
.O(\result[29]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[29]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[31]_i_6_n_6 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[29]),
.I5(opcode_2[0]),
.O(\result[29]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\result[2]_i_1
(.I0(\result[2]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[2]),
.O(\result[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[2]_i_2
(.I0(address_b_2[2]),
.I1(\result_reg[3]_i_3_n_5 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[2]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[2]),
.O(\result[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\result[30]_i_1
(.I0(\result[30]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[30]),
.O(\result[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[30]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[31]_i_6_n_5 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[30]),
.I5(opcode_2[0]),
.O(\result[30]_i_2_n_0 ));
LUT6 #(
.INIT(64'h005400000000FF00))
\result[31]_i_1
(.I0(opcode_2[3]),
.I1(\result[31]_i_3_n_0 ),
.I2(\result[31]_i_4_n_0 ),
.I3(\state_reg_n_0_[2] ),
.I4(\state_reg_n_0_[1] ),
.I5(\state_reg_n_0_[0] ),
.O(\result[31]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_10
(.I0(result[29]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[29]),
.O(\result[31]_i_10_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_11
(.I0(result[28]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[28]),
.O(\result[31]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[31]_i_12
(.I0(register_a[31]),
.I1(operand_a1),
.I2(register_b[31]),
.I3(operand_b1),
.I4(result[31]),
.O(\result[31]_i_12_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[31]_i_13
(.I0(register_a[30]),
.I1(operand_a1),
.I2(register_b[30]),
.I3(operand_b1),
.I4(result[30]),
.O(\result[31]_i_13_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[31]_i_14
(.I0(register_a[29]),
.I1(operand_a1),
.I2(register_b[29]),
.I3(operand_b1),
.I4(result[29]),
.O(\result[31]_i_14_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[31]_i_15
(.I0(register_a[28]),
.I1(operand_a1),
.I2(register_b[28]),
.I3(operand_b1),
.I4(result[28]),
.O(\result[31]_i_15_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[31]_i_2
(.I0(\result[31]_i_5_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[31]),
.O(\result[31]_i_2_n_0 ));
LUT2 #(
.INIT(4'h1))
\result[31]_i_3
(.I0(opcode_2[2]),
.I1(opcode_2[1]),
.O(\result[31]_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\result[31]_i_4
(.I0(opcode_2[0]),
.I1(opcode_2[1]),
.O(\result[31]_i_4_n_0 ));
LUT6 #(
.INIT(64'hF0FC000CF0FA000A))
\result[31]_i_5
(.I0(literal_2[15]),
.I1(\result_reg[31]_i_6_n_4 ),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(data3[31]),
.I5(opcode_2[0]),
.O(\result[31]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_8
(.I0(result[31]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[31]),
.O(\result[31]_i_8_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_9
(.I0(result[30]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[30]),
.O(\result[31]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\result[3]_i_1
(.I0(\result[3]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[3]),
.O(\result[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_10
(.I0(register_a[0]),
.I1(operand_a1),
.I2(result[0]),
.I3(address_b_2[0]),
.O(\result[3]_i_10_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[3]_i_11
(.I0(result[1]),
.I1(operand_a1),
.I2(register_a[1]),
.O(\result[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[3]_i_12
(.I0(result[0]),
.I1(operand_a1),
.I2(register_a[0]),
.O(\result[3]_i_12_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[3]_i_13
(.I0(register_a[3]),
.I1(operand_a1),
.I2(register_b[3]),
.I3(operand_b1),
.I4(result[3]),
.O(\result[3]_i_13_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[3]_i_14
(.I0(register_a[2]),
.I1(operand_a1),
.I2(register_b[2]),
.I3(operand_b1),
.I4(result[2]),
.O(\result[3]_i_14_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[3]_i_15
(.I0(register_a[1]),
.I1(operand_a1),
.I2(register_b[1]),
.I3(operand_b1),
.I4(result[1]),
.O(\result[3]_i_15_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[3]_i_16
(.I0(register_a[0]),
.I1(operand_a1),
.I2(register_b[0]),
.I3(operand_b1),
.I4(result[0]),
.O(\result[3]_i_16_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[3]_i_2
(.I0(address_b_2[3]),
.I1(\result_reg[3]_i_3_n_4 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[3]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[3]),
.O(\result[3]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[3]_i_5
(.I0(result[1]),
.I1(operand_a1),
.I2(register_a[1]),
.O(\result[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[3]_i_6
(.I0(result[0]),
.I1(operand_a1),
.I2(register_a[0]),
.O(\result[3]_i_6_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_7
(.I0(register_a[3]),
.I1(operand_a1),
.I2(result[3]),
.I3(address_b_2[3]),
.O(\result[3]_i_7_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_8
(.I0(register_a[2]),
.I1(operand_a1),
.I2(result[2]),
.I3(address_b_2[2]),
.O(\result[3]_i_8_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_9
(.I0(register_a[1]),
.I1(operand_a1),
.I2(result[1]),
.I3(address_b_2[1]),
.O(\result[3]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\result[4]_i_1
(.I0(\result[4]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[4]),
.O(\result[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[4]_i_2
(.I0(literal_2[4]),
.I1(\result_reg[7]_i_3_n_7 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[4]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[4]),
.O(\result[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\result[5]_i_1
(.I0(\result[5]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[5]),
.O(\result[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[5]_i_2
(.I0(literal_2[5]),
.I1(\result_reg[7]_i_3_n_6 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[5]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[5]),
.O(\result[5]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\result[6]_i_1
(.I0(\result[6]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[6]),
.O(\result[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[6]_i_2
(.I0(literal_2[6]),
.I1(\result_reg[7]_i_3_n_5 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[6]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[6]),
.O(\result[6]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\result[7]_i_1
(.I0(\result[7]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[7]),
.O(\result[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[7]_i_10
(.I0(register_a[6]),
.I1(operand_a1),
.I2(register_b[6]),
.I3(operand_b1),
.I4(result[6]),
.O(\result[7]_i_10_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[7]_i_11
(.I0(register_a[5]),
.I1(operand_a1),
.I2(register_b[5]),
.I3(operand_b1),
.I4(result[5]),
.O(\result[7]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[7]_i_12
(.I0(register_a[4]),
.I1(operand_a1),
.I2(register_b[4]),
.I3(operand_b1),
.I4(result[4]),
.O(\result[7]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[7]_i_2
(.I0(literal_2[7]),
.I1(\result_reg[7]_i_3_n_4 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[7]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[7]),
.O(\result[7]_i_2_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_5
(.I0(register_a[7]),
.I1(operand_a1),
.I2(result[7]),
.I3(literal_2[7]),
.O(\result[7]_i_5_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_6
(.I0(register_a[6]),
.I1(operand_a1),
.I2(result[6]),
.I3(literal_2[6]),
.O(\result[7]_i_6_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_7
(.I0(register_a[5]),
.I1(operand_a1),
.I2(result[5]),
.I3(literal_2[5]),
.O(\result[7]_i_7_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_8
(.I0(register_a[4]),
.I1(operand_a1),
.I2(result[4]),
.I3(literal_2[4]),
.O(\result[7]_i_8_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[7]_i_9
(.I0(register_a[7]),
.I1(operand_a1),
.I2(register_b[7]),
.I3(operand_b1),
.I4(result[7]),
.O(\result[7]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\result[8]_i_1
(.I0(\result[8]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[8]),
.O(\result[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[8]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[11]_i_3_n_7 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[8]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[8]),
.O(\result[8]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[9]_i_1
(.I0(\result[9]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(load_data[9]),
.O(\result[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[9]_i_2
(.I0(literal_2[15]),
.I1(\result_reg[11]_i_3_n_6 ),
.I2(\result[31]_i_3_n_0 ),
.I3(data2[9]),
.I4(\result[16]_i_4_n_0 ),
.I5(data3[9]),
.O(\result[9]_i_2_n_0 ));
FDRE \result_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[0]_i_1_n_0 ),
.Q(result[0]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[10]_i_1_n_0 ),
.Q(result[10]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[11]_i_1_n_0 ),
.Q(result[11]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[11]_i_3
(.CI(\result_reg[7]_i_3_n_0 ),
.CO({\result_reg[11]_i_3_n_0 ,\NLW_result_reg[11]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 }),
.O({\result_reg[11]_i_3_n_4 ,\result_reg[11]_i_3_n_5 ,\result_reg[11]_i_3_n_6 ,\result_reg[11]_i_3_n_7 }),
.S({\result[11]_i_5_n_0 ,\result[11]_i_6_n_0 ,\result[11]_i_7_n_0 ,\result[11]_i_8_n_0 }));
CARRY4 \result_reg[11]_i_4
(.CI(\result_reg[7]_i_4_n_0 ),
.CO({\result_reg[11]_i_4_n_0 ,\NLW_result_reg[11]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[11]_i_1_n_0 ,\write_output[10]_i_1_n_0 ,\write_output[9]_i_1_n_0 ,\write_output[8]_i_1_n_0 }),
.O(data3[11:8]),
.S({\result[11]_i_9_n_0 ,\result[11]_i_10_n_0 ,\result[11]_i_11_n_0 ,\result[11]_i_12_n_0 }));
FDRE \result_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[12]_i_1_n_0 ),
.Q(result[12]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[12]_i_3
(.CI(\result_reg[8]_i_3_n_0 ),
.CO({\result_reg[12]_i_3_n_0 ,\NLW_result_reg[12]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data2[12:9]),
.S(program_counter_2[12:9]));
FDRE \result_reg[13]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[13]_i_1_n_0 ),
.Q(result[13]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[14]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[14]_i_1_n_0 ),
.Q(result[14]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[15]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[15]_i_1_n_0 ),
.Q(result[15]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[15]_i_3
(.CI(\result_reg[11]_i_3_n_0 ),
.CO({\result_reg[15]_i_3_n_0 ,\NLW_result_reg[15]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[15]_i_1_n_0 ,\write_output[14]_i_1_n_0 ,\write_output[13]_i_1_n_0 ,\write_output[12]_i_1_n_0 }),
.O({\result_reg[15]_i_3_n_4 ,\result_reg[15]_i_3_n_5 ,\result_reg[15]_i_3_n_6 ,\result_reg[15]_i_3_n_7 }),
.S({\result[15]_i_5_n_0 ,\result[15]_i_6_n_0 ,\result[15]_i_7_n_0 ,\result[15]_i_8_n_0 }));
CARRY4 \result_reg[15]_i_4
(.CI(\result_reg[11]_i_4_n_0 ),
.CO({\result_reg[15]_i_4_n_0 ,\NLW_result_reg[15]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[15]_i_1_n_0 ,\write_output[14]_i_1_n_0 ,\write_output[13]_i_1_n_0 ,\write_output[12]_i_1_n_0 }),
.O(data3[15:12]),
.S({\result[15]_i_9_n_0 ,\result[15]_i_10_n_0 ,\result[15]_i_11_n_0 ,\result[15]_i_12_n_0 }));
FDRE \result_reg[16]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[16]_i_1_n_0 ),
.Q(result[16]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[16]_i_3
(.CI(\result_reg[12]_i_3_n_0 ),
.CO({data2[16],\NLW_result_reg[16]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_result_reg[16]_i_3_O_UNCONNECTED [3],data2[15:13]}),
.S({1'b1,program_counter_2[15:13]}));
FDRE \result_reg[17]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[17]_i_1_n_0 ),
.Q(result[17]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[18]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[18]_i_1_n_0 ),
.Q(result[18]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[19]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[19]_i_1_n_0 ),
.Q(result[19]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[19]_i_3
(.CI(\result_reg[15]_i_3_n_0 ),
.CO({\result_reg[19]_i_3_n_0 ,\NLW_result_reg[19]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[19]_i_3_n_4 ,\result_reg[19]_i_3_n_5 ,\result_reg[19]_i_3_n_6 ,\result_reg[19]_i_3_n_7 }),
.S({\result[19]_i_5_n_0 ,\result[19]_i_6_n_0 ,\result[19]_i_7_n_0 ,\result[19]_i_8_n_0 }));
CARRY4 \result_reg[19]_i_4
(.CI(\result_reg[15]_i_4_n_0 ),
.CO({\result_reg[19]_i_4_n_0 ,\NLW_result_reg[19]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[19]_i_1_n_0 ,\write_output[18]_i_1_n_0 ,\write_output[17]_i_1_n_0 ,\write_output[16]_i_1_n_0 }),
.O(data3[19:16]),
.S({\result[19]_i_9_n_0 ,\result[19]_i_10_n_0 ,\result[19]_i_11_n_0 ,\result[19]_i_12_n_0 }));
FDRE \result_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[1]_i_1_n_0 ),
.Q(result[1]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[20]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[20]_i_1_n_0 ),
.Q(result[20]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[21]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[21]_i_1_n_0 ),
.Q(result[21]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[22]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[22]_i_1_n_0 ),
.Q(result[22]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[23]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[23]_i_1_n_0 ),
.Q(result[23]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[23]_i_3
(.CI(\result_reg[19]_i_3_n_0 ),
.CO({\result_reg[23]_i_3_n_0 ,\NLW_result_reg[23]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[23]_i_3_n_4 ,\result_reg[23]_i_3_n_5 ,\result_reg[23]_i_3_n_6 ,\result_reg[23]_i_3_n_7 }),
.S({\result[23]_i_5_n_0 ,\result[23]_i_6_n_0 ,\result[23]_i_7_n_0 ,\result[23]_i_8_n_0 }));
CARRY4 \result_reg[23]_i_4
(.CI(\result_reg[19]_i_4_n_0 ),
.CO({\result_reg[23]_i_4_n_0 ,\NLW_result_reg[23]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[23]_i_1_n_0 ,\write_output[22]_i_1_n_0 ,\write_output[21]_i_1_n_0 ,\write_output[20]_i_1_n_0 }),
.O(data3[23:20]),
.S({\result[23]_i_9_n_0 ,\result[23]_i_10_n_0 ,\result[23]_i_11_n_0 ,\result[23]_i_12_n_0 }));
FDRE \result_reg[24]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[24]_i_1_n_0 ),
.Q(result[24]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[25]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[25]_i_1_n_0 ),
.Q(result[25]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[26]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[26]_i_1_n_0 ),
.Q(result[26]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[27]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[27]_i_1_n_0 ),
.Q(result[27]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[27]_i_3
(.CI(\result_reg[23]_i_3_n_0 ),
.CO({\result_reg[27]_i_3_n_0 ,\NLW_result_reg[27]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[27]_i_3_n_4 ,\result_reg[27]_i_3_n_5 ,\result_reg[27]_i_3_n_6 ,\result_reg[27]_i_3_n_7 }),
.S({\result[27]_i_5_n_0 ,\result[27]_i_6_n_0 ,\result[27]_i_7_n_0 ,\result[27]_i_8_n_0 }));
CARRY4 \result_reg[27]_i_4
(.CI(\result_reg[23]_i_4_n_0 ),
.CO({\result_reg[27]_i_4_n_0 ,\NLW_result_reg[27]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[27]_i_1_n_0 ,\write_output[26]_i_1_n_0 ,\write_output[25]_i_1_n_0 ,\write_output[24]_i_1_n_0 }),
.O(data3[27:24]),
.S({\result[27]_i_9_n_0 ,\result[27]_i_10_n_0 ,\result[27]_i_11_n_0 ,\result[27]_i_12_n_0 }));
FDRE \result_reg[28]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[28]_i_1_n_0 ),
.Q(result[28]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[29]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[29]_i_1_n_0 ),
.Q(result[29]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[2]_i_1_n_0 ),
.Q(result[2]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[30]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[30]_i_1_n_0 ),
.Q(result[30]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[31]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[31]_i_2_n_0 ),
.Q(result[31]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[31]_i_6
(.CI(\result_reg[27]_i_3_n_0 ),
.CO(\NLW_result_reg[31]_i_6_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[31]_i_6_n_4 ,\result_reg[31]_i_6_n_5 ,\result_reg[31]_i_6_n_6 ,\result_reg[31]_i_6_n_7 }),
.S({\result[31]_i_8_n_0 ,\result[31]_i_9_n_0 ,\result[31]_i_10_n_0 ,\result[31]_i_11_n_0 }));
CARRY4 \result_reg[31]_i_7
(.CI(\result_reg[27]_i_4_n_0 ),
.CO(\NLW_result_reg[31]_i_7_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,\write_output[30]_i_1_n_0 ,\write_output[29]_i_1_n_0 ,\write_output[28]_i_1_n_0 }),
.O(data3[31:28]),
.S({\result[31]_i_12_n_0 ,\result[31]_i_13_n_0 ,\result[31]_i_14_n_0 ,\result[31]_i_15_n_0 }));
FDRE \result_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[3]_i_1_n_0 ),
.Q(result[3]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[3]_i_3
(.CI(1'b0),
.CO({\result_reg[3]_i_3_n_0 ,\NLW_result_reg[3]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\result[3]_i_5_n_0 ,\result[3]_i_6_n_0 }),
.O({\result_reg[3]_i_3_n_4 ,\result_reg[3]_i_3_n_5 ,\result_reg[3]_i_3_n_6 ,\result_reg[3]_i_3_n_7 }),
.S({\result[3]_i_7_n_0 ,\result[3]_i_8_n_0 ,\result[3]_i_9_n_0 ,\result[3]_i_10_n_0 }));
CARRY4 \result_reg[3]_i_4
(.CI(1'b0),
.CO({\result_reg[3]_i_4_n_0 ,\NLW_result_reg[3]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[3]_i_1_n_0 ,\write_output[2]_i_1_n_0 ,\result[3]_i_11_n_0 ,\result[3]_i_12_n_0 }),
.O(data3[3:0]),
.S({\result[3]_i_13_n_0 ,\result[3]_i_14_n_0 ,\result[3]_i_15_n_0 ,\result[3]_i_16_n_0 }));
FDRE \result_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[4]_i_1_n_0 ),
.Q(result[4]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[4]_i_3
(.CI(1'b0),
.CO({\result_reg[4]_i_3_n_0 ,\NLW_result_reg[4]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(program_counter_2[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data2[4:1]),
.S(program_counter_2[4:1]));
FDRE \result_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[5]_i_1_n_0 ),
.Q(result[5]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[6]_i_1_n_0 ),
.Q(result[6]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[7]_i_1_n_0 ),
.Q(result[7]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[7]_i_3
(.CI(\result_reg[3]_i_3_n_0 ),
.CO({\result_reg[7]_i_3_n_0 ,\NLW_result_reg[7]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 }),
.O({\result_reg[7]_i_3_n_4 ,\result_reg[7]_i_3_n_5 ,\result_reg[7]_i_3_n_6 ,\result_reg[7]_i_3_n_7 }),
.S({\result[7]_i_5_n_0 ,\result[7]_i_6_n_0 ,\result[7]_i_7_n_0 ,\result[7]_i_8_n_0 }));
CARRY4 \result_reg[7]_i_4
(.CI(\result_reg[3]_i_4_n_0 ),
.CO({\result_reg[7]_i_4_n_0 ,\NLW_result_reg[7]_i_4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\write_output[7]_i_1_n_0 ,\write_output[6]_i_1_n_0 ,\write_output[5]_i_1_n_0 ,\write_output[4]_i_1_n_0 }),
.O(data3[7:4]),
.S({\result[7]_i_9_n_0 ,\result[7]_i_10_n_0 ,\result[7]_i_11_n_0 ,\result[7]_i_12_n_0 }));
FDRE \result_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[8]_i_1_n_0 ),
.Q(result[8]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[8]_i_3
(.CI(\result_reg[4]_i_3_n_0 ),
.CO({\result_reg[8]_i_3_n_0 ,\NLW_result_reg[8]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data2[8:5]),
.S(program_counter_2[8:5]));
FDRE \result_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[9]_i_1_n_0 ),
.Q(result[9]),
.R(INTERNAL_RST_reg));
LUT3 #(
.INIT(8'h80))
\s_output_rs232_tx[7]_i_1
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[0] ),
.I2(\s_output_rs232_tx[7]_i_2_n_0 ),
.O(\s_output_rs232_tx[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\s_output_rs232_tx[7]_i_2
(.I0(\s_output_rs232_tx[7]_i_3_n_0 ),
.I1(\s_output_rs232_tx[7]_i_4_n_0 ),
.I2(\s_output_rs232_tx[7]_i_5_n_0 ),
.I3(\s_output_rs232_tx[7]_i_6_n_0 ),
.I4(\s_output_rs232_tx[7]_i_7_n_0 ),
.I5(\s_output_rs232_tx[7]_i_8_n_0 ),
.O(\s_output_rs232_tx[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_output_rs232_tx[7]_i_3
(.I0(write_output[15]),
.I1(write_output[16]),
.I2(write_output[10]),
.I3(write_output[25]),
.I4(write_output[13]),
.I5(write_output[30]),
.O(\s_output_rs232_tx[7]_i_3_n_0 ));
LUT3 #(
.INIT(8'h01))
\s_output_rs232_tx[7]_i_4
(.I0(write_output[14]),
.I1(write_output[26]),
.I2(write_output[20]),
.O(\s_output_rs232_tx[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_output_rs232_tx[7]_i_5
(.I0(write_output[6]),
.I1(write_output[31]),
.I2(write_output[28]),
.I3(write_output[7]),
.I4(write_output[12]),
.I5(write_output[19]),
.O(\s_output_rs232_tx[7]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000000010))
\s_output_rs232_tx[7]_i_6
(.I0(write_output[1]),
.I1(write_output[11]),
.I2(\state_reg_n_0_[2] ),
.I3(write_output[24]),
.I4(write_output[21]),
.I5(write_output[3]),
.O(\s_output_rs232_tx[7]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_output_rs232_tx[7]_i_7
(.I0(write_output[22]),
.I1(write_output[5]),
.I2(write_output[17]),
.I3(write_output[18]),
.I4(write_output[0]),
.I5(write_output[29]),
.O(\s_output_rs232_tx[7]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_output_rs232_tx[7]_i_8
(.I0(write_output[9]),
.I1(write_output[4]),
.I2(write_output[27]),
.I3(write_output[8]),
.I4(write_output[23]),
.I5(write_output[2]),
.O(\s_output_rs232_tx[7]_i_8_n_0 ));
FDRE \s_output_rs232_tx_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[0]),
.Q(output_rs232_tx[0]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[1]),
.Q(output_rs232_tx[1]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[2]),
.Q(output_rs232_tx[2]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[3]),
.Q(output_rs232_tx[3]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[4]),
.Q(output_rs232_tx[4]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[5]),
.Q(output_rs232_tx[5]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[6]),
.Q(output_rs232_tx[6]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx[7]_i_1_n_0 ),
.D(write_value[7]),
.Q(output_rs232_tx[7]),
.R(1'b0));
LUT5 #(
.INIT(32'h7FFF8080))
\s_output_rs232_tx_stb[0]_i_1
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[0] ),
.I2(\s_output_rs232_tx[7]_i_2_n_0 ),
.I3(IN1_ACK),
.I4(IN1_STB),
.O(\s_output_rs232_tx_stb[0]_i_1_n_0 ));
FDRE \s_output_rs232_tx_stb_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\s_output_rs232_tx_stb[0]_i_1_n_0 ),
.Q(IN1_STB),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFF8AFFFFFFAA0000))
\state[0]_i_1
(.I0(\state_reg_n_0_[1] ),
.I1(opcode_2[1]),
.I2(opcode_2[2]),
.I3(\state_reg_n_0_[2] ),
.I4(\state[2]_i_2_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF8FFFFFFFFF0000))
\state[1]_i_1
(.I0(\result[31]_i_3_n_0 ),
.I1(opcode_2[0]),
.I2(\state_reg_n_0_[0] ),
.I3(\state_reg_n_0_[2] ),
.I4(\state[2]_i_2_n_0 ),
.I5(\state_reg_n_0_[1] ),
.O(\state[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000FFFF08000000))
\state[2]_i_1
(.I0(\state_reg_n_0_[0] ),
.I1(\state_reg_n_0_[1] ),
.I2(opcode_2[1]),
.I3(opcode_2[0]),
.I4(\state[2]_i_2_n_0 ),
.I5(\state_reg_n_0_[2] ),
.O(\state[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\state[2]_i_10
(.I0(\write_output[27]_i_1_n_0 ),
.I1(\write_output[26]_i_1_n_0 ),
.I2(\write_output[30]_i_1_n_0 ),
.I3(\write_output[31]_i_2_n_0 ),
.I4(\write_output[28]_i_1_n_0 ),
.I5(\write_output[29]_i_1_n_0 ),
.O(\state[2]_i_10_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\state[2]_i_11
(.I0(\write_output[9]_i_1_n_0 ),
.I1(\write_output[8]_i_1_n_0 ),
.I2(\write_output[12]_i_1_n_0 ),
.I3(\write_output[13]_i_1_n_0 ),
.I4(\write_output[10]_i_1_n_0 ),
.I5(\write_output[11]_i_1_n_0 ),
.O(\state[2]_i_11_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\state[2]_i_12
(.I0(\write_output[15]_i_1_n_0 ),
.I1(\write_output[14]_i_1_n_0 ),
.I2(\write_output[18]_i_1_n_0 ),
.I3(\write_output[19]_i_1_n_0 ),
.I4(\write_output[16]_i_1_n_0 ),
.I5(\write_output[17]_i_1_n_0 ),
.O(\state[2]_i_12_n_0 ));
LUT6 #(
.INIT(64'hFFFFBBABAAAAAAAA))
\state[2]_i_2
(.I0(\state[2]_i_3_n_0 ),
.I1(\state[2]_i_4_n_0 ),
.I2(\state[2]_i_5_n_0 ),
.I3(opcode_2[1]),
.I4(\state[2]_i_6_n_0 ),
.I5(\state[2]_i_7_n_0 ),
.O(\state[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8080FFFF00FFFF00))
\state[2]_i_3
(.I0(\s_output_rs232_tx[7]_i_2_n_0 ),
.I1(IN1_STB),
.I2(IN1_ACK),
.I3(\state_reg_n_0_[2] ),
.I4(\state_reg_n_0_[1] ),
.I5(\state_reg_n_0_[0] ),
.O(\state[2]_i_3_n_0 ));
LUT3 #(
.INIT(8'hEF))
\state[2]_i_4
(.I0(opcode_2[0]),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\state[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\state[2]_i_5
(.I0(\program_counter_rep[7]_i_15_n_0 ),
.I1(\state[2]_i_8_n_0 ),
.I2(\state[2]_i_9_n_0 ),
.I3(\state[2]_i_10_n_0 ),
.I4(\state[2]_i_11_n_0 ),
.I5(\state[2]_i_12_n_0 ),
.O(\state[2]_i_5_n_0 ));
LUT4 #(
.INIT(16'h046A))
\state[2]_i_6
(.I0(opcode_2[2]),
.I1(opcode_2[0]),
.I2(opcode_2[1]),
.I3(opcode_2[3]),
.O(\state[2]_i_6_n_0 ));
LUT2 #(
.INIT(4'h2))
\state[2]_i_7
(.I0(\state_reg_n_0_[0] ),
.I1(\state_reg_n_0_[2] ),
.O(\state[2]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\state[2]_i_8
(.I0(register_a[0]),
.I1(result[0]),
.I2(register_a[1]),
.I3(operand_a1),
.I4(result[1]),
.O(\state[2]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\state[2]_i_9
(.I0(\write_output[21]_i_1_n_0 ),
.I1(\write_output[20]_i_1_n_0 ),
.I2(\write_output[24]_i_1_n_0 ),
.I3(\write_output[25]_i_1_n_0 ),
.I4(\write_output[22]_i_1_n_0 ),
.I5(\write_output[23]_i_1_n_0 ),
.O(\state[2]_i_9_n_0 ));
FDSE \state_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(\state_reg_n_0_[0] ),
.S(INTERNAL_RST_reg));
FDRE \state_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\state[1]_i_1_n_0 ),
.Q(\state_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \state_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\state[2]_i_1_n_0 ),
.Q(\state_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE write_enable_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\result[31]_i_1_n_0 ),
.Q(write_enable),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
\write_output[0]_i_1
(.I0(result[0]),
.I1(operand_a1),
.I2(register_a[0]),
.O(\write_output[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[10]_i_1
(.I0(result[10]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[10]),
.O(\write_output[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[11]_i_1
(.I0(result[11]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[11]),
.O(\write_output[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[12]_i_1
(.I0(result[12]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[12]),
.O(\write_output[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[13]_i_1
(.I0(result[13]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[13]),
.O(\write_output[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[14]_i_1
(.I0(result[14]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[14]),
.O(\write_output[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[15]_i_1
(.I0(result[15]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[15]),
.O(\write_output[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[16]_i_1
(.I0(result[16]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[16]),
.O(\write_output[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[17]_i_1
(.I0(result[17]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[17]),
.O(\write_output[17]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[18]_i_1
(.I0(result[18]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[18]),
.O(\write_output[18]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[19]_i_1
(.I0(result[19]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[19]),
.O(\write_output[19]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\write_output[1]_i_1
(.I0(result[1]),
.I1(operand_a1),
.I2(register_a[1]),
.O(\write_output[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h2002000000002002))
\write_output[1]_i_2
(.I0(write_enable),
.I1(\write_output[31]_i_3_n_0 ),
.I2(address_a_2[0]),
.I3(address_z_3[0]),
.I4(address_a_2[3]),
.I5(address_z_3[3]),
.O(operand_a1));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[20]_i_1
(.I0(result[20]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[20]),
.O(\write_output[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[21]_i_1
(.I0(result[21]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[21]),
.O(\write_output[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[22]_i_1
(.I0(result[22]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[22]),
.O(\write_output[22]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[23]_i_1
(.I0(result[23]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[23]),
.O(\write_output[23]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[24]_i_1
(.I0(result[24]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[24]),
.O(\write_output[24]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[25]_i_1
(.I0(result[25]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[25]),
.O(\write_output[25]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[26]_i_1
(.I0(result[26]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[26]),
.O(\write_output[26]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[27]_i_1
(.I0(result[27]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[27]),
.O(\write_output[27]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[28]_i_1
(.I0(result[28]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[28]),
.O(\write_output[28]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[29]_i_1
(.I0(result[29]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[29]),
.O(\write_output[29]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[2]_i_1
(.I0(result[2]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[2]),
.O(\write_output[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[30]_i_1
(.I0(result[30]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[30]),
.O(\write_output[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000008000000000))
\write_output[31]_i_1
(.I0(\state_reg_n_0_[0] ),
.I1(opcode_20),
.I2(opcode_2[0]),
.I3(opcode_2[1]),
.I4(opcode_2[2]),
.I5(opcode_2[3]),
.O(\write_output[31]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[31]_i_2
(.I0(result[31]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[31]),
.O(\write_output[31]_i_2_n_0 ));
LUT4 #(
.INIT(16'h6FF6))
\write_output[31]_i_3
(.I0(address_a_2[2]),
.I1(address_z_3[2]),
.I2(address_a_2[1]),
.I3(address_z_3[1]),
.O(\write_output[31]_i_3_n_0 ));
LUT4 #(
.INIT(16'h6FF6))
\write_output[31]_i_4
(.I0(address_a_2[0]),
.I1(address_z_3[0]),
.I2(address_a_2[3]),
.I3(address_z_3[3]),
.O(\write_output[31]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[3]_i_1
(.I0(result[3]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[3]),
.O(\write_output[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[4]_i_1
(.I0(result[4]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[4]),
.O(\write_output[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[5]_i_1
(.I0(result[5]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[5]),
.O(\write_output[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[6]_i_1
(.I0(result[6]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[6]),
.O(\write_output[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[7]_i_1
(.I0(result[7]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[7]),
.O(\write_output[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[8]_i_1
(.I0(result[8]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[8]),
.O(\write_output[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\write_output[9]_i_1
(.I0(result[9]),
.I1(write_enable),
.I2(\write_output[31]_i_3_n_0 ),
.I3(\write_output[31]_i_4_n_0 ),
.I4(register_a[9]),
.O(\write_output[9]_i_1_n_0 ));
FDRE \write_output_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[0]_i_1_n_0 ),
.Q(write_output[0]),
.R(1'b0));
FDRE \write_output_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[10]_i_1_n_0 ),
.Q(write_output[10]),
.R(1'b0));
FDRE \write_output_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[11]_i_1_n_0 ),
.Q(write_output[11]),
.R(1'b0));
FDRE \write_output_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[12]_i_1_n_0 ),
.Q(write_output[12]),
.R(1'b0));
FDRE \write_output_reg[13]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[13]_i_1_n_0 ),
.Q(write_output[13]),
.R(1'b0));
FDRE \write_output_reg[14]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[14]_i_1_n_0 ),
.Q(write_output[14]),
.R(1'b0));
FDRE \write_output_reg[15]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[15]_i_1_n_0 ),
.Q(write_output[15]),
.R(1'b0));
FDRE \write_output_reg[16]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[16]_i_1_n_0 ),
.Q(write_output[16]),
.R(1'b0));
FDRE \write_output_reg[17]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[17]_i_1_n_0 ),
.Q(write_output[17]),
.R(1'b0));
FDRE \write_output_reg[18]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[18]_i_1_n_0 ),
.Q(write_output[18]),
.R(1'b0));
FDRE \write_output_reg[19]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[19]_i_1_n_0 ),
.Q(write_output[19]),
.R(1'b0));
FDRE \write_output_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[1]_i_1_n_0 ),
.Q(write_output[1]),
.R(1'b0));
FDRE \write_output_reg[20]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[20]_i_1_n_0 ),
.Q(write_output[20]),
.R(1'b0));
FDRE \write_output_reg[21]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[21]_i_1_n_0 ),
.Q(write_output[21]),
.R(1'b0));
FDRE \write_output_reg[22]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[22]_i_1_n_0 ),
.Q(write_output[22]),
.R(1'b0));
FDRE \write_output_reg[23]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[23]_i_1_n_0 ),
.Q(write_output[23]),
.R(1'b0));
FDRE \write_output_reg[24]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[24]_i_1_n_0 ),
.Q(write_output[24]),
.R(1'b0));
FDRE \write_output_reg[25]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[25]_i_1_n_0 ),
.Q(write_output[25]),
.R(1'b0));
FDRE \write_output_reg[26]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[26]_i_1_n_0 ),
.Q(write_output[26]),
.R(1'b0));
FDRE \write_output_reg[27]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[27]_i_1_n_0 ),
.Q(write_output[27]),
.R(1'b0));
FDRE \write_output_reg[28]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[28]_i_1_n_0 ),
.Q(write_output[28]),
.R(1'b0));
FDRE \write_output_reg[29]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[29]_i_1_n_0 ),
.Q(write_output[29]),
.R(1'b0));
FDRE \write_output_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[2]_i_1_n_0 ),
.Q(write_output[2]),
.R(1'b0));
FDRE \write_output_reg[30]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[30]_i_1_n_0 ),
.Q(write_output[30]),
.R(1'b0));
FDRE \write_output_reg[31]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[31]_i_2_n_0 ),
.Q(write_output[31]),
.R(1'b0));
FDRE \write_output_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[3]_i_1_n_0 ),
.Q(write_output[3]),
.R(1'b0));
FDRE \write_output_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[4]_i_1_n_0 ),
.Q(write_output[4]),
.R(1'b0));
FDRE \write_output_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[5]_i_1_n_0 ),
.Q(write_output[5]),
.R(1'b0));
FDRE \write_output_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[6]_i_1_n_0 ),
.Q(write_output[6]),
.R(1'b0));
FDRE \write_output_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[7]_i_1_n_0 ),
.Q(write_output[7]),
.R(1'b0));
FDRE \write_output_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[8]_i_1_n_0 ),
.Q(write_output[8]),
.R(1'b0));
FDRE \write_output_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(\write_output[9]_i_1_n_0 ),
.Q(write_output[9]),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
\write_value[0]_i_1
(.I0(result[0]),
.I1(operand_b1),
.I2(register_b[0]),
.O(store_data[0]));
LUT3 #(
.INIT(8'hB8))
\write_value[1]_i_1
(.I0(result[1]),
.I1(operand_b1),
.I2(register_b[1]),
.O(store_data[1]));
LUT3 #(
.INIT(8'hB8))
\write_value[2]_i_1
(.I0(result[2]),
.I1(operand_b1),
.I2(register_b[2]),
.O(store_data[2]));
LUT3 #(
.INIT(8'hB8))
\write_value[3]_i_1
(.I0(result[3]),
.I1(operand_b1),
.I2(register_b[3]),
.O(store_data[3]));
LUT3 #(
.INIT(8'hB8))
\write_value[4]_i_1
(.I0(result[4]),
.I1(operand_b1),
.I2(register_b[4]),
.O(store_data[4]));
LUT3 #(
.INIT(8'hB8))
\write_value[5]_i_1
(.I0(result[5]),
.I1(operand_b1),
.I2(register_b[5]),
.O(store_data[5]));
LUT3 #(
.INIT(8'hB8))
\write_value[6]_i_1
(.I0(result[6]),
.I1(operand_b1),
.I2(register_b[6]),
.O(store_data[6]));
LUT3 #(
.INIT(8'hB8))
\write_value[7]_i_1
(.I0(result[7]),
.I1(operand_b1),
.I2(register_b[7]),
.O(store_data[7]));
LUT6 #(
.INIT(64'h2002000000002002))
\write_value[7]_i_2
(.I0(write_enable),
.I1(\write_value[7]_i_3_n_0 ),
.I2(address_z_3[0]),
.I3(address_b_2[0]),
.I4(address_z_3[3]),
.I5(address_b_2[3]),
.O(operand_b1));
LUT4 #(
.INIT(16'h6FF6))
\write_value[7]_i_3
(.I0(address_z_3[2]),
.I1(address_b_2[2]),
.I2(address_z_3[1]),
.I3(address_b_2[1]),
.O(\write_value[7]_i_3_n_0 ));
FDRE \write_value_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[0]),
.Q(write_value[0]),
.R(1'b0));
FDRE \write_value_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[1]),
.Q(write_value[1]),
.R(1'b0));
FDRE \write_value_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[2]),
.Q(write_value[2]),
.R(1'b0));
FDRE \write_value_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[3]),
.Q(write_value[3]),
.R(1'b0));
FDRE \write_value_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[4]),
.Q(write_value[4]),
.R(1'b0));
FDRE \write_value_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[5]),
.Q(write_value[5]),
.R(1'b0));
FDRE \write_value_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[6]),
.Q(write_value[6]),
.R(1'b0));
FDRE \write_value_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\write_output[31]_i_1_n_0 ),
.D(store_data[7]),
.Q(write_value[7]),
.R(1'b0));
endmodule
module pwm_audio
(JC_IBUF,
INTERNAL_RST_reg,
ETH_CLK_OBUF);
output [0:0]JC_IBUF;
input INTERNAL_RST_reg;
input ETH_CLK_OBUF;
wire \COUNT[10]_i_2_n_0 ;
wire \COUNT[10]_i_4_n_0 ;
wire \COUNT[10]_i_5_n_0 ;
wire \COUNT[10]_i_6_n_0 ;
wire \COUNT[9]_i_2_n_0 ;
wire [10:0]COUNT_reg__0;
wire ETH_CLK_OBUF;
wire INTERNAL_RST_reg;
wire [0:0]JC_IBUF;
wire STATE;
wire STATE_i_1_n_0;
wire STATE_reg_n_0;
wire S_DATA_IN_ACK_i_1_n_0;
wire [10:0]p_0_in;
(* SOFT_HLUTNM = "soft_lutpair172" *)
LUT1 #(
.INIT(2'h1))
\COUNT[0]_i_1__4
(.I0(COUNT_reg__0[0]),
.O(p_0_in[0]));
LUT2 #(
.INIT(4'h2))
\COUNT[10]_i_1
(.I0(JC_IBUF),
.I1(STATE_reg_n_0),
.O(STATE));
LUT2 #(
.INIT(4'h2))
\COUNT[10]_i_2
(.I0(STATE_reg_n_0),
.I1(\COUNT[10]_i_4_n_0 ),
.O(\COUNT[10]_i_2_n_0 ));
LUT3 #(
.INIT(8'h6A))
\COUNT[10]_i_3
(.I0(COUNT_reg__0[10]),
.I1(\COUNT[10]_i_5_n_0 ),
.I2(COUNT_reg__0[9]),
.O(p_0_in[10]));
LUT6 #(
.INIT(64'h0000800000000000))
\COUNT[10]_i_4
(.I0(COUNT_reg__0[2]),
.I1(COUNT_reg__0[3]),
.I2(COUNT_reg__0[6]),
.I3(COUNT_reg__0[5]),
.I4(COUNT_reg__0[7]),
.I5(\COUNT[10]_i_6_n_0 ),
.O(\COUNT[10]_i_4_n_0 ));
LUT5 #(
.INIT(32'h80000000))
\COUNT[10]_i_5
(.I0(COUNT_reg__0[8]),
.I1(COUNT_reg__0[7]),
.I2(\COUNT[9]_i_2_n_0 ),
.I3(COUNT_reg__0[6]),
.I4(COUNT_reg__0[5]),
.O(\COUNT[10]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000000004))
\COUNT[10]_i_6
(.I0(COUNT_reg__0[9]),
.I1(COUNT_reg__0[10]),
.I2(COUNT_reg__0[4]),
.I3(COUNT_reg__0[8]),
.I4(COUNT_reg__0[0]),
.I5(COUNT_reg__0[1]),
.O(\COUNT[10]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair172" *)
LUT2 #(
.INIT(4'h6))
\COUNT[1]_i_1__4
(.I0(COUNT_reg__0[0]),
.I1(COUNT_reg__0[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT3 #(
.INIT(8'h78))
\COUNT[2]_i_1__3
(.I0(COUNT_reg__0[0]),
.I1(COUNT_reg__0[1]),
.I2(COUNT_reg__0[2]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h6AAA))
\COUNT[3]_i_1__2
(.I0(COUNT_reg__0[3]),
.I1(COUNT_reg__0[0]),
.I2(COUNT_reg__0[1]),
.I3(COUNT_reg__0[2]),
.O(p_0_in[3]));
LUT5 #(
.INIT(32'h7FFF8000))
\COUNT[4]_i_1__2
(.I0(COUNT_reg__0[1]),
.I1(COUNT_reg__0[0]),
.I2(COUNT_reg__0[3]),
.I3(COUNT_reg__0[2]),
.I4(COUNT_reg__0[4]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\COUNT[5]_i_1__2
(.I0(COUNT_reg__0[5]),
.I1(COUNT_reg__0[1]),
.I2(COUNT_reg__0[0]),
.I3(COUNT_reg__0[3]),
.I4(COUNT_reg__0[2]),
.I5(COUNT_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair170" *)
LUT3 #(
.INIT(8'h6A))
\COUNT[6]_i_1__2
(.I0(COUNT_reg__0[6]),
.I1(\COUNT[9]_i_2_n_0 ),
.I2(COUNT_reg__0[5]),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair170" *)
LUT4 #(
.INIT(16'h6AAA))
\COUNT[7]_i_1__2
(.I0(COUNT_reg__0[7]),
.I1(COUNT_reg__0[5]),
.I2(COUNT_reg__0[6]),
.I3(\COUNT[9]_i_2_n_0 ),
.O(p_0_in[7]));
LUT5 #(
.INIT(32'h6AAAAAAA))
\COUNT[8]_i_1
(.I0(COUNT_reg__0[8]),
.I1(COUNT_reg__0[7]),
.I2(\COUNT[9]_i_2_n_0 ),
.I3(COUNT_reg__0[6]),
.I4(COUNT_reg__0[5]),
.O(p_0_in[8]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\COUNT[9]_i_1
(.I0(COUNT_reg__0[9]),
.I1(COUNT_reg__0[5]),
.I2(COUNT_reg__0[6]),
.I3(\COUNT[9]_i_2_n_0 ),
.I4(COUNT_reg__0[7]),
.I5(COUNT_reg__0[8]),
.O(p_0_in[9]));
LUT5 #(
.INIT(32'h80000000))
\COUNT[9]_i_2
(.I0(COUNT_reg__0[4]),
.I1(COUNT_reg__0[2]),
.I2(COUNT_reg__0[3]),
.I3(COUNT_reg__0[0]),
.I4(COUNT_reg__0[1]),
.O(\COUNT[9]_i_2_n_0 ));
FDRE \COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[0]),
.Q(COUNT_reg__0[0]),
.R(STATE));
FDRE \COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[10]),
.Q(COUNT_reg__0[10]),
.R(STATE));
FDRE \COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[1]),
.Q(COUNT_reg__0[1]),
.R(STATE));
FDRE \COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[2]),
.Q(COUNT_reg__0[2]),
.R(STATE));
FDRE \COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[3]),
.Q(COUNT_reg__0[3]),
.R(STATE));
FDRE \COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[4]),
.Q(COUNT_reg__0[4]),
.R(STATE));
FDRE \COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[5]),
.Q(COUNT_reg__0[5]),
.R(STATE));
FDRE \COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[6]),
.Q(COUNT_reg__0[6]),
.R(STATE));
FDRE \COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[7]),
.Q(COUNT_reg__0[7]),
.R(STATE));
FDRE \COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[8]),
.Q(COUNT_reg__0[8]),
.R(STATE));
FDRE \COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[9]),
.Q(COUNT_reg__0[9]),
.R(STATE));
LUT3 #(
.INIT(8'h4E))
STATE_i_1
(.I0(STATE_reg_n_0),
.I1(JC_IBUF),
.I2(\COUNT[10]_i_4_n_0 ),
.O(STATE_i_1_n_0));
FDRE STATE_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(STATE_i_1_n_0),
.Q(STATE_reg_n_0),
.R(INTERNAL_RST_reg));
LUT3 #(
.INIT(8'h09))
S_DATA_IN_ACK_i_1
(.I0(STATE_reg_n_0),
.I1(JC_IBUF),
.I2(INTERNAL_RST_reg),
.O(S_DATA_IN_ACK_i_1_n_0));
FDRE S_DATA_IN_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_DATA_IN_ACK_i_1_n_0),
.Q(JC_IBUF),
.R(1'b0));
endmodule
module rmii_ethernet
(TXEN_OBUF,
TXD_OBUF,
ETH_CLK_OBUF,
RXDV_IBUF,
RXER_IBUF,
INTERNAL_RST_reg,
D);
output TXEN_OBUF;
output [1:0]TXD_OBUF;
input ETH_CLK_OBUF;
input RXDV_IBUF;
input RXER_IBUF;
input INTERNAL_RST_reg;
input [1:0]D;
wire DONE;
wire DONE_DEL;
wire DONE_SYNC;
wire DONE_i_1_n_0;
wire ETH_CLK_OBUF;
wire GO;
wire GO_DEL;
wire GO_SYNC;
wire GO_i_1_n_0;
wire INTERNAL_RST_reg;
wire NEXTCRC32_D80108_out;
wire NEXTCRC32_D80177_out;
wire NEXTCRC32_D80181_out;
wire NEXTCRC32_D80189_out;
wire NEXTCRC32_D80195_out;
wire NEXTCRC32_D80203_out;
wire NEXTCRC32_D80217_out;
wire NEXTCRC32_D8070_out;
wire NEXTCRC32_D8074_out;
wire \PREAMBLE_COUNT[0]_i_1_n_0 ;
wire \PREAMBLE_COUNT[1]_i_1_n_0 ;
wire \PREAMBLE_COUNT[2]_i_1_n_0 ;
wire \PREAMBLE_COUNT[3]_i_1_n_0 ;
wire \PREAMBLE_COUNT[4]_i_1_n_0 ;
wire \PREAMBLE_COUNT[4]_i_2_n_0 ;
wire \PREAMBLE_COUNT[4]_i_3_n_0 ;
wire \PREAMBLE_COUNT[4]_i_4_n_0 ;
wire \PREAMBLE_COUNT_reg_n_0_[0] ;
wire \PREAMBLE_COUNT_reg_n_0_[1] ;
wire \PREAMBLE_COUNT_reg_n_0_[2] ;
wire \PREAMBLE_COUNT_reg_n_0_[3] ;
wire \PREAMBLE_COUNT_reg_n_0_[4] ;
wire S_TX_ACK_i_1_n_0;
wire S_TX_ACK_reg_n_0;
wire \TXD[0]_i_10_n_0 ;
wire \TXD[0]_i_11_n_0 ;
wire \TXD[0]_i_1_n_0 ;
wire \TXD[0]_i_2_n_0 ;
wire \TXD[0]_i_3_n_0 ;
wire \TXD[0]_i_6_n_0 ;
wire \TXD[0]_i_7_n_0 ;
wire \TXD[0]_i_8_n_0 ;
wire \TXD[0]_i_9_n_0 ;
wire \TXD[1]_i_10_n_0 ;
wire \TXD[1]_i_11_n_0 ;
wire \TXD[1]_i_12_n_0 ;
wire \TXD[1]_i_1_n_0 ;
wire \TXD[1]_i_2_n_0 ;
wire \TXD[1]_i_3_n_0 ;
wire \TXD[1]_i_4_n_0 ;
wire \TXD[1]_i_7_n_0 ;
wire \TXD[1]_i_8_n_0 ;
wire \TXD[1]_i_9_n_0 ;
wire [1:0]TXD_OBUF;
wire \TXD_reg[0]_i_4_n_0 ;
wire \TXD_reg[0]_i_5_n_0 ;
wire \TXD_reg[1]_i_5_n_0 ;
wire \TXD_reg[1]_i_6_n_0 ;
wire TXEN_OBUF;
wire TXEN_i_1_n_0;
wire \TX_CRC[0]_i_1_n_0 ;
wire \TX_CRC[10]_i_3_n_0 ;
wire \TX_CRC[10]_i_4_n_0 ;
wire \TX_CRC[10]_i_5_n_0 ;
wire \TX_CRC[11]_i_1_n_0 ;
wire \TX_CRC[11]_i_2_n_0 ;
wire \TX_CRC[11]_i_3_n_0 ;
wire \TX_CRC[11]_i_4_n_0 ;
wire \TX_CRC[12]_i_1_n_0 ;
wire \TX_CRC[12]_i_2_n_0 ;
wire \TX_CRC[12]_i_3_n_0 ;
wire \TX_CRC[12]_i_4_n_0 ;
wire \TX_CRC[12]_i_5_n_0 ;
wire \TX_CRC[12]_i_6_n_0 ;
wire \TX_CRC[12]_i_7_n_0 ;
wire \TX_CRC[13]_i_3_n_0 ;
wire \TX_CRC[13]_i_4_n_0 ;
wire \TX_CRC[13]_i_5_n_0 ;
wire \TX_CRC[14]_i_2_n_0 ;
wire \TX_CRC[14]_i_3_n_0 ;
wire \TX_CRC[14]_i_4_n_0 ;
wire \TX_CRC[14]_i_5_n_0 ;
wire \TX_CRC[15]_i_1_n_0 ;
wire \TX_CRC[15]_i_2_n_0 ;
wire \TX_CRC[15]_i_3_n_0 ;
wire \TX_CRC[15]_i_4_n_0 ;
wire \TX_CRC[15]_i_5_n_0 ;
wire \TX_CRC[16]_i_1_n_0 ;
wire \TX_CRC[16]_i_2_n_0 ;
wire \TX_CRC[16]_i_3_n_0 ;
wire \TX_CRC[17]_i_3_n_0 ;
wire \TX_CRC[17]_i_5_n_0 ;
wire \TX_CRC[18]_i_2_n_0 ;
wire \TX_CRC[18]_i_3_n_0 ;
wire \TX_CRC[19]_i_1_n_0 ;
wire \TX_CRC[19]_i_2_n_0 ;
wire \TX_CRC[1]_i_2_n_0 ;
wire \TX_CRC[1]_i_5_n_0 ;
wire \TX_CRC[20]_i_1_n_0 ;
wire \TX_CRC[21]_i_1_n_0 ;
wire \TX_CRC[22]_i_1_n_0 ;
wire \TX_CRC[23]_i_2_n_0 ;
wire \TX_CRC[24]_i_3_n_0 ;
wire \TX_CRC[24]_i_4_n_0 ;
wire \TX_CRC[24]_i_5_n_0 ;
wire \TX_CRC[25]_i_2_n_0 ;
wire \TX_CRC[25]_i_3_n_0 ;
wire \TX_CRC[26]_i_1_n_0 ;
wire \TX_CRC[26]_i_2_n_0 ;
wire \TX_CRC[26]_i_3_n_0 ;
wire \TX_CRC[26]_i_4_n_0 ;
wire \TX_CRC[27]_i_2_n_0 ;
wire \TX_CRC[27]_i_3_n_0 ;
wire \TX_CRC[27]_i_4_n_0 ;
wire \TX_CRC[28]_i_2_n_0 ;
wire \TX_CRC[28]_i_3_n_0 ;
wire \TX_CRC[29]_i_2_n_0 ;
wire \TX_CRC[29]_i_3_n_0 ;
wire \TX_CRC[29]_i_4_n_0 ;
wire \TX_CRC[29]_i_5_n_0 ;
wire \TX_CRC[2]_i_1_n_0 ;
wire \TX_CRC[2]_i_2_n_0 ;
wire \TX_CRC[2]_i_3_n_0 ;
wire \TX_CRC[2]_i_4_n_0 ;
wire \TX_CRC[2]_i_5_n_0 ;
wire \TX_CRC[30]_i_2_n_0 ;
wire \TX_CRC[30]_i_3_n_0 ;
wire \TX_CRC[31]_i_1_n_0 ;
wire \TX_CRC[31]_i_2_n_0 ;
wire \TX_CRC[31]_i_3_n_0 ;
wire \TX_CRC[3]_i_3_n_0 ;
wire \TX_CRC[3]_i_4_n_0 ;
wire \TX_CRC[4]_i_2_n_0 ;
wire \TX_CRC[4]_i_3_n_0 ;
wire \TX_CRC[4]_i_4_n_0 ;
wire \TX_CRC[4]_i_5_n_0 ;
wire \TX_CRC[5]_i_4_n_0 ;
wire \TX_CRC[5]_i_5_n_0 ;
wire \TX_CRC[5]_i_6_n_0 ;
wire \TX_CRC[6]_i_2_n_0 ;
wire \TX_CRC[6]_i_3_n_0 ;
wire \TX_CRC[6]_i_4_n_0 ;
wire \TX_CRC[6]_i_5_n_0 ;
wire \TX_CRC[7]_i_1_n_0 ;
wire \TX_CRC[7]_i_2_n_0 ;
wire \TX_CRC[7]_i_3_n_0 ;
wire \TX_CRC[7]_i_4_n_0 ;
wire \TX_CRC[8]_i_1_n_0 ;
wire \TX_CRC[9]_i_1_n_0 ;
wire \TX_CRC[9]_i_2_n_0 ;
wire \TX_CRC[9]_i_3_n_0 ;
wire \TX_CRC[9]_i_4_n_0 ;
wire \TX_CRC_reg[10]_i_1_n_0 ;
wire \TX_CRC_reg[13]_i_1_n_0 ;
wire \TX_CRC_reg[14]_i_1_n_0 ;
wire \TX_CRC_reg[17]_i_1_n_0 ;
wire \TX_CRC_reg[18]_i_1_n_0 ;
wire \TX_CRC_reg[1]_i_1_n_0 ;
wire \TX_CRC_reg[23]_i_1_n_0 ;
wire \TX_CRC_reg[24]_i_1_n_0 ;
wire \TX_CRC_reg[25]_i_1_n_0 ;
wire \TX_CRC_reg[27]_i_1_n_0 ;
wire \TX_CRC_reg[28]_i_1_n_0 ;
wire \TX_CRC_reg[29]_i_1_n_0 ;
wire \TX_CRC_reg[30]_i_1_n_0 ;
wire \TX_CRC_reg[3]_i_1_n_0 ;
wire \TX_CRC_reg[4]_i_1_n_0 ;
wire \TX_CRC_reg[5]_i_1_n_0 ;
wire \TX_CRC_reg[6]_i_1_n_0 ;
wire \TX_CRC_reg_n_0_[0] ;
wire \TX_CRC_reg_n_0_[10] ;
wire \TX_CRC_reg_n_0_[11] ;
wire \TX_CRC_reg_n_0_[12] ;
wire \TX_CRC_reg_n_0_[13] ;
wire \TX_CRC_reg_n_0_[14] ;
wire \TX_CRC_reg_n_0_[15] ;
wire \TX_CRC_reg_n_0_[16] ;
wire \TX_CRC_reg_n_0_[17] ;
wire \TX_CRC_reg_n_0_[18] ;
wire \TX_CRC_reg_n_0_[19] ;
wire \TX_CRC_reg_n_0_[20] ;
wire \TX_CRC_reg_n_0_[21] ;
wire \TX_CRC_reg_n_0_[22] ;
wire \TX_CRC_reg_n_0_[23] ;
wire \TX_CRC_reg_n_0_[8] ;
wire \TX_CRC_reg_n_0_[9] ;
wire [10:1]TX_IN_COUNT;
wire \TX_IN_COUNT[10]_i_1_n_0 ;
wire \TX_IN_COUNT[10]_i_2_n_0 ;
wire \TX_IN_COUNT[10]_i_3_n_0 ;
wire \TX_IN_COUNT[10]_i_4_n_0 ;
wire \TX_IN_COUNT[1]_i_1_n_0 ;
wire \TX_IN_COUNT[2]_i_1_n_0 ;
wire \TX_IN_COUNT[3]_i_1_n_0 ;
wire \TX_IN_COUNT[4]_i_1_n_0 ;
wire \TX_IN_COUNT[5]_i_1_n_0 ;
wire \TX_IN_COUNT[6]_i_1_n_0 ;
wire \TX_IN_COUNT[7]_i_1_n_0 ;
wire \TX_IN_COUNT[8]_i_1_n_0 ;
wire \TX_IN_COUNT[9]_i_1_n_0 ;
wire TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9;
wire TX_MEMORY_reg_n_59;
wire TX_MEMORY_reg_n_67;
wire [0:0]TX_OUT_COUNT0_in;
wire \TX_OUT_COUNT[10]_i_1_n_0 ;
wire \TX_OUT_COUNT[10]_i_2_n_0 ;
wire \TX_OUT_COUNT[10]_i_3_n_0 ;
wire \TX_OUT_COUNT[10]_i_4_n_0 ;
wire \TX_OUT_COUNT[10]_i_5_n_0 ;
wire \TX_OUT_COUNT[10]_i_6_n_0 ;
wire \TX_OUT_COUNT[10]_i_7_n_0 ;
wire \TX_OUT_COUNT[10]_i_8_n_0 ;
wire \TX_OUT_COUNT[1]_i_1_n_0 ;
wire \TX_OUT_COUNT[2]_i_1_n_0 ;
wire \TX_OUT_COUNT[3]_i_1_n_0 ;
wire \TX_OUT_COUNT[4]_i_1_n_0 ;
wire \TX_OUT_COUNT[5]_i_1_n_0 ;
wire \TX_OUT_COUNT[6]_i_1_n_0 ;
wire \TX_OUT_COUNT[7]_i_1_n_0 ;
wire \TX_OUT_COUNT[8]_i_1_n_0 ;
wire \TX_OUT_COUNT[8]_i_2_n_0 ;
wire \TX_OUT_COUNT[9]_i_1_n_0 ;
wire \TX_OUT_COUNT_reg_n_0_[0] ;
wire \TX_OUT_COUNT_reg_n_0_[10] ;
wire \TX_OUT_COUNT_reg_n_0_[1] ;
wire \TX_OUT_COUNT_reg_n_0_[2] ;
wire \TX_OUT_COUNT_reg_n_0_[3] ;
wire \TX_OUT_COUNT_reg_n_0_[4] ;
wire \TX_OUT_COUNT_reg_n_0_[5] ;
wire \TX_OUT_COUNT_reg_n_0_[6] ;
wire \TX_OUT_COUNT_reg_n_0_[7] ;
wire \TX_OUT_COUNT_reg_n_0_[8] ;
wire \TX_OUT_COUNT_reg_n_0_[9] ;
wire \TX_PACKET_STATE[0]_i_1_n_0 ;
wire \TX_PACKET_STATE[1]_i_10_n_0 ;
wire \TX_PACKET_STATE[1]_i_11_n_0 ;
wire \TX_PACKET_STATE[1]_i_12_n_0 ;
wire \TX_PACKET_STATE[1]_i_13_n_0 ;
wire \TX_PACKET_STATE[1]_i_1_n_0 ;
wire \TX_PACKET_STATE[1]_i_4_n_0 ;
wire \TX_PACKET_STATE[1]_i_5_n_0 ;
wire \TX_PACKET_STATE[1]_i_6_n_0 ;
wire \TX_PACKET_STATE[1]_i_7_n_0 ;
wire \TX_PACKET_STATE[1]_i_8_n_0 ;
wire \TX_PACKET_STATE[1]_i_9_n_0 ;
wire \TX_PACKET_STATE_reg[1]_i_2_n_2 ;
wire \TX_PACKET_STATE_reg[1]_i_3_n_0 ;
wire \TX_PACKET_STATE_reg_n_0_[0] ;
wire \TX_PACKET_STATE_reg_n_0_[1] ;
wire \TX_PHY_STATE[0]_i_1_n_0 ;
wire \TX_PHY_STATE[1]_i_1_n_0 ;
wire \TX_PHY_STATE[2]_i_1_n_0 ;
wire \TX_PHY_STATE[2]_i_2_n_0 ;
wire \TX_PHY_STATE[2]_i_3_n_0 ;
wire \TX_PHY_STATE[2]_i_4_n_0 ;
wire \TX_PHY_STATE[3]_i_1_n_0 ;
wire \TX_PHY_STATE[3]_i_2_n_0 ;
wire \TX_PHY_STATE[3]_i_3_n_0 ;
wire \TX_PHY_STATE[3]_i_4_n_0 ;
wire \TX_PHY_STATE[3]_i_5_n_0 ;
wire \TX_PHY_STATE[4]_i_1_n_0 ;
wire \TX_PHY_STATE[4]_i_2_n_0 ;
wire \TX_PHY_STATE[4]_i_3_n_0 ;
wire \TX_PHY_STATE[4]_i_4_n_0 ;
wire \TX_PHY_STATE_reg_n_0_[0] ;
wire \TX_PHY_STATE_reg_n_0_[1] ;
wire \TX_PHY_STATE_reg_n_0_[2] ;
wire \TX_PHY_STATE_reg_n_0_[3] ;
wire \TX_PHY_STATE_reg_n_0_[4] ;
wire [10:0]TX_READ_ADDRESS;
wire [10:1]TX_READ_ADDRESS0;
wire \TX_READ_ADDRESS_rep[0]_i_1_n_0 ;
wire \TX_READ_ADDRESS_rep[9]_i_1_n_0 ;
wire \TX_READ_ADDRESS_rep[9]_i_2_n_0 ;
wire \TX_READ_ADDRESS_rep[9]_i_4_n_0 ;
wire TX_WRITE;
wire [10:0]TX_WRITE_ADDRESS;
wire \TX_WRITE_ADDRESS[0]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[10]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[10]_i_2_n_0 ;
wire \TX_WRITE_ADDRESS[10]_i_3_n_0 ;
wire \TX_WRITE_ADDRESS[1]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[2]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[3]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[4]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[5]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[5]_i_2_n_0 ;
wire \TX_WRITE_ADDRESS[6]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[7]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[8]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[9]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[9]_i_2_n_0 ;
wire [10:0]TX_WRITE_ADDRESS_DEL;
wire TX_WRITE_i_1_n_0;
wire p_0_in167_in;
wire p_0_in66_in;
wire p_168_in;
wire [1:0]p_16_in;
wire [1:0]p_17_in;
wire [1:0]p_18_in;
wire p_1_in126_in;
wire p_1_in128_in;
wire p_1_in130_in;
wire p_1_in132_in;
wire p_1_in133_in;
wire p_1_in135_in;
wire p_1_in136_in;
wire p_202_in;
wire [1:0]p_20_in;
wire p_214_in;
wire [1:0]p_21_in;
wire p_222_in;
wire p_224_in;
wire [1:0]p_22_in;
wire [7:0]slv1_out;
wire NLW_TX_MEMORY_reg_CASCADEOUTA_UNCONNECTED;
wire NLW_TX_MEMORY_reg_CASCADEOUTB_UNCONNECTED;
wire NLW_TX_MEMORY_reg_DBITERR_UNCONNECTED;
wire NLW_TX_MEMORY_reg_INJECTDBITERR_UNCONNECTED;
wire NLW_TX_MEMORY_reg_INJECTSBITERR_UNCONNECTED;
wire NLW_TX_MEMORY_reg_REGCEAREGCE_UNCONNECTED;
wire NLW_TX_MEMORY_reg_REGCEB_UNCONNECTED;
wire NLW_TX_MEMORY_reg_SBITERR_UNCONNECTED;
wire [31:0]NLW_TX_MEMORY_reg_DOADO_UNCONNECTED;
wire [31:16]NLW_TX_MEMORY_reg_DOBDO_UNCONNECTED;
wire [3:0]NLW_TX_MEMORY_reg_DOPADOP_UNCONNECTED;
wire [3:0]NLW_TX_MEMORY_reg_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_TX_MEMORY_reg_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_TX_MEMORY_reg_RDADDRECC_UNCONNECTED;
wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED ;
wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_2_O_UNCONNECTED ;
wire [2:0]\NLW_TX_PACKET_STATE_reg[1]_i_3_CO_UNCONNECTED ;
wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_3_O_UNCONNECTED ;
FDRE DONE_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(DONE),
.Q(DONE_DEL),
.R(1'b0));
FDRE DONE_SYNC_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(DONE_DEL),
.Q(DONE_SYNC),
.R(1'b0));
LUT6 #(
.INIT(64'hBFFFFFFF80000000))
DONE_i_1
(.I0(GO_SYNC),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[1] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(DONE),
.O(DONE_i_1_n_0));
FDRE DONE_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(DONE_i_1_n_0),
.Q(DONE),
.R(INTERNAL_RST_reg));
FDRE GO_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(GO),
.Q(GO_DEL),
.R(1'b0));
FDRE GO_SYNC_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(GO_DEL),
.Q(GO_SYNC),
.R(1'b0));
LUT4 #(
.INIT(16'hF704))
GO_i_1
(.I0(DONE_SYNC),
.I1(\TX_PACKET_STATE_reg_n_0_[1] ),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.I3(GO),
.O(GO_i_1_n_0));
FDRE GO_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(GO_i_1_n_0),
.Q(GO),
.R(INTERNAL_RST_reg));
LUT1 #(
.INIT(2'h1))
\PREAMBLE_COUNT[0]_i_1
(.I0(\PREAMBLE_COUNT_reg_n_0_[0] ),
.O(\PREAMBLE_COUNT[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair149" *)
LUT2 #(
.INIT(4'h9))
\PREAMBLE_COUNT[1]_i_1
(.I0(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
.O(\PREAMBLE_COUNT[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFDFDFDDD00000020))
\PREAMBLE_COUNT[2]_i_1
(.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.I2(\TX_PHY_STATE_reg_n_0_[0] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I4(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I5(\PREAMBLE_COUNT_reg_n_0_[2] ),
.O(\PREAMBLE_COUNT[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair149" *)
LUT4 #(
.INIT(16'hFE01))
\PREAMBLE_COUNT[3]_i_1
(.I0(\PREAMBLE_COUNT_reg_n_0_[2] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I2(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[3] ),
.O(\PREAMBLE_COUNT[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\PREAMBLE_COUNT[4]_i_1
(.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.I2(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\PREAMBLE_COUNT[4]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\PREAMBLE_COUNT[4]_i_2
(.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.O(\PREAMBLE_COUNT[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFE0001))
\PREAMBLE_COUNT[4]_i_3
(.I0(\PREAMBLE_COUNT_reg_n_0_[3] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I2(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[2] ),
.I4(\PREAMBLE_COUNT_reg_n_0_[4] ),
.O(\PREAMBLE_COUNT[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000001110100))
\PREAMBLE_COUNT[4]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE[4]_i_4_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(GO_SYNC),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\PREAMBLE_COUNT[4]_i_4_n_0 ));
FDSE \PREAMBLE_COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[0]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[0] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
FDSE \PREAMBLE_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[1]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[1] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
FDRE \PREAMBLE_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PREAMBLE_COUNT[2]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[2] ),
.R(1'b0));
FDSE \PREAMBLE_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[3]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[3] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
FDSE \PREAMBLE_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[4]_i_3_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[4] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
LUT4 #(
.INIT(16'hAE55))
S_TX_ACK_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_PACKET_STATE_reg_n_0_[0] ),
.I2(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I3(S_TX_ACK_reg_n_0),
.O(S_TX_ACK_i_1_n_0));
FDRE S_TX_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_TX_ACK_i_1_n_0),
.Q(S_TX_ACK_reg_n_0),
.R(INTERNAL_RST_reg));
(* SOFT_HLUTNM = "soft_lutpair158" *)
LUT3 #(
.INIT(8'hB8))
\TXD[0]_i_1
(.I0(\TXD[0]_i_2_n_0 ),
.I1(\TXD[1]_i_3_n_0 ),
.I2(TXD_OBUF[0]),
.O(\TXD[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[0]_i_10
(.I0(p_18_in[0]),
.I1(TX_MEMORY_reg_n_67),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_20_in[0]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_21_in[0]),
.O(\TXD[0]_i_10_n_0 ));
LUT6 #(
.INIT(64'h5F503F3F5F503030))
\TXD[0]_i_11
(.I0(slv1_out[5]),
.I1(slv1_out[7]),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_16_in[0]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_17_in[0]),
.O(\TXD[0]_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[0]_i_2
(.I0(\TXD[0]_i_3_n_0 ),
.I1(\TXD_reg[0]_i_4_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TXD_reg[0]_i_5_n_0 ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.I5(\TXD[0]_i_6_n_0 ),
.O(\TXD[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h47FF4700))
\TXD[0]_i_3
(.I0(p_1_in126_in),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(p_1_in130_in),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TXD[0]_i_7_n_0 ),
.O(\TXD[0]_i_3_n_0 ));
LUT5 #(
.INIT(32'hE2FFFFFF))
\TXD[0]_i_6
(.I0(TX_MEMORY_reg_n_59),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(p_22_in[0]),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TXD[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[0]_i_7
(.I0(p_1_in133_in),
.I1(p_1_in136_in),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[9] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[11] ),
.O(\TXD[0]_i_7_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[0]_i_8
(.I0(\TX_CRC_reg_n_0_[21] ),
.I1(\TX_CRC_reg_n_0_[23] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(slv1_out[1]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(slv1_out[3]),
.O(\TXD[0]_i_8_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[0]_i_9
(.I0(\TX_CRC_reg_n_0_[13] ),
.I1(\TX_CRC_reg_n_0_[15] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[17] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[19] ),
.O(\TXD[0]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair158" *)
LUT3 #(
.INIT(8'hB8))
\TXD[1]_i_1
(.I0(\TXD[1]_i_2_n_0 ),
.I1(\TXD[1]_i_3_n_0 ),
.I2(TXD_OBUF[1]),
.O(\TXD[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[1]_i_10
(.I0(\TX_CRC_reg_n_0_[12] ),
.I1(\TX_CRC_reg_n_0_[14] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[16] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[18] ),
.O(\TXD[1]_i_10_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[1]_i_11
(.I0(p_18_in[1]),
.I1(p_0_in66_in),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_20_in[1]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_21_in[1]),
.O(\TXD[1]_i_11_n_0 ));
LUT6 #(
.INIT(64'h5F503F3F5F503030))
\TXD[1]_i_12
(.I0(slv1_out[4]),
.I1(slv1_out[6]),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_16_in[1]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_17_in[1]),
.O(\TXD[1]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[1]_i_2
(.I0(\TXD[1]_i_4_n_0 ),
.I1(\TXD_reg[1]_i_5_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TXD_reg[1]_i_6_n_0 ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.I5(\TXD[1]_i_7_n_0 ),
.O(\TXD[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'hBFFFFFFE))
\TXD[1]_i_3
(.I0(\TX_PHY_STATE_reg_n_0_[0] ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[1] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.O(\TXD[1]_i_3_n_0 ));
LUT5 #(
.INIT(32'h47FF4700))
\TXD[1]_i_4
(.I0(\TX_CRC_reg_n_0_[0] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(p_1_in128_in),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TXD[1]_i_8_n_0 ),
.O(\TXD[1]_i_4_n_0 ));
LUT5 #(
.INIT(32'hA8882808))
\TXD[1]_i_7
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_0_in167_in),
.I4(p_22_in[1]),
.O(\TXD[1]_i_7_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[1]_i_8
(.I0(p_1_in132_in),
.I1(p_1_in135_in),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[8] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[10] ),
.O(\TXD[1]_i_8_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[1]_i_9
(.I0(\TX_CRC_reg_n_0_[20] ),
.I1(\TX_CRC_reg_n_0_[22] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(slv1_out[0]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(slv1_out[2]),
.O(\TXD[1]_i_9_n_0 ));
FDRE \TXD_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TXD[0]_i_1_n_0 ),
.Q(TXD_OBUF[0]),
.R(INTERNAL_RST_reg));
MUXF7 \TXD_reg[0]_i_4
(.I0(\TXD[0]_i_8_n_0 ),
.I1(\TXD[0]_i_9_n_0 ),
.O(\TXD_reg[0]_i_4_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
MUXF7 \TXD_reg[0]_i_5
(.I0(\TXD[0]_i_10_n_0 ),
.I1(\TXD[0]_i_11_n_0 ),
.O(\TXD_reg[0]_i_5_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDRE \TXD_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TXD[1]_i_1_n_0 ),
.Q(TXD_OBUF[1]),
.R(INTERNAL_RST_reg));
MUXF7 \TXD_reg[1]_i_5
(.I0(\TXD[1]_i_9_n_0 ),
.I1(\TXD[1]_i_10_n_0 ),
.O(\TXD_reg[1]_i_5_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
MUXF7 \TXD_reg[1]_i_6
(.I0(\TXD[1]_i_11_n_0 ),
.I1(\TXD[1]_i_12_n_0 ),
.O(\TXD_reg[1]_i_6_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
LUT6 #(
.INIT(64'h7F7FFFFF00000100))
TXEN_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.I5(TXEN_OBUF),
.O(TXEN_i_1_n_0));
FDRE TXEN_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TXEN_i_1_n_0),
.Q(TXEN_OBUF),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h8BB8744774478BB8))
\TX_CRC[0]_i_1
(.I0(\TX_CRC[12]_i_3_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_0_in167_in),
.I3(p_20_in[1]),
.I4(slv1_out[6]),
.I5(slv1_out[0]),
.O(\TX_CRC[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_2
(.I0(p_21_in[1]),
.I1(p_20_in[1]),
.I2(\TX_CRC[10]_i_4_n_0 ),
.I3(p_21_in[0]),
.I4(p_22_in[0]),
.O(NEXTCRC32_D80189_out));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_3
(.I0(slv1_out[2]),
.I1(slv1_out[3]),
.I2(p_18_in[0]),
.I3(slv1_out[0]),
.I4(\TX_CRC[10]_i_5_n_0 ),
.O(\TX_CRC[10]_i_3_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_4
(.I0(p_1_in128_in),
.I1(slv1_out[5]),
.I2(slv1_out[0]),
.I3(slv1_out[3]),
.I4(slv1_out[2]),
.O(\TX_CRC[10]_i_4_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_5
(.I0(slv1_out[5]),
.I1(p_1_in128_in),
.I2(p_16_in[1]),
.I3(p_17_in[1]),
.I4(p_17_in[0]),
.O(\TX_CRC[10]_i_5_n_0 ));
LUT6 #(
.INIT(64'hF0660F990F99F066))
\TX_CRC[11]_i_1
(.I0(p_21_in[0]),
.I1(\TX_CRC[11]_i_2_n_0 ),
.I2(\TX_CRC[11]_i_3_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(p_1_in130_in),
.I5(slv1_out[4]),
.O(\TX_CRC[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[11]_i_2
(.I0(p_22_in[1]),
.I1(p_20_in[1]),
.I2(slv1_out[0]),
.I3(slv1_out[1]),
.I4(slv1_out[3]),
.I5(p_20_in[0]),
.O(\TX_CRC[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[11]_i_3
(.I0(p_16_in[1]),
.I1(p_17_in[0]),
.I2(slv1_out[0]),
.I3(p_16_in[0]),
.I4(slv1_out[1]),
.I5(\TX_CRC[11]_i_4_n_0 ),
.O(\TX_CRC[11]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[11]_i_4
(.I0(slv1_out[3]),
.I1(p_18_in[1]),
.O(\TX_CRC[11]_i_4_n_0 ));
LUT6 #(
.INIT(64'h960096FF96FF9600))
\TX_CRC[12]_i_1
(.I0(\TX_CRC[12]_i_2_n_0 ),
.I1(\TX_CRC[12]_i_3_n_0 ),
.I2(\TX_CRC[12]_i_4_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_CRC[12]_i_5_n_0 ),
.I5(\TX_CRC[12]_i_6_n_0 ),
.O(\TX_CRC[12]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[12]_i_2
(.I0(p_18_in[0]),
.I1(p_16_in[0]),
.O(\TX_CRC[12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[12]_i_3
(.I0(p_16_in[1]),
.I1(p_0_in66_in),
.O(\TX_CRC[12]_i_3_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[12]_i_4
(.I0(p_17_in[1]),
.I1(p_1_in132_in),
.I2(slv1_out[5]),
.I3(p_18_in[1]),
.I4(\TX_CRC[12]_i_7_n_0 ),
.O(\TX_CRC[12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[12]_i_5
(.I0(p_22_in[0]),
.I1(p_20_in[0]),
.O(\TX_CRC[12]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[12]_i_6
(.I0(\TX_CRC[2]_i_4_n_0 ),
.I1(p_20_in[1]),
.I2(\TX_CRC[12]_i_7_n_0 ),
.I3(slv1_out[5]),
.I4(p_1_in132_in),
.I5(p_22_in[1]),
.O(\TX_CRC[12]_i_6_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[12]_i_7
(.I0(slv1_out[6]),
.I1(slv1_out[2]),
.I2(slv1_out[0]),
.I3(slv1_out[1]),
.I4(slv1_out[4]),
.O(\TX_CRC[12]_i_7_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[13]_i_2
(.I0(\TX_CRC[2]_i_4_n_0 ),
.I1(p_20_in[0]),
.I2(p_22_in[0]),
.I3(\TX_CRC[13]_i_4_n_0 ),
.I4(p_21_in[0]),
.I5(TX_MEMORY_reg_n_59),
.O(NEXTCRC32_D80195_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[13]_i_3
(.I0(\TX_CRC[13]_i_5_n_0 ),
.I1(TX_MEMORY_reg_n_67),
.I2(p_18_in[0]),
.I3(\TX_CRC[13]_i_4_n_0 ),
.I4(p_0_in66_in),
.I5(p_16_in[0]),
.O(\TX_CRC[13]_i_3_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[13]_i_4
(.I0(\TX_CRC[3]_i_4_n_0 ),
.I1(slv1_out[1]),
.I2(slv1_out[5]),
.I3(slv1_out[6]),
.I4(p_1_in133_in),
.O(\TX_CRC[13]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[13]_i_5
(.I0(p_17_in[0]),
.I1(p_17_in[1]),
.O(\TX_CRC[13]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_2
(.I0(p_21_in[1]),
.I1(p_0_in167_in),
.I2(p_21_in[0]),
.I3(\TX_CRC[14]_i_4_n_0 ),
.I4(TX_MEMORY_reg_n_59),
.I5(p_22_in[1]),
.O(\TX_CRC[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_3
(.I0(p_18_in[1]),
.I1(slv1_out[3]),
.I2(p_17_in[1]),
.I3(\TX_CRC[14]_i_5_n_0 ),
.I4(TX_MEMORY_reg_n_67),
.I5(p_0_in66_in),
.O(\TX_CRC[14]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_4
(.I0(p_1_in135_in),
.I1(slv1_out[7]),
.I2(slv1_out[4]),
.I3(slv1_out[3]),
.I4(slv1_out[6]),
.I5(slv1_out[2]),
.O(\TX_CRC[14]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_5
(.I0(p_17_in[0]),
.I1(slv1_out[2]),
.I2(slv1_out[6]),
.I3(slv1_out[4]),
.I4(slv1_out[7]),
.I5(p_1_in135_in),
.O(\TX_CRC[14]_i_5_n_0 ));
LUT6 #(
.INIT(64'h9F90606F909F6F60))
\TX_CRC[15]_i_1
(.I0(\TX_CRC[15]_i_2_n_0 ),
.I1(\TX_CRC[15]_i_3_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_CRC[15]_i_4_n_0 ),
.I4(slv1_out[3]),
.I5(\TX_CRC[15]_i_5_n_0 ),
.O(\TX_CRC[15]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[15]_i_2
(.I0(p_18_in[1]),
.I1(slv1_out[4]),
.O(\TX_CRC[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[15]_i_3
(.I0(TX_MEMORY_reg_n_67),
.I1(p_17_in[0]),
.I2(slv1_out[5]),
.I3(p_18_in[0]),
.I4(slv1_out[7]),
.I5(p_1_in136_in),
.O(\TX_CRC[15]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[15]_i_4
(.I0(slv1_out[4]),
.I1(p_22_in[1]),
.O(\TX_CRC[15]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[15]_i_5
(.I0(p_21_in[0]),
.I1(p_22_in[0]),
.I2(slv1_out[5]),
.I3(TX_MEMORY_reg_n_59),
.I4(slv1_out[7]),
.I5(p_1_in136_in),
.O(\TX_CRC[15]_i_5_n_0 ));
LUT6 #(
.INIT(64'h9F90606F909F6F60))
\TX_CRC[16]_i_1
(.I0(p_18_in[1]),
.I1(\TX_CRC[16]_i_2_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(slv1_out[4]),
.I4(slv1_out[0]),
.I5(\TX_CRC[16]_i_3_n_0 ),
.O(\TX_CRC[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[16]_i_2
(.I0(p_18_in[0]),
.I1(slv1_out[4]),
.I2(slv1_out[5]),
.I3(\TX_CRC_reg_n_0_[8] ),
.I4(p_16_in[1]),
.O(\TX_CRC[16]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[16]_i_3
(.I0(p_20_in[1]),
.I1(p_22_in[1]),
.I2(p_22_in[0]),
.I3(slv1_out[5]),
.I4(\TX_CRC_reg_n_0_[8] ),
.O(\TX_CRC[16]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[17]_i_2
(.I0(slv1_out[1]),
.I1(p_0_in167_in),
.I2(p_22_in[0]),
.I3(slv1_out[5]),
.I4(p_202_in),
.I5(p_20_in[0]),
.O(NEXTCRC32_D80203_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[17]_i_3
(.I0(\TX_CRC[17]_i_5_n_0 ),
.I1(slv1_out[6]),
.I2(\TX_CRC_reg_n_0_[9] ),
.I3(slv1_out[5]),
.I4(slv1_out[1]),
.I5(p_18_in[0]),
.O(\TX_CRC[17]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[17]_i_4
(.I0(slv1_out[6]),
.I1(\TX_CRC_reg_n_0_[9] ),
.O(p_202_in));
LUT2 #(
.INIT(4'h6))
\TX_CRC[17]_i_5
(.I0(p_0_in66_in),
.I1(p_16_in[0]),
.O(\TX_CRC[17]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[18]_i_2
(.I0(slv1_out[2]),
.I1(\TX_CRC[2]_i_4_n_0 ),
.I2(slv1_out[6]),
.I3(TX_MEMORY_reg_n_59),
.I4(\TX_CRC_reg_n_0_[10] ),
.I5(slv1_out[7]),
.O(\TX_CRC[18]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[18]_i_3
(.I0(\TX_CRC[29]_i_5_n_0 ),
.I1(slv1_out[7]),
.I2(\TX_CRC_reg_n_0_[10] ),
.I3(slv1_out[6]),
.I4(slv1_out[2]),
.I5(p_17_in[1]),
.O(\TX_CRC[18]_i_3_n_0 ));
LUT6 #(
.INIT(64'h9F90909F606F6F60))
\TX_CRC[19]_i_1
(.I0(TX_MEMORY_reg_n_67),
.I1(p_17_in[0]),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(TX_MEMORY_reg_n_59),
.I4(p_21_in[0]),
.I5(\TX_CRC[19]_i_2_n_0 ),
.O(\TX_CRC[19]_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\TX_CRC[19]_i_2
(.I0(\TX_CRC_reg_n_0_[11] ),
.I1(slv1_out[7]),
.I2(slv1_out[3]),
.O(\TX_CRC[19]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[1]_i_2
(.I0(p_0_in167_in),
.I1(p_20_in[0]),
.I2(p_20_in[1]),
.I3(\TX_CRC[24]_i_4_n_0 ),
.I4(TX_MEMORY_reg_n_59),
.I5(p_168_in),
.O(\TX_CRC[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[1]_i_3
(.I0(\TX_CRC[1]_i_5_n_0 ),
.I1(slv1_out[1]),
.I2(slv1_out[7]),
.I3(TX_MEMORY_reg_n_67),
.I4(slv1_out[0]),
.O(NEXTCRC32_D8070_out));
LUT2 #(
.INIT(4'h6))
\TX_CRC[1]_i_4
(.I0(slv1_out[0]),
.I1(slv1_out[6]),
.O(p_168_in));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[1]_i_5
(.I0(p_16_in[0]),
.I1(slv1_out[6]),
.I2(p_0_in66_in),
.I3(p_16_in[1]),
.O(\TX_CRC[1]_i_5_n_0 ));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[20]_i_1
(.I0(p_18_in[1]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_22_in[1]),
.I3(slv1_out[4]),
.I4(\TX_CRC_reg_n_0_[12] ),
.O(\TX_CRC[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[21]_i_1
(.I0(p_18_in[0]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_22_in[0]),
.I3(\TX_CRC_reg_n_0_[13] ),
.I4(slv1_out[5]),
.O(\TX_CRC[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[22]_i_1
(.I0(p_16_in[1]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_20_in[1]),
.I3(\TX_CRC_reg_n_0_[14] ),
.I4(slv1_out[0]),
.O(\TX_CRC[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[23]_i_2
(.I0(p_20_in[1]),
.I1(slv1_out[0]),
.I2(p_20_in[0]),
.I3(p_0_in167_in),
.I4(p_214_in),
.I5(slv1_out[6]),
.O(\TX_CRC[23]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[23]_i_3
(.I0(\TX_CRC[12]_i_3_n_0 ),
.I1(slv1_out[6]),
.I2(p_16_in[0]),
.I3(slv1_out[0]),
.I4(slv1_out[1]),
.I5(\TX_CRC_reg_n_0_[15] ),
.O(NEXTCRC32_D80108_out));
LUT2 #(
.INIT(4'h6))
\TX_CRC[23]_i_4
(.I0(slv1_out[1]),
.I1(\TX_CRC_reg_n_0_[15] ),
.O(p_214_in));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[24]_i_2
(.I0(\TX_CRC[24]_i_4_n_0 ),
.I1(TX_MEMORY_reg_n_59),
.I2(slv1_out[2]),
.I3(\TX_CRC_reg_n_0_[16] ),
.I4(p_20_in[0]),
.I5(p_21_in[1]),
.O(NEXTCRC32_D80217_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[24]_i_3
(.I0(TX_MEMORY_reg_n_67),
.I1(p_16_in[0]),
.I2(\TX_CRC_reg_n_0_[16] ),
.I3(slv1_out[2]),
.I4(slv1_out[7]),
.I5(\TX_CRC[24]_i_5_n_0 ),
.O(\TX_CRC[24]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[24]_i_4
(.I0(slv1_out[7]),
.I1(slv1_out[1]),
.O(\TX_CRC[24]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[24]_i_5
(.I0(slv1_out[1]),
.I1(p_17_in[1]),
.O(\TX_CRC[24]_i_5_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[25]_i_2
(.I0(slv1_out[3]),
.I1(\TX_CRC_reg_n_0_[17] ),
.I2(slv1_out[2]),
.I3(p_21_in[1]),
.I4(p_21_in[0]),
.O(\TX_CRC[25]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[25]_i_3
(.I0(slv1_out[2]),
.I1(p_17_in[1]),
.I2(slv1_out[3]),
.I3(\TX_CRC_reg_n_0_[17] ),
.I4(p_17_in[0]),
.O(\TX_CRC[25]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996FFFF69960000))
\TX_CRC[26]_i_1
(.I0(p_16_in[1]),
.I1(\TX_CRC[26]_i_2_n_0 ),
.I2(p_0_in66_in),
.I3(p_17_in[0]),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(\TX_CRC[26]_i_3_n_0 ),
.O(\TX_CRC[26]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[26]_i_2
(.I0(p_18_in[1]),
.I1(slv1_out[6]),
.I2(slv1_out[3]),
.I3(slv1_out[0]),
.I4(\TX_CRC_reg_n_0_[18] ),
.I5(slv1_out[4]),
.O(\TX_CRC[26]_i_2_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[26]_i_3
(.I0(p_0_in167_in),
.I1(p_20_in[1]),
.I2(\TX_CRC[26]_i_4_n_0 ),
.I3(p_22_in[1]),
.O(\TX_CRC[26]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[26]_i_4
(.I0(p_21_in[0]),
.I1(slv1_out[6]),
.I2(slv1_out[3]),
.I3(slv1_out[0]),
.I4(\TX_CRC_reg_n_0_[18] ),
.I5(slv1_out[4]),
.O(\TX_CRC[26]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[27]_i_2
(.I0(p_22_in[1]),
.I1(slv1_out[1]),
.I2(\TX_CRC[12]_i_5_n_0 ),
.I3(\TX_CRC[27]_i_4_n_0 ),
.I4(p_222_in),
.I5(TX_MEMORY_reg_n_59),
.O(\TX_CRC[27]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[27]_i_3
(.I0(slv1_out[1]),
.I1(\TX_CRC[12]_i_2_n_0 ),
.I2(p_18_in[1]),
.I3(\TX_CRC[27]_i_4_n_0 ),
.I4(TX_MEMORY_reg_n_67),
.I5(p_222_in),
.O(\TX_CRC[27]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[27]_i_4
(.I0(slv1_out[7]),
.I1(slv1_out[4]),
.O(\TX_CRC[27]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[27]_i_5
(.I0(slv1_out[5]),
.I1(\TX_CRC_reg_n_0_[19] ),
.O(p_222_in));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[28]_i_2
(.I0(slv1_out[2]),
.I1(p_0_in167_in),
.I2(p_22_in[0]),
.I3(slv1_out[5]),
.I4(p_224_in),
.I5(p_21_in[1]),
.O(\TX_CRC[28]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[28]_i_3
(.I0(slv1_out[2]),
.I1(slv1_out[5]),
.I2(p_18_in[0]),
.I3(p_17_in[1]),
.I4(p_0_in66_in),
.I5(p_224_in),
.O(\TX_CRC[28]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[28]_i_4
(.I0(slv1_out[6]),
.I1(\TX_CRC_reg_n_0_[20] ),
.O(p_224_in));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[29]_i_2
(.I0(\TX_CRC[29]_i_4_n_0 ),
.I1(p_0_in167_in),
.I2(p_21_in[0]),
.I3(\TX_CRC_reg_n_0_[21] ),
.I4(slv1_out[7]),
.I5(TX_MEMORY_reg_n_59),
.O(\TX_CRC[29]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[29]_i_3
(.I0(slv1_out[6]),
.I1(\TX_CRC[29]_i_5_n_0 ),
.I2(slv1_out[3]),
.I3(p_17_in[0]),
.I4(\TX_CRC_reg_n_0_[21] ),
.I5(slv1_out[7]),
.O(\TX_CRC[29]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[29]_i_4
(.I0(slv1_out[3]),
.I1(slv1_out[6]),
.O(\TX_CRC[29]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[29]_i_5
(.I0(TX_MEMORY_reg_n_67),
.I1(p_0_in66_in),
.O(\TX_CRC[29]_i_5_n_0 ));
LUT6 #(
.INIT(64'h4B78784B784B4B78))
\TX_CRC[2]_i_1
(.I0(\TX_CRC[2]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(slv1_out[0]),
.I3(\TX_CRC[2]_i_3_n_0 ),
.I4(p_20_in[0]),
.I5(\TX_CRC[2]_i_4_n_0 ),
.O(\TX_CRC[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[2]_i_2
(.I0(p_0_in66_in),
.I1(p_16_in[0]),
.I2(TX_MEMORY_reg_n_67),
.I3(\TX_CRC[2]_i_5_n_0 ),
.I4(p_16_in[1]),
.I5(p_17_in[1]),
.O(\TX_CRC[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[2]_i_3
(.I0(p_20_in[1]),
.I1(TX_MEMORY_reg_n_59),
.I2(slv1_out[2]),
.I3(slv1_out[1]),
.I4(slv1_out[7]),
.I5(slv1_out[6]),
.O(\TX_CRC[2]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[2]_i_4
(.I0(p_0_in167_in),
.I1(p_21_in[1]),
.O(\TX_CRC[2]_i_4_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[2]_i_5
(.I0(slv1_out[6]),
.I1(slv1_out[7]),
.I2(slv1_out[1]),
.I3(slv1_out[2]),
.O(\TX_CRC[2]_i_5_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[30]_i_2
(.I0(p_22_in[1]),
.I1(slv1_out[4]),
.I2(TX_MEMORY_reg_n_59),
.I3(slv1_out[7]),
.I4(\TX_CRC_reg_n_0_[22] ),
.O(\TX_CRC[30]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[30]_i_3
(.I0(slv1_out[4]),
.I1(p_18_in[1]),
.I2(slv1_out[7]),
.I3(\TX_CRC_reg_n_0_[22] ),
.I4(TX_MEMORY_reg_n_67),
.O(\TX_CRC[30]_i_3_n_0 ));
LUT5 #(
.INIT(32'h00000008))
\TX_CRC[31]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_CRC[31]_i_1_n_0 ));
LUT5 #(
.INIT(32'h10101000))
\TX_CRC[31]_i_2
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE_reg_n_0_[1] ),
.I2(\TX_PHY_STATE_reg_n_0_[0] ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_CRC[31]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[31]_i_3
(.I0(p_18_in[0]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_22_in[0]),
.I3(\TX_CRC_reg_n_0_[23] ),
.I4(slv1_out[5]),
.O(\TX_CRC[31]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[3]_i_2
(.I0(p_21_in[1]),
.I1(TX_MEMORY_reg_n_59),
.I2(p_21_in[0]),
.I3(\TX_CRC[3]_i_4_n_0 ),
.I4(slv1_out[1]),
.I5(p_20_in[0]),
.O(NEXTCRC32_D80177_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[3]_i_3
(.I0(TX_MEMORY_reg_n_67),
.I1(p_16_in[0]),
.I2(p_17_in[0]),
.I3(\TX_CRC[3]_i_4_n_0 ),
.I4(slv1_out[1]),
.I5(p_17_in[1]),
.O(\TX_CRC[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\TX_CRC[3]_i_4
(.I0(slv1_out[7]),
.I1(slv1_out[2]),
.I2(slv1_out[3]),
.O(\TX_CRC[3]_i_4_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[4]_i_2
(.I0(p_21_in[1]),
.I1(p_0_in167_in),
.I2(\TX_CRC[4]_i_4_n_0 ),
.I3(p_22_in[1]),
.I4(p_21_in[0]),
.O(\TX_CRC[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[4]_i_3
(.I0(slv1_out[4]),
.I1(slv1_out[3]),
.I2(slv1_out[0]),
.I3(p_18_in[1]),
.I4(\TX_CRC[4]_i_5_n_0 ),
.O(\TX_CRC[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[4]_i_4
(.I0(p_20_in[1]),
.I1(slv1_out[2]),
.I2(slv1_out[6]),
.I3(slv1_out[3]),
.I4(slv1_out[0]),
.I5(slv1_out[4]),
.O(\TX_CRC[4]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[4]_i_5
(.I0(p_17_in[1]),
.I1(slv1_out[6]),
.I2(slv1_out[2]),
.I3(p_17_in[0]),
.I4(p_16_in[1]),
.I5(p_0_in66_in),
.O(\TX_CRC[4]_i_5_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[5]_i_2
(.I0(p_0_in167_in),
.I1(p_20_in[1]),
.I2(\TX_CRC[5]_i_4_n_0 ),
.I3(p_21_in[0]),
.I4(p_22_in[0]),
.O(NEXTCRC32_D80181_out));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[5]_i_3
(.I0(TX_MEMORY_reg_n_67),
.I1(p_17_in[0]),
.I2(p_16_in[1]),
.I3(p_0_in66_in),
.I4(\TX_CRC[5]_i_5_n_0 ),
.O(NEXTCRC32_D8074_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[5]_i_4
(.I0(p_20_in[0]),
.I1(TX_MEMORY_reg_n_59),
.I2(\TX_CRC[5]_i_6_n_0 ),
.I3(slv1_out[1]),
.I4(\TX_CRC[27]_i_4_n_0 ),
.I5(p_22_in[1]),
.O(\TX_CRC[5]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[5]_i_5
(.I0(\TX_CRC[12]_i_2_n_0 ),
.I1(slv1_out[1]),
.I2(slv1_out[4]),
.I3(slv1_out[7]),
.I4(\TX_CRC[5]_i_6_n_0 ),
.I5(p_18_in[1]),
.O(\TX_CRC[5]_i_5_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[5]_i_6
(.I0(slv1_out[0]),
.I1(slv1_out[5]),
.I2(slv1_out[6]),
.I3(slv1_out[3]),
.O(\TX_CRC[5]_i_6_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_2
(.I0(p_20_in[0]),
.I1(p_22_in[0]),
.I2(p_22_in[1]),
.I3(\TX_CRC[6]_i_4_n_0 ),
.I4(TX_MEMORY_reg_n_59),
.I5(\TX_CRC[2]_i_4_n_0 ),
.O(\TX_CRC[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_3
(.I0(p_18_in[0]),
.I1(p_16_in[0]),
.I2(slv1_out[2]),
.I3(slv1_out[6]),
.I4(p_17_in[1]),
.I5(\TX_CRC[6]_i_5_n_0 ),
.O(\TX_CRC[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_4
(.I0(slv1_out[4]),
.I1(slv1_out[7]),
.I2(slv1_out[1]),
.I3(slv1_out[5]),
.I4(slv1_out[6]),
.I5(slv1_out[2]),
.O(\TX_CRC[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_5
(.I0(p_0_in66_in),
.I1(TX_MEMORY_reg_n_67),
.I2(\TX_CRC[27]_i_4_n_0 ),
.I3(slv1_out[5]),
.I4(slv1_out[1]),
.I5(p_18_in[1]),
.O(\TX_CRC[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'h690096FF69FF9600))
\TX_CRC[7]_i_1
(.I0(slv1_out[5]),
.I1(p_18_in[0]),
.I2(\TX_CRC[7]_i_2_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_CRC[7]_i_3_n_0 ),
.I5(\TX_CRC[7]_i_4_n_0 ),
.O(\TX_CRC[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[7]_i_2
(.I0(TX_MEMORY_reg_n_67),
.I1(p_16_in[1]),
.I2(p_17_in[1]),
.I3(p_17_in[0]),
.O(\TX_CRC[7]_i_2_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[7]_i_3
(.I0(slv1_out[3]),
.I1(slv1_out[2]),
.I2(slv1_out[7]),
.I3(slv1_out[0]),
.O(\TX_CRC[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[7]_i_4
(.I0(p_20_in[1]),
.I1(p_21_in[1]),
.I2(slv1_out[5]),
.I3(TX_MEMORY_reg_n_59),
.I4(p_21_in[0]),
.I5(p_22_in[0]),
.O(\TX_CRC[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'hF0660F990F99F066))
\TX_CRC[8]_i_1
(.I0(p_21_in[0]),
.I1(\TX_CRC[11]_i_2_n_0 ),
.I2(\TX_CRC[11]_i_3_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_CRC_reg_n_0_[0] ),
.I5(slv1_out[4]),
.O(\TX_CRC[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8BB8B88BB88B8BB8))
\TX_CRC[9]_i_1
(.I0(\TX_CRC[9]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_22_in[1]),
.I3(slv1_out[1]),
.I4(slv1_out[4]),
.I5(\TX_CRC[9]_i_3_n_0 ),
.O(\TX_CRC[9]_i_1_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[9]_i_2
(.I0(p_18_in[0]),
.I1(p_16_in[0]),
.I2(slv1_out[5]),
.I3(p_1_in126_in),
.I4(\TX_CRC[9]_i_4_n_0 ),
.O(\TX_CRC[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[9]_i_3
(.I0(p_22_in[0]),
.I1(p_20_in[0]),
.I2(slv1_out[2]),
.I3(p_21_in[1]),
.I4(slv1_out[5]),
.I5(p_1_in126_in),
.O(\TX_CRC[9]_i_3_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[9]_i_4
(.I0(slv1_out[2]),
.I1(p_17_in[1]),
.I2(slv1_out[4]),
.I3(slv1_out[1]),
.I4(p_18_in[1]),
.O(\TX_CRC[9]_i_4_n_0 ));
FDSE \TX_CRC_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[0]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[0] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[10]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[10] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[10]_i_1
(.I0(NEXTCRC32_D80189_out),
.I1(\TX_CRC[10]_i_3_n_0 ),
.O(\TX_CRC_reg[10]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[11]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[11] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[12]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[12] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[13]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[13]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[13] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[13]_i_1
(.I0(NEXTCRC32_D80195_out),
.I1(\TX_CRC[13]_i_3_n_0 ),
.O(\TX_CRC_reg[13]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[14]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[14]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[14] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[14]_i_1
(.I0(\TX_CRC[14]_i_2_n_0 ),
.I1(\TX_CRC[14]_i_3_n_0 ),
.O(\TX_CRC_reg[14]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[15]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[15]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[15] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[16]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[16]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[16] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[17]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[17]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[17] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[17]_i_1
(.I0(NEXTCRC32_D80203_out),
.I1(\TX_CRC[17]_i_3_n_0 ),
.O(\TX_CRC_reg[17]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[18]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[18]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[18] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[18]_i_1
(.I0(\TX_CRC[18]_i_2_n_0 ),
.I1(\TX_CRC[18]_i_3_n_0 ),
.O(\TX_CRC_reg[18]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[19]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[19]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[19] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[1]_i_1_n_0 ),
.Q(p_1_in126_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[1]_i_1
(.I0(\TX_CRC[1]_i_2_n_0 ),
.I1(NEXTCRC32_D8070_out),
.O(\TX_CRC_reg[1]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[20]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[20]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[20] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[21]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[21]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[21] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[22]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[22]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[22] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[23]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[23]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[23] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[23]_i_1
(.I0(\TX_CRC[23]_i_2_n_0 ),
.I1(NEXTCRC32_D80108_out),
.O(\TX_CRC_reg[23]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[24]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[24]_i_1_n_0 ),
.Q(slv1_out[0]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[24]_i_1
(.I0(NEXTCRC32_D80217_out),
.I1(\TX_CRC[24]_i_3_n_0 ),
.O(\TX_CRC_reg[24]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[25]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[25]_i_1_n_0 ),
.Q(slv1_out[1]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[25]_i_1
(.I0(\TX_CRC[25]_i_2_n_0 ),
.I1(\TX_CRC[25]_i_3_n_0 ),
.O(\TX_CRC_reg[25]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[26]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[26]_i_1_n_0 ),
.Q(slv1_out[2]),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[27]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[27]_i_1_n_0 ),
.Q(slv1_out[3]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[27]_i_1
(.I0(\TX_CRC[27]_i_2_n_0 ),
.I1(\TX_CRC[27]_i_3_n_0 ),
.O(\TX_CRC_reg[27]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[28]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[28]_i_1_n_0 ),
.Q(slv1_out[4]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[28]_i_1
(.I0(\TX_CRC[28]_i_2_n_0 ),
.I1(\TX_CRC[28]_i_3_n_0 ),
.O(\TX_CRC_reg[28]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[29]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[29]_i_1_n_0 ),
.Q(slv1_out[5]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[29]_i_1
(.I0(\TX_CRC[29]_i_2_n_0 ),
.I1(\TX_CRC[29]_i_3_n_0 ),
.O(\TX_CRC_reg[29]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[2]_i_1_n_0 ),
.Q(p_1_in128_in),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[30]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[30]_i_1_n_0 ),
.Q(slv1_out[6]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[30]_i_1
(.I0(\TX_CRC[30]_i_2_n_0 ),
.I1(\TX_CRC[30]_i_3_n_0 ),
.O(\TX_CRC_reg[30]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[31]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[31]_i_3_n_0 ),
.Q(slv1_out[7]),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[3]_i_1_n_0 ),
.Q(p_1_in130_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[3]_i_1
(.I0(NEXTCRC32_D80177_out),
.I1(\TX_CRC[3]_i_3_n_0 ),
.O(\TX_CRC_reg[3]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[4]_i_1_n_0 ),
.Q(p_1_in132_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[4]_i_1
(.I0(\TX_CRC[4]_i_2_n_0 ),
.I1(\TX_CRC[4]_i_3_n_0 ),
.O(\TX_CRC_reg[4]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[5]_i_1_n_0 ),
.Q(p_1_in133_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[5]_i_1
(.I0(NEXTCRC32_D80181_out),
.I1(NEXTCRC32_D8074_out),
.O(\TX_CRC_reg[5]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[6]_i_1_n_0 ),
.Q(p_1_in135_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[6]_i_1
(.I0(\TX_CRC[6]_i_2_n_0 ),
.I1(\TX_CRC[6]_i_3_n_0 ),
.O(\TX_CRC_reg[6]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[7]_i_1_n_0 ),
.Q(p_1_in136_in),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[8]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[8] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[9]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[9] ),
.S(\TX_CRC[31]_i_1_n_0 ));
LUT3 #(
.INIT(8'h04))
\TX_IN_COUNT[10]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(S_TX_ACK_reg_n_0),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.O(\TX_IN_COUNT[10]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0444))
\TX_IN_COUNT[10]_i_2
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(S_TX_ACK_reg_n_0),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.I3(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.O(\TX_IN_COUNT[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'hAAAA6AAA))
\TX_IN_COUNT[10]_i_3
(.I0(TX_IN_COUNT[10]),
.I1(TX_IN_COUNT[9]),
.I2(TX_IN_COUNT[8]),
.I3(TX_IN_COUNT[7]),
.I4(\TX_IN_COUNT[10]_i_4_n_0 ),
.O(\TX_IN_COUNT[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\TX_IN_COUNT[10]_i_4
(.I0(TX_IN_COUNT[5]),
.I1(TX_IN_COUNT[3]),
.I2(TX_IN_COUNT[1]),
.I3(TX_IN_COUNT[2]),
.I4(TX_IN_COUNT[4]),
.I5(TX_IN_COUNT[6]),
.O(\TX_IN_COUNT[10]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT5 #(
.INIT(32'hFFBF0444))
\TX_IN_COUNT[1]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(S_TX_ACK_reg_n_0),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.I3(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I4(TX_IN_COUNT[1]),
.O(\TX_IN_COUNT[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFCFDFCF00002000))
\TX_IN_COUNT[2]_i_1
(.I0(TX_IN_COUNT[1]),
.I1(\TX_PACKET_STATE_reg_n_0_[1] ),
.I2(S_TX_ACK_reg_n_0),
.I3(\TX_PACKET_STATE_reg_n_0_[0] ),
.I4(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I5(TX_IN_COUNT[2]),
.O(\TX_IN_COUNT[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\TX_IN_COUNT[3]_i_1
(.I0(TX_IN_COUNT[3]),
.I1(TX_IN_COUNT[2]),
.I2(TX_IN_COUNT[1]),
.O(\TX_IN_COUNT[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT4 #(
.INIT(16'h6AAA))
\TX_IN_COUNT[4]_i_1
(.I0(TX_IN_COUNT[4]),
.I1(TX_IN_COUNT[3]),
.I2(TX_IN_COUNT[1]),
.I3(TX_IN_COUNT[2]),
.O(\TX_IN_COUNT[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\TX_IN_COUNT[5]_i_1
(.I0(TX_IN_COUNT[5]),
.I1(TX_IN_COUNT[4]),
.I2(TX_IN_COUNT[2]),
.I3(TX_IN_COUNT[1]),
.I4(TX_IN_COUNT[3]),
.O(\TX_IN_COUNT[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\TX_IN_COUNT[6]_i_1
(.I0(TX_IN_COUNT[6]),
.I1(TX_IN_COUNT[5]),
.I2(TX_IN_COUNT[3]),
.I3(TX_IN_COUNT[1]),
.I4(TX_IN_COUNT[2]),
.I5(TX_IN_COUNT[4]),
.O(\TX_IN_COUNT[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair163" *)
LUT2 #(
.INIT(4'h9))
\TX_IN_COUNT[7]_i_1
(.I0(TX_IN_COUNT[7]),
.I1(\TX_IN_COUNT[10]_i_4_n_0 ),
.O(\TX_IN_COUNT[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair163" *)
LUT3 #(
.INIT(8'hA6))
\TX_IN_COUNT[8]_i_1
(.I0(TX_IN_COUNT[8]),
.I1(TX_IN_COUNT[7]),
.I2(\TX_IN_COUNT[10]_i_4_n_0 ),
.O(\TX_IN_COUNT[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT4 #(
.INIT(16'h9AAA))
\TX_IN_COUNT[9]_i_1
(.I0(TX_IN_COUNT[9]),
.I1(\TX_IN_COUNT[10]_i_4_n_0 ),
.I2(TX_IN_COUNT[7]),
.I3(TX_IN_COUNT[8]),
.O(\TX_IN_COUNT[9]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[10]_i_3_n_0 ),
.Q(TX_IN_COUNT[10]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_IN_COUNT[1]_i_1_n_0 ),
.Q(TX_IN_COUNT[1]),
.R(1'b0));
FDRE \TX_IN_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_IN_COUNT[2]_i_1_n_0 ),
.Q(TX_IN_COUNT[2]),
.R(1'b0));
FDRE \TX_IN_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[3]_i_1_n_0 ),
.Q(TX_IN_COUNT[3]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[4]_i_1_n_0 ),
.Q(TX_IN_COUNT[4]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[5]_i_1_n_0 ),
.Q(TX_IN_COUNT[5]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[6]_i_1_n_0 ),
.Q(TX_IN_COUNT[6]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[7]_i_1_n_0 ),
.Q(TX_IN_COUNT[7]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[8]_i_1_n_0 ),
.Q(TX_IN_COUNT[8]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[9]_i_1_n_0 ),
.Q(TX_IN_COUNT[9]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENBWREN=NEW" *)
(* RTL_RAM_BITS = "16400" *)
(* RTL_RAM_NAME = "TX_MEMORY" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "2047" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "17" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
TX_MEMORY_reg
(.ADDRARDADDR({1'b1,TX_WRITE_ADDRESS_DEL,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,TX_READ_ADDRESS,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b1),
.CASCADEOUTA(NLW_TX_MEMORY_reg_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_TX_MEMORY_reg_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(ETH_CLK_OBUF),
.DBITERR(NLW_TX_MEMORY_reg_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(NLW_TX_MEMORY_reg_DOADO_UNCONNECTED[31:0]),
.DOBDO({NLW_TX_MEMORY_reg_DOBDO_UNCONNECTED[31:16],p_20_in,p_21_in,p_22_in,p_0_in167_in,TX_MEMORY_reg_n_59,p_16_in,p_17_in,p_18_in,p_0_in66_in,TX_MEMORY_reg_n_67}),
.DOPADOP(NLW_TX_MEMORY_reg_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_TX_MEMORY_reg_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_TX_MEMORY_reg_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(TX_WRITE),
.ENBWREN(TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9),
.INJECTDBITERR(NLW_TX_MEMORY_reg_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_TX_MEMORY_reg_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_TX_MEMORY_reg_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_TX_MEMORY_reg_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_TX_MEMORY_reg_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_TX_MEMORY_reg_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff35))
TX_MEMORY_reg_ENBWREN_cooolgate_en_gate_17
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE[4]_i_2_n_0 ),
.I2(\TX_PHY_STATE[4]_i_1_n_0 ),
.I3(INTERNAL_RST_reg),
.O(TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9));
(* SOFT_HLUTNM = "soft_lutpair159" *)
LUT2 #(
.INIT(4'h7))
\TX_OUT_COUNT[0]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[0] ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.O(TX_OUT_COUNT0_in));
LUT6 #(
.INIT(64'h00000000AA100010))
\TX_OUT_COUNT[10]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[3] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(GO_SYNC),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_OUT_COUNT[10]_i_3_n_0 ),
.I5(\TX_OUT_COUNT[10]_i_4_n_0 ),
.O(\TX_OUT_COUNT[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair150" *)
LUT4 #(
.INIT(16'hE133))
\TX_OUT_COUNT[10]_i_2
(.I0(\TX_OUT_COUNT_reg_n_0_[9] ),
.I1(\TX_OUT_COUNT[10]_i_5_n_0 ),
.I2(\TX_OUT_COUNT_reg_n_0_[10] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFF7F))
\TX_OUT_COUNT[10]_i_3
(.I0(\TX_OUT_COUNT[10]_i_6_n_0 ),
.I1(\TX_OUT_COUNT[10]_i_7_n_0 ),
.I2(\TX_OUT_COUNT[10]_i_8_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[0] ),
.I4(\TX_OUT_COUNT_reg_n_0_[1] ),
.I5(\TX_OUT_COUNT_reg_n_0_[2] ),
.O(\TX_OUT_COUNT[10]_i_3_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_OUT_COUNT[10]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.O(\TX_OUT_COUNT[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFEF0F0F0F0))
\TX_OUT_COUNT[10]_i_5
(.I0(\TX_OUT_COUNT_reg_n_0_[7] ),
.I1(\TX_OUT_COUNT_reg_n_0_[5] ),
.I2(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[6] ),
.I4(\TX_OUT_COUNT_reg_n_0_[8] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[10]_i_5_n_0 ));
LUT3 #(
.INIT(8'h01))
\TX_OUT_COUNT[10]_i_6
(.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
.I1(\TX_OUT_COUNT_reg_n_0_[4] ),
.I2(\TX_OUT_COUNT_reg_n_0_[5] ),
.O(\TX_OUT_COUNT[10]_i_6_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_OUT_COUNT[10]_i_7
(.I0(\TX_OUT_COUNT_reg_n_0_[10] ),
.I1(\TX_OUT_COUNT_reg_n_0_[9] ),
.O(\TX_OUT_COUNT[10]_i_7_n_0 ));
LUT3 #(
.INIT(8'h01))
\TX_OUT_COUNT[10]_i_8
(.I0(\TX_OUT_COUNT_reg_n_0_[6] ),
.I1(\TX_OUT_COUNT_reg_n_0_[8] ),
.I2(\TX_OUT_COUNT_reg_n_0_[7] ),
.O(\TX_OUT_COUNT[10]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair159" *)
LUT3 #(
.INIT(8'h9F))
\TX_OUT_COUNT[1]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[0] ),
.I1(\TX_OUT_COUNT_reg_n_0_[1] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT4 #(
.INIT(16'hE1FF))
\TX_OUT_COUNT[2]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[1] ),
.I1(\TX_OUT_COUNT_reg_n_0_[0] ),
.I2(\TX_OUT_COUNT_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT5 #(
.INIT(32'hFE01FFFF))
\TX_OUT_COUNT[3]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[2] ),
.I1(\TX_OUT_COUNT_reg_n_0_[0] ),
.I2(\TX_OUT_COUNT_reg_n_0_[1] ),
.I3(\TX_OUT_COUNT_reg_n_0_[3] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFE0001FFFFFFFF))
\TX_OUT_COUNT[4]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
.I1(\TX_OUT_COUNT_reg_n_0_[1] ),
.I2(\TX_OUT_COUNT_reg_n_0_[0] ),
.I3(\TX_OUT_COUNT_reg_n_0_[2] ),
.I4(\TX_OUT_COUNT_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[4]_i_1_n_0 ));
LUT3 #(
.INIT(8'h95))
\TX_OUT_COUNT[5]_i_1
(.I0(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I1(\TX_OUT_COUNT_reg_n_0_[5] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT4 #(
.INIT(16'hE133))
\TX_OUT_COUNT[6]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[5] ),
.I1(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I2(\TX_OUT_COUNT_reg_n_0_[6] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT5 #(
.INIT(32'hFE013333))
\TX_OUT_COUNT[7]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[6] ),
.I1(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I2(\TX_OUT_COUNT_reg_n_0_[5] ),
.I3(\TX_OUT_COUNT_reg_n_0_[7] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFE00010F0F0F0F))
\TX_OUT_COUNT[8]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[7] ),
.I1(\TX_OUT_COUNT_reg_n_0_[5] ),
.I2(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[6] ),
.I4(\TX_OUT_COUNT_reg_n_0_[8] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFE00000000))
\TX_OUT_COUNT[8]_i_2
(.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
.I1(\TX_OUT_COUNT_reg_n_0_[1] ),
.I2(\TX_OUT_COUNT_reg_n_0_[0] ),
.I3(\TX_OUT_COUNT_reg_n_0_[2] ),
.I4(\TX_OUT_COUNT_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[8]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair150" *)
LUT3 #(
.INIT(8'h95))
\TX_OUT_COUNT[9]_i_1
(.I0(\TX_OUT_COUNT[10]_i_5_n_0 ),
.I1(\TX_OUT_COUNT_reg_n_0_[9] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[9]_i_1_n_0 ));
FDRE \TX_OUT_COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(TX_OUT_COUNT0_in),
.Q(\TX_OUT_COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[10]_i_2_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[10] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[1]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[2]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[3]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[4]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[5]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[6]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[7]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[7] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[8]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[8] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[9]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT5 #(
.INIT(32'hFF007C7C))
\TX_PACKET_STATE[0]_i_1
(.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I1(\TX_PACKET_STATE_reg_n_0_[0] ),
.I2(S_TX_ACK_reg_n_0),
.I3(DONE_SYNC),
.I4(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_PACKET_STATE[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT5 #(
.INIT(32'hFF338080))
\TX_PACKET_STATE[1]_i_1
(.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I1(\TX_PACKET_STATE_reg_n_0_[0] ),
.I2(S_TX_ACK_reg_n_0),
.I3(DONE_SYNC),
.I4(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_PACKET_STATE[1]_i_1_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_10
(.I0(TX_IN_COUNT[6]),
.I1(TX_IN_COUNT[7]),
.O(\TX_PACKET_STATE[1]_i_10_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_11
(.I0(TX_IN_COUNT[4]),
.I1(TX_IN_COUNT[5]),
.O(\TX_PACKET_STATE[1]_i_11_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_12
(.I0(TX_IN_COUNT[2]),
.I1(TX_IN_COUNT[3]),
.O(\TX_PACKET_STATE[1]_i_12_n_0 ));
LUT1 #(
.INIT(2'h1))
\TX_PACKET_STATE[1]_i_13
(.I0(TX_IN_COUNT[1]),
.O(\TX_PACKET_STATE[1]_i_13_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_4
(.I0(TX_IN_COUNT[9]),
.I1(TX_IN_COUNT[8]),
.O(\TX_PACKET_STATE[1]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\TX_PACKET_STATE[1]_i_5
(.I0(TX_IN_COUNT[10]),
.O(\TX_PACKET_STATE[1]_i_5_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_6
(.I0(TX_IN_COUNT[8]),
.I1(TX_IN_COUNT[9]),
.O(\TX_PACKET_STATE[1]_i_6_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_7
(.I0(TX_IN_COUNT[7]),
.I1(TX_IN_COUNT[6]),
.O(\TX_PACKET_STATE[1]_i_7_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_8
(.I0(TX_IN_COUNT[5]),
.I1(TX_IN_COUNT[4]),
.O(\TX_PACKET_STATE[1]_i_8_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_9
(.I0(TX_IN_COUNT[3]),
.I1(TX_IN_COUNT[2]),
.O(\TX_PACKET_STATE[1]_i_9_n_0 ));
FDRE \TX_PACKET_STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_PACKET_STATE[0]_i_1_n_0 ),
.Q(\TX_PACKET_STATE_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PACKET_STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_PACKET_STATE[1]_i_1_n_0 ),
.Q(\TX_PACKET_STATE_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
CARRY4 \TX_PACKET_STATE_reg[1]_i_2
(.CI(\TX_PACKET_STATE_reg[1]_i_3_n_0 ),
.CO({\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED [3:2],\TX_PACKET_STATE_reg[1]_i_2_n_2 ,\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,TX_IN_COUNT[10],\TX_PACKET_STATE[1]_i_4_n_0 }),
.O(\NLW_TX_PACKET_STATE_reg[1]_i_2_O_UNCONNECTED [3:0]),
.S({1'b0,1'b0,\TX_PACKET_STATE[1]_i_5_n_0 ,\TX_PACKET_STATE[1]_i_6_n_0 }));
CARRY4 \TX_PACKET_STATE_reg[1]_i_3
(.CI(1'b0),
.CO({\TX_PACKET_STATE_reg[1]_i_3_n_0 ,\NLW_TX_PACKET_STATE_reg[1]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({\TX_PACKET_STATE[1]_i_7_n_0 ,\TX_PACKET_STATE[1]_i_8_n_0 ,\TX_PACKET_STATE[1]_i_9_n_0 ,TX_IN_COUNT[1]}),
.O(\NLW_TX_PACKET_STATE_reg[1]_i_3_O_UNCONNECTED [3:0]),
.S({\TX_PACKET_STATE[1]_i_10_n_0 ,\TX_PACKET_STATE[1]_i_11_n_0 ,\TX_PACKET_STATE[1]_i_12_n_0 ,\TX_PACKET_STATE[1]_i_13_n_0 }));
LUT6 #(
.INIT(64'h80000000DFFFFFFF))
\TX_PHY_STATE[0]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.I4(\TX_PHY_STATE_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\TX_PHY_STATE[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000FFFFDFFF0000))
\TX_PHY_STATE[1]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.I5(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\TX_PHY_STATE[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8ABABA8ABA8ABA8A))
\TX_PHY_STATE[2]_i_1
(.I0(\TX_PHY_STATE[2]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8BB88BBBB8888))
\TX_PHY_STATE[2]_i_2
(.I0(\TX_PHY_STATE[2]_i_3_n_0 ),
.I1(\TX_PHY_STATE[2]_i_4_n_0 ),
.I2(GO_SYNC),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[2]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0FF0F8F0))
\TX_PHY_STATE[2]_i_3
(.I0(\TX_PHY_STATE[3]_i_5_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[2]_i_3_n_0 ));
LUT3 #(
.INIT(8'h5D))
\TX_PHY_STATE[2]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_PHY_STATE[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hCFAAC0AAC0AAC0AA))
\TX_PHY_STATE[3]_i_1
(.I0(\TX_PHY_STATE[3]_i_2_n_0 ),
.I1(\TX_PHY_STATE[3]_i_3_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(\TX_PHY_STATE[3]_i_4_n_0 ),
.O(\TX_PHY_STATE[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h3CCC8CCC))
\TX_PHY_STATE[3]_i_2
(.I0(\TX_PHY_STATE[3]_i_5_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[3]_i_2_n_0 ));
LUT3 #(
.INIT(8'hBF))
\TX_PHY_STATE[3]_i_3
(.I0(GO_SYNC),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\TX_PHY_STATE[3]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\TX_PHY_STATE[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000080))
\TX_PHY_STATE[3]_i_5
(.I0(\TX_OUT_COUNT[10]_i_6_n_0 ),
.I1(\TX_OUT_COUNT[10]_i_7_n_0 ),
.I2(\TX_OUT_COUNT[10]_i_8_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[0] ),
.I4(\TX_OUT_COUNT_reg_n_0_[1] ),
.I5(\TX_OUT_COUNT_reg_n_0_[2] ),
.O(\TX_PHY_STATE[3]_i_5_n_0 ));
LUT5 #(
.INIT(32'hAFBEAABE))
\TX_PHY_STATE[4]_i_1
(.I0(\TX_PHY_STATE[4]_i_3_n_0 ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE[4]_i_4_n_0 ),
.O(\TX_PHY_STATE[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF5FF8800FFFF0000))
\TX_PHY_STATE[4]_i_2
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(GO_SYNC),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_PHY_STATE_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_PHY_STATE[4]_i_2_n_0 ));
LUT4 #(
.INIT(16'h7FFE))
\TX_PHY_STATE[4]_i_3
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.O(\TX_PHY_STATE[4]_i_3_n_0 ));
LUT5 #(
.INIT(32'h00000001))
\TX_PHY_STATE[4]_i_4
(.I0(\PREAMBLE_COUNT_reg_n_0_[3] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I2(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[4] ),
.I4(\PREAMBLE_COUNT_reg_n_0_[2] ),
.O(\TX_PHY_STATE[4]_i_4_n_0 ));
FDRE \TX_PHY_STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[0]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[1]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[2]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[3]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[4]_i_2_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
FDRE \TX_READ_ADDRESS_reg_rep[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(\TX_READ_ADDRESS_rep[0]_i_1_n_0 ),
.Q(TX_READ_ADDRESS[0]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[10]),
.Q(TX_READ_ADDRESS[10]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[1]),
.Q(TX_READ_ADDRESS[1]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[2]),
.Q(TX_READ_ADDRESS[2]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[3]),
.Q(TX_READ_ADDRESS[3]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[4]),
.Q(TX_READ_ADDRESS[4]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[5]),
.Q(TX_READ_ADDRESS[5]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[6]),
.Q(TX_READ_ADDRESS[6]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[7]),
.Q(TX_READ_ADDRESS[7]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[8]),
.Q(TX_READ_ADDRESS[8]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[9]),
.Q(TX_READ_ADDRESS[9]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\TX_READ_ADDRESS_rep[0]_i_1
(.I0(TX_READ_ADDRESS[0]),
.O(\TX_READ_ADDRESS_rep[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\TX_READ_ADDRESS_rep[10]_i_1
(.I0(TX_READ_ADDRESS[8]),
.I1(TX_READ_ADDRESS[6]),
.I2(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I3(TX_READ_ADDRESS[7]),
.I4(TX_READ_ADDRESS[9]),
.I5(TX_READ_ADDRESS[10]),
.O(TX_READ_ADDRESS0[10]));
(* SOFT_HLUTNM = "soft_lutpair162" *)
LUT2 #(
.INIT(4'h6))
\TX_READ_ADDRESS_rep[1]_i_1
(.I0(TX_READ_ADDRESS[0]),
.I1(TX_READ_ADDRESS[1]),
.O(TX_READ_ADDRESS0[1]));
(* SOFT_HLUTNM = "soft_lutpair162" *)
LUT3 #(
.INIT(8'h78))
\TX_READ_ADDRESS_rep[2]_i_1
(.I0(TX_READ_ADDRESS[0]),
.I1(TX_READ_ADDRESS[1]),
.I2(TX_READ_ADDRESS[2]),
.O(TX_READ_ADDRESS0[2]));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT4 #(
.INIT(16'h7F80))
\TX_READ_ADDRESS_rep[3]_i_1
(.I0(TX_READ_ADDRESS[1]),
.I1(TX_READ_ADDRESS[0]),
.I2(TX_READ_ADDRESS[2]),
.I3(TX_READ_ADDRESS[3]),
.O(TX_READ_ADDRESS0[3]));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT5 #(
.INIT(32'h7FFF8000))
\TX_READ_ADDRESS_rep[4]_i_1
(.I0(TX_READ_ADDRESS[2]),
.I1(TX_READ_ADDRESS[0]),
.I2(TX_READ_ADDRESS[1]),
.I3(TX_READ_ADDRESS[3]),
.I4(TX_READ_ADDRESS[4]),
.O(TX_READ_ADDRESS0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\TX_READ_ADDRESS_rep[5]_i_1
(.I0(TX_READ_ADDRESS[3]),
.I1(TX_READ_ADDRESS[1]),
.I2(TX_READ_ADDRESS[0]),
.I3(TX_READ_ADDRESS[2]),
.I4(TX_READ_ADDRESS[4]),
.I5(TX_READ_ADDRESS[5]),
.O(TX_READ_ADDRESS0[5]));
(* SOFT_HLUTNM = "soft_lutpair161" *)
LUT2 #(
.INIT(4'h6))
\TX_READ_ADDRESS_rep[6]_i_1
(.I0(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I1(TX_READ_ADDRESS[6]),
.O(TX_READ_ADDRESS0[6]));
(* SOFT_HLUTNM = "soft_lutpair161" *)
LUT3 #(
.INIT(8'h78))
\TX_READ_ADDRESS_rep[7]_i_1
(.I0(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I1(TX_READ_ADDRESS[6]),
.I2(TX_READ_ADDRESS[7]),
.O(TX_READ_ADDRESS0[7]));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT4 #(
.INIT(16'h7F80))
\TX_READ_ADDRESS_rep[8]_i_1
(.I0(TX_READ_ADDRESS[6]),
.I1(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I2(TX_READ_ADDRESS[7]),
.I3(TX_READ_ADDRESS[8]),
.O(TX_READ_ADDRESS0[8]));
LUT6 #(
.INIT(64'h0000000000000004))
\TX_READ_ADDRESS_rep[9]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0100010000010000))
\TX_READ_ADDRESS_rep[9]_i_2
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.I4(GO_SYNC),
.I5(\TX_PHY_STATE_reg_n_0_[2] ),
.O(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT5 #(
.INIT(32'h7FFF8000))
\TX_READ_ADDRESS_rep[9]_i_3
(.I0(TX_READ_ADDRESS[7]),
.I1(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I2(TX_READ_ADDRESS[6]),
.I3(TX_READ_ADDRESS[8]),
.I4(TX_READ_ADDRESS[9]),
.O(TX_READ_ADDRESS0[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\TX_READ_ADDRESS_rep[9]_i_4
(.I0(TX_READ_ADDRESS[5]),
.I1(TX_READ_ADDRESS[3]),
.I2(TX_READ_ADDRESS[1]),
.I3(TX_READ_ADDRESS[0]),
.I4(TX_READ_ADDRESS[2]),
.I5(TX_READ_ADDRESS[4]),
.O(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair144" *)
LUT2 #(
.INIT(4'h1))
\TX_WRITE_ADDRESS[0]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[0]),
.O(\TX_WRITE_ADDRESS[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h04F0))
\TX_WRITE_ADDRESS[10]_i_1
(.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I1(S_TX_ACK_reg_n_0),
.I2(\TX_PACKET_STATE_reg_n_0_[1] ),
.I3(\TX_PACKET_STATE_reg_n_0_[0] ),
.O(\TX_WRITE_ADDRESS[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair144" *)
LUT4 #(
.INIT(16'h0078))
\TX_WRITE_ADDRESS[10]_i_2
(.I0(\TX_WRITE_ADDRESS[10]_i_3_n_0 ),
.I1(TX_WRITE_ADDRESS[9]),
.I2(TX_WRITE_ADDRESS[10]),
.I3(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_WRITE_ADDRESS[10]_i_2_n_0 ));
LUT4 #(
.INIT(16'h0800))
\TX_WRITE_ADDRESS[10]_i_3
(.I0(TX_WRITE_ADDRESS[8]),
.I1(TX_WRITE_ADDRESS[7]),
.I2(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I3(TX_WRITE_ADDRESS[6]),
.O(\TX_WRITE_ADDRESS[10]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair154" *)
LUT3 #(
.INIT(8'h06))
\TX_WRITE_ADDRESS[1]_i_1
(.I0(TX_WRITE_ADDRESS[1]),
.I1(TX_WRITE_ADDRESS[0]),
.I2(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_WRITE_ADDRESS[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT4 #(
.INIT(16'h1540))
\TX_WRITE_ADDRESS[2]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[0]),
.I2(TX_WRITE_ADDRESS[1]),
.I3(TX_WRITE_ADDRESS[2]),
.O(\TX_WRITE_ADDRESS[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT5 #(
.INIT(32'h15554000))
\TX_WRITE_ADDRESS[3]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[1]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[2]),
.I4(TX_WRITE_ADDRESS[3]),
.O(\TX_WRITE_ADDRESS[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h1555555540000000))
\TX_WRITE_ADDRESS[4]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[2]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[1]),
.I4(TX_WRITE_ADDRESS[3]),
.I5(TX_WRITE_ADDRESS[4]),
.O(\TX_WRITE_ADDRESS[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair154" *)
LUT3 #(
.INIT(8'h41))
\TX_WRITE_ADDRESS[5]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_WRITE_ADDRESS[5]_i_2_n_0 ),
.I2(TX_WRITE_ADDRESS[5]),
.O(\TX_WRITE_ADDRESS[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'h7FFFFFFF))
\TX_WRITE_ADDRESS[5]_i_2
(.I0(TX_WRITE_ADDRESS[3]),
.I1(TX_WRITE_ADDRESS[1]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[2]),
.I4(TX_WRITE_ADDRESS[4]),
.O(\TX_WRITE_ADDRESS[5]_i_2_n_0 ));
LUT3 #(
.INIT(8'h41))
\TX_WRITE_ADDRESS[6]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I2(TX_WRITE_ADDRESS[6]),
.O(\TX_WRITE_ADDRESS[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT4 #(
.INIT(16'h4510))
\TX_WRITE_ADDRESS[7]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I2(TX_WRITE_ADDRESS[6]),
.I3(TX_WRITE_ADDRESS[7]),
.O(\TX_WRITE_ADDRESS[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT5 #(
.INIT(32'h51550400))
\TX_WRITE_ADDRESS[8]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[6]),
.I2(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I3(TX_WRITE_ADDRESS[7]),
.I4(TX_WRITE_ADDRESS[8]),
.O(\TX_WRITE_ADDRESS[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h5515555500400000))
\TX_WRITE_ADDRESS[9]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[8]),
.I2(TX_WRITE_ADDRESS[7]),
.I3(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I4(TX_WRITE_ADDRESS[6]),
.I5(TX_WRITE_ADDRESS[9]),
.O(\TX_WRITE_ADDRESS[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\TX_WRITE_ADDRESS[9]_i_2
(.I0(TX_WRITE_ADDRESS[4]),
.I1(TX_WRITE_ADDRESS[2]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[1]),
.I4(TX_WRITE_ADDRESS[3]),
.I5(TX_WRITE_ADDRESS[5]),
.O(\TX_WRITE_ADDRESS[9]_i_2_n_0 ));
FDRE \TX_WRITE_ADDRESS_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[0]),
.Q(TX_WRITE_ADDRESS_DEL[0]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[10]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[10]),
.Q(TX_WRITE_ADDRESS_DEL[10]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[1]),
.Q(TX_WRITE_ADDRESS_DEL[1]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[2]),
.Q(TX_WRITE_ADDRESS_DEL[2]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[3]),
.Q(TX_WRITE_ADDRESS_DEL[3]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[4]),
.Q(TX_WRITE_ADDRESS_DEL[4]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[5]),
.Q(TX_WRITE_ADDRESS_DEL[5]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[6]),
.Q(TX_WRITE_ADDRESS_DEL[6]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[7]),
.Q(TX_WRITE_ADDRESS_DEL[7]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[8]),
.Q(TX_WRITE_ADDRESS_DEL[8]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[9]),
.Q(TX_WRITE_ADDRESS_DEL[9]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[0]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[0]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[10]_i_2_n_0 ),
.Q(TX_WRITE_ADDRESS[10]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[1]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[1]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[2]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[2]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[3]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[3]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[4]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[4]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[5]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[5]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[6]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[6]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[7]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[7]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[8]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[8]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[9]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[9]),
.R(INTERNAL_RST_reg));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'h20))
TX_WRITE_i_1
(.I0(S_TX_ACK_reg_n_0),
.I1(\TX_PACKET_STATE_reg_n_0_[1] ),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.O(TX_WRITE_i_1_n_0));
FDRE TX_WRITE_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_i_1_n_0),
.Q(TX_WRITE),
.R(1'b0));
endmodule
module serial_output
(IN1_ACK,
RS232_TX_OBUF,
INTERNAL_RST_reg,
ETH_CLK_OBUF,
IN1_STB,
Q);
output IN1_ACK;
output RS232_TX_OBUF;
input INTERNAL_RST_reg;
input ETH_CLK_OBUF;
input IN1_STB;
input [7:0]Q;
wire [11:0]BAUD_COUNT;
wire \BAUD_COUNT[11]_i_2__0_n_0 ;
wire \BAUD_COUNT[11]_i_3_n_0 ;
wire \BAUD_COUNT_reg[4]_i_2_n_0 ;
wire \BAUD_COUNT_reg[8]_i_2_n_0 ;
wire \BAUD_COUNT_reg_n_0_[0] ;
wire \BAUD_COUNT_reg_n_0_[10] ;
wire \BAUD_COUNT_reg_n_0_[11] ;
wire \BAUD_COUNT_reg_n_0_[1] ;
wire \BAUD_COUNT_reg_n_0_[2] ;
wire \BAUD_COUNT_reg_n_0_[3] ;
wire \BAUD_COUNT_reg_n_0_[4] ;
wire \BAUD_COUNT_reg_n_0_[5] ;
wire \BAUD_COUNT_reg_n_0_[6] ;
wire \BAUD_COUNT_reg_n_0_[7] ;
wire \BAUD_COUNT_reg_n_0_[8] ;
wire \BAUD_COUNT_reg_n_0_[9] ;
wire \DATA[7]_i_1_n_0 ;
wire \DATA_reg_n_0_[0] ;
wire ETH_CLK_OBUF;
wire \FSM_sequential_STATE[0]_i_1_n_0 ;
wire \FSM_sequential_STATE[1]_i_1_n_0 ;
wire \FSM_sequential_STATE[2]_i_1_n_0 ;
wire \FSM_sequential_STATE[3]_i_1_n_0 ;
wire \FSM_sequential_STATE[3]_i_2_n_0 ;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg;
wire [7:0]Q;
wire RS232_TX_OBUF;
(* RTL_KEEP = "yes" *) wire [3:0]STATE;
wire S_IN1_ACK1;
wire S_IN1_ACK_i_1_n_0;
wire TX_i_1_n_0;
wire TX_i_3_n_0;
wire TX_i_4_n_0;
wire TX_i_5_n_0;
wire TX_i_6_n_0;
wire TX_reg_i_2_n_0;
wire X16CLK_EN_i_1__0_n_0;
wire X16CLK_EN_reg_n_0;
wire [11:1]data0;
wire p_0_in;
wire p_1_in;
wire p_2_in;
wire p_3_in;
wire p_4_in;
wire p_5_in;
wire p_6_in;
wire [3:0]\NLW_BAUD_COUNT_reg[11]_i_4_CO_UNCONNECTED ;
wire [3:3]\NLW_BAUD_COUNT_reg[11]_i_4_O_UNCONNECTED ;
wire [2:0]\NLW_BAUD_COUNT_reg[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_BAUD_COUNT_reg[8]_i_2_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\BAUD_COUNT[0]_i_1
(.I0(\BAUD_COUNT_reg_n_0_[0] ),
.O(BAUD_COUNT[0]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[10]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[10]),
.O(BAUD_COUNT[10]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[11]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[11]),
.O(BAUD_COUNT[11]));
LUT6 #(
.INIT(64'hFFFFFEFFFFFFFFFF))
\BAUD_COUNT[11]_i_2__0
(.I0(\BAUD_COUNT_reg_n_0_[10] ),
.I1(\BAUD_COUNT_reg_n_0_[9] ),
.I2(\BAUD_COUNT_reg_n_0_[6] ),
.I3(\BAUD_COUNT_reg_n_0_[7] ),
.I4(\BAUD_COUNT_reg_n_0_[11] ),
.I5(\BAUD_COUNT_reg_n_0_[5] ),
.O(\BAUD_COUNT[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFDFFF))
\BAUD_COUNT[11]_i_3
(.I0(\BAUD_COUNT_reg_n_0_[8] ),
.I1(\BAUD_COUNT_reg_n_0_[1] ),
.I2(\BAUD_COUNT_reg_n_0_[4] ),
.I3(\BAUD_COUNT_reg_n_0_[0] ),
.I4(\BAUD_COUNT_reg_n_0_[2] ),
.I5(\BAUD_COUNT_reg_n_0_[3] ),
.O(\BAUD_COUNT[11]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[1]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[1]),
.O(BAUD_COUNT[1]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[2]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[2]),
.O(BAUD_COUNT[2]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[3]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[3]),
.O(BAUD_COUNT[3]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[4]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[4]),
.O(BAUD_COUNT[4]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[5]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[5]),
.O(BAUD_COUNT[5]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[6]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[6]),
.O(BAUD_COUNT[6]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[7]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[7]),
.O(BAUD_COUNT[7]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[8]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[8]),
.O(BAUD_COUNT[8]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[9]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[9]),
.O(BAUD_COUNT[9]));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[0]),
.Q(\BAUD_COUNT_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[10]),
.Q(\BAUD_COUNT_reg_n_0_[10] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[11]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[11]),
.Q(\BAUD_COUNT_reg_n_0_[11] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[11]_i_4
(.CI(\BAUD_COUNT_reg[8]_i_2_n_0 ),
.CO(\NLW_BAUD_COUNT_reg[11]_i_4_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_BAUD_COUNT_reg[11]_i_4_O_UNCONNECTED [3],data0[11:9]}),
.S({1'b0,\BAUD_COUNT_reg_n_0_[11] ,\BAUD_COUNT_reg_n_0_[10] ,\BAUD_COUNT_reg_n_0_[9] }));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[1]),
.Q(\BAUD_COUNT_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[2]),
.Q(\BAUD_COUNT_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[3]),
.Q(\BAUD_COUNT_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[4]),
.Q(\BAUD_COUNT_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[4]_i_2
(.CI(1'b0),
.CO({\BAUD_COUNT_reg[4]_i_2_n_0 ,\NLW_BAUD_COUNT_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(\BAUD_COUNT_reg_n_0_[0] ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data0[4:1]),
.S({\BAUD_COUNT_reg_n_0_[4] ,\BAUD_COUNT_reg_n_0_[3] ,\BAUD_COUNT_reg_n_0_[2] ,\BAUD_COUNT_reg_n_0_[1] }));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[5]),
.Q(\BAUD_COUNT_reg_n_0_[5] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[6]),
.Q(\BAUD_COUNT_reg_n_0_[6] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[7]),
.Q(\BAUD_COUNT_reg_n_0_[7] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[8]),
.Q(\BAUD_COUNT_reg_n_0_[8] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[8]_i_2
(.CI(\BAUD_COUNT_reg[4]_i_2_n_0 ),
.CO({\BAUD_COUNT_reg[8]_i_2_n_0 ,\NLW_BAUD_COUNT_reg[8]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data0[8:5]),
.S({\BAUD_COUNT_reg_n_0_[8] ,\BAUD_COUNT_reg_n_0_[7] ,\BAUD_COUNT_reg_n_0_[6] ,\BAUD_COUNT_reg_n_0_[5] }));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[9]),
.Q(\BAUD_COUNT_reg_n_0_[9] ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h0000000000001000))
\DATA[7]_i_1
(.I0(STATE[1]),
.I1(STATE[3]),
.I2(IN1_ACK),
.I3(IN1_STB),
.I4(STATE[2]),
.I5(STATE[0]),
.O(\DATA[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\DATA_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[0]),
.Q(\DATA_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[1]),
.Q(p_6_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[2]),
.Q(p_5_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[3]),
.Q(p_4_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[4]),
.Q(p_3_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[5]),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[6]),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[7]),
.Q(p_0_in),
.R(1'b0));
LUT3 #(
.INIT(8'h07))
\FSM_sequential_STATE[0]_i_1
(.I0(STATE[2]),
.I1(STATE[3]),
.I2(STATE[0]),
.O(\FSM_sequential_STATE[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h152A))
\FSM_sequential_STATE[1]_i_1
(.I0(STATE[0]),
.I1(STATE[2]),
.I2(STATE[3]),
.I3(STATE[1]),
.O(\FSM_sequential_STATE[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0078))
\FSM_sequential_STATE[2]_i_1
(.I0(STATE[1]),
.I1(STATE[0]),
.I2(STATE[2]),
.I3(STATE[3]),
.O(\FSM_sequential_STATE[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0F00FF010F00FE00))
\FSM_sequential_STATE[3]_i_1
(.I0(STATE[0]),
.I1(STATE[1]),
.I2(STATE[2]),
.I3(X16CLK_EN_reg_n_0),
.I4(STATE[3]),
.I5(S_IN1_ACK1),
.O(\FSM_sequential_STATE[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0870))
\FSM_sequential_STATE[3]_i_2
(.I0(STATE[1]),
.I1(STATE[0]),
.I2(STATE[3]),
.I3(STATE[2]),
.O(\FSM_sequential_STATE[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\FSM_sequential_STATE[3]_i_3
(.I0(IN1_ACK),
.I1(IN1_STB),
.O(S_IN1_ACK1));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[0]_i_1_n_0 ),
.Q(STATE[0]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[1]_i_1_n_0 ),
.Q(STATE[1]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[2]_i_1_n_0 ),
.Q(STATE[2]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[3]_i_2_n_0 ),
.Q(STATE[3]),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFFFFFD00000003))
S_IN1_ACK_i_1
(.I0(IN1_STB),
.I1(STATE[1]),
.I2(STATE[3]),
.I3(STATE[2]),
.I4(STATE[0]),
.I5(IN1_ACK),
.O(S_IN1_ACK_i_1_n_0));
FDRE #(
.INIT(1'b0))
S_IN1_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_IN1_ACK_i_1_n_0),
.Q(IN1_ACK),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFAAAABA00AAAA8A))
TX_i_1
(.I0(TX_reg_i_2_n_0),
.I1(STATE[1]),
.I2(STATE[0]),
.I3(STATE[3]),
.I4(STATE[2]),
.I5(RS232_TX_OBUF),
.O(TX_i_1_n_0));
LUT6 #(
.INIT(64'h0AC0FFFF0AC00000))
TX_i_3
(.I0(p_4_in),
.I1(p_0_in),
.I2(STATE[3]),
.I3(STATE[2]),
.I4(STATE[1]),
.I5(TX_i_5_n_0),
.O(TX_i_3_n_0));
LUT6 #(
.INIT(64'h0AFCFFFF0AFC0000))
TX_i_4
(.I0(p_3_in),
.I1(\DATA_reg_n_0_[0] ),
.I2(STATE[3]),
.I3(STATE[2]),
.I4(STATE[1]),
.I5(TX_i_6_n_0),
.O(TX_i_4_n_0));
LUT4 #(
.INIT(16'h0ACF))
TX_i_5
(.I0(p_6_in),
.I1(p_2_in),
.I2(STATE[3]),
.I3(STATE[2]),
.O(TX_i_5_n_0));
LUT4 #(
.INIT(16'h30BB))
TX_i_6
(.I0(p_5_in),
.I1(STATE[2]),
.I2(p_1_in),
.I3(STATE[3]),
.O(TX_i_6_n_0));
FDSE #(
.INIT(1'b1))
TX_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_i_1_n_0),
.Q(RS232_TX_OBUF),
.S(INTERNAL_RST_reg));
MUXF7 TX_reg_i_2
(.I0(TX_i_3_n_0),
.I1(TX_i_4_n_0),
.O(TX_reg_i_2_n_0),
.S(STATE[0]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT2 #(
.INIT(4'h1))
X16CLK_EN_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.O(X16CLK_EN_i_1__0_n_0));
FDRE #(
.INIT(1'b0))
X16CLK_EN_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(X16CLK_EN_i_1__0_n_0),
.Q(X16CLK_EN_reg_n_0),
.R(INTERNAL_RST_reg));
endmodule
module user_design
(IN1_STB,
output_rs232_tx,
IN1_ACK,
ETH_CLK_OBUF,
INTERNAL_RST_reg);
output IN1_STB;
output [7:0]output_rs232_tx;
input IN1_ACK;
input ETH_CLK_OBUF;
input INTERNAL_RST_reg;
wire ETH_CLK_OBUF;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg;
wire [7:0]output_rs232_tx;
main_0 main_0_139931286003792
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.IN1_ACK(IN1_ACK),
.IN1_STB(IN1_STB),
.INTERNAL_RST_reg(INTERNAL_RST_reg),
.output_rs232_tx(output_rs232_tx));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module Register_ShiftOutput(
input [31:0] Rt_out,
input [1:0] Mem_addr_in,
input [31:26] IR,
output [31:0] Mem_data_shift
);
wire [2:0] Rt_out_shift_ctr;
wire [31:0] Rt_out_l,Rt_out_r,Rt_out_shift;
assign Rt_out_shift_ctr[2] = (IR[31])&(!IR[30])&(IR[29])&(((!IR[28])&(IR[27])) | ((IR[27])&(!IR[26])) );
assign Rt_out_shift_ctr[1] = (IR[31])&(!IR[30])&(IR[29])&(((!IR[28])&(!IR[27])&(IR[26])) | ((IR[28])&(IR[27])&(!IR[26])));//xor better
assign Rt_out_shift_ctr[0] = (IR[31])&(!IR[30])&(IR[29])&(!IR[28])&(IR[27])&(!IR[26]);
MUX4_1 mux4_1_0(Mem_addr_in[1:0],Rt_out[31:24],8'b0,8'b0,8'b0,Rt_out_l[31:24]);
MUX4_1 mux4_1_1(Mem_addr_in[1:0],Rt_out[23:16],Rt_out[31:24],8'b0,8'b0,Rt_out_l[23:16]);
MUX4_1 mux4_1_2(Mem_addr_in[1:0],Rt_out[15:8],Rt_out[23:16],Rt_out[31:24],8'b0,Rt_out_l[15:8]);
MUX4_1 mux4_1_3(Mem_addr_in[1:0],Rt_out[7:0],Rt_out[15:8],Rt_out[23:16],Rt_out[31:24],Rt_out_l[7:0]);
MUX4_1 mux4_1_4(Mem_addr_in[1:0],Rt_out[7:0],Rt_out[15:8],Rt_out[23:16],Rt_out[31:24],Rt_out_r[31:24]);
MUX4_1 mux4_1_5(Mem_addr_in[1:0],8'b0,Rt_out[7:0],Rt_out[15:8],Rt_out[23:16],Rt_out_r[23:16]);
MUX4_1 mux4_1_6(Mem_addr_in[1:0],8'b0,8'b0,Rt_out[7:0],Rt_out[15:8],Rt_out_r[15:8]);
MUX4_1 mux4_1_7(Mem_addr_in[1:0],8'b0,8'b0,8'b0,Rt_out[7:0],Rt_out_r[7:0]);
MUX8_1 mux8_1_0(Rt_out_shift_ctr[2:0],Rt_out[7:0],8'b0,Rt_out[15:8],8'b0,Rt_out_l[31:24],Rt_out_l[31:24],Rt_out_r[31:24],8'b0,Mem_data_shift[31:24]);
MUX8_1 mux8_1_1(Rt_out_shift_ctr[2:0],Rt_out[7:0],8'b0,Rt_out[7:0],8'b0,Rt_out_l[23:16],Rt_out_l[23:16],Rt_out_r[23:16],8'b0,Mem_data_shift[23:16]);
MUX8_1 mux8_1_2(Rt_out_shift_ctr[2:0],Rt_out[7:0],8'b0,Rt_out[15:8],8'b0,Rt_out_l[15:8],Rt_out_l[15:8],Rt_out_r[15:8],8'b0,Mem_data_shift[15:8]);
MUX8_1 mux8_1_3(Rt_out_shift_ctr[2:0],Rt_out[7:0],8'b0,Rt_out[7:0],8'b0,Rt_out_l[7:0],Rt_out_l[7:0],Rt_out_r[7:0],8'b0,Mem_data_shift[7:0]);
endmodule
module DataMemory
#(parameter DATA_WIDTH = 32, parameter ADDR_WIDTH = 32)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input [3:0] we,
input clk,
output [(DATA_WIDTH-1):0] q
);
//wire [31:0] RegShift;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**(ADDR_WIDTH - 22) - 1:0];
// Variable to hold the registered read address
reg [ADDR_WIDTH-1:0] addr_reg;
initial ram[64] = 32'hf0f0f0f0;
//Register_ShiftOutput regshift(data,addr[1:0],{3'b100,PC_Write[2:0]},RegShift);
//assign RegShift = data;
always @ (negedge clk)
begin
case(we)
4'b0001: ram[addr[9:2]][7:0] <= data[7:0];
4'b0010: ram[addr[9:2]][15:8] <= data[15:8];
4'b0011: ram[addr[9:2]][15:0] <= data[15:0];
4'b0100: ram[addr[9:2]][23:16] <= data[23:16];
4'b0101: begin ram[addr[9:2]][23:16] <= data[23:16]; ram[addr[9:2]][7:0] <= data[7:0];end
4'b0110: ram[addr[9:2]][23:8] <= data[23:8];
4'b0111: ram[addr[9:2]][23:0] <= data[23:0];
4'b1000: ram[addr[9:2]][31:24] <= data[31:24];
4'b1001: begin ram[addr[9:2]][31:24] <= data[31:24]; ram[addr[9:2]][7:0] <= data[7:0];end
4'b1010: begin ram[addr[9:2]][31:24] <= data[31:24]; ram[addr[9:2]][15:8] <= data[15:8];end
4'b1011: begin ram[addr[9:2]][31:24] <= data[31:24]; ram[addr[9:2]][15:0] <= data[15:0];end
4'b1100: ram[addr[9:2]][31:16] <= data[31:16];
4'b1101: begin ram[addr[9:2]][31:16] <= data[31:16]; ram[addr[9:2]][7:0] <= data[7:0];end
4'b1110: ram[addr[9:2]][31:8] <= data[31:8];
4'b1111: ram[addr[9:2]] <= data;
default:;
endcase
end
// Continuous assignment implies read returns NEW data.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign q = ram[addr[9:2]];
endmodule
/*
module DataMemory
#(parameter DATA_WIDTH = 32, parameter ADDR_WIDTH = 32)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input [3:0] we,
input clk,
output [(DATA_WIDTH-1):0] q
);
MemorySingle DataMemory1(data[7:0],addr,we[0],clk,q[7:0]);
MemorySingle DataMemory2(data[15:8],addr,we[1],clk,q[15:8]);
MemorySingle DataMemory3(data[23:16],addr,we[2],clk,q[23:16]);
MemorySingle DataMemory4(data[31:24],addr,we[3],clk,q[31:24]);
endmodule
module MemorySingle
#(parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 32)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we,
input clk,
output [(DATA_WIDTH-1):0] q
);
reg [DATA_WIDTH-1:0] ram[2**(ADDR_WIDTH - 22) - 1:0];
always @(negedge clk)
begin
if(we)
ram[addr[9:2]][7:0] <= data[7:0];
end
assign q = ram[addr[9:2]];
endmodule
*/
|
/*
* File: lsu_reg2mem.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Description:
*
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module lsu_reg2mem(addr, lsu_op, regdata, memdata);
parameter width = `OPERAND_WIDTH;
//
// I/O
//
input [1:0] addr;
input [`LSUOP_WIDTH-1:0] lsu_op;
input [width-1:0] regdata;
output [width-1:0] memdata;
//
// big-endian memory layout
//
reg [7:0] memdata_hh; // byte address 00
reg [7:0] memdata_hl; // byte address 01
reg [7:0] memdata_lh; // byte address 10
reg [7:0] memdata_ll; // byte address 11
//
assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};
//
// Mux to memdata[31:24]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`LSUOP_STB, 2'b00} : memdata_hh = regdata[7:0];
{`LSUOP_STH, 2'b00} : memdata_hh = regdata[15:8];
{`LSUOP_STHB, 2'b00} : memdata_hh = regdata[7:0];
{`LSUOP_STW, 2'b00} : memdata_hh = regdata[31:24];
{`LSUOP_STWB, 2'b00} : memdata_hh = regdata[7:0];
default : memdata_hh = regdata[31:24];
endcase
end
//
// Mux to memdata[23:16]
// [TBD] comment out unneccessary access pattern(same with default), to evaluate syn result
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`LSUOP_STB, 2'b01} : memdata_hl = regdata[7:0];
{`LSUOP_STH, 2'b00} : memdata_hl = regdata[7:0];
{`LSUOP_STHB, 2'b00} : memdata_hl = regdata[15:8];
{`LSUOP_STW, 2'b00} : memdata_hl = regdata[23:16];
{`LSUOP_STWB, 2'b00} : memdata_hl = regdata[15:8];
default : memdata_hl = regdata[7:0];
endcase
end
//
// Mux to memdata[15:8]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`LSUOP_STB, 2'b10} : memdata_lh = regdata[7:0];
{`LSUOP_STH, 2'b10} : memdata_lh = regdata[15:8];
{`LSUOP_STHB, 2'b10} : memdata_lh = regdata[7:0];
{`LSUOP_STW, 2'b00} : memdata_lh = regdata[15:8];
{`LSUOP_STWB, 2'b00} : memdata_lh = regdata[23:16];
default : memdata_lh = regdata[15:8];
endcase
end
//
// Mux to memdata[7:0]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`LSUOP_STB, 2'b11} : memdata_ll = regdata[7:0];
{`LSUOP_STH, 2'b10} : memdata_ll = regdata[7:0];
{`LSUOP_STHB, 2'b10} : memdata_ll = regdata[15:8];
{`LSUOP_STW, 2'b00} : memdata_ll = regdata[7:0];
{`LSUOP_STWB, 2'b00} : memdata_ll = regdata[31:25];
default : memdata_ll = regdata[7:0];
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__XNOR2_BEHAVIORAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_BEHAVIORAL_PP_V |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_8_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_8_e.v,v 1.3 2006/06/26 08:39:42 wig Exp $
// $Date: 2006/06/26 08:39:42 $
// $Log: inst_8_e.v,v $
// Revision 1.3 2006/06/26 08:39:42 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_8_e
//
// No `defines in this module
module inst_8_e
//
// Generated Module inst_8
//
(
);
// Module parameters:
parameter FOO; // = __W_NODEFAULT;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_8_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// The following code implements a parameterizable Multiply-accumulate unit
// with synchronous load to reset the accumulator without losing a clock cycle
// Size of inputs/output should be less than/equal to what is supported by the architecture else extra logic/dsps will be inferred
parameter SIZEIN = <sizein>; // width of the inputs
parameter SIZEOUT = <sizeout>; // width of output
wire_or_reg <clk>; // clock
wire_or_reg <ce>; // clock enable
wire_or_reg <sload>; // synchronous load
wire_or_reg signed [SIZEIN-1:0] <a>; // 1st input to multiply-accumulate
wire_or_reg signed [SIZEIN-1:0] <b>; // 2nd input to multiply-accumulate
wire_or_reg signed [SIZEOUT-1:0] <accum_out>; // output from multiply-accumulate
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] <a_reg>, <b_reg>;
reg <sload_reg>;
reg signed [2*SIZEIN-1:0] <mult_reg>;
reg signed [SIZEOUT-1:0] <adder_out>, <old_result>;
always @(<sload_reg> or <adder_out>)
begin
if (<sload_reg>)
<old_result> <= 0;
else
// 'sload' is now and opens the accumulation loop.
// The accumulator takes the next multiplier output
// in the same cycle.
<old_result> <= <adder_out>;
end
always @(posedge <clk>)
if (<ce>)
begin
<a_reg> <= <a>;
<b_reg> <= <b>;
<mult_reg> <= <a_reg> * <b_reg>;
<sload_reg> <= <sload>;
// Store accumulation result into a register
<adder_out> <= <old_result> + <mult_reg>;
end
// Output accumulation result
assign <accum_out> = <adder_out>;
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_pmu(
input clock,
input reset,
input io_wakeup_awakeup,
input io_wakeup_dwakeup,
input io_wakeup_rtc,
input io_wakeup_reset,
output io_control_hfclkrst,
output io_control_corerst,
output io_control_reserved1,
output io_control_vddpaden,
output io_control_reserved0,
input io_regs_ie_write_valid,
input [3:0] io_regs_ie_write_bits,
output [3:0] io_regs_ie_read,
input io_regs_cause_write_valid,
input [31:0] io_regs_cause_write_bits,
output [31:0] io_regs_cause_read,
input io_regs_sleep_write_valid,
input [31:0] io_regs_sleep_write_bits,
output [31:0] io_regs_sleep_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
input io_regs_wakeupProgram_0_write_valid,
input [31:0] io_regs_wakeupProgram_0_write_bits,
output [31:0] io_regs_wakeupProgram_0_read,
input io_regs_wakeupProgram_1_write_valid,
input [31:0] io_regs_wakeupProgram_1_write_bits,
output [31:0] io_regs_wakeupProgram_1_read,
input io_regs_wakeupProgram_2_write_valid,
input [31:0] io_regs_wakeupProgram_2_write_bits,
output [31:0] io_regs_wakeupProgram_2_read,
input io_regs_wakeupProgram_3_write_valid,
input [31:0] io_regs_wakeupProgram_3_write_bits,
output [31:0] io_regs_wakeupProgram_3_read,
input io_regs_wakeupProgram_4_write_valid,
input [31:0] io_regs_wakeupProgram_4_write_bits,
output [31:0] io_regs_wakeupProgram_4_read,
input io_regs_wakeupProgram_5_write_valid,
input [31:0] io_regs_wakeupProgram_5_write_bits,
output [31:0] io_regs_wakeupProgram_5_read,
input io_regs_wakeupProgram_6_write_valid,
input [31:0] io_regs_wakeupProgram_6_write_bits,
output [31:0] io_regs_wakeupProgram_6_read,
input io_regs_wakeupProgram_7_write_valid,
input [31:0] io_regs_wakeupProgram_7_write_bits,
output [31:0] io_regs_wakeupProgram_7_read,
input io_regs_sleepProgram_0_write_valid,
input [31:0] io_regs_sleepProgram_0_write_bits,
output [31:0] io_regs_sleepProgram_0_read,
input io_regs_sleepProgram_1_write_valid,
input [31:0] io_regs_sleepProgram_1_write_bits,
output [31:0] io_regs_sleepProgram_1_read,
input io_regs_sleepProgram_2_write_valid,
input [31:0] io_regs_sleepProgram_2_write_bits,
output [31:0] io_regs_sleepProgram_2_read,
input io_regs_sleepProgram_3_write_valid,
input [31:0] io_regs_sleepProgram_3_write_bits,
output [31:0] io_regs_sleepProgram_3_read,
input io_regs_sleepProgram_4_write_valid,
input [31:0] io_regs_sleepProgram_4_write_bits,
output [31:0] io_regs_sleepProgram_4_read,
input io_regs_sleepProgram_5_write_valid,
input [31:0] io_regs_sleepProgram_5_write_bits,
output [31:0] io_regs_sleepProgram_5_read,
input io_regs_sleepProgram_6_write_valid,
input [31:0] io_regs_sleepProgram_6_write_bits,
output [31:0] io_regs_sleepProgram_6_read,
input io_regs_sleepProgram_7_write_valid,
input [31:0] io_regs_sleepProgram_7_write_bits,
output [31:0] io_regs_sleepProgram_7_read,
input io_resetCauses_wdogrst,
input io_resetCauses_erst,
input io_resetCauses_porrst
);
reg T_355;
reg [31:0] GEN_1;
reg T_356;
reg [31:0] GEN_2;
wire core_clock;
wire core_reset;
wire core_io_wakeup_awakeup;
wire core_io_wakeup_dwakeup;
wire core_io_wakeup_rtc;
wire core_io_wakeup_reset;
wire core_io_control_valid;
wire core_io_control_bits_hfclkrst;
wire core_io_control_bits_corerst;
wire core_io_control_bits_reserved1;
wire core_io_control_bits_vddpaden;
wire core_io_control_bits_reserved0;
wire [1:0] core_io_resetCause;
wire core_io_regs_ie_write_valid;
wire [3:0] core_io_regs_ie_write_bits;
wire [3:0] core_io_regs_ie_read;
wire core_io_regs_cause_write_valid;
wire [31:0] core_io_regs_cause_write_bits;
wire [31:0] core_io_regs_cause_read;
wire core_io_regs_sleep_write_valid;
wire [31:0] core_io_regs_sleep_write_bits;
wire [31:0] core_io_regs_sleep_read;
wire core_io_regs_key_write_valid;
wire [31:0] core_io_regs_key_write_bits;
wire [31:0] core_io_regs_key_read;
wire core_io_regs_wakeupProgram_0_write_valid;
wire [31:0] core_io_regs_wakeupProgram_0_write_bits;
wire [31:0] core_io_regs_wakeupProgram_0_read;
wire core_io_regs_wakeupProgram_1_write_valid;
wire [31:0] core_io_regs_wakeupProgram_1_write_bits;
wire [31:0] core_io_regs_wakeupProgram_1_read;
wire core_io_regs_wakeupProgram_2_write_valid;
wire [31:0] core_io_regs_wakeupProgram_2_write_bits;
wire [31:0] core_io_regs_wakeupProgram_2_read;
wire core_io_regs_wakeupProgram_3_write_valid;
wire [31:0] core_io_regs_wakeupProgram_3_write_bits;
wire [31:0] core_io_regs_wakeupProgram_3_read;
wire core_io_regs_wakeupProgram_4_write_valid;
wire [31:0] core_io_regs_wakeupProgram_4_write_bits;
wire [31:0] core_io_regs_wakeupProgram_4_read;
wire core_io_regs_wakeupProgram_5_write_valid;
wire [31:0] core_io_regs_wakeupProgram_5_write_bits;
wire [31:0] core_io_regs_wakeupProgram_5_read;
wire core_io_regs_wakeupProgram_6_write_valid;
wire [31:0] core_io_regs_wakeupProgram_6_write_bits;
wire [31:0] core_io_regs_wakeupProgram_6_read;
wire core_io_regs_wakeupProgram_7_write_valid;
wire [31:0] core_io_regs_wakeupProgram_7_write_bits;
wire [31:0] core_io_regs_wakeupProgram_7_read;
wire core_io_regs_sleepProgram_0_write_valid;
wire [31:0] core_io_regs_sleepProgram_0_write_bits;
wire [31:0] core_io_regs_sleepProgram_0_read;
wire core_io_regs_sleepProgram_1_write_valid;
wire [31:0] core_io_regs_sleepProgram_1_write_bits;
wire [31:0] core_io_regs_sleepProgram_1_read;
wire core_io_regs_sleepProgram_2_write_valid;
wire [31:0] core_io_regs_sleepProgram_2_write_bits;
wire [31:0] core_io_regs_sleepProgram_2_read;
wire core_io_regs_sleepProgram_3_write_valid;
wire [31:0] core_io_regs_sleepProgram_3_write_bits;
wire [31:0] core_io_regs_sleepProgram_3_read;
wire core_io_regs_sleepProgram_4_write_valid;
wire [31:0] core_io_regs_sleepProgram_4_write_bits;
wire [31:0] core_io_regs_sleepProgram_4_read;
wire core_io_regs_sleepProgram_5_write_valid;
wire [31:0] core_io_regs_sleepProgram_5_write_bits;
wire [31:0] core_io_regs_sleepProgram_5_read;
wire core_io_regs_sleepProgram_6_write_valid;
wire [31:0] core_io_regs_sleepProgram_6_write_bits;
wire [31:0] core_io_regs_sleepProgram_6_read;
wire core_io_regs_sleepProgram_7_write_valid;
wire [31:0] core_io_regs_sleepProgram_7_write_bits;
wire [31:0] core_io_regs_sleepProgram_7_read;
wire [1:0] T_358;
wire [1:0] T_359;
wire [2:0] T_360;
wire [4:0] T_361;
wire [4:0] T_362;
wire AsyncResetRegVec_1_1_clock;
wire AsyncResetRegVec_1_1_reset;
wire [4:0] AsyncResetRegVec_1_1_io_d;
wire [4:0] AsyncResetRegVec_1_1_io_q;
wire AsyncResetRegVec_1_1_io_en;
//wire [4:0] latch;
//Bob: the naming as latch is not good, which will introduce some confusing, so we give it renames here
wire [4:0] core_io_control_bits;
wire T_369_hfclkrst;
wire T_369_corerst;
wire T_369_reserved1;
wire T_369_vddpaden;
wire T_369_reserved0;
wire T_375;
wire T_376;
wire T_377;
wire T_378;
wire T_379;
wire [1:0] T_380;
wire [2:0] T_381;
//Bob: Name as Latch is not good, give it new name here
//wire SRLatch_3_q;
//wire SRLatch_3_reset;
//wire SRLatch_3_set;
wire T_382;
wire T_383;
wire T_384;
wire T_385;
//wire SRLatch_1_1_q;
//wire SRLatch_1_1_reset;
//wire SRLatch_1_1_set;
wire T_389;
//wire SRLatch_2_1_q;
//wire SRLatch_2_1_reset;
//wire SRLatch_2_1_set;
wire T_393;
wire [1:0] T_394;
wire [2:0] T_395;
wire T_396;
wire [1:0] T_397;
wire [1:0] GEN_0;
wire [1:0] T_400;
wire T_401;
wire [1:0] T_402;
sirv_pmu_core u_pmu_core (
.clock(core_clock),
.reset(core_reset),
.io_wakeup_awakeup(core_io_wakeup_awakeup),
.io_wakeup_dwakeup(core_io_wakeup_dwakeup),
.io_wakeup_rtc(core_io_wakeup_rtc),
.io_wakeup_reset(core_io_wakeup_reset),
.io_control_valid(core_io_control_valid),
.io_control_bits_hfclkrst(core_io_control_bits_hfclkrst),
.io_control_bits_corerst(core_io_control_bits_corerst),
.io_control_bits_reserved1(core_io_control_bits_reserved1),
.io_control_bits_vddpaden(core_io_control_bits_vddpaden),
.io_control_bits_reserved0(core_io_control_bits_reserved0),
.io_resetCause(core_io_resetCause),
.io_regs_ie_write_valid(core_io_regs_ie_write_valid),
.io_regs_ie_write_bits(core_io_regs_ie_write_bits),
.io_regs_ie_read(core_io_regs_ie_read),
.io_regs_cause_write_valid(core_io_regs_cause_write_valid),
.io_regs_cause_write_bits(core_io_regs_cause_write_bits),
.io_regs_cause_read(core_io_regs_cause_read),
.io_regs_sleep_write_valid(core_io_regs_sleep_write_valid),
.io_regs_sleep_write_bits(core_io_regs_sleep_write_bits),
.io_regs_sleep_read(core_io_regs_sleep_read),
.io_regs_key_write_valid(core_io_regs_key_write_valid),
.io_regs_key_write_bits(core_io_regs_key_write_bits),
.io_regs_key_read(core_io_regs_key_read),
.io_regs_wakeupProgram_0_write_valid(core_io_regs_wakeupProgram_0_write_valid),
.io_regs_wakeupProgram_0_write_bits(core_io_regs_wakeupProgram_0_write_bits),
.io_regs_wakeupProgram_0_read(core_io_regs_wakeupProgram_0_read),
.io_regs_wakeupProgram_1_write_valid(core_io_regs_wakeupProgram_1_write_valid),
.io_regs_wakeupProgram_1_write_bits(core_io_regs_wakeupProgram_1_write_bits),
.io_regs_wakeupProgram_1_read(core_io_regs_wakeupProgram_1_read),
.io_regs_wakeupProgram_2_write_valid(core_io_regs_wakeupProgram_2_write_valid),
.io_regs_wakeupProgram_2_write_bits(core_io_regs_wakeupProgram_2_write_bits),
.io_regs_wakeupProgram_2_read(core_io_regs_wakeupProgram_2_read),
.io_regs_wakeupProgram_3_write_valid(core_io_regs_wakeupProgram_3_write_valid),
.io_regs_wakeupProgram_3_write_bits(core_io_regs_wakeupProgram_3_write_bits),
.io_regs_wakeupProgram_3_read(core_io_regs_wakeupProgram_3_read),
.io_regs_wakeupProgram_4_write_valid(core_io_regs_wakeupProgram_4_write_valid),
.io_regs_wakeupProgram_4_write_bits(core_io_regs_wakeupProgram_4_write_bits),
.io_regs_wakeupProgram_4_read(core_io_regs_wakeupProgram_4_read),
.io_regs_wakeupProgram_5_write_valid(core_io_regs_wakeupProgram_5_write_valid),
.io_regs_wakeupProgram_5_write_bits(core_io_regs_wakeupProgram_5_write_bits),
.io_regs_wakeupProgram_5_read(core_io_regs_wakeupProgram_5_read),
.io_regs_wakeupProgram_6_write_valid(core_io_regs_wakeupProgram_6_write_valid),
.io_regs_wakeupProgram_6_write_bits(core_io_regs_wakeupProgram_6_write_bits),
.io_regs_wakeupProgram_6_read(core_io_regs_wakeupProgram_6_read),
.io_regs_wakeupProgram_7_write_valid(core_io_regs_wakeupProgram_7_write_valid),
.io_regs_wakeupProgram_7_write_bits(core_io_regs_wakeupProgram_7_write_bits),
.io_regs_wakeupProgram_7_read(core_io_regs_wakeupProgram_7_read),
.io_regs_sleepProgram_0_write_valid(core_io_regs_sleepProgram_0_write_valid),
.io_regs_sleepProgram_0_write_bits(core_io_regs_sleepProgram_0_write_bits),
.io_regs_sleepProgram_0_read(core_io_regs_sleepProgram_0_read),
.io_regs_sleepProgram_1_write_valid(core_io_regs_sleepProgram_1_write_valid),
.io_regs_sleepProgram_1_write_bits(core_io_regs_sleepProgram_1_write_bits),
.io_regs_sleepProgram_1_read(core_io_regs_sleepProgram_1_read),
.io_regs_sleepProgram_2_write_valid(core_io_regs_sleepProgram_2_write_valid),
.io_regs_sleepProgram_2_write_bits(core_io_regs_sleepProgram_2_write_bits),
.io_regs_sleepProgram_2_read(core_io_regs_sleepProgram_2_read),
.io_regs_sleepProgram_3_write_valid(core_io_regs_sleepProgram_3_write_valid),
.io_regs_sleepProgram_3_write_bits(core_io_regs_sleepProgram_3_write_bits),
.io_regs_sleepProgram_3_read(core_io_regs_sleepProgram_3_read),
.io_regs_sleepProgram_4_write_valid(core_io_regs_sleepProgram_4_write_valid),
.io_regs_sleepProgram_4_write_bits(core_io_regs_sleepProgram_4_write_bits),
.io_regs_sleepProgram_4_read(core_io_regs_sleepProgram_4_read),
.io_regs_sleepProgram_5_write_valid(core_io_regs_sleepProgram_5_write_valid),
.io_regs_sleepProgram_5_write_bits(core_io_regs_sleepProgram_5_write_bits),
.io_regs_sleepProgram_5_read(core_io_regs_sleepProgram_5_read),
.io_regs_sleepProgram_6_write_valid(core_io_regs_sleepProgram_6_write_valid),
.io_regs_sleepProgram_6_write_bits(core_io_regs_sleepProgram_6_write_bits),
.io_regs_sleepProgram_6_read(core_io_regs_sleepProgram_6_read),
.io_regs_sleepProgram_7_write_valid(core_io_regs_sleepProgram_7_write_valid),
.io_regs_sleepProgram_7_write_bits(core_io_regs_sleepProgram_7_write_bits),
.io_regs_sleepProgram_7_read(core_io_regs_sleepProgram_7_read)
);
sirv_AsyncResetRegVec_1 AsyncResetRegVec_1_1 (
.clock(AsyncResetRegVec_1_1_clock),
.reset(AsyncResetRegVec_1_1_reset),
.io_d(AsyncResetRegVec_1_1_io_d),
.io_q(AsyncResetRegVec_1_1_io_q),
.io_en(AsyncResetRegVec_1_1_io_en)
);
//Bob: Since the SR Latch is not friend to the ASIC flow, so I just replace it to the DFF
// And the name as Latch is not good, so give it a new name here
wire por_reset = T_382;// POR
wire erst_reset = T_383;// ERST
wire wdog_reset = T_384;// WDOG
// In case we lost the reset, we need to just use two-dff syncer to catch up the reset, and until the clock
// is there to clear it
reg por_reset_r;
reg por_reset_r_r;
always @(posedge clock or posedge por_reset) begin
if(por_reset) begin
por_reset_r <= 1'b1;
por_reset_r_r <= 1'b1;
end
else begin
por_reset_r <= 1'b0;
por_reset_r_r <= por_reset_r;
end
end
reg erst_reset_r;
reg erst_reset_r_r;
always @(posedge clock or posedge erst_reset) begin
if(erst_reset) begin
erst_reset_r <= 1'b1;
erst_reset_r_r <= 1'b1;
end
else begin
erst_reset_r <= 1'b0;
erst_reset_r_r <= erst_reset_r;
end
end
reg wdog_reset_r;
reg wdog_reset_r_r;
always @(posedge clock or posedge wdog_reset) begin
if(wdog_reset) begin
wdog_reset_r <= 1'b1;
wdog_reset_r_r <= 1'b1;
end
else begin
wdog_reset_r <= 1'b0;
wdog_reset_r_r <= wdog_reset_r;
end
end
// Reset cause priority if they are coming at same time:
// POR
// Erst
// Wdog
wire rstcause_por_set = por_reset_r_r;
wire rstcause_erst_set = erst_reset_r_r & (~por_reset_r_r);
wire rstcause_wdog_set = wdog_reset_r_r & (~erst_reset_r_r) & (~por_reset_r_r);
// The POR only clear if:
// there is no POR reset,
// And there are other two resets
wire rstcause_por_clr = (~por_reset_r_r) & (erst_reset_r_r | wdog_reset_r_r);
// The Erst only clear if:
// there is POR reset,
// or, there is no erst reset and there is wdog reset
wire rstcause_erst_clr = por_reset_r_r | ((~erst_reset_r_r) & wdog_reset_r_r);
// The Wdog only clear if:
// there is POR or Erst reset,
wire rstcause_wdog_clr = por_reset_r_r | erst_reset_r_r;
wire rstcause_por_ena = rstcause_por_set | rstcause_por_clr ;
wire rstcause_erst_ena = rstcause_erst_set | rstcause_erst_clr;
wire rstcause_wdog_ena = rstcause_wdog_set | rstcause_wdog_clr;
wire rstcause_por_nxt = rstcause_por_set | (~rstcause_por_clr );
wire rstcause_erst_nxt = rstcause_erst_set | (~rstcause_erst_clr);
wire rstcause_wdog_nxt = rstcause_wdog_set | (~rstcause_wdog_clr);
reg rstcause_por_r;
reg rstcause_wdog_r;
reg rstcause_erst_r;
// The reset cause itself cannot have reset signal
always @(posedge clock) begin
if(rstcause_por_ena) begin
rstcause_por_r <= rstcause_por_nxt;
end
end
always @(posedge clock) begin
if(rstcause_erst_ena) begin
rstcause_erst_r <= rstcause_erst_nxt;
end
end
always @(posedge clock) begin
if(rstcause_wdog_ena) begin
rstcause_wdog_r <= rstcause_wdog_nxt;
end
end
//sirv_SRLatch SRLatch_3 ( // POR
// .q(SRLatch_3_q),
// .reset(SRLatch_3_reset),
// .set(SRLatch_3_set)
//);
//sirv_SRLatch SRLatch_1_1 (// ERST
// .q(SRLatch_1_1_q),
// .reset(SRLatch_1_1_reset),
// .set(SRLatch_1_1_set)
//);
//sirv_SRLatch SRLatch_2_1 (//WDOG
// .q(SRLatch_2_1_q),
// .reset(SRLatch_2_1_reset),
// .set(SRLatch_2_1_set)
//);
assign io_control_hfclkrst = T_369_hfclkrst;
assign io_control_corerst = T_369_corerst;
assign io_control_reserved1 = T_369_reserved1;
assign io_control_vddpaden = T_369_vddpaden;
assign io_control_reserved0 = T_369_reserved0;
assign io_regs_ie_read = core_io_regs_ie_read;
assign io_regs_cause_read = core_io_regs_cause_read;
assign io_regs_sleep_read = core_io_regs_sleep_read;
assign io_regs_key_read = core_io_regs_key_read;
assign io_regs_wakeupProgram_0_read = core_io_regs_wakeupProgram_0_read;
assign io_regs_wakeupProgram_1_read = core_io_regs_wakeupProgram_1_read;
assign io_regs_wakeupProgram_2_read = core_io_regs_wakeupProgram_2_read;
assign io_regs_wakeupProgram_3_read = core_io_regs_wakeupProgram_3_read;
assign io_regs_wakeupProgram_4_read = core_io_regs_wakeupProgram_4_read;
assign io_regs_wakeupProgram_5_read = core_io_regs_wakeupProgram_5_read;
assign io_regs_wakeupProgram_6_read = core_io_regs_wakeupProgram_6_read;
assign io_regs_wakeupProgram_7_read = core_io_regs_wakeupProgram_7_read;
assign io_regs_sleepProgram_0_read = core_io_regs_sleepProgram_0_read;
assign io_regs_sleepProgram_1_read = core_io_regs_sleepProgram_1_read;
assign io_regs_sleepProgram_2_read = core_io_regs_sleepProgram_2_read;
assign io_regs_sleepProgram_3_read = core_io_regs_sleepProgram_3_read;
assign io_regs_sleepProgram_4_read = core_io_regs_sleepProgram_4_read;
assign io_regs_sleepProgram_5_read = core_io_regs_sleepProgram_5_read;
assign io_regs_sleepProgram_6_read = core_io_regs_sleepProgram_6_read;
assign io_regs_sleepProgram_7_read = core_io_regs_sleepProgram_7_read;
assign core_clock = clock;
assign core_reset = T_356;
assign core_io_wakeup_awakeup = io_wakeup_awakeup;
assign core_io_wakeup_dwakeup = io_wakeup_dwakeup;
assign core_io_wakeup_rtc = io_wakeup_rtc;
assign core_io_wakeup_reset = 1'h0;
assign core_io_resetCause = T_402;
assign core_io_regs_ie_write_valid = io_regs_ie_write_valid;
assign core_io_regs_ie_write_bits = io_regs_ie_write_bits;
assign core_io_regs_cause_write_valid = io_regs_cause_write_valid;
assign core_io_regs_cause_write_bits = io_regs_cause_write_bits;
assign core_io_regs_sleep_write_valid = io_regs_sleep_write_valid;
assign core_io_regs_sleep_write_bits = io_regs_sleep_write_bits;
assign core_io_regs_key_write_valid = io_regs_key_write_valid;
assign core_io_regs_key_write_bits = io_regs_key_write_bits;
assign core_io_regs_wakeupProgram_0_write_valid = io_regs_wakeupProgram_0_write_valid;
assign core_io_regs_wakeupProgram_0_write_bits = io_regs_wakeupProgram_0_write_bits;
assign core_io_regs_wakeupProgram_1_write_valid = io_regs_wakeupProgram_1_write_valid;
assign core_io_regs_wakeupProgram_1_write_bits = io_regs_wakeupProgram_1_write_bits;
assign core_io_regs_wakeupProgram_2_write_valid = io_regs_wakeupProgram_2_write_valid;
assign core_io_regs_wakeupProgram_2_write_bits = io_regs_wakeupProgram_2_write_bits;
assign core_io_regs_wakeupProgram_3_write_valid = io_regs_wakeupProgram_3_write_valid;
assign core_io_regs_wakeupProgram_3_write_bits = io_regs_wakeupProgram_3_write_bits;
assign core_io_regs_wakeupProgram_4_write_valid = io_regs_wakeupProgram_4_write_valid;
assign core_io_regs_wakeupProgram_4_write_bits = io_regs_wakeupProgram_4_write_bits;
assign core_io_regs_wakeupProgram_5_write_valid = io_regs_wakeupProgram_5_write_valid;
assign core_io_regs_wakeupProgram_5_write_bits = io_regs_wakeupProgram_5_write_bits;
assign core_io_regs_wakeupProgram_6_write_valid = io_regs_wakeupProgram_6_write_valid;
assign core_io_regs_wakeupProgram_6_write_bits = io_regs_wakeupProgram_6_write_bits;
assign core_io_regs_wakeupProgram_7_write_valid = io_regs_wakeupProgram_7_write_valid;
assign core_io_regs_wakeupProgram_7_write_bits = io_regs_wakeupProgram_7_write_bits;
assign core_io_regs_sleepProgram_0_write_valid = io_regs_sleepProgram_0_write_valid;
assign core_io_regs_sleepProgram_0_write_bits = io_regs_sleepProgram_0_write_bits;
assign core_io_regs_sleepProgram_1_write_valid = io_regs_sleepProgram_1_write_valid;
assign core_io_regs_sleepProgram_1_write_bits = io_regs_sleepProgram_1_write_bits;
assign core_io_regs_sleepProgram_2_write_valid = io_regs_sleepProgram_2_write_valid;
assign core_io_regs_sleepProgram_2_write_bits = io_regs_sleepProgram_2_write_bits;
assign core_io_regs_sleepProgram_3_write_valid = io_regs_sleepProgram_3_write_valid;
assign core_io_regs_sleepProgram_3_write_bits = io_regs_sleepProgram_3_write_bits;
assign core_io_regs_sleepProgram_4_write_valid = io_regs_sleepProgram_4_write_valid;
assign core_io_regs_sleepProgram_4_write_bits = io_regs_sleepProgram_4_write_bits;
assign core_io_regs_sleepProgram_5_write_valid = io_regs_sleepProgram_5_write_valid;
assign core_io_regs_sleepProgram_5_write_bits = io_regs_sleepProgram_5_write_bits;
assign core_io_regs_sleepProgram_6_write_valid = io_regs_sleepProgram_6_write_valid;
assign core_io_regs_sleepProgram_6_write_bits = io_regs_sleepProgram_6_write_bits;
assign core_io_regs_sleepProgram_7_write_valid = io_regs_sleepProgram_7_write_valid;
assign core_io_regs_sleepProgram_7_write_bits = io_regs_sleepProgram_7_write_bits;
assign T_358 = {core_io_control_bits_vddpaden,core_io_control_bits_reserved0};
assign T_359 = {core_io_control_bits_hfclkrst,core_io_control_bits_corerst};
assign T_360 = {T_359,core_io_control_bits_reserved1};
assign T_361 = {T_360,T_358};
assign T_362 = ~ T_361;
assign AsyncResetRegVec_1_1_clock = clock;
assign AsyncResetRegVec_1_1_reset = reset;
assign AsyncResetRegVec_1_1_io_d = T_362;
assign AsyncResetRegVec_1_1_io_en = core_io_control_valid;
assign core_io_control_bits = ~ AsyncResetRegVec_1_1_io_q;
assign T_369_hfclkrst = T_379;
assign T_369_corerst = T_378;
assign T_369_reserved1 = T_377;
assign T_369_vddpaden = T_376;
assign T_369_reserved0 = T_375;
assign T_375 = core_io_control_bits[0];
assign T_376 = core_io_control_bits[1];
assign T_377 = core_io_control_bits[2];
assign T_378 = core_io_control_bits[3];
assign T_379 = core_io_control_bits[4];
assign T_380 = {io_resetCauses_wdogrst,io_resetCauses_erst};
assign T_381 = {T_380,io_resetCauses_porrst};
//assign SRLatch_3_reset = T_385;
//assign SRLatch_3_set = T_382;// POR
assign T_382 = T_381[0];// The POR
assign T_383 = T_381[1];// The ERST
assign T_384 = T_381[2];// The WDOG
assign T_385 = T_383 | T_384;
//assign SRLatch_1_1_reset = T_389;
//assign SRLatch_1_1_set = T_383;// ERST
assign T_389 = T_382 | T_384;
//assign SRLatch_2_1_reset = T_393;
//assign SRLatch_2_1_set = T_384;// WDOG
assign T_393 = T_382 | T_383;
//assign T_394 = {SRLatch_2_1_q,SRLatch_1_1_q};
//Bob assign T_395 = {T_394,SRLatch_3_q};
assign T_394 = {rstcause_wdog_r,rstcause_erst_r};
assign T_395 = {T_394,rstcause_por_r};
assign T_396 = T_395[2];
assign T_397 = T_395[1:0];
assign GEN_0 = {{1'd0}, T_396};
assign T_400 = GEN_0 | T_397;
assign T_401 = T_400[1];
assign T_402 = {T_396,T_401};
//Bob: The original code is here
//always @(posedge clock) begin
// T_355 <= reset;
// T_356 <= T_355;
//end
//Bob: Why here need to flop the reset twice? this is not allowed in coding style so just comment it out
always @(posedge clock or posedge reset) begin
if(reset) begin
T_355 <= 1'b1;
T_356 <= 1'b1;
end
else begin
T_355 <= 1'b0;
T_356 <= T_355;
end
end
endmodule
|
//datae:2016/3/20
//engineer:zhaoshaomin
//module name: return address stack which is used to predict indirect branch target ,
// in MIPS such as JR or JALR(which i didn't implemente)
module core_ras(//input
clk,
rst,
//inst fetch stage prediction
en_call_in, //in my previous version ,it equals en_ret_addr_in
en_ret_in,//in my previous version ,it equals en_ret_addr_out
ret_addr_in,// which is gened by call inst
// decode stage recover something wrong,which caused by misprediction in btb, in RAS.
recover_push,//previous inst was preded as a JR inst incorrectly.
recover_push_addr,//push back the top return addr to RAs
recover_pop,// previous inst was preded as a jal inst incorrectly.
////output
//inst fetch stage poping top addr
ret_addr_out
);
//parameter
parameter ps2=2'b00;
parameter ps1=2'b01;
parameter pp1=2'b10;
parameter pp2=2'b11;
//input
input clk;
input rst;
input en_call_in;
input en_ret_in;
input [29:0] ret_addr_in;
input recover_push;
input [29:0] recover_push_addr;
input recover_pop;
//output
output [31:0] ret_addr_out;
reg en_RAS_ret;
reg en_RAS_rec;
reg en_pointer;
reg [1:0] ret_addr_out_src;
//reg of RAS
reg [29:0] RAS_1;
reg [29:0] RAS_2;
reg [29:0] RAS_3;
reg [29:0] RAS_4;
reg [29:0] RAS_5;
reg [29:0] RAS_6;
reg [29:0] RAS_7;
reg [29:0] RAS_8;
reg [2:0] pointer;
reg [1:0] pointer_src;
always@(posedge clk)
begin
if(rst)
pointer<=3'b000;
else if(en_pointer&&(pointer_src==ps2))
pointer<=pointer-3'b010;
else if(en_pointer&&(pointer_src==ps1))
pointer<=pointer-3'b001;
else if(en_pointer&&(pointer_src==pp1))
pointer<=pointer+3'b001;
else if(en_pointer&&(pointer_src==pp2))
pointer<=pointer+3'b010;
end
// reg of en vector
reg [7:0] en_pointer_P0;
reg [7:0] en_pointer_P1;
reg [7:0] en_pointer_P2;
//en vector functions
always@(*)
begin
//en_pointer_p0 means enable of pinter
case(pointer)
3'b000:en_pointer_P0=8'b00000001;
3'b001:en_pointer_P0=8'b00000010;
3'b010:en_pointer_P0=8'b00000100;
3'b011:en_pointer_P0=8'b00001000;
3'b100:en_pointer_P0=8'b00010000;
3'b101:en_pointer_P0=8'b00100000;
3'b110:en_pointer_P0=8'b01000000;
3'b111:en_pointer_P0=8'b10000000;
default:en_pointer_P0=8'b00000000;
endcase
//en_pointer_p1 means enable of pinter+1
case(pointer)
3'b111:en_pointer_P1=8'b00000001;
3'b000:en_pointer_P1=8'b00000010;
3'b001:en_pointer_P1=8'b00000100;
3'b010:en_pointer_P1=8'b00001000;
3'b011:en_pointer_P1=8'b00010000;
3'b100:en_pointer_P1=8'b00100000;
3'b101:en_pointer_P1=8'b01000000;
3'b110:en_pointer_P1=8'b10000000;
default:en_pointer_P1=8'b00000000;
endcase
//en_pointer_p2 means enable of pinter+2
case(pointer)
3'b111:en_pointer_P2=8'b00000010;
3'b000:en_pointer_P2=8'b00000100;
3'b001:en_pointer_P2=8'b00001000;
3'b010:en_pointer_P2=8'b00010000;
3'b011:en_pointer_P2=8'b00100000;
3'b100:en_pointer_P2=8'b01000000;
3'b101:en_pointer_P2=8'b10000000;
3'b110:en_pointer_P2=8'b00000001;
default:en_pointer_P2=8'b00000000;
endcase
end
//control signals for RAS
//reg of en_RAS_ret and en_RAS_rec
always@(*)
begin
//default values
en_RAS_ret=1'b0;
en_RAS_rec=1'b0;
pointer_src=pp2;
en_pointer=1'b0;
ret_addr_out_src=2'b11;
//////////////////////////////////
// when call_in meets recover_push
if(en_call_in&&recover_push)
begin
en_RAS_ret=1'b1;
en_RAS_rec=1'b1;
pointer_src=pp2;
en_pointer=1'b1;
end
else if(en_call_in&&!recover_push&&!recover_pop) //i'm not sure there is nothing wrong
begin
en_RAS_ret=1'b1;
pointer_src=pp1;
en_pointer=1'b1;
end
else if(!en_ret_in&&!en_call_in&&recover_push)
begin
en_RAS_rec=1'b1;
pointer_src=pp1;
en_pointer=1'b1;
end
///////////////////////////////////
//when ret_in meets recover_push
if(en_ret_in&&recover_push)
begin
ret_addr_out_src=2'b00;
end
else if(en_ret_in&&!recover_push&&!recover_pop)
begin
pointer_src=ps1;
en_pointer=1'b1;
ret_addr_out_src=2'b10;
end
////////////////////////////////////
///when call_in meets recover_pop
if(en_call_in&&recover_pop)
begin
en_RAS_ret=1'b1;
end
else if(!en_ret_in&&!en_call_in&&recover_pop)
begin
pointer_src=ps1;
en_pointer=1'b1;
end
////////////////////////////////////
//when ret_in meets recover_pop
if(en_ret_in&&recover_pop)
begin
ret_addr_out_src=2'b01;
pointer_src=ps2;
en_pointer=1'b1;
end
end
///////////////////////////////////
//write RAS_num
//RAS_1
always@(posedge clk)
begin
if(rst)
RAS_1<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[0]||en_pointer_P1[0]||en_pointer_P2[0]))
RAS_1<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[0]||en_pointer_P1[0]))
RAS_1<=recover_push_addr;
end
//RAS_2
always@(posedge clk)
begin
if(rst)
RAS_2<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[1]||en_pointer_P1[1]||en_pointer_P2[1]))
RAS_2<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[1]||en_pointer_P1[1]))
RAS_2<=recover_push_addr;
end
//RAS_3
always@(posedge clk)
begin
if(rst)
RAS_3<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[2]||en_pointer_P1[2]||en_pointer_P2[2]))
RAS_3<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[2]||en_pointer_P1[2]))
RAS_3<=recover_push_addr;
end
//RAS_4
always@(posedge clk)
begin
if(rst)
RAS_4<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[3]||en_pointer_P1[3]||en_pointer_P2[3]))
RAS_4<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[3]||en_pointer_P1[3]))
RAS_4<=recover_push_addr;
end
//RAS_5
always@(posedge clk)
begin
if(rst)
RAS_5<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[4]||en_pointer_P1[4]||en_pointer_P2[4]))
RAS_5<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[4]||en_pointer_P1[4]))
RAS_5<=recover_push_addr;
end
//RAS_6
always@(posedge clk)
begin
if(rst)
RAS_6<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[5]||en_pointer_P1[5]||en_pointer_P2[5]))
RAS_6<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[5]||en_pointer_P1[5]))
RAS_6<=recover_push_addr;
end
//RAS_7
always@(posedge clk)
begin
if(rst)
RAS_7<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[6]||en_pointer_P1[6]||en_pointer_P2[6]))
RAS_7<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[6]||en_pointer_P1[6]))
RAS_7<=recover_push_addr;
end
//RAS_8
always@(posedge clk)
begin
if(rst)
RAS_8<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[7]||en_pointer_P1[7]||en_pointer_P2[7]))
RAS_8<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[7]||en_pointer_P1[7]))
RAS_8<=recover_push_addr;
end
//read RAS port of pointer
reg [29:0] pointer_rd_ras;
always@(*)
begin
case(pointer)
3'b000:pointer_rd_ras=RAS_1;
3'b001:pointer_rd_ras=RAS_2;
3'b010:pointer_rd_ras=RAS_3;
3'b011:pointer_rd_ras=RAS_4;
3'b100:pointer_rd_ras=RAS_5;
3'b101:pointer_rd_ras=RAS_6;
3'b110:pointer_rd_ras=RAS_7;
3'b111:pointer_rd_ras=RAS_8;
default:pointer_rd_ras=30'hzzzzzzzz;
endcase
end
//read RAS port of pointere+1
reg [29:0] pointerP1_rd_ras;
always@(*)
begin
case(pointer)
3'b000:pointerP1_rd_ras=RAS_2;
3'b001:pointerP1_rd_ras=RAS_3;
3'b010:pointerP1_rd_ras=RAS_4;
3'b011:pointerP1_rd_ras=RAS_5;
3'b100:pointerP1_rd_ras=RAS_6;
3'b101:pointerP1_rd_ras=RAS_7;
3'b110:pointerP1_rd_ras=RAS_8;
3'b111:pointerP1_rd_ras=RAS_1;
default:pointerP1_rd_ras=30'hzzzzzzzz;
endcase
end
wire [29:0] ret_addr_out_temp;
assign ret_addr_out_temp=(ret_addr_out_src==2'b00)?recover_push_addr:
(ret_addr_out_src==2'b01)?pointer_rd_ras:
(ret_addr_out_src==2'b10)?pointerP1_rd_ras:30'hzzzzzzzz;
assign ret_addr_out={ret_addr_out_temp,2'b00};
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O21A_BEHAVIORAL_PP_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21A_BEHAVIORAL_PP_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_macstatus.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_macstatus.v,v $
// Revision 1.17 2005/03/21 20:07:18 igorm
// Some small fixes + some troubles fixed.
//
// Revision 1.16 2005/02/21 10:42:11 igorm
// Defer indication fixed.
//
// Revision 1.15 2003/01/30 13:28:19 tadejm
// Defer indication changed.
//
// Revision 1.14 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.13 2002/11/13 22:30:58 tadejm
// Late collision is reported only when not in the full duplex.
// Sample is taken (for status) as soon as MRxDV is not valid (regardless
// of the received byte cnt).
//
// Revision 1.12 2002/09/12 14:50:16 mohor
// CarrierSenseLost bug fixed when operating in full duplex mode.
//
// Revision 1.11 2002/09/04 18:38:03 mohor
// CarrierSenseLost status is not set when working in loopback mode.
//
// Revision 1.10 2002/07/25 18:17:46 mohor
// InvalidSymbol generation changed.
//
// Revision 1.9 2002/04/22 13:51:44 mohor
// Short frame and ReceivedLengthOK were not detected correctly.
//
// Revision 1.8 2002/02/18 10:40:17 mohor
// Small fixes.
//
// Revision 1.7 2002/02/15 17:07:39 mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.6 2002/02/11 09:18:21 mohor
// Tx status is written back to the BD.
//
// Revision 1.5 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
`include "timescale.v"
module eth_macstatus(
MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm,
StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
r_FullD
);
parameter Tp = 1;
input MRxClk;
input Reset;
input RxCrcError;
input MRxErr;
input MRxDV;
input RxStateSFD;
input [1:0] RxStateData;
input RxStatePreamble;
input RxStateIdle;
input Transmitting;
input [15:0] RxByteCnt;
input RxByteCntEq0;
input RxByteCntGreat2;
input RxByteCntMaxFrame;
input [3:0] MRxD;
input Collision;
input [5:0] CollValid;
input r_RecSmall;
input [15:0] r_MinFL;
input [15:0] r_MaxFL;
input r_HugEn;
input StartTxDone;
input StartTxAbort;
input [3:0] RetryCnt;
input MTxClk;
input MaxCollisionOccured;
input LateCollision;
input DeferIndication;
input TxStartFrm;
input StatePreamble;
input [1:0] StateData;
input CarrierSense;
input TxUsedData;
input Loopback;
input r_FullD;
output ReceivedLengthOK;
output ReceiveEnd;
output ReceivedPacketGood;
output InvalidSymbol;
output LatchedCrcError;
output RxLateCollision;
output ShortFrame;
output DribbleNibble;
output ReceivedPacketTooBig;
output LoadRxStatus;
output [3:0] RetryCntLatched;
output RetryLimit;
output LateCollLatched;
output DeferLatched;
input RstDeferLatched;
output CarrierSenseLost;
output LatchedMRxErr;
reg ReceiveEnd;
reg LatchedCrcError;
reg LatchedMRxErr;
reg LoadRxStatus;
reg InvalidSymbol;
reg [3:0] RetryCntLatched;
reg RetryLimit;
reg LateCollLatched;
reg DeferLatched;
reg CarrierSenseLost;
wire TakeSample;
wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
// Crc error
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedCrcError <=#Tp 1'b0;
else
if(RxStateSFD)
LatchedCrcError <=#Tp 1'b0;
else
if(RxStateData[0])
LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
end
// LatchedMRxErr
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedMRxErr <=#Tp 1'b0;
else
if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
LatchedMRxErr <=#Tp 1'b1;
else
LatchedMRxErr <=#Tp 1'b0;
end
// ReceivedPacketGood
assign ReceivedPacketGood = ~LatchedCrcError;
// ReceivedLengthOK
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
// Time to take a sample
//assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
assign TakeSample = (|RxStateData) & (~MRxDV) |
RxStateData[0] & MRxDV & RxByteCntMaxFrame;
// LoadRxStatus
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LoadRxStatus <=#Tp 1'b0;
else
LoadRxStatus <=#Tp TakeSample;
end
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ReceiveEnd <=#Tp 1'b0;
else
ReceiveEnd <=#Tp LoadRxStatus;
end
// Invalid Symbol received during 100Mbps mode
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
// InvalidSymbol
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
InvalidSymbol <=#Tp 1'b0;
else
if(LoadRxStatus & ~SetInvalidSymbol)
InvalidSymbol <=#Tp 1'b0;
else
if(SetInvalidSymbol)
InvalidSymbol <=#Tp 1'b1;
end
// Late Collision
reg RxLateCollision;
reg RxColWindow;
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxLateCollision <=#Tp 1'b0;
else
if(LoadRxStatus)
RxLateCollision <=#Tp 1'b0;
else
if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
RxLateCollision <=#Tp 1'b1;
end
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxColWindow <=#Tp 1'b1;
else
if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
RxColWindow <=#Tp 1'b0;
else
if(RxStateIdle)
RxColWindow <=#Tp 1'b1;
end
// ShortFrame
reg ShortFrame;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShortFrame <=#Tp 1'b0;
else
if(LoadRxStatus)
ShortFrame <=#Tp 1'b0;
else
if(TakeSample)
ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];
end
// DribbleNibble
reg DribbleNibble;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DribbleNibble <=#Tp 1'b0;
else
if(RxStateSFD)
DribbleNibble <=#Tp 1'b0;
else
if(~MRxDV & RxStateData[1])
DribbleNibble <=#Tp 1'b1;
end
reg ReceivedPacketTooBig;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ReceivedPacketTooBig <=#Tp 1'b0;
else
if(LoadRxStatus)
ReceivedPacketTooBig <=#Tp 1'b0;
else
if(TakeSample)
ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
end
// Latched Retry counter for tx status
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryCntLatched <=#Tp 4'h0;
else
if(StartTxDone | StartTxAbort)
RetryCntLatched <=#Tp RetryCnt;
end
// Latched Retransmission limit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryLimit <=#Tp 1'h0;
else
if(StartTxDone | StartTxAbort)
RetryLimit <=#Tp MaxCollisionOccured;
end
// Latched Late Collision
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
LateCollLatched <=#Tp 1'b0;
else
if(StartTxDone | StartTxAbort)
LateCollLatched <=#Tp LateCollision;
end
// Latched Defer state
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DeferLatched <=#Tp 1'b0;
else
if(DeferIndication)
DeferLatched <=#Tp 1'b1;
else
if(RstDeferLatched)
DeferLatched <=#Tp 1'b0;
end
// CarrierSenseLost
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
CarrierSenseLost <=#Tp 1'b0;
else
if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
CarrierSenseLost <=#Tp 1'b1;
else
if(TxStartFrm)
CarrierSenseLost <=#Tp 1'b0;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_hvl__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hvl__udp_dlatch$P dlatch0 (m0 , SCE_GATE, clkn );
and and0 (GCLK , m0n, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_PP_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR3_PP_SYMBOL_V
`define SKY130_FD_SC_LP__XOR3_PP_SYMBOL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR3_PP_SYMBOL_V
|
Require Import Coq.Lists.List.
(* type level existential quantifier *)
Notation "'existsT' x .. y , p" :=
(sigT (fun x => .. (sigT (fun y => p)) ..))
(at level 200, x binder, right associativity,
format "'[' 'existsT' '/ ' x .. y , '/ ' p ']'")
: type_scope.
(* the following shows that a decidable (or boolean valued) predicate on a finite list
can always be reified in terms of strong existence *)
Theorem reify {A: Type} (l: list A) (P: A -> bool) :
(exists x, In x l /\ P x = true) -> existsT x, P x = true.
Proof.
intro H.
induction l.
contradict H.
intro H0.
destruct H0 as [x Hx].
destruct Hx as [H1 H2].
inversion H1.
(* list not nil *)
assert (Hbiv: {P a = true} + {P a <> true}).
decide equality.
destruct Hbiv as [Htrue | Hfalse].
exists a.
assumption.
(* the element is in the tail *)
apply IHl.
destruct H as [x Hx].
destruct Hx as [Hl Hr].
assert (Hin: a = x \/ In x l). apply in_inv. assumption.
destruct Hin as [Hin1 | Hin2].
(* case a = x: impossible *)
subst.
contradict Hr. assumption.
exists x. split. assumption. assumption.
Qed.
Program Fixpoint addlist (ls1 ls2 : list nat) : list nat :=
match ls1, ls2 with
| n1 :: ls1',n2 :: ls2' => n1 + n2 :: addlist ls1' ls2'
|_, _ => nil
end.
Eval compute in fun ls => addlist nil ls.
Eval compute in fun ls => addlist ls nil.
Definition one_plus_one : 1 + 1 = 2 := eq_refl.
Definition zero_plus_n n : 0 + n = n := eq_refl.
Compute (zero_plus_n 10).
Eval compute in (zero_plus_n 10).
Fail Definition n_plus_zero n : n + 0 = n := eq_refl.
Program Definition n_plus_zero n : n + 0 = n.
induction n.
+ auto.
+ simpl. rewrite IHn. apply eq_refl.
Defined.
Print n_plus_zero.
Inductive expr :=
| Var : nat -> expr
| Add : expr -> expr -> expr
| Mul : expr -> expr -> expr.
Example expr_ex :=
Mul (Var 0) (Add (Var 0) (Var 1)).
Inductive isEven : nat -> Prop :=
| Even_O : isEven 0
| Even_SS n : isEven n -> isEven (S (S n)).
Ltac prove_even := repeat constructor.
Theorem even_256 : isEven 256.
Proof.
prove_even.
Qed.
Print even_256.
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 28 11:37:19 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.v
// Design : fifo_generator_rx_inst
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty);
(* x_interface_info = "xilinx.com:signal:clock:1.0 core_clk CLK" *) input clk;
input rst;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [63:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [63:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [10:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [10:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "1" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "11" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "64" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "2kx18" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "2046" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "2045" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "11" *)
(* C_RD_DEPTH = "2048" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "11" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "11" *)
(* C_WR_DEPTH = "2048" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "11" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(clk),
.data_count(NLW_U0_data_count_UNCONNECTED[10:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[10:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(1'b0),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[10:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [63:0]din;
wire [10:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r
(.Q(Q),
.clk(clk),
.din(din[17:0]),
.dout(dout[17:0]),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.Q(Q),
.clk(clk),
.din(din[35:18]),
.dout(dout[35:18]),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.Q(Q),
.clk(clk),
.din(din[53:36]),
.dout(dout[53:36]),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.Q(Q),
.clk(clk),
.din(din[63:54]),
.dout(dout[63:54]),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [17:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [17:0]din;
wire [10:0]Q;
wire clk;
wire [17:0]din;
wire [17:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [17:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [17:0]din;
wire [10:0]Q;
wire clk;
wire [17:0]din;
wire [17:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [17:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [17:0]din;
wire [10:0]Q;
wire clk;
wire [17:0]din;
wire [17:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [9:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [9:0]din;
wire [10:0]Q;
wire clk;
wire [9:0]din;
wire [9:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [17:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [17:0]din;
wire [10:0]Q;
wire clk;
wire [17:0]din;
wire [17:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gcc0.gc0.count_d1_reg[10] ,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[16:9],din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,din[17],din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:16],dout[16:9],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:2],dout[17],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [17:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [17:0]din;
wire [10:0]Q;
wire clk;
wire [17:0]din;
wire [17:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gcc0.gc0.count_d1_reg[10] ,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[16:9],din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,din[17],din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:16],dout[16:9],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:2],dout[17],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [17:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [17:0]din;
wire [10:0]Q;
wire clk;
wire [17:0]din;
wire [17:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gcc0.gc0.count_d1_reg[10] ,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[16:9],din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,din[17],din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:16],dout[16:9],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:2],dout[17],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [9:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [9:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_71 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_79 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [10:0]Q;
wire clk;
wire [9:0]din;
wire [9:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gcc0.gc0.count_d1_reg[10] ,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[9:5],1'b0,1'b0,1'b0,din[4:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:16],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_71 ,dout[9:5],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_79 ,dout[4:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:2],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [63:0]din;
wire [10:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [63:0]din;
wire [10:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [63:0]din;
wire [10:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
(ram_full_comb,
v1_reg,
\gc0.count_d1_reg[10] ,
wr_en,
comp1,
wr_rst_busy,
out,
ram_empty_fb_i_reg);
output ram_full_comb;
input [4:0]v1_reg;
input \gc0.count_d1_reg[10] ;
input wr_en;
input comp1;
input wr_rst_busy;
input out;
input [0:0]ram_empty_fb_i_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp0;
wire comp1;
wire \gc0.count_d1_reg[10] ;
wire out;
wire [0:0]ram_empty_fb_i_reg;
wire ram_full_comb;
wire [4:0]v1_reg;
wire wr_en;
wire wr_rst_busy;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gc0.count_d1_reg[10] ,v1_reg[4]}));
LUT6 #(
.INIT(64'h0055000000FFC0C0))
ram_full_fb_i_i_1
(.I0(comp0),
.I1(wr_en),
.I2(comp1),
.I3(wr_rst_busy),
.I4(out),
.I5(ram_empty_fb_i_reg),
.O(ram_full_comb));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
(comp1,
v1_reg_0,
\gc0.count_d1_reg[10] );
output comp1;
input [4:0]v1_reg_0;
input \gc0.count_d1_reg[10] ;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp1;
wire \gc0.count_d1_reg[10] ;
wire [4:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gc0.count_d1_reg[10] ,v1_reg_0[4]}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
(ram_empty_i_reg,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
\gc0.count_d1_reg[10] ,
rd_en,
out,
comp1,
wr_en,
ram_full_fb_i_reg);
output ram_empty_i_reg;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input \gc0.count_d1_reg[10] ;
input rd_en;
input out;
input comp1;
input wr_en;
input ram_full_fb_i_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp0;
wire comp1;
wire \gc0.count_d1_reg[10] ;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire rd_en;
wire wr_en;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S({\gcc0.gc0.count_d1_reg[6] ,\gcc0.gc0.count_d1_reg[4] ,\gcc0.gc0.count_d1_reg[2] ,\gcc0.gc0.count_d1_reg[0] }));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gc0.count_d1_reg[10] ,\gcc0.gc0.count_d1_reg[8] }));
LUT6 #(
.INIT(64'hFCF0FCF05050FCF0))
ram_empty_fb_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(out),
.I3(comp1),
.I4(wr_en),
.I5(ram_full_fb_i_reg),
.O(ram_empty_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
(comp1,
v1_reg,
\gc0.count_reg[10] );
output comp1;
input [4:0]v1_reg;
input \gc0.count_reg[10] ;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp1;
wire \gc0.count_reg[10] ;
wire [4:0]v1_reg;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gc0.count_reg[10] ,v1_reg[4]}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gl0.rd_n_2 ;
wire \gntv_or_sync_fifo.gl0.rd_n_25 ;
wire \gntv_or_sync_fifo.gl0.rd_n_3 ;
wire \gntv_or_sync_fifo.gl0.wr_n_0 ;
wire \gntv_or_sync_fifo.gl0.wr_n_2 ;
wire \gntv_or_sync_fifo.gl0.wr_n_20 ;
wire \gntv_or_sync_fifo.gl0.wr_n_21 ;
wire \gntv_or_sync_fifo.gl0.wr_n_22 ;
wire \gntv_or_sync_fifo.gl0.wr_n_23 ;
wire \gntv_or_sync_fifo.gl0.wr_n_24 ;
wire [4:0]\grss.rsts/c2/v1_reg ;
wire [10:0]p_0_out;
wire [10:0]p_11_out;
wire [10:10]p_12_out;
wire p_2_out;
wire rd_en;
wire [9:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire tmp_ram_rd_en;
wire wr_en;
wire wr_rst_busy;
wire [1:1]wr_rst_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic \gntv_or_sync_fifo.gl0.rd
(.AR(rd_rst_i[2]),
.E(\gntv_or_sync_fifo.gl0.rd_n_2 ),
.Q(p_0_out),
.clk(clk),
.empty(empty),
.\gc0.count_d1_reg[9] (rd_pntr_plus1),
.\gcc0.gc0.count_d1_reg[0] (\gntv_or_sync_fifo.gl0.wr_n_20 ),
.\gcc0.gc0.count_d1_reg[10] (p_11_out[10]),
.\gcc0.gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.wr_n_21 ),
.\gcc0.gc0.count_d1_reg[4] (\gntv_or_sync_fifo.gl0.wr_n_22 ),
.\gcc0.gc0.count_d1_reg[6] (\gntv_or_sync_fifo.gl0.wr_n_23 ),
.\gcc0.gc0.count_d1_reg[8] (\gntv_or_sync_fifo.gl0.wr_n_24 ),
.\gcc0.gc0.count_reg[10] (p_12_out),
.out(p_2_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_0 ),
.ram_full_i_reg(\gntv_or_sync_fifo.gl0.rd_n_3 ),
.ram_full_i_reg_0(\gntv_or_sync_fifo.gl0.rd_n_25 ),
.rd_en(rd_en),
.v1_reg(\grss.rsts/c2/v1_reg ),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (p_11_out),
.E(\gntv_or_sync_fifo.gl0.rd_n_2 ),
.Q(p_12_out),
.clk(clk),
.full(full),
.\gc0.count_d1_reg[10] (\gntv_or_sync_fifo.gl0.rd_n_3 ),
.\gc0.count_d1_reg[10]_0 (\gntv_or_sync_fifo.gl0.rd_n_25 ),
.\gc0.count_d1_reg[9] (p_0_out[9:0]),
.\gc0.count_reg[9] (rd_pntr_plus1),
.\gcc0.gc0.count_d1_reg[10] (\gntv_or_sync_fifo.gl0.wr_n_2 ),
.\grstd1.grst_full.grst_f.rst_d2_reg (rst_full_ff_i),
.out(\gntv_or_sync_fifo.gl0.wr_n_0 ),
.ram_empty_i_reg(\gntv_or_sync_fifo.gl0.wr_n_20 ),
.ram_empty_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_21 ),
.ram_empty_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_22 ),
.ram_empty_i_reg_2(\gntv_or_sync_fifo.gl0.wr_n_23 ),
.ram_empty_i_reg_3(\gntv_or_sync_fifo.gl0.wr_n_24 ),
.v1_reg(\grss.rsts/c2/v1_reg ),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory \gntv_or_sync_fifo.mem
(.Q(p_0_out),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (p_11_out),
.out(rd_rst_i[0]),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo rstblk
(.clk(clk),
.\gc0.count_reg[1] ({rd_rst_i[2],rd_rst_i[0]}),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.out(wr_rst_i),
.ram_empty_fb_i_reg(p_2_out),
.rd_en(rd_en),
.rst(rst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo \grf.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "1" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "11" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "64" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "2kx18" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "2046" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "2045" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "11" *)
(* C_RD_DEPTH = "2048" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "11" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "11" *)
(* C_WR_DEPTH = "2048" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "11" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [63:0]din;
input wr_en;
input rd_en;
input [10:0]prog_empty_thresh;
input [10:0]prog_empty_thresh_assert;
input [10:0]prog_empty_thresh_negate;
input [10:0]prog_full_thresh;
input [10:0]prog_full_thresh_assert;
input [10:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [63:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [10:0]data_count;
output [10:0]rd_data_count;
output [10:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[10] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[10] = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[10] = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth inst_fifo_gen
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top \gconvfifo.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
\gcc0.gc0.count_d1_reg[10] ,
Q,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [10:0]\gcc0.gc0.count_d1_reg[10] ;
input [10:0]Q;
input [63:0]din;
wire [10:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [10:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
(ram_full_i_reg,
Q,
ram_empty_i_reg,
ram_full_i_reg_0,
ram_empty_i_reg_0,
\gc0.count_d1_reg[9]_0 ,
\gcc0.gc0.count_d1_reg[10] ,
\gcc0.gc0.count_reg[10] ,
E,
clk,
AR);
output ram_full_i_reg;
output [10:0]Q;
output ram_empty_i_reg;
output ram_full_i_reg_0;
output ram_empty_i_reg_0;
output [9:0]\gc0.count_d1_reg[9]_0 ;
input [0:0]\gcc0.gc0.count_d1_reg[10] ;
input [0:0]\gcc0.gc0.count_reg[10] ;
input [0:0]E;
input clk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [10:0]Q;
wire clk;
wire \gc0.count[10]_i_2_n_0 ;
wire [9:0]\gc0.count_d1_reg[9]_0 ;
wire [0:0]\gcc0.gc0.count_d1_reg[10] ;
wire [0:0]\gcc0.gc0.count_reg[10] ;
wire [10:0]plusOp;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_full_i_reg;
wire ram_full_i_reg_0;
wire [10:10]rd_pntr_plus1;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [0]),
.O(plusOp[0]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[10]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [8]),
.I1(\gc0.count_d1_reg[9]_0 [6]),
.I2(\gc0.count[10]_i_2_n_0 ),
.I3(\gc0.count_d1_reg[9]_0 [7]),
.I4(\gc0.count_d1_reg[9]_0 [9]),
.I5(rd_pntr_plus1),
.O(plusOp[10]));
LUT6 #(
.INIT(64'h8000000000000000))
\gc0.count[10]_i_2
(.I0(\gc0.count_d1_reg[9]_0 [5]),
.I1(\gc0.count_d1_reg[9]_0 [3]),
.I2(\gc0.count_d1_reg[9]_0 [1]),
.I3(\gc0.count_d1_reg[9]_0 [0]),
.I4(\gc0.count_d1_reg[9]_0 [2]),
.I5(\gc0.count_d1_reg[9]_0 [4]),
.O(\gc0.count[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [0]),
.I1(\gc0.count_d1_reg[9]_0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [0]),
.I1(\gc0.count_d1_reg[9]_0 [1]),
.I2(\gc0.count_d1_reg[9]_0 [2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [1]),
.I1(\gc0.count_d1_reg[9]_0 [0]),
.I2(\gc0.count_d1_reg[9]_0 [2]),
.I3(\gc0.count_d1_reg[9]_0 [3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [2]),
.I1(\gc0.count_d1_reg[9]_0 [0]),
.I2(\gc0.count_d1_reg[9]_0 [1]),
.I3(\gc0.count_d1_reg[9]_0 [3]),
.I4(\gc0.count_d1_reg[9]_0 [4]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[5]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [3]),
.I1(\gc0.count_d1_reg[9]_0 [1]),
.I2(\gc0.count_d1_reg[9]_0 [0]),
.I3(\gc0.count_d1_reg[9]_0 [2]),
.I4(\gc0.count_d1_reg[9]_0 [4]),
.I5(\gc0.count_d1_reg[9]_0 [5]),
.O(plusOp[5]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[6]_i_1
(.I0(\gc0.count[10]_i_2_n_0 ),
.I1(\gc0.count_d1_reg[9]_0 [6]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[7]_i_1
(.I0(\gc0.count[10]_i_2_n_0 ),
.I1(\gc0.count_d1_reg[9]_0 [6]),
.I2(\gc0.count_d1_reg[9]_0 [7]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[8]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [6]),
.I1(\gc0.count[10]_i_2_n_0 ),
.I2(\gc0.count_d1_reg[9]_0 [7]),
.I3(\gc0.count_d1_reg[9]_0 [8]),
.O(plusOp[8]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[9]_i_1
(.I0(\gc0.count_d1_reg[9]_0 [7]),
.I1(\gc0.count[10]_i_2_n_0 ),
.I2(\gc0.count_d1_reg[9]_0 [6]),
.I3(\gc0.count_d1_reg[9]_0 [8]),
.I4(\gc0.count_d1_reg[9]_0 [9]),
.O(plusOp[9]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[10]
(.C(clk),
.CE(E),
.CLR(AR),
.D(rd_pntr_plus1),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(clk),
.CE(E),
.CLR(AR),
.D(\gc0.count_d1_reg[9]_0 [9]),
.Q(Q[9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp[0]),
.PRE(AR),
.Q(\gc0.count_d1_reg[9]_0 [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[10]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[10]),
.Q(rd_pntr_plus1));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[1]),
.Q(\gc0.count_d1_reg[9]_0 [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[2]),
.Q(\gc0.count_d1_reg[9]_0 [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[3]),
.Q(\gc0.count_d1_reg[9]_0 [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[4]),
.Q(\gc0.count_d1_reg[9]_0 [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[5]),
.Q(\gc0.count_d1_reg[9]_0 [5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[6]),
.Q(\gc0.count_d1_reg[9]_0 [6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[7]),
.Q(\gc0.count_d1_reg[9]_0 [7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[8]),
.Q(\gc0.count_d1_reg[9]_0 [8]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[9]),
.Q(\gc0.count_d1_reg[9]_0 [9]));
LUT2 #(
.INIT(4'h9))
\gmux.gm[5].gms.ms_i_1
(.I0(Q[10]),
.I1(\gcc0.gc0.count_d1_reg[10] ),
.O(ram_full_i_reg));
LUT2 #(
.INIT(4'h9))
\gmux.gm[5].gms.ms_i_1__0
(.I0(rd_pntr_plus1),
.I1(\gcc0.gc0.count_d1_reg[10] ),
.O(ram_empty_i_reg));
LUT2 #(
.INIT(4'h9))
\gmux.gm[5].gms.ms_i_1__1
(.I0(Q[10]),
.I1(\gcc0.gc0.count_reg[10] ),
.O(ram_full_i_reg_0));
LUT2 #(
.INIT(4'h9))
\gmux.gm[5].gms.ms_i_1__2
(.I0(Q[10]),
.I1(\gcc0.gc0.count_d1_reg[10] ),
.O(ram_empty_i_reg_0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
(out,
empty,
E,
ram_full_i_reg,
Q,
\gc0.count_d1_reg[9] ,
ram_full_i_reg_0,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
v1_reg,
clk,
AR,
rd_en,
\gcc0.gc0.count_d1_reg[10] ,
\gcc0.gc0.count_reg[10] ,
wr_en,
ram_full_fb_i_reg);
output out;
output empty;
output [0:0]E;
output ram_full_i_reg;
output [10:0]Q;
output [9:0]\gc0.count_d1_reg[9] ;
output ram_full_i_reg_0;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input [4:0]v1_reg;
input clk;
input [0:0]AR;
input rd_en;
input [0:0]\gcc0.gc0.count_d1_reg[10] ;
input [0:0]\gcc0.gc0.count_reg[10] ;
input wr_en;
input ram_full_fb_i_reg;
wire [0:0]AR;
wire [0:0]E;
wire [10:0]Q;
wire clk;
wire empty;
wire [9:0]\gc0.count_d1_reg[9] ;
wire \gcc0.gc0.count_d1_reg[0] ;
wire [0:0]\gcc0.gc0.count_d1_reg[10] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire [0:0]\gcc0.gc0.count_reg[10] ;
wire out;
wire ram_full_fb_i_reg;
wire ram_full_i_reg;
wire ram_full_i_reg_0;
wire rd_en;
wire rpntr_n_12;
wire rpntr_n_14;
wire [4:0]v1_reg;
wire wr_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss \grss.rsts
(.AR(AR),
.E(E),
.clk(clk),
.empty(empty),
.\gc0.count_d1_reg[10] (rpntr_n_14),
.\gc0.count_reg[10] (rpntr_n_12),
.\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ),
.\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ),
.\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.rd_en(rd_en),
.v1_reg(v1_reg),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr rpntr
(.AR(AR),
.E(E),
.Q(Q),
.clk(clk),
.\gc0.count_d1_reg[9]_0 (\gc0.count_d1_reg[9] ),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.\gcc0.gc0.count_reg[10] (\gcc0.gc0.count_reg[10] ),
.ram_empty_i_reg(rpntr_n_12),
.ram_empty_i_reg_0(rpntr_n_14),
.ram_full_i_reg(ram_full_i_reg),
.ram_full_i_reg_0(ram_full_i_reg_0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
(out,
empty,
E,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
\gc0.count_d1_reg[10] ,
v1_reg,
\gc0.count_reg[10] ,
clk,
AR,
rd_en,
wr_en,
ram_full_fb_i_reg);
output out;
output empty;
output [0:0]E;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input \gc0.count_d1_reg[10] ;
input [4:0]v1_reg;
input \gc0.count_reg[10] ;
input clk;
input [0:0]AR;
input rd_en;
input wr_en;
input ram_full_fb_i_reg;
wire [0:0]AR;
wire [0:0]E;
wire c1_n_0;
wire clk;
wire comp1;
wire \gc0.count_d1_reg[10] ;
wire \gc0.count_reg[10] ;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire ram_full_fb_i_reg;
wire rd_en;
wire [4:0]v1_reg;
wire wr_en;
assign empty = ram_empty_i;
assign out = ram_empty_fb_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 c1
(.comp1(comp1),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10] ),
.\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ),
.\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ),
.\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.out(ram_empty_fb_i),
.ram_empty_i_reg(c1_n_0),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.rd_en(rd_en),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 c2
(.comp1(comp1),
.\gc0.count_reg[10] (\gc0.count_reg[10] ),
.v1_reg(v1_reg));
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[10]_i_1
(.I0(rd_en),
.I1(ram_empty_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(c1_n_0),
.PRE(AR),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(clk),
.CE(1'b1),
.D(c1_n_0),
.PRE(AR),
.Q(ram_empty_i));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
wr_rst_busy,
tmp_ram_rd_en,
clk,
rst,
ram_empty_fb_i_reg,
rd_en);
output [0:0]out;
output [1:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output wr_rst_busy;
output tmp_ram_rd_en;
input clk;
input rst;
input ram_empty_fb_i_reg;
input rd_en;
wire clk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ;
wire p_7_out;
wire p_8_out;
wire ram_empty_fb_i_reg;
wire rd_en;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
wire rst;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire tmp_ram_rd_en;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [1] = rd_rst_reg[2];
assign \gc0.count_reg[1] [0] = rd_rst_reg[0];
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[0] = wr_rst_reg[1];
assign wr_rst_busy = rst_d3;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(rd_rst_reg[0]),
.I1(ram_empty_fb_i_reg),
.I2(rd_en),
.O(tmp_ram_rd_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.clk(clk),
.in0(rd_rst_asreg),
.\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.out(p_7_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.clk(clk),
.in0(wr_rst_asreg),
.\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.out(p_8_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.clk(clk),
.in0(rd_rst_asreg),
.out(p_7_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.clk(clk),
.in0(wr_rst_asreg),
.out(p_8_out));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[2]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
(out,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ,
in0,
clk);
output out;
output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
input [0:0]in0;
input clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
(out,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ,
in0,
clk);
output out;
output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
input [0:0]in0;
input clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
(AS,
out,
clk,
in0);
output [0:0]AS;
input out;
input clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire out;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
(AS,
out,
clk,
in0);
output [0:0]AS;
input out;
input clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire out;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
(Q,
v1_reg_0,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
v1_reg,
v1_reg_1,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_empty_i_reg_1,
ram_empty_i_reg_2,
ram_empty_i_reg_3,
\gc0.count_d1_reg[9] ,
\gc0.count_reg[9] ,
E,
clk,
AR);
output [0:0]Q;
output [4:0]v1_reg_0;
output [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output [4:0]v1_reg;
output [4:0]v1_reg_1;
output ram_empty_i_reg;
output ram_empty_i_reg_0;
output ram_empty_i_reg_1;
output ram_empty_i_reg_2;
output ram_empty_i_reg_3;
input [9:0]\gc0.count_d1_reg[9] ;
input [9:0]\gc0.count_reg[9] ;
input [0:0]E;
input clk;
input [0:0]AR;
wire [0:0]AR;
wire [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [0:0]Q;
wire clk;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gc0.count_reg[9] ;
wire \gcc0.gc0.count[10]_i_2_n_0 ;
wire [9:0]p_12_out;
wire [10:0]plusOp__0;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_empty_i_reg_1;
wire ram_empty_i_reg_2;
wire ram_empty_i_reg_3;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire [4:0]v1_reg_1;
LUT1 #(
.INIT(2'h1))
\gcc0.gc0.count[0]_i_1
(.I0(p_12_out[0]),
.O(plusOp__0[0]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gcc0.gc0.count[10]_i_1
(.I0(p_12_out[8]),
.I1(p_12_out[6]),
.I2(\gcc0.gc0.count[10]_i_2_n_0 ),
.I3(p_12_out[7]),
.I4(p_12_out[9]),
.I5(Q),
.O(plusOp__0[10]));
LUT6 #(
.INIT(64'h8000000000000000))
\gcc0.gc0.count[10]_i_2
(.I0(p_12_out[5]),
.I1(p_12_out[3]),
.I2(p_12_out[1]),
.I3(p_12_out[0]),
.I4(p_12_out[2]),
.I5(p_12_out[4]),
.O(\gcc0.gc0.count[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gcc0.gc0.count[1]_i_1
(.I0(p_12_out[0]),
.I1(p_12_out[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\gcc0.gc0.count[2]_i_1
(.I0(p_12_out[0]),
.I1(p_12_out[1]),
.I2(p_12_out[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\gcc0.gc0.count[3]_i_1
(.I0(p_12_out[1]),
.I1(p_12_out[0]),
.I2(p_12_out[2]),
.I3(p_12_out[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gcc0.gc0.count[4]_i_1
(.I0(p_12_out[2]),
.I1(p_12_out[0]),
.I2(p_12_out[1]),
.I3(p_12_out[3]),
.I4(p_12_out[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gcc0.gc0.count[5]_i_1
(.I0(p_12_out[3]),
.I1(p_12_out[1]),
.I2(p_12_out[0]),
.I3(p_12_out[2]),
.I4(p_12_out[4]),
.I5(p_12_out[5]),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gcc0.gc0.count[6]_i_1
(.I0(\gcc0.gc0.count[10]_i_2_n_0 ),
.I1(p_12_out[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h78))
\gcc0.gc0.count[7]_i_1
(.I0(\gcc0.gc0.count[10]_i_2_n_0 ),
.I1(p_12_out[6]),
.I2(p_12_out[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\gcc0.gc0.count[8]_i_1
(.I0(p_12_out[6]),
.I1(\gcc0.gc0.count[10]_i_2_n_0 ),
.I2(p_12_out[7]),
.I3(p_12_out[8]),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gcc0.gc0.count[9]_i_1
(.I0(p_12_out[7]),
.I1(\gcc0.gc0.count[10]_i_2_n_0 ),
.I2(p_12_out[6]),
.I3(p_12_out[8]),
.I4(p_12_out[9]),
.O(plusOp__0[9]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[10]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [10]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[9]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[9]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]));
FDPE #(
.INIT(1'b1))
\gcc0.gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp__0[0]),
.PRE(AR),
.Q(p_12_out[0]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[10]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[10]),
.Q(Q));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[1]),
.Q(p_12_out[1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[2]),
.Q(p_12_out[2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[3]),
.Q(p_12_out[3]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[4]),
.Q(p_12_out[4]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[5]),
.Q(p_12_out[5]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[6]),
.Q(p_12_out[6]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[7]),
.Q(p_12_out[7]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[8]),
.Q(p_12_out[8]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[9]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[9]),
.Q(p_12_out[9]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I1(\gc0.count_d1_reg[9] [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I3(\gc0.count_d1_reg[9] [1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I1(\gc0.count_reg[9] [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I3(\gc0.count_reg[9] [1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(p_12_out[0]),
.I1(\gc0.count_d1_reg[9] [0]),
.I2(p_12_out[1]),
.I3(\gc0.count_d1_reg[9] [1]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I1(\gc0.count_d1_reg[9] [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I3(\gc0.count_d1_reg[9] [1]),
.O(ram_empty_i_reg));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.I1(\gc0.count_d1_reg[9] [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.I3(\gc0.count_d1_reg[9] [3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.I1(\gc0.count_reg[9] [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.I3(\gc0.count_reg[9] [3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(p_12_out[2]),
.I1(\gc0.count_d1_reg[9] [2]),
.I2(p_12_out[3]),
.I3(\gc0.count_d1_reg[9] [3]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.I1(\gc0.count_d1_reg[9] [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.I3(\gc0.count_d1_reg[9] [3]),
.O(ram_empty_i_reg_0));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.I1(\gc0.count_d1_reg[9] [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.I3(\gc0.count_d1_reg[9] [5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.I1(\gc0.count_reg[9] [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.I3(\gc0.count_reg[9] [5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(p_12_out[4]),
.I1(\gc0.count_d1_reg[9] [4]),
.I2(p_12_out[5]),
.I3(\gc0.count_d1_reg[9] [5]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.I1(\gc0.count_d1_reg[9] [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.I3(\gc0.count_d1_reg[9] [5]),
.O(ram_empty_i_reg_1));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.I1(\gc0.count_d1_reg[9] [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.I3(\gc0.count_d1_reg[9] [7]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.I1(\gc0.count_reg[9] [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.I3(\gc0.count_reg[9] [7]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(p_12_out[6]),
.I1(\gc0.count_d1_reg[9] [6]),
.I2(p_12_out[7]),
.I3(\gc0.count_d1_reg[9] [7]),
.O(v1_reg_1[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.I1(\gc0.count_d1_reg[9] [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.I3(\gc0.count_d1_reg[9] [7]),
.O(ram_empty_i_reg_2));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.I1(\gc0.count_d1_reg[9] [8]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.I3(\gc0.count_d1_reg[9] [9]),
.O(v1_reg_0[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.I1(\gc0.count_reg[9] [8]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.I3(\gc0.count_reg[9] [9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__1
(.I0(p_12_out[8]),
.I1(\gc0.count_d1_reg[9] [8]),
.I2(p_12_out[9]),
.I3(\gc0.count_d1_reg[9] [9]),
.O(v1_reg_1[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.I1(\gc0.count_d1_reg[9] [8]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.I3(\gc0.count_d1_reg[9] [9]),
.O(ram_empty_i_reg_3));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
(out,
full,
\gcc0.gc0.count_d1_reg[10] ,
Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
v1_reg,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_empty_i_reg_1,
ram_empty_i_reg_2,
ram_empty_i_reg_3,
\gc0.count_d1_reg[10] ,
\gc0.count_d1_reg[10]_0 ,
clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
wr_en,
\gc0.count_d1_reg[9] ,
\gc0.count_reg[9] ,
wr_rst_busy,
E,
AR);
output out;
output full;
output \gcc0.gc0.count_d1_reg[10] ;
output [0:0]Q;
output [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output [4:0]v1_reg;
output ram_empty_i_reg;
output ram_empty_i_reg_0;
output ram_empty_i_reg_1;
output ram_empty_i_reg_2;
output ram_empty_i_reg_3;
input \gc0.count_d1_reg[10] ;
input \gc0.count_d1_reg[10]_0 ;
input clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input wr_en;
input [9:0]\gc0.count_d1_reg[9] ;
input [9:0]\gc0.count_reg[9] ;
input wr_rst_busy;
input [0:0]E;
input [0:0]AR;
wire [0:0]AR;
wire [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [0:0]Q;
wire [4:0]\c0/v1_reg ;
wire [4:0]\c1/v1_reg ;
wire clk;
wire full;
wire \gc0.count_d1_reg[10] ;
wire \gc0.count_d1_reg[10]_0 ;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gc0.count_reg[9] ;
wire \gcc0.gc0.count_d1_reg[10] ;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
wire out;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_empty_i_reg_1;
wire ram_empty_i_reg_2;
wire ram_empty_i_reg_3;
wire [4:0]v1_reg;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss \gwss.wsts
(.E(\gcc0.gc0.count_d1_reg[10] ),
.clk(clk),
.full(full),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10] ),
.\gc0.count_d1_reg[10]_0 (\gc0.count_d1_reg[10]_0 ),
.\grstd1.grst_full.grst_f.rst_d2_reg (\grstd1.grst_full.grst_f.rst_d2_reg ),
.out(out),
.ram_empty_fb_i_reg(E),
.v1_reg(\c0/v1_reg ),
.v1_reg_0(\c1/v1_reg ),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr wpntr
(.AR(AR),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.E(\gcc0.gc0.count_d1_reg[10] ),
.Q(Q),
.clk(clk),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gc0.count_reg[9] (\gc0.count_reg[9] ),
.ram_empty_i_reg(ram_empty_i_reg),
.ram_empty_i_reg_0(ram_empty_i_reg_0),
.ram_empty_i_reg_1(ram_empty_i_reg_1),
.ram_empty_i_reg_2(ram_empty_i_reg_2),
.ram_empty_i_reg_3(ram_empty_i_reg_3),
.v1_reg(v1_reg),
.v1_reg_0(\c0/v1_reg ),
.v1_reg_1(\c1/v1_reg ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
(out,
full,
E,
v1_reg,
\gc0.count_d1_reg[10] ,
v1_reg_0,
\gc0.count_d1_reg[10]_0 ,
clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
wr_en,
wr_rst_busy,
ram_empty_fb_i_reg);
output out;
output full;
output [0:0]E;
input [4:0]v1_reg;
input \gc0.count_d1_reg[10] ;
input [4:0]v1_reg_0;
input \gc0.count_d1_reg[10]_0 ;
input clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input wr_en;
input wr_rst_busy;
input [0:0]ram_empty_fb_i_reg;
wire [0:0]E;
wire clk;
wire comp1;
wire \gc0.count_d1_reg[10] ;
wire \gc0.count_d1_reg[10]_0 ;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
(* DONT_TOUCH *) wire ram_afull_fb;
(* DONT_TOUCH *) wire ram_afull_i;
wire [0:0]ram_empty_fb_i_reg;
wire ram_full_comb;
(* DONT_TOUCH *) wire ram_full_fb_i;
(* DONT_TOUCH *) wire ram_full_i;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_en;
wire wr_rst_busy;
assign full = ram_full_i;
assign out = ram_full_fb_i;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(ram_full_fb_i),
.O(E));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare c0
(.comp1(comp1),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10] ),
.out(ram_full_fb_i),
.ram_empty_fb_i_reg(ram_empty_fb_i_reg),
.ram_full_comb(ram_full_comb),
.v1_reg(v1_reg),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 c1
(.comp1(comp1),
.\gc0.count_d1_reg[10] (\gc0.count_d1_reg[10]_0 ),
.v1_reg_0(v1_reg_0));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b1),
.O(ram_afull_i));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b1),
.O(ram_afull_fb));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_i));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4B_4_V
`define SKY130_FD_SC_HDLL__NAND4B_4_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4b_4 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4b_4 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4B_4_V
|
// Copyright (C) 1991-2014 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////// Pipeline (Internal) for Formal Verification ////////////
//////////////////////////////////////////////////////////////////////////////////////////
// MODEL BEGIN
module pipeline_internal_fv (
// INTERFACE BEGIN
clk, // clock
ena, // clock enable
clr, // async clear
d, // data in
piped // output
);
// INTERFACE END
//// top level parameters ////
parameter data_width = 1;
parameter latency = 1;
//// port declarations ////
// data input ports
input [data_width - 1 : 0] d;
// control signals
input clk,ena,clr;
// output ports
output [data_width - 1 : 0] piped;
wire [data_width-1 : 0] out;
wire [data_width*(latency-1) : 1] t;
wire [data_width*latency-1 : 0] d_w;
assign piped = out;
//// nets/registers ////
// IMPLEMENTATION BEGIN
generate
if(latency==0) begin
assign out = d;
end
else if(latency==1) begin
assign d_w = ena? d : out;
dff_bus #(data_width) p (.q(out), .clk(clk), .d(d_w), .clr(clr));
end
else begin
assign d_w = ena? {t,d} : {out,t};
dff_bus #(data_width) p[1:latency] (.q({out,t}), .clk(clk), .d(d_w), .clr(clr));
end
endgenerate
// IMPLEMENTATION END
endmodule
// MODEL END
module dff_bus (q, clk, d, clr);
parameter data_width = 1;
input [data_width-1 : 0] d;
input clk, clr;
output [data_width-1 : 0] q;
generate
if(data_width==1) begin
dffep reg_prim_inst (q,clk,1'b1,d,1'b0,clr);
end
else begin
dffep reg_prim_inst[data_width-1:0] (q,clk,1'b1,d,1'b0,clr);
end
endgenerate
endmodule
|
`timescale 1 ns / 10 ps
module dpram (clock,
address_a, byteena_a, wrdata_a, wren_a, rddata_a,
address_b, byteena_b, wrdata_b, wren_b, rddata_b);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 7;
parameter INIT_FILE = "dummy"; // This is ignored right now
input clock;
input [ADDR_WIDTH-1:0] address_a;
input [DATA_WIDTH/8-1:0] byteena_a;
input [DATA_WIDTH-1:0] wrdata_a;
input wren_a;
output [DATA_WIDTH-1:0] rddata_a;
input [ADDR_WIDTH-1:0] address_b;
input [DATA_WIDTH-1:0] wrdata_b;
input [DATA_WIDTH/8-1:0] byteena_b;
input wren_b;
output [DATA_WIDTH-1:0] rddata_b;
dpram_simple s0(clock,
address_a, wrdata_a[ 7: 0], byteena_a[0] & wren_a, rddata_a[ 7: 0],
address_b, wrdata_b[ 7: 0], byteena_b[0] & wren_b, rddata_b[ 7: 0]);
defparam s0.DATA_WIDTH = DATA_WIDTH / 4,
s0.DATA_WIDTH = DATA_WIDTH;
dpram_simple s1(clock,
address_a, wrdata_a[15: 8], byteena_a[1] & wren_a, rddata_a[15: 8],
address_b, wrdata_b[15: 8], byteena_b[1] & wren_b, rddata_b[15: 8]);
defparam s1.DATA_WIDTH = DATA_WIDTH / 4,
s1.DATA_WIDTH = DATA_WIDTH;
dpram_simple s2(clock,
address_a, wrdata_a[23:16], byteena_a[2] & wren_a, rddata_a[23:16],
address_b, wrdata_b[23:16], byteena_b[2] & wren_b, rddata_b[23:16]);
defparam s2.DATA_WIDTH = DATA_WIDTH / 4,
s2.DATA_WIDTH = DATA_WIDTH;
dpram_simple s3(clock,
address_a, wrdata_a[31:24], byteena_a[3] & wren_a, rddata_a[31:24],
address_b, wrdata_b[31:24], byteena_b[3] & wren_b, rddata_b[31:24]);
defparam s3.DATA_WIDTH = DATA_WIDTH / 4,
s3.DATA_WIDTH = DATA_WIDTH;
endmodule
|
`timescale 1ns / 1ps
module Convierte(
input [3:0]Ver,
output reg [6:0]Salida7seg
);
always @(Ver)begin
case(Ver)
// abc_defg
7'b0000000: Salida7seg=7'b000_0001;//0
7'b0000001: Salida7seg=7'b100_1111;//1
7'b0000010: Salida7seg=7'b001_0010;//2
7'b0000011: Salida7seg=7'b000_0110;//3
7'b0000100: Salida7seg=7'b100_1100;//4
7'b0000101: Salida7seg=7'b010_0100;//5
7'b0000110: Salida7seg=7'b010_0000;//6
7'b0000111: Salida7seg=7'b000_1111;//7
7'b0001000: Salida7seg=7'b000_0000;//8
7'b0001001: Salida7seg=7'b000_0100;//9
7'b0001010: Salida7seg=7'b000_1000;//A
7'b0001011: Salida7seg=7'b110_0000;//b
7'b0001100: Salida7seg=7'b011_0001;//C
7'b0001101: Salida7seg=7'b100_0010;//d
7'b0001110: Salida7seg=7'b011_0000;//E
7'b0001111: Salida7seg=7'b011_1000;//F
/*
8'h15: Salida7seg=7'b000_1100;//q
8'h1D: Salida7seg=7'b100_0000;//w
8'h24: Salida7seg=7'b011_0000;//E
8'h2D: Salida7seg=7'b111_1010;//r
8'h2C: Salida7seg=7'b111_0000;//t
8'h35: Salida7seg=7'b100_0100;//Y
8'h3C: Salida7seg=7'b110_0011;//u
8'h43: Salida7seg=7'b100_1111;//i
8'h44: Salida7seg=7'b110_0010;//O
8'h4D: Salida7seg=7'b001_1000;//P
8'h1C: Salida7seg=7'b000_1000;//A
8'h1B: Salida7seg=7'b010_0100;//S
8'h23: Salida7seg=7'b100_0010;//d
8'h2B: Salida7seg=7'b011_1000;//F
8'h34: Salida7seg=7'b010_0001;//G
8'h33: Salida7seg=7'b110_1000;//h
8'h3B: Salida7seg=7'b100_0011;//J
8'h42: Salida7seg=7'b010_1000;//K
8'h4B: Salida7seg=7'b111_0000;//L
8'h4C: Salida7seg=7'b010_1010;//ñ
8'h1A: Salida7seg=7'b001_0011;//Z
8'h22: Salida7seg=7'b100_1000;//X
8'h21: Salida7seg=7'b111_0010;//C
8'h2A: Salida7seg=7'b100_0001;//V
8'h32: Salida7seg=7'b110_0000;//b
8'h31: Salida7seg=7'b110_1010;//n
8'h3A: Salida7seg=7'b000_1001;//M
*/
default : Salida7seg=7'b000_0001;//0
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A311O_BEHAVIORAL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire B1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_BEHAVIORAL_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Store Buffer FIFO ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Implementation of store buffer FIFO. ////
//// ////
//// To Do: ////
//// - N/A ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_sb_fifo.v,v $
// Revision 1.3 2002/11/06 13:53:41 simons
// SB mem width fixed.
//
// Revision 1.2 2002/08/22 02:18:55 lampret
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
//
// Revision 1.1 2002/08/18 19:53:08 lampret
// Added store buffer.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_sb_fifo(
clk_i, rst_i, dat_i, wr_i, rd_i, dat_o, full_o, empty_o
);
parameter dw = 68;
parameter fw = `OR1200_SB_LOG;
parameter fl = `OR1200_SB_ENTRIES;
//
// FIFO signals
//
input clk_i; // Clock
input rst_i; // Reset
input [dw-1:0] dat_i; // Input data bus
input wr_i; // Write request
input rd_i; // Read request
output [dw-1:0] dat_o; // Output data bus
output full_o; // FIFO full
output empty_o;// FIFO empty
//
// Internal regs
//
reg [dw-1:0] mem [fl-1:0];
reg [dw-1:0] dat_o;
reg [fw+1:0] cntr;
reg [fw-1:0] wr_pntr;
reg [fw-1:0] rd_pntr;
reg empty_o;
reg full_o;
always @(posedge clk_i or posedge rst_i)
if (rst_i) begin
full_o <= #1 1'b0;
empty_o <= #1 1'b1;
wr_pntr <= #1 {fw{1'b0}};
rd_pntr <= #1 {fw{1'b0}};
cntr <= #1 {fw+2{1'b0}};
dat_o <= #1 {dw{1'b0}};
end
else if (wr_i && rd_i) begin // FIFO Read and Write
mem[wr_pntr] <= #1 dat_i;
if (wr_pntr >= fl-1)
wr_pntr <= #1 {fw{1'b0}};
else
wr_pntr <= #1 wr_pntr + 1'b1;
if (empty_o) begin
dat_o <= #1 dat_i;
end
else begin
dat_o <= #1 mem[rd_pntr];
end
if (rd_pntr >= fl-1)
rd_pntr <= #1 {fw{1'b0}};
else
rd_pntr <= #1 rd_pntr + 1'b1;
end
else if (wr_i && !full_o) begin // FIFO Write
mem[wr_pntr] <= #1 dat_i;
cntr <= #1 cntr + 1'b1;
empty_o <= #1 1'b0;
if (cntr >= (fl-1)) begin
full_o <= #1 1'b1;
cntr <= #1 fl;
end
if (wr_pntr >= fl-1)
wr_pntr <= #1 {fw{1'b0}};
else
wr_pntr <= #1 wr_pntr + 1'b1;
end
else if (rd_i && !empty_o) begin // FIFO Read
dat_o <= #1 mem[rd_pntr];
cntr <= #1 cntr - 1'b1;
full_o <= #1 1'b0;
if (cntr <= 1) begin
empty_o <= #1 1'b1;
cntr <= #1 {fw+2{1'b0}};
end
if (rd_pntr >= fl-1)
rd_pntr <= #1 {fw{1'b0}};
else
rd_pntr <= #1 rd_pntr + 1'b1;
end
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Inverse_Clarke_Transform.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Inverse_Clarke_Transform
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Transform_dq_to_ABC/Inverse_Clarke_Transform
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Inverse_Clarke_Transform
(
alpha_voltage,
beta_voltage,
phase_voltages_0,
phase_voltages_1,
phase_voltages_2
);
input signed [17:0] alpha_voltage; // sfix18_En10
input signed [17:0] beta_voltage; // sfix18_En10
output signed [17:0] phase_voltages_0; // sfix18_En13
output signed [17:0] phase_voltages_1; // sfix18_En13
output signed [17:0] phase_voltages_2; // sfix18_En13
wire signed [35:0] voltage_phase_a; // sfix36_En26
wire signed [35:0] Gain1_out1; // sfix36_En26
wire signed [35:0] Gain_out1; // sfix36_En26
wire signed [35:0] voltage_phase_b; // sfix36_En26
wire signed [37:0] Add1_cast; // sfix38_En26
wire signed [37:0] Add1_cast_1; // sfix38_En26
wire signed [37:0] Add1_sub_cast; // sfix38_En26
wire signed [37:0] Add1_sub_temp; // sfix38_En26
wire signed [35:0] voltage_phase_c; // sfix36_En26
wire signed [35:0] Mux_out1 [0:2]; // sfix36_En26 [3]
wire signed [17:0] Current_Data_Type_out1 [0:2]; // sfix18_En13 [3]
// Inverse Clarke Transform
//
// Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities
// The alpha and beta components are dependent on time and speed.
// <S39>/Data Type Conversion
assign voltage_phase_a = {{2{alpha_voltage[17]}}, {alpha_voltage, 16'b0000000000000000}};
// <S39>/Gain1
assign Gain1_out1 = 56756 * beta_voltage;
// <S39>/Gain
assign Gain_out1 = {{3{alpha_voltage[17]}}, {alpha_voltage, 15'b000000000000000}};
// <S39>/Add
assign voltage_phase_b = Gain1_out1 - Gain_out1;
// <S39>/Add1
assign Add1_cast = Gain_out1;
assign Add1_cast_1 = - (Add1_cast);
assign Add1_sub_cast = Gain1_out1;
assign Add1_sub_temp = Add1_cast_1 - Add1_sub_cast;
assign voltage_phase_c = Add1_sub_temp[35:0];
// <S39>/Mux
assign Mux_out1[0] = voltage_phase_a;
assign Mux_out1[1] = voltage_phase_b;
assign Mux_out1[2] = voltage_phase_c;
// <S39>/Current_Data_Type
assign Current_Data_Type_out1[0] = ((Mux_out1[0][35] == 1'b0) && (Mux_out1[0][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[0][35] == 1'b1) && (Mux_out1[0][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[0][30:13])));
assign Current_Data_Type_out1[1] = ((Mux_out1[1][35] == 1'b0) && (Mux_out1[1][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[1][35] == 1'b1) && (Mux_out1[1][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[1][30:13])));
assign Current_Data_Type_out1[2] = ((Mux_out1[2][35] == 1'b0) && (Mux_out1[2][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[2][35] == 1'b1) && (Mux_out1[2][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[2][30:13])));
assign phase_voltages_0 = Current_Data_Type_out1[0];
assign phase_voltages_1 = Current_Data_Type_out1[1];
assign phase_voltages_2 = Current_Data_Type_out1[2];
endmodule // controllerHdl_Inverse_Clarke_Transform
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFBUF_PP_SYMBOL_V
`define SKY130_FD_SC_MS__BUFBUF_PP_SYMBOL_V
/**
* bufbuf: Double buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__bufbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFBUF_PP_SYMBOL_V
|
module ADT7310 (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output CpuIntr_o,
(* intersynth_port="Outputs_o", intersynth_conntype="Bit" *)
output ADT7310CS_n_o,
(* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *)
input[7:0] SPI_Data_i,
(* intersynth_port="SPI_Write", intersynth_conntype="Bit" *)
output SPI_Write_o,
(* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *)
output SPI_ReadNext_o,
(* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *)
output[7:0] SPI_Data_o,
(* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *)
input SPI_FIFOFull_i,
(* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *)
input SPI_FIFOEmpty_i,
(* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *)
input SPI_Transmission_i,
(* intersynth_param="SPICounterPresetH_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPresetH_i,
(* intersynth_param="SPICounterPresetL_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPresetL_i,
(* intersynth_param="Threshold_i", intersynth_conntype="Word" *)
input[15:0] Threshold_i,
(* intersynth_param="PeriodCounterPreset_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_param="SensorValue_o", intersynth_conntype="Word" *)
output[15:0] SensorValue_o,
(* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *)
output SPI_CPOL_o,
(* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *)
output SPI_CPHA_o,
(* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *)
output SPI_LSBFE_o
);
/* constant value for dynamic signal */
assign SPI_CPOL_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_CPHA_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_LSBFE_o = 1'b0;
(* keep *)
wire SPIFSM_Start_s;
(* keep *)
wire SPIFSM_Done_s;
(* keep *)
wire [7:0] SPIFSM_Byte0_s;
(* keep *)
wire [7:0] SPIFSM_Byte1_s;
SPIFSM #(
.SPPRWidth (4),
.SPRWidth (4),
.DataWidth (8)
) SPIFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
// FSM control
.Start_i (SPIFSM_Start_s),
.Done_o (SPIFSM_Done_s),
.Byte0_o (SPIFSM_Byte0_s),
.Byte1_o (SPIFSM_Byte1_s),
// to/from SPI_Master
.SPI_Transmission_i (SPI_Transmission_i),
.SPI_Write_o (SPI_Write_o),
.SPI_ReadNext_o (SPI_ReadNext_o),
.SPI_Data_o (SPI_Data_o),
.SPI_Data_i (SPI_Data_i),
.SPI_FIFOFull_i (SPI_FIFOFull_i),
.SPI_FIFOEmpty_i (SPI_FIFOEmpty_i),
// to ADT7310
.ADT7310CS_n_o (ADT7310CS_n_o),
// parameters
.ParamCounterPreset_i({SPICounterPresetH_i, SPICounterPresetL_i})
);
SensorFSM #(
.DataWidth (8)
) SensorFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.Enable_i (Enable_i),
.CpuIntr_o (CpuIntr_o),
.SensorValue_o (SensorValue_o),
.MeasureFSM_Start_o (SPIFSM_Start_s),
.MeasureFSM_Done_i (SPIFSM_Done_s),
.MeasureFSM_Byte0_i (SPIFSM_Byte0_s),
.MeasureFSM_Byte1_i (SPIFSM_Byte1_s),
// parameters
.ParamThreshold_i (Threshold_i),
.ParamCounterPreset_i(PeriodCounterPreset_i)
);
endmodule
|
/*
* Copyright 2010, Aleksander Osman, [email protected]. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module timer(
input CLK_I,
input RST_I,
input [31:2] ADR_I,
input CYC_I,
input STB_I,
input WE_I,
output reg RTY_O,
output reg interrupt_o
);
reg [27:0] counter;
always @(posedge CLK_I) begin
if(RST_I == 1'b1) begin
RTY_O <= 1'b0;
interrupt_o <= 1'b0;
counter <= 28'd0;
end
else if(counter == 28'h00FFFFF) begin
if(ADR_I == { 27'b1111_1111_1111_1111_1111_1111_111, 3'b001 } && CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b0 && interrupt_o == 1'b1) begin
RTY_O <= 1'b1;
interrupt_o <= 1'b0;
counter <= 28'd0;
end
else begin
interrupt_o <= 1'b1;
end
end
else begin
RTY_O <= 1'b0;
counter <= counter + 28'd1;
end
end
endmodule
|
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "spl_defines.vh"
`include "framework_defines.vh"
module server_io(
input wire clk,
input wire rst_n,
///////////////////////////////////// CCI Interface /////////////////////////////////////
// CCI TX read request
input wire cci_tx_rd_almostfull,
output reg spl_tx_rd_valid,
output reg [60:0] spl_tx_rd_hdr,
// CCI TX write request
input wire cci_tx_wr_almostfull,
output reg spl_tx_wr_valid,
output wire spl_tx_intr_valid,
output reg [60:0] spl_tx_wr_hdr,
output reg [511:0] spl_tx_data,
// CCI RX read response
input wire cci_rx_rd_valid,
input wire cci_rx_wr_valid0,
input wire cci_rx_cfg_valid,
input wire cci_rx_intr_valid0,
input wire cci_rx_umsg_valid,
input wire [`CCI_RX_HDR_WIDTH-1:0] cci_rx_hdr0,
input wire [511:0] cci_rx_data,
// CCI RX write response
input wire cci_rx_wr_valid1,
input wire cci_rx_intr_valid1,
input wire [`CCI_RX_HDR_WIDTH-1:0] cci_rx_hdr1,
//////////////////////////////// Server components Interfaces /////////////////////////////
// server_io <--> cmd_server: RX_RD
output reg io_rx_csr_valid,
output reg [13:0] io_rx_csr_addr,
output reg [31:0] io_rx_csr_data,
// server_io <--> cmd_server: TX_WR
output wire fc_tx_wr_ready,
input wire fc_tx_wr_valid,
input wire [31:0] fc_tx_wr_addr,
input wire [`FPGA_CORE_TAG-1:0] fc_tx_wr_tag,
input wire [511:0] fc_tx_data,
// server_io <--> cmd server: TX_RD
output wire fc_tx_rd_ready,
input wire fc_tx_rd_valid,
input wire [31:0] fc_tx_rd_addr,
input wire [`FPGA_CORE_TAG-1:0] fc_tx_rd_tag,
// server_io <--> cmd server: RX_WR
output reg fc_rx_wr_valid,
output reg [`FPGA_CORE_TAG-1:0] fc_rx_wr_tag,
// server_io <--> cmd server: RX_RD
output reg fc_rx_rd_valid,
output reg [`FPGA_CORE_TAG-1:0] fc_rx_rd_tag,
output reg [511:0] fc_rx_data,
// server_io <--> io_requester: TX_WR
output wire rq_tx_wr_ready,
input wire rq_tx_wr_valid,
input wire [48:0] rq_tx_wr_hdr,
input wire [511:0] rq_tx_data,
// server_io <--> io_requester: TX_RD
output wire rq_tx_rd_ready,
input wire rq_tx_rd_valid,
input wire [44:0] rq_tx_rd_hdr,
// server_io <--> arbiter: RX_RD
output reg io_rx_rd_valid,
output reg [511:0] io_rx_data,
output reg [12:0] io_rx_rd_tag,
// server_io <--> arbiter: RX_WR
output reg io_rx_wr_valid,
output reg [12:0] io_rx_wr_tag
);
wire wr_rp_buf_empty;
wire wr_rp_buf_valid;
wire [`CCI_RX_HDR_WIDTH-1:0] wr_rp_buf_hdr;
wire [`CCI_RX_HDR_WIDTH-1:0] wr_rp_hdr;
wire wr_rp_valid;
wire [8:0] wr_rp_buf_count;
wire [3:0] cci_tx_wr_cmd;
wire [31:0] cci_tx_wr_addr;
wire [511:0] cci_tx_data;
wire [13:0] cci_tx_wr_tag;
wire [31:0] cci_tx_rd_addr;
wire [13:0] cci_tx_rd_tag;
wire tx_wr_fifo_valid;
wire [511:0] tx_wr_fifo_data;
wire [60:0] tx_wr_fifo_hdr;
wire tx_wr_fifo_full;
wire [4:0] tx_wr_fifo_count;
wire tx_rd_fifo_valid;
wire [60:0] tx_rd_fifo_hdr;
wire tx_rd_fifo_full;
reg [31:0] idle_read_cycles;
reg [31:0] idle_write_cycles;
reg [31:0] idle_rw_cycles;
//////
always @(posedge clk) begin
if(~rst_n) begin
idle_read_cycles <= 0;
idle_write_cycles <= 0;
idle_rw_cycles <= 0;
end
else begin
if( ~cci_tx_wr_almostfull & ~spl_tx_wr_valid)
idle_write_cycles <= idle_write_cycles + 1'b1;
if( ~cci_tx_rd_almostfull & ~spl_tx_rd_valid)
idle_read_cycles <= idle_read_cycles + 1'b1;
if( ~cci_tx_wr_almostfull & ~spl_tx_wr_valid & ~cci_tx_rd_almostfull & ~spl_tx_rd_valid)
idle_rw_cycles <= idle_rw_cycles + 1'b1;
end
end
///////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// ///////////////////////////////////////
///////////////////////////// TX WR Driver ////////////////////////////////////
///////////////////////////////// ///////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// TW WR is used by cmd server and io_requester
// toward cci
assign cci_tx_wr_cmd = (fc_tx_wr_valid)?`CCI_REQ_WR_THRU : rq_tx_wr_hdr[48:45];
assign cci_tx_wr_addr = (fc_tx_wr_valid)?fc_tx_wr_addr : rq_tx_wr_hdr[44:13];
assign cci_tx_data = (fc_tx_wr_valid)?fc_tx_data : rq_tx_data;
assign cci_tx_wr_tag = (fc_tx_wr_valid)?{1'b0, {{`QPI_TAG-`FPGA_CORE_TAG-1}{1'b0}}, fc_tx_wr_tag} :
{1'b1, rq_tx_wr_hdr[12:0]};
assign spl_tx_intr_valid = 1'b0;
always @(posedge clk) begin
if(~rst_n) begin
spl_tx_wr_valid <= 0;
spl_tx_wr_hdr <= 0;
//spl_tx_data <= 0;
end
else if(~cci_tx_wr_almostfull) begin
spl_tx_wr_valid <= tx_wr_fifo_valid;
spl_tx_wr_hdr <= tx_wr_fifo_hdr;
spl_tx_data <= tx_wr_fifo_data;
end
else spl_tx_wr_valid <= 1'b0;
end
// toward cci TX WR users: i.e. cmd_server, io_requester
assign rq_tx_wr_ready = (fc_tx_wr_valid)? 1'b0 : ~tx_wr_fifo_full;
assign fc_tx_wr_ready = ~tx_wr_fifo_full;
quick_fifo #(.FIFO_WIDTH(512 + 61),
.FIFO_DEPTH_BITS(5),
.FIFO_ALMOSTFULL_THRESHOLD(2**5 - 8)
) tx_wr_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({5'b0, cci_tx_wr_cmd, 6'b0, cci_tx_wr_addr, cci_tx_wr_tag, cci_tx_data}),
.we ((fc_tx_wr_valid | rq_tx_wr_valid)),
.re (~cci_tx_wr_almostfull),
.dout ({tx_wr_fifo_hdr, tx_wr_fifo_data}),
.empty (),
.valid (tx_wr_fifo_valid),
.full (tx_wr_fifo_full),
.count (tx_wr_fifo_count),
.almostfull ()
);
///////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// ///////////////////////////////////////
///////////////////////////// TX RD Driver ////////////////////////////////////
///////////////////////////////// ///////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// TX RD is used by the io_requester and the fpga core
// toward cci
assign cci_tx_rd_addr = (fc_tx_rd_valid)? fc_tx_rd_addr : rq_tx_rd_hdr[44:13];
assign cci_tx_rd_tag = (fc_tx_rd_valid)? {1'b0, {{`QPI_TAG-`FPGA_CORE_TAG-1}{1'b0}}, fc_tx_rd_tag} :
{1'b1, rq_tx_rd_hdr[12:0]};
always @(posedge clk) begin
if(~rst_n) begin
spl_tx_rd_valid <= 0;
spl_tx_rd_hdr <= 0;
end
else if(~cci_tx_rd_almostfull) begin
spl_tx_rd_valid <= tx_rd_fifo_valid;
spl_tx_rd_hdr <= tx_rd_fifo_hdr;
end
else spl_tx_rd_valid <= 0;
end
// toward cci TX RD users: i.e. cmd_server, io_requester
assign rq_tx_rd_ready = (fc_tx_rd_valid)? 1'b0 : ~tx_rd_fifo_full;
assign fc_tx_rd_ready = ~tx_rd_fifo_full;
quick_fifo #(.FIFO_WIDTH(61),
.FIFO_DEPTH_BITS(5),
.FIFO_ALMOSTFULL_THRESHOLD(2**5 - 8)
) tx_rd_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({5'b0, `CCI_REQ_RD, 6'b0, cci_tx_rd_addr, cci_tx_rd_tag}),
.we ((rq_tx_rd_valid | fc_tx_rd_valid)),
.re (~cci_tx_rd_almostfull),
.dout (tx_rd_fifo_hdr),
.empty (),
.valid (tx_rd_fifo_valid),
.full (tx_rd_fifo_full),
.count (),
.almostfull ()
);
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// /////////////////////////////////////////////////
////////////////////////////////////////// RX RD Distributor //////////////////////////////////////////////
///////////////////////////////////////////// /////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// RX RD is used by cmd_server, arbiter, and page table
always @(posedge clk) begin
if(~rst_n) begin
io_rx_csr_valid <= 0;
io_rx_csr_addr <= 0;
io_rx_csr_data <= 0;
//
io_rx_rd_valid <= 0;
io_rx_rd_tag <= 0;
//io_rx_data <= 0;
//
//fc_rx_data <= 512'b0;
fc_rx_rd_tag <= 0;
fc_rx_rd_valid <= 1'b0;
end
else begin
//
io_rx_csr_valid <= cci_rx_cfg_valid;
io_rx_csr_addr <= cci_rx_hdr0[13:0];
io_rx_csr_data <= cci_rx_data[31:0];
//
io_rx_rd_valid <= cci_rx_rd_valid & cci_rx_hdr0[13];
io_rx_rd_tag <= cci_rx_hdr0[12:0];
io_rx_data <= cci_rx_data;
//
fc_rx_data <= cci_rx_data;
fc_rx_rd_tag <= cci_rx_hdr0[`FPGA_CORE_TAG-1:0];
fc_rx_rd_valid <= cci_rx_rd_valid & ~cci_rx_hdr0[13];
end
end
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// /////////////////////////////////////////////////
////////////////////////////////////////// RX WR Distributor //////////////////////////////////////////////
///////////////////////////////////////////// /////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// regulate RX WR multiple responses
quick_fifo #(.FIFO_WIDTH(`CCI_RX_HDR_WIDTH),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD(8)
) wr_rp_buf(
.clk (clk),
.reset_n (rst_n),
.din (cci_rx_hdr0),
.we (cci_rx_wr_valid1 & cci_rx_wr_valid0),
.re ( ~(cci_rx_wr_valid1 | cci_rx_wr_valid0) & wr_rp_buf_valid ),
.dout (wr_rp_buf_hdr),
.empty (wr_rp_buf_empty),
.valid (wr_rp_buf_valid),
.full (),
.count (wr_rp_buf_count),
.almostfull ()
);
//
assign wr_rp_valid = cci_rx_wr_valid1 | cci_rx_wr_valid0 | wr_rp_buf_valid;
assign wr_rp_hdr = (cci_rx_wr_valid1)? cci_rx_hdr1 : ((cci_rx_wr_valid0)? cci_rx_hdr0 : wr_rp_buf_hdr);
// SOME DEBUG COUNTERS
reg [39:0] rx_wr_resp_ch1;
reg [39:0] rx_wr_resp_ch0;
reg [39:0] rx_wr_resp_tot;
reg [39:0] tx_wr_req_tot;
always @(posedge clk) begin
if(~rst_n) begin
rx_wr_resp_ch1 <= 0;
rx_wr_resp_ch0 <= 0;
rx_wr_resp_tot <= 0;
tx_wr_req_tot <= 0;
end else begin
rx_wr_resp_ch1 <= (cci_rx_wr_valid1)? rx_wr_resp_ch1 + 1'b1 : rx_wr_resp_ch1;
rx_wr_resp_ch0 <= (cci_rx_wr_valid0)? rx_wr_resp_ch0 + 1'b1 : rx_wr_resp_ch0;
rx_wr_resp_tot <= (wr_rp_valid)? rx_wr_resp_tot + 1'b1 : rx_wr_resp_tot;
tx_wr_req_tot <= (spl_tx_wr_valid)? tx_wr_req_tot + 1'b1 : tx_wr_req_tot;
end
end
// RX WR is used by arbiter and cmd_server
always @(posedge clk) begin
if(~rst_n) begin
//
fc_rx_wr_tag <= 0;
fc_rx_wr_valid <= 1'b0;
io_rx_wr_valid <= 1'b0;
io_rx_wr_tag <= 0;
end
else begin
fc_rx_wr_tag <= wr_rp_hdr[`FPGA_CORE_TAG-1:0];
fc_rx_wr_valid <= wr_rp_valid & ~wr_rp_hdr[13];
io_rx_wr_valid <= wr_rp_valid & wr_rp_hdr[13];
io_rx_wr_tag <= wr_rp_hdr[12:0];
end
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: CHARMAP.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module CHARMAP (
address,
clock,
q);
input [8:0] address;
input clock;
output [17:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../charmap/charmap.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
// Retrieval info: PRIVATE: WidthData NUMERIC "18"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../charmap/charmap.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// agnus_bitplanes_tb.v
// 2014, [email protected]
`default_nettype none
`timescale 1ns/10ps
`define CLK_HP 17.857
module agnus_bitplanes_tb();
// system regs
reg CLK28;
reg RST;
// clock & reset
initial begin
RST = 1;
CLK28 = 1;
forever #`CLK_HP CLK28 = ~CLK28;
end
reg [ 2-1:0] CLK7_CNT = 2'b10;
reg CLK7_EN = 1'b1;
always @ (posedge CLK28) begin
if (RST)
CLK7_CNT <= #1 2'd2;
CLK7_EN <= #1 1'b1;
else
CLK7_CNT <= #1 CLK7_CNT + 2'b01;
CLK7_EN <= #1 CLK7_CNT == 2'b00;
end
// counter used to generate e clock enable
reg [ 4-1:0] E_CNT = 0;
always @(posedge CLK28) begin
if (CLK7_EN) begin
if (E_CNT[3] && E_CNT[0])
E_CNT[3:0] <= 4'd0;
else
E_CNT[3:0] <= E_CNT[3:0] + 4'd1;
end
end
// CCK clock output
assign CCK = ~E_CNT[0];
// module regs
reg ntsc = 0;
reg a1k = 0;
reg ecs = 0;
reg aga = 0;
reg [ 9-1:1] rga_adr = 0;
reg [16-1:0] rga_dat_w = 0;
wire [ 9-1:0] hpos;
wire [11-1:0] vpos;
wire _hsync;
wire _vsync;
wire _csync;
wire blank;
wire vbl;
wire vblend;
wire eol;
wire eof;
wire vbl_int;
wire [ 9-1:1] htotal;
reg dma_bpl_ena = 0;
wire dma_bpl;
wire [ 9-1:1] bpl_rga_adr;
wire [21-1:1] bpl_adr;
// testbench
initial begin
// bench start
$display("BENCH : start");
repeat(8) @ posedge CLK28;
// default settings
repeat (4) @ (posedge CLK28);
RST = 0;
// TODO
// test 1 bpl
// TODO
end
// reg write task
task reg_wr;
input [9:0] adr;
input [15:0] dat;
begin
wait (!CLK7_EN);
@ (posedge CLK28);
rga_adr = adr;
rga_dat = dat;
wait(CLK7_EN);
@ (posedge CLK28);
rga_adr = 0;
rga_dat = 0;
end
endtask
// agnus_beamcounter
agnus_beamcounter beamcounter (
.clk (CLK28),
.clk7_en (CLK7_EN),
.reset (RST),
.cck (CCK),
.ntsc (ntsc),
.aga (aga),
.ecs (ecs),
.a1k (a1k),
.data_in (rga_dat_w),
.data_out (),
.reg_address_in (rga_adr),
.hpos (hpos),
.vpos (vpos),
._hsync (_hsync),
._vsync (_vsync),
._csync (_csync),
.blank (blank),
.vbl (vbl),
.vblend (vblend),
.eol (sol),
.eof (sof),
.vbl_int (vbl_int),
.htotal (htotal)
);
// agnus_bitplanedma
agnus_bitplanedma bitplanedma (
.clk (CLK28),
.clk7_en (CLK7_EN),
.reset (RST),
.aga (aga),
.ecs (ecs),
.a1k (a1k),
.sof (sof),
.dmaena (dma_bpl_ena),
.vpos (vpos),
.hpos (hpos),
.dma (dma_bpl),
.reg_address_in (rga_adr),
.reg_address_out(bpl_rga_adr),
.data_in (rga_dat_W),
.address_out (bpl_adr)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXTP_BLACKBOX_V
`define SKY130_FD_SC_HD__DFXTP_BLACKBOX_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfxtp (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXTP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVKAPWR_FUNCTIONAL_V
`define SKY130_FD_SC_LP__INVKAPWR_FUNCTIONAL_V
/**
* invkapwr: Inverter on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__invkapwr (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVKAPWR_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_SYMBOL_V
`define SKY130_FD_SC_LP__NAND2B_SYMBOL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_SYMBOL_V
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Generic ODDR module
*/
module oddr #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire clk,
input wire [WIDTH-1:0] d1,
input wire [WIDTH-1:0] d2,
output wire [WIDTH-1:0] q
);
/*
Provides a consistent output DDR flip flop across multiple FPGA families
_____ _____ _____ _____
clk ____/ \_____/ \_____/ \_____/ \_____
_ ___________ ___________ ___________ ___________ __
d1 _X____D0_____X____D2_____X____D4_____X____D6_____X__
_ ___________ ___________ ___________ ___________ __
d2 _X____D1_____X____D3_____X____D5_____X____D7_____X__
_____ _____ _____ _____ _____ _____ _____ _____ ____
d _____X_D0__X_D1__X_D2__X_D3__X_D4__X_D5__X_D6__X_D7_
*/
genvar n;
generate
if (TARGET == "XILINX") begin
for (n = 0; n < WIDTH; n = n + 1) begin : oddr
if (IODDR_STYLE == "IODDR") begin
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.SRTYPE("ASYNC")
)
oddr_inst (
.Q(q[n]),
.C(clk),
.CE(1'b1),
.D1(d1[n]),
.D2(d2[n]),
.R(1'b0),
.S(1'b0)
);
end else if (IODDR_STYLE == "IODDR2") begin
ODDR2 #(
.DDR_ALIGNMENT("C0"),
.SRTYPE("ASYNC")
)
oddr_inst (
.Q(q[n]),
.C0(clk),
.C1(~clk),
.CE(1'b1),
.D0(d1[n]),
.D1(d2[n]),
.R(1'b0),
.S(1'b0)
);
end
end
end else if (TARGET == "ALTERA") begin
altddio_out #(
.WIDTH(WIDTH),
.POWER_UP_HIGH("OFF"),
.OE_REG("UNUSED")
)
altddio_out_inst (
.aset(1'b0),
.datain_h(d1),
.datain_l(d2),
.outclocken(1'b1),
.outclock(clk),
.aclr(1'b0),
.dataout(q)
);
end else begin
reg [WIDTH-1:0] d_reg_1 = {WIDTH{1'b0}};
reg [WIDTH-1:0] d_reg_2 = {WIDTH{1'b0}};
reg [WIDTH-1:0] q_reg = {WIDTH{1'b0}};
always @(posedge clk) begin
d_reg_1 <= d1;
d_reg_2 <= d2;
end
always @(posedge clk) begin
q_reg <= d1;
end
always @(negedge clk) begin
q_reg <= d_reg_2;
end
assign q = q_reg;
end
endgenerate
endmodule
|
`include "REG.v"
`include "CMD.v"
`include "BloqueDATA.v"
`include "modules/DMA.v"
module SD_host (clk_host,
reset_host,
io_enable_cmd,
CMD_PIN_IN,
CMD_PIN_OUT,
clk_SD,
data_in_register,
data_out_register,
req_register,
ack_register,
addres_register,
rw_register,
DATA_PIN_IN,
DATA_PIN_OUT,
IO_enable_Phy_SD_CARD,
pad_enable_Phy_PAD,
pad_state_Phy_PAD,
cmd_reg_write,
cmd_reg_read,
Continue,
descriptor_table,
TRAN,
STOP);
//señales del host
input wire clk_host, reset_host;
input wire DATA_PIN_IN;
output wire DATA_PIN_OUT;
output wire IO_enable_Phy_SD_CARD;
//outputs para el estado del PAD
output wire pad_enable_Phy_PAD;
output wire pad_state_Phy_PAD;
//señales del CMD
input wire CMD_PIN_IN;
output wire io_enable_cmd, CMD_PIN_OUT;
//señales del register
input wire [31:0]data_in_register;
output wire [31:0] data_out_register;
input wire req_register;
input wire ack_register;
input wire [4:0]addres_register;
input wire rw_register;
// señales de DMA
input wire cmd_reg_write;
input wire cmd_reg_read;
input wire Continue;
input wire [6:0][85:0] descriptor_table;
input wire TRAN;
input wire STOP;
//señales compartidas del SD
input wire clk_SD;
//cables de conexion entre DMA y CMD
wire new_command;
//cables de conexion entre REG y CMD
wire [31:0]cmd_argument;
wire [5:0]cmd_index;
wire [127:0]response;
wire cmd_complete, cmd_index_error;
assign cmd_argument = bloque_registers.Argument;
assign cmd_index = bloque_registers.cmd_index;
assign bloque_registers.cmd_complete = cmd_complete;
assign bloque_registers.cmd_index_error = cmd_index_error;
//wires entre REGS y DATA
wire [15:0] timeout_Reg_Regs_DATA;
wire writeRead_Regs_DATA;
wire [3:0] blockCount_Regs_DATA;
wire multipleData_Regs_DATA;
wire timeout_enable_Regs_DATA;
//wires entre DMA y DATA
wire transfer_complete_DATA_DMA;
assign timeout_Reg_Regs_DATA = bloque_registers.Timeout_Reg;
assign writeRead_Regs_DATA = bloque_registers.writeRead;
assign blockCount_Regs_DATA = bloque_registers.block_count;
assign multipleData_Regs_DATA = bloque_registers.multipleData;
assign timeout_enable_Regs_DATA = bloque_registers.timeout_enable;
// wire entre DMA y FIFO
wire FIFO_EMPTY_DMA;
wire FIFO_FULL_DMA;
wire [63:0] system_address;
wire writing_mem; // 1 if dir = 0 and TFC = 0
wire reading_mem; //
wire reading_fifo;
wire writing_fifo;
wire [5:0] next_descriptor_index;
reg [5:0] descriptor_index;
always @(posedge clk_host) begin
descriptor_index <= next_descriptor_index;
end
DMA bloqueDMA(reset,
clk_host,
transfer_complete_DATA_DMA,
cmd_reg_write,
cmd_reg_read,
Continue,
TRAN,
STOP,
FIFO_EMPTY_DMA,
FIFO_FULL_DMA,
descriptor_table [0][85:22], // data_address
descriptor_table [0][20:5], // length
descriptor_index,
descriptor_table [0][4], //act1
descriptor_table [0][3], //act2
descriptor_table [0][2], // END
descriptor_table [0][1], // valid
descriptor_table [0][0], // dir
new_command, // To CMD block
system_address,
writing_mem, // 1 if dir = 0 and TFC = 0
reading_mem, //
reading_fifo,
writing_fifo,
next_descriptor_index);
CMD bloque_CMD(clk_host, reset_host, new_command, cmd_argument, cmd_index, cmd_complete, cmd_index_error, response, CMD_PIN_OUT, IO_enable_pin, CMD_PIN_IN, clk_SD);
REG bloque_registers(clk_host, rw_register, addres_register, data_in_register, data_out_register);
//Bloque de DATA
BloqueDATA Data_Control(
.CLK(clk_host),
.SD_CLK(clk_SD),
.RESET_L(reset_host),
.timeout_Reg_Regs_DATA(timeout_Reg_Regs_DATA),
.writeRead_Regs_DATA(writeRead_Regs_DATA),
.blockCount_Regs_DATA(blockCount_Regs_DATA),
.multipleData_Regs_DATA(multipleData_Regs_DATA),
.timeout_enable_Regs_DATA(timeout_enable_Regs_DATA),
//.FIFO_OK_FIFO_DATA(),
//.[31:0] dataFromFIFO_FIFO_Phy(),
//.New_DAT_DMA_DATA(),
//.DATA_PIN_IN(DATA_PIN_IN),
//.writeFIFO_enable_Phy_FIFO(),
//.readFIFO_enable_Phy_FIFO(),
//.[31:0] dataReadToFIFO_Phy_FIFO(),
.transfer_complete_DATA_DMA(transfer_complete_DATA_DMA),
.IO_enable_Phy_SD_CARD(IO_enable_Phy_SD_CARD),
.DATA_PIN_OUT(DATA_PIN_OUT),
.pad_state_Phy_PAD(pad_state_Phy_PAD),
.pad_enable_Phy_PAD(pad_enable_Phy_PAD)
);
endmodule // SD_host
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__NAND3B_FUNCTIONAL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand3b (
Y ,
A_N,
B ,
C
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, B, not0_out, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3B_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DIODE_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DIODE_PP_SYMBOL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__diode (
//# {{power|Power}}
input DIODE,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DIODE_PP_SYMBOL_V
|
// 21 Jul 2021
// A special module for use with HardFloat's mulAddRecFN for
// easy absorption of pipeline stages by the DSPs that get
// synthesised in some FPGAs. This helps in retiming the
// paths in FPGA implementations as only immediate registers
// are absorbed, and global retiming does not seem to do this.
//
// For Zynq 7020, pipeline_p = 3
`include "bsg_defines.v"
module bsg_mul_add_unsigned #(
parameter `BSG_INV_PARAM(width_a_p)
,parameter `BSG_INV_PARAM(width_b_p)
,parameter width_c_p = width_a_p + width_b_p
,parameter width_o_p = `BSG_SAFE_CLOG2( ((1 << width_a_p) - 1) * ((1 << width_b_p) - 1) +
((1 << width_c_p)-1) + 1 )
,parameter pipeline_p = 0
) (
input clk_i
,input [width_a_p-1 : 0] a_i
,input [width_b_p-1 : 0] b_i
,input [width_c_p-1 : 0] c_i
,output [width_o_p-1 : 0] o
);
initial assert (pipeline_p > 2) else $warning ("%m: pipeline_p is set quite low; most likely frequency will be impacted")
localparam pre_pipeline_lp = pipeline_p > 2 ? 1 : 0;
localparam post_pipeline_lp = pipeline_p > 2 ? pipeline_p -1 : pipeline_p; //for excess
wire [width_a_p-1:0] a_r;
wire [width_b_p-1:0] b_r;
wire [width_c_p-1:0] c_r;
bsg_dff_chain #(width_a_p + width_b_p + width_c_p, pre_pipeline_lp)
pre_mul_add (
.clk_i(clk_i)
,.data_i({a_i, b_i, c_i})
,.data_o({a_r, b_r, c_r})
);
wire [width_o_p-1:0] o_r = a_r * b_r + c_r;
bsg_dff_chain #(width_o_p, post_pipeline_lp)
post_mul_add (
.clk_i(clk_i)
,.data_i(o_r)
,.data_o(o)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_mul_add_unsigned)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2_4_V
`define SKY130_FD_SC_HD__OR2_4_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2_4_V
|
`timescale 1ns / 1ps
module sign_inverter #(parameter W = 32)
(
input wire [W-1:0] data,
input wire [1:0] shift_region_flag,
input wire operation,
output reg [W-1:0] data_out
);
always@*
begin
if(operation == 1'b0)//coseno
begin
if(shift_region_flag == 2'b00 || shift_region_flag == 2'b11)//no hay desplazamiento
begin
data_out = data;
end
else
begin
if((shift_region_flag == 2'b01) && (data[W-1] == 1'b0))
begin
data_out = {1'b1,data[W-2:0]};
end
else if((shift_region_flag == 2'b01) && (data[W-1] == 1'b1))
begin
data_out = {1'b0,data[W-2:0]};
end
else
begin
data_out = data;
end
end
end
else //seno
begin
if(shift_region_flag == 2'b00 || shift_region_flag == 2'b11)//no hay desplazamiento
begin
data_out = data;
end
else
begin
if((shift_region_flag == 2'b10) && (data[W-1] == 1'b0))
begin
data_out = {1'b1,data[W-2:0]};
end
else if((shift_region_flag == 2'b10) && (data[W-1] == 1'b1))
begin
data_out = {1'b0,data[W-2:0]};
end
else
begin
data_out = data;
end
end
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Project Name: CoCo3FPGA Version 3.0
// File Name: sound.v
//
// CoCo3 in an FPGA
//
// Revision: 3.0 08/15/15
////////////////////////////////////////////////////////////////////////////////
//
// CPU section copyrighted by John Kent
// The FDC co-processor copyrighted Daniel Wallner.
//
////////////////////////////////////////////////////////////////////////////////
//
// Color Computer 3 compatible system on a chip
//
// Version : 3.0
//
// Copyright (c) 2008 Gary Becker ([email protected])
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://groups.yahoo.com/group/CoCo3FPGA
//
// File history :
//
// 1.0 Full Release
// 2.0 Partial Release
// 3.0 Full Release
////////////////////////////////////////////////////////////////////////////////
// Gary Becker
// [email protected]
////////////////////////////////////////////////////////////////////////////////
// Internal Sound generation
assign SOUND = {1'b0, SBS, SOUND_DTOA};
assign DAC_LEFT = {2'b00, ORCH_LEFT, ORCH_LEFT_EXT, 1'b0} + {2'b00, SOUND, 9'h000};
assign DAC_RIGHT = {2'b00, ORCH_RIGHT, ORCH_RIGHT_EXT, 1'b0} + {2'b00, SOUND, 9'h000};
assign AUD_XCK = CLK24MHZ_2;
//Delay LRCLK half cycle
always @(posedge AUD_BCLK)
begin
DACLRCLK <= AUD_DACLRCK;
ADCLRCLK <= AUD_ADCLRCK;
end
always @(negedge AUD_DACLRCK)
begin
LEFT <= DAC_LEFT;
RIGHT <= DAC_RIGHT;
end
always @(negedge AUD_BCLK or negedge RESET_N)
begin
if(!RESET_N)
DAC_STATE <= 6'h00;
else
case (DAC_STATE)
6'h00:
begin
if(!DACLRCLK)
begin
AUD_DACDAT <= LEFT[18];
DAC_STATE <= 6'h01;
end
end
6'h01:
begin
AUD_DACDAT <= LEFT[17];
DAC_STATE <= 6'h02;
end
6'h02:
begin
AUD_DACDAT <= LEFT[16];
DAC_STATE <= 6'h03;
end
6'h03:
begin
AUD_DACDAT <= LEFT[15];
DAC_STATE <= 6'h04;
end
6'h04:
begin
AUD_DACDAT <= LEFT[14];
DAC_STATE <= 6'h05;
end
6'h05:
begin
AUD_DACDAT <= LEFT[13];
DAC_STATE <= 6'h06;
end
6'h06:
begin
AUD_DACDAT <= LEFT[12];
DAC_STATE <= 6'h07;
end
6'h07:
begin
AUD_DACDAT <= LEFT[11];
DAC_STATE <= 6'h08;
end
6'h08:
begin
AUD_DACDAT <= LEFT[10];
DAC_STATE <= 6'h09;
end
6'h09:
begin
AUD_DACDAT <= LEFT[9];
DAC_STATE <= 6'h0A;
end
6'h0A:
begin
AUD_DACDAT <= LEFT[8];
DAC_STATE <= 6'h0B;
end
6'h0B:
begin
AUD_DACDAT <= LEFT[7];
DAC_STATE <= 6'h0C;
end
6'h0C:
begin
AUD_DACDAT <= LEFT[6];
DAC_STATE <= 6'h0D;
end
6'h0D:
begin
AUD_DACDAT <= LEFT[5];
DAC_STATE <= 6'h0E;
end
6'h0E:
begin
AUD_DACDAT <= LEFT[4];
DAC_STATE <= 6'h0F;
end
6'h0F:
begin
AUD_DACDAT <= LEFT[3];
DAC_STATE <= 6'h10;
end
6'h10:
begin
AUD_DACDAT <= LEFT[2];
DAC_STATE <= 6'h11;
end
6'h11:
begin
AUD_DACDAT <= LEFT[1];
DAC_STATE <= 6'h12;
end
6'h12:
begin
AUD_DACDAT <= LEFT[0];
DAC_STATE <= 6'h13;
end
6'h13:
begin
AUD_DACDAT <= 1'b0;
DAC_STATE <= 6'h14;
end
6'h14:
begin
if(DACLRCLK)
begin
AUD_DACDAT <= RIGHT[18];
DAC_STATE <= 6'h15;
end
end
6'h15:
begin
AUD_DACDAT <= RIGHT[17];
DAC_STATE <= 6'h16;
end
6'h16:
begin
AUD_DACDAT <= RIGHT[16];
DAC_STATE <= 6'h17;
end
6'h17:
begin
AUD_DACDAT <= RIGHT[15];
DAC_STATE <= 6'h18;
end
6'h18:
begin
AUD_DACDAT <= RIGHT[14];
DAC_STATE <= 6'h19;
end
6'h19:
begin
AUD_DACDAT <= RIGHT[13];
DAC_STATE <= 6'h1A;
end
6'h1A:
begin
AUD_DACDAT <= RIGHT[12];
DAC_STATE <= 6'h1B;
end
6'h1B:
begin
AUD_DACDAT <= RIGHT[11];
DAC_STATE <= 6'h1C;
end
6'h1C:
begin
AUD_DACDAT <= RIGHT[10];
DAC_STATE <= 6'h1D;
end
6'h1D:
begin
AUD_DACDAT <= RIGHT[9];
DAC_STATE <= 6'h1E;
end
6'h1E:
begin
AUD_DACDAT <= RIGHT[8];
DAC_STATE <= 6'h1F;
end
6'h1F:
begin
AUD_DACDAT <= RIGHT[7];
DAC_STATE <= 6'h20;
end
6'h20:
begin
AUD_DACDAT <= RIGHT[6];
DAC_STATE <= 6'h21;
end
6'h21:
begin
AUD_DACDAT <= RIGHT[5];
DAC_STATE <= 6'h22;
end
6'h22:
begin
AUD_DACDAT <= RIGHT[4];
DAC_STATE <= 6'h23;
end
6'h23:
begin
AUD_DACDAT <= RIGHT[3];
DAC_STATE <= 6'h24;
end
6'h24:
begin
AUD_DACDAT <= RIGHT[2];
DAC_STATE <= 6'h25;
end
6'h25:
begin
AUD_DACDAT <= RIGHT[1];
DAC_STATE <= 6'h26;
end
6'h26:
begin
AUD_DACDAT <= RIGHT[0];
DAC_STATE <= 6'h27;
end
6'h27:
begin
AUD_DACDAT <= 1'b0;
DAC_STATE <= 6'h00;
end
default:
begin
AUD_DACDAT <= 1'b0;
DAC_STATE <= 6'h00;
end
endcase
end
|
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Tue Jan 1 09:13:45 EST 2013
//
//
// Ports:
// Name I/O size props
// pcie_tx O 4
// led O 16 reg
// hsmc_out O 16 reg
// led_cathode O 20 const
// led_anode O 20
// lcd_db O 4
// lcd_e O 1
// lcd_rs O 1
// lcd_rw O 1
// gps_ppsSyncOut O 1
// flash_addr O 24 reg
// flash_ce_n O 1
// flash_oe_n O 1
// flash_we_n O 1
// flash_wp_n O 1 const
// flash_rst_n O 1 const
// flash_adv_n O 1 const
// dram_addr O 13
// dram_ba O 3
// dram_ras_n O 1
// dram_cas_n O 1
// dram_we_n O 1
// dram_reset_n O 1
// dram_cs_n O 1
// dram_odt O 1
// dram_cke O 1
// dram_dm O 2
// dram_ck_p O 1
// dram_ck_n O 1
// p125clk O 1 clock
// CLK_GATE_p125clk O 1 const
// p125rst O 1 reset
// sys0_clk I 1 clock
// sys0_rstn I 1 reset
// pcie_clk I 1 clock
// pcie_rstn I 1 reset
// pcie_rx_i I 4
// usr_sw_i I 8 reg
// hsmc_in_i I 16 reg
// gps_ppsSyncIn_x I 1 reg
// flash_fwait_i I 1 reg
// dram_rdn_i I 1
// dram_rup_i I 1
// flash_io_dq IO 16 inout
// dram_io_dq IO 16 inout
// dram_io_dqs_p IO 2 inout
// dram_io_dqs_n IO 2 inout
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFTop_alst4(sys0_clk,
sys0_rstn,
pcie_clk,
pcie_rstn,
flash_io_dq,
dram_io_dq,
dram_io_dqs_p,
dram_io_dqs_n,
pcie_rx_i,
pcie_tx,
usr_sw_i,
led,
hsmc_in_i,
hsmc_out,
led_cathode,
led_anode,
lcd_db,
lcd_e,
lcd_rs,
lcd_rw,
gps_ppsSyncIn_x,
gps_ppsSyncOut,
flash_addr,
flash_ce_n,
flash_oe_n,
flash_we_n,
flash_wp_n,
flash_rst_n,
flash_adv_n,
flash_fwait_i,
dram_addr,
dram_ba,
dram_ras_n,
dram_cas_n,
dram_we_n,
dram_reset_n,
dram_cs_n,
dram_odt,
dram_cke,
dram_dm,
dram_ck_p,
dram_ck_n,
dram_rdn_i,
dram_rup_i,
p125clk,
CLK_GATE_p125clk,
p125rst);
input sys0_clk;
input sys0_rstn;
input pcie_clk;
input pcie_rstn;
inout [15 : 0] flash_io_dq;
inout [15 : 0] dram_io_dq;
inout [1 : 0] dram_io_dqs_p;
inout [1 : 0] dram_io_dqs_n;
// action method pcie_rx
input [3 : 0] pcie_rx_i;
// value method pcie_tx
output [3 : 0] pcie_tx;
// action method usr_sw
input [7 : 0] usr_sw_i;
// value method led
output [15 : 0] led;
// action method hsmc_in
input [15 : 0] hsmc_in_i;
// value method hsmc_out
output [15 : 0] hsmc_out;
// value method led_cathode
output [19 : 0] led_cathode;
// value method led_anode
output [19 : 0] led_anode;
// value method lcd_db
output [3 : 0] lcd_db;
// value method lcd_e
output lcd_e;
// value method lcd_rs
output lcd_rs;
// value method lcd_rw
output lcd_rw;
// action method gps_ppsSyncIn
input gps_ppsSyncIn_x;
// value method gps_ppsSyncOut
output gps_ppsSyncOut;
// value method flash_addr
output [23 : 0] flash_addr;
// value method flash_ce_n
output flash_ce_n;
// value method flash_oe_n
output flash_oe_n;
// value method flash_we_n
output flash_we_n;
// value method flash_wp_n
output flash_wp_n;
// value method flash_rst_n
output flash_rst_n;
// value method flash_adv_n
output flash_adv_n;
// action method flash_fwait
input flash_fwait_i;
// value method dram_addr
output [12 : 0] dram_addr;
// value method dram_ba
output [2 : 0] dram_ba;
// value method dram_ras_n
output dram_ras_n;
// value method dram_cas_n
output dram_cas_n;
// value method dram_we_n
output dram_we_n;
// value method dram_reset_n
output dram_reset_n;
// value method dram_cs_n
output dram_cs_n;
// value method dram_odt
output dram_odt;
// value method dram_cke
output dram_cke;
// value method dram_dm
output [1 : 0] dram_dm;
// value method dram_ck_p
output dram_ck_p;
// value method dram_ck_n
output dram_ck_n;
// action method dram_rdn
input dram_rdn_i;
// action method dram_rup
input dram_rup_i;
// oscillator and gates for output clock p125clk
output p125clk;
output CLK_GATE_p125clk;
// output resets
output p125rst;
// signals for module outputs
wire [23 : 0] flash_addr;
wire [19 : 0] led_anode, led_cathode;
wire [15 : 0] hsmc_out, led;
wire [12 : 0] dram_addr;
wire [3 : 0] lcd_db, pcie_tx;
wire [2 : 0] dram_ba;
wire [1 : 0] dram_dm;
wire CLK_GATE_p125clk,
dram_cas_n,
dram_ck_n,
dram_ck_p,
dram_cke,
dram_cs_n,
dram_odt,
dram_ras_n,
dram_reset_n,
dram_we_n,
flash_adv_n,
flash_ce_n,
flash_oe_n,
flash_rst_n,
flash_we_n,
flash_wp_n,
gps_ppsSyncOut,
lcd_e,
lcd_rs,
lcd_rw,
p125clk,
p125rst;
// inlined wires
wire [127 : 0] pciw_pci0_rxDws_new_data$wget, pciw_pci0_txDws_new_data$wget;
wire [2 : 0] pciw_pci0_rxDws_delta_deq$wget,
pciw_pci0_rxDws_delta_enq$wget,
pciw_pci0_txDws_delta_deq$wget,
pciw_pci0_txDws_delta_enq$wget;
wire [1 : 0] infLed$wget;
wire pciw_pci0_avaTxEmpty$wget,
pciw_pci0_avaTxEmpty$whas,
pciw_pci0_avaTxEop$wget,
pciw_pci0_avaTxEop$whas,
pciw_pci0_avaTxErr$wget,
pciw_pci0_avaTxErr$whas,
pciw_pci0_avaTxSop$wget,
pciw_pci0_avaTxSop$whas,
pciw_pci0_avaTxValid$wget,
pciw_pci0_avaTxValid$whas,
pciw_pci0_rxDws_delta_deq$whas,
pciw_pci0_rxDws_delta_enq$whas,
pciw_pci0_rxDws_new_data$whas,
pciw_pci0_rxInF_doResetClr$whas,
pciw_pci0_rxInF_doResetDeq$whas,
pciw_pci0_rxInF_doResetEnq$whas,
pciw_pci0_rxInF_r_clr$whas,
pciw_pci0_rxInF_r_deq$whas,
pciw_pci0_rxInF_r_enq$whas,
pciw_pci0_txDws_delta_deq$whas,
pciw_pci0_txDws_delta_enq$whas,
pciw_pci0_txDws_new_data$whas,
pciw_pci0_txOutF_doResetClr$whas,
pciw_pci0_txOutF_doResetDeq$whas,
pciw_pci0_txOutF_doResetEnq$whas,
pciw_pci0_txOutF_r_clr$whas,
pciw_pci0_txOutF_r_deq$whas,
pciw_pci0_txOutF_r_enq$whas;
// register freeCnt
reg [31 : 0] freeCnt;
wire [31 : 0] freeCnt$D_IN;
wire freeCnt$EN;
// register hsmcReg
reg [15 : 0] hsmcReg;
wire [15 : 0] hsmcReg$D_IN;
wire hsmcReg$EN;
// register ledReg
reg [15 : 0] ledReg;
wire [15 : 0] ledReg$D_IN;
wire ledReg$EN;
// register needs_init
reg needs_init;
wire needs_init$D_IN, needs_init$EN;
// register pciDevice
reg [15 : 0] pciDevice;
wire [15 : 0] pciDevice$D_IN;
wire pciDevice$EN;
// register pciw_pci0_cfgDataWr
reg pciw_pci0_cfgDataWr;
wire pciw_pci0_cfgDataWr$D_IN, pciw_pci0_cfgDataWr$EN;
// register pciw_pci0_cfgSample
reg pciw_pci0_cfgSample;
wire pciw_pci0_cfgSample$D_IN, pciw_pci0_cfgSample$EN;
// register pciw_pci0_deviceReg
reg [15 : 0] pciw_pci0_deviceReg;
wire [15 : 0] pciw_pci0_deviceReg$D_IN;
wire pciw_pci0_deviceReg$EN;
// register pciw_pci0_rxDbgDeDeq
reg [15 : 0] pciw_pci0_rxDbgDeDeq;
wire [15 : 0] pciw_pci0_rxDbgDeDeq$D_IN;
wire pciw_pci0_rxDbgDeDeq$EN;
// register pciw_pci0_rxDbgDeEof
reg [15 : 0] pciw_pci0_rxDbgDeEof;
wire [15 : 0] pciw_pci0_rxDbgDeEof$D_IN;
wire pciw_pci0_rxDbgDeEof$EN;
// register pciw_pci0_rxDbgDeSof
reg [15 : 0] pciw_pci0_rxDbgDeSof;
wire [15 : 0] pciw_pci0_rxDbgDeSof$D_IN;
wire pciw_pci0_rxDbgDeSof$EN;
// register pciw_pci0_rxDbgDestage
reg [15 : 0] pciw_pci0_rxDbgDestage;
wire [15 : 0] pciw_pci0_rxDbgDestage$D_IN;
wire pciw_pci0_rxDbgDestage$EN;
// register pciw_pci0_rxDbgEnEnq
reg [15 : 0] pciw_pci0_rxDbgEnEnq;
wire [15 : 0] pciw_pci0_rxDbgEnEnq$D_IN;
wire pciw_pci0_rxDbgEnEnq$EN;
// register pciw_pci0_rxDbgEnEof
reg [15 : 0] pciw_pci0_rxDbgEnEof;
wire [15 : 0] pciw_pci0_rxDbgEnEof$D_IN;
wire pciw_pci0_rxDbgEnEof$EN;
// register pciw_pci0_rxDbgEnSof
reg [15 : 0] pciw_pci0_rxDbgEnSof;
wire [15 : 0] pciw_pci0_rxDbgEnSof$D_IN;
wire pciw_pci0_rxDbgEnSof$EN;
// register pciw_pci0_rxDbgEnstage
reg [15 : 0] pciw_pci0_rxDbgEnstage;
wire [15 : 0] pciw_pci0_rxDbgEnstage$D_IN;
wire pciw_pci0_rxDbgEnstage$EN;
// register pciw_pci0_rxDbgInstage
reg [15 : 0] pciw_pci0_rxDbgInstage;
wire [15 : 0] pciw_pci0_rxDbgInstage$D_IN;
wire pciw_pci0_rxDbgInstage$EN;
// register pciw_pci0_rxDwrDeq
reg [10 : 0] pciw_pci0_rxDwrDeq;
wire [10 : 0] pciw_pci0_rxDwrDeq$D_IN;
wire pciw_pci0_rxDwrDeq$EN;
// register pciw_pci0_rxDwrEnq
reg [10 : 0] pciw_pci0_rxDwrEnq;
wire [10 : 0] pciw_pci0_rxDwrEnq$D_IN;
wire pciw_pci0_rxDwrEnq$EN;
// register pciw_pci0_rxDws_num_empty
reg [3 : 0] pciw_pci0_rxDws_num_empty;
wire [3 : 0] pciw_pci0_rxDws_num_empty$D_IN;
wire pciw_pci0_rxDws_num_empty$EN;
// register pciw_pci0_rxDws_num_full
reg [3 : 0] pciw_pci0_rxDws_num_full;
wire [3 : 0] pciw_pci0_rxDws_num_full$D_IN;
wire pciw_pci0_rxDws_num_full$EN;
// register pciw_pci0_rxDws_vec
reg [255 : 0] pciw_pci0_rxDws_vec;
wire [255 : 0] pciw_pci0_rxDws_vec$D_IN;
wire pciw_pci0_rxDws_vec$EN;
// register pciw_pci0_rxInF_countReg
reg [5 : 0] pciw_pci0_rxInF_countReg;
wire [5 : 0] pciw_pci0_rxInF_countReg$D_IN;
wire pciw_pci0_rxInF_countReg$EN;
// register pciw_pci0_rxInF_levelsValid
reg pciw_pci0_rxInF_levelsValid;
wire pciw_pci0_rxInF_levelsValid$D_IN, pciw_pci0_rxInF_levelsValid$EN;
// register pciw_pci0_rxInFlight
reg pciw_pci0_rxInFlight;
wire pciw_pci0_rxInFlight$D_IN, pciw_pci0_rxInFlight$EN;
// register pciw_pci0_txDbgDeDeq
reg [15 : 0] pciw_pci0_txDbgDeDeq;
wire [15 : 0] pciw_pci0_txDbgDeDeq$D_IN;
wire pciw_pci0_txDbgDeDeq$EN;
// register pciw_pci0_txDbgDeEof
reg [15 : 0] pciw_pci0_txDbgDeEof;
wire [15 : 0] pciw_pci0_txDbgDeEof$D_IN;
wire pciw_pci0_txDbgDeEof$EN;
// register pciw_pci0_txDbgDeSof
reg [15 : 0] pciw_pci0_txDbgDeSof;
wire [15 : 0] pciw_pci0_txDbgDeSof$D_IN;
wire pciw_pci0_txDbgDeSof$EN;
// register pciw_pci0_txDbgDestage
reg [15 : 0] pciw_pci0_txDbgDestage;
wire [15 : 0] pciw_pci0_txDbgDestage$D_IN;
wire pciw_pci0_txDbgDestage$EN;
// register pciw_pci0_txDbgEnEnq
reg [15 : 0] pciw_pci0_txDbgEnEnq;
wire [15 : 0] pciw_pci0_txDbgEnEnq$D_IN;
wire pciw_pci0_txDbgEnEnq$EN;
// register pciw_pci0_txDbgEnEof
reg [15 : 0] pciw_pci0_txDbgEnEof;
wire [15 : 0] pciw_pci0_txDbgEnEof$D_IN;
wire pciw_pci0_txDbgEnEof$EN;
// register pciw_pci0_txDbgEnSof
reg [15 : 0] pciw_pci0_txDbgEnSof;
wire [15 : 0] pciw_pci0_txDbgEnSof$D_IN;
wire pciw_pci0_txDbgEnSof$EN;
// register pciw_pci0_txDbgEnstage
reg [15 : 0] pciw_pci0_txDbgEnstage;
wire [15 : 0] pciw_pci0_txDbgEnstage$D_IN;
wire pciw_pci0_txDbgEnstage$EN;
// register pciw_pci0_txDbgExstage
reg [15 : 0] pciw_pci0_txDbgExstage;
wire [15 : 0] pciw_pci0_txDbgExstage$D_IN;
wire pciw_pci0_txDbgExstage$EN;
// register pciw_pci0_txDwrDeq
reg [10 : 0] pciw_pci0_txDwrDeq;
wire [10 : 0] pciw_pci0_txDwrDeq$D_IN;
wire pciw_pci0_txDwrDeq$EN;
// register pciw_pci0_txDwrEnq
reg [10 : 0] pciw_pci0_txDwrEnq;
wire [10 : 0] pciw_pci0_txDwrEnq$D_IN;
wire pciw_pci0_txDwrEnq$EN;
// register pciw_pci0_txDws_num_empty
reg [3 : 0] pciw_pci0_txDws_num_empty;
wire [3 : 0] pciw_pci0_txDws_num_empty$D_IN;
wire pciw_pci0_txDws_num_empty$EN;
// register pciw_pci0_txDws_num_full
reg [3 : 0] pciw_pci0_txDws_num_full;
wire [3 : 0] pciw_pci0_txDws_num_full$D_IN;
wire pciw_pci0_txDws_num_full$EN;
// register pciw_pci0_txDws_vec
reg [255 : 0] pciw_pci0_txDws_vec;
wire [255 : 0] pciw_pci0_txDws_vec$D_IN;
wire pciw_pci0_txDws_vec$EN;
// register pciw_pci0_txInFlight
reg pciw_pci0_txInFlight;
wire pciw_pci0_txInFlight$D_IN, pciw_pci0_txInFlight$EN;
// register pciw_pci0_txOutF_countReg
reg [9 : 0] pciw_pci0_txOutF_countReg;
wire [9 : 0] pciw_pci0_txOutF_countReg$D_IN;
wire pciw_pci0_txOutF_countReg$EN;
// register pciw_pci0_txOutF_levelsValid
reg pciw_pci0_txOutF_levelsValid;
wire pciw_pci0_txOutF_levelsValid$D_IN, pciw_pci0_txOutF_levelsValid$EN;
// register pciw_pci0_txReadyD
reg pciw_pci0_txReadyD;
wire pciw_pci0_txReadyD$D_IN, pciw_pci0_txReadyD$EN;
// register pciw_pciDevice
reg [15 : 0] pciw_pciDevice;
wire [15 : 0] pciw_pciDevice$D_IN;
wire pciw_pciDevice$EN;
// register swReg
reg [7 : 0] swReg;
wire [7 : 0] swReg$D_IN;
wire swReg$EN;
// ports of submodule ctop
wire [152 : 0] ctop$server_request_put, ctop$server_response_get;
wire [127 : 0] ctop$wmemiM0_MData, ctop$wmemiM0_SData;
wire [58 : 0] ctop$cpServer_request_put;
wire [35 : 0] ctop$wmemiM0_MAddr;
wire [31 : 0] ctop$wci_m_0_SData,
ctop$wci_m_1_MAddr,
ctop$wci_m_1_MData,
ctop$wci_m_1_SData,
ctop$wci_m_2_SData,
ctop$wci_m_3_SData,
ctop$wci_m_4_MAddr,
ctop$wci_m_4_MData,
ctop$wci_m_4_SData,
ctop$wsi_s_adc_MData;
wire [15 : 0] ctop$wmemiM0_MDataByteEn;
wire [11 : 0] ctop$wmemiM0_MBurstLength, ctop$wsi_s_adc_MBurstLength;
wire [7 : 0] ctop$wsi_s_adc_MReqInfo;
wire [3 : 0] ctop$wci_m_1_MByteEn,
ctop$wci_m_4_MByteEn,
ctop$wsi_s_adc_MByteEn;
wire [2 : 0] ctop$switch_x,
ctop$wci_m_1_MCmd,
ctop$wci_m_4_MCmd,
ctop$wmemiM0_MCmd,
ctop$wsi_s_adc_MCmd;
wire [1 : 0] ctop$led,
ctop$wci_m_0_SFlag,
ctop$wci_m_0_SResp,
ctop$wci_m_1_MFlag,
ctop$wci_m_1_SFlag,
ctop$wci_m_1_SResp,
ctop$wci_m_2_SFlag,
ctop$wci_m_2_SResp,
ctop$wci_m_3_SFlag,
ctop$wci_m_3_SResp,
ctop$wci_m_4_MFlag,
ctop$wci_m_4_SFlag,
ctop$wci_m_4_SResp,
ctop$wmemiM0_SResp;
wire ctop$EN_cpServer_request_put,
ctop$EN_cpServer_response_get,
ctop$EN_server_request_put,
ctop$EN_server_response_get,
ctop$RDY_server_request_put,
ctop$RDY_server_response_get,
ctop$RST_N_wci_m_1,
ctop$RST_N_wci_m_4,
ctop$gps_ppsSyncIn_x,
ctop$gps_ppsSyncOut,
ctop$wci_m_0_SThreadBusy,
ctop$wci_m_1_MAddrSpace,
ctop$wci_m_1_SThreadBusy,
ctop$wci_m_2_SThreadBusy,
ctop$wci_m_3_SThreadBusy,
ctop$wci_m_4_MAddrSpace,
ctop$wci_m_4_SThreadBusy,
ctop$wmemiM0_MDataLast,
ctop$wmemiM0_MDataValid,
ctop$wmemiM0_MReqLast,
ctop$wmemiM0_MReset_n,
ctop$wmemiM0_SCmdAccept,
ctop$wmemiM0_SDataAccept,
ctop$wmemiM0_SRespLast,
ctop$wsi_m_dac_SReset_n,
ctop$wsi_m_dac_SThreadBusy,
ctop$wsi_s_adc_MBurstPrecise,
ctop$wsi_s_adc_MReqLast,
ctop$wsi_s_adc_MReset_n;
// ports of submodule dram0
wire [127 : 0] dram0$wmemiS0_MData, dram0$wmemiS0_SData;
wire [35 : 0] dram0$wmemiS0_MAddr;
wire [31 : 0] dram0$wciS0_MAddr, dram0$wciS0_MData, dram0$wciS0_SData;
wire [15 : 0] dram0$dram_io_dq, dram0$wmemiS0_MDataByteEn;
wire [12 : 0] dram0$dram_addr;
wire [11 : 0] dram0$wmemiS0_MBurstLength;
wire [3 : 0] dram0$wciS0_MByteEn;
wire [2 : 0] dram0$dram_ba, dram0$wciS0_MCmd, dram0$wmemiS0_MCmd;
wire [1 : 0] dram0$dram_dm,
dram0$dram_io_dqs_n,
dram0$dram_io_dqs_p,
dram0$wciS0_MFlag,
dram0$wciS0_SFlag,
dram0$wciS0_SResp,
dram0$wmemiS0_SResp;
wire dram0$dram_cas_n,
dram0$dram_ck_n,
dram0$dram_ck_p,
dram0$dram_cke,
dram0$dram_cs_n,
dram0$dram_odt,
dram0$dram_ras_n,
dram0$dram_rdn_i,
dram0$dram_reset_n,
dram0$dram_rup_i,
dram0$dram_we_n,
dram0$wciS0_MAddrSpace,
dram0$wciS0_SThreadBusy,
dram0$wmemiS0_MDataLast,
dram0$wmemiS0_MDataValid,
dram0$wmemiS0_MReqLast,
dram0$wmemiS0_MReset_n,
dram0$wmemiS0_SCmdAccept,
dram0$wmemiS0_SDataAccept,
dram0$wmemiS0_SRespLast;
// ports of submodule flash0
wire [31 : 0] flash0$wciS0_MAddr, flash0$wciS0_MData, flash0$wciS0_SData;
wire [23 : 0] flash0$flash_addr;
wire [15 : 0] flash0$flash_io_dq;
wire [3 : 0] flash0$wciS0_MByteEn;
wire [2 : 0] flash0$wciS0_MCmd;
wire [1 : 0] flash0$wciS0_MFlag, flash0$wciS0_SFlag, flash0$wciS0_SResp;
wire flash0$flash_adv_n,
flash0$flash_ce_n,
flash0$flash_fwait_i,
flash0$flash_oe_n,
flash0$flash_rst_n,
flash0$flash_we_n,
flash0$flash_wp_n,
flash0$wciS0_MAddrSpace,
flash0$wciS0_SThreadBusy;
// ports of submodule lcd_ctrl
wire [127 : 0] lcd_ctrl$setLine1_text, lcd_ctrl$setLine2_text;
wire [3 : 0] lcd_ctrl$db;
wire lcd_ctrl$EN_setLine1,
lcd_ctrl$EN_setLine2,
lcd_ctrl$e,
lcd_ctrl$rs,
lcd_ctrl$rw;
// ports of submodule pciw_aliveLed_sb
wire pciw_aliveLed_sb$dD_OUT, pciw_aliveLed_sb$sD_IN, pciw_aliveLed_sb$sEN;
// ports of submodule pciw_i2pF
wire [152 : 0] pciw_i2pF$D_IN, pciw_i2pF$D_OUT;
wire pciw_i2pF$CLR,
pciw_i2pF$DEQ,
pciw_i2pF$EMPTY_N,
pciw_i2pF$ENQ,
pciw_i2pF$FULL_N;
// ports of submodule pciw_linkLed_sb
wire pciw_linkLed_sb$dD_OUT, pciw_linkLed_sb$sD_IN, pciw_linkLed_sb$sEN;
// ports of submodule pciw_p2iF
wire [152 : 0] pciw_p2iF$D_IN, pciw_p2iF$D_OUT;
wire pciw_p2iF$CLR,
pciw_p2iF$DEQ,
pciw_p2iF$EMPTY_N,
pciw_p2iF$ENQ,
pciw_p2iF$FULL_N;
// ports of submodule pciw_pci0_pcie_ep
wire [127 : 0] pciw_pci0_pcie_ep$rx_st_data0, pciw_pci0_pcie_ep$tx_st_data0;
wire [31 : 0] pciw_pci0_pcie_ep$ava_debug, pciw_pci0_pcie_ep$tl_cfg_ctl;
wire [15 : 0] pciw_pci0_pcie_ep$rx_st_be0;
wire [7 : 0] pciw_pci0_pcie_ep$rx_st_bardec0;
wire [3 : 0] pciw_pci0_pcie_ep$pcie_rx_in,
pciw_pci0_pcie_ep$pcie_tx_out,
pciw_pci0_pcie_ep$tl_cfg_add;
wire pciw_pci0_pcie_ep$ava_alive,
pciw_pci0_pcie_ep$ava_core_clk_out,
pciw_pci0_pcie_ep$ava_lnk_up,
pciw_pci0_pcie_ep$ava_srstn,
pciw_pci0_pcie_ep$rx_st_empty0,
pciw_pci0_pcie_ep$rx_st_eop0,
pciw_pci0_pcie_ep$rx_st_mask0,
pciw_pci0_pcie_ep$rx_st_ready0,
pciw_pci0_pcie_ep$rx_st_sop0,
pciw_pci0_pcie_ep$rx_st_valid0,
pciw_pci0_pcie_ep$tl_cfg_ctl_wr,
pciw_pci0_pcie_ep$tx_st_empty0,
pciw_pci0_pcie_ep$tx_st_eop0,
pciw_pci0_pcie_ep$tx_st_err0,
pciw_pci0_pcie_ep$tx_st_ready0,
pciw_pci0_pcie_ep$tx_st_sop0,
pciw_pci0_pcie_ep$tx_st_valid0;
// ports of submodule pciw_pci0_rxEofF
wire [2 : 0] pciw_pci0_rxEofF$D_IN;
wire pciw_pci0_rxEofF$CLR,
pciw_pci0_rxEofF$DEQ,
pciw_pci0_rxEofF$EMPTY_N,
pciw_pci0_rxEofF$ENQ,
pciw_pci0_rxEofF$FULL_N;
// ports of submodule pciw_pci0_rxHeadF
wire [30 : 0] pciw_pci0_rxHeadF$D_IN, pciw_pci0_rxHeadF$D_OUT;
wire pciw_pci0_rxHeadF$CLR,
pciw_pci0_rxHeadF$DEQ,
pciw_pci0_rxHeadF$EMPTY_N,
pciw_pci0_rxHeadF$ENQ,
pciw_pci0_rxHeadF$FULL_N;
// ports of submodule pciw_pci0_rxInF
wire [154 : 0] pciw_pci0_rxInF$D_IN, pciw_pci0_rxInF$D_OUT;
wire pciw_pci0_rxInF$CLR,
pciw_pci0_rxInF$DEQ,
pciw_pci0_rxInF$EMPTY_N,
pciw_pci0_rxInF$ENQ,
pciw_pci0_rxInF$FULL_N;
// ports of submodule pciw_pci0_rxOutF
wire [152 : 0] pciw_pci0_rxOutF$D_IN, pciw_pci0_rxOutF$D_OUT;
wire pciw_pci0_rxOutF$CLR,
pciw_pci0_rxOutF$DEQ,
pciw_pci0_rxOutF$EMPTY_N,
pciw_pci0_rxOutF$ENQ,
pciw_pci0_rxOutF$FULL_N;
// ports of submodule pciw_pci0_txEofF
wire [2 : 0] pciw_pci0_txEofF$D_IN;
wire pciw_pci0_txEofF$CLR,
pciw_pci0_txEofF$DEQ,
pciw_pci0_txEofF$EMPTY_N,
pciw_pci0_txEofF$ENQ,
pciw_pci0_txEofF$FULL_N;
// ports of submodule pciw_pci0_txExF
wire pciw_pci0_txExF$CLR,
pciw_pci0_txExF$DEQ,
pciw_pci0_txExF$D_IN,
pciw_pci0_txExF$EMPTY_N,
pciw_pci0_txExF$ENQ,
pciw_pci0_txExF$FULL_N;
// ports of submodule pciw_pci0_txHeadF
wire [30 : 0] pciw_pci0_txHeadF$D_IN, pciw_pci0_txHeadF$D_OUT;
wire pciw_pci0_txHeadF$CLR,
pciw_pci0_txHeadF$DEQ,
pciw_pci0_txHeadF$EMPTY_N,
pciw_pci0_txHeadF$ENQ,
pciw_pci0_txHeadF$FULL_N;
// ports of submodule pciw_pci0_txInF
wire [152 : 0] pciw_pci0_txInF$D_IN, pciw_pci0_txInF$D_OUT;
wire pciw_pci0_txInF$CLR,
pciw_pci0_txInF$DEQ,
pciw_pci0_txInF$EMPTY_N,
pciw_pci0_txInF$ENQ,
pciw_pci0_txInF$FULL_N;
// ports of submodule pciw_pci0_txOutF
wire [154 : 0] pciw_pci0_txOutF$D_IN, pciw_pci0_txOutF$D_OUT;
wire pciw_pci0_txOutF$CLR,
pciw_pci0_txOutF$DEQ,
pciw_pci0_txOutF$EMPTY_N,
pciw_pci0_txOutF$ENQ,
pciw_pci0_txOutF$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_pciw_pci0_rxInF_reset,
WILL_FIRE_RL_pciw_pci0_rx_destage,
WILL_FIRE_RL_pciw_pci0_rx_enstage,
WILL_FIRE_RL_pciw_pci0_txOutF_reset,
WILL_FIRE_RL_pciw_pci0_tx_destage,
WILL_FIRE_RL_pciw_pci0_tx_enstage,
WILL_FIRE_RL_pciw_pci0_tx_exstage;
// inputs to muxes for submodule ports
wire MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3;
// remaining internal signals
reg [15 : 0] IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787;
wire [255 : 0] _0_CONCAT_pciw_pci0_rxDws_new_data_wget__2_BITS_ETC___d832,
_0_CONCAT_pciw_pci0_txDws_new_data_wget__8_BITS_ETC___d833,
pciw_pci0_rxDws_vec_3_SRL_IF_pciw_pci0_rxDws_d_ETC___d834,
pciw_pci0_txDws_vec_9_SRL_IF_pciw_pci0_txDws_d_ETC___d835;
wire [127 : 0] x__h14478, x__h4523, x_data__h27615, x_data__h46011;
wire [95 : 0] IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481;
wire [31 : 0] IF_pciw_pci0_txHeadF_first__59_BIT_11_60_THEN__ETC___d468,
IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492,
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831,
x__h56415,
x__h56417,
x__h56419,
x__h56421,
x__h56423,
x__h56425,
x__h56427,
x__h56429,
x__h56431,
x__h56433,
x__h56435,
x__h56437,
x__h56439,
x__h56441,
x__h56443,
x__h56445,
x__h56447,
x__h56449,
x__h56451,
y__h56416,
y__h56418,
y__h56420,
y__h56422,
y__h56424,
y__h56426,
y__h56428,
y__h56430,
y__h56432,
y__h56434,
y__h56436,
y__h56438,
y__h56440,
y__h56442,
y__h56444,
y__h56446,
y__h56448,
y__h56450,
y__h56452,
y__h56454;
wire [15 : 0] x_be__h27614;
wire [10 : 0] IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1,
IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2,
IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_IF_p_ETC___d837,
IF_pciw_pci0_rxEofF_notEmpty__62_AND_pciw_pci0_ETC___d288,
IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_rxDw_ETC___d769,
IF_pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_ETC___d523,
IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d838;
wire [8 : 0] x__h15731, x__h5776;
wire [7 : 0] INV_swReg_35_BIT_0_36_XOR_swReg_35_BIT_1_37_38_ETC___d764,
bar___1__h22106,
x__h18832,
x__h8877,
x_hit__h22096;
wire [2 : 0] IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801,
IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771,
IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804,
IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770;
wire NOT_pciw_pci0_txEofF_notEmpty__52_53_OR_NOT_pc_ETC___d495,
pciw_pci0_rxDws_num_full_7_ULE_4___d836,
pciw_pci0_txDws_num_full_3_ULE_4___d774,
pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817,
pciw_pci0_txOutF_i_notFull__48_AND_pciw_pci0_t_ETC___d502,
swParity__h48492,
z__h55844,
z__h55851,
z__h55858,
z__h55865,
z__h55872,
z__h55879,
z__h56129,
z__h56136,
z__h56143,
z__h56150,
z__h56157,
z__h56164,
z__h56171,
z__h56178,
z__h56185,
z__h56192,
z__h56199,
z__h56206,
z__h56213,
z__h56220,
z__h56227,
z__h56234,
z__h56241,
z__h56248,
z__h56255,
z__h56262,
z__h56269,
z__h56276,
z__h56283,
z__h56290,
z__h56297,
z__h56304,
z__h56311,
z__h56318,
z__h56325,
z__h56332;
// oscillator and gates for output clock p125clk
assign p125clk = pciw_pci0_pcie_ep$ava_core_clk_out ;
assign CLK_GATE_p125clk = 1'b1 ;
// output resets
assign p125rst = pciw_pci0_pcie_ep$ava_srstn ;
// value method pcie_tx
assign pcie_tx = pciw_pci0_pcie_ep$pcie_tx_out ;
// value method led
assign led = ledReg ;
// value method hsmc_out
assign hsmc_out = hsmcReg ;
// value method led_cathode
assign led_cathode = 20'd0 ;
// value method led_anode
assign led_anode = { 4'h8, ledReg } ;
// value method lcd_db
assign lcd_db = lcd_ctrl$db ;
// value method lcd_e
assign lcd_e = lcd_ctrl$e ;
// value method lcd_rs
assign lcd_rs = lcd_ctrl$rs ;
// value method lcd_rw
assign lcd_rw = lcd_ctrl$rw ;
// value method gps_ppsSyncOut
assign gps_ppsSyncOut = ctop$gps_ppsSyncOut ;
// value method flash_addr
assign flash_addr = flash0$flash_addr ;
// value method flash_ce_n
assign flash_ce_n = flash0$flash_ce_n ;
// value method flash_oe_n
assign flash_oe_n = flash0$flash_oe_n ;
// value method flash_we_n
assign flash_we_n = flash0$flash_we_n ;
// value method flash_wp_n
assign flash_wp_n = flash0$flash_wp_n ;
// value method flash_rst_n
assign flash_rst_n = flash0$flash_rst_n ;
// value method flash_adv_n
assign flash_adv_n = flash0$flash_adv_n ;
// value method dram_addr
assign dram_addr = dram0$dram_addr ;
// value method dram_ba
assign dram_ba = dram0$dram_ba ;
// value method dram_ras_n
assign dram_ras_n = dram0$dram_ras_n ;
// value method dram_cas_n
assign dram_cas_n = dram0$dram_cas_n ;
// value method dram_we_n
assign dram_we_n = dram0$dram_we_n ;
// value method dram_reset_n
assign dram_reset_n = dram0$dram_reset_n ;
// value method dram_cs_n
assign dram_cs_n = dram0$dram_cs_n ;
// value method dram_odt
assign dram_odt = dram0$dram_odt ;
// value method dram_cke
assign dram_cke = dram0$dram_cke ;
// value method dram_dm
assign dram_dm = dram0$dram_dm ;
// value method dram_ck_p
assign dram_ck_p = dram0$dram_ck_p ;
// value method dram_ck_n
assign dram_ck_n = dram0$dram_ck_n ;
// submodule ctop
mkCTop4B ctop(.pciDevice(pciDevice),
.CLK_sys0_clk(sys0_clk),
.RST_N_sys0_rst(sys0_rstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.RST_N(pciw_pci0_pcie_ep$ava_srstn),
.cpServer_request_put(ctop$cpServer_request_put),
.gps_ppsSyncIn_x(ctop$gps_ppsSyncIn_x),
.server_request_put(ctop$server_request_put),
.switch_x(ctop$switch_x),
.wci_m_0_SData(ctop$wci_m_0_SData),
.wci_m_0_SFlag(ctop$wci_m_0_SFlag),
.wci_m_0_SResp(ctop$wci_m_0_SResp),
.wci_m_1_SData(ctop$wci_m_1_SData),
.wci_m_1_SFlag(ctop$wci_m_1_SFlag),
.wci_m_1_SResp(ctop$wci_m_1_SResp),
.wci_m_2_SData(ctop$wci_m_2_SData),
.wci_m_2_SFlag(ctop$wci_m_2_SFlag),
.wci_m_2_SResp(ctop$wci_m_2_SResp),
.wci_m_3_SData(ctop$wci_m_3_SData),
.wci_m_3_SFlag(ctop$wci_m_3_SFlag),
.wci_m_3_SResp(ctop$wci_m_3_SResp),
.wci_m_4_SData(ctop$wci_m_4_SData),
.wci_m_4_SFlag(ctop$wci_m_4_SFlag),
.wci_m_4_SResp(ctop$wci_m_4_SResp),
.wmemiM0_SData(ctop$wmemiM0_SData),
.wmemiM0_SResp(ctop$wmemiM0_SResp),
.wsi_s_adc_MBurstLength(ctop$wsi_s_adc_MBurstLength),
.wsi_s_adc_MByteEn(ctop$wsi_s_adc_MByteEn),
.wsi_s_adc_MCmd(ctop$wsi_s_adc_MCmd),
.wsi_s_adc_MData(ctop$wsi_s_adc_MData),
.wsi_s_adc_MReqInfo(ctop$wsi_s_adc_MReqInfo),
.EN_server_request_put(ctop$EN_server_request_put),
.EN_server_response_get(ctop$EN_server_response_get),
.EN_cpServer_request_put(ctop$EN_cpServer_request_put),
.EN_cpServer_response_get(ctop$EN_cpServer_response_get),
.wci_m_0_SThreadBusy(ctop$wci_m_0_SThreadBusy),
.wci_m_1_SThreadBusy(ctop$wci_m_1_SThreadBusy),
.wci_m_2_SThreadBusy(ctop$wci_m_2_SThreadBusy),
.wci_m_3_SThreadBusy(ctop$wci_m_3_SThreadBusy),
.wci_m_4_SThreadBusy(ctop$wci_m_4_SThreadBusy),
.wsi_s_adc_MReqLast(ctop$wsi_s_adc_MReqLast),
.wsi_s_adc_MBurstPrecise(ctop$wsi_s_adc_MBurstPrecise),
.wsi_s_adc_MReset_n(ctop$wsi_s_adc_MReset_n),
.wsi_m_dac_SThreadBusy(ctop$wsi_m_dac_SThreadBusy),
.wsi_m_dac_SReset_n(ctop$wsi_m_dac_SReset_n),
.wmemiM0_SRespLast(ctop$wmemiM0_SRespLast),
.wmemiM0_SCmdAccept(ctop$wmemiM0_SCmdAccept),
.wmemiM0_SDataAccept(ctop$wmemiM0_SDataAccept),
.RDY_server_request_put(ctop$RDY_server_request_put),
.server_response_get(ctop$server_response_get),
.RDY_server_response_get(ctop$RDY_server_response_get),
.RDY_cpServer_request_put(),
.cpServer_response_get(),
.RDY_cpServer_response_get(),
.led(ctop$led),
.wci_m_0_MCmd(),
.wci_m_0_MAddrSpace(),
.wci_m_0_MByteEn(),
.wci_m_0_MAddr(),
.wci_m_0_MData(),
.wci_m_0_MFlag(),
.wci_m_1_MCmd(ctop$wci_m_1_MCmd),
.wci_m_1_MAddrSpace(ctop$wci_m_1_MAddrSpace),
.wci_m_1_MByteEn(ctop$wci_m_1_MByteEn),
.wci_m_1_MAddr(ctop$wci_m_1_MAddr),
.wci_m_1_MData(ctop$wci_m_1_MData),
.wci_m_1_MFlag(ctop$wci_m_1_MFlag),
.wci_m_2_MCmd(),
.wci_m_2_MAddrSpace(),
.wci_m_2_MByteEn(),
.wci_m_2_MAddr(),
.wci_m_2_MData(),
.wci_m_2_MFlag(),
.wci_m_3_MCmd(),
.wci_m_3_MAddrSpace(),
.wci_m_3_MByteEn(),
.wci_m_3_MAddr(),
.wci_m_3_MData(),
.wci_m_3_MFlag(),
.wci_m_4_MCmd(ctop$wci_m_4_MCmd),
.wci_m_4_MAddrSpace(ctop$wci_m_4_MAddrSpace),
.wci_m_4_MByteEn(ctop$wci_m_4_MByteEn),
.wci_m_4_MAddr(ctop$wci_m_4_MAddr),
.wci_m_4_MData(ctop$wci_m_4_MData),
.wci_m_4_MFlag(ctop$wci_m_4_MFlag),
.cpNow(),
.RDY_cpNow(),
.wsi_s_adc_SThreadBusy(),
.wsi_s_adc_SReset_n(),
.wsi_m_dac_MCmd(),
.wsi_m_dac_MReqLast(),
.wsi_m_dac_MBurstPrecise(),
.wsi_m_dac_MBurstLength(),
.wsi_m_dac_MData(),
.wsi_m_dac_MByteEn(),
.wsi_m_dac_MReqInfo(),
.wsi_m_dac_MReset_n(),
.wmemiM0_MCmd(ctop$wmemiM0_MCmd),
.wmemiM0_MReqLast(ctop$wmemiM0_MReqLast),
.wmemiM0_MAddr(ctop$wmemiM0_MAddr),
.wmemiM0_MBurstLength(ctop$wmemiM0_MBurstLength),
.wmemiM0_MDataValid(ctop$wmemiM0_MDataValid),
.wmemiM0_MDataLast(ctop$wmemiM0_MDataLast),
.wmemiM0_MData(ctop$wmemiM0_MData),
.wmemiM0_MDataByteEn(ctop$wmemiM0_MDataByteEn),
.wmemiM0_MReset_n(ctop$wmemiM0_MReset_n),
.gps_ppsSyncOut(ctop$gps_ppsSyncOut),
.RST_N_wci_m_0(),
.RST_N_wci_m_1(ctop$RST_N_wci_m_1),
.RST_N_wci_m_2(),
.RST_N_wci_m_3(),
.RST_N_wci_m_4(ctop$RST_N_wci_m_4));
// submodule dram0
mkDramServer_s4 #(.hasDebugLogic(1'd0)) dram0(.CLK_sys0_clk(sys0_clk),
.RST_N_sys0_rstn(sys0_rstn),
.wciS0_Clk(pciw_pci0_pcie_ep$ava_core_clk_out),
.wciS0_MReset_n(ctop$RST_N_wci_m_4),
.dram_rdn_i(dram0$dram_rdn_i),
.dram_rup_i(dram0$dram_rup_i),
.wciS0_MAddr(dram0$wciS0_MAddr),
.wciS0_MAddrSpace(dram0$wciS0_MAddrSpace),
.wciS0_MByteEn(dram0$wciS0_MByteEn),
.wciS0_MCmd(dram0$wciS0_MCmd),
.wciS0_MData(dram0$wciS0_MData),
.wciS0_MFlag(dram0$wciS0_MFlag),
.wmemiS0_MAddr(dram0$wmemiS0_MAddr),
.wmemiS0_MBurstLength(dram0$wmemiS0_MBurstLength),
.wmemiS0_MCmd(dram0$wmemiS0_MCmd),
.wmemiS0_MData(dram0$wmemiS0_MData),
.wmemiS0_MDataByteEn(dram0$wmemiS0_MDataByteEn),
.wmemiS0_MReqLast(dram0$wmemiS0_MReqLast),
.wmemiS0_MDataValid(dram0$wmemiS0_MDataValid),
.wmemiS0_MDataLast(dram0$wmemiS0_MDataLast),
.wmemiS0_MReset_n(dram0$wmemiS0_MReset_n),
.wciS0_SResp(dram0$wciS0_SResp),
.wciS0_SData(dram0$wciS0_SData),
.wciS0_SThreadBusy(dram0$wciS0_SThreadBusy),
.wciS0_SFlag(dram0$wciS0_SFlag),
.wmemiS0_SResp(dram0$wmemiS0_SResp),
.wmemiS0_SRespLast(dram0$wmemiS0_SRespLast),
.wmemiS0_SData(dram0$wmemiS0_SData),
.wmemiS0_SCmdAccept(dram0$wmemiS0_SCmdAccept),
.wmemiS0_SDataAccept(dram0$wmemiS0_SDataAccept),
.dram_addr(dram0$dram_addr),
.dram_ba(dram0$dram_ba),
.dram_ras_n(dram0$dram_ras_n),
.dram_cas_n(dram0$dram_cas_n),
.dram_we_n(dram0$dram_we_n),
.dram_reset_n(dram0$dram_reset_n),
.dram_cs_n(dram0$dram_cs_n),
.dram_odt(dram0$dram_odt),
.dram_cke(dram0$dram_cke),
.dram_dm(dram0$dram_dm),
.dram_ck_p(dram0$dram_ck_p),
.dram_ck_n(dram0$dram_ck_n),
.dram_io_dq(dram_io_dq),
.dram_io_dqs_p(dram_io_dqs_p),
.dram_io_dqs_n(dram_io_dqs_n));
// submodule flash0
mkFlashWorker #(.hasDebugLogic(1'd1)) flash0(.wciS0_Clk(pciw_pci0_pcie_ep$ava_core_clk_out),
.wciS0_MReset_n(ctop$RST_N_wci_m_1),
.flash_fwait_i(flash0$flash_fwait_i),
.wciS0_MAddr(flash0$wciS0_MAddr),
.wciS0_MAddrSpace(flash0$wciS0_MAddrSpace),
.wciS0_MByteEn(flash0$wciS0_MByteEn),
.wciS0_MCmd(flash0$wciS0_MCmd),
.wciS0_MData(flash0$wciS0_MData),
.wciS0_MFlag(flash0$wciS0_MFlag),
.wciS0_SResp(flash0$wciS0_SResp),
.wciS0_SData(flash0$wciS0_SData),
.wciS0_SThreadBusy(flash0$wciS0_SThreadBusy),
.wciS0_SFlag(flash0$wciS0_SFlag),
.flash_addr(flash0$flash_addr),
.flash_ce_n(flash0$flash_ce_n),
.flash_oe_n(flash0$flash_oe_n),
.flash_we_n(flash0$flash_we_n),
.flash_wp_n(flash0$flash_wp_n),
.flash_rst_n(flash0$flash_rst_n),
.flash_adv_n(flash0$flash_adv_n),
.flash_io_dq(flash_io_dq));
// submodule lcd_ctrl
mkLCDController lcd_ctrl(.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.RST_N(pciw_pci0_pcie_ep$ava_srstn),
.setLine1_text(lcd_ctrl$setLine1_text),
.setLine2_text(lcd_ctrl$setLine2_text),
.EN_setLine1(lcd_ctrl$EN_setLine1),
.EN_setLine2(lcd_ctrl$EN_setLine2),
.db(lcd_ctrl$db),
.e(lcd_ctrl$e),
.rs(lcd_ctrl$rs),
.rw(lcd_ctrl$rw));
// submodule pciw_aliveLed_sb
SyncBit #(.init(1'd0)) pciw_aliveLed_sb(.sCLK(sys0_clk),
.dCLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.sRST(sys0_rstn),
.sD_IN(pciw_aliveLed_sb$sD_IN),
.sEN(pciw_aliveLed_sb$sEN),
.dD_OUT(pciw_aliveLed_sb$dD_OUT));
// submodule pciw_i2pF
FIFO2 #(.width(32'd153),
.guarded(32'd1)) pciw_i2pF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_i2pF$D_IN),
.ENQ(pciw_i2pF$ENQ),
.DEQ(pciw_i2pF$DEQ),
.CLR(pciw_i2pF$CLR),
.D_OUT(pciw_i2pF$D_OUT),
.FULL_N(pciw_i2pF$FULL_N),
.EMPTY_N(pciw_i2pF$EMPTY_N));
// submodule pciw_linkLed_sb
SyncBit #(.init(1'd0)) pciw_linkLed_sb(.sCLK(sys0_clk),
.dCLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.sRST(sys0_rstn),
.sD_IN(pciw_linkLed_sb$sD_IN),
.sEN(pciw_linkLed_sb$sEN),
.dD_OUT(pciw_linkLed_sb$dD_OUT));
// submodule pciw_p2iF
FIFO2 #(.width(32'd153),
.guarded(32'd1)) pciw_p2iF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_p2iF$D_IN),
.ENQ(pciw_p2iF$ENQ),
.DEQ(pciw_p2iF$DEQ),
.CLR(pciw_p2iF$CLR),
.D_OUT(pciw_p2iF$D_OUT),
.FULL_N(pciw_p2iF$FULL_N),
.EMPTY_N(pciw_p2iF$EMPTY_N));
// submodule pciw_pci0_pcie_ep
pcie_hip_s4gx_gen2_x4_128_wrapper pciw_pci0_pcie_ep(.sys0_clk(sys0_clk),
.sys0_rstn(sys0_rstn),
.pcie_clk(pcie_clk),
.pcie_rstn(pcie_rstn),
.pcie_rx_in(pciw_pci0_pcie_ep$pcie_rx_in),
.rx_st_mask0(pciw_pci0_pcie_ep$rx_st_mask0),
.rx_st_ready0(pciw_pci0_pcie_ep$rx_st_ready0),
.tx_st_data0(pciw_pci0_pcie_ep$tx_st_data0),
.tx_st_empty0(pciw_pci0_pcie_ep$tx_st_empty0),
.tx_st_eop0(pciw_pci0_pcie_ep$tx_st_eop0),
.tx_st_err0(pciw_pci0_pcie_ep$tx_st_err0),
.tx_st_sop0(pciw_pci0_pcie_ep$tx_st_sop0),
.tx_st_valid0(pciw_pci0_pcie_ep$tx_st_valid0),
.tl_cfg_add(pciw_pci0_pcie_ep$tl_cfg_add),
.tl_cfg_ctl(pciw_pci0_pcie_ep$tl_cfg_ctl),
.tl_cfg_ctl_wr(pciw_pci0_pcie_ep$tl_cfg_ctl_wr),
.tl_cfg_sts(),
.tl_cfg_sts_wr(),
.pcie_tx_out(pciw_pci0_pcie_ep$pcie_tx_out),
.ava_alive(pciw_pci0_pcie_ep$ava_alive),
.ava_lnk_up(pciw_pci0_pcie_ep$ava_lnk_up),
.ava_debug(pciw_pci0_pcie_ep$ava_debug),
.rx_st_valid0(pciw_pci0_pcie_ep$rx_st_valid0),
.rx_st_bardec0(pciw_pci0_pcie_ep$rx_st_bardec0),
.rx_st_be0(pciw_pci0_pcie_ep$rx_st_be0),
.rx_st_data0(pciw_pci0_pcie_ep$rx_st_data0),
.rx_st_sop0(pciw_pci0_pcie_ep$rx_st_sop0),
.rx_st_eop0(pciw_pci0_pcie_ep$rx_st_eop0),
.rx_st_empty0(pciw_pci0_pcie_ep$rx_st_empty0),
.rx_st_err0(),
.tx_st_ready0(pciw_pci0_pcie_ep$tx_st_ready0),
.tx_cred0(),
.tx_fifo_empty0(),
.ava_core_clk_out(pciw_pci0_pcie_ep$ava_core_clk_out),
.ava_srstn(pciw_pci0_pcie_ep$ava_srstn));
// submodule pciw_pci0_rxEofF
FIFO2 #(.width(32'd3),
.guarded(32'd1)) pciw_pci0_rxEofF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_rxEofF$D_IN),
.ENQ(pciw_pci0_rxEofF$ENQ),
.DEQ(pciw_pci0_rxEofF$DEQ),
.CLR(pciw_pci0_rxEofF$CLR),
.D_OUT(),
.FULL_N(pciw_pci0_rxEofF$FULL_N),
.EMPTY_N(pciw_pci0_rxEofF$EMPTY_N));
// submodule pciw_pci0_rxHeadF
FIFO2 #(.width(32'd31),
.guarded(32'd1)) pciw_pci0_rxHeadF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_rxHeadF$D_IN),
.ENQ(pciw_pci0_rxHeadF$ENQ),
.DEQ(pciw_pci0_rxHeadF$DEQ),
.CLR(pciw_pci0_rxHeadF$CLR),
.D_OUT(pciw_pci0_rxHeadF$D_OUT),
.FULL_N(pciw_pci0_rxHeadF$FULL_N),
.EMPTY_N(pciw_pci0_rxHeadF$EMPTY_N));
// submodule pciw_pci0_rxInF
SizedFIFO #(.p1width(32'd155),
.p2depth(32'd32),
.p3cntr_width(32'd5),
.guarded(32'd1)) pciw_pci0_rxInF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_rxInF$D_IN),
.ENQ(pciw_pci0_rxInF$ENQ),
.DEQ(pciw_pci0_rxInF$DEQ),
.CLR(pciw_pci0_rxInF$CLR),
.D_OUT(pciw_pci0_rxInF$D_OUT),
.FULL_N(pciw_pci0_rxInF$FULL_N),
.EMPTY_N(pciw_pci0_rxInF$EMPTY_N));
// submodule pciw_pci0_rxOutF
FIFO2 #(.width(32'd153),
.guarded(32'd1)) pciw_pci0_rxOutF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_rxOutF$D_IN),
.ENQ(pciw_pci0_rxOutF$ENQ),
.DEQ(pciw_pci0_rxOutF$DEQ),
.CLR(pciw_pci0_rxOutF$CLR),
.D_OUT(pciw_pci0_rxOutF$D_OUT),
.FULL_N(pciw_pci0_rxOutF$FULL_N),
.EMPTY_N(pciw_pci0_rxOutF$EMPTY_N));
// submodule pciw_pci0_txEofF
FIFO2 #(.width(32'd3),
.guarded(32'd1)) pciw_pci0_txEofF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_txEofF$D_IN),
.ENQ(pciw_pci0_txEofF$ENQ),
.DEQ(pciw_pci0_txEofF$DEQ),
.CLR(pciw_pci0_txEofF$CLR),
.D_OUT(),
.FULL_N(pciw_pci0_txEofF$FULL_N),
.EMPTY_N(pciw_pci0_txEofF$EMPTY_N));
// submodule pciw_pci0_txExF
FIFO2 #(.width(32'd1),
.guarded(32'd1)) pciw_pci0_txExF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_txExF$D_IN),
.ENQ(pciw_pci0_txExF$ENQ),
.DEQ(pciw_pci0_txExF$DEQ),
.CLR(pciw_pci0_txExF$CLR),
.D_OUT(),
.FULL_N(pciw_pci0_txExF$FULL_N),
.EMPTY_N(pciw_pci0_txExF$EMPTY_N));
// submodule pciw_pci0_txHeadF
FIFO2 #(.width(32'd31),
.guarded(32'd1)) pciw_pci0_txHeadF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_txHeadF$D_IN),
.ENQ(pciw_pci0_txHeadF$ENQ),
.DEQ(pciw_pci0_txHeadF$DEQ),
.CLR(pciw_pci0_txHeadF$CLR),
.D_OUT(pciw_pci0_txHeadF$D_OUT),
.FULL_N(pciw_pci0_txHeadF$FULL_N),
.EMPTY_N(pciw_pci0_txHeadF$EMPTY_N));
// submodule pciw_pci0_txInF
FIFO2 #(.width(32'd153),
.guarded(32'd1)) pciw_pci0_txInF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_txInF$D_IN),
.ENQ(pciw_pci0_txInF$ENQ),
.DEQ(pciw_pci0_txInF$DEQ),
.CLR(pciw_pci0_txInF$CLR),
.D_OUT(pciw_pci0_txInF$D_OUT),
.FULL_N(pciw_pci0_txInF$FULL_N),
.EMPTY_N(pciw_pci0_txInF$EMPTY_N));
// submodule pciw_pci0_txOutF
SizedFIFO #(.p1width(32'd155),
.p2depth(32'd515),
.p3cntr_width(32'd10),
.guarded(32'd1)) pciw_pci0_txOutF(.RST(pciw_pci0_pcie_ep$ava_srstn),
.CLK(pciw_pci0_pcie_ep$ava_core_clk_out),
.D_IN(pciw_pci0_txOutF$D_IN),
.ENQ(pciw_pci0_txOutF$ENQ),
.DEQ(pciw_pci0_txOutF$DEQ),
.CLR(pciw_pci0_txOutF$CLR),
.D_OUT(pciw_pci0_txOutF$D_OUT),
.FULL_N(pciw_pci0_txOutF$FULL_N),
.EMPTY_N(pciw_pci0_txOutF$EMPTY_N));
// rule RL_pciw_pci0_rx_destage
assign WILL_FIRE_RL_pciw_pci0_rx_destage =
pciw_pci0_rxDws_num_full != 4'd0 && pciw_pci0_rxHeadF$EMPTY_N &&
pciw_pci0_rxOutF$FULL_N &&
(pciw_pci0_rxDws_num_full >= 4'd4 || pciw_pci0_rxEofF$EMPTY_N) ;
// rule RL_pciw_pci0_rx_enstage
assign WILL_FIRE_RL_pciw_pci0_rx_enstage =
pciw_pci0_rxInF$EMPTY_N &&
(!pciw_pci0_rxInF$D_OUT[153] || pciw_pci0_rxHeadF$FULL_N) &&
(!pciw_pci0_rxInF$D_OUT[152] || pciw_pci0_rxEofF$FULL_N) &&
pciw_pci0_rxDws_num_empty >= 4'd4 ;
// rule RL_pciw_pci0_tx_exstage
assign WILL_FIRE_RL_pciw_pci0_tx_exstage =
pciw_pci0_txOutF$EMPTY_N && pciw_pci0_txReadyD &&
pciw_pci0_txExF$EMPTY_N ;
// rule RL_pciw_pci0_tx_destage
assign WILL_FIRE_RL_pciw_pci0_tx_destage =
pciw_pci0_txDws_num_full != 4'd0 &&
pciw_pci0_txOutF_i_notFull__48_AND_pciw_pci0_t_ETC___d502 &&
(pciw_pci0_txDws_num_full >= 4'd4 || pciw_pci0_txEofF$EMPTY_N) ;
// rule RL_pciw_pci0_tx_enstage
assign WILL_FIRE_RL_pciw_pci0_tx_enstage =
pciw_pci0_txInF$EMPTY_N &&
(!pciw_pci0_txInF$D_OUT[152] || pciw_pci0_txHeadF$FULL_N) &&
(!pciw_pci0_txInF$D_OUT[151] || pciw_pci0_txEofF$FULL_N) &&
pciw_pci0_txDws_num_empty >= 4'd4 ;
// rule RL_pciw_pci0_rxInF_reset
assign WILL_FIRE_RL_pciw_pci0_rxInF_reset =
MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ||
WILL_FIRE_RL_pciw_pci0_rx_enstage ;
// rule RL_pciw_pci0_txOutF_reset
assign WILL_FIRE_RL_pciw_pci0_txOutF_reset =
WILL_FIRE_RL_pciw_pci0_tx_destage ||
WILL_FIRE_RL_pciw_pci0_tx_exstage ;
// inputs to muxes for submodule ports
assign MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 =
pciw_pci0_rxInF$FULL_N && pciw_pci0_pcie_ep$rx_st_valid0 ;
// inlined wires
assign pciw_pci0_avaTxValid$wget = 1'd1 ;
assign pciw_pci0_avaTxValid$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
assign pciw_pci0_avaTxErr$wget = 1'b0 ;
assign pciw_pci0_avaTxErr$whas = 1'b0 ;
assign pciw_pci0_avaTxSop$wget = pciw_pci0_txOutF$D_OUT[153] ;
assign pciw_pci0_avaTxSop$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
assign pciw_pci0_avaTxEop$wget = pciw_pci0_txOutF$D_OUT[152] ;
assign pciw_pci0_avaTxEop$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
assign pciw_pci0_avaTxEmpty$wget = pciw_pci0_txOutF$D_OUT[154] ;
assign pciw_pci0_avaTxEmpty$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
assign pciw_pci0_rxDws_delta_enq$wget =
(pciw_pci0_rxInF$D_OUT[153] && !pciw_pci0_rxInF$D_OUT[30] &&
!pciw_pci0_rxInF$D_OUT[29]) ?
3'd3 :
((pciw_pci0_rxInF$D_OUT[153] &&
(pciw_pci0_rxInF$D_OUT[29] ||
pciw_pci0_rxInF$D_OUT[30] && pciw_pci0_rxInF$D_OUT[66])) ?
3'd4 :
((pciw_pci0_rxInF$D_OUT[153] && pciw_pci0_rxInF$D_OUT[30] &&
!pciw_pci0_rxInF$D_OUT[29] &&
!pciw_pci0_rxInF$D_OUT[66]) ?
3'd3 :
((!pciw_pci0_rxInF$D_OUT[153] &&
!pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:128] == 16'hFFFF) ?
3'd4 :
((!pciw_pci0_rxInF$D_OUT[153] &&
!pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:128] == 16'h0FFF) ?
3'd3 :
((!pciw_pci0_rxInF$D_OUT[153] &&
pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:136] == 8'hFF) ?
3'd2 :
((!pciw_pci0_rxInF$D_OUT[153] &&
pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:136] == 8'h0F) ?
3'd1 :
3'd0)))))) ;
assign pciw_pci0_rxDws_delta_enq$whas = WILL_FIRE_RL_pciw_pci0_rx_enstage ;
assign pciw_pci0_rxDws_delta_deq$wget =
IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] ;
assign pciw_pci0_rxDws_delta_deq$whas = WILL_FIRE_RL_pciw_pci0_rx_destage ;
assign pciw_pci0_rxDws_new_data$wget =
pciw_pci0_rxInF$D_OUT[153] ?
{ pciw_pci0_rxInF$D_OUT[29] ?
{ pciw_pci0_rxInF$D_OUT[103:96],
pciw_pci0_rxInF$D_OUT[111:104],
pciw_pci0_rxInF$D_OUT[119:112],
pciw_pci0_rxInF$D_OUT[127:120] } :
pciw_pci0_rxInF$D_OUT[127:96],
pciw_pci0_rxInF$D_OUT[71:64],
pciw_pci0_rxInF$D_OUT[79:72],
pciw_pci0_rxInF$D_OUT[87:80],
pciw_pci0_rxInF$D_OUT[95:88],
pciw_pci0_rxInF$D_OUT[39:32],
pciw_pci0_rxInF$D_OUT[47:40],
pciw_pci0_rxInF$D_OUT[55:48],
pciw_pci0_rxInF$D_OUT[63:56],
pciw_pci0_rxInF$D_OUT[7:0],
pciw_pci0_rxInF$D_OUT[15:8],
pciw_pci0_rxInF$D_OUT[23:16],
pciw_pci0_rxInF$D_OUT[31:24] } :
pciw_pci0_rxInF$D_OUT[127:0] ;
assign pciw_pci0_rxDws_new_data$whas = WILL_FIRE_RL_pciw_pci0_rx_enstage ;
assign pciw_pci0_txDws_delta_enq$wget =
(pciw_pci0_txInF$D_OUT[152] && !pciw_pci0_txInF$D_OUT[126] &&
!pciw_pci0_txInF$D_OUT[125]) ?
3'd3 :
((pciw_pci0_txInF$D_OUT[152] &&
(pciw_pci0_txInF$D_OUT[125] ||
pciw_pci0_txInF$D_OUT[126] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFFF)) ?
3'd4 :
((pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[126] &&
!pciw_pci0_txInF$D_OUT[125] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFF0) ?
3'd3 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFFF) ?
3'd4 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFF0) ?
3'd3 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFF00) ?
3'd2 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hF000) ?
3'd1 :
3'd0)))))) ;
assign pciw_pci0_txDws_delta_enq$whas = WILL_FIRE_RL_pciw_pci0_tx_enstage ;
assign pciw_pci0_txDws_delta_deq$wget =
IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] ;
assign pciw_pci0_txDws_delta_deq$whas = WILL_FIRE_RL_pciw_pci0_tx_destage ;
assign pciw_pci0_txDws_new_data$wget =
{ pciw_pci0_txInF$D_OUT[7:0],
pciw_pci0_txInF$D_OUT[15:8],
pciw_pci0_txInF$D_OUT[23:16],
pciw_pci0_txInF$D_OUT[31:24],
pciw_pci0_txInF$D_OUT[39:32],
pciw_pci0_txInF$D_OUT[47:40],
pciw_pci0_txInF$D_OUT[55:48],
pciw_pci0_txInF$D_OUT[63:56],
pciw_pci0_txInF$D_OUT[71:64],
pciw_pci0_txInF$D_OUT[79:72],
pciw_pci0_txInF$D_OUT[87:80],
pciw_pci0_txInF$D_OUT[95:88],
pciw_pci0_txInF$D_OUT[103:96],
pciw_pci0_txInF$D_OUT[111:104],
pciw_pci0_txInF$D_OUT[119:112],
pciw_pci0_txInF$D_OUT[127:120] } ;
assign pciw_pci0_txDws_new_data$whas = WILL_FIRE_RL_pciw_pci0_tx_enstage ;
assign pciw_pci0_rxInF_r_enq$whas =
MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ;
assign pciw_pci0_rxInF_r_deq$whas = WILL_FIRE_RL_pciw_pci0_rx_enstage ;
assign pciw_pci0_rxInF_r_clr$whas = 1'b0 ;
assign pciw_pci0_rxInF_doResetEnq$whas =
MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ;
assign pciw_pci0_rxInF_doResetDeq$whas = WILL_FIRE_RL_pciw_pci0_rx_enstage ;
assign pciw_pci0_rxInF_doResetClr$whas = 1'b0 ;
assign pciw_pci0_txOutF_r_enq$whas = WILL_FIRE_RL_pciw_pci0_tx_destage ;
assign pciw_pci0_txOutF_r_deq$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
assign pciw_pci0_txOutF_r_clr$whas = 1'b0 ;
assign pciw_pci0_txOutF_doResetEnq$whas =
WILL_FIRE_RL_pciw_pci0_tx_destage ;
assign pciw_pci0_txOutF_doResetDeq$whas =
WILL_FIRE_RL_pciw_pci0_tx_exstage ;
assign pciw_pci0_txOutF_doResetClr$whas = 1'b0 ;
assign infLed$wget = ctop$led ;
// register freeCnt
assign freeCnt$D_IN = freeCnt + 32'd1 ;
assign freeCnt$EN = 1'd1 ;
// register hsmcReg
assign hsmcReg$D_IN = hsmc_in_i ;
assign hsmcReg$EN = 1'd1 ;
// register ledReg
assign ledReg$D_IN =
{ 6'd31,
~ctop$led,
INV_swReg_35_BIT_0_36_XOR_swReg_35_BIT_1_37_38_ETC___d764 } ;
assign ledReg$EN = 1'd1 ;
// register needs_init
assign needs_init$D_IN = 1'd0 ;
assign needs_init$EN = needs_init ;
// register pciDevice
assign pciDevice$D_IN = pciw_pciDevice ;
assign pciDevice$EN = 1'd1 ;
// register pciw_pci0_cfgDataWr
assign pciw_pci0_cfgDataWr$D_IN = pciw_pci0_pcie_ep$tl_cfg_ctl_wr ;
assign pciw_pci0_cfgDataWr$EN = 1'd1 ;
// register pciw_pci0_cfgSample
assign pciw_pci0_cfgSample$D_IN =
pciw_pci0_cfgDataWr != pciw_pci0_pcie_ep$tl_cfg_ctl_wr ;
assign pciw_pci0_cfgSample$EN = 1'd1 ;
// register pciw_pci0_deviceReg
assign pciw_pci0_deviceReg$D_IN =
{ pciw_pci0_pcie_ep$tl_cfg_ctl[12:0], 3'd0 } ;
assign pciw_pci0_deviceReg$EN =
pciw_pci0_cfgSample && pciw_pci0_pcie_ep$tl_cfg_add == 4'hF ;
// register pciw_pci0_rxDbgDeDeq
assign pciw_pci0_rxDbgDeDeq$D_IN =
pciw_pci0_rxDbgDeDeq +
{ 13'd0,
IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] } ;
assign pciw_pci0_rxDbgDeDeq$EN = WILL_FIRE_RL_pciw_pci0_rx_destage ;
// register pciw_pci0_rxDbgDeEof
assign pciw_pci0_rxDbgDeEof$D_IN = pciw_pci0_rxDbgDeEof + 16'd1 ;
assign pciw_pci0_rxDbgDeEof$EN =
WILL_FIRE_RL_pciw_pci0_rx_destage && pciw_pci0_rxEofF$EMPTY_N &&
pciw_pci0_rxDws_num_full_7_ULE_4___d836 ;
// register pciw_pci0_rxDbgDeSof
assign pciw_pci0_rxDbgDeSof$D_IN = pciw_pci0_rxDbgDeSof + 16'd1 ;
assign pciw_pci0_rxDbgDeSof$EN =
WILL_FIRE_RL_pciw_pci0_rx_destage && !pciw_pci0_rxInFlight ;
// register pciw_pci0_rxDbgDestage
assign pciw_pci0_rxDbgDestage$D_IN = pciw_pci0_rxDbgDestage + 16'd1 ;
assign pciw_pci0_rxDbgDestage$EN = WILL_FIRE_RL_pciw_pci0_rx_destage ;
// register pciw_pci0_rxDbgEnEnq
assign pciw_pci0_rxDbgEnEnq$D_IN =
pciw_pci0_rxDbgEnEnq +
{ 13'd0,
(pciw_pci0_rxInF$D_OUT[153] && !pciw_pci0_rxInF$D_OUT[30] &&
!pciw_pci0_rxInF$D_OUT[29]) ?
3'd3 :
((pciw_pci0_rxInF$D_OUT[153] &&
(pciw_pci0_rxInF$D_OUT[29] ||
pciw_pci0_rxInF$D_OUT[30] && pciw_pci0_rxInF$D_OUT[66])) ?
3'd4 :
((pciw_pci0_rxInF$D_OUT[153] &&
pciw_pci0_rxInF$D_OUT[30] &&
!pciw_pci0_rxInF$D_OUT[29] &&
!pciw_pci0_rxInF$D_OUT[66]) ?
3'd3 :
((!pciw_pci0_rxInF$D_OUT[153] &&
!pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:128] == 16'hFFFF) ?
3'd4 :
((!pciw_pci0_rxInF$D_OUT[153] &&
!pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:128] == 16'h0FFF) ?
3'd3 :
((!pciw_pci0_rxInF$D_OUT[153] &&
pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:136] == 8'hFF) ?
3'd2 :
((!pciw_pci0_rxInF$D_OUT[153] &&
pciw_pci0_rxInF$D_OUT[154] &&
pciw_pci0_rxInF$D_OUT[143:136] == 8'h0F) ?
3'd1 :
3'd0)))))) } ;
assign pciw_pci0_rxDbgEnEnq$EN = WILL_FIRE_RL_pciw_pci0_rx_enstage ;
// register pciw_pci0_rxDbgEnEof
assign pciw_pci0_rxDbgEnEof$D_IN = pciw_pci0_rxDbgEnEof + 16'd1 ;
assign pciw_pci0_rxDbgEnEof$EN =
WILL_FIRE_RL_pciw_pci0_rx_enstage && pciw_pci0_rxInF$D_OUT[152] ;
// register pciw_pci0_rxDbgEnSof
assign pciw_pci0_rxDbgEnSof$D_IN = pciw_pci0_rxDbgEnSof + 16'd1 ;
assign pciw_pci0_rxDbgEnSof$EN =
WILL_FIRE_RL_pciw_pci0_rx_enstage && pciw_pci0_rxInF$D_OUT[153] ;
// register pciw_pci0_rxDbgEnstage
assign pciw_pci0_rxDbgEnstage$D_IN = pciw_pci0_rxDbgEnstage + 16'd1 ;
assign pciw_pci0_rxDbgEnstage$EN = WILL_FIRE_RL_pciw_pci0_rx_enstage ;
// register pciw_pci0_rxDbgInstage
assign pciw_pci0_rxDbgInstage$D_IN = pciw_pci0_rxDbgInstage + 16'd1 ;
assign pciw_pci0_rxDbgInstage$EN =
MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ;
// register pciw_pci0_rxDwrDeq
assign pciw_pci0_rxDwrDeq$D_IN =
pciw_pci0_rxInFlight ?
pciw_pci0_rxDwrDeq -
{ 8'd0,
IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] } :
IF_pciw_pci0_rxEofF_notEmpty__62_AND_pciw_pci0_ETC___d288 ;
assign pciw_pci0_rxDwrDeq$EN = WILL_FIRE_RL_pciw_pci0_rx_destage ;
// register pciw_pci0_rxDwrEnq
assign pciw_pci0_rxDwrEnq$D_IN = 11'h0 ;
assign pciw_pci0_rxDwrEnq$EN = 1'b0 ;
// register pciw_pci0_rxDws_num_empty
assign pciw_pci0_rxDws_num_empty$D_IN =
pciw_pci0_rxDws_num_empty +
{ 1'd0,
IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801 } -
{ 1'd0,
IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 } ;
assign pciw_pci0_rxDws_num_empty$EN = 1'd1 ;
// register pciw_pci0_rxDws_num_full
assign pciw_pci0_rxDws_num_full$D_IN =
pciw_pci0_rxDws_num_full +
{ 1'd0,
IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 } -
{ 1'd0,
IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801 } ;
assign pciw_pci0_rxDws_num_full$EN = 1'd1 ;
// register pciw_pci0_rxDws_vec
assign pciw_pci0_rxDws_vec$D_IN =
{ (WILL_FIRE_RL_pciw_pci0_rx_enstage ?
_0_CONCAT_pciw_pci0_rxDws_new_data_wget__2_BITS_ETC___d832[255:32] :
224'd0) |
pciw_pci0_rxDws_vec_3_SRL_IF_pciw_pci0_rxDws_d_ETC___d834[255:32],
(WILL_FIRE_RL_pciw_pci0_rx_enstage ?
_0_CONCAT_pciw_pci0_rxDws_new_data_wget__2_BITS_ETC___d832[31:0] :
32'd0) |
pciw_pci0_rxDws_vec_3_SRL_IF_pciw_pci0_rxDws_d_ETC___d834[31:0] } ;
assign pciw_pci0_rxDws_vec$EN = 1'd1 ;
// register pciw_pci0_rxInF_countReg
assign pciw_pci0_rxInF_countReg$D_IN =
MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ?
pciw_pci0_rxInF_countReg + 6'd1 :
pciw_pci0_rxInF_countReg - 6'd1 ;
assign pciw_pci0_rxInF_countReg$EN =
MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 !=
WILL_FIRE_RL_pciw_pci0_rx_enstage ;
// register pciw_pci0_rxInF_levelsValid
assign pciw_pci0_rxInF_levelsValid$D_IN =
WILL_FIRE_RL_pciw_pci0_rxInF_reset ;
assign pciw_pci0_rxInF_levelsValid$EN =
WILL_FIRE_RL_pciw_pci0_rx_enstage ||
pciw_pci0_rxInF$FULL_N && pciw_pci0_pcie_ep$rx_st_valid0 ||
WILL_FIRE_RL_pciw_pci0_rxInF_reset ;
// register pciw_pci0_rxInFlight
assign pciw_pci0_rxInFlight$D_IN =
!pciw_pci0_rxEofF$EMPTY_N ||
!pciw_pci0_rxDws_num_full_7_ULE_4___d836 ;
assign pciw_pci0_rxInFlight$EN = WILL_FIRE_RL_pciw_pci0_rx_destage ;
// register pciw_pci0_txDbgDeDeq
assign pciw_pci0_txDbgDeDeq$D_IN =
pciw_pci0_txDbgDeDeq +
{ 13'd0,
IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] } ;
assign pciw_pci0_txDbgDeDeq$EN = WILL_FIRE_RL_pciw_pci0_tx_destage ;
// register pciw_pci0_txDbgDeEof
assign pciw_pci0_txDbgDeEof$D_IN = pciw_pci0_txDbgDeEof + 16'd1 ;
assign pciw_pci0_txDbgDeEof$EN =
WILL_FIRE_RL_pciw_pci0_tx_destage &&
pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ;
// register pciw_pci0_txDbgDeSof
assign pciw_pci0_txDbgDeSof$D_IN = pciw_pci0_txDbgDeSof + 16'd1 ;
assign pciw_pci0_txDbgDeSof$EN =
WILL_FIRE_RL_pciw_pci0_tx_destage && !pciw_pci0_txInFlight ;
// register pciw_pci0_txDbgDestage
assign pciw_pci0_txDbgDestage$D_IN = pciw_pci0_txDbgDestage + 16'd1 ;
assign pciw_pci0_txDbgDestage$EN = WILL_FIRE_RL_pciw_pci0_tx_destage ;
// register pciw_pci0_txDbgEnEnq
assign pciw_pci0_txDbgEnEnq$D_IN =
pciw_pci0_txDbgEnEnq +
{ 13'd0,
(pciw_pci0_txInF$D_OUT[152] && !pciw_pci0_txInF$D_OUT[126] &&
!pciw_pci0_txInF$D_OUT[125]) ?
3'd3 :
((pciw_pci0_txInF$D_OUT[152] &&
(pciw_pci0_txInF$D_OUT[125] ||
pciw_pci0_txInF$D_OUT[126] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFFF)) ?
3'd4 :
((pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[126] &&
!pciw_pci0_txInF$D_OUT[125] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFF0) ?
3'd3 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFFF) ?
3'd4 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFFF0) ?
3'd3 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] == 16'hFF00) ?
3'd2 :
((!pciw_pci0_txInF$D_OUT[152] &&
pciw_pci0_txInF$D_OUT[143:128] ==
16'hF000) ?
3'd1 :
3'd0)))))) } ;
assign pciw_pci0_txDbgEnEnq$EN = WILL_FIRE_RL_pciw_pci0_tx_enstage ;
// register pciw_pci0_txDbgEnEof
assign pciw_pci0_txDbgEnEof$D_IN = pciw_pci0_txDbgEnEof + 16'd1 ;
assign pciw_pci0_txDbgEnEof$EN =
WILL_FIRE_RL_pciw_pci0_tx_enstage && pciw_pci0_txInF$D_OUT[151] ;
// register pciw_pci0_txDbgEnSof
assign pciw_pci0_txDbgEnSof$D_IN = pciw_pci0_txDbgEnSof + 16'd1 ;
assign pciw_pci0_txDbgEnSof$EN =
WILL_FIRE_RL_pciw_pci0_tx_enstage && pciw_pci0_txInF$D_OUT[152] ;
// register pciw_pci0_txDbgEnstage
assign pciw_pci0_txDbgEnstage$D_IN = pciw_pci0_txDbgEnstage + 16'd1 ;
assign pciw_pci0_txDbgEnstage$EN = WILL_FIRE_RL_pciw_pci0_tx_enstage ;
// register pciw_pci0_txDbgExstage
assign pciw_pci0_txDbgExstage$D_IN = pciw_pci0_txDbgExstage + 16'd1 ;
assign pciw_pci0_txDbgExstage$EN = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
// register pciw_pci0_txDwrDeq
assign pciw_pci0_txDwrDeq$D_IN =
pciw_pci0_txInFlight ?
pciw_pci0_txDwrDeq -
{ 8'd0,
IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] } :
IF_pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_ETC___d523 ;
assign pciw_pci0_txDwrDeq$EN = WILL_FIRE_RL_pciw_pci0_tx_destage ;
// register pciw_pci0_txDwrEnq
assign pciw_pci0_txDwrEnq$D_IN = 11'h0 ;
assign pciw_pci0_txDwrEnq$EN = 1'b0 ;
// register pciw_pci0_txDws_num_empty
assign pciw_pci0_txDws_num_empty$D_IN =
pciw_pci0_txDws_num_empty +
{ 1'd0,
IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804 } -
{ 1'd0,
IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 } ;
assign pciw_pci0_txDws_num_empty$EN = 1'd1 ;
// register pciw_pci0_txDws_num_full
assign pciw_pci0_txDws_num_full$D_IN =
pciw_pci0_txDws_num_full +
{ 1'd0,
IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 } -
{ 1'd0,
IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804 } ;
assign pciw_pci0_txDws_num_full$EN = 1'd1 ;
// register pciw_pci0_txDws_vec
assign pciw_pci0_txDws_vec$D_IN =
{ (WILL_FIRE_RL_pciw_pci0_tx_enstage ?
_0_CONCAT_pciw_pci0_txDws_new_data_wget__8_BITS_ETC___d833[255:32] :
224'd0) |
pciw_pci0_txDws_vec_9_SRL_IF_pciw_pci0_txDws_d_ETC___d835[255:32],
(WILL_FIRE_RL_pciw_pci0_tx_enstage ?
_0_CONCAT_pciw_pci0_txDws_new_data_wget__8_BITS_ETC___d833[31:0] :
32'd0) |
pciw_pci0_txDws_vec_9_SRL_IF_pciw_pci0_txDws_d_ETC___d835[31:0] } ;
assign pciw_pci0_txDws_vec$EN = 1'd1 ;
// register pciw_pci0_txInFlight
assign pciw_pci0_txInFlight$D_IN =
NOT_pciw_pci0_txEofF_notEmpty__52_53_OR_NOT_pc_ETC___d495 ;
assign pciw_pci0_txInFlight$EN = WILL_FIRE_RL_pciw_pci0_tx_destage ;
// register pciw_pci0_txOutF_countReg
assign pciw_pci0_txOutF_countReg$D_IN =
WILL_FIRE_RL_pciw_pci0_tx_destage ?
pciw_pci0_txOutF_countReg + 10'd1 :
pciw_pci0_txOutF_countReg - 10'd1 ;
assign pciw_pci0_txOutF_countReg$EN =
WILL_FIRE_RL_pciw_pci0_tx_destage !=
WILL_FIRE_RL_pciw_pci0_tx_exstage ;
// register pciw_pci0_txOutF_levelsValid
assign pciw_pci0_txOutF_levelsValid$D_IN =
WILL_FIRE_RL_pciw_pci0_txOutF_reset ;
assign pciw_pci0_txOutF_levelsValid$EN =
WILL_FIRE_RL_pciw_pci0_tx_exstage ||
WILL_FIRE_RL_pciw_pci0_tx_destage ||
WILL_FIRE_RL_pciw_pci0_txOutF_reset ;
// register pciw_pci0_txReadyD
assign pciw_pci0_txReadyD$D_IN = pciw_pci0_pcie_ep$tx_st_ready0 ;
assign pciw_pci0_txReadyD$EN = 1'd1 ;
// register pciw_pciDevice
assign pciw_pciDevice$D_IN = pciw_pci0_deviceReg ;
assign pciw_pciDevice$EN = 1'd1 ;
// register swReg
assign swReg$D_IN = usr_sw_i ;
assign swReg$EN = 1'd1 ;
// submodule ctop
assign ctop$cpServer_request_put = 59'h0 ;
assign ctop$gps_ppsSyncIn_x = gps_ppsSyncIn_x ;
assign ctop$server_request_put = pciw_p2iF$D_OUT ;
assign ctop$switch_x = 3'h0 ;
assign ctop$wci_m_0_SData = 32'h0 ;
assign ctop$wci_m_0_SFlag = 2'h0 ;
assign ctop$wci_m_0_SResp = 2'h0 ;
assign ctop$wci_m_1_SData = flash0$wciS0_SData ;
assign ctop$wci_m_1_SFlag = flash0$wciS0_SFlag ;
assign ctop$wci_m_1_SResp = flash0$wciS0_SResp ;
assign ctop$wci_m_2_SData = 32'h0 ;
assign ctop$wci_m_2_SFlag = 2'h0 ;
assign ctop$wci_m_2_SResp = 2'h0 ;
assign ctop$wci_m_3_SData = 32'h0 ;
assign ctop$wci_m_3_SFlag = 2'h0 ;
assign ctop$wci_m_3_SResp = 2'h0 ;
assign ctop$wci_m_4_SData = dram0$wciS0_SData ;
assign ctop$wci_m_4_SFlag = dram0$wciS0_SFlag ;
assign ctop$wci_m_4_SResp = dram0$wciS0_SResp ;
assign ctop$wmemiM0_SData = dram0$wmemiS0_SData ;
assign ctop$wmemiM0_SResp = dram0$wmemiS0_SResp ;
assign ctop$wsi_s_adc_MBurstLength = 12'h0 ;
assign ctop$wsi_s_adc_MByteEn = 4'h0 ;
assign ctop$wsi_s_adc_MCmd = 3'h0 ;
assign ctop$wsi_s_adc_MData = 32'h0 ;
assign ctop$wsi_s_adc_MReqInfo = 8'h0 ;
assign ctop$EN_server_request_put =
ctop$RDY_server_request_put && pciw_p2iF$EMPTY_N ;
assign ctop$EN_server_response_get =
ctop$RDY_server_response_get && pciw_i2pF$FULL_N ;
assign ctop$EN_cpServer_request_put = 1'b0 ;
assign ctop$EN_cpServer_response_get = 1'b0 ;
assign ctop$wci_m_0_SThreadBusy = 1'b0 ;
assign ctop$wci_m_1_SThreadBusy = flash0$wciS0_SThreadBusy ;
assign ctop$wci_m_2_SThreadBusy = 1'b0 ;
assign ctop$wci_m_3_SThreadBusy = 1'b0 ;
assign ctop$wci_m_4_SThreadBusy = dram0$wciS0_SThreadBusy ;
assign ctop$wsi_s_adc_MReqLast = 1'b0 ;
assign ctop$wsi_s_adc_MBurstPrecise = 1'b0 ;
assign ctop$wsi_s_adc_MReset_n = 1'b0 ;
assign ctop$wsi_m_dac_SThreadBusy = 1'b0 ;
assign ctop$wsi_m_dac_SReset_n = 1'b0 ;
assign ctop$wmemiM0_SRespLast = dram0$wmemiS0_SRespLast ;
assign ctop$wmemiM0_SCmdAccept = dram0$wmemiS0_SCmdAccept ;
assign ctop$wmemiM0_SDataAccept = dram0$wmemiS0_SDataAccept ;
// submodule dram0
assign dram0$dram_rdn_i = dram_rdn_i ;
assign dram0$dram_rup_i = dram_rup_i ;
assign dram0$wciS0_MAddr = ctop$wci_m_4_MAddr ;
assign dram0$wciS0_MAddrSpace = ctop$wci_m_4_MAddrSpace ;
assign dram0$wciS0_MByteEn = ctop$wci_m_4_MByteEn ;
assign dram0$wciS0_MCmd = ctop$wci_m_4_MCmd ;
assign dram0$wciS0_MData = ctop$wci_m_4_MData ;
assign dram0$wciS0_MFlag = ctop$wci_m_4_MFlag ;
assign dram0$wmemiS0_MAddr = ctop$wmemiM0_MAddr ;
assign dram0$wmemiS0_MBurstLength = ctop$wmemiM0_MBurstLength ;
assign dram0$wmemiS0_MCmd = ctop$wmemiM0_MCmd ;
assign dram0$wmemiS0_MData = ctop$wmemiM0_MData ;
assign dram0$wmemiS0_MDataByteEn = ctop$wmemiM0_MDataByteEn ;
assign dram0$wmemiS0_MReqLast = ctop$wmemiM0_MReqLast ;
assign dram0$wmemiS0_MDataValid = ctop$wmemiM0_MDataValid ;
assign dram0$wmemiS0_MDataLast = ctop$wmemiM0_MDataLast ;
assign dram0$wmemiS0_MReset_n = ctop$wmemiM0_MReset_n ;
// submodule flash0
assign flash0$flash_fwait_i = flash_fwait_i ;
assign flash0$wciS0_MAddr = ctop$wci_m_1_MAddr ;
assign flash0$wciS0_MAddrSpace = ctop$wci_m_1_MAddrSpace ;
assign flash0$wciS0_MByteEn = ctop$wci_m_1_MByteEn ;
assign flash0$wciS0_MCmd = ctop$wci_m_1_MCmd ;
assign flash0$wciS0_MData = ctop$wci_m_1_MData ;
assign flash0$wciS0_MFlag = ctop$wci_m_1_MFlag ;
// submodule lcd_ctrl
assign lcd_ctrl$setLine1_text = 128'h202073656C75522063696D6F74412020 ;
assign lcd_ctrl$setLine2_text = 128'h203474736C61203A204950436E65704F ;
assign lcd_ctrl$EN_setLine1 = needs_init ;
assign lcd_ctrl$EN_setLine2 = needs_init ;
// submodule pciw_aliveLed_sb
assign pciw_aliveLed_sb$sD_IN = pciw_pci0_pcie_ep$ava_alive ;
assign pciw_aliveLed_sb$sEN = 1'd1 ;
// submodule pciw_i2pF
assign pciw_i2pF$D_IN = ctop$server_response_get ;
assign pciw_i2pF$ENQ = ctop$RDY_server_response_get && pciw_i2pF$FULL_N ;
assign pciw_i2pF$DEQ = pciw_i2pF$EMPTY_N && pciw_pci0_txInF$FULL_N ;
assign pciw_i2pF$CLR = 1'b0 ;
// submodule pciw_linkLed_sb
assign pciw_linkLed_sb$sD_IN = pciw_pci0_pcie_ep$ava_lnk_up ;
assign pciw_linkLed_sb$sEN = 1'd1 ;
// submodule pciw_p2iF
assign pciw_p2iF$D_IN = pciw_pci0_rxOutF$D_OUT ;
assign pciw_p2iF$ENQ = pciw_pci0_rxOutF$EMPTY_N && pciw_p2iF$FULL_N ;
assign pciw_p2iF$DEQ = ctop$RDY_server_request_put && pciw_p2iF$EMPTY_N ;
assign pciw_p2iF$CLR = 1'b0 ;
// submodule pciw_pci0_pcie_ep
assign pciw_pci0_pcie_ep$pcie_rx_in = pcie_rx_i ;
assign pciw_pci0_pcie_ep$rx_st_mask0 = 1'd0 ;
assign pciw_pci0_pcie_ep$rx_st_ready0 = pciw_pci0_rxInF_countReg < 6'd30 ;
assign pciw_pci0_pcie_ep$tx_st_data0 = pciw_pci0_txOutF$D_OUT[127:0] ;
assign pciw_pci0_pcie_ep$tx_st_empty0 =
WILL_FIRE_RL_pciw_pci0_tx_exstage &&
pciw_pci0_txOutF$D_OUT[154] ;
assign pciw_pci0_pcie_ep$tx_st_eop0 =
WILL_FIRE_RL_pciw_pci0_tx_exstage &&
pciw_pci0_txOutF$D_OUT[152] ;
assign pciw_pci0_pcie_ep$tx_st_err0 = 1'b0 ;
assign pciw_pci0_pcie_ep$tx_st_sop0 =
WILL_FIRE_RL_pciw_pci0_tx_exstage &&
pciw_pci0_txOutF$D_OUT[153] ;
assign pciw_pci0_pcie_ep$tx_st_valid0 = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
// submodule pciw_pci0_rxEofF
assign pciw_pci0_rxEofF$D_IN = 3'b010 /* unspecified value */ ;
assign pciw_pci0_rxEofF$ENQ =
WILL_FIRE_RL_pciw_pci0_rx_enstage && pciw_pci0_rxInF$D_OUT[152] ;
assign pciw_pci0_rxEofF$DEQ =
WILL_FIRE_RL_pciw_pci0_rx_destage && pciw_pci0_rxEofF$EMPTY_N &&
pciw_pci0_rxDws_num_full_7_ULE_4___d836 ;
assign pciw_pci0_rxEofF$CLR = 1'b0 ;
// submodule pciw_pci0_rxHeadF
assign pciw_pci0_rxHeadF$D_IN =
{ pciw_pci0_rxInF$D_OUT[151:144],
pciw_pci0_rxInF$D_OUT[9:0],
pciw_pci0_rxInF$D_OUT[30:29],
(pciw_pci0_rxInF$D_OUT[29] ? 11'd4 : 11'd3) +
(pciw_pci0_rxInF$D_OUT[30] ?
((pciw_pci0_rxInF$D_OUT[9:0] == 10'd0) ?
11'd1024 :
{ 1'd0, pciw_pci0_rxInF$D_OUT[9:0] }) :
11'd0) } ;
assign pciw_pci0_rxHeadF$ENQ =
WILL_FIRE_RL_pciw_pci0_rx_enstage && pciw_pci0_rxInF$D_OUT[153] ;
assign pciw_pci0_rxHeadF$DEQ =
WILL_FIRE_RL_pciw_pci0_rx_destage && pciw_pci0_rxEofF$EMPTY_N &&
pciw_pci0_rxDws_num_full_7_ULE_4___d836 ;
assign pciw_pci0_rxHeadF$CLR = 1'b0 ;
// submodule pciw_pci0_rxInF
assign pciw_pci0_rxInF$D_IN =
{ pciw_pci0_pcie_ep$rx_st_empty0,
pciw_pci0_pcie_ep$rx_st_sop0,
pciw_pci0_pcie_ep$rx_st_eop0,
x_hit__h22096,
pciw_pci0_pcie_ep$rx_st_be0,
pciw_pci0_pcie_ep$rx_st_data0 } ;
assign pciw_pci0_rxInF$ENQ =
MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ;
assign pciw_pci0_rxInF$DEQ = WILL_FIRE_RL_pciw_pci0_rx_enstage ;
assign pciw_pci0_rxInF$CLR = 1'b0 ;
// submodule pciw_pci0_rxOutF
assign pciw_pci0_rxOutF$D_IN =
{ !pciw_pci0_rxInFlight,
pciw_pci0_rxEofF$EMPTY_N &&
pciw_pci0_rxDws_num_full_7_ULE_4___d836,
pciw_pci0_rxHeadF$D_OUT[29:23],
x_be__h27614,
x_data__h27615 } ;
assign pciw_pci0_rxOutF$ENQ = WILL_FIRE_RL_pciw_pci0_rx_destage ;
assign pciw_pci0_rxOutF$DEQ = pciw_pci0_rxOutF$EMPTY_N && pciw_p2iF$FULL_N ;
assign pciw_pci0_rxOutF$CLR = 1'b0 ;
// submodule pciw_pci0_txEofF
assign pciw_pci0_txEofF$D_IN = 3'b010 /* unspecified value */ ;
assign pciw_pci0_txEofF$ENQ =
WILL_FIRE_RL_pciw_pci0_tx_enstage && pciw_pci0_txInF$D_OUT[151] ;
assign pciw_pci0_txEofF$DEQ =
WILL_FIRE_RL_pciw_pci0_tx_destage &&
pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ;
assign pciw_pci0_txEofF$CLR = 1'b0 ;
// submodule pciw_pci0_txExF
assign pciw_pci0_txExF$D_IN = 1'd0 ;
assign pciw_pci0_txExF$ENQ =
WILL_FIRE_RL_pciw_pci0_tx_destage &&
pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ;
assign pciw_pci0_txExF$DEQ =
WILL_FIRE_RL_pciw_pci0_tx_exstage &&
pciw_pci0_txOutF$D_OUT[152] ;
assign pciw_pci0_txExF$CLR = 1'b0 ;
// submodule pciw_pci0_txHeadF
assign pciw_pci0_txHeadF$D_IN =
{ 8'd0,
pciw_pci0_txInF$D_OUT[105:96],
pciw_pci0_txInF$D_OUT[126:125],
(pciw_pci0_txInF$D_OUT[125] ? 11'd4 : 11'd3) +
(pciw_pci0_txInF$D_OUT[126] ?
((pciw_pci0_txInF$D_OUT[105:96] == 10'd0) ?
11'd1024 :
{ 1'd0, pciw_pci0_txInF$D_OUT[105:96] }) :
11'd0) } ;
assign pciw_pci0_txHeadF$ENQ =
WILL_FIRE_RL_pciw_pci0_tx_enstage && pciw_pci0_txInF$D_OUT[152] ;
assign pciw_pci0_txHeadF$DEQ =
WILL_FIRE_RL_pciw_pci0_tx_destage &&
pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ;
assign pciw_pci0_txHeadF$CLR = 1'b0 ;
// submodule pciw_pci0_txInF
assign pciw_pci0_txInF$D_IN = pciw_i2pF$D_OUT ;
assign pciw_pci0_txInF$ENQ = pciw_i2pF$EMPTY_N && pciw_pci0_txInF$FULL_N ;
assign pciw_pci0_txInF$DEQ = WILL_FIRE_RL_pciw_pci0_tx_enstage ;
assign pciw_pci0_txInF$CLR = 1'b0 ;
// submodule pciw_pci0_txOutF
assign pciw_pci0_txOutF$D_IN =
{ IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] <
3'd3,
!pciw_pci0_txInFlight,
pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817,
24'd0,
x_data__h46011 } ;
assign pciw_pci0_txOutF$ENQ = WILL_FIRE_RL_pciw_pci0_tx_destage ;
assign pciw_pci0_txOutF$DEQ = WILL_FIRE_RL_pciw_pci0_tx_exstage ;
assign pciw_pci0_txOutF$CLR = 1'b0 ;
// remaining internal signals
assign IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1 =
(IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_IF_p_ETC___d837 <=
IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d838) ?
IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_IF_p_ETC___d837 :
IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d838 ;
assign IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2 =
(IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_rxDw_ETC___d769 <
11'd4) ?
IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_rxDw_ETC___d769 :
11'd4 ;
assign IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_IF_p_ETC___d837 =
(!pciw_pci0_txInFlight &&
!IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481[34] &&
IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492[30]) ?
11'd3 :
11'd4 ;
assign IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801 =
WILL_FIRE_RL_pciw_pci0_rx_destage ?
IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] :
3'd0 ;
assign IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 =
WILL_FIRE_RL_pciw_pci0_rx_enstage ?
pciw_pci0_rxDws_delta_enq$wget :
3'd0 ;
assign IF_pciw_pci0_rxEofF_notEmpty__62_AND_pciw_pci0_ETC___d288 =
(pciw_pci0_rxEofF$EMPTY_N &&
pciw_pci0_rxDws_num_full_7_ULE_4___d836) ?
11'd0 :
pciw_pci0_rxHeadF$D_OUT[10:0] -
{ 8'd0,
IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] } ;
assign IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_rxDw_ETC___d769 =
pciw_pci0_rxInFlight ?
pciw_pci0_rxDwrDeq :
pciw_pci0_rxHeadF$D_OUT[10:0] ;
assign IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804 =
WILL_FIRE_RL_pciw_pci0_tx_destage ?
IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] :
3'd0 ;
assign IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 =
WILL_FIRE_RL_pciw_pci0_tx_enstage ?
pciw_pci0_txDws_delta_enq$wget :
3'd0 ;
assign IF_pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_ETC___d523 =
pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ?
11'd0 :
pciw_pci0_txHeadF$D_OUT[10:0] -
{ 8'd0,
IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] } ;
assign IF_pciw_pci0_txHeadF_first__59_BIT_11_60_THEN__ETC___d468 =
pciw_pci0_txHeadF$D_OUT[11] ?
{ pciw_pci0_txDws_vec[103:96],
pciw_pci0_txDws_vec[111:104],
pciw_pci0_txDws_vec[119:112],
pciw_pci0_txDws_vec[127:120] } :
pciw_pci0_txDws_vec[127:96] ;
assign IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481 =
pciw_pci0_txInFlight ?
pciw_pci0_txDws_vec[127:32] :
{ IF_pciw_pci0_txHeadF_first__59_BIT_11_60_THEN__ETC___d468,
pciw_pci0_txDws_vec[71:64],
pciw_pci0_txDws_vec[79:72],
pciw_pci0_txDws_vec[87:80],
pciw_pci0_txDws_vec[95:88],
pciw_pci0_txDws_vec[39:32],
pciw_pci0_txDws_vec[47:40],
pciw_pci0_txDws_vec[55:48],
pciw_pci0_txDws_vec[63:56] } ;
assign IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492 =
pciw_pci0_txInFlight ?
pciw_pci0_txDws_vec[31:0] :
{ pciw_pci0_txDws_vec[7:0],
pciw_pci0_txDws_vec[15:8],
pciw_pci0_txDws_vec[23:16],
pciw_pci0_txDws_vec[31:24] } ;
assign IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d838 =
pciw_pci0_txInFlight ?
pciw_pci0_txDwrDeq :
pciw_pci0_txHeadF$D_OUT[10:0] ;
assign INV_swReg_35_BIT_0_36_XOR_swReg_35_BIT_1_37_38_ETC___d764 =
{ ~swParity__h48492,
~(z__h56332 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[31]),
~pciw_aliveLed_sb$dD_OUT,
~pciw_linkLed_sb$dD_OUT,
~freeCnt[29:26] } ;
assign NOT_pciw_pci0_txEofF_notEmpty__52_53_OR_NOT_pc_ETC___d495 =
!pciw_pci0_txEofF$EMPTY_N ||
!pciw_pci0_txDws_num_full_3_ULE_4___d774 ||
!pciw_pci0_txInFlight &&
!IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481[34] &&
IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492[30] ;
assign _0_CONCAT_pciw_pci0_rxDws_new_data_wget__2_BITS_ETC___d832 =
{ 128'd0, x__h4523 } << x__h5776 ;
assign _0_CONCAT_pciw_pci0_txDws_new_data_wget__8_BITS_ETC___d833 =
{ 128'd0, x__h14478 } << x__h15731 ;
assign bar___1__h22106 =
(pciw_pci0_pcie_ep$rx_st_data0[28:24] == 5'd0) ?
pciw_pci0_pcie_ep$rx_st_bardec0 :
8'd0 ;
assign pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831 =
x__h56415 | y__h56416 ;
assign pciw_pci0_rxDws_num_full_7_ULE_4___d836 =
pciw_pci0_rxDws_num_full <= 4'd4 ;
assign pciw_pci0_rxDws_vec_3_SRL_IF_pciw_pci0_rxDws_d_ETC___d834 =
pciw_pci0_rxDws_vec >> x__h8877 ;
assign pciw_pci0_txDws_num_full_3_ULE_4___d774 =
pciw_pci0_txDws_num_full <= 4'd4 ;
assign pciw_pci0_txDws_vec_9_SRL_IF_pciw_pci0_txDws_d_ETC___d835 =
pciw_pci0_txDws_vec >> x__h18832 ;
assign pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 =
pciw_pci0_txEofF$EMPTY_N &&
pciw_pci0_txDws_num_full_3_ULE_4___d774 &&
(pciw_pci0_txInFlight ||
IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481[34] ||
!IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492[30]) ;
assign pciw_pci0_txOutF_i_notFull__48_AND_pciw_pci0_t_ETC___d502 =
pciw_pci0_txOutF$FULL_N &&
(pciw_pci0_txInFlight || pciw_pci0_txHeadF$EMPTY_N) &&
(NOT_pciw_pci0_txEofF_notEmpty__52_53_OR_NOT_pc_ETC___d495 ||
pciw_pci0_txHeadF$EMPTY_N && pciw_pci0_txEofF$EMPTY_N &&
pciw_pci0_txExF$FULL_N) ;
assign swParity__h48492 = z__h55879 ^ swReg[7] ;
assign x__h14478 =
{ pciw_pci0_txDws_new_data$wget[127:32] &
{ (IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 <=
3'd3) ?
32'd0 :
32'hFFFFFFFF,
(IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 <=
3'd2) ?
32'd0 :
32'hFFFFFFFF,
(IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 <=
3'd1) ?
32'd0 :
32'hFFFFFFFF },
pciw_pci0_txDws_new_data$wget[31:0] &
((IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 ==
3'd0) ?
32'd0 :
32'hFFFFFFFF) } ;
assign x__h15731 =
{ pciw_pci0_txDws_num_full -
{ 1'd0,
IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804 },
5'd0 } ;
assign x__h18832 =
{ IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804,
5'd0 } ;
assign x__h4523 =
{ pciw_pci0_rxDws_new_data$wget[127:32] &
{ (IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 <=
3'd3) ?
32'd0 :
32'hFFFFFFFF,
(IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 <=
3'd2) ?
32'd0 :
32'hFFFFFFFF,
(IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 <=
3'd1) ?
32'd0 :
32'hFFFFFFFF },
pciw_pci0_rxDws_new_data$wget[31:0] &
((IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 ==
3'd0) ?
32'd0 :
32'hFFFFFFFF) } ;
assign x__h56415 = x__h56417 | y__h56418 ;
assign x__h56417 = x__h56419 | y__h56420 ;
assign x__h56419 = x__h56421 | y__h56422 ;
assign x__h56421 = x__h56423 | y__h56424 ;
assign x__h56423 = x__h56425 | y__h56426 ;
assign x__h56425 = x__h56427 | y__h56428 ;
assign x__h56427 = x__h56429 | y__h56430 ;
assign x__h56429 = x__h56431 | y__h56432 ;
assign x__h56431 = x__h56433 | y__h56434 ;
assign x__h56433 = x__h56435 | y__h56436 ;
assign x__h56435 = x__h56437 | y__h56438 ;
assign x__h56437 = x__h56439 | y__h56440 ;
assign x__h56439 = x__h56441 | y__h56442 ;
assign x__h56441 = x__h56443 | y__h56444 ;
assign x__h56443 = x__h56445 | y__h56446 ;
assign x__h56445 = x__h56447 | y__h56448 ;
assign x__h56447 = x__h56449 | y__h56450 ;
assign x__h56449 = x__h56451 | y__h56452 ;
assign x__h56451 = pciw_pci0_pcie_ep$ava_debug | y__h56454 ;
assign x__h5776 =
{ pciw_pci0_rxDws_num_full -
{ 1'd0,
IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801 },
5'd0 } ;
assign x__h8877 =
{ IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801,
5'd0 } ;
assign x_be__h27614 =
{ IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[0],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[1],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[2],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[3],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[4],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[5],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[6],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[7],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[8],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[9],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[10],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[11],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[12],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[13],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[14],
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[15] } ;
assign x_data__h27615 =
{ pciw_pci0_rxDws_vec[7:0],
pciw_pci0_rxDws_vec[15:8],
pciw_pci0_rxDws_vec[23:16],
pciw_pci0_rxDws_vec[31:24],
pciw_pci0_rxDws_vec[39:32],
pciw_pci0_rxDws_vec[47:40],
pciw_pci0_rxDws_vec[55:48],
pciw_pci0_rxDws_vec[63:56],
pciw_pci0_rxDws_vec[71:64],
pciw_pci0_rxDws_vec[79:72],
pciw_pci0_rxDws_vec[87:80],
pciw_pci0_rxDws_vec[95:88],
pciw_pci0_rxDws_vec[103:96],
pciw_pci0_rxDws_vec[111:104],
pciw_pci0_rxDws_vec[119:112],
pciw_pci0_rxDws_vec[127:120] } ;
assign x_data__h46011 =
pciw_pci0_txInFlight ?
pciw_pci0_txDws_vec[127:0] :
{ IF_pciw_pci0_txHeadF_first__59_BIT_11_60_THEN__ETC___d468,
pciw_pci0_txDws_vec[71:64],
pciw_pci0_txDws_vec[79:72],
pciw_pci0_txDws_vec[87:80],
pciw_pci0_txDws_vec[95:88],
pciw_pci0_txDws_vec[39:32],
pciw_pci0_txDws_vec[47:40],
pciw_pci0_txDws_vec[55:48],
pciw_pci0_txDws_vec[63:56],
pciw_pci0_txDws_vec[7:0],
pciw_pci0_txDws_vec[15:8],
pciw_pci0_txDws_vec[23:16],
pciw_pci0_txDws_vec[31:24] } ;
assign x_hit__h22096 =
pciw_pci0_pcie_ep$rx_st_sop0 ? bar___1__h22106 : 8'd0 ;
assign y__h56416 = { 16'd0, pciw_pci0_txDbgDeDeq } ;
assign y__h56418 = { 16'd0, pciw_pci0_txDbgEnEnq } ;
assign y__h56420 = { 16'd0, pciw_pci0_txDbgDeEof } ;
assign y__h56422 = { 16'd0, pciw_pci0_txDbgDeSof } ;
assign y__h56424 = { 16'd0, pciw_pci0_txDbgEnEof } ;
assign y__h56426 = { 16'd0, pciw_pci0_txDbgEnSof } ;
assign y__h56428 = { 16'd0, pciw_pci0_txDbgDestage } ;
assign y__h56430 = { 16'd0, pciw_pci0_txDbgEnstage } ;
assign y__h56432 = { 16'd0, pciw_pci0_txDbgExstage } ;
assign y__h56434 = { 31'd0, pciw_pci0_txInFlight } ;
assign y__h56436 = { 16'd0, pciw_pci0_rxDbgDeDeq } ;
assign y__h56438 = { 16'd0, pciw_pci0_rxDbgEnEnq } ;
assign y__h56440 = { 16'd0, pciw_pci0_rxDbgDeEof } ;
assign y__h56442 = { 16'd0, pciw_pci0_rxDbgDeSof } ;
assign y__h56444 = { 16'd0, pciw_pci0_rxDbgEnEof } ;
assign y__h56446 = { 16'd0, pciw_pci0_rxDbgEnSof } ;
assign y__h56448 = { 16'd0, pciw_pci0_rxDbgDestage } ;
assign y__h56450 = { 16'd0, pciw_pci0_rxDbgEnstage } ;
assign y__h56452 = { 16'd0, pciw_pci0_rxDbgInstage } ;
assign y__h56454 = { 31'd0, pciw_pci0_rxInFlight } ;
assign z__h55844 = swReg[0] ^ swReg[1] ;
assign z__h55851 = z__h55844 ^ swReg[2] ;
assign z__h55858 = z__h55851 ^ swReg[3] ;
assign z__h55865 = z__h55858 ^ swReg[4] ;
assign z__h55872 = z__h55865 ^ swReg[5] ;
assign z__h55879 = z__h55872 ^ swReg[6] ;
assign z__h56129 =
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[0] ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[1] ;
assign z__h56136 =
z__h56129 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[2] ;
assign z__h56143 =
z__h56136 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[3] ;
assign z__h56150 =
z__h56143 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[4] ;
assign z__h56157 =
z__h56150 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[5] ;
assign z__h56164 =
z__h56157 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[6] ;
assign z__h56171 =
z__h56164 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[7] ;
assign z__h56178 =
z__h56171 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[8] ;
assign z__h56185 =
z__h56178 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[9] ;
assign z__h56192 =
z__h56185 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[10] ;
assign z__h56199 =
z__h56192 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[11] ;
assign z__h56206 =
z__h56199 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[12] ;
assign z__h56213 =
z__h56206 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[13] ;
assign z__h56220 =
z__h56213 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[14] ;
assign z__h56227 =
z__h56220 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[15] ;
assign z__h56234 =
z__h56227 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[16] ;
assign z__h56241 =
z__h56234 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[17] ;
assign z__h56248 =
z__h56241 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[18] ;
assign z__h56255 =
z__h56248 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[19] ;
assign z__h56262 =
z__h56255 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[20] ;
assign z__h56269 =
z__h56262 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[21] ;
assign z__h56276 =
z__h56269 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[22] ;
assign z__h56283 =
z__h56276 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[23] ;
assign z__h56290 =
z__h56283 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[24] ;
assign z__h56297 =
z__h56290 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[25] ;
assign z__h56304 =
z__h56297 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[26] ;
assign z__h56311 =
z__h56304 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[27] ;
assign z__h56318 =
z__h56311 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[28] ;
assign z__h56325 =
z__h56318 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[29] ;
assign z__h56332 =
z__h56325 ^
pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[30] ;
always@(IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2)
begin
case (IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0])
3'd0: IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 = 16'h0;
3'd1:
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 =
16'h000F;
3'd2:
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 =
16'h00FF;
3'd3:
IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 =
16'h0FFF;
default: IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 =
16'hFFFF;
endcase
end
// handling of inlined registers
always@(posedge pciw_pci0_pcie_ep$ava_core_clk_out)
begin
if (pciw_pci0_pcie_ep$ava_srstn == `BSV_RESET_VALUE)
begin
freeCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
hsmcReg <= `BSV_ASSIGNMENT_DELAY 16'd0;
ledReg <= `BSV_ASSIGNMENT_DELAY 16'd0;
needs_init <= `BSV_ASSIGNMENT_DELAY 1'd1;
pciDevice <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_cfgDataWr <= `BSV_ASSIGNMENT_DELAY 1'h0;
pciw_pci0_cfgSample <= `BSV_ASSIGNMENT_DELAY 1'h0;
pciw_pci0_deviceReg <= `BSV_ASSIGNMENT_DELAY 16'hAAAA;
pciw_pci0_rxDbgDeDeq <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgDeEof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgDeSof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgDestage <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgEnEnq <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgEnEof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgEnSof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgEnstage <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDbgInstage <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_rxDwrDeq <= `BSV_ASSIGNMENT_DELAY 11'd0;
pciw_pci0_rxDwrEnq <= `BSV_ASSIGNMENT_DELAY 11'd0;
pciw_pci0_rxDws_num_empty <= `BSV_ASSIGNMENT_DELAY 4'd8;
pciw_pci0_rxDws_num_full <= `BSV_ASSIGNMENT_DELAY 4'd0;
pciw_pci0_rxDws_vec <= `BSV_ASSIGNMENT_DELAY 256'd0;
pciw_pci0_rxInF_countReg <= `BSV_ASSIGNMENT_DELAY 6'd0;
pciw_pci0_rxInF_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
pciw_pci0_rxInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
pciw_pci0_txDbgDeDeq <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgDeEof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgDeSof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgDestage <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgEnEnq <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgEnEof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgEnSof <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgEnstage <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDbgExstage <= `BSV_ASSIGNMENT_DELAY 16'd0;
pciw_pci0_txDwrDeq <= `BSV_ASSIGNMENT_DELAY 11'd0;
pciw_pci0_txDwrEnq <= `BSV_ASSIGNMENT_DELAY 11'd0;
pciw_pci0_txDws_num_empty <= `BSV_ASSIGNMENT_DELAY 4'd8;
pciw_pci0_txDws_num_full <= `BSV_ASSIGNMENT_DELAY 4'd0;
pciw_pci0_txDws_vec <= `BSV_ASSIGNMENT_DELAY 256'd0;
pciw_pci0_txInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
pciw_pci0_txOutF_countReg <= `BSV_ASSIGNMENT_DELAY 10'd0;
pciw_pci0_txOutF_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
pciw_pci0_txReadyD <= `BSV_ASSIGNMENT_DELAY 1'd0;
pciw_pciDevice <= `BSV_ASSIGNMENT_DELAY 16'd0;
swReg <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (freeCnt$EN) freeCnt <= `BSV_ASSIGNMENT_DELAY freeCnt$D_IN;
if (hsmcReg$EN) hsmcReg <= `BSV_ASSIGNMENT_DELAY hsmcReg$D_IN;
if (ledReg$EN) ledReg <= `BSV_ASSIGNMENT_DELAY ledReg$D_IN;
if (needs_init$EN)
needs_init <= `BSV_ASSIGNMENT_DELAY needs_init$D_IN;
if (pciDevice$EN) pciDevice <= `BSV_ASSIGNMENT_DELAY pciDevice$D_IN;
if (pciw_pci0_cfgDataWr$EN)
pciw_pci0_cfgDataWr <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_cfgDataWr$D_IN;
if (pciw_pci0_cfgSample$EN)
pciw_pci0_cfgSample <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_cfgSample$D_IN;
if (pciw_pci0_deviceReg$EN)
pciw_pci0_deviceReg <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_deviceReg$D_IN;
if (pciw_pci0_rxDbgDeDeq$EN)
pciw_pci0_rxDbgDeDeq <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgDeDeq$D_IN;
if (pciw_pci0_rxDbgDeEof$EN)
pciw_pci0_rxDbgDeEof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgDeEof$D_IN;
if (pciw_pci0_rxDbgDeSof$EN)
pciw_pci0_rxDbgDeSof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgDeSof$D_IN;
if (pciw_pci0_rxDbgDestage$EN)
pciw_pci0_rxDbgDestage <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgDestage$D_IN;
if (pciw_pci0_rxDbgEnEnq$EN)
pciw_pci0_rxDbgEnEnq <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgEnEnq$D_IN;
if (pciw_pci0_rxDbgEnEof$EN)
pciw_pci0_rxDbgEnEof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgEnEof$D_IN;
if (pciw_pci0_rxDbgEnSof$EN)
pciw_pci0_rxDbgEnSof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgEnSof$D_IN;
if (pciw_pci0_rxDbgEnstage$EN)
pciw_pci0_rxDbgEnstage <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgEnstage$D_IN;
if (pciw_pci0_rxDbgInstage$EN)
pciw_pci0_rxDbgInstage <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDbgInstage$D_IN;
if (pciw_pci0_rxDwrDeq$EN)
pciw_pci0_rxDwrDeq <= `BSV_ASSIGNMENT_DELAY pciw_pci0_rxDwrDeq$D_IN;
if (pciw_pci0_rxDwrEnq$EN)
pciw_pci0_rxDwrEnq <= `BSV_ASSIGNMENT_DELAY pciw_pci0_rxDwrEnq$D_IN;
if (pciw_pci0_rxDws_num_empty$EN)
pciw_pci0_rxDws_num_empty <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDws_num_empty$D_IN;
if (pciw_pci0_rxDws_num_full$EN)
pciw_pci0_rxDws_num_full <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDws_num_full$D_IN;
if (pciw_pci0_rxDws_vec$EN)
pciw_pci0_rxDws_vec <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxDws_vec$D_IN;
if (pciw_pci0_rxInF_countReg$EN)
pciw_pci0_rxInF_countReg <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxInF_countReg$D_IN;
if (pciw_pci0_rxInF_levelsValid$EN)
pciw_pci0_rxInF_levelsValid <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxInF_levelsValid$D_IN;
if (pciw_pci0_rxInFlight$EN)
pciw_pci0_rxInFlight <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_rxInFlight$D_IN;
if (pciw_pci0_txDbgDeDeq$EN)
pciw_pci0_txDbgDeDeq <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgDeDeq$D_IN;
if (pciw_pci0_txDbgDeEof$EN)
pciw_pci0_txDbgDeEof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgDeEof$D_IN;
if (pciw_pci0_txDbgDeSof$EN)
pciw_pci0_txDbgDeSof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgDeSof$D_IN;
if (pciw_pci0_txDbgDestage$EN)
pciw_pci0_txDbgDestage <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgDestage$D_IN;
if (pciw_pci0_txDbgEnEnq$EN)
pciw_pci0_txDbgEnEnq <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgEnEnq$D_IN;
if (pciw_pci0_txDbgEnEof$EN)
pciw_pci0_txDbgEnEof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgEnEof$D_IN;
if (pciw_pci0_txDbgEnSof$EN)
pciw_pci0_txDbgEnSof <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgEnSof$D_IN;
if (pciw_pci0_txDbgEnstage$EN)
pciw_pci0_txDbgEnstage <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgEnstage$D_IN;
if (pciw_pci0_txDbgExstage$EN)
pciw_pci0_txDbgExstage <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDbgExstage$D_IN;
if (pciw_pci0_txDwrDeq$EN)
pciw_pci0_txDwrDeq <= `BSV_ASSIGNMENT_DELAY pciw_pci0_txDwrDeq$D_IN;
if (pciw_pci0_txDwrEnq$EN)
pciw_pci0_txDwrEnq <= `BSV_ASSIGNMENT_DELAY pciw_pci0_txDwrEnq$D_IN;
if (pciw_pci0_txDws_num_empty$EN)
pciw_pci0_txDws_num_empty <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDws_num_empty$D_IN;
if (pciw_pci0_txDws_num_full$EN)
pciw_pci0_txDws_num_full <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDws_num_full$D_IN;
if (pciw_pci0_txDws_vec$EN)
pciw_pci0_txDws_vec <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txDws_vec$D_IN;
if (pciw_pci0_txInFlight$EN)
pciw_pci0_txInFlight <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txInFlight$D_IN;
if (pciw_pci0_txOutF_countReg$EN)
pciw_pci0_txOutF_countReg <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txOutF_countReg$D_IN;
if (pciw_pci0_txOutF_levelsValid$EN)
pciw_pci0_txOutF_levelsValid <= `BSV_ASSIGNMENT_DELAY
pciw_pci0_txOutF_levelsValid$D_IN;
if (pciw_pci0_txReadyD$EN)
pciw_pci0_txReadyD <= `BSV_ASSIGNMENT_DELAY pciw_pci0_txReadyD$D_IN;
if (pciw_pciDevice$EN)
pciw_pciDevice <= `BSV_ASSIGNMENT_DELAY pciw_pciDevice$D_IN;
if (swReg$EN) swReg <= `BSV_ASSIGNMENT_DELAY swReg$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
freeCnt = 32'hAAAAAAAA;
hsmcReg = 16'hAAAA;
ledReg = 16'hAAAA;
needs_init = 1'h0;
pciDevice = 16'hAAAA;
pciw_pci0_cfgDataWr = 1'h0;
pciw_pci0_cfgSample = 1'h0;
pciw_pci0_deviceReg = 16'hAAAA;
pciw_pci0_rxDbgDeDeq = 16'hAAAA;
pciw_pci0_rxDbgDeEof = 16'hAAAA;
pciw_pci0_rxDbgDeSof = 16'hAAAA;
pciw_pci0_rxDbgDestage = 16'hAAAA;
pciw_pci0_rxDbgEnEnq = 16'hAAAA;
pciw_pci0_rxDbgEnEof = 16'hAAAA;
pciw_pci0_rxDbgEnSof = 16'hAAAA;
pciw_pci0_rxDbgEnstage = 16'hAAAA;
pciw_pci0_rxDbgInstage = 16'hAAAA;
pciw_pci0_rxDwrDeq = 11'h2AA;
pciw_pci0_rxDwrEnq = 11'h2AA;
pciw_pci0_rxDws_num_empty = 4'hA;
pciw_pci0_rxDws_num_full = 4'hA;
pciw_pci0_rxDws_vec =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
pciw_pci0_rxInF_countReg = 6'h2A;
pciw_pci0_rxInF_levelsValid = 1'h0;
pciw_pci0_rxInFlight = 1'h0;
pciw_pci0_txDbgDeDeq = 16'hAAAA;
pciw_pci0_txDbgDeEof = 16'hAAAA;
pciw_pci0_txDbgDeSof = 16'hAAAA;
pciw_pci0_txDbgDestage = 16'hAAAA;
pciw_pci0_txDbgEnEnq = 16'hAAAA;
pciw_pci0_txDbgEnEof = 16'hAAAA;
pciw_pci0_txDbgEnSof = 16'hAAAA;
pciw_pci0_txDbgEnstage = 16'hAAAA;
pciw_pci0_txDbgExstage = 16'hAAAA;
pciw_pci0_txDwrDeq = 11'h2AA;
pciw_pci0_txDwrEnq = 11'h2AA;
pciw_pci0_txDws_num_empty = 4'hA;
pciw_pci0_txDws_num_full = 4'hA;
pciw_pci0_txDws_vec =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
pciw_pci0_txInFlight = 1'h0;
pciw_pci0_txOutF_countReg = 10'h2AA;
pciw_pci0_txOutF_levelsValid = 1'h0;
pciw_pci0_txReadyD = 1'h0;
pciw_pciDevice = 16'hAAAA;
swReg = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkFTop_alst4
|
// --------------------------------------------------------------------------------
//| Avalon ST Packets to MM Master Transaction Component
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
// --------------------------------------------------------------------------------
//| Fast Transaction Master
// --------------------------------------------------------------------------------
module altera_avalon_packets_to_master (
// Interface: clk
input wire clk,
input wire reset_n,
// Interface: ST in
output wire in_ready,
input wire in_valid,
input wire [ 7: 0] in_data,
input wire in_startofpacket,
input wire in_endofpacket,
// Interface: ST out
input wire out_ready,
output wire out_valid,
output wire [ 7: 0] out_data,
output wire out_startofpacket,
output wire out_endofpacket,
// Interface: MM out
output wire [31: 0] address,
input wire [31: 0] readdata,
output wire read,
output wire write,
output wire [ 3: 0] byteenable,
output wire [31: 0] writedata,
input wire waitrequest,
input wire readdatavalid
);
wire [ 35: 0] fifo_readdata;
wire fifo_read;
wire fifo_empty;
wire [ 35: 0] fifo_writedata;
wire fifo_write;
wire fifo_write_waitrequest;
// ---------------------------------------------------------------------
//| Parameter Declarations
// ---------------------------------------------------------------------
parameter EXPORT_MASTER_SIGNALS = 0;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
parameter FAST_VER = 0;
generate
if (FAST_VER) begin
packets_to_fifo p2f (
.clk (clk),
.reset_n (reset_n),
.in_ready (in_ready),
.in_valid (in_valid),
.in_data (in_data),
.in_startofpacket (in_startofpacket),
.in_endofpacket (in_endofpacket),
.address (address),
.readdata (readdata),
.read (read),
.write (write),
.byteenable (byteenable),
.writedata (writedata),
.waitrequest (waitrequest),
.readdatavalid (readdatavalid),
.fifo_writedata (fifo_writedata),
.fifo_write (fifo_write),
.fifo_write_waitrequest (fifo_write_waitrequest)
);
fifo_to_packet f2p (
.clk (clk),
.reset_n (reset_n),
.out_ready (out_ready),
.out_valid (out_valid),
.out_data (out_data),
.out_startofpacket (out_startofpacket),
.out_endofpacket (out_endofpacket),
.fifo_readdata (fifo_readdata),
.fifo_read (fifo_read),
.fifo_empty (fifo_empty)
);
fifo_buffer #(
.FIFO_DEPTHS(FIFO_DEPTHS),
.FIFO_WIDTHU(FIFO_WIDTHU)
) fb (
.wrclock (clk),
.reset_n (reset_n),
.avalonmm_write_slave_writedata (fifo_writedata),
.avalonmm_write_slave_write (fifo_write),
.avalonmm_write_slave_waitrequest (fifo_write_waitrequest),
.avalonmm_read_slave_readdata (fifo_readdata),
.avalonmm_read_slave_read (fifo_read),
.avalonmm_read_slave_waitrequest (fifo_empty)
);
end else begin
packets_to_master p2m (
.clk (clk),
.reset_n (reset_n),
.in_ready (in_ready),
.in_valid (in_valid),
.in_data (in_data),
.in_startofpacket (in_startofpacket),
.in_endofpacket (in_endofpacket),
.address (address),
.readdata (readdata),
.read (read),
.write (write),
.byteenable (byteenable),
.writedata (writedata),
.waitrequest (waitrequest),
.readdatavalid (readdatavalid),
.out_ready (out_ready),
.out_valid (out_valid),
.out_data (out_data),
.out_startofpacket (out_startofpacket),
.out_endofpacket (out_endofpacket)
);
end
endgenerate
endmodule
module packets_to_fifo (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: MM out
output reg [31: 0] address,
input [31: 0] readdata,
output reg read,
output reg write,
output reg [ 3: 0] byteenable,
output reg [31: 0] writedata,
input waitrequest,
input readdatavalid,
// Interface: FIFO
// FIFO data format:
// | sop, eop, [1:0]valid, [31:0]data |
output reg [ 35: 0] fifo_writedata,
output reg fifo_write,
input wire fifo_write_waitrequest
);
// ---------------------------------------------------------------------
//| Command Declarations
// ---------------------------------------------------------------------
localparam CMD_WRITE_NON_INCR = 8'h00;
localparam CMD_WRITE_INCR = 8'h04;
localparam CMD_READ_NON_INCR = 8'h10;
localparam CMD_READ_INCR = 8'h14;
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [ 3: 0] state;
reg [ 7: 0] command;
reg [ 1: 0] current_byte, byte_avail;
reg [ 15: 0] counter;
reg [ 31: 0] read_data_buffer;
reg [ 31: 0] fifo_data_buffer;
reg in_ready_0;
reg first_trans, last_trans, fifo_sop;
reg [ 3: 0] unshifted_byteenable;
wire enable;
localparam READY = 4'b0000,
GET_EXTRA = 4'b0001,
GET_SIZE1 = 4'b0010,
GET_SIZE2 = 4'b0011,
GET_ADDR1 = 4'b0100,
GET_ADDR2 = 4'b0101,
GET_ADDR3 = 4'b0110,
GET_ADDR4 = 4'b0111,
GET_WRITE_DATA = 4'b1000,
WRITE_WAIT = 4'b1001,
READ_ASSERT = 4'b1010,
READ_CMD_WAIT = 4'b1011,
READ_DATA_WAIT = 4'b1100,
PUSH_FIFO = 4'b1101,
PUSH_FIFO_WAIT = 4'b1110,
FIFO_CMD_WAIT = 4'b1111;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign enable = (in_ready & in_valid);
always @* begin
in_ready = in_ready_0;
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
in_ready_0 <= 1'b0;
fifo_writedata <= 'b0;
fifo_write <= 1'b0;
fifo_sop <= 1'b0;
read <= 1'b0;
write <= 1'b0;
byteenable <= 'b0;
writedata <= 'b0;
address <= 'b0;
counter <= 'b0;
command <= 'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
state <= 'b0;
current_byte <= 'b0;
read_data_buffer <= 'b0;
unshifted_byteenable <= 'b0;
byte_avail <= 'b0;
fifo_data_buffer <= 'b0;
end else begin
address[1:0] <= 'b0;
in_ready_0 <= 1'b0;
if (counter > 3) unshifted_byteenable <= 4'b1111;
else if (counter == 3) unshifted_byteenable <= 4'b0111;
else if (counter == 2) unshifted_byteenable <= 4'b0011;
else if (counter == 1) unshifted_byteenable <= 4'b0001;
case (state)
READY : begin
in_ready_0 <= !fifo_write_waitrequest;
fifo_write <= 1'b0;
end
GET_EXTRA : begin
in_ready_0 <= 1'b1;
byteenable <= 'b0;
if (enable) state <= GET_SIZE1;
end
GET_SIZE1 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[15:8] <= command[4]?in_data:8'b0;
if (enable) state <= GET_SIZE2;
end
GET_SIZE2 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[7:0] <= command[4]?in_data:8'b0;
if (enable) state <= GET_ADDR1;
end
GET_ADDR1 : begin
in_ready_0 <= 1'b1;
first_trans <= 1'b1;
last_trans <= 1'b0;
address[31:24] <= in_data;
if (enable) state <= GET_ADDR2;
end
GET_ADDR2 : begin
in_ready_0 <= 1'b1;
address[23:16] <= in_data;
if (enable) state <= GET_ADDR3;
end
GET_ADDR3 : begin
in_ready_0 <= 1'b1;
address[15:8] <= in_data;
if (enable) state <= GET_ADDR4;
end
GET_ADDR4 : begin
in_ready_0 <= 1'b1;
address[7:2] <= in_data[7:2];
current_byte <= in_data[1:0];
if (enable) begin
if (command == CMD_WRITE_NON_INCR | command == CMD_WRITE_INCR) begin
state <= GET_WRITE_DATA; //writes
in_ready_0 <= 1'b1;
end
else if (command == CMD_READ_NON_INCR | command == CMD_READ_INCR) begin
state <= READ_ASSERT; //reads
in_ready_0 <= 1'b0;
end
else begin
//nops
//treat all unrecognized commands as nops as well
in_ready_0 <= 1'b0;
state <= FIFO_CMD_WAIT;
//| sop, eop, [1:0]valid, [31:0]data |
//| 1 , 1 , 2'b11 ,{counter,reserved_byte}|
fifo_writedata[7:0] <= (8'h80 | command);
fifo_writedata[35:8]<= {4'b1111,counter[7:0],counter[15:8],8'b0};
fifo_write <= 1'b1;
counter <= 0;
end
end
end
GET_WRITE_DATA : begin
in_ready_0 <= 1'b1;
if (enable) begin
counter <= counter + 1'b1;
//2 bit, should wrap by itself
current_byte <= current_byte + 1'b1;
if (in_endofpacket || current_byte == 3)
begin
in_ready_0 <= 1'b0;
write <= 1'b1;
state <= WRITE_WAIT;
end
end
if (in_endofpacket) begin
last_trans <= 1'b1;
end
// handle byte writes properly
// drive data pins based on addresses
case (current_byte)
0: begin
writedata[7:0] <= in_data;
byteenable[0] <= 1'b1;
end
1: begin
writedata[15:8] <= in_data;
byteenable[1] <= 1'b1;
end
2: begin
writedata[23:16] <= in_data;
byteenable[2] <= 1'b1;
end
3: begin
writedata[31:24] <= in_data;
byteenable[3] <= 1'b1;
end
endcase
end
WRITE_WAIT : begin
in_ready_0 <= 1'b0;
write <= 1'b1;
if (~waitrequest) begin
write <= 1'b0;
state <= GET_WRITE_DATA;
in_ready_0 <= 1'b1;
byteenable <= 'b0;
if (command[2] == 1'b1) begin
//increment address, but word-align it
address[31:2] <= (address[31:2] + 1'b1);
end
if (last_trans) begin
in_ready_0 <= 1'b0;
state <= FIFO_CMD_WAIT;
//| sop, eop, [1:0]valid, [31:0]data |
//| 1 , 1 , 2'b11 ,{counter,reserved_byte}|
fifo_writedata[7:0] <= (8'h80 | command);
fifo_writedata[35:8]<= {4'b1111,counter[7:0],counter[15:8],8'b0};
fifo_write <= 1'b1;
counter <= 0;
end
end
end
READ_ASSERT : begin
if (current_byte == 3) byteenable <= unshifted_byteenable << 3;
if (current_byte == 2) byteenable <= unshifted_byteenable << 2;
if (current_byte == 1) byteenable <= unshifted_byteenable << 1;
if (current_byte == 0) byteenable <= unshifted_byteenable;
read <= 1'b1;
fifo_write <= 1'b0;
state <= READ_CMD_WAIT;
end
READ_CMD_WAIT : begin
// number of valid byte
case (byteenable)
4'b0000 : byte_avail <= 1'b0;
4'b0001 : byte_avail <= 1'b0;
4'b0010 : byte_avail <= 1'b0;
4'b0100 : byte_avail <= 1'b0;
4'b1000 : byte_avail <= 1'b0;
4'b0011 : byte_avail <= 1'b1;
4'b0110 : byte_avail <= 1'b1;
4'b1100 : byte_avail <= 1'b1;
4'b0111 : byte_avail <= 2'h2;
4'b1110 : byte_avail <= 2'h2;
default : byte_avail <= 2'h3;
endcase
read_data_buffer <= readdata;
read <= 1;
// if readdatavalid, take the data and
// go directly to READ_SEND_ISSUE. This is for fixed
// latency slaves. Ignore waitrequest in this case,
// since this master does not issue pipelined reads.
//
// For variable latency slaves, once waitrequest is low
// the read command is accepted, so deassert read and
// go to READ_DATA_WAIT to wait for readdatavalid
if (readdatavalid) begin
state <= PUSH_FIFO;
read <= 0;
end else begin
if (~waitrequest) begin
state <= READ_DATA_WAIT;
read <= 0;
end
end
end
READ_DATA_WAIT : begin
read_data_buffer <= readdata;
if (readdatavalid) begin
state <= PUSH_FIFO;
end
end
PUSH_FIFO : begin
fifo_write <= 1'b0;
fifo_sop <= 1'b0;
if (first_trans) begin
first_trans <= 1'b0;
fifo_sop <= 1'b1;
end
case (current_byte)
3 : begin
fifo_data_buffer <= read_data_buffer >> 24;
counter <= counter - 1'b1;
end
2 : begin
fifo_data_buffer <= read_data_buffer >> 16;
if (counter == 1) counter <= 0;
else counter <= counter - 2'h2;
end
1 : begin
fifo_data_buffer <= read_data_buffer >> 8;
if (counter < 3) counter <= 0;
else counter <= counter - 2'h3;
end
default : begin
fifo_data_buffer <= read_data_buffer;
if (counter < 4) counter <= 0;
else counter <= counter - 3'h4;
end
endcase
current_byte <= 0;
state <= PUSH_FIFO_WAIT;
end
PUSH_FIFO_WAIT : begin
// pushd return packet with data
fifo_write <= 1'b1;
fifo_writedata <= {fifo_sop,(counter == 0)?1'b1:1'b0,byte_avail,fifo_data_buffer};
// count down on the number of bytes to read
// shift current byte location within word
// if increment address, add it, so the next read
// can use it, if more reads are required
// no more bytes to send - go to READY state
if (counter == 0) begin
state <= FIFO_CMD_WAIT;
end else if (command[2]== 1'b1) begin
//increment address, but word-align it
state <= FIFO_CMD_WAIT;
address[31:2] <= (address[31:2] + 1'b1);
end
end
FIFO_CMD_WAIT : begin
// back pressure if fifo_write_waitrequest
if (!fifo_write_waitrequest) begin
if (counter == 0) begin
state <= READY;
end else begin
state <= READ_ASSERT;
end
fifo_write <= 1'b0;
end
end
endcase
if (enable & in_startofpacket) begin
state <= GET_EXTRA;
command <= in_data;
in_ready_0 <= !fifo_write_waitrequest;
end
end // end else
end // end always block
endmodule
// --------------------------------------------------------------------------------
// FIFO buffer
// --------------------------------------------------------------------------------
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module fifo_buffer_single_clock_fifo (
// inputs:
aclr,
clock,
data,
rdreq,
wrreq,
// outputs:
empty,
full,
q
)
;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output empty;
output full;
output [ 35: 0] q;
input aclr;
input clock;
input [ 35: 0] data;
input rdreq;
input wrreq;
wire empty;
wire full;
wire [ 35: 0] q;
scfifo single_clock_fifo
(
.aclr (aclr),
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.wrreq (wrreq)
);
defparam single_clock_fifo.add_ram_output_register = "OFF",
single_clock_fifo.lpm_numwords = FIFO_DEPTHS,
single_clock_fifo.lpm_showahead = "OFF",
single_clock_fifo.lpm_type = "scfifo",
single_clock_fifo.lpm_width = 36,
single_clock_fifo.lpm_widthu = FIFO_WIDTHU,
single_clock_fifo.overflow_checking = "ON",
single_clock_fifo.underflow_checking = "ON",
single_clock_fifo.use_eab = "OFF";
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module fifo_buffer_scfifo_with_controls (
// inputs:
clock,
data,
rdreq,
reset_n,
wrreq,
// outputs:
empty,
full,
q
)
;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output empty;
output full;
output [ 35: 0] q;
input clock;
input [ 35: 0] data;
input rdreq;
input reset_n;
input wrreq;
wire empty;
wire full;
wire [ 35: 0] q;
wire wrreq_valid;
//the_scfifo, which is an e_instance
fifo_buffer_single_clock_fifo #(
.FIFO_DEPTHS(FIFO_DEPTHS),
.FIFO_WIDTHU(FIFO_WIDTHU)
) the_scfifo (
.aclr (~reset_n),
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.wrreq (wrreq_valid)
);
assign wrreq_valid = wrreq & ~full;
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module fifo_buffer (
// inputs:
avalonmm_read_slave_read,
avalonmm_write_slave_write,
avalonmm_write_slave_writedata,
reset_n,
wrclock,
// outputs:
avalonmm_read_slave_readdata,
avalonmm_read_slave_waitrequest,
avalonmm_write_slave_waitrequest
)
;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output [ 35: 0] avalonmm_read_slave_readdata;
output avalonmm_read_slave_waitrequest;
output avalonmm_write_slave_waitrequest;
input avalonmm_read_slave_read;
input avalonmm_write_slave_write;
input [ 35: 0] avalonmm_write_slave_writedata;
input reset_n;
input wrclock;
wire [ 35: 0] avalonmm_read_slave_readdata;
wire avalonmm_read_slave_waitrequest;
wire avalonmm_write_slave_waitrequest;
wire clock;
wire [ 35: 0] data;
wire empty;
wire full;
wire [ 35: 0] q;
wire rdreq;
wire wrreq;
//the_scfifo_with_controls, which is an e_instance
fifo_buffer_scfifo_with_controls #(
.FIFO_DEPTHS(FIFO_DEPTHS),
.FIFO_WIDTHU(FIFO_WIDTHU)
) the_scfifo_with_controls
(
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.reset_n (reset_n),
.wrreq (wrreq)
);
//in, which is an e_avalon_slave
//out, which is an e_avalon_slave
assign data = avalonmm_write_slave_writedata;
assign wrreq = avalonmm_write_slave_write;
assign avalonmm_read_slave_readdata = q;
assign rdreq = avalonmm_read_slave_read;
assign clock = wrclock;
assign avalonmm_write_slave_waitrequest = full;
assign avalonmm_read_slave_waitrequest = empty;
endmodule
// --------------------------------------------------------------------------------
// fifo_buffer to Avalon-ST interface
// --------------------------------------------------------------------------------
module fifo_to_packet (
// Interface: clk
input clk,
input reset_n,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: FIFO in
input [ 35: 0] fifo_readdata,
output reg fifo_read,
input fifo_empty
);
reg [ 1: 0] state;
reg enable, sent_all;
reg [ 1: 0] current_byte, byte_end;
reg first_trans, last_trans;
reg [ 23:0] fifo_data_buffer;
localparam POP_FIFO = 2'b00,
POP_FIFO_WAIT = 2'b01,
FIFO_DATA_WAIT = 2'b10,
READ_SEND_ISSUE = 2'b11;
always @* begin
enable = (!fifo_empty & sent_all);
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
fifo_data_buffer <= 'b0;
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
out_data <= 'b0;
state <= 'b0;
fifo_read <= 1'b0;
current_byte <= 'b0;
byte_end <= 'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
sent_all <= 1'b1;
end else begin
if (out_ready) begin
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
end
case (state)
POP_FIFO : begin
if (out_ready) begin
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
byte_end <= 'b0;
fifo_read <= 1'b0;
sent_all <= 1'b1;
end
// start poping fifo after all data sent and data available
if (enable) begin
fifo_read <= 1'b1;
out_valid <= 1'b0;
state <= POP_FIFO_WAIT;
end
end
POP_FIFO_WAIT : begin
//fifo latency of 1
fifo_read <= 1'b0;
state <= FIFO_DATA_WAIT;
end
FIFO_DATA_WAIT : begin
sent_all <= 1'b0;
first_trans <= fifo_readdata[35];
last_trans <= fifo_readdata[34];
out_data <= fifo_readdata[7:0];
fifo_data_buffer <= fifo_readdata[31:8];
byte_end <= fifo_readdata[33:32];
current_byte <= 1'b1;
out_valid <= 1'b1;
// first byte sop eop handling
if (fifo_readdata[35] & fifo_readdata[34] & (fifo_readdata[33:32] == 0)) begin
first_trans <= 1'b0;
last_trans <= 1'b0;
out_startofpacket <= 1'b1;
out_endofpacket <= 1'b1;
state <= POP_FIFO;
end else if (fifo_readdata[35] & (fifo_readdata[33:32] == 0)) begin
first_trans <= 1'b0;
out_startofpacket <= 1'b1;
state <= POP_FIFO;
end else if (fifo_readdata[35]) begin
first_trans <= 1'b0;
out_startofpacket <= 1'b1;
state <= READ_SEND_ISSUE;
end else if (fifo_readdata[34] & (fifo_readdata[33:32] == 0)) begin
last_trans <= 1'b0;
out_endofpacket <= 1'b1;
state <= POP_FIFO;
end else begin
state <= READ_SEND_ISSUE;
end
end
READ_SEND_ISSUE : begin
out_valid <= 1'b1;
sent_all <= 1'b0;
if (out_ready) begin
out_startofpacket <= 1'b0;
// last byte
if (last_trans & (current_byte == byte_end)) begin
last_trans <= 1'b0;
out_endofpacket <= 1'b1;
state <= POP_FIFO;
end
case (current_byte)
3: begin
out_data <= fifo_data_buffer[23:16];
end
2: begin
out_data <= fifo_data_buffer[15:8];
end
1: begin
out_data <= fifo_data_buffer[7:0];
end
default: begin
//out_data <= fifo_readdata[7:0];
end
endcase
current_byte <= current_byte + 1'b1;
if (current_byte == byte_end) begin
state <= POP_FIFO;
end else begin
state <= READ_SEND_ISSUE;
end
end
end
endcase
end
end
endmodule
// --------------------------------------------------------------------------------
//| Economy Transaction Master
// --------------------------------------------------------------------------------
module packets_to_master (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: MM out
output reg [31: 0] address,
input [31: 0] readdata,
output reg read,
output reg write,
output reg [ 3: 0] byteenable,
output reg [31: 0] writedata,
input waitrequest,
input readdatavalid
);
// ---------------------------------------------------------------------
//| Parameter Declarations
// ---------------------------------------------------------------------
parameter EXPORT_MASTER_SIGNALS = 0;
// ---------------------------------------------------------------------
//| Command Declarations
// ---------------------------------------------------------------------
localparam CMD_WRITE_NON_INCR = 8'h00;
localparam CMD_WRITE_INCR = 8'h04;
localparam CMD_READ_NON_INCR = 8'h10;
localparam CMD_READ_INCR = 8'h14;
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [ 3: 0] state;
reg [ 7: 0] command;
reg [ 1: 0] current_byte; //, result_byte;
reg [ 15: 0] counter;
reg [ 23: 0] read_data_buffer;
reg in_ready_0;
reg first_trans, last_trans;
reg [ 3: 0] unshifted_byteenable;
wire enable;
localparam READY = 4'b0000,
GET_EXTRA = 4'b0001,
GET_SIZE1 = 4'b0010,
GET_SIZE2 = 4'b0011,
GET_ADDR1 = 4'b0100,
GET_ADDR2 = 4'b0101,
GET_ADDR3 = 4'b0110,
GET_ADDR4 = 4'b0111,
GET_WRITE_DATA = 4'b1000,
WRITE_WAIT = 4'b1001,
RETURN_PACKET = 4'b1010,
READ_ASSERT = 4'b1011,
READ_CMD_WAIT = 4'b1100,
READ_DATA_WAIT = 4'b1101,
READ_SEND_ISSUE= 4'b1110,
READ_SEND_WAIT = 4'b1111;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign enable = (in_ready & in_valid);
always @*
// in_ready = in_ready_0 & out_ready;
in_ready = in_ready_0;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
in_ready_0 <= 1'b0;
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
out_data <= 'b0;
read <= 1'b0;
write <= 1'b0;
byteenable <= 'b0;
writedata <= 'b0;
address <= 'b0;
counter <= 'b0;
command <= 'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
state <= 'b0;
current_byte <= 'b0;
// result_byte <= 'b0;
read_data_buffer <= 'b0;
unshifted_byteenable <= 'b0;
end else begin
address[1:0] <= 'b0;
if (out_ready) begin
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
end
in_ready_0 <= 1'b0;
if (counter >= 3) unshifted_byteenable <= 4'b1111;
else if (counter == 3) unshifted_byteenable <= 4'b0111;
else if (counter == 2) unshifted_byteenable <= 4'b0011;
else if (counter == 1) unshifted_byteenable <= 4'b0001;
case (state)
READY : begin
out_valid <= 1'b0;
in_ready_0 <= 1'b1;
end
GET_EXTRA : begin
in_ready_0 <= 1'b1;
byteenable <= 'b0;
if (enable) state <= GET_SIZE1;
end
GET_SIZE1 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[15:8] <= command[4]?in_data:8'b0;
if (enable) state <= GET_SIZE2;
end
GET_SIZE2 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[7:0] <= command[4]?in_data:8'b0;
if (enable) state <= GET_ADDR1;
end
GET_ADDR1 : begin
in_ready_0 <= 1'b1;
first_trans <= 1'b1;
last_trans <= 1'b0;
address[31:24] <= in_data;
if (enable) state <= GET_ADDR2;
end
GET_ADDR2 : begin
in_ready_0 <= 1'b1;
address[23:16] <= in_data;
if (enable) state <= GET_ADDR3;
end
GET_ADDR3 : begin
in_ready_0 <= 1'b1;
address[15:8] <= in_data;
if (enable) state <= GET_ADDR4;
end
GET_ADDR4 : begin
in_ready_0 <= 1'b1;
address[7:2] <= in_data[7:2];
current_byte <= in_data[1:0];
if (enable) begin
if (command == CMD_WRITE_NON_INCR | command == CMD_WRITE_INCR) begin
state <= GET_WRITE_DATA; //writes
in_ready_0 <= 1'b1;
end
else if (command == CMD_READ_NON_INCR | command == CMD_READ_INCR) begin
state <= READ_ASSERT; //reads
in_ready_0 <= 1'b0;
end
else begin
//nops
//treat all unrecognized commands as nops as well
state <= RETURN_PACKET;
out_startofpacket <= 1'b1;
out_data <= (8'h80 | command);
out_valid <= 1'b1;
current_byte <= 'h0;
in_ready_0 <= 1'b0;
end
end
end
GET_WRITE_DATA : begin
in_ready_0 <= 1;
if (enable) begin
counter <= counter + 1'b1;
//2 bit, should wrap by itself
current_byte <= current_byte + 1'b1;
if (in_endofpacket || current_byte == 3)
begin
in_ready_0 <= 0;
write <= 1'b1;
state <= WRITE_WAIT;
end
end
if (in_endofpacket) begin
last_trans <= 1'b1;
end
// handle byte writes properly
// drive data pins based on addresses
case (current_byte)
0: begin
writedata[7:0] <= in_data;
byteenable[0] <= 1;
end
1: begin
writedata[15:8] <= in_data;
byteenable[1] <= 1;
end
2: begin
writedata[23:16] <= in_data;
byteenable[2] <= 1;
end
3: begin
writedata[31:24] <= in_data;
byteenable[3] <= 1;
end
endcase
end
WRITE_WAIT : begin
in_ready_0 <= 0;
write <= 1'b1;
if (~waitrequest) begin
write <= 1'b0;
state <= GET_WRITE_DATA;
in_ready_0 <= 1;
byteenable <= 'b0;
if (command[2] == 1'b1) begin
//increment address, but word-align it
address[31:2] <= (address[31:2] + 1'b1);
end
if (last_trans) begin
state <= RETURN_PACKET;
out_startofpacket <= 1'b1;
out_data <= (8'h80 | command);
out_valid <= 1'b1;
current_byte <= 'h0;
in_ready_0 <= 1'b0;
end
end
end
RETURN_PACKET : begin
out_valid <= 1'b1;
if (out_ready) begin
case (current_byte)
// 0: begin
// out_startofpacket <= 1'b1;
// out_data <= (8'h80 | command);
// end
0: begin
out_data <= 8'b0;
end
1: begin
out_data <= counter[15:8];
end
2: begin
out_endofpacket <= 1'b1;
out_data <= counter[7:0];
end
default: begin
// out_data <= 8'b0;
// out_startofpacket <= 1'b0;
// out_endofpacket <= 1'b0;
end
endcase
current_byte <= current_byte + 1'b1;
if (current_byte == 3) begin
state <= READY;
out_valid <= 1'b0;
end
else state <= RETURN_PACKET;
end
end
READ_ASSERT : begin
if (current_byte == 3) byteenable <= unshifted_byteenable << 3;
if (current_byte == 2) byteenable <= unshifted_byteenable << 2;
if (current_byte == 1) byteenable <= unshifted_byteenable << 1;
if (current_byte == 0) byteenable <= unshifted_byteenable;
// byteenable <= unshifted_byteenable << current_byte;
read <= 1;
state <= READ_CMD_WAIT;
end
READ_CMD_WAIT : begin
read_data_buffer <= readdata[31:8];
out_data <= readdata[7:0];
read <= 1;
// if readdatavalid, take the data and
// go directly to READ_SEND_ISSUE. This is for fixed
// latency slaves. Ignore waitrequest in this case,
// since this master does not issue pipelined reads.
//
// For variable latency slaves, once waitrequest is low
// the read command is accepted, so deassert read and
// go to READ_DATA_WAIT to wait for readdatavalid
if (readdatavalid) begin
state <= READ_SEND_ISSUE;
read <= 0;
end else begin
if (~waitrequest) begin
state <= READ_DATA_WAIT;
read <= 0;
end
end
end
READ_DATA_WAIT : begin
read_data_buffer <= readdata[31:8];
out_data <= readdata[7:0];
if (readdatavalid) begin
state <= READ_SEND_ISSUE;
end
end
READ_SEND_ISSUE : begin
out_valid <= 1'b1;
out_startofpacket <= 'h0;
out_endofpacket <= 'h0;
if (counter == 1) begin
out_endofpacket <= 1'b1;
end
if (first_trans) begin
first_trans <= 1'b0;
out_startofpacket <= 1'b1;
end
case (current_byte)
3: begin
out_data <= read_data_buffer[23:16];
end
2: begin
out_data <= read_data_buffer[15:8];
end
1: begin
out_data <= read_data_buffer[7:0];
end
default: begin
out_data <= out_data;
end
endcase
state <= READ_SEND_WAIT;
end
READ_SEND_WAIT : begin
out_valid <= 1'b1;
if (out_ready) begin
counter <= counter - 1'b1;
current_byte <= current_byte + 1'b1;
out_valid <= 1'b0;
// count down on the number of bytes to read
// shift current byte location within word
// if increment address, add it, so the next read
// can use it, if more reads are required
// no more bytes to send - go to READY state
if (counter == 1) begin
state <= READY;
// end of current word, but we have more bytes to
// read - go back to READ_ASSERT
end else if (current_byte == 3) begin
if (command[2] == 1'b1) begin
//increment address, but word-align it
address[31:2] <= (address[31:2] + 1'b1);
end
state <= READ_ASSERT;
// continue sending current word
end else begin
state <= READ_SEND_ISSUE;
end
//maybe add in_ready_0 here so we are ready to go
//right away
end
end
endcase
if (enable & in_startofpacket) begin
state <= GET_EXTRA;
command <= in_data;
in_ready_0 <= 1'b1;
end
end // end else
end // end always block
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3B_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__NOR3B_PP_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3B_PP_BLACKBOX_V
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2000-2001 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised
// by a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement
// from Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================
// FILE DETAILS
// Project : pci_exp
// File : tb_top.v
// Title :
// Dependencies : pci_exp.v
// Description : Top level for testbench of pci_exp X4 IP with Serdes PCS PIPE
//
// =============================================================================
// REVISION HISTORY
// Version : 1.0
// Author(s) :
// Mod. Date : Aug 11, 2006
// Changes Made : Initial Creation
// =============================================================================
`timescale 100 ps/100 ps
module tb_top;
// DUT User defines
`include "pci_exp_params.v"
`include "pci_exp_dparams.v"
`include "pci_exp_ddefines.v"
// =============================================================================
// Regs for BFM & Test case
// =============================================================================
//---- Regs
reg clk_100;
reg error;
reg rst_n;
reg no_pcie_train; // This signal disables the training process
reg txtlpu_req ; // Request from TL for sending TLPs.
reg [63:0] txtlpu_data ; // Input data from TL.
reg txtlpu_st ; // start of TLP.
reg txtlpu_end ; // End of TLP.
reg txtlpu_nlfy ; // Nullify TLP.
reg ecrc_gen_enb ;
reg ecrc_chk_enb ;
reg rx_tlp_discard;
wire [23:0] tbtx_vc;
wire [23:0] tbrx_vc;
reg disable_mlfmd_check;
reg DISABLE_SKIP_CHECK;
wire [1:0] power_down_init;
wire [14:0] init_15_00;
wire [14:0] init_15_11;
wire [15:0] init_16_11;
reg enb_log;
//---- Wires
wire [2:0] rxdp_pmd_type;
wire [23:0] rxdp_vsd_data;
wire rxdp_vsd_val;
wire [1:0] rxdp_dllp_val;
wire dl_up;
wire sys_clk_125;
wire sys_clk_125_temp;
wire txdp_pm_sent;
wire [63:0] INIT_PH_FC; //Initial P HdrFC value
wire [63:0] INIT_NPH_FC; // For NPH
wire [63:0] INIT_CPLH_FC; // For CPLH
wire [95:0] INIT_PD_FC; // Initial P DataFC value
wire [95:0] INIT_NPD_FC; // For NPD
wire [95:0] INIT_CPLD_FC; // For CPLD
wire [71:0] tx_ca_ph;
wire [103:0] tx_ca_pd;
wire [71:0] tx_ca_nph;
wire [103:0] tx_ca_npd;
wire [71:0] tx_ca_cplh;
wire [103:0] tx_ca_cpld;
reg [7:0] tbrx_cmd_prsnt;
wire [7:0] tbrx_cmd_prsnt_int;
wire [7:0] ph_buf_status; // Indicate the Full/alm.Full status of the PH buffers
wire [7:0] pd_buf_status; // Indicate PD Buffer has got space less than Max Pkt size
wire [7:0] nph_buf_status; // For NPH
wire [7:0] npd_buf_status; // For NPD
wire [7:0] cplh_buf_status; // For CPLH
wire [7:0] cpld_buf_status; // For CPLD
wire [7:0] ph_processed; // TL has processed one TLP Header - PH Type
wire [7:0] pd_processed; // TL has processed one TLP Data - PD TYPE
wire [7:0] nph_processed; // For NPH
wire [7:0] npd_processed; // For NPD
wire [7:0] cplh_processed; // For CPLH
wire [7:0] cpld_processed; // For CPLD
//---------Outputs From Core------------
wire [7:0] tx_rdy;
wire [511:0] rx_data;
wire [7:0] rx_st;
wire [7:0] rx_end;
wire [7:0] rx_ecrc_err;
wire [7:0] rx_us_req;
wire [7:0] rx_malf_tlp;
wire [7:0] rx_pois_tlp;
wire [3:0] phy_ltssm_state;
wire [7:0] tx_req;
wire [2:0] rx_status;
wire [1:0] power_down;
wire tx_detect_rx;
wire tx_elec_idle;
wire tx_compliance;
wire rx_polarity;
wire [15:0] rx_valid;
wire [15:0] rx_elec_idle;
wire [15:0] phy_status;
wire rx_valid0; //For Debug
wire rx_elec_idle0;
wire phy_status0;
wire phy_realign_req;
//---- Integer
integer i;
//---------- TB_MUX signals
reg [3:0] tc_block_skip;
reg [3:0] tc_block_ts1;
reg [3:0] tc_mask_pad1;
reg [11:0] tc_allow_num1[0:3];
reg [3:0] tc_inv_polar;
reg [3:0] tc_change_laneid;
reg [3:0] tc_change_linkid;
reg [3:0] tc_change_nfts;
reg [31:0] tc_linkid;
reg [31:0] tc_laneid;
reg [31:0] tc_nfts;
wire [3:0] tbmux_allow_done1;
reg [3:0] tc_block_ts2;
reg [3:0] tc_mask_pad2;
reg [11:0] tc_allow_num2[0:3];
wire [3:0] tbmux_allow_done2;
reg [3:0] tc_force_ts1;
reg [3:0] tc_force_ts2;
reg [3:0] tc_linkid_en;
reg [3:0] tc_laneid_en;
reg [3:0] tc_lb;
reg [3:0] tc_dis;
reg [3:0] tc_hr;
reg [3:0] tc_force_EIos;
reg [3:0] tc_force_skip;
reg [3:0] tc_block_idle;
reg [4:0] tc_idle_cnt [0:3];
reg [3:0] tc_idle_gap;
reg [15:0] tx_lbk_data;
reg [1:0] tx_lbk_kcntl;
wire tx_lbk_rdy;
wire [15:0] rx_lbk_data;
wire [1:0] rx_lbk_kcntl;
wire [(`NUM_VC*16)-1:0] tx_data;
wire [`NUM_VC-1:0] tx_st;
wire [`NUM_VC-1:0] tx_end;
wire [`NUM_VC-1:0] tx_nlfy;
wire [`NUM_VC-1:0] tb_sys_clk;
parameter DLY1 = 1 ;
parameter DLY2 = 1 ;
// =============================================================================
// DUT Design params file
`include "pci_exp_ddefines.v"
// Include the test case
`include "test_rc.v"
// =============================================================================
//-------- For Flow Control Tasks
parameter P = 2'b00;
parameter NP = 2'b01;
parameter CPLX = 2'b10; //CPL is already used in some other paramter
parameter PH = 3'b000;
parameter PD = 3'b001;
parameter NPH = 3'b010;
parameter NPD = 3'b011;
parameter CPLH = 3'b100;
parameter CPLD = 3'b101;
//---- Wires
wire hdoutp_0 ;
wire hdoutn_0 ;
reg hdoutp_0_d ;
reg hdoutn_0_d ;
wire hdoutp_1 ;
wire hdoutn_1 ;
reg hdoutp_1_d ;
reg hdoutn_1_d ;
wire hdoutp_2 ;
wire hdoutn_2 ;
reg hdoutp_2_d ;
reg hdoutn_2_d ;
wire hdoutp_3 ;
wire hdoutn_3 ;
reg hdoutp_3_d ;
reg hdoutn_3_d ;
wire refclkp;
wire refclkn;
pullup (hdoutp_0);
pullup (hdoutn_0);
pullup (hdoutp_1);
pullup (hdoutn_1);
pullup (hdoutp_2);
pullup (hdoutn_2);
pullup (hdoutp_3);
pullup (hdoutn_3);
always @* begin
//0
if (!rst_n)
#DLY1 hdoutp_0_d <= hdoutp_0 ;
else if (hdoutp_0 == 1'b1)
#DLY1 hdoutp_0_d <= 1'b1 ;
else if (hdoutp_0 == 1'b0)
#DLY1 hdoutp_0_d <= 1'b0 ;
else if (hdoutp_0 === 1'bz)
#DLY1 hdoutp_0_d <= 1'b1 ;
else
#DLY1 hdoutp_0_d <= hdoutp_0_d ;
if (!rst_n)
#DLY1 hdoutn_0_d <= hdoutn_0 ;
else if (hdoutn_0 == 1'b1)
#DLY1 hdoutn_0_d <= 1'b1 ;
else if (hdoutn_0 == 1'b0)
#DLY1 hdoutn_0_d <= 1'b0 ;
else if (hdoutn_0 === 1'bz)
#DLY1 hdoutn_0_d <= 1'b1 ;
else
#DLY1 hdoutn_0_d <= hdoutn_0_d ;
end
always @* begin
//1
if (!rst_n)
#DLY1 hdoutp_1_d <= hdoutp_1 ;
else if (hdoutp_1 == 1'b1)
#DLY1 hdoutp_1_d <= 1'b1 ;
else if (hdoutp_1 == 1'b0)
#DLY1 hdoutp_1_d <= 1'b0 ;
else if (hdoutp_1 === 1'bz)
#DLY1 hdoutp_1_d <= 1'b1 ;
else
#DLY1 hdoutp_1_d <= hdoutp_1_d ;
if (!rst_n)
#DLY1 hdoutn_1_d <= hdoutn_1 ;
else if (hdoutn_1 == 1'b1)
#DLY1 hdoutn_1_d <= 1'b1 ;
else if (hdoutn_1 == 1'b0)
#DLY1 hdoutn_1_d <= 1'b0 ;
else if (hdoutn_1 === 1'bz)
#DLY1 hdoutn_1_d <= 1'b1 ;
else
#DLY1 hdoutn_1_d <= hdoutn_1_d ;
end
always @* begin
//2
if (!rst_n)
#DLY1 hdoutp_2_d <= hdoutp_2 ;
else if (hdoutp_2 == 1'b1)
#DLY1 hdoutp_2_d <= 1'b1 ;
else if (hdoutp_2 == 1'b0)
#DLY1 hdoutp_2_d <= 1'b0 ;
else if (hdoutp_2 === 1'bz)
#DLY1 hdoutp_2_d <= 1'b1 ;
else
#DLY1 hdoutp_2_d <= hdoutp_2_d ;
if (!rst_n)
#DLY1 hdoutn_2_d <= hdoutn_2 ;
else if (hdoutn_2 == 1'b1)
#DLY1 hdoutn_2_d <= 1'b1 ;
else if (hdoutn_2 == 1'b0)
#DLY1 hdoutn_2_d <= 1'b0 ;
else if (hdoutn_2 === 1'bz)
#DLY1 hdoutn_2_d <= 1'b1 ;
else
#DLY1 hdoutn_2_d <= hdoutn_2_d ;
end
always @* begin
//3
if (!rst_n)
#DLY1 hdoutp_3_d <= hdoutp_3 ;
else if (hdoutp_3 == 1'b1)
#DLY1 hdoutp_3_d <= 1'b1 ;
else if (hdoutp_3 == 1'b0)
#DLY1 hdoutp_3_d <= 1'b0 ;
else if (hdoutp_3 === 1'bz)
#DLY1 hdoutp_3_d <= 1'b1 ;
else
#DLY1 hdoutp_3_d <= hdoutp_3_d ;
if (!rst_n)
#DLY1 hdoutn_3_d <= hdoutn_3 ;
else if (hdoutn_3 == 1'b1)
#DLY1 hdoutn_3_d <= 1'b1 ;
else if (hdoutn_3 == 1'b0)
#DLY1 hdoutn_3_d <= 1'b0 ;
else if (hdoutn_3 === 1'bz)
#DLY1 hdoutn_3_d <= 1'b1 ;
else
#DLY1 hdoutn_3_d <= hdoutn_3_d ;
end
// =============================================================================
// PIPE_SIGNALS For Debug -- For X1
// =============================================================================
assign rx_valid0 = rx_valid[0];
assign rx_elec_idle0 = rx_elec_idle[0];
assign phy_status0 = phy_status[0];
// =============================================================================
// Generate tbrx_cmd_prsnt
// =============================================================================
always@(sys_clk_125) begin
tbrx_cmd_prsnt[7] <= (tbrx_cmd_prsnt_int[7] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[6] <= (tbrx_cmd_prsnt_int[6] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[5] <= (tbrx_cmd_prsnt_int[5] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[4] <= (tbrx_cmd_prsnt_int[4] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[3] <= (tbrx_cmd_prsnt_int[3] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[2] <= (tbrx_cmd_prsnt_int[2] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[1] <= (tbrx_cmd_prsnt_int[1] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[0] <= (tbrx_cmd_prsnt_int[0] === 1'b1) ? 1'b1 : 1'b0;
end
assign tbrx_vc = 3'd0;
assign tbtx_vc = 3'd0;
assign power_down_init = 2'b10;
assign init_15_00 = 15'b0000_0000_0000_000;
assign init_15_11 = 15'b1111_1111_1111_111;
assign init_16_11 = 16'b1111_1111_1111_1111;
// =============================================================================
// TBTX (User Logic on TX side) Instantiations
// =============================================================================
tbtx u_tbtx [`NUM_VC-1:0] (
//----- Inputs
.sys_clk (sys_clk_125),
.rst_n (rst_n),
.tx_tc (tbtx_vc[(`NUM_VC*3)-1:0]),
.tx_ca_ph (tx_ca_ph[(9*`NUM_VC)-1:0]),
.tx_ca_pd (tx_ca_pd[(13*`NUM_VC)-1:0]),
.tx_ca_nph (tx_ca_nph[(9*`NUM_VC)-1:0]),
.tx_ca_npd (tx_ca_npd[(13*`NUM_VC)-1:0]),
.tx_ca_cplh (tx_ca_cplh[(9*`NUM_VC)-1:0]),
.tx_ca_cpld (tx_ca_cpld[(13*`NUM_VC)-1:0]),
.tx_ca_p_recheck ( 1'b0 ),
.tx_ca_cpl_recheck ( 1'b0 ),
.tx_rdy (tx_rdy[`NUM_VC-1:0]),
//------- Outputs
.tx_req (tx_req[`NUM_VC-1:0]),
.tx_data (tx_data),
.tx_st (tx_st),
.tx_end (tx_end),
.tx_nlfy (tx_nlfy)
);
// =============================================================================
// TBRX (User Logic on RX side) Instantiations
// =============================================================================
tbrx u_tbrx [`NUM_VC-1:0] (
//----- Inputs
.sys_clk (sys_clk_125),
.rst_n (rst_n),
.rx_tc (tbrx_vc[(`NUM_VC*3)-1:0]),
.rx_data ( rx_data[(`NUM_VC*16)-1:0]),
.rx_st ( rx_st[`NUM_VC -1:0]),
.rx_end ( rx_end[`NUM_VC -1:0]),
`ifdef ECRC
.rx_ecrc_err ( rx_ecrc_err[`NUM_VC -1:0] ),
`endif
.rx_us_req ( rx_us_req[`NUM_VC -1:0] ),
.rx_malf_tlp ( rx_malf_tlp[`NUM_VC -1:0] ),
//------- Outputs
.tbrx_cmd_prsnt (tbrx_cmd_prsnt_int[`NUM_VC-1:0]),
.ph_buf_status (ph_buf_status[`NUM_VC-1:0]),
.pd_buf_status (pd_buf_status[`NUM_VC-1:0]),
.nph_buf_status (nph_buf_status[`NUM_VC-1:0]),
.npd_buf_status (npd_buf_status[`NUM_VC-1:0]),
.cplh_buf_status (cplh_buf_status[`NUM_VC-1:0]),
.cpld_buf_status (cpld_buf_status[`NUM_VC-1:0]),
.ph_processed (ph_processed[`NUM_VC-1:0]),
.pd_processed (pd_processed[`NUM_VC-1:0]),
.nph_processed (nph_processed[`NUM_VC-1:0]),
.npd_processed (npd_processed[`NUM_VC-1:0]),
.cplh_processed (cplh_processed[`NUM_VC-1:0]),
.cpld_processed (cpld_processed[`NUM_VC-1:0]),
.pd_num ( ),
.npd_num ( ),
.cpld_num ( ),
.INIT_PH_FC ( ),
.INIT_NPH_FC ( ),
.INIT_CPLH_FC ( ),
.INIT_PD_FC ( ),
.INIT_NPD_FC ( ),
.INIT_CPLD_FC ( )
);
// =============================================================================
// DUT
// =============================================================================
`USERNAME_EVAL_TOP u1_top(
//------- Clock and Reset
.refclkp ( clk_100),
.refclkn ( ~clk_100),
.sys_clk_125 ( sys_clk_125_temp ),
.rst_n ( rst_n ),
.hdinp0 ( hdoutp_0_d ),
.hdinn0 ( hdoutn_0_d ),
.hdoutp0 ( hdoutp_0 ),
.hdoutn0 ( hdoutn_0 ),
// To RXFC
// Following are Advertised during Initialization
.tx_req_vc0 (tx_req[0]),
.tx_data_vc0 (tx_data[16*1-1:0]),
.tx_st_vc0 (tx_st[0]),
.tx_end_vc0 (tx_end[0]),
.tx_nlfy_vc0 (tx_nlfy[0]),
.ph_buf_status_vc0 (ph_buf_status[0]),
.pd_buf_status_vc0 (pd_buf_status[0]),
.nph_buf_status_vc0 (nph_buf_status[0]),
.npd_buf_status_vc0 (npd_buf_status[0]),
.cplh_buf_status_vc0 (cplh_buf_status[0]),
.cpld_buf_status_vc0 (cpld_buf_status[0]),
.ph_processed_vc0 (ph_processed[0]),
.pd_processed_vc0 (pd_processed[0]),
.nph_processed_vc0 (nph_processed[0]),
.npd_processed_vc0 (npd_processed[0]),
.cplh_processed_vc0 (cplh_processed[0]),
.cpld_processed_vc0 (cpld_processed[0]),
`ifdef ECRC
.ecrc_gen_enb ( ecrc_gen_enb ) ,
.ecrc_chk_enb ( ecrc_chk_enb ) ,
`endif
.tx_rdy_vc0 (tx_rdy[0]),
.tx_ca_ph_vc0 (tx_ca_ph[(9*1)-1:0]),
.tx_ca_pd_vc0 (tx_ca_pd[(13*1)-1:0]),
.tx_ca_nph_vc0 (tx_ca_nph[(9*1)-1:0]),
.tx_ca_npd_vc0 (tx_ca_npd[(13*1)-1:0]),
.tx_ca_cplh_vc0 (tx_ca_cplh[(9*1)-1:0]),
.tx_ca_cpld_vc0 (tx_ca_cpld[(13*1)-1:0]),
// Inputs/Outputs per VC
.rx_data_vc0 ( rx_data[(16*1)-1:0]),
.rx_st_vc0 ( rx_st[0]),
.rx_end_vc0 ( rx_end[0]),
`ifdef ECRC
.rx_ecrc_err_vc0 ( rx_ecrc_err[0] ),
`endif
.rx_pois_tlp_vc0 ( rx_pois_tlp[0] ),
.rx_malf_tlp_vc0 ( rx_malf_tlp[0] ),
.inta_n ( ),
.intb_n ( ),
.intc_n ( ),
.intd_n ( ),
.ftl_err_msg ( ),
.nftl_err_msg ( ),
.cor_err_msg ( )
);
// ====================================================================
// Initilize the design
// ====================================================================
initial begin
error = 1'b0;
rst_n = 1'b0;
clk_100 = 1'b0;
rx_tlp_discard = 0;
enb_log = 1'b0 ;
ecrc_gen_enb = 1'b0;
ecrc_chk_enb = 1'b0;
end
// =============================================================================
// Timeout generation to finish hung test cases.
// =============================================================================
parameter TIMEOUT_NUM = 150000;
initial begin
repeat (TIMEOUT_NUM) @(posedge sys_clk_125);
$display(" ERROR : First - Simulation Time Out, Test case Terminated at time : %0t", $time) ;
repeat (TIMEOUT_NUM) @(posedge sys_clk_125);
$display(" ERROR : Second - Simulation Time Out, Test case Terminated at time : %0t", $time) ;
//$finish ;
end
// =============================================================================
// Simulation Time Display for long test cases
initial begin
forever begin
#100000; //every 10k (add extra zero - timescale) ns just display Time value - useful for SDF sim
$display(" Displaying Sim. Time : %0t", $time) ;
end
end
// =============================================================================
initial begin
$timeformat (-9 ,1 , "ns", 10);
`ifdef REGRESS
`else
`ifdef NO_DUMP
`else
//$recordfile ("pcie_test.trn");
//$recordvars ();
//$shm_open ("pcie_test.shm");
//$shm_probe ("ACMTF");
`endif
`endif
end
// =============================================================================
// Clocks generation
// =============================================================================
// 100 Mhz clock input to PLL to generate 125MHz for PCS
always #50 clk_100 <= ~clk_100 ;
`ifdef SDF_SIM
assign sys_clk_125 = u1_top.sys_clk_125_c;
assign tb_sys_clk = u1_top.\u1_pcie_top/pclk;
`else
assign sys_clk_125 = sys_clk_125_temp;
assign tb_sys_clk = u1_top.u1_pcie_top.pclk;
`endif
// =============================================================================
// =============================================================================
initial begin
`ifdef SDF_SIM
//$sdf_annotate("../../../../par/ecp2m/config1/synplicity/top/verilog/pci_exp_x4_top.sdf", u1_top,, "pci_exp_x4_top_sdf.log");
`endif
end
// =============================================================================
// Reset Task
// =============================================================================
task RST_DUT;
begin
repeat(2) @(negedge clk_100);
#40000;
rst_n = 1'b1;
repeat (50) @ (posedge clk_100) ;
force u1_top.u1_pcie_top.core_rst_n = 1'b1; // de-assert delayed reset to core
repeat(10) @(negedge clk_100);
end
endtask
// =============================================================================
// Reset Task
// =============================================================================
task DEFAULT_CREDITS;
reg [2:0] tmp_vcid;
begin
for(i=0; i<= `NUM_VC-1; i=i+1) begin
tmp_vcid = i;
case(tmp_vcid)
`ifdef EN_VC0
0 : begin
u_tbrx[0].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[0].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[0].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC1
1 : begin
u_tbrx[1].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[1].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[1].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC2
2 : begin
u_tbrx[2].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[2].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[2].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC3
3 : begin
u_tbrx[3].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[3].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[3].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC5
4 : begin
u_tbrx[4].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[4].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[4].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC5
5 : begin
u_tbrx[5].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[5].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[5].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC6
6 : begin
u_tbrx[6].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[6].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[6].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC7
7 : begin
u_tbrx[7].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[7].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[7].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
endcase
end
end
endtask
// =============================================================================
// Check on error signal & stop simulation if error = 1
// =============================================================================
always @(posedge sys_clk_125) begin
if (error) begin
repeat (200) @(posedge sys_clk_125);
$finish;
end
end
// =============================================================================
// TBTX TASKS
// =============================================================================
// HEADER FORMAT FOR MEM READ
// (Fmt & Type decides what kind of Request)
// ================================================
// R Fmt Type R TC R R R R TD EP ATTR R Length
// Requester ID -- TAG -- Last DW BE -- First DW BE
// ---------- Address [63:32] -------------------
// --------- Address [31:2] ----------------- R
// ================================================
// Fixed values :
// Fmt[1] = 0
// First DW BE = 4'b0000
// Last DW BE = 4'b0000
// ATTR is always 2'b00 {Ordering, Snoop} = {0,0} -> {Strong Order, Snoop}
// Arguments :
// TC/VC, Address[31:2], Fmt[0]/hdr_Type, Length
// Registers that are used :
// TBTX_TD, TBTX_EP, First_DW_BE, TBTX_UPPER32_ADDR
// For hdr_type 4 DW TBTX_UPPER32_ADDR is used (and Fmt[0] = 1)
//
// NOTE : Length is not the LENGTH of this MEM_RD Pkt
// =============================================================================
task tbtx_mem_rd;
input [2:0] vcid;
input [31:0] addr;
input [9:0] length;
input hdr_type; //0: 3 DW Header --- 1: 4 DW (with TBTX_UPPER32_ADDR)
begin
//tbtx_vc = vcid;
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_mem_rd(addr,length,hdr_type);
`endif
endcase
end
endtask
// =============================================================================
// HEADER FORMAT FOR MEM WRITE
// (Fmt & Type decides what kind of Request)
// ================================================
// R Fmt Type R TC R R R R TD EP ATTR R Length
// Requester ID -- TAG -- Last DW BE -- First DW BE
// ---------- Address [63:32] -------------------
// --------- Address [31:2] ----------------- R
// ================================================
// Arguments :
// TC/VC, Address[31:2], Fmt[0]/hdr_Type
// Registers that are used :
// TBTX_TD, TBTX_EP, First_DW_BE, Last_DW_BE, TBTX_UPPER32_ADDR
// For hdr_type 4 DW TBTX_UPPER32_ADDR is used (and Fmt[0] = 1)
// =============================================================================
task tbtx_mem_wr;
input [2:0] vcid;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [9:0] nul_len;
input nullify;
begin
//tbtx_vc = vcid;
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
endcase
end
endtask
// =============================================================================
task tbtx_msg;
input [2:0] vcid;
begin
//tbtx_vc = vcid;
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_msg;
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_msg;
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_msg;
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_msg;
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_msg;
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_msg;
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_msg;
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_msg;
`endif
endcase
end
endtask
// =============================================================================
task tbtx_msg_d;
input [2:0] vcid;
input [9:0] length;
input [9:0] nul_len;
input nullify;
begin
//tbtx_vc = vcid;
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_msg_d(length, nul_len, nullify);
`endif
endcase
end
endtask
// =============================================================================
task tbtx_cfg_rd;
input cfg; //0: cfg0, 1: cfg1
input [31:0] addr; //{Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00}
begin
u_tbtx[0].tbtx_cfg_rd(cfg, addr);
end
endtask
// =============================================================================
task tbtx_cfg_wr;
input cfg; //0: cfg0, 1: cfg1
input [31:0] addr; //{Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00}
begin
u_tbtx[0].tbtx_cfg_wr(cfg, addr);
end
endtask
// =============================================================================
task tbtx_io_rd;
input [31:0] addr;
begin
u_tbtx[0].tbtx_io_rd(addr);
end
endtask
// =============================================================================
task tbtx_io_wr;
input [31:0] addr;
begin
u_tbtx[0].tbtx_io_wr(addr);
end
endtask
// =============================================================================
task tbtx_cpl;
input [2:0] vcid;
input [11:0] byte_cnt;
input [6:0] lower_addr;
input [2:0] status;
begin
//tbtx_vc = vcid;
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
endcase
end
endtask
// =============================================================================
task tbtx_cpl_d;
input [2:0] vcid;
input [11:0] byte_cnt;
input [6:0] lower_addr;
input [2:0] status;
input [9:0] length;
input [9:0] nul_len;
input nullify;
begin
//tbtx_vc = vcid;
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
endcase
end
endtask
// =============================================================================
// TBRX TASKS
// =============================================================================
// Error Types
// NO_TLP_ERR = 4'b0000;
// ECRC_ERR = 4'b0001;
// UNSUP_ERR = 4'b0010;
// MALF_ERR = 4'b0011;
// FMT_TYPE_ERR = 4'b1111;
// =============================================================================
// tbrx_tlp:
// This task is used when User wants create TLP manually
// For fmt_type error this should be used, no other tasks supports this error.
// =============================================================================
task tbrx_tlp; //When Giving Malformed TLP (Only fmt & Type error)
input [2:0] vcid;
input [3:0] Error_Type;
input hdr_type; //3 DW or 4 DW
input [31:0] h1_msb;
input [31:0] h1_lsb;
input [31:0] h2_msb;
input [31:0] h2_lsb;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_mem_rd;
input [2:0] vcid;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_mem_wr;
input [2:0] vcid;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_msg;
input [2:0] vcid;
input [9:0] length;
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_msg(length,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_msg_d;
input [2:0] vcid;
input [9:0] length;
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_msg_d(length, Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_cfg_rd;
input cfg; //0: cfg0, 1: cfg1
input [31:0] addr; //{Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00}
input [9:0] length;
input [3:0] Error_Type;
begin
u_tbrx[0].tbrx_cfg_rd(cfg, addr,length, Error_Type);
end
endtask
// =============================================================================
task tbrx_cfg_wr;
input cfg; //0: cfg0, 1: cfg1
input [31:0] addr; //{Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00}
input [9:0] length;
input [3:0] Error_Type;
begin
u_tbrx[0].tbrx_cfg_wr(cfg, addr,length, Error_Type);
end
endtask
// =============================================================================
task tbrx_io_rd;
input [31:0] addr;
input [9:0] length;
input [3:0] Error_Type;
begin
u_tbrx[0].tbrx_io_rd(addr,length, Error_Type);
end
endtask
// =============================================================================
task tbrx_io_wr;
input [31:0] addr;
input [9:0] length;
input [3:0] Error_Type;
begin
u_tbrx[0].tbrx_io_wr(addr,length, Error_Type);
end
endtask
// =============================================================================
task tbrx_cpl;
input [2:0] vcid;
input [11:0] byte_cnt;
input [6:0] lower_addr;
input [2:0] status;
input [9:0] length;
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_cpl_d;
input [2:0] vcid;
input [11:0] byte_cnt;
input [6:0] lower_addr;
input [2:0] status;
input [9:0] length;
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
// TASKS WITH TC INPUT
// =============================================================================
task tbrx_mem_rd_tc;
input [2:0] vcid;
input [2:0] tc;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_mem_wr_tc;
input [2:0] vcid;
input [2:0] tc;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
// FLOW CONTROL TASKS
// =============================================================================
// Setting INIT values
// =============================================================================
task FC_INIT;
input [2:0] vcid;
input [1:0] type; // p/np/cpl
input [7:0] hdr;
input [11:0] data;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].FC_INIT(type, hdr, data);
`endif
endcase
end
endtask
// =============================================================================
// Asserion/Deassertion of buf_status signals
// =============================================================================
task FC_BUF_STATUS;
input [2:0] vcid;
input [2:0] type; // ph/pd/nph/npd/cpl/cpld
input set; // Set=1: Assert the signal , Set=0, De-assert the signal
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].FC_BUF_STATUS(type, set);
`endif
endcase
end
endtask
// =============================================================================
// Asserion/Deassertion of Processed signals
// Onle pulse
// =============================================================================
task FC_PROCESSED;
input [2:0] vcid;
input [2:0] type; // ph/pd/nph/npd/cpl/cpld
input set; // Set=1: Assert the signal , Set=0, De-assert the signal
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].FC_PROCESSED(type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].FC_PROCESSED(type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].FC_PROCESSED(type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].FC_PROCESSED(type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].FC_PROCESSED(type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].FC_PROCESSED(type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].FC_PROCESSED(type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].FC_PROCESSED(type);
`endif
endcase
end
endtask
endmodule
// =============================================================================
//$Log: PCI_EXP_x4_11/technology/ver1.0/testbench/beh/tb_top_ecp2m_rc.v $
|
Require Export Arith.
Require Export ArithRing.
Require Export Omega.
Ltac CaseEq f := generalize (refl_equal f);
pattern f at -1 in |- *; case f.
Fixpoint div4 (n:nat) : nat * nat :=
match n with
| S (S (S (S p))) => let (q, r) := div4 p in (S q, r)
| a => (0, a)
end.
Fixpoint bsqrt (n b:nat) {struct b} : nat * nat :=
match b with
| O => (0, 0)
| S b' =>
match div4 n with
| (O, O) => (0, 0)
| (O, S p) => (1, p)
| (q, r0) =>
let (s', r') := bsqrt q b' in
match le_gt_dec (4 * s' + 1) (4 * r' + r0) with
| left _ => (2 * s' + 1, 4 * r' + r0 - (4 * s' + 1))
| right _ => (2 * s', 4 * r' + r0)
end
end
end.
(* We start by proving a few basic properties of division by 4.
As suggested in section 8.3.1, we can use a specific induction
principle to work on div4. This is also the solution to exercise
\ref{quadruple_induction}. *)
Theorem div4_ind :
forall P:nat -> Prop,
P 0 ->
P 1 ->
P 2 ->
P 3 -> (forall n:nat, P n -> P (S (S (S (S n))))) -> forall n:nat, P n.
Proof.
intros P P0 P1 P2 P3 Prec n.
cut (P n /\ P (S n) /\ P (S (S n)) /\ P (S (S (S n)))).
intuition.
elim n; intuition.
Qed.
(* Proving the main characteristics of div4 is easy using
div4_ind. We avoid using Simpl so that multiplications
do not get unfolded into additions. *)
Lemma div4_exact : forall n:nat, let (q, r) := div4 n in n = 4 * q + r.
Proof.
intros n; elim n using div4_ind; try (simpl in |- *; auto; fail).
intros p; cbv beta iota zeta delta [div4] in |- *; fold div4 in |- *.
case (div4 p).
intros q r Hrec; rewrite Hrec; ring.
Qed.
(* Since 4 is a constant, we can use div4_exact to
obtain a linear equality in the sense of Presburger arithmetic
and the Omega decision procedure can cope with the formula.*)
Theorem div4_lt : forall n:nat, let (q, r) := div4 n in 0 < q -> q < n.
Proof.
intros n; generalize (div4_exact n); case (div4 n).
intros q r Heq; omega.
Qed.
Theorem div4_lt_rem : forall n:nat, let (q, r) := div4 n in r < 4.
Proof.
intros n; elim n using div4_ind; try (simpl in |- *; auto with arith).
intros p; case (div4 p); auto.
Qed.
Ltac remove_minus :=
match goal with
| |- context [(?X1 - ?X2 + ?X3)] =>
rewrite <- (plus_comm X3); remove_minus
| |- context [(?X1 + (?X2 - ?X3) + ?X4)] =>
rewrite (plus_assoc_reverse X1 (X2 - X3)); remove_minus
| |- context [(?X1 + (?X2 + (?X3 - ?X4)))] =>
rewrite (plus_assoc X1 X2 (X3 - X4))
| |- (_ = ?X1 + (?X2 - ?X3)) =>
apply (fun n m p:nat => plus_reg_l m p n) with X3;
try rewrite (plus_permute X3 X1 (X2 - X3));
rewrite le_plus_minus_r
end.
(* The proof of this goal is a simple matter of computation, but
NatRing can't cope with it because of the irregular behavior of
minus. The tactic remove_minus defined above takes care of that by
adding the subtracted term on both side of the equality, and then
simplifying with le_plus_minus. This simplification only works
because the theorem has the right hypothesis. *)
Theorem bsqrt_exact_lemma_le :
forall n q r s' r':nat,
n = 4 * q + r ->
q = s' * s' + r' ->
4 * s' + 1 <= 4 * r' + r ->
n = (2 * s' + 1) * (2 * s' + 1) + (4 * r' + r - (4 * s' + 1)).
Proof.
intros; remove_minus.
subst; ring.
assumption.
Qed.
Lemma bsqrt_exact_lemma_gt :
forall n q r s' r':nat,
n = 4 * q + r ->
q = s' * s' + r' ->
4 * s' + 1 > 4 * r' + r -> n = 2 * s' * (2 * s') + (4 * r' + r).
Proof.
intros; subst; ring.
Qed.
Theorem bsqrt_exact :
forall b n:nat, n <= b -> let (s, r) := bsqrt n b in n = s * s + r.
Proof.
(* Induction on the bound, as should always be the case
for bounded recursive functions. *)
intros b; elim b.
(* When the bound is zero, if n is lower than the bound, it
is also 0, it is only a matter of computation to check the
equality. *)
intros n Hle; rewrite <- (le_n_O_eq _ Hle); simpl in |- *; auto.
(*We limit simplification to the bsqrt function. *)
intros b' Hrec n Hle; cbv beta iota zeta delta [bsqrt] in |- *;
fold bsqrt in |- *.
(* We use the lemmas on div4. To avoid CaseEq, we rely on
Generalize before doing a Case analysis. *)
generalize (div4_lt n) (div4_exact n).
case (div4 n).
intros q r.
case q.
case r; intros; subst; ring.
intros q' Hlt Heq; generalize (Hrec (S q')).
case (bsqrt (S q') b').
intros s' r' Hrec'.
(* Because le_gt_dec is a well-specified function,
there is no need to generalize hypotheses to perform
the case analysis on this function call. *)
case (le_gt_dec (4 * s' + 1) (4 * r' + r)).
apply bsqrt_exact_lemma_le with (S q'); auto; omega.
apply bsqrt_exact_lemma_gt with (S q'); auto; omega.
Qed.
Theorem bsqrt_rem :
forall b n:nat, n <= b ->
let (s, r) := bsqrt n b in n < (s + 1) * (s + 1).
Proof.
intros b; elim b.
intros n Hle; rewrite <- (le_n_O_eq _ Hle);
simpl in |- *; auto with arith.
(*We limit simplification to the bsqrt function. *)
intros b' Hrec n Hle; generalize (bsqrt_exact (S b') n Hle);
cbv beta iota zeta delta [bsqrt] in |- *; fold bsqrt in |- *.
(* We use the lemmas on div4. To avoid CaseEq, we rely on
Generalize before doing a Case analysis. *)
generalize (div4_lt n) (div4_exact n) (div4_lt_rem n).
case (div4 n).
intros q r.
case q.
case r; intros; subst; simpl in |- *; auto with arith.
intros q' Hlt Heq Hlt_rem; generalize (Hrec (S q')).
case (bsqrt (S q') b').
intros s' r' Hrec'.
(* Because le_gt_dec is a well-specified function,
there is no need to generalize hypothesese to perform
the case analysis on this function call. *)
case (le_gt_dec (4 * s' + 1) (4 * r' + r)).
intros Hle' Heq'; rewrite Heq.
apply lt_le_trans with (4 * S q' + 4).
auto with arith.
replace ((2 * s' + 1 + 1) * (2 * s' + 1 + 1)) with
(4 * ((s' + 1) * (s' + 1))).
abstract omega.
ring.
intros Hgt Heq'; rewrite Heq'.
match goal with
| |- (?X1 < ?X2) => ring_simplify X1; ring_simplify X2
end.
abstract omega.
Qed.
Definition sqrt_nat :
forall n:nat,
{s : nat & {r : nat | n = s * s + r /\ n < (s + 1) * (s + 1)}}.
intros n;
generalize (bsqrt_exact n n (le_n n)) (bsqrt_rem n n (le_n n));
case (bsqrt n n).
intros s r H1 H2; exists s; exists r; auto.
Defined.
Eval compute in (bsqrt 37 37).
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V
`define SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V |
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 11.0 Build 157 04/27/2011
`ifdef MODEL_TECH
`mti_v2k_int_delays_on
`endif
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** DFFE
primitive ARRIAIIGZ_PRIM_DFFE (Q, ENA, D, CLK, CLRN, PRN, notifier);
input D;
input CLRN;
input PRN;
input CLK;
input ENA;
input notifier;
output Q; reg Q;
initial Q = 1'b0;
table
// ENA D CLK CLRN PRN notifier : Qt : Qt+1
(??) ? ? 1 1 ? : ? : -; // pessimism
x ? ? 1 1 ? : ? : -; // pessimism
1 1 (01) 1 1 ? : ? : 1; // clocked data
1 1 (01) 1 x ? : ? : 1; // pessimism
1 1 ? 1 x ? : 1 : 1; // pessimism
1 0 0 1 x ? : 1 : 1; // pessimism
1 0 x 1 (?x) ? : 1 : 1; // pessimism
1 0 1 1 (?x) ? : 1 : 1; // pessimism
1 x 0 1 x ? : 1 : 1; // pessimism
1 x x 1 (?x) ? : 1 : 1; // pessimism
1 x 1 1 (?x) ? : 1 : 1; // pessimism
1 0 (01) 1 1 ? : ? : 0; // clocked data
1 0 (01) x 1 ? : ? : 0; // pessimism
1 0 ? x 1 ? : 0 : 0; // pessimism
0 ? ? x 1 ? : ? : -;
1 1 0 x 1 ? : 0 : 0; // pessimism
1 1 x (?x) 1 ? : 0 : 0; // pessimism
1 1 1 (?x) 1 ? : 0 : 0; // pessimism
1 x 0 x 1 ? : 0 : 0; // pessimism
1 x x (?x) 1 ? : 0 : 0; // pessimism
1 x 1 (?x) 1 ? : 0 : 0; // pessimism
// 1 1 (x1) 1 1 ? : 1 : 1; // reducing pessimism
// 1 0 (x1) 1 1 ? : 0 : 0;
1 ? (x1) 1 1 ? : ? : -; // spr 80166-ignore
// x->1 edge
1 1 (0x) 1 1 ? : 1 : 1;
1 0 (0x) 1 1 ? : 0 : 0;
? ? ? 0 0 ? : ? : 0; // clear wins preset
? ? ? 0 1 ? : ? : 0; // asynch clear
? ? ? 1 0 ? : ? : 1; // asynch set
1 ? (?0) 1 1 ? : ? : -; // ignore falling clock
1 ? (1x) 1 1 ? : ? : -; // ignore falling clock
1 * ? ? ? ? : ? : -; // ignore data edges
1 ? ? (?1) ? ? : ? : -; // ignore edges on
1 ? ? ? (?1) ? : ? : -; // set and clear
0 ? ? 1 1 ? : ? : -; // set and clear
? ? ? 1 1 * : ? : x; // spr 36954 - at any
// notifier event,
// output 'x'
endtable
endprimitive
primitive ARRIAIIGZ_PRIM_DFFEAS (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b0;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier: q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
primitive ARRIAIIGZ_PRIM_DFFEAS_HIGH (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b1;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier : q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
module arriaiigz_dffe ( Q, CLK, ENA, D, CLRN, PRN );
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);
buf (CLRN_ipd, CLRN);
wire legal;
reg viol_notifier;
ARRIAIIGZ_PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier );
and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
specify
specparam TREG = 0;
specparam TREN = 0;
specparam TRSU = 0;
specparam TRH = 0;
specparam TRPR = 0;
specparam TRCL = 0;
$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
endspecify
endmodule
// ***** arriaiigz_mux21
module arriaiigz_mux21 (MO, A, B, S);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf(A_in, A);
buf(B_in, B);
buf(S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule
// ***** arriaiigz_mux41
module arriaiigz_mux41 (MO, IN0, IN1, IN2, IN3, S);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf(IN0_in, IN0);
buf(IN1_in, IN1);
buf(IN2_in, IN2);
buf(IN3_in, IN3);
buf(S1_in, S[1]);
buf(S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule
// ***** arriaiigz_and1
module arriaiigz_and1 (Y, IN1);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule
// ***** arriaiigz_and16
module arriaiigz_and16 (Y, IN1);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[8], IN1[8]);
buf (Y[9], IN1[9]);
buf (Y[10], IN1[10]);
buf (Y[11], IN1[11]);
buf (Y[12], IN1[12]);
buf (Y[13], IN1[13]);
buf (Y[14], IN1[14]);
buf (Y[15], IN1[15]);
endmodule
// ***** arriaiigz_bmux21
module arriaiigz_bmux21 (MO, A, B, S);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** arriaiigz_b17mux21
module arriaiigz_b17mux21 (MO, A, B, S);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** arriaiigz_nmux21
module arriaiigz_nmux21 (MO, A, B, S);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
// ***** arriaiigz_b5mux21
module arriaiigz_b5mux21 (MO, A, B, S);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
//--------------------------------------------------------------------
//
// Module Name : arriaiigz_jtag
//
// Description : Stratix JTAG Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_jtag (
tms,
tck,
tdi,
ntrst,
tdoutap,
tdouser,
tdo,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user);
input tms;
input tck;
input tdi;
input ntrst;
input tdoutap;
input tdouser;
output tdo;
output tmsutap;
output tckutap;
output tdiutap;
output shiftuser;
output clkdruser;
output updateuser;
output runidleuser;
output usr1user;
parameter lpm_type = "arriaiigz_jtag";
endmodule
//--------------------------------------------------------------------
//
// Module Name : arriaiigz_crcblock
//
// Description : Stratix CRCBLOCK Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_crcblock (
clk,
shiftnld,
crcerror,
regout);
input clk;
input shiftnld;
output crcerror;
output regout;
assign crcerror = 1'b0;
assign regout = 1'b0;
parameter oscillator_divider = 1;
parameter lpm_type = "arriaiigz_crcblock";
parameter crc_deld_disable = "off";
parameter error_delay = 0 ;
parameter error_dra_dl_bypass = "off";
endmodule
//------------------------------------------------------------------
//
// Module Name : arriaiigz_lcell_comb
//
// Description : ARRIAIIGZ LCELL_COMB Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_lcell_comb (
dataa,
datab,
datac,
datad,
datae,
dataf,
datag,
cin,
sharein,
combout,
sumout,
cout,
shareout
);
input dataa;
input datab;
input datac;
input datad;
input datae;
input dataf;
input datag;
input cin;
input sharein;
output combout;
output sumout;
output cout;
output shareout;
parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;
parameter shared_arith = "off";
parameter extended_lut = "off";
parameter dont_touch = "off";
parameter lpm_type = "arriaiigz_lcell_comb";
// sub masks
wire [15:0] f0_mask;
wire [15:0] f1_mask;
wire [15:0] f2_mask;
wire [15:0] f3_mask;
// sub lut outputs
reg f0_out;
reg f1_out;
reg f2_out;
reg f3_out;
// mux output for extended mode
reg g0_out;
reg g1_out;
// either datac or datag
reg f2_input3;
// F2 output using dataf
reg f2_f;
// second input to the adder
reg adder_input2;
// tmp output variables
reg combout_tmp;
reg sumout_tmp;
reg cout_tmp;
// integer representations for string parameters
reg ishared_arith;
reg iextended_lut;
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa;
input datab;
input datac;
input datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
// 5-input LUT function
function lut5;
input [31:0] mask;
input dataa;
input datab;
input datac;
input datad;
input datae;
reg e0_lut;
reg e1_lut;
reg [15:0] e0_mask;
reg [31:16] e1_mask;
begin
e0_mask = mask[15:0];
e1_mask = mask[31:16];
begin
e0_lut = lut4(e0_mask, dataa, datab, datac, datad);
e1_lut = lut4(e1_mask, dataa, datab, datac, datad);
if (datae === 1'bX) // X propogation
begin
if (e0_lut == e1_lut)
begin
lut5 = e0_lut;
end
else
begin
lut5 = 1'bX;
end
end
else
begin
lut5 = (datae == 1'b1) ? e1_lut : e0_lut;
end
end
end
endfunction
// 6-input LUT function
function lut6;
input [63:0] mask;
input dataa;
input datab;
input datac;
input datad;
input datae;
input dataf;
reg f0_lut;
reg f1_lut;
reg [31:0] f0_mask;
reg [63:32] f1_mask ;
begin
f0_mask = mask[31:0];
f1_mask = mask[63:32];
begin
lut6 = mask[{dataf, datae, datad, datac, datab, dataa}];
if (lut6 === 1'bX)
begin
f0_lut = lut5(f0_mask, dataa, datab, datac, datad, datae);
f1_lut = lut5(f1_mask, dataa, datab, datac, datad, datae);
if (dataf === 1'bX) // X propogation
begin
if (f0_lut == f1_lut)
begin
lut6 = f0_lut;
end
else
begin
lut6 = 1'bX;
end
end
else
begin
lut6 = (dataf == 1'b1) ? f1_lut : f0_lut;
end
end
end
end
endfunction
wire dataa_in;
wire datab_in;
wire datac_in;
wire datad_in;
wire datae_in;
wire dataf_in;
wire datag_in;
wire cin_in;
wire sharein_in;
buf(dataa_in, dataa);
buf(datab_in, datab);
buf(datac_in, datac);
buf(datad_in, datad);
buf(datae_in, datae);
buf(dataf_in, dataf);
buf(datag_in, datag);
buf(cin_in, cin);
buf(sharein_in, sharein);
specify
(dataa => combout) = (0, 0);
(datab => combout) = (0, 0);
(datac => combout) = (0, 0);
(datad => combout) = (0, 0);
(datae => combout) = (0, 0);
(dataf => combout) = (0, 0);
(datag => combout) = (0, 0);
(dataa => sumout) = (0, 0);
(datab => sumout) = (0, 0);
(datac => sumout) = (0, 0);
(datad => sumout) = (0, 0);
(dataf => sumout) = (0, 0);
(cin => sumout) = (0, 0);
(sharein => sumout) = (0, 0);
(dataa => cout) = (0, 0);
(datab => cout) = (0, 0);
(datac => cout) = (0, 0);
(datad => cout) = (0, 0);
(dataf => cout) = (0, 0);
(cin => cout) = (0, 0);
(sharein => cout) = (0, 0);
(dataa => shareout) = (0, 0);
(datab => shareout) = (0, 0);
(datac => shareout) = (0, 0);
(datad => shareout) = (0, 0);
endspecify
initial
begin
if (shared_arith == "on")
ishared_arith = 1;
else
ishared_arith = 0;
if (extended_lut == "on")
iextended_lut = 1;
else
iextended_lut = 0;
f0_out = 1'b0;
f1_out = 1'b0;
f2_out = 1'b0;
f3_out = 1'b0;
g0_out = 1'b0;
g1_out = 1'b0;
f2_input3 = 1'b0;
adder_input2 = 1'b0;
f2_f = 1'b0;
combout_tmp = 1'b0;
sumout_tmp = 1'b0;
cout_tmp = 1'b0;
end
// sub masks and outputs
assign f0_mask = lut_mask[15:0];
assign f1_mask = lut_mask[31:16];
assign f2_mask = lut_mask[47:32];
assign f3_mask = lut_mask[63:48];
always @(datag_in or dataf_in or datae_in or datad_in or datac_in or
datab_in or dataa_in or cin_in or sharein_in)
begin
// check for extended LUT mode
if (iextended_lut == 1)
f2_input3 = datag_in;
else
f2_input3 = datac_in;
f0_out = lut4(f0_mask, dataa_in, datab_in, datac_in, datad_in);
f1_out = lut4(f1_mask, dataa_in, datab_in, f2_input3, datad_in);
f2_out = lut4(f2_mask, dataa_in, datab_in, datac_in, datad_in);
f3_out = lut4(f3_mask, dataa_in, datab_in, f2_input3, datad_in);
// combout is the 6-input LUT
if (iextended_lut == 1)
begin
if (datae_in == 1'b0)
begin
g0_out = f0_out;
g1_out = f2_out;
end
else if (datae_in == 1'b1)
begin
g0_out = f1_out;
g1_out = f3_out;
end
else
begin
if (f0_out == f1_out)
g0_out = f0_out;
else
g0_out = 1'bX;
if (f2_out == f3_out)
g1_out = f2_out;
else
g1_out = 1'bX;
end
if (dataf_in == 1'b0)
combout_tmp = g0_out;
else if ((dataf_in == 1'b1) || (g0_out == g1_out))
combout_tmp = g1_out;
else
combout_tmp = 1'bX;
end
else
combout_tmp = lut6(lut_mask, dataa_in, datab_in, datac_in,
datad_in, datae_in, dataf_in);
// check for shareed arithmetic mode
if (ishared_arith == 1)
adder_input2 = sharein_in;
else
begin
f2_f = lut4(f2_mask, dataa_in, datab_in, datac_in, dataf_in);
adder_input2 = !f2_f;
end
// sumout & cout
sumout_tmp = cin_in ^ f0_out ^ adder_input2;
cout_tmp = (cin_in & f0_out) | (cin_in & adder_input2) |
(f0_out & adder_input2);
end
and (combout, combout_tmp, 1'b1);
and (sumout, sumout_tmp, 1'b1);
and (cout, cout_tmp, 1'b1);
and (shareout, f2_out, 1'b1);
endmodule
//------------------------------------------------------------------
//
// Module Name : arriaiigz_routing_wire
//
// Description : Simulation model for a simple routing wire
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module arriaiigz_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0) ;
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule // arriaiigz_routing_wire
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_lvds_tx_reg
//
// Description : Simulation model for a simple DFF.
// This is used for registering the enable inputs.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module arriaiigz_lvds_tx_reg (q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// BUFFER INPUTS
wire clk_in;
wire ena_in;
wire d_in;
buf (clk_in, clk);
buf (ena_in, ena);
buf (d_in, d);
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
$setuphold(posedge clk, d, 0, 0);
(posedge clk => (q +: q_tmp)) = (0, 0);
(negedge clrn => (q +: q_tmp)) = (0, 0);
(negedge prn => (q +: q_tmp)) = (0, 0);
endspecify
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q_tmp = 0;
always @ (posedge clk_in or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk_in == 1) & (ena_in == 1'b1))
q_tmp <= d_in;
end
assign q_wire = q_tmp;
and (q, q_wire, 1'b1);
endmodule // arriaiigz_lvds_tx_reg
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_lvds_tx_parallel_register
//
// Description : Register for the 10 data input channels of the ARRIAIIGZ
// LVDS Tx
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module arriaiigz_lvds_tx_parallel_register (clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 4;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [channel_width - 1:0] dataout_tmp;
wire clk_ipd;
wire enable_ipd;
wire [channel_width - 1:0] datain_ipd;
buf buf_clk (clk_ipd,clk);
buf buf_enable (enable_ipd,enable);
buf buf_datain [channel_width - 1:0] (datain_ipd,datain);
wire [channel_width - 1:0] dataout_opd;
buf buf_dataout [channel_width - 1:0] (dataout,dataout_opd);
// TIMING PATHS
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
$setuphold(posedge clk, datain, 0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk_ipd or enable_ipd or devpor or devclrn)
begin
if ((devpor === 1'b0) || (devclrn === 1'b0))
begin
dataout_tmp <= 'b0;
end
else begin
if ((clk_ipd === 1'b1) && (clk_last_value !== clk_ipd))
begin
if (enable_ipd === 1'b1)
begin
dataout_tmp <= datain_ipd;
end
end
end
clk_last_value <= clk_ipd;
end // always
assign dataout_opd = dataout_tmp;
endmodule //arriaiigz_lvds_tx_parallel_register
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_lvds_tx_out_block
//
// Description : Negative edge triggered register on the Tx output.
// Also, optionally generates an identical/inverted output clock
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module arriaiigz_lvds_tx_out_block (clk,
datain,
dataout,
devclrn,
devpor
);
parameter bypass_serializer = "false";
parameter invert_clock = "false";
parameter use_falling_clock_edge = "false";
// INPUT PORTS
input datain;
input clk;
input devclrn;
input devpor;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
reg clk_last_value;
wire bypass_mode;
wire invert_mode;
wire falling_clk_out;
// BUFFER INPUTS
wire clk_in;
wire datain_in;
buf (clk_in, clk);
buf (datain_in, datain);
// TEST PARAMETER VALUES
assign falling_clk_out = (use_falling_clock_edge == "true")?1'b1:1'b0;
assign bypass_mode = (bypass_serializer == "true")?1'b1:1'b0;
assign invert_mode = (invert_clock == "true")?1'b1:1'b0;
// TIMING PATHS
specify
if (bypass_mode == 1'b1)
(clk => dataout) = (0, 0);
if (bypass_mode == 1'b0 && falling_clk_out == 1'b1)
(negedge clk => (dataout +: dataout_tmp)) = (0, 0);
if (bypass_mode == 1'b0 && falling_clk_out == 1'b0)
(datain => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 0;
end
always @(clk_in or datain_in or devclrn or devpor)
begin
if ((devpor === 1'b0) || (devclrn === 1'b0))
begin
dataout_tmp <= 0;
end
else begin
if (bypass_serializer == "false")
begin
if (use_falling_clock_edge == "false")
dataout_tmp <= datain_in;
if ((clk_in === 1'b0) && (clk_last_value !== clk_in))
begin
if (use_falling_clock_edge == "true")
dataout_tmp <= datain_in;
end
end // bypass is off
else begin
// generate clk_out
if (invert_clock == "false")
dataout_tmp <= clk_in;
else
dataout_tmp <= !clk_in;
end // clk output
end
clk_last_value <= clk_in;
end // always
and (dataout, dataout_tmp, 1'b1);
endmodule //arriaiigz_lvds_tx_out_block
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_lvds_transmitter
//
// Description : Timing simulation model for the ARRIAIIGZ LVDS Tx WYSIWYG.
// It instantiates the following sub-modules :
// 1) primitive DFFE
// 2) ARRIAIIGZ_lvds_tx_parallel_register and
// 3) ARRIAIIGZ_lvds_tx_out_block
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module arriaiigz_lvds_transmitter (clk0,
enable0,
datain,
serialdatain,
postdpaserialdatain,
dataout,
serialfdbkout,
dpaclkin,
devclrn,
devpor
);
parameter bypass_serializer = "false";
parameter invert_clock = "false";
parameter use_falling_clock_edge = "false";
parameter use_serial_data_input = "false";
parameter use_post_dpa_serial_data_input = "false";
parameter is_used_as_outclk = "false";
parameter tx_output_path_delay_engineering_bits = -1;
parameter enable_dpaclk_to_lvdsout = "off";
parameter preemphasis_setting = 0;
parameter vod_setting = 0;
parameter differential_drive = 0;
parameter lpm_type = "arriaiigz_lvds_transmitter";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter channel_width = 10;
// SIMULATION_ONLY_PARAMETERS_END
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk0;
input enable0;
input serialdatain;
input postdpaserialdatain;
input devclrn;
input devpor;
input dpaclkin;
// OUTPUT PORTS
output dataout;
output serialfdbkout;
tri1 devclrn;
tri1 devpor;
// INTERNAL VARIABLES AND NETS
integer i;
wire dataout_tmp;
wire dataout_wire;
wire shift_out;
reg clk0_last_value;
wire [channel_width - 1:0] input_data;
reg [channel_width - 1:0] shift_data;
wire txload0;
reg [channel_width - 1:0] datain_dly;
wire bypass_mode;
wire [channel_width - 1:0] datain_in;
wire serial_din_mode;
wire postdpa_serial_din_mode;
wire enable_dpaclk_to_lvdsout_signal;
wire clk0_in;
wire serialdatain_in;
wire postdpaserialdatain_in;
buf (clk0_in, clk0);
buf datain_buf [channel_width - 1:0] (datain_in, datain);
buf (serialdatain_in, serialdatain);
buf (postdpaserialdatain_in, postdpaserialdatain);
// TEST PARAMETER VALUES
assign serial_din_mode = (use_serial_data_input == "true") ? 1'b1 : 1'b0;
assign postdpa_serial_din_mode = (use_post_dpa_serial_data_input == "true") ? 1'b1 : 1'b0;
assign enable_dpaclk_to_lvdsout_signal = (enable_dpaclk_to_lvdsout == "on") ? 1'b1 : 1'b0;
// TIMING PATHS
specify
if (serial_din_mode == 1'b1)
(serialdatain => dataout) = (0, 0);
if (postdpa_serial_din_mode == 1'b1)
(postdpaserialdatain => dataout) = (0, 0);
if (enable_dpaclk_to_lvdsout_signal == 1'b1)
(dpaclkin => dataout) = (0, 0);
endspecify
initial
begin
i = 0;
clk0_last_value = 0;
shift_data = 'b0;
end
arriaiigz_lvds_tx_reg txload0_reg (.d(enable0),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(clk0_in),
.q(txload0)
);
arriaiigz_lvds_tx_out_block output_module (.clk(clk0_in),
.datain(shift_out),
.dataout(dataout_tmp),
.devclrn(devclrn),
.devpor(devpor)
);
defparam output_module.bypass_serializer = bypass_serializer;
defparam output_module.invert_clock = invert_clock;
defparam output_module.use_falling_clock_edge = use_falling_clock_edge;
arriaiigz_lvds_tx_parallel_register input_reg (.clk(txload0),
.enable(1'b1),
.datain(datain_dly),
.dataout(input_data),
.devclrn(devclrn),
.devpor(devpor)
);
defparam input_reg.channel_width = channel_width;
always @(datain_in)
begin
datain_dly <= #1 datain_in;
end
assign shift_out = shift_data[channel_width - 1];
always @(clk0_in or devclrn or devpor)
begin
if ((devpor === 1'b0) || (devclrn === 1'b0))
begin
shift_data <= 'b0;
end
else begin
if (bypass_serializer == "false")
begin
if ((clk0_in === 1'b1) && (clk0_last_value !== clk0_in))
begin
if (txload0 === 1'b1)
begin
for (i = 0; i < channel_width; i = i + 1)
shift_data[i] <= input_data[i];
end
else begin
for (i = (channel_width - 1); i > 0; i = i - 1 )
shift_data[i] <= shift_data[i-1];
end
end
end // bypass is off
end // devpor
clk0_last_value <= clk0_in;
end // always
assign dataout_wire = (use_serial_data_input == "true") ? serialdatain_in :
(use_post_dpa_serial_data_input == "true") ? postdpaserialdatain_in :
(enable_dpaclk_to_lvdsout == "on") ? dpaclkin:
dataout_tmp;
and (dataout, dataout_wire, 1'b1);
and (serialfdbkout, dataout_wire, 1'b1);
endmodule // arriaiigz_lvds_transmitter
///////////////////////////////////////////////////////////////////////
//
// ARRIAIIGZ RUBLOCK ATOM
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module arriaiigz_rublock
(
clk,
shiftnld,
captnupdt,
regin,
rsttimer,
rconfig,
regout
);
parameter sim_init_config = "factory";
parameter sim_init_watchdog_value = 0;
parameter sim_init_status = 0;
parameter lpm_type = "arriaiigz_rublock";
input clk;
input shiftnld;
input captnupdt;
input regin;
input rsttimer;
input rconfig;
output regout;
endmodule
//--------------------------------------------------------------------------
// Module Name : arriaiigz_ram_pulse_generator
// Description : Generate pulse to initiate memory read/write operations
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter delay_pulse = 1'b0;
parameter start_delay = (delay_pulse == 1'b0) ? 1 : 2; // delay write
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0,t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode,t_access);
endspecify
buf #(start_delay) (clk_ipd,clk);
wire pulse_opd;
buf buf_pulse (pulse,pulse_opd);
initial clk_prev = 1'bx;
always @(clk_ipd or posedge pulse)
begin
if (pulse) state <= 1'b0;
else if (ena && clk_ipd === 1'b1 && clk_prev === 1'b0) state <= 1'b1;
clk_prev = clk_ipd;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
//--------------------------------------------------------------------------
// Module Name : arriaiigz_ram_register
// Description : Register module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_ram_register (
d,
clk,
aclr,
devclrn,
devpor,
stall,
ena,
q,
aclrout
);
parameter width = 1; // data width
parameter preset = 1'b0; // clear acts as preset
input [width - 1:0] d; // data
input clk; // clock
input aclr; // asynch clear
input devclrn,devpor; // device wide clear/reset
input stall; // address stall
input ena; // clock enable
output [width - 1:0] q; // register output
output aclrout; // delayed asynch clear
wire ena_ipd;
wire clk_ipd;
wire aclr_ipd;
wire [width - 1:0] d_ipd;
buf buf_ena (ena_ipd,ena);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_d [width - 1:0] (d_ipd,d);
wire stall_ipd;
buf buf_stall (stall_ipd,stall);
wire [width - 1:0] q_opd;
buf buf_q [width - 1:0] (q,q_opd);
reg [width - 1:0] q_reg;
reg viol_notifier;
wire reset;
assign reset = devpor && devclrn && (!aclr_ipd) && (ena_ipd);
specify
$setup (d, posedge clk &&& reset, 0, viol_notifier);
$setup (aclr, posedge clk, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$setup (stall, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, d , 0, viol_notifier);
$hold (posedge clk, aclr, 0, viol_notifier);
$hold (posedge clk &&& reset, ena , 0, viol_notifier );
$hold (posedge clk &&& reset, stall, 0, viol_notifier );
(posedge clk => (q +: q_reg)) = (0,0);
(posedge aclr => (q +: q_reg)) = (0,0);
endspecify
initial q_reg <= (preset) ? {width{1'b1}} : 'b0;
always @(posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (aclr_ipd || ~devclrn || ~devpor)
q_reg <= (preset) ? {width{1'b1}} : 'b0;
else if (ena_ipd & !stall_ipd)
q_reg <= d_ipd;
end
assign aclrout = aclr_ipd;
assign q_opd = q_reg;
endmodule
`timescale 1 ps/1 ps
`define PRIME 1
`define SEC 0
//--------------------------------------------------------------------------
// Module Name : arriaiigz_ram_block
// Description : Main RAM module
//--------------------------------------------------------------------------
module arriaiigz_ram_block
(
portadatain,
portaaddr,
portawe,
portare,
portbdatain,
portbaddr,
portbwe,
portbre,
clk0, clk1,
ena0, ena1,
ena2, ena3,
clr0, clr1,
portabyteenamasks,
portbbyteenamasks,
portaaddrstall,
portbaddrstall,
devclrn,
devpor,
eccstatus,
portadataout,
portbdataout
,dftout
);
// -------- GLOBAL PARAMETERS ---------
parameter operation_mode = "single_port";
parameter mixed_port_feed_through_mode = "dont_care";
parameter ram_block_type = "auto";
parameter logical_ram_name = "ram_name";
parameter init_file = "init_file.hex";
parameter init_file_layout = "none";
parameter enable_ecc = "false";
parameter width_eccstatus = 3;
parameter data_interleave_width_in_bits = 1;
parameter data_interleave_offset_in_bits = 1;
parameter port_a_logical_ram_depth = 0;
parameter port_a_logical_ram_width = 0;
parameter port_a_first_address = 0;
parameter port_a_last_address = 0;
parameter port_a_first_bit_number = 0;
parameter port_a_data_out_clear = "none";
parameter port_a_data_out_clock = "none";
parameter port_a_data_width = 1;
parameter port_a_address_width = 1;
parameter port_a_byte_enable_mask_width = 1;
parameter port_b_logical_ram_depth = 0;
parameter port_b_logical_ram_width = 0;
parameter port_b_first_address = 0;
parameter port_b_last_address = 0;
parameter port_b_first_bit_number = 0;
parameter port_b_address_clear = "none";
parameter port_b_data_out_clear = "none";
parameter port_b_data_in_clock = "clock1";
parameter port_b_address_clock = "clock1";
parameter port_b_write_enable_clock = "clock1";
parameter port_b_read_enable_clock = "clock1";
parameter port_b_byte_enable_clock = "clock1";
parameter port_b_data_out_clock = "none";
parameter port_b_data_width = 1;
parameter port_b_address_width = 1;
parameter port_b_byte_enable_mask_width = 1;
parameter port_a_read_during_write_mode = "new_data_no_nbe_read";
parameter port_b_read_during_write_mode = "new_data_no_nbe_read";
parameter power_up_uninitialized = "false";
parameter lpm_type = "arriaiigz_ram_block";
parameter lpm_hint = "true";
parameter connectivity_checking = "off";
parameter mem_init0 = 2048'b0;
parameter mem_init1 = 2048'b0;
parameter mem_init2 = 2048'b0;
parameter mem_init3 = 2048'b0;
parameter mem_init4 = 2048'b0;
parameter mem_init5 = 2048'b0;
parameter mem_init6 = 2048'b0;
parameter mem_init7 = 2048'b0;
parameter mem_init8 = 2048'b0;
parameter mem_init9 = 2048'b0;
parameter mem_init10 = 2048'b0;
parameter mem_init11 = 2048'b0;
parameter mem_init12 = 2048'b0;
parameter mem_init13 = 2048'b0;
parameter mem_init14 = 2048'b0;
parameter mem_init15 = 2048'b0;
parameter mem_init16 = 2048'b0;
parameter mem_init17 = 2048'b0;
parameter mem_init18 = 2048'b0;
parameter mem_init19 = 2048'b0;
parameter mem_init20 = 2048'b0;
parameter mem_init21 = 2048'b0;
parameter mem_init22 = 2048'b0;
parameter mem_init23 = 2048'b0;
parameter mem_init24 = 2048'b0;
parameter mem_init25 = 2048'b0;
parameter mem_init26 = 2048'b0;
parameter mem_init27 = 2048'b0;
parameter mem_init28 = 2048'b0;
parameter mem_init29 = 2048'b0;
parameter mem_init30 = 2048'b0;
parameter mem_init31 = 2048'b0;
parameter mem_init32 = 2048'b0;
parameter mem_init33 = 2048'b0;
parameter mem_init34 = 2048'b0;
parameter mem_init35 = 2048'b0;
parameter mem_init36 = 2048'b0;
parameter mem_init37 = 2048'b0;
parameter mem_init38 = 2048'b0;
parameter mem_init39 = 2048'b0;
parameter mem_init40 = 2048'b0;
parameter mem_init41 = 2048'b0;
parameter mem_init42 = 2048'b0;
parameter mem_init43 = 2048'b0;
parameter mem_init44 = 2048'b0;
parameter mem_init45 = 2048'b0;
parameter mem_init46 = 2048'b0;
parameter mem_init47 = 2048'b0;
parameter mem_init48 = 2048'b0;
parameter mem_init49 = 2048'b0;
parameter mem_init50 = 2048'b0;
parameter mem_init51 = 2048'b0;
parameter mem_init52 = 2048'b0;
parameter mem_init53 = 2048'b0;
parameter mem_init54 = 2048'b0;
parameter mem_init55 = 2048'b0;
parameter mem_init56 = 2048'b0;
parameter mem_init57 = 2048'b0;
parameter mem_init58 = 2048'b0;
parameter mem_init59 = 2048'b0;
parameter mem_init60 = 2048'b0;
parameter mem_init61 = 2048'b0;
parameter mem_init62 = 2048'b0;
parameter mem_init63 = 2048'b0;
parameter mem_init64 = 2048'b0;
parameter mem_init65 = 2048'b0;
parameter mem_init66 = 2048'b0;
parameter mem_init67 = 2048'b0;
parameter mem_init68 = 2048'b0;
parameter mem_init69 = 2048'b0;
parameter mem_init70 = 2048'b0;
parameter mem_init71 = 2048'b0;
parameter port_a_byte_size = 0;
parameter port_b_byte_size = 0;
parameter clk0_input_clock_enable = "none"; // ena0,ena2,none
parameter clk0_core_clock_enable = "none"; // ena0,ena2,none
parameter clk0_output_clock_enable = "none"; // ena0,none
parameter clk1_input_clock_enable = "none"; // ena1,ena3,none
parameter clk1_core_clock_enable = "none"; // ena1,ena3,none
parameter clk1_output_clock_enable = "none"; // ena1,none
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter port_a_address_clear = "none";
parameter port_a_data_in_clock = "clock0";
parameter port_a_address_clock = "clock0";
parameter port_a_write_enable_clock = "clock0";
parameter port_a_byte_enable_clock = "clock0";
parameter port_a_read_enable_clock = "clock0";
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter primary_port_is_a = (port_b_data_width <= port_a_data_width) ? 1'b1 : 1'b0;
parameter primary_port_is_b = ~primary_port_is_a;
parameter mode_is_rom_or_sp = ((operation_mode == "rom") || (operation_mode == "single_port")) ? 1'b1 : 1'b0;
parameter data_width = (primary_port_is_a) ? port_a_data_width : port_b_data_width;
parameter data_unit_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_data_width : port_b_data_width;
parameter address_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_address_width : port_b_address_width;
parameter address_unit_width = (mode_is_rom_or_sp | primary_port_is_a) ? port_a_address_width : port_b_address_width;
parameter wired_mode = ((port_a_address_width == 1) && (port_a_address_width == port_b_address_width)
&& (port_a_data_width != port_b_data_width));
parameter num_rows = 1 << address_unit_width;
parameter num_cols = (mode_is_rom_or_sp) ? 1 : ( wired_mode ? 2 :
( (primary_port_is_a) ?
1 << (port_b_address_width - port_a_address_width) :
1 << (port_a_address_width - port_b_address_width) ) ) ;
parameter mask_width_prime = (primary_port_is_a) ?
port_a_byte_enable_mask_width : port_b_byte_enable_mask_width;
parameter mask_width_sec = (primary_port_is_a) ?
port_b_byte_enable_mask_width : port_a_byte_enable_mask_width;
parameter byte_size_a = port_a_data_width/port_a_byte_enable_mask_width;
parameter byte_size_b = port_b_data_width/port_b_byte_enable_mask_width;
parameter mode_is_dp = (operation_mode == "dual_port") ? 1'b1 : 1'b0;
// Hardware write modes
parameter dual_clock = ((operation_mode == "dual_port") ||
(operation_mode == "bidir_dual_port")) &&
(port_b_address_clock == "clock1");
parameter both_new_data_same_port = (
((port_a_read_during_write_mode == "new_data_no_nbe_read") ||
(port_a_read_during_write_mode == "dont_care")) &&
((port_b_read_during_write_mode == "new_data_no_nbe_read") ||
(port_b_read_during_write_mode == "dont_care"))
) ? 1'b1 : 1'b0;
parameter hw_write_mode_a = (
((port_a_read_during_write_mode == "old_data") ||
(port_a_read_during_write_mode == "new_data_with_nbe_read"))
) ? "R+W" : (
dual_clock || (
mixed_port_feed_through_mode == "dont_care" &&
both_new_data_same_port
) ? "FW" : "DW"
);
parameter hw_write_mode_b = (
((port_b_read_during_write_mode == "old_data") ||
(port_b_read_during_write_mode == "new_data_with_nbe_read"))
) ? "R+W" : (
dual_clock || (
mixed_port_feed_through_mode == "dont_care" &&
both_new_data_same_port
) ? "FW" : "DW"
);
parameter delay_write_pulse_a = (mode_is_dp && mixed_port_feed_through_mode == "dont_care") ? 1'b0 : ((hw_write_mode_a != "FW") ? 1'b1 : 1'b0);
parameter delay_write_pulse_b = (hw_write_mode_b != "FW") ? 1'b1 : 1'b0;
parameter be_mask_write_a = (port_a_read_during_write_mode == "new_data_with_nbe_read") ? 1'b1 : 1'b0;
parameter be_mask_write_b = (port_b_read_during_write_mode == "new_data_with_nbe_read") ? 1'b1 : 1'b0;
parameter old_data_write_a = (port_a_read_during_write_mode == "old_data") ? 1'b1 : 1'b0;
parameter old_data_write_b = (port_b_read_during_write_mode == "old_data") ? 1'b1 : 1'b0;
parameter read_before_write_a = (hw_write_mode_a == "R+W") ? 1'b1 : 1'b0;
parameter read_before_write_b = (hw_write_mode_b == "R+W") ? 1'b1 : 1'b0;
parameter clock_duty_cycle_dependence = "ON";
// LOCAL_PARAMETERS_END
// -------- PORT DECLARATIONS ---------
input portawe;
input portare;
input [port_a_data_width - 1:0] portadatain;
input [port_a_address_width - 1:0] portaaddr;
input [port_a_byte_enable_mask_width - 1:0] portabyteenamasks;
input portbwe, portbre;
input [port_b_data_width - 1:0] portbdatain;
input [port_b_address_width - 1:0] portbaddr;
input [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks;
input clr0,clr1;
input clk0,clk1;
input ena0,ena1;
input ena2,ena3;
input devclrn,devpor;
input portaaddrstall;
input portbaddrstall;
output [port_a_data_width - 1:0] portadataout;
output [port_b_data_width - 1:0] portbdataout;
output [width_eccstatus - 1:0] eccstatus;
output [8:0] dftout;
tri0 portawe_int;
assign portawe_int = portawe;
tri1 portare_int;
assign portare_int = portare;
tri0 [port_a_data_width - 1:0] portadatain_int;
assign portadatain_int = portadatain;
tri0 [port_a_address_width - 1:0] portaaddr_int;
assign portaaddr_int = portaaddr;
tri1 [port_a_byte_enable_mask_width - 1:0] portabyteenamasks_int;
assign portabyteenamasks_int = portabyteenamasks;
tri0 portbwe_int;
assign portbwe_int = portbwe;
tri1 portbre_int;
assign portbre_int = portbre;
tri0 [port_b_data_width - 1:0] portbdatain_int;
assign portbdatain_int = portbdatain;
tri0 [port_b_address_width - 1:0] portbaddr_int;
assign portbaddr_int = portbaddr;
tri1 [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks_int;
assign portbbyteenamasks_int = portbbyteenamasks;
tri0 clr0_int,clr1_int;
assign clr0_int = clr0;
assign clr1_int = clr1;
tri0 clk0_int,clk1_int;
assign clk0_int = clk0;
assign clk1_int = clk1;
tri1 ena0_int,ena1_int;
assign ena0_int = ena0;
assign ena1_int = ena1;
tri1 ena2_int,ena3_int;
assign ena2_int = ena2;
assign ena3_int = ena3;
tri0 portaaddrstall_int;
assign portaaddrstall_int = portaaddrstall;
tri0 portbaddrstall_int;
assign portbaddrstall_int = portbaddrstall;
tri1 devclrn;
tri1 devpor;
// -------- INTERNAL signals ---------
// clock / clock enable
wire clk_a_in,clk_a_byteena,clk_a_out,clkena_a_out;
wire clk_a_rena, clk_a_wena;
wire clk_a_core;
wire clk_b_in,clk_b_byteena,clk_b_out,clkena_b_out;
wire clk_b_rena, clk_b_wena;
wire clk_b_core;
wire write_cycle_a,write_cycle_b;
// asynch clear
wire datain_a_clr,dataout_a_clr,datain_b_clr,dataout_b_clr;
wire dataout_a_clr_reg, dataout_b_clr_reg;
wire addr_a_clr,addr_b_clr;
wire byteena_a_clr,byteena_b_clr;
wire we_a_clr, re_a_clr, we_b_clr, re_b_clr;
wire datain_a_clr_in,datain_b_clr_in;
wire addr_a_clr_in,addr_b_clr_in;
wire byteena_a_clr_in,byteena_b_clr_in;
wire we_a_clr_in, re_a_clr_in, we_b_clr_in, re_b_clr_in;
reg mem_invalidate;
wire [`PRIME:`SEC] clear_asserted_during_write;
reg clear_asserted_during_write_a,clear_asserted_during_write_b;
// port A registers
wire we_a_reg;
wire re_a_reg;
wire [port_a_address_width - 1:0] addr_a_reg;
wire [port_a_data_width - 1:0] datain_a_reg, dataout_a_reg;
reg [port_a_data_width - 1:0] dataout_a;
wire [port_a_byte_enable_mask_width - 1:0] byteena_a_reg;
reg out_a_is_reg;
// port B registers
wire we_b_reg, re_b_reg;
wire [port_b_address_width - 1:0] addr_b_reg;
wire [port_b_data_width - 1:0] datain_b_reg, dataout_b_reg;
reg [port_b_data_width - 1:0] dataout_b;
wire [port_b_byte_enable_mask_width - 1:0] byteena_b_reg;
reg out_b_is_reg;
// placeholders for read/written data
reg [data_width - 1:0] read_data_latch;
reg [data_width - 1:0] mem_data;
reg [data_width - 1:0] old_mem_data;
reg [data_unit_width - 1:0] read_unit_data_latch;
reg [data_width - 1:0] mem_unit_data;
// pulses for A/B ports
wire write_pulse_a,write_pulse_b;
wire read_pulse_a,read_pulse_b;
wire read_pulse_a_feedthru,read_pulse_b_feedthru;
wire rw_pulse_a, rw_pulse_b;
wire [address_unit_width - 1:0] addr_prime_reg; // registered address
wire [address_width - 1:0] addr_sec_reg;
wire [data_width - 1:0] datain_prime_reg; // registered data
wire [data_unit_width - 1:0] datain_sec_reg;
// pulses for primary/secondary ports
wire write_pulse_prime,write_pulse_sec;
wire read_pulse_prime,read_pulse_sec;
wire read_pulse_prime_feedthru,read_pulse_sec_feedthru;
wire rw_pulse_prime, rw_pulse_sec;
reg read_pulse_prime_last_value, read_pulse_sec_last_value;
reg rw_pulse_prime_last_value, rw_pulse_sec_last_value;
reg [`PRIME:`SEC] dual_write; // simultaneous write to same location
// (row,column) coordinates
reg [address_unit_width - 1:0] row_sec;
reg [address_width + data_unit_width - address_unit_width - 1:0] col_sec;
// memory core
reg [data_width - 1:0] mem [num_rows - 1:0];
// byte enable
wire [data_width - 1:0] mask_vector_prime, mask_vector_prime_int;
wire [data_unit_width - 1:0] mask_vector_sec, mask_vector_sec_int;
reg [data_unit_width - 1:0] mask_vector_common_int;
reg [port_a_data_width - 1:0] mask_vector_a, mask_vector_a_int;
reg [port_b_data_width - 1:0] mask_vector_b, mask_vector_b_int;
// memory initialization
integer i,j,k,l;
integer addr_range_init;
reg [data_width - 1:0] init_mem_word;
reg [(port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1:0] mem_init;
// port active for read/write
wire active_a_in, active_b_in;
wire active_a_core,active_a_core_in,active_b_core,active_b_core_in;
wire active_write_a,active_write_b,active_write_clear_a,active_write_clear_b;
reg mode_is_rom,mode_is_sp,mode_is_bdp; // ram mode
reg ram_type; // ram type eg. MRAM
initial
begin
`ifdef QUARTUS_MEMORY_PLI
$memory_connect(mem);
`endif
ram_type = 0;
mode_is_rom = (operation_mode == "rom");
mode_is_sp = (operation_mode == "single_port");
mode_is_bdp = (operation_mode == "bidir_dual_port");
out_a_is_reg = (port_a_data_out_clock == "none") ? 1'b0 : 1'b1;
out_b_is_reg = (port_b_data_out_clock == "none") ? 1'b0 : 1'b1;
// powerup output latches to 0
dataout_a = 'b0;
if (mode_is_dp || mode_is_bdp) dataout_b = 'b0;
if ((power_up_uninitialized == "false") && ~ram_type)
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'b0;
if ((init_file_layout == "port_a") || (init_file_layout == "port_b"))
begin
mem_init = {
mem_init71 , mem_init70 , mem_init69 , mem_init68 , mem_init67 ,
mem_init66 , mem_init65 , mem_init64 , mem_init63 , mem_init62 ,
mem_init61 , mem_init60 , mem_init59 , mem_init58 , mem_init57 ,
mem_init56 , mem_init55 , mem_init54 , mem_init53 , mem_init52 ,
mem_init51 , mem_init50 , mem_init49 , mem_init48 , mem_init47 ,
mem_init46 , mem_init45 , mem_init44 , mem_init43 , mem_init42 ,
mem_init41 , mem_init40 , mem_init39 , mem_init38 , mem_init37 ,
mem_init36 , mem_init35 , mem_init34 , mem_init33 , mem_init32 ,
mem_init31 , mem_init30 , mem_init29 , mem_init28 , mem_init27 ,
mem_init26 , mem_init25 , mem_init24 , mem_init23 , mem_init22 ,
mem_init21 , mem_init20 , mem_init19 , mem_init18 , mem_init17 ,
mem_init16 , mem_init15 , mem_init14 , mem_init13 , mem_init12 ,
mem_init11 , mem_init10 , mem_init9 , mem_init8 , mem_init7 ,
mem_init6 , mem_init5 ,
mem_init4 , mem_init3 , mem_init2 ,
mem_init1 , mem_init0
};
addr_range_init = (primary_port_is_a) ?
port_a_last_address - port_a_first_address + 1 :
port_b_last_address - port_b_first_address + 1 ;
for (j = 0; j < addr_range_init; j = j + 1)
begin
for (k = 0; k < data_width; k = k + 1)
init_mem_word[k] = mem_init[j*data_width + k];
mem[j] = init_mem_word;
end
end
dual_write = 'b0;
end
assign clk_a_in = clk0_int;
assign clk_a_wena = (port_a_write_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_rena = (port_a_read_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_byteena = (port_a_byte_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_out = (port_a_data_out_clock == "none") ? 1'b0 : (
(port_a_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_in = (port_b_address_clock == "clock0") ? clk0_int : clk1_int;
assign clk_b_byteena = (port_b_byte_enable_clock == "none") ? 1'b0 : (
(port_b_byte_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_wena = (port_b_write_enable_clock == "none") ? 1'b0 : (
(port_b_write_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_rena = (port_b_read_enable_clock == "none") ? 1'b0 : (
(port_b_read_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_out = (port_b_data_out_clock == "none") ? 1'b0 : (
(port_b_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign addr_a_clr_in = (port_a_address_clear == "none") ? 1'b0 : clr0_int;
assign addr_b_clr_in = (port_b_address_clear == "none") ? 1'b0 : (
(port_b_address_clear == "clear0") ? clr0_int : clr1_int);
assign datain_a_clr_in = 1'b0;
assign dataout_a_clr = (port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign datain_b_clr_in = 1'b0;
assign dataout_b_clr = (port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign byteena_a_clr_in = 1'b0;
assign byteena_b_clr_in = 1'b0;
assign we_a_clr_in = 1'b0;
assign re_a_clr_in = 1'b0;
assign we_b_clr_in = 1'b0;
assign re_b_clr_in = 1'b0;
assign active_a_in = (clk0_input_clock_enable == "none") ? 1'b1 : (
(clk0_input_clock_enable == "ena0") ? ena0_int : ena2_int
);
assign active_a_core_in = (clk0_core_clock_enable == "none") ? 1'b1 : (
(clk0_core_clock_enable == "ena0") ? ena0_int : ena2_int
);
assign active_b_in = (port_b_address_clock == "clock0") ? (
(clk0_input_clock_enable == "none") ? 1'b1 : ((clk0_input_clock_enable == "ena0") ? ena0_int : ena2_int)
) : (
(clk1_input_clock_enable == "none") ? 1'b1 : ((clk1_input_clock_enable == "ena1") ? ena1_int : ena3_int)
);
assign active_b_core_in = (port_b_address_clock == "clock0") ? (
(clk0_core_clock_enable == "none") ? 1'b1 : ((clk0_core_clock_enable == "ena0") ? ena0_int : ena2_int)
) : (
(clk1_core_clock_enable == "none") ? 1'b1 : ((clk1_core_clock_enable == "ena1") ? ena1_int : ena3_int)
);
assign active_write_a = (byteena_a_reg !== 'b0);
assign active_write_b = (byteena_b_reg !== 'b0);
// Store core clock enable value for delayed write
// port A core active
arriaiigz_ram_register active_core_port_a (
.d(active_a_core_in),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_a_core),.aclrout()
);
defparam active_core_port_a.width = 1;
// port B core active
arriaiigz_ram_register active_core_port_b (
.d(active_b_core_in),
.clk(clk_b_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_b_core),.aclrout()
);
defparam active_core_port_b.width = 1;
// ------- A input registers -------
// write enable
arriaiigz_ram_register we_a_register (
.d(mode_is_rom ? 1'b0 : portawe_int),
.clk(clk_a_wena),
.aclr(we_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_core_in),
.q(we_a_reg),
.aclrout(we_a_clr)
);
defparam we_a_register.width = 1;
// read enable
arriaiigz_ram_register re_a_register (
.d(portare_int),
.clk(clk_a_rena),
.aclr(re_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_core_in),
.q(re_a_reg),
.aclrout(re_a_clr)
);
// address
arriaiigz_ram_register addr_a_register (
.d(portaaddr_int),
.clk(clk_a_in),
.aclr(addr_a_clr_in),
.devclrn(devclrn),.devpor(devpor),
.stall(portaaddrstall_int),
.ena(active_a_in),
.q(addr_a_reg),
.aclrout(addr_a_clr)
);
defparam addr_a_register.width = port_a_address_width;
// data
arriaiigz_ram_register datain_a_register (
.d(portadatain_int),
.clk(clk_a_in),
.aclr(datain_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(datain_a_reg),
.aclrout(datain_a_clr)
);
defparam datain_a_register.width = port_a_data_width;
// byte enable
arriaiigz_ram_register byteena_a_register (
.d(portabyteenamasks_int),
.clk(clk_a_byteena),
.aclr(byteena_a_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(byteena_a_reg),
.aclrout(byteena_a_clr)
);
defparam byteena_a_register.width = port_a_byte_enable_mask_width;
defparam byteena_a_register.preset = 1'b1;
// ------- B input registers -------
// write enable
arriaiigz_ram_register we_b_register (
.d(portbwe_int),
.clk(clk_b_wena),
.aclr(we_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_core_in),
.q(we_b_reg),
.aclrout(we_b_clr)
);
defparam we_b_register.width = 1;
defparam we_b_register.preset = 1'b0;
// read enable
arriaiigz_ram_register re_b_register (
.d(portbre_int),
.clk(clk_b_rena),
.aclr(re_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_core_in),
.q(re_b_reg),
.aclrout(re_b_clr)
);
defparam re_b_register.width = 1;
defparam re_b_register.preset = 1'b0;
// address
arriaiigz_ram_register addr_b_register (
.d(portbaddr_int),
.clk(clk_b_in),
.aclr(addr_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(portbaddrstall_int),
.ena(active_b_in),
.q(addr_b_reg),
.aclrout(addr_b_clr)
);
defparam addr_b_register.width = port_b_address_width;
// data
arriaiigz_ram_register datain_b_register (
.d(portbdatain_int),
.clk(clk_b_in),
.aclr(datain_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_b_in),
.q(datain_b_reg),
.aclrout(datain_b_clr)
);
defparam datain_b_register.width = port_b_data_width;
// byte enable
arriaiigz_ram_register byteena_b_register (
.d(portbbyteenamasks_int),
.clk(clk_b_byteena),
.aclr(byteena_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(byteena_b_reg),
.aclrout(byteena_b_clr)
);
defparam byteena_b_register.width = port_b_byte_enable_mask_width;
defparam byteena_b_register.preset = 1'b1;
assign datain_prime_reg = (primary_port_is_a) ? datain_a_reg : datain_b_reg;
assign addr_prime_reg = (primary_port_is_a) ? addr_a_reg : addr_b_reg;
assign datain_sec_reg = (primary_port_is_a) ? datain_b_reg : datain_a_reg;
assign addr_sec_reg = (primary_port_is_a) ? addr_b_reg : addr_a_reg;
assign mask_vector_prime = (primary_port_is_a) ? mask_vector_a : mask_vector_b;
assign mask_vector_prime_int = (primary_port_is_a) ? mask_vector_a_int : mask_vector_b_int;
assign mask_vector_sec = (primary_port_is_a) ? mask_vector_b : mask_vector_a;
assign mask_vector_sec_int = (primary_port_is_a) ? mask_vector_b_int : mask_vector_a_int;
// Hardware Write Modes
// ARRIAIIGZ
// Write pulse generation
arriaiigz_ram_pulse_generator wpgen_a (
.clk(clk_a_in),
.ena(active_a_core & active_write_a & we_a_reg),
.pulse(write_pulse_a),
.cycle(write_cycle_a)
);
defparam wpgen_a.delay_pulse = delay_write_pulse_a;
arriaiigz_ram_pulse_generator wpgen_b (
.clk(clk_b_in),
.ena(active_b_core & active_write_b & mode_is_bdp & we_b_reg),
.pulse(write_pulse_b),
.cycle(write_cycle_b)
);
defparam wpgen_b.delay_pulse = delay_write_pulse_b;
// Read pulse generation
arriaiigz_ram_pulse_generator rpgen_a (
.clk(clk_a_in),
.ena(active_a_core & re_a_reg & ~we_a_reg),
.pulse(read_pulse_a),
.cycle(clk_a_core)
);
arriaiigz_ram_pulse_generator rpgen_b (
.clk(clk_b_in),
.ena((mode_is_dp | mode_is_bdp) & active_b_core & re_b_reg & ~we_b_reg),
.pulse(read_pulse_b),
.cycle(clk_b_core)
);
// Read during write pulse generation
arriaiigz_ram_pulse_generator rwpgen_a (
.clk(clk_a_in),
.ena(active_a_core & re_a_reg & we_a_reg & read_before_write_a),
.pulse(rw_pulse_a),.cycle()
);
arriaiigz_ram_pulse_generator rwpgen_b (
.clk(clk_b_in),
.ena(active_b_core & mode_is_bdp & re_b_reg & we_b_reg & read_before_write_b),
.pulse(rw_pulse_b),.cycle()
);
assign write_pulse_prime = (primary_port_is_a) ? write_pulse_a : write_pulse_b;
assign read_pulse_prime = (primary_port_is_a) ? read_pulse_a : read_pulse_b;
assign read_pulse_prime_feedthru = (primary_port_is_a) ? read_pulse_a_feedthru : read_pulse_b_feedthru;
assign rw_pulse_prime = (primary_port_is_a) ? rw_pulse_a : rw_pulse_b;
assign write_pulse_sec = (primary_port_is_a) ? write_pulse_b : write_pulse_a;
assign read_pulse_sec = (primary_port_is_a) ? read_pulse_b : read_pulse_a;
assign read_pulse_sec_feedthru = (primary_port_is_a) ? read_pulse_b_feedthru : read_pulse_a_feedthru;
assign rw_pulse_sec = (primary_port_is_a) ? rw_pulse_b : rw_pulse_a;
// Create internal masks for byte enable processing
always @(byteena_a_reg)
begin
for (i = 0; i < port_a_data_width; i = i + 1)
begin
mask_vector_a[i] = (byteena_a_reg[i/byte_size_a] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_a_int[i] = (byteena_a_reg[i/byte_size_a] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(byteena_b_reg)
begin
for (l = 0; l < port_b_data_width; l = l + 1)
begin
mask_vector_b[l] = (byteena_b_reg[l/byte_size_b] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_b_int[l] = (byteena_b_reg[l/byte_size_b] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(posedge write_pulse_prime or posedge write_pulse_sec or
posedge read_pulse_prime or posedge read_pulse_sec
or posedge rw_pulse_prime or posedge rw_pulse_sec
)
begin
// Read before Write stage 1 : read data from memory
if (rw_pulse_prime && (rw_pulse_prime !== rw_pulse_prime_last_value))
begin
read_data_latch = mem[addr_prime_reg];
rw_pulse_prime_last_value = rw_pulse_prime;
end
if (rw_pulse_sec && (rw_pulse_sec !== rw_pulse_sec_last_value))
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
rw_pulse_sec_last_value = rw_pulse_sec;
end
// Write stage 1 : write X to memory
if (write_pulse_prime)
begin
old_mem_data = mem[addr_prime_reg];
mem_data = mem[addr_prime_reg] ^ mask_vector_prime_int;
mem[addr_prime_reg] = mem_data;
if ((row_sec == addr_prime_reg) && (read_pulse_sec))
begin
mem_unit_data = (mixed_port_feed_through_mode == "dont_care") ? {data_width{1'bx}} : old_mem_data;
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
end
end
if (write_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = mem_unit_data[j] ^ mask_vector_sec_int[j - col_sec];
mem[row_sec] = mem_unit_data;
end
if ((addr_prime_reg == row_sec) && write_pulse_prime && write_pulse_sec) dual_write = 2'b11;
// Read stage 1 : read data from memory
if (read_pulse_prime && read_pulse_prime !== read_pulse_prime_last_value)
begin
read_data_latch = mem[addr_prime_reg];
read_pulse_prime_last_value = read_pulse_prime;
end
if (read_pulse_sec && read_pulse_sec !== read_pulse_sec_last_value)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
if ((row_sec == addr_prime_reg) && (write_pulse_prime))
mem_unit_data = (mixed_port_feed_through_mode == "dont_care") ? {data_width{1'bx}} : old_mem_data;
else
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
read_pulse_sec_last_value = read_pulse_sec;
end
end
// Simultaneous write to same/overlapping location by both ports
always @(dual_write)
begin
if (dual_write == 2'b11)
begin
for (i = 0; i < data_unit_width; i = i + 1)
mask_vector_common_int[i] = mask_vector_prime_int[col_sec + i] &
mask_vector_sec_int[i];
end
else if (dual_write == 2'b01) mem_unit_data = mem[row_sec];
else if (dual_write == 'b0)
begin
mem_data = mem[addr_prime_reg];
for (i = 0; i < data_unit_width; i = i + 1)
mem_data[col_sec + i] = mem_data[col_sec + i] ^ mask_vector_common_int[i];
mem[addr_prime_reg] = mem_data;
end
end
// Write stage 2 : Write actual data to memory
always @(negedge write_pulse_prime)
begin
if (clear_asserted_during_write[`PRIME] !== 1'b1)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0)
mem_data[i] = datain_prime_reg[i];
mem[addr_prime_reg] = mem_data;
end
dual_write[`PRIME] = 1'b0;
end
always @(negedge write_pulse_sec)
begin
if (clear_asserted_during_write[`SEC] !== 1'b1)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0)
mem_unit_data[col_sec + i] = datain_sec_reg[i];
mem[row_sec] = mem_unit_data;
end
dual_write[`SEC] = 1'b0;
end
always @(negedge read_pulse_prime) read_pulse_prime_last_value = 1'b0;
always @(negedge read_pulse_sec) read_pulse_sec_last_value = 1'b0;
always @(negedge rw_pulse_prime) rw_pulse_prime_last_value = 1'b0;
always @(negedge rw_pulse_sec) rw_pulse_sec_last_value = 1'b0;
// Read stage 2 : Send data to output
always @(negedge read_pulse_prime)
begin
if (primary_port_is_a)
dataout_a = read_data_latch;
else
dataout_b = read_data_latch;
end
always @(negedge read_pulse_sec)
begin
if (primary_port_is_b)
dataout_a = read_unit_data_latch;
else
dataout_b = read_unit_data_latch;
end
// Read during Write stage 2 : Send data to output
always @(negedge rw_pulse_prime)
begin
if (primary_port_is_a)
begin
// BE mask write
if (be_mask_write_a)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] === 1'bx) // disabled byte
dataout_a[i] = read_data_latch[i];
end
else
dataout_a = read_data_latch;
end
else
begin
// BE mask write
if (be_mask_write_b)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] === 1'bx) // disabled byte
dataout_b[i] = read_data_latch[i];
end
else
dataout_b = read_data_latch;
end
end
always @(negedge rw_pulse_sec)
begin
if (primary_port_is_b)
begin
// BE mask write
if (be_mask_write_a)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] === 1'bx) // disabled byte
dataout_a[i] = read_unit_data_latch[i];
end
else
dataout_a = read_unit_data_latch;
end
else
begin
// BE mask write
if (be_mask_write_b)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] === 1'bx) // disabled byte
dataout_b[i] = read_unit_data_latch[i];
end
else
dataout_b = read_unit_data_latch;
end
end
// Same port feed through
arriaiigz_ram_pulse_generator ftpgen_a (
.clk(clk_a_in),
.ena(active_a_core & ~mode_is_dp & ~old_data_write_a & we_a_reg & re_a_reg),
.pulse(read_pulse_a_feedthru),.cycle()
);
arriaiigz_ram_pulse_generator ftpgen_b (
.clk(clk_b_in),
.ena(active_b_core & mode_is_bdp & ~old_data_write_b & we_b_reg & re_b_reg),
.pulse(read_pulse_b_feedthru),.cycle()
);
always @(negedge read_pulse_prime_feedthru)
begin
if (primary_port_is_a)
begin
if (be_mask_write_a)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0) // enabled byte
dataout_a[i] = datain_prime_reg[i];
end
else
dataout_a = datain_prime_reg ^ mask_vector_prime;
end
else
begin
if (be_mask_write_b)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0) // enabled byte
dataout_b[i] = datain_prime_reg[i];
end
else
dataout_b = datain_prime_reg ^ mask_vector_prime;
end
end
always @(negedge read_pulse_sec_feedthru)
begin
if (primary_port_is_b)
begin
if (be_mask_write_a)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0) // enabled byte
dataout_a[i] = datain_sec_reg[i];
end
else
dataout_a = datain_sec_reg ^ mask_vector_sec;
end
else
begin
if (be_mask_write_b)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0) // enabled byte
dataout_b[i] = datain_sec_reg[i];
end
else
dataout_b = datain_sec_reg ^ mask_vector_sec;
end
end
// Input register clears
always @(posedge addr_a_clr or posedge datain_a_clr or posedge we_a_clr)
clear_asserted_during_write_a = write_pulse_a;
assign active_write_clear_a = active_write_a & write_cycle_a;
always @(posedge addr_a_clr)
begin
if (active_write_clear_a & we_a_reg)
mem_invalidate = 1'b1;
else if (active_a_core & re_a_reg)
begin
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_a = 'bx;
end
end
always @(posedge datain_a_clr or posedge we_a_clr)
begin
if (active_write_clear_a & we_a_reg)
begin
if (primary_port_is_a)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 1'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign active_write_clear_b = active_write_b & write_cycle_b;
always @(posedge addr_b_clr or posedge datain_b_clr or
posedge we_b_clr)
clear_asserted_during_write_b = write_pulse_b;
always @(posedge addr_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & we_b_reg)
mem_invalidate = 1'b1;
else if ((mode_is_dp | mode_is_bdp) & active_b_core & re_b_reg)
begin
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_b = 'bx;
end
end
always @(posedge datain_b_clr or posedge we_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & we_b_reg)
begin
if (primary_port_is_b)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign clear_asserted_during_write[primary_port_is_a] = clear_asserted_during_write_a;
assign clear_asserted_during_write[primary_port_is_b] = clear_asserted_during_write_b;
always @(posedge mem_invalidate)
begin
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'bx;
mem_invalidate = 1'b0;
end
// ------- Aclr mux registers (Latch Clear) --------
// port A
arriaiigz_ram_register aclr__a__mux_register (
.d(dataout_a_clr),
.clk(clk_a_core),
.aclr(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(1'b1),
.q(dataout_a_clr_reg),.aclrout()
);
// port B
arriaiigz_ram_register aclr__b__mux_register (
.d(dataout_b_clr),
.clk(clk_b_core),
.aclr(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(1'b1),
.q(dataout_b_clr_reg),.aclrout()
);
// ------- Output registers --------
assign clkena_a_out = (port_a_data_out_clock == "clock0") ?
((clk0_output_clock_enable == "none") ? 1'b1 : ena0_int) :
((clk1_output_clock_enable == "none") ? 1'b1 : ena1_int) ;
arriaiigz_ram_register dataout_a_register (
.d(dataout_a),
.clk(clk_a_out),
.aclr(dataout_a_clr),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(clkena_a_out),
.q(dataout_a_reg),.aclrout()
);
defparam dataout_a_register.width = port_a_data_width;
reg [port_a_data_width - 1:0] portadataout_clr;
reg [port_b_data_width - 1:0] portbdataout_clr;
initial
begin
portadataout_clr = 'b0;
portbdataout_clr = 'b0;
end
assign portadataout = (out_a_is_reg) ? dataout_a_reg : (
(dataout_a_clr || dataout_a_clr_reg) ? portadataout_clr : dataout_a
);
assign clkena_b_out = (port_b_data_out_clock == "clock0") ?
((clk0_output_clock_enable == "none") ? 1'b1 : ena0_int) :
((clk1_output_clock_enable == "none") ? 1'b1 : ena1_int) ;
arriaiigz_ram_register dataout_b_register (
.d( dataout_b ),
.clk(clk_b_out),
.aclr(dataout_b_clr),
.devclrn(devclrn),.devpor(devpor),
.stall(1'b0),
.ena(clkena_b_out),
.q(dataout_b_reg),.aclrout()
);
defparam dataout_b_register.width = port_b_data_width;
assign portbdataout = (out_b_is_reg) ? dataout_b_reg : (
(dataout_b_clr || dataout_b_clr_reg) ? portbdataout_clr : dataout_b
);
assign eccstatus = {width_eccstatus{1'b0}};
endmodule // arriaiigz_ram_block
//------------------------------------------------------------------
//
// Module Name : arriaiigz_ff
//
// Description : ARRIAIIGZ FF Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_ff (
d,
clk,
clrn,
aload,
sclr,
sload,
asdata,
ena,
devclrn,
devpor,
q
);
parameter power_up = "low";
parameter x_on_violation = "on";
parameter lpm_type = "arriaiigz_ff";
input d;
input clk;
input clrn;
input aload;
input sclr;
input sload;
input asdata;
input ena;
input devclrn;
input devpor;
output q;
tri1 devclrn;
tri1 devpor;
reg q_tmp;
wire reset;
reg d_viol;
reg sclr_viol;
reg sload_viol;
reg asdata_viol;
reg ena_viol;
reg violation;
reg clk_last_value;
reg ix_on_violation;
wire d_in;
wire clk_in;
wire clrn_in;
wire aload_in;
wire sclr_in;
wire sload_in;
wire asdata_in;
wire ena_in;
wire nosloadsclr;
wire sloaddata;
buf (d_in, d);
buf (clk_in, clk);
buf (clrn_in, clrn);
buf (aload_in, aload);
buf (sclr_in, sclr);
buf (sload_in, sload);
buf (asdata_in, asdata);
buf (ena_in, ena);
assign reset = devpor && devclrn && clrn_in && ena_in;
assign nosloadsclr = reset && (!sload_in && !sclr_in);
assign sloaddata = reset && sload_in;
specify
$setuphold (posedge clk &&& nosloadsclr, d, 0, 0, d_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& sloaddata, asdata, 0, 0, asdata_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
(posedge clrn => (q +: 1'b0)) = (0, 0) ;
(posedge aload => (q +: q_tmp)) = (0, 0) ;
(asdata => q) = (0, 0) ;
endspecify
initial
begin
violation = 'b0;
clk_last_value = 'b0;
if (power_up == "low")
q_tmp = 'b0;
else if (power_up == "high")
q_tmp = 'b1;
if (x_on_violation == "on")
ix_on_violation = 1;
else
ix_on_violation = 0;
end
always @ (d_viol or sclr_viol or sload_viol or ena_viol or asdata_viol)
begin
if (ix_on_violation == 1)
violation = 'b1;
end
always @ (asdata_in or clrn_in or posedge aload_in or
devclrn or devpor)
begin
if (devpor == 'b0)
q_tmp <= 'b0;
else if (devclrn == 'b0)
q_tmp <= 'b0;
else if (clrn_in == 'b0)
q_tmp <= 'b0;
else if (aload_in == 'b1)
q_tmp <= asdata_in;
end
always @ (clk_in or posedge clrn_in or posedge aload_in or
devclrn or devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 'b0;
q_tmp <= 'bX;
end
else
begin
if (devpor == 'b0 || devclrn == 'b0 || clrn_in === 'b0)
q_tmp <= 'b0;
else if (aload_in === 'b1)
q_tmp <= asdata_in;
else if (ena_in === 'b1 && clk_in === 'b1 && clk_last_value === 'b0)
begin
if (sclr_in === 'b1)
q_tmp <= 'b0 ;
else if (sload_in === 'b1)
q_tmp <= asdata_in;
else
q_tmp <= d_in;
end
end
clk_last_value = clk_in;
end
and (q, q_tmp, 1'b1);
endmodule
//------------------------------------------------------------------
//
// Module Name : arriaiigz_clkselect
//
// Description : ARRIAIIGZ CLKSELECT Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_clkselect
(
inclk,
clkselect,
outclk
);
input [3:0] inclk;
input [1:0] clkselect;
output outclk;
parameter lpm_type = "arriaiigz_clkselect";
wire clkmux_out; // output of CLK mux
specify
(inclk[3] => outclk) = (0, 0);
(inclk[2] => outclk) = (0, 0);
(inclk[1] => outclk) = (0, 0);
(inclk[0] => outclk) = (0, 0);
(clkselect[1] => outclk) = (0, 0);
(clkselect[0] => outclk) = (0, 0);
endspecify
arriaiigz_mux41 clk_mux (
.MO(clkmux_out),
.IN0(inclk[0]),
.IN1(inclk[1]),
.IN2(inclk[2]),
.IN3(inclk[3]),
.S({clkselect[1], clkselect[0]}));
and (outclk, clkmux_out, 1'b1);
endmodule
//------------------------------------------------------------------
//
// Module Name : arriaiigz_and2
//
// Description : Simulation model for a simple 2-inputs AND gate.
// This is used for the storing delays for ARRIAIIGZ CLKENA.
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module arriaiigz_and2 (
IN1,
IN2,
Y
);
input IN1;
input IN2;
output Y;
specify
(IN1 => Y) = (0, 0);
(IN2 => Y) = (0, 0);
endspecify
and (Y, IN1, IN2);
endmodule
//------------------------------------------------------------------
//
// Module Name : arriaiigz_ena_reg
//
// Description : Simulation model for a simple DFF.
// This is used for the gated clock generation.
// Powers upto 1.
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module arriaiigz_ena_reg (
clk,
ena,
d,
clrn,
prn,
q
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
reg violation;
reg d_viol;
reg clk_last_value;
wire reset;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
assign reset = (!clrn) && (ena);
specify
$setuphold (posedge clk &&& reset, d, 0, 0, d_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
endspecify
initial
begin
q_tmp = 'b1;
violation = 'b0;
clk_last_value = clk;
end
always @ (clk or negedge clrn or negedge prn )
begin
if (d_viol == 1'b1)
begin
violation = 1'b0;
q_tmp <= 'bX;
end
else
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk_last_value === 'b0) & (clk === 1'b1) & (ena == 1'b1))
q_tmp <= d;
clk_last_value = clk;
end
and (q, q_tmp, 1'b1);
endmodule // arriaiigz_ena_reg
//------------------------------------------------------------------
//
// Module Name : arriaiigz_clkena
//
// Description : ARRIAIIGZ CLKENA Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_clkena (
inclk,
ena,
devpor,
devclrn,
enaout,
outclk
);
// INPUT PORTS
input inclk;
input ena;
input devpor;
input devclrn;
// OUTPUT PORTS
output enaout;
output outclk;
parameter clock_type = "Auto";
parameter ena_register_mode = "falling edge";
parameter lpm_type = "arriaiigz_clkena";
tri1 devclrn;
tri1 devpor;
wire cereg1_out; // output of ENA register1
wire cereg2_out; // output of ENA register2
wire ena_out; // choice of registered ENA or none.
arriaiigz_ena_reg extena_reg1(
.clk(!inclk),
.ena(1'b1),
.d(ena),
.clrn(1'b1),
.prn(devpor),
.q(cereg1_out)
);
arriaiigz_ena_reg extena_reg2(
.clk(!inclk),
.ena(1'b1),
.d(cereg1_out),
.clrn(1'b1),
.prn(devpor),
.q(cereg2_out)
);
assign ena_out = (ena_register_mode == "falling edge") ? cereg1_out :
((ena_register_mode == "none") ? ena : cereg2_out);
arriaiigz_and2 outclk_and(
.IN1(inclk),
.IN2(ena_out),
.Y(outclk)
);
arriaiigz_and2 enaout_and(
.IN1(1'b1),
.IN2(ena_out),
.Y(enaout)
);
endmodule
//--------------------------------------------------------------------------
// Module Name : arriaiigz_mlab_cell_pulse_generator
// Description : Generate pulse to initiate memory read/write operations
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_mlab_cell_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
reg state;
wire clk_ipd;
specify
specparam t_decode = 0,t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode,t_access);
endspecify
buf #(1) (clk_ipd,clk);
wire pulse_opd;
buf buf_pulse (pulse,pulse_opd);
always @(posedge clk_ipd or posedge pulse)
begin
if (pulse) state <= 1'b0;
else if (ena) state <= 1'b1;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
`timescale 1 ps/1 ps
//--------------------------------------------------------------------------
// Module Name : arriaiigz_mlab_cell
// Description : Main RAM module
//--------------------------------------------------------------------------
module arriaiigz_mlab_cell
(
portadatain,
portaaddr,
portabyteenamasks,
portbaddr,
clk0,
ena0,
portbdataout
);
// -------- GLOBAL PARAMETERS ---------
parameter logical_ram_name = "lutram";
parameter logical_ram_depth = 0;
parameter logical_ram_width = 0;
parameter first_address = 0;
parameter last_address = 0;
parameter first_bit_number = 0;
parameter init_file = "init_file.hex";
parameter data_width = 1;
parameter address_width = 1;
parameter byte_enable_mask_width = 1;
parameter lpm_type = "arriaiigz_mlab_cell";
parameter lpm_hint = "true";
parameter mem_init0 = 640'b0; // 64x10 OR 32x20
parameter mixed_port_feed_through_mode = "dont_care";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter byte_size = 1;
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter num_rows = 1 << address_width;
parameter num_cols = 1;
parameter port_byte_size = data_width/byte_enable_mask_width;
// LOCAL_PARAMETERS_END
// -------- PORT DECLARATIONS ---------
input [data_width - 1:0] portadatain;
input [address_width - 1:0] portaaddr;
input [byte_enable_mask_width - 1:0] portabyteenamasks;
input [address_width - 1:0] portbaddr;
input clk0;
input ena0;
output [data_width - 1:0] portbdataout;
reg ena0_reg;
reg viol_notifier;
wire reset;
assign reset = ena0_reg;
specify
$setup (portaaddr, negedge clk0 &&& reset, 0, viol_notifier);
$setup (portabyteenamasks, negedge clk0 &&& reset, 0, viol_notifier);
$setup (ena0, posedge clk0, 0, viol_notifier);
$hold (negedge clk0 &&& reset, portaaddr, 0, viol_notifier);
$hold (negedge clk0 &&& reset, portabyteenamasks, 0, viol_notifier);
$hold (posedge clk0, ena0, 0, viol_notifier);
(portbaddr *> portbdataout) = (0,0);
endspecify
// -------- INTERNAL signals ---------
// clock / clock enable
wire clk_a_in;
// Input/Output registers (come from outside MLAB)
// placeholders for read/written data
reg [data_width - 1:0] read_data_latch;
reg [data_width - 1:0] mem_data;
// pulses for A/B ports (no read pulse)
wire write_pulse;
wire write_cycle;
// memory core
reg [data_width - 1:0] mem [num_rows - 1:0];
// byte enable
reg [data_width - 1:0] mask_vector, mask_vector_int;
// memory initialization
integer i,j,k;
integer addr_range_init;
reg [data_width - 1:0] init_mem_word;
reg [(last_address - first_address + 1)*data_width - 1:0] mem_init;
// port active for read/write
wire active_a,active_a_in;
wire active_write_a;
// data output
reg [data_width - 1:0] dataout_b;
initial
begin
ena0_reg = 1'b0;
// powerup output to 0
dataout_b = 'b0;
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'b0;
mem_init = mem_init0;
addr_range_init = last_address - first_address + 1;
for (j = 0; j < addr_range_init; j = j + 1)
begin
for (k = 0; k < data_width; k = k + 1)
init_mem_word[k] = mem_init[j*data_width + k];
mem[j] = init_mem_word;
end
end
assign clk_a_in = clk0;
always @(posedge clk_a_in) ena0_reg <= ena0;
// Write pulse generation
arriaiigz_mlab_cell_pulse_generator wpgen_a (
.clk(~clk_a_in),
.ena(ena0_reg),
.pulse(write_pulse),
.cycle(write_cycle)
);
// Read pulse generation
// -- none --
// Create internal masks for byte enable processing
always @(portabyteenamasks)
begin
for (i = 0; i < data_width; i = i + 1)
begin
mask_vector[i] = (portabyteenamasks[i/port_byte_size] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_int[i] = (portabyteenamasks[i/port_byte_size] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(posedge write_pulse)
begin
// Write stage 1 : write X to memory
if (write_pulse)
begin
mem_data = mem[portaaddr] ^ mask_vector_int;
mem[portaaddr] = mem_data;
end
end
// Write stage 2 : Write actual data to memory
always @(negedge write_pulse)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector[i] == 1'b0)
mem_data[i] = portadatain[i];
mem[portaaddr] = mem_data;
end
// Read stage : asynchronous continuous read
assign portbdataout = mem[portbaddr];
endmodule // arriaiigz_mlab_cell_block
//////////////////////////////////////////////////////////////////////////////////
//Module Name: arriaiigz_io_ibuf //
//Description: Simulation model for ARRIAIIGZ IO Input Buffer //
// //
//////////////////////////////////////////////////////////////////////////////////
module arriaiigz_io_ibuf (
i,
ibar,
dynamicterminationcontrol,
o
);
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter differential_mode = "false";
parameter bus_hold = "false";
parameter simulate_z_as = "Z";
parameter lpm_type = "arriaiigz_io_ibuf";
// SIMULATION_ONLY_PARAMETERS_END
//Input Ports Declaration
input i;
input ibar;
input dynamicterminationcontrol;
//Output Ports Declaration
output o;
// Internal signals
reg out_tmp;
reg o_tmp;
wire out_val ;
reg prev_value;
specify
(i => o) = (0, 0);
(ibar => o) = (0, 0);
endspecify
initial
begin
prev_value = 1'b0;
end
always@(i or ibar)
begin
if(differential_mode == "false")
begin
if(i == 1'b1)
begin
o_tmp = 1'b1;
prev_value = 1'b1;
end
else if(i == 1'b0)
begin
o_tmp = 1'b0;
prev_value = 1'b0;
end
else if( i === 1'bz)
o_tmp = out_val;
else
o_tmp = i;
if( bus_hold == "true")
out_tmp = prev_value;
else
out_tmp = o_tmp;
end
else
begin
case({i,ibar})
2'b00: out_tmp = 1'bX;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bX;
default: out_tmp = 1'bX;
endcase
end
end
assign out_val = (simulate_z_as == "Z") ? 1'bz :
(simulate_z_as == "X") ? 1'bx :
(simulate_z_as == "vcc")? 1'b1 :
(simulate_z_as == "gnd") ? 1'b0 : 1'bz;
pmos (o, out_tmp, 1'b0);
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: arriaiigz_io_obuf //
//Description: Simulation model for ARRIAIIGZ IO Output Buffer //
// //
//////////////////////////////////////////////////////////////////////////////////
module arriaiigz_io_obuf (
i,
oe,
dynamicterminationcontrol,
seriesterminationcontrol,
parallelterminationcontrol,
devoe,
o,
obar
);
//Parameter Declaration
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter shift_series_termination_control = "false";
parameter sim_dynamic_termination_control_is_connected = "false";
parameter lpm_type = "arriaiigz_io_obuf";
//Input Ports Declaration
input i;
input oe;
input devoe;
input dynamicterminationcontrol;
input [13:0] seriesterminationcontrol;
input [13:0] parallelterminationcontrol;
//Outout Ports Declaration
output o;
output obar;
//INTERNAL Signals
reg out_tmp;
reg out_tmp_bar;
reg prev_value;
wire tmp;
wire tmp_bar;
wire tmp1;
wire tmp1_bar;
tri1 devoe;
specify
(i => o) = (0, 0);
(i => obar) = (0, 0);
(oe => o) = (0, 0);
(oe => obar) = (0, 0);
endspecify
initial
begin
prev_value = 'b0;
out_tmp = 'bz;
end
always@(i or oe)
begin
if(oe == 1'b1)
begin
if(open_drain_output == "true")
begin
if(i == 'b0)
begin
out_tmp = 'b0;
out_tmp_bar = 'b1;
prev_value = 'b0;
end
else
begin
out_tmp = 'bz;
out_tmp_bar = 'bz;
end
end
else
begin
if( i == 'b0)
begin
out_tmp = 'b0;
out_tmp_bar = 'b1;
prev_value = 'b0;
end
else if( i == 'b1)
begin
out_tmp = 'b1;
out_tmp_bar = 'b0;
prev_value = 'b1;
end
else
begin
out_tmp = i;
out_tmp_bar = i;
end
end
end
else if(oe == 1'b0)
begin
out_tmp = 'bz;
out_tmp_bar = 'bz;
end
else
begin
out_tmp = 'bx;
out_tmp_bar = 'bx;
end
end
assign tmp = (bus_hold == "true") ? prev_value : out_tmp;
assign tmp_bar = (bus_hold == "true") ? !prev_value : out_tmp_bar;
assign tmp1 = ((oe == 1'b1) && (dynamicterminationcontrol == 1'b1) && (sim_dynamic_termination_control_is_connected == "true")) ? 1'bx :(devoe == 1'b1) ? tmp : 1'bz;
assign tmp1_bar =((oe == 1'b1) && (dynamicterminationcontrol == 1'b1)&& (sim_dynamic_termination_control_is_connected == "true")) ? 1'bx : (devoe == 1'b1) ? tmp_bar : 1'bz;
pmos (o, tmp1, 1'b0);
pmos (obar, tmp1_bar, 1'b0);
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: arriaiigz_ddio_out //
//Description: Simulation model for ARRIAIIGZ DDIO Output //
// //
//////////////////////////////////////////////////////////////////////////////////
module arriaiigz_ddio_out (
datainlo,
datainhi,
clk,
clkhi,
clklo,
muxsel,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter half_rate_mode = "false";
parameter use_new_clocking_model = "false";
parameter lpm_type = "arriaiigz_ddio_out";
//Input Ports Declaration
input datainlo;
input datainhi;
input clk;
input clkhi;
input clklo;
input muxsel;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output dataout;
//Buried Ports Declaration
output dfflo;
output [1:0] dffhi;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg ddioreg_prn;
reg viol_notifier;
wire dfflo_tmp;
wire dffhi_tmp;
wire mux_sel;
wire dffhi1_tmp;
wire sel_mux_hi_in;
wire clk_hi;
wire clk_lo;
wire datainlo_tmp;
wire datainhi_tmp;
reg dinhi_tmp;
reg dinlo_tmp;
wire clk_hr;
reg clk1;
reg clk2;
reg muxsel1;
reg muxsel2;
reg muxsel_tmp;
reg sel_mux_lo_in_tmp;
wire muxsel3;
wire clk3;
wire sel_mux_lo_in;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = (sync_mode == "preset") ? 1'b1: 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
assign dfflo = dfflo_tmp;
assign dffhi[0] = dffhi_tmp;
assign dffhi[1] = dffhi1_tmp;
always@(clk)
begin
clk1 = clk;
clk2 <= clk1;
end
always@(muxsel)
begin
muxsel1 = muxsel;
muxsel2 <= muxsel1;
end
always@(dfflo_tmp)
begin
sel_mux_lo_in_tmp <= dfflo_tmp;
end
always@(datainlo)
begin
dinlo_tmp <= datainlo;
end
always@(datainhi)
begin
dinhi_tmp <= datainhi;
end
always @(mux_sel) begin
muxsel_tmp <= mux_sel;
end
always@(areset)
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
end
else if(async_mode == "preset")
begin
ddioreg_prn = !areset;
end
end
always@(sreset )
begin
if(sync_mode == "clear")
begin
ddioreg_sclr = sreset;
end
else if(sync_mode == "preset")
begin
ddioreg_sload = sreset;
end
end
//DDIO HIGH Register
dffeas ddioreg_hi(
.d(datainhi_tmp),
.clk(clk_hi),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dffhi_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi.power_up = power_up;
assign clk_hi = (use_new_clocking_model == "true") ? clkhi : clk;
assign datainhi_tmp = dinhi_tmp;
//DDIO Low Register
dffeas ddioreg_lo(
.d(datainlo_tmp),
.clk(clk_lo),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
assign clk_lo = (use_new_clocking_model == "true") ? clklo : clk;
assign datainlo_tmp = dinlo_tmp;
//DDIO High Register
dffeas ddioreg_hi1(
.d(dffhi_tmp),
.clk(!clk_hr),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dffhi1_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi1.power_up = power_up;
assign clk_hr = (use_new_clocking_model == "true") ? clkhi : clk;
//registered output selection
arriaiigz_mux21 sel_mux(
.MO(dataout),
.A(sel_mux_lo_in),
.B(sel_mux_hi_in),
.S(muxsel_tmp)
);
assign muxsel3 = muxsel2;
assign clk3 = clk2;
assign mux_sel = (use_new_clocking_model == "true")? muxsel3 : clk3;
assign sel_mux_lo_in = sel_mux_lo_in_tmp;
assign sel_mux_hi_in = (half_rate_mode == "true") ? dffhi1_tmp : dffhi_tmp;
endmodule
//////////////////////////////////////////////////////////////////////////////////
//Module Name: arriaiigz_ddio_oe //
//Description: Simulation model for ARRIAIIGZ DDIO OE //
// //
//////////////////////////////////////////////////////////////////////////////////
module arriaiigz_ddio_oe (
oe,
clk,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter lpm_type = "arriaiigz_ddio_oe";
//Input Ports Declaration
input oe;
input clk;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output dataout;
//Buried Ports Declaration
output dfflo;
output dffhi;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_prn;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg viol_notifier;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
wire dfflo_tmp;
wire dffhi_tmp;
always@(areset or sreset )
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
ddioreg_prn = 1'b1;
end
else if(async_mode == "preset")
begin
ddioreg_aclr = 'b1;
ddioreg_prn = !areset;
end
else
begin
ddioreg_aclr = 'b1;
ddioreg_prn = 'b1;
end
if(sync_mode == "clear")
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = sreset;
ddioreg_sload = 'b0;
end
else if(sync_mode == "preset")
begin
ddioreg_adatasdata = 'b1;
ddioreg_sclr = 'b0;
ddioreg_sload = sreset;
end
else
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = 'b0;
ddioreg_sload = 'b0;
end
end
//DDIO OE Register
dffeas ddioreg_hi(
.d(oe),
.clk(clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dffhi_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi.power_up = power_up;
//DDIO Low Register
dffeas ddioreg_lo(
.d(dffhi_tmp),
.clk(!clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
//registered output
arriaiigz_mux21 or_gate(
.MO(dataout),
.A(dffhi_tmp),
.B(dfflo_tmp),
.S(dfflo_tmp)
);
assign dfflo = dfflo_tmp;
assign dffhi = dffhi_tmp;
endmodule
////////////////////////////////////////////////////////////////////////////////
//Module Name: arriaiigz_ddio_in
//Description: Simulation model for ARRIAIIGZ DDIO IN
//
////////////////////////////////////////////////////////////////////////////////
module arriaiigz_ddio_in (
datain,
clk,
clkn,
ena,
areset,
sreset,
regoutlo,
regouthi,
dfflo,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter use_clkn = "false";
parameter lpm_type = "arriaiigz_ddio_in";
//Input Ports Declaration
input datain;
input clk;
input clkn;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output regoutlo;
output regouthi;
//burried port;
output dfflo;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_prn;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg viol_notifier;
wire ddioreg_clk;
wire dfflo_tmp;
wire regout_tmp_hi;
wire regout_tmp_lo;
wire dff_ena;
initial
begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
assign ddioreg_clk = (use_clkn == "false") ? !clk : clkn;
//Decode the control values for the DDIO registers
always@(areset or sreset )
begin
if(async_mode == "clear")
begin
ddioreg_aclr = !areset;
ddioreg_prn = 1'b1;
end
else if(async_mode == "preset")
begin
ddioreg_aclr = 'b1;
ddioreg_prn = !areset;
end
else
begin
ddioreg_aclr = 'b1;
ddioreg_prn = 'b1;
end
if(sync_mode == "clear")
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = sreset;
ddioreg_sload = 'b0;
end
else if(sync_mode == "preset")
begin
ddioreg_adatasdata = 'b1;
ddioreg_sclr = 'b0;
ddioreg_sload = sreset;
end
else
begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = 'b0;
ddioreg_sload = 'b0;
end
end
//DDIO high Register
dffeas ddioreg_hi(
.d(datain),
.clk(clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(regout_tmp_hi),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi.power_up = power_up;
//DDIO Low Register
dffeas ddioreg_lo(
.d(datain),
.clk(ddioreg_clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
dffeas ddioreg_lo1(
.d(dfflo_tmp),
.clk(clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(regout_tmp_lo),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo1.power_up = power_up;
assign regouthi = regout_tmp_hi;
assign regoutlo = regout_tmp_lo;
assign dfflo = dfflo_tmp;
endmodule
///////////////////////////////////////////////////////////////////////////////
// Module Name: arriaiigz_mac_register //
// Description: ARRIAIIGZ MAC variable width register //
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module arriaiigz_mac_register (
datain,
clk,
aclr,
sload,
bypass_register,
dataout
);
//PARAMETER
parameter data_width = 18;
//INPUT PORTS
input[data_width -1 :0] datain;
input clk;
input aclr;
input sload;
input bypass_register;
//OUTPUT PORTS
output [data_width -1 :0] dataout;
//INTERNAL SIGNALS
reg [data_width -1:0] dataout_tmp;
reg viol_notifier;
reg prev_clk_val;
//TIMING SPECIFICATION
specify
specparam TSU = 0; // Set up time
specparam TH = 0; // Hold time
specparam TCO = 0; // Clock to Output time
specparam TCLR = 0; // Clear time
specparam TCLR_MIN_PW = 0; // Minimum pulse width of clear
specparam TPRE = 0; // Preset time
specparam TPRE_MIN_PW = 0; // Minimum pulse width of preset
specparam TCLK_MIN_PW = 0; // Minimum pulse width of clock
specparam TCE_MIN_PW = 0; // Minimum pulse width of clock enable
specparam TCLKL = 0; // Minimum clock low time
specparam TCLKH = 0; // Minimum clock high time
$setup (datain, posedge clk, 0, viol_notifier);
$hold (posedge clk, datain, 0, viol_notifier);
$setup (sload, posedge clk, 0, viol_notifier );
$hold (posedge clk, sload, 0, viol_notifier );
(posedge aclr => (dataout +: 'b0)) = (0,0);
(posedge clk => (dataout +: dataout_tmp)) = (0,0);
endspecify
initial
begin
dataout_tmp = 0;
prev_clk_val = 1'b0;
end
always @(clk or posedge aclr or bypass_register or datain)
begin
if(bypass_register == 1'b1)
dataout_tmp <= datain;
else
begin
if (aclr == 1'b1)
dataout_tmp <= 0;
else if (prev_clk_val == 1'b0 && clk == 1'b1)
begin
if(sload == 1'b1)
dataout_tmp <= datain;
else
dataout_tmp <= dataout_tmp;
end
end
prev_clk_val = clk;
end
assign dataout = dataout_tmp;
endmodule
///////////////////////////////////////////////////////////////////////////////
// Module Name: arriaiigz_mac_multiplier //
// Description: ARRIAIIGZ MAC signed multiplier //
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module arriaiigz_mac_multiplier (
dataa,
datab,
signa,
signb,
dataout
);
//PARAMETER
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
//INPUT PORTS
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
//OUTPUT PORTS
output [dataout_width -1 :0] dataout;
//INTERNAL SIGNALS
wire [dataout_width -1:0] product; //product of dataa and datab
wire [dataout_width -1:0] abs_product; //|product| of dataa and datab
wire [dataa_width-1:0] abs_a; //absolute value of dataa
wire [datab_width-1:0] abs_b; //absolute value of dadab
wire product_sign; // product sign bit
wire dataa_sign; //dataa sign bit
wire datab_sign; //datab sign bit
//TIMING SPECIFICATION
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
endspecify
//Outputassignment
assign dataa_sign = dataa[dataa_width-1] && signa;
assign datab_sign = datab[datab_width-1] && signb;
assign product_sign = dataa_sign ^ datab_sign;
assign abs_a = dataa_sign ? (~dataa + 1'b1) : dataa;
assign abs_b = datab_sign ? (~datab + 1'b1) : datab;
assign abs_product = abs_a * abs_b;
assign product = product_sign ? (~abs_product + 1) : abs_product;
assign dataout = product;
endmodule
//////////////////////////////////////////////////////////////////////////////////
// Module Name: arriaiigz_mac_mult_atom //
// Description: Simulation model for arriaiigz mac mult atom. //
// This model instantiates the following components. //
// 1.arriaiigz_mac_register. //
// 2.arriaiigz_mac_multiplier. //
//////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module arriaiigz_mac_mult(
dataa,
datab,
signa,
signb,
clk,
aclr,
ena,
dataout,
scanouta,
devclrn,
devpor
);
//PARAMETERS
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataa_clock = "none";
parameter datab_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter scanouta_clock = "none";
parameter dataa_clear = "none";
parameter datab_clear = "none";
parameter signa_clear = "none";
parameter signb_clear = "none";
parameter scanouta_clear = "none";
parameter signa_internally_grounded = "false";
parameter signb_internally_grounded = "false";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = dataa_width + datab_width;
// SIMULATION_ONLY_PARAMETERS_END
parameter lpm_type = "arriaiigz_mac_mult";
//INPUT PORTS
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
input [3:0] clk;
input [3:0] aclr;
input [3:0] ena;
input devclrn;
input devpor;
//OUTPUT PORTS
output [dataout_width-1:0] dataout;
output [dataa_width-1:0] scanouta;
tri1 devclrn;
tri1 devpor;
//Internal signals to instantiate the dataa input register unit
wire [3:0] dataa_clk_value;
wire [3:0] dataa_aclr_value;
wire dataa_clk;
wire dataa_aclr;
wire dataa_sload;
wire dataa_bypass_register;
wire [dataa_width-1:0] dataa_in_reg;
//Internal signals to instantiate the datab input register unit
wire [3:0] datab_clk_value;
wire [3:0] datab_aclr_value;
wire datab_clk;
wire datab_aclr;
wire datab_sload;
wire datab_bypass_register;
wire [datab_width-1:0] datab_in_reg;
//Internal signals to instantiate the signa input register unit
wire [3:0] signa_clk_value;
wire [3:0] signa_aclr_value;
wire signa_clk;
wire signa_aclr;
wire signa_sload;
wire signa_bypass_register;
wire signa_in_reg;
//Internal signbls to instantiate the signb input register unit
wire [3:0] signb_clk_value;
wire [3:0] signb_aclr_value;
wire signb_clk;
wire signb_aclr;
wire signb_sload;
wire signb_bypass_register;
wire signb_in_reg;
//Internal scanoutals to instantiate the scanouta input register unit
wire [3:0] scanouta_clk_value;
wire [3:0] scanouta_aclr_value;
wire scanouta_clk;
wire scanouta_aclr;
wire scanouta_sload;
wire scanouta_bypass_register;
wire [dataa_width -1 :0] scanouta_in_reg;
//Internal Signals to instantiate the mac multiplier
wire signa_mult;
wire signb_mult;
//Instantiate the dataa input Register
arriaiigz_mac_register dataa_input_register (
.datain(dataa),
.clk(dataa_clk),
.aclr(dataa_aclr),
.sload(dataa_sload),
.bypass_register(dataa_bypass_register),
.dataout(dataa_in_reg)
);
defparam dataa_input_register.data_width = dataa_width;
//decode the clk and aclr values
assign dataa_clk_value = (dataa_clock == "0") ? 4'b0000 :
(dataa_clock == "1") ? 4'b0001 :
(dataa_clock == "2") ? 4'b0010 :
(dataa_clock == "3") ? 4'b0011 : 4'b0000;
assign dataa_aclr_value =(dataa_clear == "0") ? 4'b0000 :
(dataa_clear == "1") ? 4'b0001 :
(dataa_clear == "2") ? 4'b0010 :
(dataa_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign dataa_clk = clk[dataa_clk_value] ? 1'b1 : 1'b0;
assign dataa_aclr = aclr[dataa_aclr_value] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign dataa_sload = ena[dataa_clk_value] ? 1'b1 : 1'b0;
assign dataa_bypass_register = (dataa_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the datab input Register
arriaiigz_mac_register datab_input_register (
.datain(datab),
.clk(datab_clk),
.aclr(datab_aclr),
.sload(datab_sload),
.bypass_register(datab_bypass_register),
.dataout(datab_in_reg)
);
defparam datab_input_register.data_width = datab_width;
//decode the clk and aclr values
assign datab_clk_value = (datab_clock == "0") ? 4'b0000 :
(datab_clock == "1") ? 4'b0001 :
(datab_clock == "2") ? 4'b0010 :
(datab_clock == "3") ? 4'b0011 : 4'b0000;
assign datab_aclr_value = (datab_clear == "0") ? 4'b0000 :
(datab_clear == "1") ? 4'b0001 :
(datab_clear == "2") ? 4'b0010 :
(datab_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign datab_clk = clk[datab_clk_value] ? 1'b1 : 1'b0;
assign datab_aclr = aclr[datab_aclr_value] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign datab_sload = ena[datab_clk_value] ? 1'b1 : 1'b0;
assign datab_bypass_register = (datab_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the signa input Register
arriaiigz_mac_register signa_input_register (
.datain(signa),
.clk(signa_clk),
.aclr(signa_aclr),
.sload(signa_sload),
.bypass_register(signa_bypass_register),
.dataout(signa_in_reg)
);
defparam signa_input_register.data_width = 1;
//decode the clk and aclr values
assign signa_clk_value =(signa_clock == "0") ? 4'b0000 :
(signa_clock == "1") ? 4'b0001 :
(signa_clock == "2") ? 4'b0010 :
(signa_clock == "3") ? 4'b0011 : 4'b0000;
assign signa_aclr_value = (signa_clear == "0") ? 4'b0000 :
(signa_clear == "1") ? 4'b0001 :
(signa_clear == "2") ? 4'b0010 :
(signa_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signa_clk = clk[signa_clk_value] ? 1'b1 : 1'b0;
assign signa_aclr = aclr[signa_aclr_value] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign signa_sload = ena[signa_clk_value] ? 1'b1 : 1'b0;
assign signa_bypass_register = (signa_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the signb input Register
arriaiigz_mac_register signb_input_register (
.datain(signb),
.clk(signb_clk),
.aclr(signb_aclr),
.sload(signb_sload),
.bypass_register(signb_bypass_register),
.dataout(signb_in_reg)
);
defparam signb_input_register.data_width = 1;
//decode the clk and aclr values
assign signb_clk_value =(signb_clock == "0") ? 4'b0000 :
(signb_clock == "1") ? 4'b0001 :
(signb_clock == "2") ? 4'b0010 :
(signb_clock == "3") ? 4'b0011 : 4'b0000;
assign signb_aclr_value = (signb_clear == "0") ? 4'b0000 :
(signb_clear == "1") ? 4'b0001 :
(signb_clear == "2") ? 4'b0010 :
(signb_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signb_clk = clk[signb_clk_value] ? 1'b1 : 1'b0;
assign signb_aclr = aclr[signb_aclr_value] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign signb_sload = ena[signb_clk_value] ? 1'b1 : 1'b0;
assign signb_bypass_register = (signb_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the scanouta input Register
arriaiigz_mac_register scanouta_input_register (
.datain(dataa_in_reg),
.clk(scanouta_clk),
.aclr(scanouta_aclr),
.sload(scanouta_sload),
.bypass_register(scanouta_bypass_register),
.dataout(scanouta)
);
defparam scanouta_input_register.data_width = dataa_width;
//decode the clk and aclr values
assign scanouta_clk_value =(scanouta_clock == "0") ? 4'b0000 :
(scanouta_clock == "1") ? 4'b0001 :
(scanouta_clock == "2") ? 4'b0010 :
(scanouta_clock == "3") ? 4'b0011 : 4'b0000;
assign scanouta_aclr_value = (scanouta_clear == "0") ? 4'b0000 :
(scanouta_clear == "1") ? 4'b0001 :
(scanouta_clear == "2") ? 4'b0010 :
(scanouta_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign scanouta_clk = clk[scanouta_clk_value] ? 1'b1 : 1'b0;
assign scanouta_aclr = aclr[scanouta_aclr_value] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign scanouta_sload = ena[scanouta_clk_value] ? 1'b1 : 1'b0;
assign scanouta_bypass_register = (scanouta_clock == "none") ? 1'b1 : 1'b0;
//Instantiate mac_multiplier block
arriaiigz_mac_multiplier mac_multiplier (
.dataa(dataa_in_reg),
.datab(datab_in_reg),
.signa(signa_mult),
.signb(signb_mult),
.dataout(dataout)
);
defparam mac_multiplier.dataa_width = dataa_width;
defparam mac_multiplier.datab_width = datab_width;
assign signa_mult = (signa_internally_grounded == "true")? 1'b0 : signa_in_reg;
assign signb_mult = (signb_internally_grounded == "true")? 1'b0 : signb_in_reg;
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: arriaiigz_fsa_isse //
// Description: ARRIAIIGZ first stage adder input selection and sign extension block. //
//////////////////////////////////////////////////////////////////////////////////////////////////
module arriaiigz_fsa_isse(
dataa,
datab,
datac,
datad,
chainin,
signa,
signb,
dataa_out,
datab_out,
datac_out,
datad_out,
chainin_out,
operation
);
parameter dataa_width = 36;
parameter datab_width = 36;
parameter datac_width = 36;
parameter datad_width = 36;
parameter chainin_width = 44;
parameter operation_mode = "output_only";
parameter multa_signa_internally_grounded = "false";
parameter multa_signb_internally_grounded = "false";
parameter multb_signa_internally_grounded = "false";
parameter multb_signb_internally_grounded = "false";
parameter multc_signa_internally_grounded = "false";
parameter multc_signb_internally_grounded = "false";
parameter multd_signa_internally_grounded = "false";
parameter multd_signb_internally_grounded = "false";
input [dataa_width -1:0] dataa;
input [datab_width -1:0] datab;
input [datac_width -1:0] datac;
input [datad_width -1:0] datad;
input [chainin_width -1 :0] chainin;
input signa;
input signb;
output [71:0] dataa_out;
output [71:0] datab_out;
output [71:0] datac_out;
output [71:0] datad_out;
output [71:0] chainin_out;
output [3:0] operation;
wire sign;
wire [71:0] datab_out_fun;
wire [71:0] datac_out_fun;
wire [71:0] datad_out_fun;
wire [71:0] datab_out_tim;
wire [71:0] datac_out_tim;
wire [71:0] datad_out_tim;
assign sign = signa | signb;
//Decode the operation value depending on the mode of operation
assign operation = (operation_mode == "output_only") ? 4'b0000 :
(operation_mode == "one_level_adder") ? 4'b0001 :
(operation_mode == "loopback") ? 4'b0010 :
(operation_mode == "accumulator") ? 4'b0011 :
(operation_mode == "accumulator_chain_out") ? 4'b0100 :
(operation_mode == "two_level_adder") ? 4'b0101 :
(operation_mode == "two_level_adder_chain_out") ? 4'b0110 :
(operation_mode == "36_bit_multiply") ? 4'b0111 :
(operation_mode == "shift") ? 4'b1000 :
(operation_mode == "double") ? 4'b1001 : 4'b0000;
wire active_signb, active_signc, active_signd;
wire read_new_param;
assign read_new_param = ( multa_signa_internally_grounded == "false" && multa_signb_internally_grounded == "false"
&& multb_signa_internally_grounded == "false" && multb_signb_internally_grounded == "false"
&& multc_signa_internally_grounded == "false" && multc_signb_internally_grounded == "false"
&& multd_signa_internally_grounded == "false" && multd_signb_internally_grounded == "false") ? 1'b0 : 1'b1;
assign active_signb = ((operation_mode == "36_bit_multiply") ||(operation_mode == "shift") || (operation_mode == "double")) ?
((multb_signb_internally_grounded == "false" && multb_signa_internally_grounded == "true") ? signb
:((multb_signb_internally_grounded == "true" && multb_signa_internally_grounded == "false" )? signa
:((multb_signb_internally_grounded == "false" && multb_signa_internally_grounded == "false")? sign : 1'b0)))
: sign;
assign active_signc = ((operation_mode == "36_bit_multiply") ||(operation_mode == "shift") || (operation_mode == "double")) ?
((multc_signb_internally_grounded == "false" && multc_signa_internally_grounded == "true") ? signb
:((multc_signb_internally_grounded == "true" && multc_signa_internally_grounded == "false" )? signa
:((multc_signb_internally_grounded == "false" && multc_signa_internally_grounded == "false")? sign : 1'b0)))
: sign;
assign active_signd = ((operation_mode == "36_bit_multiply") ||(operation_mode == "shift") || (operation_mode == "double")) ?
((multd_signb_internally_grounded == "false" && multd_signa_internally_grounded == "true") ? signb
:((multd_signb_internally_grounded == "true" && multd_signa_internally_grounded == "false" )? signa
:((multd_signb_internally_grounded == "false" && multd_signa_internally_grounded == "false")? sign : 1'b0)))
: sign;
assign dataa_out = (dataa[dataa_width-1]&& sign)
?{{(72-dataa_width){1'b1}},dataa[dataa_width -1 : 0]}
:{{(72-dataa_width){1'b0}},dataa[dataa_width -1 : 0]} ;
assign datab_out_tim = (datab[datab_width-1]&& active_signb)
?{{(72-datab_width){1'b1}},datab[datab_width -1 : 0]}
:{{(72-datab_width){1'b0}},datab[datab_width -1 : 0]} ;
assign datac_out_tim = (datac[datac_width-1]&& active_signc)
?{{(72-datac_width){1'b1}},datac[datac_width -1 : 0]}
:{{(72-datac_width){1'b0}},datac[datac_width -1 : 0]} ;
assign datad_out_tim = (datad[datad_width-1]&& active_signd)
?{{(72-datad_width){1'b1}},datad[datad_width -1 : 0]}
:{{(72-datad_width){1'b0}},datad[datad_width -1 : 0]} ;
assign datab_out_fun = ((operation_mode == "36_bit_multiply") ||(operation_mode == "shift"))
?((datab[datab_width-1]&& signb)
?{{(72-datab_width){1'b1}},datab[datab_width -1 : 0]}
:{{(72-datab_width){1'b0}},datab[datab_width -1 : 0]})
:(operation_mode == "double")
?((datab[datab_width-1]&& signa)
?{{(72-datab_width){1'b1}},datab[datab_width -1 : 0]}
:{{(72-datab_width){1'b0}},datab[datab_width -1 : 0]})
:((datab[datab_width-1]&& sign)
?{{(72-datab_width){1'b1}},datab[datab_width -1 : 0]}
:{{(72-datab_width){1'b0}},datab[datab_width -1 : 0]}) ;
assign datac_out_fun =((operation_mode == "36_bit_multiply") ||(operation_mode == "shift"))
?((datac[datac_width-1]&& signa)
?{{(72-datac_width){1'b1}},datac[datac_width -1 : 0]}
:{{(72-datac_width){1'b0}},datac[datac_width -1 : 0]} )
:((datac[datac_width-1]&& sign)
?{{(72-datac_width){1'b1}},datac[datac_width -1 : 0]}
:{{(72-datac_width){1'b0}},datac[datac_width -1 : 0]}) ;
assign datad_out_fun = ((operation_mode == "36_bit_multiply") ||(operation_mode == "shift"))
?{{(72-datad_width){1'b0}},datad[datad_width -1 : 0]}
:(operation_mode == "double")
?((datad[datad_width-1]&& signa)
?{{(72-datad_width){1'b1}},datad[datad_width -1 : 0]}
:{{(72-datad_width){1'b0}},datad[datad_width -1 : 0]} )
:((datad[datad_width-1]&& sign)
?{{(72-datad_width){1'b1}},datad[datad_width -1 : 0]}
:{{(72-datad_width){1'b0}},datad[datad_width -1 : 0]}) ;
assign datab_out = (read_new_param == 1'b1) ? datab_out_tim : datab_out_fun;
assign datac_out = (read_new_param == 1'b1) ? datac_out_tim : datac_out_fun;
assign datad_out = (read_new_param == 1'b1) ? datad_out_tim : datad_out_fun;
assign chainin_out = (chainin[chainin_width-1])
?{{(72-chainin_width){1'b1}},chainin[chainin_width -1 : 0]}
:{{(72-chainin_width){1'b0}},chainin[chainin_width -1 : 0]} ;
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: arriaiigz_first_stage_add_sub //
// Description: ARRIAIIGZ First Stage Adder Subtractor Unit //
//////////////////////////////////////////////////////////////////////////////////////////////////
module arriaiigz_first_stage_add_sub(
dataa,
datab,
sign,
operation,
dataout
);
//PARAMETERS
parameter dataa_width = 36;
parameter datab_width = 36;
parameter fsa_mode = "add";
// INPUT PORTS
input [71 : 0 ] dataa;
input [71 : 0 ] datab;
input sign;
input [3:0] operation;
// OUTPUT PORTS
output [71: 0] dataout;
//INTERNAL SIGNALS
reg[71 :0] dataout_tmp;
reg[71:0] abs_b;
reg[71:0] abs_a;
reg sign_a;
reg sign_b;
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(sign *> dataout) = (0, 0);
endspecify
//assign the output values
assign dataout = dataout_tmp;
always @(dataa or datab or sign or operation)
begin
if((operation == 4'b0111) ||(operation == 4'b1000)|| (operation == 4'b1001)) //36 bit multiply, shift and add
begin
dataout_tmp = {dataa[53:36],dataa[35:0],18'b0} + datab;
end
else
begin
sign_a = (sign && dataa[dataa_width -1]);
abs_a = (sign_a) ? (~dataa + 1'b1) : dataa;
sign_b = (sign && datab[datab_width-1]);
abs_b = (sign_b) ? (~datab + 1'b1) : datab;
if (fsa_mode == "add")
dataout_tmp = (sign_a ? -abs_a : abs_a) + (sign_b ?-abs_b : abs_b);
else
dataout_tmp = (sign_a ? -abs_a : abs_a) - (sign_b ?-abs_b : abs_b);
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: arriaiigz_second_stage_add_accum //
// Description: ARRIAIIGZ Second stage Adder and Accumulator/Decimator Unit //
//////////////////////////////////////////////////////////////////////////////////////////////////
module arriaiigz_second_stage_add_accum(
dataa,
datab,
accumin,
sign,
operation,
dataout,
overflow
);
//PARAMETERS
parameter dataa_width = 36;
parameter datab_width = 36;
parameter accum_width = dataa_width + 8;
parameter ssa_mode = "add";
// INPUT PORTS
input [71 : 0 ] dataa;
input [71 : 0 ] datab;
input [71 : 0] accumin;
input sign;
input [3:0] operation;
// OUTPUT PORTS
output overflow;
output [71 :0] dataout;
//INTERNAL SIGNALS
reg[71 :0] dataout_tmp;
reg [71:0] dataa_tmp;
reg [71:0] datab_tmp;
reg[71:0] accum_tmp;
reg sign_a;
reg sign_b;
reg sign_accum;
reg sign_out;
reg overflow_tmp;
reg [71 :0] abs_a;
reg [71 :0] abs_b;
reg [71 :0] abs_accum;
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(sign *> dataout) = (0, 0);
(dataa *> overflow) = (0, 0);
(datab *> overflow) = (0, 0);
(sign *> overflow) = (0, 0);
if(operation == 4'b0011 || operation == 4'b0100 )
(accumin *> dataout) = (0, 0);
if(operation == 4'b0011 || operation == 4'b0100 )
(accumin *> overflow) = (0, 0);
endspecify
//assign the output values
assign dataout = dataout_tmp;
assign overflow = overflow_tmp;
always@(dataa or datab or sign or accumin or operation)
begin
sign_accum = (sign && accumin[accum_width -1]);
abs_accum = (sign_accum) ? (~accumin + 1'b1) : accumin;
sign_a = (sign && dataa[dataa_width-1]);
abs_a = (sign_a) ? (~dataa + 1'b1) : dataa;
sign_b = (sign && datab[datab_width-1]);
abs_b = (sign_b) ? (~datab + 1'b1) : datab;
if(operation == 4'b0011 || operation == 4'b0100 )//Accumultor or Accumulator chainout
begin
if (ssa_mode == "add")
dataout_tmp = (sign_accum ? -abs_accum[accum_width -1 : 0] : abs_accum[accum_width -1 : 0]) + (sign_a ? -abs_a[accum_width -1 : 0] : abs_a[accum_width -1 : 0]) + (sign_b ? -abs_b[accum_width -1 : 0] : abs_b[accum_width -1 : 0]);
else
dataout_tmp = (sign_accum ? -abs_accum[accum_width -1 : 0] : abs_accum[accum_width -1 : 0]) - (sign_a ? -abs_a[accum_width -1 : 0] : abs_a[accum_width -1 : 0]) - (sign_b ? -abs_b[accum_width -1 : 0] : abs_b[accum_width -1 : 0]);
if(sign)
overflow_tmp = dataout_tmp[accum_width] ^ dataout_tmp[accum_width -1];
else
begin
if(ssa_mode == "add")
overflow_tmp = dataout_tmp[accum_width];
else
overflow_tmp = 1'bX;
end
end
else if( operation == 4'b0101 || operation == 4'b0110)// two level adder or two level with chainout
begin
dataout_tmp = (sign_a ? -abs_a : abs_a) + (sign_b ?-abs_b : abs_b);
overflow_tmp = 'b0;
end
else if(( operation == 4'b0111) ||(operation == 4'b1000)) //36 bit multiply; shift and add
begin
dataout_tmp[71:0] = {dataa[53:0],18'b0} + datab;
overflow_tmp = 'b0;
end
else if(( operation == 4'b1001) ) //double mode
begin
dataout_tmp[71:0] = dataa + datab;
overflow_tmp = 'b0;
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: arriaiigz_round_block //
// Description: ARRIAIIGZ round block //
//////////////////////////////////////////////////////////////////////////////////////////////////
module arriaiigz_round_block(
datain,
round,
datain_width,
dataout
);
parameter round_mode = "nearest_integer";
parameter operation_mode = "output_only";
parameter round_width = 15;
input [71 :0 ] datain;
input round;
input [7:0] datain_width;
output [71 : 0] dataout;
reg sign;
reg [71 :0] result_tmp;
reg [71:0] dataout_tmp;
reg [71 :0 ] dataout_value;
integer i,j;
initial
begin
result_tmp = {(72){1'b0}};
end
assign dataout = dataout_value;
always@(datain or round)
begin
if(round == 1'b0)
dataout_value = datain;
else
begin
j = 0;
sign = 0;
dataout_value = datain;
if(datain_width > round_width)
begin
for(i = datain_width - round_width ; i < datain_width ; i = i+1)
begin
result_tmp[j]= datain[i];
j = j +1;
end
for (i = 0; i < datain_width - round_width -1 ; i = i +1)
begin
sign = sign | datain[i];
dataout_value[i] = 1'bX;
end
dataout_value[datain_width - round_width -1] = 1'bX;
//rounding logic
if(datain[datain_width - round_width -1 ] == 1'b0)// fractional < 0.5
begin
dataout_tmp = result_tmp;
end
else if((datain[datain_width - round_width -1 ] == 1'b1) && (sign == 1'b1))//fractional > 0.5
begin
dataout_tmp = result_tmp + 1'b1;
end
else
begin
if(round_mode == "nearest_even")//unbiased rounding
begin
if(result_tmp % 2) //check for odd integer
dataout_tmp = result_tmp + 1'b1;
else
dataout_tmp = result_tmp;
end
else //biased rounding
begin
dataout_tmp = result_tmp + 1'b1;
end
end
j = 0;
for(i = datain_width - round_width ; i < datain_width ; i = i+1)
begin
dataout_value[i]= dataout_tmp[j];
j = j+1;
end
end
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: arriaiigz_saturation_block //
// Description: ARRIAIIGZ saturation block //
//////////////////////////////////////////////////////////////////////////////////////////////////
module arriaiigz_saturate_block(
datain,
saturate,
round,
signa,
signb,
datain_width,
dataout,
saturation_overflow
);
parameter dataa_width = 36;
parameter datab_width = 36;
parameter round_width = 15;
parameter saturate_width = 1;
parameter accum_width = dataa_width + 8;
parameter saturate_mode = " asymmetric";
parameter operation_mode = "output_only";
input [71:0] datain;
input saturate;
input round;
input signa;
input signb;
input [7:0] datain_width;
output[71 :0 ] dataout;
output saturation_overflow;
//Internal signals
reg [71 : 0] dataout_tmp;
reg saturation_overflow_tmp;
wire msb;
wire sign;
integer i;
reg [71 :0] max;
reg [71 :0] min;
reg sign_tmp;
reg data_tmp;
initial
begin
max = {(72){1'b0}};
min = {(72){1'b1}};
sign_tmp = 1'b1;
data_tmp = 1'b0;
end
assign sign = signa | signb;
assign msb = ((operation_mode == "accumulator")
||(operation_mode == "accumulator_chain_out")
||(operation_mode == "two_level_adder_chain_out")) ? datain[accum_width] :
(operation_mode == "two_level_adder") ? datain[dataa_width + 1] :
((operation_mode == "one_level_adder")||(operation_mode == "loopback")) ? datain[dataa_width] : datain[dataa_width -1];
assign dataout = dataout_tmp;
assign saturation_overflow = saturation_overflow_tmp;
always @(datain or datain_width or sign or round or msb or saturate)
begin
if(saturate == 1'b0)
begin
dataout_tmp = datain;
saturation_overflow_tmp = 1'b0;
end
else
begin
saturation_overflow_tmp = 1'b0;
data_tmp = 1'b0;
sign_tmp = 1'b1;
// "X" when round is asserted.
if((round == 1'b1))
begin
for(i = 0; i < datain_width - round_width; i = i +1)
begin
min[i] = 1'bX;
max[i] = 1'bX;
end
end
// "X" for symmetric saturation, only if data is negative
if(( saturate_mode == "symmetric"))
begin
for(i = 0; i < datain_width - round_width; i = i +1)
begin
if(round == 1'b1)
begin
max[i] = 1'bX;
min[i] = 1'bX;
end
else
begin
max[i] = 1'b1;
min[i] = 1'b0;
end
end
for( i= datain_width - round_width; i < datain_width - saturate_width; i = i+1)
begin
data_tmp = data_tmp | datain[i];
max[i] = 1'b1;
min[i] = 1'b0;
end
if (round == 1'b1)
min[datain_width - round_width] = 1'b1;
else
min[0] = 1'b1;
end
if(( saturate_mode == "asymmetric"))
begin
for( i= 0; i < datain_width -saturate_width; i = i+1)
begin
max[i] = 1'b1;
min[i] = 1'b0;
end
end
//check for overflow
if((saturate_width ==1))
begin
if(msb != datain[datain_width-1])
saturation_overflow_tmp = 1'b1;
else
sign_tmp = sign_tmp & datain[datain_width-1];
end
else
begin
for (i = datain_width - saturate_width; i < datain_width ; i = i + 1)
begin
sign_tmp = sign_tmp & datain[i];
if(datain[datain_width -1 ] != datain[i])
saturation_overflow_tmp = 1'b1;
end
end
// Trigger the saturation overflow for data=-2^n in case of symmetric saturation.
if((sign_tmp == 1'b1) && (data_tmp == 1'b0) && (saturate_mode == "symmetric"))
saturation_overflow_tmp = 1'b1;
if(saturation_overflow_tmp)
begin
if((operation_mode == "output_only") || (operation_mode == "accumulator_chain_out") || (operation_mode == "two_level_adder_chain_out"))
begin
if(msb)
dataout_tmp = min;
else
dataout_tmp = max;
end
else
begin
if (sign)
begin
if(msb)
dataout_tmp = min;
else
dataout_tmp = max;
end
else
dataout_tmp = 72'bX;
end
end
else
dataout_tmp = datain;
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: arriaiigz_round_saturate_block //
// Description: ARRIAIIGZ round and saturation Unit. //
// This unit instantiated the following components. //
// 1.arriaiigz_round_block. //
// 2.arriaiigz_saturate_block. //
//////////////////////////////////////////////////////////////////////////////////////////////////
module arriaiigz_round_saturate_block(
datain,
round,
saturate,
signa,
signb,
datain_width,
dataout,
saturationoverflow
);
parameter dataa_width = 36;
parameter datab_width = 36;
parameter saturate_width = 15;
parameter round_width = 15;
parameter saturate_mode = " asymmetric";
parameter round_mode = "nearest_integer";
parameter operation_mode = "output_only";
input [71:0] datain;
input round;
input saturate;
input signa;
input signb;
input [7:0] datain_width;
output[71:0] dataout;
output saturationoverflow;
wire [71:0] dataout_round;
wire [7:0] datain_width;
wire [7:0] fraction_width;
wire[7:0] datasize;
specify
(datain *> dataout) = (0, 0);
(round *> dataout) = (0, 0);
(saturate *> dataout) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
(datain *> saturationoverflow) = (0, 0);
(round *> saturationoverflow) = (0, 0);
(saturate *> saturationoverflow) = (0, 0);
(signa *> saturationoverflow) = (0, 0);
(signb *> saturationoverflow) = (0, 0);
endspecify
arriaiigz_round_block round_unit (
.datain(datain),
.round(round),
.datain_width(datain_width),
.dataout(dataout_round)
);
defparam round_unit.round_mode = round_mode;
defparam round_unit.operation_mode = operation_mode;
defparam round_unit.round_width = round_width;
arriaiigz_saturate_block saturate_unit(
.datain(dataout_round),
.saturate(saturate),
.round(round),
.signa(signa),
.signb(signb),
.datain_width(datain_width),
.dataout(dataout),
.saturation_overflow(saturationoverflow)
);
defparam saturate_unit.dataa_width = dataa_width;
defparam saturate_unit.datab_width = datab_width;
defparam saturate_unit.round_width = round_width;
defparam saturate_unit.saturate_width = saturate_width;
defparam saturate_unit.saturate_mode = saturate_mode;
defparam saturate_unit.operation_mode = operation_mode;
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: arriaiigz_rotate_shift_block //
// Description: ARRIAIIGZ rotate and shift Unit. //
//////////////////////////////////////////////////////////////////////////////////////////////////
module arriaiigz_rotate_shift_block(
datain,
rotate,
shiftright,
signa,
signb,
dataout
);
parameter dataa_width = 32;
parameter datab_width = 32;
parameter operation_mode = "output_only";
input [71:0] datain;
input rotate;
input shiftright;
input signa;
input signb;
wire sign;
output [71:0] dataout;
reg[71:0] dataout_tmp;
specify
(datain *> dataout) = (0, 0);
(rotate *> dataout) = (0, 0);
(shiftright*> dataout) = (0, 0);
endspecify
assign sign = signa ^ signb;
assign dataout = dataout_tmp;
always@(datain or rotate or shiftright)
begin
dataout_tmp = datain;
if((rotate == 0) && (shiftright == 0))
dataout_tmp[39:8] = datain[39:8];
else if((rotate == 0) && (shiftright == 1))
dataout_tmp[39:8]= datain[71:40];
else if ((rotate == 1) && (shiftright == 0))
dataout_tmp[39:8] = datain[71:40] | datain[39:8];
else
dataout_tmp = datain;
end
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
// Module Name: arriaiigz_carry_chain_adder //
// Description: ARRIAIIGZ carry chain adder Unit. //
//////////////////////////////////////////////////////////////////////////////////////////////////
module arriaiigz_carry_chain_adder(
dataa,
datab,
dataout
);
// INPUT PORTS
input [71 : 0 ] dataa;
input [71 : 0 ] datab;
// OUTPUT PORTS
output [71 :0] dataout;
reg[71:0] dataout_tmp;
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
endspecify
assign dataout = dataout_tmp;
initial
begin
dataout_tmp = 72'b0;
end
always@(dataa or datab)
begin
dataout_tmp = {dataa[43],dataa[43:0]} + {datab[43],datab[43:0]};
end
endmodule
//////////////////////////////////////////////////////////////////////////////////
// Module Name: arriaiigz_mac_out_atom //
// Description: Simulation model for arriaiigz mac out atom //
// This model instantiates the following components //
// 1.arriaiigz_mac_bit_register //
// 2.arriaiigz_mac_register //
// 3.arriaiigz_fsa_isse //
// 4.arriaiigz_first_stage_add_sub //
// 5.arriaiigz_second_stage_add_accum //
// 6.arriaiigz_round_saturate_block //
// 7.arriaiigz_rotate_shift_block //
// 8.arriaiigz_carry_chain_adder //
//////////////////////////////////////////////////////////////////////////////////
module arriaiigz_mac_out(
dataa,
datab,
datac,
datad,
signa,
signb,
chainin,
round,
saturate,
zeroacc,
roundchainout,
saturatechainout,
zerochainout,
zeroloopback,
rotate,
shiftright,
clk,
ena,
aclr,
loopbackout,
dataout,
overflow,
dftout,
saturatechainoutoverflow,
devpor,
devclrn
);
//Parameter declaration
parameter operation_mode = "output_only";
parameter dataa_width = 1;
parameter datab_width = 1;
parameter datac_width = 1;
parameter datad_width = 1;
parameter chainin_width = 1;
parameter round_width = 15;
parameter round_chain_out_width = 15;
parameter saturate_width = 15;
parameter saturate_chain_out_width = 15;
parameter first_adder0_clock = "none";
parameter first_adder0_clear = "none";
parameter first_adder1_clock = "none";
parameter first_adder1_clear = "none";
parameter second_adder_clock = "none";
parameter second_adder_clear = "none";
parameter output_clock = "none";
parameter output_clear = "none";
parameter signa_clock = "none";
parameter signa_clear = "none";
parameter signb_clock = "none";
parameter signb_clear = "none";
parameter round_clock = "none";
parameter round_clear = "none";
parameter roundchainout_clock = "none";
parameter roundchainout_clear = "none";
parameter saturate_clock = "none";
parameter saturate_clear = "none";
parameter saturatechainout_clock = "none";
parameter saturatechainout_clear = "none";
parameter zeroacc_clock = "none";
parameter zeroacc_clear = "none";
parameter zeroloopback_clock = "none";
parameter zeroloopback_clear = "none";
parameter rotate_clock = "none";
parameter rotate_clear = "none";
parameter shiftright_clock = "none";
parameter shiftright_clear = "none";
parameter signa_pipeline_clock = "none";
parameter signa_pipeline_clear = "none";
parameter signb_pipeline_clock = "none";
parameter signb_pipeline_clear = "none";
parameter round_pipeline_clock = "none";
parameter round_pipeline_clear = "none";
parameter roundchainout_pipeline_clock = "none";
parameter roundchainout_pipeline_clear = "none";
parameter saturate_pipeline_clock = "none";
parameter saturate_pipeline_clear = "none";
parameter saturatechainout_pipeline_clock = "none";
parameter saturatechainout_pipeline_clear = "none";
parameter zeroacc_pipeline_clock = "none";
parameter zeroacc_pipeline_clear = "none";
parameter zeroloopback_pipeline_clock = "none";
parameter zeroloopback_pipeline_clear = "none";
parameter rotate_pipeline_clock = "none";
parameter rotate_pipeline_clear = "none";
parameter shiftright_pipeline_clock = "none";
parameter shiftright_pipeline_clear = "none";
parameter roundchainout_output_clock = "none";
parameter roundchainout_output_clear = "none";
parameter saturatechainout_output_clock = "none";
parameter saturatechainout_output_clear = "none";
parameter zerochainout_output_clock = "none";
parameter zerochainout_output_clear = "none";
parameter zeroloopback_output_clock = "none";
parameter zeroloopback_output_clear = "none";
parameter rotate_output_clock = "none";
parameter rotate_output_clear = "none";
parameter shiftright_output_clock = "none";
parameter shiftright_output_clear = "none";
parameter first_adder0_mode = "add";
parameter first_adder1_mode = "add";
parameter acc_adder_operation = "add";
parameter round_mode = "nearest_integer";
parameter round_chain_out_mode = "nearest_integer";
parameter saturate_mode = "asymmetric";
parameter saturate_chain_out_mode = "asymmetric";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter multa_signa_internally_grounded = "false";
parameter multa_signb_internally_grounded = "false";
parameter multb_signa_internally_grounded = "false";
parameter multb_signb_internally_grounded = "false";
parameter multc_signa_internally_grounded = "false";
parameter multc_signb_internally_grounded = "false";
parameter multd_signa_internally_grounded = "false";
parameter multd_signb_internally_grounded = "false";
// SIMULATION_ONLY_PARAMETERS_END
parameter lpm_type = "arriaiigz_mac_out";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = 72;
// SIMULATION_ONLY_PARAMETERS_END
input [dataa_width -1 :0] dataa;
input [datab_width -1 :0] datab;
input [datac_width -1 :0] datac;
input [datad_width -1 :0] datad;
input signa;
input signb;
input [chainin_width -1 : 0] chainin;
input round;
input saturate;
input roundchainout;
input saturatechainout;
input zeroacc;
input zerochainout;
input zeroloopback;
input rotate;
input shiftright;
input [3:0] clk;
input [3:0] aclr;
input [3:0] ena;
input devpor;
input devclrn;
output [17:0] loopbackout;
output [71:0] dataout;
output overflow;
output saturatechainoutoverflow;
output dftout;
tri1 devclrn;
tri1 devpor;
//signals for zeroloopback input register
wire [3:0] zeroloopback_clkval_ir;
wire [3:0] zeroloopback_aclrval_ir;
wire zeroloopback_clk_ir;
wire zeroloopback_aclr_ir;
wire zeroloopback_sload_ir;
wire zeroloopback_bypass_register_ir;
wire zeroloopback_in_reg;
//signals for zeroacc input register
wire [3:0] zeroacc_clkval_ir;
wire [3:0] zeroacc_aclrval_ir;
wire zeroacc_clk_ir;
wire zeroacc_aclr_ir;
wire zeroacc_sload_ir;
wire zeroacc_bypass_register_ir;
wire zeroacc_in_reg;
//Signals for signa input register
wire [3:0] signa_clkval_ir;
wire [3:0] signa_aclrval_ir;
wire signa_clk_ir;
wire signa_aclr_ir;
wire signa_sload_ir;
wire signa_bypass_register_ir;
wire signa_in_reg;
//signals for signb input register
wire [3:0] signb_clkval_ir;
wire [3:0] signb_aclrval_ir;
wire signb_clk_ir;
wire signb_aclr_ir;
wire signb_sload_ir;
wire signb_bypass_register_ir;
wire signb_in_reg;
//signals for rotate input register
wire [3:0] rotate_clkval_ir;
wire [3:0] rotate_aclrval_ir;
wire rotate_clk_ir;
wire rotate_aclr_ir;
wire rotate_sload_ir;
wire rotate_bypass_register_ir;
wire rotate_in_reg;
//signals for shiftright input register
wire [3:0] shiftright_clkval_ir;
wire [3:0] shiftright_aclrval_ir;
wire shiftright_clk_ir;
wire shiftright_aclr_ir;
wire shiftright_sload_ir;
wire shiftright_bypass_register_ir;
wire shiftright_in_reg;
//signals for round input register
wire [3:0] round_clkval_ir;
wire [3:0] round_aclrval_ir;
wire round_clk_ir;
wire round_aclr_ir;
wire round_sload_ir;
wire round_bypass_register_ir;
wire round_in_reg;
//signals for saturate input register
wire [3:0] saturate_clkval_ir;
wire [3:0] saturate_aclrval_ir;
wire saturate_clk_ir;
wire saturate_aclr_ir;
wire saturate_sload_ir;
wire saturate_bypass_register_ir;
wire saturate_in_reg;
//signals for roundchainout input register
wire [3:0] roundchainout_clkval_ir;
wire [3:0] roundchainout_aclrval_ir;
wire roundchainout_clk_ir;
wire roundchainout_aclr_ir;
wire roundchainout_sload_ir;
wire roundchainout_bypass_register_ir;
wire roundchainout_in_reg;
//signals for saturatechainout input register
wire [3:0] saturatechainout_clkval_ir;
wire [3:0] saturatechainout_aclrval_ir;
wire saturatechainout_clk_ir;
wire saturatechainout_aclr_ir;
wire saturatechainout_sload_ir;
wire saturatechainout_bypass_register_ir;
wire saturatechainout_in_reg;
//signals for fsa_input_interface
wire [71:0] dataa_fsa_in;
wire [71:0] datab_fsa_in;
wire [71:0] datac_fsa_in;
wire [71:0] datad_fsa_in;
wire [71:0] chainin_coa_in;
wire sign;
wire [3:0]operation;
//Signals for First Stage Adder units
wire [71:0] dataout_fsa0;
wire [71:0] fsa_pip_datain1;
wire [71:0] dataout_fsa1;
wire overflow_fsa0;
wire overflow_fsa1;
//signals for zeroloopback pipeline register
wire [3:0] zeroloopback_clkval_pip;
wire [3:0] zeroloopback_aclrval_pip;
wire zeroloopback_clk_pip;
wire zeroloopback_aclr_pip;
wire zeroloopback_sload_pip;
wire zeroloopback_bypass_register_pip;
wire zeroloopback_pip_reg;
//signals for zeroacc pipeline register
wire [3:0] zeroacc_clkval_pip;
wire [3:0] zeroacc_aclrval_pip;
wire zeroacc_clk_pip;
wire zeroacc_aclr_pip;
wire zeroacc_sload_pip;
wire zeroacc_bypass_register_pip;
wire zeroacc_pip_reg;
//Signals for signa pipeline register
wire [3:0] signa_clkval_pip;
wire [3:0] signa_aclrval_pip;
wire signa_clk_pip;
wire signa_aclr_pip;
wire signa_sload_pip;
wire signa_bypass_register_pip;
wire signa_pip_reg;
//signals for signb pipeline register
wire [3:0] signb_clkval_pip;
wire [3:0] signb_aclrval_pip;
wire signb_clk_pip;
wire signb_aclr_pip;
wire signb_sload_pip;
wire signb_bypass_register_pip;
wire signb_pip_reg;
//signals for rotate pipeline register
wire [3:0] rotate_clkval_pip;
wire [3:0] rotate_aclrval_pip;
wire rotate_clk_pip;
wire rotate_aclr_pip;
wire rotate_sload_pip;
wire rotate_bypass_register_pip;
wire rotate_pip_reg;
//signals for shiftright pipeline register
wire [3:0] shiftright_clkval_pip;
wire [3:0] shiftright_aclrval_pip;
wire shiftright_clk_pip;
wire shiftright_aclr_pip;
wire shiftright_sload_pip;
wire shiftright_bypass_register_pip;
wire shiftright_pip_reg;
//signals for round pipeline register
wire [3:0] round_clkval_pip;
wire [3:0] round_aclrval_pip;
wire round_clk_pip;
wire round_aclr_pip;
wire round_sload_pip;
wire round_bypass_register_pip;
wire round_pip_reg;
//signals for saturate pipeline register
wire [3:0] saturate_clkval_pip;
wire [3:0] saturate_aclrval_pip;
wire saturate_clk_pip;
wire saturate_aclr_pip;
wire saturate_sload_pip;
wire saturate_bypass_register_pip;
wire saturate_pip_reg;
//signals for roundchainout pipeline register
wire [3:0] roundchainout_clkval_pip;
wire [3:0] roundchainout_aclrval_pip;
wire roundchainout_clk_pip;
wire roundchainout_aclr_pip;
wire roundchainout_sload_pip;
wire roundchainout_bypass_register_pip;
wire roundchainout_pip_reg;
//signals for saturatechainout pipeline register
wire [3:0] saturatechainout_clkval_pip;
wire [3:0] saturatechainout_aclrval_pip;
wire saturatechainout_clk_pip;
wire saturatechainout_aclr_pip;
wire saturatechainout_sload_pip;
wire saturatechainout_bypass_register_pip;
wire saturatechainout_pip_reg;
//signals for fsa0 pipeline register
wire [3:0] fsa0_clkval_pip;
wire [3:0] fsa0_aclrval_pip;
wire fsa0_clk_pip;
wire fsa0_aclr_pip;
wire fsa0_sload_pip;
wire fsa0_bypass_register_pip;
wire[71:0] fsa0_pip_reg;
//signals for fsa1 pipeline register
wire [3:0] fsa1_clkval_pip;
wire [3:0] fsa1_aclrval_pip;
wire fsa1_clk_pip;
wire fsa1_aclr_pip;
wire fsa1_sload_pip;
wire fsa1_bypass_register_pip;
wire[71:0] fsa1_pip_reg;
//Signals for second stage adder
wire [71:0] ssa_accum_in;
wire ssa_sign;
wire [71:0] ssa_dataout;
wire ssa_overflow;
//Signals for RS block
wire[71:0] rs_datain;
wire [71:0] rs_dataout;
reg [71:0] rs_dataout_of;
wire [71:0] rs_dataout_tmp;
wire rs_saturation_overflow;
wire [7:0] ssa_datain_width;
wire [7:0] ssa_datain_width_tmp;
wire [3:0] ssa_round_width;
wire [7:0] ssa_fraction_width;
//signals for zeroloopback output register
wire [3:0] zeroloopback_clkval_or;
wire [3:0] zeroloopback_aclrval_or;
wire zeroloopback_clk_or;
wire zeroloopback_aclr_or;
wire zeroloopback_sload_or;
wire zeroloopback_bypass_register_or;
wire zeroloopback_out_reg;
//signals for zerochainout output register
wire [3:0] zerochainout_clkval_or;
wire [3:0] zerochainout_aclrval_or;
wire zerochainout_clk_or;
wire zerochainout_aclr_or;
wire zerochainout_sload_or;
wire zerochainout_bypass_register_or;
wire zerochainout_out_reg;
//Signals for saturation_overflow output register
wire [3:0] saturation_overflow_clkval_or;
wire [3:0] saturation_overflow_aclrval_or;
wire saturation_overflow_clk_or;
wire saturation_overflow_aclr_or;
wire saturation_overflow_sload_or;
wire saturation_overflow_bypass_register_or;
wire saturation_overflow_out_reg;
//signals for rs_dataout output register
wire [71:0] rs_dataout_in;
wire [3:0] rs_dataout_clkval_or;
wire [3:0] rs_dataout_aclrval_or;
wire [3:0] rs_dataout_clkval_or_co;
wire [3:0] rs_dataout_aclrval_or_co;
wire [3:0] rs_dataout_clkval_or_o;
wire [3:0] rs_dataout_aclrval_or_o;
wire rs_dataout_clk_or;
wire rs_dataout_aclr_or;
wire rs_dataout_sload_or;
wire rs_dataout_bypass_register_or;
wire rs_dataout_bypass_register_or_co;
wire rs_dataout_bypass_register_or_o;
wire[71:0] rs_dataout_out_reg;
wire rs_saturation_overflow_out_reg;
wire rs_saturation_overflow_in;
//signals for rotate output register
wire [3:0] rotate_clkval_or;
wire [3:0] rotate_aclrval_or;
wire rotate_clk_or;
wire rotate_aclr_or;
wire rotate_sload_or;
wire rotate_bypass_register_or;
wire rotate_out_reg;
//signals for shiftright output register
wire [3:0] shiftright_clkval_or;
wire [3:0] shiftright_aclrval_or;
wire shiftright_clk_or;
wire shiftright_aclr_or;
wire shiftright_sload_or;
wire shiftright_bypass_register_or;
wire shiftright_out_reg;
//signals for roundchainout output register
wire [3:0] roundchainout_clkval_or;
wire [3:0] roundchainout_aclrval_or;
wire roundchainout_clk_or;
wire roundchainout_aclr_or;
wire roundchainout_sload_or;
wire roundchainout_bypass_register_or;
wire roundchainout_out_reg;
//signals for saturatechainout output register
wire [3:0] saturatechainout_clkval_or;
wire [3:0] saturatechainout_aclrval_or;
wire saturatechainout_clk_or;
wire saturatechainout_aclr_or;
wire saturatechainout_sload_or;
wire saturatechainout_bypass_register_or;
wire saturatechainout_out_reg;
//Signals for chainout Adder RS Block
wire [71:0] coa_dataout;
wire [7:0] coa_datain_width;
wire [3:0] coa_round_width;
wire [7:0] coa_fraction_width;
wire [71:0] coa_rs_dataout;
wire coa_rs_saturation_overflow;
//signals for control signals for COA output register
wire [3:0] coa_reg_clkval_or;
wire [3:0] coa_reg_aclrval_or;
wire coa_reg_clk_or;
wire coa_reg_aclr_or;
wire coa_reg_sload_or;
wire coa_reg_bypass_register_or;
wire coa_reg_out_reg;
wire coa_rs_saturation_overflow_out_reg;
wire coa_rs_saturationchainout_overflow_out_reg;
wire [71:0] coa_rs_dataout_out_reg;
wire [71:0] dataout_shift_rot ;
reg [5:0] dataa_width_local;
wire [71:0] dataout_tmp;
wire [71:0] loopbackout_tmp;
always@(rs_dataout or rs_saturation_overflow or saturate_pip_reg)
begin
rs_dataout_of = rs_dataout;
rs_dataout_of[dataa_width -1] = (((operation_mode == "output_only")||(operation_mode == "one_level_adder") ||(operation_mode == "loopback"))
&&(dataa_width > 1) && (saturate_pip_reg == 1'b1))? rs_saturation_overflow : rs_dataout[dataa_width -1];
end
//Instantiate the zeroloopback input Register
arriaiigz_mac_register zeroloopback_input_register (
.datain(zeroloopback),
.clk(zeroloopback_clk_ir),
.aclr(zeroloopback_aclr_ir),
.sload(zeroloopback_sload_ir),
.bypass_register(zeroloopback_bypass_register_ir),
.dataout(zeroloopback_in_reg)
);
defparam zeroloopback_input_register.data_width = 1;
//decode the clk and aclr values
assign zeroloopback_clkval_ir = (zeroloopback_clock == "0") ? 4'b0000 :
(zeroloopback_clock == "1") ? 4'b0001 :
(zeroloopback_clock == "2") ? 4'b0010 :
(zeroloopback_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroloopback_aclrval_ir = (zeroloopback_clear == "0") ? 4'b0000 :
(zeroloopback_clear == "1") ? 4'b0001 :
(zeroloopback_clear == "2") ? 4'b0010 :
(zeroloopback_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroloopback_clk_ir = clk[zeroloopback_clkval_ir] ? 1'b1 : 1'b0;
assign zeroloopback_aclr_ir = aclr[zeroloopback_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign zeroloopback_sload_ir = ena[zeroloopback_clkval_ir] ? 1'b1 : 1'b0;
assign zeroloopback_bypass_register_ir = (zeroloopback_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the zeroacc input Register
arriaiigz_mac_register zeroacc_input_register (
.datain(zeroacc),
.clk(zeroacc_clk_ir),
.aclr(zeroacc_aclr_ir),
.sload(zeroacc_sload_ir),
.bypass_register(zeroacc_bypass_register_ir),
.dataout(zeroacc_in_reg)
);
defparam zeroacc_input_register.data_width = 1;
//decode the clk and aclr values
assign zeroacc_clkval_ir =(zeroacc_clock == "0") ? 4'b0000 :
(zeroacc_clock == "1") ? 4'b0001 :
(zeroacc_clock == "2") ? 4'b0010 :
(zeroacc_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroacc_aclrval_ir = (zeroacc_clear == "0") ? 4'b0000 :
(zeroacc_clear == "1") ? 4'b0001 :
(zeroacc_clear == "2") ? 4'b0010 :
(zeroacc_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroacc_clk_ir = clk[zeroacc_clkval_ir] ? 1'b1 : 1'b0;
assign zeroacc_aclr_ir = aclr[zeroacc_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign zeroacc_sload_ir = ena[zeroacc_clkval_ir] ? 1'b1 : 1'b0;
assign zeroacc_bypass_register_ir = (zeroacc_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the signa input Register
arriaiigz_mac_register signa_input_register (
.datain(signa),
.clk(signa_clk_ir),
.aclr(signa_aclr_ir),
.sload(signa_sload_ir),
.bypass_register(signa_bypass_register_ir),
.dataout(signa_in_reg)
);
defparam signa_input_register.data_width = 1;
//decode the clk and aclr values
assign signa_clkval_ir =(signa_clock == "0") ? 4'b0000 :
(signa_clock == "1") ? 4'b0001 :
(signa_clock == "2") ? 4'b0010 :
(signa_clock == "3") ? 4'b0011 : 4'b0000;
assign signa_aclrval_ir = (signa_clear == "0") ? 4'b0000 :
(signa_clear == "1") ? 4'b0001 :
(signa_clear == "2") ? 4'b0010 :
(signa_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signa_clk_ir = clk[signa_clkval_ir] ? 1'b1 : 1'b0;
assign signa_aclr_ir = aclr[signa_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign signa_sload_ir = ena[signa_clkval_ir] ? 1'b1 : 1'b0;
assign signa_bypass_register_ir = (signa_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the signb input Register
arriaiigz_mac_register signb_input_register (
.datain(signb),
.clk(signb_clk_ir),
.aclr(signb_aclr_ir),
.sload(signb_sload_ir),
.bypass_register(signb_bypass_register_ir),
.dataout(signb_in_reg)
);
defparam signb_input_register.data_width = 1;
//decode the clk and aclr values
assign signb_clkval_ir =(signb_clock == "0") ? 4'b0000 :
(signb_clock == "1") ? 4'b0001 :
(signb_clock == "2") ? 4'b0010 :
(signb_clock == "3") ? 4'b0011 : 4'b0000;
assign signb_aclrval_ir = (signb_clear == "0") ? 4'b0000 :
(signb_clear == "1") ? 4'b0001 :
(signb_clear == "2") ? 4'b0010 :
(signb_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signb_clk_ir = clk[signb_clkval_ir] ? 1'b1 : 1'b0;
assign signb_aclr_ir = aclr[signb_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign signb_sload_ir = ena[signb_clkval_ir] ? 1'b1 : 1'b0;
assign signb_bypass_register_ir = (signb_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the rotate input Register
arriaiigz_mac_register rotate_input_register (
.datain(rotate),
.clk(rotate_clk_ir),
.aclr(rotate_aclr_ir),
.sload(rotate_sload_ir),
.bypass_register(rotate_bypass_register_ir),
.dataout(rotate_in_reg)
);
defparam rotate_input_register.data_width = 1;
//decode the clk and aclr values
assign rotate_clkval_ir =(rotate_clock == "0") ? 4'b0000 :
(rotate_clock == "1") ? 4'b0001 :
(rotate_clock == "2") ? 4'b0010 :
(rotate_clock == "3") ? 4'b0011 : 4'b0000;
assign rotate_aclrval_ir = (rotate_clear == "0") ? 4'b0000 :
(rotate_clear == "1") ? 4'b0001 :
(rotate_clear == "2") ? 4'b0010 :
(rotate_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign rotate_clk_ir = clk[rotate_clkval_ir] ? 1'b1 : 1'b0;
assign rotate_aclr_ir = aclr[rotate_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign rotate_sload_ir = ena[rotate_clkval_ir] ? 1'b1 : 1'b0;
assign rotate_bypass_register_ir = (rotate_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the shiftright input Register
arriaiigz_mac_register shiftright_input_register (
.datain(shiftright),
.clk(shiftright_clk_ir),
.aclr(shiftright_aclr_ir),
.sload(shiftright_sload_ir),
.bypass_register(shiftright_bypass_register_ir),
.dataout(shiftright_in_reg)
);
defparam shiftright_input_register.data_width = 1;
//decode the clk and aclr values
assign shiftright_clkval_ir =(shiftright_clock == "0") ? 4'b0000 :
(shiftright_clock == "1") ? 4'b0001 :
(shiftright_clock == "2") ? 4'b0010 :
(shiftright_clock == "3") ? 4'b0011 : 4'b0000;
assign shiftright_aclrval_ir = (shiftright_clear == "0") ? 4'b0000 :
(shiftright_clear == "1") ? 4'b0001 :
(shiftright_clear == "2") ? 4'b0010 :
(shiftright_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign shiftright_clk_ir = clk[shiftright_clkval_ir] ? 1'b1 : 1'b0;
assign shiftright_aclr_ir = aclr[shiftright_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign shiftright_sload_ir = ena[shiftright_clkval_ir] ? 1'b1 : 1'b0;
assign shiftright_bypass_register_ir = (shiftright_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the round input Register
arriaiigz_mac_register round_input_register (
.datain(round),
.clk(round_clk_ir),
.aclr(round_aclr_ir),
.sload(round_sload_ir),
.bypass_register(round_bypass_register_ir),
.dataout(round_in_reg)
);
defparam round_input_register.data_width = 1;
//decode the clk and aclr values
assign round_clkval_ir =(round_clock == "0") ? 4'b0000 :
(round_clock == "1") ? 4'b0001 :
(round_clock == "2") ? 4'b0010 :
(round_clock == "3") ? 4'b0011 : 4'b0000;
assign round_aclrval_ir = (round_clear == "0") ? 4'b0000 :
(round_clear == "1") ? 4'b0001 :
(round_clear == "2") ? 4'b0010 :
(round_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign round_clk_ir = clk[round_clkval_ir] ? 1'b1 : 1'b0;
assign round_aclr_ir = aclr[round_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign round_sload_ir = ena[round_clkval_ir] ? 1'b1 : 1'b0;
assign round_bypass_register_ir = (round_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the saturate input Register
arriaiigz_mac_register saturate_input_register (
.datain(saturate),
.clk(saturate_clk_ir),
.aclr(saturate_aclr_ir),
.sload(saturate_sload_ir),
.bypass_register(saturate_bypass_register_ir),
.dataout(saturate_in_reg)
);
defparam saturate_input_register.data_width = 1;
//decode the clk and aclr values
assign saturate_clkval_ir =(saturate_clock == "0") ? 4'b0000 :
(saturate_clock == "1") ? 4'b0001 :
(saturate_clock == "2") ? 4'b0010 :
(saturate_clock == "3") ? 4'b0011 : 4'b0000;
assign saturate_aclrval_ir = (saturate_clear == "0") ? 4'b0000 :
(saturate_clear == "1") ? 4'b0001 :
(saturate_clear == "2") ? 4'b0010 :
(saturate_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturate_clk_ir = clk[saturate_clkval_ir] ? 1'b1 : 1'b0;
assign saturate_aclr_ir = aclr[saturate_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign saturate_sload_ir = ena[saturate_clkval_ir] ? 1'b1 : 1'b0;
assign saturate_bypass_register_ir = (saturate_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the roundchainout input Register
arriaiigz_mac_register roundchainout_input_register (
.datain(roundchainout),
.clk(roundchainout_clk_ir),
.aclr(roundchainout_aclr_ir),
.sload(roundchainout_sload_ir),
.bypass_register(roundchainout_bypass_register_ir),
.dataout(roundchainout_in_reg)
);
defparam roundchainout_input_register.data_width = 1;
//decode the clk and aclr values
assign roundchainout_clkval_ir =(roundchainout_clock == "0") ? 4'b0000 :
(roundchainout_clock == "1") ? 4'b0001 :
(roundchainout_clock == "2") ? 4'b0010 :
(roundchainout_clock == "3") ? 4'b0011 : 4'b0000;
assign roundchainout_aclrval_ir = (roundchainout_clear == "0") ? 4'b0000 :
(roundchainout_clear == "1") ? 4'b0001 :
(roundchainout_clear == "2") ? 4'b0010 :
(roundchainout_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign roundchainout_clk_ir = clk[roundchainout_clkval_ir] ? 1'b1 : 1'b0;
assign roundchainout_aclr_ir = aclr[roundchainout_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign roundchainout_sload_ir = ena[roundchainout_clkval_ir] ? 1'b1 : 1'b0;
assign roundchainout_bypass_register_ir = (roundchainout_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the saturatechainout input Register
arriaiigz_mac_register saturatechainout_input_register (
.datain(saturatechainout),
.clk(saturatechainout_clk_ir),
.aclr(saturatechainout_aclr_ir),
.sload(saturatechainout_sload_ir),
.bypass_register(saturatechainout_bypass_register_ir),
.dataout(saturatechainout_in_reg)
);
defparam saturatechainout_input_register.data_width = 1;
//decode the clk and aclr values
assign saturatechainout_clkval_ir =(saturatechainout_clock == "0") ? 4'b0000 :
(saturatechainout_clock == "1") ? 4'b0001 :
(saturatechainout_clock == "2") ? 4'b0010 :
(saturatechainout_clock == "3") ? 4'b0011 : 4'b0000;
assign saturatechainout_aclrval_ir =(saturatechainout_clear == "0") ? 4'b0000 :
(saturatechainout_clear == "1") ? 4'b0001 :
(saturatechainout_clear == "2") ? 4'b0010 :
(saturatechainout_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturatechainout_clk_ir = clk[saturatechainout_clkval_ir] ? 1'b1 : 1'b0;
assign saturatechainout_aclr_ir = aclr[saturatechainout_aclrval_ir] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign saturatechainout_sload_ir = ena[saturatechainout_clkval_ir] ? 1'b1 : 1'b0;
assign saturatechainout_bypass_register_ir = (saturatechainout_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the First level adder interface and sign extension block
arriaiigz_fsa_isse fsa_interface(
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.chainin(chainin),
.signa(signa_in_reg),
.signb(signb_in_reg),
.dataa_out(dataa_fsa_in),
.datab_out(datab_fsa_in),
.datac_out(datac_fsa_in),
.datad_out(datad_fsa_in),
.chainin_out(chainin_coa_in),
.operation(operation)
);
defparam fsa_interface.dataa_width = dataa_width;
defparam fsa_interface.datab_width = datab_width;
defparam fsa_interface.datac_width = datac_width;
defparam fsa_interface.datad_width = datad_width;
defparam fsa_interface.chainin_width = chainin_width;
defparam fsa_interface.operation_mode = operation_mode;
defparam fsa_interface.multa_signa_internally_grounded = multa_signa_internally_grounded;
defparam fsa_interface.multa_signb_internally_grounded = multa_signb_internally_grounded;
defparam fsa_interface.multb_signa_internally_grounded = multb_signa_internally_grounded;
defparam fsa_interface.multb_signb_internally_grounded = multb_signb_internally_grounded;
defparam fsa_interface.multc_signa_internally_grounded = multc_signa_internally_grounded;
defparam fsa_interface.multc_signb_internally_grounded = multc_signb_internally_grounded;
defparam fsa_interface.multd_signa_internally_grounded = multd_signa_internally_grounded;
defparam fsa_interface.multd_signb_internally_grounded = multd_signb_internally_grounded;
assign sign = signa_in_reg | signb_in_reg;
//Instantiate First Stage Adder/Subtractor Unit0
arriaiigz_first_stage_add_sub fsaunit0(
.dataa(dataa_fsa_in),
.datab(datab_fsa_in),
.sign(sign),
.operation(operation),
.dataout(dataout_fsa0)
);
defparam fsaunit0.dataa_width = dataa_width;
defparam fsaunit0.datab_width = datab_width;
defparam fsaunit0.fsa_mode = first_adder0_mode;
//Instantiate First Stage Adder/Subtractor Unit1
arriaiigz_first_stage_add_sub fsaunit1(
.dataa(datac_fsa_in),
.datab(datad_fsa_in),
.sign(sign),
.operation(operation),
.dataout(dataout_fsa1)
);
defparam fsaunit1.dataa_width = datac_width;
defparam fsaunit1.datab_width = datad_width;
defparam fsaunit1.fsa_mode = first_adder1_mode;
//Instantiate the zeroloopback pipeline Register
arriaiigz_mac_register zeroloopback_pipeline_register (
.datain(zeroloopback_in_reg),
.clk(zeroloopback_clk_pip),
.aclr(zeroloopback_aclr_pip),
.sload(zeroloopback_sload_pip),
.bypass_register(zeroloopback_bypass_register_pip),
.dataout(zeroloopback_pip_reg)
);
defparam zeroloopback_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign zeroloopback_clkval_pip =(zeroloopback_pipeline_clock == "0") ? 4'b0000 :
(zeroloopback_pipeline_clock == "1") ? 4'b0001 :
(zeroloopback_pipeline_clock == "2") ? 4'b0010 :
(zeroloopback_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroloopback_aclrval_pip = (zeroloopback_pipeline_clear == "0") ? 4'b0000 :
(zeroloopback_pipeline_clear == "1") ? 4'b0001 :
(zeroloopback_pipeline_clear == "2") ? 4'b0010 :
(zeroloopback_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroloopback_clk_pip = clk[zeroloopback_clkval_pip] ? 1'b1 : 1'b0;
assign zeroloopback_aclr_pip = aclr[zeroloopback_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign zeroloopback_sload_pip = ena[zeroloopback_clkval_pip] ? 1'b1 : 1'b0;
assign zeroloopback_bypass_register_pip = (zeroloopback_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the zeroacc pipeline Register
arriaiigz_mac_register zeroacc_pipeline_register (
.datain(zeroacc_in_reg),
.clk(zeroacc_clk_pip),
.aclr(zeroacc_aclr_pip),
.sload(zeroacc_sload_pip),
.bypass_register(zeroacc_bypass_register_pip),
.dataout(zeroacc_pip_reg)
);
defparam zeroacc_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign zeroacc_clkval_pip =(zeroacc_pipeline_clock == "0") ? 4'b0000 :
(zeroacc_pipeline_clock == "1") ? 4'b0001 :
(zeroacc_pipeline_clock == "2") ? 4'b0010 :
(zeroacc_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroacc_aclrval_pip = (zeroacc_pipeline_clear == "0") ? 4'b0000 :
(zeroacc_pipeline_clear == "1") ? 4'b0001 :
(zeroacc_pipeline_clear == "2") ? 4'b0010 :
(zeroacc_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroacc_clk_pip = clk[zeroacc_clkval_pip] ? 1'b1 : 1'b0;
assign zeroacc_aclr_pip = aclr[zeroacc_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign zeroacc_sload_pip = ena[zeroacc_clkval_pip] ? 1'b1 : 1'b0;
assign zeroacc_bypass_register_pip = (zeroacc_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the signa pipeline Register
arriaiigz_mac_register signa_pipeline_register (
.datain(signa_in_reg),
.clk(signa_clk_pip),
.aclr(signa_aclr_pip),
.sload(signa_sload_pip),
.bypass_register(signa_bypass_register_pip),
.dataout(signa_pip_reg)
);
defparam signa_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign signa_clkval_pip =(signa_pipeline_clock == "0") ? 4'b0000 :
(signa_pipeline_clock == "1") ? 4'b0001 :
(signa_pipeline_clock == "2") ? 4'b0010 :
(signa_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign signa_aclrval_pip = (signa_pipeline_clear == "0") ? 4'b0000 :
(signa_pipeline_clear == "1") ? 4'b0001 :
(signa_pipeline_clear == "2") ? 4'b0010 :
(signa_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signa_clk_pip = clk[signa_clkval_pip] ? 1'b1 : 1'b0;
assign signa_aclr_pip = aclr[signa_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign signa_sload_pip = ena[signa_clkval_pip] ? 1'b1 : 1'b0;
assign signa_bypass_register_pip = (signa_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the signb pipeline Register
arriaiigz_mac_register signb_pipeline_register (
.datain(signb_in_reg),
.clk(signb_clk_pip),
.aclr(signb_aclr_pip),
.sload(signb_sload_pip),
.bypass_register(signb_bypass_register_pip),
.dataout(signb_pip_reg)
);
defparam signb_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign signb_clkval_pip = (signb_pipeline_clock == "0") ? 4'b0000 :
(signb_pipeline_clock == "1") ? 4'b0001 :
(signb_pipeline_clock == "2") ? 4'b0010 :
(signb_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign signb_aclrval_pip = (signb_pipeline_clear == "0") ? 4'b0000 :
(signb_pipeline_clear == "1") ? 4'b0001 :
(signb_pipeline_clear == "2") ? 4'b0010 :
(signb_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign signb_clk_pip = clk[signb_clkval_pip] ? 1'b1 : 1'b0;
assign signb_aclr_pip = aclr[signb_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign signb_sload_pip = ena[signb_clkval_pip] ? 1'b1 : 1'b0;
assign signb_bypass_register_pip = (signb_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the rotate pipeline Register
arriaiigz_mac_register rotate_pipeline_register (
.datain(rotate_in_reg),
.clk(rotate_clk_pip),
.aclr(rotate_aclr_pip),
.sload(rotate_sload_pip),
.bypass_register(rotate_bypass_register_pip),
.dataout(rotate_pip_reg)
);
defparam rotate_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign rotate_clkval_pip =(rotate_pipeline_clock == "0") ? 4'b0000 :
(rotate_pipeline_clock == "1") ? 4'b0001 :
(rotate_pipeline_clock == "2") ? 4'b0010 :
(rotate_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign rotate_aclrval_pip =(rotate_pipeline_clear == "0") ? 4'b0000 :
(rotate_pipeline_clear == "1") ? 4'b0001 :
(rotate_pipeline_clear == "2") ? 4'b0010 :
(rotate_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign rotate_clk_pip = clk[rotate_clkval_pip] ? 1'b1 : 1'b0;
assign rotate_aclr_pip = aclr[rotate_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign rotate_sload_pip = ena[rotate_clkval_pip] ? 1'b1 : 1'b0;
assign rotate_bypass_register_pip = (rotate_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the shiftright pipeline Register
arriaiigz_mac_register shiftright_pipeline_register (
.datain(shiftright_in_reg),
.clk(shiftright_clk_pip),
.aclr(shiftright_aclr_pip),
.sload(shiftright_sload_pip),
.bypass_register(shiftright_bypass_register_pip),
.dataout(shiftright_pip_reg)
);
defparam shiftright_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign shiftright_clkval_pip =(shiftright_pipeline_clock == "0") ? 4'b0000 :
(shiftright_pipeline_clock == "1") ? 4'b0001 :
(shiftright_pipeline_clock == "2") ? 4'b0010 :
(shiftright_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign shiftright_aclrval_pip = (shiftright_pipeline_clear == "0") ? 4'b0000 :
(shiftright_pipeline_clear == "1") ? 4'b0001 :
(shiftright_pipeline_clear == "2") ? 4'b0010 :
(shiftright_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign shiftright_clk_pip = clk[shiftright_clkval_pip] ? 1'b1 : 1'b0;
assign shiftright_aclr_pip = aclr[shiftright_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign shiftright_sload_pip = ena[shiftright_clkval_pip] ? 1'b1 : 1'b0;
assign shiftright_bypass_register_pip = (shiftright_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the round pipeline Register
arriaiigz_mac_register round_pipeline_register (
.datain(round_in_reg),
.clk(round_clk_pip),
.aclr(round_aclr_pip),
.sload(round_sload_pip),
.bypass_register(round_bypass_register_pip),
.dataout(round_pip_reg)
);
defparam round_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign round_clkval_pip = (round_pipeline_clock == "0") ? 4'b0000 :
(round_pipeline_clock == "1") ? 4'b0001 :
(round_pipeline_clock == "2") ? 4'b0010 :
(round_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign round_aclrval_pip = (round_pipeline_clear == "0") ? 4'b0000 :
(round_pipeline_clear == "1") ? 4'b0001 :
(round_pipeline_clear == "2") ? 4'b0010 :
(round_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign round_clk_pip = clk[round_clkval_pip] ? 1'b1 : 1'b0;
assign round_aclr_pip = aclr[round_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign round_sload_pip = ena[round_clkval_pip] ? 1'b1 : 1'b0;
assign round_bypass_register_pip = (round_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the saturate pipeline Register
arriaiigz_mac_register saturate_pipeline_register (
.datain(saturate_in_reg),
.clk(saturate_clk_pip),
.aclr(saturate_aclr_pip),
.sload(saturate_sload_pip),
.bypass_register(saturate_bypass_register_pip),
.dataout(saturate_pip_reg)
);
defparam saturate_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign saturate_clkval_pip =(saturate_pipeline_clock == "0") ? 4'b0000 :
(saturate_pipeline_clock == "1") ? 4'b0001 :
(saturate_pipeline_clock == "2") ? 4'b0010 :
(saturate_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign saturate_aclrval_pip = (saturate_pipeline_clear == "0") ? 4'b0000 :
(saturate_pipeline_clear == "1") ? 4'b0001 :
(saturate_pipeline_clear == "2") ? 4'b0010 :
(saturate_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturate_clk_pip = clk[saturate_clkval_pip] ? 1'b1 : 1'b0;
assign saturate_aclr_pip = aclr[saturate_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign saturate_sload_pip = ena[saturate_clkval_pip] ? 1'b1 : 1'b0;
assign saturate_bypass_register_pip = (saturate_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the roundchainout pipeline Register
arriaiigz_mac_register roundchainout_pipeline_register (
.datain(roundchainout_in_reg),
.clk(roundchainout_clk_pip),
.aclr(roundchainout_aclr_pip),
.sload(roundchainout_sload_pip),
.bypass_register(roundchainout_bypass_register_pip),
.dataout(roundchainout_pip_reg)
);
defparam roundchainout_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign roundchainout_clkval_pip = (roundchainout_pipeline_clock == "0") ? 4'b0000 :
(roundchainout_pipeline_clock == "1") ? 4'b0001 :
(roundchainout_pipeline_clock == "2") ? 4'b0010 :
(roundchainout_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign roundchainout_aclrval_pip = (roundchainout_pipeline_clear == "0") ? 4'b0000 :
(roundchainout_pipeline_clear == "1") ? 4'b0001 :
(roundchainout_pipeline_clear == "2") ? 4'b0010 :
(roundchainout_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign roundchainout_clk_pip = clk[roundchainout_clkval_pip] ? 1'b1 : 1'b0;
assign roundchainout_aclr_pip = aclr[roundchainout_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign roundchainout_sload_pip = ena[roundchainout_clkval_pip] ? 1'b1 : 1'b0;
assign roundchainout_bypass_register_pip = (roundchainout_pipeline_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the saturatechainout pipeline Register
arriaiigz_mac_register saturatechainout_pipeline_register (
.datain(saturatechainout_in_reg),
.clk(saturatechainout_clk_pip),
.aclr(saturatechainout_aclr_pip),
.sload(saturatechainout_sload_pip),
.bypass_register(saturatechainout_bypass_register_pip),
.dataout(saturatechainout_pip_reg)
);
defparam saturatechainout_pipeline_register.data_width = 1;
//decode the clk and aclr values
assign saturatechainout_clkval_pip =(saturatechainout_pipeline_clock == "0") ? 4'b0000 :
(saturatechainout_pipeline_clock == "1") ? 4'b0001 :
(saturatechainout_pipeline_clock == "2") ? 4'b0010 :
(saturatechainout_pipeline_clock == "3") ? 4'b0011 : 4'b0000;
assign saturatechainout_aclrval_pip = (saturatechainout_pipeline_clear == "0") ? 4'b0000 :
(saturatechainout_pipeline_clear == "1") ? 4'b0001 :
(saturatechainout_pipeline_clear == "2") ? 4'b0010 :
(saturatechainout_pipeline_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturatechainout_clk_pip = clk[saturatechainout_clkval_pip] ? 1'b1 : 1'b0;
assign saturatechainout_aclr_pip = aclr[saturatechainout_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign saturatechainout_sload_pip = ena[saturatechainout_clkval_pip] ? 1'b1 : 1'b0;
assign saturatechainout_bypass_register_pip = (saturatechainout_pipeline_clock == "none") ? 1'b1 : 1'b0;
// Instantiate fsa0 dataout pipline register
arriaiigz_mac_register fsa0_pipeline_register (
.datain(fsa_pip_datain1),
.clk(fsa0_clk_pip),
.aclr(fsa0_aclr_pip),
.sload(fsa0_sload_pip),
.bypass_register(fsa0_bypass_register_pip),
.dataout(fsa0_pip_reg)
);
defparam fsa0_pipeline_register.data_width = 72;
assign fsa_pip_datain1 = (operation_mode == "output_only") ? dataa_fsa_in : dataout_fsa0;
//decode the clk and aclr values
assign fsa0_clkval_pip =(first_adder0_clock == "0") ? 4'b0000 :
(first_adder0_clock == "1") ? 4'b0001 :
(first_adder0_clock == "2") ? 4'b0010 :
(first_adder0_clock == "3") ? 4'b0011 : 4'b0000;
assign fsa0_aclrval_pip = (first_adder0_clear == "0") ? 4'b0000 :
(first_adder0_clear == "1") ? 4'b0001 :
(first_adder0_clear == "2") ? 4'b0010 :
(first_adder0_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign fsa0_clk_pip = clk[fsa0_clkval_pip] ? 1'b1 : 1'b0;
assign fsa0_aclr_pip = aclr[fsa0_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign fsa0_sload_pip = ena[fsa0_clkval_pip] ? 1'b1 : 1'b0;
assign fsa0_bypass_register_pip = (first_adder0_clock == "none") ? 1'b1 : 1'b0;
// Instantiate fsa1 dataout pipline register
arriaiigz_mac_register fsa1_pipeline_register (
.datain(dataout_fsa1),
.clk(fsa1_clk_pip),
.aclr(fsa1_aclr_pip),
.sload(fsa1_sload_pip),
.bypass_register(fsa1_bypass_register_pip),
.dataout(fsa1_pip_reg)
);
defparam fsa1_pipeline_register.data_width = 72;
//decode the clk and aclr values
assign fsa1_clkval_pip =(first_adder1_clock == "0") ? 4'b0000 :
(first_adder1_clock == "1") ? 4'b0001 :
(first_adder1_clock == "2") ? 4'b0010 :
(first_adder1_clock == "3") ? 4'b0011 : 4'b0000;
assign fsa1_aclrval_pip = (first_adder1_clear == "0") ? 4'b0000 :
(first_adder1_clear == "1") ? 4'b0001 :
(first_adder1_clear == "2") ? 4'b0010 :
(first_adder1_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign fsa1_clk_pip = clk[fsa1_clkval_pip] ? 1'b1 : 1'b0;
assign fsa1_aclr_pip = aclr[fsa1_aclrval_pip] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign fsa1_sload_pip = ena[fsa1_clkval_pip] ? 1'b1 : 1'b0;
assign fsa1_bypass_register_pip = (first_adder1_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the second level adder/accumulator block
arriaiigz_second_stage_add_accum ssa_unit(
.dataa(fsa0_pip_reg),
.datab(fsa1_pip_reg),
.accumin(ssa_accum_in),
.sign(ssa_sign),
.operation(operation),
.dataout(ssa_dataout),
.overflow(ssa_overflow)
);
defparam ssa_unit.dataa_width = dataa_width +1;
defparam ssa_unit.datab_width = datac_width + 1;
defparam ssa_unit.accum_width = dataa_width + 8;
defparam ssa_unit.ssa_mode = acc_adder_operation;
assign ssa_accum_in = (!zeroacc_pip_reg) ? rs_dataout_out_reg : 0;
assign ssa_sign = signa_pip_reg | signb_pip_reg;
// Instantiate round and saturation block
arriaiigz_round_saturate_block rs_block(
.datain(rs_datain),
.round(round_pip_reg),
.saturate(saturate_pip_reg),
.signa(signa_pip_reg),
.signb(signb_pip_reg),
.datain_width(ssa_datain_width),
.dataout(rs_dataout),
.saturationoverflow(rs_saturation_overflow)
);
defparam rs_block.dataa_width = dataa_width;
defparam rs_block.datab_width = datab_width;
defparam rs_block.saturate_width = saturate_width;
defparam rs_block.round_width = round_width;
defparam rs_block.saturate_mode = saturate_mode;
defparam rs_block.round_mode = round_mode;
defparam rs_block.operation_mode = operation_mode;
assign rs_datain = ((operation_mode == "output_only") ||
(operation_mode == "one_level_adder")||
(operation_mode == "loopback")) ? fsa0_pip_reg :ssa_dataout ;
assign ssa_datain_width_tmp = (((operation_mode == "accumulator")||(operation_mode == "accumulator_chain_out")||(operation_mode == "two_level_adder_chain_out")) ? (dataa_width[7:0] + 4'h8) :
(operation_mode == "two_level_adder") ? (dataa_width[7:0] + 4'h2) :
((operation_mode == "shift" ) || (operation_mode == "36_bit_multiply" )) ? (dataa_width[7:0] + datab_width[7:0]):
((operation_mode == "double" )) ? (dataa_width[7:0] + 4'h8) : dataa_width[7:0]);
assign ssa_datain_width = (ssa_datain_width_tmp >= round_width) ? ssa_datain_width_tmp : round_width[7:0];
//Instantiate the zeroloopback output Register
arriaiigz_mac_register zeroloopback_output_register (
.datain(zeroloopback_pip_reg),
.clk(zeroloopback_clk_or),
.aclr(zeroloopback_aclr_or),
.sload(zeroloopback_sload_or),
.bypass_register(zeroloopback_bypass_register_or),
.dataout(zeroloopback_out_reg)
);
defparam zeroloopback_output_register.data_width = 1;
//decode the clk and aclr values
assign zeroloopback_clkval_or =(zeroloopback_output_clock == "0") ? 4'b0000 :
(zeroloopback_output_clock == "1") ? 4'b0001 :
(zeroloopback_output_clock == "2") ? 4'b0010 :
(zeroloopback_output_clock == "3") ? 4'b0011 : 4'b0000;
assign zeroloopback_aclrval_or =(zeroloopback_output_clear == "0") ? 4'b0000 :
(zeroloopback_output_clear == "1") ? 4'b0001 :
(zeroloopback_output_clear == "2") ? 4'b0010 :
(zeroloopback_output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zeroloopback_clk_or = clk[zeroloopback_clkval_or] ? 1'b1 : 1'b0;
assign zeroloopback_aclr_or = aclr[zeroloopback_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign zeroloopback_sload_or = ena[zeroloopback_clkval_or] ? 1'b1 : 1'b0;
assign zeroloopback_bypass_register_or = (zeroloopback_output_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the zerochainout output Register
arriaiigz_mac_register zerochainout_output_register (
.datain(zerochainout),
.clk(zerochainout_clk_or),
.aclr(zerochainout_aclr_or),
.sload(zerochainout_sload_or),
.bypass_register(zerochainout_bypass_register_or),
.dataout(zerochainout_out_reg)
);
defparam zerochainout_output_register.data_width = 1;
//decode the clk and aclr values
assign zerochainout_clkval_or =(zerochainout_output_clock == "0") ? 4'b0000 :
(zerochainout_output_clock == "1") ? 4'b0001 :
(zerochainout_output_clock == "2") ? 4'b0010 :
(zerochainout_output_clock == "3") ? 4'b0011 : 4'b0000;
assign zerochainout_aclrval_or =(zerochainout_output_clear == "0") ? 4'b0000 :
(zerochainout_output_clear == "1") ? 4'b0001 :
(zerochainout_output_clear == "2") ? 4'b0010 :
(zerochainout_output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign zerochainout_clk_or = clk[zerochainout_clkval_or] ? 1'b1 : 1'b0;
assign zerochainout_aclr_or = aclr[zerochainout_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign zerochainout_sload_or = ena[zerochainout_clkval_or] ? 1'b1 : 1'b0;
assign zerochainout_bypass_register_or = (zerochainout_output_clock == "none") ? 1'b1 : 1'b0;
// Instantiate Round_Saturate dataout output register
arriaiigz_mac_register rs_dataout_output_register (
.datain(rs_dataout_in),
.clk(rs_dataout_clk_or),
.aclr(rs_dataout_aclr_or),
.sload(rs_dataout_sload_or),
.bypass_register(rs_dataout_bypass_register_or),
.dataout(rs_dataout_out_reg)
);
defparam rs_dataout_output_register.data_width = 72;
assign rs_dataout_in = ((operation_mode == "36_bit_multiply" )||(operation_mode == "shift")) ?
ssa_dataout : rs_dataout_of;
// Instantiate Round_Saturate saturation_overflow output register
arriaiigz_mac_register rs_saturation_overflow_output_register (
.datain(rs_saturation_overflow_in),
.clk(rs_dataout_clk_or),
.aclr(rs_dataout_aclr_or),
.sload(rs_dataout_sload_or),
.bypass_register(rs_dataout_bypass_register_or),
.dataout(rs_saturation_overflow_out_reg)
);
defparam rs_saturation_overflow_output_register.data_width = 1;
// rs_dataout and the saturation_overflow uses the same control signals "second_adder_clock/clear" in chainout mode else output_clock/clear
//decode the clk and aclr values
assign rs_saturation_overflow_in = (saturate_pip_reg == 1'b1) ? rs_saturation_overflow : ssa_overflow;
assign rs_dataout_clkval_or_co = (second_adder_clock == "0") ? 4'b0000 :
(second_adder_clock == "1") ? 4'b0001 :
(second_adder_clock == "2") ? 4'b0010 :
(second_adder_clock == "3") ? 4'b0011 : 4'b0000;
assign rs_dataout_aclrval_or_co = (second_adder_clear == "0") ? 4'b0000 :
(second_adder_clear == "1") ? 4'b0001 :
(second_adder_clear == "2") ? 4'b0010 :
(second_adder_clear == "3") ? 4'b0011 : 4'b0000;
assign rs_dataout_clkval_or_o = (output_clock == "0") ? 4'b0000 :
(output_clock == "1") ? 4'b0001 :
(output_clock == "2") ? 4'b0010 :
(output_clock == "3") ? 4'b0011 : 4'b0000;
assign rs_dataout_aclrval_or_o = (output_clear == "0") ? 4'b0000 :
(output_clear == "1") ? 4'b0001 :
(output_clear == "2") ? 4'b0010 :
(output_clear == "3") ? 4'b0011 : 4'b0000;
assign rs_dataout_clkval_or = ((operation_mode == "two_level_adder_chain_out") || (operation_mode == "accumulator_chain_out" )) ? rs_dataout_clkval_or_co : rs_dataout_clkval_or_o;
assign rs_dataout_aclrval_or = ((operation_mode == "two_level_adder_chain_out") || (operation_mode == "accumulator_chain_out" )) ? rs_dataout_aclrval_or_co : rs_dataout_aclrval_or_o;
//assign the corresponding clk,aclr,enable and bypass register values.
assign rs_dataout_clk_or = clk[rs_dataout_clkval_or] ? 1'b1 : 1'b0;
assign rs_dataout_aclr_or = aclr[rs_dataout_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign rs_dataout_sload_or = ena[rs_dataout_clkval_or] ? 1'b1 : 1'b0;
assign rs_dataout_bypass_register_or_co = (second_adder_clock == "none") ? 1'b1 : 1'b0;
assign rs_dataout_bypass_register_or_o = (output_clock == "none") ? 1'b1 : 1'b0;
assign rs_dataout_bypass_register_or = ((operation_mode == "two_level_adder_chain_out") || (operation_mode == "accumulator_chain_out" )) ? rs_dataout_bypass_register_or_co : rs_dataout_bypass_register_or_o;
//Instantiate the rotate output Register
arriaiigz_mac_register rotate_output_register (
.datain(rotate_pip_reg),
.clk(rotate_clk_or),
.aclr(rotate_aclr_or),
.sload(rotate_sload_or),
.bypass_register(rotate_bypass_register_or),
.dataout(rotate_out_reg)
);
defparam rotate_output_register.data_width = 1;
//decode the clk and aclr values
assign rotate_clkval_or = (rotate_output_clock == "0") ? 4'b0000 :
(rotate_output_clock == "1") ? 4'b0001 :
(rotate_output_clock == "2") ? 4'b0010 :
(rotate_output_clock == "3") ? 4'b0011 : 4'b0000;
assign rotate_aclrval_or = (rotate_output_clear == "0") ? 4'b0000 :
(rotate_output_clear == "1") ? 4'b0001 :
(rotate_output_clear == "2") ? 4'b0010 :
(rotate_output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign rotate_clk_or = clk[rotate_clkval_or] ? 1'b1 : 1'b0;
assign rotate_aclr_or = aclr[rotate_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign rotate_sload_or = ena[rotate_clkval_or] ? 1'b1 : 1'b0;
assign rotate_bypass_register_or = (rotate_output_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the shiftright output Register
arriaiigz_mac_register shiftright_output_register (
.datain(shiftright_pip_reg),
.clk(shiftright_clk_or),
.aclr(shiftright_aclr_or),
.sload(shiftright_sload_or),
.bypass_register(shiftright_bypass_register_or),
.dataout(shiftright_out_reg)
);
defparam shiftright_output_register.data_width = 1;
//decode the clk and aclr values
assign shiftright_clkval_or = (shiftright_output_clock == "0") ? 4'b0000 :
(shiftright_output_clock == "1") ? 4'b0001 :
(shiftright_output_clock == "2") ? 4'b0010 :
(shiftright_output_clock == "3") ? 4'b0011 : 4'b0000;
assign shiftright_aclrval_or = (shiftright_output_clear == "0") ? 4'b0000 :
(shiftright_output_clear == "1") ? 4'b0001 :
(shiftright_output_clear == "2") ? 4'b0010 :
(shiftright_output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign shiftright_clk_or = clk[shiftright_clkval_or] ? 1'b1 : 1'b0;
assign shiftright_aclr_or = aclr[shiftright_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign shiftright_sload_or = ena[shiftright_clkval_or] ? 1'b1 : 1'b0;
assign shiftright_bypass_register_or = (shiftright_output_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the roundchainout output Register
arriaiigz_mac_register roundchainout_output_register (
.datain(roundchainout_pip_reg),
.clk(roundchainout_clk_or),
.aclr(roundchainout_aclr_or),
.sload(roundchainout_sload_or),
.bypass_register(roundchainout_bypass_register_or),
.dataout(roundchainout_out_reg)
);
defparam roundchainout_output_register.data_width = 1;
//decode the clk and aclr values
assign roundchainout_clkval_or =(roundchainout_output_clock == "0") ? 4'b0000 :
(roundchainout_output_clock == "1") ? 4'b0001 :
(roundchainout_output_clock == "2") ? 4'b0010 :
(roundchainout_output_clock == "3") ? 4'b0011 : 4'b0000;
assign roundchainout_aclrval_or = (roundchainout_output_clear == "0") ? 4'b0000 :
(roundchainout_output_clear == "1") ? 4'b0001 :
(roundchainout_output_clear == "2") ? 4'b0010 :
(roundchainout_output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign roundchainout_clk_or = clk[roundchainout_clkval_or] ? 1'b1 : 1'b0;
assign roundchainout_aclr_or = aclr[roundchainout_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign roundchainout_sload_or = ena[roundchainout_clkval_or] ? 1'b1 : 1'b0;
assign roundchainout_bypass_register_or = (roundchainout_output_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the saturatechainout output Register
arriaiigz_mac_register saturatechainout_output_register (
.datain(saturatechainout_pip_reg),
.clk(saturatechainout_clk_or),
.aclr(saturatechainout_aclr_or),
.sload(saturatechainout_sload_or),
.bypass_register(saturatechainout_bypass_register_or),
.dataout(saturatechainout_out_reg)
);
defparam saturatechainout_output_register.data_width = 1;
//decode the clk and aclr values
assign saturatechainout_clkval_or =(saturatechainout_output_clock == "0") ? 4'b0000 :
(saturatechainout_output_clock == "1") ? 4'b0001 :
(saturatechainout_output_clock == "2") ? 4'b0010 :
(saturatechainout_output_clock == "3") ? 4'b0011 : 4'b0000;
assign saturatechainout_aclrval_or = (saturatechainout_output_clear == "0") ? 4'b0000 :
(saturatechainout_output_clear == "1") ? 4'b0001 :
(saturatechainout_output_clear == "2") ? 4'b0010 :
(saturatechainout_output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign saturatechainout_clk_or = clk[saturatechainout_clkval_or] ? 1'b1 : 1'b0;
assign saturatechainout_aclr_or = aclr[saturatechainout_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign saturatechainout_sload_or = ena[saturatechainout_clkval_or] ? 1'b1 : 1'b0;
assign saturatechainout_bypass_register_or = (saturatechainout_output_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the Carry chainout Adder
arriaiigz_carry_chain_adder chainout_adder(
.dataa(rs_dataout_out_reg),
.datab(chainin_coa_in),
.dataout(coa_dataout)
);
//Instantiate the carry chainout adder RS Block
arriaiigz_round_saturate_block coa_rs_block(
.datain(coa_dataout),
.round(roundchainout_out_reg),
.saturate(saturatechainout_out_reg),
.signa(signa_pip_reg),
.signb(signb_pip_reg),
.datain_width(coa_datain_width),
.dataout(coa_rs_dataout),
.saturationoverflow(coa_rs_saturation_overflow)
);
defparam coa_rs_block.dataa_width = dataa_width;
defparam coa_rs_block.datab_width = datab_width;
defparam coa_rs_block.saturate_width = saturate_chain_out_width;
defparam coa_rs_block.round_width =round_width;
defparam coa_rs_block.saturate_mode = saturate_chain_out_mode;
defparam coa_rs_block.round_mode = round_chain_out_mode;
defparam coa_rs_block.operation_mode = operation_mode;
assign coa_datain_width = ssa_datain_width;
assign coa_round_width = round_chain_out_width[3:0];
assign coa_fraction_width = coa_datain_width - saturate_chain_out_width[7:0];
//Instantiate the rs_saturation_overflow output register (after COA)
arriaiigz_mac_register coa_rs_saturation_overflow_register (
.datain(rs_saturation_overflow_out_reg),
.clk(coa_reg_clk_or),
.aclr(coa_reg_aclr_or),
.sload(coa_reg_sload_or),
.bypass_register(1'b1),
.dataout(coa_rs_saturation_overflow_out_reg)
);
defparam coa_rs_saturation_overflow_register.data_width = 1;
//Instantiate the rs_saturationchainout_overflow output register
arriaiigz_mac_register coa_rs_saturationchainout_overflow_register (
.datain(coa_rs_saturation_overflow),
.clk(coa_reg_clk_or),
.aclr(coa_reg_aclr_or),
.sload(coa_reg_sload_or),
.bypass_register(coa_reg_bypass_register_or),
.dataout(coa_rs_saturationchainout_overflow_out_reg)
);
defparam coa_rs_saturationchainout_overflow_register.data_width = 1;
// Instantiate the coa_rs_dataout output register
arriaiigz_mac_register coa_rs_dataout_register (
.datain(coa_rs_dataout),
.clk(coa_reg_clk_or),
.aclr(coa_reg_aclr_or),
.sload(coa_reg_sload_or),
.bypass_register(coa_reg_bypass_register_or),
.dataout(coa_rs_dataout_out_reg)
);
defparam coa_rs_dataout_register.data_width = 72;
//decode the clk and aclr values
assign coa_reg_clkval_or =(output_clock == "0") ? 4'b0000 :
(output_clock == "1") ? 4'b0001 :
(output_clock == "2") ? 4'b0010 :
(output_clock == "3") ? 4'b0011 : 4'b0000;
assign coa_reg_aclrval_or =(output_clear == "0") ? 4'b0000 :
(output_clear == "1") ? 4'b0001 :
(output_clear == "2") ? 4'b0010 :
(output_clear == "3") ? 4'b0011 : 4'b0000;
//assign the corresponding clk,aclr,enable and bypass register values.
assign coa_reg_clk_or = clk[coa_reg_clkval_or] ? 1'b1 : 1'b0;
assign coa_reg_aclr_or = aclr[coa_reg_aclrval_or] || ~devclrn || ~devpor ? 1'b1 : 1'b0;
assign coa_reg_sload_or = ena[coa_reg_clkval_or] ? 1'b1 : 1'b0;
assign coa_reg_bypass_register_or = (output_clock == "none") ? 1'b1 : 1'b0;
//Instantiate the Shift/Rotate Unit
arriaiigz_rotate_shift_block shift_rot_unit(
.datain(rs_dataout_out_reg),
.rotate(rotate_out_reg),
.shiftright(shiftright_out_reg),
.signa(signa_pip_reg),
.signb(signb_pip_reg),
.dataout(dataout_shift_rot)
);
defparam shift_rot_unit.dataa_width = dataa_width;
defparam shift_rot_unit.datab_width = datab_width;
//Assign the dataout depending on the mode of operation
assign dataout_tmp = ((operation_mode == "accumulator_chain_out")||(operation_mode == "two_level_adder_chain_out"))
? coa_rs_dataout_out_reg :
(operation_mode == "shift") ? dataout_shift_rot : rs_dataout_out_reg;
//Assign the loopbackout for loopback mode
assign loopbackout_tmp = ((operation_mode == "loopback") && (!zeroloopback_out_reg)) ? rs_dataout_out_reg : 0;
//Assign the saturation overflow output
assign overflow = ((operation_mode == "accumulator") ||(operation_mode == "two_level_adder"))
? rs_saturation_overflow_out_reg :
((operation_mode == "accumulator_chain_out")||(operation_mode == "two_level_adder_chain_out"))
? coa_rs_saturation_overflow_out_reg : 1'b0;
//Assign the saturationchainout overflow output
assign saturatechainoutoverflow = ((operation_mode == "accumulator_chain_out") ||(operation_mode == "two_level_adder_chain_out"))
? coa_rs_saturationchainout_overflow_out_reg : 1'b0;
assign dataout = (((operation_mode == "accumulator_chain_out")||(operation_mode == "two_level_adder_chain_out")) &&(zerochainout_out_reg == 1'b1)) ? 72'b0 :dataout_tmp;
assign loopbackout = loopbackout_tmp[35:18];
endmodule
// begin_ddr
//-----------------------------------------------------------------------------
// Module Name: arriaiigz_ddr_gray_decoder
// Description: auxilary module for ddr. Gray decoder
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_ddr_gray_decoder (
gin,
bout
);
parameter width = 6;
input [width-1 : 0] gin;
output [width-1 : 0] bout;
reg [width-1 : 0] breg;
integer i;
assign bout = breg;
always @(gin)
begin
breg[width-1] = gin[width-1];
if (width > 1)
begin
for (i=width-2; i >= 0; i=i-1)
breg[i] = breg[i+1] ^ gin[i];
end
end
endmodule
//-----------------------------------------------------------------------------
// Module Name: arriaiigz_ddr_delay_chain_s
// Description: auxilary module - delay chain-setting
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_ddr_delay_chain_s (
clk,
delayctrlin,
phasectrlin,
delayed_clkout
);
parameter use_phasectrlin = "true";
parameter phase_setting = 0;
parameter sim_buffer_intrinsic_delay = 350;
parameter sim_buffer_delay_increment = 10;
parameter phasectrlin_limit = 7;
input clk;
input [5 : 0] delayctrlin;
input [3 : 0] phasectrlin;
output delayed_clkout;
// decoded counter
wire [5:0] delayctrl_bin;
// cell delay
integer acell_delay;
integer delay_chain_len;
integer clk_delay;
// int signals
reg delayed_clk;
// filtering X/U etc.
wire [5 : 0] delayctrlin_in;
wire [3 : 0] phasectrlin_in;
assign delayctrlin_in[0] = (delayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[1] = (delayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[2] = (delayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[3] = (delayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[4] = (delayctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[5] = (delayctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[0] = (phasectrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[1] = (phasectrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[2] = (phasectrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[3] = (phasectrlin[3] === 1'b1) ? 1'b1 : 1'b0;
initial
begin
acell_delay = 0;
delay_chain_len = 0;
clk_delay = 0;
delayed_clk = 1'b0;
end
arriaiigz_ddr_gray_decoder m_delayctrl_in_dec(delayctrlin_in, delayctrl_bin);
always @(delayctrl_bin or phasectrlin_in)
begin
// cell
acell_delay = sim_buffer_intrinsic_delay + delayctrl_bin * sim_buffer_delay_increment;
// no of cells
if (use_phasectrlin == "false")
delay_chain_len = phase_setting;
else
delay_chain_len = (phasectrlin_in > phasectrlin_limit) ? 0 : phasectrlin_in;
// total delay - added extra 1 ps for resolving racing
clk_delay = delay_chain_len * acell_delay + 1;
if ((use_phasectrlin == "true") && (phasectrlin_in > phasectrlin_limit))
begin
$display($time, " Warning: DDR phasesetting %m has invalid setting %b", phasectrlin_in);
end
end
// delayed clock
always @(clk)
delayed_clk <= #(clk_delay) clk;
assign delayed_clkout = delayed_clk;
endmodule
//-----------------------------------------------------------------------------
// Module Name: arriaiigz_ddr_io_reg
// Description: io register model based on dffeas with
// input port 'rpt_viloation' addition
//-----------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module arriaiigz_ddr_io_reg (
d,
clk,
ena,
clrn,
prn,
aload,
asdata,
sclr,
sload,
devclrn,
devpor,
rpt_violation,
q
);
// GLOBAL PARAMETER DECLARATION
parameter power_up = "DONT_CARE";
parameter is_wysiwyg = "false";
// LOCAL_PARAMETERS_BEGIN
parameter x_on_violation = "on";
// LOCAL_PARAMETERS_END
input d;
input clk;
input ena;
input clrn;
input prn;
input aload;
input asdata;
input sclr;
input sload;
input devclrn;
input devpor;
input rpt_violation;
output q;
wire q_tmp;
wire reset;
reg viol;
wire nosloadsclr;
wire sloaddata;
assign reset = devpor && devclrn && clrn && ena && rpt_violation;
assign nosloadsclr = reset && (~sload && ~sclr);
assign sloaddata = reset && sload;
assign q = q_tmp;
dffeas ddr_reg (
.d(d),
.clk(clk),
.clrn(clrn),
.aload(aload),
.sclr(sclr),
.sload(sload),
.asdata(asdata),
.ena(ena),
.prn(prn),
.q(q_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddr_reg.power_up = power_up;
specify
$setuphold (posedge clk &&& nosloadsclr, d, 0, 0, viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, viol) ;
$setuphold (posedge clk &&& sloaddata, asdata, 0, 0, viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, viol) ;
(posedge clk => (q +: d)) = 0 ;
(posedge clrn => (q +: 1'b0)) = (0, 0) ;
(posedge prn => (q +: 1'b1)) = (0, 0) ;
(posedge aload => (q +: d)) = (0, 0) ;
(asdata => q) = (0, 0) ;
endspecify
endmodule
//-----------------------------------------------------------------------------
//
// Module Name : arriaiigz_dll
//
// Description : ARRIAIIGZ Delay Locked Loop
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_dll (
clk,
aload,
upndnin,
upndninclkena,
devclrn,
devpor,
offsetdelayctrlout,
offsetdelayctrlclkout,
delayctrlout,
dqsupdate,
upndnout
);
// GLOBAL PARAMETERS - total 12
parameter input_frequency = "0 ps";
parameter delay_buffer_mode = "low"; // consistent with dqs
parameter delay_chain_length = 12;
parameter delayctrlout_mode = "normal";
parameter jitter_reduction = "false";
parameter use_upndnin = "false";
parameter use_upndninclkena = "false";
parameter sim_valid_lock = 16;
parameter sim_valid_lockcount = 0; // 0 = 350 + 10*dllcounter
parameter sim_low_buffer_intrinsic_delay = 350;
parameter sim_high_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
parameter static_delay_ctrl = 0; // for test
parameter dual_phase_comparators = "true"; // new in arriaiigz
parameter lpm_type = "arriaiigz_dll";
// LOCAL_PARAMETERS_BEGIN
parameter sim_buffer_intrinsic_delay = (delay_buffer_mode == "low") ? sim_low_buffer_intrinsic_delay
: sim_high_buffer_intrinsic_delay;
// LOCAL_PARAMETERS_END
// INPUT PORTS
input aload;
input clk;
input upndnin;
input upndninclkena;
input devclrn;
input devpor;
// OUTPUT PORTS
output [5:0] delayctrlout;
output dqsupdate;
output [5:0] offsetdelayctrlout;
output offsetdelayctrlclkout;
output upndnout;
tri1 devclrn;
tri1 devpor;
// BUFFERED BUS INPUTS
// TMP OUTPUTS
wire [5:0] delayctrl_out;
wire [5:0] offsetdelayctrl_out;
wire dqsupdate_out;
wire upndn_out;
// FUNCTIONS
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction // str2int
// Const VARIABLES to represent string parameters
reg [1:0] para_delay_buffer_mode;
reg [1:0] para_delayctrlout_mode;
reg [5:0] para_static_delay_ctrl;
reg para_jitter_reduction;
reg para_use_upndnin;
reg para_use_upndninclkena;
// INTERNAL NETS AND VARIABLES
// for functionality - by modules
// two reg on the de-assertion of dll
wire aload_in;
reg aload_reg1;
reg aload_reg2;
// delay and offset control out resolver
wire [5:0] dr_delayctrl_out;
wire [5:0] dr_delayctrl_int;
wire [5:0] dr_offsetctrl_out;
wire [5:0] dr_dllcount_in;
wire dr_clk8_in;
wire dr_aload_in;
reg [5:0] dr_reg_dllcount;
// delay chain setting counter
wire [5:0] dc_dllcount_out;
wire [5:0] dc_dllcount_out_gray;
wire dc_upndn_in;
wire dc_aload_in;
wire dc_upndnclkena_in;
wire dc_clk8_in;
wire dc_clk1_in;
wire dc_dlltolock_in;
reg [5:0] dc_reg_dllcount;
reg dc_reg_dlltolock_pulse;
// jitter reduction counter
wire jc_upndn_out;
wire jc_upndnclkena_out;
wire jc_clk8_in;
wire jc_upndn_in;
wire jc_aload_in;
wire jc_clkena_in; // new in arriaiigz
integer jc_count;
reg jc_reg_upndn;
reg jc_reg_upndnclkena;
// phase comparator
wire pc_lock; // new in arriaiigz
wire pc_upndn_out;
wire [5:0] pc_dllcount_in;
wire pc_clk1_in;
wire pc_clk8_in;
wire pc_aload_in;
reg pc_reg_upndn;
integer pc_delay;
reg pc_lock_reg; // new in arriaiigz
integer pc_comp_range; // new in arriaiigz
// clock generator
wire cg_clk_in;
wire cg_aload_in;
wire cg_clk1_out;
wire cg_clk8a_out;
wire cg_clk8b_out;
reg cg_reg_1;
reg cg_rega_2;
reg cg_rega_3;
reg cg_regb_2;
reg cg_regb_3;
// for violation checks
reg clk_in_last_value;
reg got_first_rising_edge;
reg got_first_falling_edge;
reg per_violation;
reg duty_violation;
reg sent_per_violation;
reg sent_duty_violation;
reg dll_to_lock; // exported signal
time clk_in_last_rising_edge;
time clk_in_last_falling_edge;
integer input_period;
integer clk_per_tolerance;
integer duty_cycle;
integer half_cycles_to_lock;
integer clk_in_period;
integer clk_in_duty_cycle;
// Timing hooks
// BUFFER INPUTS
wire clk_in;
wire aload_in_buf;
wire upndn_in;
wire upndninclkena_in;
assign clk_in = clk;
assign aload_in_buf = (aload === 1'b1) ? 1'b1 : 1'b0;
assign upndn_in = (upndnin === 1'b1) ? 1'b1 : 1'b0;
assign upndninclkena_in = (upndninclkena === 1'b1) ? 1'b1 : 1'b0;
// TCO DELAYS, IO PATH and SETUP-HOLD CHECKS
specify
(posedge clk => (delayctrlout[0] +: delayctrl_out[0])) = (0, 0);
(posedge clk => (delayctrlout[1] +: delayctrl_out[1])) = (0, 0);
(posedge clk => (delayctrlout[2] +: delayctrl_out[2])) = (0, 0);
(posedge clk => (delayctrlout[3] +: delayctrl_out[3])) = (0, 0);
(posedge clk => (delayctrlout[4] +: delayctrl_out[4])) = (0, 0);
(posedge clk => (delayctrlout[5] +: delayctrl_out[5])) = (0, 0);
(posedge clk => (upndnout +: upndn_out)) = (0, 0);
$setuphold(posedge clk, upndnin, 0, 0);
$setuphold(posedge clk, upndninclkena, 0, 0);
endspecify
// DRIVERs FOR outputs
and (delayctrlout[0], delayctrl_out[0], 1'b1);
and (delayctrlout[1], delayctrl_out[1], 1'b1);
and (delayctrlout[2], delayctrl_out[2], 1'b1);
and (delayctrlout[3], delayctrl_out[3], 1'b1);
and (delayctrlout[4], delayctrl_out[4], 1'b1);
and (delayctrlout[5], delayctrl_out[5], 1'b1);
and (offsetdelayctrlout[5], offsetdelayctrl_out[5], 1'b1);
and (offsetdelayctrlout[0], offsetdelayctrl_out[0], 1'b1);
and (offsetdelayctrlout[1], offsetdelayctrl_out[1], 1'b1);
and (offsetdelayctrlout[2], offsetdelayctrl_out[2], 1'b1);
and (offsetdelayctrlout[3], offsetdelayctrl_out[3], 1'b1);
and (offsetdelayctrlout[4], offsetdelayctrl_out[4], 1'b1);
and (offsetdelayctrlout[5], offsetdelayctrl_out[5], 1'b1);
and (dqsupdate, dqsupdate_out, 1'b1);
and (upndnout, upndn_out, 1'b1);
// INITIAL BLOCK - info messsage and legaity checks
initial
begin
input_period = str2int(input_frequency);
$display("Note: DLL instance %m has input frequency %0d ps", input_period);
$display(" sim_valid_lock %0d", sim_valid_lock);
$display(" sim_valid_lockcount %0d", sim_valid_lockcount);
$display(" sim_low_buffer_intrinsic_delay %0d", sim_buffer_intrinsic_delay);
$display(" sim_high_buffer_intrinsic_delay %0d", sim_buffer_intrinsic_delay);
$display(" delay_buffer_mode %0s", delay_buffer_mode);
$display(" sim_buffer_intrinsic_delay %0d", sim_buffer_intrinsic_delay);
$display(" sim_buffer_delay_increment %0d", sim_buffer_delay_increment);
$display(" delay_chain_length %0d", delay_chain_length);
clk_in_last_value = 0;
clk_in_last_rising_edge = 0;
clk_in_last_falling_edge = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
per_violation = 1'b0;
duty_violation = 1'b0;
sent_per_violation = 1'b0;
sent_duty_violation = 1'b0;
duty_cycle = input_period/2;
clk_per_tolerance = 2;
clk_in_period = 0;
clk_in_duty_cycle = 0;
dll_to_lock = 0;
half_cycles_to_lock = 0;
// Resolve string parameters
para_delay_buffer_mode = delay_buffer_mode == "auto" ? 2'b00 :
delay_buffer_mode == "low" ? 2'b01 : 2'b10;
para_delayctrlout_mode = delayctrlout_mode == "test" ? 2'b01 :
delayctrlout_mode == "normal" ? 2'b10 :
delayctrlout_mode == "static" ? 2'b11 : 2'b00;
para_static_delay_ctrl = static_delay_ctrl;
para_jitter_reduction = jitter_reduction == "true" ? 1'b1 : 1'b0;
para_use_upndnin = use_upndnin == "true" ? 1'b1 : 1'b0;
para_use_upndninclkena = use_upndninclkena == "true" ? 1'b1 : 1'b0;
$display(" delayctrlout_mode %0s", delayctrlout_mode);
$display(" static_delay_ctrl %0d", para_static_delay_ctrl);
$display(" use_jitter_reduction %0s", jitter_reduction);
$display(" use_upndnin %0s", use_upndnin);
$display(" use_upndninclkena %0s", use_upndninclkena);
end
// CLOCK PERIOD and DUTY CYCLE VIOLATION CHECKS and DLL_TO_LOCK
// exported signals to outside of this block:
// - dll_to_lock
always @(clk_in)
begin
if (clk_in == 1'b1 && clk_in != clk_in_last_value) // rising edge
begin
if (got_first_rising_edge == 1'b0)
begin
got_first_rising_edge <= 1;
half_cycles_to_lock = half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock)
begin
dll_to_lock <= 1;
$display($time, " Note : DLL instance %m to lock to incoming clock per sim_valid_lock half clock cycles.");
end
end
else // subsequent rising edge
begin
// check for clk_period violation and duty cycle violation
clk_in_period = $time - clk_in_last_rising_edge;
clk_in_duty_cycle = $time - clk_in_last_falling_edge;
if ( (clk_in_period < (input_period - clk_per_tolerance)) ||
(clk_in_period > (input_period + clk_per_tolerance)) )
begin
per_violation = 1'b1;
if (sent_per_violation != 1'b1)
begin
$display($time, " Warning : Input frequency violation on DLL instance %m. Specified input period is %0d ps but actual is %0d ps",
input_period, clk_in_period);
sent_per_violation = 1'b1;
end
end
else if ( (clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1)) ||
(clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1)) )
begin
duty_violation = 1'b1;
if (sent_duty_violation != 1'b1)
begin
$display($time, " Warning : Duty Cycle violation DLL instance %m. Specified duty cycle is %0d ps but actual is %0d ps",
duty_cycle, clk_in_duty_cycle);
sent_duty_violation = 1'b1;
end
end
else
begin
if (per_violation === 1'b1)
begin
$display($time, " Note : Input frequency on DLL instance %m now matches with specified clock frequency.");
sent_per_violation = 1'b0;
end
per_violation = 1'b0;
duty_violation = 1'b0;
end
if ((duty_violation == 1'b0) && (per_violation == 1'b0) && (dll_to_lock == 1'b0))
begin
// increment lock counter
half_cycles_to_lock = half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock)
begin
dll_to_lock <= 1;
$display($time, " Note : DLL instance %m to lock to incoming clock per sim_valid_lock half clock cycles.");
end
end
end
clk_in_last_rising_edge = $time;
end
else if (clk_in == 1'b0 && clk_in != clk_in_last_value) // falling edge
begin
got_first_falling_edge = 1;
if (got_first_rising_edge == 1'b1)
begin
// check for duty cycle violation
clk_in_duty_cycle = $time - clk_in_last_rising_edge;
if ( (clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1)) ||
(clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1)) )
begin
duty_violation = 1'b1;
if (sent_duty_violation != 1'b1)
begin
$display($time, " Warning : Duty Cycle violation DLL instance %m. Specified duty cycle is %0d ps but actual is %0d ps",
duty_cycle, clk_in_duty_cycle);
sent_duty_violation = 1'b1;
end
end
else
duty_violation = 1'b0;
if (dll_to_lock == 1'b0 && duty_violation == 1'b0)
begin
// increment lock counter
half_cycles_to_lock = half_cycles_to_lock + 1;
end
end
else
begin
// first clk edge is falling edge, do nothing
end
clk_in_last_falling_edge = $time;
end
else if (got_first_rising_edge == 1'b1 || got_first_falling_edge == 1'b1)
begin
// 1 or 0 to X transitions - illegal
// reset lock and unlock counters
half_cycles_to_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
if (dll_to_lock)
begin
dll_to_lock <= 0;
$display($time, " Warning : clock switches from 0/1 to X. DLL instance %m will lose lock.");
end
else
begin
$display($time, " Warning : clock switches from 0/1 to X on DLL instance %m");
end
end
clk_in_last_value <= clk_in;
end
// CONNCECTING the DLL outputs ------------------------------------------------
assign delayctrl_out = dr_delayctrl_out;
assign offsetdelayctrl_out = dr_offsetctrl_out;
assign offsetdelayctrlclkout = dr_clk8_in;
assign dqsupdate_out = cg_clk8a_out;
assign upndn_out = pc_upndn_out;
// two reg on the de-assertion of dll -----------------------------------------
assign aload_in = aload_in_buf | aload_reg2;
initial begin
aload_reg1 = 1'b1;
aload_reg2 = 1'b1;
end
always @(negedge clk_in)
begin
aload_reg1 <= aload_in_buf;
aload_reg2 <= aload_reg1;
end
// Delay and offset ctrl out resolver -----------------------------------------
// inputs
assign dr_clk8_in = ~cg_clk8b_out; // inverted
assign dr_dllcount_in = dc_dllcount_out_gray; // gray-coded for all outputs
assign dr_aload_in = aload_in;
// outputs
// ,addnsub,
assign dr_delayctrl_out = (delayctrlout_mode == "test") ? {cg_clk1_out,aload,1'bx,dr_reg_dllcount[2:0]}
: dr_reg_dllcount; // both static and normal
assign dr_offsetctrl_out = dr_delayctrl_int; // non-registered of delayout_out
// model
// assumed para_static_delay_ctrl is gray-coded
assign dr_delayctrl_int = (delayctrlout_mode == "static") ? para_static_delay_ctrl : dr_dllcount_in;
// por
initial
begin
dr_reg_dllcount = 6'b000000;
end
always @(posedge dr_clk8_in or posedge dr_aload_in )
begin
if (dr_aload_in === 1'b1)
dr_reg_dllcount <= 6'b000000;
else
dr_reg_dllcount <= dr_delayctrl_int;
end
// Delay Setting Control Counter ----------------------------------------------
//inputs
assign dc_dlltolock_in = dll_to_lock;
assign dc_aload_in = aload_in;
assign dc_clk1_in = cg_clk1_out;
assign dc_clk8_in = ~cg_clk8b_out; // inverted
assign dc_upndnclkena_in = (para_use_upndninclkena === 1'b1) ? upndninclkena :
(para_jitter_reduction === 1'b1) ? jc_upndnclkena_out :
(dual_phase_comparators == "true") ? ~pc_lock : 1'b1; // new in arriaiigz
assign dc_upndn_in = (para_use_upndnin === 1'b1) ? upndnin :
(para_jitter_reduction === 1'b1) ? jc_upndn_out : pc_upndn_out;
// outputs
assign dc_dllcount_out_gray = dc_reg_dllcount ^ (dc_reg_dllcount >> 1);
assign dc_dllcount_out = dc_reg_dllcount;
// parameters used
// sim_valid_lockcount - ideal dll count value
// delay_buffer_mode -
// Model - registers to 0 in hardware by POR
initial
begin
// low=32=6'b100000 others=16
dc_reg_dllcount = (delay_buffer_mode == "low") ? 6'b000000 : 6'b000000;
dc_reg_dlltolock_pulse = 1'b0;
end
// dll counter logic - binary
always @(posedge dc_clk8_in or posedge dc_aload_in or posedge dc_dlltolock_in)
begin
if (dc_aload_in === 1'b1)
dc_reg_dllcount <= delay_buffer_mode == "low" ? 6'b100000 : 6'b010000;
else if (dc_dlltolock_in === 1'b1 && dc_upndnclkena_in === 1'b1 &&
para_use_upndnin === 1'b0 && dc_reg_dlltolock_pulse != 1'b1)
begin
dc_reg_dllcount <= sim_valid_lockcount;
dc_reg_dlltolock_pulse <= 1'b1;
end
else if (dc_upndnclkena_in === 1'b1) // posedge clk
begin
if (dc_upndn_in === 1'b1)
begin
if ((para_delay_buffer_mode == 2'b01 && dc_reg_dllcount < 6'b111111) ||
(para_delay_buffer_mode != 2'b01 && dc_reg_dllcount < 6'b011111))
dc_reg_dllcount <= dc_reg_dllcount + 1'b1;
end
else if (dc_upndn_in === 1'b0)
begin
if (dc_reg_dllcount > 6'b000000)
dc_reg_dllcount <= dc_reg_dllcount - 1'b1;
end
end
end
// Jitter reduction counter ---------------------------------------------------
// inputs
assign jc_clk8_in = ~cg_clk8b_out; // inverted
assign jc_upndn_in = pc_upndn_out;
assign jc_aload_in = aload_in;
// new in arriaiigz
assign jc_clkena_in = (dual_phase_comparators == "false") ? 1'b1 : ~pc_lock;
// outputs
assign jc_upndn_out = jc_reg_upndn;
assign jc_upndnclkena_out = jc_reg_upndnclkena;
// Model
initial
begin
jc_count = 8;
jc_reg_upndnclkena = 1'b0;
jc_reg_upndn = 1'b0;
end
always @(posedge jc_clk8_in or posedge jc_aload_in)
begin
if (jc_aload_in === 1'b1)
jc_count <= 8;
else if (jc_clkena_in === 1'b1)
begin
if (jc_count == 12)
begin
jc_reg_upndn <= 1'b1;
jc_reg_upndnclkena <= 1'b1;
jc_count <= 8;
end
else if (jc_count == 4)
begin
jc_reg_upndn <= 1'b0;
jc_reg_upndnclkena <= 1'b1;
jc_count <= 8;
end
else // increment/decrement counter
begin
jc_reg_upndnclkena <= 1'b0;
if (jc_upndn_in === 1'b1)
jc_count <= jc_count + 1;
else if (jc_upndn_in === 1'b0)
jc_count <= jc_count - 1;
end
end
else
jc_reg_upndnclkena <= 1'b0;
end
// Phase comparator -----------------------------------------------------------
// inputs
assign pc_clk1_in = cg_clk1_out;
assign pc_clk8_in = cg_clk8b_out; // positive edge
assign pc_dllcount_in = dc_dllcount_out; // for phase loop calculation: binary
assign pc_aload_in = aload_in;
// outputs
assign pc_upndn_out = pc_reg_upndn;
assign pc_lock = pc_lock_reg;
// parameter used
// sim_loop_intrinsic_delay, sim_buffer_delay_increment
// Model
initial
begin
pc_reg_upndn = 1'b1;
pc_delay = 0;
pc_lock_reg = 1'b0;
pc_comp_range = (3*delay_chain_length*sim_buffer_delay_increment)/2;
end
always @(posedge pc_clk8_in or posedge pc_aload_in)
begin
if (pc_aload_in === 1'b1)
pc_reg_upndn <= 1'b1;
else
begin
pc_delay = delay_chain_length *(sim_buffer_intrinsic_delay + sim_buffer_delay_increment * pc_dllcount_in);
if (dual_phase_comparators == "false")
begin
pc_lock_reg <= 1'b0;
if (pc_delay > input_period)
pc_reg_upndn <= 1'b0;
else
pc_reg_upndn <= 1'b1;
end
else
begin
if (pc_delay < (input_period - pc_comp_range/2))
begin
pc_reg_upndn <= 1'b1;
pc_lock_reg <= 1'b0;
end
else if ( pc_delay <= (input_period + pc_comp_range/2) )
begin
pc_lock_reg <= 1'b1;
pc_reg_upndn <= 1'b0;
end
else
begin
pc_lock_reg <= 1'b0;
pc_reg_upndn <= 1'b0;
end
end
end
end
// Clock Generator -----------------------------------------------------------
// inputs
assign cg_clk_in = clk_in;
assign cg_aload_in = aload_in;
// outputs
assign cg_clk8a_out = cg_rega_3;
assign cg_clk8b_out = cg_regb_3;
assign cg_clk1_out = (cg_aload_in === 1'b1) ? 1'b0 : cg_clk_in;
// Model
// por
initial
begin
cg_reg_1 = 1'b0;
cg_rega_2 = 1'b0;
cg_rega_3 = 1'b0;
cg_regb_2 = 1'b1;
cg_regb_3 = 1'b0;
end
always @(posedge cg_clk1_out or posedge cg_aload_in)
begin
if (cg_aload_in === 1'b1)
cg_reg_1 <= 1'b0;
else
cg_reg_1 <= ~cg_reg_1;
end
always @(posedge cg_reg_1 or posedge cg_aload_in)
begin
if (cg_aload_in === 1'b1)
begin
cg_rega_2 <= 1'b0;
cg_regb_2 <= 1'b1;
end
else
begin
cg_rega_2 <= ~cg_rega_2;
cg_regb_2 <= ~cg_regb_2;
end
end
always @(posedge cg_rega_2 or posedge cg_aload_in)
begin
if (cg_aload_in === 1'b1)
cg_rega_3 <= 1'b0;
else
cg_rega_3 <= ~cg_rega_3;
end
always @(posedge cg_regb_2 or posedge cg_aload_in)
begin
if (cg_aload_in === 1'b1)
cg_regb_3 <= 1'b0;
else if ($time != 0)
cg_regb_3 <= ~cg_regb_3;
end
endmodule // arriaiigz_dll
//-----------------------------------------------------------------------------
//
// Module Name : arriaiigz_offset_ctrl
//
// Description : ARRIAIIGZ Delay Locked Loop Offset Control
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_dll_offset_ctrl (
clk,
aload,
offsetdelayctrlin,
offset,
addnsub,
devclrn,
devpor,
offsettestout,
offsetctrlout
);
parameter use_offset = "false";
parameter static_offset = "0";
parameter delay_buffer_mode = "low"; // consistent with dqs
parameter lpm_type = "arriaiigz_dll_offset_ctrl";
// INPUT PORTS
input clk;
input aload;
input [5:0] offsetdelayctrlin;
input [5:0] offset;
input addnsub;
input devclrn;
input devpor;
// OUTPUT PORTS
output [5:0] offsetctrlout;
output [5:0] offsettestout;
tri1 devclrn;
tri1 devpor;
// TMP OUTPUTS
wire [5:0] offsetctrl_out;
// FUNCTIONS
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction // str2int
// Const VARIABLES to represent string parameters
reg [1:0] para_delay_buffer_mode;
reg [1:0] para_use_offset;
integer para_static_offset;
// INTERNAL NETS AND VARIABLES
// for functionality - by modules
// two reg on the de-assertion of dll
reg aload_reg1;
reg aload_reg2;
// delay and offset control out resolver
wire [5:0] dr_offsettest_out;
wire [5:0] dr_offsetctrl_out;
wire [5:0] dr_offsetctrl_out_gray;
wire dr_clk8_in;
wire dr_aload_in;
wire dr_addnsub_in;
wire [5:0] dr_offset_in_gray;
wire [5:0] dr_delayctrl_in_gray;
wire [5:0] para_static_offset_gray;
//decoder
wire [5:0] dr_delayctrl_in_bin;
wire [5:0] dr_offset_in_bin;
wire [5:0] dr_offset_in_bin_pos;
wire [5:0] para_static_offset_bin;
wire [5:0] para_static_offset_bin_pos;
reg [5:0] dr_reg_offset;
// Timing hooks
// BUFFER INPUTS
wire clk_in;
wire aload_in;
wire offset_in5;
wire offset_in4;
wire offset_in3;
wire offset_in2;
wire offset_in1;
wire offset_in0;
wire addnsub_in;
wire [5:0] offsetdelayctrlin_in;
wire [5:0] offset_in;
assign clk_in = clk;
assign aload_in = (aload === 1'b1) ? 1'b1 : 1'b0;
assign offset_in5 = (offset[5] === 1'b1) ? 1'b1 : 1'b0;
assign offset_in4 = (offset[4] === 1'b1) ? 1'b1 : 1'b0;
assign offset_in3 = (offset[3] === 1'b1) ? 1'b1 : 1'b0;
assign offset_in2 = (offset[2] === 1'b1) ? 1'b1 : 1'b0;
assign offset_in1 = (offset[1] === 1'b1) ? 1'b1 : 1'b0;
assign offset_in0 = (offset[0] === 1'b1) ? 1'b1 : 1'b0;
assign addnsub_in = (addnsub === 1'b1) ? 1'b1 : 1'b0;
assign offsetdelayctrlin_in[5] = (offsetdelayctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign offsetdelayctrlin_in[4] = (offsetdelayctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign offsetdelayctrlin_in[3] = (offsetdelayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign offsetdelayctrlin_in[2] = (offsetdelayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign offsetdelayctrlin_in[1] = (offsetdelayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign offsetdelayctrlin_in[0] = (offsetdelayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign offset_in = {offset_in5, offset_in4,
offset_in3, offset_in2,
offset_in1, offset_in0};
// TCO DELAYS, IO PATH and SETUP-HOLD CHECKS
// These timing paths existed from ARRIAIIGZ, currently not modeled in arriaiigz
specify
(posedge clk => (offsetctrlout[0] +: offsetctrl_out[0])) = (0, 0);
(posedge clk => (offsetctrlout[1] +: offsetctrl_out[1])) = (0, 0);
(posedge clk => (offsetctrlout[2] +: offsetctrl_out[2])) = (0, 0);
(posedge clk => (offsetctrlout[3] +: offsetctrl_out[3])) = (0, 0);
(posedge clk => (offsetctrlout[4] +: offsetctrl_out[4])) = (0, 0);
(posedge clk => (offsetctrlout[5] +: offsetctrl_out[5])) = (0, 0);
(offset => offsetctrlout) = (0, 0);
$setuphold(posedge clk, offset[0], 0, 0);
$setuphold(posedge clk, offset[1], 0, 0);
$setuphold(posedge clk, offset[2], 0, 0);
$setuphold(posedge clk, offset[3], 0, 0);
$setuphold(posedge clk, offset[4], 0, 0);
$setuphold(posedge clk, offset[5], 0, 0);
$setuphold(posedge clk, addnsub, 0, 0);
endspecify
// DRIVERs FOR outputs
and (offsetctrlout[0], offsetctrl_out[0], 1'b1);
and (offsetctrlout[1], offsetctrl_out[1], 1'b1);
and (offsetctrlout[2], offsetctrl_out[2], 1'b1);
and (offsetctrlout[3], offsetctrl_out[3], 1'b1);
and (offsetctrlout[4], offsetctrl_out[4], 1'b1);
and (offsetctrlout[5], offsetctrl_out[5], 1'b1);
// INITIAL BLOCK - info messsage and legaity checks
initial
begin
// Resolve string parameters
para_delay_buffer_mode = delay_buffer_mode == "low" ? 2'b01 : 2'b00;
para_use_offset = use_offset == "true" ? 2'b01 : 2'b00;
para_static_offset = str2int(static_offset);
$display("Note: DLL_offset_ctrl instance %m has delay_buffer_mode %0s", delay_buffer_mode);
$display(" use_offset %0s", use_offset);
$display(" static_offset %0d", para_static_offset);
end
// CONNCECTING primary outputs ------------------------------------------------
assign offsetctrl_out = dr_offsetctrl_out_gray;
assign offsettestout = dr_offsettest_out;
// ----------------------------------------------------------------------------
// offset ctrl out resolver:
// adding offset_in into offsetdelayin according to offsetctrlout_mode
// ----------------------------------------------------------------------------
// two reg on the de-assertion of dll -----------------------------------------
// it is the clk feeding into DLL, not /8 clock.
initial begin
aload_reg1 = 1'b1;
aload_reg2 = 1'b1;
end
always @(negedge clk_in)
begin
aload_reg1 <= aload_in;
aload_reg2 <= aload_reg1;
end
// inputs
assign dr_clk8_in = clk_in;
assign dr_aload_in = aload_in; // aload_in | aload_reg2;
assign dr_addnsub_in = addnsub_in;
assign dr_delayctrl_in_gray = offsetdelayctrlin_in;
// ------------------------------------------------------------------------
// substraction flow:
// - decode
// - ADD or (2's complement then sub - better for overflow check)
//Addtion flow:
// - decode
// - add
//------------------------------------------------------------------------
assign dr_offset_in_gray = offset_in;
assign para_static_offset_gray = para_static_offset[5:0];
// for counter overflow check - getting the binary abs() of the binary para_static
assign para_static_offset_bin_pos = (para_static_offset > 0) ? para_static_offset_bin :
(6'b111111 - para_static_offset_bin + 6'b000001);
assign dr_offset_in_bin_pos = ((use_offset == "true") && (dr_addnsub_in === 1'b0)) ?
(6'b111111 - dr_offset_in_bin + 6'b000001) : dr_offset_in_bin;
// outputs
assign dr_offsetctrl_out = dr_reg_offset;
assign dr_offsetctrl_out_gray = dr_reg_offset ^ (dr_reg_offset >> 1);
assign dr_offsettest_out = (use_offset == "false") ? para_static_offset[5:0] : offset_in;
// model
// gray decoder
arriaiigz_ddr_gray_decoder mdr_delayctrl_in_dec(dr_delayctrl_in_gray, dr_delayctrl_in_bin);
arriaiigz_ddr_gray_decoder mdr_offset_in_dec(dr_offset_in_gray, dr_offset_in_bin);
arriaiigz_ddr_gray_decoder mpara_static_offset_dec(para_static_offset_gray, para_static_offset_bin);
// por
initial
begin
dr_reg_offset = 6'b000000;
end
// based on dr_delayctrl_in and dr_offset_in_bin (for dynamic) and para_static_offset_bin
always @(posedge dr_clk8_in or posedge dr_aload_in)
begin
if (dr_aload_in === 1'b1)
begin
dr_reg_offset <= 6'b000000;
end
else if (use_offset == "true") // addnsub
begin
if (dr_addnsub_in === 1'b1)
if (dr_delayctrl_in_bin < 6'b111111 - dr_offset_in_bin)
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin;
else
dr_reg_offset <= 6'b111111;
else if (dr_addnsub_in === 1'b0)
if (dr_delayctrl_in_bin > dr_offset_in_bin_pos)
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin; // same as - _pos
else
dr_reg_offset <= 6'b000000;
end
else // static
begin
if (para_static_offset >= 0)
if (para_static_offset_bin < 64 && para_static_offset_bin < 6'b111111 - dr_delayctrl_in_bin)
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin;
else
dr_reg_offset <= 6'b111111;
else // donot use a_vec - b_vec >=0 as it is always true
if (para_static_offset_bin_pos < 63 && dr_delayctrl_in_bin > para_static_offset_bin_pos)
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin; // same as - *_pos
else
dr_reg_offset <= 6'b000000;
end
end
endmodule // arriaiigz_offset_ctrl
//-----------------------------------------------------------------------------
//
// Module Name : arriaiigz_dqs_delay_chain
//
// Description : ARRIAIIGZ DQS Delay Chain (within DQS I/O)
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_dqs_delay_chain (
dqsin,
delayctrlin,
offsetctrlin,
dqsupdateen,
phasectrlin,
devclrn,
devpor,
dffin,
dqsbusout
);
parameter dqs_input_frequency = "unused" ; // not used
parameter use_phasectrlin = "false"; // rev 1.21
parameter phase_setting = 0; // <0 - 4>
parameter delay_buffer_mode = "low";
parameter dqs_phase_shift = 0; // <0..36000> for TAN only
parameter dqs_offsetctrl_enable = "false";
parameter dqs_ctrl_latches_enable = "false";
// test parameters added in WYS 1.33
parameter test_enable = "false";
parameter test_select = 0;
// Simulation parameters
parameter sim_low_buffer_intrinsic_delay = 350;
parameter sim_high_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
parameter lpm_type = "arriaiigz_dqs_delay_chain";
// INPUT PORTS
input dqsin;
input [5:0] delayctrlin;
input [5:0] offsetctrlin;
input dqsupdateen;
input [2:0] phasectrlin;
input devclrn, devpor;
// OUTPUT PORTS
output dqsbusout;
output dffin; // buried
// LOCAL_PARAMETERS_BEGIN
parameter sim_intrinsic_delay = (delay_buffer_mode == "low") ? sim_low_buffer_intrinsic_delay :
sim_high_buffer_intrinsic_delay;
// LOCAL_PARAMETERS_END
tri1 devclrn;
tri1 devpor;
// decoded counter
wire [5:0] delayctrl_bin;
wire [5:0] offsetctrl_bin;
// offsetctrl after "dqs_offsetctrl_enable" mux
wire [5:0] offsetctrl_mux;
// reged outputs of delay count
reg [5:0] delayctrl_reg;
reg [5:0] offsetctrl_reg;
// delay count after latch enable mux
wire [5:0] delayctrl_reg_mux;
wire [5:0] offsetctrl_reg_mux;
// single cell delay
integer tmp_delayctrl;
integer tmp_offsetctrl;
integer acell_delay;
integer aoffsetcell_delay;
integer delay_chain_len;
integer dqs_delay;
reg tmp_dqsbusout;
// Buffer Layer
wire dqsin_in;
wire [5:0] delayctrlin_in;
wire [5:0] offsetctrlin_in;
wire dqsupdateen_in;
wire [2:0] phasectrlin_in;
wire [12:0] test_bus;
wire test_lpbk;
wire tmp_dqsin; // after and with test_loopback
assign dqsin_in = dqsin;
assign delayctrlin_in[5] = (delayctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[4] = (delayctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[3] = (delayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[2] = (delayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[1] = (delayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[0] = (delayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign offsetctrlin_in[5] = (offsetctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign offsetctrlin_in[4] = (offsetctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign offsetctrlin_in[3] = (offsetctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign offsetctrlin_in[2] = (offsetctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign offsetctrlin_in[1] = (offsetctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign offsetctrlin_in[0] = (offsetctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign dqsupdateen_in = (dqsupdateen === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[2] = (phasectrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[1] = (phasectrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[0] = (phasectrlin[0] === 1'b1) ? 1'b1 : 1'b0;
specify
(dqsin => dqsbusout) = (0,0);
$setuphold(posedge dqsupdateen, delayctrlin[0], 0, 0);
$setuphold(posedge dqsupdateen, delayctrlin[1], 0, 0);
$setuphold(posedge dqsupdateen, delayctrlin[2], 0, 0);
$setuphold(posedge dqsupdateen, delayctrlin[3], 0, 0);
$setuphold(posedge dqsupdateen, delayctrlin[4], 0, 0);
$setuphold(posedge dqsupdateen, delayctrlin[5], 0, 0);
$setuphold(posedge dqsupdateen, offsetctrlin[0], 0, 0);
$setuphold(posedge dqsupdateen, offsetctrlin[1], 0, 0);
$setuphold(posedge dqsupdateen, offsetctrlin[2], 0, 0);
$setuphold(posedge dqsupdateen, offsetctrlin[3], 0, 0);
$setuphold(posedge dqsupdateen, offsetctrlin[4], 0, 0);
$setuphold(posedge dqsupdateen, offsetctrlin[5], 0, 0);
endspecify
// reg
initial begin
delayctrl_reg = 6'b111111;
offsetctrl_reg = 6'b111111;
tmp_delayctrl = 0;
tmp_offsetctrl = 0;
acell_delay = 0;
end
always @(posedge dqsupdateen_in)
begin
delayctrl_reg <= delayctrlin_in;
offsetctrl_reg <= offsetctrl_mux;
end
assign offsetctrl_mux = (dqs_offsetctrl_enable == "true") ? offsetctrlin_in : delayctrlin_in;
// mux after reg
assign delayctrl_reg_mux = (dqs_ctrl_latches_enable == "true") ? delayctrl_reg : delayctrlin_in;
assign offsetctrl_reg_mux = (dqs_ctrl_latches_enable == "true") ? offsetctrl_reg : offsetctrl_mux;
// decode
arriaiigz_ddr_gray_decoder m_delayctrl_in_dec (delayctrl_reg_mux, delayctrl_bin);
arriaiigz_ddr_gray_decoder m_offsetctrl_in_dec(offsetctrl_reg_mux, offsetctrl_bin);
always @(delayctrl_bin or offsetctrl_bin or phasectrlin_in)
begin
tmp_delayctrl = (delay_buffer_mode == "high" && delayctrl_bin[5] == 1'b1) ? 31 : delayctrl_bin;
tmp_offsetctrl = (delay_buffer_mode == "high" && offsetctrl_bin[5] == 1'b1) ? 31 : offsetctrl_bin;
// cell
acell_delay = sim_intrinsic_delay + tmp_delayctrl * sim_buffer_delay_increment;
if (dqs_offsetctrl_enable == "true")
aoffsetcell_delay = sim_intrinsic_delay + tmp_offsetctrl * sim_buffer_delay_increment;
else
aoffsetcell_delay = acell_delay;
// no of cells
if (use_phasectrlin == "false")
delay_chain_len = phase_setting;
else if (phasectrlin_in[2] === 1'b1)
delay_chain_len = 0;
else
delay_chain_len = phasectrlin_in + 3'b001;
// total delay
if (delay_chain_len == 0)
dqs_delay = 0;
else
dqs_delay = (delay_chain_len - 1)*acell_delay + aoffsetcell_delay;
end
// test bus loopback
assign test_bus = {~dqsupdateen_in, offsetctrl_reg_mux, delayctrl_reg_mux};
assign test_lpbk = (0 <= test_select && test_select <= 12) ? test_bus[test_select] : 1'bz;
assign tmp_dqsin = (test_enable == "true") ? (test_lpbk & dqsin_in) : dqsin_in;
always @(tmp_dqsin)
tmp_dqsbusout <= #(dqs_delay) tmp_dqsin;
pmos (dqsbusout, tmp_dqsbusout, 1'b0);
endmodule // arriaiigz_dqs_delay_chain
//-----------------------------------------------------------------------------
//
// Module Name : arriaiigz_dqs_enable
//
// Description : ARRIAIIGZ DQS Enable
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_dqs_enable (
dqsin,
dqsenable,
devclrn,
devpor,
dqsbusout
);
parameter lpm_type = "arriaiigz_dqs_enable";
// INPUT PORTS
input dqsin;
input dqsenable;
input devclrn;
input devpor;
// OUTPUT PORTS
output dqsbusout;
tri1 devclrn;
tri1 devpor;
wire tmp_dqsbusout;
reg ena_reg;
// BUFFER wrapper
wire dqsin_in;
wire dqsenable_in;
assign dqsin_in = dqsin;
assign dqsenable_in = (dqsenable === 1'b1) ? 1'b1 : 1'b0;
specify
(dqsin => dqsbusout) = (0,0);
(dqsenable => dqsbusout) = (0,0); // annotated on the dqsenable port
endspecify
initial ena_reg = 1'b1;
assign tmp_dqsbusout = ena_reg & dqsin_in;
always @(negedge tmp_dqsbusout or posedge dqsenable_in)
begin
if (dqsenable_in === 1'b1)
ena_reg <= 1'b1;
else
ena_reg <= 1'b0;
end
pmos (dqsbusout, tmp_dqsbusout, 1'b0);
endmodule // arriaiigz_dqs_enable
//-----------------------------------------------------------------------------
//
// Module Name : arriaiigz_dqs_enable_ctrl
//
// Description : ARRIAIIGZ DQS Enable Control
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_dqs_enable_ctrl (
dqsenablein,
clk,
delayctrlin,
phasectrlin,
enaphasetransferreg,
phaseinvertctrl,
devclrn, devpor,
dffin,
dffextenddqsenable,
dqsenableout
);
parameter use_phasectrlin = "true";
parameter phase_setting = 0;
parameter delay_buffer_mode = "high";
parameter level_dqs_enable = "false";
parameter delay_dqs_enable_by_half_cycle = "false";
parameter add_phase_transfer_reg = "false";
parameter invert_phase = "false";
parameter sim_low_buffer_intrinsic_delay = 350;
parameter sim_high_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
parameter lpm_type = "arriaiigz_dqs_enable_ctrl";
// INPUT PORTS
input dqsenablein;
input clk;
input [5:0] delayctrlin;
input [3:0] phasectrlin;
input enaphasetransferreg;
input phaseinvertctrl;
input devclrn;
input devpor;
// OUTPUT PORTS
output dqsenableout;
output dffin;
output dffextenddqsenable; // buried
// LOCAL_PARAMETERS_BEGIN
parameter sim_intrinsic_delay = (delay_buffer_mode == "low") ? sim_low_buffer_intrinsic_delay :
sim_high_buffer_intrinsic_delay;
// LOCAL_PARAMETERS_END
tri1 devclrn;
tri1 devpor;
// decoded counter
wire [5:0] delayctrl_bin;
// cell delay
integer acell_delay;
integer delay_chain_len;
integer clk_delay;
// int signals
wire phasectrl_clkout;
wire delayed_clk;
wire dqsenablein_reg_q;
wire dqsenablein_level_ena;
// transfer delay
wire dqsenablein_reg_dly;
wire phasetransferdelay_mux_out;
wire dqsenable_delayed_regp;
wire dqsenable_delayed_regn;
wire tmp_dqsenableout;
// BUFFER wrapper
wire dqsenablein_in;
wire clk_in;
wire [5:0] delayctrlin_in;
wire [3:0] phasectrlin_in;
wire enaphasetransferreg_in;
wire phaseinvertctrl_in;
wire devclrn_in, devpor_in;
assign phaseinvertctrl_in = (phaseinvertctrl === 1'b1) ? 1'b1 : 1'b0;
assign dqsenablein_in = (dqsenablein === 1'b1) ? 1'b1 : 1'b0;
assign clk_in = clk;
assign enaphasetransferreg_in = (enaphasetransferreg === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[5] = (delayctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[4] = (delayctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[3] = (delayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[2] = (delayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[1] = (delayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[0] = (delayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[3] = (phasectrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[2] = (phasectrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[1] = (phasectrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[0] = (phasectrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign devclrn_in = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign devpor_in = (devpor === 1'b0) ? 1'b0 : 1'b1;
// no top-level timing delays
// specify
// (dqsenablein => dqsenableout) = (0,0);
// endspecify
// delay chain
arriaiigz_ddr_delay_chain_s m_delay_chain(
.clk(clk_in),
.delayctrlin(delayctrlin_in),
.phasectrlin(phasectrlin_in),
.delayed_clkout(phasectrl_clkout)
);
defparam m_delay_chain.phase_setting = phase_setting;
defparam m_delay_chain.use_phasectrlin = use_phasectrlin;
defparam m_delay_chain.sim_buffer_intrinsic_delay = sim_intrinsic_delay;
defparam m_delay_chain.sim_buffer_delay_increment = sim_buffer_delay_increment;
assign delayed_clk = (invert_phase == "true") ? (~phasectrl_clkout) :
(invert_phase == "false") ? phasectrl_clkout :
(phaseinvertctrl_in === 1'b1) ? (~phasectrl_clkout) : phasectrl_clkout;
// disable data path
arriaiigz_ddr_io_reg dqsenablein_reg(
.d(dqsenablein_in),
.clk(clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(1'b0),
.asdata(1'b0),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(dqsenablein_reg_q)
);
arriaiigz_ddr_io_reg dqsenable_transfer_reg(
.d(dqsenablein_reg_q),
.clk(~delayed_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(1'b0),
.asdata(1'b0),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(dqsenablein_reg_dly)
);
// add phase transfer mux
assign phasetransferdelay_mux_out =
(add_phase_transfer_reg == "true") ? dqsenablein_reg_dly :
(add_phase_transfer_reg == "false") ? dqsenablein_reg_q :
(enaphasetransferreg_in === 1'b1) ? dqsenablein_reg_dly : dqsenablein_reg_q;
assign dqsenablein_level_ena = (level_dqs_enable == "true") ? phasetransferdelay_mux_out : dqsenablein_in;
arriaiigz_ddr_io_reg dqsenableout_reg(
.d(dqsenablein_level_ena),
.clk(delayed_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(1'b0),
.asdata(1'b0),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(dqsenable_delayed_regp)
);
arriaiigz_ddr_io_reg dqsenableout_extend_reg(
.d(dqsenable_delayed_regp),
.clk(~delayed_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(1'b0),
.asdata(1'b0),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(dqsenable_delayed_regn)
);
assign tmp_dqsenableout = (delay_dqs_enable_by_half_cycle == "false") ? dqsenable_delayed_regp
: (dqsenable_delayed_regp & dqsenable_delayed_regn);
assign dqsenableout = tmp_dqsenableout;
endmodule // arriaiigz_dqs_enable_ctrl
//-----------------------------------------------------------------------------
//
// Module Name : arriaiigz_delay_chain
//
// Description : ARRIAIIGZ Delay Chain (dynamic adjustable delay chain)
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_delay_chain (
datain,
delayctrlin,
finedelayctrlin,
devclrn,
devpor,
dataout
);
parameter sim_delayctrlin_rising_delay_0 = 0;
parameter sim_delayctrlin_rising_delay_1 = 50;
parameter sim_delayctrlin_rising_delay_2 = 100;
parameter sim_delayctrlin_rising_delay_3 = 150;
parameter sim_delayctrlin_rising_delay_4 = 200;
parameter sim_delayctrlin_rising_delay_5 = 250;
parameter sim_delayctrlin_rising_delay_6 = 300;
parameter sim_delayctrlin_rising_delay_7 = 350;
parameter sim_delayctrlin_rising_delay_8 = 400;
parameter sim_delayctrlin_rising_delay_9 = 450;
parameter sim_delayctrlin_rising_delay_10 = 500;
parameter sim_delayctrlin_rising_delay_11 = 550;
parameter sim_delayctrlin_rising_delay_12 = 600;
parameter sim_delayctrlin_rising_delay_13 = 650;
parameter sim_delayctrlin_rising_delay_14 = 700;
parameter sim_delayctrlin_rising_delay_15 = 750;
parameter sim_delayctrlin_falling_delay_0 = 0;
parameter sim_delayctrlin_falling_delay_1 = 50;
parameter sim_delayctrlin_falling_delay_2 = 100;
parameter sim_delayctrlin_falling_delay_3 = 150;
parameter sim_delayctrlin_falling_delay_4 = 200;
parameter sim_delayctrlin_falling_delay_5 = 250;
parameter sim_delayctrlin_falling_delay_6 = 300;
parameter sim_delayctrlin_falling_delay_7 = 350;
parameter sim_delayctrlin_falling_delay_8 = 400;
parameter sim_delayctrlin_falling_delay_9 = 450;
parameter sim_delayctrlin_falling_delay_10 = 500;
parameter sim_delayctrlin_falling_delay_11 = 550;
parameter sim_delayctrlin_falling_delay_12 = 600;
parameter sim_delayctrlin_falling_delay_13 = 650;
parameter sim_delayctrlin_falling_delay_14 = 700;
parameter sim_delayctrlin_falling_delay_15 = 750;
//new STRATIXIV - ww30.2008
parameter sim_finedelayctrlin_falling_delay_0 = 0 ;
parameter sim_finedelayctrlin_falling_delay_1 = 25 ;
parameter sim_finedelayctrlin_rising_delay_0 = 0 ;
parameter sim_finedelayctrlin_rising_delay_1 = 25 ;
parameter use_finedelayctrlin = "false";
parameter lpm_type = "arriaiigz_delay_chain";
// parameter removed in rev 1.23
parameter use_delayctrlin = "true";
parameter delay_setting = 0; // <0 - 15>
// INPUT PORTS
input datain;
input [3:0] delayctrlin;
input devclrn;
input devpor;
input finedelayctrlin; //new STRATIXIV - ww30.2008
// OUTPUT PORTS
output dataout;
tri1 devclrn;
tri1 devpor;
// delays
integer dly_table_rising[0:15];
integer dly_table_falling[0:15];
integer finedly_table_rising[0:1];
integer finedly_table_falling[0:1];
integer dly_setting;
integer rising_dly, falling_dly;
reg tmp_dataout;
//Buffer layers
wire datain_in;
wire [3:0] delayctrlin_in;
wire finedelayctrlin_in;
assign datain_in = datain;
specify
(datain => dataout) = (0,0);
endspecify
// filtering X/U etc.
assign delayctrlin_in[0] = (delayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[1] = (delayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[2] = (delayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[3] = (delayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign finedelayctrlin_in = (finedelayctrlin === 1'b1) ? 1'b1 : 1'b0;
initial
begin
dly_table_rising[0] = sim_delayctrlin_rising_delay_0;
dly_table_rising[1] = sim_delayctrlin_rising_delay_1;
dly_table_rising[2] = sim_delayctrlin_rising_delay_2;
dly_table_rising[3] = sim_delayctrlin_rising_delay_3;
dly_table_rising[4] = sim_delayctrlin_rising_delay_4;
dly_table_rising[5] = sim_delayctrlin_rising_delay_5;
dly_table_rising[6] = sim_delayctrlin_rising_delay_6;
dly_table_rising[7] = sim_delayctrlin_rising_delay_7;
dly_table_rising[8] = sim_delayctrlin_rising_delay_8;
dly_table_rising[9] = sim_delayctrlin_rising_delay_9;
dly_table_rising[10] = sim_delayctrlin_rising_delay_10;
dly_table_rising[11] = sim_delayctrlin_rising_delay_11;
dly_table_rising[12] = sim_delayctrlin_rising_delay_12;
dly_table_rising[13] = sim_delayctrlin_rising_delay_13;
dly_table_rising[14] = sim_delayctrlin_rising_delay_14;
dly_table_rising[15] = sim_delayctrlin_rising_delay_15;
dly_table_falling[0] = sim_delayctrlin_falling_delay_0;
dly_table_falling[1] = sim_delayctrlin_falling_delay_1;
dly_table_falling[2] = sim_delayctrlin_falling_delay_2;
dly_table_falling[3] = sim_delayctrlin_falling_delay_3;
dly_table_falling[4] = sim_delayctrlin_falling_delay_4;
dly_table_falling[5] = sim_delayctrlin_falling_delay_5;
dly_table_falling[6] = sim_delayctrlin_falling_delay_6;
dly_table_falling[7] = sim_delayctrlin_falling_delay_7;
dly_table_falling[8] = sim_delayctrlin_falling_delay_8;
dly_table_falling[9] = sim_delayctrlin_falling_delay_9;
dly_table_falling[10] = sim_delayctrlin_falling_delay_10;
dly_table_falling[11] = sim_delayctrlin_falling_delay_11;
dly_table_falling[12] = sim_delayctrlin_falling_delay_12;
dly_table_falling[13] = sim_delayctrlin_falling_delay_13;
dly_table_falling[14] = sim_delayctrlin_falling_delay_14;
dly_table_falling[15] = sim_delayctrlin_falling_delay_15;
finedly_table_rising[0] = sim_finedelayctrlin_rising_delay_0;
finedly_table_rising[1] = sim_finedelayctrlin_rising_delay_1;
finedly_table_falling[0] = sim_finedelayctrlin_falling_delay_0;
finedly_table_falling[1] = sim_finedelayctrlin_falling_delay_1;
dly_setting = 0;
rising_dly = 0;
falling_dly = 0;
tmp_dataout = 1'bx;
end
always @(delayctrlin_in or finedelayctrlin_in)
begin
if (use_delayctrlin == "false")
dly_setting = delay_setting;
else
dly_setting = delayctrlin_in;
if (use_finedelayctrlin == "true")
begin
rising_dly = dly_table_rising[dly_setting] + finedly_table_rising[finedelayctrlin_in];
falling_dly = dly_table_falling[dly_setting] + finedly_table_falling[finedelayctrlin_in];
end
else
begin
rising_dly = dly_table_rising[dly_setting];
falling_dly = dly_table_falling[dly_setting];
end
end
always @(datain_in)
begin
if (datain_in === 1'b0)
tmp_dataout <= #(falling_dly) datain_in;
else
tmp_dataout <= #(rising_dly) datain_in;
end
assign dataout = tmp_dataout;
endmodule // arriaiigz_delay_chain
//-----------------------------------------------------------------------------
//
// Module Name : arriaiigz_io_clock_divider
//
// Description : ARRIAIIGZ I/O Clock Divider
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_io_clock_divider (
clk,
phaseselect,
delayctrlin,
phasectrlin,
masterin,
phaseinvertctrl,
devclrn,
devpor,
clkout,
slaveout
);
parameter use_phasectrlin = "true";
parameter phase_setting = 0; // <0 - 7>
parameter delay_buffer_mode = "high";
parameter use_masterin = "false"; // new in 1.19
parameter invert_phase = "false";
parameter sim_low_buffer_intrinsic_delay = 350;
parameter sim_high_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
parameter lpm_type = "arriaiigz_io_clock_divider";
// INPUT PORTS
input clk;
input phaseselect;
input [5:0] delayctrlin;
input [3:0] phasectrlin;
input phaseinvertctrl;
input masterin;
input devclrn;
input devpor;
// OUTPUT PORTS
output clkout;
output slaveout;
// LOCAL_PARAMETERS_BEGIN
parameter sim_intrinsic_delay = (delay_buffer_mode == "low") ? sim_low_buffer_intrinsic_delay :
sim_high_buffer_intrinsic_delay;
// LOCAL_PARAMETERS_END
tri1 devclrn;
tri1 devpor;
// int signals
wire phasectrl_clkout;
wire delayed_clk;
wire divided_clk_in;
reg divided_clk;
wire tmp_clkout;
// input buffer layer
wire clk_in, phaseselect_in;
wire [5:0] delayctrlin_in;
wire [3:0] phasectrlin_in;
wire masterin_in;
wire phaseinvertctrl_in;
assign clk_in = clk;
assign phaseselect_in = (phaseselect === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[5] = (delayctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[4] = (delayctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[3] = (delayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[2] = (delayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[1] = (delayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[0] = (delayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[3] = (phasectrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[2] = (phasectrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[1] = (phasectrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[0] = (phasectrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign masterin_in = masterin;
assign phaseinvertctrl_in = (phaseinvertctrl === 1'b1) ? 1'b1 : 1'b0;
specify
(clk => clkout) = (0,0);
endspecify
// delay chain
arriaiigz_ddr_delay_chain_s m_delay_chain(
.clk(clk_in),
.delayctrlin(delayctrlin_in),
.phasectrlin(phasectrlin_in),
.delayed_clkout(phasectrl_clkout)
);
defparam m_delay_chain.phase_setting = phase_setting;
defparam m_delay_chain.use_phasectrlin = use_phasectrlin;
defparam m_delay_chain.sim_buffer_intrinsic_delay = sim_intrinsic_delay;
defparam m_delay_chain.sim_buffer_delay_increment = sim_buffer_delay_increment;
defparam m_delay_chain.phasectrlin_limit = 7;
assign delayed_clk = (invert_phase == "true") ? (~phasectrl_clkout) :
(invert_phase == "false") ? phasectrl_clkout :
(phaseinvertctrl_in === 1'b1) ? (~phasectrl_clkout) : phasectrl_clkout;
initial
divided_clk = 1'b0;
assign divided_clk_in = (use_masterin == "true") ? masterin_in : divided_clk;
always @(posedge delayed_clk)
begin
if (delayed_clk == 'b1)
divided_clk <= ~divided_clk_in;
end
assign tmp_clkout = (phaseselect_in === 1'b1) ? ~divided_clk : divided_clk;
assign clkout = tmp_clkout;
assign slaveout = divided_clk;
endmodule // arriaiigz_io_clock_divider
//-----------------------------------------------------------------------------
//
// Module Name : arriaiigz_output_phase_alignment
//
// Description : output phase alignment
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_output_phase_alignment (
datain,
clk,
delayctrlin,
phasectrlin,
areset,
sreset,
clkena,
enaoutputcycledelay,
enaphasetransferreg,
phaseinvertctrl,
delaymode,
dutycycledelayctrlin,
devclrn,
devpor,
dffin,
dff1t,
dffddiodataout,
dataout
);
parameter operation_mode = "ddio_out";
parameter use_phasectrlin = "true";
parameter phase_setting = 0; // <0..10>
parameter delay_buffer_mode = "high";
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter add_output_cycle_delay = "false";
parameter use_delayed_clock = "false"; // new in 1.21
parameter add_phase_transfer_reg = "false"; // <false,true,dynamic>
parameter use_phasectrl_clock = "true"; // new in 1.21
parameter use_primary_clock = "true"; // new in 1.21
parameter invert_phase = "false"; // new in 1.26
parameter phase_setting_for_delayed_clock = 2; // new in 1.28
parameter bypass_input_register = "false"; // new in 1.36
parameter sim_low_buffer_intrinsic_delay = 350;
parameter sim_high_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
// new in STRATIXIV: ww30.2008
parameter duty_cycle_delay_mode = "none";
parameter sim_dutycycledelayctrlin_falling_delay_0 = 0 ;
parameter sim_dutycycledelayctrlin_falling_delay_1 = 25 ;
parameter sim_dutycycledelayctrlin_falling_delay_10 = 250 ;
parameter sim_dutycycledelayctrlin_falling_delay_11 = 275 ;
parameter sim_dutycycledelayctrlin_falling_delay_12 = 300 ;
parameter sim_dutycycledelayctrlin_falling_delay_13 = 325 ;
parameter sim_dutycycledelayctrlin_falling_delay_14 = 350 ;
parameter sim_dutycycledelayctrlin_falling_delay_15 = 375 ;
parameter sim_dutycycledelayctrlin_falling_delay_2 = 50 ;
parameter sim_dutycycledelayctrlin_falling_delay_3 = 75 ;
parameter sim_dutycycledelayctrlin_falling_delay_4 = 100 ;
parameter sim_dutycycledelayctrlin_falling_delay_5 = 125 ;
parameter sim_dutycycledelayctrlin_falling_delay_6 = 150 ;
parameter sim_dutycycledelayctrlin_falling_delay_7 = 175 ;
parameter sim_dutycycledelayctrlin_falling_delay_8 = 200 ;
parameter sim_dutycycledelayctrlin_falling_delay_9 = 225 ;
parameter sim_dutycycledelayctrlin_rising_delay_0 = 0 ;
parameter sim_dutycycledelayctrlin_rising_delay_1 = 25 ;
parameter sim_dutycycledelayctrlin_rising_delay_10 = 250 ;
parameter sim_dutycycledelayctrlin_rising_delay_11 = 275 ;
parameter sim_dutycycledelayctrlin_rising_delay_12 = 300 ;
parameter sim_dutycycledelayctrlin_rising_delay_13 = 325 ;
parameter sim_dutycycledelayctrlin_rising_delay_14 = 350 ;
parameter sim_dutycycledelayctrlin_rising_delay_15 = 375 ;
parameter sim_dutycycledelayctrlin_rising_delay_2 = 50 ;
parameter sim_dutycycledelayctrlin_rising_delay_3 = 75 ;
parameter sim_dutycycledelayctrlin_rising_delay_4 = 100 ;
parameter sim_dutycycledelayctrlin_rising_delay_5 = 125 ;
parameter sim_dutycycledelayctrlin_rising_delay_6 = 150 ;
parameter sim_dutycycledelayctrlin_rising_delay_7 = 175 ;
parameter sim_dutycycledelayctrlin_rising_delay_8 = 200 ;
parameter sim_dutycycledelayctrlin_rising_delay_9 = 225 ;
parameter lpm_type = "arriaiigz_output_phase_alignment";
// INPUT PORTS
input [1:0] datain;
input clk;
input [5:0] delayctrlin;
input [3:0] phasectrlin;
input areset;
input sreset;
input clkena;
input enaoutputcycledelay;
input enaphasetransferreg;
input phaseinvertctrl;
// new in STRATIXIV: ww30.2008
input delaymode;
input [3:0] dutycycledelayctrlin;
input devclrn;
input devpor;
// OUTPUT PORTS
output dataout;
output [1:0] dffin; // buried port
output [1:0] dff1t; // buried port
output dffddiodataout; // buried port
// LOCAL_PARAMETERS_BEGIN
parameter sim_intrinsic_delay = (delay_buffer_mode == "low") ? sim_low_buffer_intrinsic_delay
: sim_high_buffer_intrinsic_delay;
// LOCAL_PARAMETERS_END
tri1 devclrn;
tri1 devpor;
// int signals on clock paths
wire clk_in_delayed;
wire clk_in_mux;
wire phasectrl_clkout;
wire phaseinvertctrl_out;
// IO registers
// common
reg adatasdata_in_r; //sync reset - common for transfer and output reg
reg sclr_in_r;
reg sload_in_r;
wire sclr_in;
wire sload_in;
wire adatasdata_in;
reg clrn_in_r; //async reset - common for all registers
reg prn_in_r;
wire datain_q;
wire ddio_datain_q;
wire cycledelay_q;
wire ddio_cycledelay_q;
wire cycledelay_mux_out;
wire ddio_cycledelay_mux_out;
wire bypass_input_reg_mux_out;
wire ddio_bypass_input_reg_mux_out;
// transfer delay now by negative clk
wire transfer_q;
wire ddio_transfer_q;
// Duty Cycle Delay
wire dcd_in;
wire dcd_out;
wire dcd_both;
reg dcd_both_gnd;
reg dcd_both_vcc;
wire dcd_fallnrise;
reg dcd_fallnrise_gnd;
reg dcd_fallnrise_vcc;
integer dcd_table_rising[0:15];
integer dcd_table_falling[0:15];
integer dcd_dly_setting;
integer dcd_rising_dly;
integer dcd_falling_dly;
wire dlyclk_clk;
wire dlyclk_d;
wire dlyclk_q;
wire ddio_dlyclk_d;
wire ddio_dlyclk_q;
wire ddio_out_clk_mux;
wire ddio_out_lo_q;
wire ddio_out_hi_q;
wire dlyclk_clkena_in; // shared
wire dlyclk_extended_q;
wire dlyclk_extended_clk;
wire normal_dataout;
wire extended_dataout;
wire ddio_dataout;
wire tmp_dataout;
// buffer layer
wire [1:0] datain_in;
wire clk_in;
wire [5:0] delayctrlin_in;
wire [3:0] phasectrlin_in;
wire areset_in;
wire sreset_in;
wire clkena_in;
wire enaoutputcycledelay_in;
wire enaphasetransferreg_in;
wire devclrn_in, devpor_in;
wire phaseinvertctrl_in;
wire delaymode_in;
wire [3:0] dutycycledelayctrlin_in;
assign devclrn_in = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign devpor_in = (devpor === 1'b0) ? 1'b0 : 1'b1;
assign datain_in = datain;
assign clk_in = clk;
assign delayctrlin_in[5] = (delayctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[4] = (delayctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[3] = (delayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[2] = (delayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[1] = (delayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[0] = (delayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[3] = (phasectrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[2] = (phasectrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[1] = (phasectrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[0] = (phasectrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign areset_in = (areset === 1'b1) ? 1'b1 : 1'b0;
assign sreset_in = (sreset === 1'b1) ? 1'b1 : 1'b0;
assign clkena_in = (clkena === 1'b1) ? 1'b1 : 1'b0;
assign enaoutputcycledelay_in = (enaoutputcycledelay === 1'b1) ? 1'b1 : 1'b0;
assign enaphasetransferreg_in = (enaphasetransferreg === 1'b1) ? 1'b1 : 1'b0;
assign phaseinvertctrl_in = (phaseinvertctrl === 1'b1) ? 1'b1 : 1'b0;
assign delaymode_in = (delaymode === 1'b1) ? 1'b1 : 1'b0;
assign dutycycledelayctrlin_in[0] = (dutycycledelayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign dutycycledelayctrlin_in[1] = (dutycycledelayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign dutycycledelayctrlin_in[2] = (dutycycledelayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign dutycycledelayctrlin_in[3] = (dutycycledelayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
// delay chain for clk_in delay
arriaiigz_ddr_delay_chain_s m_clk_in_delay_chain(
.clk(clk_in),
.delayctrlin(delayctrlin_in),
.phasectrlin(phasectrlin_in),
.delayed_clkout(clk_in_delayed)
);
defparam m_clk_in_delay_chain.phase_setting = phase_setting_for_delayed_clock;
defparam m_clk_in_delay_chain.use_phasectrlin = "false";
defparam m_clk_in_delay_chain.sim_buffer_intrinsic_delay = sim_intrinsic_delay;
defparam m_clk_in_delay_chain.sim_buffer_delay_increment = sim_buffer_delay_increment;
// clock source for datain and cycle delay registers
assign clk_in_mux = (use_delayed_clock == "true") ? clk_in_delayed : clk_in;
// delay chain for phase control
arriaiigz_ddr_delay_chain_s m_delay_chain(
.clk(clk_in),
.delayctrlin(delayctrlin_in),
.phasectrlin(phasectrlin_in),
.delayed_clkout(phasectrl_clkout)
);
defparam m_delay_chain.phase_setting = phase_setting;
defparam m_delay_chain.use_phasectrlin = use_phasectrlin;
defparam m_delay_chain.sim_buffer_intrinsic_delay = sim_intrinsic_delay;
defparam m_delay_chain.sim_buffer_delay_increment = sim_buffer_delay_increment;
defparam m_delay_chain.phasectrlin_limit = (use_primary_clock == "true") ? 10 : 7;
// primary outputs
assign normal_dataout = dlyclk_q;
assign extended_dataout = dlyclk_q | dlyclk_extended_q; // oe port is active low
assign ddio_dataout = (ddio_out_clk_mux === 1'b1) ? ddio_out_hi_q : ddio_out_lo_q;
assign tmp_dataout = (operation_mode == "ddio_out") ? ddio_dataout :
(operation_mode == "extended_oe" || operation_mode == "extended_rtena") ? extended_dataout :
(operation_mode == "output" || operation_mode == "oe" || operation_mode == "rtena") ? normal_dataout
: 1'bz;
assign dataout = tmp_dataout;
assign #1 ddio_out_clk_mux = dlyclk_clk; // symbolic T4 to remove glitch on data_h
assign #2 ddio_out_lo_q = dlyclk_q; // symbolic 2 T4 to remove glitch on data_l
assign ddio_out_hi_q = ddio_dlyclk_q;
// resolve reset/areset modes
initial begin
adatasdata_in_r = (sync_mode == "preset") ? 1'b1: 1'b0;
sclr_in_r = 1'b0;
sload_in_r = 1'b0;
clrn_in_r = 1'b1;
prn_in_r = 1'b1;
end
always @(areset_in)
begin
if (async_mode == "clear")
begin
clrn_in_r = ~areset_in;
end
else if (async_mode == "preset")
begin
prn_in_r = ~areset_in;
end
end
always @(sreset_in)
begin
if (sync_mode == "clear")
begin
sclr_in_r = sreset_in;
end
else if(sync_mode == "preset")
begin
sload_in_r = sreset_in;
end
end
assign sclr_in = (operation_mode == "rtena" || operation_mode == "extended_rtena") ? 1'b0 : sclr_in_r;
assign sload_in = (operation_mode == "rtena" || operation_mode == "extended_rtena") ? 1'b0 : sload_in_r;
assign adatasdata_in = adatasdata_in_r;
assign dlyclk_clkena_in = (operation_mode == "rtena" || operation_mode == "extended_rtena") ? 1'b1 : clkena_in;
// Datain Register
arriaiigz_ddr_io_reg datain_reg(
.d(datain_in[0]),
.clk(clk_in_mux),
.ena(1'b1),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(datain_q)
);
defparam datain_reg.power_up = power_up;
// DDIO Datain Register
arriaiigz_ddr_io_reg ddio_datain_reg(
.d(datain_in[1]),
.clk(clk_in_mux),
.ena(1'b1),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(ddio_datain_q)
);
defparam ddio_datain_reg.power_up = power_up;
// Cycle Delay Register
arriaiigz_ddr_io_reg cycledelay_reg(
.d(datain_q),
.clk(clk_in_mux),
.ena(1'b1),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(cycledelay_q)
);
defparam cycledelay_reg.power_up = power_up;
// DDIO Cycle Delay Register
arriaiigz_ddr_io_reg ddio_cycledelay_reg(
.d(ddio_datain_q),
.clk(clk_in_mux),
.ena(1'b1),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(ddio_cycledelay_q)
);
defparam ddio_cycledelay_reg.power_up = power_up;
// enaoutputcycledelay data path mux
assign cycledelay_mux_out = (add_output_cycle_delay == "true") ? cycledelay_q :
(add_output_cycle_delay == "false") ? datain_q :
(enaoutputcycledelay_in === 1'b1) ? cycledelay_q : datain_q;
// input register bypass mux
assign bypass_input_reg_mux_out = (bypass_input_register == "true") ? datain_in[0] : cycledelay_mux_out;
//assign #300 transfer_q = cycledelay_mux_out;
// transfer delay is implemented with negative register in rev1.26
arriaiigz_ddr_io_reg transferdelay_reg(
.d(bypass_input_reg_mux_out),
.clk(~clk_in_mux),
.ena(1'b1),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(sclr_in),
.sload(sload_in),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(transfer_q)
);
defparam transferdelay_reg.power_up = power_up;
// add phase transfer (true/false/dynamic) data path mux
assign dlyclk_d = (add_phase_transfer_reg == "true") ? transfer_q :
(add_phase_transfer_reg == "false") ? bypass_input_reg_mux_out :
(enaphasetransferreg_in === 1'b1) ? transfer_q : bypass_input_reg_mux_out;
// clock mux for the output register
assign phaseinvertctrl_out = (invert_phase == "true") ? (~phasectrl_clkout) :
(invert_phase == "false") ? phasectrl_clkout :
(phaseinvertctrl_in === 1'b1) ? (~phasectrl_clkout) : phasectrl_clkout;
// Duty Cycle Delay
assign dcd_in = (use_phasectrl_clock == "true") ? phaseinvertctrl_out : clk_in_mux;
initial
begin
dcd_table_rising[0] = sim_dutycycledelayctrlin_rising_delay_0;
dcd_table_rising[1] = sim_dutycycledelayctrlin_rising_delay_1;
dcd_table_rising[2] = sim_dutycycledelayctrlin_rising_delay_2;
dcd_table_rising[3] = sim_dutycycledelayctrlin_rising_delay_3;
dcd_table_rising[4] = sim_dutycycledelayctrlin_rising_delay_4;
dcd_table_rising[5] = sim_dutycycledelayctrlin_rising_delay_5;
dcd_table_rising[6] = sim_dutycycledelayctrlin_rising_delay_6;
dcd_table_rising[7] = sim_dutycycledelayctrlin_rising_delay_7;
dcd_table_rising[8] = sim_dutycycledelayctrlin_rising_delay_8;
dcd_table_rising[9] = sim_dutycycledelayctrlin_rising_delay_9;
dcd_table_rising[10] = sim_dutycycledelayctrlin_rising_delay_10;
dcd_table_rising[11] = sim_dutycycledelayctrlin_rising_delay_11;
dcd_table_rising[12] = sim_dutycycledelayctrlin_rising_delay_12;
dcd_table_rising[13] = sim_dutycycledelayctrlin_rising_delay_13;
dcd_table_rising[14] = sim_dutycycledelayctrlin_rising_delay_14;
dcd_table_rising[15] = sim_dutycycledelayctrlin_rising_delay_15;
dcd_table_falling[0] = sim_dutycycledelayctrlin_falling_delay_0;
dcd_table_falling[1] = sim_dutycycledelayctrlin_falling_delay_1;
dcd_table_falling[2] = sim_dutycycledelayctrlin_falling_delay_2;
dcd_table_falling[3] = sim_dutycycledelayctrlin_falling_delay_3;
dcd_table_falling[4] = sim_dutycycledelayctrlin_falling_delay_4;
dcd_table_falling[5] = sim_dutycycledelayctrlin_falling_delay_5;
dcd_table_falling[6] = sim_dutycycledelayctrlin_falling_delay_6;
dcd_table_falling[7] = sim_dutycycledelayctrlin_falling_delay_7;
dcd_table_falling[8] = sim_dutycycledelayctrlin_falling_delay_8;
dcd_table_falling[9] = sim_dutycycledelayctrlin_falling_delay_9;
dcd_table_falling[10] = sim_dutycycledelayctrlin_falling_delay_10;
dcd_table_falling[11] = sim_dutycycledelayctrlin_falling_delay_11;
dcd_table_falling[12] = sim_dutycycledelayctrlin_falling_delay_12;
dcd_table_falling[13] = sim_dutycycledelayctrlin_falling_delay_13;
dcd_table_falling[14] = sim_dutycycledelayctrlin_falling_delay_14;
dcd_table_falling[15] = sim_dutycycledelayctrlin_falling_delay_15;
dcd_dly_setting = 0;
dcd_rising_dly = 0;
dcd_falling_dly = 0;
end
always @(dutycycledelayctrlin_in)
begin
dcd_dly_setting = dutycycledelayctrlin_in;
dcd_rising_dly = dcd_table_rising[dcd_dly_setting];
dcd_falling_dly = dcd_table_falling[dcd_dly_setting];
end
always @(dcd_in)
begin
dcd_both_gnd <= dcd_in;
if (dcd_in === 1'b0)
begin
dcd_both_vcc <= #(dcd_falling_dly) dcd_in;
dcd_fallnrise_gnd <= #(dcd_falling_dly) dcd_in;
dcd_fallnrise_vcc <= dcd_in;
end
else
begin
dcd_both_vcc <= #(dcd_rising_dly) dcd_in;
dcd_fallnrise_gnd <= dcd_in;
dcd_fallnrise_vcc <= #(dcd_rising_dly) dcd_in;
end
end
assign dcd_both = (delaymode_in === 1'b1) ? dcd_both_vcc : dcd_both_gnd;
assign dcd_fallnrise = (delaymode_in === 1'b1) ? dcd_fallnrise_vcc : dcd_fallnrise_gnd;
assign dlyclk_clk = (duty_cycle_delay_mode == "both") ? dcd_both :
(duty_cycle_delay_mode == "fallnrise") ? dcd_fallnrise : dcd_in;
// Output Register clocked by phasectrl_clk
arriaiigz_ddr_io_reg dlyclk_reg(
.d(dlyclk_d),
.clk(dlyclk_clk),
.ena(dlyclk_clkena_in),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(sclr_in),
.sload(sload_in),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(dlyclk_q)
);
defparam dlyclk_reg.power_up = power_up;
// enaoutputcycledelay data path mux - DDIO
assign ddio_cycledelay_mux_out = (add_output_cycle_delay == "true") ? ddio_cycledelay_q :
(add_output_cycle_delay == "false") ? ddio_datain_q :
(enaoutputcycledelay_in === 1'b1) ? ddio_cycledelay_q : ddio_datain_q;
// input register bypass mux
assign ddio_bypass_input_reg_mux_out = (bypass_input_register == "true") ? datain_in[1] : ddio_cycledelay_mux_out;
//assign #300 ddio_transfer_q = ddio_cycledelay_mux_out;
// transfer delay is implemented with negative register in rev1.26
arriaiigz_ddr_io_reg ddio_transferdelay_reg(
.d(ddio_bypass_input_reg_mux_out),
.clk(~clk_in_mux),
.ena(1'b1),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(sclr_in),
.sload(sload_in),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(ddio_transfer_q)
);
defparam ddio_transferdelay_reg.power_up = power_up;
// add phase transfer data path mux
assign ddio_dlyclk_d = (add_phase_transfer_reg == "true") ? ddio_transfer_q :
(add_phase_transfer_reg == "false") ? ddio_bypass_input_reg_mux_out :
(enaphasetransferreg_in === 1'b1) ? ddio_transfer_q : ddio_bypass_input_reg_mux_out;
// Output Register clocked by phasectrl_clk
arriaiigz_ddr_io_reg ddio_dlyclk_reg(
.d(ddio_dlyclk_d),
.clk(dlyclk_clk),
.ena(dlyclk_clkena_in),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(sclr_in),
.sload(sload_in),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(ddio_dlyclk_q)
);
defparam ddio_dlyclk_reg.power_up = power_up;
// Extension Register
assign dlyclk_extended_clk = ~dlyclk_clk;
arriaiigz_ddr_io_reg dlyclk_extended_reg(
.d(dlyclk_q),
.clk(dlyclk_extended_clk),
.ena(dlyclk_clkena_in),
.clrn(clrn_in_r),
.prn(prn_in_r),
.aload(1'b0),
.asdata(adatasdata_in),
.sclr(sclr_in),
.sload(sload_in),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(dlyclk_extended_q)
);
defparam dlyclk_extended_reg.power_up = power_up;
endmodule // arriaiigz_output_phase_alignment
//-----------------------------------------------------------------------------
//
// Module Name : arriaiigz_input_phase_alignment
//
// Description : input phase alignment
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_input_phase_alignment (
datain,
clk,
delayctrlin,
phasectrlin,
areset,
enainputcycledelay,
enaphasetransferreg, // new in 1.19
phaseinvertctrl,
devclrn,
devpor,
dffin,
dff1t,
dataout
);
parameter use_phasectrlin = "true";
parameter phase_setting = 0;
parameter delay_buffer_mode = "high";
parameter power_up = "low";
parameter async_mode = "none";
parameter add_input_cycle_delay = "false";
parameter bypass_output_register = "false";
parameter add_phase_transfer_reg = "false"; // new in 1.19
parameter invert_phase = "false"; // new in 1.26
parameter sim_low_buffer_intrinsic_delay = 350;
parameter sim_high_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
parameter lpm_type = "arriaiigz_input_phase_alignment";
input datain;
input clk;
input [5:0] delayctrlin;
input [3:0] phasectrlin;
input areset;
input enainputcycledelay;
input enaphasetransferreg;
input phaseinvertctrl;
input devclrn;
input devpor;
output dataout;
output dffin; // buried port
output dff1t; // buried port
// LOCAL_PARAMETERS_BEGIN
parameter sim_intrinsic_delay = (delay_buffer_mode == "low") ? sim_low_buffer_intrinsic_delay
: sim_high_buffer_intrinsic_delay;
// LOCAL_PARAMETERS_END
tri1 devclrn;
tri1 devpor;
// int signals
wire phasectrl_clkout;
wire delayed_clk;
// IO registers
// common
reg adatasdata_in_r;
reg aload_in_r;
wire datain_q;
wire cycledelay_q;
wire cycledelay_mux_out;
wire cycledelay_mux_out_dly;
wire dlyclk_d;
wire dlyclk_q;
wire tmp_dataout;
// buffer layer
wire datain_in;
wire clk_in;
wire [5:0] delayctrlin_in;
wire [3:0] phasectrlin_in;
wire areset_in;
wire enainputcycledelay_in;
wire enaphasetransferreg_in;
wire devclrn_in, devpor_in;
wire phaseinvertctrl_in;
assign phaseinvertctrl_in = (phaseinvertctrl === 1'b1) ? 1'b1 : 1'b0;
assign datain_in = (datain === 1'b1) ? 1'b1 : 1'b0;
assign clk_in = clk;
assign areset_in = (areset === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[5] = (delayctrlin[5] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[4] = (delayctrlin[4] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[3] = (delayctrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[2] = (delayctrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[1] = (delayctrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign delayctrlin_in[0] = (delayctrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[3] = (phasectrlin[3] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[2] = (phasectrlin[2] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[1] = (phasectrlin[1] === 1'b1) ? 1'b1 : 1'b0;
assign phasectrlin_in[0] = (phasectrlin[0] === 1'b1) ? 1'b1 : 1'b0;
assign enainputcycledelay_in = (enainputcycledelay === 1'b1) ? 1'b1 : 1'b0;
assign enaphasetransferreg_in = (enaphasetransferreg === 1'b1) ? 1'b1 : 1'b0;
assign devclrn_in = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign devpor_in = (devpor === 1'b0) ? 1'b0 : 1'b1;
// delay chain
arriaiigz_ddr_delay_chain_s m_delay_chain(
.clk(clk_in),
.delayctrlin(delayctrlin_in),
.phasectrlin(phasectrlin_in),
.delayed_clkout(phasectrl_clkout)
);
defparam m_delay_chain.phase_setting = phase_setting;
defparam m_delay_chain.use_phasectrlin = use_phasectrlin;
defparam m_delay_chain.sim_buffer_intrinsic_delay = sim_intrinsic_delay;
defparam m_delay_chain.sim_buffer_delay_increment = sim_buffer_delay_increment;
defparam m_delay_chain.phasectrlin_limit = 7;
assign delayed_clk = (invert_phase == "true") ? (~phasectrl_clkout) :
(invert_phase == "false") ? phasectrl_clkout :
(phaseinvertctrl_in === 1'b1) ? (~phasectrl_clkout) : phasectrl_clkout;
// primary output
assign dataout = tmp_dataout;
assign tmp_dataout = (bypass_output_register == "true") ? dlyclk_d : dlyclk_q;
// add phase transfer data path mux
assign dlyclk_d = (add_phase_transfer_reg == "true") ? cycledelay_mux_out_dly :
(add_phase_transfer_reg == "false") ? cycledelay_mux_out :
(enaphasetransferreg_in === 1'b1) ? cycledelay_mux_out_dly : cycledelay_mux_out;
// enaoutputcycledelay data path mux
assign cycledelay_mux_out = (add_input_cycle_delay == "true") ? cycledelay_q :
(add_input_cycle_delay == "false") ? datain_q :
(enainputcycledelay_in === 1'b1) ? cycledelay_q : datain_q;
// resolve reset modes
always @(areset_in)
begin
if(async_mode == "clear")
begin
aload_in_r = areset_in;
adatasdata_in_r = 1'b0;
end
else if(async_mode == "preset")
begin
aload_in_r = areset_in;
adatasdata_in_r = 1'b1;
end
else // async_mode == "none"
begin
aload_in_r = 1'b0;
adatasdata_in_r = 1'b0;
end
end
// Datain Register
arriaiigz_ddr_io_reg datain_reg(
.d(datain_in),
.clk(delayed_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(datain_q)
);
defparam datain_reg.power_up = power_up;
// Cycle Delay Register
arriaiigz_ddr_io_reg cycledelay_reg(
.d(datain_q),
.clk(delayed_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(cycledelay_q)
);
defparam cycledelay_reg.power_up = power_up;
// assign #300 cycledelay_mux_out_dly = cycledelay_mux_out; replaced by neg reg
// Transfer Register - clocked by negative edge
arriaiigz_ddr_io_reg transfer_reg(
.d(cycledelay_mux_out),
.clk(~delayed_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(cycledelay_mux_out_dly)
);
defparam transfer_reg.power_up = power_up;
// Register clocked by actually by clk_in
arriaiigz_ddr_io_reg dlyclk_reg(
.d(dlyclk_d),
.clk(clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(dlyclk_q)
);
defparam dlyclk_reg.power_up = power_up;
endmodule // arriaiigz_input_phase_alignment
//-----------------------------------------------------------------------------
//
// Module Name : arriaiigz_half_rate_input
//
// Description : ARRIAIIGZ half rate input
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_half_rate_input (
datain,
directin,
clk,
areset,
dataoutbypass,
devclrn,
devpor,
dffin,
dataout
);
parameter power_up = "low";
parameter async_mode = "none";
parameter use_dataoutbypass = "false";
parameter lpm_type = "arriaiigz_half_rate_input";
input [1:0] datain;
input directin;
input clk;
input areset;
input dataoutbypass;
input devclrn;
input devpor;
output [3:0] dataout;
output [1:0] dffin; // buried
tri1 devclrn;
tri1 devpor;
// delayed version to ensure one cycle of latency in functional as expected
wire [1:0] datain_in;
// IO registers
// common
wire neg_clk_in;
reg adatasdata_in_r;
reg aload_in_r;
// low_bank = {1, 0} - capturing datain at falling edge then sending at falling rise
// high_bank = {3, 2} - output of register datain at rising
wire [1:0] high_bank;
wire [1:0] low_bank;
wire low_bank_low;
wire low_bank_high;
wire high_bank_low;
wire high_bank_high;
wire [1:0] dataout_reg_n;
wire [3:0] tmp_dataout;
// buffer layer
wire [1:0] datain_ipd;
wire directin_in;
wire clk_in;
wire areset_in;
wire dataoutbypass_in;
wire devclrn_in, devpor_in;
assign datain_ipd = datain;
assign directin_in = directin;
assign clk_in = clk;
assign areset_in = (areset === 1'b1) ? 1'b1 : 1'b0;
assign dataoutbypass_in = (dataoutbypass === 1'b1) ? 1'b1 : 1'b0;
assign devclrn_in = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign devpor_in = (devpor === 1'b0) ? 1'b0 : 1'b1;
// primary input
assign #2 datain_in = datain_ipd;
// primary output
assign dataout = tmp_dataout;
assign tmp_dataout[3] = (dataoutbypass_in === 1'b0 && use_dataoutbypass == "true") ? directin_in : high_bank_high;
assign tmp_dataout[2] = (dataoutbypass_in === 1'b0 && use_dataoutbypass == "true") ? directin_in : high_bank_low;
assign tmp_dataout[1] = low_bank[1];
assign tmp_dataout[0] = low_bank[0];
assign low_bank = {low_bank_high, low_bank_low};
assign high_bank = {high_bank_high, high_bank_low};
// resolve reset modes
always @(areset_in)
begin
if(async_mode == "clear")
begin
aload_in_r = areset_in;
adatasdata_in_r = 1'b0;
end
else if(async_mode == "preset")
begin
aload_in_r = areset_in;
adatasdata_in_r = 1'b1;
end
else // async_mode == "none"
begin
aload_in_r = 1'b0;
adatasdata_in_r = 1'b0;
end
end
assign neg_clk_in = ~clk_in;
// datain_1 - H
arriaiigz_ddr_io_reg reg1_h(
.d(datain_in[1]),
.clk(clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(high_bank_high)
);
defparam reg1_h.power_up = power_up;
// datain_0 - H
arriaiigz_ddr_io_reg reg0_h(
.d(datain_in[0]),
.clk(clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(high_bank_low)
);
defparam reg0_h.power_up = power_up;
// datain_1 - L (n)
arriaiigz_ddr_io_reg reg1_l_n(
.d(datain_in[1]),
.clk(neg_clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(dataout_reg_n[1])
);
defparam reg1_l_n.power_up = power_up;
// datain_1 - L
arriaiigz_ddr_io_reg reg1_l(
.d(dataout_reg_n[1]),
.clk(clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(low_bank_high)
);
defparam reg1_l.power_up = power_up;
// datain_0 - L (n)
arriaiigz_ddr_io_reg reg0_l_n(
.d(datain_in[0]),
.clk(neg_clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b1),
.q(dataout_reg_n[0])
);
defparam reg0_l_n.power_up = power_up;
// datain_0 - L
arriaiigz_ddr_io_reg reg0_l(
.d(dataout_reg_n[0]),
.clk(clk_in),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.aload(aload_in_r),
.asdata(adatasdata_in_r),
.sclr(1'b0),
.sload(1'b0),
.devclrn(devclrn_in),
.devpor(devpor_in),
.rpt_violation(1'b0),
.q(low_bank_low)
);
defparam reg0_l.power_up = power_up;
endmodule // arriaiigz_half_rate_input
//-----------------------------------------------------------------------------
//
// Module Name : arriaiigz_io_config
//
// Description : ARRIAIIGZ I/O Configuration Register
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_io_config (
datain,
clk,
ena,
update,
devclrn,
devpor,
padtoinputregisterdelaysetting,
outputdelaysetting1,
outputdelaysetting2,
dutycycledelaymode,
dutycycledelaysettings,
outputfinedelaysetting1,
outputfinedelaysetting2,
outputonlydelaysetting2,
outputonlyfinedelaysetting2,
padtoinputregisterfinedelaysetting,
dataout
);
parameter enhanced_mode = "false";
parameter lpm_type = "arriaiigz_io_config";
input datain;
input clk;
input ena;
input update;
input devclrn;
input devpor;
output [3:0] padtoinputregisterdelaysetting;
output [3:0] outputdelaysetting1;
output [2:0] outputdelaysetting2;
output dataout;
// new STRATIXIV: ww30.2008
output dutycycledelaymode;
output [3:0] dutycycledelaysettings;
output outputfinedelaysetting1;
output outputfinedelaysetting2;
output [2:0] outputonlydelaysetting2;
output outputonlyfinedelaysetting2;
output padtoinputregisterfinedelaysetting;
tri1 devclrn;
tri1 devpor;
reg [10:0] shift_reg;
reg [10:0] output_reg;
wire tmp_dataout;
wire [10:0] tmp_output;
reg [22:0] enhance_shift_reg;
reg [22:0] enhance_output_reg;
wire [22:0] enhance_tmp_output;
// buffer layer
wire datain_in;
wire clk_in;
wire ena_in;
wire update_in;
wire devclrn_in, devpor_in;
assign datain_in = datain;
assign clk_in = clk;
assign ena_in = (ena === 1'b1) ? 1'b1 : 1'b0;
assign update_in = (update === 1'b1) ? 1'b1 : 1'b0;
assign devclrn_in = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign devpor_in = (devpor === 1'b0) ? 1'b0 : 1'b1;
// TCO DELAYS, IO PATH and SETUP-HOLD CHECKS
specify
(posedge clk => (dataout +: tmp_dataout)) = (0, 0);
$setuphold(posedge clk, datain, 0, 0);
endspecify
// DRIVERs FOR outputs
and (dataout, tmp_dataout, 1'b1);
// primary outputs
assign tmp_dataout = (enhanced_mode == "true") ? enhance_shift_reg[22] : shift_reg[10];
// bit order changed in wys revision 1.32
assign outputdelaysetting1 = (enhanced_mode == "true") ? enhance_tmp_output[3:0] : tmp_output[3:0];
assign outputdelaysetting2 = (enhanced_mode == "true") ? enhance_tmp_output[6:4] : tmp_output[6:4];
assign padtoinputregisterdelaysetting = (enhanced_mode == "true") ? enhance_tmp_output[10:7] : tmp_output[10:7];
assign outputfinedelaysetting1 = (enhanced_mode == "true") ? enhance_tmp_output[11] : 1'b0;
assign outputfinedelaysetting2 = (enhanced_mode == "true") ? enhance_tmp_output[12] : 1'b0;
assign padtoinputregisterfinedelaysetting = (enhanced_mode == "true") ? enhance_tmp_output[13] : 1'b0;
assign outputonlyfinedelaysetting2 = (enhanced_mode == "true") ? enhance_tmp_output[14] : 1'b0;
assign outputonlydelaysetting2 = (enhanced_mode == "true") ? enhance_tmp_output[17:15] : 3'b000;
assign dutycycledelaymode = (enhanced_mode == "true") ? enhance_tmp_output[18] : 1'b0;
assign dutycycledelaysettings = (enhanced_mode == "true") ? enhance_tmp_output[22:19] : 4'h0;
assign tmp_output = output_reg;
assign enhance_tmp_output = enhance_output_reg;
initial
begin
shift_reg = 'b0;
output_reg = 'b0;
enhance_shift_reg = 'b0;
enhance_output_reg = 'b0;
end
always @(posedge clk_in)
begin
if (ena_in === 1'b1)
begin
shift_reg[0] <= datain_in;
shift_reg[10:1] <= shift_reg[9:0];
enhance_shift_reg[0] <= datain_in;
enhance_shift_reg[22:1] <= enhance_shift_reg[21:0];
end
end
always @(posedge clk_in)
begin
if (update_in === 1'b1)
begin
output_reg <= shift_reg;
enhance_output_reg <= enhance_shift_reg;
end
end
endmodule // arriaiigz_io_config
//-----------------------------------------------------------------------------
//
// Module Name : arriaiigz_dqs_config
//
// Description : ARRIAIIGZ DQS Configuration Register
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_dqs_config (
datain,
clk,
ena,
update,
devclrn,
devpor,
dqsbusoutdelaysetting,
dqsinputphasesetting,
dqsenablectrlphasesetting,
dqsoutputphasesetting,
dqoutputphasesetting,
resyncinputphasesetting,
dividerphasesetting,
enaoctcycledelaysetting,
enainputcycledelaysetting,
enaoutputcycledelaysetting,
dqsenabledelaysetting,
octdelaysetting1,
octdelaysetting2,
enadataoutbypass,
enadqsenablephasetransferreg, // new in 1.23
enaoctphasetransferreg, // new in 1.23
enaoutputphasetransferreg, // new in 1.23
enainputphasetransferreg, // new in 1.23
resyncinputphaseinvert, // new in 1.26
dqsenablectrlphaseinvert, // new in 1.26
dqoutputphaseinvert, // new in 1.26
dqsoutputphaseinvert, // new in 1.26
dqsbusoutfinedelaysetting,
dqsenablefinedelaysetting,
dataout
);
parameter enhanced_mode = "false";
parameter lpm_type = "arriaiigz_dqs_config";
// INPUT PORTS
input datain;
input clk;
input ena;
input update;
input devclrn;
input devpor;
// OUTPUT PORTS
output [3:0] dqsbusoutdelaysetting;
output [2:0] dqsinputphasesetting;
output [3:0] dqsenablectrlphasesetting;
output [3:0] dqsoutputphasesetting;
output [3:0] dqoutputphasesetting;
output [3:0] resyncinputphasesetting;
output dividerphasesetting;
output enaoctcycledelaysetting;
output enainputcycledelaysetting;
output enaoutputcycledelaysetting;
output [2:0] dqsenabledelaysetting;
output [3:0] octdelaysetting1;
output [2:0] octdelaysetting2;
output enadataoutbypass;
output enadqsenablephasetransferreg; // new in 1.23
output enaoctphasetransferreg; // new in 1.23
output enaoutputphasetransferreg; // new in 1.23
output enainputphasetransferreg; // new in 1.23
output resyncinputphaseinvert; // new in 1.26
output dqsenablectrlphaseinvert; // new in 1.26
output dqoutputphaseinvert; // new in 1.26
output dqsoutputphaseinvert; // new in 1.26
output dqsbusoutfinedelaysetting; // new in 1.39
output dqsenablefinedelaysetting; // new in 1.39
output dataout;
tri1 devclrn;
tri1 devpor;
reg [47:0] shift_reg;
reg [47:0] output_reg;
wire tmp_dataout;
wire [47:0] tmp_output;
// buffer layer
wire datain_in;
wire clk_in;
wire ena_in;
wire update_in;
wire devclrn_in, devpor_in;
assign datain_in = datain;
assign clk_in = clk;
assign ena_in = (ena === 1'b1) ? 1'b1 : 1'b0;
assign update_in = (update === 1'b1) ? 1'b1 : 1'b0;
assign devclrn_in = (devclrn === 1'b0) ? 1'b0 : 1'b1;
assign devpor_in = (devpor === 1'b0) ? 1'b0 : 1'b1;
// TCO DELAYS, IO PATH and SETUP-HOLD CHECKS
specify
(posedge clk => (dataout +: tmp_dataout)) = (0, 0);
$setuphold(posedge clk, datain, 0, 0);
endspecify
// DRIVERs FOR outputs
and (dataout, tmp_dataout, 1'b1);
// primary outputs
assign tmp_dataout = (enhanced_mode == "true") ? shift_reg[47] : shift_reg[45];
assign dqsbusoutdelaysetting = tmp_output[3 : 0];
assign dqsinputphasesetting = tmp_output[6 : 4];
assign dqsenablectrlphasesetting = tmp_output[10 : 7];
assign dqsoutputphasesetting = tmp_output[14 : 11];
assign dqoutputphasesetting = tmp_output[18 : 15];
assign resyncinputphasesetting = tmp_output[22 : 19];
assign dividerphasesetting = tmp_output[23];
assign enaoctcycledelaysetting = tmp_output[24];
assign enainputcycledelaysetting = tmp_output[25];
assign enaoutputcycledelaysetting= tmp_output[26];
assign dqsenabledelaysetting = tmp_output[29 : 27];
assign octdelaysetting1 = tmp_output[33 : 30];
assign octdelaysetting2 = tmp_output[36 : 34];
assign enadataoutbypass = tmp_output[37];
assign enadqsenablephasetransferreg = tmp_output[38]; // new in 1.23
assign enaoctphasetransferreg = tmp_output[39]; // new in 1.23
assign enaoutputphasetransferreg = tmp_output[40]; // new in 1.23
assign enainputphasetransferreg = tmp_output[41]; // new in 1.23
assign resyncinputphaseinvert = tmp_output[42]; // new in 1.26
assign dqsenablectrlphaseinvert = tmp_output[43]; // new in 1.26
assign dqoutputphaseinvert = tmp_output[44]; // new in 1.26
assign dqsoutputphaseinvert = tmp_output[45]; // new in 1.26
// new in STRATIXIV: ww30.2008
assign dqsbusoutfinedelaysetting = (enhanced_mode == "true") ? tmp_output[46] : 1'b0;
assign dqsenablefinedelaysetting = (enhanced_mode == "true") ? tmp_output[47] : 1'b0;
assign tmp_output = output_reg;
initial
begin
shift_reg = 'b0;
output_reg = 'b0;
end
always @(posedge clk_in)
begin
if (ena_in === 1'b1)
begin
shift_reg[0] <= datain_in;
shift_reg[47:1] <= shift_reg[46:0];
end
end
always @(posedge clk_in)
begin
if (update_in === 1'b1)
output_reg <= shift_reg;
end
endmodule // arriaiigz_dqs_config
// end_ddr
// --------------------------------------------------------------------
// Module Name: arriaiigz_rt_sm
// Description: Parallel Termination State Machine
// --------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_rt_sm (
rup,rdn,clk,clken,clr,rtena,rscaldone,
rtoffsetp,rtoffsetn,caldone,
sel_rup_vref,sel_rdn_vref
);
input rup;
input rdn;
input clk;
input clken;
input clr;
input rtena;
input rscaldone;
output [3:0] rtoffsetp;
output [3:0] rtoffsetn;
output caldone;
output [2:0] sel_rup_vref;
output [2:0] sel_rdn_vref;
parameter ARRIAIIGZ_RTOCT_WAIT = 5'b00000;
parameter RUP_VREF_M_RDN_VER_M = 5'b00001;
parameter RUP_VREF_L_RDN_VER_L = 5'b00010;
parameter RUP_VREF_H_RDN_VER_H = 5'b00011;
parameter RUP_VREF_L_RDN_VER_H = 5'b00100;
parameter RUP_VREF_H_RDN_VER_L = 5'b00101;
parameter ARRIAIIGZ_RTOCT_INC_PN = 5'b01000;
parameter ARRIAIIGZ_RTOCT_DEC_PN = 5'b01001;
parameter ARRIAIIGZ_RTOCT_INC_P = 5'b01010;
parameter ARRIAIIGZ_RTOCT_DEC_P = 5'b01011;
parameter ARRIAIIGZ_RTOCT_INC_N = 5'b01100;
parameter ARRIAIIGZ_RTOCT_DEC_N = 5'b01101;
parameter ARRIAIIGZ_RTOCT_SWITCH_REG = 5'b10001;
parameter ARRIAIIGZ_RTOCT_DONE = 5'b11111;
// interface
wire nclr; // for synthesis
wire rtcalclk;
// sm
reg [4:0] current_state, next_state;
reg sel_rup_vref_h_d, sel_rup_vref_h;
reg sel_rup_vref_m_d, sel_rup_vref_m;
reg sel_rup_vref_l_d, sel_rup_vref_l;
reg sel_rdn_vref_h_d, sel_rdn_vref_h;
reg sel_rdn_vref_m_d, sel_rdn_vref_m;
reg sel_rdn_vref_l_d, sel_rdn_vref_l;
reg switch_region_d, switch_region;
reg cmpup, cmpdn;
reg rt_sm_done_d, rt_sm_done;
// cnt
reg [2:0] p_cnt_d, p_cnt, n_cnt_d, n_cnt;
reg p_cnt_sub_d,p_cnt_sub,n_cnt_sub_d,n_cnt_sub;
// primary output - MSB is sign bit
assign rtoffsetp = {p_cnt_sub, p_cnt};
assign rtoffsetn = {n_cnt_sub, n_cnt};
assign caldone = (rtena == 1'b1) ? rt_sm_done : 1'b1;
assign sel_rup_vref = {sel_rup_vref_h,sel_rup_vref_m,sel_rup_vref_l};
assign sel_rdn_vref = {sel_rdn_vref_h,sel_rdn_vref_m,sel_rdn_vref_l};
// input interface
assign nclr = ~clr;
assign rtcalclk = (rscaldone & clken & ~caldone & clk);
// latch registers - rising on everything except cmpup and cmpdn
// cmpup/dn
always @(negedge rtcalclk or negedge nclr)
begin
if (nclr == 1'b0)
begin
cmpup <= 1'b0;
cmpdn <= 1'b0;
end
else
begin
cmpup <= rup;
cmpdn <= rdn;
end
end
// other regisers
always @(posedge rtcalclk or posedge clr)
begin
if (clr == 1'b1)
begin
current_state <= ARRIAIIGZ_RTOCT_WAIT;
switch_region <= 1'b0;
rt_sm_done <= 1'b0;
p_cnt <= 3'b000;
p_cnt_sub <= 1'b0;
n_cnt <= 3'b000;
n_cnt_sub <= 1'b0;
sel_rup_vref_h <= 1'b0;
sel_rup_vref_m <= 1'b1;
sel_rup_vref_l <= 1'b0;
sel_rdn_vref_h <= 1'b0;
sel_rdn_vref_m <= 1'b1;
sel_rdn_vref_l <= 1'b0;
end
else
begin
current_state <= next_state;
switch_region <= switch_region_d;
rt_sm_done <= rt_sm_done_d;
p_cnt <= p_cnt_d;
p_cnt_sub <= p_cnt_sub_d;
n_cnt <= n_cnt_d;
n_cnt_sub <= n_cnt_sub_d;
sel_rup_vref_h <= sel_rup_vref_h_d;
sel_rup_vref_m <= sel_rup_vref_m_d;
sel_rup_vref_l <= sel_rup_vref_l_d;
sel_rdn_vref_h <= sel_rdn_vref_h_d;
sel_rdn_vref_m <= sel_rdn_vref_m_d;
sel_rdn_vref_l <= sel_rdn_vref_l_d;
end
end
// state machine
always @(current_state or rtena or cmpup or cmpdn or p_cnt or n_cnt or switch_region)
begin
p_cnt_d = p_cnt;
n_cnt_d = n_cnt;
p_cnt_sub_d = 1'b0;
n_cnt_sub_d = 1'b0;
case (current_state)
ARRIAIIGZ_RTOCT_WAIT :
if (rtena == 1'b0)
next_state = ARRIAIIGZ_RTOCT_WAIT;
else
begin
next_state = RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_m_d = 1'b1;
sel_rup_vref_l_d = 1'b0;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_m_d = 1'b1;
sel_rdn_vref_l_d = 1'b0;
end
RUP_VREF_M_RDN_VER_M :
if (cmpup == 1'b0 && cmpdn == 1'b0)
begin
next_state = RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b1;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b1;
end
else if (cmpup == 1'b1 && cmpdn == 1'b1)
begin
next_state = RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d = 1'b1;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b0;
sel_rdn_vref_h_d = 1'b1;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b0;
end
else if (cmpup == 1'b1 && cmpdn == 1'b0)
begin
next_state = ARRIAIIGZ_RTOCT_INC_PN;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b0;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b0;
end
else if (cmpup == 1'b0 && cmpdn == 1'b1)
begin
next_state = ARRIAIIGZ_RTOCT_DEC_PN;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b1;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b1;
end
RUP_VREF_L_RDN_VER_L :
if (cmpup == 1'b1 && cmpdn == 1'b1)
begin
next_state = ARRIAIIGZ_RTOCT_DONE;
end
else if (cmpup == 1'b0)
begin
next_state = ARRIAIIGZ_RTOCT_DEC_N;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b1;
end
else if (cmpup == 1'b1 && cmpdn == 1'b0)
begin
next_state = ARRIAIIGZ_RTOCT_INC_P;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b0;
end
RUP_VREF_H_RDN_VER_H :
if (cmpup == 1'b0 && cmpdn == 1'b0)
begin
next_state = ARRIAIIGZ_RTOCT_DONE;
end
else if (cmpup == 1'b1)
begin
next_state = ARRIAIIGZ_RTOCT_INC_N;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b0;
end
else if (cmpup == 1'b0 && cmpdn == 1'b1)
begin
next_state = ARRIAIIGZ_RTOCT_DEC_P;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b1;
end
RUP_VREF_L_RDN_VER_H :
if (cmpup == 1'b1 && cmpdn == 1'b0)
begin
next_state = ARRIAIIGZ_RTOCT_DONE;
end
else if (cmpup == 1'b1 && switch_region == 1'b1)
begin
next_state = ARRIAIIGZ_RTOCT_DEC_P;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b1;
end
else if (cmpup == 1'b0 && switch_region == 1'b1)
begin
next_state = ARRIAIIGZ_RTOCT_DEC_N;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b1;
end
else if ((switch_region == 1'b0) && (cmpup == 1'b0 || cmpdn == 1'b1))
begin
next_state = ARRIAIIGZ_RTOCT_SWITCH_REG;
switch_region_d = 1'b1;
end
RUP_VREF_H_RDN_VER_L :
if (cmpup == 1'b0 && cmpdn == 1'b1)
begin
next_state = ARRIAIIGZ_RTOCT_DONE;
end
else if (cmpup == 1'b1 && switch_region == 1'b1)
begin
next_state = ARRIAIIGZ_RTOCT_INC_N;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b0;
end
else if (cmpup == 1'b0 && switch_region == 1'b1)
begin
next_state = ARRIAIIGZ_RTOCT_INC_P;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b0;
end
else if ((switch_region == 1'b0) && (cmpup == 1'b1 || cmpdn == 1'b0))
begin
next_state = ARRIAIIGZ_RTOCT_SWITCH_REG;
switch_region_d = 1'b1;
end
ARRIAIIGZ_RTOCT_INC_PN :
if (cmpup == 1'b1 && cmpdn == 1'b0)
begin
next_state = ARRIAIIGZ_RTOCT_INC_PN;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b0;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b0;
end
else if (cmpup == 1'b0 && cmpdn == 1'b0)
begin
next_state = RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b1;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b1;
end
else if (cmpup == 1'b1 && cmpdn == 1'b1)
begin
next_state = RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d = 1'b1;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b0;
sel_rdn_vref_h_d = 1'b1;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b0;
end
else if (cmpup == 1'b0 && cmpdn == 1'b1)
begin
next_state = RUP_VREF_L_RDN_VER_H;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b1;
sel_rdn_vref_h_d = 1'b1;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b0;
end
ARRIAIIGZ_RTOCT_DEC_PN :
if (cmpup == 1'b0 && cmpdn == 1'b1)
begin
next_state = ARRIAIIGZ_RTOCT_DEC_PN;
p_cnt_d = p_cnt_d + 3'b001;
p_cnt_sub_d = 1'b1;
n_cnt_d = n_cnt_d + 3'b001;
n_cnt_sub_d = 1'b1;
end
else if (cmpup == 1'b0 && cmpdn == 1'b0)
begin
next_state = RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b1;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b1;
end
else if (cmpup == 1'b1 && cmpdn == 1'b1)
begin
next_state = RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d = 1'b1;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b0;
sel_rdn_vref_h_d = 1'b1;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b0;
end
else if (cmpup == 1'b1 && cmpdn == 1'b0)
begin
next_state = RUP_VREF_H_RDN_VER_L;
sel_rup_vref_h_d = 1'b1;
sel_rup_vref_m_d = 1'b0;
sel_rup_vref_l_d = 1'b0;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_m_d = 1'b0;
sel_rdn_vref_l_d = 1'b1;
end
ARRIAIIGZ_RTOCT_INC_P,ARRIAIIGZ_RTOCT_DEC_P,ARRIAIIGZ_RTOCT_INC_N,ARRIAIIGZ_RTOCT_DEC_N :
if (switch_region == 1'b1)
begin
next_state = ARRIAIIGZ_RTOCT_DONE;
end
else if (switch_region == 1'b0)
begin
next_state = RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_m_d = 1'b1;
sel_rup_vref_l_d = 1'b0;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_m_d = 1'b1;
sel_rdn_vref_l_d = 1'b0;
end
ARRIAIIGZ_RTOCT_SWITCH_REG :
begin
next_state = RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_m_d = 1'b1;
sel_rup_vref_l_d = 1'b0;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_m_d = 1'b1;
sel_rdn_vref_l_d = 1'b0;
end
ARRIAIIGZ_RTOCT_DONE :
begin
next_state = ARRIAIIGZ_RTOCT_DONE;
rt_sm_done_d = 1'b1;
end
default :
next_state = ARRIAIIGZ_RTOCT_WAIT;
endcase // case(current_state)
end // always
// initial registers for simulations
initial begin
current_state = ARRIAIIGZ_RTOCT_WAIT;
next_state = ARRIAIIGZ_RTOCT_WAIT;
sel_rup_vref_h_d = 1'b0;
sel_rup_vref_h = 1'b0;
sel_rup_vref_m_d = 1'b1;
sel_rup_vref_m = 1'b1;
sel_rup_vref_l_d = 1'b0;
sel_rup_vref_l = 1'b0;
sel_rdn_vref_h_d = 1'b0;
sel_rdn_vref_h = 1'b0;
sel_rdn_vref_m_d = 1'b1;
sel_rdn_vref_m = 1'b1;
sel_rdn_vref_l_d = 1'b0;
sel_rdn_vref_l = 1'b0;
switch_region_d = 1'b0;
switch_region = 1'b0;
cmpup = 1'b0;
cmpdn = 1'b0;
rt_sm_done_d = 1'b0;
rt_sm_done = 1'b0;
p_cnt = 1'b0;
n_cnt = 1'b0;
p_cnt_sub = 1'b0;
n_cnt_sub = 1'b0;
end
endmodule
// --------------------------------------------------------------------
// Module Name: arriaiigz_termination_aux_clock_div
// Description: auxilary clock divider
// --------------------------------------------------------------------
`timescale 1 ps / 1 ps
module arriaiigz_termination_aux_clock_div (
clk, // input clock
reset, // reset
clkout // divided clock
);
input clk;
input reset;
output clkout;
parameter clk_divide_by = 1;
parameter extra_latency = 0;
integer clk_edges,m;
reg [2*extra_latency:0] div_n_register;
initial
begin
div_n_register = 'b0;
clk_edges = -1;
m = 0;
end
always @(posedge clk or negedge clk or posedge reset)
begin
if (reset === 1'b1)
begin
clk_edges = -1;
div_n_register <= 'b0;
end
else
begin
if (clk_edges == -1)
begin
div_n_register[0] <= clk;
if (clk == 1'b1)
clk_edges = 0;
end
else if (clk_edges % clk_divide_by == 0)
div_n_register[0] <= ~div_n_register[0];
if (clk_edges >= 0 || clk == 1'b1)
clk_edges = (clk_edges + 1) % (2*clk_divide_by) ;
end
for (m = 0; m < 2*extra_latency; m=m+1)
div_n_register[m+1] <= div_n_register[m];
end
assign clkout = div_n_register[2*extra_latency];
endmodule
//-----------------------------------------------------------------------------
//
// Module Name : arriaiigz_termination
//
// Description : ARRIAIIGZ Termination Atom
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_termination (
rup,rdn,terminationclock,terminationclear,terminationenable,
serializerenable,terminationcontrolin,
scanin, scanen,
otherserializerenable,
devclrn,devpor,
incrup,incrdn,
serializerenableout,
terminationcontrol,terminationcontrolprobe,
scanout,
shiftregisterprobe
);
parameter runtime_control = "false";
parameter allow_serial_data_from_core = "false";
parameter power_down = "true";
parameter test_mode = "false";
parameter enable_parallel_termination = "false";
parameter enable_calclk_divider= "false"; // replaced by below to remove
parameter clock_divider_enable = "false";
parameter enable_pwrupmode_enser_for_usrmode = "false"; // to remove
parameter bypass_enser_logic = "false"; // to remove
parameter bypass_rt_calclk = "false"; //RTEST3
parameter enable_rt_scan_mode = "false"; // to remove
parameter enable_loopback = "false";
parameter force_rtcalen_for_pllbiasen = "false";
parameter enable_rt_sm_loopback = "false"; // RTEST4
parameter select_vrefl_values = 0;
parameter select_vrefh_values = 0;
parameter divide_intosc_by = 2;
parameter use_usrmode_clear_for_configmode = "false";
parameter lpm_type = "arriaiigz_termination";
input rup;
input rdn;
input terminationclock;
input terminationclear;
input terminationenable;
input serializerenable; // ENSERUSR
input terminationcontrolin;
input scanin; // to remove
input scanen;
input [8:0] otherserializerenable;
input devclrn;
input devpor;
output incrup;
output incrdn;
output serializerenableout;
output terminationcontrol;
output terminationcontrolprobe;
output shiftregisterprobe;
output scanout;
tri1 devclrn;
tri1 devpor;
// HW outputs
wire compout_rup_core, compout_rdn_core;
wire ser_data_io, ser_data_core;
// HW inputs
wire usr_clk, cal_clk, rscal_clk, cal_clken, cal_nclr;
// gated user control
reg enserusr_reg, clkenusr_reg, nclrusr_reg; // registered by neg clk
wire enserusr_gated; // (enserusr & !clkenusr) - for P2S, S2P to shift
wire clkenusr_gated; // (enserusr & clkenusr) - for calibration
wire nclrusr_gated; // (enserusr | nclrusr): enserusr = 1 forces no clear
// clk divider
wire clkdiv_out;
// generating calclk and clkenout - 1 cycle latency
reg calclken_reg;
//wire clkenout;
// legality check on enser
reg enser_checked;
// Shift Register
reg [6:0] sreg_bit_out;
reg sreg_bit_BIT_0;
reg sreg_vshift_bit_out;
reg sreg_bit0_next;
reg sreg_vshift_bit_tmp;
reg sreg_rscaldone_prev, sreg_rscaldone_prev1, sregn_rscaldone_out;
reg sreg_bit6_prev;
// nreg before SA-ADC
wire regn_rup_in, regn_rdn_in;
reg [6:0] regn_compout_rup, regn_compout_rdn;
reg regn_compout_rup_extra, regn_compout_rdn_extra; // extra is bit[8] accomodate last move
// SA-ADC
wire [6:0] sa_octcaln_out_tmp; // this + _extra ==> code
wire [6:0] sa_octcalp_out_tmp;
wire [6:0] sa_octcaln_out_tmp_extra;
wire [6:0] sa_octcalp_out_tmp_extra;
wire [6:0] sa_octcaln_out; // RUP - NMOS
wire [6:0] sa_octcalp_out; // RDN - PMOS
wire [6:0] sa_octcaln_in, sa_octcalp_in;
// ENSER
wire enser_out;
wire enser_gen_out;
reg [5:0] enser_cnt;
reg enser_gen_usr_out;
// RT State Machine
wire rtsm_rup_in, rtsm_rdn_in;
wire rtsm_rtena_in, rtsm_rscaldone_in;
wire rtsm_caldone_out;
wire [3:0] rtsm_rtoffsetp_out, rtsm_rtoffsetn_out;
wire [2:0] rtsm_sel_rup_vref_out, rtsm_sel_rdn_vref_out;
// RT State Machine Scan Chain
wire rtsm_sc_clk;
wire rtsm_sc_in;
reg [17:0] rtsm_sc_out_reg;
wire [17:0] rtsm_sc_out_reg_d;
wire [17:0] rtsm_sc_lpbk_mux;
// RT Adder/Sub
wire [6:0] rtas_rs_rpcdp_in, rtas_rs_rpcdn_in;
wire [6:0] rtas_rtoffsetp_in, rtas_rtoffsetn_in;
wire [6:0] rtas_rs_rpcdp_out, rtas_rs_rpcdn_out;
wire [6:0] rtas_rt_rpcdp_out, rtas_rt_rpcdn_out;
// P2S
wire [6:0] p2s_rs_rpcdp_in, p2s_rs_rpcdn_in;
wire [6:0] p2s_rt_rpcdp_in, p2s_rt_rpcdn_in;
wire p2s_ser_data_out;
wire p2s_clk_ser_data;
reg p2s_enser_reg;
wire [27:0] p2s_parallel_code;
wire [27:0] p2s_shift_d;
reg [27:0] p2s_shift_regs;
// timing
wire rup_ipd;
wire rdn_ipd;
wire terminationclock_ipd;
wire terminationclear_ipd;
wire terminationenable_ipd;
wire serializerenable_ipd;
wire terminationcontrolin_ipd;
wire [8:0] otherserializerenable_ipd;
// primary outputs
assign incrup = (enable_loopback == "true") ? terminationenable_ipd : compout_rup_core;
assign incrdn = (enable_loopback == "true") ? terminationclear_ipd : compout_rdn_core;
assign serializerenableout = (enable_loopback == "true") ? serializerenable : enser_gen_usr_out;
assign terminationcontrol = ser_data_io;
assign terminationcontrolprobe = (enable_loopback == "true") ? serializerenable_ipd : ser_data_core;
assign shiftregisterprobe = (enable_loopback == "true") ? terminationclock_ipd : sreg_vshift_bit_out;
// disabled comparator when calibration is not enabled
assign compout_rup_core = (calclken_reg === 1'b1) ? rup : 1'bx;
assign compout_rdn_core = (calclken_reg === 1'b1) ? rdn : 1'bx;
assign ser_data_io = (allow_serial_data_from_core == "true") ? terminationcontrolin : p2s_ser_data_out;
assign ser_data_core = p2s_ser_data_out;
// primary inputs
assign usr_clk = terminationclock_ipd;
// gating the enserusr, clken and nclrusr ----------------------------------------------------
initial begin
enserusr_reg = 1'b0;
clkenusr_reg = 1'b0;
nclrusr_reg = 1'b1;
end
always @(negedge usr_clk)
begin
if (serializerenable_ipd === 1'b1)
enserusr_reg <= 1'b1;
else
enserusr_reg <= 1'b0;
if (terminationenable_ipd === 1'b1)
clkenusr_reg <= 1'b1;
else
clkenusr_reg <= 1'b0;
if (terminationclear_ipd === 1'b1) // active low to high
nclrusr_reg <= 1'b0;
else
nclrusr_reg <= 1'b1;
end
assign enserusr_gated = enserusr_reg & ~clkenusr_reg; // code transfer (P2S and S2P)
assign clkenusr_gated = enserusr_reg & clkenusr_reg; // calibration
assign nclrusr_gated = enserusr_reg | nclrusr_reg; // active low
// clk divider ----------------------------------------------------------------
arriaiigz_termination_aux_clock_div m_gen_calclk (
.clk(usr_clk),
.reset(~clkenusr_gated),
.clkout(clkdiv_out));
defparam m_gen_calclk.clk_divide_by = 20; // user clock is of 20 Mhz updated from 100;
defparam m_gen_calclk.extra_latency = 4; // 5th rising edge after reset
// generating clkenout - a registered version of clkensur_gated ---------------
initial calclken_reg = 1'b0;
always @(negedge clkdiv_out or negedge clkenusr_gated)
begin
if (clkenusr_gated == 1'b0)
calclken_reg <= 1'b0;
else
calclken_reg <= 1'b1;
end
//assign clkenout = calclken_reg;
// generating cal_clkout - 1 cycle latency of divided clock ---------------
assign cal_clk = calclken_reg & clkdiv_out;
assign cal_nclr = nclrusr_gated; // active low
assign cal_clken = clkenusr_gated;
assign rscal_clk = cal_clk & (~sregn_rscaldone_out);
// legality check on enser
initial begin
enser_checked = 1'b0;
end
always @(posedge usr_clk)
begin
if (serializerenable === 1'b1 && terminationenable === 1'b0)
begin
if (otherserializerenable[0] === 1'b1 || otherserializerenable[1] === 1'b1 ||
otherserializerenable[2] === 1'b1 || otherserializerenable[3] === 1'b1 ||
otherserializerenable[4] === 1'b1 || otherserializerenable[5] === 1'b1 ||
otherserializerenable[6] === 1'b1 || otherserializerenable[7] === 1'b1 ||
otherserializerenable[8] === 1'b1)
begin
if (enser_checked === 1'b0)
begin
$display ("Warning: serializizerable and some bits of otherserializerenable are asserted at time %t ps. This is not allowed in hardware data transfer time", $realtime);
$display ("Time: %0t Instance: %m", $time);
enser_checked <= 1'b1;
end
end
else
begin
enser_checked <= 1'b0; // for another check
end
end
else
begin
enser_checked <= 1'b0; // for another check
end
end
// SHIFT regiter
// ICD BIT_7 .. BIT_1 ===> sreg_bit_out[6..0];
// ICD BIT_0 ===> sreg_bit_BIT_0;
initial begin
sreg_bit6_prev = 1'b1;
sreg_bit_out = 6'b000000;
sreg_bit0_next = 1'b0;
sreg_bit_BIT_0 = 1'b0;
sreg_vshift_bit_tmp = 1'b0;
sreg_vshift_bit_out = 1'b0; // sending to shiftreg_probe
sregn_rscaldone_out = 1'b0;
sreg_rscaldone_prev = 1'b0;
sreg_rscaldone_prev1 = 1'b0;
end
always @(posedge rscal_clk or negedge cal_nclr)
begin
if (cal_nclr == 1'b0)
begin
sreg_bit6_prev <= 1'b1;
sreg_bit_out <= 6'b000000;
sreg_bit0_next <= 1'b0;
sreg_bit_BIT_0 <= 1'b0;
sreg_vshift_bit_tmp <= 1'b0;
sreg_vshift_bit_out <= 1'b0;
sreg_rscaldone_prev <= 1'b0;
sreg_rscaldone_prev1 <= 1'b0;
end
else if (cal_clken == 1'b1)
begin
sreg_bit_out[6] <= sreg_bit6_prev;
sreg_bit_out[5:0] <= sreg_bit_out[6:1];
sreg_bit0_next <= sreg_bit_out[0]; // extra latency for ICD BIT_0
sreg_bit_BIT_0 <= sreg_bit0_next;
sreg_vshift_bit_tmp <= sreg_bit_out[0];
sreg_vshift_bit_out <= sreg_bit_out[0] | sreg_vshift_bit_tmp;
sreg_bit6_prev <= 1'b0;
end
// might falling outside of 10 cycles
if (sreg_vshift_bit_tmp == 1'b1)
sreg_rscaldone_prev <= 1'b1;
sreg_rscaldone_prev1 <= sreg_rscaldone_prev;
end
always @(negedge rscal_clk or negedge cal_nclr)
begin
if (cal_nclr == 1'b0)
sregn_rscaldone_out <= 1'b0;
else // if (cal_clken == 1'b1) - outside of 10 cycles
begin
if (sreg_rscaldone_prev1 == 1'b1 && sregn_rscaldone_out == 1'b0)
sregn_rscaldone_out <= 1'b1;
end
end
// nreg and SA-ADC:
//
// RDN_vol < ref_voltage < RUP_voltage
// after reset, ref_voltage=VCCN/2; after ref_voltage_shift, ref_voltage=neighbor(VCCN/2)
// at 0 code, RUP=VCCN so voltage_compare_out for RUP = 0
// RDN=GND so voltage compare out for RDN = 0
assign regn_rup_in = rup;
assign regn_rdn_in = ~rdn; // inverted --------------------------
initial begin
regn_compout_rup = 6'b00000;
regn_compout_rdn = 6'b00000;
regn_compout_rup_extra = 1'b0;
regn_compout_rdn_extra = 1'b0;
end
always @(negedge rscal_clk or negedge cal_nclr)
begin
if (cal_nclr == 1'b0)
begin
regn_compout_rup <= 6'b00000;
regn_compout_rdn <= 6'b00000;
regn_compout_rup_extra <= 1'b0;
regn_compout_rdn_extra <= 1'b0;
end
else
begin
// rup
if (sreg_bit_BIT_0 == 1'b1)
regn_compout_rup_extra <= regn_rup_in;
if (sreg_bit_out[0] == 1'b1)
regn_compout_rup[0] <= regn_rup_in;
if (sreg_bit_out[1] == 1'b1)
regn_compout_rup[1] <= regn_rup_in;
if (sreg_bit_out[2] == 1'b1)
regn_compout_rup[2] <= regn_rup_in;
if (sreg_bit_out[3] == 1'b1)
regn_compout_rup[3] <= regn_rup_in;
if (sreg_bit_out[4] == 1'b1)
regn_compout_rup[4] <= regn_rup_in;
if (sreg_bit_out[5] == 1'b1)
regn_compout_rup[5] <= regn_rup_in;
if (sreg_bit_out[6] == 1'b1)
regn_compout_rup[6] <= regn_rup_in;
// rdn
if (sreg_bit_BIT_0 == 1'b1)
regn_compout_rdn_extra <= regn_rdn_in;
if (sreg_bit_out[0] == 1'b1)
regn_compout_rdn[0] <= regn_rdn_in;
if (sreg_bit_out[1] == 1'b1)
regn_compout_rdn[1] <= regn_rdn_in;
if (sreg_bit_out[2] == 1'b1)
regn_compout_rdn[2] <= regn_rdn_in;
if (sreg_bit_out[3] == 1'b1)
regn_compout_rdn[3] <= regn_rdn_in;
if (sreg_bit_out[4] == 1'b1)
regn_compout_rdn[4] <= regn_rdn_in;
if (sreg_bit_out[5] == 1'b1)
regn_compout_rdn[5] <= regn_rdn_in;
if (sreg_bit_out[6] == 1'b1)
regn_compout_rdn[6] <= regn_rdn_in;
end
end
assign sa_octcaln_in = sreg_bit_out;
assign sa_octcalp_in = sreg_bit_out;
// RUP - octcaln_in == 1 = (pin_voltage < ref_voltage): clear the bit setting
assign sa_octcaln_out_tmp_extra = (cal_nclr == 1'b0) ? 1'b0 :
(sreg_bit_BIT_0 == 1'b1) ? 1'b1: regn_compout_rup_extra;
assign sa_octcaln_out_tmp[0] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcaln_in[0] == 1'b1) ? 1'b1: regn_compout_rup[0];
assign sa_octcaln_out_tmp[1] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcaln_in[1] == 1'b1) ? 1'b1: regn_compout_rup[1];
assign sa_octcaln_out_tmp[2] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcaln_in[2] == 1'b1) ? 1'b1: regn_compout_rup[2];
assign sa_octcaln_out_tmp[3] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcaln_in[3] == 1'b1) ? 1'b1: regn_compout_rup[3];
assign sa_octcaln_out_tmp[4] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcaln_in[4] == 1'b1) ? 1'b1: regn_compout_rup[4];
assign sa_octcaln_out_tmp[5] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcaln_in[5] == 1'b1) ? 1'b1: regn_compout_rup[5];
assign sa_octcaln_out_tmp[6] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcaln_in[6] == 1'b1) ? 1'b1: regn_compout_rup[6];
// RDN - octcalp_in == 1 = (pin_voltage > ref_voltage): clear the bit setting
assign sa_octcalp_out_tmp_extra = (cal_nclr == 1'b0) ? 1'b0 :
(sreg_bit_BIT_0 == 1'b1) ? 1'b1: regn_compout_rdn_extra;
assign sa_octcalp_out_tmp[0] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcalp_in[0] == 1'b1) ? 1'b1: regn_compout_rdn[0];
assign sa_octcalp_out_tmp[1] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcalp_in[1] == 1'b1) ? 1'b1: regn_compout_rdn[1];
assign sa_octcalp_out_tmp[2] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcalp_in[2] == 1'b1) ? 1'b1: regn_compout_rdn[2];
assign sa_octcalp_out_tmp[3] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcalp_in[3] == 1'b1) ? 1'b1: regn_compout_rdn[3];
assign sa_octcalp_out_tmp[4] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcalp_in[4] == 1'b1) ? 1'b1: regn_compout_rdn[4];
assign sa_octcalp_out_tmp[5] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcalp_in[5] == 1'b1) ? 1'b1: regn_compout_rdn[5];
assign sa_octcalp_out_tmp[6] = (cal_nclr == 1'b0) ? 1'b0 :
(sa_octcalp_in[6] == 1'b1) ? 1'b1: regn_compout_rdn[6];
assign sa_octcaln_out = sa_octcaln_out_tmp + sa_octcaln_out_tmp_extra;
assign sa_octcalp_out = sa_octcalp_out_tmp + sa_octcalp_out_tmp_extra;
// ENSER
assign enser_out = (runtime_control == "true") ? enser_gen_usr_out : enser_gen_out;
// user mode
initial enser_gen_usr_out = 1'b0;
always @(negedge usr_clk)
begin
enser_gen_usr_out <= serializerenable;
end
// for powerup mode
assign enser_gen_out = (enser_cnt > 6'd00 && enser_cnt < 6'd31) ? 1'b1 : 1'b0;
initial begin
enser_cnt = 'b0;
end
always @(posedge usr_clk or posedge sregn_rscaldone_out)
begin
if (sregn_rscaldone_out == 1'b0)
enser_cnt <= 6'b000000;
else if (enser_cnt < 6'd63)
enser_cnt <= enser_cnt + 6'b000001;
end
// RT SM
assign rtsm_rup_in = rup;
assign rtsm_rdn_in = rdn;
assign rtsm_rtena_in = (enable_parallel_termination == "true") ? 1'b1 : 1'b0;
assign rtsm_rscaldone_in = sregn_rscaldone_out;
arriaiigz_rt_sm m_rt_sm(
.rup(rtsm_rup_in),
.rdn(rtsm_rdn_in),
.clk(cal_clk),
.clken(cal_clken),
.clr(~cal_nclr),
.rtena(rtsm_rtena_in),
.rscaldone(rtsm_rscaldone_in),
.rtoffsetp(rtsm_rtoffsetp_out),
.rtoffsetn(rtsm_rtoffsetn_out),
.caldone(rtsm_caldone_out),
.sel_rup_vref(rtsm_sel_rup_vref_out),
.sel_rdn_vref(rtsm_sel_rdn_vref_out)
);
// RT State Machine Scan Chain
initial rtsm_sc_out_reg = 'b0;
assign rtsm_sc_clk = (bypass_rt_calclk == "true") ? cal_clk : cal_clk; // : rtcal_clk
assign rtsm_sc_in = terminationcontrolin_ipd;
//TEST4&RTEST3 not implemented - requires identical RT_SM
assign rtsm_sc_lpbk_mux = (bypass_rt_calclk == "true" && enable_rt_sm_loopback == "true") ?
18'bx : 18'bx;
assign rtsm_sc_out_reg_d[17] = (bypass_rt_calclk == "true" && scanen === 1'b0) ? rtsm_sc_in
: rtsm_sc_lpbk_mux[17];
assign rtsm_sc_out_reg_d[16:0] = (bypass_rt_calclk == "true" && scanen === 1'b0) ? rtsm_sc_out_reg[17:1]
: rtsm_sc_lpbk_mux[16:0];
assign scanout = rtsm_sc_out_reg[0];
always @(posedge rtsm_sc_clk or negedge cal_nclr)
begin
if (cal_nclr == 1'b0)
rtsm_sc_out_reg <= 'b0;
else
rtsm_sc_out_reg <= rtsm_sc_out_reg_d;
end
// RT Adder/Sub
assign rtas_rs_rpcdp_in = sa_octcalp_out;
assign rtas_rs_rpcdn_in = sa_octcaln_out;
assign rtas_rtoffsetp_in = {4'b0000, rtsm_rtoffsetp_out[2:0]};
assign rtas_rtoffsetn_in = {4'b0000, rtsm_rtoffsetn_out[2:0]};
assign rtas_rs_rpcdp_out = rtas_rs_rpcdp_in;
assign rtas_rs_rpcdn_out = rtas_rs_rpcdn_in;
assign rtas_rt_rpcdn_out = (rtsm_rtoffsetn_out[3] == 1'b0) ? (rtas_rs_rpcdn_in + rtas_rtoffsetn_in) :
(rtas_rs_rpcdn_in - rtas_rtoffsetn_in);
assign rtas_rt_rpcdp_out = (rtsm_rtoffsetp_out[3] == 1'b0) ? (rtas_rs_rpcdp_in + rtas_rtoffsetp_in) :
(rtas_rs_rpcdp_in - rtas_rtoffsetp_in);
// P2S ------------------------------------------------------------------------
// during calibration - enser_reg = 0
// - enser_reg is low D inputs of shfit_reg select parallel code
// caldone generating a rising pulse on clk_ser_data: shift_regs read in D (parallel_load)
// during serial shift - enser_reg = 1 for 28 cycles
// - clk_ser_data = clkusr
// 28-bit are barrel-shifting
//
assign p2s_rs_rpcdp_in = rtas_rs_rpcdp_out;
assign p2s_rs_rpcdn_in = rtas_rs_rpcdn_out;
assign p2s_rt_rpcdp_in = rtas_rt_rpcdp_out;
assign p2s_rt_rpcdn_in = rtas_rt_rpcdn_out;
// serial shift clock
assign p2s_clk_ser_data = (enserusr_gated === 1'b1) ? (~usr_clk) : // serial mode
(calclken_reg === 1'b1) ? (rtsm_caldone_out & sregn_rscaldone_out) : 1'b1; // one pulse for pload
// load D of shift register through - mux selection enser_reg
initial p2s_enser_reg = 1'b1; // load parallel code into D of shift reg - cleared by pllbiasen
always @(negedge usr_clk)
begin
p2s_enser_reg <= ~calclken_reg;
end
assign p2s_parallel_code = {p2s_rs_rpcdp_in,p2s_rs_rpcdn_in,p2s_rt_rpcdp_in,p2s_rt_rpcdn_in};
assign p2s_shift_d = (p2s_enser_reg === 1'b1) ? {p2s_shift_regs[26:0], p2s_shift_regs[27]} : p2s_parallel_code;
// shifting - cleared by PLLBIASEN
initial p2s_shift_regs = 'b0;
always @(posedge p2s_clk_ser_data)
begin
p2s_shift_regs <= p2s_shift_d;
end
assign p2s_ser_data_out = (enserusr_gated === 1'b1) ? p2s_shift_regs[27] : 1'bx;
// timing - input path
buf buf_rup_ipd (rup_ipd,rup);
buf buf_rdn_ipd (rdn_ipd,rdn);
buf buf_terminationclock_ipd (terminationclock_ipd,terminationclock);
buf buf_terminationclear_ipd (terminationclear_ipd,terminationclear);
buf buf_terminationenable_ipd (terminationenable_ipd, terminationenable);
buf buf_serializerenable_ipd (serializerenable_ipd,serializerenable);
buf buf_terminationcontrolin_ipd (terminationcontrolin_ipd,terminationcontrolin);
buf buf_otherserializerenable_ipd [8:0] (otherserializerenable_ipd,otherserializerenable);
endmodule // arriaiigz_termination
//-----------------------------------------------------------------------------
//
// Module Name : arriaiigz_termination_logic
//
// Description : ARRIAIIGZ Termination Logic Atom
// Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_termination_logic (
serialloadenable,terminationclock,parallelloadenable,terminationdata,
devclrn,devpor,
seriesterminationcontrol,parallelterminationcontrol
);
parameter test_mode = "false";
parameter lpm_type = "arriaiigz_termination_logic";
input serialloadenable;
input terminationclock;
input parallelloadenable;
input terminationdata;
input devclrn;
input devpor;
output [13:0] seriesterminationcontrol;
output [13:0] parallelterminationcontrol;
tri1 devclrn;
tri1 devpor;
wire usr_clk;
wire shift_clk;
wire pload_clk;
reg [27:0] shift_reg;
reg [27:0] output_reg;
assign seriesterminationcontrol = output_reg[27:14];
assign parallelterminationcontrol = output_reg[13:0];
assign #11 usr_clk = terminationclock;
assign shift_clk = (serialloadenable === 1'b0) ? 1'b0 : usr_clk; // serena & clk
assign pload_clk = (parallelloadenable === 1'b1) ? 1'b1 : 1'b0; // ploaden
initial begin
// does not get reset so whatever power-up values
shift_reg = 'b0;
output_reg = 'b0;
end
always @(posedge shift_clk)
shift_reg <= {shift_reg[26:0], terminationdata};
always @(posedge pload_clk)
output_reg <= shift_reg;
endmodule // arriaiigz_termination_logic
//--------------------------------------------------------------------------
// Module Name : arriaiigz_io_pad
// Description : Simulation model for arriaiigz IO pad
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_io_pad (
padin,
padout
);
parameter lpm_type = "arriaiigz_io_pad";
//INPUT PORTS
input padin; //Input Pad
//OUTPUT PORTS
output padout;//Output Pad
//INTERNAL SIGNALS
wire padin_ipd;
wire padout_opd;
//INPUT BUFFER INSERTION FOR VERILOG-XL
buf padin_buf (padin_ipd,padin);
assign padout_opd = padin_ipd;
//OUTPUT BUFFER INSERTION FOR VERILOG-XL
buf padout_buf (padout, padout_opd);
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_m_cntr
//
// Description : Timing simulation model for the M counter. This is the
// loop feedback counter for the ARRIAIIGZ PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module arriaiigz_m_cntr ( clk,
reset,
cout,
initial_value,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'b1 && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
end
clk_last_value = clk;
// cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // arriaiigz_m_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_n_cntr
//
// Description : Timing simulation model for the N counter. This is the
// input clock divide counter for the ARRIAIIGZ PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module arriaiigz_n_cntr ( clk,
reset,
cout,
modulus);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
clk_last_value = clk;
end
assign cout = tmp_cout;
endmodule // arriaiigz_n_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_scale_cntr
//
// Description : Timing simulation model for the output scale-down counters.
// This is a common model for the C0-C9
// output counters of the ARRIAIIGZ PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module arriaiigz_scale_cntr ( clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset)
begin
if (init !== 1'b1)
begin
clk_last_value = 0;
init = 1'b1;
end
if (reset)
begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end
else if (clk_last_value !== clk)
begin
if (mode == " off")
tmp_cout = 0;
else if (mode == "bypass")
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else if (first_rising_edge == 0)
begin
if (clk == 1)
begin
if (output_shift_count == initial_value)
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else
output_shift_count = output_shift_count + 1;
end
end
else if (output_shift_count < initial_value)
begin
if (clk == 1)
output_shift_count = output_shift_count + 1;
end
else
begin
count = count + 1;
if (mode == " even" && (count == (high*2) + 1))
tmp_cout = 0;
else if (mode == " odd" && (count == (high*2)))
tmp_cout = 0;
else if (count == (high + low)*2 + 1)
begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // arriaiigz_scale_cntr
//BEGIN MF PORTING DELETE
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_pll_reg
//
// Description : Simulation model for a simple DFF.
// This is required for the generation of the bit slip-signals.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module arriaiigz_pll_reg ( q,
clk,
ena,
d,
clrn,
prn);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
reg clk_last_value;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @ (clk or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q <= 1;
else if (clrn == 1'b0)
q <= 0;
else if ((clk === 1'b1) && (clk_last_value === 1'b0) && (ena === 1'b1))
q <= d;
clk_last_value = clk;
end
endmodule // arriaiigz_pll_reg
//END MF PORTING DELETE
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_pll
//
// Description : Timing simulation model for the ARRIAIIGZ PLL.
// In the functional mode, it is also the model for the altpll
// megafunction.
//
// Limitations : Does not support Spread Spectrum and Bandwidth.
//
// Outputs : Up to 10 output clocks, each defined by its own set of
// parameters. Locked output (active high) indicates when the
// PLL locks. clkbad and activeclock are used for
// clock switchover to indicate which input clock has gone
// bad, when the clock switchover initiates and which input
// clock is being used as the reference, respectively.
// scandataout is the data output of the serial scan chain.
//
// New Features : The list below outlines key new features in ARRIAIIGZ:
// 1. Dynamic Phase Reconfiguration
// 2. Dynamic PLL Reconfiguration (different protocol)
// 3. More output counters
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`define WORD_LENGTH 18
module arriaiigz_pll (inclk,
fbin,
fbout,
clkswitch,
areset,
pfdena,
scanclk,
scandata,
scanclkena,
configupdate,
clk,
phasecounterselect,
phaseupdown,
phasestep,
clkbad,
activeclock,
locked,
scandataout,
scandone,
phasedone,
vcooverrange,
vcounderrange
);
parameter operation_mode = "normal";
parameter pll_type = "auto"; // auto,fast(left_right),enhanced(top_bottom)
parameter compensate_clock = "clock0";
parameter inclk0_input_frequency = 0;
parameter inclk1_input_frequency = 0;
parameter self_reset_on_loss_lock = "off";
parameter switch_over_type = "auto";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "off";
parameter dpa_multiply_by = 0;
parameter dpa_divide_by = 0;
parameter dpa_divider = 0; // 0, 1, 2, 4
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false";
parameter lock_high = 0; // 0 .. 4095
parameter lock_low = 0; // 0 .. 7
parameter lock_window_ui = "0.05"; // "0.05", "0.1", "0.15", "0.2"
parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0;
parameter clk0_divide_by = 0;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 0;
parameter clk1_divide_by = 0;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 0;
parameter clk2_divide_by = 0;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 0;
parameter clk3_divide_by = 0;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 0;
parameter clk4_divide_by = 0;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter clk5_output_frequency = 0;
parameter clk5_multiply_by = 0;
parameter clk5_divide_by = 0;
parameter clk5_phase_shift = "0";
parameter clk5_duty_cycle = 50;
parameter clk6_output_frequency = 0;
parameter clk6_multiply_by = 0;
parameter clk6_divide_by = 0;
parameter clk6_phase_shift = "0";
parameter clk6_duty_cycle = 50;
parameter clk7_output_frequency = 0;
parameter clk7_multiply_by = 0;
parameter clk7_divide_by = 0;
parameter clk7_phase_shift = "0";
parameter clk7_duty_cycle = 50;
parameter clk8_output_frequency = 0;
parameter clk8_multiply_by = 0;
parameter clk8_divide_by = 0;
parameter clk8_phase_shift = "0";
parameter clk8_duty_cycle = 50;
parameter clk9_output_frequency = 0;
parameter clk9_multiply_by = 0;
parameter clk9_divide_by = 0;
parameter clk9_phase_shift = "0";
parameter clk9_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// ADVANCED USE PARAMETERS
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter c5_high = 1;
parameter c5_low = 1;
parameter c5_initial = 1;
parameter c5_mode = "bypass";
parameter c5_ph = 0;
parameter c6_high = 1;
parameter c6_low = 1;
parameter c6_initial = 1;
parameter c6_mode = "bypass";
parameter c6_ph = 0;
parameter c7_high = 1;
parameter c7_low = 1;
parameter c7_initial = 1;
parameter c7_mode = "bypass";
parameter c7_ph = 0;
parameter c8_high = 1;
parameter c8_low = 1;
parameter c8_initial = 1;
parameter c8_mode = "bypass";
parameter c8_ph = 0;
parameter c9_high = 1;
parameter c9_low = 1;
parameter c9_initial = 1;
parameter c9_mode = "bypass";
parameter c9_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "unused";
parameter clk1_counter = "unused";
parameter clk2_counter = "unused";
parameter clk3_counter = "unused";
parameter clk4_counter = "unused";
parameter clk5_counter = "unused";
parameter clk6_counter = "unused";
parameter clk7_counter = "unused";
parameter clk8_counter = "unused";
parameter clk9_counter = "unused";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter c5_use_casc_in = "off";
parameter c6_use_casc_in = "off";
parameter c7_use_casc_in = "off";
parameter c8_use_casc_in = "off";
parameter c9_use_casc_in = "off";
parameter m_test_source = -1;
parameter c0_test_source = -1;
parameter c1_test_source = -1;
parameter c2_test_source = -1;
parameter c3_test_source = -1;
parameter c4_test_source = -1;
parameter c5_test_source = -1;
parameter c6_test_source = -1;
parameter c7_test_source = -1;
parameter c8_test_source = -1;
parameter c9_test_source = -1;
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1; // 1 .. 2
parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10;
parameter loop_filter_r = "1.0"; // "1.0", "2.0", "4.0", "6.0", "8.0", "12.0", "16.0", "20.0"
parameter loop_filter_c = 0; // 0 , 2 , 4
parameter pll_compensation_delay = 0;
parameter simulation_type = "functional";
parameter lpm_type = "arriaiigz_pll";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter down_spread = "0.0";
parameter lock_c = 4;
parameter sim_gate_lock_device_behavior = "off";
parameter clk0_phase_shift_num = 0;
parameter clk1_phase_shift_num = 0;
parameter clk2_phase_shift_num = 0;
parameter clk3_phase_shift_num = 0;
parameter clk4_phase_shift_num = 0;
parameter family_name = "ARRIAIIGZ";
parameter clk0_use_even_counter_mode = "off";
parameter clk1_use_even_counter_mode = "off";
parameter clk2_use_even_counter_mode = "off";
parameter clk3_use_even_counter_mode = "off";
parameter clk4_use_even_counter_mode = "off";
parameter clk5_use_even_counter_mode = "off";
parameter clk6_use_even_counter_mode = "off";
parameter clk7_use_even_counter_mode = "off";
parameter clk8_use_even_counter_mode = "off";
parameter clk9_use_even_counter_mode = "off";
parameter clk0_use_even_counter_value = "off";
parameter clk1_use_even_counter_value = "off";
parameter clk2_use_even_counter_value = "off";
parameter clk3_use_even_counter_value = "off";
parameter clk4_use_even_counter_value = "off";
parameter clk5_use_even_counter_value = "off";
parameter clk6_use_even_counter_value = "off";
parameter clk7_use_even_counter_value = "off";
parameter clk8_use_even_counter_value = "off";
parameter clk9_use_even_counter_value = "off";
// TEST ONLY
parameter init_block_reset_a_count = 1;
parameter init_block_reset_b_count = 1;
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter phase_counter_select_width = 4;
parameter lock_window = 5;
parameter inclk0_freq = inclk0_input_frequency;
parameter inclk1_freq = inclk1_input_frequency;
parameter charge_pump_current_bits = 0;
parameter lock_window_ui_bits = 0;
parameter loop_filter_c_bits = 0;
parameter loop_filter_r_bits = 0;
parameter test_counter_c0_delay_chain_bits = 0;
parameter test_counter_c1_delay_chain_bits = 0;
parameter test_counter_c2_delay_chain_bits = 0;
parameter test_counter_c3_delay_chain_bits = 0;
parameter test_counter_c4_delay_chain_bits = 0;
parameter test_counter_c5_delay_chain_bits = 0;
parameter test_counter_c6_delay_chain_bits = 0;
parameter test_counter_c7_delay_chain_bits = 0;
parameter test_counter_c8_delay_chain_bits = 0;
parameter test_counter_c9_delay_chain_bits = 0;
parameter test_counter_m_delay_chain_bits = 0;
parameter test_counter_n_delay_chain_bits = 0;
parameter test_feedback_comp_delay_chain_bits = 0;
parameter test_input_comp_delay_chain_bits = 0;
parameter test_volt_reg_output_mode_bits = 0;
parameter test_volt_reg_output_voltage_bits = 0;
parameter test_volt_reg_test_mode = "false";
parameter vco_range_detector_high_bits = -1;
parameter vco_range_detector_low_bits = -1;
parameter scan_chain_mif_file = "";
parameter test_counter_c3_sclk_delay_chain_bits = -1;
parameter test_counter_c4_sclk_delay_chain_bits = -1;
parameter test_counter_c5_lden_delay_chain_bits = -1;
parameter test_counter_c6_lden_delay_chain_bits = -1;
parameter auto_settings = "true";
// LOCAL_PARAMETERS_END
// INPUT PORTS
input [1:0] inclk;
input fbin;
input clkswitch;
input areset;
input pfdena;
input [phase_counter_select_width - 1:0] phasecounterselect;
input phaseupdown;
input phasestep;
input scanclk;
input scanclkena;
input scandata;
input configupdate;
// OUTPUT PORTS
output [9:0] clk;
output [1:0] clkbad;
output activeclock;
output locked;
output scandataout;
output scandone;
output fbout;
output phasedone;
output vcooverrange;
output vcounderrange;
// TIMING CHECKS
specify
$setuphold(negedge scanclk, scandata, 0, 0);
$setuphold(negedge scanclk, scanclkena, 0, 0);
endspecify
// INTERNAL VARIABLES AND NETS
reg [8*6:1] clk_num[0:9];
integer scan_chain_length;
integer i;
integer j;
integer k;
integer x;
integer y;
integer l_index;
integer gate_count;
integer egpp_offset;
integer sched_time;
integer delay_chain;
integer low;
integer high;
integer initial_delay;
integer fbk_phase;
integer fbk_delay;
integer phase_shift[0:7];
integer last_phase_shift[0:7];
integer m_times_vco_period;
integer new_m_times_vco_period;
integer refclk_period;
integer fbclk_period;
integer high_time;
integer low_time;
integer my_rem;
integer tmp_rem;
integer rem;
integer tmp_vco_per;
integer vco_per;
integer offset;
integer temp_offset;
integer cycles_to_lock;
integer cycles_to_unlock;
integer loop_xplier;
integer loop_initial;
integer loop_ph;
integer cycle_to_adjust;
integer total_pull_back;
integer pull_back_M;
time fbclk_time;
time first_fbclk_time;
time refclk_time;
reg switch_clock;
reg [31:0] real_lock_high;
reg got_first_refclk;
reg got_second_refclk;
reg got_first_fbclk;
reg refclk_last_value;
reg fbclk_last_value;
reg inclk_last_value;
reg pll_is_locked;
reg locked_tmp;
reg areset_last_value;
reg pfdena_last_value;
reg inclk_out_of_range;
reg schedule_vco_last_value;
// Test bypass lock detect
reg pfd_locked;
integer cycles_pfd_low, cycles_pfd_high;
reg gate_out;
reg vco_val;
reg [31:0] m_initial_val;
reg [31:0] m_val[0:1];
reg [31:0] n_val[0:1];
reg [31:0] m_delay;
reg [8*6:1] m_mode_val[0:1];
reg [8*6:1] n_mode_val[0:1];
reg [31:0] c_high_val[0:9];
reg [31:0] c_low_val[0:9];
reg [8*6:1] c_mode_val[0:9];
reg [31:0] c_initial_val[0:9];
integer c_ph_val[0:9];
reg [31:0] c_val; // placeholder for c_high,c_low values
// VCO Frequency Range control
reg vco_over, vco_under;
// temporary registers for reprogramming
integer c_ph_val_tmp[0:9];
reg [31:0] c_high_val_tmp[0:9];
reg [31:0] c_hval[0:9];
reg [31:0] c_low_val_tmp[0:9];
reg [31:0] c_lval[0:9];
reg [8*6:1] c_mode_val_tmp[0:9];
// hold registers for reprogramming
integer c_ph_val_hold[0:9];
reg [31:0] c_high_val_hold[0:9];
reg [31:0] c_low_val_hold[0:9];
reg [8*6:1] c_mode_val_hold[0:9];
// old values
reg [31:0] m_val_old[0:1];
reg [31:0] m_val_tmp[0:1];
reg [31:0] n_val_old[0:1];
reg [8*6:1] m_mode_val_old[0:1];
reg [8*6:1] n_mode_val_old[0:1];
reg [31:0] c_high_val_old[0:9];
reg [31:0] c_low_val_old[0:9];
reg [8*6:1] c_mode_val_old[0:9];
integer c_ph_val_old[0:9];
integer m_ph_val_old;
integer m_ph_val_tmp;
integer cp_curr_old;
integer cp_curr_val;
integer lfc_old;
integer lfc_val;
integer vco_cur;
integer vco_old;
reg [9*8:1] lfr_val;
reg [9*8:1] lfr_old;
reg [1:2] lfc_val_bit_setting, lfc_val_old_bit_setting;
reg vco_val_bit_setting, vco_val_old_bit_setting;
reg [3:7] lfr_val_bit_setting, lfr_val_old_bit_setting;
reg [14:16] cp_curr_bit_setting, cp_curr_old_bit_setting;
// Setting on - display real values
// Setting off - display only bits
reg pll_reconfig_display_full_setting;
reg [7:0] m_hi;
reg [7:0] m_lo;
reg [7:0] n_hi;
reg [7:0] n_lo;
// ph tap orig values (POF)
integer c_ph_val_orig[0:9];
integer m_ph_val_orig;
reg schedule_vco;
reg stop_vco;
reg inclk_n;
reg inclk_man;
reg inclk_es;
reg [7:0] vco_out;
reg [7:0] vco_tap;
reg [7:0] vco_out_last_value;
reg [7:0] vco_tap_last_value;
wire inclk_c0;
wire inclk_c1;
wire inclk_c2;
wire inclk_c3;
wire inclk_c4;
wire inclk_c5;
wire inclk_c6;
wire inclk_c7;
wire inclk_c8;
wire inclk_c9;
wire inclk_c0_from_vco;
wire inclk_c1_from_vco;
wire inclk_c2_from_vco;
wire inclk_c3_from_vco;
wire inclk_c4_from_vco;
wire inclk_c5_from_vco;
wire inclk_c6_from_vco;
wire inclk_c7_from_vco;
wire inclk_c8_from_vco;
wire inclk_c9_from_vco;
wire inclk_m_from_vco;
wire inclk_m;
wire pfdena_wire;
wire [9:0] clk_tmp, clk_out_pfd;
wire [9:0] clk_out;
wire c0_clk;
wire c1_clk;
wire c2_clk;
wire c3_clk;
wire c4_clk;
wire c5_clk;
wire c6_clk;
wire c7_clk;
wire c8_clk;
wire c9_clk;
reg first_schedule;
reg vco_period_was_phase_adjusted;
reg phase_adjust_was_scheduled;
wire refclk;
wire fbclk;
wire pllena_reg;
wire test_mode_inclk;
// Self Reset
wire reset_self;
// Clock Switchover
reg clk0_is_bad;
reg clk1_is_bad;
reg inclk0_last_value;
reg inclk1_last_value;
reg other_clock_value;
reg other_clock_last_value;
reg primary_clk_is_bad;
reg current_clk_is_bad;
reg external_switch;
reg active_clock;
reg got_curr_clk_falling_edge_after_clkswitch;
integer clk0_count;
integer clk1_count;
integer switch_over_count;
wire scandataout_tmp;
reg scandata_in, scandata_out; // hold scan data in negative-edge triggered ff (on either side on chain)
reg scandone_tmp;
reg initiate_reconfig;
integer quiet_time;
integer slowest_clk_old;
integer slowest_clk_new;
reg reconfig_err;
reg error;
time scanclk_last_rising_edge;
time scanread_active_edge;
reg got_first_scanclk;
reg got_first_gated_scanclk;
reg gated_scanclk;
integer scanclk_period;
reg scanclk_last_value;
wire update_conf_latches;
reg update_conf_latches_reg;
reg [-1:232] scan_data;
reg scanclkena_reg; // register scanclkena on negative edge of scanclk
reg c0_rising_edge_transfer_done;
reg c1_rising_edge_transfer_done;
reg c2_rising_edge_transfer_done;
reg c3_rising_edge_transfer_done;
reg c4_rising_edge_transfer_done;
reg c5_rising_edge_transfer_done;
reg c6_rising_edge_transfer_done;
reg c7_rising_edge_transfer_done;
reg c8_rising_edge_transfer_done;
reg c9_rising_edge_transfer_done;
reg scanread_setup_violation;
integer index;
integer scanclk_cycles;
reg d_msg;
integer num_output_cntrs;
reg no_warn;
// Phase reconfig
reg [3:0] phasecounterselect_reg;
reg phaseupdown_reg;
reg phasestep_reg;
integer select_counter;
integer phasestep_high_count;
reg update_phase;
// LOCAL_PARAMETERS_BEGIN
parameter SCAN_CHAIN = 144;
parameter GPP_SCAN_CHAIN = 234;
parameter FAST_SCAN_CHAIN = 180;
// primary clk is always inclk0
parameter num_phase_taps = 8;
// LOCAL_PARAMETERS_END
// internal variables for scaling of multiply_by and divide_by values
integer i_clk0_mult_by;
integer i_clk0_div_by;
integer i_clk1_mult_by;
integer i_clk1_div_by;
integer i_clk2_mult_by;
integer i_clk2_div_by;
integer i_clk3_mult_by;
integer i_clk3_div_by;
integer i_clk4_mult_by;
integer i_clk4_div_by;
integer i_clk5_mult_by;
integer i_clk5_div_by;
integer i_clk6_mult_by;
integer i_clk6_div_by;
integer i_clk7_mult_by;
integer i_clk7_div_by;
integer i_clk8_mult_by;
integer i_clk8_div_by;
integer i_clk9_mult_by;
integer i_clk9_div_by;
integer max_d_value;
integer new_multiplier;
// internal variables for storing the phase shift number.(used in lvds mode only)
integer i_clk0_phase_shift;
integer i_clk1_phase_shift;
integer i_clk2_phase_shift;
integer i_clk3_phase_shift;
integer i_clk4_phase_shift;
// user to advanced internal signals
integer i_m_initial;
integer i_m;
integer i_n;
integer i_c_high[0:9];
integer i_c_low[0:9];
integer i_c_initial[0:9];
integer i_c_ph[0:9];
reg [8*6:1] i_c_mode[0:9];
integer i_vco_min;
integer i_vco_max;
integer i_vco_min_no_division;
integer i_vco_max_no_division;
integer i_vco_center;
integer i_pfd_min;
integer i_pfd_max;
integer i_m_ph;
integer m_ph_val;
reg [8*2:1] i_clk9_counter;
reg [8*2:1] i_clk8_counter;
reg [8*2:1] i_clk7_counter;
reg [8*2:1] i_clk6_counter;
reg [8*2:1] i_clk5_counter;
reg [8*2:1] i_clk4_counter;
reg [8*2:1] i_clk3_counter;
reg [8*2:1] i_clk2_counter;
reg [8*2:1] i_clk1_counter;
reg [8*2:1] i_clk0_counter;
integer i_charge_pump_current;
integer i_loop_filter_r;
integer max_neg_abs;
integer output_count;
integer new_divisor;
integer loop_filter_c_arr[0:3];
integer fpll_loop_filter_c_arr[0:3];
integer charge_pump_curr_arr[0:15];
reg pll_in_test_mode;
reg pll_is_in_reset;
reg pll_has_just_been_reconfigured;
// uppercase to lowercase parameter values
reg [8*`WORD_LENGTH:1] l_operation_mode;
reg [8*`WORD_LENGTH:1] l_pll_type;
reg [8*`WORD_LENGTH:1] l_compensate_clock;
reg [8*`WORD_LENGTH:1] l_scan_chain;
reg [8*`WORD_LENGTH:1] l_switch_over_type;
reg [8*`WORD_LENGTH:1] l_bandwidth_type;
reg [8*`WORD_LENGTH:1] l_simulation_type;
reg [8*`WORD_LENGTH:1] l_sim_gate_lock_device_behavior;
reg [8*`WORD_LENGTH:1] l_vco_frequency_control;
reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter;
reg [8*`WORD_LENGTH:1] l_self_reset_on_loss_lock;
integer current_clock;
integer current_clock_man;
reg is_fast_pll;
reg ic1_use_casc_in;
reg ic2_use_casc_in;
reg ic3_use_casc_in;
reg ic4_use_casc_in;
reg ic5_use_casc_in;
reg ic6_use_casc_in;
reg ic7_use_casc_in;
reg ic8_use_casc_in;
reg ic9_use_casc_in;
reg init;
reg tap0_is_active;
real inclk0_period, last_inclk0_period,inclk1_period, last_inclk1_period;
real last_inclk0_edge,last_inclk1_edge,diff_percent_period;
reg first_inclk0_edge_detect,first_inclk1_edge_detect;
specify
endspecify
// finds the closest integer fraction of a given pair of numerator and denominator.
task find_simple_integer_fraction;
input numerator;
input denominator;
input max_denom;
output fraction_num;
output fraction_div;
parameter max_iter = 20;
integer numerator;
integer denominator;
integer max_denom;
integer fraction_num;
integer fraction_div;
integer quotient_array[max_iter-1:0];
integer int_loop_iter;
integer int_quot;
integer m_value;
integer d_value;
integer old_m_value;
integer swap;
integer loop_iter;
integer num;
integer den;
integer i_max_iter;
begin
loop_iter = 0;
num = (numerator == 0) ? 1 : numerator;
den = (denominator == 0) ? 1 : denominator;
i_max_iter = max_iter;
while (loop_iter < i_max_iter)
begin
int_quot = num / den;
quotient_array[loop_iter] = int_quot;
num = num - (den*int_quot);
loop_iter=loop_iter+1;
if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter))
begin
// calculate the numerator and denominator if there is a restriction on the
// max denom value or if the loop is ending
m_value = 0;
d_value = 1;
// get the rounded value at this stage for the remaining fraction
if (den != 0)
begin
m_value = (2*num/den);
end
// calculate the fraction numerator and denominator at this stage
for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1)
begin
if (m_value == 0)
begin
m_value = quotient_array[int_loop_iter];
d_value = 1;
end
else
begin
old_m_value = m_value;
m_value = quotient_array[int_loop_iter]*m_value + d_value;
d_value = old_m_value;
end
end
// if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) || (max_denom == -1))
begin
fraction_num = m_value;
fraction_div = d_value;
end
// end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) && (max_denom != -1)) || (num == 0))
begin
i_max_iter = loop_iter;
end
end
// swap the numerator and denominator for the next round
swap = den;
den = num;
num = swap;
end
end
endtask // find_simple_integer_fraction
// get the absolute value
function integer abs;
input value;
integer value;
begin
if (value < 0)
abs = value * -1;
else abs = value;
end
endfunction
// find twice the period of the slowest clock
function integer slowest_clk;
input C0, C0_mode, C1, C1_mode, C2, C2_mode, C3, C3_mode, C4, C4_mode, C5, C5_mode, C6, C6_mode, C7, C7_mode, C8, C8_mode, C9, C9_mode, refclk, m_mod;
integer C0, C1, C2, C3, C4, C5, C6, C7, C8, C9;
reg [8*6:1] C0_mode, C1_mode, C2_mode, C3_mode, C4_mode, C5_mode, C6_mode, C7_mode, C8_mode, C9_mode;
integer refclk;
reg [31:0] m_mod;
integer max_modulus;
begin
max_modulus = 1;
if (C0_mode != "bypass" && C0_mode != " off")
max_modulus = C0;
if (C1 > max_modulus && C1_mode != "bypass" && C1_mode != " off")
max_modulus = C1;
if (C2 > max_modulus && C2_mode != "bypass" && C2_mode != " off")
max_modulus = C2;
if (C3 > max_modulus && C3_mode != "bypass" && C3_mode != " off")
max_modulus = C3;
if (C4 > max_modulus && C4_mode != "bypass" && C4_mode != " off")
max_modulus = C4;
if (C5 > max_modulus && C5_mode != "bypass" && C5_mode != " off")
max_modulus = C5;
if (C6 > max_modulus && C6_mode != "bypass" && C6_mode != " off")
max_modulus = C6;
if (C7 > max_modulus && C7_mode != "bypass" && C7_mode != " off")
max_modulus = C7;
if (C8 > max_modulus && C8_mode != "bypass" && C8_mode != " off")
max_modulus = C8;
if (C9 > max_modulus && C9_mode != "bypass" && C9_mode != " off")
max_modulus = C9;
slowest_clk = (refclk * max_modulus *2 / m_mod);
end
endfunction
// count the number of digits in the given integer
function integer count_digit;
input X;
integer X;
integer count, result;
begin
count = 0;
result = X;
while (result != 0)
begin
result = (result / 10);
count = count + 1;
end
count_digit = count;
end
endfunction
// reduce the given huge number(X) to Y significant digits
function integer scale_num;
input X, Y;
integer X, Y;
integer count;
integer fac_ten, lc;
begin
fac_ten = 1;
count = count_digit(X);
for (lc = 0; lc < (count-Y); lc = lc + 1)
fac_ten = fac_ten * 10;
scale_num = (X / fac_ten);
end
endfunction
// find the greatest common denominator of X and Y
function integer gcd;
input X,Y;
integer X,Y;
integer L, S, R, G;
begin
if (X < Y) // find which is smaller.
begin
S = X;
L = Y;
end
else
begin
S = Y;
L = X;
end
R = S;
while ( R > 1)
begin
S = L;
L = R;
R = S % L; // divide bigger number by smaller.
// remainder becomes smaller number.
end
if (R == 0) // if evenly divisible then L is gcd else it is 1.
G = L;
else
G = R;
gcd = G;
end
endfunction
// find the least common multiple of A1 to A10
function integer lcm;
input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R;
begin
M1 = (A1 * A2)/gcd(A1, A2);
M2 = (M1 * A3)/gcd(M1, A3);
M3 = (M2 * A4)/gcd(M2, A4);
M4 = (M3 * A5)/gcd(M3, A5);
M5 = (M4 * A6)/gcd(M4, A6);
M6 = (M5 * A7)/gcd(M5, A7);
M7 = (M6 * A8)/gcd(M6, A8);
M8 = (M7 * A9)/gcd(M7, A9);
M9 = (M8 * A10)/gcd(M8, A10);
if (M9 < 3)
R = 10;
else if ((M9 <= 10) && (M9 >= 3))
R = 4 * M9;
else if (M9 > 1000)
R = scale_num(M9, 3);
else
R = M9;
lcm = R;
end
endfunction
// find the M and N values for Manual phase based on the following 5 criterias:
// 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
// 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
// 3. M is less than 512
// 4. N is less than 512
// 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
// of the desired vco-phase-shift-step
task find_m_and_n_4_manual_phase;
input inclock_period;
input vco_phase_shift_step;
input clk0_mult, clk1_mult, clk2_mult, clk3_mult, clk4_mult;
input clk5_mult, clk6_mult, clk7_mult, clk8_mult, clk9_mult;
input clk0_div, clk1_div, clk2_div, clk3_div, clk4_div;
input clk5_div, clk6_div, clk7_div, clk8_div, clk9_div;
input clk0_used, clk1_used, clk2_used, clk3_used, clk4_used;
input clk5_used, clk6_used, clk7_used, clk8_used, clk9_used;
output m;
output n;
parameter max_m = 511;
parameter max_n = 511;
parameter max_pfd = 720;
parameter min_pfd = 5;
parameter max_vco = 1600; // max vco frequency. (in mHz)
parameter min_vco = 300; // min vco frequency. (in mHz)
parameter max_offset = 0.004;
reg[160:1] clk0_used, clk1_used, clk2_used, clk3_used, clk4_used;
reg[160:1] clk5_used, clk6_used, clk7_used, clk8_used, clk9_used;
integer inclock_period;
integer vco_phase_shift_step;
integer clk0_mult, clk1_mult, clk2_mult, clk3_mult, clk4_mult;
integer clk5_mult, clk6_mult, clk7_mult, clk8_mult, clk9_mult;
integer clk0_div, clk1_div, clk2_div, clk3_div, clk4_div;
integer clk5_div, clk6_div, clk7_div, clk8_div, clk9_div;
integer m;
integer n;
integer pre_m;
integer pre_n;
integer m_out;
integer n_out;
integer closest_vco_step_value;
integer vco_period;
integer pfd_freq;
integer vco_freq;
integer vco_ps_step_value;
real clk0_div_factor_real;
real clk1_div_factor_real;
real clk2_div_factor_real;
real clk3_div_factor_real;
real clk4_div_factor_real;
real clk5_div_factor_real;
real clk6_div_factor_real;
real clk7_div_factor_real;
real clk8_div_factor_real;
real clk9_div_factor_real;
real clk0_div_factor_diff;
real clk1_div_factor_diff;
real clk2_div_factor_diff;
real clk3_div_factor_diff;
real clk4_div_factor_diff;
real clk5_div_factor_diff;
real clk6_div_factor_diff;
real clk7_div_factor_diff;
real clk8_div_factor_diff;
real clk9_div_factor_diff;
integer clk0_div_factor_int;
integer clk1_div_factor_int;
integer clk2_div_factor_int;
integer clk3_div_factor_int;
integer clk4_div_factor_int;
integer clk5_div_factor_int;
integer clk6_div_factor_int;
integer clk7_div_factor_int;
integer clk8_div_factor_int;
integer clk9_div_factor_int;
begin
vco_period = vco_phase_shift_step * 8;
pre_m = 0;
pre_n = 0;
closest_vco_step_value = 0;
begin : LOOP_1
for (n_out = 1; n_out < max_n; n_out = n_out +1)
begin
for (m_out = 1; m_out < max_m; m_out = m_out +1)
begin
clk0_div_factor_real = (clk0_div * m_out * 1.0 ) / (clk0_mult * n_out);
clk1_div_factor_real = (clk1_div * m_out * 1.0) / (clk1_mult * n_out);
clk2_div_factor_real = (clk2_div * m_out * 1.0) / (clk2_mult * n_out);
clk3_div_factor_real = (clk3_div * m_out * 1.0) / (clk3_mult * n_out);
clk4_div_factor_real = (clk4_div * m_out * 1.0) / (clk4_mult * n_out);
clk5_div_factor_real = (clk5_div * m_out * 1.0) / (clk5_mult * n_out);
clk6_div_factor_real = (clk6_div * m_out * 1.0) / (clk6_mult * n_out);
clk7_div_factor_real = (clk7_div * m_out * 1.0) / (clk7_mult * n_out);
clk8_div_factor_real = (clk8_div * m_out * 1.0) / (clk8_mult * n_out);
clk9_div_factor_real = (clk9_div * m_out * 1.0) / (clk9_mult * n_out);
clk0_div_factor_int = clk0_div_factor_real;
clk1_div_factor_int = clk1_div_factor_real;
clk2_div_factor_int = clk2_div_factor_real;
clk3_div_factor_int = clk3_div_factor_real;
clk4_div_factor_int = clk4_div_factor_real;
clk5_div_factor_int = clk5_div_factor_real;
clk6_div_factor_int = clk6_div_factor_real;
clk7_div_factor_int = clk7_div_factor_real;
clk8_div_factor_int = clk8_div_factor_real;
clk9_div_factor_int = clk9_div_factor_real;
clk0_div_factor_diff = (clk0_div_factor_real - clk0_div_factor_int < 0) ? (clk0_div_factor_real - clk0_div_factor_int) * -1.0 : clk0_div_factor_real - clk0_div_factor_int;
clk1_div_factor_diff = (clk1_div_factor_real - clk1_div_factor_int < 0) ? (clk1_div_factor_real - clk1_div_factor_int) * -1.0 : clk1_div_factor_real - clk1_div_factor_int;
clk2_div_factor_diff = (clk2_div_factor_real - clk2_div_factor_int < 0) ? (clk2_div_factor_real - clk2_div_factor_int) * -1.0 : clk2_div_factor_real - clk2_div_factor_int;
clk3_div_factor_diff = (clk3_div_factor_real - clk3_div_factor_int < 0) ? (clk3_div_factor_real - clk3_div_factor_int) * -1.0 : clk3_div_factor_real - clk3_div_factor_int;
clk4_div_factor_diff = (clk4_div_factor_real - clk4_div_factor_int < 0) ? (clk4_div_factor_real - clk4_div_factor_int) * -1.0 : clk4_div_factor_real - clk4_div_factor_int;
clk5_div_factor_diff = (clk5_div_factor_real - clk5_div_factor_int < 0) ? (clk5_div_factor_real - clk5_div_factor_int) * -1.0 : clk5_div_factor_real - clk5_div_factor_int;
clk6_div_factor_diff = (clk6_div_factor_real - clk6_div_factor_int < 0) ? (clk6_div_factor_real - clk6_div_factor_int) * -1.0 : clk6_div_factor_real - clk6_div_factor_int;
clk7_div_factor_diff = (clk7_div_factor_real - clk7_div_factor_int < 0) ? (clk7_div_factor_real - clk7_div_factor_int) * -1.0 : clk7_div_factor_real - clk7_div_factor_int;
clk8_div_factor_diff = (clk8_div_factor_real - clk8_div_factor_int < 0) ? (clk8_div_factor_real - clk8_div_factor_int) * -1.0 : clk8_div_factor_real - clk8_div_factor_int;
clk9_div_factor_diff = (clk9_div_factor_real - clk9_div_factor_int < 0) ? (clk9_div_factor_real - clk9_div_factor_int) * -1.0 : clk9_div_factor_real - clk9_div_factor_int;
if (((clk0_div_factor_diff < max_offset) || (clk0_used == "unused")) &&
((clk1_div_factor_diff < max_offset) || (clk1_used == "unused")) &&
((clk2_div_factor_diff < max_offset) || (clk2_used == "unused")) &&
((clk3_div_factor_diff < max_offset) || (clk3_used == "unused")) &&
((clk4_div_factor_diff < max_offset) || (clk4_used == "unused")) &&
((clk5_div_factor_diff < max_offset) || (clk5_used == "unused")) &&
((clk6_div_factor_diff < max_offset) || (clk6_used == "unused")) &&
((clk7_div_factor_diff < max_offset) || (clk7_used == "unused")) &&
((clk8_div_factor_diff < max_offset) || (clk8_used == "unused")) &&
((clk9_div_factor_diff < max_offset) || (clk9_used == "unused")) )
begin
if ((m_out != 0) && (n_out != 0))
begin
pfd_freq = 1000000 / (inclock_period * n_out);
vco_freq = (1000000 * m_out) / (inclock_period * n_out);
vco_ps_step_value = (inclock_period * n_out) / (8 * m_out);
if ( (m_out < max_m) && (n_out < max_n) && (pfd_freq >= min_pfd) && (pfd_freq <= max_pfd) &&
(vco_freq >= min_vco) && (vco_freq <= max_vco) )
begin
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
begin
pre_m = m_out;
pre_n = n_out;
disable LOOP_1;
end
else
begin
if ((closest_vco_step_value == 0) || (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
begin
pre_m = m_out;
pre_n = n_out;
closest_vco_step_value = vco_ps_step_value;
end
end
end
end
end
end
end
end
if ((pre_m != 0) && (pre_n != 0))
begin
find_simple_integer_fraction(pre_m, pre_n,
max_n, m, n);
end
else
begin
n = 1;
m = lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end
end
endtask // find_m_and_n_4_manual_phase
// find the factor of division of the output clock frequency
// compared to the VCO
function integer output_counter_value;
input clk_divide, clk_mult, M, N;
integer clk_divide, clk_mult, M, N;
real r;
integer r_int;
begin
r = (clk_divide * M * 1.0)/(clk_mult * N);
r_int = r;
output_counter_value = r_int;
end
endfunction
// find the mode of each of the PLL counters - bypass, even or odd
function [8*6:1] counter_mode;
input duty_cycle;
input output_counter_value;
integer duty_cycle;
integer output_counter_value;
integer half_cycle_high;
reg [8*6:1] R;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
if (output_counter_value == 1)
R = "bypass";
else if ((half_cycle_high % 2) == 0)
R = " even";
else
R = " odd";
counter_mode = R;
end
endfunction
// find the number of VCO clock cycles to hold the output clock high
function integer counter_high;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle;
integer half_cycle_high;
integer tmp_counter_high;
integer mode;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_high = tmp_counter_high + !mode;
end
endfunction
// find the number of VCO clock cycles to hold the output clock low
function integer counter_low;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle, counter_h;
integer half_cycle_high;
integer mode;
integer tmp_counter_high;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100.0;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_h = tmp_counter_high + !mode;
counter_low = output_counter_value - counter_h;
end
endfunction
// find the smallest time delay amongst t1 to t10
function integer mintimedelay;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2)
m1 = t1;
else
m1 = t2;
if (m1 < t3)
m2 = m1;
else
m2 = t3;
if (m2 < t4)
m3 = m2;
else
m3 = t4;
if (m3 < t5)
m4 = m3;
else
m4 = t5;
if (m4 < t6)
m5 = m4;
else
m5 = t6;
if (m5 < t7)
m6 = m5;
else
m6 = t7;
if (m6 < t8)
m7 = m6;
else
m7 = t8;
if (m7 < t9)
m8 = m7;
else
m8 = t9;
if (m8 < t10)
m9 = m8;
else
m9 = t10;
if (m9 > 0)
mintimedelay = m9;
else
mintimedelay = 0;
end
endfunction
// find the numerically largest negative number, and return its absolute value
function integer maxnegabs;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2) m1 = t1; else m1 = t2;
if (m1 < t3) m2 = m1; else m2 = t3;
if (m2 < t4) m3 = m2; else m3 = t4;
if (m3 < t5) m4 = m3; else m4 = t5;
if (m4 < t6) m5 = m4; else m5 = t6;
if (m5 < t7) m6 = m5; else m6 = t7;
if (m6 < t8) m7 = m6; else m7 = t8;
if (m7 < t9) m8 = m7; else m8 = t9;
if (m8 < t10) m9 = m8; else m9 = t10;
maxnegabs = (m9 < 0) ? 0 - m9 : 0;
end
endfunction
// adjust the given tap_phase by adding the largest negative number (ph_base)
function integer ph_adjust;
input tap_phase, ph_base;
integer tap_phase, ph_base;
begin
ph_adjust = tap_phase + ph_base;
end
endfunction
// find the number of VCO clock cycles to wait initially before the first
// rising edge of the output clock
function integer counter_initial;
input tap_phase, m, n;
integer tap_phase, m, n, phase;
begin
if (tap_phase < 0) tap_phase = 0 - tap_phase;
// adding 0.5 for rounding correction (required in order to round
// to the nearest integer instead of truncating)
phase = ((tap_phase * m) / (360.0 * n)) + 0.6;
counter_initial = phase;
end
endfunction
// find which VCO phase tap to align the rising edge of the output clock to
function integer counter_ph;
input tap_phase;
input m,n;
integer m,n, phase;
integer tap_phase;
begin
// adding 0.5 for rounding correction
phase = (tap_phase * m / n) + 0.5;
counter_ph = (phase % 360) / 45.0;
if (counter_ph == 8)
counter_ph = 0;
end
endfunction
// convert the given string to length 6 by padding with spaces
function [8*6:1] translate_string;
input [8*6:1] mode;
reg [8*6:1] new_mode;
begin
if (mode == "bypass")
new_mode = "bypass";
else if (mode == "even")
new_mode = " even";
else if (mode == "odd")
new_mode = " odd";
translate_string = new_mode;
end
endfunction
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
// this is for arriaiigz lvds only
// convert phase delay to integer
function integer get_int_phase_shift;
input [8*16:1] s;
input i_phase_shift;
integer i_phase_shift;
begin
if (i_phase_shift != 0)
begin
get_int_phase_shift = i_phase_shift;
end
else
begin
get_int_phase_shift = str2int(s);
end
end
endfunction
// calculate the given phase shift (in ps) in terms of degrees
function integer get_phase_degree;
input phase_shift;
integer phase_shift, result;
begin
result = (phase_shift * 360) / inclk0_freq;
// this is to round up the calculation result
if ( result > 0 )
result = result + 1;
else if ( result < 0 )
result = result - 1;
else
result = 0;
// assign the rounded up result
get_phase_degree = result;
end
endfunction
// convert uppercase parameter values to lowercase
// assumes that the maximum character length of a parameter is 18
function [8*`WORD_LENGTH:1] alpha_tolower;
input [8*`WORD_LENGTH:1] given_string;
reg [8*`WORD_LENGTH:1] return_string;
reg [8*`WORD_LENGTH:1] reg_string;
reg [8:1] tmp;
reg [8:1] conv_char;
integer byte_count;
begin
return_string = " "; // initialise strings to spaces
conv_char = " ";
reg_string = given_string;
for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1)
begin
tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)];
reg_string = reg_string << 8;
if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
return_string = {return_string, conv_char};
end
else
return_string = {return_string, tmp};
end
alpha_tolower = return_string;
end
endfunction
function integer display_msg;
input [8*2:1] cntr_name;
input msg_code;
integer msg_code;
begin
if (msg_code == 1)
$display ("Warning : %s counter switched from BYPASS mode to enabled. PLL may lose lock.", cntr_name);
else if (msg_code == 2)
$display ("Warning : Illegal 1 value for %s counter. Instead, the %s counter should be BYPASSED. Reconfiguration may not work.", cntr_name, cntr_name);
else if (msg_code == 3)
$display ("Warning : Illegal value for counter %s in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.", cntr_name);
else if (msg_code == 4)
$display ("Warning : %s counter switched from enabled to BYPASS mode. PLL may lose lock.", cntr_name);
$display ("Time: %0t Instance: %m", $time);
display_msg = 1;
end
endfunction
initial
begin
scandata_out = 1'b0;
first_inclk0_edge_detect = 1'b0;
first_inclk1_edge_detect = 1'b0;
pll_reconfig_display_full_setting = 1'b0;
initiate_reconfig = 1'b0;
switch_over_count = 0;
// convert string parameter values from uppercase to lowercase,
// as expected in this model
l_operation_mode = alpha_tolower(operation_mode);
l_pll_type = alpha_tolower(pll_type);
l_compensate_clock = alpha_tolower(compensate_clock);
l_switch_over_type = alpha_tolower(switch_over_type);
l_bandwidth_type = alpha_tolower(bandwidth_type);
l_simulation_type = alpha_tolower(simulation_type);
l_sim_gate_lock_device_behavior = alpha_tolower(sim_gate_lock_device_behavior);
l_vco_frequency_control = alpha_tolower(vco_frequency_control);
l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter);
l_self_reset_on_loss_lock = alpha_tolower(self_reset_on_loss_lock);
real_lock_high = (l_sim_gate_lock_device_behavior == "on") ? lock_high : 0;
// initialize charge_pump_current, and loop_filter tables
loop_filter_c_arr[0] = 0;
loop_filter_c_arr[1] = 0;
loop_filter_c_arr[2] = 0;
loop_filter_c_arr[3] = 0;
fpll_loop_filter_c_arr[0] = 0;
fpll_loop_filter_c_arr[1] = 0;
fpll_loop_filter_c_arr[2] = 0;
fpll_loop_filter_c_arr[3] = 0;
charge_pump_curr_arr[0] = 0;
charge_pump_curr_arr[1] = 0;
charge_pump_curr_arr[2] = 0;
charge_pump_curr_arr[3] = 0;
charge_pump_curr_arr[4] = 0;
charge_pump_curr_arr[5] = 0;
charge_pump_curr_arr[6] = 0;
charge_pump_curr_arr[7] = 0;
charge_pump_curr_arr[8] = 0;
charge_pump_curr_arr[9] = 0;
charge_pump_curr_arr[10] = 0;
charge_pump_curr_arr[11] = 0;
charge_pump_curr_arr[12] = 0;
charge_pump_curr_arr[13] = 0;
charge_pump_curr_arr[14] = 0;
charge_pump_curr_arr[15] = 0;
i_vco_max = vco_max;
i_vco_min = vco_min;
if(vco_post_scale == 1)
begin
i_vco_max_no_division = vco_max * 2;
i_vco_min_no_division = vco_min * 2;
end
else
begin
i_vco_max_no_division = vco_max;
i_vco_min_no_division = vco_min;
end
if (m == 0)
begin
i_clk9_counter = "c9";
i_clk8_counter = "c8";
i_clk7_counter = "c7";
i_clk6_counter = "c6";
i_clk5_counter = "c5" ;
i_clk4_counter = "c4" ;
i_clk3_counter = "c3" ;
i_clk2_counter = "c2" ;
i_clk1_counter = "c1" ;
i_clk0_counter = "c0" ;
end
else begin
i_clk9_counter = alpha_tolower(clk9_counter);
i_clk8_counter = alpha_tolower(clk8_counter);
i_clk7_counter = alpha_tolower(clk7_counter);
i_clk6_counter = alpha_tolower(clk6_counter);
i_clk5_counter = alpha_tolower(clk5_counter);
i_clk4_counter = alpha_tolower(clk4_counter);
i_clk3_counter = alpha_tolower(clk3_counter);
i_clk2_counter = alpha_tolower(clk2_counter);
i_clk1_counter = alpha_tolower(clk1_counter);
i_clk0_counter = alpha_tolower(clk0_counter);
end
if (m == 0)
begin
// set the limit of the divide_by value that can be returned by
// the following function.
max_d_value = 500;
// scale down the multiply_by and divide_by values provided by the design
// before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(clk6_multiply_by, clk6_divide_by,
max_d_value, i_clk6_mult_by, i_clk6_div_by);
find_simple_integer_fraction(clk7_multiply_by, clk7_divide_by,
max_d_value, i_clk7_mult_by, i_clk7_div_by);
find_simple_integer_fraction(clk8_multiply_by, clk8_divide_by,
max_d_value, i_clk8_mult_by, i_clk8_div_by);
find_simple_integer_fraction(clk9_multiply_by, clk9_divide_by,
max_d_value, i_clk9_mult_by, i_clk9_div_by);
// convert user parameters to advanced
if (l_vco_frequency_control == "manual_phase")
begin
find_m_and_n_4_manual_phase(inclk0_freq, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,i_clk4_mult_by,
i_clk5_mult_by,
i_clk6_mult_by, i_clk7_mult_by,
i_clk8_mult_by, i_clk9_mult_by,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,i_clk4_div_by,
i_clk5_div_by,
i_clk6_div_by, i_clk7_div_by,
i_clk8_div_by, i_clk9_div_by,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,clk4_counter,
clk5_counter,
clk6_counter, clk7_counter,
clk8_counter, clk9_counter,
i_m, i_n);
end
else if (((l_pll_type == "fast") || (l_pll_type == "lvds") || (l_pll_type == "left_right")) && (vco_multiply_by != 0) && (vco_divide_by != 0))
begin
i_n = vco_divide_by;
i_m = vco_multiply_by;
end
else begin
i_n = 1;
if (((l_pll_type == "fast") || (l_pll_type == "left_right")) && (l_compensate_clock == "lvdsclk"))
i_m = i_clk0_mult_by;
else
i_m = lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,i_clk4_mult_by,
i_clk5_mult_by,
i_clk6_mult_by, i_clk7_mult_by,
i_clk8_mult_by, i_clk9_mult_by,
inclk0_freq);
end
i_c_high[0] = counter_high (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high[1] = counter_high (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high[2] = counter_high (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high[3] = counter_high (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high[4] = counter_high (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high[5] = counter_high (output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_high[6] = counter_high (output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_high[7] = counter_high (output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_high[8] = counter_high (output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_high[9] = counter_high (output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_c_low[0] = counter_low (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low[1] = counter_low (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low[2] = counter_low (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low[3] = counter_low (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low[4] = counter_low (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low[5] = counter_low (output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low[6] = counter_low (output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_low[7] = counter_low (output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_low[8] = counter_low (output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_low[9] = counter_low (output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
if (l_pll_type == "flvds")
begin
// Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier = clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier);
i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier);
i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier);
i_clk3_phase_shift = 0;
i_clk4_phase_shift = 0;
end
else
begin
i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num);
i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num);
i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num);
i_clk3_phase_shift = get_int_phase_shift(clk3_phase_shift, clk3_phase_shift_num);
i_clk4_phase_shift = get_int_phase_shift(clk4_phase_shift, clk4_phase_shift_num);
end
max_neg_abs = maxnegabs ( i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
i_clk3_phase_shift,
i_clk4_phase_shift,
str2int(clk5_phase_shift),
str2int(clk6_phase_shift),
str2int(clk7_phase_shift),
str2int(clk8_phase_shift),
str2int(clk9_phase_shift)
);
i_c_initial[0] = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[1] = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[2] = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[3] = counter_initial(get_phase_degree(ph_adjust(i_clk3_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[4] = counter_initial(get_phase_degree(ph_adjust(i_clk4_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[5] = counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[6] = counter_initial(get_phase_degree(ph_adjust(str2int(clk6_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[7] = counter_initial(get_phase_degree(ph_adjust(str2int(clk7_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[8] = counter_initial(get_phase_degree(ph_adjust(str2int(clk8_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[9] = counter_initial(get_phase_degree(ph_adjust(str2int(clk9_phase_shift), max_neg_abs)), i_m, i_n);
i_c_mode[0] = counter_mode(clk0_duty_cycle,output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode[1] = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode[2] = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode[3] = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode[4] = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode[5] = counter_mode(clk5_duty_cycle,output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_c_mode[6] = counter_mode(clk6_duty_cycle,output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n));
i_c_mode[7] = counter_mode(clk7_duty_cycle,output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n));
i_c_mode[8] = counter_mode(clk8_duty_cycle,output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n));
i_c_mode[9] = counter_mode(clk9_duty_cycle,output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n));
i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n);
i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n);
i_c_ph[0] = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[1] = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[2] = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[3] = counter_ph(get_phase_degree(ph_adjust(i_clk3_phase_shift,max_neg_abs)), i_m, i_n);
i_c_ph[4] = counter_ph(get_phase_degree(ph_adjust(i_clk4_phase_shift,max_neg_abs)), i_m, i_n);
i_c_ph[5] = counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[6] = counter_ph(get_phase_degree(ph_adjust(str2int(clk6_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[7] = counter_ph(get_phase_degree(ph_adjust(str2int(clk7_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[8] = counter_ph(get_phase_degree(ph_adjust(str2int(clk8_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[9] = counter_ph(get_phase_degree(ph_adjust(str2int(clk9_phase_shift),max_neg_abs)), i_m, i_n);
end
else
begin // m != 0
i_n = n;
i_m = m;
i_c_high[0] = c0_high;
i_c_high[1] = c1_high;
i_c_high[2] = c2_high;
i_c_high[3] = c3_high;
i_c_high[4] = c4_high;
i_c_high[5] = c5_high;
i_c_high[6] = c6_high;
i_c_high[7] = c7_high;
i_c_high[8] = c8_high;
i_c_high[9] = c9_high;
i_c_low[0] = c0_low;
i_c_low[1] = c1_low;
i_c_low[2] = c2_low;
i_c_low[3] = c3_low;
i_c_low[4] = c4_low;
i_c_low[5] = c5_low;
i_c_low[6] = c6_low;
i_c_low[7] = c7_low;
i_c_low[8] = c8_low;
i_c_low[9] = c9_low;
i_c_initial[0] = c0_initial;
i_c_initial[1] = c1_initial;
i_c_initial[2] = c2_initial;
i_c_initial[3] = c3_initial;
i_c_initial[4] = c4_initial;
i_c_initial[5] = c5_initial;
i_c_initial[6] = c6_initial;
i_c_initial[7] = c7_initial;
i_c_initial[8] = c8_initial;
i_c_initial[9] = c9_initial;
i_c_mode[0] = translate_string(alpha_tolower(c0_mode));
i_c_mode[1] = translate_string(alpha_tolower(c1_mode));
i_c_mode[2] = translate_string(alpha_tolower(c2_mode));
i_c_mode[3] = translate_string(alpha_tolower(c3_mode));
i_c_mode[4] = translate_string(alpha_tolower(c4_mode));
i_c_mode[5] = translate_string(alpha_tolower(c5_mode));
i_c_mode[6] = translate_string(alpha_tolower(c6_mode));
i_c_mode[7] = translate_string(alpha_tolower(c7_mode));
i_c_mode[8] = translate_string(alpha_tolower(c8_mode));
i_c_mode[9] = translate_string(alpha_tolower(c9_mode));
i_c_ph[0] = c0_ph;
i_c_ph[1] = c1_ph;
i_c_ph[2] = c2_ph;
i_c_ph[3] = c3_ph;
i_c_ph[4] = c4_ph;
i_c_ph[5] = c5_ph;
i_c_ph[6] = c6_ph;
i_c_ph[7] = c7_ph;
i_c_ph[8] = c8_ph;
i_c_ph[9] = c9_ph;
i_m_ph = m_ph; // default
i_m_initial = m_initial;
end // user to advanced conversion
switch_clock = 1'b0;
refclk_period = inclk0_freq * i_n;
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
fbclk_period = 0;
high_time = 0;
low_time = 0;
schedule_vco = 0;
vco_out[7:0] = 8'b0;
vco_tap[7:0] = 8'b0;
fbclk_last_value = 0;
offset = 0;
temp_offset = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
refclk_time = 0;
first_schedule = 1;
sched_time = 0;
vco_val = 0;
gate_count = 0;
gate_out = 0;
initial_delay = 0;
fbk_phase = 0;
for (i = 0; i <= 7; i = i + 1)
begin
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
fbk_delay = 0;
inclk_n = 0;
inclk_es = 0;
inclk_man = 0;
cycle_to_adjust = 0;
m_delay = 0;
total_pull_back = 0;
pull_back_M = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
inclk_out_of_range = 0;
scandone_tmp = 1'b0;
schedule_vco_last_value = 0;
if ((l_pll_type == "fast") || (l_pll_type == "lvds") || (l_pll_type == "left_right"))
begin
scan_chain_length = FAST_SCAN_CHAIN;
num_output_cntrs = 7;
end
else
begin
scan_chain_length = GPP_SCAN_CHAIN;
num_output_cntrs = 10;
end
phasestep_high_count = 0;
update_phase = 0;
// set initial values for counter parameters
m_initial_val = i_m_initial;
m_val[0] = i_m;
n_val[0] = i_n;
m_ph_val = i_m_ph;
m_ph_val_orig = i_m_ph;
m_ph_val_tmp = i_m_ph;
m_val_tmp[0] = i_m;
if (m_val[0] == 1)
m_mode_val[0] = "bypass";
else m_mode_val[0] = "";
if (m_val[1] == 1)
m_mode_val[1] = "bypass";
if (n_val[0] == 1)
n_mode_val[0] = "bypass";
if (n_val[1] == 1)
n_mode_val[1] = "bypass";
for (i = 0; i < 10; i=i+1)
begin
c_high_val[i] = i_c_high[i];
c_low_val[i] = i_c_low[i];
c_initial_val[i] = i_c_initial[i];
c_mode_val[i] = i_c_mode[i];
c_ph_val[i] = i_c_ph[i];
c_high_val_tmp[i] = i_c_high[i];
c_hval[i] = i_c_high[i];
c_low_val_tmp[i] = i_c_low[i];
c_lval[i] = i_c_low[i];
if (c_mode_val[i] == "bypass")
begin
if (l_pll_type == "fast" || l_pll_type == "lvds" || l_pll_type == "left_right")
begin
c_high_val[i] = 5'b10000;
c_low_val[i] = 5'b10000;
c_high_val_tmp[i] = 5'b10000;
c_low_val_tmp[i] = 5'b10000;
end
else begin
c_high_val[i] = 9'b100000000;
c_low_val[i] = 9'b100000000;
c_high_val_tmp[i] = 9'b100000000;
c_low_val_tmp[i] = 9'b100000000;
end
end
c_mode_val_tmp[i] = i_c_mode[i];
c_ph_val_tmp[i] = i_c_ph[i];
c_ph_val_orig[i] = i_c_ph[i];
c_high_val_hold[i] = i_c_high[i];
c_low_val_hold[i] = i_c_low[i];
c_mode_val_hold[i] = i_c_mode[i];
end
lfc_val = loop_filter_c;
lfr_val = loop_filter_r;
cp_curr_val = charge_pump_current;
vco_cur = vco_post_scale;
i = 0;
j = 0;
inclk_last_value = 0;
// initialize clkswitch variables
clk0_is_bad = 0;
clk1_is_bad = 0;
inclk0_last_value = 0;
inclk1_last_value = 0;
other_clock_value = 0;
other_clock_last_value = 0;
primary_clk_is_bad = 0;
current_clk_is_bad = 0;
external_switch = 0;
current_clock = 0;
current_clock_man = 0;
active_clock = 0; // primary_clk is always inclk0
if (l_pll_type == "fast" || (l_pll_type == "left_right"))
l_switch_over_type = "manual";
if (l_switch_over_type == "manual" && clkswitch === 1'b1)
begin
current_clock_man = 1;
active_clock = 1;
end
got_curr_clk_falling_edge_after_clkswitch = 0;
clk0_count = 0;
clk1_count = 0;
// initialize reconfiguration variables
// quiet_time
quiet_time = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
c_high_val[1]+c_low_val[1], c_mode_val[1],
c_high_val[2]+c_low_val[2], c_mode_val[2],
c_high_val[3]+c_low_val[3], c_mode_val[3],
c_high_val[4]+c_low_val[4], c_mode_val[4],
c_high_val[5]+c_low_val[5], c_mode_val[5],
c_high_val[6]+c_low_val[6], c_mode_val[6],
c_high_val[7]+c_low_val[7], c_mode_val[7],
c_high_val[8]+c_low_val[8], c_mode_val[8],
c_high_val[9]+c_low_val[9], c_mode_val[9],
refclk_period, m_val[0]);
reconfig_err = 0;
error = 0;
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
c5_rising_edge_transfer_done = 0;
c6_rising_edge_transfer_done = 0;
c7_rising_edge_transfer_done = 0;
c8_rising_edge_transfer_done = 0;
c9_rising_edge_transfer_done = 0;
got_first_scanclk = 0;
got_first_gated_scanclk = 0;
gated_scanclk = 1;
scanread_setup_violation = 0;
index = 0;
vco_over = 1'b0;
vco_under = 1'b0;
// Initialize the scan chain
// LF unused : bit 1
scan_data[-1:0] = 2'b00;
// LF Capacitance : bits 1,2 : all values are legal
scan_data[1:2] = loop_filter_c_bits;
// LF Resistance : bits 3-7
scan_data[3:7] = loop_filter_r_bits;
// VCO post scale
if(vco_post_scale == 1)
begin
scan_data[8] = 1'b1;
vco_val_old_bit_setting = 1'b1;
end
else
begin
scan_data[8] = 1'b0;
vco_val_old_bit_setting = 1'b0;
end
scan_data[9:13] = 5'b00000;
// CP
// Bit 8 : CRBYPASS
// Bit 9-13 : unused
// Bits 14-16 : all values are legal
scan_data[14:16] = charge_pump_current_bits;
// store as old values
cp_curr_old_bit_setting = charge_pump_current_bits;
lfc_val_old_bit_setting = loop_filter_c_bits;
lfr_val_old_bit_setting = loop_filter_r_bits;
// C counters (start bit 53) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
for (i = 0; i < num_output_cntrs; i = i + 1)
begin
// 1. Mode - bypass
if (c_mode_val[i] == "bypass")
begin
scan_data[53 + i*18 + 0] = 1'b1;
if (c_mode_val[i] == " odd")
scan_data[53 + i*18 + 9] = 1'b1;
else
scan_data[53 + i*18 + 9] = 1'b0;
end
else
begin
scan_data[53 + i*18 + 0] = 1'b0;
// 3. Mode - odd/even
if (c_mode_val[i] == " odd")
scan_data[53 + i*18 + 9] = 1'b1;
else
scan_data[53 + i*18 + 9] = 1'b0;
end
// 2. Hi
c_val = c_high_val[i];
for (j = 1; j <= 8; j = j + 1)
scan_data[53 + i*18 + j] = c_val[8 - j];
// 4. Low
c_val = c_low_val[i];
for (j = 10; j <= 17; j = j + 1)
scan_data[53 + i*18 + j] = c_val[17 - j];
end
// M counter
// 1. Mode - bypass (bit 17)
if (m_mode_val[0] == "bypass")
scan_data[17] = 1'b1;
else
scan_data[17] = 1'b0; // set bypass bit to 0
// 2. High (bit 18-25)
// 3. Mode - odd/even (bit 26)
if (m_val[0] % 2 == 0)
begin
// M is an even no. : set M high = low,
// set odd/even bit to 0
scan_data[18:25] = m_val[0]/2;
scan_data[26] = 1'b0;
end
else
begin
// M is odd : M high = low + 1
scan_data[18:25] = m_val[0]/2 + 1;
scan_data[26] = 1'b1;
end
// 4. Low (bit 27-34)
scan_data[27:34] = m_val[0]/2;
// N counter
// 1. Mode - bypass (bit 35)
if (n_mode_val[0] == "bypass")
scan_data[35] = 1'b1;
else
scan_data[35] = 1'b0; // set bypass bit to 0
// 2. High (bit 36-43)
// 3. Mode - odd/even (bit 44)
if (n_val[0] % 2 == 0)
begin
// N is an even no. : set N high = low,
// set odd/even bit to 0
scan_data[36:43] = n_val[0]/2;
scan_data[44] = 1'b0;
end
else
begin // N is odd : N high = N low + 1
scan_data[36:43] = n_val[0]/2 + 1;
scan_data[44] = 1'b1;
end
// 4. Low (bit 45-52)
scan_data[45:52] = n_val[0]/2;
l_index = 1;
stop_vco = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
locked_tmp = 0;
pll_is_locked = 0;
no_warn = 1'b0;
pfd_locked = 1'b0;
cycles_pfd_high = 0;
cycles_pfd_low = 0;
// check if pll is in test mode
if (m_test_source != -1 || c0_test_source != -1 || c1_test_source != -1 || c2_test_source != -1 || c3_test_source != -1 || c4_test_source != -1 || c5_test_source != -1 || c6_test_source != -1 || c7_test_source != -1 || c8_test_source != -1 || c9_test_source != -1)
pll_in_test_mode = 1'b1;
else
pll_in_test_mode = 1'b0;
pll_is_in_reset = 0;
pll_has_just_been_reconfigured = 0;
if (l_pll_type == "fast" || l_pll_type == "lvds" || l_pll_type == "left_right")
is_fast_pll = 1;
else is_fast_pll = 0;
if (c1_use_casc_in == "on")
ic1_use_casc_in = 1;
else
ic1_use_casc_in = 0;
if (c2_use_casc_in == "on")
ic2_use_casc_in = 1;
else
ic2_use_casc_in = 0;
if (c3_use_casc_in == "on")
ic3_use_casc_in = 1;
else
ic3_use_casc_in = 0;
if (c4_use_casc_in == "on")
ic4_use_casc_in = 1;
else
ic4_use_casc_in = 0;
if (c5_use_casc_in == "on")
ic5_use_casc_in = 1;
else
ic5_use_casc_in = 0;
if (c6_use_casc_in == "on")
ic6_use_casc_in = 1;
else
ic6_use_casc_in = 0;
if (c7_use_casc_in == "on")
ic7_use_casc_in = 1;
else
ic7_use_casc_in = 0;
if (c8_use_casc_in == "on")
ic8_use_casc_in = 1;
else
ic8_use_casc_in = 0;
if (c9_use_casc_in == "on")
ic9_use_casc_in = 1;
else
ic9_use_casc_in = 0;
tap0_is_active = 1;
// To display clock mapping
case( i_clk0_counter)
"c0" : clk_num[0] = " clk0";
"c1" : clk_num[0] = " clk1";
"c2" : clk_num[0] = " clk2";
"c3" : clk_num[0] = " clk3";
"c4" : clk_num[0] = " clk4";
"c5" : clk_num[0] = " clk5";
"c6" : clk_num[0] = " clk6";
"c7" : clk_num[0] = " clk7";
"c8" : clk_num[0] = " clk8";
"c9" : clk_num[0] = " clk9";
default:clk_num[0] = "unused";
endcase
case( i_clk1_counter)
"c0" : clk_num[1] = " clk0";
"c1" : clk_num[1] = " clk1";
"c2" : clk_num[1] = " clk2";
"c3" : clk_num[1] = " clk3";
"c4" : clk_num[1] = " clk4";
"c5" : clk_num[1] = " clk5";
"c6" : clk_num[1] = " clk6";
"c7" : clk_num[1] = " clk7";
"c8" : clk_num[1] = " clk8";
"c9" : clk_num[1] = " clk9";
default:clk_num[1] = "unused";
endcase
case( i_clk2_counter)
"c0" : clk_num[2] = " clk0";
"c1" : clk_num[2] = " clk1";
"c2" : clk_num[2] = " clk2";
"c3" : clk_num[2] = " clk3";
"c4" : clk_num[2] = " clk4";
"c5" : clk_num[2] = " clk5";
"c6" : clk_num[2] = " clk6";
"c7" : clk_num[2] = " clk7";
"c8" : clk_num[2] = " clk8";
"c9" : clk_num[2] = " clk9";
default:clk_num[2] = "unused";
endcase
case( i_clk3_counter)
"c0" : clk_num[3] = " clk0";
"c1" : clk_num[3] = " clk1";
"c2" : clk_num[3] = " clk2";
"c3" : clk_num[3] = " clk3";
"c4" : clk_num[3] = " clk4";
"c5" : clk_num[3] = " clk5";
"c6" : clk_num[3] = " clk6";
"c7" : clk_num[3] = " clk7";
"c8" : clk_num[3] = " clk8";
"c9" : clk_num[3] = " clk9";
default:clk_num[3] = "unused";
endcase
case( i_clk4_counter)
"c0" : clk_num[4] = " clk0";
"c1" : clk_num[4] = " clk1";
"c2" : clk_num[4] = " clk2";
"c3" : clk_num[4] = " clk3";
"c4" : clk_num[4] = " clk4";
"c5" : clk_num[4] = " clk5";
"c6" : clk_num[4] = " clk6";
"c7" : clk_num[4] = " clk7";
"c8" : clk_num[4] = " clk8";
"c9" : clk_num[4] = " clk9";
default:clk_num[4] = "unused";
endcase
case( i_clk5_counter)
"c0" : clk_num[5] = " clk0";
"c1" : clk_num[5] = " clk1";
"c2" : clk_num[5] = " clk2";
"c3" : clk_num[5] = " clk3";
"c4" : clk_num[5] = " clk4";
"c5" : clk_num[5] = " clk5";
"c6" : clk_num[5] = " clk6";
"c7" : clk_num[5] = " clk7";
"c8" : clk_num[5] = " clk8";
"c9" : clk_num[5] = " clk9";
default:clk_num[5] = "unused";
endcase
case( i_clk6_counter)
"c0" : clk_num[6] = " clk0";
"c1" : clk_num[6] = " clk1";
"c2" : clk_num[6] = " clk2";
"c3" : clk_num[6] = " clk3";
"c4" : clk_num[6] = " clk4";
"c5" : clk_num[6] = " clk5";
"c6" : clk_num[6] = " clk6";
"c7" : clk_num[6] = " clk7";
"c8" : clk_num[6] = " clk8";
"c9" : clk_num[6] = " clk9";
default:clk_num[6] = "unused";
endcase
case( i_clk7_counter)
"c0" : clk_num[7] = " clk0";
"c1" : clk_num[7] = " clk1";
"c2" : clk_num[7] = " clk2";
"c3" : clk_num[7] = " clk3";
"c4" : clk_num[7] = " clk4";
"c5" : clk_num[7] = " clk5";
"c6" : clk_num[7] = " clk6";
"c7" : clk_num[7] = " clk7";
"c8" : clk_num[7] = " clk8";
"c9" : clk_num[7] = " clk9";
default:clk_num[7] = "unused";
endcase
case( i_clk8_counter)
"c0" : clk_num[8] = " clk0";
"c1" : clk_num[8] = " clk1";
"c2" : clk_num[8] = " clk2";
"c3" : clk_num[8] = " clk3";
"c4" : clk_num[8] = " clk4";
"c5" : clk_num[8] = " clk5";
"c6" : clk_num[8] = " clk6";
"c7" : clk_num[8] = " clk7";
"c8" : clk_num[8] = " clk8";
"c9" : clk_num[8] = " clk9";
default:clk_num[8] = "unused";
endcase
case( i_clk9_counter)
"c0" : clk_num[9] = " clk0";
"c1" : clk_num[9] = " clk1";
"c2" : clk_num[9] = " clk2";
"c3" : clk_num[9] = " clk3";
"c4" : clk_num[9] = " clk4";
"c5" : clk_num[9] = " clk5";
"c6" : clk_num[9] = " clk6";
"c7" : clk_num[9] = " clk7";
"c8" : clk_num[9] = " clk8";
"c9" : clk_num[9] = " clk9";
default:clk_num[9] = "unused";
endcase
end
// Clock Switchover
always @(clkswitch)
begin
if (clkswitch === 1'b1 && l_switch_over_type == "auto")
external_switch = 1;
else if (l_switch_over_type == "manual")
begin
if(clkswitch === 1'b1)
switch_clock = 1'b1;
else
switch_clock = 1'b0;
end
end
always @(posedge inclk[0])
begin
// Determine the inclk0 frequency
if (first_inclk0_edge_detect == 1'b0)
begin
first_inclk0_edge_detect = 1'b1;
end
else
begin
last_inclk0_period = inclk0_period;
inclk0_period = $realtime - last_inclk0_edge;
end
last_inclk0_edge = $realtime;
end
always @(posedge inclk[1])
begin
// Determine the inclk1 frequency
if (first_inclk1_edge_detect == 1'b0)
begin
first_inclk1_edge_detect = 1'b1;
end
else
begin
last_inclk1_period = inclk1_period;
inclk1_period = $realtime - last_inclk1_edge;
end
last_inclk1_edge = $realtime;
end
always @(inclk[0] or inclk[1])
begin
if(switch_clock == 1'b1)
begin
if(current_clock_man == 0)
begin
current_clock_man = 1;
active_clock = 1;
end
else
begin
current_clock_man = 0;
active_clock = 0;
end
switch_clock = 1'b0;
end
if (current_clock_man == 0)
inclk_man = inclk[0];
else
inclk_man = inclk[1];
// save the inclk event value
if (inclk[0] !== inclk0_last_value)
begin
if (current_clock != 0)
other_clock_value = inclk[0];
end
if (inclk[1] !== inclk1_last_value)
begin
if (current_clock != 1)
other_clock_value = inclk[1];
end
// check if either input clk is bad
if (inclk[0] === 1'b1 && inclk[0] !== inclk0_last_value)
begin
clk0_count = clk0_count + 1;
clk0_is_bad = 0;
clk1_count = 0;
if (clk0_count > 2)
begin
// no event on other clk for 2 cycles
clk1_is_bad = 1;
if (current_clock == 1)
current_clk_is_bad = 1;
end
end
if (inclk[1] === 1'b1 && inclk[1] !== inclk1_last_value)
begin
clk1_count = clk1_count + 1;
clk1_is_bad = 0;
clk0_count = 0;
if (clk1_count > 2)
begin
// no event on other clk for 2 cycles
clk0_is_bad = 1;
if (current_clock == 0)
current_clk_is_bad = 1;
end
end
// check if the bad clk is the primary clock, which is always clk0
if (clk0_is_bad == 1'b1)
primary_clk_is_bad = 1;
else
primary_clk_is_bad = 0;
// actual switching -- manual switch
if ((inclk[0] !== inclk0_last_value) && current_clock == 0)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk[0] === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_es = inclk[0];
end
end
else inclk_es = inclk[0];
end
if ((inclk[1] !== inclk1_last_value) && current_clock == 1)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk[1] === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_es = inclk[1];
end
end
else inclk_es = inclk[1];
end
// actual switching -- automatic switch
if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && l_enable_switch_over_counter == "on" && primary_clk_is_bad)
switch_over_count = switch_over_count + 1;
if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value))
begin
if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (primary_clk_is_bad && (clkswitch !== 1'b1) && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter))))
begin
if (areset === 1'b0)
begin
if ((inclk0_period > inclk1_period) && (inclk1_period != 0))
diff_percent_period = (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
else if (inclk0_period != 0)
diff_percent_period = (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
if((diff_percent_period > 20)&& (l_switch_over_type == "auto"))
begin
$display ("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality.");
$display ("Time: %0t Instance: %m", $time);
end
end
got_curr_clk_falling_edge_after_clkswitch = 0;
if (current_clock == 0)
current_clock = 1;
else
current_clock = 0;
active_clock = ~active_clock;
switch_over_count = 0;
external_switch = 0;
current_clk_is_bad = 0;
end
else if(l_switch_over_type == "auto")
begin
if(current_clock == 0 && clk0_is_bad == 1'b1 && clk1_is_bad == 1'b0 )
begin
current_clock = 1;
active_clock = ~active_clock;
end
if(current_clock == 1 && clk1_is_bad == 1'b1 && clk0_is_bad == 1'b0 )
begin
current_clock = 0;
active_clock = ~active_clock;
end
end
end
if(l_switch_over_type == "manual")
inclk_n = inclk_man;
else
inclk_n = inclk_es;
inclk0_last_value = inclk[0];
inclk1_last_value = inclk[1];
other_clock_last_value = other_clock_value;
end
and (clkbad[0], clk0_is_bad, 1'b1);
and (clkbad[1], clk1_is_bad, 1'b1);
and (activeclock, active_clock, 1'b1);
assign inclk_m = (m_test_source == 0) ? fbclk : (m_test_source == 1) ? refclk : inclk_m_from_vco;
arriaiigz_m_cntr m1 (.clk(inclk_m),
.reset(areset || stop_vco),
.cout(fbclk),
.initial_value(m_initial_val),
.modulus(m_val[0]),
.time_delay(m_delay));
arriaiigz_n_cntr n1 (.clk(inclk_n),
.reset(areset),
.cout(refclk),
.modulus(n_val[0]));
// Update clock on /o counters from corresponding VCO tap
assign inclk_m_from_vco = vco_tap[m_ph_val];
assign inclk_c0_from_vco = vco_tap[c_ph_val[0]];
assign inclk_c1_from_vco = vco_tap[c_ph_val[1]];
assign inclk_c2_from_vco = vco_tap[c_ph_val[2]];
assign inclk_c3_from_vco = vco_tap[c_ph_val[3]];
assign inclk_c4_from_vco = vco_tap[c_ph_val[4]];
assign inclk_c5_from_vco = vco_tap[c_ph_val[5]];
assign inclk_c6_from_vco = vco_tap[c_ph_val[6]];
assign inclk_c7_from_vco = vco_tap[c_ph_val[7]];
assign inclk_c8_from_vco = vco_tap[c_ph_val[8]];
assign inclk_c9_from_vco = vco_tap[c_ph_val[9]];
always @(vco_out)
begin
// check which VCO TAP has event
for (x = 0; x <= 7; x = x + 1)
begin
if (vco_out[x] !== vco_out_last_value[x])
begin
// TAP 'X' has event
if ((x == 0) && (!pll_is_in_reset) && (stop_vco !== 1'b1))
begin
if (vco_out[0] == 1'b1)
tap0_is_active = 1;
if (tap0_is_active == 1'b1)
vco_tap[0] <= vco_out[0];
end
else if (tap0_is_active == 1'b1)
vco_tap[x] <= vco_out[x];
if (stop_vco === 1'b1)
vco_out[x] <= 1'b0;
end
end
vco_out_last_value = vco_out;
end
always @(vco_tap)
begin
// Update phase taps for C/M counters on negative edge of VCO clock output
if (update_phase == 1'b1)
begin
for (x = 0; x <= 7; x = x + 1)
begin
if ((vco_tap[x] === 1'b0) && (vco_tap[x] !== vco_tap_last_value[x]))
begin
for (y = 0; y < 10; y = y + 1)
begin
if (c_ph_val_tmp[y] == x)
c_ph_val[y] = c_ph_val_tmp[y];
end
if (m_ph_val_tmp == x)
m_ph_val = m_ph_val_tmp;
end
end
update_phase <= #(0.5*scanclk_period) 1'b0;
end
// On reset, set all C/M counter phase taps to POF programmed values
if (areset === 1'b1)
begin
m_ph_val = m_ph_val_orig;
m_ph_val_tmp = m_ph_val_orig;
for (i=0; i<= 9; i=i+1)
begin
c_ph_val[i] = c_ph_val_orig[i];
c_ph_val_tmp[i] = c_ph_val_orig[i];
end
end
vco_tap_last_value = vco_tap;
end
assign inclk_c0 = (c0_test_source == 0) ? fbclk : (c0_test_source == 1) ? refclk : inclk_c0_from_vco;
arriaiigz_scale_cntr c0 (.clk(inclk_c0),
.reset(areset || stop_vco),
.cout(c0_clk),
.high(c_high_val[0]),
.low(c_low_val[0]),
.initial_value(c_initial_val[0]),
.mode(c_mode_val[0]),
.ph_tap(c_ph_val[0]));
// Update /o counters mode and duty cycle immediately after configupdate is asserted
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[0] <= c_high_val_tmp[0];
c_mode_val[0] <= c_mode_val_tmp[0];
c0_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c0_rising_edge_transfer_done)
begin
c_low_val[0] <= c_low_val_tmp[0];
end
end
assign inclk_c1 = (c1_test_source == 0) ? fbclk : (c1_test_source == 1) ? refclk : (ic1_use_casc_in == 1) ? c0_clk : inclk_c1_from_vco;
arriaiigz_scale_cntr c1 (.clk(inclk_c1),
.reset(areset || stop_vco),
.cout(c1_clk),
.high(c_high_val[1]),
.low(c_low_val[1]),
.initial_value(c_initial_val[1]),
.mode(c_mode_val[1]),
.ph_tap(c_ph_val[1]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[1] <= c_high_val_tmp[1];
c_mode_val[1] <= c_mode_val_tmp[1];
c1_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c1_rising_edge_transfer_done)
begin
c_low_val[1] <= c_low_val_tmp[1];
end
end
assign inclk_c2 = (c2_test_source == 0) ? fbclk : (c2_test_source == 1) ? refclk :(ic2_use_casc_in == 1) ? c1_clk : inclk_c2_from_vco;
arriaiigz_scale_cntr c2 (.clk(inclk_c2),
.reset(areset || stop_vco),
.cout(c2_clk),
.high(c_high_val[2]),
.low(c_low_val[2]),
.initial_value(c_initial_val[2]),
.mode(c_mode_val[2]),
.ph_tap(c_ph_val[2]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[2] <= c_high_val_tmp[2];
c_mode_val[2] <= c_mode_val_tmp[2];
c2_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c2_rising_edge_transfer_done)
begin
c_low_val[2] <= c_low_val_tmp[2];
end
end
assign inclk_c3 = (c3_test_source == 0) ? fbclk : (c3_test_source == 1) ? refclk : (ic3_use_casc_in == 1) ? c2_clk : inclk_c3_from_vco;
arriaiigz_scale_cntr c3 (.clk(inclk_c3),
.reset(areset || stop_vco),
.cout(c3_clk),
.high(c_high_val[3]),
.low(c_low_val[3]),
.initial_value(c_initial_val[3]),
.mode(c_mode_val[3]),
.ph_tap(c_ph_val[3]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[3] <= c_high_val_tmp[3];
c_mode_val[3] <= c_mode_val_tmp[3];
c3_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c3_rising_edge_transfer_done)
begin
c_low_val[3] <= c_low_val_tmp[3];
end
end
assign inclk_c4 = ((c4_test_source == 0) ? fbclk : (c4_test_source == 1) ? refclk : (ic4_use_casc_in == 1) ? c3_clk : inclk_c4_from_vco);
arriaiigz_scale_cntr c4 (.clk(inclk_c4),
.reset(areset || stop_vco),
.cout(c4_clk),
.high(c_high_val[4]),
.low(c_low_val[4]),
.initial_value(c_initial_val[4]),
.mode(c_mode_val[4]),
.ph_tap(c_ph_val[4]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[4] <= c_high_val_tmp[4];
c_mode_val[4] <= c_mode_val_tmp[4];
c4_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c4_rising_edge_transfer_done)
begin
c_low_val[4] <= c_low_val_tmp[4];
end
end
assign inclk_c5 = (c5_test_source == 0) ? fbclk : (c5_test_source == 1) ? refclk : (ic5_use_casc_in == 1) ? c4_clk : inclk_c5_from_vco;
arriaiigz_scale_cntr c5 (.clk(inclk_c5),
.reset(areset || stop_vco),
.cout(c5_clk),
.high(c_high_val[5]),
.low(c_low_val[5]),
.initial_value(c_initial_val[5]),
.mode(c_mode_val[5]),
.ph_tap(c_ph_val[5]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[5] <= c_high_val_tmp[5];
c_mode_val[5] <= c_mode_val_tmp[5];
c5_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c5_rising_edge_transfer_done)
begin
c_low_val[5] <= c_low_val_tmp[5];
end
end
assign inclk_c6 = ((c6_test_source == 0) ? fbclk : (c6_test_source == 1) ? refclk : (ic6_use_casc_in == 1) ? c5_clk : inclk_c6_from_vco);
arriaiigz_scale_cntr c6 (.clk(inclk_c6),
.reset(areset || stop_vco),
.cout(c6_clk),
.high(c_high_val[6]),
.low(c_low_val[6]),
.initial_value(c_initial_val[6]),
.mode(c_mode_val[6]),
.ph_tap(c_ph_val[6]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[6] <= c_high_val_tmp[6];
c_mode_val[6] <= c_mode_val_tmp[6];
c6_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c6_rising_edge_transfer_done)
begin
c_low_val[6] <= c_low_val_tmp[6];
end
end
assign inclk_c7 = ((c7_test_source == 0) ? fbclk : (c7_test_source == 1) ? refclk : (ic7_use_casc_in == 1) ? c6_clk : inclk_c7_from_vco);
arriaiigz_scale_cntr c7 (.clk(inclk_c7),
.reset(areset || stop_vco),
.cout(c7_clk),
.high(c_high_val[7]),
.low(c_low_val[7]),
.initial_value(c_initial_val[7]),
.mode(c_mode_val[7]),
.ph_tap(c_ph_val[7]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[7] <= c_high_val_tmp[7];
c_mode_val[7] <= c_mode_val_tmp[7];
c7_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c7_rising_edge_transfer_done)
begin
c_low_val[7] <= c_low_val_tmp[7];
end
end
assign inclk_c8 = ((c8_test_source == 0) ? fbclk : (c8_test_source == 1) ? refclk : (ic8_use_casc_in == 1) ? c7_clk : inclk_c8_from_vco);
arriaiigz_scale_cntr c8 (.clk(inclk_c8),
.reset(areset || stop_vco),
.cout(c8_clk),
.high(c_high_val[8]),
.low(c_low_val[8]),
.initial_value(c_initial_val[8]),
.mode(c_mode_val[8]),
.ph_tap(c_ph_val[8]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[8] <= c_high_val_tmp[8];
c_mode_val[8] <= c_mode_val_tmp[8];
c8_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c8_rising_edge_transfer_done)
begin
c_low_val[8] <= c_low_val_tmp[8];
end
end
assign inclk_c9 = ((c9_test_source == 0) ? fbclk : (c9_test_source == 1) ? refclk : (ic9_use_casc_in == 1) ? c8_clk : inclk_c9_from_vco);
arriaiigz_scale_cntr c9 (.clk(inclk_c9),
.reset(areset || stop_vco),
.cout(c9_clk),
.high(c_high_val[9]),
.low(c_low_val[9]),
.initial_value(c_initial_val[9]),
.mode(c_mode_val[9]),
.ph_tap(c_ph_val[9]));
always @(posedge scanclk)
begin
if (update_conf_latches_reg == 1'b1)
begin
c_high_val[9] <= c_high_val_tmp[9];
c_mode_val[9] <= c_mode_val_tmp[9];
c9_rising_edge_transfer_done = 1;
end
end
always @(negedge scanclk)
begin
if (c9_rising_edge_transfer_done)
begin
c_low_val[9] <= c_low_val_tmp[9];
end
end
assign locked = (test_bypass_lock_detect == "on") ? pfd_locked : locked_tmp;
// Register scanclk enable
always @(negedge scanclk)
scanclkena_reg <= scanclkena;
// Negative edge flip-flop in front of scan-chain
always @(negedge scanclk)
begin
if (scanclkena_reg)
begin
scandata_in <= scandata;
end
end
// Scan chain
always @(posedge scanclk)
begin
if (got_first_scanclk === 1'b0)
got_first_scanclk = 1'b1;
else
scanclk_period = $time - scanclk_last_rising_edge;
if (scanclkena_reg)
begin
for (j = scan_chain_length-2; j >= 0; j = j - 1)
scan_data[j] = scan_data[j - 1];
scan_data[-1] <= scandata_in;
end
scanclk_last_rising_edge = $realtime;
end
// Scan output
assign scandataout_tmp = (l_pll_type == "fast" || l_pll_type == "lvds" || l_pll_type == "left_right") ? scan_data[FAST_SCAN_CHAIN-2] : scan_data[GPP_SCAN_CHAIN-2];
// Negative edge flip-flop in rear of scan-chain
always @(negedge scanclk)
begin
if (scanclkena_reg)
begin
scandata_out <= scandataout_tmp;
end
end
// Scan complete
always @(negedge scandone_tmp)
begin
if (got_first_scanclk === 1'b1)
begin
if (reconfig_err == 1'b0)
begin
$display("NOTE : PLL Reprogramming completed with the following values (Values in parantheses are original values) : ");
$display ("Time: %0t Instance: %m", $time);
$display(" N modulus = %0d (%0d) ", n_val[0], n_val_old[0]);
$display(" M modulus = %0d (%0d) ", m_val[0], m_val_old[0]);
for (i = 0; i < num_output_cntrs; i=i+1)
begin
$display(" %s : C%0d high = %0d (%0d), C%0d low = %0d (%0d), C%0d mode = %s (%s)", clk_num[i],i, c_high_val[i], c_high_val_old[i], i, c_low_val_tmp[i], c_low_val_old[i], i, c_mode_val[i], c_mode_val_old[i]);
end
// display Charge pump and loop filter values
if (pll_reconfig_display_full_setting == 1'b1)
begin
$display (" Charge Pump Current (uA) = %0d (%0d) ", cp_curr_val, cp_curr_old);
$display (" Loop Filter Capacitor (pF) = %0d (%0d) ", lfc_val, lfc_old);
$display (" Loop Filter Resistor (Kohm) = %s (%s) ", lfr_val, lfr_old);
$display (" VCO_Post_Scale = %0d (%0d) ", vco_cur, vco_old);
end
else
begin
$display (" Charge Pump Current = %0d (%0d) ", cp_curr_bit_setting, cp_curr_old_bit_setting);
$display (" Loop Filter Capacitor = %0d (%0d) ", lfc_val_bit_setting, lfc_val_old_bit_setting);
$display (" Loop Filter Resistor = %0d (%0d) ", lfr_val_bit_setting, lfr_val_old_bit_setting);
$display (" VCO_Post_Scale = %b (%b) ", vco_val_bit_setting, vco_val_old_bit_setting);
end
cp_curr_old_bit_setting = cp_curr_bit_setting;
lfc_val_old_bit_setting = lfc_val_bit_setting;
lfr_val_old_bit_setting = lfr_val_bit_setting;
vco_val_old_bit_setting = vco_val_bit_setting;
end
else begin
$display("Warning : Errors were encountered during PLL reprogramming. Please refer to error/warning messages above.");
$display ("Time: %0t Instance: %m", $time);
end
end
end
// ************ PLL Phase Reconfiguration ************* //
// Latch updown,counter values at pos edge of scan clock
always @(posedge scanclk)
begin
if (phasestep_reg == 1'b1)
begin
if (phasestep_high_count == 1)
begin
phasecounterselect_reg <= phasecounterselect;
phaseupdown_reg <= phaseupdown;
// start reconfiguration
if (phasecounterselect < 4'b1100) // no counters selected
begin
if (phasecounterselect == 0) // all output counters selected
begin
for (i = 0; i < num_output_cntrs; i = i + 1)
c_ph_val_tmp[i] = (phaseupdown == 1'b1) ?
(c_ph_val_tmp[i] + 1) % num_phase_taps :
(c_ph_val_tmp[i] == 0) ? num_phase_taps - 1 : (c_ph_val_tmp[i] - 1) % num_phase_taps ;
end
else if (phasecounterselect == 1) // select M counter
begin
m_ph_val_tmp = (phaseupdown == 1'b1) ?
(m_ph_val + 1) % num_phase_taps :
(m_ph_val == 0) ? num_phase_taps - 1 : (m_ph_val - 1) % num_phase_taps ;
end
else // select C counters
begin
select_counter = phasecounterselect - 2;
c_ph_val_tmp[select_counter] = (phaseupdown == 1'b1) ?
(c_ph_val_tmp[select_counter] + 1) % num_phase_taps :
(c_ph_val_tmp[select_counter] == 0) ? num_phase_taps - 1 : (c_ph_val_tmp[select_counter] - 1) % num_phase_taps ;
end
update_phase <= 1'b1;
end
end
phasestep_high_count = phasestep_high_count + 1;
end
end
// Latch phase enable (same as phasestep) on neg edge of scan clock
always @(negedge scanclk)
begin
phasestep_reg <= phasestep;
end
always @(posedge phasestep)
begin
if (update_phase == 1'b0) phasestep_high_count = 0; // phase adjustments must be 1 cycle apart
// if not, next phasestep cycle is skipped
end
// ************ PLL Full Reconfiguration ************* //
assign update_conf_latches = configupdate;
// reset counter transfer flags
always @(negedge scandone_tmp)
begin
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
c5_rising_edge_transfer_done = 0;
c6_rising_edge_transfer_done = 0;
c7_rising_edge_transfer_done = 0;
c8_rising_edge_transfer_done = 0;
c9_rising_edge_transfer_done = 0;
update_conf_latches_reg <= 1'b0;
end
always @(posedge update_conf_latches)
begin
initiate_reconfig <= 1'b1;
end
always @(posedge areset)
begin
if (scandone_tmp == 1'b1) scandone_tmp = 1'b0;
end
always @(posedge scanclk)
begin
if (initiate_reconfig == 1'b1)
begin
initiate_reconfig <= 1'b0;
$display ("NOTE : PLL Reprogramming initiated ....");
$display ("Time: %0t Instance: %m", $time);
scandone_tmp <= #(scanclk_period) 1'b1;
update_conf_latches_reg <= update_conf_latches;
error = 0;
reconfig_err = 0;
scanread_setup_violation = 0;
// save old values
cp_curr_old = cp_curr_val;
lfc_old = lfc_val;
lfr_old = lfr_val;
vco_old = vco_cur;
// save old values of bit settings
cp_curr_bit_setting = scan_data[14:16];
lfc_val_bit_setting = scan_data[1:2];
lfr_val_bit_setting = scan_data[3:7];
vco_val_bit_setting = scan_data[8];
// LF unused : bit 1
// LF Capacitance : bits 1,2 : all values are legal
if ((l_pll_type == "fast") || (l_pll_type == "lvds") || (l_pll_type == "left_right"))
lfc_val = fpll_loop_filter_c_arr[scan_data[1:2]];
else
lfc_val = loop_filter_c_arr[scan_data[1:2]];
// LF Resistance : bits 3-7
// valid values - 00000,00100,10000,10100,11000,11011,11100,11110
if (((scan_data[3:7] == 5'b00000) || (scan_data[3:7] == 5'b00100)) ||
((scan_data[3:7] == 5'b10000) || (scan_data[3:7] == 5'b10100)) ||
((scan_data[3:7] == 5'b11000) || (scan_data[3:7] == 5'b11011)) ||
((scan_data[3:7] == 5'b11100) || (scan_data[3:7] == 5'b11110))
)
begin
lfr_val = (scan_data[3:7] == 5'b00000) ? "20" :
(scan_data[3:7] == 5'b00100) ? "16" :
(scan_data[3:7] == 5'b10000) ? "12" :
(scan_data[3:7] == 5'b10100) ? "8" :
(scan_data[3:7] == 5'b11000) ? "6" :
(scan_data[3:7] == 5'b11011) ? "4" :
(scan_data[3:7] == 5'b11100) ? "2" : "1";
end
//VCO post scale value
if (scan_data[8] === 1'b1) // vco_post_scale = 1
begin
i_vco_max = i_vco_max_no_division/2;
i_vco_min = i_vco_min_no_division/2;
vco_cur = 1;
end
else
begin
i_vco_max = vco_max;
i_vco_min = vco_min;
vco_cur = 2;
end
// CP
// Bit 8 : CRBYPASS
// Bit 9-13 : unused
// Bits 14-16 : all values are legal
cp_curr_val = scan_data[14:16];
// save old values for display info.
for (i=0; i<=1; i=i+1)
begin
m_val_old[i] = m_val[i];
n_val_old[i] = n_val[i];
m_mode_val_old[i] = m_mode_val[i];
n_mode_val_old[i] = n_mode_val[i];
end
for (i=0; i< num_output_cntrs; i=i+1)
begin
c_high_val_old[i] = c_high_val[i];
c_low_val_old[i] = c_low_val[i];
c_mode_val_old[i] = c_mode_val[i];
end
// M counter
// 1. Mode - bypass (bit 17)
if (scan_data[17] == 1'b1)
m_mode_val[0] = "bypass";
// 3. Mode - odd/even (bit 26)
else if (scan_data[26] == 1'b1)
m_mode_val[0] = " odd";
else
m_mode_val[0] = " even";
// 2. High (bit 18-25)
m_hi = scan_data[18:25];
// 4. Low (bit 27-34)
m_lo = scan_data[27:34];
// N counter
// 1. Mode - bypass (bit 35)
if (scan_data[35] == 1'b1)
n_mode_val[0] = "bypass";
// 3. Mode - odd/even (bit 44)
else if (scan_data[44] == 1'b1)
n_mode_val[0] = " odd";
else
n_mode_val[0] = " even";
// 2. High (bit 36-43)
n_hi = scan_data[36:43];
// 4. Low (bit 45-52)
n_lo = scan_data[45:52];
//Update the current M and N counter values if the counters are NOT bypassed
if (m_mode_val[0] != "bypass")
m_val[0] = m_hi + m_lo;
if (n_mode_val[0] != "bypass")
n_val[0] = n_hi + n_lo;
// C counters (start bit 53) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
for (i = 0; i < num_output_cntrs; i = i + 1)
begin
// 1. Mode - bypass
if (scan_data[53 + i*18 + 0] == 1'b1)
c_mode_val_tmp[i] = "bypass";
// 3. Mode - odd/even
else if (scan_data[53 + i*18 + 9] == 1'b1)
c_mode_val_tmp[i] = " odd";
else
c_mode_val_tmp[i] = " even";
// 2. Hi
for (j = 1; j <= 8; j = j + 1)
c_val[8-j] = scan_data[53 + i*18 + j];
c_hval[i] = c_val[7:0];
if (c_hval[i] !== 32'h00000000)
c_high_val_tmp[i] = c_hval[i];
else
c_high_val_tmp[i] = 9'b100000000;
// 4. Low
for (j = 10; j <= 17; j = j + 1)
c_val[17 - j] = scan_data[53 + i*18 + j];
c_lval[i] = c_val[7:0];
if (c_lval[i] !== 32'h00000000)
c_low_val_tmp[i] = c_lval[i];
else
c_low_val_tmp[i] = 9'b100000000;
end
// Legality Checks
if (m_mode_val[0] != "bypass")
begin
if ((m_hi !== m_lo) && (m_mode_val[0] != " odd"))
begin
reconfig_err = 1;
$display ("Warning : The M counter of the %s Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work", family_name);
$display ("Time: %0t Instance: %m", $time);
end
else if (m_hi !== 8'b00000000)
begin
// counter value
m_val_tmp[0] = m_hi + m_lo;
end
else
m_val_tmp[0] = 9'b100000000;
end
else
m_val_tmp[0] = 8'b00000001;
if (n_mode_val[0] != "bypass")
begin
if ((n_hi !== n_lo) && (n_mode_val[0] != " odd"))
begin
reconfig_err = 1;
$display ("Warning : The N counter of the %s Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work", family_name);
$display ("Time: %0t Instance: %m", $time);
end
else if (n_hi !== 8'b00000000)
begin
// counter value
n_val[0] = n_hi + n_lo;
end
else
n_val[0] = 9'b100000000;
end
else
n_val[0] = 8'b00000001;
// TODO : Give warnings/errors in the following cases?
// 1. Illegal counter values (error)
// 2. Change of mode (warning)
// 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
end
end
// Self reset on loss of lock
assign reset_self = (l_self_reset_on_loss_lock == "on") ? ~pll_is_locked : 1'b0;
always @(posedge reset_self)
begin
$display (" Note : %s PLL self reset due to loss of lock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
// Phase shift on /o counters
always @(schedule_vco or areset)
begin
sched_time = 0;
for (i = 0; i <= 7; i=i+1)
last_phase_shift[i] = phase_shift[i];
cycle_to_adjust = 0;
l_index = 1;
m_times_vco_period = new_m_times_vco_period;
// give appropriate messages
// if areset was asserted
if (areset === 1'b1 && areset_last_value !== areset)
begin
$display (" Note : %s PLL was reset", family_name);
$display ("Time: %0t Instance: %m", $time);
// reset lock parameters
pll_is_locked = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
tap0_is_active = 0;
phase_adjust_was_scheduled = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
// illegal value on areset
if (areset === 1'bx && (areset_last_value === 1'b0 || areset_last_value === 1'b1))
begin
$display("Warning : Illegal value 'X' detected on ARESET input");
$display ("Time: %0t Instance: %m", $time);
end
if ((areset == 1'b1))
begin
pll_is_in_reset = 1;
got_first_refclk = 0;
got_second_refclk = 0;
end
if ((schedule_vco !== schedule_vco_last_value) && (areset == 1'b1 || stop_vco == 1'b1))
begin
// drop VCO taps to 0
for (i = 0; i <= 7; i=i+1)
begin
for (j = 0; j <= last_phase_shift[i] + 1; j=j+1)
vco_out[i] <= #(j) 1'b0;
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
// reset lock parameters
pll_is_locked = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
fbclk_period = 0;
first_schedule = 1;
vco_val = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
// reset all counter phase tap values to POF programmed values
m_ph_val = m_ph_val_orig;
for (i=0; i<= 5; i=i+1)
c_ph_val[i] = c_ph_val_orig[i];
end else if (areset === 1'b0 && stop_vco === 1'b0)
begin
// else note areset deassert time
// note it as refclk_time to prevent false triggering
// of stop_vco after areset
if (areset === 1'b0 && areset_last_value === 1'b1 && pll_is_in_reset === 1'b1)
begin
refclk_time = $time;
locked_tmp = 1'b0;
end
pll_is_in_reset = 0;
// calculate loop_xplier : this will be different from m_val in ext. fbk mode
loop_xplier = m_val[0];
loop_initial = i_m_initial - 1;
loop_ph = m_ph_val;
// convert initial value to delay
initial_delay = (loop_initial * m_times_vco_period)/loop_xplier;
// convert loop ph_tap to delay
rem = m_times_vco_period % loop_xplier;
vco_per = m_times_vco_period/loop_xplier;
if (rem != 0)
vco_per = vco_per + 1;
fbk_phase = (loop_ph * vco_per)/8;
pull_back_M = initial_delay + fbk_phase;
total_pull_back = pull_back_M;
if (l_simulation_type == "timing")
total_pull_back = total_pull_back + pll_compensation_delay;
while (total_pull_back > refclk_period)
total_pull_back = total_pull_back - refclk_period;
if (total_pull_back > 0)
offset = refclk_period - total_pull_back;
else
offset = 0;
fbk_delay = total_pull_back - fbk_phase;
if (fbk_delay < 0)
begin
offset = offset - fbk_phase;
fbk_delay = total_pull_back;
end
// assign m_delay
m_delay = fbk_delay;
for (i = 1; i <= loop_xplier; i=i+1)
begin
// adjust cycles
tmp_vco_per = m_times_vco_period/loop_xplier;
if (rem != 0 && l_index <= rem)
begin
tmp_rem = (loop_xplier * l_index) % rem;
cycle_to_adjust = (loop_xplier * l_index) / rem;
if (tmp_rem != 0)
cycle_to_adjust = cycle_to_adjust + 1;
end
if (cycle_to_adjust == i)
begin
tmp_vco_per = tmp_vco_per + 1;
l_index = l_index + 1;
end
// calculate high and low periods
high_time = tmp_vco_per/2;
if (tmp_vco_per % 2 != 0)
high_time = high_time + 1;
low_time = tmp_vco_per - high_time;
// schedule the rising and falling egdes
for (j=0; j<=1; j=j+1)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
// schedule taps with appropriate phase shifts
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
if (first_schedule)
vco_out[k] <= #(sched_time + phase_shift[k]) vco_val;
else
vco_out[k] <= #(sched_time + last_phase_shift[k]) vco_val;
end
end
end
if (first_schedule)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
vco_out[k] <= #(sched_time+phase_shift[k]) vco_val;
end
first_schedule = 0;
end
schedule_vco <= #(sched_time) ~schedule_vco;
if (vco_period_was_phase_adjusted)
begin
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 1;
tmp_vco_per = m_times_vco_period/loop_xplier;
for (k = 0; k <= 7; k=k+1)
phase_shift[k] = (k*tmp_vco_per)/8;
end
end
areset_last_value = areset;
schedule_vco_last_value = schedule_vco;
end
assign pfdena_wire = (pfdena === 1'b0) ? 1'b0 : 1'b1;
// PFD enable
always @(pfdena_wire)
begin
if (pfdena_wire === 1'b0)
begin
if (pll_is_locked)
locked_tmp = 1'bx;
pll_is_locked = 0;
cycles_to_lock = 0;
$display (" Note : PFDENA was deasserted");
$display ("Time: %0t Instance: %m", $time);
end
else if (pfdena_wire === 1'b1 && pfdena_last_value === 1'b0)
begin
// PFD was disabled, now enabled again
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = $time;
end
pfdena_last_value = pfdena_wire;
end
always @(negedge refclk or negedge fbclk)
begin
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
// Bypass lock detect
always @(posedge refclk)
begin
if (test_bypass_lock_detect == "on")
begin
if (pfdena_wire === 1'b1)
begin
cycles_pfd_low = 0;
if (pfd_locked == 1'b0)
begin
if (cycles_pfd_high == lock_high)
begin
$display ("Note : %s PLL locked in test mode on PFD enable assert", family_name);
$display ("Time: %0t Instance: %m", $time);
pfd_locked <= 1'b1;
end
cycles_pfd_high = cycles_pfd_high + 1;
end
end
if (pfdena_wire === 1'b0)
begin
cycles_pfd_high = 0;
if (pfd_locked == 1'b1)
begin
if (cycles_pfd_low == lock_low)
begin
$display ("Note : %s PLL lost lock in test mode on PFD enable deassert", family_name);
$display ("Time: %0t Instance: %m", $time);
pfd_locked <= 1'b0;
end
cycles_pfd_low = cycles_pfd_low + 1;
end
end
end
end
always @(posedge scandone_tmp or posedge locked_tmp)
begin
if(scandone_tmp == 1)
pll_has_just_been_reconfigured <= 1;
else
pll_has_just_been_reconfigured <= 0;
end
// VCO Frequency Range check
always @(posedge refclk or posedge fbclk)
begin
if (refclk == 1'b1 && refclk_last_value !== refclk && areset === 1'b0)
begin
if (! got_first_refclk)
begin
got_first_refclk = 1;
end else
begin
got_second_refclk = 1;
refclk_period = $time - refclk_time;
// check if incoming freq. will cause VCO range to be
// exceeded
if ((i_vco_max != 0 && i_vco_min != 0) && (pfdena_wire === 1'b1) &&
((refclk_period/loop_xplier > i_vco_max) ||
(refclk_period/loop_xplier < i_vco_min)) )
begin
if (pll_is_locked == 1'b1)
begin
if (refclk_period/loop_xplier > i_vco_max)
begin
$display ("Warning : Input clock freq. is over VCO range. %s PLL may lose lock", family_name);
vco_over = 1'b1;
end
if (refclk_period/loop_xplier < i_vco_min)
begin
$display ("Warning : Input clock freq. is under VCO range. %s PLL may lose lock", family_name);
vco_under = 1'b1;
end
$display ("Time: %0t Instance: %m", $time);
if (inclk_out_of_range === 1'b1)
begin
// unlock
pll_is_locked = 0;
locked_tmp = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
else begin
if (no_warn == 1'b0)
begin
if (refclk_period/loop_xplier > i_vco_max)
begin
$display ("Warning : Input clock freq. is over VCO range. %s PLL may lose lock", family_name);
vco_over = 1'b1;
end
if (refclk_period/loop_xplier < i_vco_min)
begin
$display ("Warning : Input clock freq. is under VCO range. %s PLL may lose lock", family_name);
vco_under = 1'b1;
end
$display ("Time: %0t Instance: %m", $time);
no_warn = 1'b1;
end
end
inclk_out_of_range = 1;
end
else begin
vco_over = 1'b0;
vco_under = 1'b0;
inclk_out_of_range = 0;
no_warn = 1'b0;
end
end
if (stop_vco == 1'b1)
begin
stop_vco = 0;
schedule_vco = ~schedule_vco;
end
refclk_time = $time;
end
// Update M counter value on feedback clock edge
if (fbclk == 1'b1 && fbclk_last_value !== fbclk)
begin
if (update_conf_latches === 1'b1)
begin
m_val[0] <= m_val_tmp[0];
m_val[1] <= m_val_tmp[1];
end
if (!got_first_fbclk)
begin
got_first_fbclk = 1;
first_fbclk_time = $time;
end
else
fbclk_period = $time - fbclk_time;
// need refclk_period here, so initialized to proper value above
if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_wire === 1'b1 && pll_is_locked === 1'b1) ||
( ($time - refclk_time > 5 * refclk_period) && (pfdena_wire === 1'b1) && (pll_has_just_been_reconfigured == 0) ) ||
( ($time - refclk_time > 50 * refclk_period) && (pfdena_wire === 1'b1) && (pll_has_just_been_reconfigured == 1) ) )
begin
stop_vco = 1;
// reset
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
if (pll_is_locked == 1'b1)
begin
pll_is_locked = 0;
locked_tmp = 0;
$display ("Note : %s PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame.", family_name);
if ((i_vco_max == 0) && (i_vco_min == 0))
$display ("Note : Please run timing simulation to check whether the input clock is operating within the supported VCO range or not.");
$display ("Time: %0t Instance: %m", $time);
end
cycles_to_lock = 0;
cycles_to_unlock = 0;
first_schedule = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
fbclk_time = $time;
end
// Core lock functionality
if (got_second_refclk && pfdena_wire === 1'b1 && (!inclk_out_of_range))
begin
// now we know actual incoming period
if (abs(fbclk_time - refclk_time) <= lock_window || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window))
begin
// considered in phase
if (cycles_to_lock == real_lock_high)
begin
if (pll_is_locked === 1'b0)
begin
$display (" Note : %s PLL locked to incoming clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_is_locked = 1;
locked_tmp = 1;
cycles_to_unlock = 0;
end
// increment lock counter only if the second part of the above
// time check is not true
if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window))
begin
cycles_to_lock = cycles_to_lock + 1;
end
// adjust m_times_vco_period
new_m_times_vco_period = refclk_period;
end else
begin
// if locked, begin unlock
if (pll_is_locked)
begin
cycles_to_unlock = cycles_to_unlock + 1;
if (cycles_to_unlock == lock_low)
begin
pll_is_locked = 0;
locked_tmp = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
end
end
if (abs(refclk_period - fbclk_period) <= 2)
begin
// frequency is still good
if ($time == fbclk_time && (!phase_adjust_was_scheduled))
begin
if (abs(fbclk_time - refclk_time) > refclk_period/2)
begin
new_m_times_vco_period = abs(m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)));
vco_period_was_phase_adjusted = 1;
end else
begin
new_m_times_vco_period = abs(m_times_vco_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted = 1;
end
end
end else
begin
new_m_times_vco_period = refclk_period;
phase_adjust_was_scheduled = 0;
end
end
end
if (reconfig_err == 1'b1)
begin
locked_tmp = 0;
end
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
assign clk_tmp[0] = i_clk0_counter == "c0" ? c0_clk : i_clk0_counter == "c1" ? c1_clk : i_clk0_counter == "c2" ? c2_clk : i_clk0_counter == "c3" ? c3_clk : i_clk0_counter == "c4" ? c4_clk : i_clk0_counter == "c5" ? c5_clk : i_clk0_counter == "c6" ? c6_clk : i_clk0_counter == "c7" ? c7_clk : i_clk0_counter == "c8" ? c8_clk : i_clk0_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[1] = i_clk1_counter == "c0" ? c0_clk : i_clk1_counter == "c1" ? c1_clk : i_clk1_counter == "c2" ? c2_clk : i_clk1_counter == "c3" ? c3_clk : i_clk1_counter == "c4" ? c4_clk : i_clk1_counter == "c5" ? c5_clk : i_clk1_counter == "c6" ? c6_clk : i_clk1_counter == "c7" ? c7_clk : i_clk1_counter == "c8" ? c8_clk : i_clk1_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[2] = i_clk2_counter == "c0" ? c0_clk : i_clk2_counter == "c1" ? c1_clk : i_clk2_counter == "c2" ? c2_clk : i_clk2_counter == "c3" ? c3_clk : i_clk2_counter == "c4" ? c4_clk : i_clk2_counter == "c5" ? c5_clk : i_clk2_counter == "c6" ? c6_clk : i_clk2_counter == "c7" ? c7_clk : i_clk2_counter == "c8" ? c8_clk : i_clk2_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[3] = i_clk3_counter == "c0" ? c0_clk : i_clk3_counter == "c1" ? c1_clk : i_clk3_counter == "c2" ? c2_clk : i_clk3_counter == "c3" ? c3_clk : i_clk3_counter == "c4" ? c4_clk : i_clk3_counter == "c5" ? c5_clk : i_clk3_counter == "c6" ? c6_clk : i_clk3_counter == "c7" ? c7_clk : i_clk3_counter == "c8" ? c8_clk : i_clk3_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[4] = i_clk4_counter == "c0" ? c0_clk : i_clk4_counter == "c1" ? c1_clk : i_clk4_counter == "c2" ? c2_clk : i_clk4_counter == "c3" ? c3_clk : i_clk4_counter == "c4" ? c4_clk : i_clk4_counter == "c5" ? c5_clk : i_clk4_counter == "c6" ? c6_clk : i_clk4_counter == "c7" ? c7_clk : i_clk4_counter == "c8" ? c8_clk : i_clk4_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[5] = i_clk5_counter == "c0" ? c0_clk : i_clk5_counter == "c1" ? c1_clk : i_clk5_counter == "c2" ? c2_clk : i_clk5_counter == "c3" ? c3_clk : i_clk5_counter == "c4" ? c4_clk : i_clk5_counter == "c5" ? c5_clk : i_clk5_counter == "c6" ? c6_clk : i_clk5_counter == "c7" ? c7_clk : i_clk5_counter == "c8" ? c8_clk : i_clk5_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[6] = i_clk6_counter == "c0" ? c0_clk : i_clk6_counter == "c1" ? c1_clk : i_clk6_counter == "c2" ? c2_clk : i_clk6_counter == "c3" ? c3_clk : i_clk6_counter == "c4" ? c4_clk : i_clk6_counter == "c5" ? c5_clk : i_clk6_counter == "c6" ? c6_clk : i_clk6_counter == "c7" ? c7_clk : i_clk6_counter == "c8" ? c8_clk : i_clk6_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[7] = i_clk7_counter == "c0" ? c0_clk : i_clk7_counter == "c1" ? c1_clk : i_clk7_counter == "c2" ? c2_clk : i_clk7_counter == "c3" ? c3_clk : i_clk7_counter == "c4" ? c4_clk : i_clk7_counter == "c5" ? c5_clk : i_clk7_counter == "c6" ? c6_clk : i_clk7_counter == "c7" ? c7_clk : i_clk7_counter == "c8" ? c8_clk : i_clk7_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[8] = i_clk8_counter == "c0" ? c0_clk : i_clk8_counter == "c1" ? c1_clk : i_clk8_counter == "c2" ? c2_clk : i_clk8_counter == "c3" ? c3_clk : i_clk8_counter == "c4" ? c4_clk : i_clk8_counter == "c5" ? c5_clk : i_clk8_counter == "c6" ? c6_clk : i_clk8_counter == "c7" ? c7_clk : i_clk8_counter == "c8" ? c8_clk : i_clk8_counter == "c9" ? c9_clk : 1'b0;
assign clk_tmp[9] = i_clk9_counter == "c0" ? c0_clk : i_clk9_counter == "c1" ? c1_clk : i_clk9_counter == "c2" ? c2_clk : i_clk9_counter == "c3" ? c3_clk : i_clk9_counter == "c4" ? c4_clk : i_clk9_counter == "c5" ? c5_clk : i_clk9_counter == "c6" ? c6_clk : i_clk9_counter == "c7" ? c7_clk : i_clk9_counter == "c8" ? c8_clk : i_clk9_counter == "c9" ? c9_clk : 1'b0;
assign clk_out_pfd[0] = (pfd_locked == 1'b1) ? clk_tmp[0] : 1'bx;
assign clk_out_pfd[1] = (pfd_locked == 1'b1) ? clk_tmp[1] : 1'bx;
assign clk_out_pfd[2] = (pfd_locked == 1'b1) ? clk_tmp[2] : 1'bx;
assign clk_out_pfd[3] = (pfd_locked == 1'b1) ? clk_tmp[3] : 1'bx;
assign clk_out_pfd[4] = (pfd_locked == 1'b1) ? clk_tmp[4] : 1'bx;
assign clk_out_pfd[5] = (pfd_locked == 1'b1) ? clk_tmp[5] : 1'bx;
assign clk_out_pfd[6] = (pfd_locked == 1'b1) ? clk_tmp[6] : 1'bx;
assign clk_out_pfd[7] = (pfd_locked == 1'b1) ? clk_tmp[7] : 1'bx;
assign clk_out_pfd[8] = (pfd_locked == 1'b1) ? clk_tmp[8] : 1'bx;
assign clk_out_pfd[9] = (pfd_locked == 1'b1) ? clk_tmp[9] : 1'bx;
assign clk_out[0] = (test_bypass_lock_detect == "on") ? clk_out_pfd[0] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[0] : 1'bx);
assign clk_out[1] = (test_bypass_lock_detect == "on") ? clk_out_pfd[1] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[1] : 1'bx);
assign clk_out[2] = (test_bypass_lock_detect == "on") ? clk_out_pfd[2] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[2] : 1'bx);
assign clk_out[3] = (test_bypass_lock_detect == "on") ? clk_out_pfd[3] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[3] : 1'bx);
assign clk_out[4] = (test_bypass_lock_detect == "on") ? clk_out_pfd[4] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[4] : 1'bx);
assign clk_out[5] = (test_bypass_lock_detect == "on") ? clk_out_pfd[5] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[5] : 1'bx);
assign clk_out[6] = (test_bypass_lock_detect == "on") ? clk_out_pfd[6] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[6] : 1'bx);
assign clk_out[7] = (test_bypass_lock_detect == "on") ? clk_out_pfd[7] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[7] : 1'bx);
assign clk_out[8] = (test_bypass_lock_detect == "on") ? clk_out_pfd[8] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[8] : 1'bx);
assign clk_out[9] = (test_bypass_lock_detect == "on") ? clk_out_pfd[9] : ((areset === 1'b1 || pll_in_test_mode === 1'b1) || (locked == 1'b1 && !reconfig_err) ? clk_tmp[9] : 1'bx);
// ACCELERATE OUTPUTS
and (clk[0], 1'b1, clk_out[0]);
and (clk[1], 1'b1, clk_out[1]);
and (clk[2], 1'b1, clk_out[2]);
and (clk[3], 1'b1, clk_out[3]);
and (clk[4], 1'b1, clk_out[4]);
and (clk[5], 1'b1, clk_out[5]);
and (clk[6], 1'b1, clk_out[6]);
and (clk[7], 1'b1, clk_out[7]);
and (clk[8], 1'b1, clk_out[8]);
and (clk[9], 1'b1, clk_out[9]);
and (scandataout, 1'b1, scandata_out);
and (scandone, 1'b1, scandone_tmp);
assign fbout = fbclk;
assign vcooverrange = (vco_range_detector_high_bits == -1) ? 1'bz : vco_over;
assign vcounderrange = (vco_range_detector_low_bits == -1) ? 1'bz :vco_under;
assign phasedone = ~update_phase;
endmodule // arriaiigz_pll
//---------------------------------------------------------------------
//
// Module Name : arriaiigz_asmiblock
//
// Description : ARRIAIIGZ ASMIBLOCK Verilog Simulation model
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_asmiblock
(
dclkin,
scein,
sdoin,
data0in,
oe,
dclkout,
sceout,
sdoout,
data0out
);
input dclkin;
input scein;
input sdoin;
input data0in;
input oe;
output dclkout;
output sceout;
output sdoout;
output data0out;
parameter lpm_type = "arriaiigz_asmiblock";
endmodule // arriaiigz_asmiblock
//---------------------------------------------------------------------
//
// Module Name : arriaiigz_tsdblock
//
// Description : ARRIAIIGZ TSDBLOCK Verilog Simulation model
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_tsdblock
(
offset,
clk,
ce,
clr,
testin,
tsdcalo,
tsdcaldone,
fdbkctrlfromcore,
compouttest,
tsdcompout,
offsetout
);
input [5:0] offset;
input [7:0] testin;
input clk;
input ce;
input clr;
input fdbkctrlfromcore;
input compouttest;
output [7:0] tsdcalo;
output tsdcaldone;
output tsdcompout;
output [5:0] offsetout;
parameter poi_cal_temperature = 85;
parameter clock_divider_enable = "on";
parameter clock_divider_value = 40;
parameter sim_tsdcalo = 0;
parameter user_offset_enable = "off";
parameter lpm_type = "arriaiigz_tsdblock";
endmodule // arriaiigz_tsdblock
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_lvds_rx_fifo_sync_ram
//
// Description :
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module arriaiigz_lvds_rx_fifo_sync_ram (
clk,
datain,
write_reset,
waddr,
raddr,
we,
dataout
);
// INPUT PORTS
input clk;
input write_reset;
input datain;
input [2:0] waddr;
input [2:0] raddr;
input we;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
reg [0:5] ram_d;
reg [0:5] ram_q;
wire [0:5] data_reg;
integer i;
initial
begin
dataout_tmp = 0;
for (i=0; i<= 5; i=i+1)
ram_q[i] <= 1'b0;
end
// Write port
always @(posedge clk or posedge write_reset)
begin
if(write_reset == 1'b1)
begin
for (i=0; i<= 5; i=i+1)
ram_q[i] <= 1'b0;
end
else begin
for (i=0; i<= 5; i=i+1)
ram_q[i] <= ram_d[i];
end
end
always @(we or data_reg or ram_q)
begin
if(we === 1'b1)
begin
ram_d <= data_reg;
end
else begin
ram_d <= ram_q;
end
end
// Read port
assign data_reg[0] = ( waddr == 3'b000 ) ? datain : ram_q[0];
assign data_reg[1] = ( waddr == 3'b001 ) ? datain : ram_q[1];
assign data_reg[2] = ( waddr == 3'b010 ) ? datain : ram_q[2];
assign data_reg[3] = ( waddr == 3'b011 ) ? datain : ram_q[3];
assign data_reg[4] = ( waddr == 3'b100 ) ? datain : ram_q[4];
assign data_reg[5] = ( waddr == 3'b101 ) ? datain : ram_q[5];
always @(ram_q or we or waddr or raddr)
begin
case ( raddr )
3'b000 : dataout_tmp = ram_q[0];
3'b001 : dataout_tmp = ram_q[1];
3'b010 : dataout_tmp = ram_q[2];
3'b011 : dataout_tmp = ram_q[3];
3'b100 : dataout_tmp = ram_q[4];
3'b101 : dataout_tmp = ram_q[5];
default : dataout_tmp = 0;
endcase
end
// set output
assign dataout = dataout_tmp;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_lvds_rx_fifo
//
// Description :
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module arriaiigz_lvds_rx_fifo (
wclk,
rclk,
dparst,
fiforst,
datain,
dataout
);
parameter channel_width = 10;
// INPUT PORTS
input wclk;
input rclk;
input dparst;
input fiforst;
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
wire data_out;
integer i;
reg ram_datain;
wire ram_dataout;
reg [2:0] wrPtr,rdPtr; // writer pointer, read pointer
wire [2:0] rdAddr; // read address
reg ram_we;
reg wclk_last_value, rclk_last_value;
reg write_side_sync_reset;
reg read_side_sync_reset;
specify
(posedge rclk => (dataout +: data_out)) = (0, 0);
(posedge dparst => (dataout +: data_out)) = (0, 0);
endspecify
initial
begin
dataout_tmp = 0;
wrPtr = 2'b00;
rdPtr = 2'b11;
write_side_sync_reset = 1'b0;
read_side_sync_reset = 1'b0;
end
assign rdAddr = rdPtr;
arriaiigz_lvds_rx_fifo_sync_ram s_fifo_ram (
.clk(wclk),
.datain(ram_datain),
.write_reset(write_side_sync_reset),
.waddr(wrPtr),
.raddr(rdAddr), // rdPtr ??
.we(ram_we),
.dataout(ram_dataout)
);
// update pointer and RAM input
always @(wclk or dparst)
begin
if (dparst === 1'b1 || (fiforst === 1'b1 && wclk === 1'b1 && wclk_last_value === 1'b0))
begin
write_side_sync_reset <= 1'b1;
ram_datain <= 1'b0;
wrPtr <= 0;
ram_we <= 'b0;
end
else if (dparst === 1'b0 && (fiforst === 1'b0 && wclk === 1'b1 && wclk_last_value === 1'b0))
begin
write_side_sync_reset <= 1'b0;
end
if (wclk === 1'b1 && wclk_last_value === 1'b0 && write_side_sync_reset === 1'b0 && fiforst === 1'b0 && dparst === 1'b0)
begin
ram_datain <= datain; // input register
ram_we <= 'b1;
wrPtr <= wrPtr + 1;
if (wrPtr == 5)
wrPtr <= 0;
end
wclk_last_value = wclk;
end
always @(rclk or dparst)
begin
if (dparst === 1'b1 || (fiforst === 1'b1 && rclk === 1'b1 && rclk_last_value === 1'b0))
begin
read_side_sync_reset <= 1'b1;
rdPtr <= 3;
dataout_tmp <= 0;
end
else if (dparst === 1'b0 && (fiforst === 1'b0 && rclk === 1'b1 && rclk_last_value === 1'b0))
begin
read_side_sync_reset <= 0;
end
if (rclk === 1'b1 && rclk_last_value === 1'b0 && read_side_sync_reset === 1'b0 && fiforst === 1'b0 && dparst === 1'b0)
begin
rdPtr <= rdPtr + 1;
if (rdPtr == 5)
rdPtr <= 0;
dataout_tmp <= ram_dataout; // output register
end
rclk_last_value = rclk;
end
assign data_out = dataout_tmp;
buf (dataout, data_out);
endmodule // arriaiigz_lvds_rx_fifo
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_lvds_rx_bitslip
//
// Description :
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module arriaiigz_lvds_rx_bitslip (
clk0,
bslipcntl,
bsliprst,
datain,
bslipmax,
dataout
);
parameter channel_width = 10;
parameter bitslip_rollover = 12;
parameter x_on_bitslip = "on";
// INPUT PORTS
input clk0;
input bslipcntl;
input bsliprst;
input datain;
// OUTPUT PORTS
output bslipmax;
output dataout;
// INTERNAL VARIABLES AND NETS
integer slip_count;
integer i, j;
wire dataout_tmp;
wire dataout_wire;
wire bslipmax_wire;
reg clk0_last_value;
reg bsliprst_last_value;
reg bslipcntl_last_value;
reg start_corrupt_bits;
reg [1:0] num_corrupt_bits;
reg [11:0] bitslip_arr;
reg bslipmax_tmp;
reg ix_on_bitslip;
wire bslipcntl_reg;
// TIMING PATHS
specify
(posedge clk0 => (bslipmax +: bslipmax_tmp)) = (0, 0);
(posedge bsliprst => (bslipmax +: bslipmax_tmp)) = (0, 0);
endspecify
initial
begin
slip_count = 0;
bslipmax_tmp = 0;
bitslip_arr = 12'b0;
start_corrupt_bits = 0;
num_corrupt_bits = 0;
if (x_on_bitslip == "on")
ix_on_bitslip = 1;
else
ix_on_bitslip = 0;
end
arriaiigz_lvds_reg bslipcntlreg (
.d(bslipcntl),
.clk(clk0),
.ena(1'b1),
.clrn(!bsliprst),
.prn(1'b1),
.q(bslipcntl_reg)
);
// 4-bit slip counter
always @(bslipcntl_reg or bsliprst)
begin
if (bsliprst === 1'b1)
begin
slip_count <= 0;
bslipmax_tmp <= 1'b0;
if (bsliprst === 1'b1 && bsliprst_last_value === 1'b0)
begin
$display("Note: Bit Slip Circuit was reset. Serial Data stream will have 0 latency");
$display("Time: %0t, Instance: %m", $time);
end
end
else if (bslipcntl_reg === 1'b1 && bslipcntl_last_value === 1'b0)
begin
if (ix_on_bitslip == 1)
start_corrupt_bits <= 1;
num_corrupt_bits <= 0;
if (slip_count == bitslip_rollover)
begin
$display("Note: Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency.");
$display("Time: %0t, Instance: %m", $time);
slip_count <= 0;
bslipmax_tmp <= 1'b0;
end
else
begin
slip_count <= slip_count + 1;
if ((slip_count+1) == bitslip_rollover)
begin
$display("Note: The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip.");
$display("Time: %0t, Instance: %m", $time);
bslipmax_tmp <= 1'b1;
end
end
end
else if (bslipcntl_reg === 1'b0 && bslipcntl_last_value === 1'b1)
begin
start_corrupt_bits <= 0;
num_corrupt_bits <= 0;
end
bslipcntl_last_value <= bslipcntl_reg;
bsliprst_last_value <= bsliprst;
end
// Bit Slip shift register
always @(clk0)
begin
if (clk0 === 1'b1 && clk0_last_value === 1'b0)
begin
bitslip_arr[0] <= datain;
for (i = 0; i < bitslip_rollover; i=i+1)
bitslip_arr[i+1] <= bitslip_arr[i];
if (start_corrupt_bits == 1'b1)
num_corrupt_bits <= num_corrupt_bits + 1;
if (num_corrupt_bits+1 == 3)
start_corrupt_bits <= 0;
end
clk0_last_value <= clk0;
end
arriaiigz_lvds_reg dataoutreg (
.d(bitslip_arr[slip_count]),
.clk(clk0),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.q(dataout_tmp)
);
assign dataout_wire = (start_corrupt_bits == 1'b0) ? dataout_tmp : (num_corrupt_bits < 3) ? 1'bx : dataout_tmp;
assign bslipmax_wire = bslipmax_tmp;
and (dataout, dataout_wire, 1'b1);
and (bslipmax, bslipmax_wire, 1'b1);
endmodule // arriaiigz_lvds_rx_bitslip
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_lvds_rx_deser
//
// Description : Timing simulation model for the arriaiigz LVDS RECEIVER
// Deserializer. This module receives serial data and outputs
// parallel data word of width = channel_width
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module arriaiigz_lvds_rx_deser (
clk,
datain,
devclrn,
devpor,
dataout
);
parameter channel_width = 10;
// INPUT PORTS
input clk;
input datain;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg [channel_width - 1:0] dataout_tmp;
reg clk_last_value;
integer i;
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk or devclrn or devpor)
begin
if (devclrn === 1'b0 || devpor === 1'b0)
begin
dataout_tmp <= 'b0;
end
else if (clk === 1'b1 && clk_last_value === 1'b0)
begin
for (i = (channel_width-1); i > 0; i=i-1)
dataout_tmp[i] <= dataout_tmp[i-1];
dataout_tmp[0] <= datain;
end
clk_last_value <= clk;
end
assign dataout = dataout_tmp;
endmodule //arriaiigz_lvds_rx_deser
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_lvds_rx_parallel_reg
//
// Description : Timing simulation model for the arriaiigz LVDS RECEIVER
// PARALLEL REGISTER. The data width equals max. channel width,
// which is 10.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module arriaiigz_lvds_rx_parallel_reg (
clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 10;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [channel_width - 1:0] dataout_tmp;
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk or devpor or devclrn)
begin
if ((devpor === 1'b0) || (devclrn === 1'b0))
begin
dataout_tmp <= 'b0;
end
else
begin
if ((clk === 1) && (clk_last_value !== clk))
begin
if (enable === 1)
begin
dataout_tmp <= datain;
end
end
end
clk_last_value <= clk;
end //always
assign dataout = dataout_tmp;
endmodule //arriaiigz_lvds_rx_parallel_reg
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_lvds_reg
//
// Description : Simulation model for a simple DFF.
// This is used for registering the enable inputs.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module arriaiigz_lvds_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
(posedge clk => (q +: q_tmp)) = (0, 0);
(negedge clrn => (q +: q_tmp)) = (0, 0);
(negedge prn => (q +: q_tmp)) = (0, 0);
endspecify
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q_tmp = 0;
always @ (posedge clk or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk == 1) & (ena == 1'b1))
q_tmp <= d;
end
assign q_wire = q_tmp;
and (q, q_wire, 1'b1);
endmodule // arriaiigz_lvds_reg
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_pclk_divider
//
// Description : Simulation model for a clock divider
// output clock is divided by value specified
// in the parameter clk_divide_by
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module arriaiigz_pclk_divider (
clkin,
lloaden,
clkout
);
parameter clk_divide_by =1;
input clkin;
output lloaden;
output clkout;
reg clkout_tmp;
reg[4:0] cnt;
reg start;
reg count;
reg lloaden_tmp;
assign clkout = (clk_divide_by == 1) ? clkin :clkout_tmp;
assign lloaden = lloaden_tmp;
initial
begin
clkout_tmp = 1'b0;
cnt = 5'b00000;
start = 1'b0;
count = 1'b0;
lloaden_tmp = 1'b0;
end
always @(clkin)
begin
if (clkin == 1'b1 )
begin
count = 1'b1;
end
if(count == 1'b1)
begin
if(cnt < clk_divide_by)
begin
clkout_tmp = 1'b0;
cnt = cnt + 1'b1;
end
else
begin
if(cnt == 2*clk_divide_by -1)
cnt = 0;
else
begin
clkout_tmp = 1'b1;
cnt = cnt + 1;
end
end
end
end
always@( clkin or cnt )
begin
if( cnt == 2*clk_divide_by -2)
lloaden_tmp = 1'b1;
else if(cnt == 0)
lloaden_tmp = 1'b0;
end
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_select_ini_phase_dpaclk
//
// Description : Simulation model for selecting the initial phase of the dpa clock
//
//
///////////////////////////////////////////////////////////////////////////////
module arriaiigz_select_ini_phase_dpaclk(
clkin,
loaden,
enable,
clkout,
loadenout
);
parameter initial_phase_select = 0;
input clkin;
input enable;
input loaden;
output clkout;
output loadenout;
wire clkout_tmp;
wire loadenout_tmp;
real clk_period, last_clk_period;
real last_clkin_edge;
reg first_clkin_edge_detect;
reg clk0_tmp;
reg clk1_tmp;
reg clk2_tmp;
reg clk3_tmp;
reg clk4_tmp;
reg clk5_tmp;
reg clk6_tmp;
reg clk7_tmp;
reg loaden0_tmp;
reg loaden1_tmp;
reg loaden2_tmp;
reg loaden3_tmp;
reg loaden4_tmp;
reg loaden5_tmp;
reg loaden6_tmp;
reg loaden7_tmp;
assign clkout_tmp = (initial_phase_select == 1) ? clk1_tmp :
(initial_phase_select == 2) ? clk2_tmp :
(initial_phase_select == 3) ? clk3_tmp :
(initial_phase_select == 4) ? clk4_tmp :
(initial_phase_select == 5) ? clk5_tmp :
(initial_phase_select == 6) ? clk6_tmp :
(initial_phase_select == 7) ? clk7_tmp :
clk0_tmp;
assign loadenout_tmp = (initial_phase_select == 1) ? loaden1_tmp :
(initial_phase_select == 2) ? loaden2_tmp :
(initial_phase_select == 3) ? loaden3_tmp :
(initial_phase_select == 4) ? loaden4_tmp :
(initial_phase_select == 5) ? loaden5_tmp :
(initial_phase_select == 6) ? loaden6_tmp :
(initial_phase_select == 7) ? loaden7_tmp :
loaden0_tmp;
assign clkout = (enable == 1'b1) ? clkout_tmp : clkin;
assign loadenout = (enable == 1'b1) ? loadenout_tmp : loaden;
initial
begin
first_clkin_edge_detect = 1'b0;
end
always @(posedge clkin)
begin
// Determine the clock frequency
if (first_clkin_edge_detect == 1'b0)
begin
first_clkin_edge_detect = 1'b1;
end
else
begin
last_clk_period = clk_period;
clk_period = $realtime - last_clkin_edge;
end
last_clkin_edge = $realtime;
end
//assign phase shifted clock and data values
always@(clkin)
begin
clk0_tmp <= clkin;
clk1_tmp <= #(clk_period * 0.125) clkin;
clk2_tmp <= #(clk_period * 0.25) clkin;
clk3_tmp <= #(clk_period * 0.375) clkin;
clk4_tmp <= #(clk_period * 0.5) clkin;
clk5_tmp <= #(clk_period * 0.625) clkin;
clk6_tmp <= #(clk_period * 0.75) clkin;
clk7_tmp <= #(clk_period * 0.875) clkin;
end
always@(loaden)
begin
loaden0_tmp <= loaden;
loaden1_tmp <= #(clk_period * 0.125) loaden;
loaden2_tmp <= #(clk_period * 0.25) loaden;
loaden3_tmp <= #(clk_period * 0.375) loaden;
loaden4_tmp <= #(clk_period * 0.5) loaden;
loaden5_tmp <= #(clk_period * 0.625) loaden;
loaden6_tmp <= #(clk_period * 0.75) loaden;
loaden7_tmp <= #(clk_period * 0.875) loaden;
end
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_dpa_retime_block
//
// Description : Simulation model for generating the retimed clock,data and loaden.
// Each of the signals has 8 different phase shifted versions.
//
//
///////////////////////////////////////////////////////////////////////////////
module arriaiigz_dpa_retime_block(
clkin,
datain,
reset,
clk0,
clk1,
clk2,
clk3,
clk4,
clk5,
clk6,
clk7,
data0,
data1,
data2,
data3,
data4,
data5,
data6,
data7,
lock
);
input clkin;
input datain;
input reset;
output clk0;
output clk1;
output clk2;
output clk3;
output clk4;
output clk5;
output clk6;
output clk7;
output data0;
output data1;
output data2;
output data3;
output data4;
output data5;
output data6;
output data7;
output lock;
real clk_period, last_clk_period;
real last_clkin_edge;
reg first_clkin_edge_detect;
reg clk0_tmp;
reg clk1_tmp;
reg clk2_tmp;
reg clk3_tmp;
reg clk4_tmp;
reg clk5_tmp;
reg clk6_tmp;
reg clk7_tmp;
reg data0_tmp;
reg data1_tmp;
reg data2_tmp;
reg data3_tmp;
reg data4_tmp;
reg data5_tmp;
reg data6_tmp;
reg data7_tmp;
reg lock_tmp;
assign clk0 = (reset == 1'b1) ? 1'b0 : clk0_tmp;
assign clk1 = (reset == 1'b1) ? 1'b0 : clk1_tmp;
assign clk2 = (reset == 1'b1) ? 1'b0 : clk2_tmp;
assign clk3 = (reset == 1'b1) ? 1'b0 : clk3_tmp;
assign clk4 = (reset == 1'b1) ? 1'b0 : clk4_tmp;
assign clk5 = (reset == 1'b1) ? 1'b0 : clk5_tmp;
assign clk6 = (reset == 1'b1) ? 1'b0 : clk6_tmp;
assign clk7 = (reset == 1'b1) ? 1'b0 : clk7_tmp;
assign data0 =(reset == 1'b1) ? 1'b0 : data0_tmp;
assign data1 =(reset == 1'b1) ? 1'b0 : data1_tmp;
assign data2 =(reset == 1'b1) ? 1'b0 : data2_tmp;
assign data3 =(reset == 1'b1) ? 1'b0 : data3_tmp;
assign data4 =(reset == 1'b1) ? 1'b0 : data4_tmp;
assign data5 =(reset == 1'b1) ? 1'b0 : data5_tmp;
assign data6 =(reset == 1'b1) ? 1'b0 : data6_tmp;
assign data7 =(reset == 1'b1) ? 1'b0 : data7_tmp;
assign lock = (reset == 1'b1) ? 1'b0 : lock_tmp;
initial
begin
first_clkin_edge_detect = 1'b0;
lock_tmp = 1'b0;
end
always @(posedge clkin)
begin
// Determine the clock frequency
if (first_clkin_edge_detect == 1'b0)
begin
first_clkin_edge_detect = 1'b1;
end
else
begin
last_clk_period = clk_period;
clk_period = $realtime - last_clkin_edge;
end
last_clkin_edge = $realtime;
//assign dpa lock
if(((clk_period ==last_clk_period) ||(clk_period == last_clk_period-1) || (clk_period ==last_clk_period +1)) && (clk_period != 0) && (last_clk_period != 0))
lock_tmp = 1'b1;
else
lock_tmp = 1'b0;
end
//assign phase shifted clock and data values
always@(clkin)
begin
clk0_tmp <= clkin;
clk1_tmp <= #(clk_period * 0.125) clkin;
clk2_tmp <= #(clk_period * 0.25) clkin;
clk3_tmp <= #(clk_period * 0.375) clkin;
clk4_tmp <= #(clk_period * 0.5) clkin;
clk5_tmp <= #(clk_period * 0.625) clkin;
clk6_tmp <= #(clk_period * 0.75) clkin;
clk7_tmp <= #(clk_period * 0.875) clkin;
end
always@(datain)
begin
data0_tmp <= datain;
data1_tmp <= #(clk_period * 0.125) datain;
data2_tmp <= #(clk_period * 0.25) datain;
data3_tmp <= #(clk_period * 0.375) datain;
data4_tmp <= #(clk_period * 0.5) datain;
data5_tmp <= #(clk_period * 0.625) datain;
data6_tmp <= #(clk_period * 0.75) datain;
data7_tmp <= #(clk_period * 0.875) datain;
end
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_dpa_block
//
// Description : Simulation model for selecting the retimed data, clock and loaden
// depending on the PPM varaiation and direction of shift.
//
///////////////////////////////////////////////////////////////////////////////
module arriaiigz_dpa_block(clkin,
dpareset,
dpahold,
datain,
clkout,
dataout,
dpalock
);
parameter net_ppm_variation = 0;
parameter is_negative_ppm_drift = "off";
parameter enable_soft_cdr_mode= "on";
input clkin ;
input dpareset ;
input dpahold ;
input datain ;
output clkout;
output dataout;
output dpalock;
wire clk0_tmp;
wire clk1_tmp;
wire clk2_tmp;
wire clk3_tmp;
wire clk4_tmp;
wire clk5_tmp;
wire clk6_tmp;
wire clk7_tmp;
wire data0_tmp;
wire data1_tmp;
wire data2_tmp;
wire data3_tmp;
wire data4_tmp;
wire data5_tmp;
wire data6_tmp;
wire data7_tmp;
reg[2:0] select;
reg clkout_tmp ;
reg dataout_tmp;
real counter_reset_value;
integer count_value;
integer i;
initial
begin
if(net_ppm_variation != 0)
begin
counter_reset_value = 1000000/(net_ppm_variation * 8);
count_value = counter_reset_value;
end
i = 0;
select = 3'b000;
clkout_tmp = clkin;
dataout_tmp = datain;
end
assign dataout = (enable_soft_cdr_mode == "on") ? dataout_tmp : datain;
assign clkout = (enable_soft_cdr_mode == "on") ? clkout_tmp : clkin;
arriaiigz_dpa_retime_block data_clock_retime(
.clkin(clkin),
.datain(datain),
.reset(dpareset),
.clk0(clk0_tmp),
.clk1(clk1_tmp),
.clk2(clk2_tmp),
.clk3(clk3_tmp),
.clk4(clk4_tmp),
.clk5(clk5_tmp),
.clk6(clk6_tmp),
.clk7(clk7_tmp),
.data0(data0_tmp),
.data1(data1_tmp),
.data2(data2_tmp),
.data3(data3_tmp),
.data4(data4_tmp),
.data5(data5_tmp),
.data6(data6_tmp),
.data7(data7_tmp),
.lock (dpalock)
);
always@(posedge clkin or posedge dpareset or posedge dpahold)
begin
if(net_ppm_variation == 0)
begin
select = 3'b000;
end
else
begin
if(dpareset == 1'b1)
begin
i = 0;
select = 3'b000;
end
else
begin
if(dpahold == 1'b0)
begin
if(i < count_value)
begin
i = i + 1;
end
else
begin
select = select + 1'b1;
i = 0;
end
end
end
end
end
always@(select or clk0_tmp or clk1_tmp or clk2_tmp or clk3_tmp or
clk4_tmp or clk5_tmp or clk6_tmp or clk7_tmp or
data0_tmp or data1_tmp or data2_tmp or data3_tmp or
data4_tmp or data5_tmp or data6_tmp or data7_tmp )
begin
case(select)
3'b000 :
begin
clkout_tmp = clk0_tmp;
dataout_tmp = data0_tmp;
end
3'b001:
begin
clkout_tmp = (is_negative_ppm_drift == "off") ? clk1_tmp : clk7_tmp ;
dataout_tmp =( is_negative_ppm_drift == "off") ? data1_tmp : data7_tmp ;
end
3'b010:
begin
clkout_tmp = (is_negative_ppm_drift == "off") ? clk2_tmp : clk6_tmp ;
dataout_tmp =( is_negative_ppm_drift == "off") ? data2_tmp : data6_tmp ;
end
3'b011:
begin
clkout_tmp = ( is_negative_ppm_drift == "off") ? clk3_tmp : clk5_tmp ;
dataout_tmp = ( is_negative_ppm_drift == "off") ? data3_tmp : data5_tmp ;
end
3'b100:
begin
clkout_tmp = clk4_tmp ;
dataout_tmp = data4_tmp ;
end
3'b101:
begin
clkout_tmp = ( is_negative_ppm_drift == "off") ? clk5_tmp : clk3_tmp ;
dataout_tmp = ( is_negative_ppm_drift == "off") ? data5_tmp : data3_tmp ;
end
3'b110:
begin
clkout_tmp = ( is_negative_ppm_drift == "off") ? clk6_tmp : clk2_tmp ;
dataout_tmp = ( is_negative_ppm_drift == "off") ? data6_tmp : data2_tmp ;
end
3'b111:
begin
clkout_tmp = ( is_negative_ppm_drift == "off") ? clk7_tmp : clk1_tmp ;
dataout_tmp = ( is_negative_ppm_drift == "off") ? data7_tmp : data1_tmp ;
end
default:
begin
clkout_tmp = clk0_tmp;
dataout_tmp = data0_tmp;
end
endcase
end
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : arriaiigz_LVDS_RECEIVER
//
// Description : Timing simulation model for the arriaiigz LVDS RECEIVER
// atom. This module instantiates the following sub-modules :
// 1) arriaiigz_lvds_rx_fifo
// 2) arriaiigz_lvds_rx_bitslip
// 3) DFFEs for the LOADEN signals
// 4) arriaiigz_lvds_rx_deser
// 5) arriaiigz_lvds_rx_parallel_reg
// 6) arriaiigz_select_ini_phase_dpaclk
// 7)arriaiigz_dpa_block
// 8) arriaiigz_pclk_divider
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module arriaiigz_lvds_receiver (
clk0,
datain,
enable0,
dpareset,
dpahold,
dpaswitch,
fiforeset,
bitslip,
bitslipreset,
serialfbk,
dataout,
dpalock,
bitslipmax,
serialdataout,
postdpaserialdataout,
divfwdclk,
dpaclkout,
devclrn,
devpor
);
parameter data_align_rollover = 2;
parameter enable_dpa = "off";
parameter lose_lock_on_one_change = "off";
parameter reset_fifo_at_first_lock = "on";
parameter align_to_rising_edge_only = "on";
parameter use_serial_feedback_input = "off";
parameter dpa_debug = "off";
parameter x_on_bitslip = "on";
parameter enable_soft_cdr = "off";
parameter dpa_output_clock_phase_shift = 0;
parameter enable_dpa_initial_phase_selection = "off";
parameter dpa_initial_phase_value = 0;
parameter enable_dpa_align_to_rising_edge_only = "off";
parameter net_ppm_variation = 0;
parameter is_negative_ppm_drift = "off";
parameter rx_input_path_delay_engineering_bits = 2;
parameter lpm_type = "arriaiigz_lvds_receiver";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter channel_width = 10;
// SIMULATION_ONLY_PARAMETERS_END
// INPUT PORTS
input clk0;
input datain;
input enable0;
input dpareset;
input dpahold;
input dpaswitch;
input fiforeset;
input bitslip;
input bitslipreset;
input serialfbk;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
output dpalock;
output bitslipmax;
output serialdataout;
output postdpaserialdataout;
output divfwdclk;
output dpaclkout;
tri1 devclrn;
tri1 devpor;
// Input registers
wire in_reg_data;
reg in_reg_data_dly;
wire datain_reg;
wire datain_reg_neg;
wire datain_reg_tmp;
// dpa phase select
wire ini_phase_select_enable;
wire ini_dpa_clk;
wire ini_dpa_load;
// dpa circuit
wire dpareg0_out;
wire dpareg1_out;
wire dpa_clk_shift;
wire dpa_data_shift;
wire dpa_enable0_shift;
wire dpa_clk;
wire dpa_rst;
wire lock_tmp;
// fifo
wire fifo_wclk;
wire fifo_rclk;
wire fifo_datain;
wire fifo_dataout;
wire fifo_reset;
reg reset_fifo;
// bitslip
wire slip_datain;
wire slip_dataout;
wire bitslip_reset;
wire slip_datain_tmp;
wire s_bitslip_clk;
//deserializer
wire [channel_width - 1:0] deser_dataout;
wire postdpaserialdataout_tmp;
wire dpalock_tmp;
wire rxload;
wire loaden;
wire lloaden;
wire divfwdclk_tmp;
wire gnd;
integer i;
// TIMING PATHS
specify
(posedge clk0 => (dpalock +: dpalock_tmp)) = (0, 0);
endspecify
assign gnd = 1'b0;
initial
begin
if (reset_fifo_at_first_lock == "on")
reset_fifo = 1;
else
reset_fifo = 0;
end
// reset_fifo at
always @(lock_tmp)
begin
reset_fifo = !lock_tmp;
end
always @(in_reg_data)
begin
if( dpaswitch == 1'b1)
begin
if(rx_input_path_delay_engineering_bits == 1 )
in_reg_data_dly <= #60 in_reg_data ;
else if ( rx_input_path_delay_engineering_bits == 2)
in_reg_data_dly <= #120 in_reg_data;
else if ( rx_input_path_delay_engineering_bits == 3)
in_reg_data_dly <= #180 in_reg_data;
else
in_reg_data_dly <= in_reg_data;
end
else
in_reg_data_dly <= in_reg_data;
end
// input register in non-DPA mode for sampling incoming data
arriaiigz_lvds_reg in_reg (
.d(in_reg_data_dly),
.clk(clk0),
.ena(1'b1),
.clrn(devclrn || devpor),
.prn(1'b1),
.q(datain_reg)
);
assign in_reg_data = (use_serial_feedback_input == "on") ? serialfbk : datain;
arriaiigz_lvds_reg neg_reg (
.d(in_reg_data_dly),
.clk(!clk0),
.ena(1'b1),
.clrn(devclrn || devpor),
.prn(1'b1),
.q(datain_reg_neg)
);
assign datain_reg_tmp = (align_to_rising_edge_only == "on") ? datain_reg : datain_reg_neg;
// Initial DPA clock phase select
arriaiigz_select_ini_phase_dpaclk ini_clk_phase_select(
.clkin(clk0),
.enable(ini_phase_select_enable),
.loaden(enable0),
.clkout(ini_dpa_clk),
.loadenout(ini_dpa_load)
);
defparam ini_clk_phase_select.initial_phase_select = dpa_initial_phase_value;
assign ini_phase_select_enable = (enable_dpa_initial_phase_selection == "on") ? 1'b1 : 1'b0;
// DPA Circuitary
arriaiigz_lvds_reg dpareg0 (
.d(in_reg_data_dly),
.clk(ini_dpa_clk),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.q(dpareg0_out)
);
arriaiigz_lvds_reg dpareg1 (
.d(dpareg0_out),
.clk(ini_dpa_clk),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.q(dpareg1_out)
);
arriaiigz_dpa_block dpa_circuit(
.clkin(ini_dpa_clk),
.dpareset(dpa_rst),
.dpahold(dpahold),
.datain(dpareg1_out),
.clkout(dpa_clk_shift),
.dataout(dpa_data_shift),
.dpalock (lock_tmp)
);
defparam dpa_circuit.net_ppm_variation = net_ppm_variation;
defparam dpa_circuit.is_negative_ppm_drift = is_negative_ppm_drift;
defparam dpa_circuit.enable_soft_cdr_mode= enable_soft_cdr;
assign dpa_clk = ((enable_soft_cdr == "on")|| (enable_dpa == "on")) ? dpa_clk_shift : 1'b0;
assign dpa_rst = ((enable_soft_cdr == "on")|| (enable_dpa == "on")) ? dpareset : 1'b0;
// DPA clock divide and generate lloaden for soft CDR mode
arriaiigz_pclk_divider clk_forward(
.clkin(dpa_clk),
.lloaden(lloaden),
.clkout(divfwdclk_tmp)
);
defparam clk_forward.clk_divide_by = channel_width;
// FIFO
arriaiigz_lvds_rx_fifo s_fifo (
.wclk(dpa_clk),
.rclk(fifo_rclk),
.fiforst(fifo_reset),
.dparst(dpa_rst),
.datain(fifo_datain),
.dataout(fifo_dataout)
);
defparam s_fifo.channel_width = channel_width;
assign fifo_rclk = (enable_dpa == "on") ? clk0 : gnd;
assign fifo_wclk = dpa_clk;
assign fifo_datain = (enable_dpa == "on") ? dpa_data_shift : gnd;
assign fifo_reset = (!devpor) || (!devclrn) || fiforeset || reset_fifo || dpa_rst;
// BIT SLIP
arriaiigz_lvds_rx_bitslip s_bslip (
.clk0(s_bitslip_clk),
.bslipcntl(bitslip),
.bsliprst(bitslip_reset),
.datain(slip_datain),
.bslipmax(bitslipmax),
.dataout(slip_dataout)
);
defparam s_bslip.channel_width = channel_width;
defparam s_bslip.bitslip_rollover = data_align_rollover;
defparam s_bslip.x_on_bitslip = x_on_bitslip;
assign bitslip_reset = (!devpor) || (!devclrn) || bitslipreset;
assign slip_datain_tmp = (enable_dpa == "on") ? fifo_dataout : datain_reg_tmp;
assign slip_datain = (enable_soft_cdr == "on") ? dpa_data_shift : slip_datain_tmp;
assign s_bitslip_clk = (enable_soft_cdr == "on") ? dpa_clk : clk0;
// DESERIALISER
arriaiigz_lvds_reg rxload_reg (
.d(loaden),
.clk(s_bitslip_clk),
.ena(1'b1),
.clrn(1'b1),
.prn(1'b1),
.q(rxload)
);
assign loaden = (enable_soft_cdr == "on") ? lloaden : ini_dpa_load;
arriaiigz_lvds_rx_deser s_deser (
.clk(s_bitslip_clk),
.datain(slip_dataout),
.devclrn(devclrn),
.devpor(devpor),
.dataout(deser_dataout)
);
defparam s_deser.channel_width = channel_width;
arriaiigz_lvds_rx_parallel_reg output_reg (
.clk(s_bitslip_clk),
.enable(rxload),
.datain(deser_dataout),
.devpor(devpor),
.devclrn(devclrn),
.dataout(dataout)
);
defparam output_reg.channel_width = channel_width;
// generate outputs
assign dpalock_tmp = gnd;
assign postdpaserialdataout_tmp = dpa_data_shift;
assign divfwdclk = divfwdclk_tmp;
assign dpaclkout = dpa_clk_shift;
and (postdpaserialdataout, postdpaserialdataout_tmp, 1'b1);
and (serialdataout, datain, 1'b1);
and (dpalock, dpalock_tmp, 1'b1);
endmodule // arriaiigz_lvds_receiver
//////////////////////////////////////////////////////////////////////////////////
//Module Name: arriaiigz_pseudo_diff_out //
//Description: Simulation model for ARRIAIIGZ Pseudo Differential //
// Output Buffer //
//////////////////////////////////////////////////////////////////////////////////
module arriaiigz_pseudo_diff_out(
i,
o,
obar
);
parameter lpm_type = "arriaiigz_pseudo_diff_out";
input i;
output o;
output obar;
reg o_tmp;
reg obar_tmp;
assign o = o_tmp;
assign obar = obar_tmp;
always@(i)
begin
if( i == 1'b1)
begin
o_tmp = 1'b1;
obar_tmp = 1'b0;
end
else if( i == 1'b0)
begin
o_tmp = 1'b0;
obar_tmp = 1'b1;
end
else
begin
o_tmp = i;
obar_tmp = i;
end
end
endmodule
// -----------------------------------------------------------
//
// Module Name : arriaiigz_bias_logic
//
// Description : ARRIAIIGZ Bias Block's Logic Block
// Verilog simulation model
//
// -----------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_bias_logic (
clk,
shiftnld,
captnupdt,
mainclk,
updateclk,
capture,
update
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
// OUTPUTPUT PORTS
output mainclk;
output updateclk;
output capture;
output update;
// INTERNAL VARIABLES
reg mainclk_tmp;
reg updateclk_tmp;
reg capture_tmp;
reg update_tmp;
initial
begin
mainclk_tmp <= 'b0;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
always @(captnupdt or shiftnld or clk)
begin
case ({captnupdt, shiftnld})
2'b10, 2'b11 :
begin
mainclk_tmp <= 'b0;
updateclk_tmp <= clk;
capture_tmp <= 'b1;
update_tmp <= 'b0;
end
2'b01 :
begin
mainclk_tmp <= 'b0;
updateclk_tmp <= clk;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
2'b00 :
begin
mainclk_tmp <= clk;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b1;
end
default :
begin
mainclk_tmp <= 'b0;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
endcase
end
and (mainclk, mainclk_tmp, 1'b1);
and (updateclk, updateclk_tmp, 1'b1);
and (capture, capture_tmp, 1'b1);
and (update, update_tmp, 1'b1);
endmodule // arriaiigz_bias_logic
// -----------------------------------------------------------
//
// Module Name : arriaiigz_bias_generator
//
// Description : ARRIAIIGZ Bias Generator Verilog simulation model
//
// -----------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_bias_generator (
din,
mainclk,
updateclk,
capture,
update,
dout
);
// INPUT PORTS
input din;
input mainclk;
input updateclk;
input capture;
input update;
// OUTPUTPUT PORTS
output dout;
parameter TOTAL_REG = 202;
// INTERNAL VARIABLES
reg dout_tmp;
reg generator_reg [TOTAL_REG - 1:0];
reg update_reg [TOTAL_REG - 1:0];
integer i;
initial
begin
dout_tmp <= 'b0;
for (i = 0; i < TOTAL_REG; i = i + 1)
begin
generator_reg [i] <= 'b0;
update_reg [i] <= 'b0;
end
end
// main generator registers
always @(posedge mainclk)
begin
if ((capture == 'b0) && (update == 'b1)) //update main registers
begin
for (i = 0; i < TOTAL_REG; i = i + 1)
begin
generator_reg[i] <= update_reg[i];
end
end
end
// update registers
always @(posedge updateclk)
begin
dout_tmp <= update_reg[TOTAL_REG - 1];
if ((capture == 'b0) && (update == 'b0)) //shift update registers
begin
for (i = (TOTAL_REG - 1); i > 0; i = i - 1)
begin
update_reg[i] <= update_reg[i - 1];
end
update_reg[0] <= din;
end
else if ((capture == 'b1) && (update == 'b0)) //load update registers
begin
for (i = 0; i < TOTAL_REG; i = i + 1)
begin
update_reg[i] <= generator_reg[i];
end
end
end
and (dout, dout_tmp, 1'b1);
endmodule // arriaiigz_bias_generator
// -----------------------------------------------------------
//
// Module Name : arriaiigz_bias_block
//
// Description : ARRIAIIGZ Bias Block Verilog simulation model
//
// -----------------------------------------------------------
`timescale 1 ps/1 ps
module arriaiigz_bias_block(
clk,
shiftnld,
captnupdt,
din,
dout
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
input din;
// OUTPUTPUT PORTS
output dout;
parameter lpm_type = "arriaiigz_bias_block";
// INTERNAL VARIABLES
reg din_viol;
reg shiftnld_viol;
reg captnupdt_viol;
wire mainclk_wire;
wire updateclk_wire;
wire capture_wire;
wire update_wire;
wire dout_tmp;
specify
$setuphold (posedge clk, din, 0, 0, din_viol) ;
$setuphold (posedge clk, shiftnld, 0, 0, shiftnld_viol) ;
$setuphold (posedge clk, captnupdt, 0, 0, captnupdt_viol) ;
(posedge clk => (dout +: dout_tmp)) = 0 ;
endspecify
arriaiigz_bias_logic logic_block (
.clk(clk),
.shiftnld(shiftnld),
.captnupdt(captnupdt),
.mainclk(mainclk_wire),
.updateclk(updateclk_wire),
.capture(capture_wire),
.update(update_wire)
);
arriaiigz_bias_generator bias_generator (
.din(din),
.mainclk(mainclk_wire),
.updateclk(updateclk_wire),
.capture(capture_wire),
.update(update_wire),
.dout(dout_tmp)
);
and (dout, dout_tmp, 1'b1);
endmodule // arriaiigz_bias_block
`ifdef MODEL_TECH
`mti_v2k_int_delays_off
`endif
|
Require Import Coq.Sets.Ensembles.
Require Import List.
From OakIFC Require Import
Lattice
Parameters
GenericMap
ModelSemUtils
RuntimeModel
State
Events.
Import ListNotations.
Arguments Ensembles.In {U}.
Arguments Ensembles.Add {U}.
Arguments Ensembles.Subtract {U}.
Arguments Ensembles.Singleton {U}.
From RecordUpdate Require Import RecordSet.
Import RecordSetNotations.
Local Open Scope map_scope.
Local Open Scope ev_notation.
(*
The top-level security condition compares traces involving both states (as
in "state" in RuntimeModel.v) and events. This file augments the semantics
in RuntimeModel.v with rules that also produce labeled Events (in Events.v)
that represent values that are inputs/outputs to/from nodes. It also builds
traces that are sequences of pairs of states and events. In the future,
events will also represent downgrades of values. These events are abstract
objects that are used in the specification of the security condition.
The "input" event during the read is the one that is really strictly needed.
The model of a node does not contain any state corresponding to values.
So a purely state-based security condition would not say anything about values
that are read by a node.
I considered whether traces can be JUST sequences of events
rather than sequences of state/event pairs. I think the answer is no
because then it might be possible to leak information via
the handles a node has. (Even though the call of a node does not contain
informtion because the choice of call is always essentially non-deterministic,
so the call is a piece of state that probably does not matter at the moment)
When downgrades events are added, a trace might need to be
list (state * (Ensemble event)) (Ensembles are sets)
rather than
list (state * event)
since individual calls might produce more than one event. For example,
when a read call does a declassification it would produce an input event
and a downgrade event.
*)
Definition trace := list (state * event_l).
(* This is used for state/event pairs in EvAug.
* The type is slightly awkward now post refactor *)
Definition head_st (t: trace) :=
match t with
| nil => None
| (s', _)::_ => Some s'
end.
Inductive step_node_ev (id: node_id): call -> state -> state -> event_l -> Prop :=
| SWriteChanEv s nlbl han msg s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (WriteChannel han msg) s s' ->
step_node_ev id (WriteChannel han msg) s s' (nlbl ---> msg)
(* The notations used for events on this last line and others
is in Events.v *)
| SReadChanEv s nlbl han chan msg s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (ReadChannel han) s s' ->
msg_is_head chan msg ->
step_node_ev id (ReadChannel han) s s' (nlbl <--- msg)
| SCreateChanEv s nlbl clbl s':
(* It seems clear that no event is needed since nodes only observe
* contents of channels indirectly via reads *)
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (CreateChannel clbl) s s' ->
step_node_ev id (CreateChannel clbl) s s' (nlbl --- )
| SCreateNodeEv s nlbl new_lbl h s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (CreateNode new_lbl h) s s' ->
step_node_ev id (CreateNode new_lbl h) s s' ( -- nlbl -- )
| SWaitOnChannelsEv s hs nlbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (WaitOnChannels hs) s s' ->
step_node_ev id (WaitOnChannels hs) s s' (nlbl ---)
| SChannelCloseEv s han nlbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (ChannelClose han) s s' ->
step_node_ev id (ChannelClose han) s s' (nlbl ---)
| SNodeLabelReadEv s nlbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id NodeLabelRead s s' ->
step_node_ev id NodeLabelRead s s' (nlbl <--L nlbl)
| SChannelLabelReadEv s han nlbl clbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
(s.(chans) .[?han]).(lbl) = clbl ->
step_node id (ChannelLabelRead han) s s' ->
step_node_ev id (ChannelLabelRead han) s s' (nlbl <--L clbl)
| SInternalEv s nlbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id Internal s s' ->
step_node_ev id Internal s s' (nlbl ---).
Inductive step_system_ev: state -> state -> event_l -> Prop :=
| SytsemEvSkip s ell: step_system_ev s s (ell ---)
| SystemEvStepNode id n c c' s s' e:
(s.(nodes).[?id]).(obj) = Some n ->
n.(ncall) = c ->
step_node_ev id c s s' e ->
let s'' := (s_set_call s' id c') in
(* Here c' is an arbitrary command. The next ABI call
that the node makes after the one executed here is an arbitrary one
of that node's choosing *)
step_system_ev s s'' e.
(* TODO
Theorem that proves that step_system_ev is sound/complete for step_system.
(* should be trivial ? *)
The reason why there is more than one state transition relation is that the
'events' are just an abstract concept meant to state the security theorems,
so it seemed useful to keep them separate from the main specification of
behavior.
Alternatively, we could just decide that actually including events in the
main specification of behavior is just fine, and then we just replace
step_sytem with step_system_ev.
*)
Inductive step_system_ev_t: trace -> trace -> Prop :=
| StepTrace t s s' e:
head_st t = Some s ->
step_system_ev s s' e ->
step_system_ev_t t ((s', e) :: t).
Inductive step_system_ev_multi: trace -> trace -> Prop :=
| multi_system_ev_refl t t':
step_system_ev_t t t' ->
step_system_ev_multi t t'
| multi_system_ev_tran t1 t2 t3:
step_system_ev_t t2 t3 ->
step_system_ev_multi t1 t2 ->
step_system_ev_multi t1 t3.
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_load_store_unit.v
// Title : Load and store unit
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : Instead of disallowing an instruction cache miss on a data cache
// : miss, both can now occur at the same time. If both occur at same
// : time, then restart address is the address of instruction that
// : caused data cache miss.
// Version : 3.2
// : EBRs use SYNC resets instead of ASYNC resets.
// Version : 3.3
// : Support for new non-cacheable Data Memory that is accessible by
// : the data port and has a one cycle access latency.
// Version : 3.4
// : No change
// Version : 3.5
// : Bug fix: Inline memory is correctly generated if it is not a
// : power-of-two
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_load_store_unit (
// ----- Inputs -------
clk_i,
rst_i,
// From pipeline
stall_a,
stall_x,
stall_m,
kill_m,
exception_m,
store_operand_x,
load_store_address_x,
load_store_address_m,
load_store_address_w,
load_x,
store_x,
load_q_x,
store_q_x,
load_q_m,
store_q_m,
sign_extend_x,
size_x,
`ifdef CFG_DCACHE_ENABLED
dflush,
`endif
`ifdef CFG_IROM_ENABLED
irom_data_m,
`endif
// From Wishbone
d_dat_i,
d_ack_i,
d_err_i,
d_rty_i,
// ----- Outputs -------
// To pipeline
`ifdef CFG_DCACHE_ENABLED
dcache_refill_request,
dcache_restart_request,
dcache_stall_request,
dcache_refilling,
`endif
`ifdef CFG_IROM_ENABLED
irom_store_data_m,
irom_address_xm,
irom_we_xm,
irom_stall_request_x,
`endif
load_data_w,
stall_wb_load,
// To Wishbone
d_dat_o,
d_adr_o,
d_cyc_o,
d_sel_o,
d_stb_o,
d_we_o,
d_cti_o,
d_lock_o,
d_bte_o
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter associativity = 1; // Associativity of the cache (Number of ways)
parameter sets = 512; // Number of sets
parameter bytes_per_line = 16; // Number of bytes per cache line
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory
// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
localparam addr_offset_lsb = 2;
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_a; // A stage stall
input stall_x; // X stage stall
input stall_m; // M stage stall
input kill_m; // Kill instruction in M stage
input exception_m; // An exception occured in the M stage
input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address
input [`LM32_WORD_RNG] load_store_address_m; // M stage load/store address
input [1:0] load_store_address_w; // W stage load/store address (only least two significant bits are needed)
input load_x; // Load instruction in X stage
input store_x; // Store instruction in X stage
input load_q_x; // Load instruction in X stage
input store_q_x; // Store instruction in X stage
input load_q_m; // Load instruction in M stage
input store_q_m; // Store instruction in M stage
input sign_extend_x; // Whether load instruction in X stage should sign extend or zero extend
input [`LM32_SIZE_RNG] size_x; // Size of load or store (byte, hword, word)
`ifdef CFG_DCACHE_ENABLED
input dflush; // Flush the data cache
`endif
`ifdef CFG_IROM_ENABLED
input [`LM32_WORD_RNG] irom_data_m; // Data from Instruction-ROM
`endif
input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data
input d_ack_i; // Data Wishbone interface acknowledgement
input d_err_i; // Data Wishbone interface error
input d_rty_i; // Data Wishbone interface retry
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
`ifdef CFG_DCACHE_ENABLED
output dcache_refill_request; // Request to refill data cache
wire dcache_refill_request;
output dcache_restart_request; // Request to restart the instruction that caused a data cache miss
wire dcache_restart_request;
output dcache_stall_request; // Data cache stall request
wire dcache_stall_request;
output dcache_refilling;
wire dcache_refilling;
`endif
`ifdef CFG_IROM_ENABLED
output irom_store_data_m; // Store data to Instruction ROM
wire [`LM32_WORD_RNG] irom_store_data_m;
output [`LM32_WORD_RNG] irom_address_xm; // Load/store address to Instruction ROM
wire [`LM32_WORD_RNG] irom_address_xm;
output irom_we_xm; // Write-enable of 2nd port of Instruction ROM
wire irom_we_xm;
output irom_stall_request_x; // Stall instruction in D stage
wire irom_stall_request_x;
`endif
output [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
reg [`LM32_WORD_RNG] load_data_w;
output stall_wb_load; // Request to stall pipeline due to a load from the Wishbone interface
reg stall_wb_load;
output [`LM32_WORD_RNG] d_dat_o; // Data Wishbone interface write data
reg [`LM32_WORD_RNG] d_dat_o;
output [`LM32_WORD_RNG] d_adr_o; // Data Wishbone interface address
reg [`LM32_WORD_RNG] d_adr_o;
output d_cyc_o; // Data Wishbone interface cycle
reg d_cyc_o;
output [`LM32_BYTE_SELECT_RNG] d_sel_o; // Data Wishbone interface byte select
reg [`LM32_BYTE_SELECT_RNG] d_sel_o;
output d_stb_o; // Data Wishbone interface strobe
reg d_stb_o;
output d_we_o; // Data Wishbone interface write enable
reg d_we_o;
output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type
reg [`LM32_CTYPE_RNG] d_cti_o;
output d_lock_o; // Date Wishbone interface lock bus
reg d_lock_o;
output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type
wire [`LM32_BTYPE_RNG] d_bte_o;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
// Microcode pipeline registers - See inputs for description
reg [`LM32_SIZE_RNG] size_m;
reg [`LM32_SIZE_RNG] size_w;
reg sign_extend_m;
reg sign_extend_w;
reg [`LM32_WORD_RNG] store_data_x;
reg [`LM32_WORD_RNG] store_data_m;
reg [`LM32_BYTE_SELECT_RNG] byte_enable_x;
reg [`LM32_BYTE_SELECT_RNG] byte_enable_m;
wire [`LM32_WORD_RNG] data_m;
reg [`LM32_WORD_RNG] data_w;
`ifdef CFG_DCACHE_ENABLED
wire dcache_select_x; // Select data cache to load from / store to
reg dcache_select_m;
wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache
wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from
reg dcache_refill_ready; // Indicates the next word of refill data is ready
wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
wire last_word; // Indicates if this is the last word in the cache line
wire [`LM32_WORD_RNG] first_address; // First cache refill address
`endif
`ifdef CFG_DRAM_ENABLED
wire dram_select_x; // Select data RAM to load from / store to
reg dram_select_m;
reg dram_bypass_en; // RAW in data RAM; read latched (bypass) value rather than value from memory
reg [`LM32_WORD_RNG] dram_bypass_data; // Latched value of store'd data to data RAM
wire [`LM32_WORD_RNG] dram_data_out; // Data read from data RAM
wire [`LM32_WORD_RNG] dram_data_m; // Data read from data RAM: bypass value or value from memory
wire [`LM32_WORD_RNG] dram_store_data_m; // Data to write to RAM
`endif
wire wb_select_x; // Select Wishbone to load from / store to
`ifdef CFG_IROM_ENABLED
wire irom_select_x; // Select instruction ROM to load from / store to
reg irom_select_m;
`endif
reg wb_select_m;
reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone
reg wb_load_complete; // Indicates when a Wishbone load is complete
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
`include "lm32_functions.v"
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
`ifdef CFG_DRAM_ENABLED
// Data RAM
pmi_ram_dp_true
#(
// ----- Parameters -------
.pmi_family (`LATTICE_FAMILY),
//.pmi_addr_depth_a (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
//.pmi_addr_width_a ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
//.pmi_data_width_a (`LM32_WORD_WIDTH),
//.pmi_addr_depth_b (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
//.pmi_addr_width_b ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
//.pmi_data_width_b (`LM32_WORD_WIDTH),
.pmi_addr_depth_a (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
.pmi_addr_width_a (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
.pmi_data_width_a (`LM32_WORD_WIDTH),
.pmi_addr_depth_b (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
.pmi_addr_width_b (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
.pmi_data_width_b (`LM32_WORD_WIDTH),
.pmi_regmode_a ("noreg"),
.pmi_regmode_b ("noreg"),
.pmi_gsr ("enable"),
.pmi_resetmode ("sync"),
.pmi_init_file (`CFG_DRAM_INIT_FILE),
.pmi_init_file_format (`CFG_DRAM_INIT_FILE_FORMAT),
.module_type ("pmi_ram_dp_true")
)
ram (
// ----- Inputs -------
.ClockA (clk_i),
.ClockB (clk_i),
.ResetA (rst_i),
.ResetB (rst_i),
.DataInA ({32{1'b0}}),
.DataInB (dram_store_data_m),
.AddressA (load_store_address_x[clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
.AddressB (load_store_address_m[clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
// .ClockEnA (!stall_x & (load_x | store_x)),
.ClockEnA (!stall_x),
.ClockEnB (!stall_m),
.WrA (`FALSE),
.WrB (store_q_m & dram_select_m),
// ----- Outputs -------
.QA (dram_data_out),
.QB ()
);
/*----------------------------------------------------------------------
EBRs cannot perform reads from location 'written to' on the same clock
edge. Therefore bypass logic is required to latch the store'd value
and use it for the load (instead of value from memory).
----------------------------------------------------------------------*/
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
if (rst_i == `TRUE)
begin
dram_bypass_en <= #1 `FALSE;
dram_bypass_data <= #1 0;
end
else
begin
if (stall_x == `FALSE)
dram_bypass_data <= #1 dram_store_data_m;
if ( (stall_m == `FALSE)
&& (stall_x == `FALSE)
&& (store_q_m == `TRUE)
&& ( (load_x == `TRUE)
|| (store_x == `TRUE)
)
&& (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
)
dram_bypass_en <= #1 `TRUE;
else
if ( (dram_bypass_en == `TRUE)
&& (stall_x == `FALSE)
)
dram_bypass_en <= #1 `FALSE;
end
assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
`endif
`ifdef CFG_DCACHE_ENABLED
// Data cache
lm32_dcache #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
.base_address (base_address),
.limit (limit)
) dcache (
// ----- Inputs -----
.clk_i (clk_i),
.rst_i (rst_i),
.stall_a (stall_a),
.stall_x (stall_x),
.stall_m (stall_m),
.address_x (load_store_address_x),
.address_m (load_store_address_m),
.load_q_m (load_q_m & dcache_select_m),
.store_q_m (store_q_m & dcache_select_m),
.store_data (store_data_m),
.store_byte_select (byte_enable_m & {4{dcache_select_m}}),
.refill_ready (dcache_refill_ready),
.refill_data (wb_data_m),
.dflush (dflush),
// ----- Outputs -----
.stall_request (dcache_stall_request),
.restart_request (dcache_restart_request),
.refill_request (dcache_refill_request),
.refill_address (dcache_refill_address),
.refilling (dcache_refilling),
.load_data (dcache_data_m)
);
`endif
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Select where data should be loaded from / stored to
`ifdef CFG_DRAM_ENABLED
assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS)
&& (load_store_address_x <= `CFG_DRAM_LIMIT);
`endif
`ifdef CFG_IROM_ENABLED
assign irom_select_x = (load_store_address_x >= `CFG_IROM_BASE_ADDRESS)
&& (load_store_address_x <= `CFG_IROM_LIMIT);
`endif
`ifdef CFG_DCACHE_ENABLED
assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS)
&& (load_store_address_x <= `CFG_DCACHE_LIMIT)
`ifdef CFG_DRAM_ENABLED
&& (dram_select_x == `FALSE)
`endif
`ifdef CFG_IROM_ENABLED
&& (irom_select_x == `FALSE)
`endif
;
`endif
assign wb_select_x = `TRUE
`ifdef CFG_DCACHE_ENABLED
&& !dcache_select_x
`endif
`ifdef CFG_DRAM_ENABLED
&& !dram_select_x
`endif
`ifdef CFG_IROM_ENABLED
&& !irom_select_x
`endif
;
// Make sure data to store is in correct byte lane
always @(*)
begin
case (size_x)
`LM32_SIZE_BYTE: store_data_x = {4{store_operand_x[7:0]}};
`LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}};
`LM32_SIZE_WORD: store_data_x = store_operand_x;
default: store_data_x = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
// Generate byte enable accoring to size of load or store and address being accessed
always @(*)
begin
casez ({size_x, load_store_address_x[1:0]})
{`LM32_SIZE_BYTE, 2'b11}: byte_enable_x = 4'b0001;
{`LM32_SIZE_BYTE, 2'b10}: byte_enable_x = 4'b0010;
{`LM32_SIZE_BYTE, 2'b01}: byte_enable_x = 4'b0100;
{`LM32_SIZE_BYTE, 2'b00}: byte_enable_x = 4'b1000;
{`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011;
{`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100;
{`LM32_SIZE_WORD, 2'b??}: byte_enable_x = 4'b1111;
default: byte_enable_x = 4'bxxxx;
endcase
end
`ifdef CFG_DRAM_ENABLED
// Only replace selected bytes
assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG];
assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG];
assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG];
assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG];
`endif
`ifdef CFG_IROM_ENABLED
// Only replace selected bytes
assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG];
assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG];
assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG];
assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG];
`endif
`ifdef CFG_IROM_ENABLED
// Instead of implementing a byte-addressable instruction ROM (for store byte instruction),
// a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite
// byte is replaced, and the whole 32-bit value is written back
assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE))
? load_store_address_m
: load_store_address_x;
// All store instructions perform a write operation in the M stage
assign irom_we_xm = (irom_select_m == `TRUE)
&& (store_q_m == `TRUE);
// A single port in instruction ROM is available to load-store unit for doing loads/stores.
// Since every store requires a load (in X stage) and then a store (in M stage), we cannot
// allow load (or store) instructions sequentially after the store instructions to proceed
// until the store instruction has vacated M stage (i.e., completed the store operation)
assign irom_stall_request_x = (irom_select_x == `TRUE)
&& (store_q_x == `TRUE);
`endif
`ifdef CFG_DCACHE_ENABLED
`ifdef CFG_DRAM_ENABLED
`ifdef CFG_IROM_ENABLED
// WB + DC + DRAM + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_select_m == `TRUE
? dram_data_m
: irom_select_m == `TRUE
? irom_data_m
: dcache_data_m;
`else
// WB + DC + DRAM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_select_m == `TRUE
? dram_data_m
: dcache_data_m;
`endif
`else
`ifdef CFG_IROM_ENABLED
// WB + DC + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: irom_select_m == `TRUE
? irom_data_m
: dcache_data_m;
`else
// WB + DC
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dcache_data_m;
`endif
`endif
`else
`ifdef CFG_DRAM_ENABLED
`ifdef CFG_IROM_ENABLED
// WB + DRAM + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_select_m == `TRUE
? dram_data_m
: irom_data_m;
`else
// WB + DRAM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_data_m;
`endif
`else
`ifdef CFG_IROM_ENABLED
// WB + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: irom_data_m;
`else
// WB
assign data_m = wb_data_m;
`endif
`endif
`endif
// Sub-word selection and sign/zero-extension for loads
always @(*)
begin
casez ({size_w, load_store_address_w[1:0]})
{`LM32_SIZE_BYTE, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
{`LM32_SIZE_BYTE, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
{`LM32_SIZE_BYTE, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
{`LM32_SIZE_BYTE, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
{`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
{`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
{`LM32_SIZE_WORD, 2'b??}: load_data_w = data_w;
default: load_data_w = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
// Unused/constant Wishbone signals
assign d_bte_o = `LM32_BTYPE_LINEAR;
`ifdef CFG_DCACHE_ENABLED
// Generate signal to indicate last word in cache line
generate
case (bytes_per_line)
4:
begin
assign first_cycle_type = `LM32_CTYPE_END;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = `TRUE;
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00};
end
8:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
end
16:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
end
endcase
endgenerate
`endif
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// Data Wishbone interface
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
d_cyc_o <= #1 `FALSE;
d_stb_o <= #1 `FALSE;
d_dat_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
d_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
d_sel_o <= #1 {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
d_we_o <= #1 `FALSE;
d_cti_o <= #1 `LM32_CTYPE_END;
d_lock_o <= #1 `FALSE;
wb_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}};
wb_load_complete <= #1 `FALSE;
stall_wb_load <= #1 `FALSE;
`ifdef CFG_DCACHE_ENABLED
dcache_refill_ready <= #1 `FALSE;
`endif
end
else
begin
`ifdef CFG_DCACHE_ENABLED
// Refill ready should only be asserted for a single cycle
dcache_refill_ready <= #1 `FALSE;
`endif
// Is a Wishbone cycle already in progress?
if (d_cyc_o == `TRUE)
begin
// Is the cycle complete?
if ((d_ack_i == `TRUE) || (d_err_i == `TRUE))
begin
`ifdef CFG_DCACHE_ENABLED
if ((dcache_refilling == `TRUE) && (!last_word))
begin
// Fetch next word of cache line
d_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
end
else
`endif
begin
// Refill/access complete
d_cyc_o <= #1 `FALSE;
d_stb_o <= #1 `FALSE;
d_lock_o <= #1 `FALSE;
end
`ifdef CFG_DCACHE_ENABLED
d_cti_o <= #1 next_cycle_type;
// If we are performing a refill, indicate to cache next word of data is ready
dcache_refill_ready <= #1 dcache_refilling;
`endif
// Register data read from Wishbone interface
wb_data_m <= #1 d_dat_i;
// Don't set when stores complete - otherwise we'll deadlock if load in m stage
wb_load_complete <= #1 !d_we_o;
end
// synthesis translate_off
if (d_err_i == `TRUE)
$display ("Data bus error. Address: %x", d_adr_o);
// synthesis translate_on
end
else
begin
`ifdef CFG_DCACHE_ENABLED
if (dcache_refill_request == `TRUE)
begin
// Start cache refill
d_adr_o <= #1 first_address;
d_cyc_o <= #1 `TRUE;
d_sel_o <= #1 {`LM32_WORD_WIDTH/8{`TRUE}};
d_stb_o <= #1 `TRUE;
d_we_o <= #1 `FALSE;
d_cti_o <= #1 first_cycle_type;
//d_lock_o <= #1 `TRUE;
end
else
`endif
if ( (store_q_m == `TRUE)
&& (stall_m == `FALSE)
`ifdef CFG_DRAM_ENABLED
&& (dram_select_m == `FALSE)
`endif
`ifdef CFG_IROM_ENABLED
&& (irom_select_m == `FALSE)
`endif
)
begin
// Data cache is write through, so all stores go to memory
d_dat_o <= #1 store_data_m;
d_adr_o <= #1 load_store_address_m;
d_cyc_o <= #1 `TRUE;
d_sel_o <= #1 byte_enable_m;
d_stb_o <= #1 `TRUE;
d_we_o <= #1 `TRUE;
d_cti_o <= #1 `LM32_CTYPE_END;
end
else if ( (load_q_m == `TRUE)
&& (wb_select_m == `TRUE)
&& (wb_load_complete == `FALSE)
// stall_m will be TRUE, because stall_wb_load will be TRUE
)
begin
// Read requested address
stall_wb_load <= #1 `FALSE;
d_adr_o <= #1 load_store_address_m;
d_cyc_o <= #1 `TRUE;
d_sel_o <= #1 byte_enable_m;
d_stb_o <= #1 `TRUE;
d_we_o <= #1 `FALSE;
d_cti_o <= #1 `LM32_CTYPE_END;
end
end
// Clear load/store complete flag when instruction leaves M stage
if (stall_m == `FALSE)
wb_load_complete <= #1 `FALSE;
// When a Wishbone load first enters the M stage, we need to stall it
if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
stall_wb_load <= #1 `TRUE;
// Clear stall request if load instruction is killed
if ((kill_m == `TRUE) || (exception_m == `TRUE))
stall_wb_load <= #1 `FALSE;
end
end
// Pipeline registers
// X/M stage pipeline registers
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
sign_extend_m <= #1 `FALSE;
size_m <= #1 2'b00;
byte_enable_m <= #1 `FALSE;
store_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}};
`ifdef CFG_DCACHE_ENABLED
dcache_select_m <= #1 `FALSE;
`endif
`ifdef CFG_DRAM_ENABLED
dram_select_m <= #1 `FALSE;
`endif
`ifdef CFG_IROM_ENABLED
irom_select_m <= #1 `FALSE;
`endif
wb_select_m <= #1 `FALSE;
end
else
begin
if (stall_m == `FALSE)
begin
sign_extend_m <= #1 sign_extend_x;
size_m <= #1 size_x;
byte_enable_m <= #1 byte_enable_x;
store_data_m <= #1 store_data_x;
`ifdef CFG_DCACHE_ENABLED
dcache_select_m <= #1 dcache_select_x;
`endif
`ifdef CFG_DRAM_ENABLED
dram_select_m <= #1 dram_select_x;
`endif
`ifdef CFG_IROM_ENABLED
irom_select_m <= #1 irom_select_x;
`endif
wb_select_m <= #1 wb_select_x;
end
end
end
// M/W stage pipeline registers
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
size_w <= #1 2'b00;
data_w <= #1 {`LM32_WORD_WIDTH{1'b0}};
sign_extend_w <= #1 `FALSE;
end
else
begin
size_w <= #1 size_m;
data_w <= #1 data_m;
sign_extend_w <= #1 sign_extend_m;
end
end
/////////////////////////////////////////////////////
// Behavioural Logic
/////////////////////////////////////////////////////
// synthesis translate_off
// Check for non-aligned loads or stores
always @(posedge clk_i)
begin
if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE))
begin
if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0))
$display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00))
$display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
end
end
// synthesis translate_on
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module reads and writes data to the RS232 connector on Altera's *
* DE-series Development and Education Boards. *
* *
******************************************************************************/
module nios_system_rs232_0 (
// Inputs
clk,
reset,
address,
chipselect,
byteenable,
read,
write,
writedata,
UART_RXD,
// Bidirectionals
// Outputs
irq,
readdata,
UART_TXD
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 434;
parameter HALF_BAUD_TICK_COUNT = 217;
parameter TDW = 10; // Total data width
parameter DW = 8; // Data width
parameter ODD_PARITY = 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input address;
input chipselect;
input [ 3: 0] byteenable;
input read;
input write;
input [31: 0] writedata;
input UART_RXD;
// Bidirectionals
// Outputs
output reg irq;
output reg [31: 0] readdata;
output UART_TXD;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_fifo_read_en;
wire [ 7: 0] read_available;
wire read_data_valid;
wire [(DW-1):0] read_data;
wire parity_error;
wire write_data_parity;
wire [ 7: 0] write_space;
// Internal Registers
reg read_interrupt_en;
reg write_interrupt_en;
reg read_interrupt;
reg write_interrupt;
reg write_fifo_write_en;
reg [(DW-1):0] data_to_uart;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
irq <= 1'b0;
else
irq <= write_interrupt | read_interrupt;
end
always @(posedge clk)
begin
if (reset)
readdata <= 32'h00000000;
else if (chipselect)
begin
if (address == 1'b0)
readdata <=
{8'h00,
read_available,
read_data_valid,
5'h00,
parity_error,
1'b0,
read_data[(DW - 1):0]};
else
readdata <=
{8'h00,
write_space,
6'h00,
write_interrupt,
read_interrupt,
6'h00,
write_interrupt_en,
read_interrupt_en};
end
end
always @(posedge clk)
begin
if (reset)
read_interrupt_en <= 1'b0;
else if ((chipselect) && (write) && (address) && (byteenable[0]))
read_interrupt_en <= writedata[0];
end
always @(posedge clk)
begin
if (reset)
write_interrupt_en <= 1'b0;
else if ((chipselect) && (write) && (address) && (byteenable[0]))
write_interrupt_en <= writedata[1];
end
always @(posedge clk)
begin
if (reset)
read_interrupt <= 1'b0;
else if (read_interrupt_en == 1'b0)
read_interrupt <= 1'b0;
else
read_interrupt <= (&(read_available[6:5]) | read_available[7]);
end
always @(posedge clk)
begin
if (reset)
write_interrupt <= 1'b0;
else if (write_interrupt_en == 1'b0)
write_interrupt <= 1'b0;
else
write_interrupt <= (&(write_space[6:5]) | write_space[7]);
end
always @(posedge clk)
begin
if (reset)
write_fifo_write_en <= 1'b0;
else
write_fifo_write_en <=
chipselect & write & ~address & byteenable[0];
end
always @(posedge clk)
begin
if (reset)
data_to_uart <= 'h0;
else
data_to_uart <= writedata[(DW - 1):0];
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign parity_error = 1'b0;
assign read_fifo_read_en = chipselect & read & ~address & byteenable[0];
assign write_data_parity = (^(data_to_uart)) ^ ODD_PARITY;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_in_deserializer RS232_In_Deserializer (
// Inputs
.clk (clk),
.reset (reset),
.serial_data_in (UART_RXD),
.receive_data_en (read_fifo_read_en),
// Bidirectionals
// Outputs
.fifo_read_available (read_available),
.received_data_valid (read_data_valid),
.received_data (read_data)
);
defparam
RS232_In_Deserializer.CW = CW,
RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Deserializer.TDW = TDW,
RS232_In_Deserializer.DW = (DW - 1);
altera_up_rs232_out_serializer RS232_Out_Serializer (
// Inputs
.clk (clk),
.reset (reset),
.transmit_data (data_to_uart),
.transmit_data_en (write_fifo_write_en),
// Bidirectionals
// Outputs
.fifo_write_space (write_space),
.serial_data_out (UART_TXD)
);
defparam
RS232_Out_Serializer.CW = CW,
RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Serializer.TDW = TDW,
RS232_Out_Serializer.DW = (DW - 1);
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:19:07 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemTextures/MemTextures_stub.v
// Design : MemTextures
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dist_mem_gen_v8_0,Vivado 2014.4" *)
module MemTextures(a, clk, spo)
/* synthesis syn_black_box black_box_pad_pin="a[7:0],clk,spo[91:0]" */;
input [7:0]a;
input clk;
output [91:0]spo;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : ddr_phy_top.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Aug 03 2009
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Top level memory interface block. Instantiates a clock
// and reset generator, the memory controller, the phy and
// the user interface blocks.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_0_ddr_phy_top #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter DDR3_VDD_OP_VOLT = 135, // Voltage mode used for DDR3
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter LP_DDR_CK_WIDTH = 2,
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
// five fields, one per possible I/O bank, 4 bits in each field,
// 1 per lane data=1/ctl=0
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
// defines the byte lanes in I/O banks being used in the interface
// 1- Used, 0- Unused
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
// defines the bit lanes in I/O banks being used in the interface. Each
// parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// This parameter must be set based on memory clock frequency
// It must be set to 4 for frequencies above 533 MHz?? (undecided)
// and set to 2 for 533 MHz and below
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T"
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
parameter OUTPUT_DRV = "HIGH", // to calib_top
parameter REG_CTRL = "OFF", // to calib_top
parameter RTT_NOM = "60", // to calib_top
parameter RTT_WR = "120", // to calib_top
parameter tCK = 2500, // pS
parameter tRFC = 110000, // pS
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter WRLVL = "OFF", // to calib_top
parameter DEBUG_PORT = "OFF", // to calib_top
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// Simulation /debug options
parameter SIM_BYPASS_INIT_CAL = "OFF",
// Parameter used to force skipping
// or abbreviation of initialization
// and calibration. Overrides
// SIM_INIT_OPTION, SIM_CAL_OPTION,
// and disables various other blocks
//parameter SIM_INIT_OPTION = "SKIP_PU_DLY", // Skip various init steps
//parameter SIM_CAL_OPTION = "NONE", // Skip various calib steps
parameter REFCLK_FREQ = 200.0, // IODELAY ref clock freq (MHz)
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter RD_PATH_REG = 0 // optional registers in the read path
// to MC for timing improvement.
// =1 enabled, = 0 disabled
)
(
input clk, // Fabric logic clock
// To MC, calib_top, hard PHY
input clk_ref, // Idelay_ctrl reference clock
// To hard PHY (external source)
input freq_refclk, // To hard PHY for Phasers
input mem_refclk, // Memory clock to hard PHY
input pll_lock, // System PLL lock signal
input sync_pulse, // 1/N sync pulse used to
// synchronize all PHASERS
input error, // Support for TG error detect
output rst_tg_mc, // Support for TG error detect
input [11:0] device_temp,
input tempmon_sample_en,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input rst,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// From MC
input [nCK_PER_CLK-1:0] mc_ras_n,
input [nCK_PER_CLK-1:0] mc_cas_n,
input [nCK_PER_CLK-1:0] mc_we_n,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
input mc_reset_n,
input [1:0] mc_odt,
input [nCK_PER_CLK-1:0] mc_cke,
// AUX - For ODT and CKE assertion during reads and writes
input [3:0] mc_aux_out0,
input [3:0] mc_aux_out1,
input mc_cmd_wren,
input mc_ctl_wren,
input [2:0] mc_cmd,
input [1:0] mc_cas_slot,
input [5:0] mc_data_offset,
input [5:0] mc_data_offset_1,
input [5:0] mc_data_offset_2,
input [1:0] mc_rank_cnt,
// Write
input mc_wrdata_en,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mc_wrdata_mask,
input idle,
// DDR bus signals
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
// Debug Port Outputs
output [255:0] dbg_calib_top,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output dbg_rddata_valid,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output [255:0] dbg_phy_wrlvl,
output dbg_pi_phaselock_start,
output dbg_pi_phaselocked_done,
output dbg_pi_phaselock_err,
output [11:0] dbg_pi_phase_locked_phy4lanes,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_pi_dqsfound_err,
output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrcal_err,
// FIFO status flags
output phy_mc_ctl_full,
output phy_mc_cmd_full,
output phy_mc_data_full,
// Calibration status and resultant outputs
output init_calib_complete,
output init_wrcal_complete,
output [6*RANKS-1:0] calib_rd_data_offset_0,
output [6*RANKS-1:0] calib_rd_data_offset_1,
output [6*RANKS-1:0] calib_rd_data_offset_2,
output phy_rddata_valid,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data,
output ref_dll_lock,
input rst_phaser_ref,
output [6*RANKS-1:0] dbg_rd_data_offset,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [5:0] dbg_pi_counter_read_val,
output [8:0] dbg_po_counter_read_val,
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data
);
// Calculate number of slots in the system
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
// Parameter used to force skipping or abbreviation of initialization
// and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and
// disables various other blocks depending on the option selected
// This option should only be used during simulation. In the case of
// the "SKIP" option, the testbench used should also not be modeling
// propagation delays.
// Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"}
// "NONE" = options determined by the individual parameter settings
// "SIM_FULL" = skip power-up delay. FULL calibration performed without
// averaging algorithm turned ON during window detection.
// "SKIP" = skip power-up delay. Skip calibration not yet supported.
// "FAST" = skip power-up delay, and calibrate (read leveling, write
// leveling, and phase detector) only using one DQS group, and
// apply the results to all other DQS groups.
localparam SIM_INIT_OPTION
= ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_INIT" :
((SIM_BYPASS_INIT_CAL == "FAST") ||
(SIM_BYPASS_INIT_CAL == "SIM_FULL")) ? "SKIP_PU_DLY" :
"NONE");
localparam SIM_CAL_OPTION
= ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_CAL" :
(SIM_BYPASS_INIT_CAL == "FAST") ? "FAST_CAL" :
((SIM_BYPASS_INIT_CAL == "SIM_FULL") ||
(SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")) ? "FAST_WIN_DETECT" :
"NONE");
localparam WRLVL_W
= (SIM_BYPASS_INIT_CAL == "SKIP") ? "OFF" : WRLVL;
localparam HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 :
(BYTE_LANES_B2 != 0 ? 3 :
(BYTE_LANES_B1 != 0 ? 2 : 1))));
localparam HIGHEST_LANE_B0 = BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 :
BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 :
0;
localparam HIGHEST_LANE_B1 = BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 :
BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 :
0;
localparam HIGHEST_LANE_B2 = BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 :
BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 :
0;
localparam HIGHEST_LANE_B3 = BYTE_LANES_B3[3] ? 4 : BYTE_LANES_B3[2] ? 3 :
BYTE_LANES_B3[1] ? 2 : BYTE_LANES_B3[0] ? 1 :
0;
localparam HIGHEST_LANE_B4 = BYTE_LANES_B4[3] ? 4 : BYTE_LANES_B4[2] ? 3 :
BYTE_LANES_B4[1] ? 2 : BYTE_LANES_B4[0] ? 1 :
0;
localparam HIGHEST_LANE =
(HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) :
((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) :
((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) :
((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) :
HIGHEST_LANE_B0)));
localparam N_CTL_LANES = ((0+(!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) +
(0+(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) +
(0+(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) +
(0+(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) +
((0+(!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) +
(0+(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) +
(0+(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) +
(0+(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) +
((0+(!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) +
(0+(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) +
(0+(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) +
(0+(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) +
((0+(!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) +
(0+(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) +
(0+(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) +
(0+(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) +
((0+(!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) +
(0+(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) +
(0+(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) +
(0+(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]));
// Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank
// This should be the case since the PLL should be placed adjacent
// to the same IO Bank as Ck/Addr/Cmd and Control
localparam [2:0] CTL_BANK = (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) |
((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) |
((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) ?
3'b000 :
(((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) |
((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) ?
3'b001 :
(((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) |
((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) ?
3'b010 :
(((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) |
((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) ?
3'b011 :
(((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) |
((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) |
((!DATA_CTL_B4[3]) & BYTE_LANES_B4[3])) ?
3'b100 : 3'b000;
localparam [7:0] CTL_BYTE_LANE = (N_CTL_LANES == 4) ? 8'b11_10_01_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
8'b00_10_01_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_11_01_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_11_10_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_11_10_01 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]))) ?
8'b00_00_01_00 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_00_11_00 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_00_11_10 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
8'b00_00_10_01 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_00_11_01 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
8'b00_00_10_00 : 8'b11_10_01_00;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire [(HIGHEST_LANE*12)-1:0] ddr_cmd_ctl_data;
wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out;
wire [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk;
wire phy_mc_go;
wire phy_ctl_full;
wire phy_cmd_full;
wire phy_data_full;
wire phy_pre_data_a_full;
wire if_empty /* synthesis syn_maxfan = 3 */;
wire phy_write_calib;
wire phy_read_calib;
wire [HIGHEST_BANK-1:0] rst_stg1_cal;
wire [5:0] calib_sel;
wire calib_in_common /* synthesis syn_maxfan = 10 */;
wire [HIGHEST_BANK-1:0] calib_zero_inputs;
wire [HIGHEST_BANK-1:0] calib_zero_ctrl;
wire pi_phase_locked;
wire pi_phase_locked_all;
wire pi_found_dqs;
wire pi_dqs_found_all;
wire pi_dqs_out_of_range;
wire pi_enstg2_f;
wire pi_stg2_fincdec;
wire pi_stg2_load;
wire [5:0] pi_stg2_reg_l;
wire idelay_ce;
wire idelay_inc;
wire idelay_ld;
wire [2:0] po_sel_stg2stg3;
wire [2:0] po_stg2_cincdec;
wire [2:0] po_enstg2_c;
wire [2:0] po_stg2_fincdec;
wire [2:0] po_enstg2_f;
wire [8:0] po_counter_read_val;
wire [5:0] pi_counter_read_val;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata;
reg [nCK_PER_CLK-1:0] parity;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] phy_bank;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n;
wire [nCK_PER_CLK-1:0] phy_ras_n;
wire [nCK_PER_CLK-1:0] phy_cas_n;
wire [nCK_PER_CLK-1:0] phy_we_n;
wire phy_reset_n;
wire [3:0] calib_aux_out;
wire [nCK_PER_CLK-1:0] calib_cke;
wire [1:0] calib_odt;
wire calib_ctl_wren;
wire calib_cmd_wren;
wire calib_wrdata_en;
wire [2:0] calib_cmd;
wire [1:0] calib_seq;
wire [5:0] calib_data_offset_0;
wire [5:0] calib_data_offset_1;
wire [5:0] calib_data_offset_2;
wire [1:0] calib_rank_cnt;
wire [1:0] calib_cas_slot;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address;
wire [3:0] mux_aux_out;
wire [3:0] aux_out_map;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank;
wire [2:0] mux_cmd;
wire mux_cmd_wren;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n;
wire mux_ctl_wren;
wire [1:0] mux_cas_slot;
wire [5:0] mux_data_offset;
wire [5:0] mux_data_offset_1;
wire [5:0] mux_data_offset_2;
wire [nCK_PER_CLK-1:0] mux_ras_n;
wire [nCK_PER_CLK-1:0] mux_cas_n;
wire [1:0] mux_rank_cnt;
wire mux_reset_n;
wire [nCK_PER_CLK-1:0] mux_we_n;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata;
wire [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask;
wire mux_wrdata_en;
wire [nCK_PER_CLK-1:0] mux_cke ;
wire [1:0] mux_odt ;
wire phy_if_empty_def;
wire phy_if_reset;
wire phy_init_data_sel;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_map;
wire phy_rddata_valid_w;
reg rddata_valid_reg;
reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_reg;
wire [4:0] idelaye2_init_val;
wire [5:0] oclkdelay_init_val;
wire po_counter_load_en;
//***************************************************************************
assign dbg_rddata_valid = rddata_valid_reg;
assign dbg_rddata = rd_data_reg;
assign dbg_rd_data_offset = calib_rd_data_offset_0;
assign dbg_pi_phaselocked_done = pi_phase_locked_all;
assign dbg_po_counter_read_val = po_counter_read_val;
assign dbg_pi_counter_read_val = pi_counter_read_val;
//***************************************************************************
genvar i;
generate
for (i = 0; i < CK_WIDTH; i = i+1) begin: clock_gen
assign ddr_ck[i] = ddr_clk[LP_DDR_CK_WIDTH * i];
assign ddr_ck_n[i] = ddr_clk[(LP_DDR_CK_WIDTH * i) + 1];
end
endgenerate
//***************************************************************************
// During memory initialization and calibration the calibration logic drives
// the memory signals. After calibration is complete the memory controller
// drives the memory signals.
// Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps
//***************************************************************************
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_temp ;
genvar v ;
generate
if((REG_CTRL == "ON") && (DRAM_TYPE == "DDR3") && (RANKS == 1) && (nCS_PER_RANK ==2)) begin : cs_rdimm
for(v = 0 ; v < CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK ; v = v+1 ) begin
if((v%(CS_WIDTH*nCS_PER_RANK)) == 0) begin
assign mc_cs_n_temp[v] = mc_cs_n[v] ;
end else begin
assign mc_cs_n_temp[v] = 'b1 ;
end
end
end else begin
assign mc_cs_n_temp = mc_cs_n ;
end
endgenerate
assign mux_wrdata = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata : phy_wrdata;
assign mux_wrdata_mask = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_mask : 'b0;
assign mux_address = (phy_init_data_sel | init_wrcal_complete) ? mc_address : phy_address;
assign mux_bank = (phy_init_data_sel | init_wrcal_complete) ? mc_bank : phy_bank;
assign mux_cs_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cs_n_temp : phy_cs_n;
assign mux_ras_n = (phy_init_data_sel | init_wrcal_complete) ? mc_ras_n : phy_ras_n;
assign mux_cas_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_n : phy_cas_n;
assign mux_we_n = (phy_init_data_sel | init_wrcal_complete) ? mc_we_n : phy_we_n;
assign mux_reset_n = (phy_init_data_sel | init_wrcal_complete) ? mc_reset_n : phy_reset_n;
assign mux_aux_out = (phy_init_data_sel | init_wrcal_complete) ? mc_aux_out0 : calib_aux_out;
assign mux_odt = (phy_init_data_sel | init_wrcal_complete) ? mc_odt : calib_odt ;
assign mux_cke = (phy_init_data_sel | init_wrcal_complete) ? mc_cke : calib_cke ;
assign mux_cmd_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd_wren :
calib_cmd_wren;
assign mux_ctl_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_ctl_wren :
calib_ctl_wren;
assign mux_wrdata_en = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_en :
calib_wrdata_en;
assign mux_cmd = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd : calib_cmd;
assign mux_cas_slot = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_slot : calib_cas_slot;
assign mux_data_offset = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset :
calib_data_offset_0;
assign mux_data_offset_1 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_1 :
calib_data_offset_1;
assign mux_data_offset_2 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_2 :
calib_data_offset_2;
// Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601
assign mux_rank_cnt = 2'b00;
// Assigning cke & odt for DDR2 & DDR3
// No changes for DDR3 & DDR2 dual rank
// DDR2 single rank systems might potentially need 3 odt signals.
// Aux_out[2] will have the odt toggled by phy and controller
// wiring aux_out[2] to 0 & 3. Depending upon the odt parameter
// all of the three odt bits or some of them might be used.
// mapping done in mc_phy_wrapper module
generate
if(CKE_ODT_AUX == "TRUE") begin
assign aux_out_map = ((DRAM_TYPE == "DDR2") && (RANKS == 1)) ?
{mux_aux_out[1],mux_aux_out[1],mux_aux_out[1],mux_aux_out[0]} :
mux_aux_out;
end else begin
assign aux_out_map = 4'b0000 ;
end
endgenerate
assign init_calib_complete = phy_init_data_sel;
assign phy_mc_ctl_full = phy_ctl_full;
assign phy_mc_cmd_full = phy_cmd_full;
assign phy_mc_data_full = phy_pre_data_a_full;
//***************************************************************************
// Generate parity for DDR3 RDIMM.
//***************************************************************************
generate
if ((DRAM_TYPE == "DDR3") && (REG_CTRL == "ON")) begin: gen_ddr3_parity
if (nCK_PER_CLK == 4) begin
always @(posedge clk) begin
parity[0] <= #TCQ (^{mux_address[(ROW_WIDTH*4)-1:ROW_WIDTH*3],
mux_bank[(BANK_WIDTH*4)-1:BANK_WIDTH*3],
mux_cas_n[3], mux_ras_n[3], mux_we_n[3]});
end
always @(*) begin
parity[1] = (^{mux_address[ROW_WIDTH-1:0], mux_bank[BANK_WIDTH-1:0],
mux_cas_n[0],mux_ras_n[0], mux_we_n[0]});
parity[2] = (^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH],
mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH],
mux_cas_n[1], mux_ras_n[1], mux_we_n[1]});
parity[3] = (^{mux_address[(ROW_WIDTH*3)-1:ROW_WIDTH*2],
mux_bank[(BANK_WIDTH*3)-1:BANK_WIDTH*2],
mux_cas_n[2],mux_ras_n[2], mux_we_n[2]});
end
end else begin
always @(posedge clk) begin
parity[0] <= #TCQ(^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH],
mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH],
mux_cas_n[1], mux_ras_n[1], mux_we_n[1]});
end
always @(*) begin
parity[1] = (^{mux_address[ROW_WIDTH-1:0],
mux_bank[BANK_WIDTH-1:0],
mux_cas_n[0], mux_ras_n[0], mux_we_n[0]});
end
end
end else begin: gen_ddr3_noparity
if (nCK_PER_CLK == 4) begin
always @(posedge clk) begin
parity[0] <= #TCQ 1'b0;
parity[1] <= #TCQ 1'b0;
parity[2] <= #TCQ 1'b0;
parity[3] <= #TCQ 1'b0;
end
end else begin
always @(posedge clk) begin
parity[0] <= #TCQ 1'b0;
parity[1] <= #TCQ 1'b0;
end
end
end
endgenerate
//***************************************************************************
// Code for optional register stage in read path to MC for timing
//***************************************************************************
generate
if(RD_PATH_REG == 1)begin:RD_REG_TIMING
always @(posedge clk)begin
rddata_valid_reg <= #TCQ phy_rddata_valid_w;
rd_data_reg <= #TCQ rd_data_map;
end // always @ (posedge clk)
end else begin : RD_REG_NO_TIMING // block: RD_REG_TIMING
always @(phy_rddata_valid_w or rd_data_map)begin
rddata_valid_reg = phy_rddata_valid_w;
rd_data_reg = rd_data_map;
end
end
endgenerate
assign phy_rddata_valid = rddata_valid_reg;
assign phy_rd_data = rd_data_reg;
//***************************************************************************
// Hard PHY and accompanying bit mapping logic
//***************************************************************************
mig_7series_v2_0_ddr_mc_phy_wrapper #
(
.TCQ (TCQ),
.tCK (tCK),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.BANK_WIDTH (BANK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.CS_WIDTH (CS_WIDTH),
.CK_WIDTH (CK_WIDTH),
.LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.CWL (CWL),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.REG_CTRL (REG_CTRL),
.ROW_WIDTH (ROW_WIDTH),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.HIGHEST_BANK (HIGHEST_BANK),
.HIGHEST_LANE (HIGHEST_LANE),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.MASTER_PHY_CTL (MASTER_PHY_CTL)
)
u_ddr_mc_phy_wrapper
(
.rst (rst),
.clk (clk),
// For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk
// For memory frequencies below 400 MHz mem_refclk = mem_refclk and
// freq_refclk = 2x or 4x mem_refclk such that it remains in the
// 400~1066 MHz range
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.idelayctrl_refclk (clk_ref),
.phy_cmd_wr_en (mux_cmd_wren),
.phy_data_wr_en (mux_wrdata_en),
// phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23],
// DataOffset[22:17],HiIndex[16:15],LowIndex[14:12],
// AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]}
// The fields ACTPRE, and BankCount are only used
// when the hard PHY counters are used by the MC.
.phy_ctl_wd ({5'd0, mux_cas_slot, calib_seq, mux_data_offset,
mux_rank_cnt, 3'd0, aux_out_map,
5'd0, mux_cmd}),
.phy_ctl_wr (mux_ctl_wren),
.phy_if_empty_def (phy_if_empty_def),
.phy_if_reset (phy_if_reset),
.data_offset_1 (mux_data_offset_1),
.data_offset_2 (mux_data_offset_2),
.aux_in_1 (aux_out_map),
.aux_in_2 (aux_out_map),
.idelaye2_init_val (idelaye2_init_val),
.oclkdelay_init_val (oclkdelay_init_val),
.if_empty (if_empty),
.phy_ctl_full (phy_ctl_full),
.phy_cmd_full (phy_cmd_full),
.phy_data_full (phy_data_full),
.phy_pre_data_a_full (phy_pre_data_a_full),
.ddr_clk (ddr_clk),
.phy_mc_go (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.po_fine_enable (po_enstg2_f),
.po_coarse_enable (po_enstg2_c),
.po_fine_inc (po_stg2_fincdec),
.po_coarse_inc (po_stg2_cincdec),
.po_counter_load_en (po_counter_load_en),
.po_counter_read_en (1'b1),
.po_sel_fine_oclk_delay (po_sel_stg2stg3),
.po_counter_load_val (),
.po_counter_read_val (po_counter_read_val),
.pi_rst_dqs_find (rst_stg1_cal),
.pi_fine_enable (pi_enstg2_f),
.pi_fine_inc (pi_stg2_fincdec),
.pi_counter_load_en (pi_stg2_load),
.pi_counter_load_val (pi_stg2_reg_l),
.pi_counter_read_val (pi_counter_read_val),
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.idelay_ld (idelay_ld),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (pi_found_dqs),
.pi_dqs_found_all (pi_dqs_found_all),
// Currently not being used. May be used in future if periodic reads
// become a requirement. This output could also be used to signal a
// catastrophic failure in read capture and the need for re-cal
.pi_dqs_out_of_range (pi_dqs_out_of_range),
.phy_init_data_sel (phy_init_data_sel),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.mux_address (mux_address),
.mux_bank (mux_bank),
.mux_cs_n (mux_cs_n),
.mux_ras_n (mux_ras_n),
.mux_cas_n (mux_cas_n),
.mux_we_n (mux_we_n),
.mux_reset_n (mux_reset_n),
.parity_in (parity),
.mux_wrdata (mux_wrdata),
.mux_wrdata_mask (mux_wrdata_mask),
.mux_odt (mux_odt),
.mux_cke (mux_cke),
.idle (idle),
.rd_data (rd_data_map),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_parity (ddr_parity),
.ddr_ras_n (ddr_ras_n),
.ddr_we_n (ddr_we_n),
.ddr_dq (ddr_dq),
.ddr_dqs (ddr_dqs),
.ddr_dqs_n (ddr_dqs_n),
.ddr_reset_n (ddr_reset_n),
.dbg_pi_counter_read_en (1'b1),
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes)
);
//***************************************************************************
// Soft memory initialization and calibration logic
//***************************************************************************
mig_7series_v2_0_ddr_calib_top #
(
.TCQ (TCQ),
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
.nCK_PER_CLK (nCK_PER_CLK),
.PRE_REV3ES (PRE_REV3ES),
.tCK (tCK),
.CLK_PERIOD (CLK_PERIOD),
.N_CTL_LANES (N_CTL_LANES),
.CTL_BYTE_LANE (CTL_BYTE_LANE),
.CTL_BANK (CTL_BANK),
.DRAM_TYPE (DRAM_TYPE),
.PRBS_WIDTH (8),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.HIGHEST_BANK (HIGHEST_BANK),
.BANK_TYPE (BANK_TYPE),
.HIGHEST_LANE (HIGHEST_LANE),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.BANK_WIDTH (BANK_WIDTH),
.CA_MIRROR (CA_MIRROR),
.COL_WIDTH (COL_WIDTH),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nCS_PER_RANK (nCS_PER_RANK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANKS (RANKS),
.CS_WIDTH (CS_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.PER_BIT_DESKEW ("OFF"),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.AL (AL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.nCL (CL),
.nCWL (CWL),
.tRFC (tRFC),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.WRLVL (WRLVL_W),
.USE_ODT_PORT (USE_ODT_PORT),
.SIM_INIT_OPTION (SIM_INIT_OPTION),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DEBUG_PORT (DEBUG_PORT)
)
u_ddr_calib_top
(
.clk (clk),
.rst (rst),
.tg_err (error),
.rst_tg_mc (rst_tg_mc),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
// PHY Control Block and IN_FIFO status
.phy_ctl_ready (phy_mc_go),
.phy_ctl_full (1'b0),
.phy_cmd_full (1'b0),
.phy_data_full (1'b0),
.phy_if_empty (if_empty),
.idelaye2_init_val (idelaye2_init_val),
.oclkdelay_init_val (oclkdelay_init_val),
// From calib logic To data IN_FIFO
// DQ IDELAY tap value from Calib logic
// port to be added to mc_phy by Gary
.dlyval_dq (),
// hard PHY calibration modes
.write_calib (phy_write_calib),
.read_calib (phy_read_calib),
// DQS count and ck/addr/cmd to be mapped to calib_sel
// based on parameter that defines placement of ctl lanes
// and DQS byte groups in each bank. When phy_write_calib
// is de-asserted calib_sel should select CK/addr/cmd/ctl.
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.phy_if_empty_def (phy_if_empty_def),
.phy_if_reset (phy_if_reset),
// Signals from calib logic to be MUXED with MC
// signals before sending to hard PHY
.calib_ctl_wren (calib_ctl_wren),
.calib_cmd_wren (calib_cmd_wren),
.calib_seq (calib_seq),
.calib_aux_out (calib_aux_out),
.calib_odt (calib_odt),
.calib_cke (calib_cke),
.calib_cmd (calib_cmd),
.calib_wrdata_en (calib_wrdata_en),
.calib_rank_cnt (calib_rank_cnt),
.calib_cas_slot (calib_cas_slot),
.calib_data_offset_0 (calib_data_offset_0),
.calib_data_offset_1 (calib_data_offset_1),
.calib_data_offset_2 (calib_data_offset_2),
.phy_reset_n (phy_reset_n),
.phy_address (phy_address),
.phy_bank (phy_bank),
.phy_cs_n (phy_cs_n),
.phy_ras_n (phy_ras_n),
.phy_cas_n (phy_cas_n),
.phy_we_n (phy_we_n),
.phy_wrdata (phy_wrdata),
// DQS Phaser_IN calibration/status signals
.pi_phaselocked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_found_dqs (pi_found_dqs),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.pi_rst_stg1_cal (rst_stg1_cal),
.pi_en_stg2_f (pi_enstg2_f),
.pi_stg2_f_incdec (pi_stg2_fincdec),
.pi_stg2_load (pi_stg2_load),
.pi_stg2_reg_l (pi_stg2_reg_l),
.pi_counter_read_val (pi_counter_read_val),
.device_temp (device_temp),
.tempmon_sample_en (tempmon_sample_en),
// IDELAY tap enable and inc signals
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.idelay_ld (idelay_ld),
// DQS Phaser_OUT calibration/status signals
.po_sel_stg2stg3 (po_sel_stg2stg3),
.po_stg2_c_incdec (po_stg2_cincdec),
.po_en_stg2_c (po_enstg2_c),
.po_stg2_f_incdec (po_stg2_fincdec),
.po_en_stg2_f (po_enstg2_f),
.po_counter_load_en (po_counter_load_en),
.po_counter_read_val (po_counter_read_val),
// From data IN_FIFO To Calib logic and MC/UI
.phy_rddata (rd_data_map),
// From calib logic To MC
.phy_rddata_valid (phy_rddata_valid_w),
.calib_rd_data_offset_0 (calib_rd_data_offset_0),
.calib_rd_data_offset_1 (calib_rd_data_offset_1),
.calib_rd_data_offset_2 (calib_rd_data_offset_2),
.calib_writes (),
// Mem Init and Calibration status To MC
.init_calib_complete (phy_init_data_sel),
.init_wrcal_complete (init_wrcal_complete),
// Debug Error signals
.pi_phase_locked_err (dbg_pi_phaselock_err),
.pi_dqsfound_err (dbg_pi_dqsfound_err),
.wrcal_err (dbg_wrcal_err),
// Debug Signals
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_calib_top (dbg_calib_top),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done)
);
endmodule
|
module fifo(
input w_clk,
input r_clk,
input we,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [15 :0] mask,
output [DATA_WIDTH - 1 : 0] q,
output empty,
output full
);
parameter DATA_WIDTH = 1;
parameter ASYNC = 0;
wire [15:0] _d, _q;
genvar i;
generate
if (DATA_WIDTH <= 16 & DATA_WIDTH > 8)
begin
assign _d = { {(16 - DATA_WIDTH){1'b0}}, {d} };
assign q = { {(16 - DATA_WIDTH){1'b0}}, {_q} };
fifo_#(
.MODE(0),
.ADDR_WIDTH(8),
.ASYNC(ASYNC)
) fifo_256x16_(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(mask) // only masked option
);
end // if (16 >= DATA_WIDTH > 8)
else if ( DATA_WIDTH <= 8 & DATA_WIDTH > 4)
begin
for (i = 0; i < 8; i=i+1)
begin
assign _d[i * 2 + 1] = 1'b0;
assign _d[i * 2] = i < DATA_WIDTH ? d[i] : 1'b0;
if (i < DATA_WIDTH)
begin
assign q[i] = _q[i * 2];
end
end
fifo_#(
.MODE(1),
.ADDR_WIDTH(9),
.ASYNC(ASYNC)
) fifo_512x8(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(16'b0)
);
end // if ( 8 >= DATA_WIDTH > 4)
else if ( DATA_WIDTH <= 4 & DATA_WIDTH > 2)
begin
for (i = 0; i < 4; i=i+1)
begin
assign _d[i * 4 + 0] = 1'b0;
assign _d[i * 4 + 1] = i < DATA_WIDTH ? d[i] : 1'b0;
assign _d[i * 4 + 2] = 1'b0;
assign _d[i * 4 + 3] = 1'b0;
if (i < DATA_WIDTH)
begin
assign q[i] = _q[i * 4 + 1];
end
end
fifo_#(
.MODE(2),
.ADDR_WIDTH(10),
.ASYNC(ASYNC)
) fifo_1024x4(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(16'b0)
);
end // if ( 4 >= DATA_WIDTH > 2)
else if ( DATA_WIDTH <= 2 & DATA_WIDTH > 0)
begin
for (i = 0; i < 2; i=i+1)
begin
assign _d[i * 8 + 2 : i * 8] = 0;
assign _d[i * 8 + 3] = i < DATA_WIDTH ? d[i] : 1'b0;
assign _d[i * 8 + 7 : i * 8 + 4] = 0;
if (i < DATA_WIDTH)
begin
assign q[i] = _q[i * 8 + 3];
end
end
fifo_#(
.MODE(3),
.ADDR_WIDTH(11),
.ASYNC(ASYNC)
) fifo_2048x2(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(16'b0)
);
end // if ( 2 >= DATA_WIDTH > 0)
endgenerate
endmodule // fifo
module fifo_(
input w_clk,
input r_clk,
input we,
input [RAM_DATA_WIDTH - 1 : 0] d,
input re,
input [RAM_DATA_WIDTH - 1 :0] mask,
output [RAM_DATA_WIDTH - 1 : 0] q,
output empty,
output full
);
function [ADDR_WIDTH :0] bin_to_gray;
input [ADDR_WIDTH :0] bin;
bin_to_gray = (bin >> 1) ^ bin;
endfunction // bin_to_gray
parameter MODE = 0;
parameter ADDR_WIDTH = 0;
parameter ASYNC = 0;
localparam RAM_ADDR_WIDTH = 11;
localparam RAM_DATA_WIDTH = 16;
reg [ADDR_WIDTH - 1 : 0] raddr = 0, waddr = 0;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
SB_RAM40_4K #(
.WRITE_MODE(MODE),
.READ_MODE(MODE)
) bram (
.RDATA(q),
.RADDR(_raddr),
.RCLK(r_clk),
.RCLKE(1'b1),
.RE(re),
.WADDR(_waddr),
.WCLK(w_clk),
.WCLKE(1'b1),
.WDATA(d),
.WE(we),
.MASK(mask)
);
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
always @ (posedge w_clk)
begin
if (we & ~full)
begin
waddr <= waddr + 1;
end
end
always @ (posedge r_clk)
begin
if (re & ~empty)
begin
raddr <= raddr + 1;
end
end
generate
if (ASYNC)
begin : async_ctrs
reg _full = 0, _empty = 1;
reg [ADDR_WIDTH : 0] wptr = 0, rptr = 0;
reg [ADDR_WIDTH : 0] rq1_wptr = 0, rq2_wptr = 0;
reg [ADDR_WIDTH : 0] wq1_rptr = 0, wq2_rptr = 0;
wire [ADDR_WIDTH : 0] _wptr, _rptr;
assign _wptr = bin_to_gray(waddr + (we & ~full));
assign _rptr = bin_to_gray(raddr + (re & ~empty));
assign full = _full;
assign empty = _empty;
always @ (posedge w_clk)
begin
wptr <= _wptr;
_full <= (_wptr ==
{~wq2_rptr[ADDR_WIDTH:ADDR_WIDTH-1], wq2_rptr[ADDR_WIDTH-2:0]});
end
always @ (posedge r_clk)
begin
_empty <= (_rptr == rq2_wptr);
rptr <= _rptr;
end
always @ (posedge w_clk)
begin
wq1_rptr <= rptr;
wq2_rptr <= wq1_rptr;
end
always @ (posedge r_clk)
begin
rq1_wptr <= wptr;
rq2_wptr <= rq1_wptr;
end
end // if (ASYNC)
else
begin : sync_ctrs
reg [ADDR_WIDTH - 1 : 0] ctr = 0;
assign full = &ctr;
assign empty = ~&ctr;
always @ (posedge w_clk)
begin
if (we & ~re & ~full)
begin
ctr <= ctr + 1;
end
else if(re & ~we & ~empty)
begin
ctr <= ctr - 1;
end
end // always @ (posedge w_clk)
end // else: !if(ASYNC)
endgenerate
endmodule // fifo_
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_req_ack_unique (clock, reset, enable, req, ack, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter min_cks = 1;
parameter max_cks = 15;
parameter method = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input req, ack;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_REQ_ACK_UNIQUE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_req_ack_unique_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_req_ack_unique
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__AND3_PP_BLACKBOX_V
/**
* and3: 3-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
`include "Defintions.v"
module MiniAlu
(
input wire Clock,
input wire Reset,
input wire PS2_CLK,
input wire PS2_DATA,
output wire [7:0] oLed
);
wire [15:0] wIP,wIP_temp,IMUL_Result;
wire [7:0] imul_result;
reg Subroutine_Flag;
reg Return_Flag;
wire [15:0] wReturn_Sub;
reg rWriteEnable,rBranchTaken;
wire [27:0] wInstruction;
wire [3:0] wOperation;
reg signed [32:0] rResult;
wire [7:0] KeyCode,wKeyCode;
wire KeyCodeReady;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination;
wire signed [15:0] wSourceData0,wSourceData1,wImmediateValue;
wire [15:0] wIPInitialValue;
wire [15:0] oIMUL2;
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wInstruction[7:0] ),
.iReadAddress1( wInstruction[15:8] ),
.iWriteAddress( wDestination ),
.iDataIn( rResult ),
.oDataOut0( wSourceData0 ),
.oDataOut1( wSourceData1 )
);
assign wIPInitialValue = (Reset) ? 8'b0 : (Return_Flag? wReturn_Sub:wDestination);
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
assign wIP = (rBranchTaken) ? (Return_Flag? wReturn_Sub:wIPInitialValue): wIP_temp;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( KeyCodeReady ),
.D( wKeyCode ),
.Q( oLed )
);
//***************************** FFD Subroutine **********************************
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FFDSub
(
.Clock(Subroutine_Flag),
.Reset(Reset),
.Enable(1'b1),
.D(wIP_temp),
.Q(wReturn_Sub)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FFDKEy
(
.Clock(Clock),
.Reset(Reset),
.Enable(KeyCodeReady),
.D(KeyCode),
.Q(wKeyCode)
);
KeyBoard_Controller KBC
(
.Clk(PS2_CLK),
.Data(PS2_DATA),
.reset(Reset),
.Parallel_data(KeyCode),
.Sent(KeyCodeReady)
);
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 + wSourceData0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
`SUB:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 - wSourceData0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
`SMUL:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 * wSourceData0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
rResult <= wImmediateValue;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
end
//-------------------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
`CALL:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b1;
rWriteEnable <= 1'b0;
Subroutine_Flag <=1'b1;
Return_Flag <=1'b0;
rResult <= 0;
end
//-------------------------------------
`RET:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b1;
rWriteEnable <= 1'b0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b1;
rResult <= 0;
end
//-------------------------------------
`BRANCH_IF_KB:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
if (KeyCodeReady)
rBranchTaken <= 1'b0;
else
rBranchTaken <= 1'b1;
end
//-------------------------------------
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
endcase
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:42:00 06/18/2014
// Design Name: timer_counter
// Module Name: F:/ISE/work/final_exp/washing_machine/timer_counter_test.v
// Project Name: washing_machine
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: timer_counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module timer_counter_test;
// Inputs
reg CP;
reg [7:0] RS;
// Outputs
wire [7:0] Q;
wire QCC;
parameter PERIOD = 10;
// Instantiate the Unit Under Test (UUT)
timer_counter uut (
.CP(CP),
.RS(RS),
.Q(Q),
.QCC(QCC)
);
always begin
CP = 1;
#(PERIOD/2);
CP = 0;
#(PERIOD/2);
end
initial begin
// Initialize Inputs
CP = 0;
RS = 8'b00010101;
// Wait 100 ns for global reset to finish
#300;
RS = 8'b00110001;
// Add stimulus here
end
endmodule
|
// synthesis VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
//
// This file is part of multiexp-a5gx.
//
// multiexp-a5gx is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see http://www.gnu.org/licenses/.
module multiexp_top #( parameter fifo_widthu = 11
, parameter n_mult = 1
)
( input clk
, input pcie_perstn
, input pcie_ready
, input user_resetn
, input pll_core_locked
, output ctrl_reset_n
, input [31:0] fifo_datai
, input fifo_empty
, output fifo_rden
, input [fifo_widthu:0] fifo_usedw_in
, input pcie_writing
, output [31:0] fifo_datao
, output fifo_wren
, input [fifo_widthu:0] fifo_usedw_out
, output [3:0] status_leds
// memory interface i/o (pin directly from toplevel)
, output [12:0] ddr3_a // memory.mem_a
, output [2:0] ddr3_ba // .mem_ba
, output ddr3_ck_p // .mem_ck
, output ddr3_ck_n // .mem_ck_n
, output ddr3_cke // .mem_cke
, output ddr3_csn // .mem_cs_n
, output [3:0] ddr3_dm // .mem_dm
, output ddr3_rasn // .mem_ras_n
, output ddr3_casn // .mem_cas_n
, output ddr3_wen // .mem_we_n
, output ddr3_rstn // .mem_reset_n
, inout [31:0] ddr3_dq // .mem_dq
, inout [3:0] ddr3_dqs_p // .mem_dqs
, inout [3:0] ddr3_dqs_n // .mem_dqs_n
, output ddr3_odt // .mem_odt
, input ddr3_oct_rzq // oct.rzqin
, input clkin_100_p
);
/* *** HOST INTERFACE COMMANDS ***
MSB LSB
LOAD_ERAM 000001 _ _____ ____________________
| | | |
command field (6'b000001) -------------------| | | |
load previous result from dram? (1 bit) -------| | |
e_ram select (5 bits) -------------------------------| |
d_ram address of corresponding result (20 bits) ---------------------------
This command should be followed by e_words * c_size words of the
exponents in LSB->MSB order, in order corresponding to the TRAM
values (i.e., the first exponent should correspond to TRAM address
0, first base, the next to the TRAM address 0, second base, etc.)
NOTE that when the load_result bit is 0, the controller will preload {'0,1'b1}
instead of a value from RAM.
When this command is finished, the controller responds with {4'h1,28'b0}.
SET_ADDR 000010 _ _____ ____________________
| | | |
command field (6'b000001) -------------------| | | |
load previous result from dram? (1 bit) -------| | |
e_ram select (5 bits) -------------------------------| |
d_ram address (20 bits) ---------------------------------------------------
This command behaves much like LOAD_ERAM, except that it does not actually
update the e_ram. It should be used when a multiplier does not need to be
used in the next sequence of executions; the user should write an address
to this multiplier such that next time its contents are written to dram
(e.g., as the result of SET_ADDR or LOAD_ERAM) they do not overwrite a
useful result. (One possibility is to set aside address 2^20-1 for this
purpose.)
When this command is finished, the controller responds with {4'h2,28'b0}.
LOAD_TRAM 000100 ___________ _______________
| | |
command field (6'b000010) -------------------| | |
unused (11 bits) ----------------------------------------| |
tram start address (15 bits) --------------------------------------------|
This command should be followed by 2 * n_words words of table values.
The system computes the third table value and writes it to the table automatically.
Note that alignment of the address is not checked, so the host must be
sure to give an address correctly aligned to n_words!
When this command is finished, the controller responds with {4'h3,28'b0}.
READ_RESULT 001000 ______ ____________________
| | |
command field (6'b000100) -------------------| | |
unused (6 bits) ------------------------------------| |
d_ram address of result to read (20 bits) -------------------------------|
Reads n_words of a result out of DRAM.
The controller responds with {4'h4,8'(n_words),address} followed by n_words of result.
START_MULTIPLICATION 100000 __________________________
| |
command field (6'b010000) -------------------| |
unused (26 bits) -------------------------------------------------------|
A chunk of expmod batches. In other words, executes 16 * e_words * c_size
multiplications and 32 * e_words - 1 squarings in each multiplier.
When this command is finished, the controller responds with {4'h6,28'b0}.
*/
// for now, these can't really be parameterized at this level.
// Changes to allow full parameterization are pretty minor, though.
localparam n_words = 40;
localparam e_words = 4;
localparam c_size = 1024;
localparam gbits = 9;
localparam ebits = 7;
reg [6:0] dcmd_reg, dcmd_next;
wire [4:0] d_unitsel;
wire [8:0] d_g_addr;
wire d_g_rden, d_g_wren;
wire [26:0] d_g_data;
wire d_idle;
wire d_active;
reg [4:0] unit_reg, unit_next;
wire [4:0] unit_select = d_active ? d_unitsel : unit_reg;
reg [8:0] g_addr_reg, g_addr_next;
wire [8:0] g_addr = d_active ? d_g_addr : g_addr_reg;
reg g_rden_reg, g_rden_next, g_wren_reg, g_wren_next;
wire g_rden = d_active ? d_g_rden : g_rden_reg;
wire g_wren = d_active ? d_g_wren : g_wren_reg;
reg [26:0] g_data_reg, g_data_next;
wire [26:0] g_data = d_active ? d_g_data : g_data_reg;
reg [14:0] address_reg, address_next;
wire [26:0] t_datai = g_data_reg;
wire [14:0] t_wraddr = address_reg;
reg [2:0] t_wren_reg, t_wren_next;
wire [26:0] tdata_0, tdata_1, tdata_2;
wire t_idle;
reg [1:0] tcmd_reg, tcmd_next;
wire [n_mult-1:0] m_idle;
reg [2:0] mcmd_reg, mcmd_next;
// no tristate busses allowed inside the FPGA; we must mux
wire [26:0] m_g_q[n_mult-1:0];
reg [26:0] g_q;
always_comb begin
if (unit_select < n_mult) begin
g_q = m_g_q[unit_select];
end else begin
g_q = '0;
end
end
wire [31:0] e_data, e_q;
wire [11:0] e_addr;
reg e_wren_reg, e_wren_next;
assign e_data = fifo_datai;
assign e_addr = {~address_reg[1:0],address_reg[11:2]};
/* e_addr explanation:
we are getting a stream of data from the host
0:LSB . . MSB
1:LSB . . MSB
...
What we want is to be able to scan through these like this
MSB0 MSB1 MSB2 ... (M-1)SB0 (M-1)SB1 (M-1)SB2 ...
So the LSB of the first word wants to go at address 3*1024
The next byte of the 1st word wants to go at address 2*1024
The next byte of the 1st word wants to go at address 1*1024
Then the MSB of the 1st word wants to go at address 0*1024
If address is counting up naturally, then it goes {'0,2'b00}, {'0,2'b01}, {'0,2b'10}, {'0,2'b11}
If we invert the lsbits of address, then we get 11, 10, 01, 00, which are the multiples of 1024
we want. Thus, we use the bottom two bits as the "bank select," and the top bits as the address.
This gets us the memory layout we want for the e_rams.
*/
reg [2:0] state_reg, state_next;
`include "mult_commands.vh"
localparam ST_IDLE = 3'b000;
localparam ST_INTERPRET = 3'b001;
localparam ST_LOAD_ERAM = 3'b010;
localparam ST_LOAD_TRAM = 3'b011;
localparam ST_READ_RESULT = 3'b100;
localparam ST_START_MULT = 3'b110;
localparam CMD_LOAD_ERAM = 6'b000001;
localparam CMD_SET_ADDR = 6'b000010;
localparam CMD_LOAD_TRAM = 6'b000100;
localparam CMD_READ_RESULT = 6'b001000;
localparam CMD_START_MULT = 6'b100000;
localparam CMD_D_GRAM2DRAM = 2'b10;
localparam CMD_D_DRAM2GRAM = 2'b11;
localparam CMD_D_BLANKGRAM = 2'b01;
localparam CMD_T_START = 2'b01;
localparam CMD_T_RESET = 2'b10;
localparam CMD_T_ABORT = 2'b11;
localparam CMD_M_RSTCOUNT = 3'b111;
wire inST_IDLE = state_reg == ST_IDLE;
wire inST_INTERPRET = state_reg == ST_INTERPRET;
wire inST_LOAD_ERAM = state_reg == ST_LOAD_ERAM;
wire inST_LOAD_TRAM = state_reg == ST_LOAD_TRAM;
wire inST_READ_RESULT = state_reg == ST_READ_RESULT;
wire inST_START_MULT = state_reg == ST_START_MULT;
reg [31:0] fifo_datao_reg, fifo_datao_next;
reg fifo_rden_reg, fifo_rden_next, fifo_wren_reg, fifo_wren_next;
reg loadprev_reg, loadprev_next;
assign fifo_datao = fifo_datao_reg;
assign fifo_rden = fifo_rden_reg;
assign fifo_wren = fifo_wren_reg;
wire [5:0] command_in = fifo_datai[31:26];
wire fifo_full = fifo_usedw_out[fifo_widthu];
assign d_active = (d_g_rden | d_g_wren) & ~inST_READ_RESULT;
wire rfifo_has_40 = fifo_usedw_in > (n_words - 1);
wire wfifo_has_space = (fifo_usedw_out + n_words + 1) < (1 << fifo_widthu);
wire load_eram_last = address_reg[11:0] == {12{1'b1}};
wire load_eram_alast = address_reg[11:0] == {{11{1'b1}},1'b0};
wire load_tram_tlast = g_addr_reg[5:0] == (n_words + 1);
wire load_tram_last = g_addr_reg[5:0] == (n_words - 1);
wire load_tram_aalast = g_addr_reg[5:0] == (n_words - 3);
wire load_tram_mstart = g_addr_reg[5:0] == 6'd1;
reg delay_reg, delay_next;
wire m_idle_all = m_idle == {n_mult{1'b1}};
wire square_time = address_reg[gbits-1:0] == {gbits{1'b1}};
wire fmult_time = g_addr_reg[ebits-1:0] == {ebits{1'b1}};
assign status_leds = {~m_idle_all, ~inST_START_MULT, ~inST_LOAD_ERAM, ~inST_LOAD_TRAM};
always_comb begin
dcmd_next = dcmd_reg;
unit_next = unit_reg;
g_addr_next = g_addr_reg;
g_rden_next = g_rden_reg;
g_wren_next = g_wren_reg;
g_data_next = g_data_reg;
t_wren_next = t_wren_reg;
tcmd_next = tcmd_reg;
mcmd_next = mcmd_reg;
e_wren_next = e_wren_reg;
state_next = state_reg;
address_next = address_reg;
fifo_datao_next = fifo_datao_reg;
fifo_rden_next = fifo_rden_reg;
fifo_wren_next = fifo_wren_reg;
loadprev_next = loadprev_reg;
delay_next = '0;
case (state_reg)
ST_IDLE: begin
dcmd_next = '0;
g_addr_next = '0;
g_rden_next = '0;
g_wren_next = '0;
g_data_next = '0;
t_wren_next = '0;
tcmd_next = '0;
mcmd_next = '0;
e_wren_next = '0;
state_next = ST_IDLE;
address_next = '0;
fifo_datao_next = '0;
fifo_rden_next = '1;
fifo_wren_next = '0;
loadprev_next = '0;
delay_next = '0;
if (fifo_rden_reg & ~fifo_empty) begin
fifo_rden_next = '0;
state_next = ST_INTERPRET;
end
end
ST_INTERPRET: begin
case (command_in)
CMD_SET_ADDR, CMD_LOAD_ERAM: begin
if (g_rden_reg) begin
g_rden_next = '0;
g_data_next = {7'b0,fifo_datai[19:0]};
g_wren_next = '1;
end else if (g_wren_reg) begin
g_data_next = {7'b0,g_q[19:0]};
g_addr_next = 9'd193;
loadprev_next = fifo_datai[25];
if (command_in == CMD_SET_ADDR) begin
address_next[14] = '1;
end else begin
address_next[14] = '0;
end
state_next = ST_LOAD_ERAM;
end else begin
unit_next = fifo_datai[24:20];
g_addr_next = 9'd192;
g_rden_next = '1;
end
end
CMD_LOAD_TRAM: begin
// spin here, waiting for fifo to be sufficiently full
// such that we will be able to read in everything at
// once
if (rfifo_has_40) begin
address_next = fifo_datai[14:0];
g_addr_next = 9'd64;
fifo_rden_next = '1;
unit_next = '0;
delay_next = '1;
state_next = ST_LOAD_TRAM;
end
end
CMD_READ_RESULT: begin
// block until we have space for the whole thing
if (wfifo_has_space) begin
delay_next = '1;
dcmd_next = {CMD_D_DRAM2GRAM,5'b11100};
state_next = ST_READ_RESULT;
fifo_datao_next = {4'h4,8'(n_words),fifo_datai[19:0]};
fifo_wren_next = '1;
end
end
CMD_START_MULT: begin
if (tcmd_reg == CMD_T_RESET) begin
tcmd_next = CMD_T_START;
mcmd_next = CMD_BEGINMULT;
delay_next = '1;
state_next = ST_START_MULT;
end else begin
// make sure table controller is in the correct state
tcmd_next = CMD_T_RESET;
mcmd_next = CMD_M_RSTCOUNT;
unit_next = 5'b11111;
address_next = '0;
g_addr_next = '0;
loadprev_next = '0;
end
end
default: begin
// I can't do that, Dave.
state_next = ST_IDLE;
end
endcase
end
ST_START_MULT: begin
mcmd_next = '0;
if (tcmd_reg != CMD_T_RESET) begin
tcmd_next = '0;
end
if (fifo_wren_reg) begin
if (~fifo_full) begin
fifo_wren_next = '0;
state_next = ST_IDLE;
end
end else if (~delay_reg & loadprev_reg & m_idle_all) begin
fifo_wren_next = '1;
fifo_datao_next = {4'h6,28'b0};
if (~fifo_full) begin
state_next = ST_IDLE;
end
end else if (~delay_reg & (tcmd_reg == CMD_T_RESET) & m_idle_all) begin
tcmd_next = '0;
if (fmult_time) begin
loadprev_next = '1;
delay_next = '1;
mcmd_next = CMD_STORE;
end else begin
address_next = '0;
g_addr_next = g_addr_reg + 1'b1;
delay_next = '1;
tcmd_next = CMD_T_START;
mcmd_next = CMD_BEGINMULT;
end
end else if (~delay_reg & m_idle_all) begin
if (~t_idle) begin
tcmd_next = CMD_T_ABORT;
delay_next = '1;
end else begin
delay_next = '1;
if (square_time) begin
tcmd_next = CMD_T_RESET;
if (fmult_time) begin
// we're done; chain with previously loaded result
mcmd_next = CMD_BEGINRAMMULT;
end else begin
// square and continue multiplying
mcmd_next = CMD_BEGINSQUARE;
end
end else begin
address_next = address_reg + 1'b1;
tcmd_next = CMD_T_START;
mcmd_next = CMD_BEGINMULT;
end
end
end
end
ST_READ_RESULT: begin
if (delay_reg) begin
dcmd_next = '0;
fifo_wren_next = '0;
end else begin
if (~d_idle) begin
fifo_wren_next = d_g_wren;
fifo_datao_next = {5'b0,d_g_data};
end else begin
fifo_wren_next = '0;
state_next = ST_IDLE;
end
end
end
ST_LOAD_TRAM: begin
if (g_addr_reg[7:6] == 2'b01) begin
// first phase: read in g_0
if (delay_reg) begin
t_wren_next = '0;
g_wren_next = '0;
end else begin
g_data_next = fifo_datai[26:0];
if (fifo_rden_reg | g_wren_reg) begin
// we've gotten here, so we know that the FIFO will
// not be empty before we're done with this phase
g_wren_next = '1;
t_wren_next = 3'b001;
if (g_wren_reg) begin
if (load_tram_aalast) begin
fifo_rden_next = '0;
end
if (load_tram_last) begin
g_wren_next = '0;
t_wren_next = '0;
end else begin
g_addr_next = g_addr_reg + 1'b1;
address_next = address_reg + 1'b1;
end
end
// as we're writing this into memory, read it into the
// result register
if (load_tram_mstart) begin
mcmd_next = CMD_PRELOAD;
end else begin
mcmd_next = '0;
end
end else begin
if (rfifo_has_40) begin
g_addr_next = '0;
address_next = address_reg - 6'd39;
fifo_rden_next = '1;
delay_next = '1;
end
end
end
end else if (g_addr_reg[7:6] == 2'b00) begin
// second phase: read in g_1
if (delay_reg) begin
t_wren_next = '0;
g_wren_next = '0;
end else begin
g_data_next = fifo_datai[26:0];
if (fifo_rden_reg | g_wren_reg) begin
g_wren_next = '1;
t_wren_next = 3'b010;
if (g_wren_reg) begin
if (load_tram_aalast) begin
fifo_rden_next = '0;
end
if (load_tram_last) begin
g_wren_next = '0;
t_wren_next = '0;
end else begin
g_addr_next = g_addr_reg + 1'b1;
address_next = address_reg + 1'b1;
end
end
// as we're writing this into memory, start
// multiplication
if (load_tram_mstart) begin
mcmd_next = CMD_BEGINRAMMULT;
end else begin
mcmd_next = '0;
end
end else begin
if (m_idle[0]) begin
// multiplication is finished; read out result
mcmd_next = CMD_STORE;
g_addr_next = 9'b110111110;
address_next = address_reg - 6'd39;
end
end
end
end else if (fifo_wren_reg) begin
// block here until the write fifo is clear to write back
// the response to the host
if (~fifo_full) begin
fifo_wren_next = '0;
state_next = ST_IDLE;
end
end else begin
// third phase: read multiplication result
g_data_next = g_q[26:0];
mcmd_next = '0;
if (~g_rden_reg & ~t_wren_reg[2]) begin
// allow a few cycles for the multiplier to start storing the result
if (load_tram_mstart) begin
g_addr_next = 9'd128;
g_rden_next = '1;
delay_next = '1;
end else begin
g_addr_next = g_addr_reg + 1'b1;
end
end else begin
g_addr_next = g_addr_reg + 1'b1;
if (~delay_reg) begin
t_wren_next = 3'b100;
if (t_wren_reg[2]) begin
if (load_tram_tlast) begin
address_next = '0;
t_wren_next = '0;
fifo_datao_next = {4'h3,28'b0};
fifo_wren_next = '1;
// write back response to host
if (~fifo_full) begin
state_next = ST_IDLE;
end
end else begin
address_next = address_reg + 1'b1;
end
end
end
if (load_tram_last) begin
g_rden_next = '0;
end
end
end
end
ST_LOAD_ERAM: begin
if (g_wren_reg) begin
g_wren_next = '0;
if (~address_reg[14]) begin
fifo_rden_next = '1;
end
dcmd_next = {CMD_D_GRAM2DRAM,unit_reg};
mcmd_next = CMD_RESETRESULT;
end else begin
mcmd_next = '0;
e_wren_next = '0;
if (dcmd_reg != 2'b00) begin
dcmd_next = '0;
end else if (~address_reg[12] & d_idle) begin
address_next[12] = 1'b1;
if (loadprev_reg) begin
dcmd_next = {CMD_D_DRAM2GRAM,unit_reg};
delay_next = '1;
end else begin
dcmd_next = {CMD_D_BLANKGRAM,unit_reg};
delay_next = '1;
end
end
if (~address_reg[14]) begin
if (~address_reg[13]) begin
if (e_wren_reg) begin
if (load_eram_last) begin
address_next[13] = 1'b1;
fifo_rden_next = '0;
e_wren_next = '0;
end else begin
address_next[11:0] = address_next[11:0] + 1'b1;
end
end
if (~fifo_empty & fifo_rden_reg) begin
if ( (load_eram_alast & e_wren_reg) | load_eram_last ) begin
// either we're currently writing the second-last value,
// or we did at some point in the past, so this is the
// final time we should read from the FIFO
fifo_rden_next = '0;
end
e_wren_next = '1;
end
end else begin
if (fifo_wren_reg) begin
// wait until we can write our status word to the fifo
if (~fifo_full) begin
address_next = '0;
fifo_wren_next = '0;
state_next = ST_IDLE;
end
end else if (address_reg[12] & d_idle & ~delay_reg) begin
fifo_datao_next = {4'h1,28'b0};
fifo_wren_next = '1;
if (~fifo_full) begin
address_next = '0;
state_next = ST_IDLE;
end
end
end
end else begin
if (fifo_wren_reg) begin
if (~fifo_full) begin
address_next = '0;
fifo_wren_next = '0;
state_next = ST_IDLE;
end
end else if (address_reg[12] & d_idle & ~delay_reg) begin
fifo_datao_next = {4'h2,28'b0};
fifo_wren_next = '1;
if (~fifo_full) begin
address_next ='0;
state_next = ST_IDLE;
end
end
end
end
end
default: begin
state_next = ST_IDLE;
end
endcase
end
always_ff @(posedge clk or negedge ctrl_reset_n) begin
if (~ctrl_reset_n) begin
dcmd_reg <= '0;
unit_reg <= '0;
g_addr_reg <= '0;
g_rden_reg <= '0;
g_wren_reg <= '0;
g_data_reg <= '0;
t_wren_reg <= '0;
tcmd_reg <= '0;
mcmd_reg <= '0;
e_wren_reg <= '0;
state_reg <= '0;
address_reg <= '0;
fifo_datao_reg <= '0;
fifo_rden_reg <= '0;
fifo_wren_reg <= '0;
loadprev_reg <= '0;
delay_reg <= '0;
end else begin
dcmd_reg <= dcmd_next;
unit_reg <= unit_next;
g_addr_reg <= g_addr_next;
g_rden_reg <= g_rden_next;
g_wren_reg <= g_wren_next;
g_data_reg <= g_data_next;
t_wren_reg <= t_wren_next;
tcmd_reg <= tcmd_next;
mcmd_reg <= mcmd_next;
e_wren_reg <= e_wren_next;
state_reg <= state_next;
address_reg <= address_next;
fifo_datao_reg <= fifo_datao_next;
fifo_rden_reg <= fifo_rden_next;
fifo_wren_reg <= fifo_wren_next;
loadprev_reg <= loadprev_next;
delay_reg <= delay_next;
end
end
dram_control idram ( .clk (clk)
, .pcie_perstn (pcie_perstn)
, .pcie_ready (pcie_ready & pll_core_locked)
, .user_resetn (user_resetn)
, .ctrl_reset_n (ctrl_reset_n)
, .command (dcmd_reg)
, .g_mem_addr ({d_unitsel, d_g_addr})
, .g_mem_wren (d_g_wren)
, .g_mem_rden (d_g_rden)
, .g_mem_datai (d_g_data)
, .g_mem_datao (g_q)
, .addr_direct (fifo_datai[19:0])
, .ddr3_a (ddr3_a)
, .ddr3_ba (ddr3_ba)
, .ddr3_ck_p (ddr3_ck_p)
, .ddr3_ck_n (ddr3_ck_n)
, .ddr3_cke (ddr3_cke)
, .ddr3_csn (ddr3_csn)
, .ddr3_dm (ddr3_dm)
, .ddr3_rasn (ddr3_rasn)
, .ddr3_casn (ddr3_casn)
, .ddr3_wen (ddr3_wen)
, .ddr3_rstn (ddr3_rstn)
, .ddr3_dq (ddr3_dq)
, .ddr3_dqs_p (ddr3_dqs_p)
, .ddr3_dqs_n (ddr3_dqs_n)
, .ddr3_odt (ddr3_odt)
, .ddr3_oct_rzq (ddr3_oct_rzq)
, .clkin_100_p (clkin_100_p)
, .idle (d_idle)
);
table_control itabl ( .clk (clk)
, .ctrl_reset_n (ctrl_reset_n)
, .tdatai (t_datai)
, .twraddr (t_wraddr)
, .twren (t_wren_reg)
, .tdata_0 (tdata_0)
, .tdata_1 (tdata_1)
, .tdata_2 (tdata_2)
, .command (tcmd_reg)
, .idle (t_idle)
);
genvar MGen;
generate for(MGen=0; MGen<n_mult; MGen++) begin: MGenIter
mult_unit #( .mult_addr (MGen)
) imult
( .clk (clk)
, .ctrl_reset_n (ctrl_reset_n)
, .unit_select (unit_select)
, .g_addr (g_addr)
, .g_data (g_data)
, .g_rden (g_rden)
, .g_wren (g_wren)
, .g_q (m_g_q[MGen])
, .e_wraddr (e_addr)
, .e_data (e_data)
, .e_wren (e_wren_reg)
, .command (mcmd_reg)
, .idle (m_idle[MGen])
, .tdata_0 (tdata_0)
, .tdata_1 (tdata_1)
, .tdata_2 (tdata_2)
);
end
endgenerate
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 00:43:54 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_ov7670_controller_0_0 -prefix
// system_ov7670_controller_0_0_ system_ov7670_controller_0_0_sim_netlist.v
// Design : system_ov7670_controller_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_ov7670_controller_0_0_i2c_sender
(E,
sioc,
p_0_in,
\busy_sr_reg[1]_0 ,
siod,
\busy_sr_reg[31]_0 ,
clk,
p_1_in,
DOADO,
\busy_sr_reg[31]_1 );
output [0:0]E;
output sioc;
output p_0_in;
output \busy_sr_reg[1]_0 ;
output siod;
input \busy_sr_reg[31]_0 ;
input clk;
input [0:0]p_1_in;
input [15:0]DOADO;
input [0:0]\busy_sr_reg[31]_1 ;
wire [15:0]DOADO;
wire [0:0]E;
wire busy_sr0;
wire \busy_sr[0]_i_3_n_0 ;
wire \busy_sr[0]_i_5_n_0 ;
wire \busy_sr[10]_i_1_n_0 ;
wire \busy_sr[11]_i_1_n_0 ;
wire \busy_sr[12]_i_1_n_0 ;
wire \busy_sr[13]_i_1_n_0 ;
wire \busy_sr[14]_i_1_n_0 ;
wire \busy_sr[15]_i_1_n_0 ;
wire \busy_sr[16]_i_1_n_0 ;
wire \busy_sr[17]_i_1_n_0 ;
wire \busy_sr[18]_i_1_n_0 ;
wire \busy_sr[19]_i_1_n_0 ;
wire \busy_sr[1]_i_1_n_0 ;
wire \busy_sr[20]_i_1_n_0 ;
wire \busy_sr[21]_i_1_n_0 ;
wire \busy_sr[22]_i_1_n_0 ;
wire \busy_sr[23]_i_1_n_0 ;
wire \busy_sr[24]_i_1_n_0 ;
wire \busy_sr[25]_i_1_n_0 ;
wire \busy_sr[26]_i_1_n_0 ;
wire \busy_sr[27]_i_1_n_0 ;
wire \busy_sr[28]_i_1_n_0 ;
wire \busy_sr[29]_i_1_n_0 ;
wire \busy_sr[2]_i_1_n_0 ;
wire \busy_sr[30]_i_1_n_0 ;
wire \busy_sr[31]_i_1_n_0 ;
wire \busy_sr[31]_i_2_n_0 ;
wire \busy_sr[3]_i_1_n_0 ;
wire \busy_sr[4]_i_1_n_0 ;
wire \busy_sr[5]_i_1_n_0 ;
wire \busy_sr[6]_i_1_n_0 ;
wire \busy_sr[7]_i_1_n_0 ;
wire \busy_sr[8]_i_1_n_0 ;
wire \busy_sr[9]_i_1_n_0 ;
wire \busy_sr_reg[1]_0 ;
wire \busy_sr_reg[31]_0 ;
wire [0:0]\busy_sr_reg[31]_1 ;
wire \busy_sr_reg_n_0_[0] ;
wire \busy_sr_reg_n_0_[10] ;
wire \busy_sr_reg_n_0_[11] ;
wire \busy_sr_reg_n_0_[12] ;
wire \busy_sr_reg_n_0_[13] ;
wire \busy_sr_reg_n_0_[14] ;
wire \busy_sr_reg_n_0_[15] ;
wire \busy_sr_reg_n_0_[16] ;
wire \busy_sr_reg_n_0_[17] ;
wire \busy_sr_reg_n_0_[18] ;
wire \busy_sr_reg_n_0_[1] ;
wire \busy_sr_reg_n_0_[21] ;
wire \busy_sr_reg_n_0_[22] ;
wire \busy_sr_reg_n_0_[23] ;
wire \busy_sr_reg_n_0_[24] ;
wire \busy_sr_reg_n_0_[25] ;
wire \busy_sr_reg_n_0_[26] ;
wire \busy_sr_reg_n_0_[27] ;
wire \busy_sr_reg_n_0_[28] ;
wire \busy_sr_reg_n_0_[29] ;
wire \busy_sr_reg_n_0_[2] ;
wire \busy_sr_reg_n_0_[30] ;
wire \busy_sr_reg_n_0_[3] ;
wire \busy_sr_reg_n_0_[4] ;
wire \busy_sr_reg_n_0_[5] ;
wire \busy_sr_reg_n_0_[6] ;
wire \busy_sr_reg_n_0_[7] ;
wire \busy_sr_reg_n_0_[8] ;
wire \busy_sr_reg_n_0_[9] ;
wire clk;
wire \data_sr[10]_i_1_n_0 ;
wire \data_sr[12]_i_1_n_0 ;
wire \data_sr[13]_i_1_n_0 ;
wire \data_sr[14]_i_1_n_0 ;
wire \data_sr[15]_i_1_n_0 ;
wire \data_sr[16]_i_1_n_0 ;
wire \data_sr[17]_i_1_n_0 ;
wire \data_sr[18]_i_1_n_0 ;
wire \data_sr[19]_i_1_n_0 ;
wire \data_sr[22]_i_1_n_0 ;
wire \data_sr[27]_i_1_n_0 ;
wire \data_sr[30]_i_1_n_0 ;
wire \data_sr[31]_i_1_n_0 ;
wire \data_sr[31]_i_2_n_0 ;
wire \data_sr[3]_i_1_n_0 ;
wire \data_sr[4]_i_1_n_0 ;
wire \data_sr[5]_i_1_n_0 ;
wire \data_sr[6]_i_1_n_0 ;
wire \data_sr[7]_i_1_n_0 ;
wire \data_sr[8]_i_1_n_0 ;
wire \data_sr[9]_i_1_n_0 ;
wire \data_sr_reg_n_0_[10] ;
wire \data_sr_reg_n_0_[11] ;
wire \data_sr_reg_n_0_[12] ;
wire \data_sr_reg_n_0_[13] ;
wire \data_sr_reg_n_0_[14] ;
wire \data_sr_reg_n_0_[15] ;
wire \data_sr_reg_n_0_[16] ;
wire \data_sr_reg_n_0_[17] ;
wire \data_sr_reg_n_0_[18] ;
wire \data_sr_reg_n_0_[19] ;
wire \data_sr_reg_n_0_[1] ;
wire \data_sr_reg_n_0_[20] ;
wire \data_sr_reg_n_0_[21] ;
wire \data_sr_reg_n_0_[22] ;
wire \data_sr_reg_n_0_[23] ;
wire \data_sr_reg_n_0_[24] ;
wire \data_sr_reg_n_0_[25] ;
wire \data_sr_reg_n_0_[26] ;
wire \data_sr_reg_n_0_[27] ;
wire \data_sr_reg_n_0_[28] ;
wire \data_sr_reg_n_0_[29] ;
wire \data_sr_reg_n_0_[2] ;
wire \data_sr_reg_n_0_[30] ;
wire \data_sr_reg_n_0_[31] ;
wire \data_sr_reg_n_0_[3] ;
wire \data_sr_reg_n_0_[4] ;
wire \data_sr_reg_n_0_[5] ;
wire \data_sr_reg_n_0_[6] ;
wire \data_sr_reg_n_0_[7] ;
wire \data_sr_reg_n_0_[8] ;
wire \data_sr_reg_n_0_[9] ;
wire [7:6]divider_reg__0;
wire [5:0]divider_reg__1;
wire p_0_in;
wire [7:0]p_0_in__0;
wire [0:0]p_1_in;
wire [1:0]p_1_in_0;
wire sioc;
wire sioc_i_1_n_0;
wire sioc_i_2_n_0;
wire sioc_i_3_n_0;
wire sioc_i_4_n_0;
wire sioc_i_5_n_0;
wire siod;
wire siod_INST_0_i_1_n_0;
LUT6 #(
.INIT(64'h4000FFFF40004000))
\busy_sr[0]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.I2(divider_reg__0[7]),
.I3(p_0_in),
.I4(\busy_sr_reg[1]_0 ),
.I5(p_1_in),
.O(busy_sr0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\busy_sr[0]_i_3
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(\busy_sr[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\busy_sr[0]_i_4
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[3]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(\busy_sr[0]_i_5_n_0 ),
.O(\busy_sr_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFFFE))
\busy_sr[0]_i_5
(.I0(divider_reg__1[5]),
.I1(divider_reg__1[4]),
.I2(divider_reg__0[7]),
.I3(divider_reg__0[6]),
.O(\busy_sr[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[10]_i_1
(.I0(\busy_sr_reg_n_0_[9] ),
.I1(p_0_in),
.O(\busy_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[11]_i_1
(.I0(\busy_sr_reg_n_0_[10] ),
.I1(p_0_in),
.O(\busy_sr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[12]_i_1
(.I0(\busy_sr_reg_n_0_[11] ),
.I1(p_0_in),
.O(\busy_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[13]_i_1
(.I0(\busy_sr_reg_n_0_[12] ),
.I1(p_0_in),
.O(\busy_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[14]_i_1
(.I0(\busy_sr_reg_n_0_[13] ),
.I1(p_0_in),
.O(\busy_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[15]_i_1
(.I0(\busy_sr_reg_n_0_[14] ),
.I1(p_0_in),
.O(\busy_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[16]_i_1
(.I0(\busy_sr_reg_n_0_[15] ),
.I1(p_0_in),
.O(\busy_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[17]_i_1
(.I0(\busy_sr_reg_n_0_[16] ),
.I1(p_0_in),
.O(\busy_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[18]_i_1
(.I0(\busy_sr_reg_n_0_[17] ),
.I1(p_0_in),
.O(\busy_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[19]_i_1
(.I0(\busy_sr_reg_n_0_[18] ),
.I1(p_0_in),
.O(\busy_sr[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[1]_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(p_0_in),
.O(\busy_sr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[20]_i_1
(.I0(p_1_in_0[0]),
.I1(p_0_in),
.O(\busy_sr[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[21]_i_1
(.I0(p_1_in_0[1]),
.I1(p_0_in),
.O(\busy_sr[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[22]_i_1
(.I0(\busy_sr_reg_n_0_[21] ),
.I1(p_0_in),
.O(\busy_sr[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[23]_i_1
(.I0(\busy_sr_reg_n_0_[22] ),
.I1(p_0_in),
.O(\busy_sr[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[24]_i_1
(.I0(\busy_sr_reg_n_0_[23] ),
.I1(p_0_in),
.O(\busy_sr[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[25]_i_1
(.I0(\busy_sr_reg_n_0_[24] ),
.I1(p_0_in),
.O(\busy_sr[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[26]_i_1
(.I0(\busy_sr_reg_n_0_[25] ),
.I1(p_0_in),
.O(\busy_sr[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[27]_i_1
(.I0(\busy_sr_reg_n_0_[26] ),
.I1(p_0_in),
.O(\busy_sr[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[28]_i_1
(.I0(\busy_sr_reg_n_0_[27] ),
.I1(p_0_in),
.O(\busy_sr[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[29]_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(p_0_in),
.O(\busy_sr[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[2]_i_1
(.I0(\busy_sr_reg_n_0_[1] ),
.I1(p_0_in),
.O(\busy_sr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[30]_i_1
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(p_0_in),
.O(\busy_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h22222222A2222222))
\busy_sr[31]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.I3(divider_reg__0[7]),
.I4(divider_reg__0[6]),
.I5(\busy_sr[0]_i_3_n_0 ),
.O(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[31]_i_2
(.I0(p_0_in),
.I1(\busy_sr_reg_n_0_[30] ),
.O(\busy_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[3]_i_1
(.I0(\busy_sr_reg_n_0_[2] ),
.I1(p_0_in),
.O(\busy_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[4]_i_1
(.I0(\busy_sr_reg_n_0_[3] ),
.I1(p_0_in),
.O(\busy_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[5]_i_1
(.I0(\busy_sr_reg_n_0_[4] ),
.I1(p_0_in),
.O(\busy_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[6]_i_1
(.I0(\busy_sr_reg_n_0_[5] ),
.I1(p_0_in),
.O(\busy_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[7]_i_1
(.I0(\busy_sr_reg_n_0_[6] ),
.I1(p_0_in),
.O(\busy_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[8]_i_1
(.I0(\busy_sr_reg_n_0_[7] ),
.I1(p_0_in),
.O(\busy_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[9]_i_1
(.I0(\busy_sr_reg_n_0_[8] ),
.I1(p_0_in),
.O(\busy_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\busy_sr_reg[0]
(.C(clk),
.CE(busy_sr0),
.D(p_1_in),
.Q(\busy_sr_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[10]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[10] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[11]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[11] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[12]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[12] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[13]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[13] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[14]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[14] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[15]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[15] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[16]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[16] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[17]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[17] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[18]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[18] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[19]_i_1_n_0 ),
.Q(p_1_in_0[0]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[1]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[1] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[20]_i_1_n_0 ),
.Q(p_1_in_0[1]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[21]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[21] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[22]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[22]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[22] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[23]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[23] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[24]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[24] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[25]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[25] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[26]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[26] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[27]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[27]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[27] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[28]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[28] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[29]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[29] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[2]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[2] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[30]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[30] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[31]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[31]_i_2_n_0 ),
.Q(p_0_in),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[3]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[3] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[4]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[4] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[5]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[5] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[6]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[6] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[7]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[7] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[8]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[8] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[9]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[9] ),
.S(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[10]_i_1
(.I0(\data_sr_reg_n_0_[9] ),
.I1(p_0_in),
.I2(DOADO[7]),
.O(\data_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[12]_i_1
(.I0(\data_sr_reg_n_0_[11] ),
.I1(p_0_in),
.I2(DOADO[8]),
.O(\data_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[13]_i_1
(.I0(\data_sr_reg_n_0_[12] ),
.I1(p_0_in),
.I2(DOADO[9]),
.O(\data_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[14]_i_1
(.I0(\data_sr_reg_n_0_[13] ),
.I1(p_0_in),
.I2(DOADO[10]),
.O(\data_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[15]_i_1
(.I0(\data_sr_reg_n_0_[14] ),
.I1(p_0_in),
.I2(DOADO[11]),
.O(\data_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[16]_i_1
(.I0(\data_sr_reg_n_0_[15] ),
.I1(p_0_in),
.I2(DOADO[12]),
.O(\data_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[17]_i_1
(.I0(\data_sr_reg_n_0_[16] ),
.I1(p_0_in),
.I2(DOADO[13]),
.O(\data_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[18]_i_1
(.I0(\data_sr_reg_n_0_[17] ),
.I1(p_0_in),
.I2(DOADO[14]),
.O(\data_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[19]_i_1
(.I0(\data_sr_reg_n_0_[18] ),
.I1(p_0_in),
.I2(DOADO[15]),
.O(\data_sr[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[22]_i_1
(.I0(\data_sr_reg_n_0_[22] ),
.I1(\data_sr_reg_n_0_[21] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[27]_i_1
(.I0(\data_sr_reg_n_0_[27] ),
.I1(\data_sr_reg_n_0_[26] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[27]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\data_sr[30]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.O(\data_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[31]_i_1
(.I0(\data_sr_reg_n_0_[31] ),
.I1(\data_sr_reg_n_0_[30] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\data_sr[31]_i_2
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(\data_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[3]_i_1
(.I0(\data_sr_reg_n_0_[2] ),
.I1(p_0_in),
.I2(DOADO[0]),
.O(\data_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[4]_i_1
(.I0(\data_sr_reg_n_0_[3] ),
.I1(p_0_in),
.I2(DOADO[1]),
.O(\data_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[5]_i_1
(.I0(\data_sr_reg_n_0_[4] ),
.I1(p_0_in),
.I2(DOADO[2]),
.O(\data_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[6]_i_1
(.I0(\data_sr_reg_n_0_[5] ),
.I1(p_0_in),
.I2(DOADO[3]),
.O(\data_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[7]_i_1
(.I0(\data_sr_reg_n_0_[6] ),
.I1(p_0_in),
.I2(DOADO[4]),
.O(\data_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[8]_i_1
(.I0(\data_sr_reg_n_0_[7] ),
.I1(p_0_in),
.I2(DOADO[5]),
.O(\data_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[9]_i_1
(.I0(\data_sr_reg_n_0_[8] ),
.I1(p_0_in),
.I2(DOADO[6]),
.O(\data_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[10]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[10] ),
.Q(\data_sr_reg_n_0_[11] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[12]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[13]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[14]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[15]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[16]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[16] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[17]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[17] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[18]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[18] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[19]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[19] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(p_0_in),
.Q(\data_sr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[19] ),
.Q(\data_sr_reg_n_0_[20] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[20] ),
.Q(\data_sr_reg_n_0_[21] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[22]
(.C(clk),
.CE(1'b1),
.D(\data_sr[22]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[22] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[22] ),
.Q(\data_sr_reg_n_0_[23] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[23] ),
.Q(\data_sr_reg_n_0_[24] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[24] ),
.Q(\data_sr_reg_n_0_[25] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[25] ),
.Q(\data_sr_reg_n_0_[26] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[27]
(.C(clk),
.CE(1'b1),
.D(\data_sr[27]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[27] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[27] ),
.Q(\data_sr_reg_n_0_[28] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[28] ),
.Q(\data_sr_reg_n_0_[29] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[1] ),
.Q(\data_sr_reg_n_0_[2] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[29] ),
.Q(\data_sr_reg_n_0_[30] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[31]
(.C(clk),
.CE(1'b1),
.D(\data_sr[31]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[31] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[3]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[4]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[5]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[6]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[7]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[8]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[9]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT1 #(
.INIT(2'h1))
\divider[0]_i_1
(.I0(divider_reg__1[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\divider[1]_i_1
(.I0(divider_reg__1[0]),
.I1(divider_reg__1[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\divider[2]_i_1
(.I0(divider_reg__1[1]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[2]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\divider[3]_i_1
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[1]),
.I3(divider_reg__1[3]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\divider[4]_i_1
(.I0(divider_reg__1[3]),
.I1(divider_reg__1[1]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[2]),
.I4(divider_reg__1[4]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\divider[5]_i_1
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(p_0_in__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\divider[6]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hD2))
\divider[7]_i_2
(.I0(divider_reg__0[6]),
.I1(\busy_sr[0]_i_3_n_0 ),
.I2(divider_reg__0[7]),
.O(p_0_in__0[7]));
FDRE #(
.INIT(1'b1))
\divider_reg[0]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[0]),
.Q(divider_reg__1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[1]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[1]),
.Q(divider_reg__1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[2]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[2]),
.Q(divider_reg__1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[3]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[3]),
.Q(divider_reg__1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[4]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[4]),
.Q(divider_reg__1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[5]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[5]),
.Q(divider_reg__1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[6]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[6]),
.Q(divider_reg__0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[7]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[7]),
.Q(divider_reg__0[7]),
.R(1'b0));
LUT6 #(
.INIT(64'hFCFCFFF8FFFFFFFF))
sioc_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(sioc_i_2_n_0),
.I2(sioc_i_3_n_0),
.I3(\busy_sr_reg_n_0_[1] ),
.I4(sioc_i_4_n_0),
.I5(p_0_in),
.O(sioc_i_1_n_0));
LUT2 #(
.INIT(4'h6))
sioc_i_2
(.I0(divider_reg__0[6]),
.I1(divider_reg__0[7]),
.O(sioc_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hA222))
sioc_i_3
(.I0(sioc_i_5_n_0),
.I1(\busy_sr_reg_n_0_[30] ),
.I2(divider_reg__0[6]),
.I3(p_0_in),
.O(sioc_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7FFF))
sioc_i_4
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(\busy_sr_reg_n_0_[2] ),
.I2(p_0_in),
.I3(\busy_sr_reg_n_0_[30] ),
.O(sioc_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
sioc_i_5
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(\busy_sr_reg_n_0_[1] ),
.I2(\busy_sr_reg_n_0_[29] ),
.I3(\busy_sr_reg_n_0_[2] ),
.O(sioc_i_5_n_0));
FDRE sioc_reg
(.C(clk),
.CE(1'b1),
.D(sioc_i_1_n_0),
.Q(sioc),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
siod_INST_0
(.I0(\data_sr_reg_n_0_[31] ),
.I1(siod_INST_0_i_1_n_0),
.O(siod));
LUT6 #(
.INIT(64'hB0BBB0BB0000B0BB))
siod_INST_0_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(\busy_sr_reg_n_0_[29] ),
.I2(p_1_in_0[0]),
.I3(p_1_in_0[1]),
.I4(\busy_sr_reg_n_0_[11] ),
.I5(\busy_sr_reg_n_0_[10] ),
.O(siod_INST_0_i_1_n_0));
FDRE taken_reg
(.C(clk),
.CE(1'b1),
.D(\busy_sr_reg[31]_0 ),
.Q(E),
.R(1'b0));
endmodule
module system_ov7670_controller_0_0_ov7670_controller
(config_finished,
siod,
sioc,
resend,
clk);
output config_finished;
output siod;
output sioc;
input resend;
input clk;
wire Inst_i2c_sender_n_3;
wire Inst_ov7670_registers_n_16;
wire Inst_ov7670_registers_n_18;
wire clk;
wire config_finished;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire sioc;
wire siod;
wire [15:0]sreg_reg;
wire taken;
system_ov7670_controller_0_0_i2c_sender Inst_i2c_sender
(.DOADO(sreg_reg),
.E(taken),
.\busy_sr_reg[1]_0 (Inst_i2c_sender_n_3),
.\busy_sr_reg[31]_0 (Inst_ov7670_registers_n_18),
.\busy_sr_reg[31]_1 (Inst_ov7670_registers_n_16),
.clk(clk),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.sioc(sioc),
.siod(siod));
system_ov7670_controller_0_0_ov7670_registers Inst_ov7670_registers
(.DOADO(sreg_reg),
.E(taken),
.clk(clk),
.config_finished(config_finished),
.\divider_reg[2] (Inst_i2c_sender_n_3),
.\divider_reg[7] (Inst_ov7670_registers_n_16),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.resend(resend),
.taken_reg(Inst_ov7670_registers_n_18));
endmodule
module system_ov7670_controller_0_0_ov7670_registers
(DOADO,
\divider_reg[7] ,
config_finished,
taken_reg,
p_1_in,
clk,
\divider_reg[2] ,
p_0_in,
resend,
E);
output [15:0]DOADO;
output [0:0]\divider_reg[7] ;
output config_finished;
output taken_reg;
output [0:0]p_1_in;
input clk;
input \divider_reg[2] ;
input p_0_in;
input resend;
input [0:0]E;
wire [15:0]DOADO;
wire [0:0]E;
wire [7:0]address;
wire [7:0]address_reg__0;
wire \address_rep[0]_i_1_n_0 ;
wire \address_rep[1]_i_1_n_0 ;
wire \address_rep[2]_i_1_n_0 ;
wire \address_rep[3]_i_1_n_0 ;
wire \address_rep[4]_i_1_n_0 ;
wire \address_rep[5]_i_1_n_0 ;
wire \address_rep[6]_i_1_n_0 ;
wire \address_rep[7]_i_1_n_0 ;
wire \address_rep[7]_i_2_n_0 ;
wire clk;
wire config_finished;
wire config_finished_INST_0_i_1_n_0;
wire config_finished_INST_0_i_2_n_0;
wire config_finished_INST_0_i_3_n_0;
wire config_finished_INST_0_i_4_n_0;
wire \divider_reg[2] ;
wire [0:0]\divider_reg[7] ;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire taken_reg;
wire [15:0]NLW_sreg_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPBDOP_UNCONNECTED;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address_reg__0[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address_reg__0[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address_reg__0[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address_reg__0[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address_reg__0[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address_reg__0[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address_reg__0[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address_reg__0[7]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address[7]),
.R(resend));
LUT1 #(
.INIT(2'h1))
\address_rep[0]_i_1
(.I0(address_reg__0[0]),
.O(\address_rep[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h6))
\address_rep[1]_i_1
(.I0(address_reg__0[0]),
.I1(address_reg__0[1]),
.O(\address_rep[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h78))
\address_rep[2]_i_1
(.I0(address_reg__0[1]),
.I1(address_reg__0[0]),
.I2(address_reg__0[2]),
.O(\address_rep[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h7F80))
\address_rep[3]_i_1
(.I0(address_reg__0[2]),
.I1(address_reg__0[0]),
.I2(address_reg__0[1]),
.I3(address_reg__0[3]),
.O(\address_rep[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h7FFF8000))
\address_rep[4]_i_1
(.I0(address_reg__0[3]),
.I1(address_reg__0[1]),
.I2(address_reg__0[0]),
.I3(address_reg__0[2]),
.I4(address_reg__0[4]),
.O(\address_rep[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\address_rep[5]_i_1
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h9))
\address_rep[6]_i_1
(.I0(\address_rep[7]_i_2_n_0 ),
.I1(address_reg__0[6]),
.O(\address_rep[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hD2))
\address_rep[7]_i_1
(.I0(address_reg__0[6]),
.I1(\address_rep[7]_i_2_n_0 ),
.I2(address_reg__0[7]),
.O(\address_rep[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\address_rep[7]_i_2
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h0000FFFE))
\busy_sr[0]_i_2
(.I0(config_finished_INST_0_i_4_n_0),
.I1(config_finished_INST_0_i_3_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_1_n_0),
.I4(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0001))
config_finished_INST_0
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.O(config_finished));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_1
(.I0(DOADO[5]),
.I1(DOADO[4]),
.I2(DOADO[7]),
.I3(DOADO[6]),
.O(config_finished_INST_0_i_1_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_2
(.I0(DOADO[1]),
.I1(DOADO[0]),
.I2(DOADO[3]),
.I3(DOADO[2]),
.O(config_finished_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_3
(.I0(DOADO[13]),
.I1(DOADO[12]),
.I2(DOADO[15]),
.I3(DOADO[14]),
.O(config_finished_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_4
(.I0(DOADO[9]),
.I1(DOADO[8]),
.I2(DOADO[11]),
.I3(DOADO[10]),
.O(config_finished_INST_0_i_4_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\divider[7]_i_1
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.I4(\divider_reg[2] ),
.I5(p_0_in),
.O(\divider_reg[7] ));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "4096" *)
(* RTL_RAM_NAME = "U0/Inst_ov7670_registers/sreg" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "1023" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "15" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h53295217510C50344F4014383A04401004008C003E000C001100120412801280),
.INIT_01(256'h229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440),
.INIT_02(256'h90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
sreg_reg
(.ADDRARDADDR({1'b0,1'b0,address,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(clk),
.CLKBWRCLK(1'b0),
.DIADI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO(DOADO),
.DOBDO(NLW_sreg_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_sreg_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_sreg_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000055555554))
taken_i_1
(.I0(p_0_in),
.I1(config_finished_INST_0_i_1_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_3_n_0),
.I4(config_finished_INST_0_i_4_n_0),
.I5(\divider_reg[2] ),
.O(taken_reg));
endmodule
(* CHECK_LICENSE_TYPE = "system_ov7670_controller_0_0,ov7670_controller,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_controller,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_ov7670_controller_0_0
(clk,
resend,
config_finished,
sioc,
siod,
reset,
pwdn,
xclk);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input resend;
output config_finished;
output sioc;
inout siod;
(* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) output reset;
output pwdn;
output xclk;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire config_finished;
wire resend;
wire sioc;
wire siod;
assign pwdn = \<const0> ;
assign reset = \<const1> ;
GND GND
(.G(\<const0> ));
system_ov7670_controller_0_0_ov7670_controller U0
(.clk(clk),
.config_finished(config_finished),
.resend(resend),
.sioc(sioc),
.siod(siod));
VCC VCC
(.P(\<const1> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The top module of always on domain
//
// ====================================================================
module sirv_aon_top #(
parameter ASYNC_FF_LEVELS = 2
)(
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
input io_pads_aon_erst_n_i_ival,
output io_pads_aon_erst_n_o_oval,
output io_pads_aon_erst_n_o_oe,
output io_pads_aon_erst_n_o_ie,
output io_pads_aon_erst_n_o_pue,
output io_pads_aon_erst_n_o_ds,
input io_pads_aon_pmu_dwakeup_n_i_ival,
output io_pads_aon_pmu_dwakeup_n_o_oval,
output io_pads_aon_pmu_dwakeup_n_o_oe,
output io_pads_aon_pmu_dwakeup_n_o_ie,
output io_pads_aon_pmu_dwakeup_n_o_pue,
output io_pads_aon_pmu_dwakeup_n_o_ds,
input io_pads_aon_pmu_vddpaden_i_ival,
output io_pads_aon_pmu_vddpaden_o_oval,
output io_pads_aon_pmu_vddpaden_o_oe,
output io_pads_aon_pmu_vddpaden_o_ie,
output io_pads_aon_pmu_vddpaden_o_pue,
output io_pads_aon_pmu_vddpaden_o_ds,
input io_pads_aon_pmu_padrst_i_ival,
output io_pads_aon_pmu_padrst_o_oval,
output io_pads_aon_pmu_padrst_o_oe,
output io_pads_aon_pmu_padrst_o_ie,
output io_pads_aon_pmu_padrst_o_pue,
output io_pads_aon_pmu_padrst_o_ds,
input io_pads_dbgmode0_n_i_ival,
input io_pads_dbgmode1_n_i_ival,
input io_pads_dbgmode2_n_i_ival,
input io_pads_bootrom_n_i_ival,
output io_pads_bootrom_n_o_oval,
output io_pads_bootrom_n_o_oe,
output io_pads_bootrom_n_o_ie,
output io_pads_bootrom_n_o_pue,
output io_pads_bootrom_n_o_ds,
input io_pads_jtagpwd_n_i_ival,
output io_pads_jtagpwd_n_o_oval,
output io_pads_jtagpwd_n_o_oe,
output io_pads_jtagpwd_n_o_ie,
output io_pads_jtagpwd_n_o_pue,
output io_pads_jtagpwd_n_o_ds,
output hfclkrst,
output corerst,
output jtagpwd_iso,
output inspect_mode,
output inspect_por_rst,
output inspect_32k_clk,
input inspect_pc_29b,
input inspect_dbg_irq,
output [32-1:0] pc_rtvec,
output aon_wdg_irq,
output aon_rtc_irq,
output aon_rtcToggle,
input lfextclk,
output lfxoscen,
input test_mode,
input test_iso_override
);
// Since the Aon module need to handle the path from the MOFF domain, which
// maybe powered down, so we need to have the isolation cells here
// it can be handled by UPF flow, but we can also add them mannually here
// The inputs from MOFF to aon domain need to be isolated
// The outputs does not need to be isolated
wire isl_icb_cmd_valid;
wire isl_icb_cmd_ready;
wire [32-1:0] isl_icb_cmd_addr;
wire isl_icb_cmd_read;
wire [32-1:0] isl_icb_cmd_wdata;
wire isl_icb_rsp_valid;
wire isl_icb_rsp_ready;
wire [32-1:0] isl_icb_rsp_rdata;
wire aon_iso;
assign isl_icb_cmd_valid = aon_iso ? 1'b0 : i_icb_cmd_valid;
assign isl_icb_cmd_addr = aon_iso ? 32'b0 : i_icb_cmd_addr ;
assign isl_icb_cmd_read = aon_iso ? 1'b0 : i_icb_cmd_read ;
assign isl_icb_cmd_wdata = aon_iso ? 32'b0 : i_icb_cmd_wdata;
assign isl_icb_rsp_ready = aon_iso ? 1'b0 : i_icb_rsp_ready;
assign i_icb_rsp_valid = isl_icb_rsp_valid;
assign i_icb_cmd_ready = isl_icb_cmd_ready;
assign i_icb_rsp_rdata = isl_icb_rsp_rdata;
wire synced_icb_cmd_valid;
wire synced_icb_cmd_ready;
wire [32-1:0] synced_icb_cmd_addr;
wire synced_icb_cmd_read;
wire [32-1:0] synced_icb_cmd_wdata;
wire synced_icb_rsp_valid;
wire synced_icb_rsp_ready;
wire [32-1:0] synced_icb_rsp_rdata;
wire lclkgen_icb_cmd_valid;
wire lclkgen_icb_cmd_ready;
wire [15-1:0] lclkgen_icb_cmd_addr;
wire lclkgen_icb_cmd_read;
wire [32-1:0] lclkgen_icb_cmd_wdata;
wire lclkgen_icb_rsp_valid;
wire lclkgen_icb_rsp_ready;
wire [32-1:0] lclkgen_icb_rsp_rdata;
wire aon_icb_cmd_valid;
wire aon_icb_cmd_ready;
wire [15-1:0] aon_icb_cmd_addr;
wire aon_icb_cmd_read;
wire [32-1:0] aon_icb_cmd_wdata;
wire aon_icb_rsp_valid;
wire aon_icb_rsp_ready;
wire [32-1:0] aon_icb_rsp_rdata;
localparam CMD_PACK_W = 65;
wire [CMD_PACK_W-1:0] synced_icb_cmd_pack;
wire [CMD_PACK_W-1:0] isl_icb_cmd_pack;
assign isl_icb_cmd_pack = {
isl_icb_cmd_addr,
isl_icb_cmd_read,
isl_icb_cmd_wdata};
assign {synced_icb_cmd_addr,
synced_icb_cmd_read,
synced_icb_cmd_wdata} = synced_icb_cmd_pack;
wire crossing_clock;
wire crossing_reset;
wire crossing_reset_n = ~crossing_reset;
sirv_gnrl_cdc_tx
# (
.DW (32),
.SYNC_DP (ASYNC_FF_LEVELS)
) u_aon_icb_cdc_tx (
.o_vld (isl_icb_rsp_valid ),
.o_rdy_a(isl_icb_rsp_ready ),
.o_dat (isl_icb_rsp_rdata ),
.i_vld (synced_icb_rsp_valid ),
.i_rdy (synced_icb_rsp_ready ),
.i_dat (synced_icb_rsp_rdata ),
.clk (crossing_clock),
.rst_n (crossing_reset_n)
);
sirv_gnrl_cdc_rx
# (
.DW (CMD_PACK_W),
.SYNC_DP (ASYNC_FF_LEVELS)
) u_aon_icb_cdc_rx (
.i_vld_a(isl_icb_cmd_valid),
.i_rdy (isl_icb_cmd_ready),
.i_dat (isl_icb_cmd_pack),
.o_vld (synced_icb_cmd_valid),
.o_rdy (synced_icb_cmd_ready),
.o_dat (synced_icb_cmd_pack),
.clk (crossing_clock),
.rst_n (crossing_reset_n)
);
sirv_icb1to2_bus # (
.ICB_FIFO_DP (0),//Pass through
.ICB_FIFO_CUT_READY (1),//
.AW (15),
.DW (32),
.SPLT_FIFO_OUTS_NUM (1),// Allow 1 oustanding
.SPLT_FIFO_CUT_READY (1),// Always cut ready
// * LCLKGEN : 0x200 -- 0x2FF
.O0_BASE_ADDR (15'h200),
.O0_BASE_REGION_LSB (8)
)u_aon_1to2_icb(
.i_icb_cmd_valid (synced_icb_cmd_valid),
.i_icb_cmd_ready (synced_icb_cmd_ready),
.i_icb_cmd_addr (synced_icb_cmd_addr[14:0] ),
.i_icb_cmd_read (synced_icb_cmd_read ),
.i_icb_cmd_wdata (synced_icb_cmd_wdata),
.i_icb_cmd_wmask (4'hF),
.i_icb_cmd_lock (1'b0),
.i_icb_cmd_excl (1'b0 ),
.i_icb_cmd_size (2'b0 ),
.i_icb_cmd_burst (2'b0 ),
.i_icb_cmd_beat (2'b0 ),
.i_icb_rsp_valid (synced_icb_rsp_valid),
.i_icb_rsp_ready (synced_icb_rsp_ready),
.i_icb_rsp_err (),
.i_icb_rsp_excl_ok(),
.i_icb_rsp_rdata (synced_icb_rsp_rdata),
// * LCLKGEN
//
.o0_icb_cmd_valid (lclkgen_icb_cmd_valid),
.o0_icb_cmd_ready (lclkgen_icb_cmd_ready),
.o0_icb_cmd_addr (lclkgen_icb_cmd_addr ),
.o0_icb_cmd_read (lclkgen_icb_cmd_read ),
.o0_icb_cmd_wdata (lclkgen_icb_cmd_wdata),
.o0_icb_cmd_wmask (),
.o0_icb_cmd_lock (),
.o0_icb_cmd_excl (),
.o0_icb_cmd_size (),
.o0_icb_cmd_burst (),
.o0_icb_cmd_beat (),
.o0_icb_rsp_valid (lclkgen_icb_rsp_valid),
.o0_icb_rsp_ready (lclkgen_icb_rsp_ready),
.o0_icb_rsp_err (1'b0),
.o0_icb_rsp_excl_ok(1'b0 ),
.o0_icb_rsp_rdata (lclkgen_icb_rsp_rdata),
// * AON
.o1_icb_cmd_valid (aon_icb_cmd_valid),
.o1_icb_cmd_ready (aon_icb_cmd_ready),
.o1_icb_cmd_addr (aon_icb_cmd_addr ),
.o1_icb_cmd_read (aon_icb_cmd_read ),
.o1_icb_cmd_wdata (aon_icb_cmd_wdata),
.o1_icb_cmd_wmask (),
.o1_icb_cmd_lock (),
.o1_icb_cmd_excl (),
.o1_icb_cmd_size (),
.o1_icb_cmd_burst (),
.o1_icb_cmd_beat (),
.o1_icb_rsp_valid (aon_icb_rsp_valid),
.o1_icb_rsp_ready (aon_icb_rsp_ready),
.o1_icb_rsp_err (1'b0 ),
.o1_icb_rsp_excl_ok(1'b0 ),
.o1_icb_rsp_rdata (aon_icb_rsp_rdata),
.clk (crossing_clock),
.rst_n (crossing_reset_n)
);
wire aon_reset;
wire aon_reset_n = ~aon_reset;
sirv_aon_lclkgen_regs u_aon_lclkgen_regs(
.clk (crossing_clock),// Crossing clock is actually the aon_clk
.rst_n (aon_reset_n),// Here we need to use the aon_rst rather than the crossing reset
.lfxoscen (lfxoscen ),
.i_icb_cmd_valid(lclkgen_icb_cmd_valid),
.i_icb_cmd_ready(lclkgen_icb_cmd_ready),
.i_icb_cmd_addr (lclkgen_icb_cmd_addr[7:0]),
.i_icb_cmd_read (lclkgen_icb_cmd_read ),
.i_icb_cmd_wdata(lclkgen_icb_cmd_wdata),
.i_icb_rsp_valid(lclkgen_icb_rsp_valid),
.i_icb_rsp_ready(lclkgen_icb_rsp_ready),
.i_icb_rsp_rdata(lclkgen_icb_rsp_rdata)
);
wire io_tl_in_0_a_ready;
assign aon_icb_cmd_ready = io_tl_in_0_a_ready;
wire io_tl_in_0_a_valid = aon_icb_cmd_valid;
wire [2:0] io_tl_in_0_a_bits_opcode = aon_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_tl_in_0_a_bits_param = 3'b0;
wire [2:0] io_tl_in_0_a_bits_size = 3'd2;
wire [4:0] io_tl_in_0_a_bits_source = 5'b0;
wire [28:0] io_tl_in_0_a_bits_address = {14'b0,aon_icb_cmd_addr[14:0]};
wire [3:0] io_tl_in_0_a_bits_mask = 4'b1111;
wire [31:0] io_tl_in_0_a_bits_data = aon_icb_cmd_wdata;
wire io_tl_in_0_d_ready = aon_icb_rsp_ready;
wire [2:0] io_tl_in_0_d_bits_opcode;
wire [1:0] io_tl_in_0_d_bits_param;
wire [2:0] io_tl_in_0_d_bits_size;
wire [4:0] io_tl_in_0_d_bits_source;
wire io_tl_in_0_d_bits_sink;
wire [1:0] io_tl_in_0_d_bits_addr_lo;
wire [31:0] io_tl_in_0_d_bits_data;
wire io_tl_in_0_d_bits_error;
wire io_tl_in_0_d_valid;
assign aon_icb_rsp_valid = io_tl_in_0_d_valid;
assign aon_icb_rsp_rdata = io_tl_in_0_d_bits_data;
// Not used
wire io_tl_in_0_b_ready = 1'b0;
wire io_tl_in_0_b_valid;
wire [2:0] io_tl_in_0_b_bits_opcode;
wire [1:0] io_tl_in_0_b_bits_param;
wire [2:0] io_tl_in_0_b_bits_size;
wire [4:0] io_tl_in_0_b_bits_source;
wire [28:0] io_tl_in_0_b_bits_address;
wire [3:0] io_tl_in_0_b_bits_mask;
wire [31:0] io_tl_in_0_b_bits_data;
// Not used
wire io_tl_in_0_c_ready;
wire io_tl_in_0_c_valid = 1'b0;
wire [2:0] io_tl_in_0_c_bits_opcode = 3'b0;
wire [2:0] io_tl_in_0_c_bits_param = 3'b0;
wire [2:0] io_tl_in_0_c_bits_size = 3'd2;
wire [4:0] io_tl_in_0_c_bits_source = 5'b0;
wire [28:0] io_tl_in_0_c_bits_address = 29'b0;
wire [31:0] io_tl_in_0_c_bits_data = 32'b0;
wire io_tl_in_0_c_bits_error = 1'b0;
// Not used
wire io_tl_in_0_e_ready;
wire io_tl_in_0_e_valid = 1'b0;
wire io_tl_in_0_e_bits_sink = 1'b0;
sirv_aon_wrapper u_sirv_aon_wrapper(
.aon_reset (aon_reset),
.aon_iso (aon_iso),
.jtagpwd_iso (jtagpwd_iso),
.crossing_clock (crossing_clock),
.crossing_reset (crossing_reset),
.io_in_0_a_ready (io_tl_in_0_a_ready ),
.io_in_0_a_valid (io_tl_in_0_a_valid ),
.io_in_0_a_bits_opcode (io_tl_in_0_a_bits_opcode ),
.io_in_0_a_bits_param (io_tl_in_0_a_bits_param ),
.io_in_0_a_bits_size (io_tl_in_0_a_bits_size ),
.io_in_0_a_bits_source (io_tl_in_0_a_bits_source ),
.io_in_0_a_bits_address (io_tl_in_0_a_bits_address ),
.io_in_0_a_bits_mask (io_tl_in_0_a_bits_mask ),
.io_in_0_a_bits_data (io_tl_in_0_a_bits_data ),
.io_in_0_b_ready (io_tl_in_0_b_ready ),
.io_in_0_b_valid (io_tl_in_0_b_valid ),
.io_in_0_b_bits_opcode (io_tl_in_0_b_bits_opcode ),
.io_in_0_b_bits_param (io_tl_in_0_b_bits_param ),
.io_in_0_b_bits_size (io_tl_in_0_b_bits_size ),
.io_in_0_b_bits_source (io_tl_in_0_b_bits_source ),
.io_in_0_b_bits_address (io_tl_in_0_b_bits_address ),
.io_in_0_b_bits_mask (io_tl_in_0_b_bits_mask ),
.io_in_0_b_bits_data (io_tl_in_0_b_bits_data ),
.io_in_0_c_ready (io_tl_in_0_c_ready ),
.io_in_0_c_valid (io_tl_in_0_c_valid ),
.io_in_0_c_bits_opcode (io_tl_in_0_c_bits_opcode ),
.io_in_0_c_bits_param (io_tl_in_0_c_bits_param ),
.io_in_0_c_bits_size (io_tl_in_0_c_bits_size ),
.io_in_0_c_bits_source (io_tl_in_0_c_bits_source ),
.io_in_0_c_bits_address (io_tl_in_0_c_bits_address ),
.io_in_0_c_bits_data (io_tl_in_0_c_bits_data ),
.io_in_0_c_bits_error (io_tl_in_0_c_bits_error ),
.io_in_0_d_ready (io_tl_in_0_d_ready ),
.io_in_0_d_valid (io_tl_in_0_d_valid ),
.io_in_0_d_bits_opcode (io_tl_in_0_d_bits_opcode ),
.io_in_0_d_bits_param (io_tl_in_0_d_bits_param ),
.io_in_0_d_bits_size (io_tl_in_0_d_bits_size ),
.io_in_0_d_bits_source (io_tl_in_0_d_bits_source ),
.io_in_0_d_bits_sink (io_tl_in_0_d_bits_sink ),
.io_in_0_d_bits_addr_lo (io_tl_in_0_d_bits_addr_lo ),
.io_in_0_d_bits_data (io_tl_in_0_d_bits_data ),
.io_in_0_d_bits_error (io_tl_in_0_d_bits_error ),
.io_in_0_e_ready (io_tl_in_0_e_ready ),
.io_in_0_e_valid (io_tl_in_0_e_valid ),
.io_in_0_e_bits_sink (io_tl_in_0_e_bits_sink ),
.io_ip_0_0 (aon_wdg_irq),
.io_ip_0_1 (aon_rtc_irq),
.io_pads_erst_n_i_ival (io_pads_aon_erst_n_i_ival ),
.io_pads_erst_n_o_oval (io_pads_aon_erst_n_o_oval ),
.io_pads_erst_n_o_oe (io_pads_aon_erst_n_o_oe ),
.io_pads_erst_n_o_ie (io_pads_aon_erst_n_o_ie ),
.io_pads_erst_n_o_pue (io_pads_aon_erst_n_o_pue ),
.io_pads_erst_n_o_ds (io_pads_aon_erst_n_o_ds ),
.io_pads_lfextclk_i_ival (lfextclk ),
.io_pads_lfextclk_o_oval (),
.io_pads_lfextclk_o_oe (),
.io_pads_lfextclk_o_ie (),
.io_pads_lfextclk_o_pue (),
.io_pads_lfextclk_o_ds (),
.io_pads_pmu_dwakeup_n_i_ival(io_pads_aon_pmu_dwakeup_n_i_ival),
.io_pads_pmu_dwakeup_n_o_oval(io_pads_aon_pmu_dwakeup_n_o_oval),
.io_pads_pmu_dwakeup_n_o_oe (io_pads_aon_pmu_dwakeup_n_o_oe ),
.io_pads_pmu_dwakeup_n_o_ie (io_pads_aon_pmu_dwakeup_n_o_ie ),
.io_pads_pmu_dwakeup_n_o_pue (io_pads_aon_pmu_dwakeup_n_o_pue ),
.io_pads_pmu_dwakeup_n_o_ds (io_pads_aon_pmu_dwakeup_n_o_ds ),
.io_pads_pmu_vddpaden_i_ival (io_pads_aon_pmu_vddpaden_i_ival ),
.io_pads_pmu_vddpaden_o_oval (io_pads_aon_pmu_vddpaden_o_oval ),
.io_pads_pmu_vddpaden_o_oe (io_pads_aon_pmu_vddpaden_o_oe ),
.io_pads_pmu_vddpaden_o_ie (io_pads_aon_pmu_vddpaden_o_ie ),
.io_pads_pmu_vddpaden_o_pue (io_pads_aon_pmu_vddpaden_o_pue ),
.io_pads_pmu_vddpaden_o_ds (io_pads_aon_pmu_vddpaden_o_ds ),
.io_pads_pmu_padrst_i_ival (io_pads_aon_pmu_padrst_i_ival ),
.io_pads_pmu_padrst_o_oval (io_pads_aon_pmu_padrst_o_oval ),
.io_pads_pmu_padrst_o_oe (io_pads_aon_pmu_padrst_o_oe ),
.io_pads_pmu_padrst_o_ie (io_pads_aon_pmu_padrst_o_ie ),
.io_pads_pmu_padrst_o_pue (io_pads_aon_pmu_padrst_o_pue ),
.io_pads_pmu_padrst_o_ds (io_pads_aon_pmu_padrst_o_ds ),
.io_pads_jtagpwd_n_i_ival (io_pads_jtagpwd_n_i_ival),
.io_pads_jtagpwd_n_o_oval (io_pads_jtagpwd_n_o_oval),
.io_pads_jtagpwd_n_o_oe (io_pads_jtagpwd_n_o_oe ),
.io_pads_jtagpwd_n_o_ie (io_pads_jtagpwd_n_o_ie ),
.io_pads_jtagpwd_n_o_pue (io_pads_jtagpwd_n_o_pue ),
.io_pads_jtagpwd_n_o_ds (io_pads_jtagpwd_n_o_ds ),
.io_pads_bootrom_n_i_ival (io_pads_bootrom_n_i_ival),
.io_pads_bootrom_n_o_oval (io_pads_bootrom_n_o_oval),
.io_pads_bootrom_n_o_oe (io_pads_bootrom_n_o_oe ),
.io_pads_bootrom_n_o_ie (io_pads_bootrom_n_o_ie ),
.io_pads_bootrom_n_o_pue (io_pads_bootrom_n_o_pue ),
.io_pads_bootrom_n_o_ds (io_pads_bootrom_n_o_ds ),
.io_pads_dbgmode0_n_i_ival (io_pads_dbgmode0_n_i_ival),
.io_pads_dbgmode1_n_i_ival (io_pads_dbgmode1_n_i_ival),
.io_pads_dbgmode2_n_i_ival (io_pads_dbgmode2_n_i_ival),
.inspect_mode (inspect_mode ),
.inspect_pc_29b (inspect_pc_29b ),
.inspect_por_rst (inspect_por_rst ),
.inspect_32k_clk (inspect_32k_clk ),
.inspect_dbg_irq (inspect_dbg_irq ),
.pc_rtvec (pc_rtvec),
.io_rsts_hfclkrst(hfclkrst),
.io_rsts_corerst (corerst ),
.io_rtc (aon_rtcToggle),
.test_mode (test_mode ),
.test_iso_override(test_iso_override)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3B_SYMBOL_V
`define SKY130_FD_SC_MS__OR3B_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3B_SYMBOL_V
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// ports $00-$3f are in FPGA, $40-$ff are in CPLD
module ports(
din, // NGS z80 cpu DATA BUS inputs
dout, // NGS z80 cpu DATA BUS outputs
busin, // direction of bus: =1 - input, =0 - output
a, // NSG z80 cpu ADDRESS BUS
iorq_n,mreq_n,rd_n,wr_n, // NGS z80 cpu control signals
data_port_input, // data_port input from zxbus module (async)
data_port_output, // data_port output to zxbus module (async to zxbus, sync here)
command_port_input, // command_port input from zxbus (async)
data_bit_input, // data_bit from zxbus module (sync)
command_bit_input, // --//-- (sync)
data_bit_output, // output to zxbus module
command_bit_output,
data_bit_wr, // strobes (positive) to zxbus module, synchronous
command_bit_wr,
mode_8chans, // mode outputs for sound_main module
mode_pan4ch, //
mode_ramro, // mode outputs for memmap module
mode_norom,
mode_pg0, // page registers for memmap module
mode_pg1,
clksel0, // clock select (output from FPGA)
clksel1,
snd_wrtoggle, // toggle to write sound data to sound system memory
snd_datnvol, // whether it's for volume (=0) or for samples (=1)
snd_addr, // address: which channel to be written (0-7)
snd_data, // actual 8-bit data to be written
md_din, // mp3 data interface
md_start,
md_dreq,
md_halfspeed,
mc_ncs, // mp3 control interface
mc_xrst,
mc_dout,
mc_din,
mc_start,
mc_halfspeed,
sd_ncs, // SD card interface
sd_dout,
sd_din,
sd_start,
sd_det,
sd_wp,
led, // LED control
led_toggle,
rst_n,
cpu_clock // Z80 CPU clock (clk_fpga on schematics)
);
localparam MPAG = 6'h00;
localparam MPAGEX = 6'h10;
localparam ZXCMD = 6'h01;
localparam ZXDATRD = 6'h02;
localparam ZXDATWR = 6'h03;
localparam ZXSTAT = 6'h04;
localparam CLRCBIT = 6'h05;
localparam VOL1 = 6'h06;
localparam VOL2 = 6'h07;
localparam VOL3 = 6'h08;
localparam VOL4 = 6'h09;
localparam VOL5 = 6'h16;
localparam VOL6 = 6'h17;
localparam VOL7 = 6'h18;
localparam VOL8 = 6'h19;
localparam DAMNPORT1 = 6'h0a;
localparam DAMNPORT2 = 6'h0b;
localparam LEDCTR = 6'h01;
localparam GSCFG0 = 6'h0f;
localparam SCTRL = 6'h11;
localparam SSTAT = 6'h12;
localparam SD_SEND = 6'h13;
localparam SD_READ = 6'h13;
localparam SD_RSTR = 6'h14;
localparam MD_SEND = 6'h14; // same as SD_RSTR!!!
localparam MC_SEND = 6'h15;
localparam MC_READ = 6'h15;
// inputs/outputs description
input [7:0] din;
output reg [7:0] dout;
output reg busin; // =1 - dbus ins, =0 - dbus outs
input [15:0] a;
input iorq_n,mreq_n,rd_n,wr_n;
input [7:0] data_port_input;
input [7:0] command_port_input;
output reg [7:0] data_port_output;
input data_bit_input;
input command_bit_input;
output reg data_bit_output;
output reg command_bit_output;
output reg data_bit_wr;
output reg command_bit_wr;
output reg mode_8chans;
output reg mode_pan4ch;
output reg mode_ramro;
output reg mode_norom;
output reg [6:0] mode_pg0;
output reg [6:0] mode_pg1;
output reg clksel0;
output reg clksel1;
output reg snd_wrtoggle;
output reg snd_datnvol;
output reg [2:0] snd_addr;
output reg [7:0] snd_data;
input rst_n;
input cpu_clock;
// SPI interfaces related
// MP3 data interface
output [7:0] md_din; // data to MP3 data SPI interface
output md_start; // start toggle for mp3 data spi
input md_dreq; // data request from mp3 decoder
output reg md_halfspeed;
// MP3 control interface
output reg mc_ncs; // nCS signal
output reg mc_xrst; // xRESET signal
output mc_start; // start toggle
output reg mc_halfspeed;
output [7:0] mc_din; // data to send
input [7:0] mc_dout; // received data
// SDcard interface
output reg sd_ncs;
output sd_start;
output [7:0] sd_din;
input [7:0] sd_dout;
input sd_det;
input sd_wp;
// LED control register
output reg led;
input led_toggle;
// internal regs & wires
reg mode_expag; // extended paging mode register
reg port09_bit5;
wire port_enabled; // =1 when port address is in enabled region ($00-$3f)
wire mem_enabled; // =1 when memory mapped sound regs are addressed ($6000-$7FFF)
reg volports_enabled; // when volume ports are addressed (6-9 and $16-$19)
reg iowrn_reg; // registered io write signal (all positive edge!)
reg iordn_reg; // --//--
reg merdn_reg; // --//--
reg port_wr; // synchronous positive write pulse (write from z80 to fpga regs)
reg port_rd; // synchronous positive read pulse (read done from fpga regs to z80)
reg memreg_rd; // when memory-mapped sound regs are read
wire port00_wr; // specific write and read strobes (1 clock cycle long positive)
wire p_ledctr_wr;
wire port02_rd;
wire port03_wr;
wire port05_wrrd;
wire port09_wr;
wire port0a_wrrd;
wire port0b_wrrd;
wire port0f_wr;
wire port10_wr;
wire p_sstat_rd;
wire p_sctrl_rd;
wire p_sctrl_wr;
wire p_sdsnd_wr;
wire p_sdrd_rd;
wire p_sdrst_rd;
wire p_mdsnd_wr;
wire p_mcsnd_wr;
wire p_mcrd_rd;
reg [2:0] volnum; // volume register number from port address
// actual code
//enabled ports
assign port_enabled = ~(a[7] | a[6]); // $00-$3F
//enabled mem
assign mem_enabled = (~a[15]) & a[14] & a[13]; // $6000-$7FFF
// volume ports enabled
always @*
begin
if( a[5:0]==VOL1 ||
a[5:0]==VOL2 ||
a[5:0]==VOL3 ||
a[5:0]==VOL4 ||
a[5:0]==VOL5 ||
a[5:0]==VOL6 ||
a[5:0]==VOL7 ||
a[5:0]==VOL8 )
volports_enabled <= 1'b1;
else
volports_enabled <= 1'b0;
end
//when data bus outputs
always @*
begin
if( port_enabled && (!iorq_n) && (!rd_n) )
busin <= 1'b0; // bus outputs
else
busin <= 1'b1; // bus inputs
end
// rd/wr/iorq syncing in and pulses
always @(posedge cpu_clock)
begin
iowrn_reg <= iorq_n | wr_n;
iordn_reg <= iorq_n | rd_n;
if( port_enabled && (!iorq_n) && (!wr_n) && iowrn_reg )
port_wr <= 1'b1;
else
port_wr <= 1'b0;
if( port_enabled && (!iorq_n) && (!rd_n) && iordn_reg )
port_rd <= 1'b1;
else
port_rd <= 1'b0;
end
// mreq syncing and mem read pulse
always @(negedge cpu_clock)
begin
merdn_reg <= mreq_n | rd_n;
if( mem_enabled && (!mreq_n) && (!rd_n) && merdn_reg )
memreg_rd <= 1'b1;
else
memreg_rd <= 1'b0;
end
// specific ports strobes
assign port00_wr = ( a[5:0]==MPAG && port_wr );
assign port02_rd = ( a[5:0]==ZXDATRD && port_rd );
assign port03_wr = ( a[5:0]==ZXDATWR && port_wr );
assign port05_wrrd = ( a[5:0]==CLRCBIT && (port_wr||port_rd) );
assign port09_wr = ( a[5:0]==VOL4 && port_wr );
assign port0a_wrrd = ( a[5:0]==DAMNPORT1 && (port_wr||port_rd) );
assign port0b_wrrd = ( a[5:0]==DAMNPORT2 && (port_wr||port_rd) );
assign port0f_wr = ( a[5:0]==GSCFG0 && port_wr );
assign port10_wr = ( a[5:0]==MPAGEX && port_wr );
assign p_sctrl_rd = ( a[5:0]==SCTRL && port_rd );
assign p_sctrl_wr = ( a[5:0]==SCTRL && port_wr );
assign p_sstat_rd = ( a[5:0]==SSTAT && port_rd );
assign p_sdsnd_wr = ( a[5:0]==SD_SEND && port_wr );
assign p_sdrd_rd = ( a[5:0]==SD_READ && port_rd );
assign p_sdrst_rd = ( a[5:0]==SD_RSTR && port_rd );
assign p_mdsnd_wr = ( a[5:0]==MD_SEND && port_wr );
assign p_mcsnd_wr = ( a[5:0]==MC_SEND && port_wr );
assign p_mcrd_rd = ( a[5:0]==MC_READ && port_rd );
assign p_ledctr_wr = ( a[5:0]==LEDCTR && port_wr );
// read from fpga to Z80
always @*
begin
case( a[5:0] )
ZXCMD: // command register
dout <= command_port_input;
ZXDATRD: // data register
dout <= data_port_input;
ZXSTAT: // status bits
dout <= { data_bit_input, 6'bXXXXXX, command_bit_input };
GSCFG0: // config register #0F
dout <= { 1'b0, mode_pan4ch, clksel1, clksel0, mode_expag, mode_8chans, mode_ramro, mode_norom };
SSTAT:
dout <= { 5'd0, sd_wp, sd_det, md_dreq };
SCTRL:
dout <= { 3'd0, md_halfspeed, mc_halfspeed, mc_xrst, mc_ncs, sd_ncs };
SD_READ:
dout <= sd_dout;
SD_RSTR:
dout <= sd_dout;
MC_READ:
dout <= mc_dout;
default:
dout <= 8'bXXXXXXXX;
endcase
end
// write to $00 and $10 ports ++
always @(posedge cpu_clock)
begin
if( port00_wr==1'b1 ) // port 00
begin
if( mode_expag==1'b0 ) // normal paging
mode_pg0[6:0] <= { din[5:0], 1'b0 };
else // extended paging
mode_pg0[6:0] <= { din[5:0], din[7] };
end
if( mode_expag==1'b0 && port00_wr==1'b1 ) // port 10 (when in normal mode, part of port 00)
mode_pg1[6:0] <= { din[5:0], 1'b1 };
else if( mode_expag==1'b1 && port10_wr==1'b1 )
mode_pg1[6:0] <= { din[5:0], din[7] };
end
// port $03 write ++
always @(posedge cpu_clock)
begin
if( port03_wr==1'b1 )
data_port_output <= din;
end
// port $09 bit tracing
always @(posedge cpu_clock)
begin
if( port09_wr==1'b1 )
port09_bit5 <= din[5];
end
// write and reset of port $0F ++
always @(posedge cpu_clock,negedge rst_n)
begin
if( rst_n==1'b0 ) // reset!
{ mode_pan4ch, clksel1, clksel0, mode_expag, mode_8chans, mode_ramro, mode_norom } <= 7'b0110000;
else // write to port
begin
if( port0f_wr == 1'b1 )
begin
{ mode_pan4ch, clksel1, clksel0, mode_expag, mode_8chans, mode_ramro, mode_norom } <= din[6:0];
end
end
end
// data bit handling
always @*
begin
case( {port02_rd,port03_wr,port0a_wrrd} )
3'b100:
begin
data_bit_output <= 1'b0;
data_bit_wr <= 1'b1;
end
3'b010:
begin
data_bit_output <= 1'b1; // ++
data_bit_wr <= 1'b1;
end
3'b001:
begin
data_bit_output <= ~mode_pg0[0];
data_bit_wr <= 1'b1;
end
default:
begin
data_bit_output <= 1'bX;
data_bit_wr <= 1'b0;
end
endcase
end
// command bit handling
always @*
begin
casex( {port05_wrrd,port0b_wrrd} )
2'b10:
begin
command_bit_output <= 1'b0;
command_bit_wr <= 1'b1;
end
2'b01:
begin
command_bit_output <= port09_bit5;
command_bit_wr <= 1'b1;
end
default:
begin
command_bit_output <= 1'bX;
command_bit_wr <= 1'b0;
end
endcase
end
// handle data going to sound module (volume and samples values)
always @*
begin
case( a[5:0] ) // port addresses to volume register numbers
VOL1:
volnum <= 3'd0;
VOL2:
volnum <= 3'd1;
VOL3:
volnum <= 3'd2;
VOL4:
volnum <= 3'd3;
VOL5:
volnum <= 3'd4;
VOL6:
volnum <= 3'd5;
VOL7:
volnum <= 3'd6;
VOL8:
volnum <= 3'd7;
default:
volnum <= 3'bXXX;
endcase
end
// handling itself (sending data to sound module)
always @(posedge cpu_clock)
begin
if( memreg_rd ) // memory read - sample data write
begin
snd_wrtoggle <= ~snd_wrtoggle;
snd_datnvol <= 1'b1; // sample data
if( !mode_8chans ) // 4 channel mode
snd_addr <= { 1'b0, a[9:8] };
else // 8 channel mode
snd_addr <= a[10:8];
snd_data <= din;
end
else if( volports_enabled && port_wr )
begin
snd_wrtoggle <= ~snd_wrtoggle;
snd_datnvol <= 1'b0; // volume data
snd_addr <= volnum;
snd_data <= din;
end
end
//SPI (mp3, SD) interfaces
assign sd_din = (a[5:0]==SD_RSTR) ? 8'hFF : din;
assign mc_din = din;
assign md_din = din;
assign sd_start = p_sdsnd_wr | p_sdrst_rd;
assign mc_start = p_mcsnd_wr;
assign md_start = p_mdsnd_wr;
always @(posedge cpu_clock, negedge rst_n)
begin
if( !rst_n ) // async reset
begin
md_halfspeed <= 1'b0;
mc_halfspeed <= 1'b1;
mc_xrst <= 1'b0;
mc_ncs <= 1'b1;
sd_ncs <= 1'b1;
end
else // clock
begin
if( p_sctrl_wr )
begin
if( din[0] )
sd_ncs <= din[7];
if( din[1] )
mc_ncs <= din[7];
if( din[2] )
mc_xrst <= din[7];
if( din[3] )
mc_halfspeed <= din[7];
if( din[4] )
md_halfspeed <= din[7];
end
end
end
// LED control
always @(posedge cpu_clock, negedge rst_n)
begin
if( !rst_n )
led <= 1'b0;
else
begin
if( p_ledctr_wr )
led <= din[0];
else if( led_toggle )
led <= ~led;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_BLACKBOX_V
`define SKY130_FD_SC_LS__NAND2_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_BLACKBOX_V
|
module c3dClkGen2 (
input CLKIN,
output SYSTEM_CLK,
output SYNC_CLK,
output C2C_CLK,
output C2C_CLK180,
output PLL0_LOCK
// Other clocks i.e. for DDR if required
);
// PLL for C2C and B2B modules
PLL_BASE #(.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(2), // Multiplication factor for all output clocks
.CLKFBOUT_PHASE(0.0), // Phase shift (degrees) of all output clocks
.CLKIN_PERIOD(3.2), // Clock period (ns) of input clock on CLKIN
.CLKOUT0_DIVIDE(4), // Division factor for CLKOUT0 (1 to 128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.01 to 0.99)
.CLKOUT0_PHASE(0.0), // Phase shift (degrees) for CLKOUT0 (0.0 to 360.0)
.CLKOUT1_DIVIDE(2), // Division factor for CLKOUT1 (1 to 128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT1 (0.01 to 0.99)
.CLKOUT1_PHASE(0.0), // Phase shift (degrees) for CLKOUT1 (0.0 to 360.0)
.CLKOUT2_DIVIDE(16), // Division factor for CLKOUT2 (1 to 128)
.CLKOUT2_DUTY_CYCLE(0.375), // Duty cycle for CLKOUT2 (0.01 to 0.99)
.CLKOUT2_PHASE(0.0), // Phase shift (degrees) for CLKOUT2 (0.0 to 360.0)
.CLKOUT3_DIVIDE(4), // Division factor for CLKOUT3 (1 to 128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT3 (0.01 to 0.99)
.CLKOUT3_PHASE(180.0), // Phase shift (degrees) for CLKOUT3 (0.0 to 360.0)
.CLKOUT4_DIVIDE(8), // Division factor for CLKOUT4 (1 to 128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT4 (0.01 to 0.99)
.CLKOUT4_PHASE(0.0), // Phase shift (degrees) for CLKOUT4 (0.0 to 360.0)
.CLKOUT5_DIVIDE(4), // Division factor for CLKOUT5 (1 to 128)
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT5 (0.01 to 0.99)
.CLKOUT5_PHASE(180.0), // Phase shift (degrees) for CLKOUT5 (0.0 to 360.0)
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS",
.DIVCLK_DIVIDE(1), // Division factor for all clocks (1 to 52)
.REF_JITTER(0.100)) // Input reference jitter (0.000 to 0.999 UI%)
pll_0 (.CLKFBOUT(pll0_fb ), // General output feedback signal
.CLKOUT0 (pll0_0 ), // 156.25 MHz system clock before buffering
.CLKOUT1 (pll0_1 ), // 312.5 MHz clock for GTP TXUSRCLK
.CLKOUT2 ( ), //
.CLKOUT3 (C2C_CLK180 ), // 156.25 MHz system clock before buffering, 180deg
.CLKOUT4 ( ), //
.CLKOUT5 ( ), //
.LOCKED (PLL0_LOCK ), // Active high PLL lock signal
.CLKFBIN (pll0_fb ), // Clock feedback input
.CLKIN (CLKIN ), // 312.5 MHz clock input from GTP
.RST (1'b0 )
);
BUFG bufg_0_0 (.I(pll0_0), .O(SYSTEM_CLK));
BUFG bufg_0_1 (.I(pll0_1), .O(SYNC_CLK));
assign C2C_CLK = pll0_0;
// 2nd PLL for DDR if required
//This PLL generates MCLK and MCLK90 at whatever frequency we want.
PLL_BASE #(.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(20), // Multiplication factor for all output clocks
.CLKFBOUT_PHASE(0.0), // Phase shift (degrees) of all output clocks
.CLKIN_PERIOD(10.0), // Clock period (ns) of input clock on CLKIN
.CLKOUT0_DIVIDE(4), // Division factor for MCLK (1 to 128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.01 to 0.99)
.CLKOUT0_PHASE(0.0), // Phase shift (degrees) for CLKOUT0 (0.0 to 360.0)
.CLKOUT1_DIVIDE(4), // Division factor for MCLK90 (1 to 128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT1 (0.01 to 0.99)
.CLKOUT1_PHASE(90.0), // Phase shift (degrees) for CLKOUT1 (0.0 to 360.0)
.CLKOUT2_DIVIDE(16), // Division factor for Ph0 (1 to 128)
.CLKOUT2_DUTY_CYCLE(0.375), // Duty cycle for CLKOUT2 (0.01 to 0.99)
.CLKOUT2_PHASE(0.0), // Phase shift (degrees) for CLKOUT2 (0.0 to 360.0)
.CLKOUT3_DIVIDE(4), // Division factor for MCLK180 (1 to 128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT3 (0.01 to 0.99)
.CLKOUT3_PHASE(180.0), // Phase shift (degrees) for CLKOUT3 (0.0 to 360.0)
.CLKOUT4_DIVIDE(8), // Division factor for CLK (1 to 128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT4 (0.01 to 0.99)
.CLKOUT4_PHASE(0.0), // Phase shift (degrees) for CLKOUT4 (0.0 to 360.0)
.CLKOUT5_DIVIDE(4), // Division factor for CLK200 (1 to 128)
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT5 (0.01 to 0.99)
.CLKOUT5_PHASE(180.0), // Phase shift (degrees) for CLKOUT5 (0.0 to 360.0)
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS",
.DIVCLK_DIVIDE(2), // Division factor for all clocks (1 to 52)
.REF_JITTER(0.100)) // Input reference jitter (0.000 to 0.999 UI%)
pll1 (.CLKFBOUT(pll1_fb ), // General output feedback signal
.CLKOUT0 (pll1_0 ), // 266 MHz
.CLKOUT1 (pll1_1 ), // 266 MHz, 90 degree shift
.CLKOUT2 (pll1_2 ), // MCLK/4
.CLKOUT3 (pll1_3 ),
.CLKOUT4 (pll1_4 ), // MCLK/2
.CLKOUT5 ( ),
.LOCKED (PLL1_LOCK), // Active high PLL lock signal
.CLKFBIN (pll1_fb ), // Clock feedback input
.CLKIN (CLK_IN ), // Clock input
.RST (1'b0 )
);
BUFG bufg_1_0 (.I(pll1_0), .O(PLL1_OUT0)); // MCLK
BUFG bufg_1_1 (.I(pll1_1), .O(PLL1_OUT1)); // MCLK90
BUFG pufg_1_2 (.I(pll1_2), .O(PLL1_OUT2)); // PH0
BUFG bufg_1_3 (.I(pll1_4), .O(PLL1_OUT4)); // CLK
//BUFG bufg_1_4 (.I(MCLKx), .O(RingCLK));
//BUFGMUX_CTRL swClkbuf (
//.O(swClock), // Clock MUX output
//.I0(MCLKx), // Clock0 input
//.I1(MCLK180x), // Clock1 input
//.S(switchClock) // Clock select input
//);
endmodule
|
`include "riscv_functions.vh"
module riscv_mem (
input clk,
input rstn,
//Downstream
input ex_mem_rdy,
output ex_mem_ack,
//MEM input
input [31:0] ex_mem_result,
input [`MEM_FUNCT_W-1:0] ex_mem_funct,
input [31:0] ex_mem_data,
input [4:0] ex_mem_wb_rsd,
//Upstream
output mem_wb_rdy,
input mem_wb_ack,
//Mem bus output
output [31:0] data_bif_addr,
output data_bif_req,
output data_bif_rnw,
output [3:0] data_bif_wmask,
output [31:0] data_bif_wdata,
input data_bif_ack,
//WB output
output [`LD_FUNCT_W-1:0] mem_wb_funct,
output [1:0] mem_wb_baddr,
output [31:0] mem_wb_data,
output [4:0] mem_wb_rsd
);
//Output regs
reg [`LD_FUNCT_W-1:0] mem_wb_funct;
reg [1:0] mem_wb_baddr;
reg [31:0] mem_wb_data;
reg [4:0] mem_wb_rsd;
reg mem_wb_rdy_reg;
reg [3:0] waddr_mask;
wire [1:0] baddr;
wire [31:0] waddr;
wire data_req;
assign baddr = ex_mem_result[1:0];
assign waddr = {ex_mem_result[31:2], 2'b0};
assign data_req = (ex_mem_funct == `MEM_NOP) ? 1'b0 : 1'b1;
/*
assign load_op = |(ex_mem_funct[`LD_FUNCT_W-1:0]);
*/
assign data_bif_addr = waddr;
assign data_bif_rnw = |(ex_mem_funct[`LD_FUNCT_W-1:0]);
assign data_bif_req = data_req;
assign data_bif_wmask = waddr_mask << (8*baddr_addr);
assign data_bif_wdata = ex_mem_data;
//This module cannot stall
assign ex_mem_ack = mem_wb_rdy;
assign mem_wb_rdy = mem_wb_rdy_reg & (~data_req | data_bif_ack);
always @ (*) begin
case (ex_mem_funct)
`MEM_SB : waddr_mask = 4'b0001;
`MEM_SH : waddr_mask = 4'b0011;
`MEM_SW : waddr_mask = 4'b1111;
default : waddr_mask = 4'b0000;
endcase
end
always @ (posedge clk, negedge rstn) begin
if (~rstn) begin
mem_wb_rdy_reg <= 1'b0;
mem_wb_funct <= `LD_NOP;
mem_wb_data <= 'h0;
mem_wb_rsd <= 'h0;
end
else begin
if (mem_wb_rdy && mem_wb_ack) begin
mem_wb_rdy_reg <= ex_mem_rdy;
mem_wb_funct <= ex_mem_funct[`LD_FUNCT_W-1:0];
mem_wb_data <= ex_mem_data;
mem_wb_rsd <= ex_mem_wb_rsd;
end
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: prefetch.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: This is a very simple instruction fetch approach. It gets
// one instruction at a time. Future versions should pipeline
// fetches and perhaps even cache results--this doesn't do that.
// It should, however, be simple enough to get things running.
//
// The interface is fascinating. The 'i_pc' input wire is just
// a suggestion of what to load. Other wires may be loaded
// instead. i_pc is what must be output, not necessarily input.
//
// 20150919 -- Added support for the WB error signal. When reading an
// instruction results in this signal being raised, the pipefetch
// module will set an illegal instruction flag to be returned to
// the CPU together with the instruction. Hence, the ZipCPU
// can trap on it if necessary.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
// Flash requires a minimum of 4 clocks per byte to read, so that would be
// 4*(4bytes/32bit word) = 16 clocks per word read---and that's in pipeline
// mode which this prefetch does not support. In non--pipelined mode, the
// flash will require (16+6+6)*2 = 56 clocks plus 16 clocks per word read,
// or 72 clocks to fetch one instruction.
module prefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stalled_n, i_pc,
o_i, o_pc, o_valid, o_illegal,
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
parameter ADDRESS_WIDTH=32;
localparam AW=ADDRESS_WIDTH;
input wire i_clk, i_rst, i_new_pc, i_clear_cache,
i_stalled_n;
input wire [(AW-1):0] i_pc;
output reg [31:0] o_i;
output wire [(AW-1):0] o_pc;
output reg o_valid;
// Wishbone outputs
output reg o_wb_cyc, o_wb_stb;
output wire o_wb_we;
output reg [(AW-1):0] o_wb_addr;
output wire [31:0] o_wb_data;
// And return inputs
input wire i_wb_ack, i_wb_stall, i_wb_err;
input wire [31:0] i_wb_data;
output reg o_illegal;
assign o_wb_we = 1'b0;
assign o_wb_data = 32'h0000;
// Let's build it simple and upgrade later: For each instruction
// we do one bus cycle to get the instruction. Later we should
// pipeline this, but for now let's just do one at a time.
initial o_wb_cyc = 1'b0;
initial o_wb_stb = 1'b0;
initial o_wb_addr= 0;
always @(posedge i_clk)
if ((i_rst)||(i_wb_ack)||(i_wb_err))
begin
o_wb_cyc <= 1'b0;
o_wb_stb <= 1'b0;
end else if ((!o_wb_cyc)&&((i_stalled_n)||(!o_valid)||(i_new_pc)))
begin // Initiate a bus cycle
o_wb_cyc <= 1'b1;
o_wb_stb <= 1'b1;
end else if (o_wb_cyc) // Independent of ce
begin
if (!i_wb_stall)
o_wb_stb <= 1'b0;
end
reg invalid;
initial invalid = 1'b0;
always @(posedge i_clk)
if (!o_wb_cyc)
invalid <= 1'b0;
else if ((i_new_pc)||(i_clear_cache))
invalid <= 1'b1;
always @(posedge i_clk)
if (i_new_pc)
o_wb_addr <= i_pc;
else if ((!o_wb_cyc)&&(i_stalled_n)&&(!invalid))
o_wb_addr <= o_wb_addr + 1'b1;
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_ack))
o_i <= i_wb_data;
initial o_valid = 1'b0;
initial o_illegal = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(i_new_pc))
begin
o_valid <= 1'b0;
o_illegal <= 1'b0;
end else if ((o_wb_cyc)&&((i_wb_ack)||(i_wb_err)))
begin
o_valid <= (!invalid);
o_illegal <= ( i_wb_err)&&(!invalid);
end else if ((i_stalled_n)||(i_clear_cache)||(i_new_pc))
begin
o_valid <= 1'b0;
o_illegal <= 1'b0;
end
assign o_pc = o_wb_addr;
endmodule
|
// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
// This file represents the Composite Function Block for CfbOvercurrentDetector
module FB_CfbOvercurrentDetector
(
input wire clk,
//input events
input wire tick_eI,
input wire i_measured_eI,
input wire test_eI,
input wire set_eI,
input wire iSet_change_eI,
//output events
output wire b_change_eO,
//input variables
input wire unsigned [7:0] i_I,
input wire unsigned [7:0] iSet_I,
//output variables
output wire b_O ,
input reset
);
//Wires needed for event connections
wire tick_conn;
wire i_measured_conn;
wire iSet_change_conn;
wire test_conn;
wire set_conn;
wire curve_unsafe_conn;
wire sr_b_change_conn;
//Wires needed for data connections
wire unsigned [7:0] i_conn;
wire unsigned [7:0] iSet_conn;
wire sr_b_conn;
//top level I/O to signals
//input events
assign tick_conn = tick_eI;
assign i_measured_conn = i_measured_eI;
assign test_conn = test_eI;
assign set_conn = set_eI;
assign iSet_change_conn = iSet_change_eI;
//output events
assign b_change_eO = sr_b_change_conn;
//input variables
assign i_conn = i_I;
assign iSet_conn = iSet_I;
//output events
assign b_O = sr_b_conn;
// child I/O to signals
FB_BfbSetterResetter sr (
.clk(clk),
//event outputs
.b_change_eO(sr_b_change_conn),
//event inputs
.test_eI(test_conn),
.set_eI(set_conn),
.unsafe_eI(curve_unsafe_conn),
//data outputs
.b_O(sr_b_conn),
//data inputs
.reset(reset)
);
FB_BfbIDMTCurve curve (
.clk(clk),
//event outputs
.unsafe_eO(curve_unsafe_conn),
//event inputs
.tick_eI(tick_conn),
.i_measured_eI(i_measured_conn),
.iSet_change_eI(iSet_change_conn),
//data outputs
//data inputs
.i_I(i_conn),
.iSet_I(iSet_conn),
.reset(reset)
);
endmodule |
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