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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/13/2016 08:27:22 PM
// Design Name:
// Module Name: FullAdder
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FullAdder(
input [3:0] A,
input [3:0] B,
input Operation,
output [3:0] S,
output Cout
);
// Operation detects if subtraction or addition is being done
//assign B = B ^ {Operation, Operation, Operation, Operation};
wire carry_out1, carry_out2, carry_out3;
AdderSlice Bit0 (
.A(A[0]),
.B(B[0]), // or try B[0] ^ Operation
.S(S[0]),
.Cout(carry_out1),
.Cin(Operation)
);
AdderSlice Bit1 (
.A(A[1]),
.B(B[1] ),
.S(S[1]),
.Cout(carry_out2), //no overflow -> .Cout(S[2:0]),
.Cin(carry_out1)
);
AdderSlice Bit2 (
.A(A[2]),
.B(B[2] ),
.S(S[2]),
.Cout(carry_out3), //no overflow -> .Cout(S[2:0]),
.Cin(carry_out2)
);
AdderSlice Bit3 (
.A(A[3]),
.B(B[3] ),
.S(S[3]),
.Cout(Cout), //no overflow -> .Cout(S[2:0]),
.Cin(carry_out3)
);
endmodule
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 10
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
//`define VERBOSE
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
wire start;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_host_interface_tester s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
`ifdef VERBOSE $display (""); `endif
end
else begin
`ifdef VERBOSE $display ("Error unrecognized line: %h" % ch); `endif
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
`ifdef VERBOSE $display ("Sleep for %h Clock cycles", r_in_data_count); `endif
`SLEEP_CLK(r_in_data_count);
`ifdef VERBOSE $display ("Sleep Finished"); `endif
end
else begin
`ifdef VERBOSE $display ("Error: read_count = %h != 4", read_count); `endif
`ifdef VERBOSE $display ("Character: %h", ch); `endif
end
end
else begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
`endif
`ifdef VERBOSE $display ("Execute Command"); `endif
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
`ifdef VERBOSE $display ("TB: reading a new double word: %h", r_in_data); `endif
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
`ifdef VERBOSE $display ("Command Finished"); `endif
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
`ifdef VERBOSE $display ("TB: finished command"); `endif
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
`endif
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
`ifdef VERBOSE $display ("TB: sdram is ready"); `endif
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
else begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
`ifdef VERBOSE $display ("TB: Ping Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
`ifdef VERBOSE $display ("In Write Response"); `endif
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
`ifdef VERBOSE $display ("TB: Write Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Write Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
`ifdef VERBOSE $display ("TB: Read Response Good"); `endif
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
`ifdef VERBOSE $display ("TB: Read Response Bad (Malformed response: %h)", w_out_status); `endif
state <= FINISHED;
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
`ifdef VERBOSE $display ("TB: Read a 32bit data packet"); `endif
`ifdef VERBOSE $display ("TB: \tRead Data: %h", w_out_data); `endif
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
`ifdef VERBOSE $display ("Execute Command is low"); `endif
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
`ifdef VERBOSE $display("TB: Output Handler Recieved interrupt"); `endif
`ifdef VERBOSE $display("TB:\tcommand: %h", w_out_status); `endif
`ifdef VERBOSE $display("TB:\taddress: %h", w_out_address); `endif
`ifdef VERBOSE $display("TB:\tdata: %h", w_out_data); `endif
end
end//not reset
end
endmodule
|
//b12015 ROHIT PATIYAL
module UDivider(Quotient, Remainder, Dividend, Divisor);
output [31:0] Quotient;
output [31:0] Remainder;
input [31:0] Divisor;
input [31:0] Dividend;
wire [31:0] TR[0:32];
wire cin;
wire cout;
wire garbage;
stepof32 myStep1(TR[0], garbage, 0, Dividend[31], Divisor, 1);
stepof32 myStep2(TR[1], Quotient[31], TR[0], Dividend[30], Divisor, garbage);
stepof32 myStep3(TR[2], Quotient[30], TR[1], Dividend[29], Divisor, Quotient[31]);
stepof32 myStep4(TR[3], Quotient[29], TR[2], Dividend[28], Divisor, Quotient[30]);
stepof32 myStep5(TR[4], Quotient[28], TR[3], Dividend[27], Divisor, Quotient[29]);
stepof32 myStep6(TR[5], Quotient[27], TR[4], Dividend[26], Divisor, Quotient[28]);
stepof32 myStep7(TR[6], Quotient[26], TR[5], Dividend[25], Divisor, Quotient[27]);
stepof32 myStep8(TR[7], Quotient[25], TR[6], Dividend[24], Divisor, Quotient[26]);
stepof32 myStep9(TR[8], Quotient[24], TR[7], Dividend[23], Divisor, Quotient[25]);
stepof32 myStep10(TR[9], Quotient[23], TR[8], Dividend[22], Divisor, Quotient[24]);
stepof32 myStep11(TR[10], Quotient[22], TR[9], Dividend[21], Divisor, Quotient[23]);
stepof32 myStep12(TR[11], Quotient[21], TR[10], Dividend[20], Divisor, Quotient[22]);
stepof32 myStep13(TR[12], Quotient[20], TR[11], Dividend[19], Divisor, Quotient[21]);
stepof32 myStep14(TR[13], Quotient[19], TR[12], Dividend[18], Divisor, Quotient[20]);
stepof32 myStep15(TR[14], Quotient[18], TR[13], Dividend[17], Divisor, Quotient[19]);
stepof32 myStep16(TR[15], Quotient[17], TR[14], Dividend[16], Divisor, Quotient[18]);
stepof32 myStep17(TR[16], Quotient[16], TR[15], Dividend[15], Divisor, Quotient[17]);
stepof32 myStep18(TR[17], Quotient[15], TR[16], Dividend[14], Divisor, Quotient[16]);
stepof32 myStep19(TR[18], Quotient[14], TR[17], Dividend[13], Divisor, Quotient[15]);
stepof32 myStep20(TR[19], Quotient[13], TR[18], Dividend[12], Divisor, Quotient[14]);
stepof32 myStep21(TR[20], Quotient[12], TR[19], Dividend[11], Divisor, Quotient[13]);
stepof32 myStep22(TR[21], Quotient[11], TR[20], Dividend[10], Divisor, Quotient[12]);
stepof32 myStep23(TR[22], Quotient[10], TR[21], Dividend[9], Divisor, Quotient[11]);
stepof32 myStep24(TR[23], Quotient[9], TR[22], Dividend[8], Divisor, Quotient[10]);
stepof32 myStep25(TR[24], Quotient[8], TR[23], Dividend[7], Divisor, Quotient[9]);
stepof32 myStep26(TR[25], Quotient[7], TR[24], Dividend[6], Divisor, Quotient[8]);
stepof32 myStep27(TR[26], Quotient[6], TR[25], Dividend[5], Divisor, Quotient[7]);
stepof32 myStep28(TR[27], Quotient[5], TR[26], Dividend[4], Divisor, Quotient[6]);
stepof32 myStep29(TR[28], Quotient[4], TR[27], Dividend[3], Divisor, Quotient[5]);
stepof32 myStep30(TR[29], Quotient[3], TR[28], Dividend[2], Divisor, Quotient[4]);
stepof32 myStep31(TR[30], Quotient[2], TR[29], Dividend[1], Divisor, Quotient[3]);
stepof32 myStep32(TR[31], Quotient[1], TR[30], Dividend[0], Divisor, Quotient[2]);
laststepof32 myStep33(Remainder,Quotient[0],TR[31],Divisor,Quotient[1]); //Includes a step similar to stepof32
//$display ("HEllo");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTN_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DLRTN_BEHAVIORAL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_no_pg/sky130_fd_sc_hs__u_dl_p_r_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrtn (
RESET_B,
D ,
GATE_N ,
Q ,
VPWR ,
VGND
);
// Module ports
input RESET_B;
input D ;
input GATE_N ;
output Q ;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_hs__u_dl_p_r_no_pg u_dl_p_r_no_pg0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTN_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22A_BLACKBOX_V
`define SKY130_FD_SC_MS__O22A_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o22a (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22A_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__EDFXTP_FUNCTIONAL_PP_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_edf_p_pg/sky130_fd_sc_hs__u_edf_p_pg.v"
`celldefine
module sky130_fd_sc_hs__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_edf_p_pg `UNIT_DELAY u_edf_p_pg0 (buf_Q , D, CLK, DE, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXTP_FUNCTIONAL_PP_V |
// MBT 7/24/2014
// DDR or center/edge-aligned SDR source synchronous input channel
//
// this implements:
// incoming source-synchronous capture flops
// async fifo to go from source-synchronous domain to core domain
// outgoing token channel to go from core domain deque to out of chip
// outgoing source-synchronous launch flops for token
// programmable capture on either or both edges of the clock
//
// note, the default FIFO depth is set to 2^5
// based on the following calculation:
//
// 2 clks for channel crossing
// 3 clks for receive fifo crossing
// 1 clk for deque
// 3 clks for receive token fifo crossing
// 4 clks for token decimation
// 2 clks for channel crossing
// 3 clks for sender token fifo crossing
// 1 clk for sender credit counter adjust
// -----------
// 19 clks
//
// This leaves us with 13 elements of margin
// for FPGA inefficiency. Since the FPGA may run
// at 4X slower, this is equivalent to 3 FPGA cycles.
//
// Aside: SERDES make bandwidth-delay product much worse
// because they simultaneously increase bandwidth and delay!
//
// io_*: signals synchronous to io_clk_i
// core_*: signals synchronous to core_clk_i
//
// During reset, the SS output channel needs to toggle its input toggle clock.
// To do this, it must assert the two trigger lines (0x180 on { valid , data })
// and wait at least 2**(lg_credit_to_token_decimation_p+1) cycles and then deassert
// it. This will be routed around by the SS input channel and toggle the trigger
// clock line, allowing it be reset.
//
//
// perf fixme: data comes in at 64 bits per core cycle, but it is serialized
// to 32-bits per cycle in the core domain. thus in theory some assembler-like changes could
// allow for the in I/O data rate to be twice the core frequency. but the assembler
// may be on the core critical path.
//
`include "bsg_defines.v"
module bsg_source_sync_input #(parameter lg_fifo_depth_p=5
, parameter lg_credit_to_token_decimation_p=3
, parameter channel_width_p=8
)
(
// source synchronous input channel; coming from chip edge
input io_clk_i // sdi_sclk
, input io_reset_i // synchronous reset
, input io_token_bypass_i // {v,d[7]} controls token signal
, input [channel_width_p-1:0] io_data_i // sdi_data
, input io_valid_i // sdi_valid
, input [1:0] io_edge_i // bit vector of which
// edges to capture <pos, neg edge>
// 11=DDR
// 10=edge-aligned SDR
// 01=center-aligned SDR
//
, output io_token_r_o // sdi_token; output registered
// positive edge snoop
, output [channel_width_p:0] io_snoop_pos_r_o // { valid, data};
// negative edge snoop
, output [channel_width_p:0] io_snoop_neg_r_o // { valid, data};
// for calibration
, input io_trigger_mode_en_i // in trigger mode
, input io_trigger_mode_alt_en_i // use alternate trigger
// going into core; uses core clock
, input core_clk_i
, input core_reset_i // synchronous reset
, output [channel_width_p-1:0] core_data_o
, output core_valid_o
, input core_yumi_i // accept data if:
// core_valid_o high, and then
// core_yumi_i high
);
// ******************************************
// DDR capture registers
//
// we capture data on both edges. the negedge comes before the
// positive edge logically and hence is labeled 0. we delay
// the negedge so we can consider both data words on the same cycle.
//
// set_dont_touch these and apply the
// static timing rules
logic [channel_width_p-1:0] core_data_0, core_data_1
, io_data_0_r, io_data_1_r;
logic core_valid_0, core_valid_1
, io_valid_0_r, io_valid_1_r
, io_valid_negedge_r;
logic [channel_width_p-1:0] io_data_negedge_r;
// capture negedge data and valid
always @(negedge io_clk_i)
begin
io_data_negedge_r <= io_data_i;
io_valid_negedge_r <= io_valid_i;
end
// then capture posedge data and valid
always @(posedge io_clk_i)
begin
io_data_0_r <= io_data_negedge_r; io_valid_0_r <= io_valid_negedge_r;
io_data_1_r <= io_data_i; io_valid_1_r <= io_valid_i;
end
assign io_snoop_pos_r_o = {io_valid_1_r, io_data_1_r};
assign io_snoop_neg_r_o = {io_valid_0_r, io_data_0_r};
// ******************************************
// trigger_mode
//
// Trigger mode is used for alignment. We sample the input in bursts of 8 pairs
// and then send through the FIFO.
//
// In alternate mode, we capture the valid bit instead of
// a data bit. Which data bit should we substitute out?
// We don't want the alternate trigger wire to be next to the valid/ncmd line.
// GF28: valid (ncmd) bit is between data_0 and sclk.
// UCSD_BGA: valid (ncmd) bit is between data_3 and sclk.
// So substituting in for the top bit of the data should be fine for both cases.
//
//
wire [channel_width_p-1:0] io_data_0_r_swizzle = io_trigger_mode_alt_en_i
? {io_valid_0_r, io_data_0_r[0+:channel_width_p-1] }
: io_data_0_r;
wire [channel_width_p-1:0] io_data_1_r_swizzle = io_trigger_mode_alt_en_i
? {io_valid_1_r, io_data_1_r[0+:channel_width_p-1] }
: io_data_1_r;
wire io_trigger_mode_0, io_trigger_mode_1;
// when we are in trigger mode, we have not aligned bits yet
// so we have the risk of metastability, so we must synchronize
// both possible trigger bits.
// fixme: do these need launch flops?
bsg_sync_sync #(.width_p(1)) bssv
(.oclk_i(io_clk_i)
,.iclk_data_i(io_valid_1_r)
,.oclk_data_o(io_trigger_mode_0)
);
// note if you change the location of the trigger bit
// then you need to potentially change the calibration codes
bsg_sync_sync #(.width_p(1)) bssd
(.oclk_i(io_clk_i)
,.iclk_data_i(io_data_1_r[channel_width_p-1])
,.oclk_data_o(io_trigger_mode_1)
);
localparam lg_io_trigger_words_lp = 3;
logic io_trigger_line_r;
logic [lg_io_trigger_words_lp+1-1:0] io_trigger_count_r;
wire io_trigger_line = io_trigger_mode_alt_en_i
? io_trigger_mode_1
: io_trigger_mode_0;
wire io_trigger_mode_active = (| io_trigger_count_r);
always @(posedge io_clk_i)
if (io_reset_i)
begin
io_trigger_line_r <= 0;
io_trigger_count_r <= 0;
end
else
begin
// delay by one full clock cycle to detect transition
io_trigger_line_r <= io_trigger_line;
if (io_trigger_mode_active)
io_trigger_count_r <= io_trigger_count_r - 1;
else
// if trigger line switched over last cycle
// we go ahead and capture data
if (io_trigger_line ^ io_trigger_line_r)
io_trigger_count_r <= 2**(lg_io_trigger_words_lp);
end
// ******************************************
// clock-crossing async fifo (with DDR interface)
//
// we enque both DDR words side-by-side, with valid bits
// if either one of them is valid. this us allows us
// to reconcile the ordering of negedge versus posedge clock
//
wire io_async_fifo_full;
wire io_async_fifo_enq = io_trigger_mode_en_i
? io_trigger_mode_active // enque if we in trigger mode
: (io_valid_0_r | io_valid_1_r); // enque if either valid bit set
// synopsys translate_off
always @(negedge io_clk_i)
assert(!(io_async_fifo_full===1 && io_async_fifo_enq===1))
else $error("attempt to enque on full async fifo");
// synopsys translate_on
wire core_actual_deque;
wire core_valid_o_tmp;
bsg_async_fifo #(.lg_size_p(lg_fifo_depth_p) // 32 elements
,.width_p( (channel_width_p+1)*2 ) // room for both valids and
// for both data words
,.control_width_p(2)
) baf
(
.w_clk_i(io_clk_i)
,.w_reset_i(io_reset_i)
,.w_enq_i(io_async_fifo_enq)
,.w_data_i(io_trigger_mode_en_i
? { 1'b1 , 1'b1
, io_data_1_r_swizzle , io_data_0_r_swizzle}
: { io_valid_1_r & io_edge_i[1], io_valid_0_r & io_edge_i[0]
, io_data_1_r , io_data_0_r })
,.w_full_o(io_async_fifo_full)
,.r_clk_i(core_clk_i)
,.r_reset_i(core_reset_i)
,.r_deq_i(core_actual_deque)
,.r_data_o({core_valid_1, core_valid_0, core_data_1, core_data_0})
// there is data in the FIFO
,.r_valid_o(core_valid_o_tmp)
);
logic core_sent_0_want_to_send_1_r;
// send 1 if we already sent 0; or if there is no 0.
wire [channel_width_p-1:0] core_data_o_pre_twofer
= (core_sent_0_want_to_send_1_r | ~core_valid_0)
? core_data_1
: core_data_0;
wire core_valid_o_pre_twofer = core_valid_o_tmp; // remove inout warning from lint
wire core_twofer_ready;
// Oct 17, 2014
// we insert a minimal fifo here for two purposes;
// first, this reduces critical
// paths causes by excessive access times of the async fifo.
//
// second, it ensures that asynchronous paths end inside of this module
// and do not propogate out to other modules that may be attached, complicating
// timing assertions.
//
bsg_two_fifo #(.width_p(channel_width_p)) twofer
(.clk_i(core_clk_i)
,.reset_i(core_reset_i)
// we feed this into the local yumi, but only if it is valid
,.ready_o(core_twofer_ready)
,.data_i(core_data_o_pre_twofer)
,.v_i(core_valid_o_pre_twofer)
,.v_o(core_valid_o)
,.data_o(core_data_o)
,.yumi_i(core_yumi_i)
);
// a word was transferred to the two input fifo if ...
wire core_transfer_success = core_valid_o_tmp & core_twofer_ready;
/*
// deque if there was an actual transfer, AND (
assign core_actual_deque = core_transfer_success
// we sent the 0th word already,
// and just sent the 1st word, OR
& ((core_sent_0_want_to_send_1_r & core_valid_1)
// we sent the 0th word and there is no 1st word OR
// we sent the 1st word, and there is no 0th word
| (core_valid_0 ^ core_valid_1));
*/
assign core_actual_deque = core_transfer_success & ~(~core_sent_0_want_to_send_1_r & core_valid_1 & core_valid_0);
always @(posedge core_clk_i)
begin
if (core_reset_i)
core_sent_0_want_to_send_1_r <= 0;
else
// if we transferred data, but do not deque, we must have another word to
// transfer. mbt fixme: this was originally:
// core_transfer_success & ~core_actual_deque
// but had a bug. review further.
core_sent_0_want_to_send_1_r <= core_transfer_success
? ~core_actual_deque
: core_sent_0_want_to_send_1_r;
end
// **********************************************
// credit return
//
// these are credits coming from the receive end of the async fifo in the core clk
// domain and passing to the io clk domain and out of the chip.
//
logic [lg_fifo_depth_p+1-1:0] core_credits_gray_r_iosync
, core_credits_binary_r_iosync
, io_credits_sent_r, io_credits_sent_r_gray
, io_credits_sent_r_p1, io_credits_sent_r_p2;
bsg_async_ptr_gray #(.lg_size_p(lg_fifo_depth_p+1)) bapg
(.w_clk_i (core_clk_i)
,.w_reset_i(core_reset_i)
,.w_inc_i (core_transfer_success)
,.r_clk_i (io_clk_i)
,.w_ptr_binary_r_o() // not needed
,.w_ptr_gray_r_o() // not needed
,.w_ptr_gray_r_rsync_o(core_credits_gray_r_iosync)
);
// this logic allows us to return two credits at a time
// note: generally relies on power-of-twoness of io_credits_sent_r
// to do correct wrap around.
always_comb io_credits_sent_r_p1 = io_credits_sent_r+1;
always_comb io_credits_sent_r_p2 = io_credits_sent_r+2;
// which bit of the io_credits_sent_r counter we use determines
// the value of the token line in credits
//
//
// this signal's register should be placed right next to the I/O pad:
// glitch sensitive.
assign io_token_r_o = io_credits_sent_r[lg_credit_to_token_decimation_p];
// we actually absorb credits one or two at a time rather as fast as we can.
// this because otherwise we would not be slowing transition rates on the token
// signal, which is the whole point of tokens! this is slightly suboptimal,
// because if enough cycles have passed from the last
// time we sent a token, we could actually acknowledge things faster if we
// absorbed more than one credit at a time.
// that's okay. we skip this optimization.
// during token bypass mode, we hardwire the credit signal to the trigger mode signals;
// this gives the output channel control over the credit signal which
// allows it to toggle and reset the credit logic.
// the use of this trigger signal means that we should avoid the use of these
// two signals for calibration codes, so that we do not mix calibration codes
// when reset goes low with token reset operation, which would be difficult to avoid
// since generally we cannot control the timing of these reset signals when
// they cross asynchronous boundaries
// this is an optimized token increment system
// we actually gray code two options and compare against
// the incoming greycoded pointer. this is because it's cheaper
// to grey code than to de-gray code. moreover, we theorize it's cheaper
// to compute an incremented gray code than to add one to a pointer.
assign io_credits_sent_r_gray = (io_credits_sent_r >> 1) ^ io_credits_sent_r;
logic [lg_fifo_depth_p+1-1:0] io_credits_sent_p1_r_gray;
bsg_binary_plus_one_to_gray #(.width_p(lg_fifo_depth_p+1)) bsg_bp1_2g
(.binary_i(io_credits_sent_r)
,.gray_o(io_credits_sent_p1_r_gray)
);
wire empty_1 = (core_credits_gray_r_iosync != io_credits_sent_p1_r_gray);
wire empty_0 = (core_credits_gray_r_iosync != io_credits_sent_r_gray);
always @(posedge io_clk_i)
begin
if (io_token_bypass_i)
io_credits_sent_r <= { lg_fifo_depth_p+1
{ io_trigger_mode_1 & io_trigger_mode_0 } };
else
// we absorb up to two credits per cycles, since we receive at DDR,
// we need this to rate match the incoming data
// code is written like this because empty_1 is late relative to empty_0
io_credits_sent_r <= (empty_1
? (empty_0 ? io_credits_sent_r_p2 : io_credits_sent_r)
: (empty_0 ? io_credits_sent_r_p1 : io_credits_sent_r));
end
endmodule // bsg_source_sync_input
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_SYMBOL_V
`define SKY130_FD_SC_LP__A22OI_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_SYMBOL_V
|
module I2S_DAC(clk50M, sck, ws, sd,
//DAC_L, DAC_R
dac_dat,
outr,
sw1
);
//general
input wire clk50M;
//i2s
input wire sck, ws, sd;
//custom dac
//output wire DAC_L, DAC_R;
//r2r 8bit dac
output wire [7:0] dac_dat;
output wire outr;
input wire sw1;
//i2s receiver
wire [31:0] data_left;
wire [31:0] data_right;
i2s_receive2 rcv(.sck(sck),
.ws(ws),
.sd(sd),
.data_left(data_left),
.data_right(data_right));
assign outr = (data_left==data_right);
wire [31:0] us_data_left = data_left + 32'b10000000000000000000000000000000; //signed data in unsigned register. this is conversion
wire [31:0] us_data_right = data_right + 32'b10000000000000000000000000000000; //signed data in unsigned register. this is conversion
//assign dac_dat = us_data_right[31:31-7];
//dac regs cross domain
reg [31:0] word_l_;
//reg [31:0] word_r_;
reg [31:0] word_l__;
//reg [31:0] word_r__;
reg [7:0] word_l;
//reg [7:0] word_r;
wire clk200M;
pll200M pll(.inclk0(clk50M),
.c0(clk200M));
always @(posedge clk200M) begin
word_l_ <= (us_data_left);
//word_r_ <= (us_data_left);
word_l__ <= word_l_;
//word_r__ <= word_r_;
word_l <= word_l__[31:31-7];
//word_r <= word_r__[31:31-7];
end
//dacs
wire DAC_L, DAC_R;
ds8dac1 /*#(.width(8))*/ dac_l(.clk(clk200M),
.DACin(word_l),
.DACout(DAC_L));
//pwm8dac1 dac_r(.clk(clk200M),
// .in_data(word_r),
// .sout(DAC_R));
//standart 8 bit pwm dac
assign dac_dat = (sw1) ? {DAC_L,DAC_L,DAC_L,DAC_L,DAC_L,DAC_L,DAC_L,DAC_L} : word_l;
//assign dac_dat = us_data_right[31:31-7];
//hi pwm, lo r2r
//assign dac_dat = {word_l__[23],word_l__[22],word_l__[21],word_l__[20],word_l__[19],word_l__[18],word_l__[17],word_l__[16]};
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_sys.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`timescale 1ps/1ps
//------------------------------------------------------------
//Here We do the system level operation.
//------------------------------------------------------------
module bw_sys(/*AUTOARG*/
// Outputs
ssi_miso, ext_int_l, clk_stretch, warm_rst_l, temp_trig,
// Inputs
j_rst_l, jbus_gclk, ssi_sck, ssi_mosi
);
//input to system.
input j_rst_l;
input jbus_gclk;
input ssi_sck;
input ssi_mosi;
//output to ciop.
output ssi_miso;
output ext_int_l;
output clk_stretch;
output warm_rst_l;
output temp_trig;
//temp. registers
reg ssi_miso_r;
reg ext_int_l_r;
reg temp_trig_r;
reg clk_stretch_r;
//ok push button rst
reg ok_io, ok_reset, rst_val;
// initial values for all reg
initial begin
rst_val = 1 ;
ext_int_l_r = 1 ;
temp_trig_r = 0 ;
clk_stretch_r = 0;
end
//create wramrest signal.
assign warm_rst_l = rst_val ;
initial begin
ok_reset = 1;
end
//how many cores are turned on.
//assign and drive
assign ext_int_l = ext_int_l_r;
assign ssi_miso = ssi_miso_r;
assign temp_trig = temp_trig_r;
assign clk_stretch = clk_stretch_r;
initial
begin
ok_io = 0;
ext_int_l_r = 1;
ssi_miso_r = 0;
temp_trig_r = 0;
while (j_rst_l !== 0) @(posedge jbus_gclk) ;
@(posedge j_rst_l);//wait for the push button reset.
ok_io = 1;
end
//interface between ssi bus and io.
always @(posedge ssi_sck)begin
if(ok_io)$ssi_drive(
//input
ssi_mosi,
//ouput
ssi_miso_r,
);
end // always @ (posedge ssi_sck)
// jbus clk domain here.
// 2). warm reset
// 3). external interrupt
always @(posedge jbus_gclk)begin
if(ok_reset)begin
$pc_trigger_event(3,
rst_val,
ext_int_l_r,
temp_trig_r,
clk_stretch_r
);
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 29 22:11:05 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_xlconstant_0_1/system_xlconstant_0_1_sim_netlist.v
// Design : system_xlconstant_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *)
(* NotValidForBitStream *)
module system_xlconstant_0_1
(dout);
output [31:0]dout;
wire \<const0> ;
wire \<const1> ;
assign dout[31] = \<const0> ;
assign dout[30] = \<const0> ;
assign dout[29] = \<const0> ;
assign dout[28] = \<const0> ;
assign dout[27] = \<const0> ;
assign dout[26] = \<const0> ;
assign dout[25] = \<const0> ;
assign dout[24] = \<const0> ;
assign dout[23] = \<const0> ;
assign dout[22] = \<const0> ;
assign dout[21] = \<const0> ;
assign dout[20] = \<const0> ;
assign dout[19] = \<const0> ;
assign dout[18] = \<const0> ;
assign dout[17] = \<const0> ;
assign dout[16] = \<const0> ;
assign dout[15] = \<const0> ;
assign dout[14] = \<const0> ;
assign dout[13] = \<const1> ;
assign dout[12] = \<const0> ;
assign dout[11] = \<const0> ;
assign dout[10] = \<const1> ;
assign dout[9] = \<const1> ;
assign dout[8] = \<const1> ;
assign dout[7] = \<const0> ;
assign dout[6] = \<const0> ;
assign dout[5] = \<const0> ;
assign dout[4] = \<const1> ;
assign dout[3] = \<const0> ;
assign dout[2] = \<const0> ;
assign dout[1] = \<const0> ;
assign dout[0] = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module nukv_Read #(
parameter KEY_WIDTH = 128,
parameter META_WIDTH = 96,
parameter HASHADDR_WIDTH = 32,
parameter MEMADDR_WIDTH = 20
)
(
// Clock
input wire clk,
input wire rst,
input wire [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] input_data,
input wire input_valid,
output wire input_ready,
input wire [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] feedback_data,
input wire feedback_valid,
output wire feedback_ready,
output reg [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] output_data,
output reg output_valid,
input wire output_ready,
output reg [31:0] rdcmd_data,
output reg rdcmd_valid,
input wire rdcmd_ready
);
reg selectInputNext;
reg selectInput; //1 == input, 0==feedback
localparam [2:0]
ST_IDLE = 0,
ST_ISSUE_READ = 3,
ST_OUTPUT_KEY = 4;
reg [2:0] state;
wire[HASHADDR_WIDTH+KEY_WIDTH+META_WIDTH-1:0] in_data;
wire in_valid;
reg in_ready;
wire[31:0] hash_data;
assign in_data = (selectInput==1) ? input_data : feedback_data;
assign in_valid = (selectInput==1) ? input_valid : feedback_valid;
assign input_ready = (selectInput==1) ? in_ready : 0;
assign feedback_ready = (selectInput==1) ? 0 : in_ready;
assign hash_data = (selectInput==1) ? input_data[KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH] : feedback_data[KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH];
wire[MEMADDR_WIDTH-1:0] addr;
assign addr = hash_data[31:32 - MEMADDR_WIDTH] ^ hash_data[MEMADDR_WIDTH-1:0];
always @(posedge clk) begin
if (rst) begin
selectInput <= 1;
selectInputNext <= 0;
state <= ST_IDLE;
in_ready <= 0;
rdcmd_valid <= 0;
output_valid <= 0;
end
else begin
if (rdcmd_ready==1 && rdcmd_valid==1) begin
rdcmd_valid <= 0;
end
if (output_ready==1 && output_valid==1) begin
output_valid <= 0;
end
in_ready <= 0;
case (state)
ST_IDLE : begin
if (output_ready==1 && rdcmd_ready==1) begin
selectInput <= selectInputNext;
selectInputNext <= ~selectInputNext;
if (selectInputNext==1 && input_valid==0 && feedback_valid==1) begin
selectInput <= 0;
selectInputNext <= 1;
end
if (selectInputNext==0 && input_valid==1 && feedback_valid==0) begin
selectInput <= 1;
selectInputNext <= 0;
end
if (selectInput==1 && input_valid==1) begin
state <= ST_ISSUE_READ;
end
if (selectInput==0 && feedback_valid==1) begin
state <= ST_ISSUE_READ;
end
end
end
ST_ISSUE_READ: begin
if (in_data[KEY_WIDTH+META_WIDTH-4]==1) begin
// ignore this and don't send read!
end else begin
rdcmd_data <= addr;
rdcmd_valid <= 1;
rdcmd_data[31:MEMADDR_WIDTH] <= 0;
end
state <= ST_OUTPUT_KEY;
output_data <= in_data;
output_data[KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH] <= addr; //(in_data[KEY_WIDTH+META_WIDTH-1]==0) ? addr1 : addr2;
in_ready <= 1;
end
ST_OUTPUT_KEY: begin
if (output_ready==1) begin
output_valid <= 1;
state <= ST_IDLE;
end
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTN_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLRTN_PP_SYMBOL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTN_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_P_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_DFF_P_BLACKBOX_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dff$P (
Q ,
D ,
CLK
);
output Q ;
input D ;
input CLK;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_P_BLACKBOX_V
|
// Identifies the sequence 11101
// includes a overlap bit sequence as well
module jfsmMooreWithOverlap(dataout, clock, reset, datain);
output reg dataout;
input clock, reset, datain;
reg[2:0] cs, ns;
parameter a = 3'b000;
parameter b = 3'b001;
parameter c = 3'b010;
parameter d = 3'b011;
parameter e = 3'b100;
parameter f = 3'b101;
always @(posedge clock)
begin
if(reset)
cs <= a;
else
cs <= ns;
end
always @(cs, datain)
begin
case(cs)
a:
begin
if(datain)
ns <= b;
else
ns <= a;
end
b:
begin
if(datain)
ns <= c;
else
ns <= b;
end
c:
begin
if(datain)
ns <= d;
else
ns <= a;
end
d:
begin
if(datain)
ns <= d;
else
ns <= e;
end
e:
begin
if(datain)
ns <= f;
else
ns <= a;
end
f:
begin
if(datain)
ns <= c; // This has to be ns <= a; if we have to consider with overlap
else
ns <= a;
end
endcase
end
// This will assign the correct status to the dataout bit
always @(cs, datain)
begin
if ( cs == e && datain == 1 )
dataout <= 1;
else
dataout <= 0;
end
endmodule
|
module arbiter(/*AUTOARG*/
// Outputs
wb_m0_vcache_dat_o, wb_m0_vcache_ack_o, wb_m1_cpu_dat_o,
wb_m1_cpu_ack_o, wb_s0_cellram_wb_adr_o, wb_s0_cellram_wb_dat_o,
wb_s0_cellram_wb_sel_o, wb_s0_cellram_wb_stb_o,
wb_s0_cellram_wb_cyc_o, wb_s0_cellram_wb_we_o,
// Inputs
wb_clk, wb_rst, wb_m0_vcache_adr_i, wb_m0_vcache_dat_i,
wb_m0_vcache_sel_i, wb_m0_vcache_cyc_i, wb_m0_vcache_stb_i,
wb_m0_vcache_we_i, wb_m1_cpu_adr_i, wb_m1_cpu_dat_i,
wb_m1_cpu_sel_i, wb_m1_cpu_cyc_i, wb_m1_cpu_stb_i, wb_m1_cpu_we_i,
wb_s0_cellram_wb_dat_i, wb_s0_cellram_wb_ack_i
//
,cellram_mst_sel
);
input wire wb_clk, wb_rst;
input wire [31:0] wb_m0_vcache_adr_i;
input wire [31:0] wb_m0_vcache_dat_i;
input wire [3:0] wb_m0_vcache_sel_i;
input wire wb_m0_vcache_cyc_i;
input wire wb_m0_vcache_stb_i;
input wire wb_m0_vcache_we_i;
output wire [31:0] wb_m0_vcache_dat_o;
output wire wb_m0_vcache_ack_o;
input wire [31:0] wb_m1_cpu_adr_i;
input wire [31:0] wb_m1_cpu_dat_i;
input wire [3:0] wb_m1_cpu_sel_i;
input wire wb_m1_cpu_cyc_i;
input wire wb_m1_cpu_stb_i;
input wire wb_m1_cpu_we_i;
output wire [31:0] wb_m1_cpu_dat_o;
output wire wb_m1_cpu_ack_o;
output wire [31:0] wb_s0_cellram_wb_adr_o;
output wire [31:0] wb_s0_cellram_wb_dat_o;
output wire [3:0] wb_s0_cellram_wb_sel_o;
output wire wb_s0_cellram_wb_stb_o;
output wire wb_s0_cellram_wb_cyc_o;
output wire wb_s0_cellram_wb_we_o;
input wire [31:0] wb_s0_cellram_wb_dat_i;
input wire wb_s0_cellram_wb_ack_i;
//output wire wb_m1_cpu_gnt;
//output wire wb_m0_vcache_gnt;
output reg [1:0] cellram_mst_sel;
//assign cellram_mst_sel[1] = wb_m0_vcache_cyc_i & wb_m0_vcache_stb_i
//& !(cellram_mst_sel[1] & (wb_s0_cellram_wb_ack_i | cellram_arb_reset))
// ;
//assign cellram_mst_sel[0] = !cellram_mst_sel[1] & wb_m1_cpu_cyc_i & wb_m1_cpu_stb_i
//& !(cellram_mst_sel[0] & (wb_s0_cellram_wb_ack_i | cellram_arb_reset))
// ;
reg [9:0] cellram_arb_timeout;
wire cellram_arb_reset;
//assign wb_m1_cpu_gnt = cellram_mst_sel[0];
//assign wb_m0_vcache_gnt = cellram_mst_sel[1];
always @(posedge wb_clk)
if (wb_rst)
cellram_mst_sel <= 0;
else begin
if (cellram_mst_sel==2'b00) begin
/* wait for new access from masters. vcache takes priority */
if (wb_m0_vcache_cyc_i & wb_m0_vcache_stb_i) //if (wbs_d_cellram_cyc_i & wbs_d_cellram_stb_i)
cellram_mst_sel[1] <= 1;
else if (wb_m1_cpu_cyc_i & wb_m1_cpu_stb_i) //else if (wbs_i_cellram_cyc_i & wbs_i_cellram_stb_i)
cellram_mst_sel[0] <= 1;
end
else begin
if (wb_s0_cellram_wb_ack_i) //| cellram_arb_reset) //TODO: reset
cellram_mst_sel <= 0;
end // else: !if(cellram_mst_sel==2'b00)
end // else: !if(wb_rst)
reg [3:0] cellram_rst_counter;
always @(posedge wb_clk or posedge wb_rst)
if (wb_rst)
cellram_rst_counter <= 4'hf;
else if (|cellram_rst_counter)
cellram_rst_counter <= cellram_rst_counter - 1;
assign wb_s0_cellram_wb_adr_o = cellram_mst_sel[0] ? wb_m1_cpu_adr_i :
wb_m0_vcache_adr_i;
assign wb_s0_cellram_wb_dat_o = cellram_mst_sel[0] ? wb_m1_cpu_dat_i :
wb_m0_vcache_dat_i;
assign wb_s0_cellram_wb_stb_o = (cellram_mst_sel[0] ? wb_m1_cpu_stb_i :
cellram_mst_sel[1] ? wb_m0_vcache_stb_i : 0) &
!(|cellram_rst_counter);
assign wb_s0_cellram_wb_cyc_o = cellram_mst_sel[0] ? wb_m1_cpu_cyc_i :
cellram_mst_sel[1] ? wb_m0_vcache_cyc_i : 0;
assign wb_s0_cellram_wb_we_o = cellram_mst_sel[0] ? wb_m1_cpu_we_i :
wb_m0_vcache_we_i;
assign wb_s0_cellram_wb_sel_o = cellram_mst_sel[0] ? wb_m1_cpu_sel_i :
wb_m0_vcache_sel_i;
assign wb_m1_cpu_dat_o = wb_s0_cellram_wb_dat_i;
assign wb_m0_vcache_dat_o = wb_s0_cellram_wb_dat_i;
assign wb_m1_cpu_ack_o = wb_s0_cellram_wb_ack_i & cellram_mst_sel[0];
assign wb_m0_vcache_ack_o = wb_s0_cellram_wb_ack_i & cellram_mst_sel[1];
assign wb_m1_cpu_err_o = cellram_arb_reset & cellram_mst_sel[0];
assign wb_m1_cpu_rty_o = 0;
assign wb_m0_vcache_err_o = cellram_arb_reset & cellram_mst_sel[1];
assign wb_m0_vcache_rty_o = 0;
always @(posedge wb_clk)
if (wb_rst)
cellram_arb_timeout <= 0;
else if (wb_s0_cellram_wb_ack_i)
cellram_arb_timeout <= 0;
else if (wb_s0_cellram_wb_stb_o & wb_s0_cellram_wb_cyc_o)
cellram_arb_timeout <= cellram_arb_timeout + 1;
assign cellram_arb_reset = (&cellram_arb_timeout);
endmodule
|
`timescale 1ps/1ps
module aurora_64b66b_25p4G_gt_gtye4_common_wrapper (
input [0:0] GTYE4_COMMON_BGBYPASSB,
input [0:0] GTYE4_COMMON_BGMONITORENB,
input [0:0] GTYE4_COMMON_BGPDB,
input [4:0] GTYE4_COMMON_BGRCALOVRD,
input [0:0] GTYE4_COMMON_BGRCALOVRDENB,
input [15:0] GTYE4_COMMON_DRPADDR,
input [0:0] GTYE4_COMMON_DRPCLK,
input [15:0] GTYE4_COMMON_DRPDI,
input [0:0] GTYE4_COMMON_DRPEN,
input [0:0] GTYE4_COMMON_DRPWE,
input [0:0] GTYE4_COMMON_GTGREFCLK0,
input [0:0] GTYE4_COMMON_GTGREFCLK1,
input [0:0] GTYE4_COMMON_GTNORTHREFCLK00,
input [0:0] GTYE4_COMMON_GTNORTHREFCLK01,
input [0:0] GTYE4_COMMON_GTNORTHREFCLK10,
input [0:0] GTYE4_COMMON_GTNORTHREFCLK11,
input [0:0] GTYE4_COMMON_GTREFCLK00,
input [0:0] GTYE4_COMMON_GTREFCLK01,
input [0:0] GTYE4_COMMON_GTREFCLK10,
input [0:0] GTYE4_COMMON_GTREFCLK11,
input [0:0] GTYE4_COMMON_GTSOUTHREFCLK00,
input [0:0] GTYE4_COMMON_GTSOUTHREFCLK01,
input [0:0] GTYE4_COMMON_GTSOUTHREFCLK10,
input [0:0] GTYE4_COMMON_GTSOUTHREFCLK11,
input [2:0] GTYE4_COMMON_PCIERATEQPLL0,
input [2:0] GTYE4_COMMON_PCIERATEQPLL1,
input [7:0] GTYE4_COMMON_PMARSVD0,
input [7:0] GTYE4_COMMON_PMARSVD1,
input [0:0] GTYE4_COMMON_QPLL0CLKRSVD0,
input [0:0] GTYE4_COMMON_QPLL0CLKRSVD1,
input [7:0] GTYE4_COMMON_QPLL0FBDIV,
input [0:0] GTYE4_COMMON_QPLL0LOCKDETCLK,
input [0:0] GTYE4_COMMON_QPLL0LOCKEN,
input [0:0] GTYE4_COMMON_QPLL0PD,
input [2:0] GTYE4_COMMON_QPLL0REFCLKSEL,
input [0:0] GTYE4_COMMON_QPLL0RESET,
input [0:0] GTYE4_COMMON_QPLL1CLKRSVD0,
input [0:0] GTYE4_COMMON_QPLL1CLKRSVD1,
input [7:0] GTYE4_COMMON_QPLL1FBDIV,
input [0:0] GTYE4_COMMON_QPLL1LOCKDETCLK,
input [0:0] GTYE4_COMMON_QPLL1LOCKEN,
input [0:0] GTYE4_COMMON_QPLL1PD,
input [2:0] GTYE4_COMMON_QPLL1REFCLKSEL,
input [0:0] GTYE4_COMMON_QPLL1RESET,
input [7:0] GTYE4_COMMON_QPLLRSVD1,
input [4:0] GTYE4_COMMON_QPLLRSVD2,
input [4:0] GTYE4_COMMON_QPLLRSVD3,
input [7:0] GTYE4_COMMON_QPLLRSVD4,
input [0:0] GTYE4_COMMON_RCALENB,
input [24:0] GTYE4_COMMON_SDM0DATA,
input [0:0] GTYE4_COMMON_SDM0RESET,
input [0:0] GTYE4_COMMON_SDM0TOGGLE,
input [1:0] GTYE4_COMMON_SDM0WIDTH,
input [24:0] GTYE4_COMMON_SDM1DATA,
input [0:0] GTYE4_COMMON_SDM1RESET,
input [0:0] GTYE4_COMMON_SDM1TOGGLE,
input [1:0] GTYE4_COMMON_SDM1WIDTH,
input [0:0] GTYE4_COMMON_UBCFGSTREAMEN,
input [15:0] GTYE4_COMMON_UBDO,
input [0:0] GTYE4_COMMON_UBDRDY,
input [0:0] GTYE4_COMMON_UBENABLE,
input [1:0] GTYE4_COMMON_UBGPI,
input [1:0] GTYE4_COMMON_UBINTR,
input [0:0] GTYE4_COMMON_UBIOLMBRST,
input [0:0] GTYE4_COMMON_UBMBRST,
input [0:0] GTYE4_COMMON_UBMDMCAPTURE,
input [0:0] GTYE4_COMMON_UBMDMDBGRST,
input [0:0] GTYE4_COMMON_UBMDMDBGUPDATE,
input [3:0] GTYE4_COMMON_UBMDMREGEN,
input [0:0] GTYE4_COMMON_UBMDMSHIFT,
input [0:0] GTYE4_COMMON_UBMDMSYSRST,
input [0:0] GTYE4_COMMON_UBMDMTCK,
input [0:0] GTYE4_COMMON_UBMDMTDI,
output [15:0] GTYE4_COMMON_DRPDO,
output [0:0] GTYE4_COMMON_DRPRDY,
output [7:0] GTYE4_COMMON_PMARSVDOUT0,
output [7:0] GTYE4_COMMON_PMARSVDOUT1,
output [0:0] GTYE4_COMMON_QPLL0FBCLKLOST,
output [0:0] GTYE4_COMMON_QPLL0LOCK,
output [0:0] GTYE4_COMMON_QPLL0OUTCLK,
output [0:0] GTYE4_COMMON_QPLL0OUTREFCLK,
output [0:0] GTYE4_COMMON_QPLL0REFCLKLOST,
output [0:0] GTYE4_COMMON_QPLL1FBCLKLOST,
output [0:0] GTYE4_COMMON_QPLL1LOCK,
output [0:0] GTYE4_COMMON_QPLL1OUTCLK,
output [0:0] GTYE4_COMMON_QPLL1OUTREFCLK,
output [0:0] GTYE4_COMMON_QPLL1REFCLKLOST,
output [7:0] GTYE4_COMMON_QPLLDMONITOR0,
output [7:0] GTYE4_COMMON_QPLLDMONITOR1,
output [0:0] GTYE4_COMMON_REFCLKOUTMONITOR0,
output [0:0] GTYE4_COMMON_REFCLKOUTMONITOR1,
output [1:0] GTYE4_COMMON_RXRECCLK0SEL,
output [1:0] GTYE4_COMMON_RXRECCLK1SEL,
output [3:0] GTYE4_COMMON_SDM0FINALOUT,
output [14:0] GTYE4_COMMON_SDM0TESTDATA,
output [3:0] GTYE4_COMMON_SDM1FINALOUT,
output [14:0] GTYE4_COMMON_SDM1TESTDATA,
output [15:0] GTYE4_COMMON_UBDADDR,
output [0:0] GTYE4_COMMON_UBDEN,
output [15:0] GTYE4_COMMON_UBDI,
output [0:0] GTYE4_COMMON_UBDWE,
output [0:0] GTYE4_COMMON_UBMDMTDO,
output [0:0] GTYE4_COMMON_UBRSVDOUT,
output [0:0] GTYE4_COMMON_UBTXUART
);
gtwizard_ultrascale_v1_7_1_gtye4_common #(
.GTYE4_COMMON_AEN_QPLL0_FBDIV (1'b1),
.GTYE4_COMMON_AEN_QPLL1_FBDIV (1'b1),
.GTYE4_COMMON_AEN_SDM0TOGGLE (1'b0),
.GTYE4_COMMON_AEN_SDM1TOGGLE (1'b0),
.GTYE4_COMMON_A_SDM0TOGGLE (1'b0),
.GTYE4_COMMON_A_SDM1DATA_HIGH (9'b000000000),
.GTYE4_COMMON_A_SDM1DATA_LOW (16'b0000000000000000),
.GTYE4_COMMON_A_SDM1TOGGLE (1'b0),
.GTYE4_COMMON_BGBYPASSB_TIE_EN (1'b0),
.GTYE4_COMMON_BGBYPASSB_VAL (1'b1),
.GTYE4_COMMON_BGMONITORENB_TIE_EN (1'b0),
.GTYE4_COMMON_BGMONITORENB_VAL (1'b1),
.GTYE4_COMMON_BGPDB_TIE_EN (1'b0),
.GTYE4_COMMON_BGPDB_VAL (1'b1),
.GTYE4_COMMON_BGRCALOVRDENB_TIE_EN (1'b0),
.GTYE4_COMMON_BGRCALOVRDENB_VAL (1'b1),
.GTYE4_COMMON_BGRCALOVRD_TIE_EN (1'b0),
.GTYE4_COMMON_BGRCALOVRD_VAL (5'b10000),
.GTYE4_COMMON_BIAS_CFG0 (16'b0000000000000000),
.GTYE4_COMMON_BIAS_CFG1 (16'b0000000000000000),
.GTYE4_COMMON_BIAS_CFG2 (16'b0000010100100100),
.GTYE4_COMMON_BIAS_CFG3 (16'b0000000001000001),
.GTYE4_COMMON_BIAS_CFG4 (16'b0000000000010000),
.GTYE4_COMMON_BIAS_CFG_RSVD (16'b0000000000000000),
.GTYE4_COMMON_COMMON_CFG0 (16'b0000000000000000),
.GTYE4_COMMON_COMMON_CFG1 (16'b0000000000000000),
.GTYE4_COMMON_DRPADDR_TIE_EN (1'b0),
.GTYE4_COMMON_DRPADDR_VAL (16'b0000000000000000),
.GTYE4_COMMON_DRPCLK_TIE_EN (1'b0),
.GTYE4_COMMON_DRPCLK_VAL (1'b0),
.GTYE4_COMMON_DRPDI_TIE_EN (1'b0),
.GTYE4_COMMON_DRPDI_VAL (16'b0000000000000000),
.GTYE4_COMMON_DRPEN_TIE_EN (1'b0),
.GTYE4_COMMON_DRPEN_VAL (1'b0),
.GTYE4_COMMON_DRPWE_TIE_EN (1'b0),
.GTYE4_COMMON_DRPWE_VAL (1'b0),
.GTYE4_COMMON_GTGREFCLK0_TIE_EN (1'b0),
.GTYE4_COMMON_GTGREFCLK0_VAL (1'b0),
.GTYE4_COMMON_GTGREFCLK1_TIE_EN (1'b0),
.GTYE4_COMMON_GTGREFCLK1_VAL (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK00_TIE_EN (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK00_VAL (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK01_TIE_EN (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK01_VAL (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK10_TIE_EN (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK10_VAL (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK11_TIE_EN (1'b0),
.GTYE4_COMMON_GTNORTHREFCLK11_VAL (1'b0),
.GTYE4_COMMON_GTREFCLK00_TIE_EN (1'b0),
.GTYE4_COMMON_GTREFCLK00_VAL (1'b0),
.GTYE4_COMMON_GTREFCLK01_TIE_EN (1'b0),
.GTYE4_COMMON_GTREFCLK01_VAL (1'b0),
.GTYE4_COMMON_GTREFCLK10_TIE_EN (1'b0),
.GTYE4_COMMON_GTREFCLK10_VAL (1'b0),
.GTYE4_COMMON_GTREFCLK11_TIE_EN (1'b0),
.GTYE4_COMMON_GTREFCLK11_VAL (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK00_TIE_EN (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK00_VAL (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK01_TIE_EN (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK01_VAL (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK10_TIE_EN (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK10_VAL (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK11_TIE_EN (1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK11_VAL (1'b0),
.GTYE4_COMMON_PCIERATEQPLL0_TIE_EN (1'b0),
.GTYE4_COMMON_PCIERATEQPLL0_VAL (3'b000),
.GTYE4_COMMON_PCIERATEQPLL1_TIE_EN (1'b0),
.GTYE4_COMMON_PCIERATEQPLL1_VAL (3'b000),
.GTYE4_COMMON_PMARSVD0_TIE_EN (1'b0),
.GTYE4_COMMON_PMARSVD0_VAL (8'b00000000),
.GTYE4_COMMON_PMARSVD1_TIE_EN (1'b0),
.GTYE4_COMMON_PMARSVD1_VAL (8'b00000000),
.GTYE4_COMMON_POR_CFG (16'b0000000000000000),
.GTYE4_COMMON_PPF0_CFG (16'b0000100000000000),
.GTYE4_COMMON_PPF1_CFG (16'b0000011000000000),
.GTYE4_COMMON_QPLL0CLKOUT_RATE ("FULL"),
.GTYE4_COMMON_QPLL0CLKRSVD0_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0CLKRSVD0_VAL (1'b0),
.GTYE4_COMMON_QPLL0CLKRSVD1_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0CLKRSVD1_VAL (1'b0),
.GTYE4_COMMON_QPLL0FBDIV_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0FBDIV_VAL (8'b00000000),
.GTYE4_COMMON_QPLL0LOCKDETCLK_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0LOCKDETCLK_VAL (1'b0),
.GTYE4_COMMON_QPLL0LOCKEN_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0LOCKEN_VAL (1'b1),
.GTYE4_COMMON_QPLL0PD_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0PD_VAL (1'b0),
.GTYE4_COMMON_QPLL0REFCLKSEL_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0REFCLKSEL_VAL (3'b001),
.GTYE4_COMMON_QPLL0RESET_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL0RESET_VAL (1'b0),
.GTYE4_COMMON_QPLL0_CFG0 (16'b0011001100011100),
.GTYE4_COMMON_QPLL0_CFG1 (16'b1101000000111000),
.GTYE4_COMMON_QPLL0_CFG1_G3 (16'b1101000000111000),
.GTYE4_COMMON_QPLL0_CFG2 (16'b0000111111000011),
.GTYE4_COMMON_QPLL0_CFG2_G3 (16'b0000111111000011),
.GTYE4_COMMON_QPLL0_CFG3 (16'b0000000100100000),
.GTYE4_COMMON_QPLL0_CFG4 (16'b0000000010000100),
.GTYE4_COMMON_QPLL0_CP (10'b0011111111),
.GTYE4_COMMON_QPLL0_CP_G3 (10'b0000001111),
.GTYE4_COMMON_QPLL0_FBDIV (127),
.GTYE4_COMMON_QPLL0_FBDIV_G3 (160),
.GTYE4_COMMON_QPLL0_INIT_CFG0 (16'b0000001010110010),
.GTYE4_COMMON_QPLL0_INIT_CFG1 (8'b00000000),
.GTYE4_COMMON_QPLL0_LOCK_CFG (16'b0010010111101000),
.GTYE4_COMMON_QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
.GTYE4_COMMON_QPLL0_LPF (10'b1000011111),
.GTYE4_COMMON_QPLL0_LPF_G3 (10'b0111010101),
.GTYE4_COMMON_QPLL0_PCI_EN (1'b0),
.GTYE4_COMMON_QPLL0_RATE_SW_USE_DRP (1'b1),
.GTYE4_COMMON_QPLL0_REFCLK_DIV (1),
.GTYE4_COMMON_QPLL0_SDM_CFG0 (16'b0000000010000000),
.GTYE4_COMMON_QPLL0_SDM_CFG1 (16'b0000000000000000),
.GTYE4_COMMON_QPLL0_SDM_CFG2 (16'b0000000000000000),
.GTYE4_COMMON_QPLL1CLKOUT_RATE ("HALF"),
.GTYE4_COMMON_QPLL1CLKRSVD0_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1CLKRSVD0_VAL (1'b0),
.GTYE4_COMMON_QPLL1CLKRSVD1_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1CLKRSVD1_VAL (1'b0),
.GTYE4_COMMON_QPLL1FBDIV_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1FBDIV_VAL (8'b00000000),
.GTYE4_COMMON_QPLL1LOCKDETCLK_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1LOCKDETCLK_VAL (1'b0),
.GTYE4_COMMON_QPLL1LOCKEN_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1LOCKEN_VAL (1'b0),
.GTYE4_COMMON_QPLL1PD_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1PD_VAL (1'b1),
.GTYE4_COMMON_QPLL1REFCLKSEL_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1REFCLKSEL_VAL (3'b001),
.GTYE4_COMMON_QPLL1RESET_TIE_EN (1'b0),
.GTYE4_COMMON_QPLL1RESET_VAL (1'b1),
.GTYE4_COMMON_QPLL1_CFG0 (16'b0011001100011100),
.GTYE4_COMMON_QPLL1_CFG1 (16'b1101000000111000),
.GTYE4_COMMON_QPLL1_CFG1_G3 (16'b1101000000111000),
.GTYE4_COMMON_QPLL1_CFG2 (16'b0000111111000011),
.GTYE4_COMMON_QPLL1_CFG2_G3 (16'b0000111111000011),
.GTYE4_COMMON_QPLL1_CFG3 (16'b0000000100100000),
.GTYE4_COMMON_QPLL1_CFG4 (16'b0000000000000010),
.GTYE4_COMMON_QPLL1_CP (10'b0011111111),
.GTYE4_COMMON_QPLL1_CP_G3 (10'b0001111111),
.GTYE4_COMMON_QPLL1_FBDIV (66),
.GTYE4_COMMON_QPLL1_FBDIV_G3 (80),
.GTYE4_COMMON_QPLL1_INIT_CFG0 (16'b0000001010110010),
.GTYE4_COMMON_QPLL1_INIT_CFG1 (8'b00000000),
.GTYE4_COMMON_QPLL1_LOCK_CFG (16'b0010010111101000),
.GTYE4_COMMON_QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
.GTYE4_COMMON_QPLL1_LPF (10'b1000011111),
.GTYE4_COMMON_QPLL1_LPF_G3 (10'b0111010100),
.GTYE4_COMMON_QPLL1_PCI_EN (1'b0),
.GTYE4_COMMON_QPLL1_RATE_SW_USE_DRP (1'b1),
.GTYE4_COMMON_QPLL1_REFCLK_DIV (1),
.GTYE4_COMMON_QPLL1_SDM_CFG0 (16'b0000000010000000),
.GTYE4_COMMON_QPLL1_SDM_CFG1 (16'b0000000000000000),
.GTYE4_COMMON_QPLL1_SDM_CFG2 (16'b0000000000000000),
.GTYE4_COMMON_QPLLRSVD1_TIE_EN (1'b0),
.GTYE4_COMMON_QPLLRSVD1_VAL (8'b00000000),
.GTYE4_COMMON_QPLLRSVD2_TIE_EN (1'b0),
.GTYE4_COMMON_QPLLRSVD2_VAL (5'b00000),
.GTYE4_COMMON_QPLLRSVD3_TIE_EN (1'b0),
.GTYE4_COMMON_QPLLRSVD3_VAL (5'b00000),
.GTYE4_COMMON_QPLLRSVD4_TIE_EN (1'b0),
.GTYE4_COMMON_QPLLRSVD4_VAL (8'b00000000),
.GTYE4_COMMON_RCALENB_TIE_EN (1'b0),
.GTYE4_COMMON_RCALENB_VAL (1'b1),
.GTYE4_COMMON_RSVD_ATTR0 (16'b0000000000000000),
.GTYE4_COMMON_RSVD_ATTR1 (16'b0000000000000000),
.GTYE4_COMMON_RSVD_ATTR2 (16'b0000000000000000),
.GTYE4_COMMON_RSVD_ATTR3 (16'b0000000000000000),
.GTYE4_COMMON_RXRECCLKOUT0_SEL (2'b00),
.GTYE4_COMMON_RXRECCLKOUT1_SEL (2'b00),
.GTYE4_COMMON_SARC_ENB (1'b0),
.GTYE4_COMMON_SARC_SEL (1'b0),
.GTYE4_COMMON_SDM0DATA_TIE_EN (1'b0),
.GTYE4_COMMON_SDM0DATA_VAL (25'b0000000000000000000000000),
.GTYE4_COMMON_SDM0INITSEED0_0 (16'b0000000100010001),
.GTYE4_COMMON_SDM0INITSEED0_1 (9'b000010001),
.GTYE4_COMMON_SDM0RESET_TIE_EN (1'b0),
.GTYE4_COMMON_SDM0RESET_VAL (1'b0),
.GTYE4_COMMON_SDM0TOGGLE_TIE_EN (1'b0),
.GTYE4_COMMON_SDM0TOGGLE_VAL (1'b0),
.GTYE4_COMMON_SDM0WIDTH_TIE_EN (1'b0),
.GTYE4_COMMON_SDM0WIDTH_VAL (2'b00),
.GTYE4_COMMON_SDM1DATA_TIE_EN (1'b0),
.GTYE4_COMMON_SDM1DATA_VAL (25'b0000000000000000000000000),
.GTYE4_COMMON_SDM1INITSEED0_0 (16'b0000000100010001),
.GTYE4_COMMON_SDM1INITSEED0_1 (9'b000010001),
.GTYE4_COMMON_SDM1RESET_TIE_EN (1'b0),
.GTYE4_COMMON_SDM1RESET_VAL (1'b0),
.GTYE4_COMMON_SDM1TOGGLE_TIE_EN (1'b0),
.GTYE4_COMMON_SDM1TOGGLE_VAL (1'b0),
.GTYE4_COMMON_SDM1WIDTH_TIE_EN (1'b0),
.GTYE4_COMMON_SDM1WIDTH_VAL (2'b00),
.GTYE4_COMMON_SIM_DEVICE ("ULTRASCALE_PLUS"),
.GTYE4_COMMON_SIM_MODE ("FAST"),
.GTYE4_COMMON_SIM_RESET_SPEEDUP ("TRUE"),
.GTYE4_COMMON_UBCFGSTREAMEN_TIE_EN (1'b0),
.GTYE4_COMMON_UBCFGSTREAMEN_VAL (1'b0),
.GTYE4_COMMON_UBDO_TIE_EN (1'b0),
.GTYE4_COMMON_UBDO_VAL (16'b0000000000000000),
.GTYE4_COMMON_UBDRDY_TIE_EN (1'b0),
.GTYE4_COMMON_UBDRDY_VAL (1'b0),
.GTYE4_COMMON_UBENABLE_TIE_EN (1'b0),
.GTYE4_COMMON_UBENABLE_VAL (1'b0),
.GTYE4_COMMON_UBGPI_TIE_EN (1'b0),
.GTYE4_COMMON_UBGPI_VAL (2'b00),
.GTYE4_COMMON_UBINTR_TIE_EN (1'b0),
.GTYE4_COMMON_UBINTR_VAL (2'b00),
.GTYE4_COMMON_UBIOLMBRST_TIE_EN (1'b0),
.GTYE4_COMMON_UBIOLMBRST_VAL (1'b0),
.GTYE4_COMMON_UBMBRST_TIE_EN (1'b0),
.GTYE4_COMMON_UBMBRST_VAL (1'b0),
.GTYE4_COMMON_UBMDMCAPTURE_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMCAPTURE_VAL (1'b0),
.GTYE4_COMMON_UBMDMDBGRST_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMDBGRST_VAL (1'b0),
.GTYE4_COMMON_UBMDMDBGUPDATE_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMDBGUPDATE_VAL (1'b0),
.GTYE4_COMMON_UBMDMREGEN_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMREGEN_VAL (4'b0000),
.GTYE4_COMMON_UBMDMSHIFT_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMSHIFT_VAL (1'b0),
.GTYE4_COMMON_UBMDMSYSRST_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMSYSRST_VAL (1'b0),
.GTYE4_COMMON_UBMDMTCK_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMTCK_VAL (1'b0),
.GTYE4_COMMON_UBMDMTDI_TIE_EN (1'b0),
.GTYE4_COMMON_UBMDMTDI_VAL (1'b0),
.GTYE4_COMMON_UB_CFG0 (16'b0000000000000000),
.GTYE4_COMMON_UB_CFG1 (16'b0000000000000000),
.GTYE4_COMMON_UB_CFG2 (16'b0000000000000000),
.GTYE4_COMMON_UB_CFG3 (16'b0000000000000000),
.GTYE4_COMMON_UB_CFG4 (16'b0000000000000000),
.GTYE4_COMMON_UB_CFG5 (16'b0000010000000000),
.GTYE4_COMMON_UB_CFG6 (16'b0000000000000000)
) common_inst (
// inputs
.GTYE4_COMMON_BGBYPASSB (GTYE4_COMMON_BGBYPASSB),
.GTYE4_COMMON_BGMONITORENB (GTYE4_COMMON_BGMONITORENB),
.GTYE4_COMMON_BGPDB (GTYE4_COMMON_BGPDB),
.GTYE4_COMMON_BGRCALOVRD (GTYE4_COMMON_BGRCALOVRD),
.GTYE4_COMMON_BGRCALOVRDENB (GTYE4_COMMON_BGRCALOVRDENB),
.GTYE4_COMMON_DRPADDR (GTYE4_COMMON_DRPADDR),
.GTYE4_COMMON_DRPCLK (GTYE4_COMMON_DRPCLK),
.GTYE4_COMMON_DRPDI (GTYE4_COMMON_DRPDI),
.GTYE4_COMMON_DRPEN (GTYE4_COMMON_DRPEN),
.GTYE4_COMMON_DRPWE (GTYE4_COMMON_DRPWE),
.GTYE4_COMMON_GTGREFCLK0 (GTYE4_COMMON_GTGREFCLK0),
.GTYE4_COMMON_GTGREFCLK1 (GTYE4_COMMON_GTGREFCLK1),
.GTYE4_COMMON_GTNORTHREFCLK00 (GTYE4_COMMON_GTNORTHREFCLK00),
.GTYE4_COMMON_GTNORTHREFCLK01 (GTYE4_COMMON_GTNORTHREFCLK01),
.GTYE4_COMMON_GTNORTHREFCLK10 (GTYE4_COMMON_GTNORTHREFCLK10),
.GTYE4_COMMON_GTNORTHREFCLK11 (GTYE4_COMMON_GTNORTHREFCLK11),
.GTYE4_COMMON_GTREFCLK00 (GTYE4_COMMON_GTREFCLK00),
.GTYE4_COMMON_GTREFCLK01 (GTYE4_COMMON_GTREFCLK01),
.GTYE4_COMMON_GTREFCLK10 (GTYE4_COMMON_GTREFCLK10),
.GTYE4_COMMON_GTREFCLK11 (GTYE4_COMMON_GTREFCLK11),
.GTYE4_COMMON_GTSOUTHREFCLK00 (GTYE4_COMMON_GTSOUTHREFCLK00),
.GTYE4_COMMON_GTSOUTHREFCLK01 (GTYE4_COMMON_GTSOUTHREFCLK01),
.GTYE4_COMMON_GTSOUTHREFCLK10 (GTYE4_COMMON_GTSOUTHREFCLK10),
.GTYE4_COMMON_GTSOUTHREFCLK11 (GTYE4_COMMON_GTSOUTHREFCLK11),
.GTYE4_COMMON_PCIERATEQPLL0 (GTYE4_COMMON_PCIERATEQPLL0),
.GTYE4_COMMON_PCIERATEQPLL1 (GTYE4_COMMON_PCIERATEQPLL1),
.GTYE4_COMMON_PMARSVD0 (GTYE4_COMMON_PMARSVD0),
.GTYE4_COMMON_PMARSVD1 (GTYE4_COMMON_PMARSVD1),
.GTYE4_COMMON_QPLL0CLKRSVD0 (GTYE4_COMMON_QPLL0CLKRSVD0),
.GTYE4_COMMON_QPLL0CLKRSVD1 (GTYE4_COMMON_QPLL0CLKRSVD1),
.GTYE4_COMMON_QPLL0FBDIV (GTYE4_COMMON_QPLL0FBDIV),
.GTYE4_COMMON_QPLL0LOCKDETCLK (GTYE4_COMMON_QPLL0LOCKDETCLK),
.GTYE4_COMMON_QPLL0LOCKEN (GTYE4_COMMON_QPLL0LOCKEN),
.GTYE4_COMMON_QPLL0PD (GTYE4_COMMON_QPLL0PD),
.GTYE4_COMMON_QPLL0REFCLKSEL (GTYE4_COMMON_QPLL0REFCLKSEL),
.GTYE4_COMMON_QPLL0RESET (GTYE4_COMMON_QPLL0RESET),
.GTYE4_COMMON_QPLL1CLKRSVD0 (GTYE4_COMMON_QPLL1CLKRSVD0),
.GTYE4_COMMON_QPLL1CLKRSVD1 (GTYE4_COMMON_QPLL1CLKRSVD1),
.GTYE4_COMMON_QPLL1FBDIV (GTYE4_COMMON_QPLL1FBDIV),
.GTYE4_COMMON_QPLL1LOCKDETCLK (GTYE4_COMMON_QPLL1LOCKDETCLK),
.GTYE4_COMMON_QPLL1LOCKEN (GTYE4_COMMON_QPLL1LOCKEN),
.GTYE4_COMMON_QPLL1PD (GTYE4_COMMON_QPLL1PD),
.GTYE4_COMMON_QPLL1REFCLKSEL (GTYE4_COMMON_QPLL1REFCLKSEL),
.GTYE4_COMMON_QPLL1RESET (GTYE4_COMMON_QPLL1RESET),
.GTYE4_COMMON_QPLLRSVD1 (GTYE4_COMMON_QPLLRSVD1),
.GTYE4_COMMON_QPLLRSVD2 (GTYE4_COMMON_QPLLRSVD2),
.GTYE4_COMMON_QPLLRSVD3 (GTYE4_COMMON_QPLLRSVD3),
.GTYE4_COMMON_QPLLRSVD4 (GTYE4_COMMON_QPLLRSVD4),
.GTYE4_COMMON_RCALENB (GTYE4_COMMON_RCALENB),
.GTYE4_COMMON_SDM0DATA (GTYE4_COMMON_SDM0DATA),
.GTYE4_COMMON_SDM0RESET (GTYE4_COMMON_SDM0RESET),
.GTYE4_COMMON_SDM0TOGGLE (GTYE4_COMMON_SDM0TOGGLE),
.GTYE4_COMMON_SDM0WIDTH (GTYE4_COMMON_SDM0WIDTH),
.GTYE4_COMMON_SDM1DATA (GTYE4_COMMON_SDM1DATA),
.GTYE4_COMMON_SDM1RESET (GTYE4_COMMON_SDM1RESET),
.GTYE4_COMMON_SDM1TOGGLE (GTYE4_COMMON_SDM1TOGGLE),
.GTYE4_COMMON_SDM1WIDTH (GTYE4_COMMON_SDM1WIDTH),
.GTYE4_COMMON_UBCFGSTREAMEN (GTYE4_COMMON_UBCFGSTREAMEN),
.GTYE4_COMMON_UBDO (GTYE4_COMMON_UBDO),
.GTYE4_COMMON_UBDRDY (GTYE4_COMMON_UBDRDY),
.GTYE4_COMMON_UBENABLE (GTYE4_COMMON_UBENABLE),
.GTYE4_COMMON_UBGPI (GTYE4_COMMON_UBGPI),
.GTYE4_COMMON_UBINTR (GTYE4_COMMON_UBINTR),
.GTYE4_COMMON_UBIOLMBRST (GTYE4_COMMON_UBIOLMBRST),
.GTYE4_COMMON_UBMBRST (GTYE4_COMMON_UBMBRST),
.GTYE4_COMMON_UBMDMCAPTURE (GTYE4_COMMON_UBMDMCAPTURE),
.GTYE4_COMMON_UBMDMDBGRST (GTYE4_COMMON_UBMDMDBGRST),
.GTYE4_COMMON_UBMDMDBGUPDATE (GTYE4_COMMON_UBMDMDBGUPDATE),
.GTYE4_COMMON_UBMDMREGEN (GTYE4_COMMON_UBMDMREGEN),
.GTYE4_COMMON_UBMDMSHIFT (GTYE4_COMMON_UBMDMSHIFT),
.GTYE4_COMMON_UBMDMSYSRST (GTYE4_COMMON_UBMDMSYSRST),
.GTYE4_COMMON_UBMDMTCK (GTYE4_COMMON_UBMDMTCK),
.GTYE4_COMMON_UBMDMTDI (GTYE4_COMMON_UBMDMTDI),
// outputs
.GTYE4_COMMON_DRPDO (GTYE4_COMMON_DRPDO),
.GTYE4_COMMON_DRPRDY (GTYE4_COMMON_DRPRDY),
.GTYE4_COMMON_PMARSVDOUT0 (GTYE4_COMMON_PMARSVDOUT0),
.GTYE4_COMMON_PMARSVDOUT1 (GTYE4_COMMON_PMARSVDOUT1),
.GTYE4_COMMON_QPLL0FBCLKLOST (GTYE4_COMMON_QPLL0FBCLKLOST),
.GTYE4_COMMON_QPLL0LOCK (GTYE4_COMMON_QPLL0LOCK),
.GTYE4_COMMON_QPLL0OUTCLK (GTYE4_COMMON_QPLL0OUTCLK),
.GTYE4_COMMON_QPLL0OUTREFCLK (GTYE4_COMMON_QPLL0OUTREFCLK),
.GTYE4_COMMON_QPLL0REFCLKLOST (GTYE4_COMMON_QPLL0REFCLKLOST),
.GTYE4_COMMON_QPLL1FBCLKLOST (GTYE4_COMMON_QPLL1FBCLKLOST),
.GTYE4_COMMON_QPLL1LOCK (GTYE4_COMMON_QPLL1LOCK),
.GTYE4_COMMON_QPLL1OUTCLK (GTYE4_COMMON_QPLL1OUTCLK),
.GTYE4_COMMON_QPLL1OUTREFCLK (GTYE4_COMMON_QPLL1OUTREFCLK),
.GTYE4_COMMON_QPLL1REFCLKLOST (GTYE4_COMMON_QPLL1REFCLKLOST),
.GTYE4_COMMON_QPLLDMONITOR0 (GTYE4_COMMON_QPLLDMONITOR0),
.GTYE4_COMMON_QPLLDMONITOR1 (GTYE4_COMMON_QPLLDMONITOR1),
.GTYE4_COMMON_REFCLKOUTMONITOR0 (GTYE4_COMMON_REFCLKOUTMONITOR0),
.GTYE4_COMMON_REFCLKOUTMONITOR1 (GTYE4_COMMON_REFCLKOUTMONITOR1),
.GTYE4_COMMON_RXRECCLK0SEL (GTYE4_COMMON_RXRECCLK0SEL),
.GTYE4_COMMON_RXRECCLK1SEL (GTYE4_COMMON_RXRECCLK1SEL),
.GTYE4_COMMON_SDM0FINALOUT (GTYE4_COMMON_SDM0FINALOUT),
.GTYE4_COMMON_SDM0TESTDATA (GTYE4_COMMON_SDM0TESTDATA),
.GTYE4_COMMON_SDM1FINALOUT (GTYE4_COMMON_SDM1FINALOUT),
.GTYE4_COMMON_SDM1TESTDATA (GTYE4_COMMON_SDM1TESTDATA),
.GTYE4_COMMON_UBDADDR (GTYE4_COMMON_UBDADDR),
.GTYE4_COMMON_UBDEN (GTYE4_COMMON_UBDEN),
.GTYE4_COMMON_UBDI (GTYE4_COMMON_UBDI),
.GTYE4_COMMON_UBDWE (GTYE4_COMMON_UBDWE),
.GTYE4_COMMON_UBMDMTDO (GTYE4_COMMON_UBMDMTDO),
.GTYE4_COMMON_UBRSVDOUT (GTYE4_COMMON_UBRSVDOUT),
.GTYE4_COMMON_UBTXUART (GTYE4_COMMON_UBTXUART)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O211AI_FUNCTIONAL_PP_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211AI_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DLYGATE4SD1_FUNCTIONAL_PP_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__dlygate4sd1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD1_FUNCTIONAL_PP_V |
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 1.5
// \ \ Application : 7 Series FPGAs Transceivers Wizard
// / / Filename : rocketio_wrapper_tile_top.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
//
// Module ROCKETIO_WRAPPER_TILE_top
// Generated by Xilinx 7 Series FPGAs Transceivers Wizard
//
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`timescale 1ns / 1ps
`define DLY #1
//***********************************Entity Declaration************************
module mgtTop # // ROCKETIO_WRAPPER_TILE_top #
(
parameter EXAMPLE_CONFIG_INDEPENDENT_LANES = 1,//configuration for frame gen and check
parameter EXAMPLE_LANE_WITH_START_CHAR = 0, // specifies lane with unique start frame char
parameter EXAMPLE_WORDS_IN_BRAM = 512, // specifies amount of data in BRAM
parameter EXAMPLE_SIM_GTRESET_SPEEDUP = "TRUE", // simulation setting for GT SecureIP model
parameter EXAMPLE_USE_CHIPSCOPE = 0 // Set to 1 to use Chipscope to drive resets
)
(
input wire Q0_CLK0_GTREFCLK_PAD_N_IN,
input wire Q0_CLK0_GTREFCLK_PAD_P_IN,
input wire Q0_CLK1_GTREFCLK_PAD_N_IN,
input wire Q0_CLK1_GTREFCLK_PAD_P_IN,
input wire Q1_CLK0_GTREFCLK_PAD_N_IN,
input wire Q1_CLK0_GTREFCLK_PAD_P_IN,
input wire Q1_CLK1_GTREFCLK_PAD_N_IN,
input wire Q1_CLK1_GTREFCLK_PAD_P_IN,
input wire SYSCLK_IN,
input wire GTTXRESET_IN,
input wire GTRXRESET_IN,
output wire TRACK_DATA_OUT,
input wire [7:0] RXN_IN,
input wire [7:0] RXP_IN,
output wire [7:0] TXN_OUT,
output wire [7:0] TXP_OUT,
// Wishbone Interface
input wire wb_clk,
input wire wb_reset,
input wire wb_stb_i,
output reg [31:0] wb_dat_o,
input wire [31:0] wb_dat_i,
output reg wb_ack_o,
input wire [31:0] wb_adr_i,
input wire wb_we_i,
input wire wb_cyc_i,
input wire [3:0] wb_sel_i,
output wire wb_err_o,
output reg wb_rty_o
);
//************************** Register Declarations ****************************
reg gt0_txuserrdy_r;
reg gt0_txresetdone_r;
reg gt0_txresetdone_r2;
reg gt0_rxuserrdy_r;
reg gt0_rxresetdone_r;
reg gt0_rxresetdone_r2;
reg gt0_rxresetdone_r3;
reg gt1_txuserrdy_r;
reg gt1_txresetdone_r;
reg gt1_txresetdone_r2;
reg gt1_rxuserrdy_r;
reg gt1_rxresetdone_r;
reg gt1_rxresetdone_r2;
reg gt1_rxresetdone_r3;
reg gt2_txuserrdy_r;
reg gt2_txresetdone_r;
reg gt2_txresetdone_r2;
reg gt2_rxuserrdy_r;
reg gt2_rxresetdone_r;
reg gt2_rxresetdone_r2;
reg gt2_rxresetdone_r3;
reg gt3_txuserrdy_r;
reg gt3_txresetdone_r;
reg gt3_txresetdone_r2;
reg gt3_rxuserrdy_r;
reg gt3_rxresetdone_r;
reg gt3_rxresetdone_r2;
reg gt3_rxresetdone_r3;
reg gt4_txuserrdy_r;
reg gt4_txresetdone_r;
reg gt4_txresetdone_r2;
reg gt4_rxuserrdy_r;
reg gt4_rxresetdone_r;
reg gt4_rxresetdone_r2;
reg gt4_rxresetdone_r3;
reg gt5_txuserrdy_r;
reg gt5_txresetdone_r;
reg gt5_txresetdone_r2;
reg gt5_rxuserrdy_r;
reg gt5_rxresetdone_r;
reg gt5_rxresetdone_r2;
reg gt5_rxresetdone_r3;
reg gt6_txuserrdy_r;
reg gt6_txresetdone_r;
reg gt6_txresetdone_r2;
reg gt6_rxuserrdy_r;
reg gt6_rxresetdone_r;
reg gt6_rxresetdone_r2;
reg gt6_rxresetdone_r3;
reg gt7_txuserrdy_r;
reg gt7_txresetdone_r;
reg gt7_txresetdone_r2;
reg gt7_rxuserrdy_r;
reg gt7_rxresetdone_r;
reg gt7_rxresetdone_r2;
reg gt7_rxresetdone_r3;
//**************************** Wire Declarations ******************************//
//------------------------ GT Wrapper Wires ------------------------------
//________________________________________________________________________
//________________________________________________________________________
//GT0 (X0Y0)
//------------------------------ Channel PLL -------------------------------
wire gt0_cpllfbclklost_i;
wire gt0_cplllock_i;
wire gt0_cpllrefclklost_i;
wire gt0_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt0_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt0_loopback_i;
wire [1:0] gt0_rxpd_i;
wire [1:0] gt0_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt0_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt0_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt0_rxbyteisaligned_i;
wire gt0_rxbyterealign_i;
wire gt0_rxcommadet_i;
wire gt0_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt0_gtrxreset_i;
wire [15:0] gt0_rxdata_i;
wire gt0_rxoutclk_i;
wire gt0_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt0_gtxrxn_i;
wire gt0_gtxrxp_i;
wire gt0_rxcdrlock_i;
wire gt0_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt0_rxbufreset_i;
wire [2:0] gt0_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt0_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt0_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt0_txprecursorinv_i;
wire gt0_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt0_gttxreset_i;
wire [15:0] gt0_txdata_i;
wire gt0_txoutclk_i;
wire gt0_txoutclkfabric_i;
wire gt0_txoutclkpcs_i;
wire gt0_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt0_gtxtxn_i;
wire gt0_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt0_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt0_txresetdone_i;
//________________________________________________________________________
//________________________________________________________________________
//GT1 (X0Y1)
//------------------------------ Channel PLL -------------------------------
wire gt1_cpllfbclklost_i;
wire gt1_cplllock_i;
wire gt1_cpllrefclklost_i;
wire gt1_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt1_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt1_loopback_i;
wire [1:0] gt1_rxpd_i;
wire [1:0] gt1_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt1_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt1_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt1_rxbyteisaligned_i;
wire gt1_rxbyterealign_i;
wire gt1_rxcommadet_i;
wire gt1_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt1_gtrxreset_i;
wire [15:0] gt1_rxdata_i;
wire gt1_rxoutclk_i;
wire gt1_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt1_gtxrxn_i;
wire gt1_gtxrxp_i;
wire gt1_rxcdrlock_i;
wire gt1_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt1_rxbufreset_i;
wire [2:0] gt1_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt1_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt1_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt1_txprecursorinv_i;
wire gt1_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt1_gttxreset_i;
wire [15:0] gt1_txdata_i;
wire gt1_txoutclk_i;
wire gt1_txoutclkfabric_i;
wire gt1_txoutclkpcs_i;
wire gt1_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt1_gtxtxn_i;
wire gt1_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt1_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt1_txresetdone_i;
//________________________________________________________________________
//________________________________________________________________________
//GT2 (X0Y2)
//------------------------------ Channel PLL -------------------------------
wire gt2_cpllfbclklost_i;
wire gt2_cplllock_i;
wire gt2_cpllrefclklost_i;
wire gt2_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt2_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt2_loopback_i;
wire [1:0] gt2_rxpd_i;
wire [1:0] gt2_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt2_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt2_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt2_rxbyteisaligned_i;
wire gt2_rxbyterealign_i;
wire gt2_rxcommadet_i;
wire gt2_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt2_gtrxreset_i;
wire [15:0] gt2_rxdata_i;
wire gt2_rxoutclk_i;
wire gt2_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt2_gtxrxn_i;
wire gt2_gtxrxp_i;
wire gt2_rxcdrlock_i;
wire gt2_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt2_rxbufreset_i;
wire [2:0] gt2_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt2_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt2_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt2_txprecursorinv_i;
wire gt2_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt2_gttxreset_i;
wire [15:0] gt2_txdata_i;
wire gt2_txoutclk_i;
wire gt2_txoutclkfabric_i;
wire gt2_txoutclkpcs_i;
wire gt2_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt2_gtxtxn_i;
wire gt2_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt2_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt2_txresetdone_i;
//________________________________________________________________________
//________________________________________________________________________
//GT3 (X0Y3)
//------------------------------ Channel PLL -------------------------------
wire gt3_cpllfbclklost_i;
wire gt3_cplllock_i;
wire gt3_cpllrefclklost_i;
wire gt3_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt3_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt3_loopback_i;
wire [1:0] gt3_rxpd_i;
wire [1:0] gt3_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt3_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt3_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt3_rxbyteisaligned_i;
wire gt3_rxbyterealign_i;
wire gt3_rxcommadet_i;
wire gt3_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt3_gtrxreset_i;
wire [15:0] gt3_rxdata_i;
wire gt3_rxoutclk_i;
wire gt3_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt3_gtxrxn_i;
wire gt3_gtxrxp_i;
wire gt3_rxcdrlock_i;
wire gt3_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt3_rxbufreset_i;
wire [2:0] gt3_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt3_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt3_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt3_txprecursorinv_i;
wire gt3_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt3_gttxreset_i;
wire [15:0] gt3_txdata_i;
wire gt3_txoutclk_i;
wire gt3_txoutclkfabric_i;
wire gt3_txoutclkpcs_i;
wire gt3_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt3_gtxtxn_i;
wire gt3_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt3_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt3_txresetdone_i;
//________________________________________________________________________
//________________________________________________________________________
//GT4 (X0Y4)
//------------------------------ Channel PLL -------------------------------
wire gt4_cpllfbclklost_i;
wire gt4_cplllock_i;
wire gt4_cpllrefclklost_i;
wire gt4_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt4_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt4_loopback_i;
wire [1:0] gt4_rxpd_i;
wire [1:0] gt4_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt4_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt4_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt4_rxbyteisaligned_i;
wire gt4_rxbyterealign_i;
wire gt4_rxcommadet_i;
wire gt4_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt4_gtrxreset_i;
wire [15:0] gt4_rxdata_i;
wire gt4_rxoutclk_i;
wire gt4_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt4_gtxrxn_i;
wire gt4_gtxrxp_i;
wire gt4_rxcdrlock_i;
wire gt4_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt4_rxbufreset_i;
wire [2:0] gt4_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt4_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt4_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt4_txprecursorinv_i;
wire gt4_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt4_gttxreset_i;
wire [15:0] gt4_txdata_i;
wire gt4_txoutclk_i;
wire gt4_txoutclkfabric_i;
wire gt4_txoutclkpcs_i;
wire gt4_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt4_gtxtxn_i;
wire gt4_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt4_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt4_txresetdone_i;
//________________________________________________________________________
//________________________________________________________________________
//GT5 (X0Y5)
//------------------------------ Channel PLL -------------------------------
wire gt5_cpllfbclklost_i;
wire gt5_cplllock_i;
wire gt5_cpllrefclklost_i;
wire gt5_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt5_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt5_loopback_i;
wire [1:0] gt5_rxpd_i;
wire [1:0] gt5_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt5_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt5_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt5_rxbyteisaligned_i;
wire gt5_rxbyterealign_i;
wire gt5_rxcommadet_i;
wire gt5_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt5_gtrxreset_i;
wire [15:0] gt5_rxdata_i;
wire gt5_rxoutclk_i;
wire gt5_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt5_gtxrxn_i;
wire gt5_gtxrxp_i;
wire gt5_rxcdrlock_i;
wire gt5_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt5_rxbufreset_i;
wire [2:0] gt5_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt5_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt5_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt5_txprecursorinv_i;
wire gt5_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt5_gttxreset_i;
wire [15:0] gt5_txdata_i;
wire gt5_txoutclk_i;
wire gt5_txoutclkfabric_i;
wire gt5_txoutclkpcs_i;
wire gt5_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt5_gtxtxn_i;
wire gt5_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt5_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt5_txresetdone_i;
//________________________________________________________________________
//________________________________________________________________________
//GT6 (X0Y6)
//------------------------------ Channel PLL -------------------------------
wire gt6_cpllfbclklost_i;
wire gt6_cplllock_i;
wire gt6_cpllrefclklost_i;
wire gt6_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt6_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt6_loopback_i;
wire [1:0] gt6_rxpd_i;
wire [1:0] gt6_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt6_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt6_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt6_rxbyteisaligned_i;
wire gt6_rxbyterealign_i;
wire gt6_rxcommadet_i;
wire gt6_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt6_gtrxreset_i;
wire [15:0] gt6_rxdata_i;
wire gt6_rxoutclk_i;
wire gt6_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt6_gtxrxn_i;
wire gt6_gtxrxp_i;
wire gt6_rxcdrlock_i;
wire gt6_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt6_rxbufreset_i;
wire [2:0] gt6_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt6_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt6_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt6_txprecursorinv_i;
wire gt6_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt6_gttxreset_i;
wire [15:0] gt6_txdata_i;
wire gt6_txoutclk_i;
wire gt6_txoutclkfabric_i;
wire gt6_txoutclkpcs_i;
wire gt6_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt6_gtxtxn_i;
wire gt6_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt6_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt6_txresetdone_i;
//________________________________________________________________________
//________________________________________________________________________
//GT7 (X0Y7)
//------------------------------ Channel PLL -------------------------------
wire gt7_cpllfbclklost_i;
wire gt7_cplllock_i;
wire gt7_cpllrefclklost_i;
wire gt7_cpllreset_i;
//----------------------------- Eye Scan Ports -----------------------------
wire gt7_eyescandataerror_i;
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gt7_loopback_i;
wire [1:0] gt7_rxpd_i;
wire [1:0] gt7_txpd_i;
//----------------------------- Receive Ports ------------------------------
wire gt7_rxuserrdy_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [1:0] gt7_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gt7_rxbyteisaligned_i;
wire gt7_rxbyterealign_i;
wire gt7_rxcommadet_i;
wire gt7_rxslide_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire gt7_gtrxreset_i;
wire [15:0] gt7_rxdata_i;
wire gt7_rxoutclk_i;
wire gt7_rxpcsreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gt7_gtxrxn_i;
wire gt7_gtxrxp_i;
wire gt7_rxcdrlock_i;
wire gt7_rxelecidle_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gt7_rxbufreset_i;
wire [2:0] gt7_rxbufstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gt7_rxresetdone_i;
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
wire gt7_rxvalid_i;
//----------------------------- Transmit Ports -----------------------------
wire gt7_txprecursorinv_i;
wire gt7_txuserrdy_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire gt7_gttxreset_i;
wire [15:0] gt7_txdata_i;
wire gt7_txoutclk_i;
wire gt7_txoutclkfabric_i;
wire gt7_txoutclkpcs_i;
wire gt7_txpcsreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire gt7_gtxtxn_i;
wire gt7_gtxtxp_i;
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
wire [1:0] gt7_txbufstatus_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gt7_txresetdone_i;
//----------------------------- Global Signals -----------------------------
wire drpclk_in_i;
wire gt0_tx_system_reset_c;
wire gt0_rx_system_reset_c;
wire gt1_tx_system_reset_c;
wire gt1_rx_system_reset_c;
wire gt2_tx_system_reset_c;
wire gt2_rx_system_reset_c;
wire gt3_tx_system_reset_c;
wire gt3_rx_system_reset_c;
wire gt4_tx_system_reset_c;
wire gt4_rx_system_reset_c;
wire gt5_tx_system_reset_c;
wire gt5_rx_system_reset_c;
wire gt6_tx_system_reset_c;
wire gt6_rx_system_reset_c;
wire gt7_tx_system_reset_c;
wire gt7_rx_system_reset_c;
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [7:0] tied_to_vcc_vec_i;
//--------------------------- User Clocks ---------------------------------
wire gt0_txusrclk_i;
wire gt0_txusrclk2_i;
wire gt0_txclk_lock_out_i;
wire gt0_rxusrclk_i;
wire gt0_rxusrclk2_i;
wire gt0_rxclk_lock_out_i;
wire gt1_txusrclk_i;
wire gt1_txusrclk2_i;
wire gt1_txclk_lock_out_i;
wire gt1_rxusrclk_i;
wire gt1_rxusrclk2_i;
wire gt1_rxclk_lock_out_i;
wire gt2_txusrclk_i;
wire gt2_txusrclk2_i;
wire gt2_txclk_lock_out_i;
wire gt2_rxusrclk_i;
wire gt2_rxusrclk2_i;
wire gt2_rxclk_lock_out_i;
wire gt3_txusrclk_i;
wire gt3_txusrclk2_i;
wire gt3_txclk_lock_out_i;
wire gt3_rxusrclk_i;
wire gt3_rxusrclk2_i;
wire gt3_rxclk_lock_out_i;
wire gt4_txusrclk_i;
wire gt4_txusrclk2_i;
wire gt4_txclk_lock_out_i;
wire gt4_rxusrclk_i;
wire gt4_rxusrclk2_i;
wire gt4_rxclk_lock_out_i;
wire gt5_txusrclk_i;
wire gt5_txusrclk2_i;
wire gt5_txclk_lock_out_i;
wire gt5_rxusrclk_i;
wire gt5_rxusrclk2_i;
wire gt5_rxclk_lock_out_i;
wire gt6_txusrclk_i;
wire gt6_txusrclk2_i;
wire gt6_txclk_lock_out_i;
wire gt6_rxusrclk_i;
wire gt6_rxusrclk2_i;
wire gt6_rxclk_lock_out_i;
wire gt7_txusrclk_i;
wire gt7_txusrclk2_i;
wire gt7_txclk_lock_out_i;
wire gt7_rxusrclk_i;
wire gt7_rxusrclk2_i;
wire gt7_rxclk_lock_out_i;
//--------------------------- Reference Clocks ----------------------------
wire q0_clk0_refclk_i;
wire q0_clk1_refclk_i;
wire q1_clk0_refclk_i;
wire q1_clk1_refclk_i;
//--------------------- Frame check/gen Module Signals --------------------
wire gt0_matchn_i;
wire [5:0] gt0_txcharisk_float_i;
wire [15:0] gt0_txdata_float16_i;
wire [47:0] gt0_txdata_float_i;
wire gt0_block_sync_i;
wire gt0_track_data_i;
wire [7:0] gt0_error_count_i;
wire gt0_frame_check_reset_i;
wire gt0_inc_in_i;
wire gt0_inc_out_i;
wire [15:0] gt0_unscrambled_data_i;
wire gt1_matchn_i;
wire [5:0] gt1_txcharisk_float_i;
wire [15:0] gt1_txdata_float16_i;
wire [47:0] gt1_txdata_float_i;
wire gt1_block_sync_i;
wire gt1_track_data_i;
wire [7:0] gt1_error_count_i;
wire gt1_frame_check_reset_i;
wire gt1_inc_in_i;
wire gt1_inc_out_i;
wire [15:0] gt1_unscrambled_data_i;
wire gt2_matchn_i;
wire [5:0] gt2_txcharisk_float_i;
wire [15:0] gt2_txdata_float16_i;
wire [47:0] gt2_txdata_float_i;
wire gt2_block_sync_i;
wire gt2_track_data_i;
wire [7:0] gt2_error_count_i;
wire gt2_frame_check_reset_i;
wire gt2_inc_in_i;
wire gt2_inc_out_i;
wire [15:0] gt2_unscrambled_data_i;
wire gt3_matchn_i;
wire [5:0] gt3_txcharisk_float_i;
wire [15:0] gt3_txdata_float16_i;
wire [47:0] gt3_txdata_float_i;
wire gt3_block_sync_i;
wire gt3_track_data_i;
wire [7:0] gt3_error_count_i;
wire gt3_frame_check_reset_i;
wire gt3_inc_in_i;
wire gt3_inc_out_i;
wire [15:0] gt3_unscrambled_data_i;
wire gt4_matchn_i;
wire [5:0] gt4_txcharisk_float_i;
wire [15:0] gt4_txdata_float16_i;
wire [47:0] gt4_txdata_float_i;
wire gt4_block_sync_i;
wire gt4_track_data_i;
wire [7:0] gt4_error_count_i;
wire gt4_frame_check_reset_i;
wire gt4_inc_in_i;
wire gt4_inc_out_i;
wire [15:0] gt4_unscrambled_data_i;
wire gt5_matchn_i;
wire [5:0] gt5_txcharisk_float_i;
wire [15:0] gt5_txdata_float16_i;
wire [47:0] gt5_txdata_float_i;
wire gt5_block_sync_i;
wire gt5_track_data_i;
wire [7:0] gt5_error_count_i;
wire gt5_frame_check_reset_i;
wire gt5_inc_in_i;
wire gt5_inc_out_i;
wire [15:0] gt5_unscrambled_data_i;
wire gt6_matchn_i;
wire [5:0] gt6_txcharisk_float_i;
wire [15:0] gt6_txdata_float16_i;
wire [47:0] gt6_txdata_float_i;
wire gt6_block_sync_i;
wire gt6_track_data_i;
wire [7:0] gt6_error_count_i;
wire gt6_frame_check_reset_i;
wire gt6_inc_in_i;
wire gt6_inc_out_i;
wire [15:0] gt6_unscrambled_data_i;
wire gt7_matchn_i;
wire [5:0] gt7_txcharisk_float_i;
wire [15:0] gt7_txdata_float16_i;
wire [47:0] gt7_txdata_float_i;
wire gt7_block_sync_i;
wire gt7_track_data_i;
wire [7:0] gt7_error_count_i;
wire gt7_frame_check_reset_i;
wire gt7_inc_in_i;
wire gt7_inc_out_i;
wire [15:0] gt7_unscrambled_data_i;
wire reset_on_data_error_i;
wire track_data_out_i;
//--------------------- Chipscope Signals ---------------------------------
wire [35:0] tx_data_vio_control_i;
wire [35:0] rx_data_vio_control_i;
wire [35:0] shared_vio_control_i;
wire [35:0] ila_control_i;
wire [31:0] tx_data_vio_async_in_i;
wire [31:0] tx_data_vio_sync_in_i;
wire [31:0] tx_data_vio_async_out_i;
wire [31:0] tx_data_vio_sync_out_i;
wire [31:0] rx_data_vio_async_in_i;
wire [31:0] rx_data_vio_sync_in_i;
wire [31:0] rx_data_vio_async_out_i;
wire [31:0] rx_data_vio_sync_out_i;
wire [31:0] shared_vio_in_i;
wire [31:0] shared_vio_out_i;
wire [163:0] ila_in_i;
wire [31:0] gt0_tx_data_vio_async_in_i;
wire [31:0] gt0_tx_data_vio_sync_in_i;
wire [31:0] gt0_tx_data_vio_async_out_i;
wire [31:0] gt0_tx_data_vio_sync_out_i;
wire [31:0] gt0_rx_data_vio_async_in_i;
wire [31:0] gt0_rx_data_vio_sync_in_i;
wire [31:0] gt0_rx_data_vio_async_out_i;
wire [31:0] gt0_rx_data_vio_sync_out_i;
wire [163:0] gt0_ila_in_i;
wire [31:0] gt1_tx_data_vio_async_in_i;
wire [31:0] gt1_tx_data_vio_sync_in_i;
wire [31:0] gt1_tx_data_vio_async_out_i;
wire [31:0] gt1_tx_data_vio_sync_out_i;
wire [31:0] gt1_rx_data_vio_async_in_i;
wire [31:0] gt1_rx_data_vio_sync_in_i;
wire [31:0] gt1_rx_data_vio_async_out_i;
wire [31:0] gt1_rx_data_vio_sync_out_i;
wire [163:0] gt1_ila_in_i;
wire [31:0] gt2_tx_data_vio_async_in_i;
wire [31:0] gt2_tx_data_vio_sync_in_i;
wire [31:0] gt2_tx_data_vio_async_out_i;
wire [31:0] gt2_tx_data_vio_sync_out_i;
wire [31:0] gt2_rx_data_vio_async_in_i;
wire [31:0] gt2_rx_data_vio_sync_in_i;
wire [31:0] gt2_rx_data_vio_async_out_i;
wire [31:0] gt2_rx_data_vio_sync_out_i;
wire [163:0] gt2_ila_in_i;
wire [31:0] gt3_tx_data_vio_async_in_i;
wire [31:0] gt3_tx_data_vio_sync_in_i;
wire [31:0] gt3_tx_data_vio_async_out_i;
wire [31:0] gt3_tx_data_vio_sync_out_i;
wire [31:0] gt3_rx_data_vio_async_in_i;
wire [31:0] gt3_rx_data_vio_sync_in_i;
wire [31:0] gt3_rx_data_vio_async_out_i;
wire [31:0] gt3_rx_data_vio_sync_out_i;
wire [163:0] gt3_ila_in_i;
wire [31:0] gt4_tx_data_vio_async_in_i;
wire [31:0] gt4_tx_data_vio_sync_in_i;
wire [31:0] gt4_tx_data_vio_async_out_i;
wire [31:0] gt4_tx_data_vio_sync_out_i;
wire [31:0] gt4_rx_data_vio_async_in_i;
wire [31:0] gt4_rx_data_vio_sync_in_i;
wire [31:0] gt4_rx_data_vio_async_out_i;
wire [31:0] gt4_rx_data_vio_sync_out_i;
wire [163:0] gt4_ila_in_i;
wire [31:0] gt5_tx_data_vio_async_in_i;
wire [31:0] gt5_tx_data_vio_sync_in_i;
wire [31:0] gt5_tx_data_vio_async_out_i;
wire [31:0] gt5_tx_data_vio_sync_out_i;
wire [31:0] gt5_rx_data_vio_async_in_i;
wire [31:0] gt5_rx_data_vio_sync_in_i;
wire [31:0] gt5_rx_data_vio_async_out_i;
wire [31:0] gt5_rx_data_vio_sync_out_i;
wire [163:0] gt5_ila_in_i;
wire [31:0] gt6_tx_data_vio_async_in_i;
wire [31:0] gt6_tx_data_vio_sync_in_i;
wire [31:0] gt6_tx_data_vio_async_out_i;
wire [31:0] gt6_tx_data_vio_sync_out_i;
wire [31:0] gt6_rx_data_vio_async_in_i;
wire [31:0] gt6_rx_data_vio_sync_in_i;
wire [31:0] gt6_rx_data_vio_async_out_i;
wire [31:0] gt6_rx_data_vio_sync_out_i;
wire [163:0] gt6_ila_in_i;
wire [31:0] gt7_tx_data_vio_async_in_i;
wire [31:0] gt7_tx_data_vio_sync_in_i;
wire [31:0] gt7_tx_data_vio_async_out_i;
wire [31:0] gt7_tx_data_vio_sync_out_i;
wire [31:0] gt7_rx_data_vio_async_in_i;
wire [31:0] gt7_rx_data_vio_sync_in_i;
wire [31:0] gt7_rx_data_vio_async_out_i;
wire [31:0] gt7_rx_data_vio_sync_out_i;
wire [163:0] gt7_ila_in_i;
// WishBone interface
reg [127:0] data_o;
reg [31:0] control_reg;
reg [127:0] data_reg;
reg [127:0] data_i;
reg ready_i;
wire gttxreset_i;
wire gtrxreset_i;
wire [2:0] mux_sel_i;
wire user_tx_reset_i;
wire user_rx_reset_i;
wire tx_vio_clk_i;
wire tx_vio_clk_mux_out_i;
wire rx_vio_ila_clk_i;
wire rx_vio_ila_clk_mux_out_i;
wire cpllreset_i;
//--------------------- Wishbone Interface ---------------
always @(posedge wb_clk or posedge wb_reset) begin
if(wb_reset==1) begin
wb_ack_o <= #1 0;
wb_dat_o <= #1 0;
control_reg <= #1 32'h0;
data_reg <= #1 127'h0;
data_o <= #1 127'h0;
end
else begin
if(ready_i) begin
control_reg[1] <= #1 1'b1;
data_reg <= #1 data_i;
end
else if(wb_stb_i && wb_cyc_i && wb_we_i && ~wb_ack_o) begin
wb_ack_o<=#1 1;
case(wb_adr_i[7:0])
8'h0: begin
//Writing control register
control_reg<= #1 wb_dat_i;
end
8'h4: begin
data_o[127:96]<= #1 wb_dat_i;
end
8'h8: begin
data_o[95:64]<= #1 wb_dat_i;
end
8'hC: begin
data_o[63:32]<= #1 wb_dat_i;
end
8'h10:begin
data_o[31:0]<= #1 wb_dat_i;
end
endcase
end
else if(wb_stb_i && wb_cyc_i && ~wb_we_i && ~wb_ack_o) begin
wb_ack_o<=#1 1;
case(wb_adr_i[7:0])
8'h0: begin
wb_dat_o<= #1 control_reg;
control_reg[1]<=1'b0;
end
8'h24: begin
wb_dat_o<= #1 data_reg[127:96];
end
8'h28: begin
wb_dat_o<= #1 data_reg[95:64];
end
8'h2C: begin
wb_dat_o<= #1 data_reg[63:32];
end
8'h30: begin
wb_dat_o<= #1 data_reg[31:0];
end
endcase
end
else begin
wb_ack_o<=#1 0;
control_reg[0]<= #1 1'b0;
end
end
end
// Xilinx add in an output register
always @(posedge wb_clk) begin
//wb_rty_o <= tile0_rxlossofsync0_i & tile0_rxlossofsync1_i & tile1_rxlossofsync0_i & tile1_rxlossofsync1_i & tile2_rxlossofsync0_i & tile2_rxlossofsync1_i & tile3_rxlossofsync0_i & tile3_rxlossofsync1_i ;
wb_rty_o <= gt0_cpllrefclklost_i & gt1_cpllrefclklost_i & gt2_cpllrefclklost_i & gt3_cpllrefclklost_i &
gt4_cpllrefclklost_i & gt5_cpllrefclklost_i & gt6_cpllrefclklost_i & gt7_cpllrefclklost_i;
end
//**************************** Main Body of GT Code *******************************
// Static signal Assigments
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 8'hff;
ROCKETIO_WRAPPER_TILE_GT_USRCLK_SOURCE gt_usrclk_source
(
.Q0_CLK0_GTREFCLK_PAD_N_IN (Q0_CLK0_GTREFCLK_PAD_N_IN),
.Q0_CLK0_GTREFCLK_PAD_P_IN (Q0_CLK0_GTREFCLK_PAD_P_IN),
.Q0_CLK0_GTREFCLK_OUT (q0_clk0_refclk_i),
.Q0_CLK1_GTREFCLK_PAD_N_IN (Q0_CLK1_GTREFCLK_PAD_N_IN),
.Q0_CLK1_GTREFCLK_PAD_P_IN (Q0_CLK1_GTREFCLK_PAD_P_IN),
.Q0_CLK1_GTREFCLK_OUT (q0_clk1_refclk_i),
.Q1_CLK0_GTREFCLK_PAD_N_IN (Q1_CLK0_GTREFCLK_PAD_N_IN),
.Q1_CLK0_GTREFCLK_PAD_P_IN (Q1_CLK0_GTREFCLK_PAD_P_IN),
.Q1_CLK0_GTREFCLK_OUT (q1_clk0_refclk_i),
.Q1_CLK1_GTREFCLK_PAD_N_IN (Q1_CLK1_GTREFCLK_PAD_N_IN),
.Q1_CLK1_GTREFCLK_PAD_P_IN (Q1_CLK1_GTREFCLK_PAD_P_IN),
.Q1_CLK1_GTREFCLK_OUT (q1_clk1_refclk_i),
.GT0_TXUSRCLK_OUT (gt0_txusrclk_i),
.GT0_TXUSRCLK2_OUT (gt0_txusrclk2_i),
.GT0_TXOUTCLK_IN (gt0_txoutclk_i),
.GT0_RXUSRCLK_OUT (gt0_rxusrclk_i),
.GT0_RXUSRCLK2_OUT (gt0_rxusrclk2_i),
.GT0_RXOUTCLK_IN (gt0_rxoutclk_i),
.GT1_TXUSRCLK_OUT (gt1_txusrclk_i),
.GT1_TXUSRCLK2_OUT (gt1_txusrclk2_i),
.GT1_TXOUTCLK_IN (gt1_txoutclk_i),
.GT1_RXUSRCLK_OUT (gt1_rxusrclk_i),
.GT1_RXUSRCLK2_OUT (gt1_rxusrclk2_i),
.GT1_RXOUTCLK_IN (gt1_rxoutclk_i),
.GT2_TXUSRCLK_OUT (gt2_txusrclk_i),
.GT2_TXUSRCLK2_OUT (gt2_txusrclk2_i),
.GT2_TXOUTCLK_IN (gt2_txoutclk_i),
.GT2_RXUSRCLK_OUT (gt2_rxusrclk_i),
.GT2_RXUSRCLK2_OUT (gt2_rxusrclk2_i),
.GT2_RXOUTCLK_IN (gt2_rxoutclk_i),
.GT3_TXUSRCLK_OUT (gt3_txusrclk_i),
.GT3_TXUSRCLK2_OUT (gt3_txusrclk2_i),
.GT3_TXOUTCLK_IN (gt3_txoutclk_i),
.GT3_RXUSRCLK_OUT (gt3_rxusrclk_i),
.GT3_RXUSRCLK2_OUT (gt3_rxusrclk2_i),
.GT3_RXOUTCLK_IN (gt3_rxoutclk_i),
.GT4_TXUSRCLK_OUT (gt4_txusrclk_i),
.GT4_TXUSRCLK2_OUT (gt4_txusrclk2_i),
.GT4_TXOUTCLK_IN (gt4_txoutclk_i),
.GT4_RXUSRCLK_OUT (gt4_rxusrclk_i),
.GT4_RXUSRCLK2_OUT (gt4_rxusrclk2_i),
.GT4_RXOUTCLK_IN (gt4_rxoutclk_i),
.GT5_TXUSRCLK_OUT (gt5_txusrclk_i),
.GT5_TXUSRCLK2_OUT (gt5_txusrclk2_i),
.GT5_TXOUTCLK_IN (gt5_txoutclk_i),
.GT5_RXUSRCLK_OUT (gt5_rxusrclk_i),
.GT5_RXUSRCLK2_OUT (gt5_rxusrclk2_i),
.GT5_RXOUTCLK_IN (gt5_rxoutclk_i),
.GT6_TXUSRCLK_OUT (gt6_txusrclk_i),
.GT6_TXUSRCLK2_OUT (gt6_txusrclk2_i),
.GT6_TXOUTCLK_IN (gt6_txoutclk_i),
.GT6_RXUSRCLK_OUT (gt6_rxusrclk_i),
.GT6_RXUSRCLK2_OUT (gt6_rxusrclk2_i),
.GT6_RXOUTCLK_IN (gt6_rxoutclk_i),
.GT7_TXUSRCLK_OUT (gt7_txusrclk_i),
.GT7_TXUSRCLK2_OUT (gt7_txusrclk2_i),
.GT7_TXOUTCLK_IN (gt7_txoutclk_i),
.GT7_RXUSRCLK_OUT (gt7_rxusrclk_i),
.GT7_RXUSRCLK2_OUT (gt7_rxusrclk2_i),
.GT7_RXOUTCLK_IN (gt7_rxoutclk_i),
.DRPCLK_IN (SYSCLK_IN),
.DRPCLK_OUT(drpclk_in_i)
);
//***********************************************************************//
// //
//--------------------------- The GT Wrapper ----------------------------//
// //
//***********************************************************************//
// Use the instantiation template in the example directory to add the GT wrapper to your design.
// In this example, the wrapper is wired up for basic operation with a frame generator and frame
// checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
// enabled, bonding should occur after alignment.
ROCKETIO_WRAPPER_TILE #
(
.WRAPPER_SIM_GTRESET_SPEEDUP (EXAMPLE_SIM_GTRESET_SPEEDUP)
)
ROCKETIO_WRAPPER_TILE_i
(
//_____________________________________________________________________
//_____________________________________________________________________
//GT0 (X0Y0)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT0_GTREFCLK0_IN (q0_clk0_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT0_CPLLFBCLKLOST_OUT (gt0_cpllfbclklost_i),
.GT0_CPLLLOCK_OUT (gt0_cplllock_i),
.GT0_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT0_CPLLREFCLKLOST_OUT (gt0_cpllrefclklost_i),
.GT0_CPLLRESET_IN (gt0_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT0_EYESCANDATAERROR_OUT (gt0_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT0_LOOPBACK_IN (gt0_loopback_i),
.GT0_RXPD_IN (gt0_rxpd_i),
.GT0_TXPD_IN (gt0_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT0_RXUSERRDY_IN (gt0_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT0_RXCLKCORCNT_OUT (gt0_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT0_RXBYTEISALIGNED_OUT (gt0_rxbyteisaligned_i),
.GT0_RXBYTEREALIGN_OUT (gt0_rxbyterealign_i),
.GT0_RXCOMMADET_OUT (gt0_rxcommadet_i),
.GT0_RXSLIDE_IN (gt0_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT0_GTRXRESET_IN (gt0_gtrxreset_i),
.GT0_RXDATA_OUT (gt0_rxdata_i),
.GT0_RXOUTCLK_OUT (gt0_rxoutclk_i),
.GT0_RXPCSRESET_IN (gt0_rxpcsreset_i),
.GT0_RXUSRCLK_IN (gt0_txusrclk_i),
.GT0_RXUSRCLK2_IN (gt0_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT0_GTXRXN_IN (RXN_IN[0]),
.GT0_GTXRXP_IN (RXP_IN[0]),
.GT0_RXCDRLOCK_OUT (gt0_rxcdrlock_i),
.GT0_RXELECIDLE_OUT (gt0_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT0_RXBUFRESET_IN (gt0_rxbufreset_i),
.GT0_RXBUFSTATUS_OUT (gt0_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT0_RXRESETDONE_OUT (gt0_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT0_RXVALID_OUT (gt0_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT0_TXPRECURSORINV_IN (gt0_txprecursorinv_i),
.GT0_TXUSERRDY_IN (gt0_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT0_GTTXRESET_IN (gt0_gttxreset_i),
.GT0_TXDATA_IN (gt0_txdata_i),
.GT0_TXOUTCLK_OUT (gt0_txoutclk_i),
.GT0_TXOUTCLKFABRIC_OUT (gt0_txoutclkfabric_i),
.GT0_TXOUTCLKPCS_OUT (gt0_txoutclkpcs_i),
.GT0_TXPCSRESET_IN (gt0_txpcsreset_i),
.GT0_TXUSRCLK_IN (gt0_txusrclk_i),
.GT0_TXUSRCLK2_IN (gt0_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT0_GTXTXN_OUT (TXN_OUT[0]),
.GT0_GTXTXP_OUT (TXP_OUT[0]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT0_TXBUFSTATUS_OUT (gt0_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT0_TXRESETDONE_OUT (gt0_txresetdone_i),
//_____________________________________________________________________
//_____________________________________________________________________
//GT1 (X0Y1)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT1_GTREFCLK0_IN (q0_clk0_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT1_CPLLFBCLKLOST_OUT (gt1_cpllfbclklost_i),
.GT1_CPLLLOCK_OUT (gt1_cplllock_i),
.GT1_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT1_CPLLREFCLKLOST_OUT (gt1_cpllrefclklost_i),
.GT1_CPLLRESET_IN (gt1_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT1_EYESCANDATAERROR_OUT (gt1_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT1_LOOPBACK_IN (gt1_loopback_i),
.GT1_RXPD_IN (gt1_rxpd_i),
.GT1_TXPD_IN (gt1_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT1_RXUSERRDY_IN (gt1_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT1_RXCLKCORCNT_OUT (gt1_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT1_RXBYTEISALIGNED_OUT (gt1_rxbyteisaligned_i),
.GT1_RXBYTEREALIGN_OUT (gt1_rxbyterealign_i),
.GT1_RXCOMMADET_OUT (gt1_rxcommadet_i),
.GT1_RXSLIDE_IN (gt1_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT1_GTRXRESET_IN (gt1_gtrxreset_i),
.GT1_RXDATA_OUT (gt1_rxdata_i),
.GT1_RXOUTCLK_OUT (gt1_rxoutclk_i),
.GT1_RXPCSRESET_IN (gt1_rxpcsreset_i),
.GT1_RXUSRCLK_IN (gt0_txusrclk_i),
.GT1_RXUSRCLK2_IN (gt0_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT1_GTXRXN_IN (RXN_IN[1]),
.GT1_GTXRXP_IN (RXP_IN[1]),
.GT1_RXCDRLOCK_OUT (gt1_rxcdrlock_i),
.GT1_RXELECIDLE_OUT (gt1_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT1_RXBUFRESET_IN (gt1_rxbufreset_i),
.GT1_RXBUFSTATUS_OUT (gt1_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT1_RXRESETDONE_OUT (gt1_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT1_RXVALID_OUT (gt1_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT1_TXPRECURSORINV_IN (gt1_txprecursorinv_i),
.GT1_TXUSERRDY_IN (gt1_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT1_GTTXRESET_IN (gt1_gttxreset_i),
.GT1_TXDATA_IN (gt1_txdata_i),
.GT1_TXOUTCLK_OUT (gt1_txoutclk_i),
.GT1_TXOUTCLKFABRIC_OUT (gt1_txoutclkfabric_i),
.GT1_TXOUTCLKPCS_OUT (gt1_txoutclkpcs_i),
.GT1_TXPCSRESET_IN (gt1_txpcsreset_i),
.GT1_TXUSRCLK_IN (gt0_txusrclk_i),
.GT1_TXUSRCLK2_IN (gt0_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT1_GTXTXN_OUT (TXN_OUT[1]),
.GT1_GTXTXP_OUT (TXP_OUT[1]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT1_TXBUFSTATUS_OUT (gt1_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT1_TXRESETDONE_OUT (gt1_txresetdone_i),
//_____________________________________________________________________
//_____________________________________________________________________
//GT2 (X0Y2)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT2_GTREFCLK0_IN (q0_clk1_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT2_CPLLFBCLKLOST_OUT (gt2_cpllfbclklost_i),
.GT2_CPLLLOCK_OUT (gt2_cplllock_i),
.GT2_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT2_CPLLREFCLKLOST_OUT (gt2_cpllrefclklost_i),
.GT2_CPLLRESET_IN (gt2_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT2_EYESCANDATAERROR_OUT (gt2_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT2_LOOPBACK_IN (gt2_loopback_i),
.GT2_RXPD_IN (gt2_rxpd_i),
.GT2_TXPD_IN (gt2_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT2_RXUSERRDY_IN (gt2_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT2_RXCLKCORCNT_OUT (gt2_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT2_RXBYTEISALIGNED_OUT (gt2_rxbyteisaligned_i),
.GT2_RXBYTEREALIGN_OUT (gt2_rxbyterealign_i),
.GT2_RXCOMMADET_OUT (gt2_rxcommadet_i),
.GT2_RXSLIDE_IN (gt2_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT2_GTRXRESET_IN (gt2_gtrxreset_i),
.GT2_RXDATA_OUT (gt2_rxdata_i),
.GT2_RXOUTCLK_OUT (gt2_rxoutclk_i),
.GT2_RXPCSRESET_IN (gt2_rxpcsreset_i),
.GT2_RXUSRCLK_IN (gt2_txusrclk_i),
.GT2_RXUSRCLK2_IN (gt2_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT2_GTXRXN_IN (RXN_IN[2]),
.GT2_GTXRXP_IN (RXP_IN[2]),
.GT2_RXCDRLOCK_OUT (gt2_rxcdrlock_i),
.GT2_RXELECIDLE_OUT (gt2_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT2_RXBUFRESET_IN (gt2_rxbufreset_i),
.GT2_RXBUFSTATUS_OUT (gt2_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT2_RXRESETDONE_OUT (gt2_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT2_RXVALID_OUT (gt2_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT2_TXPRECURSORINV_IN (gt2_txprecursorinv_i),
.GT2_TXUSERRDY_IN (gt2_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT2_GTTXRESET_IN (gt2_gttxreset_i),
.GT2_TXDATA_IN (gt2_txdata_i),
.GT2_TXOUTCLK_OUT (gt2_txoutclk_i),
.GT2_TXOUTCLKFABRIC_OUT (gt2_txoutclkfabric_i),
.GT2_TXOUTCLKPCS_OUT (gt2_txoutclkpcs_i),
.GT2_TXPCSRESET_IN (gt2_txpcsreset_i),
.GT2_TXUSRCLK_IN (gt2_txusrclk_i),
.GT2_TXUSRCLK2_IN (gt2_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT2_GTXTXN_OUT (TXN_OUT[2]),
.GT2_GTXTXP_OUT (TXP_OUT[2]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT2_TXBUFSTATUS_OUT (gt2_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT2_TXRESETDONE_OUT (gt2_txresetdone_i),
//_____________________________________________________________________
//_____________________________________________________________________
//GT3 (X0Y3)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT3_GTREFCLK0_IN (q0_clk1_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT3_CPLLFBCLKLOST_OUT (gt3_cpllfbclklost_i),
.GT3_CPLLLOCK_OUT (gt3_cplllock_i),
.GT3_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT3_CPLLREFCLKLOST_OUT (gt3_cpllrefclklost_i),
.GT3_CPLLRESET_IN (gt3_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT3_EYESCANDATAERROR_OUT (gt3_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT3_LOOPBACK_IN (gt3_loopback_i),
.GT3_RXPD_IN (gt3_rxpd_i),
.GT3_TXPD_IN (gt3_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT3_RXUSERRDY_IN (gt3_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT3_RXCLKCORCNT_OUT (gt3_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT3_RXBYTEISALIGNED_OUT (gt3_rxbyteisaligned_i),
.GT3_RXBYTEREALIGN_OUT (gt3_rxbyterealign_i),
.GT3_RXCOMMADET_OUT (gt3_rxcommadet_i),
.GT3_RXSLIDE_IN (gt3_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT3_GTRXRESET_IN (gt3_gtrxreset_i),
.GT3_RXDATA_OUT (gt3_rxdata_i),
.GT3_RXOUTCLK_OUT (gt3_rxoutclk_i),
.GT3_RXPCSRESET_IN (gt3_rxpcsreset_i),
.GT3_RXUSRCLK_IN (gt2_txusrclk_i),
.GT3_RXUSRCLK2_IN (gt2_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT3_GTXRXN_IN (RXN_IN[3]),
.GT3_GTXRXP_IN (RXP_IN[3]),
.GT3_RXCDRLOCK_OUT (gt3_rxcdrlock_i),
.GT3_RXELECIDLE_OUT (gt3_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT3_RXBUFRESET_IN (gt3_rxbufreset_i),
.GT3_RXBUFSTATUS_OUT (gt3_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT3_RXRESETDONE_OUT (gt3_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT3_RXVALID_OUT (gt3_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT3_TXPRECURSORINV_IN (gt3_txprecursorinv_i),
.GT3_TXUSERRDY_IN (gt3_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT3_GTTXRESET_IN (gt3_gttxreset_i),
.GT3_TXDATA_IN (gt3_txdata_i),
.GT3_TXOUTCLK_OUT (gt3_txoutclk_i),
.GT3_TXOUTCLKFABRIC_OUT (gt3_txoutclkfabric_i),
.GT3_TXOUTCLKPCS_OUT (gt3_txoutclkpcs_i),
.GT3_TXPCSRESET_IN (gt3_txpcsreset_i),
.GT3_TXUSRCLK_IN (gt2_txusrclk_i),
.GT3_TXUSRCLK2_IN (gt2_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT3_GTXTXN_OUT (TXN_OUT[3]),
.GT3_GTXTXP_OUT (TXP_OUT[3]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT3_TXBUFSTATUS_OUT (gt3_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT3_TXRESETDONE_OUT (gt3_txresetdone_i),
//_____________________________________________________________________
//_____________________________________________________________________
//GT4 (X0Y4)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT4_GTREFCLK0_IN (q1_clk0_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT4_CPLLFBCLKLOST_OUT (gt4_cpllfbclklost_i),
.GT4_CPLLLOCK_OUT (gt4_cplllock_i),
.GT4_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT4_CPLLREFCLKLOST_OUT (gt4_cpllrefclklost_i),
.GT4_CPLLRESET_IN (gt4_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT4_EYESCANDATAERROR_OUT (gt4_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT4_LOOPBACK_IN (gt4_loopback_i),
.GT4_RXPD_IN (gt4_rxpd_i),
.GT4_TXPD_IN (gt4_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT4_RXUSERRDY_IN (gt4_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT4_RXCLKCORCNT_OUT (gt4_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT4_RXBYTEISALIGNED_OUT (gt4_rxbyteisaligned_i),
.GT4_RXBYTEREALIGN_OUT (gt4_rxbyterealign_i),
.GT4_RXCOMMADET_OUT (gt4_rxcommadet_i),
.GT4_RXSLIDE_IN (gt4_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT4_GTRXRESET_IN (gt4_gtrxreset_i),
.GT4_RXDATA_OUT (gt4_rxdata_i),
.GT4_RXOUTCLK_OUT (gt4_rxoutclk_i),
.GT4_RXPCSRESET_IN (gt4_rxpcsreset_i),
.GT4_RXUSRCLK_IN (gt4_txusrclk_i),
.GT4_RXUSRCLK2_IN (gt4_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT4_GTXRXN_IN (RXN_IN[4]),
.GT4_GTXRXP_IN (RXP_IN[4]),
.GT4_RXCDRLOCK_OUT (gt4_rxcdrlock_i),
.GT4_RXELECIDLE_OUT (gt4_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT4_RXBUFRESET_IN (gt4_rxbufreset_i),
.GT4_RXBUFSTATUS_OUT (gt4_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT4_RXRESETDONE_OUT (gt4_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT4_RXVALID_OUT (gt4_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT4_TXPRECURSORINV_IN (gt4_txprecursorinv_i),
.GT4_TXUSERRDY_IN (gt4_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT4_GTTXRESET_IN (gt4_gttxreset_i),
.GT4_TXDATA_IN (gt4_txdata_i),
.GT4_TXOUTCLK_OUT (gt4_txoutclk_i),
.GT4_TXOUTCLKFABRIC_OUT (gt4_txoutclkfabric_i),
.GT4_TXOUTCLKPCS_OUT (gt4_txoutclkpcs_i),
.GT4_TXPCSRESET_IN (gt4_txpcsreset_i),
.GT4_TXUSRCLK_IN (gt4_txusrclk_i),
.GT4_TXUSRCLK2_IN (gt4_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT4_GTXTXN_OUT (TXN_OUT[4]),
.GT4_GTXTXP_OUT (TXP_OUT[4]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT4_TXBUFSTATUS_OUT (gt4_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT4_TXRESETDONE_OUT (gt4_txresetdone_i),
//_____________________________________________________________________
//_____________________________________________________________________
//GT5 (X0Y5)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT5_GTREFCLK0_IN (q1_clk0_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT5_CPLLFBCLKLOST_OUT (gt5_cpllfbclklost_i),
.GT5_CPLLLOCK_OUT (gt5_cplllock_i),
.GT5_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT5_CPLLREFCLKLOST_OUT (gt5_cpllrefclklost_i),
.GT5_CPLLRESET_IN (gt5_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT5_EYESCANDATAERROR_OUT (gt5_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT5_LOOPBACK_IN (gt5_loopback_i),
.GT5_RXPD_IN (gt5_rxpd_i),
.GT5_TXPD_IN (gt5_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT5_RXUSERRDY_IN (gt5_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT5_RXCLKCORCNT_OUT (gt5_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT5_RXBYTEISALIGNED_OUT (gt5_rxbyteisaligned_i),
.GT5_RXBYTEREALIGN_OUT (gt5_rxbyterealign_i),
.GT5_RXCOMMADET_OUT (gt5_rxcommadet_i),
.GT5_RXSLIDE_IN (gt5_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT5_GTRXRESET_IN (gt5_gtrxreset_i),
.GT5_RXDATA_OUT (gt5_rxdata_i),
.GT5_RXOUTCLK_OUT (gt5_rxoutclk_i),
.GT5_RXPCSRESET_IN (gt5_rxpcsreset_i),
.GT5_RXUSRCLK_IN (gt4_txusrclk_i),
.GT5_RXUSRCLK2_IN (gt4_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT5_GTXRXN_IN (RXN_IN[5]),
.GT5_GTXRXP_IN (RXP_IN[5]),
.GT5_RXCDRLOCK_OUT (gt5_rxcdrlock_i),
.GT5_RXELECIDLE_OUT (gt5_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT5_RXBUFRESET_IN (gt5_rxbufreset_i),
.GT5_RXBUFSTATUS_OUT (gt5_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT5_RXRESETDONE_OUT (gt5_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT5_RXVALID_OUT (gt5_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT5_TXPRECURSORINV_IN (gt5_txprecursorinv_i),
.GT5_TXUSERRDY_IN (gt5_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT5_GTTXRESET_IN (gt5_gttxreset_i),
.GT5_TXDATA_IN (gt5_txdata_i),
.GT5_TXOUTCLK_OUT (gt5_txoutclk_i),
.GT5_TXOUTCLKFABRIC_OUT (gt5_txoutclkfabric_i),
.GT5_TXOUTCLKPCS_OUT (gt5_txoutclkpcs_i),
.GT5_TXPCSRESET_IN (gt5_txpcsreset_i),
.GT5_TXUSRCLK_IN (gt4_txusrclk_i),
.GT5_TXUSRCLK2_IN (gt4_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT5_GTXTXN_OUT (TXN_OUT[5]),
.GT5_GTXTXP_OUT (TXP_OUT[5]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT5_TXBUFSTATUS_OUT (gt5_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT5_TXRESETDONE_OUT (gt5_txresetdone_i),
//_____________________________________________________________________
//_____________________________________________________________________
//GT6 (X0Y6)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT6_GTREFCLK0_IN (q1_clk1_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT6_CPLLFBCLKLOST_OUT (gt6_cpllfbclklost_i),
.GT6_CPLLLOCK_OUT (gt6_cplllock_i),
.GT6_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT6_CPLLREFCLKLOST_OUT (gt6_cpllrefclklost_i),
.GT6_CPLLRESET_IN (gt6_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT6_EYESCANDATAERROR_OUT (gt6_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT6_LOOPBACK_IN (gt6_loopback_i),
.GT6_RXPD_IN (gt6_rxpd_i),
.GT6_TXPD_IN (gt6_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT6_RXUSERRDY_IN (gt6_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT6_RXCLKCORCNT_OUT (gt6_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT6_RXBYTEISALIGNED_OUT (gt6_rxbyteisaligned_i),
.GT6_RXBYTEREALIGN_OUT (gt6_rxbyterealign_i),
.GT6_RXCOMMADET_OUT (gt6_rxcommadet_i),
.GT6_RXSLIDE_IN (gt6_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT6_GTRXRESET_IN (gt6_gtrxreset_i),
.GT6_RXDATA_OUT (gt6_rxdata_i),
.GT6_RXOUTCLK_OUT (gt6_rxoutclk_i),
.GT6_RXPCSRESET_IN (gt6_rxpcsreset_i),
.GT6_RXUSRCLK_IN (gt6_txusrclk_i),
.GT6_RXUSRCLK2_IN (gt6_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT6_GTXRXN_IN (RXN_IN[6]),
.GT6_GTXRXP_IN (RXP_IN[6]),
.GT6_RXCDRLOCK_OUT (gt6_rxcdrlock_i),
.GT6_RXELECIDLE_OUT (gt6_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT6_RXBUFRESET_IN (gt6_rxbufreset_i),
.GT6_RXBUFSTATUS_OUT (gt6_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT6_RXRESETDONE_OUT (gt6_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT6_RXVALID_OUT (gt6_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT6_TXPRECURSORINV_IN (gt6_txprecursorinv_i),
.GT6_TXUSERRDY_IN (gt6_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT6_GTTXRESET_IN (gt6_gttxreset_i),
.GT6_TXDATA_IN (gt6_txdata_i),
.GT6_TXOUTCLK_OUT (gt6_txoutclk_i),
.GT6_TXOUTCLKFABRIC_OUT (gt6_txoutclkfabric_i),
.GT6_TXOUTCLKPCS_OUT (gt6_txoutclkpcs_i),
.GT6_TXPCSRESET_IN (gt6_txpcsreset_i),
.GT6_TXUSRCLK_IN (gt6_txusrclk_i),
.GT6_TXUSRCLK2_IN (gt6_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT6_GTXTXN_OUT (TXN_OUT[6]),
.GT6_GTXTXP_OUT (TXP_OUT[6]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT6_TXBUFSTATUS_OUT (gt6_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT6_TXRESETDONE_OUT (gt6_txresetdone_i),
//_____________________________________________________________________
//_____________________________________________________________________
//GT7 (X0Y7)
//----------------------- Channel - Ref Clock Ports ------------------------
.GT7_GTREFCLK0_IN (q1_clk1_refclk_i),
//------------------------------ Channel PLL -------------------------------
.GT7_CPLLFBCLKLOST_OUT (gt7_cpllfbclklost_i),
.GT7_CPLLLOCK_OUT (gt7_cplllock_i),
.GT7_CPLLLOCKDETCLK_IN (drpclk_in_i),
.GT7_CPLLREFCLKLOST_OUT (gt7_cpllrefclklost_i),
.GT7_CPLLRESET_IN (gt7_cpllreset_i),
//----------------------------- Eye Scan Ports -----------------------------
.GT7_EYESCANDATAERROR_OUT (gt7_eyescandataerror_i),
//---------------------- Loopback and Powerdown Ports ----------------------
.GT7_LOOPBACK_IN (gt7_loopback_i),
.GT7_RXPD_IN (gt7_rxpd_i),
.GT7_TXPD_IN (gt7_txpd_i),
//----------------------------- Receive Ports ------------------------------
.GT7_RXUSERRDY_IN (gt7_rxuserrdy_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GT7_RXCLKCORCNT_OUT (gt7_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GT7_RXBYTEISALIGNED_OUT (gt7_rxbyteisaligned_i),
.GT7_RXBYTEREALIGN_OUT (gt7_rxbyterealign_i),
.GT7_RXCOMMADET_OUT (gt7_rxcommadet_i),
.GT7_RXSLIDE_IN (gt7_rxslide_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GT7_GTRXRESET_IN (gt7_gtrxreset_i),
.GT7_RXDATA_OUT (gt7_rxdata_i),
.GT7_RXOUTCLK_OUT (gt7_rxoutclk_i),
.GT7_RXPCSRESET_IN (gt7_rxpcsreset_i),
.GT7_RXUSRCLK_IN (gt6_txusrclk_i),
.GT7_RXUSRCLK2_IN (gt6_txusrclk_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GT7_GTXRXN_IN (RXN_IN[7]),
.GT7_GTXRXP_IN (RXP_IN[7]),
.GT7_RXCDRLOCK_OUT (gt7_rxcdrlock_i),
.GT7_RXELECIDLE_OUT (gt7_rxelecidle_i),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GT7_RXBUFRESET_IN (gt7_rxbufreset_i),
.GT7_RXBUFSTATUS_OUT (gt7_rxbufstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GT7_RXRESETDONE_OUT (gt7_rxresetdone_i),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.GT7_RXVALID_OUT (gt7_rxvalid_i),
//----------------------------- Transmit Ports -----------------------------
.GT7_TXPRECURSORINV_IN (gt7_txprecursorinv_i),
.GT7_TXUSERRDY_IN (gt7_txuserrdy_i),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GT7_GTTXRESET_IN (gt7_gttxreset_i),
.GT7_TXDATA_IN (gt7_txdata_i),
.GT7_TXOUTCLK_OUT (gt7_txoutclk_i),
.GT7_TXOUTCLKFABRIC_OUT (gt7_txoutclkfabric_i),
.GT7_TXOUTCLKPCS_OUT (gt7_txoutclkpcs_i),
.GT7_TXPCSRESET_IN (gt7_txpcsreset_i),
.GT7_TXUSRCLK_IN (gt6_txusrclk_i),
.GT7_TXUSRCLK2_IN (gt6_txusrclk_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GT7_GTXTXN_OUT (TXN_OUT[7]),
.GT7_GTXTXP_OUT (TXP_OUT[7]),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.GT7_TXBUFSTATUS_OUT (gt7_txbufstatus_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GT7_TXRESETDONE_OUT (gt7_txresetdone_i)
);
//***********************************************************************//
// //
//--------------------------- User Module Resets-------------------------//
// //
//***********************************************************************//
// All the User Modules i.e. FRAME_GEN, FRAME_CHECK and the sync modules
// are held in reset till the RESETDONE goes high.
// The RESETDONE is registered a couple of times on *USRCLK2 and connected
// to the reset of the modules
always @(posedge gt0_txusrclk_i or negedge gt0_rxresetdone_i)
begin
if (!gt0_rxresetdone_i)
begin
gt0_rxresetdone_r <= `DLY 1'b0;
gt0_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt0_rxresetdone_r <= `DLY gt0_rxresetdone_i;
gt0_rxresetdone_r2 <= `DLY gt0_rxresetdone_r;
end
end
always @(posedge gt0_txusrclk_i)
gt0_rxresetdone_r3 <= `DLY gt0_rxresetdone_r2;
always @(posedge gt0_txusrclk_i or negedge gt0_txresetdone_i)
begin
if (!gt0_txresetdone_i)
begin
gt0_txresetdone_r <= `DLY 1'b0;
gt0_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt0_txresetdone_r <= `DLY gt0_txresetdone_i;
gt0_txresetdone_r2 <= `DLY gt0_txresetdone_r;
end
end
always @(posedge gt0_txusrclk_i or negedge gt1_rxresetdone_i)
begin
if (!gt1_rxresetdone_i)
begin
gt1_rxresetdone_r <= `DLY 1'b0;
gt1_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt1_rxresetdone_r <= `DLY gt1_rxresetdone_i;
gt1_rxresetdone_r2 <= `DLY gt1_rxresetdone_r;
end
end
always @(posedge gt0_txusrclk_i)
gt1_rxresetdone_r3 <= `DLY gt1_rxresetdone_r2;
always @(posedge gt0_txusrclk_i or negedge gt1_txresetdone_i)
begin
if (!gt1_txresetdone_i)
begin
gt1_txresetdone_r <= `DLY 1'b0;
gt1_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt1_txresetdone_r <= `DLY gt1_txresetdone_i;
gt1_txresetdone_r2 <= `DLY gt1_txresetdone_r;
end
end
always @(posedge gt2_txusrclk_i or negedge gt2_rxresetdone_i)
begin
if (!gt2_rxresetdone_i)
begin
gt2_rxresetdone_r <= `DLY 1'b0;
gt2_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt2_rxresetdone_r <= `DLY gt2_rxresetdone_i;
gt2_rxresetdone_r2 <= `DLY gt2_rxresetdone_r;
end
end
always @(posedge gt2_txusrclk_i)
gt2_rxresetdone_r3 <= `DLY gt2_rxresetdone_r2;
always @(posedge gt2_txusrclk_i or negedge gt2_txresetdone_i)
begin
if (!gt2_txresetdone_i)
begin
gt2_txresetdone_r <= `DLY 1'b0;
gt2_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt2_txresetdone_r <= `DLY gt2_txresetdone_i;
gt2_txresetdone_r2 <= `DLY gt2_txresetdone_r;
end
end
always @(posedge gt2_txusrclk_i or negedge gt3_rxresetdone_i)
begin
if (!gt3_rxresetdone_i)
begin
gt3_rxresetdone_r <= `DLY 1'b0;
gt3_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt3_rxresetdone_r <= `DLY gt3_rxresetdone_i;
gt3_rxresetdone_r2 <= `DLY gt3_rxresetdone_r;
end
end
always @(posedge gt2_txusrclk_i)
gt3_rxresetdone_r3 <= `DLY gt3_rxresetdone_r2;
always @(posedge gt2_txusrclk_i or negedge gt3_txresetdone_i)
begin
if (!gt3_txresetdone_i)
begin
gt3_txresetdone_r <= `DLY 1'b0;
gt3_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt3_txresetdone_r <= `DLY gt3_txresetdone_i;
gt3_txresetdone_r2 <= `DLY gt3_txresetdone_r;
end
end
always @(posedge gt4_txusrclk_i or negedge gt4_rxresetdone_i)
begin
if (!gt4_rxresetdone_i)
begin
gt4_rxresetdone_r <= `DLY 1'b0;
gt4_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt4_rxresetdone_r <= `DLY gt4_rxresetdone_i;
gt4_rxresetdone_r2 <= `DLY gt4_rxresetdone_r;
end
end
always @(posedge gt4_txusrclk_i)
gt4_rxresetdone_r3 <= `DLY gt4_rxresetdone_r2;
always @(posedge gt4_txusrclk_i or negedge gt4_txresetdone_i)
begin
if (!gt4_txresetdone_i)
begin
gt4_txresetdone_r <= `DLY 1'b0;
gt4_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt4_txresetdone_r <= `DLY gt4_txresetdone_i;
gt4_txresetdone_r2 <= `DLY gt4_txresetdone_r;
end
end
always @(posedge gt4_txusrclk_i or negedge gt5_rxresetdone_i)
begin
if (!gt5_rxresetdone_i)
begin
gt5_rxresetdone_r <= `DLY 1'b0;
gt5_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt5_rxresetdone_r <= `DLY gt5_rxresetdone_i;
gt5_rxresetdone_r2 <= `DLY gt5_rxresetdone_r;
end
end
always @(posedge gt4_txusrclk_i)
gt5_rxresetdone_r3 <= `DLY gt5_rxresetdone_r2;
always @(posedge gt4_txusrclk_i or negedge gt5_txresetdone_i)
begin
if (!gt5_txresetdone_i)
begin
gt5_txresetdone_r <= `DLY 1'b0;
gt5_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt5_txresetdone_r <= `DLY gt5_txresetdone_i;
gt5_txresetdone_r2 <= `DLY gt5_txresetdone_r;
end
end
always @(posedge gt6_txusrclk_i or negedge gt6_rxresetdone_i)
begin
if (!gt6_rxresetdone_i)
begin
gt6_rxresetdone_r <= `DLY 1'b0;
gt6_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt6_rxresetdone_r <= `DLY gt6_rxresetdone_i;
gt6_rxresetdone_r2 <= `DLY gt6_rxresetdone_r;
end
end
always @(posedge gt6_txusrclk_i)
gt6_rxresetdone_r3 <= `DLY gt6_rxresetdone_r2;
always @(posedge gt6_txusrclk_i or negedge gt6_txresetdone_i)
begin
if (!gt6_txresetdone_i)
begin
gt6_txresetdone_r <= `DLY 1'b0;
gt6_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt6_txresetdone_r <= `DLY gt6_txresetdone_i;
gt6_txresetdone_r2 <= `DLY gt6_txresetdone_r;
end
end
always @(posedge gt6_txusrclk_i or negedge gt7_rxresetdone_i)
begin
if (!gt7_rxresetdone_i)
begin
gt7_rxresetdone_r <= `DLY 1'b0;
gt7_rxresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt7_rxresetdone_r <= `DLY gt7_rxresetdone_i;
gt7_rxresetdone_r2 <= `DLY gt7_rxresetdone_r;
end
end
always @(posedge gt6_txusrclk_i)
gt7_rxresetdone_r3 <= `DLY gt7_rxresetdone_r2;
always @(posedge gt6_txusrclk_i or negedge gt7_txresetdone_i)
begin
if (!gt7_txresetdone_i)
begin
gt7_txresetdone_r <= `DLY 1'b0;
gt7_txresetdone_r2 <= `DLY 1'b0;
end
else
begin
gt7_txresetdone_r <= `DLY gt7_txresetdone_i;
gt7_txresetdone_r2 <= `DLY gt7_txresetdone_r;
end
end
//***********************************************************************//
// //
//------------------------ Frame Generators ---------------------------//
// //
//***********************************************************************//
// The example design uses Block RAM based frame generators to provide test
// data to the GTs for transmission. By default the frame generators are
// loaded with an incrementing data sequence that includes commas/alignment
// characters for alignment. If your protocol uses channel bonding, the
// frame generator will also be preloaded with a channel bonding sequence.
// You can modify the data transmitted by changing the INIT values of the frame
// generator in this file. Pay careful attention to bit order and the spacing
// of your control and alignment characters.
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt0_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt0_txdata_float_i,gt0_txdata_i,gt0_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt0_txusrclk_i),
.SYSTEM_RESET (gt0_tx_system_reset_c)
);
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt1_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt1_txdata_float_i,gt1_txdata_i,gt1_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt0_txusrclk_i),
.SYSTEM_RESET (gt1_tx_system_reset_c)
);
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt2_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt2_txdata_float_i,gt2_txdata_i,gt2_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt2_txusrclk_i),
.SYSTEM_RESET (gt2_tx_system_reset_c)
);
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt3_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt3_txdata_float_i,gt3_txdata_i,gt3_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt2_txusrclk_i),
.SYSTEM_RESET (gt3_tx_system_reset_c)
);
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt4_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt4_txdata_float_i,gt4_txdata_i,gt4_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt4_txusrclk_i),
.SYSTEM_RESET (gt4_tx_system_reset_c)
);
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt5_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt5_txdata_float_i,gt5_txdata_i,gt5_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt4_txusrclk_i),
.SYSTEM_RESET (gt5_tx_system_reset_c)
);
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt6_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt6_txdata_float_i,gt6_txdata_i,gt6_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt6_txusrclk_i),
.SYSTEM_RESET (gt6_tx_system_reset_c)
);
ROCKETIO_WRAPPER_TILE_GT_FRAME_GEN #
(
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM)
)
gt7_frame_gen
(
// User Interface
.TX_DATA_OUT ({gt7_txdata_float_i,gt7_txdata_i,gt7_txdata_float16_i}),
.TXCTRL_OUT (),
// System Interface
.USER_CLK (gt6_txusrclk_i),
.SYSTEM_RESET (gt7_tx_system_reset_c)
);
//***********************************************************************//
// //
//------------------------ Frame Checkers -----------------------------//
// //
//***********************************************************************//
// The example design uses Block RAM based frame checkers to verify incoming
// data. By default the frame generators are loaded with a data sequence that
// matches the outgoing sequence of the frame generators for the TX ports.
// You can modify the expected data sequence by changing the INIT values of the frame
// checkers in this file. Pay careful attention to bit order and the spacing
// of your control and alignment characters.
// When the frame checker receives data, it attempts to synchronise to the
// incoming pattern by looking for the first sequence in the pattern. Once it
// finds the first sequence, it increments through the sequence, and indicates an
// error whenever the next value received does not match the expected value.
assign gt0_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt0_matchn_i;
// gt0_frame_check0 is always connected to the lane with the start of char
// and this lane starts off the data checking on all the other lanes. The INC_IN port is tied off
assign gt0_inc_in_i = 1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt0_frame_check
(
// GT Interface
.RX_DATA_IN (gt0_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt0_txusrclk_i),
.SYSTEM_RESET (gt0_rx_system_reset_c),
.ERROR_COUNT_OUT (gt0_error_count_i),
.RX_SLIDE (gt0_rxslide_i),
.TRACK_DATA_OUT (gt0_track_data_i)
);
assign gt1_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt1_matchn_i;
// in the "independent lanes" configuration, each of the lanes looks for the unique start char and
// in this case, the INC_IN port is tied off.
// Else, the data checking is triggered by the "master" lane
assign gt1_inc_in_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?gt0_inc_out_i:1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt1_frame_check
(
// GT Interface
.RX_DATA_IN (gt1_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt0_txusrclk_i),
.SYSTEM_RESET (gt1_rx_system_reset_c),
.ERROR_COUNT_OUT (gt1_error_count_i),
.RX_SLIDE (gt1_rxslide_i),
.TRACK_DATA_OUT (gt1_track_data_i)
);
assign gt2_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt2_matchn_i;
// in the "independent lanes" configuration, each of the lanes looks for the unique start char and
// in this case, the INC_IN port is tied off.
// Else, the data checking is triggered by the "master" lane
assign gt2_inc_in_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?gt0_inc_out_i:1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt2_frame_check
(
// GT Interface
.RX_DATA_IN (gt2_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt2_txusrclk_i),
.SYSTEM_RESET (gt2_rx_system_reset_c),
.ERROR_COUNT_OUT (gt2_error_count_i),
.RX_SLIDE (gt2_rxslide_i),
.TRACK_DATA_OUT (gt2_track_data_i)
);
assign gt3_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt3_matchn_i;
// in the "independent lanes" configuration, each of the lanes looks for the unique start char and
// in this case, the INC_IN port is tied off.
// Else, the data checking is triggered by the "master" lane
assign gt3_inc_in_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?gt0_inc_out_i:1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt3_frame_check
(
// GT Interface
.RX_DATA_IN (gt3_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt2_txusrclk_i),
.SYSTEM_RESET (gt3_rx_system_reset_c),
.ERROR_COUNT_OUT (gt3_error_count_i),
.RX_SLIDE (gt3_rxslide_i),
.TRACK_DATA_OUT (gt3_track_data_i)
);
assign gt4_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt4_matchn_i;
// in the "independent lanes" configuration, each of the lanes looks for the unique start char and
// in this case, the INC_IN port is tied off.
// Else, the data checking is triggered by the "master" lane
assign gt4_inc_in_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?gt0_inc_out_i:1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt4_frame_check
(
// GT Interface
.RX_DATA_IN (gt4_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt4_txusrclk_i),
.SYSTEM_RESET (gt4_rx_system_reset_c),
.ERROR_COUNT_OUT (gt4_error_count_i),
.RX_SLIDE (gt4_rxslide_i),
.TRACK_DATA_OUT (gt4_track_data_i)
);
assign gt5_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt5_matchn_i;
// in the "independent lanes" configuration, each of the lanes looks for the unique start char and
// in this case, the INC_IN port is tied off.
// Else, the data checking is triggered by the "master" lane
assign gt5_inc_in_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?gt0_inc_out_i:1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt5_frame_check
(
// GT Interface
.RX_DATA_IN (gt5_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt4_txusrclk_i),
.SYSTEM_RESET (gt5_rx_system_reset_c),
.ERROR_COUNT_OUT (gt5_error_count_i),
.RX_SLIDE (gt5_rxslide_i),
.TRACK_DATA_OUT (gt5_track_data_i)
);
assign gt6_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt6_matchn_i;
// in the "independent lanes" configuration, each of the lanes looks for the unique start char and
// in this case, the INC_IN port is tied off.
// Else, the data checking is triggered by the "master" lane
assign gt6_inc_in_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?gt0_inc_out_i:1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt6_frame_check
(
// GT Interface
.RX_DATA_IN (gt6_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt6_txusrclk_i),
.SYSTEM_RESET (gt6_rx_system_reset_c),
.ERROR_COUNT_OUT (gt6_error_count_i),
.RX_SLIDE (gt6_rxslide_i),
.TRACK_DATA_OUT (gt6_track_data_i)
);
assign gt7_frame_check_reset_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?reset_on_data_error_i:gt7_matchn_i;
// in the "independent lanes" configuration, each of the lanes looks for the unique start char and
// in this case, the INC_IN port is tied off.
// Else, the data checking is triggered by the "master" lane
assign gt7_inc_in_i = (EXAMPLE_CONFIG_INDEPENDENT_LANES==0)?gt0_inc_out_i:1'b0;
ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
.RX_DATA_WIDTH(16),
.RXCTRL_WIDTH(2),
.WORDS_IN_BRAM(EXAMPLE_WORDS_IN_BRAM),
.START_OF_PACKET_CHAR(16'h027c)
)
gt7_frame_check
(
// GT Interface
.RX_DATA_IN (gt7_rxdata_i),
.RXENMCOMMADET_OUT ( ),
.RXENPCOMMADET_OUT ( ),
// System Interface
.USER_CLK (gt6_txusrclk_i),
.SYSTEM_RESET (gt7_rx_system_reset_c),
.ERROR_COUNT_OUT (gt7_error_count_i),
.RX_SLIDE (gt7_rxslide_i),
.TRACK_DATA_OUT (gt7_track_data_i)
);
assign TRACK_DATA_OUT = track_data_out_i;
assign track_data_out_i =
gt0_track_data_i &
gt1_track_data_i &
gt2_track_data_i &
gt3_track_data_i &
gt4_track_data_i &
gt5_track_data_i &
gt6_track_data_i &
gt7_track_data_i ;
//-------------------------------------------------------------------------------------
//***********************************************************************//
// //
//--------------------- Chipscope Connections ---------------------------//
// //
//***********************************************************************//
// When the example design is run in hardware, it uses chipscope to allow the
// example design and GT wrapper to be controlled and monitored. The
// EXAMPLE_USE_CHIPSCOPE parameter allows chipscope to be removed for simulation.
generate
if (EXAMPLE_USE_CHIPSCOPE==1)
begin : chipscope
// Shared VIO for all GTs
data_vio shared_vio_i
(
.control (shared_vio_control_i),
.async_in (shared_vio_in_i),
.async_out (shared_vio_out_i),
.sync_in (tied_to_ground_vec_i[31:0]),
.sync_out (),
.clk (tied_to_ground_i)
);
// ICON for all VIOs
icon icon_i
(
.control0 (shared_vio_control_i),
.control1 (tx_data_vio_control_i),
.control2 (rx_data_vio_control_i),
.control3 (ila_control_i)
);
// TX VIO
data_vio tx_data_vio_i
(
.control (tx_data_vio_control_i),
.async_in (tx_data_vio_async_in_i),
.async_out (tx_data_vio_async_out_i),
.sync_in (tx_data_vio_sync_in_i),
.sync_out (tx_data_vio_sync_out_i),
.clk (tx_vio_clk_i)
);
// RX VIO
data_vio rx_data_vio_i
(
.control (rx_data_vio_control_i),
.async_in (rx_data_vio_async_in_i),
.async_out (rx_data_vio_async_out_i),
.sync_in (rx_data_vio_sync_in_i),
.sync_out (rx_data_vio_sync_out_i),
.clk (rx_vio_ila_clk_i)
);
// RX ILA
ila ila_i
(
.control (ila_control_i),
.clk (rx_vio_ila_clk_i),
.trig0 (ila_in_i)
);
// The TX VIO uses GT0's TXUSRCLK2
assign tx_vio_clk_i = gt0_txusrclk_i;
// The RX VIO and ILA uses GT0's RXUSRCLK2
assign rx_vio_ila_clk_i = gt0_txusrclk_i;
// assign resets for frame_gen modules
assign gt0_tx_system_reset_c = !gt0_txresetdone_r2 || user_tx_reset_i;
assign gt1_tx_system_reset_c = !gt1_txresetdone_r2 || user_tx_reset_i;
assign gt2_tx_system_reset_c = !gt2_txresetdone_r2 || user_tx_reset_i;
assign gt3_tx_system_reset_c = !gt3_txresetdone_r2 || user_tx_reset_i;
assign gt4_tx_system_reset_c = !gt4_txresetdone_r2 || user_tx_reset_i;
assign gt5_tx_system_reset_c = !gt5_txresetdone_r2 || user_tx_reset_i;
assign gt6_tx_system_reset_c = !gt6_txresetdone_r2 || user_tx_reset_i;
assign gt7_tx_system_reset_c = !gt7_txresetdone_r2 || user_tx_reset_i;
// assign resets for frame_check modules
assign gt0_rx_system_reset_c = !gt0_rxresetdone_r3 || user_rx_reset_i;
assign gt1_rx_system_reset_c = !gt1_rxresetdone_r3 || user_rx_reset_i;
assign gt2_rx_system_reset_c = !gt2_rxresetdone_r3 || user_rx_reset_i;
assign gt3_rx_system_reset_c = !gt3_rxresetdone_r3 || user_rx_reset_i;
assign gt4_rx_system_reset_c = !gt4_rxresetdone_r3 || user_rx_reset_i;
assign gt5_rx_system_reset_c = !gt5_rxresetdone_r3 || user_rx_reset_i;
assign gt6_rx_system_reset_c = !gt6_rxresetdone_r3 || user_rx_reset_i;
assign gt7_rx_system_reset_c = !gt7_rxresetdone_r3 || user_rx_reset_i;
assign gt0_gtrxreset_i = gtrxreset_i || !gt0_cplllock_i;
assign gt0_gttxreset_i = gttxreset_i || !gt0_cplllock_i;
assign gt1_gtrxreset_i = gtrxreset_i || !gt1_cplllock_i;
assign gt1_gttxreset_i = gttxreset_i || !gt1_cplllock_i;
assign gt2_gtrxreset_i = gtrxreset_i || !gt2_cplllock_i;
assign gt2_gttxreset_i = gttxreset_i || !gt2_cplllock_i;
assign gt3_gtrxreset_i = gtrxreset_i || !gt3_cplllock_i;
assign gt3_gttxreset_i = gttxreset_i || !gt3_cplllock_i;
assign gt4_gtrxreset_i = gtrxreset_i || !gt4_cplllock_i;
assign gt4_gttxreset_i = gttxreset_i || !gt4_cplllock_i;
assign gt5_gtrxreset_i = gtrxreset_i || !gt5_cplllock_i;
assign gt5_gttxreset_i = gttxreset_i || !gt5_cplllock_i;
assign gt6_gtrxreset_i = gtrxreset_i || !gt6_cplllock_i;
assign gt6_gttxreset_i = gttxreset_i || !gt6_cplllock_i;
assign gt7_gtrxreset_i = gtrxreset_i || !gt7_cplllock_i;
assign gt7_gttxreset_i = gttxreset_i || !gt7_cplllock_i;
assign gt0_cpllreset_i = cpllreset_i;
assign gt1_cpllreset_i = cpllreset_i;
assign gt2_cpllreset_i = cpllreset_i;
assign gt3_cpllreset_i = cpllreset_i;
assign gt4_cpllreset_i = cpllreset_i;
assign gt5_cpllreset_i = cpllreset_i;
assign gt6_cpllreset_i = cpllreset_i;
assign gt7_cpllreset_i = cpllreset_i;
// Shared VIO Outputs
assign gttxreset_i = shared_vio_out_i[31];
assign gtrxreset_i = shared_vio_out_i[30];
assign user_tx_reset_i = shared_vio_out_i[29];
assign user_rx_reset_i = shared_vio_out_i[28];
assign mux_sel_i = shared_vio_out_i[27:25];
assign cpllreset_i = shared_vio_out_i[24];
// Shared VIO Inputs
assign shared_vio_in_i[31:0] = 32'b00000000000000000000000000000000;
// Chipscope connections on GT 0
assign gt0_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt0_tx_data_vio_sync_in_i[31] = gt0_txresetdone_i;
assign gt0_tx_data_vio_sync_in_i[30:29] = gt0_txbufstatus_i;
assign gt0_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt0_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt0_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt0_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt0_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt0_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt0_rx_data_vio_sync_in_i[31] = gt0_rxresetdone_i;
assign gt0_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt0_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt0_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt0_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt0_ila_in_i[163:162] = gt0_rxclkcorcnt_i;
assign gt0_ila_in_i[161] = gt0_rxbyteisaligned_i;
assign gt0_ila_in_i[160] = gt0_rxbyterealign_i;
assign gt0_ila_in_i[159] = gt0_rxcommadet_i;
assign gt0_ila_in_i[158:143] = gt0_rxdata_i;
assign gt0_ila_in_i[142:140] = gt0_rxbufstatus_i;
assign gt0_ila_in_i[139] = gt0_rxvalid_i;
assign gt0_ila_in_i[138:131] = gt0_error_count_i;
assign gt0_ila_in_i[130] = gt0_track_data_i;
assign gt0_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// Chipscope connections on GT 1
assign gt1_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt1_tx_data_vio_sync_in_i[31] = gt1_txresetdone_i;
assign gt1_tx_data_vio_sync_in_i[30:29] = gt1_txbufstatus_i;
assign gt1_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt1_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt1_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt1_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt1_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt1_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt1_rx_data_vio_sync_in_i[31] = gt1_rxresetdone_i;
assign gt1_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt1_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt1_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt1_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt1_ila_in_i[163:162] = gt1_rxclkcorcnt_i;
assign gt1_ila_in_i[161] = gt1_rxbyteisaligned_i;
assign gt1_ila_in_i[160] = gt1_rxbyterealign_i;
assign gt1_ila_in_i[159] = gt1_rxcommadet_i;
assign gt1_ila_in_i[158:143] = gt1_rxdata_i;
assign gt1_ila_in_i[142:140] = gt1_rxbufstatus_i;
assign gt1_ila_in_i[139] = gt1_rxvalid_i;
assign gt1_ila_in_i[138:131] = gt1_error_count_i;
assign gt1_ila_in_i[130] = gt1_track_data_i;
assign gt1_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// Chipscope connections on GT 2
assign gt2_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt2_tx_data_vio_sync_in_i[31] = gt2_txresetdone_i;
assign gt2_tx_data_vio_sync_in_i[30:29] = gt2_txbufstatus_i;
assign gt2_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt2_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt2_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt2_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt2_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt2_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt2_rx_data_vio_sync_in_i[31] = gt2_rxresetdone_i;
assign gt2_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt2_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt2_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt2_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt2_ila_in_i[163:162] = gt2_rxclkcorcnt_i;
assign gt2_ila_in_i[161] = gt2_rxbyteisaligned_i;
assign gt2_ila_in_i[160] = gt2_rxbyterealign_i;
assign gt2_ila_in_i[159] = gt2_rxcommadet_i;
assign gt2_ila_in_i[158:143] = gt2_rxdata_i;
assign gt2_ila_in_i[142:140] = gt2_rxbufstatus_i;
assign gt2_ila_in_i[139] = gt2_rxvalid_i;
assign gt2_ila_in_i[138:131] = gt2_error_count_i;
assign gt2_ila_in_i[130] = gt2_track_data_i;
assign gt2_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// Chipscope connections on GT 3
assign gt3_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt3_tx_data_vio_sync_in_i[31] = gt3_txresetdone_i;
assign gt3_tx_data_vio_sync_in_i[30:29] = gt3_txbufstatus_i;
assign gt3_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt3_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt3_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt3_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt3_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt3_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt3_rx_data_vio_sync_in_i[31] = gt3_rxresetdone_i;
assign gt3_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt3_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt3_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt3_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt3_ila_in_i[163:162] = gt3_rxclkcorcnt_i;
assign gt3_ila_in_i[161] = gt3_rxbyteisaligned_i;
assign gt3_ila_in_i[160] = gt3_rxbyterealign_i;
assign gt3_ila_in_i[159] = gt3_rxcommadet_i;
assign gt3_ila_in_i[158:143] = gt3_rxdata_i;
assign gt3_ila_in_i[142:140] = gt3_rxbufstatus_i;
assign gt3_ila_in_i[139] = gt3_rxvalid_i;
assign gt3_ila_in_i[138:131] = gt3_error_count_i;
assign gt3_ila_in_i[130] = gt3_track_data_i;
assign gt3_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// Chipscope connections on GT 4
assign gt4_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt4_tx_data_vio_sync_in_i[31] = gt4_txresetdone_i;
assign gt4_tx_data_vio_sync_in_i[30:29] = gt4_txbufstatus_i;
assign gt4_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt4_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt4_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt4_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt4_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt4_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt4_rx_data_vio_sync_in_i[31] = gt4_rxresetdone_i;
assign gt4_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt4_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt4_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt4_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt4_ila_in_i[163:162] = gt4_rxclkcorcnt_i;
assign gt4_ila_in_i[161] = gt4_rxbyteisaligned_i;
assign gt4_ila_in_i[160] = gt4_rxbyterealign_i;
assign gt4_ila_in_i[159] = gt4_rxcommadet_i;
assign gt4_ila_in_i[158:143] = gt4_rxdata_i;
assign gt4_ila_in_i[142:140] = gt4_rxbufstatus_i;
assign gt4_ila_in_i[139] = gt4_rxvalid_i;
assign gt4_ila_in_i[138:131] = gt4_error_count_i;
assign gt4_ila_in_i[130] = gt4_track_data_i;
assign gt4_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// Chipscope connections on GT 5
assign gt5_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt5_tx_data_vio_sync_in_i[31] = gt5_txresetdone_i;
assign gt5_tx_data_vio_sync_in_i[30:29] = gt5_txbufstatus_i;
assign gt5_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt5_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt5_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt5_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt5_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt5_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt5_rx_data_vio_sync_in_i[31] = gt5_rxresetdone_i;
assign gt5_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt5_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt5_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt5_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt5_ila_in_i[163:162] = gt5_rxclkcorcnt_i;
assign gt5_ila_in_i[161] = gt5_rxbyteisaligned_i;
assign gt5_ila_in_i[160] = gt5_rxbyterealign_i;
assign gt5_ila_in_i[159] = gt5_rxcommadet_i;
assign gt5_ila_in_i[158:143] = gt5_rxdata_i;
assign gt5_ila_in_i[142:140] = gt5_rxbufstatus_i;
assign gt5_ila_in_i[139] = gt5_rxvalid_i;
assign gt5_ila_in_i[138:131] = gt5_error_count_i;
assign gt5_ila_in_i[130] = gt5_track_data_i;
assign gt5_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// Chipscope connections on GT 6
assign gt6_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt6_tx_data_vio_sync_in_i[31] = gt6_txresetdone_i;
assign gt6_tx_data_vio_sync_in_i[30:29] = gt6_txbufstatus_i;
assign gt6_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt6_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt6_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt6_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt6_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt6_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt6_rx_data_vio_sync_in_i[31] = gt6_rxresetdone_i;
assign gt6_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt6_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt6_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt6_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt6_ila_in_i[163:162] = gt6_rxclkcorcnt_i;
assign gt6_ila_in_i[161] = gt6_rxbyteisaligned_i;
assign gt6_ila_in_i[160] = gt6_rxbyterealign_i;
assign gt6_ila_in_i[159] = gt6_rxcommadet_i;
assign gt6_ila_in_i[158:143] = gt6_rxdata_i;
assign gt6_ila_in_i[142:140] = gt6_rxbufstatus_i;
assign gt6_ila_in_i[139] = gt6_rxvalid_i;
assign gt6_ila_in_i[138:131] = gt6_error_count_i;
assign gt6_ila_in_i[130] = gt6_track_data_i;
assign gt6_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// Chipscope connections on GT 7
assign gt7_tx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt7_tx_data_vio_sync_in_i[31] = gt7_txresetdone_i;
assign gt7_tx_data_vio_sync_in_i[30:29] = gt7_txbufstatus_i;
assign gt7_tx_data_vio_sync_in_i[28:0] = 29'b00000000000000000000000000000;
assign gt7_loopback_i = tx_data_vio_async_out_i[31:29];
assign gt7_txprecursorinv_i = tx_data_vio_async_out_i[28];
assign gt7_txuserrdy_i = tx_data_vio_sync_out_i[31];
assign gt7_txpd_i = tx_data_vio_sync_out_i[30:29];
assign gt7_rx_data_vio_async_in_i[31:0] = 32'b00000000000000000000000000000000;
assign gt7_rx_data_vio_sync_in_i[31] = gt7_rxresetdone_i;
assign gt7_rx_data_vio_sync_in_i[30:0] = 31'b0000000000000000000000000000000;
assign gt7_rxuserrdy_i = rx_data_vio_async_out_i[31];
assign gt7_rxpd_i = rx_data_vio_async_out_i[30:29];
assign gt7_rxbufreset_i = rx_data_vio_async_out_i[28];
assign gt7_ila_in_i[163:162] = gt7_rxclkcorcnt_i;
assign gt7_ila_in_i[161] = gt7_rxbyteisaligned_i;
assign gt7_ila_in_i[160] = gt7_rxbyterealign_i;
assign gt7_ila_in_i[159] = gt7_rxcommadet_i;
assign gt7_ila_in_i[158:143] = gt7_rxdata_i;
assign gt7_ila_in_i[142:140] = gt7_rxbufstatus_i;
assign gt7_ila_in_i[139] = gt7_rxvalid_i;
assign gt7_ila_in_i[138:131] = gt7_error_count_i;
assign gt7_ila_in_i[130] = gt7_track_data_i;
assign gt7_ila_in_i[129:0] = 130'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign tx_data_vio_async_in_i = (mux_sel_i == 3'b000)?gt0_tx_data_vio_async_in_i:
(mux_sel_i == 3'b001)?gt1_tx_data_vio_async_in_i:
(mux_sel_i == 3'b010)?gt2_tx_data_vio_async_in_i:
(mux_sel_i == 3'b011)?gt3_tx_data_vio_async_in_i:
(mux_sel_i == 3'b100)?gt4_tx_data_vio_async_in_i:
(mux_sel_i == 3'b101)?gt5_tx_data_vio_async_in_i:
(mux_sel_i == 3'b110)?gt6_tx_data_vio_async_in_i:
gt7_tx_data_vio_async_in_i;
assign tx_data_vio_sync_in_i = (mux_sel_i == 3'b000)?gt0_tx_data_vio_sync_in_i:
(mux_sel_i == 3'b001)?gt1_tx_data_vio_sync_in_i:
(mux_sel_i == 3'b010)?gt2_tx_data_vio_sync_in_i:
(mux_sel_i == 3'b011)?gt3_tx_data_vio_sync_in_i:
(mux_sel_i == 3'b100)?gt4_tx_data_vio_sync_in_i:
(mux_sel_i == 3'b101)?gt5_tx_data_vio_sync_in_i:
(mux_sel_i == 3'b110)?gt6_tx_data_vio_sync_in_i:
gt7_tx_data_vio_sync_in_i;
assign rx_data_vio_async_in_i = (mux_sel_i == 3'b000)?gt0_rx_data_vio_async_in_i:
(mux_sel_i == 3'b001)?gt1_rx_data_vio_async_in_i:
(mux_sel_i == 3'b010)?gt2_rx_data_vio_async_in_i:
(mux_sel_i == 3'b011)?gt3_rx_data_vio_async_in_i:
(mux_sel_i == 3'b100)?gt4_rx_data_vio_async_in_i:
(mux_sel_i == 3'b101)?gt5_rx_data_vio_async_in_i:
(mux_sel_i == 3'b110)?gt6_rx_data_vio_async_in_i:
gt7_rx_data_vio_async_in_i;
assign rx_data_vio_sync_in_i = (mux_sel_i == 3'b000)?gt0_rx_data_vio_sync_in_i:
(mux_sel_i == 3'b001)?gt1_rx_data_vio_sync_in_i:
(mux_sel_i == 3'b010)?gt2_rx_data_vio_sync_in_i:
(mux_sel_i == 3'b011)?gt3_rx_data_vio_sync_in_i:
(mux_sel_i == 3'b100)?gt4_rx_data_vio_sync_in_i:
(mux_sel_i == 3'b101)?gt5_rx_data_vio_sync_in_i:
(mux_sel_i == 3'b110)?gt6_rx_data_vio_sync_in_i:
gt7_rx_data_vio_sync_in_i;
assign ila_in_i = (mux_sel_i == 3'b000)?gt0_ila_in_i:
(mux_sel_i == 3'b001)?gt1_ila_in_i:
(mux_sel_i == 3'b010)?gt2_ila_in_i:
(mux_sel_i == 3'b011)?gt3_ila_in_i:
(mux_sel_i == 3'b100)?gt4_ila_in_i:
(mux_sel_i == 3'b101)?gt5_ila_in_i:
(mux_sel_i == 3'b110)?gt6_ila_in_i:
gt7_ila_in_i;
end //end EXAMPLE_USE_CHIPSCOPE=1 generate section
else
begin: no_chipscope
// If Chipscope is not being used, drive GT reset signal
// from the top level ports
//***********************************************************************//
// //
//--------------------- Reset Logic -----------------------------------//
// //
//***********************************************************************//
// The Example design supports Sequence Mode; hence PCS and PMA resets
// are tied to ground. In Single mode, the user needs to follow the
// reset sequencing given in the user guide.
assign gt0_rxuserrdy_i = gt0_rxuserrdy_r;
assign gt0_txuserrdy_i = gt0_txuserrdy_r;
assign gt1_rxuserrdy_i = gt1_rxuserrdy_r;
assign gt1_txuserrdy_i = gt1_txuserrdy_r;
assign gt2_rxuserrdy_i = gt2_rxuserrdy_r;
assign gt2_txuserrdy_i = gt2_txuserrdy_r;
assign gt3_rxuserrdy_i = gt3_rxuserrdy_r;
assign gt3_txuserrdy_i = gt3_txuserrdy_r;
assign gt4_rxuserrdy_i = gt4_rxuserrdy_r;
assign gt4_txuserrdy_i = gt4_txuserrdy_r;
assign gt5_rxuserrdy_i = gt5_rxuserrdy_r;
assign gt5_txuserrdy_i = gt5_txuserrdy_r;
assign gt6_rxuserrdy_i = gt6_rxuserrdy_r;
assign gt6_txuserrdy_i = gt6_txuserrdy_r;
assign gt7_rxuserrdy_i = gt7_rxuserrdy_r;
assign gt7_txuserrdy_i = gt7_txuserrdy_r;
always @(posedge gt0_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt0_rxuserrdy_r <= `DLY 1'b0;
else
gt0_rxuserrdy_r <= `DLY gt0_cplllock_i;
end
always @(posedge gt0_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt0_txuserrdy_r <= `DLY 1'b0;
else
gt0_txuserrdy_r <= `DLY gt0_cplllock_i;
end
always @(posedge gt0_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt1_rxuserrdy_r <= `DLY 1'b0;
else
gt1_rxuserrdy_r <= `DLY gt1_cplllock_i;
end
always @(posedge gt0_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt1_txuserrdy_r <= `DLY 1'b0;
else
gt1_txuserrdy_r <= `DLY gt1_cplllock_i;
end
always @(posedge gt2_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt2_rxuserrdy_r <= `DLY 1'b0;
else
gt2_rxuserrdy_r <= `DLY gt2_cplllock_i;
end
always @(posedge gt2_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt2_txuserrdy_r <= `DLY 1'b0;
else
gt2_txuserrdy_r <= `DLY gt2_cplllock_i;
end
always @(posedge gt2_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt3_rxuserrdy_r <= `DLY 1'b0;
else
gt3_rxuserrdy_r <= `DLY gt3_cplllock_i;
end
always @(posedge gt2_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt3_txuserrdy_r <= `DLY 1'b0;
else
gt3_txuserrdy_r <= `DLY gt3_cplllock_i;
end
always @(posedge gt4_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt4_rxuserrdy_r <= `DLY 1'b0;
else
gt4_rxuserrdy_r <= `DLY gt4_cplllock_i;
end
always @(posedge gt4_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt4_txuserrdy_r <= `DLY 1'b0;
else
gt4_txuserrdy_r <= `DLY gt4_cplllock_i;
end
always @(posedge gt4_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt5_rxuserrdy_r <= `DLY 1'b0;
else
gt5_rxuserrdy_r <= `DLY gt5_cplllock_i;
end
always @(posedge gt4_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt5_txuserrdy_r <= `DLY 1'b0;
else
gt5_txuserrdy_r <= `DLY gt5_cplllock_i;
end
always @(posedge gt6_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt6_rxuserrdy_r <= `DLY 1'b0;
else
gt6_rxuserrdy_r <= `DLY gt6_cplllock_i;
end
always @(posedge gt6_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt6_txuserrdy_r <= `DLY 1'b0;
else
gt6_txuserrdy_r <= `DLY gt6_cplllock_i;
end
always @(posedge gt6_txusrclk_i or posedge GTRXRESET_IN)
begin
if(GTRXRESET_IN)
gt7_rxuserrdy_r <= `DLY 1'b0;
else
gt7_rxuserrdy_r <= `DLY gt7_cplllock_i;
end
always @(posedge gt6_txusrclk_i or posedge GTTXRESET_IN)
begin
if(GTTXRESET_IN)
gt7_txuserrdy_r <= `DLY 1'b0;
else
gt7_txuserrdy_r <= `DLY gt7_cplllock_i;
end
assign gt0_gtrxreset_i = GTRXRESET_IN || !gt0_cplllock_i;
assign gt0_gttxreset_i = GTTXRESET_IN || !gt0_cplllock_i;
assign gt0_cpllreset_i = GTTXRESET_IN;
assign gt1_gtrxreset_i = GTRXRESET_IN || !gt1_cplllock_i;
assign gt1_gttxreset_i = GTTXRESET_IN || !gt1_cplllock_i;
assign gt1_cpllreset_i = GTTXRESET_IN;
assign gt2_gtrxreset_i = GTRXRESET_IN || !gt2_cplllock_i;
assign gt2_gttxreset_i = GTTXRESET_IN || !gt2_cplllock_i;
assign gt2_cpllreset_i = GTTXRESET_IN;
assign gt3_gtrxreset_i = GTRXRESET_IN || !gt3_cplllock_i;
assign gt3_gttxreset_i = GTTXRESET_IN || !gt3_cplllock_i;
assign gt3_cpllreset_i = GTTXRESET_IN;
assign gt4_gtrxreset_i = GTRXRESET_IN || !gt4_cplllock_i;
assign gt4_gttxreset_i = GTTXRESET_IN || !gt4_cplllock_i;
assign gt4_cpllreset_i = GTTXRESET_IN;
assign gt5_gtrxreset_i = GTRXRESET_IN || !gt5_cplllock_i;
assign gt5_gttxreset_i = GTTXRESET_IN || !gt5_cplllock_i;
assign gt5_cpllreset_i = GTTXRESET_IN;
assign gt6_gtrxreset_i = GTRXRESET_IN || !gt6_cplllock_i;
assign gt6_gttxreset_i = GTTXRESET_IN || !gt6_cplllock_i;
assign gt6_cpllreset_i = GTTXRESET_IN;
assign gt7_gtrxreset_i = GTRXRESET_IN || !gt7_cplllock_i;
assign gt7_gttxreset_i = GTTXRESET_IN || !gt7_cplllock_i;
assign gt7_cpllreset_i = GTTXRESET_IN;
assign gt0_rxpcsreset_i = tied_to_ground_i;
assign gt0_txpcsreset_i = tied_to_ground_i;
assign gt1_rxpcsreset_i = tied_to_ground_i;
assign gt1_txpcsreset_i = tied_to_ground_i;
assign gt2_rxpcsreset_i = tied_to_ground_i;
assign gt2_txpcsreset_i = tied_to_ground_i;
assign gt3_rxpcsreset_i = tied_to_ground_i;
assign gt3_txpcsreset_i = tied_to_ground_i;
assign gt4_rxpcsreset_i = tied_to_ground_i;
assign gt4_txpcsreset_i = tied_to_ground_i;
assign gt5_rxpcsreset_i = tied_to_ground_i;
assign gt5_txpcsreset_i = tied_to_ground_i;
assign gt6_rxpcsreset_i = tied_to_ground_i;
assign gt6_txpcsreset_i = tied_to_ground_i;
assign gt7_rxpcsreset_i = tied_to_ground_i;
assign gt7_txpcsreset_i = tied_to_ground_i;
// assign resets for frame_gen modules
assign gt0_tx_system_reset_c = !gt0_txresetdone_r2;
assign gt1_tx_system_reset_c = !gt1_txresetdone_r2;
assign gt2_tx_system_reset_c = !gt2_txresetdone_r2;
assign gt3_tx_system_reset_c = !gt3_txresetdone_r2;
assign gt4_tx_system_reset_c = !gt4_txresetdone_r2;
assign gt5_tx_system_reset_c = !gt5_txresetdone_r2;
assign gt6_tx_system_reset_c = !gt6_txresetdone_r2;
assign gt7_tx_system_reset_c = !gt7_txresetdone_r2;
// assign resets for frame_check modules
assign gt0_rx_system_reset_c = !gt0_rxresetdone_r3;
assign gt1_rx_system_reset_c = !gt1_rxresetdone_r3;
assign gt2_rx_system_reset_c = !gt2_rxresetdone_r3;
assign gt3_rx_system_reset_c = !gt3_rxresetdone_r3;
assign gt4_rx_system_reset_c = !gt4_rxresetdone_r3;
assign gt5_rx_system_reset_c = !gt5_rxresetdone_r3;
assign gt6_rx_system_reset_c = !gt6_rxresetdone_r3;
assign gt7_rx_system_reset_c = !gt7_rxresetdone_r3;
//-------------------------------------------------------------
assign gttxreset_i = tied_to_ground_i;
assign gtrxreset_i = tied_to_ground_i;
assign user_tx_reset_i = tied_to_ground_i;
assign user_rx_reset_i = tied_to_ground_i;
assign mux_sel_i = tied_to_ground_vec_i[2:0];
assign gt0_loopback_i = tied_to_ground_vec_i[2:0];
assign gt0_txprecursorinv_i = tied_to_ground_i;
assign gt0_txpd_i = tied_to_ground_vec_i[1:0];
assign gt0_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt0_rxbufreset_i = tied_to_ground_i;
assign gt1_loopback_i = tied_to_ground_vec_i[2:0];
assign gt1_txprecursorinv_i = tied_to_ground_i;
assign gt1_txpd_i = tied_to_ground_vec_i[1:0];
assign gt1_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt1_rxbufreset_i = tied_to_ground_i;
assign gt2_loopback_i = tied_to_ground_vec_i[2:0];
assign gt2_txprecursorinv_i = tied_to_ground_i;
assign gt2_txpd_i = tied_to_ground_vec_i[1:0];
assign gt2_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt2_rxbufreset_i = tied_to_ground_i;
assign gt3_loopback_i = tied_to_ground_vec_i[2:0];
assign gt3_txprecursorinv_i = tied_to_ground_i;
assign gt3_txpd_i = tied_to_ground_vec_i[1:0];
assign gt3_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt3_rxbufreset_i = tied_to_ground_i;
assign gt4_loopback_i = tied_to_ground_vec_i[2:0];
assign gt4_txprecursorinv_i = tied_to_ground_i;
assign gt4_txpd_i = tied_to_ground_vec_i[1:0];
assign gt4_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt4_rxbufreset_i = tied_to_ground_i;
assign gt5_loopback_i = tied_to_ground_vec_i[2:0];
assign gt5_txprecursorinv_i = tied_to_ground_i;
assign gt5_txpd_i = tied_to_ground_vec_i[1:0];
assign gt5_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt5_rxbufreset_i = tied_to_ground_i;
assign gt6_loopback_i = tied_to_ground_vec_i[2:0];
assign gt6_txprecursorinv_i = tied_to_ground_i;
assign gt6_txpd_i = tied_to_ground_vec_i[1:0];
assign gt6_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt6_rxbufreset_i = tied_to_ground_i;
assign gt7_loopback_i = tied_to_ground_vec_i[2:0];
assign gt7_txprecursorinv_i = tied_to_ground_i;
assign gt7_txpd_i = tied_to_ground_vec_i[1:0];
assign gt7_rxpd_i = tied_to_ground_vec_i[1:0];
assign gt7_rxbufreset_i = tied_to_ground_i;
end
endgenerate //End generate for EXAMPLE_USE_CHIPSCOPE
endmodule
//-------------------------------------------------------------------
//
// VIO core module declaration
//
//-------------------------------------------------------------------
module data_vio
(
control,
clk,
async_in,
async_out,
sync_in,
sync_out
);
inout [35:0] control;
input clk;
input [31:0] async_in;
output [31:0] async_out;
input [31:0] sync_in;
output [31:0] sync_out;
endmodule
//-------------------------------------------------------------------
//
// ICON core module declaration
//
//-------------------------------------------------------------------
module icon
(
control0,
control1,
control2,
control3
);
inout [35:0] control0;
inout [35:0] control1;
inout [35:0] control2;
inout [35:0] control3;
endmodule
//-------------------------------------------------------------------
//
// ILA core module declaration
// This is used to allow RX signals to be monitored
//
//-------------------------------------------------------------------
module ila
(
control,
clk,
trig0
);
inout [35:0] control;
input clk ;
input [163:0] trig0 ;
endmodule
|
// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3
// Component : VexRiscv
// Git hash : 22555b464a02d8b7f8ed23cbb87c57aa9acddc90
`define Input2Kind_binary_sequential_type [0:0]
`define Input2Kind_binary_sequential_RS 1'b0
`define Input2Kind_binary_sequential_IMM_I 1'b1
`define EnvCtrlEnum_binary_sequential_type [1:0]
`define EnvCtrlEnum_binary_sequential_NONE 2'b00
`define EnvCtrlEnum_binary_sequential_XRET 2'b01
`define EnvCtrlEnum_binary_sequential_WFI 2'b10
`define EnvCtrlEnum_binary_sequential_ECALL 2'b11
`define BranchCtrlEnum_binary_sequential_type [1:0]
`define BranchCtrlEnum_binary_sequential_INC 2'b00
`define BranchCtrlEnum_binary_sequential_B 2'b01
`define BranchCtrlEnum_binary_sequential_JAL 2'b10
`define BranchCtrlEnum_binary_sequential_JALR 2'b11
`define ShiftCtrlEnum_binary_sequential_type [1:0]
`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00
`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01
`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10
`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11
`define AluBitwiseCtrlEnum_binary_sequential_type [1:0]
`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00
`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01
`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10
`define Src2CtrlEnum_binary_sequential_type [1:0]
`define Src2CtrlEnum_binary_sequential_RS 2'b00
`define Src2CtrlEnum_binary_sequential_IMI 2'b01
`define Src2CtrlEnum_binary_sequential_IMS 2'b10
`define Src2CtrlEnum_binary_sequential_PC 2'b11
`define AluCtrlEnum_binary_sequential_type [1:0]
`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00
`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01
`define AluCtrlEnum_binary_sequential_BITWISE 2'b10
`define Src1CtrlEnum_binary_sequential_type [1:0]
`define Src1CtrlEnum_binary_sequential_RS 2'b00
`define Src1CtrlEnum_binary_sequential_IMU 2'b01
`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10
`define Src1CtrlEnum_binary_sequential_URS1 2'b11
module VexRiscv (
input [31:0] externalResetVector,
input timerInterrupt,
input softwareInterrupt,
input [31:0] externalInterruptArray,
input debug_bus_cmd_valid,
output reg debug_bus_cmd_ready,
input debug_bus_cmd_payload_wr,
input [7:0] debug_bus_cmd_payload_address,
input [31:0] debug_bus_cmd_payload_data,
output reg [31:0] debug_bus_rsp_data,
output debug_resetOut,
output CfuPlugin_bus_cmd_valid,
input CfuPlugin_bus_cmd_ready,
output [9:0] CfuPlugin_bus_cmd_payload_function_id,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_0,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_1,
input CfuPlugin_bus_rsp_valid,
output CfuPlugin_bus_rsp_ready,
input [31:0] CfuPlugin_bus_rsp_payload_outputs_0,
output reg iBusWishbone_CYC,
output reg iBusWishbone_STB,
input iBusWishbone_ACK,
output iBusWishbone_WE,
output [29:0] iBusWishbone_ADR,
input [31:0] iBusWishbone_DAT_MISO,
output [31:0] iBusWishbone_DAT_MOSI,
output [3:0] iBusWishbone_SEL,
input iBusWishbone_ERR,
output [2:0] iBusWishbone_CTI,
output [1:0] iBusWishbone_BTE,
output dBusWishbone_CYC,
output dBusWishbone_STB,
input dBusWishbone_ACK,
output dBusWishbone_WE,
output [29:0] dBusWishbone_ADR,
input [31:0] dBusWishbone_DAT_MISO,
output [31:0] dBusWishbone_DAT_MOSI,
output [3:0] dBusWishbone_SEL,
input dBusWishbone_ERR,
output [2:0] dBusWishbone_CTI,
output [1:0] dBusWishbone_BTE,
input clk,
input reset,
input debugReset
);
wire IBusCachedPlugin_cache_io_flush;
wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck;
wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved;
wire IBusCachedPlugin_cache_io_cpu_decode_isValid;
wire IBusCachedPlugin_cache_io_cpu_decode_isStuck;
wire IBusCachedPlugin_cache_io_cpu_decode_isUser;
reg IBusCachedPlugin_cache_io_cpu_fill_valid;
wire dataCache_1_io_cpu_execute_isValid;
wire [31:0] dataCache_1_io_cpu_execute_address;
wire dataCache_1_io_cpu_memory_isValid;
wire [31:0] dataCache_1_io_cpu_memory_address;
reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess;
reg dataCache_1_io_cpu_writeBack_isValid;
wire dataCache_1_io_cpu_writeBack_isUser;
wire [31:0] dataCache_1_io_cpu_writeBack_storeData;
wire [31:0] dataCache_1_io_cpu_writeBack_address;
wire dataCache_1_io_cpu_writeBack_fence_SW;
wire dataCache_1_io_cpu_writeBack_fence_SR;
wire dataCache_1_io_cpu_writeBack_fence_SO;
wire dataCache_1_io_cpu_writeBack_fence_SI;
wire dataCache_1_io_cpu_writeBack_fence_PW;
wire dataCache_1_io_cpu_writeBack_fence_PR;
wire dataCache_1_io_cpu_writeBack_fence_PO;
wire dataCache_1_io_cpu_writeBack_fence_PI;
wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM;
wire dataCache_1_io_cpu_flush_valid;
wire dataCache_1_io_mem_cmd_ready;
reg [31:0] _zz_RegFilePlugin_regFile_port0;
reg [31:0] _zz_RegFilePlugin_regFile_port1;
wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
wire IBusCachedPlugin_cache_io_cpu_decode_error;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuException;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
wire IBusCachedPlugin_cache_io_mem_cmd_valid;
wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
wire dataCache_1_io_cpu_execute_haltIt;
wire dataCache_1_io_cpu_execute_refilling;
wire dataCache_1_io_cpu_memory_isWrite;
wire dataCache_1_io_cpu_writeBack_haltIt;
wire [31:0] dataCache_1_io_cpu_writeBack_data;
wire dataCache_1_io_cpu_writeBack_mmuException;
wire dataCache_1_io_cpu_writeBack_unalignedAccess;
wire dataCache_1_io_cpu_writeBack_accessError;
wire dataCache_1_io_cpu_writeBack_isWrite;
wire dataCache_1_io_cpu_writeBack_keepMemRspData;
wire dataCache_1_io_cpu_writeBack_exclusiveOk;
wire dataCache_1_io_cpu_flush_ready;
wire dataCache_1_io_cpu_redo;
wire dataCache_1_io_mem_cmd_valid;
wire dataCache_1_io_mem_cmd_payload_wr;
wire dataCache_1_io_mem_cmd_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_payload_size;
wire dataCache_1_io_mem_cmd_payload_last;
wire [51:0] _zz_memory_MUL_LOW;
wire [51:0] _zz_memory_MUL_LOW_1;
wire [51:0] _zz_memory_MUL_LOW_2;
wire [51:0] _zz_memory_MUL_LOW_3;
wire [32:0] _zz_memory_MUL_LOW_4;
wire [51:0] _zz_memory_MUL_LOW_5;
wire [49:0] _zz_memory_MUL_LOW_6;
wire [51:0] _zz_memory_MUL_LOW_7;
wire [49:0] _zz_memory_MUL_LOW_8;
wire [31:0] _zz_execute_SHIFT_RIGHT;
wire [32:0] _zz_execute_SHIFT_RIGHT_1;
wire [32:0] _zz_execute_SHIFT_RIGHT_2;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2;
wire _zz_decode_LEGAL_INSTRUCTION_3;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4;
wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8;
wire _zz_decode_LEGAL_INSTRUCTION_9;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10;
wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14;
wire _zz_decode_LEGAL_INSTRUCTION_15;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16;
wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17;
wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1;
reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6;
wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc;
wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1;
wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2;
wire [19:0] _zz__zz_2;
wire [11:0] _zz__zz_4;
wire [31:0] _zz__zz_6;
wire [31:0] _zz__zz_6_1;
wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload;
wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted;
wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2;
wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6;
wire [27:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20;
wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35;
wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47;
wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70;
wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102;
wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127;
wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140;
wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168;
wire _zz_RegFilePlugin_regFile_port;
wire _zz_decode_RegFilePlugin_rs1Data;
wire _zz_RegFilePlugin_regFile_port_1;
wire _zz_decode_RegFilePlugin_rs2Data;
wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA;
wire [2:0] _zz__zz_execute_SRC1;
wire [4:0] _zz__zz_execute_SRC1_1;
wire [11:0] _zz__zz_execute_SRC2_3;
wire [31:0] _zz_execute_SrcPlugin_addSub;
wire [31:0] _zz_execute_SrcPlugin_addSub_1;
wire [31:0] _zz_execute_SrcPlugin_addSub_2;
wire [31:0] _zz_execute_SrcPlugin_addSub_3;
wire [31:0] _zz_execute_SrcPlugin_addSub_4;
wire [31:0] _zz_execute_SrcPlugin_addSub_5;
wire [31:0] _zz_execute_SrcPlugin_addSub_6;
wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2;
wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2;
wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2;
wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4;
wire _zz_execute_BranchPlugin_branch_src2_6;
wire _zz_execute_BranchPlugin_branch_src2_7;
wire _zz_execute_BranchPlugin_branch_src2_8;
wire [2:0] _zz_execute_BranchPlugin_branch_src2_9;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1;
wire _zz_when;
wire _zz_when_1;
wire [65:0] _zz_writeBack_MulPlugin_result;
wire [65:0] _zz_writeBack_MulPlugin_result_1;
wire [31:0] _zz__zz_decode_RS2_2;
wire [31:0] _zz__zz_decode_RS2_2_1;
wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext;
wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator;
wire [32:0] _zz_memory_DivPlugin_div_result_1;
wire [32:0] _zz_memory_DivPlugin_div_result_2;
wire [32:0] _zz_memory_DivPlugin_div_result_3;
wire [32:0] _zz_memory_DivPlugin_div_result_4;
wire [0:0] _zz_memory_DivPlugin_div_result_5;
wire [32:0] _zz_memory_DivPlugin_rs1_2;
wire [0:0] _zz_memory_DivPlugin_rs1_3;
wire [31:0] _zz_memory_DivPlugin_rs2_1;
wire [0:0] _zz_memory_DivPlugin_rs2_2;
wire [9:0] _zz_execute_CfuPlugin_functionsIds_0;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25;
wire [26:0] _zz_iBusWishbone_ADR_1;
wire [51:0] memory_MUL_LOW;
wire writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire execute_CfuPlugin_CFU_IN_FLIGHT;
wire [33:0] memory_MUL_HH;
wire [33:0] execute_MUL_HH;
wire [33:0] execute_MUL_HL;
wire [33:0] execute_MUL_LH;
wire [31:0] execute_MUL_LL;
wire [31:0] execute_SHIFT_RIGHT;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire [31:0] memory_MEMORY_STORE_DATA_RF;
wire [31:0] execute_MEMORY_STORE_DATA_RF;
wire decode_DO_EBREAK;
wire decode_CSR_READ_OPCODE;
wire decode_CSR_WRITE_OPCODE;
wire decode_PREDICTION_HAD_BRANCHED2;
wire decode_SRC2_FORCE_ZERO;
wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
wire decode_CfuPlugin_CFU_ENABLE;
wire decode_IS_RS2_SIGNED;
wire decode_IS_RS1_SIGNED;
wire decode_IS_DIV;
wire memory_IS_MUL;
wire execute_IS_MUL;
wire decode_IS_MUL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1;
wire decode_IS_CSR;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
wire decode_SRC_LESS_UNSIGNED;
wire decode_MEMORY_MANAGMENT;
wire memory_MEMORY_WR;
wire decode_MEMORY_WR;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1;
wire decode_MEMORY_FORCE_CONSTISTENCY;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire [31:0] memory_PC;
reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire memory_CfuPlugin_CFU_IN_FLIGHT;
wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire execute_CfuPlugin_CFU_ENABLE;
wire execute_DO_EBREAK;
wire decode_IS_EBREAK;
wire execute_IS_RS1_SIGNED;
wire execute_IS_DIV;
wire execute_IS_RS2_SIGNED;
wire memory_IS_DIV;
wire writeBack_IS_MUL;
wire [33:0] writeBack_MUL_HH;
wire [51:0] writeBack_MUL_LOW;
wire [33:0] memory_MUL_HL;
wire [33:0] memory_MUL_LH;
wire [31:0] memory_MUL_LL;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire execute_IS_CSR;
wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL;
wire [31:0] execute_BRANCH_CALC;
wire execute_BRANCH_DO;
wire [31:0] execute_PC;
wire execute_PREDICTION_HAD_BRANCHED2;
(* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ;
wire execute_BRANCH_COND_RESULT;
wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL;
wire decode_RS2_USE;
wire decode_RS1_USE;
reg [31:0] _zz_decode_RS2;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire [31:0] memory_INSTRUCTION;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_RS2;
reg [31:0] decode_RS1;
wire [31:0] memory_SHIFT_RIGHT;
reg [31:0] _zz_decode_RS2_1;
wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC2_FORCE_ZERO;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_execute_SRC2;
wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL;
wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL;
wire decode_SRC_USE_SUB_LESS;
wire decode_SRC_ADD_ZERO;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL;
wire [31:0] execute_SRC2;
wire [31:0] execute_SRC1;
wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL;
wire [31:0] _zz_lastStageRegFileWrite_payload_address;
wire _zz_lastStageRegFileWrite_valid;
reg _zz_1;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire decode_LEGAL_INSTRUCTION;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1;
reg [31:0] _zz_decode_RS2_2;
wire writeBack_MEMORY_WR;
wire [31:0] writeBack_MEMORY_STORE_DATA_RF;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire writeBack_MEMORY_ENABLE;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire memory_MEMORY_ENABLE;
wire execute_MEMORY_FORCE_CONSTISTENCY;
wire execute_MEMORY_MANAGMENT;
(* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ;
wire execute_MEMORY_WR;
wire [31:0] execute_SRC_ADD;
wire execute_MEMORY_ENABLE;
wire [31:0] execute_INSTRUCTION;
wire decode_MEMORY_ENABLE;
wire decode_FLUSH_ALL;
reg IBusCachedPlugin_rsp_issueDetected_4;
reg IBusCachedPlugin_rsp_issueDetected_3;
reg IBusCachedPlugin_rsp_issueDetected_2;
reg IBusCachedPlugin_rsp_issueDetected_1;
wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1;
wire [31:0] decode_INSTRUCTION;
reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT;
wire [31:0] decode_PC;
wire [31:0] writeBack_PC;
wire [31:0] writeBack_INSTRUCTION;
reg decode_arbitration_haltItself;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushIt;
reg decode_arbitration_flushNext;
reg decode_arbitration_isValid;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
reg execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
reg execute_arbitration_flushIt;
reg execute_arbitration_flushNext;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
wire memory_arbitration_flushIt;
wire memory_arbitration_flushNext;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
reg writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
reg writeBack_arbitration_flushIt;
reg writeBack_arbitration_flushNext;
reg writeBack_arbitration_isValid;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring;
wire [31:0] lastStageInstruction /* verilator public */ ;
wire [31:0] lastStagePc /* verilator public */ ;
wire lastStageIsValid /* verilator public */ ;
wire lastStageIsFiring /* verilator public */ ;
reg IBusCachedPlugin_fetcherHalt;
reg IBusCachedPlugin_incomingInstruction;
wire IBusCachedPlugin_predictionJumpInterface_valid;
(* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ;
reg IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire IBusCachedPlugin_decodePrediction_rsp_wasWrong;
wire IBusCachedPlugin_pcValids_0;
wire IBusCachedPlugin_pcValids_1;
wire IBusCachedPlugin_pcValids_2;
wire IBusCachedPlugin_pcValids_3;
reg IBusCachedPlugin_decodeExceptionPort_valid;
reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
wire IBusCachedPlugin_mmuBus_cmd_0_isValid;
wire IBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire IBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire IBusCachedPlugin_mmuBus_rsp_isPaging;
wire IBusCachedPlugin_mmuBus_rsp_allowRead;
wire IBusCachedPlugin_mmuBus_rsp_allowWrite;
wire IBusCachedPlugin_mmuBus_rsp_allowExecute;
wire IBusCachedPlugin_mmuBus_rsp_exception;
wire IBusCachedPlugin_mmuBus_rsp_refilling;
wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire IBusCachedPlugin_mmuBus_end;
wire IBusCachedPlugin_mmuBus_busy;
wire dBus_cmd_valid;
wire dBus_cmd_ready;
wire dBus_cmd_payload_wr;
wire dBus_cmd_payload_uncached;
wire [31:0] dBus_cmd_payload_address;
wire [31:0] dBus_cmd_payload_data;
wire [3:0] dBus_cmd_payload_mask;
wire [2:0] dBus_cmd_payload_size;
wire dBus_cmd_payload_last;
wire dBus_rsp_valid;
wire dBus_rsp_payload_last;
wire [31:0] dBus_rsp_payload_data;
wire dBus_rsp_payload_error;
wire DBusCachedPlugin_mmuBus_cmd_0_isValid;
wire DBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire DBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire DBusCachedPlugin_mmuBus_rsp_isPaging;
wire DBusCachedPlugin_mmuBus_rsp_allowRead;
wire DBusCachedPlugin_mmuBus_rsp_allowWrite;
wire DBusCachedPlugin_mmuBus_rsp_allowExecute;
wire DBusCachedPlugin_mmuBus_rsp_exception;
wire DBusCachedPlugin_mmuBus_rsp_refilling;
wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire DBusCachedPlugin_mmuBus_end;
wire DBusCachedPlugin_mmuBus_busy;
reg DBusCachedPlugin_redoBranch_valid;
wire [31:0] DBusCachedPlugin_redoBranch_payload;
reg DBusCachedPlugin_exceptionBus_valid;
reg [3:0] DBusCachedPlugin_exceptionBus_payload_code;
wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr;
reg _zz_when_DBusCachedPlugin_l386;
wire decodeExceptionPort_valid;
wire [3:0] decodeExceptionPort_payload_code;
wire [31:0] decodeExceptionPort_payload_badAddr;
wire BranchPlugin_jumpInterface_valid;
wire [31:0] BranchPlugin_jumpInterface_payload;
reg BranchPlugin_branchExceptionPort_valid;
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
wire [31:0] CsrPlugin_csrMapping_readDataSignal;
wire [31:0] CsrPlugin_csrMapping_readDataInit;
wire [31:0] CsrPlugin_csrMapping_writeDataSignal;
wire CsrPlugin_csrMapping_allowCsrSignal;
wire CsrPlugin_csrMapping_hazardFree;
reg CsrPlugin_inWfi /* verilator public */ ;
reg CsrPlugin_thirdPartyWake;
reg CsrPlugin_jumpInterface_valid;
reg [31:0] CsrPlugin_jumpInterface_payload;
wire CsrPlugin_exceptionPendings_0;
wire CsrPlugin_exceptionPendings_1;
wire CsrPlugin_exceptionPendings_2;
wire CsrPlugin_exceptionPendings_3;
wire externalInterrupt;
wire contextSwitching;
reg [1:0] CsrPlugin_privilege;
reg CsrPlugin_forceMachineWire;
reg CsrPlugin_selfException_valid;
reg [3:0] CsrPlugin_selfException_payload_code;
wire [31:0] CsrPlugin_selfException_payload_badAddr;
reg CsrPlugin_allowInterrupts;
reg CsrPlugin_allowException;
reg CsrPlugin_allowEbreakException;
reg IBusCachedPlugin_injectionPort_valid;
reg IBusCachedPlugin_injectionPort_ready;
wire [31:0] IBusCachedPlugin_injectionPort_payload;
wire IBusCachedPlugin_externalFlush;
wire IBusCachedPlugin_jump_pcLoad_valid;
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4;
wire IBusCachedPlugin_fetchPc_output_valid;
wire IBusCachedPlugin_fetchPc_output_ready;
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusCachedPlugin_fetchPc_correction;
reg IBusCachedPlugin_fetchPc_correctionReg;
wire IBusCachedPlugin_fetchPc_output_fire;
wire IBusCachedPlugin_fetchPc_corrected;
reg IBusCachedPlugin_fetchPc_pcRegPropagate;
reg IBusCachedPlugin_fetchPc_booted;
reg IBusCachedPlugin_fetchPc_inc;
wire when_Fetcher_l131;
wire IBusCachedPlugin_fetchPc_output_fire_1;
wire when_Fetcher_l131_1;
reg [31:0] IBusCachedPlugin_fetchPc_pc;
wire IBusCachedPlugin_fetchPc_redo_valid;
wire [31:0] IBusCachedPlugin_fetchPc_redo_payload;
reg IBusCachedPlugin_fetchPc_flushed;
wire when_Fetcher_l158;
reg IBusCachedPlugin_iBusRsp_redoFetch;
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
wire IBusCachedPlugin_iBusRsp_stages_1_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_1_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_1_halt;
wire IBusCachedPlugin_iBusRsp_stages_2_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_2_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_2_halt;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire IBusCachedPlugin_iBusRsp_flush;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg IBusCachedPlugin_iBusRsp_readyForError;
wire IBusCachedPlugin_iBusRsp_output_valid;
wire IBusCachedPlugin_iBusRsp_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc;
wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
wire IBusCachedPlugin_iBusRsp_output_payload_isRvc;
wire when_Fetcher_l240;
wire when_Fetcher_l320;
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
wire when_Fetcher_l329;
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
wire when_Fetcher_l329_1;
reg IBusCachedPlugin_injector_nextPcCalc_valids_2;
wire when_Fetcher_l329_2;
reg IBusCachedPlugin_injector_nextPcCalc_valids_3;
wire when_Fetcher_l329_3;
reg IBusCachedPlugin_injector_nextPcCalc_valids_4;
wire when_Fetcher_l329_4;
wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1;
wire _zz_2;
reg [10:0] _zz_3;
wire _zz_4;
reg [18:0] _zz_5;
reg _zz_6;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload;
reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3;
wire iBus_cmd_valid;
wire iBus_cmd_ready;
reg [31:0] iBus_cmd_payload_address;
wire [2:0] iBus_cmd_payload_size;
wire iBus_rsp_valid;
wire [31:0] iBus_rsp_payload_data;
wire iBus_rsp_payload_error;
wire [31:0] _zz_IBusCachedPlugin_rspCounter;
reg [31:0] IBusCachedPlugin_rspCounter;
wire IBusCachedPlugin_s0_tightlyCoupledHit;
reg IBusCachedPlugin_s1_tightlyCoupledHit;
reg IBusCachedPlugin_s2_tightlyCoupledHit;
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
wire IBusCachedPlugin_rsp_issueDetected;
reg IBusCachedPlugin_rsp_redoFetch;
wire when_IBusCachedPlugin_l239;
wire when_IBusCachedPlugin_l244;
wire when_IBusCachedPlugin_l250;
wire when_IBusCachedPlugin_l256;
wire when_IBusCachedPlugin_l267;
wire dataCache_1_io_mem_cmd_s2mPipe_valid;
reg dataCache_1_io_mem_cmd_s2mPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_last;
reg dataCache_1_io_mem_cmd_rValid;
reg dataCache_1_io_mem_cmd_rData_wr;
reg dataCache_1_io_mem_cmd_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_rData_size;
reg dataCache_1_io_mem_cmd_rData_last;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
reg dataCache_1_io_mem_cmd_s2mPipe_rValid;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_last;
wire when_Stream_l342;
wire [31:0] _zz_DBusCachedPlugin_rspCounter;
reg [31:0] DBusCachedPlugin_rspCounter;
wire when_DBusCachedPlugin_l303;
wire [1:0] execute_DBusCachedPlugin_size;
reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF;
wire dataCache_1_io_cpu_flush_isStall;
wire when_DBusCachedPlugin_l343;
wire when_DBusCachedPlugin_l359;
wire when_DBusCachedPlugin_l386;
wire when_DBusCachedPlugin_l438;
wire when_DBusCachedPlugin_l458;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3;
reg [31:0] writeBack_DBusCachedPlugin_rspShifted;
wire [31:0] writeBack_DBusCachedPlugin_rspRf;
wire [1:0] switch_Misc_l200;
wire _zz_writeBack_DBusCachedPlugin_rspFormated;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1;
wire _zz_writeBack_DBusCachedPlugin_rspFormated_2;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3;
reg [31:0] writeBack_DBusCachedPlugin_rspFormated;
wire when_DBusCachedPlugin_l484;
wire [34:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
wire when_RegFilePlugin_l63;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg lastStageRegFileWrite_valid /* verilator public */ ;
reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
reg _zz_7;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_execute_REGFILE_WRITE_DATA;
reg [31:0] _zz_execute_SRC1;
wire _zz_execute_SRC2_1;
reg [19:0] _zz_execute_SRC2_2;
wire _zz_execute_SRC2_3;
reg [19:0] _zz_execute_SRC2_4;
reg [31:0] _zz_execute_SRC2_5;
reg [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
wire [4:0] execute_FullBarrelShifterPlugin_amplitude;
reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed;
wire [31:0] execute_FullBarrelShifterPlugin_reversed;
reg [31:0] _zz_decode_RS2_3;
reg HazardSimplePlugin_src0Hazard;
reg HazardSimplePlugin_src1Hazard;
wire HazardSimplePlugin_writeBackWrites_valid;
wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address;
wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data;
reg HazardSimplePlugin_writeBackBuffer_valid;
reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address;
reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data;
wire HazardSimplePlugin_addr0Match;
wire HazardSimplePlugin_addr1Match;
wire when_HazardSimplePlugin_l47;
wire when_HazardSimplePlugin_l48;
wire when_HazardSimplePlugin_l51;
wire when_HazardSimplePlugin_l45;
wire when_HazardSimplePlugin_l57;
wire when_HazardSimplePlugin_l58;
wire when_HazardSimplePlugin_l48_1;
wire when_HazardSimplePlugin_l51_1;
wire when_HazardSimplePlugin_l45_1;
wire when_HazardSimplePlugin_l57_1;
wire when_HazardSimplePlugin_l58_1;
wire when_HazardSimplePlugin_l48_2;
wire when_HazardSimplePlugin_l51_2;
wire when_HazardSimplePlugin_l45_2;
wire when_HazardSimplePlugin_l57_2;
wire when_HazardSimplePlugin_l58_2;
wire when_HazardSimplePlugin_l105;
wire when_HazardSimplePlugin_l108;
wire when_HazardSimplePlugin_l113;
wire execute_BranchPlugin_eq;
wire [2:0] switch_Misc_l200_1;
reg _zz_execute_BRANCH_COND_RESULT;
reg _zz_execute_BRANCH_COND_RESULT_1;
wire _zz_execute_BranchPlugin_missAlignedTarget;
reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1;
wire _zz_execute_BranchPlugin_missAlignedTarget_2;
reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3;
wire _zz_execute_BranchPlugin_missAlignedTarget_4;
reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5;
reg _zz_execute_BranchPlugin_missAlignedTarget_6;
wire execute_BranchPlugin_missAlignedTarget;
reg [31:0] execute_BranchPlugin_branch_src1;
reg [31:0] execute_BranchPlugin_branch_src2;
wire _zz_execute_BranchPlugin_branch_src2;
reg [19:0] _zz_execute_BranchPlugin_branch_src2_1;
wire _zz_execute_BranchPlugin_branch_src2_2;
reg [10:0] _zz_execute_BranchPlugin_branch_src2_3;
wire _zz_execute_BranchPlugin_branch_src2_4;
reg [18:0] _zz_execute_BranchPlugin_branch_src2_5;
wire [31:0] execute_BranchPlugin_branchAdder;
wire when_BranchPlugin_l296;
reg [1:0] CsrPlugin_misa_base;
reg [25:0] CsrPlugin_misa_extensions;
reg [1:0] CsrPlugin_mtvec_mode;
reg [29:0] CsrPlugin_mtvec_base;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg [31:0] CsrPlugin_mscratch;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mtval;
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire _zz_when_CsrPlugin_l952;
wire _zz_when_CsrPlugin_l952_1;
wire _zz_when_CsrPlugin_l952_2;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire when_CsrPlugin_l909;
wire when_CsrPlugin_l909_1;
wire when_CsrPlugin_l909_2;
wire when_CsrPlugin_l909_3;
wire when_CsrPlugin_l922;
reg CsrPlugin_interrupt_valid;
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
wire when_CsrPlugin_l946;
wire when_CsrPlugin_l952;
wire when_CsrPlugin_l952_1;
wire when_CsrPlugin_l952_2;
wire CsrPlugin_exception;
reg CsrPlugin_lastStageWasWfi;
reg CsrPlugin_pipelineLiberator_pcValids_0;
reg CsrPlugin_pipelineLiberator_pcValids_1;
reg CsrPlugin_pipelineLiberator_pcValids_2;
wire CsrPlugin_pipelineLiberator_active;
wire when_CsrPlugin_l980;
wire when_CsrPlugin_l980_1;
wire when_CsrPlugin_l980_2;
wire when_CsrPlugin_l985;
reg CsrPlugin_pipelineLiberator_done;
wire when_CsrPlugin_l991;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_hadException /* verilator public */ ;
reg [1:0] CsrPlugin_targetPrivilege;
reg [3:0] CsrPlugin_trapCause;
reg [1:0] CsrPlugin_xtvec_mode;
reg [29:0] CsrPlugin_xtvec_base;
wire when_CsrPlugin_l1019;
wire when_CsrPlugin_l1064;
wire [1:0] switch_CsrPlugin_l1068;
reg execute_CsrPlugin_wfiWake;
wire when_CsrPlugin_l1108;
wire when_CsrPlugin_l1110;
wire when_CsrPlugin_l1116;
wire execute_CsrPlugin_blockedBySideEffects;
reg execute_CsrPlugin_illegalAccess;
reg execute_CsrPlugin_illegalInstruction;
wire when_CsrPlugin_l1129;
wire when_CsrPlugin_l1136;
wire when_CsrPlugin_l1137;
wire when_CsrPlugin_l1144;
reg execute_CsrPlugin_writeInstruction;
reg execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [31:0] execute_CsrPlugin_readToWriteData;
wire switch_Misc_l200_2;
reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal;
wire when_CsrPlugin_l1176;
wire when_CsrPlugin_l1180;
wire [11:0] execute_CsrPlugin_csrAddress;
reg execute_MulPlugin_aSigned;
reg execute_MulPlugin_bSigned;
wire [31:0] execute_MulPlugin_a;
wire [31:0] execute_MulPlugin_b;
wire [1:0] switch_MulPlugin_l87;
wire [15:0] execute_MulPlugin_aULow;
wire [15:0] execute_MulPlugin_bULow;
wire [16:0] execute_MulPlugin_aSLow;
wire [16:0] execute_MulPlugin_bSLow;
wire [16:0] execute_MulPlugin_aHigh;
wire [16:0] execute_MulPlugin_bHigh;
wire [65:0] writeBack_MulPlugin_result;
wire when_MulPlugin_l147;
wire [1:0] switch_MulPlugin_l148;
reg [32:0] memory_DivPlugin_rs1;
reg [31:0] memory_DivPlugin_rs2;
reg [64:0] memory_DivPlugin_accumulator;
wire memory_DivPlugin_frontendOk;
reg memory_DivPlugin_div_needRevert;
reg memory_DivPlugin_div_counter_willIncrement;
reg memory_DivPlugin_div_counter_willClear;
reg [5:0] memory_DivPlugin_div_counter_valueNext;
reg [5:0] memory_DivPlugin_div_counter_value;
wire memory_DivPlugin_div_counter_willOverflowIfInc;
wire memory_DivPlugin_div_counter_willOverflow;
reg memory_DivPlugin_div_done;
wire when_MulDivIterativePlugin_l126;
wire when_MulDivIterativePlugin_l126_1;
reg [31:0] memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l128;
wire when_MulDivIterativePlugin_l129;
wire when_MulDivIterativePlugin_l132;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] memory_DivPlugin_div_stage_0_outNumerator;
wire when_MulDivIterativePlugin_l151;
wire [31:0] _zz_memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l162;
wire _zz_memory_DivPlugin_rs2;
wire _zz_memory_DivPlugin_rs1;
reg [32:0] _zz_memory_DivPlugin_rs1_1;
reg [31:0] externalInterruptArray_regNext;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1;
reg DebugPlugin_firstCycle;
reg DebugPlugin_secondCycle;
reg DebugPlugin_resetIt;
reg DebugPlugin_haltIt;
reg DebugPlugin_stepIt;
reg DebugPlugin_isPipBusy;
reg DebugPlugin_godmode;
wire when_DebugPlugin_l225;
reg DebugPlugin_haltedByBreak;
reg DebugPlugin_debugUsed /* verilator public */ ;
reg DebugPlugin_disableEbreak;
wire DebugPlugin_allowEBreak;
reg [31:0] DebugPlugin_busReadDataReg;
reg _zz_when_DebugPlugin_l244;
wire when_DebugPlugin_l244;
wire [5:0] switch_DebugPlugin_l256;
wire when_DebugPlugin_l260;
wire when_DebugPlugin_l260_1;
wire when_DebugPlugin_l261;
wire when_DebugPlugin_l261_1;
wire when_DebugPlugin_l262;
wire when_DebugPlugin_l263;
wire when_DebugPlugin_l264;
wire when_DebugPlugin_l264_1;
wire when_DebugPlugin_l284;
wire when_DebugPlugin_l287;
wire when_DebugPlugin_l300;
reg DebugPlugin_resetIt_regNext;
wire when_DebugPlugin_l316;
wire execute_CfuPlugin_schedule;
reg execute_CfuPlugin_hold;
reg execute_CfuPlugin_fired;
wire CfuPlugin_bus_cmd_fire;
wire when_CfuPlugin_l171;
wire when_CfuPlugin_l175;
wire [9:0] execute_CfuPlugin_functionsIds_0;
wire _zz_CfuPlugin_bus_cmd_payload_inputs_1;
reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1;
reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
wire CfuPlugin_bus_rsp_rsp_valid;
reg CfuPlugin_bus_rsp_rsp_ready;
wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0;
reg CfuPlugin_bus_rsp_rValid;
reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0;
wire when_CfuPlugin_l208;
wire when_Pipeline_l124;
reg [31:0] decode_to_execute_PC;
wire when_Pipeline_l124_1;
reg [31:0] execute_to_memory_PC;
wire when_Pipeline_l124_2;
reg [31:0] memory_to_writeBack_PC;
wire when_Pipeline_l124_3;
reg [31:0] decode_to_execute_INSTRUCTION;
wire when_Pipeline_l124_4;
reg [31:0] execute_to_memory_INSTRUCTION;
wire when_Pipeline_l124_5;
reg [31:0] memory_to_writeBack_INSTRUCTION;
wire when_Pipeline_l124_6;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
wire when_Pipeline_l124_7;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
wire when_Pipeline_l124_8;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
wire when_Pipeline_l124_9;
reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
wire when_Pipeline_l124_10;
reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL;
wire when_Pipeline_l124_11;
reg decode_to_execute_SRC_USE_SUB_LESS;
wire when_Pipeline_l124_12;
reg decode_to_execute_MEMORY_ENABLE;
wire when_Pipeline_l124_13;
reg execute_to_memory_MEMORY_ENABLE;
wire when_Pipeline_l124_14;
reg memory_to_writeBack_MEMORY_ENABLE;
wire when_Pipeline_l124_15;
reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL;
wire when_Pipeline_l124_16;
reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL;
wire when_Pipeline_l124_17;
reg decode_to_execute_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_18;
reg execute_to_memory_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_19;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_20;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
wire when_Pipeline_l124_21;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_22;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_23;
reg decode_to_execute_MEMORY_WR;
wire when_Pipeline_l124_24;
reg execute_to_memory_MEMORY_WR;
wire when_Pipeline_l124_25;
reg memory_to_writeBack_MEMORY_WR;
wire when_Pipeline_l124_26;
reg decode_to_execute_MEMORY_MANAGMENT;
wire when_Pipeline_l124_27;
reg decode_to_execute_SRC_LESS_UNSIGNED;
wire when_Pipeline_l124_28;
reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL;
wire when_Pipeline_l124_29;
reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL;
wire when_Pipeline_l124_30;
reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL;
wire when_Pipeline_l124_31;
reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL;
wire when_Pipeline_l124_32;
reg decode_to_execute_IS_CSR;
wire when_Pipeline_l124_33;
reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL;
wire when_Pipeline_l124_34;
reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL;
wire when_Pipeline_l124_35;
reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL;
wire when_Pipeline_l124_36;
reg decode_to_execute_IS_MUL;
wire when_Pipeline_l124_37;
reg execute_to_memory_IS_MUL;
wire when_Pipeline_l124_38;
reg memory_to_writeBack_IS_MUL;
wire when_Pipeline_l124_39;
reg decode_to_execute_IS_DIV;
wire when_Pipeline_l124_40;
reg execute_to_memory_IS_DIV;
wire when_Pipeline_l124_41;
reg decode_to_execute_IS_RS1_SIGNED;
wire when_Pipeline_l124_42;
reg decode_to_execute_IS_RS2_SIGNED;
wire when_Pipeline_l124_43;
reg decode_to_execute_CfuPlugin_CFU_ENABLE;
wire when_Pipeline_l124_44;
reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire when_Pipeline_l124_45;
reg [31:0] decode_to_execute_RS1;
wire when_Pipeline_l124_46;
reg [31:0] decode_to_execute_RS2;
wire when_Pipeline_l124_47;
reg decode_to_execute_SRC2_FORCE_ZERO;
wire when_Pipeline_l124_48;
reg decode_to_execute_PREDICTION_HAD_BRANCHED2;
wire when_Pipeline_l124_49;
reg decode_to_execute_CSR_WRITE_OPCODE;
wire when_Pipeline_l124_50;
reg decode_to_execute_CSR_READ_OPCODE;
wire when_Pipeline_l124_51;
reg decode_to_execute_DO_EBREAK;
wire when_Pipeline_l124_52;
reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_53;
reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_54;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_55;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_56;
reg [31:0] execute_to_memory_SHIFT_RIGHT;
wire when_Pipeline_l124_57;
reg [31:0] execute_to_memory_MUL_LL;
wire when_Pipeline_l124_58;
reg [33:0] execute_to_memory_MUL_LH;
wire when_Pipeline_l124_59;
reg [33:0] execute_to_memory_MUL_HL;
wire when_Pipeline_l124_60;
reg [33:0] execute_to_memory_MUL_HH;
wire when_Pipeline_l124_61;
reg [33:0] memory_to_writeBack_MUL_HH;
wire when_Pipeline_l124_62;
reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_63;
reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_64;
reg [51:0] memory_to_writeBack_MUL_LOW;
wire when_Pipeline_l151;
wire when_Pipeline_l154;
wire when_Pipeline_l151_1;
wire when_Pipeline_l154_1;
wire when_Pipeline_l151_2;
wire when_Pipeline_l154_2;
reg [2:0] switch_Fetcher_l362;
wire when_Fetcher_l378;
wire when_CsrPlugin_l1264;
reg execute_CsrPlugin_csr_3264;
wire when_CsrPlugin_l1264_1;
reg execute_CsrPlugin_csr_3857;
wire when_CsrPlugin_l1264_2;
reg execute_CsrPlugin_csr_3858;
wire when_CsrPlugin_l1264_3;
reg execute_CsrPlugin_csr_3859;
wire when_CsrPlugin_l1264_4;
reg execute_CsrPlugin_csr_3860;
wire when_CsrPlugin_l1264_5;
reg execute_CsrPlugin_csr_769;
wire when_CsrPlugin_l1264_6;
reg execute_CsrPlugin_csr_768;
wire when_CsrPlugin_l1264_7;
reg execute_CsrPlugin_csr_836;
wire when_CsrPlugin_l1264_8;
reg execute_CsrPlugin_csr_772;
wire when_CsrPlugin_l1264_9;
reg execute_CsrPlugin_csr_773;
wire when_CsrPlugin_l1264_10;
reg execute_CsrPlugin_csr_833;
wire when_CsrPlugin_l1264_11;
reg execute_CsrPlugin_csr_832;
wire when_CsrPlugin_l1264_12;
reg execute_CsrPlugin_csr_834;
wire when_CsrPlugin_l1264_13;
reg execute_CsrPlugin_csr_835;
wire when_CsrPlugin_l1264_14;
reg execute_CsrPlugin_csr_2816;
wire when_CsrPlugin_l1264_15;
reg execute_CsrPlugin_csr_2944;
wire when_CsrPlugin_l1264_16;
reg execute_CsrPlugin_csr_2818;
wire when_CsrPlugin_l1264_17;
reg execute_CsrPlugin_csr_2946;
wire when_CsrPlugin_l1264_18;
reg execute_CsrPlugin_csr_3072;
wire when_CsrPlugin_l1264_19;
reg execute_CsrPlugin_csr_3200;
wire when_CsrPlugin_l1264_20;
reg execute_CsrPlugin_csr_3074;
wire when_CsrPlugin_l1264_21;
reg execute_CsrPlugin_csr_3202;
wire when_CsrPlugin_l1264_22;
reg execute_CsrPlugin_csr_3008;
wire when_CsrPlugin_l1264_23;
reg execute_CsrPlugin_csr_4032;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24;
wire when_CsrPlugin_l1297;
wire when_CsrPlugin_l1302;
reg [2:0] _zz_iBusWishbone_ADR;
wire when_InstructionCache_l239;
reg _zz_iBus_rsp_valid;
reg [31:0] iBusWishbone_DAT_MISO_regNext;
reg [2:0] _zz_dBus_cmd_ready;
wire _zz_dBus_cmd_ready_1;
wire _zz_dBus_cmd_ready_2;
wire _zz_dBus_cmd_ready_3;
wire _zz_dBus_cmd_ready_4;
wire _zz_dBus_cmd_ready_5;
reg _zz_dBus_rsp_valid;
reg [31:0] dBusWishbone_DAT_MISO_regNext;
`ifndef SYNTHESIS
reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string;
reg [39:0] decode_ENV_CTRL_string;
reg [39:0] _zz_decode_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string;
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string;
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_decode_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string;
reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] memory_ENV_CTRL_string;
reg [39:0] _zz_memory_ENV_CTRL_string;
reg [39:0] execute_ENV_CTRL_string;
reg [39:0] _zz_execute_ENV_CTRL_string;
reg [39:0] writeBack_ENV_CTRL_string;
reg [39:0] _zz_writeBack_ENV_CTRL_string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_execute_BRANCH_CTRL_string;
reg [71:0] memory_SHIFT_CTRL_string;
reg [71:0] _zz_memory_SHIFT_CTRL_string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_execute_SHIFT_CTRL_string;
reg [23:0] execute_SRC2_CTRL_string;
reg [23:0] _zz_execute_SRC2_CTRL_string;
reg [95:0] execute_SRC1_CTRL_string;
reg [95:0] _zz_execute_SRC1_CTRL_string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_execute_ALU_CTRL_string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_decode_ENV_CTRL_1_string;
reg [31:0] _zz_decode_BRANCH_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_1_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string;
reg [23:0] _zz_decode_SRC2_CTRL_1_string;
reg [63:0] _zz_decode_ALU_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_1_string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_decode_BRANCH_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_2_string;
reg [63:0] _zz_decode_ALU_CTRL_2_string;
reg [23:0] _zz_decode_SRC2_CTRL_2_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string;
reg [71:0] _zz_decode_SHIFT_CTRL_2_string;
reg [31:0] _zz_decode_BRANCH_CTRL_2_string;
reg [39:0] _zz_decode_ENV_CTRL_2_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string;
reg [95:0] decode_to_execute_SRC1_CTRL_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
reg [23:0] decode_to_execute_SRC2_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [71:0] execute_to_memory_SHIFT_CTRL_string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
reg [39:0] decode_to_execute_ENV_CTRL_string;
reg [39:0] execute_to_memory_ENV_CTRL_string;
reg [39:0] memory_to_writeBack_ENV_CTRL_string;
reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
`endif
(* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00);
assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00);
assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5));
assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3));
assign _zz_memory_MUL_LOW_2 = 52'h0;
assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL};
assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4};
assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16);
assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6};
assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16);
assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8};
assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude);
assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0];
assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001);
assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00};
assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1};
assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101);
assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100);
assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS;
assign _zz__zz_execute_SRC1 = 3'b100;
assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15];
assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4));
assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3));
assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1;
assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6);
assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001;
assign _zz_execute_SrcPlugin_addSub_6 = 32'h0;
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100;
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01);
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01);
assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW};
assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32);
assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0];
assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32];
assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement;
assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1};
assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2};
assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])};
assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2;
assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3;
assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4);
assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert;
assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5};
assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1;
assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3};
assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2;
assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2};
assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]};
assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5);
assign _zz_decode_RegFilePlugin_rs1Data = 1'b1;
assign _zz_decode_RegFilePlugin_rs2Data = 1'b1;
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3};
assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0];
assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1];
assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f;
assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f);
assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073;
assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073);
assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063);
assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f;
assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f);
assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003;
assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063);
assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f);
assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f;
assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f);
assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013;
assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033);
assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033);
assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}};
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7];
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = (decode_INSTRUCTION & 32'h10103050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 32'h00100050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = (((decode_INSTRUCTION & 32'h02004064) == 32'h02004020) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) == 32'h02000030) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9} != 2'b00),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21}}}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h02004074;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00001050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00001050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = (decode_INSTRUCTION & 32'h00002050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = 32'h00002050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h00007034);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = (decode_INSTRUCTION & 32'h02007064);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = 32'h00005020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h00007034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = 32'h02007054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = 32'h00001000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = (decode_INSTRUCTION & 32'h00003000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = 32'h00002000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50) == 32'h00004004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = 32'h00005000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = 32'h00004054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59) == 32'h00002040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81}} != 6'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = 32'h00000064;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = 32'h00002040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = (decode_INSTRUCTION & 32'h00001040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00001040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77) == 32'h00000008);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = 6'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = 32'h00100040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (decode_INSTRUCTION & 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = (decode_INSTRUCTION & 32'h00000038);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = 32'h00000008;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = (decode_INSTRUCTION & 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = (decode_INSTRUCTION & 32'h00004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = 32'h00004020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = 32'h00002030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = (decode_INSTRUCTION & 32'h00001030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00002020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = (decode_INSTRUCTION & 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = 32'h00001010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (decode_INSTRUCTION & 32'h00000070);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131) == 32'h00004010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141} != 4'b0000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h00000030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = 32'h02000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02002060;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = 32'h02003020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = (decode_INSTRUCTION & 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = 32'h00004014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = (decode_INSTRUCTION & 32'h00006014);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = 32'h00000044;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = (decode_INSTRUCTION & 32'h00000018);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = 32'h00000058;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156) == 32'h40000030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167) == 32'h00001004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h00002014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = 32'h40000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = 32'h00000014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = (decode_INSTRUCTION & 32'h00000044);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = 32'h00000004;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167 = 32'h00005054;
assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7];
assign _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0;
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs1Data) begin
_zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs2Data) begin
_zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
always @(posedge clk) begin
if(_zz_1) begin
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
end
InstructionCache IBusCachedPlugin_cache (
.io_flush (IBusCachedPlugin_cache_io_flush ), //i
.io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i
.io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o
.io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i
.io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i
.io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i
.io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i
.io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i
.io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o
.io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i
.io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o
.io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i
.io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i
.io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i
.io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o
.io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o
.io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o
.io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o
.io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o
.io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o
.io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i
.io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i
.io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i
.io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (iBus_cmd_ready ), //i
.io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o
.io_mem_rsp_valid (iBus_rsp_valid ), //i
.io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i
._zz_when_Fetcher_l398 (switch_Fetcher_l362 ), //i
._zz_io_cpu_fetch_data_regNextWhen (IBusCachedPlugin_injectionPort_payload ), //i
.clk (clk ), //i
.reset (reset ) //i
);
DataCache dataCache_1 (
.io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i
.io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i
.io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o
.io_cpu_execute_args_wr (execute_MEMORY_WR ), //i
.io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i
.io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i
.io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o
.io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i
.io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i
.io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o
.io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i
.io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i
.io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i
.io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i
.io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i
.io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o
.io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o
.io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i
.io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o
.io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i
.io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o
.io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o
.io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o
.io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o
.io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i
.io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i
.io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i
.io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i
.io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i
.io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i
.io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i
.io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i
.io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i
.io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o
.io_cpu_redo (dataCache_1_io_cpu_redo ), //o
.io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i
.io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o
.io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i
.io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o
.io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o
.io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o
.io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o
.io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o
.io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o
.io_mem_rsp_valid (dBus_rsp_valid ), //i
.io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i
.io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
always @(*) begin
case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6)
2'b00 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload;
end
2'b01 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload;
end
2'b10 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload;
end
default : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_1)
2'b00 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0;
end
2'b01 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1;
end
2'b10 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_3)
1'b0 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
`ifndef SYNTHESIS
always @(*) begin
case(decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL";
default : decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL";
default : _zz_decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC ";
default : _zz_decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL";
default : memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL";
default : _zz_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL";
default : execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL";
default : _zz_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL";
default : writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR";
default : _zz_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 ";
default : memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC ";
default : execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC ";
default : _zz_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 ";
default : execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR";
default : _zz_decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_2)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_2_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_2)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_2_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_2)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC ";
default : _zz_decode_SRC2_CTRL_2_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_2)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_2)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_2_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_2)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR";
default : _zz_decode_BRANCH_CTRL_2_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_2)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL";
default : _zz_decode_ENV_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
default : decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL";
default : decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL";
default : execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
`endif
assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7));
assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired);
assign memory_MUL_HH = execute_to_memory_MUL_HH;
assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow));
assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow);
assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT;
assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA;
assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF;
assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF;
assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak);
assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20);
assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0))));
assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch;
assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33];
assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31];
assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30];
assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29];
assign memory_IS_MUL = execute_to_memory_IS_MUL;
assign execute_IS_MUL = decode_to_execute_IS_MUL;
assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28];
assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1;
assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1;
assign decode_ENV_CTRL = _zz_decode_ENV_CTRL;
assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1;
assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25];
assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1;
assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1;
assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1;
assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17];
assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16];
assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR;
assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13];
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12];
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11];
assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1;
assign decode_ALU_CTRL = _zz_decode_ALU_CTRL;
assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1;
assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL;
assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1;
assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0;
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004);
assign memory_PC = execute_to_memory_PC;
always @(*) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT;
if(memory_arbitration_isStuck) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
always @(*) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT;
if(execute_arbitration_isStuck) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE;
assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK;
assign decode_IS_EBREAK = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32];
assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
assign execute_IS_DIV = decode_to_execute_IS_DIV;
assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
assign memory_IS_DIV = execute_to_memory_IS_DIV;
assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL;
assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH;
assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW;
assign memory_MUL_HL = execute_to_memory_MUL_HL;
assign memory_MUL_LH = execute_to_memory_MUL_LH;
assign memory_MUL_LL = execute_to_memory_MUL_LL;
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign memory_ENV_CTRL = _zz_memory_ENV_CTRL;
assign execute_ENV_CTRL = _zz_execute_ENV_CTRL;
assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL;
assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0};
assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
assign execute_PC = decode_to_execute_PC;
assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1;
assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL;
assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15];
assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5];
always @(*) begin
_zz_decode_RS2 = execute_REGFILE_WRITE_DATA;
if(when_CsrPlugin_l1176) begin
_zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal;
end
end
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
always @(*) begin
decode_RS2 = decode_RegFilePlugin_rs2Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr1Match) begin
decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l51) begin
decode_RS2 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l51_1) begin
decode_RS2 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l51_2) begin
decode_RS2 = _zz_decode_RS2;
end
end
end
end
always @(*) begin
decode_RS1 = decode_RegFilePlugin_rs1Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr0Match) begin
decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l48) begin
decode_RS1 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l48_1) begin
decode_RS1 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l48_2) begin
decode_RS1 = _zz_decode_RS2;
end
end
end
end
assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT;
always @(*) begin
_zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA;
if(memory_arbitration_isValid) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_SLL_1 : begin
_zz_decode_RS2_1 = _zz_decode_RS2_3;
end
`ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin
_zz_decode_RS2_1 = memory_SHIFT_RIGHT;
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l128) begin
_zz_decode_RS2_1 = memory_DivPlugin_div_result;
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
_zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0;
end
end
assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL;
assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_execute_SRC2 = execute_PC;
assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL;
assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL;
assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3];
assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20];
assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub;
assign execute_SRC_LESS = execute_SrcPlugin_less;
assign execute_ALU_CTRL = _zz_execute_ALU_CTRL;
assign execute_SRC2 = _zz_execute_SRC2_5;
assign execute_SRC1 = _zz_execute_SRC1;
assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL;
assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION;
assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID;
always @(*) begin
_zz_1 = 1'b0;
if(lastStageRegFileWrite_valid) begin
_zz_1 = 1'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data);
always @(*) begin
decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10];
if(when_RegFilePlugin_l63) begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
end
assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0);
always @(*) begin
_zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA;
if(when_DBusCachedPlugin_l484) begin
_zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated;
end
if(when_MulPlugin_l147) begin
case(switch_MulPlugin_l148)
2'b00 : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2;
end
default : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1;
end
endcase
end
end
assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR;
assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR;
assign execute_SRC_ADD = execute_SrcPlugin_addSub;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4];
assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0];
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3;
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_rsp_issueDetected_4 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2;
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_issueDetected_3 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_rsp_issueDetected_2 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_issueDetected_1 = 1'b1;
end
end
assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1;
assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
always @(*) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT;
if(BranchPlugin_jumpInterface_valid) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload;
end
end
always @(*) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload;
end
end
assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
always @(*) begin
decode_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l303) begin
decode_arbitration_haltItself = 1'b1;
end
case(switch_Fetcher_l362)
3'b010 : begin
decode_arbitration_haltItself = 1'b1;
end
default : begin
end
endcase
end
always @(*) begin
decode_arbitration_haltByOther = 1'b0;
if(when_HazardSimplePlugin_l113) begin
decode_arbitration_haltByOther = 1'b1;
end
if(CsrPlugin_pipelineLiberator_active) begin
decode_arbitration_haltByOther = 1'b1;
end
if(when_CsrPlugin_l1116) begin
decode_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
decode_arbitration_removeIt = 1'b0;
if(_zz_when) begin
decode_arbitration_removeIt = 1'b1;
end
if(decode_arbitration_isFlushed) begin
decode_arbitration_removeIt = 1'b1;
end
end
assign decode_arbitration_flushIt = 1'b0;
always @(*) begin
decode_arbitration_flushNext = 1'b0;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
decode_arbitration_flushNext = 1'b1;
end
if(_zz_when) begin
decode_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l343) begin
execute_arbitration_haltItself = 1'b1;
end
if(when_CsrPlugin_l1108) begin
if(when_CsrPlugin_l1110) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CsrPlugin_l1180) begin
if(execute_CsrPlugin_blockedBySideEffects) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CfuPlugin_l175) begin
execute_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltByOther = 1'b0;
if(when_DBusCachedPlugin_l359) begin
execute_arbitration_haltByOther = 1'b1;
end
if(when_DebugPlugin_l284) begin
execute_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
execute_arbitration_removeIt = 1'b0;
if(_zz_when_1) begin
execute_arbitration_removeIt = 1'b1;
end
if(execute_arbitration_isFlushed) begin
execute_arbitration_removeIt = 1'b1;
end
end
always @(*) begin
execute_arbitration_flushIt = 1'b0;
if(when_DebugPlugin_l284) begin
if(when_DebugPlugin_l287) begin
execute_arbitration_flushIt = 1'b1;
end
end
end
always @(*) begin
execute_arbitration_flushNext = 1'b0;
if(BranchPlugin_jumpInterface_valid) begin
execute_arbitration_flushNext = 1'b1;
end
if(_zz_when_1) begin
execute_arbitration_flushNext = 1'b1;
end
if(when_DebugPlugin_l284) begin
if(when_DebugPlugin_l287) begin
execute_arbitration_flushNext = 1'b1;
end
end
end
always @(*) begin
memory_arbitration_haltItself = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l129) begin
memory_arbitration_haltItself = 1'b1;
end
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
if(when_CfuPlugin_l208) begin
memory_arbitration_haltItself = 1'b1;
end
end
end
assign memory_arbitration_haltByOther = 1'b0;
always @(*) begin
memory_arbitration_removeIt = 1'b0;
if(memory_arbitration_isFlushed) begin
memory_arbitration_removeIt = 1'b1;
end
end
assign memory_arbitration_flushIt = 1'b0;
assign memory_arbitration_flushNext = 1'b0;
always @(*) begin
writeBack_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l458) begin
writeBack_arbitration_haltItself = 1'b1;
end
end
assign writeBack_arbitration_haltByOther = 1'b0;
always @(*) begin
writeBack_arbitration_removeIt = 1'b0;
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_removeIt = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
writeBack_arbitration_removeIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushIt = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushNext = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1019) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1064) begin
writeBack_arbitration_flushNext = 1'b1;
end
end
assign lastStageInstruction = writeBack_INSTRUCTION;
assign lastStagePc = writeBack_PC;
assign lastStageIsValid = writeBack_arbitration_isValid;
assign lastStageIsFiring = writeBack_arbitration_isFiring;
always @(*) begin
IBusCachedPlugin_fetcherHalt = 1'b0;
if(when_CsrPlugin_l922) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1019) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1064) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_DebugPlugin_l284) begin
if(when_DebugPlugin_l287) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
end
if(DebugPlugin_haltIt) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_DebugPlugin_l300) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_incomingInstruction = 1'b0;
if(when_Fetcher_l240) begin
IBusCachedPlugin_incomingInstruction = 1'b1;
end
end
always @(*) begin
_zz_when_DBusCachedPlugin_l386 = 1'b0;
if(DebugPlugin_godmode) begin
_zz_when_DBusCachedPlugin_l386 = 1'b1;
end
end
assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0;
assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit;
always @(*) begin
CsrPlugin_inWfi = 1'b0;
if(when_CsrPlugin_l1108) begin
CsrPlugin_inWfi = 1'b1;
end
end
always @(*) begin
CsrPlugin_thirdPartyWake = 1'b0;
if(DebugPlugin_haltIt) begin
CsrPlugin_thirdPartyWake = 1'b1;
end
end
always @(*) begin
CsrPlugin_jumpInterface_valid = 1'b0;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
if(when_CsrPlugin_l1064) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00};
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
end
default : begin
end
endcase
end
end
always @(*) begin
CsrPlugin_forceMachineWire = 1'b0;
if(DebugPlugin_godmode) begin
CsrPlugin_forceMachineWire = 1'b1;
end
end
always @(*) begin
CsrPlugin_allowInterrupts = 1'b1;
if(when_DebugPlugin_l316) begin
CsrPlugin_allowInterrupts = 1'b0;
end
end
always @(*) begin
CsrPlugin_allowException = 1'b1;
if(DebugPlugin_godmode) begin
CsrPlugin_allowException = 1'b0;
end
end
always @(*) begin
CsrPlugin_allowEbreakException = 1'b1;
if(DebugPlugin_allowEBreak) begin
CsrPlugin_allowEbreakException = 1'b0;
end
end
assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000);
assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}};
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1));
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3];
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
always @(*) begin
IBusCachedPlugin_fetchPc_correction = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
end
assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg);
always @(*) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0;
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1;
end
end
assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate);
assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready);
always @(*) begin
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc);
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
end
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
end
always @(*) begin
IBusCachedPlugin_fetchPc_flushed = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
end
assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate));
assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted);
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc;
always @(*) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b0;
if(IBusCachedPlugin_rsp_redoFetch) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b1;
end
end
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0;
if(IBusCachedPlugin_mmuBus_busy) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt);
assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0;
if(when_IBusCachedPlugin_l267) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt);
assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch;
assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch);
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg;
assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
if(when_Fetcher_l320) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
end
end
assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid);
assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0);
assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready));
assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready));
assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck);
assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck);
assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck);
assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1;
assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2;
assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3;
assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4;
assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck);
always @(*) begin
decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid;
case(switch_Fetcher_l362)
3'b010 : begin
decode_arbitration_isValid = 1'b1;
end
3'b011 : begin
decode_arbitration_isValid = 1'b1;
end
default : begin
end
endcase
end
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11];
always @(*) begin
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
end
always @(*) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31]));
if(_zz_6) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0;
end
end
assign _zz_2 = _zz__zz_2[19];
always @(*) begin
_zz_3[10] = _zz_2;
_zz_3[9] = _zz_2;
_zz_3[8] = _zz_2;
_zz_3[7] = _zz_2;
_zz_3[6] = _zz_2;
_zz_3[5] = _zz_2;
_zz_3[4] = _zz_2;
_zz_3[3] = _zz_2;
_zz_3[2] = _zz_2;
_zz_3[1] = _zz_2;
_zz_3[0] = _zz_2;
end
assign _zz_4 = _zz__zz_4[11];
always @(*) begin
_zz_5[18] = _zz_4;
_zz_5[17] = _zz_4;
_zz_5[16] = _zz_4;
_zz_5[15] = _zz_4;
_zz_5[14] = _zz_4;
_zz_5[13] = _zz_4;
_zz_5[12] = _zz_4;
_zz_5[11] = _zz_4;
_zz_5[10] = _zz_4;
_zz_5[9] = _zz_4;
_zz_5[8] = _zz_4;
_zz_5[7] = _zz_4;
_zz_5[6] = _zz_4;
_zz_5[5] = _zz_4;
_zz_5[4] = _zz_4;
_zz_5[3] = _zz_4;
_zz_5[2] = _zz_4;
_zz_5[1] = _zz_4;
_zz_5[0] = _zz_4;
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_6 = _zz__zz_6[1];
end
default : begin
_zz_6 = _zz__zz_6_1[1];
end
endcase
end
assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch);
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
end
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
end
assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}));
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
always @(*) begin
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
end
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid;
assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush);
assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00);
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
assign IBusCachedPlugin_rsp_issueDetected = 1'b0;
always @(*) begin
IBusCachedPlugin_rsp_redoFetch = 1'b0;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling));
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001;
end
end
assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00};
assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected));
assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1));
assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2));
assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3));
assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt);
assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid;
assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready;
assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data;
assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload;
assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL);
assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last);
always @(*) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
if(when_Stream_l342) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1;
end
end
assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid);
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last;
assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready;
assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE);
assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12];
assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD;
always @(*) begin
case(execute_DBusCachedPlugin_size)
2'b00 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0];
end
endcase
end
assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT);
assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready));
assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt);
assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid);
assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE);
assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA;
assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid;
assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck;
assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address;
assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
always @(*) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess;
if(when_DBusCachedPlugin_l386) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1;
end
end
assign when_DBusCachedPlugin_l386 = (_zz_when_DBusCachedPlugin_l386 && (! dataCache_1_io_cpu_memory_isWrite));
always @(*) begin
dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
if(writeBack_arbitration_haltByOther) begin
dataCache_1_io_cpu_writeBack_isValid = 1'b0;
end
end
assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00);
assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA;
assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF;
always @(*) begin
DBusCachedPlugin_redoBranch_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_redoBranch_valid = 1'b1;
end
end
end
assign DBusCachedPlugin_redoBranch_payload = writeBack_PC;
always @(*) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
end
end
end
assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA;
always @(*) begin
DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code};
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101);
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1};
end
end
end
assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt);
assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0];
assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8];
assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16];
assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24];
always @(*) begin
writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted;
writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2;
writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2;
writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3;
end
assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0];
assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12];
assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0];
end
assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0];
end
always @(*) begin
case(switch_Misc_l200)
2'b00 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1;
end
2'b01 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3;
end
default : begin
writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf;
end
endcase
end
assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign IBusCachedPlugin_mmuBus_busy = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign DBusCachedPlugin_mmuBus_busy = 1'b0;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1) != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}};
assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1];
assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2;
assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6];
assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2;
assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8];
assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2;
assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18];
assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2;
assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21];
assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2;
assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23];
assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2;
assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26];
assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[34 : 34];
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION));
assign decodeExceptionPort_payload_code = 4'b0010;
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0);
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0;
assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1;
always @(*) begin
lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
if(_zz_7) begin
lastStageRegFileWrite_valid = 1'b1;
end
end
always @(*) begin
lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
if(_zz_7) begin
lastStageRegFileWrite_payload_address = 5'h0;
end
end
always @(*) begin
lastStageRegFileWrite_payload_data = _zz_decode_RS2_2;
if(_zz_7) begin
lastStageRegFileWrite_payload_data = 32'h0;
end
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_BITWISE : begin
_zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_binary_sequential_SLT_SLTU : begin
_zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA};
end
default : begin
_zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB;
end
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC1 = execute_RS1;
end
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin
_zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1};
end
`Src1CtrlEnum_binary_sequential_IMU : begin
_zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0};
end
default : begin
_zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1};
end
endcase
end
assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_SRC2_2[19] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[18] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[17] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[16] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[15] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[14] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[13] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[12] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[11] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[10] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[9] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[8] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[7] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[6] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[5] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[4] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[3] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[2] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[1] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[0] = _zz_execute_SRC2_1;
end
assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11];
always @(*) begin
_zz_execute_SRC2_4[19] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[18] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[17] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[16] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[15] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[14] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[13] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[12] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[11] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[10] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[9] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[8] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[7] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[6] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[5] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[4] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[3] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[2] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[1] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[0] = _zz_execute_SRC2_3;
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC2_5 = execute_RS2;
end
`Src2CtrlEnum_binary_sequential_IMI : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_binary_sequential_IMS : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_execute_SRC2_5 = _zz_execute_SRC2;
end
endcase
end
always @(*) begin
execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub;
if(execute_SRC2_FORCE_ZERO) begin
execute_SrcPlugin_addSub = execute_SRC1;
end
end
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0];
always @(*) begin
_zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31];
_zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30];
_zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29];
_zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28];
_zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27];
_zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26];
_zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25];
_zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24];
_zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23];
_zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22];
_zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21];
_zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20];
_zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19];
_zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18];
_zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17];
_zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16];
_zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15];
_zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14];
_zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13];
_zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12];
_zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11];
_zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10];
_zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9];
_zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8];
_zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7];
_zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6];
_zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5];
_zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4];
_zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3];
_zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2];
_zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1];
_zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0];
end
assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1);
always @(*) begin
_zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31];
_zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30];
_zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29];
_zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28];
_zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27];
_zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26];
_zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25];
_zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24];
_zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23];
_zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22];
_zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21];
_zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20];
_zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19];
_zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18];
_zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17];
_zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16];
_zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15];
_zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14];
_zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13];
_zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12];
_zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11];
_zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10];
_zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9];
_zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8];
_zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7];
_zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6];
_zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5];
_zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4];
_zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3];
_zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2];
_zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1];
_zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0];
end
always @(*) begin
HazardSimplePlugin_src0Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l48) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l48_1) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l48_2) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l105) begin
HazardSimplePlugin_src0Hazard = 1'b0;
end
end
always @(*) begin
HazardSimplePlugin_src1Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l51) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l51_1) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l51_2) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l108) begin
HazardSimplePlugin_src1Hazard = 1'b0;
end
end
assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2;
assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]);
assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l47 = 1'b1;
assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47));
assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE));
assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE));
assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE);
assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE);
assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard));
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12];
always @(*) begin
casez(switch_Misc_l200_1)
3'b000 : begin
_zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq;
end
3'b001 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq);
end
3'b1?1 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS);
end
default : begin
_zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS;
end
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b0;
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
default : begin
_zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT;
end
endcase
end
assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]);
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1];
end
default : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1];
end
endcase
end
assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6);
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src1 = execute_RS1;
end
default : begin
execute_BranchPlugin_branch_src1 = execute_PC;
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]};
end
default : begin
execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0});
if(execute_PREDICTION_HAD_BRANCHED2) begin
execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9};
end
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2;
end
assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4;
end
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0));
assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC;
always @(*) begin
BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1]));
if(when_BranchPlugin_l296) begin
BranchPlugin_branchExceptionPort_valid = 1'b0;
end
end
assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000;
assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC;
assign when_BranchPlugin_l296 = 1'b0;
assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid;
always @(*) begin
CsrPlugin_privilege = 2'b11;
if(CsrPlugin_forceMachineWire) begin
CsrPlugin_privilege = 2'b11;
end
end
assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11;
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0];
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0];
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
end
if(decode_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
end
if(execute_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
if(memory_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
end
end
assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck);
assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000);
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11));
assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0));
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid);
assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt);
always @(*) begin
CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2;
if(when_CsrPlugin_l991) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
if(CsrPlugin_hadException) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
end
assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000);
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
always @(*) begin
CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
if(CsrPlugin_hadException) begin
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
end
end
always @(*) begin
CsrPlugin_trapCause = CsrPlugin_interrupt_code;
if(CsrPlugin_hadException) begin
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
end
end
always @(*) begin
CsrPlugin_xtvec_mode = 2'bxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
end
default : begin
end
endcase
end
always @(*) begin
CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
end
default : begin
end
endcase
end
assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump);
assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28];
assign contextSwitching = CsrPlugin_jumpInterface_valid;
assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI));
assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake);
assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000);
assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0);
always @(*) begin
execute_CsrPlugin_illegalAccess = 1'b1;
if(execute_CsrPlugin_csr_3264) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3857) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3858) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3859) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3860) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_769) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_768) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_836) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_772) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_773) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_833) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_832) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_834) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_835) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2816) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2944) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2818) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2946) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_3072) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3200) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3074) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3202) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3008) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_4032) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(CsrPlugin_csrMapping_allowCsrSignal) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_illegalAccess = 1'b1;
end
if(when_CsrPlugin_l1302) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_illegalInstruction = 1'b0;
if(when_CsrPlugin_l1136) begin
if(when_CsrPlugin_l1137) begin
execute_CsrPlugin_illegalInstruction = 1'b1;
end
end
end
always @(*) begin
CsrPlugin_selfException_valid = 1'b0;
if(when_CsrPlugin_l1129) begin
CsrPlugin_selfException_valid = 1'b1;
end
if(when_CsrPlugin_l1144) begin
CsrPlugin_selfException_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_selfException_payload_code = 4'bxxxx;
if(when_CsrPlugin_l1129) begin
CsrPlugin_selfException_payload_code = 4'b0010;
end
if(when_CsrPlugin_l1144) begin
case(CsrPlugin_privilege)
2'b00 : begin
CsrPlugin_selfException_payload_code = 4'b1000;
end
default : begin
CsrPlugin_selfException_payload_code = 4'b1011;
end
endcase
end
end
assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction);
assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]);
assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL));
always @(*) begin
execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_writeInstruction = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_readInstruction = 1'b0;
end
end
assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck));
assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck));
assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects);
assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal;
assign switch_Misc_l200_2 = execute_INSTRUCTION[13];
always @(*) begin
case(switch_Misc_l200_2)
1'b0 : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1;
end
default : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
end
endcase
end
assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal;
assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR);
assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0));
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
assign execute_MulPlugin_a = execute_RS1;
assign execute_MulPlugin_b = execute_RS2;
assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12];
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_aSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_aSigned = 1'b1;
end
default : begin
execute_MulPlugin_aSigned = 1'b0;
end
endcase
end
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_bSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_bSigned = 1'b0;
end
default : begin
execute_MulPlugin_bSigned = 1'b0;
end
endcase
end
assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0];
assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0];
assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]};
assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]};
assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]};
assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]};
assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1));
assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL);
assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12];
assign memory_DivPlugin_frontendOk = 1'b1;
always @(*) begin
memory_DivPlugin_div_counter_willIncrement = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_div_counter_willIncrement = 1'b1;
end
end
end
always @(*) begin
memory_DivPlugin_div_counter_willClear = 1'b0;
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_div_counter_willClear = 1'b1;
end
end
assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21);
assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement);
always @(*) begin
if(memory_DivPlugin_div_counter_willOverflow) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end else begin
memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext);
end
if(memory_DivPlugin_div_counter_willClear) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end
end
assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20);
assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck);
assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV);
assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done));
assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done));
assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0];
assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]};
assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator);
assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1);
assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0];
assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20);
assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]);
assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck);
assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED);
assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
always @(*) begin
_zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
_zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1;
end
assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext);
assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0);
assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy));
assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak));
always @(*) begin
debug_bus_cmd_ready = 1'b1;
if(debug_bus_cmd_valid) begin
case(switch_DebugPlugin_l256)
6'h01 : begin
if(debug_bus_cmd_payload_wr) begin
debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready;
end
end
default : begin
end
endcase
end
end
always @(*) begin
debug_bus_rsp_data = DebugPlugin_busReadDataReg;
if(when_DebugPlugin_l244) begin
debug_bus_rsp_data[0] = DebugPlugin_resetIt;
debug_bus_rsp_data[1] = DebugPlugin_haltIt;
debug_bus_rsp_data[2] = DebugPlugin_isPipBusy;
debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak;
debug_bus_rsp_data[4] = DebugPlugin_stepIt;
end
end
assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244);
always @(*) begin
IBusCachedPlugin_injectionPort_valid = 1'b0;
if(debug_bus_cmd_valid) begin
case(switch_DebugPlugin_l256)
6'h01 : begin
if(debug_bus_cmd_payload_wr) begin
IBusCachedPlugin_injectionPort_valid = 1'b1;
end
end
default : begin
end
endcase
end
end
assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data;
assign switch_DebugPlugin_l256 = debug_bus_cmd_payload_address[7 : 2];
assign when_DebugPlugin_l260 = debug_bus_cmd_payload_data[16];
assign when_DebugPlugin_l260_1 = debug_bus_cmd_payload_data[24];
assign when_DebugPlugin_l261 = debug_bus_cmd_payload_data[17];
assign when_DebugPlugin_l261_1 = debug_bus_cmd_payload_data[25];
assign when_DebugPlugin_l262 = debug_bus_cmd_payload_data[25];
assign when_DebugPlugin_l263 = debug_bus_cmd_payload_data[25];
assign when_DebugPlugin_l264 = debug_bus_cmd_payload_data[18];
assign when_DebugPlugin_l264_1 = debug_bus_cmd_payload_data[26];
assign when_DebugPlugin_l284 = (execute_arbitration_isValid && execute_DO_EBREAK);
assign when_DebugPlugin_l287 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0);
assign when_DebugPlugin_l300 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction);
assign debug_resetOut = DebugPlugin_resetIt_regNext;
assign when_DebugPlugin_l316 = (DebugPlugin_haltIt || DebugPlugin_stepIt);
assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE);
assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready);
assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers);
assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired));
assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready));
assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1;
assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2;
end
default : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]};
end
endcase
end
assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0);
always @(*) begin
CfuPlugin_bus_rsp_rsp_ready = 1'b0;
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers);
end
end
assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid);
assign when_Pipeline_l124 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack));
assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL;
assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1;
assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL;
assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL;
assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1;
assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL;
assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1;
assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL;
assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL;
assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1;
assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL;
assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL;
assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1;
assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck);
assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL;
assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck);
assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL;
assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL;
assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL;
assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck);
assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL;
assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL;
assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL;
assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL;
assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1;
assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck);
assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL;
assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck);
assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL;
assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck);
assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL;
assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck);
assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_51 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_55 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_61 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_62 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_64 = (! writeBack_arbitration_isStuck);
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000));
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000));
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00));
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0));
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt);
assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
always @(*) begin
IBusCachedPlugin_injectionPort_ready = 1'b0;
case(switch_Fetcher_l362)
3'b100 : begin
IBusCachedPlugin_injectionPort_ready = 1'b1;
end
default : begin
end
endcase
end
assign when_Fetcher_l378 = (! decode_arbitration_isStuck);
assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck);
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0;
if(execute_CsrPlugin_csr_3264) begin
_zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000;
_zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0;
if(execute_CsrPlugin_csr_3857) begin
_zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = 4'b1011;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0;
if(execute_CsrPlugin_csr_3858) begin
_zz_CsrPlugin_csrMapping_readDataInit_4[4 : 0] = 5'h16;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0;
if(execute_CsrPlugin_csr_3859) begin
_zz_CsrPlugin_csrMapping_readDataInit_5[5 : 0] = 6'h21;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0;
if(execute_CsrPlugin_csr_769) begin
_zz_CsrPlugin_csrMapping_readDataInit_6[31 : 30] = CsrPlugin_misa_base;
_zz_CsrPlugin_csrMapping_readDataInit_6[25 : 0] = CsrPlugin_misa_extensions;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0;
if(execute_CsrPlugin_csr_768) begin
_zz_CsrPlugin_csrMapping_readDataInit_7[12 : 11] = CsrPlugin_mstatus_MPP;
_zz_CsrPlugin_csrMapping_readDataInit_7[7 : 7] = CsrPlugin_mstatus_MPIE;
_zz_CsrPlugin_csrMapping_readDataInit_7[3 : 3] = CsrPlugin_mstatus_MIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0;
if(execute_CsrPlugin_csr_836) begin
_zz_CsrPlugin_csrMapping_readDataInit_8[11 : 11] = CsrPlugin_mip_MEIP;
_zz_CsrPlugin_csrMapping_readDataInit_8[7 : 7] = CsrPlugin_mip_MTIP;
_zz_CsrPlugin_csrMapping_readDataInit_8[3 : 3] = CsrPlugin_mip_MSIP;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0;
if(execute_CsrPlugin_csr_772) begin
_zz_CsrPlugin_csrMapping_readDataInit_9[11 : 11] = CsrPlugin_mie_MEIE;
_zz_CsrPlugin_csrMapping_readDataInit_9[7 : 7] = CsrPlugin_mie_MTIE;
_zz_CsrPlugin_csrMapping_readDataInit_9[3 : 3] = CsrPlugin_mie_MSIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0;
if(execute_CsrPlugin_csr_773) begin
_zz_CsrPlugin_csrMapping_readDataInit_10[31 : 2] = CsrPlugin_mtvec_base;
_zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = CsrPlugin_mtvec_mode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0;
if(execute_CsrPlugin_csr_833) begin
_zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = CsrPlugin_mepc;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0;
if(execute_CsrPlugin_csr_832) begin
_zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = CsrPlugin_mscratch;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0;
if(execute_CsrPlugin_csr_834) begin
_zz_CsrPlugin_csrMapping_readDataInit_13[31 : 31] = CsrPlugin_mcause_interrupt;
_zz_CsrPlugin_csrMapping_readDataInit_13[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0;
if(execute_CsrPlugin_csr_835) begin
_zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mtval;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0;
if(execute_CsrPlugin_csr_2816) begin
_zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0;
if(execute_CsrPlugin_csr_2944) begin
_zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0;
if(execute_CsrPlugin_csr_2818) begin
_zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_minstret[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0;
if(execute_CsrPlugin_csr_2946) begin
_zz_CsrPlugin_csrMapping_readDataInit_18[31 : 0] = CsrPlugin_minstret[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0;
if(execute_CsrPlugin_csr_3072) begin
_zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0;
if(execute_CsrPlugin_csr_3200) begin
_zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0;
if(execute_CsrPlugin_csr_3074) begin
_zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_minstret[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0;
if(execute_CsrPlugin_csr_3202) begin
_zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_minstret[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0;
if(execute_CsrPlugin_csr_3008) begin
_zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0;
if(execute_CsrPlugin_csr_4032) begin
_zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1;
end
end
assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_6) | (_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8))) | (((_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10) | (_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12)) | ((_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16)))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24))));
assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]);
assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR));
assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR};
assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010);
assign iBusWishbone_BTE = 2'b00;
assign iBusWishbone_SEL = 4'b1111;
assign iBusWishbone_WE = 1'b0;
assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
always @(*) begin
iBusWishbone_CYC = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_CYC = 1'b1;
end
end
always @(*) begin
iBusWishbone_STB = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_STB = 1'b1;
end
end
assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000));
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
assign iBus_rsp_valid = _zz_iBus_rsp_valid;
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
assign iBus_rsp_payload_error = 1'b0;
assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101);
assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid;
assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr;
assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111));
assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4));
assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2);
assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000);
assign dBusWishbone_BTE = 2'b00;
assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111);
assign dBusWishbone_WE = _zz_dBus_cmd_ready_3;
assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data;
assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK);
assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1;
assign dBusWishbone_STB = _zz_dBus_cmd_ready_1;
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
assign dBus_rsp_payload_error = 1'b0;
always @(posedge clk) begin
if(reset) begin
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
IBusCachedPlugin_fetchPc_booted <= 1'b0;
IBusCachedPlugin_fetchPc_inc <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter;
IBusCachedPlugin_rspCounter <= 32'h0;
dataCache_1_io_mem_cmd_rValid <= 1'b0;
dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0;
DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter;
DBusCachedPlugin_rspCounter <= 32'h0;
_zz_7 <= 1'b1;
HazardSimplePlugin_writeBackBuffer_valid <= 1'b0;
CsrPlugin_misa_base <= 2'b01;
CsrPlugin_misa_extensions <= 26'h0000042;
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= 1'b0;
CsrPlugin_mstatus_MPP <= 2'b11;
CsrPlugin_mie_MEIE <= 1'b0;
CsrPlugin_mie_MTIE <= 1'b0;
CsrPlugin_mie_MSIE <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
CsrPlugin_interrupt_valid <= 1'b0;
CsrPlugin_lastStageWasWfi <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
CsrPlugin_hadException <= 1'b0;
execute_CsrPlugin_wfiWake <= 1'b0;
memory_DivPlugin_div_counter_value <= 6'h0;
_zz_CsrPlugin_csrMapping_readDataInit <= 32'h0;
execute_CfuPlugin_hold <= 1'b0;
execute_CfuPlugin_fired <= 1'b0;
CfuPlugin_bus_rsp_rValid <= 1'b0;
execute_arbitration_isValid <= 1'b0;
memory_arbitration_isValid <= 1'b0;
writeBack_arbitration_isValid <= 1'b0;
switch_Fetcher_l362 <= 3'b000;
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0;
_zz_iBusWishbone_ADR <= 3'b000;
_zz_iBus_rsp_valid <= 1'b0;
_zz_dBus_cmd_ready <= 3'b000;
_zz_dBus_rsp_valid <= 1'b0;
end else begin
if(IBusCachedPlugin_fetchPc_correction) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_output_fire) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
end
IBusCachedPlugin_fetchPc_booted <= 1'b1;
if(when_Fetcher_l131) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_output_fire_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b1;
end
if(when_Fetcher_l131_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(when_Fetcher_l158) begin
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
end
if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0));
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
end
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush));
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
end
if(when_Fetcher_l329) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(when_Fetcher_l329_1) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(when_Fetcher_l329_2) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(when_Fetcher_l329_3) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(when_Fetcher_l329_4) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(iBus_rsp_valid) begin
IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001);
end
if(dataCache_1_io_mem_cmd_valid) begin
dataCache_1_io_mem_cmd_rValid <= 1'b1;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_rValid <= 1'b0;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid;
end
if(dBus_rsp_valid) begin
DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001);
end
_zz_7 <= 1'b0;
HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid;
if(when_CsrPlugin_l909) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
end
if(when_CsrPlugin_l909_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
end
if(when_CsrPlugin_l909_2) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
end
if(when_CsrPlugin_l909_3) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
end
CsrPlugin_interrupt_valid <= 1'b0;
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
end
CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI));
if(CsrPlugin_pipelineLiberator_active) begin
if(when_CsrPlugin_l980) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1;
end
if(when_CsrPlugin_l980_1) begin
CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0;
end
if(when_CsrPlugin_l980_2) begin
CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1;
end
end
if(when_CsrPlugin_l985) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
end
if(CsrPlugin_interruptJump) begin
CsrPlugin_interrupt_valid <= 1'b0;
end
CsrPlugin_hadException <= CsrPlugin_exception;
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
end
default : begin
end
endcase
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_mstatus_MPP <= 2'b00;
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
CsrPlugin_mstatus_MPIE <= 1'b1;
end
default : begin
end
endcase
end
execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake);
memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext;
if(execute_CfuPlugin_schedule) begin
execute_CfuPlugin_hold <= 1'b1;
end
if(CfuPlugin_bus_cmd_ready) begin
execute_CfuPlugin_hold <= 1'b0;
end
if(CfuPlugin_bus_cmd_fire) begin
execute_CfuPlugin_fired <= 1'b1;
end
if(when_CfuPlugin_l171) begin
execute_CfuPlugin_fired <= 1'b0;
end
if(CfuPlugin_bus_rsp_valid) begin
CfuPlugin_bus_rsp_rValid <= 1'b1;
end
if(CfuPlugin_bus_rsp_rsp_ready) begin
CfuPlugin_bus_rsp_rValid <= 1'b0;
end
if(when_Pipeline_l124_62) begin
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l151) begin
execute_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154) begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(when_Pipeline_l151_1) begin
memory_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_1) begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(when_Pipeline_l151_2) begin
writeBack_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_2) begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
case(switch_Fetcher_l362)
3'b000 : begin
if(IBusCachedPlugin_injectionPort_valid) begin
switch_Fetcher_l362 <= 3'b001;
end
end
3'b001 : begin
switch_Fetcher_l362 <= 3'b010;
end
3'b010 : begin
switch_Fetcher_l362 <= 3'b011;
end
3'b011 : begin
if(when_Fetcher_l378) begin
switch_Fetcher_l362 <= 3'b100;
end
end
3'b100 : begin
switch_Fetcher_l362 <= 3'b000;
end
default : begin
end
endcase
if(execute_CsrPlugin_csr_769) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30];
CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0];
end
end
if(execute_CsrPlugin_csr_768) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11];
CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_772) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11];
CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_3008) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(when_InstructionCache_l239) begin
if(iBusWishbone_ACK) begin
_zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001);
end
end
_zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK);
if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin
_zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001);
if(_zz_dBus_cmd_ready_4) begin
_zz_dBus_cmd_ready <= 3'b000;
end
end
_zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK);
end
end
always @(posedge clk) begin
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload;
end
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
end
if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin
IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit;
end
if(dataCache_1_io_mem_cmd_ready) begin
dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr;
dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached;
dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address;
dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data;
dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask;
dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size;
dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address;
dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data;
dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size;
dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last;
end
HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address;
HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data;
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
CsrPlugin_mip_MSIP <= softwareInterrupt;
CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001);
if(writeBack_arbitration_isFiring) begin
CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001);
end
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
end
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr);
end
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code;
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr;
end
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_code <= 4'b0111;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_code <= 4'b0011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_code <= 4'b1011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
end
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
CsrPlugin_mepc <= writeBack_PC;
if(CsrPlugin_hadException) begin
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
end
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l126) begin
memory_DivPlugin_div_done <= 1'b1;
end
if(when_MulDivIterativePlugin_l126_1) begin
memory_DivPlugin_div_done <= 1'b0;
end
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator;
memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder;
if(when_MulDivIterativePlugin_l151) begin
memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0];
end
end
end
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_accumulator <= 65'h0;
memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2);
memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1);
memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13]))));
end
externalInterruptArray_regNext <= externalInterruptArray;
if(CfuPlugin_bus_rsp_ready) begin
CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0;
end
if(when_Pipeline_l124) begin
decode_to_execute_PC <= decode_PC;
end
if(when_Pipeline_l124_1) begin
execute_to_memory_PC <= _zz_execute_SRC2;
end
if(when_Pipeline_l124_2) begin
memory_to_writeBack_PC <= memory_PC;
end
if(when_Pipeline_l124_3) begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if(when_Pipeline_l124_4) begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if(when_Pipeline_l124_5) begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if(when_Pipeline_l124_6) begin
decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_7) begin
execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_8) begin
memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_9) begin
decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY;
end
if(when_Pipeline_l124_10) begin
decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL;
end
if(when_Pipeline_l124_11) begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if(when_Pipeline_l124_12) begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if(when_Pipeline_l124_13) begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if(when_Pipeline_l124_14) begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
end
if(when_Pipeline_l124_15) begin
decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL;
end
if(when_Pipeline_l124_16) begin
decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL;
end
if(when_Pipeline_l124_17) begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_18) begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_19) begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_20) begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if(when_Pipeline_l124_21) begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_22) begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_23) begin
decode_to_execute_MEMORY_WR <= decode_MEMORY_WR;
end
if(when_Pipeline_l124_24) begin
execute_to_memory_MEMORY_WR <= execute_MEMORY_WR;
end
if(when_Pipeline_l124_25) begin
memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR;
end
if(when_Pipeline_l124_26) begin
decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT;
end
if(when_Pipeline_l124_27) begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if(when_Pipeline_l124_28) begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL;
end
if(when_Pipeline_l124_29) begin
decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL;
end
if(when_Pipeline_l124_30) begin
execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL;
end
if(when_Pipeline_l124_31) begin
decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL;
end
if(when_Pipeline_l124_32) begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if(when_Pipeline_l124_33) begin
decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL;
end
if(when_Pipeline_l124_34) begin
execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL;
end
if(when_Pipeline_l124_35) begin
memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL;
end
if(when_Pipeline_l124_36) begin
decode_to_execute_IS_MUL <= decode_IS_MUL;
end
if(when_Pipeline_l124_37) begin
execute_to_memory_IS_MUL <= execute_IS_MUL;
end
if(when_Pipeline_l124_38) begin
memory_to_writeBack_IS_MUL <= memory_IS_MUL;
end
if(when_Pipeline_l124_39) begin
decode_to_execute_IS_DIV <= decode_IS_DIV;
end
if(when_Pipeline_l124_40) begin
execute_to_memory_IS_DIV <= execute_IS_DIV;
end
if(when_Pipeline_l124_41) begin
decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
end
if(when_Pipeline_l124_42) begin
decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
end
if(when_Pipeline_l124_43) begin
decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE;
end
if(when_Pipeline_l124_44) begin
decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
end
if(when_Pipeline_l124_45) begin
decode_to_execute_RS1 <= decode_RS1;
end
if(when_Pipeline_l124_46) begin
decode_to_execute_RS2 <= decode_RS2;
end
if(when_Pipeline_l124_47) begin
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
end
if(when_Pipeline_l124_48) begin
decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2;
end
if(when_Pipeline_l124_49) begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if(when_Pipeline_l124_50) begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if(when_Pipeline_l124_51) begin
decode_to_execute_DO_EBREAK <= decode_DO_EBREAK;
end
if(when_Pipeline_l124_52) begin
execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_53) begin
memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_54) begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2;
end
if(when_Pipeline_l124_55) begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1;
end
if(when_Pipeline_l124_56) begin
execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT;
end
if(when_Pipeline_l124_57) begin
execute_to_memory_MUL_LL <= execute_MUL_LL;
end
if(when_Pipeline_l124_58) begin
execute_to_memory_MUL_LH <= execute_MUL_LH;
end
if(when_Pipeline_l124_59) begin
execute_to_memory_MUL_HL <= execute_MUL_HL;
end
if(when_Pipeline_l124_60) begin
execute_to_memory_MUL_HH <= execute_MUL_HH;
end
if(when_Pipeline_l124_61) begin
memory_to_writeBack_MUL_HH <= memory_MUL_HH;
end
if(when_Pipeline_l124_63) begin
memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l124_64) begin
memory_to_writeBack_MUL_LOW <= memory_MUL_LOW;
end
if(when_CsrPlugin_l1264) begin
execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0);
end
if(when_CsrPlugin_l1264_1) begin
execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11);
end
if(when_CsrPlugin_l1264_2) begin
execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12);
end
if(when_CsrPlugin_l1264_3) begin
execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13);
end
if(when_CsrPlugin_l1264_4) begin
execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14);
end
if(when_CsrPlugin_l1264_5) begin
execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301);
end
if(when_CsrPlugin_l1264_6) begin
execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300);
end
if(when_CsrPlugin_l1264_7) begin
execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344);
end
if(when_CsrPlugin_l1264_8) begin
execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304);
end
if(when_CsrPlugin_l1264_9) begin
execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305);
end
if(when_CsrPlugin_l1264_10) begin
execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341);
end
if(when_CsrPlugin_l1264_11) begin
execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340);
end
if(when_CsrPlugin_l1264_12) begin
execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342);
end
if(when_CsrPlugin_l1264_13) begin
execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343);
end
if(when_CsrPlugin_l1264_14) begin
execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00);
end
if(when_CsrPlugin_l1264_15) begin
execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80);
end
if(when_CsrPlugin_l1264_16) begin
execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02);
end
if(when_CsrPlugin_l1264_17) begin
execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82);
end
if(when_CsrPlugin_l1264_18) begin
execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00);
end
if(when_CsrPlugin_l1264_19) begin
execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80);
end
if(when_CsrPlugin_l1264_20) begin
execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02);
end
if(when_CsrPlugin_l1264_21) begin
execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82);
end
if(when_CsrPlugin_l1264_22) begin
execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0);
end
if(when_CsrPlugin_l1264_23) begin
execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0);
end
if(execute_CsrPlugin_csr_836) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_773) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2];
CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0];
end
end
if(execute_CsrPlugin_csr_833) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_832) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_834) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31];
CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0];
end
end
if(execute_CsrPlugin_csr_835) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2816) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2944) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2818) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2946) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO;
end
always @(posedge clk) begin
DebugPlugin_firstCycle <= 1'b0;
if(debug_bus_cmd_ready) begin
DebugPlugin_firstCycle <= 1'b1;
end
DebugPlugin_secondCycle <= DebugPlugin_firstCycle;
DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction);
if(writeBack_arbitration_isValid) begin
DebugPlugin_busReadDataReg <= _zz_decode_RS2_2;
end
_zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2];
if(when_DebugPlugin_l284) begin
DebugPlugin_busReadDataReg <= execute_PC;
end
DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt;
end
always @(posedge clk) begin
if(debugReset) begin
DebugPlugin_resetIt <= 1'b0;
DebugPlugin_haltIt <= 1'b0;
DebugPlugin_stepIt <= 1'b0;
DebugPlugin_godmode <= 1'b0;
DebugPlugin_haltedByBreak <= 1'b0;
DebugPlugin_debugUsed <= 1'b0;
DebugPlugin_disableEbreak <= 1'b0;
end else begin
if(when_DebugPlugin_l225) begin
DebugPlugin_godmode <= 1'b1;
end
if(debug_bus_cmd_valid) begin
DebugPlugin_debugUsed <= 1'b1;
end
if(debug_bus_cmd_valid) begin
case(switch_DebugPlugin_l256)
6'h0 : begin
if(debug_bus_cmd_payload_wr) begin
DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4];
if(when_DebugPlugin_l260) begin
DebugPlugin_resetIt <= 1'b1;
end
if(when_DebugPlugin_l260_1) begin
DebugPlugin_resetIt <= 1'b0;
end
if(when_DebugPlugin_l261) begin
DebugPlugin_haltIt <= 1'b1;
end
if(when_DebugPlugin_l261_1) begin
DebugPlugin_haltIt <= 1'b0;
end
if(when_DebugPlugin_l262) begin
DebugPlugin_haltedByBreak <= 1'b0;
end
if(when_DebugPlugin_l263) begin
DebugPlugin_godmode <= 1'b0;
end
if(when_DebugPlugin_l264) begin
DebugPlugin_disableEbreak <= 1'b1;
end
if(when_DebugPlugin_l264_1) begin
DebugPlugin_disableEbreak <= 1'b0;
end
end
end
default : begin
end
endcase
end
if(when_DebugPlugin_l284) begin
if(when_DebugPlugin_l287) begin
DebugPlugin_haltIt <= 1'b1;
DebugPlugin_haltedByBreak <= 1'b1;
end
end
if(when_DebugPlugin_l300) begin
if(decode_arbitration_isValid) begin
DebugPlugin_haltIt <= 1'b1;
end
end
end
end
endmodule
module DataCache (
input io_cpu_execute_isValid,
input [31:0] io_cpu_execute_address,
output reg io_cpu_execute_haltIt,
input io_cpu_execute_args_wr,
input [1:0] io_cpu_execute_args_size,
input io_cpu_execute_args_totalyConsistent,
output io_cpu_execute_refilling,
input io_cpu_memory_isValid,
input io_cpu_memory_isStuck,
output io_cpu_memory_isWrite,
input [31:0] io_cpu_memory_address,
input [31:0] io_cpu_memory_mmuRsp_physicalAddress,
input io_cpu_memory_mmuRsp_isIoAccess,
input io_cpu_memory_mmuRsp_isPaging,
input io_cpu_memory_mmuRsp_allowRead,
input io_cpu_memory_mmuRsp_allowWrite,
input io_cpu_memory_mmuRsp_allowExecute,
input io_cpu_memory_mmuRsp_exception,
input io_cpu_memory_mmuRsp_refilling,
input io_cpu_memory_mmuRsp_bypassTranslation,
input io_cpu_writeBack_isValid,
input io_cpu_writeBack_isStuck,
input io_cpu_writeBack_isUser,
output reg io_cpu_writeBack_haltIt,
output io_cpu_writeBack_isWrite,
input [31:0] io_cpu_writeBack_storeData,
output reg [31:0] io_cpu_writeBack_data,
input [31:0] io_cpu_writeBack_address,
output io_cpu_writeBack_mmuException,
output io_cpu_writeBack_unalignedAccess,
output reg io_cpu_writeBack_accessError,
output io_cpu_writeBack_keepMemRspData,
input io_cpu_writeBack_fence_SW,
input io_cpu_writeBack_fence_SR,
input io_cpu_writeBack_fence_SO,
input io_cpu_writeBack_fence_SI,
input io_cpu_writeBack_fence_PW,
input io_cpu_writeBack_fence_PR,
input io_cpu_writeBack_fence_PO,
input io_cpu_writeBack_fence_PI,
input [3:0] io_cpu_writeBack_fence_FM,
output io_cpu_writeBack_exclusiveOk,
output reg io_cpu_redo,
input io_cpu_flush_valid,
output io_cpu_flush_ready,
output reg io_mem_cmd_valid,
input io_mem_cmd_ready,
output reg io_mem_cmd_payload_wr,
output io_mem_cmd_payload_uncached,
output reg [31:0] io_mem_cmd_payload_address,
output [31:0] io_mem_cmd_payload_data,
output [3:0] io_mem_cmd_payload_mask,
output reg [2:0] io_mem_cmd_payload_size,
output io_mem_cmd_payload_last,
input io_mem_rsp_valid,
input io_mem_rsp_payload_last,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [21:0] _zz_ways_0_tags_port0;
reg [31:0] _zz_ways_0_data_port0;
wire [21:0] _zz_ways_0_tags_port;
wire [9:0] _zz_stage0_dataColisions;
wire [9:0] _zz__zz_stageA_dataColisions;
wire [0:0] _zz_when;
wire [2:0] _zz_loader_counter_valueNext;
wire [0:0] _zz_loader_counter_valueNext_1;
wire [1:0] _zz_loader_waysAllocator;
reg _zz_1;
reg _zz_2;
wire haltCpu;
reg tagsReadCmd_valid;
reg [6:0] tagsReadCmd_payload;
reg tagsWriteCmd_valid;
reg [0:0] tagsWriteCmd_payload_way;
reg [6:0] tagsWriteCmd_payload_address;
reg tagsWriteCmd_payload_data_valid;
reg tagsWriteCmd_payload_data_error;
reg [19:0] tagsWriteCmd_payload_data_address;
reg tagsWriteLastCmd_valid;
reg [0:0] tagsWriteLastCmd_payload_way;
reg [6:0] tagsWriteLastCmd_payload_address;
reg tagsWriteLastCmd_payload_data_valid;
reg tagsWriteLastCmd_payload_data_error;
reg [19:0] tagsWriteLastCmd_payload_data_address;
reg dataReadCmd_valid;
reg [9:0] dataReadCmd_payload;
reg dataWriteCmd_valid;
reg [0:0] dataWriteCmd_payload_way;
reg [9:0] dataWriteCmd_payload_address;
reg [31:0] dataWriteCmd_payload_data;
reg [3:0] dataWriteCmd_payload_mask;
wire _zz_ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_error;
wire [19:0] ways_0_tagsReadRsp_address;
wire [21:0] _zz_ways_0_tagsReadRsp_valid_1;
wire _zz_ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRsp;
wire when_DataCache_l634;
wire when_DataCache_l637;
wire when_DataCache_l656;
wire rspSync;
wire rspLast;
reg memCmdSent;
wire io_mem_cmd_fire;
wire when_DataCache_l678;
reg [3:0] _zz_stage0_mask;
wire [3:0] stage0_mask;
wire [0:0] stage0_dataColisions;
wire [0:0] stage0_wayInvalidate;
wire stage0_isAmo;
wire when_DataCache_l763;
reg stageA_request_wr;
reg [1:0] stageA_request_size;
reg stageA_request_totalyConsistent;
wire when_DataCache_l763_1;
reg [3:0] stageA_mask;
wire stageA_isAmo;
wire stageA_isLrsc;
wire [0:0] stageA_wayHits;
wire when_DataCache_l763_2;
reg [0:0] stageA_wayInvalidate;
wire when_DataCache_l763_3;
reg [0:0] stage0_dataColisions_regNextWhen;
wire [0:0] _zz_stageA_dataColisions;
wire [0:0] stageA_dataColisions;
wire when_DataCache_l814;
reg stageB_request_wr;
reg [1:0] stageB_request_size;
reg stageB_request_totalyConsistent;
reg stageB_mmuRspFreeze;
wire when_DataCache_l816;
reg [31:0] stageB_mmuRsp_physicalAddress;
reg stageB_mmuRsp_isIoAccess;
reg stageB_mmuRsp_isPaging;
reg stageB_mmuRsp_allowRead;
reg stageB_mmuRsp_allowWrite;
reg stageB_mmuRsp_allowExecute;
reg stageB_mmuRsp_exception;
reg stageB_mmuRsp_refilling;
reg stageB_mmuRsp_bypassTranslation;
wire when_DataCache_l813;
reg stageB_tagsReadRsp_0_valid;
reg stageB_tagsReadRsp_0_error;
reg [19:0] stageB_tagsReadRsp_0_address;
wire when_DataCache_l813_1;
reg [31:0] stageB_dataReadRsp_0;
wire when_DataCache_l812;
reg [0:0] stageB_wayInvalidate;
wire stageB_consistancyHazard;
wire when_DataCache_l812_1;
reg [0:0] stageB_dataColisions;
wire when_DataCache_l812_2;
reg stageB_unaligned;
wire when_DataCache_l812_3;
reg [0:0] stageB_waysHitsBeforeInvalidate;
wire [0:0] stageB_waysHits;
wire stageB_waysHit;
wire [31:0] stageB_dataMux;
wire when_DataCache_l812_4;
reg [3:0] stageB_mask;
reg stageB_loaderValid;
wire [31:0] stageB_ioMemRspMuxed;
reg stageB_flusher_waitDone;
wire stageB_flusher_hold;
reg [7:0] stageB_flusher_counter;
wire when_DataCache_l842;
wire when_DataCache_l848;
reg stageB_flusher_start;
wire stageB_isAmo;
wire stageB_isAmoCached;
wire stageB_isExternalLsrc;
wire stageB_isExternalAmo;
wire [31:0] stageB_requestDataBypass;
reg stageB_cpuWriteToCache;
wire when_DataCache_l911;
wire stageB_badPermissions;
wire stageB_loadStoreFault;
wire stageB_bypassCache;
wire when_DataCache_l980;
wire when_DataCache_l989;
wire when_DataCache_l994;
wire when_DataCache_l1005;
wire when_DataCache_l1017;
wire when_DataCache_l976;
wire when_DataCache_l1051;
wire when_DataCache_l1060;
reg loader_valid;
reg loader_counter_willIncrement;
wire loader_counter_willClear;
reg [2:0] loader_counter_valueNext;
reg [2:0] loader_counter_value;
wire loader_counter_willOverflowIfInc;
wire loader_counter_willOverflow;
reg [0:0] loader_waysAllocator;
reg loader_error;
wire loader_kill;
reg loader_killReg;
wire when_DataCache_l1075;
wire loader_done;
wire when_DataCache_l1103;
reg loader_valid_regNext;
wire when_DataCache_l1107;
wire when_DataCache_l1110;
(* ram_style = "block" *) reg [21:0] ways_0_tags [0:127];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023];
reg [7:0] _zz_ways_0_datasymbol_read;
reg [7:0] _zz_ways_0_datasymbol_read_1;
reg [7:0] _zz_ways_0_datasymbol_read_2;
reg [7:0] _zz_ways_0_datasymbol_read_3;
assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0);
assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0);
assign _zz_when = 1'b1;
assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement;
assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1};
assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]};
assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}};
always @(posedge clk) begin
if(_zz_ways_0_tagsReadRsp_valid) begin
_zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(*) begin
_zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read};
end
always @(posedge clk) begin
if(_zz_ways_0_dataReadRspMem) begin
_zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload];
end
end
always @(posedge clk) begin
if(dataWriteCmd_payload_mask[0] && _zz_1) begin
ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0];
end
if(dataWriteCmd_payload_mask[1] && _zz_1) begin
ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8];
end
if(dataWriteCmd_payload_mask[2] && _zz_1) begin
ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16];
end
if(dataWriteCmd_payload_mask[3] && _zz_1) begin
ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(when_DataCache_l637) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(when_DataCache_l634) begin
_zz_2 = 1'b1;
end
end
assign haltCpu = 1'b0;
assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck));
assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0;
assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0];
assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1];
assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2];
assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck));
assign ways_0_dataReadRspMem = _zz_ways_0_data_port0;
assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0];
assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]);
assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]);
always @(*) begin
tagsReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
tagsReadCmd_valid = 1'b1;
end
end
always @(*) begin
tagsReadCmd_payload = 7'bxxxxxxx;
if(when_DataCache_l656) begin
tagsReadCmd_payload = io_cpu_execute_address[11 : 5];
end
end
always @(*) begin
dataReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
dataReadCmd_valid = 1'b1;
end
end
always @(*) begin
dataReadCmd_payload = 10'bxxxxxxxxxx;
if(when_DataCache_l656) begin
dataReadCmd_payload = io_cpu_execute_address[11 : 2];
end
end
always @(*) begin
tagsWriteCmd_valid = 1'b0;
if(when_DataCache_l842) begin
tagsWriteCmd_valid = 1'b1;
end
if(when_DataCache_l1051) begin
tagsWriteCmd_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_valid = 1'b1;
end
end
always @(*) begin
tagsWriteCmd_payload_way = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_way = 1'b1;
end
if(loader_done) begin
tagsWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
tagsWriteCmd_payload_address = 7'bxxxxxxx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_address = stageB_flusher_counter[6:0];
end
if(loader_done) begin
tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5];
end
end
always @(*) begin
tagsWriteCmd_payload_data_valid = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_data_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg));
end
end
always @(*) begin
tagsWriteCmd_payload_data_error = 1'bx;
if(loader_done) begin
tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error));
end
end
always @(*) begin
tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx;
if(loader_done) begin
tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12];
end
end
always @(*) begin
dataWriteCmd_valid = 1'b0;
if(stageB_cpuWriteToCache) begin
if(when_DataCache_l911) begin
dataWriteCmd_valid = 1'b1;
end
end
if(when_DataCache_l1051) begin
dataWriteCmd_valid = 1'b0;
end
if(when_DataCache_l1075) begin
dataWriteCmd_valid = 1'b1;
end
end
always @(*) begin
dataWriteCmd_payload_way = 1'bx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_way = stageB_waysHits;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
dataWriteCmd_payload_address = 10'bxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2];
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value};
end
end
always @(*) begin
dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_data = io_mem_rsp_payload_data;
end
end
always @(*) begin
dataWriteCmd_payload_mask = 4'bxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_mask = 4'b0000;
if(_zz_when[0]) begin
dataWriteCmd_payload_mask[3 : 0] = stageB_mask;
end
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_mask = 4'b1111;
end
end
assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck));
always @(*) begin
io_cpu_execute_haltIt = 1'b0;
if(when_DataCache_l842) begin
io_cpu_execute_haltIt = 1'b1;
end
end
assign rspSync = 1'b1;
assign rspLast = 1'b1;
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck);
always @(*) begin
_zz_stage0_mask = 4'bxxxx;
case(io_cpu_execute_args_size)
2'b00 : begin
_zz_stage0_mask = 4'b0001;
end
2'b01 : begin
_zz_stage0_mask = 4'b0011;
end
2'b10 : begin
_zz_stage0_mask = 4'b1111;
end
default : begin
end
endcase
end
assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]);
assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stage0_wayInvalidate = 1'b0;
assign stage0_isAmo = 1'b0;
assign when_DataCache_l763 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck);
assign io_cpu_memory_isWrite = stageA_request_wr;
assign stageA_isAmo = 1'b0;
assign stageA_isLrsc = 1'b0;
assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid);
assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck);
assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions);
assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_mmuRspFreeze = 1'b0;
if(when_DataCache_l1110) begin
stageB_mmuRspFreeze = 1'b1;
end
end
assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze));
assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck);
assign stageB_consistancyHazard = 1'b0;
assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck);
assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate));
assign stageB_waysHit = (stageB_waysHits != 1'b0);
assign stageB_dataMux = stageB_dataReadRsp_0;
assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_loaderValid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
if(io_mem_cmd_ready) begin
stageB_loaderValid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
stageB_loaderValid = 1'b0;
end
end
assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0];
always @(*) begin
io_cpu_writeBack_haltIt = 1'b1;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
if(when_DataCache_l980) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end else begin
if(when_DataCache_l989) begin
if(when_DataCache_l994) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
assign stageB_flusher_hold = 1'b0;
assign when_DataCache_l842 = (! stageB_flusher_counter[7]);
assign when_DataCache_l848 = (! stageB_flusher_hold);
assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]);
assign stageB_isAmo = 1'b0;
assign stageB_isAmoCached = 1'b0;
assign stageB_isExternalLsrc = 1'b0;
assign stageB_isExternalAmo = 1'b0;
assign stageB_requestDataBypass = io_cpu_writeBack_storeData;
always @(*) begin
stageB_cpuWriteToCache = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
stageB_cpuWriteToCache = 1'b1;
end
end
end
end
end
assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit);
assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)));
assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions));
always @(*) begin
io_cpu_redo = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
if(when_DataCache_l1005) begin
io_cpu_redo = 1'b1;
end
end
end
end
end
if(when_DataCache_l1060) begin
io_cpu_redo = 1'b1;
end
if(when_DataCache_l1107) begin
io_cpu_redo = 1'b1;
end
end
always @(*) begin
io_cpu_writeBack_accessError = 1'b0;
if(stageB_bypassCache) begin
io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error);
end else begin
io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging)));
end
end
assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging);
assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned);
assign io_cpu_writeBack_isWrite = stageB_request_wr;
always @(*) begin
io_mem_cmd_valid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
io_mem_cmd_valid = (! memCmdSent);
end else begin
if(when_DataCache_l989) begin
if(stageB_request_wr) begin
io_mem_cmd_valid = 1'b1;
end
end else begin
if(when_DataCache_l1017) begin
io_mem_cmd_valid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_mem_cmd_valid = 1'b0;
end
end
always @(*) begin
io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_address[4 : 0] = 5'h0;
end
end
end
end
end
assign io_mem_cmd_payload_last = 1'b1;
always @(*) begin
io_mem_cmd_payload_wr = stageB_request_wr;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_wr = 1'b0;
end
end
end
end
end
assign io_mem_cmd_payload_mask = stageB_mask;
assign io_mem_cmd_payload_data = stageB_requestDataBypass;
assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess;
always @(*) begin
io_mem_cmd_payload_size = {1'd0, stageB_request_size};
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_size = 3'b101;
end
end
end
end
end
assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo);
assign io_cpu_writeBack_keepMemRspData = 1'b0;
assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready);
assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached)));
assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready);
assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0));
assign when_DataCache_l1017 = (! memCmdSent);
assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc);
always @(*) begin
if(stageB_bypassCache) begin
io_cpu_writeBack_data = stageB_ioMemRspMuxed;
end else begin
io_cpu_writeBack_data = stageB_dataMux;
end
end
assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess);
assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard));
always @(*) begin
loader_counter_willIncrement = 1'b0;
if(when_DataCache_l1075) begin
loader_counter_willIncrement = 1'b1;
end
end
assign loader_counter_willClear = 1'b0;
assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111);
assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement);
always @(*) begin
loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext);
if(loader_counter_willClear) begin
loader_counter_valueNext = 3'b000;
end
end
assign loader_kill = 1'b0;
assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast);
assign loader_done = loader_counter_willOverflow;
assign when_DataCache_l1103 = (! loader_valid);
assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext));
assign io_cpu_execute_refilling = loader_valid;
assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid);
always @(posedge clk) begin
tagsWriteLastCmd_valid <= tagsWriteCmd_valid;
tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way;
tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address;
tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid;
tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error;
tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address;
if(when_DataCache_l763) begin
stageA_request_wr <= io_cpu_execute_args_wr;
stageA_request_size <= io_cpu_execute_args_size;
stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent;
end
if(when_DataCache_l763_1) begin
stageA_mask <= stage0_mask;
end
if(when_DataCache_l763_2) begin
stageA_wayInvalidate <= stage0_wayInvalidate;
end
if(when_DataCache_l763_3) begin
stage0_dataColisions_regNextWhen <= stage0_dataColisions;
end
if(when_DataCache_l814) begin
stageB_request_wr <= stageA_request_wr;
stageB_request_size <= stageA_request_size;
stageB_request_totalyConsistent <= stageA_request_totalyConsistent;
end
if(when_DataCache_l816) begin
stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress;
stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess;
stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging;
stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead;
stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite;
stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute;
stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception;
stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling;
stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation;
end
if(when_DataCache_l813) begin
stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid;
stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error;
stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address;
end
if(when_DataCache_l813_1) begin
stageB_dataReadRsp_0 <= ways_0_dataReadRsp;
end
if(when_DataCache_l812) begin
stageB_wayInvalidate <= stageA_wayInvalidate;
end
if(when_DataCache_l812_1) begin
stageB_dataColisions <= stageA_dataColisions;
end
if(when_DataCache_l812_2) begin
stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00);
end
if(when_DataCache_l812_3) begin
stageB_waysHitsBeforeInvalidate <= stageA_wayHits;
end
if(when_DataCache_l812_4) begin
stageB_mask <= stageA_mask;
end
loader_valid_regNext <= loader_valid;
end
always @(posedge clk) begin
if(reset) begin
memCmdSent <= 1'b0;
stageB_flusher_waitDone <= 1'b0;
stageB_flusher_counter <= 8'h0;
stageB_flusher_start <= 1'b1;
loader_valid <= 1'b0;
loader_counter_value <= 3'b000;
loader_waysAllocator <= 1'b1;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end else begin
if(io_mem_cmd_fire) begin
memCmdSent <= 1'b1;
end
if(when_DataCache_l678) begin
memCmdSent <= 1'b0;
end
if(io_cpu_flush_ready) begin
stageB_flusher_waitDone <= 1'b0;
end
if(when_DataCache_l842) begin
if(when_DataCache_l848) begin
stageB_flusher_counter <= (stageB_flusher_counter + 8'h01);
end
end
stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo));
if(stageB_flusher_start) begin
stageB_flusher_waitDone <= 1'b1;
stageB_flusher_counter <= 8'h0;
end
`ifndef SYNTHESIS
`ifdef FORMAL
assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck)));
`else
if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin
$display("ERROR writeBack stuck by another plugin is not allowed");
end
`endif
`endif
if(stageB_loaderValid) begin
loader_valid <= 1'b1;
end
loader_counter_value <= loader_counter_valueNext;
if(loader_kill) begin
loader_killReg <= 1'b1;
end
if(when_DataCache_l1075) begin
loader_error <= (loader_error || io_mem_rsp_payload_error);
end
if(loader_done) begin
loader_valid <= 1'b0;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end
if(when_DataCache_l1103) begin
loader_waysAllocator <= _zz_loader_waysAllocator[0:0];
end
end
end
endmodule
module InstructionCache (
input io_flush,
input io_cpu_prefetch_isValid,
output reg io_cpu_prefetch_haltIt,
input [31:0] io_cpu_prefetch_pc,
input io_cpu_fetch_isValid,
input io_cpu_fetch_isStuck,
input io_cpu_fetch_isRemoved,
input [31:0] io_cpu_fetch_pc,
output [31:0] io_cpu_fetch_data,
input [31:0] io_cpu_fetch_mmuRsp_physicalAddress,
input io_cpu_fetch_mmuRsp_isIoAccess,
input io_cpu_fetch_mmuRsp_isPaging,
input io_cpu_fetch_mmuRsp_allowRead,
input io_cpu_fetch_mmuRsp_allowWrite,
input io_cpu_fetch_mmuRsp_allowExecute,
input io_cpu_fetch_mmuRsp_exception,
input io_cpu_fetch_mmuRsp_refilling,
input io_cpu_fetch_mmuRsp_bypassTranslation,
output [31:0] io_cpu_fetch_physicalAddress,
input io_cpu_decode_isValid,
input io_cpu_decode_isStuck,
input [31:0] io_cpu_decode_pc,
output [31:0] io_cpu_decode_physicalAddress,
output [31:0] io_cpu_decode_data,
output io_cpu_decode_cacheMiss,
output io_cpu_decode_error,
output io_cpu_decode_mmuRefilling,
output io_cpu_decode_mmuException,
input io_cpu_decode_isUser,
input io_cpu_fill_valid,
input [31:0] io_cpu_fill_payload,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [2:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input [2:0] _zz_when_Fetcher_l398,
input [31:0] _zz_io_cpu_fetch_data_regNextWhen,
input clk,
input reset
);
reg [31:0] _zz_banks_0_port1;
reg [22:0] _zz_ways_0_tags_port1;
wire [22:0] _zz_ways_0_tags_port;
reg _zz_1;
reg _zz_2;
reg lineLoader_fire;
reg lineLoader_valid;
(* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ;
reg lineLoader_hadError;
reg lineLoader_flushPending;
reg [6:0] lineLoader_flushCounter;
wire when_InstructionCache_l338;
reg _zz_when_InstructionCache_l342;
wire when_InstructionCache_l342;
wire when_InstructionCache_l351;
reg lineLoader_cmdSent;
wire io_mem_cmd_fire;
wire when_Utils_l357;
reg lineLoader_wayToAllocate_willIncrement;
wire lineLoader_wayToAllocate_willClear;
wire lineLoader_wayToAllocate_willOverflowIfInc;
wire lineLoader_wayToAllocate_willOverflow;
(* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ;
wire lineLoader_write_tag_0_valid;
wire [5:0] lineLoader_write_tag_0_payload_address;
wire lineLoader_write_tag_0_payload_data_valid;
wire lineLoader_write_tag_0_payload_data_error;
wire [20:0] lineLoader_write_tag_0_payload_data_address;
wire lineLoader_write_data_0_valid;
wire [8:0] lineLoader_write_data_0_payload_address;
wire [31:0] lineLoader_write_data_0_payload_data;
wire when_InstructionCache_l401;
wire [8:0] _zz_fetchStage_read_banksValue_0_dataMem;
wire _zz_fetchStage_read_banksValue_0_dataMem_1;
wire [31:0] fetchStage_read_banksValue_0_dataMem;
wire [31:0] fetchStage_read_banksValue_0_data;
wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid;
wire _zz_fetchStage_read_waysValues_0_tag_valid_1;
wire fetchStage_read_waysValues_0_tag_valid;
wire fetchStage_read_waysValues_0_tag_error;
wire [20:0] fetchStage_read_waysValues_0_tag_address;
wire [22:0] _zz_fetchStage_read_waysValues_0_tag_valid_2;
wire fetchStage_hit_hits_0;
wire fetchStage_hit_valid;
wire fetchStage_hit_error;
wire [31:0] fetchStage_hit_data;
wire [31:0] fetchStage_hit_word;
wire when_InstructionCache_l435;
reg [31:0] io_cpu_fetch_data_regNextWhen;
wire when_InstructionCache_l459;
reg [31:0] decodeStage_mmuRsp_physicalAddress;
reg decodeStage_mmuRsp_isIoAccess;
reg decodeStage_mmuRsp_isPaging;
reg decodeStage_mmuRsp_allowRead;
reg decodeStage_mmuRsp_allowWrite;
reg decodeStage_mmuRsp_allowExecute;
reg decodeStage_mmuRsp_exception;
reg decodeStage_mmuRsp_refilling;
reg decodeStage_mmuRsp_bypassTranslation;
wire when_InstructionCache_l459_1;
reg decodeStage_hit_valid;
wire when_InstructionCache_l459_2;
reg decodeStage_hit_error;
wire when_Fetcher_l398;
(* ram_style = "block" *) reg [31:0] banks_0 [0:511];
(* ram_style = "block" *) reg [22:0] ways_0_tags [0:63];
assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
always @(posedge clk) begin
if(_zz_1) begin
banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin
_zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin
_zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(lineLoader_write_data_0_valid) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(lineLoader_write_tag_0_valid) begin
_zz_2 = 1'b1;
end
end
always @(*) begin
lineLoader_fire = 1'b0;
if(io_mem_rsp_valid) begin
if(when_InstructionCache_l401) begin
lineLoader_fire = 1'b1;
end
end
end
always @(*) begin
io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
if(when_InstructionCache_l338) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(when_InstructionCache_l342) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(io_flush) begin
io_cpu_prefetch_haltIt = 1'b1;
end
end
assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]);
assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342);
assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0};
assign io_mem_cmd_payload_size = 3'b101;
assign when_Utils_l357 = (! lineLoader_valid);
always @(*) begin
lineLoader_wayToAllocate_willIncrement = 1'b0;
if(when_Utils_l357) begin
lineLoader_wayToAllocate_willIncrement = 1'b1;
end
end
assign lineLoader_wayToAllocate_willClear = 1'b0;
assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6]));
assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]);
assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6];
assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11];
assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1);
assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex};
assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111);
assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[10 : 2];
assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck);
assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1;
assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0];
assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[10 : 5];
assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck);
assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1;
assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0];
assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1];
assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[22 : 2];
assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11]));
assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0);
assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
assign fetchStage_hit_data = fetchStage_read_banksValue_0_data;
assign fetchStage_hit_word = fetchStage_hit_data;
assign io_cpu_fetch_data = fetchStage_hit_word;
assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen;
assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress;
assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))));
assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling;
assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)));
assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
assign when_Fetcher_l398 = (_zz_when_Fetcher_l398 != 3'b000);
always @(posedge clk) begin
if(reset) begin
lineLoader_valid <= 1'b0;
lineLoader_hadError <= 1'b0;
lineLoader_flushPending <= 1'b1;
lineLoader_cmdSent <= 1'b0;
lineLoader_wordIndex <= 3'b000;
end else begin
if(lineLoader_fire) begin
lineLoader_valid <= 1'b0;
end
if(lineLoader_fire) begin
lineLoader_hadError <= 1'b0;
end
if(io_cpu_fill_valid) begin
lineLoader_valid <= 1'b1;
end
if(io_flush) begin
lineLoader_flushPending <= 1'b1;
end
if(when_InstructionCache_l351) begin
lineLoader_flushPending <= 1'b0;
end
if(io_mem_cmd_fire) begin
lineLoader_cmdSent <= 1'b1;
end
if(lineLoader_fire) begin
lineLoader_cmdSent <= 1'b0;
end
if(io_mem_rsp_valid) begin
lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001);
if(io_mem_rsp_payload_error) begin
lineLoader_hadError <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if(io_cpu_fill_valid) begin
lineLoader_address <= io_cpu_fill_payload;
end
if(when_InstructionCache_l338) begin
lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01);
end
_zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6];
if(when_InstructionCache_l351) begin
lineLoader_flushCounter <= 7'h0;
end
if(when_InstructionCache_l435) begin
io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data;
end
if(when_InstructionCache_l459) begin
decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress;
decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess;
decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging;
decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead;
decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite;
decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute;
decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception;
decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling;
decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation;
end
if(when_InstructionCache_l459_1) begin
decodeStage_hit_valid <= fetchStage_hit_valid;
end
if(when_InstructionCache_l459_2) begin
decodeStage_hit_error <= fetchStage_hit_error;
end
if(when_Fetcher_l398) begin
io_cpu_fetch_data_regNextWhen <= _zz_io_cpu_fetch_data_regNextWhen;
end
end
endmodule
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module system_processing_system7_0_0 (
SDIO0_WP,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_5_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100.0),
.C_FCLK_CLK1_FREQ(50.0),
.C_FCLK_CLK2_FREQ(50.0),
.C_FCLK_CLK3_FREQ(50.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/*
*--------------------------------------------------------------
* This module converts a counter value N into a reset value
* for an 8-bit LFSR. The count is initialized by "reset" high
* or "start" transition high. When the count is valid, it is
* latched into "dp" and the signal "done" is raised to indicate
* a valid new value of "dp".
*--------------------------------------------------------------
*/
module map9v3(clock, reset, start, N, dp, done, counter, sr);
input clock;
input start; // run at rising edge of start
input reset; // high is reset case ( run after reset)
input [8:0] N; // the number to divide by
output [8:0] dp; // these outputs drive an LFSR counter
output done;
output [7:0] counter;
output [7:0] sr;
reg [8:0] dp;
reg [7:0] sr;
reg [7:0] counter;
reg [1:0] startbuf;
reg done;
reg [2:0] state;
parameter INIT = 3'b000;
parameter RUN = 3'b001;
parameter ALMOSTDONE = 3'b010;
parameter DONE = 3'b011;
parameter WAIT = 3'b100;
always @(posedge clock or posedge reset) begin
if (reset == 1) begin
dp <= 9'b0;
sr <= 8'b0;
counter <= 8'b0;
startbuf <= 2'b00;
done <= 0;
state <= INIT;
end else begin
if (state == INIT) begin
counter <= 255 - N[8:1] + 3;
sr <= 8'b0;
done <= 0;
state <= RUN;
end else if (state == RUN) begin
sr[7] <= sr[6];
sr[6] <= sr[5];
sr[5] <= sr[4];
sr[4] <= sr[3];
sr[3] <= sr[2];
sr[2] <= sr[1];
sr[1] <= sr[0];
sr[0] <= ~(sr[7] ^ sr[5] ^ sr[4] ^ sr[3]);
counter <= counter - 1;
if (counter == 0) begin
state <= ALMOSTDONE;
end
end else if (state == ALMOSTDONE) begin
dp[0] <= N[0];
dp[8:1] <= sr[7:0];
state <= DONE;
end else if (state == DONE) begin
done <= 1;
state <= WAIT;
end else if (state == WAIT) begin
if (startbuf == 2'b01) begin
state <= INIT;
end
end
startbuf <= {startbuf[0], start};
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:04:44 11/05/2014
// Design Name: plus_data_flow
// Module Name: /home/varun/Desktop/eld/ass9/fpplusdata/plus_data_flow_fixture.v
// Project Name: fpplusdata
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: plus_data_flow
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module plus_data_flow_fixture;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;
// Outputs
wire [3:0] q;
wire cout;
// Instantiate the Unit Under Test (UUT)
plus_data_flow uut (
.q(q),
.cout(cout),
.a(a),
.b(b),
.cin(cin)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
/******************************************************************************
* File Name : jhash_in.v
* Version : 0.1
* Date : 2008 08 29
* Description: jash in module
* Dependencies:
*
*
* Company: Beijing Soul
*
* BUG:
*
*****************************************************************************/
module jhash_in(/*AUTOARG*/
// Outputs
m_src_getn, stream_data0, stream_data1, stream_data2,
stream_valid, stream_done, stream_left,
// Inputs
ce, clk, fi, fo_full, m_last, rst, src_empty, stream_ack
);
input ce;
input clk;
input [63:0] fi;
input fo_full;
input m_last;
input rst;
input src_empty;
output m_src_getn;
input stream_ack;
output [31:0] stream_data0,
stream_data1,
stream_data2;
output stream_valid;
output stream_done;
output [1:0] stream_left;
/*AUTOREG*/
reg pull_n;
assign m_src_getn = ce ? ~(pull_n) : 1'bz;
reg [31:0] stream_data0_n,
stream_data1_n,
stream_data2_n;
reg [2:0] state,
state_n;
reg stream_valid_n;
parameter [2:0]
S_IDLE = 3'b100,
S_RUN_01 = 3'b001,
S_RUN_01_N= 3'b101,
S_RUN_10 = 3'b010,
S_RUN_10_N= 3'b110,
S_DONE = 3'b111;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_n;
end
reg [1:0] dstart, dstart_n;
reg [31:0] d0, d1,
d0_n, d1_n;
always @(posedge clk)
begin
d0 <= #1 d0_n;
d1 <= #1 d1_n;
dstart <= #1 dstart_n;
end
always @(/*AS*/ce or d0 or d1 or dstart or fi or m_last
or src_empty or state or stream_ack)
begin
state_n = state;
pull_n = 1'b0;
d0_n = d0;
d1_n = d1;
dstart_n = dstart;
case (state)
S_IDLE: if (~src_empty && ce) begin
d0_n = fi[31:00];
d1_n = fi[63:32];
pull_n = 1'b1;
dstart_n= 2'b10;
state_n = S_RUN_10;
end
S_RUN_10_N: if (m_last)
state_n = S_DONE;
else if (~src_empty) begin
d0_n = fi[31:00];
d1_n = fi[63:32];
pull_n = 1'b1;
dstart_n= 2'b10;
state_n = S_RUN_10;
end
S_RUN_10: if (stream_ack) begin
if (~src_empty && ~m_last) begin
d0_n = fi[63:32];
pull_n = 1'b1;
dstart_n = 2'b01;
state_n = S_RUN_01;
end else
state_n = S_RUN_01_N;
end
S_RUN_01_N: if (m_last)
state_n = S_DONE;
else if (~src_empty) begin
d0_n = fi[63:32];
pull_n = 1'b1;
dstart_n = 2'b01;
state_n = S_RUN_01;
end
S_RUN_01: if (stream_ack) begin
if (~src_empty && ~m_last) begin
state_n = S_RUN_10_N;
pull_n = 1'b1;
end if (m_last)
state_n = S_DONE;
end
S_DONE: ;
endcase
end // always @ (...
assign stream_left = dstart;
assign stream_valid= ~state[2] && ~src_empty;
assign stream_data0= d0;
assign stream_data1= state[1] ? d1 : fi[31:00];
assign stream_data2= state[1] ? fi[31:0]: fi[63:32];
assign stream_done = m_last;
endmodule // jhash |
/*
** -----------------------------------------------------------------------------**
** sdseq333.v
**
** formely part of mcontr333.v
**
** Copyright (C) 2002-2008 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X333
** X333 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
// 05/06/2008 - modified to delay precharge after write (tWR) - there was violation with
// clock period less than 7.5ns
// external commands sync to clk180
module sdseq (clk0, // global clock 75-100MHz (hope to get to 120MHz with Spartan3)
rst, // when active will use mancmd as a source for ras,cas,we,ba,a
xfer, // start block transfer (=stepsEn[2]) - when address is ready
mode, // 0 - 128x1, 1 - 18x9 (will work only in read mode, channnel 2)
wnr,
refr, // start auto refresh (should be delayed same time as read/write)
sa, // block start address
chsel, // channel number (0..3) - used to generate delayed dsel;
param, // dual-purpose parameter. In 256x1 mode specifies (5 LSBs) number of 8-word long groups to r/w (0- all 32),
// actually for all but 0 (when exactly 256 words are xfered) will transfer one word more
// In 18x9 mode specifies bits 13:8 of address increment between lines
mancmd,// always high except 1 cycle long when it sources {ras,cas,we,ba[1:0],a[11:0]}. Works only whe rst is active
// Will use 18 bits from unused descriptor cell , a[11] will be skipped and set to 1'b0????
sfa, // [23:8]), start address of a frame - ugly hack to roll over the last (extra) 4 lines of a frame
// to the beginning of a frame - used in photofinish mode.
rovr, // roll over mode (photofinish, cntrl0[12]==1, last line of tiles)
drun_rd, // enable read data (from SDRAM) to blockRAM buffer
drun_wr, // enable write data (to SDRAM) from blockRAM buffer
prefirstdrun, // 1 cycle ahead of the first drun_rd/drun_wr to be used by bufCntr256 to sample channel enable
dlast, //last cycle of drun active for read, 1 cycle later for write **** for the last cycle in multi-drun accesses !
precmd, // 1 cycle ahead {ras,cas,we} command bits to be registered at the output pads
prea, // 13 bits (including ba) 1 cycle ahead of output A[12:0]
preb, // 2 bits of bank address 1 cycle ahead of output BA[1:0]
next, // get next request from que.
pre2trist, // tristate data outputs (two ahead).
predqt, // tristate DQ outputs (one extra for FF in output buffer)
dmask, // [1:0] - now both the same (even number of words written)
dqs_re, // enable read from DQS i/o-s for phase adjustments (latency 2 from the SDRAM RD command)
dsel); // data buffer select (number of buffer to source SDRAM data in), so it is needed only for WRITE to SDRAM
input clk0;
input rst,xfer,mode,wnr,refr;
input [24:3] sa;
input [ 1:0] chsel;
input [ 5:0] param;
input [17:0] mancmd;
input [24:8] sfa; // start frame address - photofinish hack
input rovr; // roll over mode (photofinish, cntrl0[12]==1, last line of tiles)
output drun_rd;
output drun_wr;
output prefirstdrun;
output dlast;
output [ 2:0] precmd;
output [12:0] prea;
output [ 1:0] preb;
output next;
output pre2trist;
output predqt;
output [ 1:0] dmask;
output dqs_re;
output [ 1:0] dsel;
reg [4:0] left; // full page will be 31, not 32 copunts - first delay will just be longer
reg mode_r;//, wnr_r; //after xfer
reg prefirst,first;
reg [1:0] dsel;
reg [12:0] prea;
reg [ 1:0] preb;
wire [2:0] precmd;
reg [1:0] dmask; // for now both bits are the same
reg next;
reg pre2trist;// made 1 extra early - add FF to the i/op module
reg predqt; // will go through additional FF at falling clk0 in I/O module
reg drun_rd;
reg drun_wr; //3 cycles ahead of data out available inside FPGA (before DDR resyncing)
reg dlast;
reg dqs_re;
// internals
reg [24:3] fullAddr; // full SDRAM address;
reg [24:3] nextAddr; // full SDRAM address for the next 10-word block (in next line)
// reg [24:9] nextPageAddr; // used only for the the second access in mode1
reg [24:10] nextPageAddr; // used only for the the second access in mode1
reg start_m1; // start in mode1 - both first and next lines
reg startf_m1; // start in mode1 - only first line !
reg start_m0r; // start in mode0 - read
reg start_m0w; // start in mode0 - write
// wire pre6prech_m; // 6 cycles ahead of precmd "precharge" mode1, single access or second in dual
reg pre6prech_m; // 6 cycles ahead of precmd "precharge" mode1, single access or second in dual
reg [1:0] pre7prech_m; // 7 cycles ahead of precmd "precharge", [0] - read, [1] - write
wire pre2prech_m; // 2 cycles ahead of precmd "precharge" mode1, single access or second in dual
wire pre2prech_m1d1; // 2 cycles ahead of precmd "precharge" mode1, dual access, first cycle
wire pre2act_m1d2; // 2 cycles ahead of precmd "activate" mode1, dual access, second cycle
wire prenext_m1s; // 1 cycle ahead of possible "next" - mode1, single access - starts from start_m1
wire prenext_m1d; // 1 cycle ahead of possible "next" - mode1, dual access
wire precontinue_m1; // 3 cycles ahead of "activate" of continuation cycle
reg continue_m1; // 2 cycles ahead of "activate" of continuation cycle
wire continue_m0; // 2 cycles ahead of "activate" of continuation cycle
reg possible_dual; // lower bits in full address are all ones - possible two acccesses will be needed in the current line
reg setNextAddr; // update nextAddr
reg decLeft;
wire prenext_m0r;
wire prenext_m0w1;
wire prenext_m0;
wire pre2refr;
wire prenext_refr;
reg prerefr;
reg preact;
reg preprech;
reg preread;
reg prewrite;
reg prerw; // for address multiplexor
reg pre1act_m1d2;
wire pre2read;
wire pre2write;
reg predrun_wr;
reg pre4drun_rd;
wire predrun_rd;
wire pre4drun_rd_abort; // in second access of dual-access, where precharge command is later (to meet activate-to-precharge time)
wire predrun_wr_abort; // write nneeds extra NOP befrore precharge
wire predmask;
wire predlast_rd;
wire predlast_wr;
wire predqs_re;
reg repeat_r;
wire repeat_r_end;
reg repeat_w;
wire pre2read_next8;
wire pre2write_next8;
reg prefirstdrun; // to sample cs in bufCntr256
wire pre2firstdrun_rd;
reg rollover; //photofinish hack
reg prenext_wr; // same timing as it was "next" earlier
wire pre_next_old=(left==5'h1) && (prenext_m1s || prenext_m1d || prenext_m0);
always @ (negedge clk0)
if (rst) begin
mode_r <= 1'b0;
end else if (xfer) begin
mode_r <= mode;
end
always @ (negedge clk0) begin
rollover <= (left[4:0]==5'h4) && rovr;
if (first) fullAddr[ 9:3] <= sa[ 9:3];
else if (pre2act_m1d2) fullAddr[ 9:3] <= 7'h0;
else if (prerw) fullAddr[ 9:3] <= fullAddr[ 9:3]+1;
else if (continue_m1) fullAddr[ 9:3] <= {rollover?sfa[9:8]:nextAddr[9:8],nextAddr[ 7:3]}; // stored from sa[7:3]
if (first) fullAddr[24:10] <= sa[24:10];
else if (continue_m1) fullAddr[24:10] <= rollover?sfa[24:10]:nextAddr[24:10];
else if (pre2act_m1d2) fullAddr[24:10] <= nextPageAddr[24:10];
if (pre2prech_m1d1) nextPageAddr[24:10] <= fullAddr[24:10]+1;
if (rst) possible_dual <= 0;
else if (first) possible_dual <= (sa[ 7:3] == 5'h1f);
start_m1 <= !rst && ((first && mode_r) || continue_m1);
startf_m1 <= !rst && (first && mode_r);
start_m0r <= first && !mode_r && !wnr;
start_m0w <= first && !mode_r && wnr;
setNextAddr <= start_m1;
if (setNextAddr) nextAddr[24:8] <= fullAddr[24:8]+param[5:0]; // 2 cycles after fullAddr was set
if (first) nextAddr[ 7:3] <= sa [7:3];
prenext_wr <= drun_wr && pre_next_old;
next <= prenext_refr || prenext_wr || (!drun_wr && pre_next_old); // add m0 and refr here too
decLeft <= (prenext_m1s || prenext_m1d || prenext_m0); // add m0 and refr here too
if (first) left[4:0] <= (mode)? 5'h14:((param[4:0]==5'b0)?5'h1f:param[4:0]);
else if (decLeft) left[4:0] <= left[4:0] -1;
end
// aHa! Here was the bug!!
// MSRL16_1 i_prenext_m1s (.Q(prenext_m1s), .A(4'h0), .CLK(clk0), .D(start_m1 && ~(possible_dual && fullAddr[8])));
MSRL16_1 i_prenext_m1s (.Q(prenext_m1s), .A(4'h0), .CLK(clk0), .D(start_m1 && ~(possible_dual && &fullAddr[9:8])));
// modified to match tWR (delay precharge after write)
// MSRL16_1 i_pre6prech_m (.Q(pre6prech_m), .A(4'h1), .CLK(clk0), .D(prenext_m1s ||
// prenext_m1d ||
// ((left==5'h1) && prenext_m0)));
MSRL16_1 i_pre2prech_m (.Q(pre2prech_m), .A(4'h3), .CLK(clk0), .D(pre6prech_m));
// MSRL16_1 i_pre2prech_m1d1 (.Q(pre2prech_m1d1), .A(4'h5), .CLK(clk0), .D(start_m1 && (possible_dual && fullAddr[8])));
MSRL16_1 i_pre2prech_m1d1 (.Q(pre2prech_m1d1), .A(4'h5), .CLK(clk0), .D(start_m1 && (possible_dual && &fullAddr[9:8])));
MSRL16_1 i_prenext_m1d (.Q(prenext_m1d), .A(4'h1), .CLK(clk0), .D(pre2prech_m1d1));
MSRL16_1 i_pre2act_m1d2 (.Q(pre2act_m1d2), .A(4'h0), .CLK(clk0), .D(prenext_m1d));
MSRL16_1 i_precontinue_m1 (.Q(precontinue_m1), .A(4'h1), .CLK(clk0), .D((left!=5'h0) && pre2prech_m));
MSRL16_1 i_prenext_m0r (.Q(prenext_m0r), .A((param[4:0]==5'b0)?4'h3:4'h0), .CLK(clk0), .D(start_m0r));
MSRL16_1 i_prenext_m0w1 (.Q(prenext_m0w1), .A((param[4:0]==5'b0)?4'h6:4'h3), .CLK(clk0), .D(start_m0w));
assign prenext_m0=prenext_m0r || prenext_m0w1 || continue_m0;
MSRL16_1 i_continue_m0 (.Q(continue_m0), .A(4'h3), .CLK(clk0), .D(!rst && (left!=5'h1) && prenext_m0));
MSRL16_1 i_pre2refr (.Q(pre2refr), .A(4'h6), .CLK(clk0), .D(refr));
MSRL16_1 i_prenext_refr (.Q(prenext_refr), .A(4'h2), .CLK(clk0), .D(pre2refr));
// secondary signals (just delays from the primary ones)
MSRL16_1 i_pre2read (.Q(pre2read), .A(4'h1), .CLK(clk0), .D(start_m0r || start_m1 || pre1act_m1d2));
MSRL16_1 i_pre2write (.Q(pre2write), .A(4'h1), .CLK(clk0), .D(start_m0w));
MSRL16_1 i_predrun_rd (.Q(predrun_rd), .A(4'h2), .CLK(clk0), .D(pre4drun_rd));
MSRL16_1 i_pre4drun_rd_abort (.Q(pre4drun_rd_abort), .A(4'h4), .CLK(clk0), .D(pre2act_m1d2));
MSRL16_1 i_predrun_wr_abort (.Q(predrun_wr_abort), .A(4'h0), .CLK(clk0), .D((prenext_m0w1 || continue_m0) && (left==5'h1)));
MSRL16_1 i_predlast_rd (.Q(predlast_rd), .A(4'h2), .CLK(clk0), .D(pre4drun_rd && (preprech || pre4drun_rd_abort)));
MSRL16_1 i_predlast_wr (.Q(predlast_wr), .A(4'h0), .CLK(clk0), .D(predrun_wr && predrun_wr_abort));
MSRL16_1 i_predmask (.Q(predmask), .A(4'h2), .CLK(clk0), .D(!predrun_wr));
MSRL16_1 i_predqs_re (.Q(predqs_re), .A(4'h1), .CLK(clk0), .D(pre4drun_rd));
MSRL16_1 i_pre2read_next8 (.Q(pre2read_next8), .A(4'h2), .CLK(clk0), .D(preread));
MSRL16_1 i_pre2write_next8 (.Q(pre2write_next8), .A(4'h2), .CLK(clk0), .D(prewrite));
assign repeat_r_end= pre2prech_m || pre2prech_m1d1; // will work for read - add for write
MSRL16_1 i_pre2firstdrun_rd (.Q(pre2firstdrun_rd), .A(4'h5), .CLK(clk0), .D(start_m0r || startf_m1));
always @ (negedge clk0) begin
pre7prech_m[1:0] <= {pre7prech_m[0],prenext_m1s ||
prenext_m1d ||
(prenext_m0 && (left==5'h1))};
pre6prech_m <= drun_wr?pre7prech_m[1]:pre7prech_m[0];
prefirstdrun <= start_m0w || pre2firstdrun_rd;
continue_m1 <= precontinue_m1;
repeat_r <= !rst && !repeat_r_end && (repeat_r || first || continue_m1);
repeat_w <= !rst && !pre6prech_m && (repeat_w || first);
prefirst <= xfer;
first <= prefirst;
pre1act_m1d2 <= !rst && pre2act_m1d2;
prerefr <= !rst && pre2refr;
preact <= !rst && (first || continue_m1 || pre2act_m1d2);
preprech <= !rst && (pre2prech_m || pre2prech_m1d1);
preread <= !rst && ~(pre2prech_m || pre2prech_m1d1) && (pre2read || (pre2read_next8 && repeat_r));
prewrite <= !rst && (pre2write || (pre2write_next8 && repeat_w));
prerw <= (~(pre2prech_m || pre2prech_m1d1) && (pre2read || (pre2read_next8 && repeat_r))) ||
(pre2write || (pre2write_next8 && repeat_w));
// prea[12:0] <= rst? mancmd[12:0] : (prerw? {4'b0,fullAddr[8:3],3'b0} :(first?sa[21:9] :fullAddr[21:9]));
// preb[ 1:0] <= rst? mancmd[14:13] : (first?sa[23:22]:fullAddr[23:22]);
prea[12:0] <= rst?
mancmd[12:0] :
(prerw?
{3'b0,fullAddr[9:3],3'b0} :
(first?
sa[22:10] :
fullAddr[22:10]));
preb[ 1:0] <= rst?
mancmd[14:13] :
(first?
sa[24:23]:
fullAddr[24:23]);
if (start_m0w) dsel[1:0] <= chsel[1:0];
predrun_wr <= start_m0w || (!rst && predrun_wr && ~predrun_wr_abort);
pre4drun_rd <= preread || (!rst && pre4drun_rd && ~(preprech || pre4drun_rd_abort));
drun_rd <= predrun_rd;
drun_wr <= predrun_wr;
dlast <= (left==5'h0 ) && (predlast_rd || predlast_wr) && !pre1act_m1d2; // !pre1act_m1d2 removes first pulse in dual access lines
dmask <={predmask,predmask};
pre2trist<=rst || preprech || (pre2trist && ~prewrite);
predqt <=rst || (pre2trist && ~prewrite);
dqs_re <=predqs_re;
end
// Use FF for cas, ras, we for correct simulation
FD_1 #(.INIT(1'b1)) i_precmd_0 (.D(mancmd[15] && ~(prewrite | preprech)), .C(clk0),.Q(precmd[0])); //WE
FD_1 #(.INIT(1'b1)) i_precmd_1 (.D(mancmd[16] && ~(prerefr | preread | prewrite)),.C(clk0),.Q(precmd[1])); //CAS
FD_1 #(.INIT(1'b1)) i_precmd_2 (.D(mancmd[17] && ~(prerefr | preact | preprech)), .C(clk0),.Q(precmd[2])); //RAS
endmodule
|
//
// Author: Steffen Reith ([email protected])
//
// Creation Date: Fri Feb 15 20:53:58 CET 2019
// Module Name: Board_IceBreaker - Behavioral
// Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL
//
//
module IceBreaker (nreset,
clk12Mhz,
extInt,
leds,
pwmLeds,
pButtons,
pmodA,
rx,
tx,
uartLed);
// Input ports
input nreset;
input clk12Mhz;
input [0:0] extInt;
input [1:0] pButtons;
input rx;
// Output ports
output [3:0] leds;
output [0:0] pwmLeds;
output tx;
output uartLed;
// Bidirectional port
inout [7:0] pmodA;
// Clock generation
wire boardClk;
wire boardClkLocked;
// Internal wiring
wire [7:0] pmodA_read;
wire [7:0] pmodA_write;
wire [7:0] pmodA_writeEnable;
// Internal wire for reset
wire reset;
// Instantiate a PLL to make a 18Mhz clock
PLL makeClk (.clkIn (clk12Mhz),
.clkOut (boardClk),
.isLocked (boardClkLocked));
// Instantiate the J1SoC core generated by Spinal
J1Ice core (.reset (reset),
.boardClk (boardClk),
.boardClkLocked (boardClkLocked),
.extInt (extInt),
.leds (leds),
.pwmLeds (pwmLeds),
.pButtons (pButtons),
.pmodA_read (pmodA_read),
.pmodA_write (pmodA_write),
.pmodA_writeEnable (pmodA_writeEnable),
.rx (rx),
.tx (tx),
.uartLed (uartLed));
// Invert the negative reset
assign reset = !nreset;
// Generate the write port and equip it with tristate functionality
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin
// Instantiate the ith tristate buffer
SB_IO #(.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 0)
) iobuf (
.PACKAGE_PIN(pmodA[i]),
.OUTPUT_ENABLE(pmodA_writeEnable[i]),
.D_OUT_0(pmodA_write[i]),
.D_IN_0(pmodA_read[i]));
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:33:08 11/02/2013
// Design Name:
// Module Name: sounds_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sounds_module(input lrck, input reset, input[2:0] sound_code,
output reg[15:0] left_data, output reg[15:0] right_data);
/** Variable para recorrer el arreglo de la data de cada sonido */
reg [2:0] position;
/** Matriz que contiene los datos de un sonido */
parameter [15:0] sample_sound_left [2:0];
parameter [15:0] sample_sound_right [2:0];
initial
begin
/** Position empieza en cero */
position <= 1;
/** Se debe guardar los datos de los sonidos */
sample_sound_left[0] <= 16'd1;
sample_sound_right[0] <= 16'd2;
sample_sound_left[1] <= 16'd3;
sample_sound_right[1] <= 16'd4;
sample_sound_left[2] <= 16'd5;
sample_sound_right[2] <= 16'd6;
end
always @ (negedge lrck)
begin
case(sound_code)
3'b000:
begin
left_data <= sample_sound_left[position];
right_data <= sample_sound_right[position];
end
default:
begin
left_data <= sample_sound_left[position];
right_data <= sample_sound_right[position];
end
endcase
position <= position + 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4B_1_V
`define SKY130_FD_SC_HDLL__NOR4B_1_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4B_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXBP_TB_V
`define SKY130_FD_SC_HS__SDFXBP_TB_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfxbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 SCD = 1'b1;
#160 SCE = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 SCD = 1'b0;
#260 SCE = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SCE = 1'b1;
#380 SCD = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SCE = 1'bx;
#480 SCD = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__sdfxbp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4BB_SYMBOL_V
`define SKY130_FD_SC_LP__NAND4BB_SYMBOL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand4bb (
//# {{data|Data Signals}}
input A_N,
input B_N,
input C ,
input D ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4BB_SYMBOL_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fbkb
#(parameter
ID = 0,
NUM_STAGE = 5,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fadd_3_full_dsp_32 convolve_kernel_ap_fadd_3_full_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
/**
* $Id: red_pitaya_hk.v 961 2014-01-21 11:40:39Z matej.oblak $
*
* @brief Red Pitaya house keeping.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* House keeping module takes care of system identification.
*
*
* This module takes care of system identification via DNA readout at startup and
* ID register which user can define at compile time.
*
* Beside that it is currently also used to test expansion connector and for
* driving LEDs.
*
*/
module red_pitaya_hk #(
parameter DWL = 8, // data width for LED
parameter DWE = 8, // data width for extension
parameter [57-1:0] DNA = 57'h0823456789ABCDE
)(
// system signals
input clk_i , // clock
input rstn_i , // reset - active low
// LED
output reg [DWL-1:0] led_o , // LED output
// global configuration
output reg digital_loop,
// Expansion connector
input [DWE-1:0] exp_p_dat_i, // exp. con. input data
output reg [DWE-1:0] exp_p_dat_o, // exp. con. output data
output reg [DWE-1:0] exp_p_dir_o, // exp. con. 1-output enable
input [DWE-1:0] exp_n_dat_i, //
output reg [DWE-1:0] exp_n_dat_o, //
output reg [DWE-1:0] exp_n_dir_o, //
// System bus
input [ 32-1:0] sys_addr , // bus address
input [ 32-1:0] sys_wdata , // bus write data
input [ 4-1:0] sys_sel , // bus write byte select
input sys_wen , // bus write enable
input sys_ren , // bus read enable
output reg [ 32-1:0] sys_rdata , // bus read data
output reg sys_err , // bus error indicator
output reg sys_ack // bus acknowledge signal
);
//---------------------------------------------------------------------------------
//
// Read device DNA
wire dna_dout ;
reg dna_clk ;
reg dna_read ;
reg dna_shift;
reg [ 9-1: 0] dna_cnt ;
reg [57-1: 0] dna_value;
reg dna_done ;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
dna_clk <= 1'b0;
dna_read <= 1'b0;
dna_shift <= 1'b0;
dna_cnt <= 9'd0;
dna_value <= 57'd0;
dna_done <= 1'b0;
end else begin
if (!dna_done)
dna_cnt <= dna_cnt + 1'd1;
dna_clk <= dna_cnt[2] ;
dna_read <= (dna_cnt < 9'd10);
dna_shift <= (dna_cnt > 9'd18);
if ((dna_cnt[2:0]==3'h0) && !dna_done)
dna_value <= {dna_value[57-2:0], dna_dout};
if (dna_cnt > 9'd465)
dna_done <= 1'b1;
end
// parameter specifies a sample 57-bit DNA value for simulation
DNA_PORT #(.SIM_DNA_VALUE (DNA)) i_DNA (
.DOUT ( dna_dout ), // 1-bit output: DNA output data.
.CLK ( dna_clk ), // 1-bit input: Clock input.
.DIN ( 1'b0 ), // 1-bit input: User data input pin.
.READ ( dna_read ), // 1-bit input: Active high load DNA, active low read input.
.SHIFT ( dna_shift ) // 1-bit input: Active high shift enable input.
);
//---------------------------------------------------------------------------------
//
// Design identification
wire [32-1: 0] id_value;
assign id_value[31: 4] = 28'h0; // reserved
assign id_value[ 3: 0] = 4'h1; // board type 1 - release 1
//---------------------------------------------------------------------------------
//
// System bus connection
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
led_o <= {DWL{1'b0}};
exp_p_dat_o <= {DWE{1'b0}};
exp_p_dir_o <= {DWE{1'b0}};
exp_n_dat_o <= {DWE{1'b0}};
exp_n_dir_o <= {DWE{1'b0}};
end else if (sys_wen) begin
if (sys_addr[19:0]==20'h0c) digital_loop <= sys_wdata[0];
if (sys_addr[19:0]==20'h10) exp_p_dir_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h14) exp_n_dir_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h18) exp_p_dat_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h1C) exp_n_dat_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h30) led_o <= sys_wdata[DWL-1:0];
end
wire sys_en;
assign sys_en = sys_wen | sys_ren;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
sys_err <= 1'b0;
sys_ack <= 1'b0;
end else begin
sys_err <= 1'b0;
casez (sys_addr[19:0])
20'h00000: begin sys_ack <= sys_en; sys_rdata <= { id_value }; end
20'h00004: begin sys_ack <= sys_en; sys_rdata <= { dna_value[32-1: 0]}; end
20'h00008: begin sys_ack <= sys_en; sys_rdata <= {{64- 57{1'b0}}, dna_value[57-1:32]}; end
20'h0000c: begin sys_ack <= sys_en; sys_rdata <= {{32- 1{1'b0}}, digital_loop }; end
20'h00010: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dir_o} ; end
20'h00014: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_n_dir_o} ; end
20'h00018: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dat_o} ; end
20'h0001C: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_n_dat_o} ; end
20'h00020: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dat_i} ; end
20'h00024: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_n_dat_i} ; end
20'h00030: begin sys_ack <= sys_en; sys_rdata <= {{32-DWL{1'b0}}, led_o} ; end
default: begin sys_ack <= sys_en; sys_rdata <= 32'h0 ; end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_PP_BLACKBOX_V
/**
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_clkbufkapwr (
X ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_PP_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// raminfr.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Inferrable Distributed RAM for FIFOs ////
//// ////
//// Known problems (limits): ////
//// None . ////
//// ////
//// To Do: ////
//// Nothing so far. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// ////
//// Created: 2002/07/22 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// Modified for use in the ZAP project by Revanth Kamaraj ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
//Following is the Verilog code for a dual-port RAM with asynchronous read.
module raminfr
(clk, we, a, dpra, di, dpo);
parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;
input clk;
input we;
input [addr_width-1:0] a;
input [addr_width-1:0] dpra;
input [data_width-1:0] di;
//output [data_width-1:0] spo;
output [data_width-1:0] dpo;
reg [data_width-1:0] ram [depth-1:0];
wire [data_width-1:0] dpo;
wire [data_width-1:0] di;
wire [addr_width-1:0] a;
wire [addr_width-1:0] dpra;
always @(posedge clk) begin
if (we)
ram[a] <= di;
end
// assign spo = ram[a];
assign dpo = ram[dpra];
endmodule
|
module MemoryUnit
#(
parameter DATA_WIDTH = 32,
parameter MEMORY_ADDR_WIDTH = 13,
parameter BIOS_ADDRESS_WIDTH = 8,
parameter STORAGE_ADDR_WIDTH = 15,
parameter INSTRUCTION_SIZE = 16
)(
input allow_write_on_memory, slow_clock, fast_clock,
input [(DATA_WIDTH -1):0] original_address,
original_instruction_address,
MemOut,
input is_bios,
output [(INSTRUCTION_SIZE -1):0] output_instruction,
output [(DATA_WIDTH-1):0] data_read_from_memory
);
wire [(STORAGE_ADDR_WIDTH - 1) : 0] storage_addr;
wire [(DATA_WIDTH -1): 0] memory_data, storage_data;
wire is_storage;
wire [(INSTRUCTION_SIZE -1) : 0] memory_instruction,
bios_instruction;
MemoryController controller(
original_address,
is_storage,
storage_addr
);
Memory main_memory(
MemOut,
original_instruction_address[(MEMORY_ADDR_WIDTH - 1) : 0],
original_address[(MEMORY_ADDR_WIDTH - 1) : 0],
allow_write_on_memory, fast_clock, slow_clock,
memory_instruction,
memory_data
);
StorageDrive hd(
storage_addr,
MemOut,
is_storage && allow_write_on_memory , fast_clock, slow_clock,
storage_data
);
MemoryDataHandler poolMux(
is_storage,
storage_data, memory_data,
data_read_from_memory
);
BIOS bios(
fast_clock,
original_instruction_address[(BIOS_ADDRESS_WIDTH - 1):0],
bios_instruction
);
MemoryDataHandler #(.DATA_WIDTH(INSTRUCTION_SIZE))
instructionMUX(
is_bios,
bios_instruction,
memory_instruction,
output_instruction
);
endmodule |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_addr_cmd_pads(
/*
config_data_in,
config_clock_in,
config_io_ena,
config_update,
*/
reset_n,
reset_n_afi_clk,
pll_hr_clk,
pll_avl_phy_clk,
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
phy_ddio_address,
dll_delayctrl_in,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_ck,
phy_ddio_reset_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_reset_n,
phy_mem_ck,
phy_mem_ck_n
);
parameter DEVICE_FAMILY = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter DLL_WIDTH = "";
parameter ADC_PHASE_SETTING = "";
parameter ADC_INVERT_PHASE = "";
parameter IS_HHP_HPS = "";
/*
input config_data_in;
input config_clock_in;
input config_io_ena;
input config_update;
*/
input reset_n;
input reset_n_afi_clk;
input pll_afi_clk;
input pll_hr_clk;
input pll_avl_phy_clk;
input pll_mem_clk;
input pll_write_clk;
input [DLL_WIDTH-1:0] dll_delayctrl_in;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output phy_mem_reset_n;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
/* ********* *
* A/C Logic *
* ********* */
localparam CMD_WIDTH =
MEM_CHIP_SELECT_WIDTH +
MEM_CLK_EN_WIDTH +
MEM_ODT_WIDTH +
MEM_CONTROL_WIDTH +
MEM_CONTROL_WIDTH +
MEM_CONTROL_WIDTH;
localparam AC_CLK_WIDTH = MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH + 1;
localparam IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC = "false";
wire [AC_CLK_WIDTH-1:0] ac_clk;
generate
genvar i;
for (i = 0; i < AC_CLK_WIDTH; i = i + 1)
begin: address_gen
wire addr_cmd_clk;
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) acv_ac_ldc (
.pll_hr_clk(pll_avl_phy_clk),
.pll_dq_clk(pll_write_clk),
.pll_dqs_clk (pll_mem_clk),
.dll_phy_delayctrl(dll_delayctrl_in),
.adc_clk_cps(ac_clk[i])
);
end
endgenerate
hps_sdram_p0_generic_ddio uaddress_pad(
.datain(phy_ddio_address),
.halfratebypass(1'b1),
.dataout(phy_mem_address),
.clk_hr({MEM_ADDRESS_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH-1:0])
);
defparam uaddress_pad.WIDTH = MEM_ADDRESS_WIDTH;
hps_sdram_p0_generic_ddio ubank_pad(
.datain(phy_ddio_bank),
.halfratebypass(1'b1),
.dataout(phy_mem_bank),
.clk_hr({MEM_BANK_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH - 1: MEM_ADDRESS_WIDTH])
);
defparam ubank_pad.WIDTH = MEM_BANK_WIDTH;
hps_sdram_p0_generic_ddio ucmd_pad(
.datain({
phy_ddio_we_n,
phy_ddio_cas_n,
phy_ddio_ras_n,
phy_ddio_odt,
phy_ddio_cke,
phy_ddio_cs_n
}),
.halfratebypass(1'b1),
.dataout({
phy_mem_we_n,
phy_mem_cas_n,
phy_mem_ras_n,
phy_mem_odt,
phy_mem_cke,
phy_mem_cs_n
}),
.clk_hr({CMD_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH - 1: MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH])
);
defparam ucmd_pad.WIDTH = CMD_WIDTH;
hps_sdram_p0_generic_ddio ureset_n_pad(
.datain(phy_ddio_reset_n),
.halfratebypass(1'b1),
.dataout(phy_mem_reset_n),
.clk_hr(pll_hr_clk),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH])
);
defparam ureset_n_pad.WIDTH = 1;
/* ************ *
* Config Logic *
* ************ */
wire [4:0] outputdelaysetting;
wire [4:0] outputenabledelaysetting;
wire outputhalfratebypass;
wire [4:0] inputdelaysetting;
wire [1:0] rfifo_clock_select;
wire [2:0] rfifo_mode;
/*
cyclonev_io_config ioconfig (
.datain(config_data_in),
.clk(config_clock_in),
.ena(config_io_ena),
.update(config_update),
.outputregdelaysetting(outputdelaysetting),
.outputenabledelaysetting(outputenabledelaysetting),
.outputhalfratebypass(outputhalfratebypass),
.readfiforeadclockselect(rfifo_clock_select),
.readfifomode(rfifo_mode),
.padtoinputregisterdelaysetting(inputdelaysetting),
.dataout()
);
*/
/* *************** *
* Mem Clock Logic *
* *************** */
wire [MEM_CK_WIDTH-1:0] mem_ck_source;
wire [MEM_CK_WIDTH-1:0] mem_ck;
generate
genvar clock_width;
for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
begin: clock_gen
if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
begin
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) acv_ck_ldc (
.pll_hr_clk(pll_avl_phy_clk),
.pll_dq_clk(pll_write_clk),
.pll_dqs_clk (pll_mem_clk),
.dll_phy_delayctrl(dll_delayctrl_in),
.adc_clk_cps(mem_ck_source[clock_width])
);
end
else
begin
wire [3:0] phy_clk_in;
wire [3:0] phy_clk_out;
assign phy_clk_in = {pll_avl_phy_clk,pll_write_clk,pll_mem_clk,1'b0};
if (IS_HHP_HPS == "true") begin
assign phy_clk_out = phy_clk_in;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk (phy_clk_in),
.outclk (phy_clk_out)
);
end
wire [3:0] leveled_dqs_clocks;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_out[1]),
.delayctrlin (dll_delayctrl_in),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
cyclonev_clk_phase_select clk_phase_select_dqs (
`ifndef SIMGEN
.clkin (leveled_dqs_clocks[0]),
`else
.clkin (leveled_dqs_clocks),
`endif
.clkout (mem_ck_source[clock_width])
);
defparam clk_phase_select_dqs.physical_clock_source = "DQS";
defparam clk_phase_select_dqs.use_phasectrlin = "false";
defparam clk_phase_select_dqs.phase_setting = 0;
end
wire mem_ck_hi;
wire mem_ck_lo;
if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
begin
assign mem_ck_hi = 1'b0;
assign mem_ck_lo = 1'b1;
end
else
begin
assign mem_ck_hi = phy_ddio_ck[0];
assign mem_ck_lo = phy_ddio_ck[1];
end
altddio_out umem_ck_pad(
.aclr (1'b0),
.aset (1'b0),
.datain_h (mem_ck_hi),
.datain_l (mem_ck_lo),
.dataout (mem_ck[clock_width]),
.oe (1'b1),
.outclock (mem_ck_source[clock_width]),
.outclocken (1'b1)
);
defparam
umem_ck_pad.extend_oe_disable = "UNUSED",
umem_ck_pad.intended_device_family = DEVICE_FAMILY,
umem_ck_pad.invert_output = "OFF",
umem_ck_pad.lpm_hint = "UNUSED",
umem_ck_pad.lpm_type = "altddio_out",
umem_ck_pad.oe_reg = "UNUSED",
umem_ck_pad.power_up_high = "OFF",
umem_ck_pad.width = 1;
wire mem_ck_temp;
assign mem_ck_temp = mem_ck[clock_width];
hps_sdram_p0_clock_pair_generator uclk_generator(
.datain (mem_ck_temp),
.dataout (phy_mem_ck[clock_width]),
.dataout_b (phy_mem_ck_n[clock_width])
);
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:43:45 02/20/2015
// Design Name:
// Module Name: Fetch
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Fetch_Crude(
input [98:0] InstructionPacket,
input clock,
input stall,
output reg [31:0] x_input = 32'h00000000,
output reg [31:0] y_input = 32'h00000000,
output reg [31:0] z_input = 32'h00000000,
output reg [1:0] mode,
output reg operation,
output reg load = 1'b0
);
wire [3:0] Opcode;
wire [31:0] x_processor;
wire [31:0] y_processor;
wire [31:0] z_processor;
assign Opcode = InstructionPacket[98:96];
assign x_processor = InstructionPacket[31:0];
assign y_processor = InstructionPacket[63:32];
assign z_processor = InstructionPacket[95:64];
parameter sin_cos = 4'd0,
sinh_cosh = 4'd1,
arctan = 4'd2,
arctanh = 4'd3,
exp = 4'd4,
sqr_root = 4'd5, // This requires pre processing. x = (a+1)/4 and y = (a-1)/4
division = 4'd6,
tan = 4'd7, // This is iterative. sin_cos followed by division.
tanh = 4'd8, // This is iterative. sinh_cosh followed by division.
nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1)
hypotenuse = 4'd10;
parameter vectoring = 1'b0,
rotation = 1'b1;
parameter circular = 2'b01,
linear = 2'b00,
hyperbolic = 2'b11;
always @ (posedge clock)
begin
if (stall == 1'b0) begin
case(Opcode)
sin_cos:
begin
mode <= circular;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h00000000;
z_input <= z_processor;
load <= 1'b1;
end
sinh_cosh:
begin
mode <= hyperbolic;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h00000000;
z_input <= z_processor;
load <= 1'b1;
end
arctan:
begin
mode <= circular;
operation <= vectoring;
x_input <= 32'h3F800000;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
arctanh:
begin
mode <= hyperbolic;
operation <= vectoring;
x_input <= 32'h3F800000;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
exp:
begin
mode <= hyperbolic;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h3F800000;
z_input <= z_processor;
load <= 1'b1;
end
sqr_root:
begin
mode <= hyperbolic;
operation <= vectoring;
x_input <= Register_File[x_address];
y_input <= Register_File[y_address];
z_input <= 32'h00000000;
load <= 1'b1;
end
division:
begin
mode <= linear;
operation <= vectoring;
x_input <= x_processor;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
hypotenuse:
begin
mode <= circular;
operation <= vectoring;
x_input <= x_processor;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
endcase
end
else begin
load <= 1'b0;
end
end
endmodule
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 1
(* X_CORE_INFO = "axi_register_slice_v2_1_axi_register_slice,Vivado 2013.4" *)
(* CHECK_LICENSE_TYPE = "system_m04_regslice_12,axi_register_slice_v2_1_axi_register_slice,{}" *)
(* CORE_GENERATION_INFO = "system_m04_regslice_12,axi_register_slice_v2_1_axi_register_slice,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_AXI_PROTOCOL=2,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=9,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_REG_CONFIG_W=7,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=7}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_m04_regslice_12 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [8 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [8 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [8 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [8 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(9),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(7),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(7)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_top
//
// Generated
// by: wig
// on: Tue Apr 18 07:50:26 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_top.v,v 1.1 2006/04/19 07:33:13 wig Exp $
// $Date: 2006/04/19 07:33:13 $
// $Log: avfb_top.v,v $
// Revision 1.1 2006/04/19 07:33:13 wig
// Updated/added testcase for 20060404c issue. Needs more work!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.82 2006/04/13 13:31:52 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_top
//
// No user `defines in this module
`define top_rs_selclk_out2_par_c 'b0 // __I_VectorConv
module avfb_top
//
// Generated module i_avfb_top
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [4:0] top_rs_selclk_out2_par;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign top_rs_selclk_out2_par[4:4] = `top_rs_selclk_out2_par_c;
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for i_avfb_cgu
cgu i_avfb_cgu (
.selclk_out2_par_i(top_rs_selclk_out2_par)
);
// End of Generated Instance Port Map for i_avfb_cgu
// Generated Instance Port Map for i_avfb_logic
avfb_logic i_avfb_logic (
.top_rs_selclk_out2_par_go(top_rs_selclk_out2_par)
);
// End of Generated Instance Port Map for i_avfb_logic
endmodule
//
// End of Generated Module rtl of avfb_top
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_axis_tx_core (
// dac interface
dac_clk,
dac_rd,
dac_valid,
dac_data,
// dma interface
dma_clk,
dma_fs,
dma_valid,
dma_data,
dma_ready,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter DATA_WIDTH = 64;
localparam DW = DATA_WIDTH - 1;
// dac interface
input dac_clk;
input dac_rd;
output dac_valid;
output [DW:0] dac_data;
// dma interface
input dma_clk;
output dma_fs;
input dma_valid;
input [63:0] dma_data;
output dma_ready;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal clock and resets
wire dac_rst;
wire dma_rst;
// internal signals
wire dma_ovf_s;
wire dma_unf_s;
wire [31:0] dma_frmcnt_s;
// dma interface
ad_axis_dma_tx #(.DATA_WIDTH(DATA_WIDTH)) i_axis_dma_tx (
.dma_clk (dma_clk),
.dma_rst (dma_rst),
.dma_fs (dma_fs),
.dma_valid (dma_valid),
.dma_data (dma_data),
.dma_ready (dma_ready),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_rd (dac_rd),
.dac_valid (dac_valid),
.dac_data (dac_data),
.dma_frmcnt (dma_frmcnt_s));
// processor interface
up_axis_dma_tx i_up_axis_dma_tx (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dma_clk (dma_clk),
.dma_rst (dma_rst),
.dma_frmcnt (dma_frmcnt_s),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4B_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NOR4B_PP_BLACKBOX_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4B_PP_BLACKBOX_V
|
module display_logic( input pxl_clk,
input [9:0] hcount,
input [9:0] vcount,
input [9:0] ball_y,
input [9:0] ball_x,
input [5:0] player_position,
input [3:0] block_num,
input vsync,
input lose,
input win,
output reg drawing_player,
output reg drawing_block,
output reg [2:0] rgb );
`include "defines.v"
reg [2:0] flash;
reg [3:0] flash_time;
reg flash_hold;
always @ (hcount, vcount, ball_y, ball_x, player_position, block_num, lose, win, flash)
begin : display_decoder
drawing_player = 0;
drawing_block = 0;
if (hcount > `screen_right || vcount > `screen_bottom) rgb <= 3'b000;
else if (win) rgb <= flash;
else if (lose) rgb <= `red;
else if (vcount < `bottom_edge && hcount < `left_edge) rgb <= `green;
else if (vcount < `bottom_edge && hcount > `right_edge) rgb <= `green;
else if (vcount < `top_edge ) rgb <= `green;
else if (vcount > `bottom_edge) rgb <= `red;
else if (vcount < ball_y + 3 && vcount > ball_y - 3 &&
hcount < ball_x + 3 && hcount > ball_x - 3) rgb <= `white;
else if ( vcount > `player_vstart && vcount < (`player_vstart + `player_width ) &&
hcount > (player_position << 5) - `player_hlength + `left_edge &&
hcount < ((player_position << 5) + `player_hlength + `left_edge) )
begin
rgb <= `white;
drawing_player <= 1;
end
else if (vcount > `blocks_vstart && vcount <= `blocks_vend && hcount > `blocks_hstart && hcount <= `blocks_hend && |block_num)
begin
drawing_block <= 1;
if ( |block_num[2:0] ) rgb <= block_num[2:0];
else rgb <= block_num[2:0] + 3;
// rgb <= ~|block_num[3:0] ? block_num[2:0] : block_num[2:0] + 3'd3;
end
else rgb <= `black;
end
always @ (posedge pxl_clk)
begin
if (!vsync)
begin
if (!flash_hold) flash_time <= flash_time + 1;
flash_hold <= 1;
end
else
begin
flash_hold <= 0;
end
if (flash_time == 0)
begin
flash <= `black;
end
else if (flash_time == 3)
begin
if (win) flash <= `white;
else if (lose) flash <= `red;
end
else if (flash_time >= 6)
begin
flash_time <= 0;
end
end
endmodule |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_wseldp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ifu_wsel
// Description:
// Way selects removed from icache and done here
*/
module sparc_ifu_wseldp (/*AUTOARG*/
// Outputs
wsel_fdp_fetdata_s1, wsel_fdp_topdata_s1, wsel_mbist_icache_data,
so,
// Inputs
rclk, se, si, icd_wsel_fetdata_s1, icd_wsel_topdata_s1,
itlb_wsel_waysel_s1, ifq_erb_asiway_f
);
input rclk,
se,
si;
input [135:0] icd_wsel_fetdata_s1,
icd_wsel_topdata_s1;
input [3:0] itlb_wsel_waysel_s1;
input [1:0] ifq_erb_asiway_f;
output [33:0] wsel_fdp_fetdata_s1;
output [33:0] wsel_fdp_topdata_s1;
output [67:0] wsel_mbist_icache_data;
output so;
// local signals
wire [3:0] dec_asiway_s_l,
waysel_buf_s1;
wire [1:0] asiway_s;
wire [33:0] rdc_fetdata_s1,
rdc_topdata_s1,
erb_asidata_s,
asi_topdata_s;
wire clk;
//
// Code begins here
//
//------------------
// Control Portion
//------------------
assign clk = rclk;
// flop and decode waysel
dff_s #(2) asiway_reg(.din (ifq_erb_asiway_f),
.q (asiway_s),
.clk (clk), .se(se), .si(), .so());
assign dec_asiway_s_l[0] = ~(~asiway_s[1] & ~asiway_s[0]);
assign dec_asiway_s_l[1] = ~(~asiway_s[1] & asiway_s[0]);
assign dec_asiway_s_l[2] = ~( asiway_s[1] & ~asiway_s[0]);
assign dec_asiway_s_l[3] = ~( asiway_s[1] & asiway_s[0]);
//--------------------------
// Datapath Section
//--------------------------
// buffer wayselect from itlb
// align these buffers with the corresponding pins in itlb
assign waysel_buf_s1 = itlb_wsel_waysel_s1;
// Very Timing Critical Wayselect Muxes
// !!Cannot be a one-hot mux!!
// use ao2222
// bw_u1_ao2222_2x #(34) fetway_mx(.z (rdc_fetdata_s1[33:0]),
// .a2 (icd_wsel_fetdata_s1[33:0]),
// .b2 (icd_wsel_fetdata_s1[67:34]),
// .c2 (icd_wsel_fetdata_s1[101:68]),
// .d2 (icd_wsel_fetdata_s1[135:102]),
// .a1 (waysel_buf_s1[0]),
// .b1 (waysel_buf_s1[1]),
// .c1 (waysel_buf_s1[2]),
// .d1 (waysel_buf_s1[3]));
// bw_u1_ao2222_2x #(34) topway_mx(.z (rdc_topdata_s1[33:0]),
// .a2 (icd_wsel_topdata_s1[33:0]),
// .b2 (icd_wsel_topdata_s1[67:34]),
// .c2 (icd_wsel_topdata_s1[101:68]),
// .d2 (icd_wsel_topdata_s1[135:102]),
// .a1 (waysel_buf_s1[0]),
// .b1 (waysel_buf_s1[1]),
// .c1 (waysel_buf_s1[2]),
// .d1 (waysel_buf_s1[3]));
assign rdc_fetdata_s1 = icd_wsel_fetdata_s1[33:0] & {34{waysel_buf_s1[0]}} |
icd_wsel_fetdata_s1[67:34] & {34{waysel_buf_s1[1]}} |
icd_wsel_fetdata_s1[101:68] & {34{waysel_buf_s1[2]}} |
icd_wsel_fetdata_s1[135:102] & {34{waysel_buf_s1[3]}};
assign rdc_topdata_s1 = icd_wsel_topdata_s1[33:0] & {34{waysel_buf_s1[0]}} |
icd_wsel_topdata_s1[67:34] & {34{waysel_buf_s1[1]}} |
icd_wsel_topdata_s1[101:68] & {34{waysel_buf_s1[2]}} |
icd_wsel_topdata_s1[135:102] & {34{waysel_buf_s1[3]}};
// buffer and send to fdp
assign wsel_fdp_fetdata_s1 = rdc_fetdata_s1;
assign wsel_fdp_topdata_s1 = rdc_topdata_s1;
// mux for asi data, not critical
dp_mux4ds #(34) asid_mx(.dout (erb_asidata_s[33:0]),
.in0 (icd_wsel_fetdata_s1[33:0]),
.in1 (icd_wsel_fetdata_s1[67:34]),
.in2 (icd_wsel_fetdata_s1[101:68]),
.in3 (icd_wsel_fetdata_s1[135:102]),
.sel0_l (dec_asiway_s_l[0]),
.sel1_l (dec_asiway_s_l[1]),
.sel2_l (dec_asiway_s_l[2]),
.sel3_l (dec_asiway_s_l[3]));
dp_mux4ds #(34) asitop_mx(.dout (asi_topdata_s[33:0]),
.in0 (icd_wsel_topdata_s1[33:0]),
.in1 (icd_wsel_topdata_s1[67:34]),
.in2 (icd_wsel_topdata_s1[101:68]),
.in3 (icd_wsel_topdata_s1[135:102]),
.sel0_l (dec_asiway_s_l[0]),
.sel1_l (dec_asiway_s_l[1]),
.sel2_l (dec_asiway_s_l[2]),
.sel3_l (dec_asiway_s_l[3]));
// buffer before sending to bist/errdp
assign wsel_mbist_icache_data = {asi_topdata_s[33:32],
erb_asidata_s[33:32],
asi_topdata_s[31:0],
erb_asidata_s[31:0]};
// Everything below can be ignored for physical implementation
// monitor for waysel -- moved here from itlb
// Keeping this around for 0-in. cmp level check is in icache_mutex_mon.v
`ifdef DEFINE_0IN
always @ (negedge clk)
begin
if (!((waysel_buf_s1 == 4'b0001) ||
(waysel_buf_s1 == 4'b0010) ||
(waysel_buf_s1 == 4'b0100) ||
(waysel_buf_s1 == 4'b1000) ||
(waysel_buf_s1 == 4'b0000)))
begin
// 0in <fire -message "FATAL ERROR: icache waysel not mutex"
//$error("IC_WAYSEL", "FATAL ERROR: icache waysel not mutex %b",
// waysel_buf_s1);
end
end // always @ (negedge clk)
`endif
endmodule // sparc_ifu_wseldp
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
module altpciexpav_stif_rx
# (
parameter CG_COMMON_CLOCK_MODE = 0,
parameter CB_A2P_PERF_PROFILE = 3,
parameter CB_P2A_PERF_PROFILE = 3,
parameter CB_PCIE_MODE = 0,
parameter CB_PCIE_RX_LITE = 0,
parameter CB_RXM_DATA_WIDTH = 64,
parameter port_type_hwtcl = "Native endpoint",
parameter AVALON_ADDR_WIDTH = 32
)
( input Clk_i,
input AvlClk_i,
input Rstn_i,
input RxmRstn_i,
// Rx port interface to PCI Exp HIP
output RxStReady_o,
output RxStMask_o,
input [63:0] RxStData_i,
input [31:0] RxStParity_i,
input [7:0] RxStBe_i,
input [1:0] RxStEmpty_i,
input RxStErr_i,
input RxStSop_i,
input RxStEop_i,
input RxStValid_i,
input [7:0] RxStBarDec1_i,
input [7:0] RxStBarDec2_i,
// Tx module interface
// buffer credit for accepting rx read
input TxCpl_i,
input [9:0] TxCplLen_i, // Dw
// Rx pnding read fifo
output [56:0] RxPndgRdFifoDat_o,
output RxPndgRdFifoEmpty_o,
input RxPndgRdFifoRdReq_i,
output CplTagRelease_o,
output [130:0] RxRpFifoWrData_o,
output RxRpFifoWrReq_o,
/// RX Master Read Write Interface
output RxmWrite_0_o,
output [AVALON_ADDR_WIDTH-1:0] RxmAddress_0_o,
output [CB_RXM_DATA_WIDTH-1:0] RxmWriteData_0_o,
output [(CB_RXM_DATA_WIDTH/8)-1:0] RxmByteEnable_0_o,
output [6:0] RxmBurstCount_0_o,
input RxmWaitRequest_0_i,
output RxmRead_0_o,
output RxmWrite_1_o,
output [AVALON_ADDR_WIDTH-1:0] RxmAddress_1_o,
output [CB_RXM_DATA_WIDTH-1:0] RxmWriteData_1_o,
output [(CB_RXM_DATA_WIDTH/8)-1:0] RxmByteEnable_1_o,
output [6:0] RxmBurstCount_1_o,
input RxmWaitRequest_1_i,
output RxmRead_1_o,
output RxmWrite_2_o,
output [AVALON_ADDR_WIDTH-1:0] RxmAddress_2_o,
output [CB_RXM_DATA_WIDTH-1:0] RxmWriteData_2_o,
output [(CB_RXM_DATA_WIDTH/8)-1:0] RxmByteEnable_2_o,
output [6:0] RxmBurstCount_2_o,
input RxmWaitRequest_2_i,
output RxmRead_2_o,
output RxmWrite_3_o,
output [AVALON_ADDR_WIDTH-1:0] RxmAddress_3_o,
output [CB_RXM_DATA_WIDTH-1:0] RxmWriteData_3_o,
output [(CB_RXM_DATA_WIDTH/8)-1:0] RxmByteEnable_3_o,
output [6:0] RxmBurstCount_3_o,
input RxmWaitRequest_3_i,
output RxmRead_3_o,
output RxmWrite_4_o,
output [AVALON_ADDR_WIDTH-1:0] RxmAddress_4_o,
output [(CB_RXM_DATA_WIDTH/8)-1:0] RxmByteEnable_4_o,
output [CB_RXM_DATA_WIDTH-1:0] RxmWriteData_4_o,
output [6:0] RxmBurstCount_4_o,
input RxmWaitRequest_4_i,
output RxmRead_4_o,
output RxmWrite_5_o,
output [AVALON_ADDR_WIDTH-1:0] RxmAddress_5_o,
output [CB_RXM_DATA_WIDTH-1:0] RxmWriteData_5_o,
output [(CB_RXM_DATA_WIDTH/8)-1:0] RxmByteEnable_5_o,
output [6:0] RxmBurstCount_5_o,
input RxmWaitRequest_5_i,
output RxmRead_5_o,
output [63:0] TxReadData_o,
output TxReadDataValid_o,
/// paramter signals
input [31:0] cb_p2a_avalon_addr_b0_i,
input [31:0] cb_p2a_avalon_addr_b1_i,
input [31:0] cb_p2a_avalon_addr_b2_i,
input [31:0] cb_p2a_avalon_addr_b3_i,
input [31:0] cb_p2a_avalon_addr_b4_i,
input [31:0] cb_p2a_avalon_addr_b5_i,
input [31:0] cb_p2a_avalon_addr_b6_i,
input [227:0] k_bar_i,
input TxRespIdle_i,
input [31:0] DevCsr_i,
output rxcntrl_sm_idle
);
//define the clogb2 constant function
function integer clogb2;
input [31:0] depth;
begin
depth = depth - 1 ;
for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1)
depth = depth >> 1 ;
end
endfunction // clogb2
localparam CB_RX_CD_BUFFER_DEPTH = (CB_P2A_PERF_PROFILE == 2)? 64 : 128;
localparam CB_RX_CPL_BUFFER_DEPTH =512; // 8 tags , 512B
localparam RXCD_BUFF_ADDR_WIDTH = clogb2(CB_RX_CD_BUFFER_DEPTH) ;
localparam RX_CPL_BUFF_ADDR_WIDTH = clogb2(CB_RX_CPL_BUFFER_DEPTH) ;
wire [7:0] cdfifo_wrusedw;
wire cdfifo_wrreq;
wire [71:0] cdfifo_datain;
wire [3:0] rxpndgrd_fifo_usedw;
wire rxpndgrd_fifo_wrreq;
wire [56:0] rxpndgrd_fifo_datain;
wire cdfifo_rdempty;
wire [71:0] cdfifo_dataout;
wire rxpndgrd_fifo_wrfull;
wire cdfifo_rdreq;
wire [8:0] cplram_wraddr;
wire [8:0] cplram_rdaddr;
wire [65:0] cplram_wrdat;
wire [73:0] cplram_data_out;
wire cpl_realease_tag;
wire [4:0] cpl_desc;
wire cpl_req;
wire cplram_wr_ena;
reg [56:0] rx_pending_read_reg;
reg rx_pending_valid_reg;
reg rx_read_in_progress_reg;
wire rx_read_in_progress;
// instantiate the Rx control module on the PCIe clock domain
altpciexpav_stif_rx_cntrl
#(
.CG_COMMON_CLOCK_MODE(CG_COMMON_CLOCK_MODE),
.CB_A2P_PERF_PROFILE(CB_A2P_PERF_PROFILE),
.CB_P2A_PERF_PROFILE(CB_P2A_PERF_PROFILE),
.CB_PCIE_MODE(CB_PCIE_MODE),
.CB_RXM_DATA_WIDTH (CB_RXM_DATA_WIDTH),
.CB_PCIE_RX_LITE (CB_PCIE_RX_LITE) ,
.port_type_hwtcl(port_type_hwtcl),
.AVALON_ADDR_WIDTH (AVALON_ADDR_WIDTH)
)
rx_pcie_cntrl
( .Clk_i(Clk_i),
.Rstn_i(Rstn_i),
.AvlClk_i(AvlClk_i),
.RxmRstn_i(RxmRstn_i),
// Rx port interface to PCI Exp core
.RxStReady_o(RxStReady_o),
.RxStMask_o(RxStMask_o),
.RxStData_i(RxStData_i),
.RxStParity_i(RxStParity_i),
.RxStBe_i(RxStBe_i),
.RxStEmpty_i(RxStEmpty_i),
.RxStErr_i(RxStErr_i),
.RxStSop_i(RxStSop_i),
.RxStEop_i(RxStEop_i),
.RxStValid_i(RxStValid_i),
.RxStBarDec1_i(RxStBarDec1_i),
.RxStBarDec2_i(RxStBarDec2_i),
/// RX Master Read Write Interface
.RxmWrite_0_o ( RxmWrite_0_o ),
.RxmAddress_0_o ( RxmAddress_0_o ),
.RxmWriteData_0_o ( RxmWriteData_0_o ),
.RxmByteEnable_0_o ( RxmByteEnable_0_o ),
.RxmBurstCount_0_o ( RxmBurstCount_0_o ),
.RxmWaitRequest_0_i ( RxmWaitRequest_0_i ),
.RxmRead_0_o ( RxmRead_0_o ),
.RxmWrite_1_o ( RxmWrite_1_o ),
.RxmAddress_1_o ( RxmAddress_1_o ),
.RxmWriteData_1_o ( RxmWriteData_1_o ),
.RxmByteEnable_1_o ( RxmByteEnable_1_o ),
.RxmBurstCount_1_o ( RxmBurstCount_1_o ),
.RxmWaitRequest_1_i ( RxmWaitRequest_1_i ),
.RxmRead_1_o ( RxmRead_1_o ),
.RxmWrite_2_o ( RxmWrite_2_o ),
.RxmAddress_2_o ( RxmAddress_2_o ),
.RxmWriteData_2_o ( RxmWriteData_2_o ),
.RxmByteEnable_2_o ( RxmByteEnable_2_o ),
.RxmBurstCount_2_o ( RxmBurstCount_2_o ),
.RxmWaitRequest_2_i ( RxmWaitRequest_2_i ),
.RxmRead_2_o ( RxmRead_2_o ),
.RxmWrite_3_o ( RxmWrite_3_o ),
.RxmAddress_3_o ( RxmAddress_3_o ),
.RxmWriteData_3_o ( RxmWriteData_3_o ),
.RxmByteEnable_3_o ( RxmByteEnable_3_o ),
.RxmBurstCount_3_o ( RxmBurstCount_3_o ),
.RxmWaitRequest_3_i ( RxmWaitRequest_3_i ),
.RxmRead_3_o ( RxmRead_3_o ),
.RxmWrite_4_o ( RxmWrite_4_o ),
.RxmAddress_4_o ( RxmAddress_4_o ),
.RxmWriteData_4_o ( RxmWriteData_4_o ),
.RxmByteEnable_4_o ( RxmByteEnable_4_o ),
.RxmBurstCount_4_o ( RxmBurstCount_4_o ),
.RxmWaitRequest_4_i ( RxmWaitRequest_4_i ),
.RxmRead_4_o ( RxmRead_4_o ),
.RxmWrite_5_o ( RxmWrite_5_o ),
.RxmAddress_5_o ( RxmAddress_5_o ),
.RxmWriteData_5_o ( RxmWriteData_5_o ),
.RxmByteEnable_5_o ( RxmByteEnable_5_o ),
.RxmBurstCount_5_o ( RxmBurstCount_5_o ),
.RxmWaitRequest_5_i ( RxmWaitRequest_5_i ),
.RxmRead_5_o ( RxmRead_5_o ),
.CplReq_o(cpl_req),
.CplDesc_o(cpl_desc),
.PndngRdFifoUsedW_i(rxpndgrd_fifo_usedw),
.PndgRdFifoWrReq_o(rxpndgrd_fifo_wrreq),
.PndgRdHeader_o(rxpndgrd_fifo_datain),
.PndngRdFifoEmpty_i(RxPndgRdFifoEmpty_o),
.RxRdInProgress_i(rx_read_in_progress),
// Completion data dual port ram interface
.CplRamWrAddr_o(cplram_wraddr),
.CplRamWrDat_o(cplram_wrdat),
.CplRamWrEna_o(cplram_wr_ena),
// Read respose module interface
// Tx Completion interface
.TxCpl_i(TxCpl_i),
.TxCplLen_i(TxCplLen_i), // this is modified len (+1, +2, or unchanged)
.RxRpFifoWrData_o(RxRpFifoWrData_o),
.RxRpFifoWrReq_o(RxRpFifoWrReq_o),
// cfg signals
.DevCsr_i(DevCsr_i),
/// paramter signals
.k_bar_i(k_bar_i),
.cb_p2a_avalon_addr_b0_i(cb_p2a_avalon_addr_b0_i),
.cb_p2a_avalon_addr_b1_i(cb_p2a_avalon_addr_b1_i),
.cb_p2a_avalon_addr_b2_i(cb_p2a_avalon_addr_b2_i),
.cb_p2a_avalon_addr_b3_i(cb_p2a_avalon_addr_b3_i),
.cb_p2a_avalon_addr_b4_i(cb_p2a_avalon_addr_b4_i),
.cb_p2a_avalon_addr_b5_i(cb_p2a_avalon_addr_b5_i),
.cb_p2a_avalon_addr_b6_i(cb_p2a_avalon_addr_b6_i),
.TxRespIdle_i(TxRespIdle_i),
.rxcntrl_sm_idle(rxcntrl_sm_idle)
);
generate if (CB_PCIE_RX_LITE == 0)
begin
scfifo pndgtxrd_fifo (
.rdreq (RxPndgRdFifoRdReq_i),
.clock (AvlClk_i),
.wrreq (rxpndgrd_fifo_wrreq),
.data (rxpndgrd_fifo_datain),
.usedw (rxpndgrd_fifo_usedw),
.empty (RxPndgRdFifoEmpty_o),
.q (RxPndgRdFifoDat_o),
.full () ,
.aclr (~Rstn_i),
.almost_empty (),
.almost_full (),
.sclr ()
);
defparam
pndgtxrd_fifo.add_ram_output_register = "ON",
pndgtxrd_fifo.intended_device_family = "Stratix IV",
pndgtxrd_fifo.lpm_numwords = 16,
pndgtxrd_fifo.lpm_showahead = "OFF",
pndgtxrd_fifo.lpm_type = "scfifo",
pndgtxrd_fifo.lpm_width = 57,
pndgtxrd_fifo.lpm_widthu = 4,
pndgtxrd_fifo.overflow_checking = "ON",
pndgtxrd_fifo.underflow_checking = "ON",
pndgtxrd_fifo.use_eab = "ON";
assign rx_read_in_progress = 1'b0;
end
else
begin
always @ (posedge Clk_i or negedge Rstn_i)
if(~Rstn_i)
rx_pending_read_reg <= 57'h0;
else if(rxpndgrd_fifo_wrreq)
rx_pending_read_reg <= rxpndgrd_fifo_datain;
always @ (posedge Clk_i or negedge Rstn_i)
begin
if(~Rstn_i)
rx_pending_valid_reg <= 1'b0;
else if(rxpndgrd_fifo_wrreq)
rx_pending_valid_reg <= 1'b1;
else if(RxPndgRdFifoRdReq_i)
rx_pending_valid_reg <= 1'b0;
end
always @ (posedge Clk_i or negedge Rstn_i)
begin
if(~Rstn_i)
rx_read_in_progress_reg <= 1'b0;
else if(rxpndgrd_fifo_wrreq)
rx_read_in_progress_reg <= 1'b1;
else if(TxCpl_i)
rx_read_in_progress_reg <= 1'b0;
end
assign RxPndgRdFifoEmpty_o = ~rx_pending_valid_reg;
assign RxPndgRdFifoDat_o = rx_pending_read_reg;
assign rx_read_in_progress = rx_read_in_progress_reg;
end
endgenerate
// instantiate the Rx Read respose module
altpciexpav_stif_rx_resp
# (
.CG_COMMON_CLOCK_MODE(CG_COMMON_CLOCK_MODE)
)
rxavl_resp
( .Clk_i(Clk_i),
.AvlClk_i(AvlClk_i),
.Rstn_i(Rstn_i),
.RxmRstn_i(RxmRstn_i),
// Interface to Transaction layer
.CplReq_i(cpl_req),
.CplDesc_i(cpl_desc),
/// interface to completion buffer
.CplRdAddr_o(cplram_rdaddr),
.CplBufData_i(cplram_data_out),
// interface to tx control
.TagRelease_o(CplTagRelease_o),
// interface to Avalon slave
//.TxsReadData_o(TxReadData_o),
.TxsReadDataValid_o(TxReadDataValid_o)
);
// Muxing the tag ram read address
// from the two reading sources : main control and read response
//// instantiate the Rx Completion data ram
generate if(CB_PCIE_MODE == 0)
begin
altsyncram
#(
.intended_device_family("Stratix"),
.operation_mode("DUAL_PORT"),
.width_a(66),
.widthad_a(RX_CPL_BUFF_ADDR_WIDTH),
.numwords_a(CB_RX_CPL_BUFFER_DEPTH),
.width_b(66),
.widthad_b(RX_CPL_BUFF_ADDR_WIDTH),
.numwords_b(CB_RX_CPL_BUFFER_DEPTH),
.lpm_type("altsyncram"),
.width_byteena_a(1),
.outdata_reg_b("UNREGISTERED"),
.indata_aclr_a("NONE"),
.wrcontrol_aclr_a("NONE"),
.address_aclr_a("NONE"),
.address_reg_b("CLOCK0"),
.address_aclr_b("NONE"),
.outdata_aclr_b("NONE"),
.read_during_write_mode_mixed_ports("DONT_CARE"),
.power_up_uninitialized("FALSE")
)
cpl_ram (
.wren_a (cplram_wr_ena),
.clock0 (AvlClk_i),
.address_a (cplram_wraddr),
.address_b (cplram_rdaddr),
.data_a (cplram_wrdat),
.q_b (cplram_data_out),
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.data_b (),
.q_a (),
.rden_b (),
.wren_b ()
);
assign TxReadData_o = cplram_data_out[63:0];
end
else
begin
assign TxReadData_o = 64'h0;
end
endgenerate
endmodule
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 10
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
//`define VERBOSE
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
wire start;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_artemis_pcie_platform s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
`ifdef VERBOSE $display (""); `endif
end
else begin
`ifdef VERBOSE $display ("Error unrecognized line: %h" % ch); `endif
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
`ifdef VERBOSE $display ("Sleep for %h Clock cycles", r_in_data_count); `endif
`SLEEP_CLK(r_in_data_count);
`ifdef VERBOSE $display ("Sleep Finished"); `endif
end
else begin
`ifdef VERBOSE $display ("Error: read_count = %h != 4", read_count); `endif
`ifdef VERBOSE $display ("Character: %h", ch); `endif
end
end
else begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
`endif
`ifdef VERBOSE $display ("Execute Command"); `endif
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
`ifdef VERBOSE $display ("TB: reading a new double word: %h", r_in_data); `endif
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
`ifdef VERBOSE $display ("Command Finished"); `endif
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
`ifdef VERBOSE $display ("TB: finished command"); `endif
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
`endif
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
`ifdef VERBOSE $display ("TB: sdram is ready"); `endif
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
else begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
`ifdef VERBOSE $display ("TB: Ping Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
`ifdef VERBOSE $display ("In Write Response"); `endif
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
`ifdef VERBOSE $display ("TB: Write Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Write Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
`ifdef VERBOSE $display ("TB: Read Response Good"); `endif
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
`ifdef VERBOSE $display ("TB: Read Response Bad (Malformed response: %h)", w_out_status); `endif
state <= FINISHED;
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
`ifdef VERBOSE $display ("TB: Read a 32bit data packet"); `endif
`ifdef VERBOSE $display ("TB: \tRead Data: %h", w_out_data); `endif
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
`ifdef VERBOSE $display ("Execute Command is low"); `endif
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
`ifdef VERBOSE $display("TB: Output Handler Recieved interrupt"); `endif
`ifdef VERBOSE $display("TB:\tcommand: %h", w_out_status); `endif
`ifdef VERBOSE $display("TB:\taddress: %h", w_out_address); `endif
`ifdef VERBOSE $display("TB:\tdata: %h", w_out_data); `endif
end
end//not reset
end
endmodule
|
`ifndef _alu
`define _alu
/*`include "rc_adder.v"*/
module alu(
input [3:0] ctl,
input [31:0] a, b,
output reg [31:0] out,
output zero);
wire [31:0] sub_ab;
wire [31:0] add_ab;
wire oflow_add;
wire oflow_sub;
wire oflow;
wire slt;
assign zero = (0 == out);
assign sub_ab = a - b;
assign add_ab = a + b;
/*rc_adder #(.N(32)) add0(.a(a), .b(b), .s(add_ab));*/
// overflow occurs (with 2s complement numbers) when
// the operands have the same sign, but the sign of the result is
// different. The actual sign is the opposite of the result.
// It is also dependent on whether addition or subtraction is performed.
assign oflow_add = (a[31] == b[31] && add_ab[31] != a[31]) ? 1 : 0;
assign oflow_sub = (a[31] == b[31] && sub_ab[31] != a[31]) ? 1 : 0;
assign oflow = (ctl == 4'b0010) ? oflow_add : oflow_sub;
// set if less than, 2s compliment 32-bit numbers
assign slt = oflow_sub ? ~(a[31]) : a[31];
always @(*) begin
case (ctl)
4'd2: out <= add_ab; /* add */
4'd0: out <= a & b; /* and */
4'd12: out <= ~(a | b); /* nor */
4'd1: out <= a | b; /* or */
4'd7: out <= {{31{1'b0}}, slt}; /* slt */
4'd6: out <= sub_ab; /* sub */
4'd13: out <= a ^ b; /* xor */
default: out <= 0;
endcase
end
endmodule
`endif
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module ym_timer #(parameter cnt_width = 8, mult_width = 1) (
input CLK,
input TICK_144,
input nRESET,
input [cnt_width-1:0] LOAD_VALUE,
input LOAD,
input CLR_FLAG,
input SET_RUN,
input CLR_RUN,
output reg OVF_FLAG,
output reg OVF
);
reg RUN;
reg [mult_width-1:0] MULT;
reg [cnt_width-1:0] CNT;
reg [mult_width+cnt_width-1:0] NEXT, INIT;
always @(posedge CLK)
begin
if (CLR_RUN || !nRESET)
RUN <= 0;
else if (SET_RUN || LOAD)
RUN <= 1;
if (CLR_FLAG || !nRESET)
OVF_FLAG <= 0;
else if (OVF)
OVF_FLAG <= 1;
if (TICK_144)
begin
if (LOAD)
begin
MULT <= { (mult_width){1'b0} };
CNT <= LOAD_VALUE;
end
else if (RUN)
{ CNT, MULT } <= OVF ? INIT : NEXT;
end
end
always @(*)
begin
{ OVF, NEXT } <= { 1'b0, CNT, MULT } + 1'b1;
INIT <= { LOAD_VALUE, { (mult_width){1'b0} } };
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSTP_BLACKBOX_V
`define SKY130_FD_SC_LS__SDFSTP_BLACKBOX_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSTP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3B_1_V
`define SKY130_FD_SC_LS__OR3B_1_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or3b_1 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or3b_1 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3B_1_V
|
(** * Logic: Logic in Coq *)
Require Export MoreCoq.
(** Coq's built-in logic is very small: the only primitives are
[Inductive] definitions, universal quantification ([forall]), and
implication ([->]), while all the other familiar logical
connectives -- conjunction, disjunction, negation, existential
quantification, even equality -- can be encoded using just these.
This chapter explains the encodings and shows how the tactics
we've seen can be used to carry out standard forms of logical
reasoning involving these connectives.
*)
(* ########################################################### *)
(** * Propositions *)
(** In previous chapters, we have seen many examples of factual
claims (_propositions_) and ways of presenting evidence of their
truth (_proofs_). In particular, we have worked extensively with
_equality propositions_ of the form [e1 = e2], with
implications ([P -> Q]), and with quantified propositions
([forall x, P]).
*)
(** In Coq, the type of things that can (potentially)
be proven is [Prop]. *)
(** Here is an example of a provable proposition: *)
Check (3 = 3).
(* ===> Prop *)
(** Here is an example of an unprovable proposition: *)
Check (forall (n:nat), n = 2).
(* ===> Prop *)
(** Recall that [Check] asks Coq to tell us the type of the indicated
expression. *)
(* ########################################################### *)
(** * Proofs and Evidence *)
(** In Coq, propositions have the same status as other types, such as
[nat]. Just as the natural numbers [0], [1], [2], etc. inhabit
the type [nat], a Coq proposition [P] is inhabited by its
_proofs_. We will refer to such inhabitants as _proof term_ or
_proof object_ or _evidence_ for the truth of [P].
In Coq, when we state and then prove a lemma such as:
Lemma silly : 0 * 3 = 0.
Proof. reflexivity. Qed.
the tactics we use within the [Proof]...[Qed] keywords tell Coq
how to construct a proof term that inhabits the proposition. In
this case, the proposition [0 * 3 = 0] is justified by a
combination of the _definition_ of [mult], which says that [0 * 3]
_simplifies_ to just [0], and the _reflexive_ principle of
equality, which says that [0 = 0].
*)
(** *** *)
Lemma silly : 0 * 3 = 0.
Proof. reflexivity. Qed.
(** We can see which proof term Coq constructs for a given Lemma by
using the [Print] directive: *)
Print silly.
(* ===> silly = eq_refl : 0 * 3 = 0 *)
(** Here, the [eq_refl] proof term witnesses the equality. (More on
equality later!)*)
(** ** Implications _are_ functions *)
(** Just as we can implement natural number multiplication as a
function:
[
mult : nat -> nat -> nat
]
The _proof term_ for an implication [P -> Q] is a _function_ that
takes evidence for [P] as input and produces evidence for [Q] as its
output.
*)
Lemma silly_implication : (1 + 1) = 2 -> 0 * 3 = 0.
Proof. intros H. reflexivity. Qed.
(** We can see that the proof term for the above lemma is indeed a
function: *)
Print silly_implication.
(* ===> silly_implication = fun _ : 1 + 1 = 2 => eq_refl
: 1 + 1 = 2 -> 0 * 3 = 0 *)
(** ** Defining propositions *)
(** Just as we can create user-defined inductive types (like the
lists, binary representations of natural numbers, etc., that we
seen before), we can also create _user-defined_ propositions.
Question: How do you define the meaning of a proposition?
*)
(** *** *)
(** The meaning of a proposition is given by _rules_ and _definitions_
that say how to construct _evidence_ for the truth of the
proposition from other evidence.
- Typically, rules are defined _inductively_, just like any other
datatype.
- Sometimes a proposition is declared to be true without
substantiating evidence. Such propositions are called _axioms_.
In this, and subsequence chapters, we'll see more about how these
proof terms work in more detail.
*)
(* ########################################################### *)
(** * Conjunction (Logical "and") *)
(** The logical conjunction of propositions [P] and [Q] can be
represented using an [Inductive] definition with one
constructor. *)
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
(** The intuition behind this definition is simple: to
construct evidence for [and P Q], we must provide evidence
for [P] and evidence for [Q]. More precisely:
- [conj p q] can be taken as evidence for [and P Q] if [p]
is evidence for [P] and [q] is evidence for [Q]; and
- this is the _only_ way to give evidence for [and P Q] --
that is, if someone gives us evidence for [and P Q], we
know it must have the form [conj p q], where [p] is
evidence for [P] and [q] is evidence for [Q].
Since we'll be using conjunction a lot, let's introduce a more
familiar-looking infix notation for it. *)
Notation "P /\ Q" := (and P Q) : type_scope.
(** (The [type_scope] annotation tells Coq that this notation
will be appearing in propositions, not values.) *)
(** Consider the "type" of the constructor [conj]: *)
Check conj.
(* ===> forall P Q : Prop, P -> Q -> P /\ Q *)
(** Notice that it takes 4 inputs -- namely the propositions [P]
and [Q] and evidence for [P] and [Q] -- and returns as output the
evidence of [P /\ Q]. *)
(** ** "Introducing" conjunctions *)
(** Besides the elegance of building everything up from a tiny
foundation, what's nice about defining conjunction this way is
that we can prove statements involving conjunction using the
tactics that we already know. For example, if the goal statement
is a conjuction, we can prove it by applying the single
constructor [conj], which (as can be seen from the type of [conj])
solves the current goal and leaves the two parts of the
conjunction as subgoals to be proved separately. *)
Theorem and_example :
(0 = 0) /\ (4 = mult 2 2).
Proof.
apply conj.
Case "left". reflexivity.
Case "right". reflexivity. Qed.
(** Just for convenience, we can use the tactic [split] as a shorthand for
[apply conj]. *)
Theorem and_example' :
(0 = 0) /\ (4 = mult 2 2).
Proof.
split.
Case "left". reflexivity.
Case "right". reflexivity. Qed.
(** ** "Eliminating" conjunctions *)
(** Conversely, the [destruct] tactic can be used to take a
conjunction hypothesis in the context, calculate what evidence
must have been used to build it, and add variables representing
this evidence to the proof context. *)
Theorem proj1 : forall P Q : Prop,
P /\ Q -> P.
Proof.
intros P Q H.
destruct H as [HP HQ].
apply HP. Qed.
(** **** Exercise: 1 star, optional (proj2) *)
Theorem proj2 : forall P Q : Prop,
P /\ Q -> Q.
Proof.
intros P Q H.
destruct H as [HP HQ].
apply HQ.
Qed.
(** [] *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
(* WORKED IN CLASS *)
intros P Q H.
destruct H as [HP HQ].
split.
Case "left". apply HQ.
Case "right". apply HP. Qed.
(** **** Exercise: 2 stars (and_assoc) *)
(** In the following proof, notice how the _nested pattern_ in the
[destruct] breaks the hypothesis [H : P /\ (Q /\ R)] down into
[HP: P], [HQ : Q], and [HR : R]. Finish the proof from there: *)
Theorem and_assoc : forall P Q R : Prop,
P /\ (Q /\ R) -> (P /\ Q) /\ R.
Proof.
intros P Q R H.
destruct H as [HP [HQ HR]].
split.
Case "P /\ Q".
split.
SCase "P". apply HP.
SCase "Q". apply HQ.
Case "R".
apply HR.
Qed.
(** [] *)
(* ###################################################### *)
(** * Iff *)
(** The handy "if and only if" connective is just the conjunction of
two implications. *)
Definition iff (P Q : Prop) := (P -> Q) /\ (Q -> P).
Notation "P <-> Q" := (iff P Q)
(at level 95, no associativity)
: type_scope.
Theorem iff_implies : forall P Q : Prop,
(P <-> Q) -> P -> Q.
Proof.
intros P Q H.
destruct H as [HAB HBA]. apply HAB. Qed.
Theorem iff_sym : forall P Q : Prop,
(P <-> Q) -> (Q <-> P).
Proof.
(* WORKED IN CLASS *)
intros P Q H.
destruct H as [HAB HBA].
split.
Case "->". apply HBA.
Case "<-". apply HAB. Qed.
(** **** Exercise: 1 star, optional (iff_properties) *)
(** Using the above proof that [<->] is symmetric ([iff_sym]) as
a guide, prove that it is also reflexive and transitive. *)
Theorem iff_refl : forall P : Prop,
P <-> P.
Proof.
intros P.
split.
intros HP. apply HP.
intros HP. apply HP.
Qed.
Theorem iff_trans : forall P Q R : Prop,
(P <-> Q) -> (Q <-> R) -> (P <-> R).
Proof.
intros P Q R PQ QR.
split.
Case "P -> R".
destruct PQ as [HPQ HQP].
destruct QR as [HQR HRQ].
intros HP.
apply HQR.
apply HPQ.
apply HP.
Case "P <- R".
destruct PQ as [HPQ HQP].
destruct QR as [HQR HRQ].
intros HR.
apply HQP.
apply HRQ.
apply HR.
Qed.
(** Hint: If you have an iff hypothesis in the context, you can use
[inversion] to break it into two separate implications. (Think
about why this works.) *)
(** [] *)
(** Some of Coq's tactics treat [iff] statements specially, thus
avoiding the need for some low-level manipulation when reasoning
with them. In particular, [rewrite] can be used with [iff]
statements, not just equalities. *)
(* ############################################################ *)
(** * Disjunction (Logical "or") *)
(** ** Implementing disjunction *)
(** Disjunction ("logical or") can also be defined as an
inductive proposition. *)
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
Notation "P \/ Q" := (or P Q) : type_scope.
(** Consider the "type" of the constructor [or_introl]: *)
Check or_introl.
(* ===> forall P Q : Prop, P -> P \/ Q *)
(** It takes 3 inputs, namely the propositions [P], [Q] and
evidence of [P], and returns, as output, the evidence of [P \/ Q].
Next, look at the type of [or_intror]: *)
Check or_intror.
(* ===> forall P Q : Prop, Q -> P \/ Q *)
(** It is like [or_introl] but it requires evidence of [Q]
instead of evidence of [P]. *)
(** Intuitively, there are two ways of giving evidence for [P \/ Q]:
- give evidence for [P] (and say that it is [P] you are giving
evidence for -- this is the function of the [or_introl]
constructor), or
- give evidence for [Q], tagged with the [or_intror]
constructor. *)
(** *** *)
(** Since [P \/ Q] has two constructors, doing [destruct] on a
hypothesis of type [P \/ Q] yields two subgoals. *)
Theorem or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
destruct H as [HP | HQ].
Case "left". apply or_intror. apply HP.
Case "right". apply or_introl. apply HQ. Qed.
(** From here on, we'll use the shorthand tactics [left] and [right]
in place of [apply or_introl] and [apply or_intror]. *)
Theorem or_commut' : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
destruct H as [HP | HQ].
Case "left". right. apply HP.
Case "right". left. apply HQ. Qed.
Theorem or_distributes_over_and_1 : forall P Q R : Prop,
P \/ (Q /\ R) -> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R. intros H. destruct H as [HP | [HQ HR]].
Case "left". split.
SCase "left". left. apply HP.
SCase "right". left. apply HP.
Case "right". split.
SCase "left". right. apply HQ.
SCase "right". right. apply HR. Qed.
(** **** Exercise: 2 stars (or_distributes_over_and_2) *)
Theorem or_distributes_over_and_2 : forall P Q R : Prop,
(P \/ Q) /\ (P \/ R) -> P \/ (Q /\ R).
Proof.
intros P Q R H.
destruct H as [PQ PR].
destruct PQ as [HP | HQ].
Case "P".
left.
apply HP.
Case "Q".
destruct PR as [HP' | HR].
SCase "P".
left.
apply HP'.
SCase "R".
right.
split.
apply HQ.
apply HR.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (or_distributes_over_and) *)
Theorem or_distributes_over_and : forall P Q R : Prop,
P \/ (Q /\ R) <-> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R.
split.
Case "->".
intros H.
destruct H as [HP | [HQ HR]].
SCase "P".
split.
left. apply HP.
left. apply HP.
SCase "Q /\ R".
split.
right. apply HQ.
right. apply HR.
Case "<-".
intros H.
destruct H as [[HP | HQ] [HP' | HR]].
SCase "P". left. apply HP.
SCase "P R". left. apply HP.
SCase "Q P". left. apply HP'.
SCase "Q R". right. split. apply HQ. apply HR.
Qed.
(** [] *)
(* ################################################### *)
(** ** Relating [/\] and [\/] with [andb] and [orb] *)
(** We've already seen several places where analogous structures
can be found in Coq's computational ([Type]) and logical ([Prop])
worlds. Here is one more: the boolean operators [andb] and [orb]
are clearly analogs of the logical connectives [/\] and [\/].
This analogy can be made more precise by the following theorems,
which show how to translate knowledge about [andb] and [orb]'s
behaviors on certain inputs into propositional facts about those
inputs. *)
Theorem andb_prop : forall b c,
andb b c = true -> b = true /\ c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
destruct b.
Case "b = true". destruct c.
SCase "c = true". apply conj. reflexivity. reflexivity.
SCase "c = false". inversion H.
Case "b = false". inversion H. Qed.
Theorem andb_true_intro : forall b c,
b = true /\ c = true -> andb b c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
destruct H.
rewrite H. rewrite H0. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (andb_false) *)
Theorem andb_false : forall b c,
andb b c = false -> b = false \/ c = false.
Proof.
intros b c H.
destruct b, c.
Case "T T". inversion H.
Case "T F". right. reflexivity.
Case "F T". left. reflexivity.
Case "F F". left. reflexivity.
Qed.
(** **** Exercise: 2 stars, optional (orb_false) *)
Theorem orb_prop : forall b c,
orb b c = true -> b = true \/ c = true.
Proof.
intros b c H.
destruct b, c.
Case "T T". left. reflexivity.
Case "T F". left. reflexivity.
Case "F T". right. reflexivity.
Case "F F". inversion H.
Qed.
(** **** Exercise: 2 stars, optional (orb_false_elim) *)
Theorem orb_false_elim : forall b c,
orb b c = false -> b = false /\ c = false.
Proof.
intros b c H.
destruct b, c.
Case "T T". inversion H.
Case "T F". inversion H.
Case "F T". inversion H.
Case "F F". split. reflexivity. reflexivity.
Qed.
(** [] *)
(* ################################################### *)
(** * Falsehood *)
(** Logical falsehood can be represented in Coq as an inductively
defined proposition with no constructors. *)
Inductive False : Prop := .
(** Intuition: [False] is a proposition for which there is no way
to give evidence. *)
(** Since [False] has no constructors, inverting an assumption
of type [False] always yields zero subgoals, allowing us to
immediately prove any goal. *)
Theorem False_implies_nonsense :
False -> 2 + 2 = 5.
Proof.
intros contra.
inversion contra. Qed.
(** How does this work? The [inversion] tactic breaks [contra] into
each of its possible cases, and yields a subgoal for each case.
As [contra] is evidence for [False], it has _no_ possible cases,
hence, there are no possible subgoals and the proof is done. *)
(** *** *)
(** Conversely, the only way to prove [False] is if there is already
something nonsensical or contradictory in the context: *)
Theorem nonsense_implies_False :
2 + 2 = 5 -> False.
Proof.
intros contra.
inversion contra. Qed.
(** Actually, since the proof of [False_implies_nonsense]
doesn't actually have anything to do with the specific nonsensical
thing being proved; it can easily be generalized to work for an
arbitrary [P]: *)
Theorem ex_falso_quodlibet : forall (P:Prop),
False -> P.
Proof.
(* WORKED IN CLASS *)
intros P contra.
inversion contra. Qed.
(** The Latin _ex falso quodlibet_ means, literally, "from
falsehood follows whatever you please." This theorem is also
known as the _principle of explosion_. *)
(* #################################################### *)
(** ** Truth *)
(** Since we have defined falsehood in Coq, one might wonder whether
it is possible to define truth in the same way. We can. *)
(** **** Exercise: 2 stars, advanced (True) *)
(** Define [True] as another inductively defined proposition. (The
intution is that [True] should be a proposition for which it is
trivial to give evidence.) *)
(* FILL IN HERE *)
Inductive True :=
| truth : True.
(** [] *)
(** However, unlike [False], which we'll use extensively, [True] is
used fairly rarely. By itself, it is trivial (and therefore
uninteresting) to prove as a goal, and it carries no useful
information as a hypothesis. But it can be useful when defining
complex [Prop]s using conditionals, or as a parameter to
higher-order [Prop]s. *)
(* #################################################### *)
(** * Negation *)
(** The logical complement of a proposition [P] is written [not
P] or, for shorthand, [~P]: *)
Definition not (P:Prop) := P -> False.
(** The intuition is that, if [P] is not true, then anything at
all (even [False]) follows from assuming [P]. *)
Notation "~ x" := (not x) : type_scope.
Check not.
(* ===> Prop -> Prop *)
(** It takes a little practice to get used to working with
negation in Coq. Even though you can see perfectly well why
something is true, it can be a little hard at first to get things
into the right configuration so that Coq can see it! Here are
proofs of a few familiar facts about negation to get you warmed
up. *)
Theorem not_False :
~ False.
Proof.
unfold not. intros H. inversion H. Qed.
(** *** *)
Theorem contradiction_implies_anything : forall P Q : Prop,
(P /\ ~P) -> Q.
Proof.
(* WORKED IN CLASS *)
intros P Q H. destruct H as [HP HNA]. unfold not in HNA.
apply HNA in HP. inversion HP. Qed.
Theorem double_neg : forall P : Prop,
P -> ~~P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not. intros G. apply G. apply H. Qed.
(** **** Exercise: 2 stars, advanced (double_neg_inf) *)
(** Write an informal proof of [double_neg]:
_Theorem_: [P] implies [~~P], for any proposition [P].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars (contrapositive) *)
Theorem contrapositive : forall P Q : Prop,
(P -> Q) -> (~Q -> ~P).
Proof.
intros P Q HPQ.
unfold not.
intros HQ HP.
apply HPQ in HP.
apply HQ in HP.
inversion HP.
Qed.
(** [] *)
(** **** Exercise: 1 star (not_both_true_and_false) *)
Theorem not_both_true_and_false : forall P : Prop,
~ (P /\ ~P).
Proof.
intros P.
unfold not.
intros H.
destruct H as [HP HNP].
apply HNP in HP.
inversion HP.
Qed.
(** [] *)
(** **** Exercise: 1 star, advanced (informal_not_PNP) *)
(** Write an informal proof (in English) of the proposition [forall P
: Prop, ~(P /\ ~P)]. *)
(* FILL IN HERE *)
(** [] *)
(** *** Constructive logic *)
(** Note that some theorems that are true in classical logic are _not_
provable in Coq's (constructive) logic. E.g., let's look at how
this proof gets stuck... *)
Theorem classic_double_neg : forall P : Prop,
~~P -> P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not in H.
(* But now what? There is no way to "invent" evidence for [~P]
from evidence for [P]. *)
Abort.
(** **** Exercise: 5 stars, advanced, optional (classical_axioms) *)
(** For those who like a challenge, here is an exercise
taken from the Coq'Art book (p. 123). The following five
statements are often considered as characterizations of
classical logic (as opposed to constructive logic, which is
what is "built in" to Coq). We can't prove them in Coq, but
we can consistently add any one of them as an unproven axiom
if we wish to work in classical logic. Prove that these five
propositions are equivalent. *)
Definition peirce := forall P Q: Prop,
((P->Q)->P)->P.
Definition classic := forall P:Prop,
~~P -> P.
Definition excluded_middle := forall P:Prop,
P \/ ~P.
Definition de_morgan_not_and_not := forall P Q:Prop,
~(~P /\ ~Q) -> P\/Q.
Definition implies_to_or := forall P Q:Prop,
(P->Q) -> (~P\/Q).
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (excluded_middle_irrefutable) *)
(** This theorem implies that it is always safe to add a decidability
axiom (i.e. an instance of excluded middle) for any _particular_ Prop [P].
Why? Because we cannot prove the negation of such an axiom; if we could,
we would have both [~ (P \/ ~P)] and [~ ~ (P \/ ~P)], a contradiction. *)
Theorem excluded_middle_irrefutable: forall (P:Prop), ~ ~ (P \/ ~ P).
Proof.
intros P.
unfold not.
intros H.
apply H.
right.
intros HP.
apply H.
left.
apply HP.
Qed.
(* ########################################################## *)
(** ** Inequality *)
(** Saying [x <> y] is just the same as saying [~(x = y)]. *)
Notation "x <> y" := (~ (x = y)) : type_scope.
(** Since inequality involves a negation, it again requires
a little practice to be able to work with it fluently. Here
is one very useful trick. If you are trying to prove a goal
that is nonsensical (e.g., the goal state is [false = true]),
apply the lemma [ex_falso_quodlibet] to change the goal to
[False]. This makes it easier to use assumptions of the form
[~P] that are available in the context -- in particular,
assumptions of the form [x<>y]. *)
Theorem not_false_then_true : forall b : bool,
b <> false -> b = true.
Proof.
intros b H. destruct b.
Case "b = true". reflexivity.
Case "b = false".
unfold not in H.
apply ex_falso_quodlibet.
apply H. reflexivity. Qed.
(** *** *)
(** *** *)
(** *** *)
(** *** *)
(** *** *)
(** **** Exercise: 2 stars (false_beq_nat) *)
Theorem false_beq_nat : forall n m : nat,
n <> m ->
beq_nat n m = false.
Proof.
intros n.
induction n as [| n'].
Case "n = 0".
intros m H.
unfold not in H.
destruct m as [| m'].
SCase "m = 0".
simpl.
apply ex_falso_quodlibet.
apply H.
reflexivity.
SCase "m = S m'".
reflexivity.
Case "n = S n'".
intros m H.
unfold not in H.
destruct m as [| m'].
SCase "m = 0".
reflexivity.
SCase "m = S m'".
simpl.
apply IHn'.
unfold not.
intros Heq.
apply H.
apply f_equal.
apply Heq.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (beq_nat_false) *)
Theorem beq_nat_false : forall n m,
beq_nat n m = false -> n <> m.
Proof.
intros n.
induction n as [| n'].
Case "n = 0".
unfold not.
intros m H.
destruct m as [| m'].
SCase "m = 0".
apply ex_falso_quodlibet.
inversion H.
SCase "m = S m'".
intros contra.
inversion contra.
Case "n = S n'".
unfold not.
intros m H.
destruct m as [| m'].
SCase "m = 0".
intros contra.
inversion contra.
SCase "m = S m'".
simpl in H.
apply IHn' in H.
unfold not in H.
intros Eq.
apply H.
inversion Eq.
reflexivity.
Qed.
(** [] *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
//Autogenerated verilog on 2015-05-13 11:01:32.310768
`timescale 1 ns / 1 ps
module rbo_test
(
input clk,
output reg CAL,
output CS,
output reg IS1,
output reg IS2,
output reg LE,
output reg R12,
output reg RBI,
output reg RESET,
output reg RPHI1,
output reg RPHI2,
output reg SBI,
output reg SEB,
output reg SPHI1,
output reg SPHI2,
output reg SR,
output [15:0]Aref,
output [15:0]RG,
output [15:0]Vana,
output [15:0]Vthr,
input reset_gen
);
reg [31:0]counter;
reg [7:0]stage;
reg [15:0]stage_iter;
assign CS=0;
assign Vthr=16'H0025;
assign Aref=16'H0033;
assign Vana=16'H0066;
assign RG=16'H0033;
always @(posedge clk) begin
if(reset_gen == 1) begin
counter <= 0;
stage <= 0;
stage_iter <= 0;
end
else begin
if(stage == 0) begin
if(counter == 0) begin
CAL <= 0;
SBI <= 0;
SPHI1 <= 0;
SPHI2 <= 0;
SEB <= 1;
IS1 <= 1;
IS2 <= 0;
SR <= 1;
RESET <= 1;
R12 <= 1;
RBI <= 0;
RPHI1 <= 1;
RPHI2 <= 1;
LE <= 0;
end
if(counter == 7) begin
RBI <= 1;
end
if(counter == 16) begin
RBI <= 0;
end
if(counter == 22) begin
RPHI1 <= 0;
RPHI2 <= 0;
end
if(counter == 24) begin
RBI <= 1;
end
if(counter == 25) begin
RPHI1 <= 1;
end
if(counter == 26) begin
RPHI1 <= 0;
end
if(counter == 27) begin
RBI <= 0;
end
if(counter == 28) begin
RPHI2 <= 1;
end
if(counter == 29) begin
RPHI2 <= 0;
end
if(counter == 29) begin
if(stage_iter == 0) begin
stage <= (stage + 1) % 2;
stage_iter <= 0;
end
else begin
stage_iter <= stage_iter + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
if(stage == 1) begin
if(counter == 0) begin
CAL <= 0;
SBI <= 0;
SPHI1 <= 0;
SPHI2 <= 0;
SEB <= 1;
IS1 <= 1;
IS2 <= 0;
SR <= 1;
RESET <= 1;
R12 <= 1;
RBI <= 0;
RPHI1 <= 1;
RPHI2 <= 0;
LE <= 0;
end
if(counter == 1) begin
RPHI1 <= 0;
end
if(counter == 2) begin
RPHI2 <= 1;
end
if(counter == 3) begin
RPHI2 <= 0;
end
if(counter == 3) begin
if(stage_iter == 128) begin
stage <= (stage + 1) % 2;
stage_iter <= 0;
end
else begin
stage_iter <= stage_iter + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
end
end
endmodule |
module test_processor();
reg clk,reset;
wire [15:0] IR,ALUreg_wire,A_out_wire,B_out_wire,PC_out_wire,ALU_out_wire;
wire N, Z, P,Mux11,wrf,wpc,wir,lccr,wmem,wa,wb, lalu;
wire [1:0] Mux2,Mux4,Mux5,Mux6,Mux7,aluop,alushop;
wire [2:0] Mux3;
wire [4:0] StateID;
lc_3b_processor processor1(clk,reset,IR,N,Z,P,StateID,Mux1,Mux2,Mux3,Mux4,Mux5,Mux6,Mux7,Mux11,wrf,wpc,wir,lccr,aluop,alushop,
wmem,ALUreg_wire,A_out_wire,B_out_wire,PC_out_wire,ALU_out_wire,wa,wb, lalu);
initial begin
$dumpfile("test.vcd");
$dumpvars(0);
clk = 0;
reset = 0;
#15
reset = 1;
#500
$finish;
end
always begin
#5
clk = ~clk;
end
endmodule
//----------------------------------------------------------------------------------------
module lc_3b_processor(clk,reset,IR,N,Z,P,StateID,Mux1,Mux2,Mux3,Mux4,Mux5,Mux6,Mux7,Mux11,wrf,wpc,wir,lccr,aluop,alushop,
wmem,ALUreg_wire,A_out_wire,B_out_wire,PC_out_wire,ALU_out_wire,wa,wb, lalu);
input clk,reset;
output [15:0] IR;
output N, Z, P;
output [4:0] StateID;
output Mux1;
output [1:0] Mux2;
output [2:0] Mux3;
output [1:0] Mux4;
output [1:0] Mux5;
output [1:0] Mux6;
output [1:0] Mux7;
output Mux11;
output wrf;
output wpc;
output wir;
output lccr;
output [1:0] aluop;
output [1:0] alushop;
output wmem;
output wire wa,wb, lalu;
output [15:0]ALUreg_wire,A_out_wire,B_out_wire,PC_out_wire,ALU_out_wire;
datapath d1(.reset(reset),.clk(clk),.IR(IR),.N(N), .P(P), .Z(Z), .Mux1(Mux1), .Mux2(Mux2), .Mux3(Mux3), .Mux4(Mux4),
.Mux5(Mux5), .Mux6(Mux6), .Mux7(Mux7), .Mux11(Mux11), .wrf(wrf), .wpc(wpc), .wir(wir), .lccr(lccr), .aluop(aluop),
.alushop(alushop), .wmem(wmem), .ALUreg_wire(ALUreg_wire), .A_out_wire(A_out_wire), .B_out_wire(B_out_wire),
.PC_out_wire(PC_out_wire), .ALU_out_wire(ALU_out_wire),.wa(wa),.wb(wb), .lalu(lalu));
controller c1(.reset(reset),.clk(clk), .IR(IR), .N(N), .Z(Z), .P(P), .StateID(StateID), .Mux1(Mux1), .Mux2(Mux2), .Mux3(Mux3),
.Mux4(Mux4), .Mux5(Mux5), .Mux6(Mux6), .Mux7(Mux7), .Mux11(Mux11), .wrf(wrf), .wpc(wpc), .wir(wir),
.lccr(lccr), .aluop(aluop), .alushop(alushop), .wmem(wmem),.wa(wa),.wb(wb), .lalu(lalu));
endmodule
module controller(reset,clk, IR, N, Z, P, StateID, Mux1, Mux2, Mux3, Mux4, Mux5, Mux6, Mux7, Mux11, wrf, wpc, wir,wa,wb, lccr, aluop, alushop, wmem, nextStateID, lalu); // Implements the designed controller for LC-3b.
input [15:0] IR;
input clk, N, Z, P,reset;
output reg [4:0] StateID;
output reg Mux1;
output reg [1:0] Mux2;
output reg [2:0] Mux3;
output reg [1:0] Mux4;
output reg [1:0] Mux5;
output reg [1:0] Mux6;
output reg [1:0] Mux7;
output reg Mux11;
output reg wrf;
output reg wpc;
output reg wir;
output reg wa;
output reg wb;
output reg lalu;
output reg lccr;
output reg [1:0] aluop;
output reg [1:0] alushop;
output reg wmem;
output reg [4:0] nextStateID;
always@(negedge clk) begin
case(StateID)
1: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b01;
Mux5 = 2'b01;
Mux6 = 2'b10;
Mux7 = 2'b10;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b0;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
2: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b000;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b0;
wb = 1'b0;
lalu = 1'b1;
end
3: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b000;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = {IR[15], IR[14]};
alushop = {IR[5], IR[4]};
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b0;
end
4: begin
Mux1 = 1'b1;
Mux2 = 2'b01;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
5: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b011;
Mux4 = 2'b01;
Mux5 = 2'b00;
Mux6 = 2'b00;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
6: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
7: begin
Mux1 = 1'b1;
Mux2 = 2'b10;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
8: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b001;
Mux4 = 2'b01;
Mux5 = 2'b00;
Mux6 = 2'b01;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
9: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b101;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b0;
end
10: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b01;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
11: begin
Mux1 = 1'b1;
Mux2 = 2'b00;
Mux3 = 3'b111;
Mux4 = 2'b10;
Mux5 = 2'b10;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
12: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b010;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b0;
end
13: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b011;
Mux4 = 2'b01;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b0;
end
14: begin
Mux1 = 1'b1;
Mux2 = 2'b01;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
15: begin
Mux1 = 1'b0;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b0;
wb = 1'b0;
lalu = 1'b1;
end
16: begin
Mux1 = 1'b0;
Mux2 = 2'b11;
Mux3 = 3'b101;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
end
17: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b01;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b0;
wa = 1'b1;
wb = 1'b1;
end
18: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b010;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
end
default: begin
Mux1 = 1'b0;
Mux2 = 2'b00;
Mux3 = 3'b000;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b00;
Mux7 = 2'b00;
Mux11 = 1'b0;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b0;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b00;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
end
endcase
StateID = nextStateID;
end
always@(*) begin
if(reset ==0)
StateID = 0;
else
begin
case(StateID)
0: nextStateID=1;
1: begin
case(IR[15:12])
0: nextStateID=5;
4: nextStateID=7;
3: nextStateID=15;
7: nextStateID=15;
default: nextStateID=2;
endcase
end
2: begin
case(IR[15:12])
12: nextStateID=6;
2: nextStateID=9;
6: nextStateID=12;
4: nextStateID=8;
14: nextStateID=13;
default: nextStateID=3;
endcase
end
3: nextStateID=4;
4: nextStateID=1;
5: nextStateID=1;
6: nextStateID=1;
7: nextStateID=2;
8: nextStateID=1;
9: nextStateID=10;
10: nextStateID=11;
11: nextStateID=1;
12: nextStateID=10;
13: nextStateID=14;
14: nextStateID=1;
15: begin
case(IR[15:12])
3: StateID = 16;
7: StateID = 18;
default: nextStateID=1;
endcase
end
16: nextStateID=17;
17: nextStateID=1;
18: nextStateID=17;
default: nextStateID=1;
endcase
end
end
endmodule
module datapath(reset,clk,IR,N,P,Z,Mux1,Mux2,Mux3,Mux4,Mux5,Mux6,Mux7,Mux11,wrf, wpc, wir, wa,wb,lccr, aluop, alushop, wmem
,ALUreg_wire,A_out_wire,B_out_wire,PC_out_wire,ALU_out_wire, mem_out_wire, mdr_wire, lalu);
input clk,reset;
output [15:0]IR;
input Mux1,Mux11;
input [1:0] Mux2,Mux4,Mux5,Mux6,Mux7;
input [2:0]Mux3;
output N,P,Z;
input wrf, wpc, wir, lccr, wmem,wa,wb, lalu;
input[1:0] aluop, alushop;
output [15:0]ALUreg_wire,A_out_wire,B_out_wire,PC_out_wire,ALU_out_wire;//
wire [15:0] A_out_wire,ALUreg_wire,PC_out_wire,mem_address_wire;
wire[15:0] mux6_in_1_wire,mux6_in_0_wire;
output wire[15:0] mem_out_wire, mdr_wire,outir;
mux16x2 m7(.data0(A_out_wire),.data1(ALUreg_wire),.data2(PC_out_wire),.data3(PC_out_wire),.selectinput(Mux7),.out(mem_address_wire));//data3 is never slelcted(just done this to prevent latch formation
mem16 memory(.outir(outir),.address(mem_address_wire), .write(wmem),.clk(clk), .in(A_out_wire),.out(mem_out_wire),.ir14(IR[14]), .reset(reset));
latch16 inst_reg(.in(outir),.out(IR),.write(wir));
latch16 mdr(.in(mem_out_wire),.out(mdr_wire),.write(1'b0));
wire [2:0] IA1_wire,WA_wire;
mux3x1 m1(.data0(IR[11:9]),.data1(IR[8:6]),.selectinput(Mux1),.out(IA1_wire));
mux3x1 m11(.data0(IR[11:9]),.data1(3'd7),.selectinput(Mux11),.out(WA_wire)); // Is this right ?
wire [15:0]reg_file_data_in_wire;
mux16x2 m2(.data0(mdr_wire),.data1(ALUreg_wire),.data2(PC_out_wire),.data3(PC_out_wire),.selectinput(Mux2),.out(reg_file_data_in_wire));
wire[15:0] A_in_wire,B_in_wire,regfile_out2_wire;
register_file rf1(.clk(clk), .out1(A_in_wire), .out2(regfile_out2_wire),
.readAdd1(IA1_wire),.readAdd2(IR[2:0]),.write(wrf),.writeAdd(WA_wire),.in(reg_file_data_in_wire), .reset(reset));
wire[15:0] sext11_0_wire, sext8_0_wire,sext5_0_wire;
sext12 s11_0(.in(IR[11:0]),.out(sext11_0_wire));
sext9 s8_0(.in(IR[8:0]),.out(sext8_0_wire));
sext6 s5_0(.in(IR[5:0]),.out(sext5_0_wire));
wire[15:0] lshf11_0_wire, lshf8_0_wire,lshf5_0_wire;
lshift1 lshf11_0(.in(sext11_0_wire),.out(lshf11_0_wire));
lshift1 lshf8_0(.in(sext8_0_wire),.out(lshf8_0_wire));
lshift1 lshf5_0(.in(sext5_0_wire),.out(lshf5_0_wire));
wire [15:0] mux3_in_0_wire;
mux16x1 m8(.data0(regfile_out2_wire),.data1(sext5_0_wire),.selectinput(IR[5]),.out(mux3_in_0_wire));
mux16x3 m3(.data0(mux3_in_0_wire),.data1(lshf11_0_wire),.data2(lshf5_0_wire),.data3(lshf8_0_wire),.data4(sext11_0_wire),.data5(sext5_0_wire),.selectinput(Mux3),.out(B_in_wire));
wire[15:0] B_out_wire;
register16 A (.clk(clk), .out(A_out_wire),.in(A_in_wire),.write(wa),.reset(reset));
register16 B (.clk(clk), .out(B_out_wire),.in(B_in_wire),.write(wb),.reset(reset));
wire[15:0] ALU_in_1_wire,ALU_in_2_wire;
mux16x2 m4(.data0(A_out_wire),.data1(PC_out_wire),.data2(mdr_wire),.data3(mdr_wire),.selectinput(Mux4),.out(ALU_in_1_wire));
mux16x2 m5 (.data0(B_out_wire),.data1(16'd2),.data2(16'd0),.data3(16'd0),.selectinput(Mux5),.out(ALU_in_2_wire));
wire[15:0]ALU_out_wire;
wire zero,negative,positive;
alu ALU(.in1(ALU_in_1_wire), .in2(ALU_in_2_wire),.op(aluop), .shop(alushop),.shift(IR[3:0]), .out(ALU_out_wire), .zero(zero),.positive(positive),.negative(negative));
register1b neg_reg(.clk(clk),.out(N),.in(negative),.write(lccr),.reset(reset));
register1b pos_reg(.clk(clk),.out(P),.in(positive),.write(lccr),.reset(reset));
register1b zero_reg(.clk(clk),.out(Z),.in(zero),.write(lccr),.reset(reset));
wire[15:0] PC_in_wire;
register16 PC (.clk(clk), .out(PC_out_wire),.in(PC_in_wire),.write(wpc),.reset(reset));
wire hc;
assign hc =( (IR[11]&&N)|| (IR[10]&&Z)||(IR[9]&&P));
mux16x1 m9(.data0(PC_out_wire),.data1(ALU_out_wire),.selectinput(hc),.out(mux6_in_0_wire));
register16 ALUreg(.clk(clk),.out(ALUreg_wire),.in(ALU_out_wire),.write(lalu),.reset(reset));
mux16x1 m10(.data0(ALU_out_wire),.data1(A_out_wire),.selectinput(IR[11]),.out(mux6_in_1_wire));
mux16x2 m6(.data0(mux6_in_0_wire),.data1(mux6_in_1_wire),.data2(ALU_out_wire),.data3(A_out_wire),.selectinput(Mux6),.out(PC_in_wire));
endmodule
module sext9(in,out);
input [8:0] in;
output[15:0] out;
assign out= {{7{in[8]}},in[8:0]};
endmodule
module sext12(in,out);
input [11:0] in;
output[15:0] out;
assign out= {{4{in[11]}},in[11:0]};
endmodule
module sext6(in,out);
input [5:0] in;
output[15:0] out;
assign out= {{10{in[5]}},in[5:0]};
endmodule
module register16(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [15:0] out;
input [15:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 16'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register1b(clk, out, in, write, reset); // Negedge-triggered 1 bit flipflop register for with active-low write signal and reset
output reg out;
input in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 1'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register_file(clk, out1, out2, readAdd1, readAdd2, write, writeAdd, in, reset);
output [15:0] out1, out2;
input [15:0] in;
input [2:0] readAdd1, readAdd2, writeAdd;
input write, clk, reset;
wire [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
wire [7:0] writeLinesInit, writeLines;
demux8 dem(writeAdd, writeLinesInit);
mux16x8 mux1(data0, data1, data2, data3, data4, data5, data6, data7, readAdd1, out1);
mux16x8 mux2(data0, data1, data2, data3, data4, data5, data6, data7, readAdd2, out2);
or a0(writeLines[0], write, ~writeLinesInit[0]);
or a1(writeLines[1], write, ~writeLinesInit[1]);
or a2(writeLines[2], write, ~writeLinesInit[2]);
or a3(writeLines[3], write, ~writeLinesInit[3]);
or a4(writeLines[4], write, ~writeLinesInit[4]);
or a5(writeLines[5], write, ~writeLinesInit[5]);
or a6(writeLines[6], write, ~writeLinesInit[6]);
or a7(writeLines[7], write, ~writeLinesInit[7]);
register16 r0(clk, data0, in, writeLines[0], reset);
register16 r1(clk, data1, in, writeLines[1], reset);
register16 r2(clk, data2, in, writeLines[2], reset);
register16 r3(clk, data3, in, writeLines[3], reset);
register16 r4(clk, data4, in, writeLines[4], reset);
register16 r5(clk, data5, in, writeLines[5], reset);
register16 r6(clk, data6, in, writeLines[6], reset);
register16 r7(clk, data7, in, writeLines[7], reset);
endmodule
module mux16x1(data0,data1,selectinput,out);//used in mux 1,8,9,10,11
input [15:0] data0,data1;
input selectinput;
output reg [15:0] out;
always @(*)
begin
case (selectinput)
0:
out = data0;
1:
out = data1;
default:
out = data0;
endcase
end
endmodule
module mux3x1(data0,data1,selectinput,out);//used in mux 1,8,9,10,11
input [2:0] data0,data1;
input selectinput;
output reg [2:0] out;
always @(*)
begin
case (selectinput)
0:
out = data0;
1:
out = data1;
default:
out = data0;
endcase
end
endmodule
module mux16x2(data0,data1,data2,data3,selectinput,out);//used in mux 2,4,5,6,7
input [15:0] data0,data1,data2,data3;
input [1:0]selectinput;
output reg [15:0] out;
always @(*)
begin
case (selectinput)
0:
out = data0;
1:
out = data1;
2:
out = data2;
3:
out = data3;
default:
out = data0;
endcase
end
endmodule
module mux16x3(data0,data1,data2,data3,data4,data5,selectinput,out);//used in mux 2,4,5,6,7
input [15:0] data0,data1,data2,data3,data4,data5;
input [2:0]selectinput;
output reg [15:0] out;
always @(*)
begin
case (selectinput)
0:
out = data0;
1:
out = data1;
2:
out = data2;
3:
out = data3;
4:
out = data4;
5:
out = data5;
default:
out = data0;
endcase
end
endmodule
module muxalu(data0, data1, data2, data3, data4, data5, op, shop, out); // 8-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3, data4, data5;
input [1:0] op;
input [1:0]shop;
always@(*) begin
case(op)
0: out = data0;
1: out = data1;
2: out = data2;
default:
case(shop)
0: out = data3;
1: out = data4;
3: out = data5;
default: out = data5;
endcase
endcase
end
endmodule
module mux16x8(data0, data1, data2, data3, data4, data5, data6, data7, selectInput, out); // 8-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
input [2:0] selectInput;
always@(data0 or data1 or data2 or data3 or data4 or data5 or data6 or data7 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
4: out = data4;
5: out = data5;
6: out = data6;
7: out = data7;
endcase
end
endmodule
module memory1(reset,address,in,out,write,clk, testWire); // LSB
input [7:0] in;
input clk,write,reset;
input [14:0] address;
output reg [7:0] out;
output wire [7:0] testWire;
reg [7:0] mem [0:255];
integer i;
assign testWire = mem[0];
always @(negedge clk)
begin
out = mem[address];
if(reset== 1'b0)
begin
for(i=0;i<256;i=i+1)
mem [i] = 0;
mem[0] = 8'b00111111;
mem[1] = 8'b00000000;
mem[2] = 8'b10000001;
end
else
if(write ==1'b0)
begin
mem[address] <= in;
end
end
endmodule
module memory2(reset,address,in,out,write,clk, testWire); // MSB
input [7:0] in;
input clk,write,reset;
input [14:0] address;
output reg [7:0] out;
output wire [7:0] testWire;
reg [7:0] mem [0:255];
integer i;
assign testWire = mem[0];
always @(negedge clk)
begin
out = mem[address];
if(reset== 1'b0)
begin
for(i=0;i<256;i=i+1)
mem [i] = 0;
mem[0] = 8'b10010010;
mem[1] = 8'b01100100;
mem[2] = 8'b00010110;
end
if(write ==1'b0)
begin
mem[address] <= in;
end
end
endmodule
module mem16(reset,address, write,clk, in, out,ir14,outir);
input [15:0] in;
input [15:0] address;
input write,clk,ir14,reset;
output reg [15:0] out;
output [15:0]outir;
reg wreven,wrodd;
wire [7:0] outeven,outodd;
reg [7:0] ineven,inodd;
memory1 even(.reset(reset),.address(address[15:1]),.in(ineven),.out(outeven),.clk(clk),.write(wreven));
memory2 odd (.reset(reset),.address(address[15:1]),.in(inodd),.out(outodd),.clk(clk),.write(wrodd));
//for in signals of individual memories
always @(*)
begin
if(ir14==0)
begin
ineven<=in[7:0];
inodd<=in[7:0];
end
else
begin
ineven<= in[7:0];
inodd<=in[15:8];
end
end
//-----------------------------------------------
assign outir[15:8] = outodd;
assign outir[7:0] = outeven;
//for out signals of individual memories
always @(*)
begin
if(ir14 ==1'b1)
begin
out[15:8]<=outodd;
out[7:0]<=outeven;
end
else
if(address[0]==0)
begin
out<= {{8{outeven[7]}},outeven[7:0]};
end
else
begin
out<= {{8{outodd[7]}},outodd[7:0]};
end
end
//-------------------------------------------------
//for write signal
always @(*)
begin
if(ir14==0&&address[0]==1'b1)
begin
wreven<=1'b1;
end
else
begin
wreven<=write;
end
end
always @(*)
begin
if(ir14==0&&address[0]==1'b0)
begin
wrodd<=1'b1;
end
else
begin
wrodd<=write;
end
end
endmodule
module lshift1(in,out);
input [15:0] in;
output [15:0] out;
assign out = {in[14:0],1'b0};
endmodule
module latch16(in,out,write);
input [15:0]in;
input write;//active low wrie
output reg [15:0] out;
always @(*)
begin
if(write == 1'b0)
out = in;
else
out = out;
end
endmodule
module demux8(selectInput, out); // 8-output demux
output reg [7:0] out;
input [2:0] selectInput;
always@(selectInput) begin
case(selectInput)
0: out = 8'b00000001;
1: out = 8'b00000010;
2: out = 8'b00000100;
3: out = 8'b00001000;
4: out = 8'b00010000;
5: out = 8'b00100000;
6: out = 8'b01000000;
7: out = 8'b10000000;
endcase
end
endmodule
module alu(in1, in2, op,shop,shift, out, zero, positive, negative);
output [15:0] out;
input [15:0] in1, in2;
input [1:0] op,shop;
input [3:0] shift;
output zero, positive,negative;
nor n1(zero,out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7],out[8],out[9],out[10],out[11],out[12],out[13],out[14],out[15]);
assign positive = (~out[15])&(~zero);
assign negative = out[15];
wire [15:0] outAdd, outAnd, outXor, outLshf, outRshfl, outRshfa;
muxalu m1(outAdd, outAnd, outXor, outLshf, outRshfl, outRshfa, op, shop, out);
adder16 add1(in1, in2, outAdd);
and16 and1(in1, in2, outAnd);
xor16 xor1(in1, in2, outXor);
left_shift lshf1(in1, outLshf, shift);
right_shift_logical rshfl1(in1, outRshfl, shift);
right_shift_arithmetic rshfa1(in1, outRshfa, shift);
endmodule
module adder16(in1, in2 , out); // Implements a full 16-bit adder
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 + in2;
endmodule
module and16(in1, in2, out); // Implements bitwise AND for two 16-bit numbers
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 & in2;
endmodule
module left_shift(in, out, shift);
output [15:0] out;
input [15:0] in;
input [3:0] shift;
assign out = in << shift;
endmodule
module right_shift_arithmetic(in, out, shift);
output reg [15:0] out;
input [15:0] in;
input [3:0] shift;
always @(*) begin
case(shift)
4'd0: out=in;
4'd1: out={in[15],in[15:1]};
4'd2: out={{2{in[15]}},in[15:2]};
4'd3: out={{3{in[15]}},in[15:3]};
4'd4: out={{4{in[15]}},in[15:4]};
4'd5: out={{5{in[15]}},in[15:5]};
4'd6: out={{6{in[15]}},in[15:6]};
4'd7: out={{7{in[15]}},in[15:7]};
4'd8: out={{8{in[15]}},in[15:8]};
4'd9: out={{9{in[15]}},in[15:9]};
4'd10: out={{10{in[15]}},in[15:10]};
4'd11: out={{11{in[15]}},in[15:11]};
4'd12: out={{12{in[15]}},in[15:12]};
4'd13: out={{13{in[15]}},in[15:13]};
4'd14: out={{14{in[15]}},in[15:14]};
4'd15: out={16{in[15]}};
endcase
end
endmodule
module right_shift_logical(in, out, shift);
output [15:0] out;
input [15:0] in;
input [3:0] shift;
assign out = in >> shift;
endmodule
module xor16(in1, in2, out); // Implements bitwise XOR for two 16-bit numbers
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 ^ in2;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_TB_V
`define SKY130_FD_SC_LS__FILL_TB_V
/**
* fill: Fill cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fill.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__fill dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_TB_V
|
/***************************************************************************************************
* *
* Module: Altera_UP_PS2 *
* Description: *
* This module communicates with the PS2 core. *
* Retrived from: http://www.eecg.toronto.edu/~jayar/ece241_08F/AudioVideoCores/ps2/ps2.html *
***************************************************************************************************/
module PS2_Controller #(parameter INITIALIZE_MOUSE = 0) (
// Inputs
CLOCK_50,
reset,
the_command,
send_command,
// Bidirectionals
PS2_CLK, // PS2 Clock
PS2_DAT, // PS2 Data
// Outputs
command_was_sent,
error_communication_timed_out,
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input reset;
input [7:0] the_command;
input send_command;
// Bidirectionals
inout PS2_CLK;
inout PS2_DAT;
// Outputs
output command_was_sent;
output error_communication_timed_out;
output [7:0] received_data;
output received_data_en;
wire [7:0] the_command_w;
wire send_command_w, command_was_sent_w, error_communication_timed_out_w;
generate
if(INITIALIZE_MOUSE) begin
assign the_command_w = init_done ? the_command : 8'hf4;
assign send_command_w = init_done ? send_command : (!command_was_sent_w && !error_communication_timed_out_w);
assign command_was_sent = init_done ? command_was_sent_w : 0;
assign error_communication_timed_out = init_done ? error_communication_timed_out_w : 1;
reg init_done;
always @(posedge CLOCK_50)
if(reset) init_done <= 0;
else if(command_was_sent_w) init_done <= 1;
end else begin
assign the_command_w = the_command;
assign send_command_w = send_command;
assign command_was_sent = command_was_sent_w;
assign error_communication_timed_out = error_communication_timed_out_w;
end
endgenerate
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire ps2_clk_posedge;
wire ps2_clk_negedge;
wire start_receiving_data;
wire wait_for_incoming_data;
// Internal Registers
reg [7:0] idle_counter;
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
// State Machine Registers
reg [2:0] ns_ps2_transceiver;
reg [2:0] s_ps2_transceiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
s_ps2_transceiver <= PS2_STATE_0_IDLE;
else
s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*)
begin
// Defaults
ns_ps2_transceiver = PS2_STATE_0_IDLE;
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if ((idle_counter == 8'hFF) &&
(send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else
ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
if ((received_data_en == 1'b1)/* && (ps2_clk_posedge == 1'b1)*/)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if ((command_was_sent == 1'b1) ||
(error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if (send_command == 1'b0)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if (received_data_en == 1'b1)
begin
if (send_command == 1'b0)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else
begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= PS2_CLK;
ps2_data_reg <= PS2_DAT;
end
end
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
idle_counter <= 6'h00;
else if ((s_ps2_transceiver == PS2_STATE_0_IDLE) &&
(idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign ps2_clk_posedge =
((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge =
((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data =
(s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_PS2_Data_In PS2_Data_In (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
// Bidirectionals
// Outputs
.received_data (received_data),
.received_data_en (received_data_en)
);
Altera_UP_PS2_Command_Out PS2_Command_Out (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.the_command (the_command_w),
.send_command (send_command_w),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
// Bidirectionals
.PS2_CLK (PS2_CLK),
.PS2_DAT (PS2_DAT),
// Outputs
.command_was_sent (command_was_sent_w),
.error_communication_timed_out (error_communication_timed_out_w)
);
endmodule
|
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ([email protected])
//
// Brief Description:
// Parallelized LFSR w/ PRBS vector. PRBS goes from MSb -> LSb.
//
//------------------------------------------------------------------------------
`ifndef _ZL_LFSR_V_
`define _ZL_LFSR_V_
module zl_lfsr #
(
parameter LFSR_poly = 0,
parameter LFSR_width = 0,
parameter LFSR_init_value = 0,
parameter PRBS_width = 0
)
(
input clk,
input rst_n,
//
input stall,
input clear,
output [LFSR_width-1:0] lfsr_state,
output [PRBS_width-1:0] prbs
);
reg [LFSR_width-1:0] state_reg;
reg [LFSR_width-1:0] state_next;
reg [PRBS_width-1:0] prbs_internal;
integer i;
function [LFSR_width-1:0] lfsr_state_next_serial;
input [LFSR_width-1:0] cur_state;
begin
lfsr_state_next_serial = {cur_state[LFSR_width-2:0],
^(cur_state & LFSR_poly[LFSR_width:1])};
end
endfunction
always @(*) begin
state_next = state_reg;
for(i=0;i<PRBS_width;i=i+1) begin
state_next = lfsr_state_next_serial(state_next);
prbs_internal[PRBS_width-i-1] = state_next[0];
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state_reg <= LFSR_init_value;
end
else if (clear && !stall) begin
state_reg <= LFSR_init_value;
end
else if (!stall) begin
state_reg <= state_next;
end
end
assign lfsr_state = state_reg;
assign prbs = prbs_internal;
endmodule // zl_lfsr
`endif // _ZL_LFSR_V_
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/30/2009
This block is used to communicate information back and forth between the SGDMA
and the host. When the response port is not set to streaming then this block
will be used to generate interrupts for the host. The address span of this block
differs depending on whether the enhanced features are enabled. The enhanced
features enables sequence number readback capabilties. The address map is as follows:
Enhanced features off:
Bytes Access Type Description
----- ----------- -----------
0-3 R Status(1)
4-7 R/W Control(2)
8-12 R Descriptor Watermark (write watermark[15:0],read watermark [15:0])
13-15 R Response Watermark
16-31 N/A <Reserved>
Enhanced features on:
Bytes Access Type Description
----- ----------- -----------
0-3 R Status(1)
4-7 R/W Control(2)
8-12 R Descriptor Watermark (write watermark[15:0],read watermark [15:0])
13-15 R Response Watermark
16-20 R Sequence Number (write sequence[15:0],read sequence[15:0])
21-31 N/A <Reserved>
(1) Writing to the interrupt bit of the status register clears the interrupt bit (when applicable)
(2) Writing to the software reset bit will clear the entire register (as well as all the registers for the entire SGDMA)
Status Register:
Bits Description
---- -----------
0 Busy
1 Descriptor Buffer Empty
2 Descriptor Buffer Full
3 Response Buffer Empty
4 Response Buffer Full
5 Stop State
6 Reset State
7 Stopped on Error
8 Stopped on Early Termination
9 IRQ
10-15 <Reserved>
15-31 Done count (JSF: Added 06/13/2011)
Control Register:
Bits Description
---- -----------
0 Stop (will also be set if a stop on error/early termination condition occurs)
1 Software Reset
2 Stop on Error
3 Stop on Early Termination
4 Global Interrupt Enable Mask
5 Stop descriptors (stops the dispatcher from issuing more read/write commands)
6-31 <Reserved>
Author: JCJB
Date: 08/18/2010
1.0 - Initial release
1.1 - Removed delayed reset, added set and hold sw_reset
1.2 - Updated the sw_reset register to be set when control[1] is set instead of one cycle after.
This will prevent the read or write masters from starting back up when reset while in the stop state.
1.3 - Added the stop dispatcher bit (5) to the control register
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module csr_block (
clk,
reset,
csr_writedata,
csr_write,
csr_byteenable,
csr_readdata,
csr_read,
csr_address,
csr_irq,
done_strobe,
busy,
descriptor_buffer_empty,
descriptor_buffer_full,
stop_state,
stopped_on_error,
stopped_on_early_termination,
reset_stalled,
stop,
sw_reset,
stop_on_error,
stop_on_early_termination,
stop_descriptors,
sequence_number,
descriptor_watermark,
response_watermark,
response_buffer_empty,
response_buffer_full,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
error,
early_termination
);
parameter ADDRESS_WIDTH = 3;
localparam CONTROL_REGISTER_ADDRESS = 3'b001;
input clk;
input reset;
input [31:0] csr_writedata;
input csr_write;
input [3:0] csr_byteenable;
output wire [31:0] csr_readdata;
input csr_read;
input [ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
input done_strobe;
input busy;
input descriptor_buffer_empty;
input descriptor_buffer_full;
input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to)
input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers
output wire stop;
output reg stopped_on_error;
output reg stopped_on_early_termination;
output reg sw_reset;
output wire stop_on_error;
output wire stop_on_early_termination;
output wire stop_descriptors;
input [31:0] sequence_number;
input [31:0] descriptor_watermark;
input [15:0] response_watermark;
input response_buffer_empty;
input response_buffer_full;
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input [7:0] error;
input early_termination;
/* Internal wires and registers */
wire [31:0] status;
reg [31:0] control;
reg [31:0] readdata;
reg [31:0] readdata_d1;
reg irq; // writing to the status register clears the irq bit
wire set_irq;
wire clear_irq;
reg [15:0] irq_count; // writing to bit 0 clears the counter
wire clear_irq_count;
wire incr_irq_count;
wire set_stopped_on_error;
wire set_stopped_on_early_termination;
wire set_stop;
wire clear_stop;
wire global_interrupt_enable;
wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset
wire set_sw_reset;
wire clear_sw_reset;
/********************************************** Registers ***************************************************/
// read latency is 1 cycle
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else if (csr_read == 1)
begin
readdata_d1 <= readdata;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[31:1] <= 0;
end
else
begin
if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset
begin
control[31:1] <= 0;
end
else
begin
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1))
begin
control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1))
begin
control[15:8] <= csr_writedata[15:8];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1))
begin
control[23:16] <= csr_writedata[23:16];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1))
begin
control[31:24] <= csr_writedata[31:24];
end
end
end
end
// control bit 0 (stop) is set by different sources so handling it seperately
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[0] <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
control[0] <= 0;
end
else
begin
case ({set_stop, clear_stop})
2'b00: control[0] <= control[0];
2'b01: control[0] <= 1'b0;
2'b10: control[0] <= 1'b1;
2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sw_reset <= 0;
end
else
begin
if (set_sw_reset == 1)
begin
sw_reset <= 1;
end
else if (clear_sw_reset == 1)
begin
sw_reset <= 0;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_error <= 0;
end
else
begin
case ({set_stopped_on_error, clear_stop})
2'b00: stopped_on_error <= stopped_on_error;
2'b01: stopped_on_error <= 1'b0;
2'b10: stopped_on_error <= 1'b1;
2'b11: stopped_on_error <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_early_termination <= 0;
end
else
begin
case ({set_stopped_on_early_termination, clear_stop})
2'b00: stopped_on_early_termination <= stopped_on_early_termination;
2'b01: stopped_on_early_termination <= 1'b0;
2'b10: stopped_on_early_termination <= 1'b1;
2'b11: stopped_on_early_termination <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
irq <= 0;
end
else
begin
case ({clear_irq, set_irq})
2'b00: irq <= irq;
2'b01: irq <= 1'b1;
2'b10: irq <= 1'b0;
2'b11: irq <= 1'b1; // setting will win over a clear
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq_count <= {16{1'b0}};
end
else
begin
if (sw_reset_strobe == 1)
begin
irq_count <= {16{1'b0}};
end
else
begin
case ({clear_irq_count, incr_irq_count})
2'b00: irq_count <= irq_count;
2'b01: irq_count <= irq_count + 1;
2'b10: irq_count <= {16{1'b0}};
2'b11: irq_count <= {{15{1'b0}}, 1'b1};
endcase
end
end
end
/******************************************** End Registers *************************************************/
/**************************************** Combinational Signals *********************************************/
generate
if (ADDRESS_WIDTH == 3)
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
3'b011: readdata = response_watermark;
default: readdata = sequence_number; // all other addresses will decode to the sequence number
endcase
end
end
else
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
default: readdata = response_watermark; // all other addresses will decode to the response watermark
endcase
end
end
endgenerate
assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit
assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled
((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled
((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled
((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled
assign csr_irq = irq;
// Done count
assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset
assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit
assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0);
assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared
assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared
assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit
(set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master
(set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows
assign stop = control[0];
assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1);
assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0);
assign sw_reset_strobe = control[1];
assign stop_on_error = control[2];
assign stop_on_early_termination = control[3];
assign global_interrupt_enable = control[4];
assign stop_descriptors = control[5];
assign csr_readdata = readdata_d1;
assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit
/**************************************** Combinational Signals *********************************************/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
/**
* udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
* (Q output UDP) with both active high reset and
* set (set dominate). Includes VPWR and VGND
* power pins and notifier pin.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$NSR_pp$PG$N (
Q ,
SET ,
RESET ,
CLK_N ,
D ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input SET ;
input RESET ;
input CLK_N ;
input D ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Apr 14 18:39:27 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top bd_auto_cc_0 -prefix
// bd_auto_cc_0_ bd_auto_cc_0_stub.v
// Design : bd_auto_cc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4" *)
module bd_auto_cc_0(s_axi_aclk, s_axi_aresetn, s_axi_awid,
s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache,
s_axi_awprot, s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata,
s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
s_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst,
s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid,
s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready,
m_axi_aclk, m_axi_aresetn, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awid[3:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[3:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[3:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[3:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_aclk,m_axi_aresetn,m_axi_awid[3:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[3:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[3:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[3:0],m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input s_axi_aclk;
input s_axi_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input m_axi_aclk;
input m_axi_aresetn;
output [3:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [3:0]m_axi_bid;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [3:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [3:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
module keyed_permutation #(
parameter UNIT_WIDTH = 1
)(
input wire i_clk,
input wire [`$NUNITS`*UNIT_WIDTH-1:0] i_dat,
input wire [`$NUNITS`*INDEX_WIDTH-1:0] i_key,
input wire i_inverse,
output reg [`$NUNITS`*UNIT_WIDTH-1:0] o_dat
);
localparam NUNITS = `$NUNITS`;
localparam INDEX_WIDTH = `$INDEX_WIDTH`;
localparam KEY_WIDTH = `$KEY_WIDTH`;
function [INDEX_WIDTH-1:0] get_nth_zero_index;
input [NUNITS-1:0] in;
input [INDEX_WIDTH-1:0] index;
integer i;
reg [INDEX_WIDTH-1:0] zero_index;
reg [INDEX_WIDTH-1:0] out;
begin
out = {INDEX_WIDTH{1'bx}};
zero_index = 0;
for(i=0;i<NUNITS;i=i+1) begin
if(~in[i]) begin
if(index==zero_index) begin
out = i;
end
zero_index = zero_index + 1;
end
end
get_nth_zero_index = out;
end
endfunction
function [NUNITS*INDEX_WIDTH-1:0] compute_map;
input [KEY_WIDTH-1:0] key;
reg [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS-1:0] done;
reg [INDEX_WIDTH-1:0] outPos;
reg [NUNITS-1:0] outDone;
reg [8:0] pos;
reg [INDEX_WIDTH-1:0] index;
``if {$COMPACT_KEY} {``
begin
outDone = {NUNITS{1'b0}};
pos = 0;
outPos = 0;
``
set remaining [expr $NUNITS-1]
for {set i 0} {$i<$NUNITS} {incr i} {
set indexWidth [binWidth $remaining]
``
index = {INDEX_WIDTH{1'b0}};
``if {$i!=$NUNITS-1} {``
index = key[pos+:`$indexWidth`] % `expr $remaining + 1`;
pos = pos + `$indexWidth`;
``}``
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=`$i`;
map[`$i`*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
``
incr remaining -1
}``
``} else {``
integer i;
reg [INDEX_WIDTH:0] remaining;
begin
outDone = {NUNITS{1'b0}};
pos = 0;
outPos = 0;
remaining = NUNITS;
for(i=0;i<NUNITS;i=i+1) begin
index = {INDEX_WIDTH{1'b0}};
if(i!=NUNITS-1) begin
index = key[pos+:INDEX_WIDTH] % remaining;
remaining = remaining - 1;
pos = pos + INDEX_WIDTH;
end
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
map[i*INDEX_WIDTH+:INDEX_WIDTH]=outPos;
end
``}``
compute_map = map;
end
endfunction
function [NUNITS*UNIT_WIDTH-1:0] permute;
input [NUNITS*UNIT_WIDTH-1:0] in;
input [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS*UNIT_WIDTH-1:0] out;
integer i;
reg [INDEX_WIDTH-1:0] index;
begin
for(i=0;i<NUNITS;i=i+1) begin
index = map[i*INDEX_WIDTH+:INDEX_WIDTH];
out[i*UNIT_WIDTH+:UNIT_WIDTH] = in[index*UNIT_WIDTH+:UNIT_WIDTH];
end
permute = out;
end
endfunction
function [NUNITS*UNIT_WIDTH-1:0] unpermute;
input [NUNITS*UNIT_WIDTH-1:0] in;
input [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS*UNIT_WIDTH-1:0] out;
integer i;
reg [INDEX_WIDTH-1:0] index;
begin
for(i=0;i<NUNITS;i=i+1) begin
index = map[i*INDEX_WIDTH+:INDEX_WIDTH];
out[index*UNIT_WIDTH+:UNIT_WIDTH] = in[i*UNIT_WIDTH+:UNIT_WIDTH];
end
unpermute = out;
end
endfunction
reg [NUNITS*INDEX_WIDTH-1:0] map;
always @(posedge i_clk) begin
map <= compute_map(i_key);
o_dat <= i_inverse ? unpermute(i_dat,map) : permute(i_dat,map);
end
endmodule
|
/* this file automatically generated by make_wp.py script
* for file rtl/top_2core2dr.v
* for module top_2core2dr
* with the instance name top
*/
// file automatically generated by top_generator script
// this is a memory hierarchy done as a class project for CMPE220 at UCSC
// this specific file was generated for:
// 2 core(s),
// 4 data cache slice(s) per core, and
// 2 directory(ies)
`include "scmem.vh"
module integration_2core2dr(
/* verilator lint_off UNUSED */
/* verilator lint_off UNDRIVEN */
input logic clk
,input logic reset
//******************************************
//* CORE 0 *
//******************************************//
// icache core 0
,input logic core0_coretoic_pc_valid
,output logic core0_coretoic_pc_retry
// ,input I_coretoic_pc_type core0_coretoic_pc
,input CORE_reqid_type core0_coretoic_pc_coreid
,input SC_poffset_type core0_coretoic_pc_poffset
,output logic core0_ictocore_valid
,input logic core0_ictocore_retry
// ,output I_ictocore_type core0_ictocore
,output CORE_reqid_type core0_ictocore_coreid
,output SC_fault_type core0_ictocore_fault
,output IC_fwidth_type core0_ictocore_data
// dcache core 0, slice 0
,input logic core0_slice0_coretodc_ld_valid
,output logic core0_slice0_coretodc_ld_retry
// ,input I_coretodc_ld_type core0_slice0_coretodc_ld
,input DC_ckpid_type core0_slice0_coretodc_ld_ckpid
,input CORE_reqid_type core0_slice0_coretodc_ld_coreid
,input CORE_lop_type core0_slice0_coretodc_ld_lop
,input logic core0_slice0_coretodc_ld_pnr
,input SC_pcsign_type core0_slice0_coretodc_ld_pcsign
,input SC_poffset_type core0_slice0_coretodc_ld_poffset
,input SC_imm_type core0_slice0_coretodc_ld_imm
,output logic core0_slice0_dctocore_ld_valid
,input logic core0_slice0_dctocore_ld_retry
// ,output I_dctocore_ld_type core0_slice0_dctocore_ld
,output CORE_reqid_type core0_slice0_dctocore_ld_coreid
,output SC_fault_type core0_slice0_dctocore_ld_fault
,output SC_line_type core0_slice0_dctocore_ld_data
,input logic core0_slice0_coretodc_std_valid
,output logic core0_slice0_coretodc_std_retry
// ,input I_coretodc_std_type core0_slice0_coretodc_std
,input DC_ckpid_type core0_slice0_coretodc_std_ckpid
,input CORE_reqid_type core0_slice0_coretodc_std_coreid
,input CORE_mop_type core0_slice0_coretodc_std_mop
,input logic core0_slice0_coretodc_std_pnr
,input SC_pcsign_type core0_slice0_coretodc_std_pcsign
,input SC_poffset_type core0_slice0_coretodc_std_poffset
,input SC_imm_type core0_slice0_coretodc_std_imm
,input SC_line_type core0_slice0_coretodc_std_data
,output logic core0_slice0_dctocore_std_ack_valid
,input logic core0_slice0_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core0_slice0_dctocore_std_ack
,output SC_fault_type core0_slice0_dctocore_std_ack_fault
,output CORE_reqid_type core0_slice0_dctocore_std_ack_coreid
,input logic c0_s0_coretodctlb_ld_valid
,output logic c0_s0_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c0_s0_coretodctlb_ld
,input DC_ckpid_type c0_s0_coretodctlb_ld_ckpid
,input CORE_reqid_type c0_s0_coretodctlb_ld_coreid
,input CORE_lop_type c0_s0_coretodctlb_ld_lop
,input logic c0_s0_coretodctlb_ld_pnr
,input SC_laddr_type c0_s0_coretodctlb_ld_laddr
,input SC_imm_type c0_s0_coretodctlb_ld_imm
,input SC_sptbr_type c0_s0_coretodctlb_ld_sptbr
,input logic c0_s0_coretodctlb_ld_user
,input logic c0_s0_coretodctlb_st_valid
,output logic c0_s0_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c0_s0_coretodctlb_st
,input DC_ckpid_type c0_s0_coretodctlb_st_ckpid
,input CORE_reqid_type c0_s0_coretodctlb_st_coreid
,input CORE_mop_type c0_s0_coretodctlb_st_mop
,input logic c0_s0_coretodctlb_st_pnr
,input SC_laddr_type c0_s0_coretodctlb_st_laddr
,input SC_imm_type c0_s0_coretodctlb_st_imm
,input SC_sptbr_type c0_s0_coretodctlb_st_sptbr
,input logic c0_s0_coretodctlb_st_user
// dcache core 0, slice 1
,input logic core0_slice1_coretodc_ld_valid
,output logic core0_slice1_coretodc_ld_retry
// ,input I_coretodc_ld_type core0_slice1_coretodc_ld
,input DC_ckpid_type core0_slice1_coretodc_ld_ckpid
,input CORE_reqid_type core0_slice1_coretodc_ld_coreid
,input CORE_lop_type core0_slice1_coretodc_ld_lop
,input logic core0_slice1_coretodc_ld_pnr
,input SC_pcsign_type core0_slice1_coretodc_ld_pcsign
,input SC_poffset_type core0_slice1_coretodc_ld_poffset
,input SC_imm_type core0_slice1_coretodc_ld_imm
,output logic core0_slice1_dctocore_ld_valid
,input logic core0_slice1_dctocore_ld_retry
// ,output I_dctocore_ld_type core0_slice1_dctocore_ld
,output CORE_reqid_type core0_slice1_dctocore_ld_coreid
,output SC_fault_type core0_slice1_dctocore_ld_fault
,output SC_line_type core0_slice1_dctocore_ld_data
,input logic core0_slice1_coretodc_std_valid
,output logic core0_slice1_coretodc_std_retry
// ,input I_coretodc_std_type core0_slice1_coretodc_std
,input DC_ckpid_type core0_slice1_coretodc_std_ckpid
,input CORE_reqid_type core0_slice1_coretodc_std_coreid
,input CORE_mop_type core0_slice1_coretodc_std_mop
,input logic core0_slice1_coretodc_std_pnr
,input SC_pcsign_type core0_slice1_coretodc_std_pcsign
,input SC_poffset_type core0_slice1_coretodc_std_poffset
,input SC_imm_type core0_slice1_coretodc_std_imm
,input SC_line_type core0_slice1_coretodc_std_data
,output logic core0_slice1_dctocore_std_ack_valid
,input logic core0_slice1_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core0_slice1_dctocore_std_ack
,output SC_fault_type core0_slice1_dctocore_std_ack_fault
,output CORE_reqid_type core0_slice1_dctocore_std_ack_coreid
,input logic c0_s1_coretodctlb_ld_valid
,output logic c0_s1_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c0_s1_coretodctlb_ld
,input DC_ckpid_type c0_s1_coretodctlb_ld_ckpid
,input CORE_reqid_type c0_s1_coretodctlb_ld_coreid
,input CORE_lop_type c0_s1_coretodctlb_ld_lop
,input logic c0_s1_coretodctlb_ld_pnr
,input SC_laddr_type c0_s1_coretodctlb_ld_laddr
,input SC_imm_type c0_s1_coretodctlb_ld_imm
,input SC_sptbr_type c0_s1_coretodctlb_ld_sptbr
,input logic c0_s1_coretodctlb_ld_user
,input logic c0_s1_coretodctlb_st_valid
,output logic c0_s1_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c0_s1_coretodctlb_st
,input DC_ckpid_type c0_s1_coretodctlb_st_ckpid
,input CORE_reqid_type c0_s1_coretodctlb_st_coreid
,input CORE_mop_type c0_s1_coretodctlb_st_mop
,input logic c0_s1_coretodctlb_st_pnr
,input SC_laddr_type c0_s1_coretodctlb_st_laddr
,input SC_imm_type c0_s1_coretodctlb_st_imm
,input SC_sptbr_type c0_s1_coretodctlb_st_sptbr
,input logic c0_s1_coretodctlb_st_user
`ifdef SC_4PIPE
// dcache core 0, slice 2
,input logic core0_slice2_coretodc_ld_valid
,output logic core0_slice2_coretodc_ld_retry
// ,input I_coretodc_ld_type core0_slice2_coretodc_ld
,input DC_ckpid_type core0_slice2_coretodc_ld_ckpid
,input CORE_reqid_type core0_slice2_coretodc_ld_coreid
,input CORE_lop_type core0_slice2_coretodc_ld_lop
,input logic core0_slice2_coretodc_ld_pnr
,input SC_pcsign_type core0_slice2_coretodc_ld_pcsign
,input SC_poffset_type core0_slice2_coretodc_ld_poffset
,input SC_imm_type core0_slice2_coretodc_ld_imm
,output logic core0_slice2_dctocore_ld_valid
,input logic core0_slice2_dctocore_ld_retry
// ,output I_dctocore_ld_type core0_slice2_dctocore_ld
,output CORE_reqid_type core0_slice2_dctocore_ld_coreid
,output SC_fault_type core0_slice2_dctocore_ld_fault
,output SC_line_type core0_slice2_dctocore_ld_data
,input logic core0_slice2_coretodc_std_valid
,output logic core0_slice2_coretodc_std_retry
// ,input I_coretodc_std_type core0_slice2_coretodc_std
,input DC_ckpid_type core0_slice2_coretodc_std_ckpid
,input CORE_reqid_type core0_slice2_coretodc_std_coreid
,input CORE_mop_type core0_slice2_coretodc_std_mop
,input logic core0_slice2_coretodc_std_pnr
,input SC_pcsign_type core0_slice2_coretodc_std_pcsign
,input SC_poffset_type core0_slice2_coretodc_std_poffset
,input SC_imm_type core0_slice2_coretodc_std_imm
,input SC_line_type core0_slice2_coretodc_std_data
,output logic core0_slice2_dctocore_std_ack_valid
,input logic core0_slice2_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core0_slice2_dctocore_std_ack
,output SC_fault_type core0_slice2_dctocore_std_ack_fault
,output CORE_reqid_type core0_slice2_dctocore_std_ack_coreid
,input logic c0_s2_coretodctlb_ld_valid
,output logic c0_s2_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c0_s2_coretodctlb_ld
,input DC_ckpid_type c0_s2_coretodctlb_ld_ckpid
,input CORE_reqid_type c0_s2_coretodctlb_ld_coreid
,input CORE_lop_type c0_s2_coretodctlb_ld_lop
,input logic c0_s2_coretodctlb_ld_pnr
,input SC_laddr_type c0_s2_coretodctlb_ld_laddr
,input SC_imm_type c0_s2_coretodctlb_ld_imm
,input SC_sptbr_type c0_s2_coretodctlb_ld_sptbr
,input logic c0_s2_coretodctlb_ld_user
,input logic c0_s2_coretodctlb_st_valid
,output logic c0_s2_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c0_s2_coretodctlb_st
,input DC_ckpid_type c0_s2_coretodctlb_st_ckpid
,input CORE_reqid_type c0_s2_coretodctlb_st_coreid
,input CORE_mop_type c0_s2_coretodctlb_st_mop
,input logic c0_s2_coretodctlb_st_pnr
,input SC_laddr_type c0_s2_coretodctlb_st_laddr
,input SC_imm_type c0_s2_coretodctlb_st_imm
,input SC_sptbr_type c0_s2_coretodctlb_st_sptbr
,input logic c0_s2_coretodctlb_st_user
// dcache core 0, slice 3
,input logic core0_slice3_coretodc_ld_valid
,output logic core0_slice3_coretodc_ld_retry
// ,input I_coretodc_ld_type core0_slice3_coretodc_ld
,input DC_ckpid_type core0_slice3_coretodc_ld_ckpid
,input CORE_reqid_type core0_slice3_coretodc_ld_coreid
,input CORE_lop_type core0_slice3_coretodc_ld_lop
,input logic core0_slice3_coretodc_ld_pnr
,input SC_pcsign_type core0_slice3_coretodc_ld_pcsign
,input SC_poffset_type core0_slice3_coretodc_ld_poffset
,input SC_imm_type core0_slice3_coretodc_ld_imm
,output logic core0_slice3_dctocore_ld_valid
,input logic core0_slice3_dctocore_ld_retry
// ,output I_dctocore_ld_type core0_slice3_dctocore_ld
,output CORE_reqid_type core0_slice3_dctocore_ld_coreid
,output SC_fault_type core0_slice3_dctocore_ld_fault
,output SC_line_type core0_slice3_dctocore_ld_data
,input logic core0_slice3_coretodc_std_valid
,output logic core0_slice3_coretodc_std_retry
// ,input I_coretodc_std_type core0_slice3_coretodc_std
,input DC_ckpid_type core0_slice3_coretodc_std_ckpid
,input CORE_reqid_type core0_slice3_coretodc_std_coreid
,input CORE_mop_type core0_slice3_coretodc_std_mop
,input logic core0_slice3_coretodc_std_pnr
,input SC_pcsign_type core0_slice3_coretodc_std_pcsign
,input SC_poffset_type core0_slice3_coretodc_std_poffset
,input SC_imm_type core0_slice3_coretodc_std_imm
,input SC_line_type core0_slice3_coretodc_std_data
,output logic core0_slice3_dctocore_std_ack_valid
,input logic core0_slice3_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core0_slice3_dctocore_std_ack
,output SC_fault_type core0_slice3_dctocore_std_ack_fault
,output CORE_reqid_type core0_slice3_dctocore_std_ack_coreid
,input logic c0_s3_coretodctlb_ld_valid
,output logic c0_s3_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c0_s3_coretodctlb_ld
,input DC_ckpid_type c0_s3_coretodctlb_ld_ckpid
,input CORE_reqid_type c0_s3_coretodctlb_ld_coreid
,input CORE_lop_type c0_s3_coretodctlb_ld_lop
,input logic c0_s3_coretodctlb_ld_pnr
,input SC_laddr_type c0_s3_coretodctlb_ld_laddr
,input SC_imm_type c0_s3_coretodctlb_ld_imm
,input SC_sptbr_type c0_s3_coretodctlb_ld_sptbr
,input logic c0_s3_coretodctlb_ld_user
,input logic c0_s3_coretodctlb_st_valid
,output logic c0_s3_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c0_s3_coretodctlb_st
,input DC_ckpid_type c0_s3_coretodctlb_st_ckpid
,input CORE_reqid_type c0_s3_coretodctlb_st_coreid
,input CORE_mop_type c0_s3_coretodctlb_st_mop
,input logic c0_s3_coretodctlb_st_pnr
,input SC_laddr_type c0_s3_coretodctlb_st_laddr
,input SC_imm_type c0_s3_coretodctlb_st_imm
,input SC_sptbr_type c0_s3_coretodctlb_st_sptbr
,input logic c0_s3_coretodctlb_st_user
`endif
// core 0 prefetch
,input logic core0_pfgtopfe_op_valid
,output logic core0_pfgtopfe_op_retry
// ,input I_pfgtopfe_op_type core0_pfgtopfe_op
,input PF_delta_type core0_pfgtopfe_op_delta
,input PF_weigth_type core0_pfgtopfe_op_w1
,input PF_weigth_type core0_pfgtopfe_op_w2
,input SC_pcsign_type core0_pfgtopfe_op_pcsign
,input SC_laddr_type core0_pfgtopfe_op_laddr
,input SC_sptbr_type core0_pfgtopfe_op_sptbr
//******************************************
//* CORE 1 *
//******************************************//
// icache core 1
,input logic core1_coretoic_pc_valid
,output logic core1_coretoic_pc_retry
// ,input I_coretoic_pc_type core1_coretoic_pc
,input CORE_reqid_type core1_coretoic_pc_coreid
,input SC_poffset_type core1_coretoic_pc_poffset
,output logic core1_ictocore_valid
,input logic core1_ictocore_retry
// ,output I_ictocore_type core1_ictocore
,output CORE_reqid_type core1_ictocore_coreid
,output SC_fault_type core1_ictocore_fault
,output IC_fwidth_type core1_ictocore_data
// dcache core 1, slice 0
,input logic core1_slice0_coretodc_ld_valid
,output logic core1_slice0_coretodc_ld_retry
// ,input I_coretodc_ld_type core1_slice0_coretodc_ld
,input DC_ckpid_type core1_slice0_coretodc_ld_ckpid
,input CORE_reqid_type core1_slice0_coretodc_ld_coreid
,input CORE_lop_type core1_slice0_coretodc_ld_lop
,input logic core1_slice0_coretodc_ld_pnr
,input SC_pcsign_type core1_slice0_coretodc_ld_pcsign
,input SC_poffset_type core1_slice0_coretodc_ld_poffset
,input SC_imm_type core1_slice0_coretodc_ld_imm
,output logic core1_slice0_dctocore_ld_valid
,input logic core1_slice0_dctocore_ld_retry
// ,output I_dctocore_ld_type core1_slice0_dctocore_ld
,output CORE_reqid_type core1_slice0_dctocore_ld_coreid
,output SC_fault_type core1_slice0_dctocore_ld_fault
,output SC_line_type core1_slice0_dctocore_ld_data
,input logic core1_slice0_coretodc_std_valid
,output logic core1_slice0_coretodc_std_retry
// ,input I_coretodc_std_type core1_slice0_coretodc_std
,input DC_ckpid_type core1_slice0_coretodc_std_ckpid
,input CORE_reqid_type core1_slice0_coretodc_std_coreid
,input CORE_mop_type core1_slice0_coretodc_std_mop
,input logic core1_slice0_coretodc_std_pnr
,input SC_pcsign_type core1_slice0_coretodc_std_pcsign
,input SC_poffset_type core1_slice0_coretodc_std_poffset
,input SC_imm_type core1_slice0_coretodc_std_imm
,input SC_line_type core1_slice0_coretodc_std_data
,output logic core1_slice0_dctocore_std_ack_valid
,input logic core1_slice0_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core1_slice0_dctocore_std_ack
,output SC_fault_type core1_slice0_dctocore_std_ack_fault
,output CORE_reqid_type core1_slice0_dctocore_std_ack_coreid
,input logic c1_s0_coretodctlb_ld_valid
,output logic c1_s0_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c1_s0_coretodctlb_ld
,input DC_ckpid_type c1_s0_coretodctlb_ld_ckpid
,input CORE_reqid_type c1_s0_coretodctlb_ld_coreid
,input CORE_lop_type c1_s0_coretodctlb_ld_lop
,input logic c1_s0_coretodctlb_ld_pnr
,input SC_laddr_type c1_s0_coretodctlb_ld_laddr
,input SC_imm_type c1_s0_coretodctlb_ld_imm
,input SC_sptbr_type c1_s0_coretodctlb_ld_sptbr
,input logic c1_s0_coretodctlb_ld_user
,input logic c1_s0_coretodctlb_st_valid
,output logic c1_s0_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c1_s0_coretodctlb_st
,input DC_ckpid_type c1_s0_coretodctlb_st_ckpid
,input CORE_reqid_type c1_s0_coretodctlb_st_coreid
,input CORE_mop_type c1_s0_coretodctlb_st_mop
,input logic c1_s0_coretodctlb_st_pnr
,input SC_laddr_type c1_s0_coretodctlb_st_laddr
,input SC_imm_type c1_s0_coretodctlb_st_imm
,input SC_sptbr_type c1_s0_coretodctlb_st_sptbr
,input logic c1_s0_coretodctlb_st_user
// dcache core 1, slice 1
,input logic core1_slice1_coretodc_ld_valid
,output logic core1_slice1_coretodc_ld_retry
// ,input I_coretodc_ld_type core1_slice1_coretodc_ld
,input DC_ckpid_type core1_slice1_coretodc_ld_ckpid
,input CORE_reqid_type core1_slice1_coretodc_ld_coreid
,input CORE_lop_type core1_slice1_coretodc_ld_lop
,input logic core1_slice1_coretodc_ld_pnr
,input SC_pcsign_type core1_slice1_coretodc_ld_pcsign
,input SC_poffset_type core1_slice1_coretodc_ld_poffset
,input SC_imm_type core1_slice1_coretodc_ld_imm
,output logic core1_slice1_dctocore_ld_valid
,input logic core1_slice1_dctocore_ld_retry
// ,output I_dctocore_ld_type core1_slice1_dctocore_ld
,output CORE_reqid_type core1_slice1_dctocore_ld_coreid
,output SC_fault_type core1_slice1_dctocore_ld_fault
,output SC_line_type core1_slice1_dctocore_ld_data
,input logic core1_slice1_coretodc_std_valid
,output logic core1_slice1_coretodc_std_retry
// ,input I_coretodc_std_type core1_slice1_coretodc_std
,input DC_ckpid_type core1_slice1_coretodc_std_ckpid
,input CORE_reqid_type core1_slice1_coretodc_std_coreid
,input CORE_mop_type core1_slice1_coretodc_std_mop
,input logic core1_slice1_coretodc_std_pnr
,input SC_pcsign_type core1_slice1_coretodc_std_pcsign
,input SC_poffset_type core1_slice1_coretodc_std_poffset
,input SC_imm_type core1_slice1_coretodc_std_imm
,input SC_line_type core1_slice1_coretodc_std_data
,output logic core1_slice1_dctocore_std_ack_valid
,input logic core1_slice1_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core1_slice1_dctocore_std_ack
,output SC_fault_type core1_slice1_dctocore_std_ack_fault
,output CORE_reqid_type core1_slice1_dctocore_std_ack_coreid
,input logic c1_s1_coretodctlb_ld_valid
,output logic c1_s1_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c1_s1_coretodctlb_ld
,input DC_ckpid_type c1_s1_coretodctlb_ld_ckpid
,input CORE_reqid_type c1_s1_coretodctlb_ld_coreid
,input CORE_lop_type c1_s1_coretodctlb_ld_lop
,input logic c1_s1_coretodctlb_ld_pnr
,input SC_laddr_type c1_s1_coretodctlb_ld_laddr
,input SC_imm_type c1_s1_coretodctlb_ld_imm
,input SC_sptbr_type c1_s1_coretodctlb_ld_sptbr
,input logic c1_s1_coretodctlb_ld_user
,input logic c1_s1_coretodctlb_st_valid
,output logic c1_s1_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c1_s1_coretodctlb_st
,input DC_ckpid_type c1_s1_coretodctlb_st_ckpid
,input CORE_reqid_type c1_s1_coretodctlb_st_coreid
,input CORE_mop_type c1_s1_coretodctlb_st_mop
,input logic c1_s1_coretodctlb_st_pnr
,input SC_laddr_type c1_s1_coretodctlb_st_laddr
,input SC_imm_type c1_s1_coretodctlb_st_imm
,input SC_sptbr_type c1_s1_coretodctlb_st_sptbr
,input logic c1_s1_coretodctlb_st_user
`ifdef SC_4PIPE
// dcache core 1, slice 2
,input logic core1_slice2_coretodc_ld_valid
,output logic core1_slice2_coretodc_ld_retry
// ,input I_coretodc_ld_type core1_slice2_coretodc_ld
,input DC_ckpid_type core1_slice2_coretodc_ld_ckpid
,input CORE_reqid_type core1_slice2_coretodc_ld_coreid
,input CORE_lop_type core1_slice2_coretodc_ld_lop
,input logic core1_slice2_coretodc_ld_pnr
,input SC_pcsign_type core1_slice2_coretodc_ld_pcsign
,input SC_poffset_type core1_slice2_coretodc_ld_poffset
,input SC_imm_type core1_slice2_coretodc_ld_imm
,output logic core1_slice2_dctocore_ld_valid
,input logic core1_slice2_dctocore_ld_retry
// ,output I_dctocore_ld_type core1_slice2_dctocore_ld
,output CORE_reqid_type core1_slice2_dctocore_ld_coreid
,output SC_fault_type core1_slice2_dctocore_ld_fault
,output SC_line_type core1_slice2_dctocore_ld_data
,input logic core1_slice2_coretodc_std_valid
,output logic core1_slice2_coretodc_std_retry
// ,input I_coretodc_std_type core1_slice2_coretodc_std
,input DC_ckpid_type core1_slice2_coretodc_std_ckpid
,input CORE_reqid_type core1_slice2_coretodc_std_coreid
,input CORE_mop_type core1_slice2_coretodc_std_mop
,input logic core1_slice2_coretodc_std_pnr
,input SC_pcsign_type core1_slice2_coretodc_std_pcsign
,input SC_poffset_type core1_slice2_coretodc_std_poffset
,input SC_imm_type core1_slice2_coretodc_std_imm
,input SC_line_type core1_slice2_coretodc_std_data
,output logic core1_slice2_dctocore_std_ack_valid
,input logic core1_slice2_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core1_slice2_dctocore_std_ack
,output SC_fault_type core1_slice2_dctocore_std_ack_fault
,output CORE_reqid_type core1_slice2_dctocore_std_ack_coreid
,input logic c1_s2_coretodctlb_ld_valid
,output logic c1_s2_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c1_s2_coretodctlb_ld
,input DC_ckpid_type c1_s2_coretodctlb_ld_ckpid
,input CORE_reqid_type c1_s2_coretodctlb_ld_coreid
,input CORE_lop_type c1_s2_coretodctlb_ld_lop
,input logic c1_s2_coretodctlb_ld_pnr
,input SC_laddr_type c1_s2_coretodctlb_ld_laddr
,input SC_imm_type c1_s2_coretodctlb_ld_imm
,input SC_sptbr_type c1_s2_coretodctlb_ld_sptbr
,input logic c1_s2_coretodctlb_ld_user
,input logic c1_s2_coretodctlb_st_valid
,output logic c1_s2_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c1_s2_coretodctlb_st
,input DC_ckpid_type c1_s2_coretodctlb_st_ckpid
,input CORE_reqid_type c1_s2_coretodctlb_st_coreid
,input CORE_mop_type c1_s2_coretodctlb_st_mop
,input logic c1_s2_coretodctlb_st_pnr
,input SC_laddr_type c1_s2_coretodctlb_st_laddr
,input SC_imm_type c1_s2_coretodctlb_st_imm
,input SC_sptbr_type c1_s2_coretodctlb_st_sptbr
,input logic c1_s2_coretodctlb_st_user
// dcache core 1, slice 3
,input logic core1_slice3_coretodc_ld_valid
,output logic core1_slice3_coretodc_ld_retry
// ,input I_coretodc_ld_type core1_slice3_coretodc_ld
,input DC_ckpid_type core1_slice3_coretodc_ld_ckpid
,input CORE_reqid_type core1_slice3_coretodc_ld_coreid
,input CORE_lop_type core1_slice3_coretodc_ld_lop
,input logic core1_slice3_coretodc_ld_pnr
,input SC_pcsign_type core1_slice3_coretodc_ld_pcsign
,input SC_poffset_type core1_slice3_coretodc_ld_poffset
,input SC_imm_type core1_slice3_coretodc_ld_imm
,output logic core1_slice3_dctocore_ld_valid
,input logic core1_slice3_dctocore_ld_retry
// ,output I_dctocore_ld_type core1_slice3_dctocore_ld
,output CORE_reqid_type core1_slice3_dctocore_ld_coreid
,output SC_fault_type core1_slice3_dctocore_ld_fault
,output SC_line_type core1_slice3_dctocore_ld_data
,input logic core1_slice3_coretodc_std_valid
,output logic core1_slice3_coretodc_std_retry
// ,input I_coretodc_std_type core1_slice3_coretodc_std
,input DC_ckpid_type core1_slice3_coretodc_std_ckpid
,input CORE_reqid_type core1_slice3_coretodc_std_coreid
,input CORE_mop_type core1_slice3_coretodc_std_mop
,input logic core1_slice3_coretodc_std_pnr
,input SC_pcsign_type core1_slice3_coretodc_std_pcsign
,input SC_poffset_type core1_slice3_coretodc_std_poffset
,input SC_imm_type core1_slice3_coretodc_std_imm
,input SC_line_type core1_slice3_coretodc_std_data
,output logic core1_slice3_dctocore_std_ack_valid
,input logic core1_slice3_dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type core1_slice3_dctocore_std_ack
,output SC_fault_type core1_slice3_dctocore_std_ack_fault
,output CORE_reqid_type core1_slice3_dctocore_std_ack_coreid
,input logic c1_s3_coretodctlb_ld_valid
,output logic c1_s3_coretodctlb_ld_retry
// ,input I_coretodctlb_ld_type c1_s3_coretodctlb_ld
,input DC_ckpid_type c1_s3_coretodctlb_ld_ckpid
,input CORE_reqid_type c1_s3_coretodctlb_ld_coreid
,input CORE_lop_type c1_s3_coretodctlb_ld_lop
,input logic c1_s3_coretodctlb_ld_pnr
,input SC_laddr_type c1_s3_coretodctlb_ld_laddr
,input SC_imm_type c1_s3_coretodctlb_ld_imm
,input SC_sptbr_type c1_s3_coretodctlb_ld_sptbr
,input logic c1_s3_coretodctlb_ld_user
,input logic c1_s3_coretodctlb_st_valid
,output logic c1_s3_coretodctlb_st_retry
// ,input I_coretodctlb_st_type c1_s3_coretodctlb_st
,input DC_ckpid_type c1_s3_coretodctlb_st_ckpid
,input CORE_reqid_type c1_s3_coretodctlb_st_coreid
,input CORE_mop_type c1_s3_coretodctlb_st_mop
,input logic c1_s3_coretodctlb_st_pnr
,input SC_laddr_type c1_s3_coretodctlb_st_laddr
,input SC_imm_type c1_s3_coretodctlb_st_imm
,input SC_sptbr_type c1_s3_coretodctlb_st_sptbr
,input logic c1_s3_coretodctlb_st_user
`endif
// core 1 prefetch
,input logic core1_pfgtopfe_op_valid
,output logic core1_pfgtopfe_op_retry
// ,input I_pfgtopfe_op_type core1_pfgtopfe_op
,input PF_delta_type core1_pfgtopfe_op_delta
,input PF_weigth_type core1_pfgtopfe_op_w1
,input PF_weigth_type core1_pfgtopfe_op_w2
,input SC_pcsign_type core1_pfgtopfe_op_pcsign
,input SC_laddr_type core1_pfgtopfe_op_laddr
,input SC_sptbr_type core1_pfgtopfe_op_sptbr
//******************************************
//* Directory 0 *
//******************************************//
,output logic dr0_drtomem_req_valid
,input logic dr0_drtomem_req_retry
// ,output I_drtomem_req_type dr0_drtomem_req
,output DR_reqid_type dr0_drtomem_req_drid
,output SC_cmd_type dr0_drtomem_req_cmd
,output SC_paddr_type dr0_drtomem_req_paddr
,input logic dr0_memtodr_ack_valid
,output logic dr0_memtodr_ack_retry
// ,input I_memtodr_ack_type dr0_memtodr_ack
,input DR_reqid_type dr0_memtodr_ack_drid
,input SC_nodeid_type dr0_memtodr_ack_nid
,input SC_paddr_type dr0_memtodr_ack_paddr
,input SC_snack_type dr0_memtodr_ack_ack
,input SC_line_type dr0_memtodr_ack_line
,output logic dr0_drtomem_wb_valid
,input logic dr0_drtomem_wb_retry
// ,output I_drtomem_wb_type dr0_drtomem_wb
,output SC_line_type dr0_drtomem_wb_line
,output SC_paddr_type dr0_drtomem_wb_paddr
,output logic dr0_drtomem_pfreq_valid
,input logic dr0_drtomem_pfreq_retry
// ,output I_drtomem_pfreq_type dr0_drtomem_pfreq
,output SC_nodeid_type dr0_drtomem_pfreq_nid
,output SC_paddr_type dr0_drtomem_pfreq_paddr
//******************************************
//* Directory 1 *
//******************************************//
,output logic dr1_drtomem_req_valid
,input logic dr1_drtomem_req_retry
// ,output I_drtomem_req_type dr1_drtomem_req
,output DR_reqid_type dr1_drtomem_req_drid
,output SC_cmd_type dr1_drtomem_req_cmd
,output SC_paddr_type dr1_drtomem_req_paddr
,input logic dr1_memtodr_ack_valid
,output logic dr1_memtodr_ack_retry
// ,input I_memtodr_ack_type dr1_memtodr_ack
,input DR_reqid_type dr1_memtodr_ack_drid
,input SC_nodeid_type dr1_memtodr_ack_nid
,input SC_paddr_type dr1_memtodr_ack_paddr
,input SC_snack_type dr1_memtodr_ack_ack
,input SC_line_type dr1_memtodr_ack_line
,output logic dr1_drtomem_wb_valid
,input logic dr1_drtomem_wb_retry
// ,output I_drtomem_wb_type dr1_drtomem_wb
,output SC_line_type dr1_drtomem_wb_line
,output SC_paddr_type dr1_drtomem_wb_paddr
,output logic dr1_drtomem_pfreq_valid
,input logic dr1_drtomem_pfreq_retry
// ,output I_drtomem_pfreq_type dr1_drtomem_pfreq
,output SC_nodeid_type dr1_drtomem_pfreq_nid
,output SC_paddr_type dr1_drtomem_pfreq_paddr
);
I_coretoic_pc_type core0_coretoic_pc;
assign core0_coretoic_pc.coreid = core0_coretoic_pc_coreid;
assign core0_coretoic_pc.poffset = core0_coretoic_pc_poffset;
I_ictocore_type core0_ictocore;
assign core0_ictocore_coreid = core0_ictocore.coreid;
assign core0_ictocore_fault = core0_ictocore.fault;
assign core0_ictocore_data = core0_ictocore.data;
I_coretodc_ld_type core0_slice0_coretodc_ld;
assign core0_slice0_coretodc_ld.ckpid = core0_slice0_coretodc_ld_ckpid;
assign core0_slice0_coretodc_ld.coreid = core0_slice0_coretodc_ld_coreid;
assign core0_slice0_coretodc_ld.lop = core0_slice0_coretodc_ld_lop;
assign core0_slice0_coretodc_ld.pnr = core0_slice0_coretodc_ld_pnr;
assign core0_slice0_coretodc_ld.pcsign = core0_slice0_coretodc_ld_pcsign;
assign core0_slice0_coretodc_ld.poffset = core0_slice0_coretodc_ld_poffset;
assign core0_slice0_coretodc_ld.imm = core0_slice0_coretodc_ld_imm;
I_dctocore_ld_type core0_slice0_dctocore_ld;
assign core0_slice0_dctocore_ld_coreid = core0_slice0_dctocore_ld.coreid;
assign core0_slice0_dctocore_ld_fault = core0_slice0_dctocore_ld.fault;
assign core0_slice0_dctocore_ld_data = core0_slice0_dctocore_ld.data;
I_coretodc_std_type core0_slice0_coretodc_std;
assign core0_slice0_coretodc_std.ckpid = core0_slice0_coretodc_std_ckpid;
assign core0_slice0_coretodc_std.coreid = core0_slice0_coretodc_std_coreid;
assign core0_slice0_coretodc_std.mop = core0_slice0_coretodc_std_mop;
assign core0_slice0_coretodc_std.pnr = core0_slice0_coretodc_std_pnr;
assign core0_slice0_coretodc_std.pcsign = core0_slice0_coretodc_std_pcsign;
assign core0_slice0_coretodc_std.poffset = core0_slice0_coretodc_std_poffset;
assign core0_slice0_coretodc_std.imm = core0_slice0_coretodc_std_imm;
assign core0_slice0_coretodc_std.data = core0_slice0_coretodc_std_data;
I_dctocore_std_ack_type core0_slice0_dctocore_std_ack;
assign core0_slice0_dctocore_std_ack_fault = core0_slice0_dctocore_std_ack.fault;
assign core0_slice0_dctocore_std_ack_coreid = core0_slice0_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c0_s0_coretodctlb_ld;
assign c0_s0_coretodctlb_ld.ckpid = c0_s0_coretodctlb_ld_ckpid;
assign c0_s0_coretodctlb_ld.coreid = c0_s0_coretodctlb_ld_coreid;
assign c0_s0_coretodctlb_ld.lop = c0_s0_coretodctlb_ld_lop;
assign c0_s0_coretodctlb_ld.pnr = c0_s0_coretodctlb_ld_pnr;
assign c0_s0_coretodctlb_ld.laddr = c0_s0_coretodctlb_ld_laddr;
assign c0_s0_coretodctlb_ld.imm = c0_s0_coretodctlb_ld_imm;
assign c0_s0_coretodctlb_ld.sptbr = c0_s0_coretodctlb_ld_sptbr;
assign c0_s0_coretodctlb_ld.user = c0_s0_coretodctlb_ld_user;
I_coretodctlb_st_type c0_s0_coretodctlb_st;
assign c0_s0_coretodctlb_st.ckpid = c0_s0_coretodctlb_st_ckpid;
assign c0_s0_coretodctlb_st.coreid = c0_s0_coretodctlb_st_coreid;
assign c0_s0_coretodctlb_st.mop = c0_s0_coretodctlb_st_mop;
assign c0_s0_coretodctlb_st.pnr = c0_s0_coretodctlb_st_pnr;
assign c0_s0_coretodctlb_st.laddr = c0_s0_coretodctlb_st_laddr;
assign c0_s0_coretodctlb_st.imm = c0_s0_coretodctlb_st_imm;
assign c0_s0_coretodctlb_st.sptbr = c0_s0_coretodctlb_st_sptbr;
assign c0_s0_coretodctlb_st.user = c0_s0_coretodctlb_st_user;
I_coretodc_ld_type core0_slice1_coretodc_ld;
assign core0_slice1_coretodc_ld.ckpid = core0_slice1_coretodc_ld_ckpid;
assign core0_slice1_coretodc_ld.coreid = core0_slice1_coretodc_ld_coreid;
assign core0_slice1_coretodc_ld.lop = core0_slice1_coretodc_ld_lop;
assign core0_slice1_coretodc_ld.pnr = core0_slice1_coretodc_ld_pnr;
assign core0_slice1_coretodc_ld.pcsign = core0_slice1_coretodc_ld_pcsign;
assign core0_slice1_coretodc_ld.poffset = core0_slice1_coretodc_ld_poffset;
assign core0_slice1_coretodc_ld.imm = core0_slice1_coretodc_ld_imm;
I_dctocore_ld_type core0_slice1_dctocore_ld;
assign core0_slice1_dctocore_ld_coreid = core0_slice1_dctocore_ld.coreid;
assign core0_slice1_dctocore_ld_fault = core0_slice1_dctocore_ld.fault;
assign core0_slice1_dctocore_ld_data = core0_slice1_dctocore_ld.data;
I_coretodc_std_type core0_slice1_coretodc_std;
assign core0_slice1_coretodc_std.ckpid = core0_slice1_coretodc_std_ckpid;
assign core0_slice1_coretodc_std.coreid = core0_slice1_coretodc_std_coreid;
assign core0_slice1_coretodc_std.mop = core0_slice1_coretodc_std_mop;
assign core0_slice1_coretodc_std.pnr = core0_slice1_coretodc_std_pnr;
assign core0_slice1_coretodc_std.pcsign = core0_slice1_coretodc_std_pcsign;
assign core0_slice1_coretodc_std.poffset = core0_slice1_coretodc_std_poffset;
assign core0_slice1_coretodc_std.imm = core0_slice1_coretodc_std_imm;
assign core0_slice1_coretodc_std.data = core0_slice1_coretodc_std_data;
I_dctocore_std_ack_type core0_slice1_dctocore_std_ack;
assign core0_slice1_dctocore_std_ack_fault = core0_slice1_dctocore_std_ack.fault;
assign core0_slice1_dctocore_std_ack_coreid = core0_slice1_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c0_s1_coretodctlb_ld;
assign c0_s1_coretodctlb_ld.ckpid = c0_s1_coretodctlb_ld_ckpid;
assign c0_s1_coretodctlb_ld.coreid = c0_s1_coretodctlb_ld_coreid;
assign c0_s1_coretodctlb_ld.lop = c0_s1_coretodctlb_ld_lop;
assign c0_s1_coretodctlb_ld.pnr = c0_s1_coretodctlb_ld_pnr;
assign c0_s1_coretodctlb_ld.laddr = c0_s1_coretodctlb_ld_laddr;
assign c0_s1_coretodctlb_ld.imm = c0_s1_coretodctlb_ld_imm;
assign c0_s1_coretodctlb_ld.sptbr = c0_s1_coretodctlb_ld_sptbr;
assign c0_s1_coretodctlb_ld.user = c0_s1_coretodctlb_ld_user;
I_coretodctlb_st_type c0_s1_coretodctlb_st;
assign c0_s1_coretodctlb_st.ckpid = c0_s1_coretodctlb_st_ckpid;
assign c0_s1_coretodctlb_st.coreid = c0_s1_coretodctlb_st_coreid;
assign c0_s1_coretodctlb_st.mop = c0_s1_coretodctlb_st_mop;
assign c0_s1_coretodctlb_st.pnr = c0_s1_coretodctlb_st_pnr;
assign c0_s1_coretodctlb_st.laddr = c0_s1_coretodctlb_st_laddr;
assign c0_s1_coretodctlb_st.imm = c0_s1_coretodctlb_st_imm;
assign c0_s1_coretodctlb_st.sptbr = c0_s1_coretodctlb_st_sptbr;
assign c0_s1_coretodctlb_st.user = c0_s1_coretodctlb_st_user;
`ifdef SC_4PIPE
I_coretodc_ld_type core0_slice2_coretodc_ld;
assign core0_slice2_coretodc_ld.ckpid = core0_slice2_coretodc_ld_ckpid;
assign core0_slice2_coretodc_ld.coreid = core0_slice2_coretodc_ld_coreid;
assign core0_slice2_coretodc_ld.lop = core0_slice2_coretodc_ld_lop;
assign core0_slice2_coretodc_ld.pnr = core0_slice2_coretodc_ld_pnr;
assign core0_slice2_coretodc_ld.pcsign = core0_slice2_coretodc_ld_pcsign;
assign core0_slice2_coretodc_ld.poffset = core0_slice2_coretodc_ld_poffset;
assign core0_slice2_coretodc_ld.imm = core0_slice2_coretodc_ld_imm;
I_dctocore_ld_type core0_slice2_dctocore_ld;
assign core0_slice2_dctocore_ld_coreid = core0_slice2_dctocore_ld.coreid;
assign core0_slice2_dctocore_ld_fault = core0_slice2_dctocore_ld.fault;
assign core0_slice2_dctocore_ld_data = core0_slice2_dctocore_ld.data;
I_coretodc_std_type core0_slice2_coretodc_std;
assign core0_slice2_coretodc_std.ckpid = core0_slice2_coretodc_std_ckpid;
assign core0_slice2_coretodc_std.coreid = core0_slice2_coretodc_std_coreid;
assign core0_slice2_coretodc_std.mop = core0_slice2_coretodc_std_mop;
assign core0_slice2_coretodc_std.pnr = core0_slice2_coretodc_std_pnr;
assign core0_slice2_coretodc_std.pcsign = core0_slice2_coretodc_std_pcsign;
assign core0_slice2_coretodc_std.poffset = core0_slice2_coretodc_std_poffset;
assign core0_slice2_coretodc_std.imm = core0_slice2_coretodc_std_imm;
assign core0_slice2_coretodc_std.data = core0_slice2_coretodc_std_data;
I_dctocore_std_ack_type core0_slice2_dctocore_std_ack;
assign core0_slice2_dctocore_std_ack_fault = core0_slice2_dctocore_std_ack.fault;
assign core0_slice2_dctocore_std_ack_coreid = core0_slice2_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c0_s2_coretodctlb_ld;
assign c0_s2_coretodctlb_ld.ckpid = c0_s2_coretodctlb_ld_ckpid;
assign c0_s2_coretodctlb_ld.coreid = c0_s2_coretodctlb_ld_coreid;
assign c0_s2_coretodctlb_ld.lop = c0_s2_coretodctlb_ld_lop;
assign c0_s2_coretodctlb_ld.pnr = c0_s2_coretodctlb_ld_pnr;
assign c0_s2_coretodctlb_ld.laddr = c0_s2_coretodctlb_ld_laddr;
assign c0_s2_coretodctlb_ld.imm = c0_s2_coretodctlb_ld_imm;
assign c0_s2_coretodctlb_ld.sptbr = c0_s2_coretodctlb_ld_sptbr;
assign c0_s2_coretodctlb_ld.user = c0_s2_coretodctlb_ld_user;
I_coretodctlb_st_type c0_s2_coretodctlb_st;
assign c0_s2_coretodctlb_st.ckpid = c0_s2_coretodctlb_st_ckpid;
assign c0_s2_coretodctlb_st.coreid = c0_s2_coretodctlb_st_coreid;
assign c0_s2_coretodctlb_st.mop = c0_s2_coretodctlb_st_mop;
assign c0_s2_coretodctlb_st.pnr = c0_s2_coretodctlb_st_pnr;
assign c0_s2_coretodctlb_st.laddr = c0_s2_coretodctlb_st_laddr;
assign c0_s2_coretodctlb_st.imm = c0_s2_coretodctlb_st_imm;
assign c0_s2_coretodctlb_st.sptbr = c0_s2_coretodctlb_st_sptbr;
assign c0_s2_coretodctlb_st.user = c0_s2_coretodctlb_st_user;
I_coretodc_ld_type core0_slice3_coretodc_ld;
assign core0_slice3_coretodc_ld.ckpid = core0_slice3_coretodc_ld_ckpid;
assign core0_slice3_coretodc_ld.coreid = core0_slice3_coretodc_ld_coreid;
assign core0_slice3_coretodc_ld.lop = core0_slice3_coretodc_ld_lop;
assign core0_slice3_coretodc_ld.pnr = core0_slice3_coretodc_ld_pnr;
assign core0_slice3_coretodc_ld.pcsign = core0_slice3_coretodc_ld_pcsign;
assign core0_slice3_coretodc_ld.poffset = core0_slice3_coretodc_ld_poffset;
assign core0_slice3_coretodc_ld.imm = core0_slice3_coretodc_ld_imm;
I_dctocore_ld_type core0_slice3_dctocore_ld;
assign core0_slice3_dctocore_ld_coreid = core0_slice3_dctocore_ld.coreid;
assign core0_slice3_dctocore_ld_fault = core0_slice3_dctocore_ld.fault;
assign core0_slice3_dctocore_ld_data = core0_slice3_dctocore_ld.data;
I_coretodc_std_type core0_slice3_coretodc_std;
assign core0_slice3_coretodc_std.ckpid = core0_slice3_coretodc_std_ckpid;
assign core0_slice3_coretodc_std.coreid = core0_slice3_coretodc_std_coreid;
assign core0_slice3_coretodc_std.mop = core0_slice3_coretodc_std_mop;
assign core0_slice3_coretodc_std.pnr = core0_slice3_coretodc_std_pnr;
assign core0_slice3_coretodc_std.pcsign = core0_slice3_coretodc_std_pcsign;
assign core0_slice3_coretodc_std.poffset = core0_slice3_coretodc_std_poffset;
assign core0_slice3_coretodc_std.imm = core0_slice3_coretodc_std_imm;
assign core0_slice3_coretodc_std.data = core0_slice3_coretodc_std_data;
I_dctocore_std_ack_type core0_slice3_dctocore_std_ack;
assign core0_slice3_dctocore_std_ack_fault = core0_slice3_dctocore_std_ack.fault;
assign core0_slice3_dctocore_std_ack_coreid = core0_slice3_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c0_s3_coretodctlb_ld;
assign c0_s3_coretodctlb_ld.ckpid = c0_s3_coretodctlb_ld_ckpid;
assign c0_s3_coretodctlb_ld.coreid = c0_s3_coretodctlb_ld_coreid;
assign c0_s3_coretodctlb_ld.lop = c0_s3_coretodctlb_ld_lop;
assign c0_s3_coretodctlb_ld.pnr = c0_s3_coretodctlb_ld_pnr;
assign c0_s3_coretodctlb_ld.laddr = c0_s3_coretodctlb_ld_laddr;
assign c0_s3_coretodctlb_ld.imm = c0_s3_coretodctlb_ld_imm;
assign c0_s3_coretodctlb_ld.sptbr = c0_s3_coretodctlb_ld_sptbr;
assign c0_s3_coretodctlb_ld.user = c0_s3_coretodctlb_ld_user;
I_coretodctlb_st_type c0_s3_coretodctlb_st;
assign c0_s3_coretodctlb_st.ckpid = c0_s3_coretodctlb_st_ckpid;
assign c0_s3_coretodctlb_st.coreid = c0_s3_coretodctlb_st_coreid;
assign c0_s3_coretodctlb_st.mop = c0_s3_coretodctlb_st_mop;
assign c0_s3_coretodctlb_st.pnr = c0_s3_coretodctlb_st_pnr;
assign c0_s3_coretodctlb_st.laddr = c0_s3_coretodctlb_st_laddr;
assign c0_s3_coretodctlb_st.imm = c0_s3_coretodctlb_st_imm;
assign c0_s3_coretodctlb_st.sptbr = c0_s3_coretodctlb_st_sptbr;
assign c0_s3_coretodctlb_st.user = c0_s3_coretodctlb_st_user;
`endif
I_pfgtopfe_op_type core0_pfgtopfe_op;
assign core0_pfgtopfe_op.delta = core0_pfgtopfe_op_delta;
assign core0_pfgtopfe_op.w1 = core0_pfgtopfe_op_w1;
assign core0_pfgtopfe_op.w2 = core0_pfgtopfe_op_w2;
assign core0_pfgtopfe_op.pcsign = core0_pfgtopfe_op_pcsign;
assign core0_pfgtopfe_op.laddr = core0_pfgtopfe_op_laddr;
assign core0_pfgtopfe_op.sptbr = core0_pfgtopfe_op_sptbr;
I_coretoic_pc_type core1_coretoic_pc;
assign core1_coretoic_pc.coreid = core1_coretoic_pc_coreid;
assign core1_coretoic_pc.poffset = core1_coretoic_pc_poffset;
I_ictocore_type core1_ictocore;
assign core1_ictocore_coreid = core1_ictocore.coreid;
assign core1_ictocore_fault = core1_ictocore.fault;
assign core1_ictocore_data = core1_ictocore.data;
I_coretodc_ld_type core1_slice0_coretodc_ld;
assign core1_slice0_coretodc_ld.ckpid = core1_slice0_coretodc_ld_ckpid;
assign core1_slice0_coretodc_ld.coreid = core1_slice0_coretodc_ld_coreid;
assign core1_slice0_coretodc_ld.lop = core1_slice0_coretodc_ld_lop;
assign core1_slice0_coretodc_ld.pnr = core1_slice0_coretodc_ld_pnr;
assign core1_slice0_coretodc_ld.pcsign = core1_slice0_coretodc_ld_pcsign;
assign core1_slice0_coretodc_ld.poffset = core1_slice0_coretodc_ld_poffset;
assign core1_slice0_coretodc_ld.imm = core1_slice0_coretodc_ld_imm;
I_dctocore_ld_type core1_slice0_dctocore_ld;
assign core1_slice0_dctocore_ld_coreid = core1_slice0_dctocore_ld.coreid;
assign core1_slice0_dctocore_ld_fault = core1_slice0_dctocore_ld.fault;
assign core1_slice0_dctocore_ld_data = core1_slice0_dctocore_ld.data;
I_coretodc_std_type core1_slice0_coretodc_std;
assign core1_slice0_coretodc_std.ckpid = core1_slice0_coretodc_std_ckpid;
assign core1_slice0_coretodc_std.coreid = core1_slice0_coretodc_std_coreid;
assign core1_slice0_coretodc_std.mop = core1_slice0_coretodc_std_mop;
assign core1_slice0_coretodc_std.pnr = core1_slice0_coretodc_std_pnr;
assign core1_slice0_coretodc_std.pcsign = core1_slice0_coretodc_std_pcsign;
assign core1_slice0_coretodc_std.poffset = core1_slice0_coretodc_std_poffset;
assign core1_slice0_coretodc_std.imm = core1_slice0_coretodc_std_imm;
assign core1_slice0_coretodc_std.data = core1_slice0_coretodc_std_data;
I_dctocore_std_ack_type core1_slice0_dctocore_std_ack;
assign core1_slice0_dctocore_std_ack_fault = core1_slice0_dctocore_std_ack.fault;
assign core1_slice0_dctocore_std_ack_coreid = core1_slice0_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c1_s0_coretodctlb_ld;
assign c1_s0_coretodctlb_ld.ckpid = c1_s0_coretodctlb_ld_ckpid;
assign c1_s0_coretodctlb_ld.coreid = c1_s0_coretodctlb_ld_coreid;
assign c1_s0_coretodctlb_ld.lop = c1_s0_coretodctlb_ld_lop;
assign c1_s0_coretodctlb_ld.pnr = c1_s0_coretodctlb_ld_pnr;
assign c1_s0_coretodctlb_ld.laddr = c1_s0_coretodctlb_ld_laddr;
assign c1_s0_coretodctlb_ld.imm = c1_s0_coretodctlb_ld_imm;
assign c1_s0_coretodctlb_ld.sptbr = c1_s0_coretodctlb_ld_sptbr;
assign c1_s0_coretodctlb_ld.user = c1_s0_coretodctlb_ld_user;
I_coretodctlb_st_type c1_s0_coretodctlb_st;
assign c1_s0_coretodctlb_st.ckpid = c1_s0_coretodctlb_st_ckpid;
assign c1_s0_coretodctlb_st.coreid = c1_s0_coretodctlb_st_coreid;
assign c1_s0_coretodctlb_st.mop = c1_s0_coretodctlb_st_mop;
assign c1_s0_coretodctlb_st.pnr = c1_s0_coretodctlb_st_pnr;
assign c1_s0_coretodctlb_st.laddr = c1_s0_coretodctlb_st_laddr;
assign c1_s0_coretodctlb_st.imm = c1_s0_coretodctlb_st_imm;
assign c1_s0_coretodctlb_st.sptbr = c1_s0_coretodctlb_st_sptbr;
assign c1_s0_coretodctlb_st.user = c1_s0_coretodctlb_st_user;
I_coretodc_ld_type core1_slice1_coretodc_ld;
assign core1_slice1_coretodc_ld.ckpid = core1_slice1_coretodc_ld_ckpid;
assign core1_slice1_coretodc_ld.coreid = core1_slice1_coretodc_ld_coreid;
assign core1_slice1_coretodc_ld.lop = core1_slice1_coretodc_ld_lop;
assign core1_slice1_coretodc_ld.pnr = core1_slice1_coretodc_ld_pnr;
assign core1_slice1_coretodc_ld.pcsign = core1_slice1_coretodc_ld_pcsign;
assign core1_slice1_coretodc_ld.poffset = core1_slice1_coretodc_ld_poffset;
assign core1_slice1_coretodc_ld.imm = core1_slice1_coretodc_ld_imm;
I_dctocore_ld_type core1_slice1_dctocore_ld;
assign core1_slice1_dctocore_ld_coreid = core1_slice1_dctocore_ld.coreid;
assign core1_slice1_dctocore_ld_fault = core1_slice1_dctocore_ld.fault;
assign core1_slice1_dctocore_ld_data = core1_slice1_dctocore_ld.data;
I_coretodc_std_type core1_slice1_coretodc_std;
assign core1_slice1_coretodc_std.ckpid = core1_slice1_coretodc_std_ckpid;
assign core1_slice1_coretodc_std.coreid = core1_slice1_coretodc_std_coreid;
assign core1_slice1_coretodc_std.mop = core1_slice1_coretodc_std_mop;
assign core1_slice1_coretodc_std.pnr = core1_slice1_coretodc_std_pnr;
assign core1_slice1_coretodc_std.pcsign = core1_slice1_coretodc_std_pcsign;
assign core1_slice1_coretodc_std.poffset = core1_slice1_coretodc_std_poffset;
assign core1_slice1_coretodc_std.imm = core1_slice1_coretodc_std_imm;
assign core1_slice1_coretodc_std.data = core1_slice1_coretodc_std_data;
I_dctocore_std_ack_type core1_slice1_dctocore_std_ack;
assign core1_slice1_dctocore_std_ack_fault = core1_slice1_dctocore_std_ack.fault;
assign core1_slice1_dctocore_std_ack_coreid = core1_slice1_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c1_s1_coretodctlb_ld;
assign c1_s1_coretodctlb_ld.ckpid = c1_s1_coretodctlb_ld_ckpid;
assign c1_s1_coretodctlb_ld.coreid = c1_s1_coretodctlb_ld_coreid;
assign c1_s1_coretodctlb_ld.lop = c1_s1_coretodctlb_ld_lop;
assign c1_s1_coretodctlb_ld.pnr = c1_s1_coretodctlb_ld_pnr;
assign c1_s1_coretodctlb_ld.laddr = c1_s1_coretodctlb_ld_laddr;
assign c1_s1_coretodctlb_ld.imm = c1_s1_coretodctlb_ld_imm;
assign c1_s1_coretodctlb_ld.sptbr = c1_s1_coretodctlb_ld_sptbr;
assign c1_s1_coretodctlb_ld.user = c1_s1_coretodctlb_ld_user;
I_coretodctlb_st_type c1_s1_coretodctlb_st;
assign c1_s1_coretodctlb_st.ckpid = c1_s1_coretodctlb_st_ckpid;
assign c1_s1_coretodctlb_st.coreid = c1_s1_coretodctlb_st_coreid;
assign c1_s1_coretodctlb_st.mop = c1_s1_coretodctlb_st_mop;
assign c1_s1_coretodctlb_st.pnr = c1_s1_coretodctlb_st_pnr;
assign c1_s1_coretodctlb_st.laddr = c1_s1_coretodctlb_st_laddr;
assign c1_s1_coretodctlb_st.imm = c1_s1_coretodctlb_st_imm;
assign c1_s1_coretodctlb_st.sptbr = c1_s1_coretodctlb_st_sptbr;
assign c1_s1_coretodctlb_st.user = c1_s1_coretodctlb_st_user;
`ifdef SC_4PIPE
I_coretodc_ld_type core1_slice2_coretodc_ld;
assign core1_slice2_coretodc_ld.ckpid = core1_slice2_coretodc_ld_ckpid;
assign core1_slice2_coretodc_ld.coreid = core1_slice2_coretodc_ld_coreid;
assign core1_slice2_coretodc_ld.lop = core1_slice2_coretodc_ld_lop;
assign core1_slice2_coretodc_ld.pnr = core1_slice2_coretodc_ld_pnr;
assign core1_slice2_coretodc_ld.pcsign = core1_slice2_coretodc_ld_pcsign;
assign core1_slice2_coretodc_ld.poffset = core1_slice2_coretodc_ld_poffset;
assign core1_slice2_coretodc_ld.imm = core1_slice2_coretodc_ld_imm;
I_dctocore_ld_type core1_slice2_dctocore_ld;
assign core1_slice2_dctocore_ld_coreid = core1_slice2_dctocore_ld.coreid;
assign core1_slice2_dctocore_ld_fault = core1_slice2_dctocore_ld.fault;
assign core1_slice2_dctocore_ld_data = core1_slice2_dctocore_ld.data;
I_coretodc_std_type core1_slice2_coretodc_std;
assign core1_slice2_coretodc_std.ckpid = core1_slice2_coretodc_std_ckpid;
assign core1_slice2_coretodc_std.coreid = core1_slice2_coretodc_std_coreid;
assign core1_slice2_coretodc_std.mop = core1_slice2_coretodc_std_mop;
assign core1_slice2_coretodc_std.pnr = core1_slice2_coretodc_std_pnr;
assign core1_slice2_coretodc_std.pcsign = core1_slice2_coretodc_std_pcsign;
assign core1_slice2_coretodc_std.poffset = core1_slice2_coretodc_std_poffset;
assign core1_slice2_coretodc_std.imm = core1_slice2_coretodc_std_imm;
assign core1_slice2_coretodc_std.data = core1_slice2_coretodc_std_data;
I_dctocore_std_ack_type core1_slice2_dctocore_std_ack;
assign core1_slice2_dctocore_std_ack_fault = core1_slice2_dctocore_std_ack.fault;
assign core1_slice2_dctocore_std_ack_coreid = core1_slice2_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c1_s2_coretodctlb_ld;
assign c1_s2_coretodctlb_ld.ckpid = c1_s2_coretodctlb_ld_ckpid;
assign c1_s2_coretodctlb_ld.coreid = c1_s2_coretodctlb_ld_coreid;
assign c1_s2_coretodctlb_ld.lop = c1_s2_coretodctlb_ld_lop;
assign c1_s2_coretodctlb_ld.pnr = c1_s2_coretodctlb_ld_pnr;
assign c1_s2_coretodctlb_ld.laddr = c1_s2_coretodctlb_ld_laddr;
assign c1_s2_coretodctlb_ld.imm = c1_s2_coretodctlb_ld_imm;
assign c1_s2_coretodctlb_ld.sptbr = c1_s2_coretodctlb_ld_sptbr;
assign c1_s2_coretodctlb_ld.user = c1_s2_coretodctlb_ld_user;
I_coretodctlb_st_type c1_s2_coretodctlb_st;
assign c1_s2_coretodctlb_st.ckpid = c1_s2_coretodctlb_st_ckpid;
assign c1_s2_coretodctlb_st.coreid = c1_s2_coretodctlb_st_coreid;
assign c1_s2_coretodctlb_st.mop = c1_s2_coretodctlb_st_mop;
assign c1_s2_coretodctlb_st.pnr = c1_s2_coretodctlb_st_pnr;
assign c1_s2_coretodctlb_st.laddr = c1_s2_coretodctlb_st_laddr;
assign c1_s2_coretodctlb_st.imm = c1_s2_coretodctlb_st_imm;
assign c1_s2_coretodctlb_st.sptbr = c1_s2_coretodctlb_st_sptbr;
assign c1_s2_coretodctlb_st.user = c1_s2_coretodctlb_st_user;
I_coretodc_ld_type core1_slice3_coretodc_ld;
assign core1_slice3_coretodc_ld.ckpid = core1_slice3_coretodc_ld_ckpid;
assign core1_slice3_coretodc_ld.coreid = core1_slice3_coretodc_ld_coreid;
assign core1_slice3_coretodc_ld.lop = core1_slice3_coretodc_ld_lop;
assign core1_slice3_coretodc_ld.pnr = core1_slice3_coretodc_ld_pnr;
assign core1_slice3_coretodc_ld.pcsign = core1_slice3_coretodc_ld_pcsign;
assign core1_slice3_coretodc_ld.poffset = core1_slice3_coretodc_ld_poffset;
assign core1_slice3_coretodc_ld.imm = core1_slice3_coretodc_ld_imm;
I_dctocore_ld_type core1_slice3_dctocore_ld;
assign core1_slice3_dctocore_ld_coreid = core1_slice3_dctocore_ld.coreid;
assign core1_slice3_dctocore_ld_fault = core1_slice3_dctocore_ld.fault;
assign core1_slice3_dctocore_ld_data = core1_slice3_dctocore_ld.data;
I_coretodc_std_type core1_slice3_coretodc_std;
assign core1_slice3_coretodc_std.ckpid = core1_slice3_coretodc_std_ckpid;
assign core1_slice3_coretodc_std.coreid = core1_slice3_coretodc_std_coreid;
assign core1_slice3_coretodc_std.mop = core1_slice3_coretodc_std_mop;
assign core1_slice3_coretodc_std.pnr = core1_slice3_coretodc_std_pnr;
assign core1_slice3_coretodc_std.pcsign = core1_slice3_coretodc_std_pcsign;
assign core1_slice3_coretodc_std.poffset = core1_slice3_coretodc_std_poffset;
assign core1_slice3_coretodc_std.imm = core1_slice3_coretodc_std_imm;
assign core1_slice3_coretodc_std.data = core1_slice3_coretodc_std_data;
I_dctocore_std_ack_type core1_slice3_dctocore_std_ack;
assign core1_slice3_dctocore_std_ack_fault = core1_slice3_dctocore_std_ack.fault;
assign core1_slice3_dctocore_std_ack_coreid = core1_slice3_dctocore_std_ack.coreid;
I_coretodctlb_ld_type c1_s3_coretodctlb_ld;
assign c1_s3_coretodctlb_ld.ckpid = c1_s3_coretodctlb_ld_ckpid;
assign c1_s3_coretodctlb_ld.coreid = c1_s3_coretodctlb_ld_coreid;
assign c1_s3_coretodctlb_ld.lop = c1_s3_coretodctlb_ld_lop;
assign c1_s3_coretodctlb_ld.pnr = c1_s3_coretodctlb_ld_pnr;
assign c1_s3_coretodctlb_ld.laddr = c1_s3_coretodctlb_ld_laddr;
assign c1_s3_coretodctlb_ld.imm = c1_s3_coretodctlb_ld_imm;
assign c1_s3_coretodctlb_ld.sptbr = c1_s3_coretodctlb_ld_sptbr;
assign c1_s3_coretodctlb_ld.user = c1_s3_coretodctlb_ld_user;
I_coretodctlb_st_type c1_s3_coretodctlb_st;
assign c1_s3_coretodctlb_st.ckpid = c1_s3_coretodctlb_st_ckpid;
assign c1_s3_coretodctlb_st.coreid = c1_s3_coretodctlb_st_coreid;
assign c1_s3_coretodctlb_st.mop = c1_s3_coretodctlb_st_mop;
assign c1_s3_coretodctlb_st.pnr = c1_s3_coretodctlb_st_pnr;
assign c1_s3_coretodctlb_st.laddr = c1_s3_coretodctlb_st_laddr;
assign c1_s3_coretodctlb_st.imm = c1_s3_coretodctlb_st_imm;
assign c1_s3_coretodctlb_st.sptbr = c1_s3_coretodctlb_st_sptbr;
assign c1_s3_coretodctlb_st.user = c1_s3_coretodctlb_st_user;
`endif
I_pfgtopfe_op_type core1_pfgtopfe_op;
assign core1_pfgtopfe_op.delta = core1_pfgtopfe_op_delta;
assign core1_pfgtopfe_op.w1 = core1_pfgtopfe_op_w1;
assign core1_pfgtopfe_op.w2 = core1_pfgtopfe_op_w2;
assign core1_pfgtopfe_op.pcsign = core1_pfgtopfe_op_pcsign;
assign core1_pfgtopfe_op.laddr = core1_pfgtopfe_op_laddr;
assign core1_pfgtopfe_op.sptbr = core1_pfgtopfe_op_sptbr;
I_drtomem_req_type dr0_drtomem_req;
assign dr0_drtomem_req_drid = dr0_drtomem_req.drid;
assign dr0_drtomem_req_cmd = dr0_drtomem_req.cmd;
assign dr0_drtomem_req_paddr = dr0_drtomem_req.paddr;
I_memtodr_ack_type dr0_memtodr_ack;
assign dr0_memtodr_ack.drid = dr0_memtodr_ack_drid;
assign dr0_memtodr_ack.nid = dr0_memtodr_ack_nid;
assign dr0_memtodr_ack.paddr = dr0_memtodr_ack_paddr;
assign dr0_memtodr_ack.ack = dr0_memtodr_ack_ack;
assign dr0_memtodr_ack.line = dr0_memtodr_ack_line;
I_drtomem_wb_type dr0_drtomem_wb;
assign dr0_drtomem_wb_line = dr0_drtomem_wb.line;
assign dr0_drtomem_wb_paddr = dr0_drtomem_wb.paddr;
I_drtomem_pfreq_type dr0_drtomem_pfreq;
assign dr0_drtomem_pfreq_nid = dr0_drtomem_pfreq.nid;
assign dr0_drtomem_pfreq_paddr = dr0_drtomem_pfreq.paddr;
I_drtomem_req_type dr1_drtomem_req;
assign dr1_drtomem_req_drid = dr1_drtomem_req.drid;
assign dr1_drtomem_req_cmd = dr1_drtomem_req.cmd;
assign dr1_drtomem_req_paddr = dr1_drtomem_req.paddr;
I_memtodr_ack_type dr1_memtodr_ack;
assign dr1_memtodr_ack.drid = dr1_memtodr_ack_drid;
assign dr1_memtodr_ack.nid = dr1_memtodr_ack_nid;
assign dr1_memtodr_ack.paddr = dr1_memtodr_ack_paddr;
assign dr1_memtodr_ack.ack = dr1_memtodr_ack_ack;
assign dr1_memtodr_ack.line = dr1_memtodr_ack_line;
I_drtomem_wb_type dr1_drtomem_wb;
assign dr1_drtomem_wb_line = dr1_drtomem_wb.line;
assign dr1_drtomem_wb_paddr = dr1_drtomem_wb.paddr;
I_drtomem_pfreq_type dr1_drtomem_pfreq;
assign dr1_drtomem_pfreq_nid = dr1_drtomem_pfreq.nid;
assign dr1_drtomem_pfreq_paddr = dr1_drtomem_pfreq.paddr;
top_2core2dr top(.*);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAP_TB_V
`define SKY130_FD_SC_HS__TAP_TB_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__tap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VPWR = 1'b0;
#60 VGND = 1'b1;
#80 VPWR = 1'b1;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 VPWR = 1'b1;
#160 VGND = 1'b1;
#180 VPWR = 1'bx;
#200 VGND = 1'bx;
end
sky130_fd_sc_hs__tap dut (.VPWR(VPWR), .VGND(VGND));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAP_TB_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// slaveRxStatusMonitor.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
input [1:0] connectStateIn;
input resumeDetectedIn;
input clk;
input rst;
output resetEventOut;
output [1:0] connectStateOut;
output resumeIntOut;
wire [1:0] connectStateIn;
wire resumeDetectedIn;
reg resetEventOut;
reg [1:0] connectStateOut;
reg resumeIntOut;
wire clk;
wire rst;
reg [1:0]oldConnectState;
reg oldResumeDetected;
always @(connectStateIn)
begin
connectStateOut <= connectStateIn;
end
always @(posedge clk)
begin
if (rst == 1'b1)
begin
oldConnectState <= connectStateIn;
oldResumeDetected <= resumeDetectedIn;
end
else
begin
oldConnectState <= connectStateIn;
oldResumeDetected <= resumeDetectedIn;
if (oldConnectState != connectStateIn)
resetEventOut <= 1'b1;
else
resetEventOut <= 1'b0;
if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
resumeIntOut <= 1'b1;
else
resumeIntOut <= 1'b0;
end
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_26x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 203 02/05/2008 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_26x256 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [25:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [25:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [25:0] sub_wire2;
wire sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire [25:0] q = sub_wire2[25:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 26,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "26"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "26"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "26"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 26 0 INPUT NODEFVAL data[25..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 26 0 OUTPUT NODEFVAL q[25..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 26 0 data 0 0 26 0
// Retrieval info: CONNECT: q 0 0 26 0 @q 0 0 26 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_26x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_26x256.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_26x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_26x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_26x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_26x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_26x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_26x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
Data Cache Tiles
Fetch 64 or 48 bits from the data cache.
Support misaligned access up to 32 bits.
Require 32-bit alignment for 64-bit access.
D-Cache Tiles are 4 DWORDs, or 16 bytes.
This cache operates inside the virtual address space.
(WR, OE):
0, 0: Neither read nor write.
0, 1: Read.
1, 0: Write.
1, 1: Read Modify Write.
states:
0: Ready
1: Cool Down
2: Load Tile (Direct 128-bit)
3: Store Tile (Direct 128-bit)
4..7: Load Tile (4x DWORD)
8..B: Store Tile (4x DWORD)
*/
`include "CoreDefs.v"
module DcTile3(
/* verilator lint_off UNUSED */
clock, reset,
regInData, regOutData,
regInAddr, regOutOK,
regInOE, regInWR,
regInOp,
memPcData, memOutData,
memPcAddr, memPcOK,
memPcOE, memPcWR,
memPcOp
);
input clock;
input reset;
input[63:0] regInAddr; //input PC address
input[63:0] regInData; //input data (store)
input regInOE; //Load
input regInWR; //Store
input[4:0] regInOp; //Operation Size/Type
output[63:0] regOutData; //output data (load)
output[1:0] regOutOK; //set if operation suceeds
input[127:0] memPcData; //memory data in
output[127:0] memOutData; //memory data out
output[63:0] memPcAddr; //memory address
output memPcOE; //memory load
output memPcWR; //memory store
input[1:0] memPcOK; //memory OK
output[4:0] memPcOp; //memory PC operation
// reg[31:0] icBlkLo[511:0]; //Block Low DWord
// reg[31:0] icBlkHi[511:0]; //Block High DWord
(* ram_style="block" *) reg[31:0] icBlkA[255:0]; //Block DWord A
(* ram_style="block" *) reg[31:0] icBlkB[255:0]; //Block DWord B
(* ram_style="block" *) reg[31:0] icBlkC[255:0]; //Block DWord C
(* ram_style="block" *) reg[31:0] icBlkD[255:0]; //Block DWord D
(* ram_style="block" *) reg[31:0] icBlkE[255:0]; //Block DWord E
(* ram_style="block" *) reg[27:0] icBlkAd[255:0]; //Block Addresses
(* ram_style="block" *) reg[3:0] icBlkFl[255:0]; //Block Addresses
reg[31:0] tRegInPc1;
reg[31:0] tRegInPc2;
reg[27:0] tBlkNeedAd1;
reg[27:0] tBlkNeedAd2;
reg[27:0] tBlkNeedAd3;
reg[27:0] tBlkNeedAd4;
reg[31:0] tRegInPc3;
reg[31:0] tRegInPc4;
reg[63:0] tBlkData1;
reg[63:0] tBlkData2;
reg[63:0] tBlkData2B;
reg[63:0] tBlkData3;
reg[63:0] tBlkData4;
reg[63:0] tRegOutData;
reg[1:0] tRegOutOK;
reg tRdZx;
reg[63:0] tRegInData;
reg[63:0] tMemPcAddr; //memory address
reg tMemPcOE; //memory load
reg tMemPcWR; //memory store
reg[127:0] tMemOutData; //memory data
reg[4:0] tMemPcOp; //memory operation
assign memPcAddr = tMemPcAddr;
assign memOutData = tMemOutData;
assign memPcOE = tMemPcOE;
assign memPcWR = tMemPcWR;
assign memPcOp = tMemPcOp;
reg[27:0] reqNeedAd;
reg[27:0] nReqNeedAd;
assign regOutData = tRegOutData;
assign regOutOK = tRegOutOK;
assign memPcAddr = tMemPcAddr;
assign memPcOE = tMemPcOE;
reg[63:0] tRegOutDataB;
reg[3:0] isReqTileSt;
reg[27:0] isReqNeedAd;
reg[3:0] nxtReqTileSt;
reg[27:0] nxtReqNeedAd;
reg nxtReqCommit;
reg[27:0] nxtReqCommitAd1;
reg[27:0] nxtReqCommitAd2;
reg[3:0] nxtReqCommitFl;
reg[159:0] reqTempBlk;
reg[159:0] nxtReqTempBlk;
reg[159:0] accTempBlk;
reg accHit;
reg accNoCache;
reg nxtAccHit;
reg accCommitOK;
reg nxtAccCommitOK;
always @*
begin
tRegInPc1=regInAddr[31:0];
tRegInPc2=regInAddr[31:0]+4;
tBlkNeedAd1=tRegInPc1[31:4];
tBlkNeedAd2=tRegInPc2[31:4];
tRegOutData=0;
tRegOutOK=0;
nReqNeedAd=0;
tBlkNeedAd3=tBlkNeedAd1;
tBlkNeedAd4=tBlkNeedAd2;
nxtReqTempBlk=reqTempBlk;
nxtReqCommitFl=0;
tBlkData2=UV64_XX;
nxtReqCommitAd1=28'hXXXXXXX;
nxtReqCommitAd2=28'hXXXXXXX;
nxtAccCommitOK=0;
nxtReqNeedAd=0;
// tMemPcAddr=32'hX;
tMemPcAddr=0;
tMemOutData=128'hX;
tMemPcOE=0;
tMemPcWR=0;
tMemPcOp=0;
nxtAccHit=0;
// accHit=0;
accNoCache=0;
if(regInAddr[31:29]==3'b101)
accNoCache=1;
if(regInAddr[31:29]==3'b110)
accNoCache=1;
if(regInAddr[31:29]==3'b111)
accNoCache=1;
if((regInOE || regInWR) &&
(isReqTileSt==0))
begin
if(accNoCache)
begin
nxtAccHit=0;
// accTempBlk=160'hX;
tMemPcAddr[29:2]=regInAddr[29:2];
tMemOutData={96'h0, regInData[31:0]};
tMemPcOE=regInOE;
tMemPcWR=regInWR;
tMemPcOp=1;
tRegOutOK=memPcOK;
end
else
begin
if((tBlkNeedAd1==icBlkAd[tBlkNeedAd1[7:0]]) &&
(tBlkNeedAd2==icBlkAd[tBlkNeedAd2[7:0]]))
begin
nxtAccHit=1;
end
else if(tBlkNeedAd1==icBlkAd[tBlkNeedAd1[7:0]])
begin
nReqNeedAd=tBlkNeedAd2;
tBlkNeedAd3=tBlkNeedAd2;
end
else
begin
nReqNeedAd=tBlkNeedAd1;
tBlkNeedAd3=tBlkNeedAd1;
end
end
if(nxtAccHit)
begin
/* Read Stage */
case(regInAddr[3:2])
2'b00: tBlkData2=accTempBlk[ 63: 0];
2'b01: tBlkData2=accTempBlk[ 95: 32];
2'b10: tBlkData2=accTempBlk[127: 64];
2'b11: tBlkData2=accTempBlk[159: 96];
endcase
tRdZx = (regInOp[4:2]==3'b011);
case(regInOp[1:0])
2'b00: begin
case(regInAddr[1:0])
2'b00: tRegOutData={
(tBlkData2[ 7] && !tRdZx) ? 56'hF : 56'h0,
tBlkData2[ 7: 0] };
2'b01: tRegOutData={
(tBlkData2[15] && !tRdZx) ? 56'hF : 56'h0,
tBlkData2[15: 8]};
2'b10: tRegOutData={
(tBlkData2[23] && !tRdZx) ? 56'hF : 56'h0,
tBlkData2[23:16]};
2'b11: tRegOutData={
(tBlkData2[31] && !tRdZx) ? 56'hF : 56'h0,
tBlkData2[31:24]};
endcase
end
2'b01: begin
case(regInAddr[1:0])
2'b00: tRegOutData={
(tBlkData2[15] && !tRdZx) ? 48'hF : 48'h0,
tBlkData2[ 15: 0] };
2'b01: tRegOutData={
(tBlkData2[23] && !tRdZx) ? 48'hF : 48'h0,
tBlkData2[23: 8]};
2'b10: tRegOutData={
(tBlkData2[31] && !tRdZx) ? 48'hF : 48'h0,
tBlkData2[31:16]};
2'b11: tRegOutData={
(tBlkData2[39] && !tRdZx) ? 48'hF : 48'h0,
tBlkData2[39:24]};
endcase
end
2'b10: begin
case(regInAddr[1:0])
2'b00: tRegOutData={
(tBlkData2[31] && !tRdZx) ? 32'hF : 32'h0,
tBlkData2[ 31: 0] };
2'b01: tRegOutData={
(tBlkData2[39] && !tRdZx) ? 32'hF : 32'h0,
tBlkData2[39: 8]};
2'b10: tRegOutData={
(tBlkData2[47] && !tRdZx) ? 32'hF : 32'h0,
tBlkData2[47:16]};
2'b11: tRegOutData={
(tBlkData2[55] && !tRdZx) ? 32'hF : 32'h0,
tBlkData2[55:24]};
endcase
end
2'b11: tRegOutData= tBlkData2[63: 0] ;
endcase
/* Write Stage */
tRegInData = regInData;
case(regInOp[4:2])
3'b000: tRegInData = regInData;
3'b001: tRegInData = tRegOutDataB + regInData;
3'b010: tRegInData = tRegOutDataB - regInData;
3'b011: tRegInData = regInData;
3'b100: tRegInData = tRegOutDataB & regInData;
3'b101: tRegInData = tRegOutDataB | regInData;
3'b110: tRegInData = tRegOutDataB ^ regInData;
3'b111: tRegInData = regInData;
endcase
case(regInOp[1:0])
2'b00: begin
case(regInAddr[1:0])
2'b00: begin
tBlkData3[ 7:0]=tRegInData[ 7:0];
tBlkData3[63:8]=tBlkData2B[63:8];
end
2'b01: begin
tBlkData3[ 7: 0]=tBlkData2B[ 7: 0];
tBlkData3[15: 8]=tRegInData[ 7: 0];
tBlkData3[63:16]=tBlkData2B[63:16];
end
2'b10: begin
tBlkData3[15: 0]=tBlkData2B[15: 0];
tBlkData3[23:16]=tRegInData[ 7: 0];
tBlkData3[63:24]=tBlkData2B[63:24];
end
2'b11: begin
tBlkData3[23: 0]=tBlkData2B[23: 0];
tBlkData3[31:24]=tRegInData[ 7: 0];
tBlkData3[63:32]=tBlkData2B[63:32];
end
endcase
end
2'b01: begin
case(regInAddr[1:0])
2'b00: begin
tBlkData3[15: 0]=tRegInData[15: 0];
tBlkData3[63:16]=tBlkData2B[63:16];
end
2'b01: begin
tBlkData3[ 7: 0]=tBlkData2B[ 7: 0];
tBlkData3[23: 8]=tRegInData[15: 0];
tBlkData3[63:24]=tBlkData2B[63:24];
end
2'b10: begin
tBlkData3[15: 0]=tBlkData2B[15: 0];
tBlkData3[31:16]=tRegInData[15: 0];
tBlkData3[63:32]=tBlkData2B[63:32];
end
2'b11: begin
tBlkData3[23: 0]=tBlkData2B[23: 0];
tBlkData3[39:24]=tRegInData[15: 0];
tBlkData3[63:40]=tBlkData2B[63:40];
end
endcase
end
2'b10: begin
case(regInAddr[1:0])
2'b00: begin
tBlkData3[31: 0]=tRegInData[31: 0];
tBlkData3[63:32]=tBlkData2B[63:32];
end
2'b01: begin
tBlkData3[ 7: 0]=tBlkData2B[ 7: 0];
tBlkData3[39: 8]=tRegInData[31: 0];
tBlkData3[63:40]=tBlkData2B[63:40];
end
2'b10: begin
tBlkData3[15: 0]=tBlkData2B[15: 0];
tBlkData3[47:16]=tRegInData[31: 0];
tBlkData3[63:48]=tBlkData2B[63:48];
end
2'b11: begin
tBlkData3[23: 0]=tBlkData2B[23: 0];
tBlkData3[55:24]=tRegInData[31: 0];
tBlkData3[63:56]=tBlkData2B[63:56];
end
endcase
end
2'b11: begin
tBlkData3[63: 0]=tRegInData[63: 0];
end
endcase
// tBlkData4[31: 0]=regInPc[2]?tBlkData3[63:32]:tBlkData3[31: 0];
// tBlkData4[63:32]=regInPc[2]?tBlkData3[31: 0]:tBlkData3[63:32];
nxtReqTempBlk=accTempBlk;
case(regInAddr[3:2])
2'b00: nxtReqTempBlk[ 63: 0]=tBlkData3;
2'b01: nxtReqTempBlk[ 95: 32]=tBlkData3;
2'b10: nxtReqTempBlk[127: 64]=tBlkData3;
2'b11: nxtReqTempBlk[159: 96]=tBlkData3;
endcase
nxtReqCommit=regInWR && accHit;
nxtReqCommitAd1=tBlkNeedAd3;
nxtReqCommitAd2=tBlkNeedAd4;
nxtReqCommitFl=1;
nxtAccCommitOK = regInWR && accHit;
/* Output */
tRegOutOK=((accHit && !regInWR) || accCommitOK) ?
UMEM_OK_OK : UMEM_OK_HOLD;
end
end
nxtReqTileSt=isReqTileSt;
nxtReqCommit=0;
case(isReqTileSt)
4'h0: begin
if(reqNeedAd!=0)
begin
nxtReqNeedAd=reqNeedAd;
nxtReqTileSt=4;
if(icBlkFl[reqNeedAd[7:0]][0])
begin
nxtReqTempBlk=accTempBlk;
nxtReqTileSt=8;
end
end
end
4'h1: begin
nxtReqTileSt=0;
end
4'h2: begin
nxtReqTempBlk[127: 0]=memPcData[127:0];
nxtReqTempBlk[159:128]=memPcData[ 31:0];
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=0;
tMemPcOE=1;
tMemPcWR=0;
tMemPcOp=1;
nxtReqTileSt=4'h1;
nxtReqCommit=1;
nxtReqCommitAd1=isReqNeedAd;
nxtReqCommitAd2=isReqNeedAd;
nxtReqCommitFl=0;
end
4'h3: begin
tMemPcAddr[31:4]=icBlkAd[reqNeedAd[7:0]];
tMemPcAddr[3:2]=0;
tMemOutData[127:0] = nxtReqTempBlk[127: 0];
tMemPcOE=0;
tMemPcWR=1;
tMemPcOp=1;
nxtReqTileSt=4'h1;
end
4'h4: begin
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemPcOE=1;
tMemPcOp=2;
nxtReqTileSt=5;
nxtReqTempBlk[ 31: 0]=memPcData[31:0];
nxtReqTempBlk[159:128]=memPcData[31:0];
end
4'h5: begin
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemPcOE=1;
tMemPcOp=2;
nxtReqTileSt=6;
nxtReqTempBlk[63:32]=memPcData[31:0];
end
4'h6: begin
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemPcOE=1;
tMemPcOp=2;
nxtReqTileSt=7;
nxtReqTempBlk[95:64]=memPcData[31:0];
end
4'h7: begin
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemPcOE=1;
tMemPcOp=2;
nxtReqTileSt=1;
nxtReqTempBlk[127:96]=memPcData[31:0];
nxtReqCommit=1;
nxtReqCommitAd1=isReqNeedAd;
nxtReqCommitAd2=isReqNeedAd;
nxtReqCommitFl=0;
end
4'h8: begin
tMemPcAddr[31:4]=icBlkAd[reqNeedAd[7:0]];
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemOutData[31:0] = nxtReqTempBlk[ 31: 0];
tMemPcWR=1;
tMemPcOp=2;
nxtReqTileSt=4'h9;
end
4'h9: begin
tMemPcAddr[31:4]=icBlkAd[reqNeedAd[7:0]];
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemOutData[31:0] = nxtReqTempBlk[ 63: 32];
tMemPcWR=1;
tMemPcOp=2;
nxtReqTileSt=4'hA;
end
4'hA: begin
tMemPcAddr[31:4]=icBlkAd[reqNeedAd[7:0]];
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemOutData[31:0] = nxtReqTempBlk[ 95: 64];
tMemPcWR=1;
tMemPcOp=2;
nxtReqTileSt=4'hB;
end
4'hB: begin
tMemPcAddr[31:4]=icBlkAd[reqNeedAd[7:0]];
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemOutData[31:0] = nxtReqTempBlk[127: 96];
tMemPcWR=1;
tMemPcOp=2;
nxtReqTileSt=4'h1;
end
default: begin end
endcase
end
always @ (posedge clock)
begin
reqNeedAd <= nReqNeedAd;
isReqNeedAd <= nxtReqNeedAd;
reqTempBlk <= nxtReqTempBlk;
accTempBlk[ 31: 0] <= icBlkA[tBlkNeedAd3[7:0]];
accTempBlk[ 63: 32] <= icBlkB[tBlkNeedAd3[7:0]];
accTempBlk[ 95: 64] <= icBlkC[tBlkNeedAd3[7:0]];
accTempBlk[127: 96] <= icBlkD[tBlkNeedAd3[7:0]];
accTempBlk[159:128] <= icBlkE[tBlkNeedAd4[7:0]];
accHit <= nxtAccHit;
accCommitOK <= nxtAccCommitOK;
tBlkData2B <= tBlkData2;
tRegOutDataB <= tRegOutData;
if(nxtReqCommit)
begin
icBlkA[nxtReqCommitAd1[7:0]] <= nxtReqTempBlk[ 31: 0];
icBlkB[nxtReqCommitAd1[7:0]] <= nxtReqTempBlk[ 63: 32];
icBlkC[nxtReqCommitAd1[7:0]] <= nxtReqTempBlk[ 95: 64];
icBlkD[nxtReqCommitAd1[7:0]] <= nxtReqTempBlk[127: 96];
icBlkE[nxtReqCommitAd2[7:0]] <= nxtReqTempBlk[159:128];
icBlkAd[nxtReqCommitAd1[7:0]] <= nxtReqCommitAd1;
icBlkFl[nxtReqCommitAd1[7:0]] <= nxtReqCommitFl;
end
if(memPcOK==UMEM_OK_OK)
begin
isReqTileSt <= nxtReqTileSt;
end
else if(memPcOK==UMEM_OK_READY)
begin
case(isReqTileSt)
4'h0: begin
isReqTileSt <= nxtReqTileSt;
end
4'h1: begin
isReqTileSt <= nxtReqTileSt;
end
default: begin end
endcase
end
end
endmodule
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module MC6502MemoryController(
clk,
rst_x,
i_rdy,
i_db,
o_db,
o_ab,
o_rw,
o_sync,
// InterruptLogic interfaces
il2mc_addr,
il2mc_read,
il2mc_write,
il2mc_data,
mc2il_data,
mc2il_brk,
// RegisterFile interfaces
rf2mc_pc,
rf2mc_a,
rf2mc_x,
rf2mc_y,
rf2mc_s,
rf2mc_psr,
mc2rf_fetched,
mc2rf_pushed,
mc2rf_pull,
mc2rf_pc,
mc2rf_set_pc,
mc2rf_psr,
mc2rf_set_psr,
// InstructionDecode interfaces
id2mc_fetch,
id2mc_sync,
id2mc_operand,
id2mc_modex,
id2mc_mode,
id2mc_reg,
id2mc_store,
id2mc_push,
id2mc_pop,
id2mc_p_reg,
id2mc_jump,
mc2id_data,
mc2id_valid,
// ExecutionController interfaces
ec2mc_data,
ec2mc_store);
input clk;
input rst_x;
input i_rdy;
input [ 7:0] i_db;
output [ 7:0] o_db;
output [15:0] o_ab;
output o_rw;
output o_sync;
input [15:0] il2mc_addr;
input il2mc_read;
input il2mc_write;
input [ 7:0] il2mc_data;
output [ 7:0] mc2il_data;
output mc2il_brk;
input [15:0] rf2mc_pc;
input [ 7:0] rf2mc_a;
input [ 7:0] rf2mc_x;
input [ 7:0] rf2mc_y;
input [ 7:0] rf2mc_s;
input [ 7:0] rf2mc_psr;
output mc2rf_fetched;
output mc2rf_pushed;
output mc2rf_pull;
output [15:0] mc2rf_pc;
output mc2rf_set_pc;
output [ 7:0] mc2rf_psr;
output mc2rf_set_psr;
input id2mc_fetch;
input id2mc_sync;
input id2mc_operand;
input [ 2:0] id2mc_mode;
input id2mc_modex;
input [ 1:0] id2mc_reg;
input id2mc_store;
input id2mc_push;
input id2mc_pop;
input id2mc_p_reg;
input id2mc_jump;
output [ 7:0] mc2id_data;
output mc2id_valid;
input [ 7:0] ec2mc_data;
input ec2mc_store;
reg [ 2:0] r_operand;
reg r_modex;
reg [ 2:0] r_mode;
reg [15:0] r_data;
reg [ 1:0] r_reg;
reg r_carry;
reg r_store;
reg r_push;
reg r_pop;
reg r_jump;
wire w_adder_valid;
wire [ 8:0] w_adder_sum;
wire [ 7:0] w_adder_in_a;
wire [ 7:0] w_adder_in_b;
wire w_write;
wire w_push_cycle;
wire w_pop_cycle;
wire w_il_active;
wire [15:0] w_il_addr;
wire w_id_active;
wire [15:0] w_id_addr;
wire w_1t_mode;
wire w_2t_mode;
wire w_3t_mode;
wire w_4t_mode;
wire w_5t_mode;
wire w_6t_mode;
wire w_fetch_opcode;
wire w_fetch_next;
wire w_register;
wire w_immediate;
wire w_absolute;
wire w_absolute_pc;
wire w_indirect_pc;
wire w_abs_idx;
wire w_abs_idx_x;
wire w_abs_idx_y;
wire w_zero_page;
wire w_zero_idx;
wire w_zero_idx_x;
wire w_zero_idx_y;
wire w_indirect;
wire w_indirect_x;
wire w_indirect_y;
wire [15:0] w_immediate_addr;
wire [15:0] w_absolute_addr;
wire [15:0] w_abs_idx_addr;
wire [15:0] w_zero_page_addr;
wire [15:0] w_zero_idx_addr;
wire [15:0] w_indirect_addr;
wire [15:0] w_idx_ind_addr;
wire [15:0] w_ind_idx_addr;
wire w_abs_idx_add;
wire w_zero_idx_add;
wire w_idx_ind_add;
wire w_ind_idx_add;
wire [ 7:0] w_register_data;
wire [ 7:0] w_jsr_data;
wire w_jmp;
wire w_jsr;
wire w_brk;
wire w_rts;
wire w_rti;
`include "MC6502Common.vh"
assign o_db = ec2mc_store ? ec2mc_data :
il2mc_write ? il2mc_data :
(r_push & r_jump) ? w_jsr_data :
(r_reg == REG_A) ? rf2mc_a :
(r_reg == REG_Y) ? rf2mc_y :
(r_push & !r_jump) ? rf2mc_psr : rf2mc_x;
assign o_ab = w_il_active ? w_il_addr :
ec2mc_store ? r_data :
w_push_cycle ? { 8'h01, rf2mc_s } :
w_pop_cycle ? { 8'h01, rf2mc_s } : w_id_addr;
assign o_rw = !w_write;
assign o_sync = w_id_active & id2mc_sync;
assign mc2il_data = il2mc_read ? i_db : 8'hxx;
assign mc2il_brk = w_brk & (r_operand == 3'b101);
assign mc2rf_fetched = w_fetch_opcode | w_fetch_next;
assign mc2rf_pushed = w_push_cycle;
assign mc2rf_pull = ((w_rts | w_rti) & ((r_operand == 3'b101) |
(r_operand == 3'b100))) |
(!w_rts & r_pop & (r_operand == 3'b011));
assign mc2rf_pc = (w_jsr | w_rts | w_rti) ? r_data :
{ i_db, r_data[15:8] };
assign mc2rf_set_pc = (w_jmp & ((r_operand == 3'b001) |
((r_operand == 3'b11) & w_indirect_pc))) |
((w_jsr | w_rti)& (r_operand == 3'b001)) |
(w_rts & (r_operand == 3'b010));
assign mc2rf_psr = mc2rf_set_psr ? i_db : 8'hxx;
assign mc2rf_set_psr = w_rti & (r_operand == 3'b100);
assign mc2id_data = (!mc2id_valid | w_write) ? 8'hxx :
(!w_fetch_opcode & w_register) ? w_register_data :
i_db;
assign mc2id_valid = w_fetch_opcode | (r_operand == 3'b001);
assign w_write = (r_store & (r_operand == 3'b001)) |
ec2mc_store | w_push_cycle | il2mc_write;
assign w_push_cycle = (r_push & !r_jump & (r_operand == 3'b010)) |
(w_jsr & ((r_operand == 3'b011) |
(r_operand == 3'b010)));
assign w_pop_cycle = r_pop & ((!r_jump & ((r_operand == 3'b010) |
(r_operand == 3'b001))) |
(r_jump & ((r_operand == 3'b100) |
(r_operand == 3'b011))) |
(w_rti & (r_operand == 3'b010)));
assign w_il_active = il2mc_read | il2mc_write;
assign w_il_addr = il2mc_addr;
assign w_id_active = !w_il_active;
assign w_id_addr = (r_operand == 3'b000) ? rf2mc_pc :
w_immediate ? w_immediate_addr :
w_absolute ? w_absolute_addr :
w_abs_idx ? w_abs_idx_addr :
w_zero_page ? w_zero_page_addr :
w_zero_idx ? w_zero_idx_addr :
w_indirect ? w_indirect_addr : rf2mc_pc;
assign w_1t_mode = !id2mc_push & !id2mc_pop &
((id2mc_modex & (id2mc_mode == MODEX_IMMEDIATE)) |
(!id2mc_modex & (id2mc_mode == MODE_IMMEDIATE)) |
(id2mc_modex & (id2mc_mode == MODEX_REGISTER)));
assign w_2t_mode = (id2mc_mode == MODE_ZERO_PAGE) |
((id2mc_mode == MODEX_ABSOLUTE_PC) & id2mc_jump &
!id2mc_push) |
(id2mc_push & !id2mc_jump);
assign w_3t_mode = ((id2mc_mode == MODE_ABSOLUTE) & !id2mc_jump) |
(id2mc_pop & !id2mc_jump) |
(id2mc_mode == MODE_ZERO_PAGE_INDEX_X) |
(id2mc_mode == MODE_ABSOLUTE_INDEXED_X) |
(id2mc_mode == MODE_ABSOLUTE_INDEXED_Y);
assign w_4t_mode = id2mc_mode == MODE_INDIRECT_INDEX;
assign w_5t_mode = !id2mc_jump & !id2mc_modex &
(id2mc_mode == MODE_INDEXED_INDIRECT) |
(id2mc_jump & id2mc_push & !id2mc_p_reg) |
(id2mc_jump & id2mc_pop);
assign w_6t_mode = (id2mc_jump & id2mc_push & id2mc_p_reg);
assign w_register = r_modex & (r_mode == MODEX_REGISTER);
assign w_immediate = (r_modex & (r_mode == MODEX_IMMEDIATE)) |
(!r_modex & (r_mode == MODE_IMMEDIATE));
assign w_absolute = (r_mode == MODEX_ABSOLUTE) & !r_jump;
assign w_absolute_pc = (r_mode == MODEX_ABSOLUTE_PC) &
(w_jmp | (r_jump & r_push));
assign w_indirect_pc = (r_mode == MODEX_INDIRECT_PC) & w_jmp;
assign w_abs_idx = (r_mode == MODE_ABSOLUTE_INDEXED_X) |
(r_mode == MODE_ABSOLUTE_INDEXED_Y);
assign w_abs_idx_x = !r_modex && (r_mode == MODE_ABSOLUTE_INDEXED_X);
assign w_abs_idx_y = w_abs_idx & !w_abs_idx_x;
assign w_zero_page = r_mode == MODEX_ZERO_PAGE;
assign w_zero_idx = r_mode == MODE_ZERO_PAGE_INDEX_X;
assign w_zero_idx_x = !r_modex & w_zero_idx;
assign w_zero_idx_y = r_modex & w_zero_idx;
assign w_indirect = !r_modex & ((r_mode == MODE_INDEXED_INDIRECT) |
(r_mode == MODE_INDIRECT_INDEX));
assign w_indirect_x = !r_modex & (r_mode == MODE_INDEXED_INDIRECT);
assign w_indirect_y = !r_modex & (r_mode == MODE_INDIRECT_INDEX);
assign w_immediate_addr = rf2mc_pc;
assign w_absolute_addr = (r_operand != 3'b001) ? rf2mc_pc : r_data;
assign w_abs_idx_addr = ((r_operand == 3'b010) && r_carry) ? r_data :
(r_operand == 3'b001) ? r_data : rf2mc_pc;
assign w_zero_page_addr = (r_operand == 3'b010) ? rf2mc_pc :
{ 8'h00, r_data[15:8] };
assign w_zero_idx_addr = (r_operand == 3'b010) ? { 8'h00, r_data[15:8] } :
(r_operand == 3'b001) ? { 8'h00, r_data[7:0] } :
rf2mc_pc;
assign w_idx_ind_addr = (r_operand == 3'b100) ? { 8'h00, r_data[15:8] } :
(r_operand == 3'b011) ? { 8'h00, r_data[7:0] } :
(r_operand == 3'b010) ? { 8'h00, r_data[7:0] } :
(r_operand == 3'b001) ? { 8'h00, r_data[7:0] } :
rf2mc_pc;
assign w_ind_idx_addr = (r_operand == 3'b011) ? { 8'h00, r_data[15:8] } :
(r_operand == 3'b010) ? { 8'h00, r_data[7:0] } :
(r_operand == 3'b001) ? r_data : rf2mc_pc;
assign w_indirect_addr = w_indirect_x ? w_idx_ind_addr : w_ind_idx_addr;
assign w_abs_idx_add = w_abs_idx & (r_operand == 3'b010);
assign w_zero_idx_add = w_zero_idx & (r_operand == 3'b010);
assign w_idx_ind_add = w_indirect_x & ((r_operand == 3'b100) |
(r_operand == 3'b011));
assign w_ind_idx_add = w_indirect_y & ((r_operand == 3'b011) |
(r_operand == 3'b010));
assign w_fetch_opcode = w_id_active & id2mc_fetch & i_rdy;
assign w_fetch_next = ((w_absolute | w_abs_idx) & (r_operand == 3'b011)) |
(w_jmp & (r_operand == 3'b010)) |
(w_indirect_pc & (r_operand == 3'b100)) |
(w_absolute_pc & (r_operand == 3'b010)) |
(!w_register & !r_jump & !r_push & !r_pop &
(r_operand == 3'b001)) |
(w_brk & (r_operand == 3'b110)) |
(w_jsr & (r_operand == 3'b101)) |
(w_rts & (r_operand == 3'b001));
assign w_adder_in_a = (w_idx_ind_add & (r_operand == 3'b011)) ?
r_data[7:0] :
w_adder_valid ? r_data[15:8] : 8'h00;
assign w_adder_in_b = !w_adder_valid ? 8'h00 :
r_carry ? 8'h01 :
(w_idx_ind_add & (r_operand == 3'b011)) ? 8'h01 :
(w_ind_idx_add & (r_operand == 3'b011)) ? 8'h01 :
(w_abs_idx_x | w_zero_idx_x | w_indirect_x) ?
rf2mc_x : rf2mc_y;
assign w_adder_sum = w_adder_in_a + w_adder_in_b;
assign w_adder_valid = (w_abs_idx_add | w_zero_idx_add | w_idx_ind_add |
w_ind_idx_add);
assign w_register_data = (r_reg == REG_A) ? rf2mc_a :
(r_reg == REG_X) ? rf2mc_x :
(r_reg == REG_Y) ? rf2mc_y : rf2mc_s;
assign w_jsr_data = (r_operand == 3'b011) ? rf2mc_pc[15:8] :
rf2mc_pc[7:0];
assign w_jmp = r_jump & !r_push & !r_pop;
assign w_jsr = r_jump & r_push & !r_reg[0];
assign w_brk = r_jump & r_push & r_reg[0];
assign w_rts = r_jump & r_pop & !r_reg[0];
assign w_rti = r_jump & r_pop & r_reg[0];
always @ (posedge clk or negedge rst_x) begin
if (!rst_x) begin
r_operand <= 3'b000;
r_modex <= 1'b0;
r_mode <= 3'b000;
r_data <= 16'h00;
r_reg <= 2'b00;
r_carry <= 1'b0;
r_store <= 1'b0;
r_push <= 1'b0;
r_pop <= 1'b0;
r_jump <= 1'b0;
end else if (id2mc_operand) begin
r_operand <= w_1t_mode ? 3'b001 :
w_2t_mode ? 3'b010 :
w_3t_mode ? 3'b011 :
w_4t_mode ? 3'b100 :
w_5t_mode ? 3'b101 :
w_6t_mode ? 3'b110 : 3'bxxx;
r_modex <= id2mc_modex;
r_mode <= id2mc_mode;
r_reg <= (id2mc_push | id2mc_pop) ? { 1'b0, id2mc_p_reg } : id2mc_reg;
r_store <= id2mc_store;
r_push <= id2mc_push;
r_pop <= id2mc_pop;
r_jump <= id2mc_jump;
end else if (r_operand != 3'b000) begin
if ((w_abs_idx | w_indirect_y) & w_adder_sum[8] & !r_carry) begin
r_carry <= 1'b1;
end else begin
r_operand <= r_operand - 3'b001;
r_carry <= 1'b0;
end
if (r_carry) begin
r_data <= { w_adder_sum[7:0], r_data[7:0] };
end else if (w_adder_valid) begin
r_data <= { i_db, w_adder_sum[7:0] };
end else if (w_jsr & ((r_operand == 3'b011) |
(r_operand == 3'b010))) begin
r_data <= r_data;
end else if (r_operand == 3'b001) begin
r_data <= o_ab;
end else begin
r_data <= { i_db, r_data[15:8] };
end
end
end
endmodule // MC6502MemoryController
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module fpga_core
(
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire [1:0] sw,
input wire [3:0] jp,
output wire [3:0] led,
/*
* Silicon Labs CP2102 USB UART
*/
output wire uart_rst,
input wire uart_suspend,
output wire uart_ri,
output wire uart_dcd,
input wire uart_dtr,
output wire uart_dsr,
input wire uart_txd,
output wire uart_rxd,
input wire uart_rts,
output wire uart_cts,
/*
* AirMax I/O
*/
output wire amh_right_mdc,
input wire amh_right_mdio_i,
output wire amh_right_mdio_o,
output wire amh_right_mdio_t,
output wire amh_left_mdc,
input wire amh_left_mdio_i,
output wire amh_left_mdio_o,
output wire amh_left_mdio_t,
/*
* 10G Ethernet
*/
output wire [63:0] eth_r0_txd,
output wire [7:0] eth_r0_txc,
input wire [63:0] eth_r0_rxd,
input wire [7:0] eth_r0_rxc,
output wire [63:0] eth_r1_txd,
output wire [7:0] eth_r1_txc,
input wire [63:0] eth_r1_rxd,
input wire [7:0] eth_r1_rxc,
output wire [63:0] eth_r2_txd,
output wire [7:0] eth_r2_txc,
input wire [63:0] eth_r2_rxd,
input wire [7:0] eth_r2_rxc,
output wire [63:0] eth_r3_txd,
output wire [7:0] eth_r3_txc,
input wire [63:0] eth_r3_rxd,
input wire [7:0] eth_r3_rxc,
output wire [63:0] eth_r4_txd,
output wire [7:0] eth_r4_txc,
input wire [63:0] eth_r4_rxd,
input wire [7:0] eth_r4_rxc,
output wire [63:0] eth_r5_txd,
output wire [7:0] eth_r5_txc,
input wire [63:0] eth_r5_rxd,
input wire [7:0] eth_r5_rxc,
output wire [63:0] eth_r6_txd,
output wire [7:0] eth_r6_txc,
input wire [63:0] eth_r6_rxd,
input wire [7:0] eth_r6_rxc,
output wire [63:0] eth_r7_txd,
output wire [7:0] eth_r7_txc,
input wire [63:0] eth_r7_rxd,
input wire [7:0] eth_r7_rxc,
output wire [63:0] eth_r8_txd,
output wire [7:0] eth_r8_txc,
input wire [63:0] eth_r8_rxd,
input wire [7:0] eth_r8_rxc,
output wire [63:0] eth_r9_txd,
output wire [7:0] eth_r9_txc,
input wire [63:0] eth_r9_rxd,
input wire [7:0] eth_r9_rxc,
output wire [63:0] eth_r10_txd,
output wire [7:0] eth_r10_txc,
input wire [63:0] eth_r10_rxd,
input wire [7:0] eth_r10_rxc,
output wire [63:0] eth_r11_txd,
output wire [7:0] eth_r11_txc,
input wire [63:0] eth_r11_rxd,
input wire [7:0] eth_r11_rxc,
output wire [63:0] eth_l0_txd,
output wire [7:0] eth_l0_txc,
input wire [63:0] eth_l0_rxd,
input wire [7:0] eth_l0_rxc,
output wire [63:0] eth_l1_txd,
output wire [7:0] eth_l1_txc,
input wire [63:0] eth_l1_rxd,
input wire [7:0] eth_l1_rxc,
output wire [63:0] eth_l2_txd,
output wire [7:0] eth_l2_txc,
input wire [63:0] eth_l2_rxd,
input wire [7:0] eth_l2_rxc,
output wire [63:0] eth_l3_txd,
output wire [7:0] eth_l3_txc,
input wire [63:0] eth_l3_rxd,
input wire [7:0] eth_l3_rxc,
output wire [63:0] eth_l4_txd,
output wire [7:0] eth_l4_txc,
input wire [63:0] eth_l4_rxd,
input wire [7:0] eth_l4_rxc,
output wire [63:0] eth_l5_txd,
output wire [7:0] eth_l5_txc,
input wire [63:0] eth_l5_rxd,
input wire [7:0] eth_l5_rxc,
output wire [63:0] eth_l6_txd,
output wire [7:0] eth_l6_txc,
input wire [63:0] eth_l6_rxd,
input wire [7:0] eth_l6_rxc,
output wire [63:0] eth_l7_txd,
output wire [7:0] eth_l7_txc,
input wire [63:0] eth_l7_rxd,
input wire [7:0] eth_l7_rxc,
output wire [63:0] eth_l8_txd,
output wire [7:0] eth_l8_txc,
input wire [63:0] eth_l8_rxd,
input wire [7:0] eth_l8_rxc,
output wire [63:0] eth_l9_txd,
output wire [7:0] eth_l9_txc,
input wire [63:0] eth_l9_rxd,
input wire [7:0] eth_l9_rxc,
output wire [63:0] eth_l10_txd,
output wire [7:0] eth_l10_txc,
input wire [63:0] eth_l10_rxd,
input wire [7:0] eth_l10_rxc,
output wire [63:0] eth_l11_txd,
output wire [7:0] eth_l11_txc,
input wire [63:0] eth_l11_rxd,
input wire [7:0] eth_l11_rxc
);
// UART
assign uart_rst = 1'b1;
assign uart_txd = 1'b1;
// AirMax I/O
assign amh_right_mdc = 1'b1;
assign amh_right_mdio_o = 1'b1;
assign amh_right_mdio_t = 1'b1;
assign amh_left_mdc = 1'b1;
assign amh_left_mdio_o = 1'b1;
assign amh_left_mdio_t = 1'b1;
assign eth_l8_txd = 64'h0707070707070707;
assign eth_l8_txc = 8'hff;
assign eth_l9_txd = 64'h0707070707070707;
assign eth_l9_txc = 8'hff;
assign eth_l10_txd = 64'h0707070707070707;
assign eth_l10_txc = 8'hff;
//assign eth_l11_txd = 64'h0707070707070707;
//assign eth_l11_txc = 8'hff;
assign eth_r8_txd = 64'h0707070707070707;
assign eth_r8_txc = 8'hff;
assign eth_r9_txd = 64'h0707070707070707;
assign eth_r9_txc = 8'hff;
assign eth_r10_txd = 64'h0707070707070707;
assign eth_r10_txc = 8'hff;
assign eth_r11_txd = 64'h0707070707070707;
assign eth_r11_txc = 8'hff;
reg [7:0] select_reg_0 = 0;
reg [7:0] select_reg_1 = 1;
reg [7:0] select_reg_2 = 2;
reg [7:0] select_reg_3 = 3;
reg [7:0] select_reg_4 = 4;
reg [7:0] select_reg_5 = 5;
reg [7:0] select_reg_6 = 6;
reg [7:0] select_reg_7 = 7;
reg [7:0] select_reg_8 = 8;
reg [7:0] select_reg_9 = 9;
reg [7:0] select_reg_10 = 10;
reg [7:0] select_reg_11 = 11;
reg [7:0] select_reg_12 = 12;
reg [7:0] select_reg_13 = 13;
reg [7:0] select_reg_14 = 14;
reg [7:0] select_reg_15 = 15;
axis_crosspoint #(
.S_COUNT(16),
.M_COUNT(16),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0)
)
axis_crosspoint_inst (
.clk(clk),
.rst(rst),
.s_axis_tdata({eth_r7_rxd, eth_r6_rxd, eth_r5_rxd, eth_r4_rxd, eth_r3_rxd, eth_r2_rxd, eth_r1_rxd, eth_r0_rxd, eth_l7_rxd, eth_l6_rxd, eth_l5_rxd, eth_l4_rxd, eth_l3_rxd, eth_l2_rxd, eth_l1_rxd, eth_l0_rxd}),
.s_axis_tkeep({eth_r7_rxc, eth_r6_rxc, eth_r5_rxc, eth_r4_rxc, eth_r3_rxc, eth_r2_rxc, eth_r1_rxc, eth_r0_rxc, eth_l7_rxc, eth_l6_rxc, eth_l5_rxc, eth_l4_rxc, eth_l3_rxc, eth_l2_rxc, eth_l1_rxc, eth_l0_rxc}),
.s_axis_tvalid(16'hffff),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
.m_axis_tdata({eth_r7_txd, eth_r6_txd, eth_r5_txd, eth_r4_txd, eth_r3_txd, eth_r2_txd, eth_r1_txd, eth_r0_txd, eth_l7_txd, eth_l6_txd, eth_l5_txd, eth_l4_txd, eth_l3_txd, eth_l2_txd, eth_l1_txd, eth_l0_txd}),
.m_axis_tkeep({eth_r7_txc, eth_r6_txc, eth_r5_txc, eth_r4_txc, eth_r3_txc, eth_r2_txc, eth_r1_txc, eth_r0_txc, eth_l7_txc, eth_l6_txc, eth_l5_txc, eth_l4_txc, eth_l3_txc, eth_l2_txc, eth_l1_txc, eth_l0_txc}),
.m_axis_tvalid(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.select({select_reg_15[3:0], select_reg_14[3:0], select_reg_13[3:0], select_reg_12[3:0], select_reg_11[3:0], select_reg_10[3:0], select_reg_9[3:0], select_reg_8[3:0], select_reg_7[3:0], select_reg_6[3:0], select_reg_5[3:0], select_reg_4[3:0], select_reg_3[3:0], select_reg_2[3:0], select_reg_1[3:0], select_reg_0[3:0]})
);
wire [63:0] eth_rx_axis_tdata;
wire [7:0] eth_rx_axis_tkeep;
wire eth_rx_axis_tvalid;
wire eth_rx_axis_tready;
wire eth_rx_axis_tlast;
wire eth_rx_axis_tuser;
wire eth_rx_hdr_valid;
wire eth_rx_hdr_ready;
wire [47:0] eth_rx_dest_mac;
wire [47:0] eth_rx_src_mac;
wire [15:0] eth_rx_type;
wire [63:0] eth_rx_payload_axis_tdata;
wire [7:0] eth_rx_payload_axis_tkeep;
wire eth_rx_payload_axis_tvalid;
wire eth_rx_payload_axis_tready;
wire eth_rx_payload_axis_tlast;
wire eth_rx_payload_axis_tuser;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_fifo_inst (
.rx_clk(clk),
.rx_rst(rst),
.tx_clk(clk),
.tx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(0),
.tx_axis_tkeep(0),
.tx_axis_tvalid(0),
.tx_axis_tready(),
.tx_axis_tlast(0),
.tx_axis_tuser(0),
.rx_axis_tdata(eth_rx_axis_tdata),
.rx_axis_tkeep(eth_rx_axis_tkeep),
.rx_axis_tvalid(eth_rx_axis_tvalid),
.rx_axis_tready(eth_rx_axis_tready),
.rx_axis_tlast(eth_rx_axis_tlast),
.rx_axis_tuser(eth_rx_axis_tuser),
.xgmii_rxd(eth_l11_rxd),
.xgmii_rxc(eth_l11_rxc),
.xgmii_txd(eth_l11_txd),
.xgmii_txc(eth_l11_txc),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
);
eth_axis_rx #(
.DATA_WIDTH(64),
.KEEP_WIDTH(8)
)
eth_axis_rxinst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(eth_rx_axis_tdata),
.s_axis_tkeep(eth_rx_axis_tkeep),
.s_axis_tvalid(eth_rx_axis_tvalid),
.s_axis_tready(eth_rx_axis_tready),
.s_axis_tlast(eth_rx_axis_tlast),
.s_axis_tuser(eth_rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(eth_rx_hdr_valid),
.m_eth_hdr_ready(eth_rx_hdr_ready),
.m_eth_dest_mac(eth_rx_dest_mac),
.m_eth_src_mac(eth_rx_src_mac),
.m_eth_type(eth_rx_type),
.m_eth_payload_axis_tdata(eth_rx_payload_axis_tdata),
.m_eth_payload_axis_tkeep(eth_rx_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(eth_rx_payload_axis_tvalid),
.m_eth_payload_axis_tready(eth_rx_payload_axis_tready),
.m_eth_payload_axis_tlast(eth_rx_payload_axis_tlast),
.m_eth_payload_axis_tuser(eth_rx_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
// interpret config packet
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WORD_0 = 3'd1,
STATE_WORD_1 = 3'd2,
STATE_WAIT = 3'd3;
reg [2:0] state_reg = STATE_IDLE;
reg eth_rx_hdr_ready_reg = 0;
reg eth_rx_payload_axis_tready_reg = 0;
assign eth_rx_hdr_ready = eth_rx_hdr_ready_reg;
assign eth_rx_payload_axis_tready = eth_rx_payload_axis_tready_reg;
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 0;
select_reg_0 <= 0;
select_reg_1 <= 1;
select_reg_2 <= 2;
select_reg_3 <= 3;
select_reg_4 <= 4;
select_reg_5 <= 5;
select_reg_6 <= 6;
select_reg_7 <= 7;
select_reg_8 <= 8;
select_reg_9 <= 9;
select_reg_10 <= 10;
select_reg_11 <= 11;
select_reg_12 <= 12;
select_reg_13 <= 13;
select_reg_14 <= 14;
select_reg_15 <= 15;
end else begin
case (state_reg)
STATE_IDLE: begin
eth_rx_hdr_ready_reg <= 1;
eth_rx_payload_axis_tready_reg <= 0;
if (eth_rx_hdr_ready && eth_rx_hdr_valid) begin
if (eth_rx_type == 16'h8099) begin
state_reg <= STATE_WORD_0;
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
end else begin
state_reg <= STATE_WAIT;
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
end
end
end
STATE_WORD_0: begin
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
if (eth_rx_payload_axis_tready && eth_rx_payload_axis_tvalid) begin
if (eth_rx_payload_axis_tlast) begin
state_reg <= STATE_IDLE;
eth_rx_hdr_ready_reg <= 1;
eth_rx_payload_axis_tready_reg <= 0;
end else begin
select_reg_0 <= eth_rx_payload_axis_tdata[7:0];
select_reg_1 <= eth_rx_payload_axis_tdata[15:8];
select_reg_2 <= eth_rx_payload_axis_tdata[23:16];
select_reg_3 <= eth_rx_payload_axis_tdata[31:24];
select_reg_4 <= eth_rx_payload_axis_tdata[39:32];
select_reg_5 <= eth_rx_payload_axis_tdata[47:40];
select_reg_6 <= eth_rx_payload_axis_tdata[55:48];
select_reg_7 <= eth_rx_payload_axis_tdata[63:56];
state_reg <= STATE_WORD_1;
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
end
end
end
STATE_WORD_1: begin
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
if (eth_rx_payload_axis_tready && eth_rx_payload_axis_tvalid) begin
if (eth_rx_payload_axis_tlast) begin
state_reg <= STATE_IDLE;
eth_rx_hdr_ready_reg <= 1;
eth_rx_payload_axis_tready_reg <= 0;
end else begin
select_reg_8 <= eth_rx_payload_axis_tdata[7:0];
select_reg_9 <= eth_rx_payload_axis_tdata[15:8];
select_reg_10 <= eth_rx_payload_axis_tdata[23:16];
select_reg_11 <= eth_rx_payload_axis_tdata[31:24];
select_reg_12 <= eth_rx_payload_axis_tdata[39:32];
select_reg_13 <= eth_rx_payload_axis_tdata[47:40];
select_reg_14 <= eth_rx_payload_axis_tdata[55:48];
select_reg_15 <= eth_rx_payload_axis_tdata[63:56];
state_reg <= STATE_WAIT;
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
end
end
end
STATE_WAIT: begin
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
if (eth_rx_payload_axis_tready && eth_rx_payload_axis_tvalid) begin
if (eth_rx_payload_axis_tlast) begin
state_reg <= STATE_IDLE;
eth_rx_hdr_ready_reg <= 1;
eth_rx_payload_axis_tready_reg <= 0;
end else begin
state_reg <= STATE_WAIT;
eth_rx_hdr_ready_reg <= 0;
eth_rx_payload_axis_tready_reg <= 1;
end
end
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//----------------------------------------------------------
//Copyright (c) 2016, Xilinx, Inc.
//All rights reserved.
//
//Redistribution and use in source and binary forms, with or without modification,
//are permitted provided that the following conditions are met:
//
//1. Redistributions of source code must retain the above copyright notice,
//this list of conditions and the following disclaimer.
//
//2. Redistributions in binary form must reproduce the above copyright notice,
//this list of conditions and the following disclaimer in the documentation
//and/or other materials provided with the distribution.
//
//3. Neither the name of the copyright holder nor the names of its contributors
//may be used to endorse or promote products derived from this software
//without specific prior written permission.
//
//THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
//ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
//THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
//INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
//PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
//HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
//OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
//EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//----------------------------------------------------------
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.11.2013 10:48:44
// Design Name:
// Module Name: tcp_ip_wrapper
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tcp_ip_wrapper #(
parameter MAC_ADDRESS = 48'hE59D02350A00, // LSB first, 00:0A:35:02:9D:E5
parameter IP_ADDRESS = 32'h00000000,
parameter IP_SUBNET_MASK = 32'h00FFFFFF,
parameter IP_DEFAULT_GATEWAY = 32'h00000000,
parameter DHCP_EN = 0
)(
input aclk,
//input reset,
input aresetn,
// network interface streams
output AXI_M_Stream_TVALID,
input AXI_M_Stream_TREADY,
output[63:0] AXI_M_Stream_TDATA,
output[7:0] AXI_M_Stream_TKEEP,
output AXI_M_Stream_TLAST,
input AXI_S_Stream_TVALID,
output AXI_S_Stream_TREADY,
input[63:0] AXI_S_Stream_TDATA,
input[7:0] AXI_S_Stream_TKEEP,
input AXI_S_Stream_TLAST,
// memory rx cmd streams
output m_axis_rxread_cmd_TVALID,
input m_axis_rxread_cmd_TREADY,
output[71:0] m_axis_rxread_cmd_TDATA,
output m_axis_rxwrite_cmd_TVALID,
input m_axis_rxwrite_cmd_TREADY,
output[71:0] m_axis_rxwrite_cmd_TDATA,
// memory rx sts streams
input s_axis_rxread_sts_TVALID,
output s_axis_rxread_sts_TREADY,
input[7:0] s_axis_rxread_sts_TDATA,
input s_axis_rxwrite_sts_TVALID,
output s_axis_rxwrite_sts_TREADY,
input[31:0] s_axis_rxwrite_sts_TDATA,
// memory rx data streams
input s_axis_rxread_data_TVALID,
output s_axis_rxread_data_TREADY,
input[63:0] s_axis_rxread_data_TDATA,
input[7:0] s_axis_rxread_data_TKEEP,
input s_axis_rxread_data_TLAST,
output m_axis_rxwrite_data_TVALID,
input m_axis_rxwrite_data_TREADY,
output[63:0] m_axis_rxwrite_data_TDATA,
output[7:0] m_axis_rxwrite_data_TKEEP,
output m_axis_rxwrite_data_TLAST,
// memory tx cmd streams
output m_axis_txread_cmd_TVALID,
input m_axis_txread_cmd_TREADY,
output[71:0] m_axis_txread_cmd_TDATA,
output m_axis_txwrite_cmd_TVALID,
input m_axis_txwrite_cmd_TREADY,
output[71:0] m_axis_txwrite_cmd_TDATA,
// memory tx sts streams
input s_axis_txread_sts_TVALID,
output s_axis_txread_sts_TREADY,
input[7:0] s_axis_txread_sts_TDATA,
input s_axis_txwrite_sts_TVALID,
output s_axis_txwrite_sts_TREADY,
input[63:0] s_axis_txwrite_sts_TDATA,
// memory tx data streams
input s_axis_txread_data_TVALID,
output s_axis_txread_data_TREADY,
input[63:0] s_axis_txread_data_TDATA,
input[7:0] s_axis_txread_data_TKEEP,
input s_axis_txread_data_TLAST,
output m_axis_txwrite_data_TVALID,
input m_axis_txwrite_data_TREADY,
output[63:0] m_axis_txwrite_data_TDATA,
output[7:0] m_axis_txwrite_data_TKEEP,
output m_axis_txwrite_data_TLAST,
//application interface streams
output m_axis_listen_port_status_TVALID,
input m_axis_listen_port_status_TREADY,
output[7:0] m_axis_listen_port_status_TDATA,
output m_axis_notifications_TVALID,
input m_axis_notifications_TREADY,
output[87:0] m_axis_notifications_TDATA,
output m_axis_open_status_TVALID,
input m_axis_open_status_TREADY,
output[23:0] m_axis_open_status_TDATA,
output m_axis_rx_data_TVALID,
input m_axis_rx_data_TREADY,
output[63:0] m_axis_rx_data_TDATA,
output[7:0] m_axis_rx_data_TKEEP,
output m_axis_rx_data_TLAST,
output m_axis_rx_metadata_TVALID,
input m_axis_rx_metadata_TREADY,
output[15:0] m_axis_rx_metadata_TDATA,
output m_axis_tx_status_TVALID,
input m_axis_tx_status_TREADY,
output[63:0] m_axis_tx_status_TDATA,
input s_axis_listen_port_TVALID,
output s_axis_listen_port_TREADY,
input[15:0] s_axis_listen_port_TDATA,
//input s_axis_close_port_TVALID,
//output s_axis_close_port_TREADY,
//input[15:0] s_axis_close_port_TDATA,
input s_axis_close_connection_TVALID,
output s_axis_close_connection_TREADY,
input[15:0] s_axis_close_connection_TDATA,
input s_axis_open_connection_TVALID,
output s_axis_open_connection_TREADY,
input[47:0] s_axis_open_connection_TDATA,
input s_axis_read_package_TVALID,
output s_axis_read_package_TREADY,
input[31:0] s_axis_read_package_TDATA,
input s_axis_tx_data_TVALID,
output s_axis_tx_data_TREADY,
input[63:0] s_axis_tx_data_TDATA,
input[7:0] s_axis_tx_data_TKEEP,
input s_axis_tx_data_TLAST,
input s_axis_tx_metadata_TVALID,
output s_axis_tx_metadata_TREADY,
input[31:0] s_axis_tx_metadata_TDATA, //change to 15?
//debug
output debug_axi_intercon_to_mie_tready,
output debug_axi_intercon_to_mie_tvalid,
output debug_axi_slice_toe_mie_tvalid,
output debug_axi_slice_toe_mie_tready,
output [161:0] debug_out,
output[31:0] ip_address_out,
output[15:0] regSessionCount_V,
output regSessionCount_V_ap_vld,
input[3:0] board_number,
input[1:0] subnet_number
);
// cmd streams
wire axis_rxread_cmd_TVALID;
wire axis_rxread_cmd_TREADY;
wire[71:0] axis_rxread_cmd_TDATA;
wire axis_rxwrite_cmd_TVALID;
wire axis_rxwrite_cmd_TREADY;
wire[71:0] axis_rxwrite_cmd_TDATA;
wire axis_txread_cmd_TVALID;
wire axis_txread_cmd_TREADY;
wire[71:0] axis_txread_cmd_TDATA;
wire axis_txwrite_cmd_TVALID;
wire axis_txwrite_cmd_TREADY;
wire[71:0] axis_txwrite_cmd_TDATA;
// sts streams
wire axis_rxread_sts_TVALID;
wire axis_rxread_sts_TREADY;
wire[7:0] axis_rxread_sts_TDATA;
wire axis_rxwrite_sts_TVALID;
wire axis_rxwrite_sts_TREADY;
wire[7:0] axis_rxwrite_sts_TDATA;
wire axis_txread_sts_TVALID;
wire axis_txread_sts_TREADY;
wire[7:0] axis_txread_sts_TDATA;
wire axis_txwrite_sts_TVALID;
wire axis_txwrite_sts_TREADY;
wire[63:0] axis_txwrite_sts_TDATA;
//data streams
wire axis_rxbuffer2app_TVALID;
wire axis_rxbuffer2app_TREADY;
wire[63:0] axis_rxbuffer2app_TDATA;
wire[7:0] axis_rxbuffer2app_TKEEP;
wire axis_rxbuffer2app_TLAST;
wire axis_tcp2rxbuffer_TVALID;
wire axis_tcp2rxbuffer_TREADY;
wire[63:0] axis_tcp2rxbuffer_TDATA;
wire[7:0] axis_tcp2rxbuffer_TKEEP;
wire axis_tcp2rxbuffer_TLAST;
wire axis_txbuffer2tcp_TVALID;
wire axis_txbuffer2tcp_TREADY;
wire[63:0] axis_txbuffer2tcp_TDATA;
wire[7:0] axis_txbuffer2tcp_TKEEP;
wire axis_txbuffer2tcp_TLAST;
wire axis_app2txbuffer_TVALID;
wire axis_app2txbuffer_TREADY;
wire[63:0] axis_app2txbuffer_TDATA;
wire[7:0] axis_app2txbuffer_TKEEP;
wire axis_app2txbuffer_TLAST;
wire upd_req_TVALID;
wire upd_req_TREADY;
wire[111:0] upd_req_TDATA; //(1 + 1 + 14 + 96) - 1 = 111
wire upd_rsp_TVALID;
wire upd_rsp_TREADY;
wire[15:0] upd_rsp_TDATA;
wire ins_req_TVALID;
wire ins_req_TREADY;
wire[111:0] ins_req_TDATA;
wire del_req_TVALID;
wire del_req_TREADY;
wire[111:0] del_req_TDATA;
wire lup_req_TVALID;
wire lup_req_TREADY;
wire[97:0] lup_req_TDATA; //should be 96, also wrong in SmartCam
wire lup_rsp_TVALID;
wire lup_rsp_TREADY;
wire[15:0] lup_rsp_TDATA;
//wire[14:0] free_list_data_count;
// IP Handler Outputs
wire axi_iph_to_arp_slice_tvalid;
wire axi_iph_to_arp_slice_tready;
wire[63:0] axi_iph_to_arp_slice_tdata;
wire[7:0] axi_iph_to_arp_slice_tkeep;
wire axi_iph_to_arp_slice_tlast;
wire axi_iph_to_icmp_slice_tvalid;
wire axi_iph_to_icmp_slice_tready;
wire[63:0] axi_iph_to_icmp_slice_tdata;
wire[7:0] axi_iph_to_icmp_slice_tkeep;
wire axi_iph_to_icmp_slice_tlast;
wire axi_iph_to_udp_slice_tvalid;
wire axi_iph_to_udp_slice_tready;
wire[63:0] axi_iph_to_udp_slice_tdata;
wire[7:0] axi_iph_to_udp_slice_tkeep;
wire axi_iph_to_udp_slice_tlast;
wire axi_iph_to_toe_slice_tvalid;
wire axi_iph_to_toe_slice_tready;
wire[63:0] axi_iph_to_toe_slice_tdata;
wire[7:0] axi_iph_to_toe_slice_tkeep;
wire axi_iph_to_toe_slice_tlast;
//Slice connections on RX path
wire axi_arp_slice_to_arp_tvalid;
wire axi_arp_slice_to_arp_tready;
wire[63:0] axi_arp_slice_to_arp_tdata;
wire[7:0] axi_arp_slice_to_arp_tkeep;
wire axi_arp_slice_to_arp_tlast;
wire axi_icmp_slice_to_icmp_tvalid;
wire axi_icmp_slice_to_icmp_tready;
wire[63:0] axi_icmp_slice_to_icmp_tdata;
wire[7:0] axi_icmp_slice_to_icmp_tkeep;
wire axi_icmp_slice_to_icmp_tlast;
wire axi_udp_slice_to_udp_tvalid;
wire axi_udp_slice_to_udp_tready;
wire[63:0] axi_udp_slice_to_udp_tdata;
wire[7:0] axi_udp_slice_to_udp_tkeep;
wire axi_udp_slice_to_udp_tlast;
wire axi_toe_slice_to_toe_tvalid;
wire axi_toe_slice_to_toe_tready;
wire[63:0] axi_toe_slice_to_toe_tdata;
wire[7:0] axi_toe_slice_to_toe_tkeep;
wire axi_toe_slice_to_toe_tlast;
// MAC-IP Encode Inputs
wire axi_intercon_to_mie_tvalid;
wire axi_intercon_to_mie_tready;
wire[63:0] axi_intercon_to_mie_tdata;
wire[7:0] axi_intercon_to_mie_tkeep;
wire axi_intercon_to_mie_tlast;
wire axi_mie_to_intercon_tvalid;
wire axi_mie_to_intercon_tready;
wire[63:0] axi_mie_to_intercon_tdata;
wire[7:0] axi_mie_to_intercon_tkeep;
wire axi_mie_to_intercon_tlast;
/*wire axi_arp_slice_to_mie_tvalid;
wire axi_arp_slice_to_mie_tready;
wire[63:0] axi_arp_slice_to_mie_tdata;
wire[7:0] axi_arp_slice_to_mie_tkeep;
wire axi_arp_slice_to_mie_tlast;
wire axi_icmp_slice_to_mie_tvalid;
wire axi_icmp_slice_to_mie_tready;
wire[63:0] axi_icmp_slice_to_mie_tdata;
wire[7:0] axi_icmp_slice_to_mie_tkeep;
wire axi_icmp_slice_to_mie_tlast;
wire axi_toe_slice_to_mie_tvalid;
wire axi_toe_slice_to_mie_tready;
wire[63:0] axi_toe_slice_to_mie_tdata;
wire[7:0] axi_toe_slice_to_mie_tkeep;
wire axi_toe_slice_to_mie_tlast;*/
//Slice connections on RX path
wire axi_arp_to_arp_slice_tvalid;
wire axi_arp_to_arp_slice_tready;
wire[63:0] axi_arp_to_arp_slice_tdata;
wire[7:0] axi_arp_to_arp_slice_tkeep;
wire axi_arp_to_arp_slice_tlast;
wire axi_icmp_to_icmp_slice_tvalid;
wire axi_icmp_to_icmp_slice_tready;
wire[63:0] axi_icmp_to_icmp_slice_tdata;
wire[7:0] axi_icmp_to_icmp_slice_tkeep;
wire axi_icmp_to_icmp_slice_tlast;
wire axi_toe_to_toe_slice_tvalid;
wire axi_toe_to_toe_slice_tready;
wire[63:0] axi_toe_to_toe_slice_tdata;
wire[7:0] axi_toe_to_toe_slice_tkeep;
wire axi_toe_to_toe_slice_tlast;
wire axi_udp_to_merge_tvalid;
wire axi_udp_to_merge_tready;
wire[63:0] axi_udp_to_merge_tdata;
wire[7:0] axi_udp_to_merge_tkeep;
wire axi_udp_to_merge_tlast;
wire cam_ready;
wire sc_led0;
wire sc_led1;
wire[255:0] sc_debug;
wire [157:0] debug_out_ips;
assign debug_axi_intercon_to_mie_tready = axi_intercon_to_mie_tready;
assign debug_axi_intercon_to_mie_tvalid = axi_intercon_to_mie_tvalid;
assign debug_axi_slice_toe_mie_tvalid = axi_mie_to_intercon_tvalid;
assign debug_axi_slice_toe_mie_tready = axi_mie_to_intercon_tready;
// RX assignments
assign m_axis_rxread_cmd_TVALID = axis_rxread_cmd_TVALID;
assign axis_rxread_cmd_TREADY = m_axis_rxread_cmd_TREADY;
assign m_axis_rxread_cmd_TDATA = axis_rxread_cmd_TDATA;
assign m_axis_rxwrite_cmd_TVALID = axis_rxwrite_cmd_TVALID;
assign axis_rxwrite_cmd_TREADY = m_axis_rxwrite_cmd_TREADY;
assign m_axis_rxwrite_cmd_TDATA = axis_rxwrite_cmd_TDATA;
assign axis_rxread_sts_TVALID = s_axis_rxread_sts_TVALID;
assign s_axis_rxread_sts_TREADY = axis_rxread_sts_TREADY;
assign axis_rxread_sts_TDATA = s_axis_rxread_sts_TDATA;
assign axis_rxwrite_sts_TVALID = s_axis_rxwrite_sts_TVALID;
assign s_axis_rxwrite_sts_TREADY = axis_rxwrite_sts_TREADY;
assign axis_rxwrite_sts_TDATA = s_axis_rxwrite_sts_TDATA;
// read
/*assign axis_rxbuffer2app_TVALID = s_axis_rxread_data_TVALID;
assign s_axis_rxread_data_TREADY = axis_rxbuffer2app_TREADY;
assign axis_rxbuffer2app_TDATA = s_axis_rxread_data_TDATA;
assign axis_rxbuffer2app_TKEEP = s_axis_rxread_data_TKEEP;
assign axis_rxbuffer2app_TLAST = s_axis_rxread_data_TLAST;
// write
assign m_axis_rxwrite_data_TVALID = axis_tcp2rxbuffer_TVALID;
assign axis_tcp2rxbuffer_TREADY = m_axis_rxwrite_data_TREADY;
assign m_axis_rxwrite_data_TDATA = axis_tcp2rxbuffer_TDATA;
assign m_axis_rxwrite_data_TKEEP = axis_tcp2rxbuffer_TKEEP;
assign m_axis_rxwrite_data_TLAST = axis_tcp2rxbuffer_TLAST;*/
// TX assignments
assign m_axis_txread_cmd_TVALID = axis_txread_cmd_TVALID;
assign axis_txread_cmd_TREADY = m_axis_txread_cmd_TREADY;
assign m_axis_txread_cmd_TDATA = axis_txread_cmd_TDATA;
assign m_axis_txwrite_cmd_TVALID = axis_txwrite_cmd_TVALID;
assign axis_txwrite_cmd_TREADY = m_axis_txwrite_cmd_TREADY;
assign m_axis_txwrite_cmd_TDATA = axis_txwrite_cmd_TDATA;
assign axis_txread_sts_TVALID = s_axis_txread_sts_TVALID;
assign s_axis_txread_sts_TREADY = axis_txread_sts_TREADY;
assign axis_txread_sts_TDATA = s_axis_txread_sts_TDATA;
assign axis_txwrite_sts_TVALID = s_axis_txwrite_sts_TVALID;
assign s_axis_txwrite_sts_TREADY = axis_txwrite_sts_TREADY;
assign axis_txwrite_sts_TDATA = s_axis_txwrite_sts_TDATA;
// read
assign axis_txbuffer2tcp_TVALID = s_axis_txread_data_TVALID;
assign s_axis_txread_data_TREADY = axis_txbuffer2tcp_TREADY;
assign axis_txbuffer2tcp_TDATA = s_axis_txread_data_TDATA;
assign axis_txbuffer2tcp_TKEEP = s_axis_txread_data_TKEEP;
assign axis_txbuffer2tcp_TLAST = s_axis_txread_data_TLAST;
// write
assign m_axis_txwrite_data_TVALID = axis_app2txbuffer_TVALID;
assign axis_app2txbuffer_TREADY = m_axis_txwrite_data_TREADY;
assign m_axis_txwrite_data_TDATA = axis_app2txbuffer_TDATA;
assign m_axis_txwrite_data_TKEEP = axis_app2txbuffer_TKEEP;
assign m_axis_txwrite_data_TLAST = axis_app2txbuffer_TLAST;
// because read status is not used
assign axis_rxread_sts_TREADY = 1'b1;
assign axis_txread_sts_TREADY = 1'b1;
// Register and distribute ip address
wire[31:0] dhcp_ip_address;
wire dhcp_ip_address_en;
reg[47:0] mie_mac_address;
reg[47:0] arp_mac_address;
reg[31:0] iph_ip_address;
reg[31:0] arp_ip_address;
reg[31:0] toe_ip_address;
reg[31:0] ip_subnet_mask;
reg[31:0] ip_default_gateway;
//assign dhcp_ip_address_en = 1'b1;
//assign dhcp_ip_address = 32'hD1D4010A;
always @(posedge aclk)
begin
if (aresetn == 0) begin
mie_mac_address <= 48'h000000000000;
arp_mac_address <= 48'h000000000000;
iph_ip_address <= 32'h00000000;
arp_ip_address <= 32'h00000000;
toe_ip_address <= 32'h00000000;
ip_subnet_mask <= 32'h00000000;
ip_default_gateway <= 32'h00000000;
end
else begin
mie_mac_address <= {MAC_ADDRESS[47:44], (MAC_ADDRESS[43:40]+board_number), MAC_ADDRESS[39:0]};
arp_mac_address <= {MAC_ADDRESS[47:44], (MAC_ADDRESS[43:40]+board_number), MAC_ADDRESS[39:0]};
if (DHCP_EN == 1) begin
if (dhcp_ip_address_en == 1'b1) begin
iph_ip_address <= dhcp_ip_address;
arp_ip_address <= dhcp_ip_address;
toe_ip_address <= dhcp_ip_address;
end
end
else begin
iph_ip_address <= {IP_ADDRESS[31:28], IP_ADDRESS[27:24]+board_number, IP_ADDRESS[23:4], IP_ADDRESS[3:0]+subnet_number};
arp_ip_address <= {IP_ADDRESS[31:28], IP_ADDRESS[27:24]+board_number, IP_ADDRESS[23:4], IP_ADDRESS[3:0]+subnet_number};
toe_ip_address <= {IP_ADDRESS[31:28], IP_ADDRESS[27:24]+board_number, IP_ADDRESS[23:4], IP_ADDRESS[3:0]+subnet_number};
ip_subnet_mask <= IP_SUBNET_MASK;
ip_default_gateway <= {IP_DEFAULT_GATEWAY[31:4], IP_DEFAULT_GATEWAY[3:0]+subnet_number};
end
end
end
// ip address output
assign ip_address_out = iph_ip_address;
wire [157:0] debug_out_tcp;
wire [7:0] aux;
// for shortcut_toe
assign axis_rxread_cmd_TVALID = 1'b0;
assign axis_rxwrite_cmd_TVALID = 1'b0;
assign axis_rxwrite_sts_TREADY = 1'b1;
/*assign axis_rxbuffer2app_TREADY = 1'b1;
assign axis_tcp2rxbuffer_TVALID = 1'b0;*/
wire[31:0] rx_buffer_data_count;
shortcut_toe_NODELAY_ip toe_inst (
// Data output
.m_axis_tcp_data_TVALID(axi_toe_to_toe_slice_tvalid), // output AXI_M_Stream_TVALID
.m_axis_tcp_data_TREADY(axi_toe_to_toe_slice_tready), // input AXI_M_Stream_TREADY
.m_axis_tcp_data_TDATA(axi_toe_to_toe_slice_tdata), // output [63 : 0] AXI_M_Stream_TDATA
.m_axis_tcp_data_TKEEP(axi_toe_to_toe_slice_tkeep), // output [7 : 0] AXI_M_Stream_TSTRB
.m_axis_tcp_data_TLAST(axi_toe_to_toe_slice_tlast), // output [0 : 0] AXI_M_Stream_TLAST
// Data input
.s_axis_tcp_data_TVALID(axi_toe_slice_to_toe_tvalid), // input AXI_S_Stream_TVALID
.s_axis_tcp_data_TREADY(axi_toe_slice_to_toe_tready), // output AXI_S_Stream_TREADY
.s_axis_tcp_data_TDATA(axi_toe_slice_to_toe_tdata), // input [63 : 0] AXI_S_Stream_TDATA
.s_axis_tcp_data_TKEEP(axi_toe_slice_to_toe_tkeep), // input [7 : 0] AXI_S_Stream_TKEEP
.s_axis_tcp_data_TLAST(axi_toe_slice_to_toe_tlast), // input [0 : 0] AXI_S_Stream_TLAST
// rx read commands
/*.m_axis_rxread_cmd_TVALID(axis_rxread_cmd_TVALID),
.m_axis_rxread_cmd_TREADY(axis_rxread_cmd_TREADY),
.m_axis_rxread_cmd_TDATA(axis_rxread_cmd_TDATA),
// rx write commands
.m_axis_rxwrite_cmd_TVALID(axis_rxwrite_cmd_TVALID),
.m_axis_rxwrite_cmd_TREADY(axis_rxwrite_cmd_TREADY),
.m_axis_rxwrite_cmd_TDATA(axis_rxwrite_cmd_TDATA),
// rx write status
.s_axis_rxwrite_sts_TVALID(axis_rxwrite_sts_TVALID),
.s_axis_rxwrite_sts_TREADY(axis_rxwrite_sts_TREADY),
.s_axis_rxwrite_sts_TDATA(axis_rxwrite_sts_TDATA),*/
// rx buffer read path
.s_axis_rxread_data_TVALID(axis_rxbuffer2app_TVALID),
.s_axis_rxread_data_TREADY(axis_rxbuffer2app_TREADY),
.s_axis_rxread_data_TDATA(axis_rxbuffer2app_TDATA),
.s_axis_rxread_data_TKEEP(axis_rxbuffer2app_TKEEP),
.s_axis_rxread_data_TLAST(axis_rxbuffer2app_TLAST),
// rx buffer write path
.m_axis_rxwrite_data_TVALID(axis_tcp2rxbuffer_TVALID),
.m_axis_rxwrite_data_TREADY(axis_tcp2rxbuffer_TREADY),
.m_axis_rxwrite_data_TDATA(axis_tcp2rxbuffer_TDATA),
.m_axis_rxwrite_data_TKEEP(axis_tcp2rxbuffer_TKEEP),
.m_axis_rxwrite_data_TLAST(axis_tcp2rxbuffer_TLAST),
// tx read commands
.m_axis_txread_cmd_TVALID(axis_txread_cmd_TVALID),
.m_axis_txread_cmd_TREADY(axis_txread_cmd_TREADY),
.m_axis_txread_cmd_TDATA(axis_txread_cmd_TDATA),
//tx write commands
.m_axis_txwrite_cmd_TVALID(axis_txwrite_cmd_TVALID),
.m_axis_txwrite_cmd_TREADY(axis_txwrite_cmd_TREADY),
.m_axis_txwrite_cmd_TDATA(axis_txwrite_cmd_TDATA),
// tx write status
.s_axis_txwrite_sts_TVALID(axis_txwrite_sts_TVALID),
.s_axis_txwrite_sts_TREADY(axis_txwrite_sts_TREADY),
.s_axis_txwrite_sts_TDATA(axis_txwrite_sts_TDATA),
// tx read path
.s_axis_txread_data_TVALID(axis_txbuffer2tcp_TVALID),
.s_axis_txread_data_TREADY(axis_txbuffer2tcp_TREADY),
.s_axis_txread_data_TDATA(axis_txbuffer2tcp_TDATA),
.s_axis_txread_data_TKEEP(axis_txbuffer2tcp_TKEEP),
.s_axis_txread_data_TLAST(axis_txbuffer2tcp_TLAST),
// tx write path
.m_axis_txwrite_data_TVALID(axis_app2txbuffer_TVALID),
.m_axis_txwrite_data_TREADY(axis_app2txbuffer_TREADY),
.m_axis_txwrite_data_TDATA(axis_app2txbuffer_TDATA),
.m_axis_txwrite_data_TKEEP(axis_app2txbuffer_TKEEP),
.m_axis_txwrite_data_TLAST(axis_app2txbuffer_TLAST),
/// SmartCAM I/F ///
.m_axis_session_upd_req_TVALID(upd_req_TVALID),
.m_axis_session_upd_req_TREADY(upd_req_TREADY),
.m_axis_session_upd_req_TDATA(upd_req_TDATA),
.s_axis_session_upd_rsp_TVALID(upd_rsp_TVALID),
.s_axis_session_upd_rsp_TREADY(upd_rsp_TREADY),
.s_axis_session_upd_rsp_TDATA(upd_rsp_TDATA),
.m_axis_session_lup_req_TVALID(lup_req_TVALID),
.m_axis_session_lup_req_TREADY(lup_req_TREADY),
.m_axis_session_lup_req_TDATA(lup_req_TDATA),
.s_axis_session_lup_rsp_TVALID(lup_rsp_TVALID),
.s_axis_session_lup_rsp_TREADY(lup_rsp_TREADY),
.s_axis_session_lup_rsp_TDATA(lup_rsp_TDATA),
/* Application Interface */
// listen&close port
.s_axis_listen_port_req_TVALID(s_axis_listen_port_TVALID),
.s_axis_listen_port_req_TREADY(s_axis_listen_port_TREADY),
.s_axis_listen_port_req_TDATA(s_axis_listen_port_TDATA),
.m_axis_listen_port_rsp_TVALID(m_axis_listen_port_status_TVALID),
.m_axis_listen_port_rsp_TREADY(m_axis_listen_port_status_TREADY),
.m_axis_listen_port_rsp_TDATA(m_axis_listen_port_status_TDATA),
// notification & read request
.m_axis_notification_TVALID(m_axis_notifications_TVALID),
.m_axis_notification_TREADY(m_axis_notifications_TREADY),
.m_axis_notification_TDATA(m_axis_notifications_TDATA),
.s_axis_rx_data_req_TVALID(s_axis_read_package_TVALID),
.s_axis_rx_data_req_TREADY(s_axis_read_package_TREADY),
.s_axis_rx_data_req_TDATA(s_axis_read_package_TDATA),
// open&close connection
.s_axis_open_conn_req_TVALID(s_axis_open_connection_TVALID),
.s_axis_open_conn_req_TREADY(s_axis_open_connection_TREADY),
.s_axis_open_conn_req_TDATA(s_axis_open_connection_TDATA),
.m_axis_open_conn_rsp_TVALID(m_axis_open_status_TVALID),
.m_axis_open_conn_rsp_TREADY(m_axis_open_status_TREADY),
.m_axis_open_conn_rsp_TDATA(m_axis_open_status_TDATA),
.s_axis_close_conn_req_TVALID(s_axis_close_connection_TVALID),//axis_close_connection_TVALID
.s_axis_close_conn_req_TREADY(s_axis_close_connection_TREADY),
.s_axis_close_conn_req_TDATA(s_axis_close_connection_TDATA),
// rx data
.m_axis_rx_data_rsp_metadata_TVALID(m_axis_rx_metadata_TVALID),
.m_axis_rx_data_rsp_metadata_TREADY(m_axis_rx_metadata_TREADY),
.m_axis_rx_data_rsp_metadata_TDATA(m_axis_rx_metadata_TDATA),
.m_axis_rx_data_rsp_TVALID(m_axis_rx_data_TVALID),
.m_axis_rx_data_rsp_TREADY(m_axis_rx_data_TREADY),
.m_axis_rx_data_rsp_TDATA(m_axis_rx_data_TDATA),
.m_axis_rx_data_rsp_TKEEP(m_axis_rx_data_TKEEP),
.m_axis_rx_data_rsp_TLAST(m_axis_rx_data_TLAST),
// tx data
.s_axis_tx_data_req_metadata_TVALID(s_axis_tx_metadata_TVALID),
.s_axis_tx_data_req_metadata_TREADY(s_axis_tx_metadata_TREADY),
.s_axis_tx_data_req_metadata_TDATA(s_axis_tx_metadata_TDATA),
.s_axis_tx_data_req_TVALID(s_axis_tx_data_TVALID),
.s_axis_tx_data_req_TREADY(s_axis_tx_data_TREADY),
.s_axis_tx_data_req_TDATA(s_axis_tx_data_TDATA),
.s_axis_tx_data_req_TKEEP(s_axis_tx_data_TKEEP),
.s_axis_tx_data_req_TLAST(s_axis_tx_data_TLAST),
.m_axis_tx_data_rsp_TVALID(m_axis_tx_status_TVALID),
.m_axis_tx_data_rsp_TREADY(m_axis_tx_status_TREADY),
.m_axis_tx_data_rsp_TDATA(m_axis_tx_status_TDATA[63:0]),
.regIpAddress_V(toe_ip_address),
.regSessionCount_V(regSessionCount_V),
.regSessionCount_V_ap_vld(regSessionCount_V_ap_vld),
//for external RX Buffer
.axis_data_count_V(rx_buffer_data_count),
.axis_max_data_count_V(32'd2048),
//.debug_out(debug_out_tcp[157:0]),
.aclk(aclk), // input aclk
.aresetn(aresetn) // input aresetn
);
assign debug_out = {debug_out_tcp[137:0], debug_out_ips[19:0]};
//assign m_axis_tx_status_TDATA[7:0] = debug_out;
//RX BUFFER FIFO
fifo_generator_0 rx_buffer_fifo (
.s_aresetn(aresetn), // input wire s_axis_aresetn
.s_aclk(aclk), // input wire s_axis_aclk
.s_axis_tvalid(axis_tcp2rxbuffer_TVALID), // inp wire s_axis_tvalid
.s_axis_tready(axis_tcp2rxbuffer_TREADY), // output wire s_axis_tready
.s_axis_tdata(axis_tcp2rxbuffer_TDATA), // input wire [63 : 0] s_axis_tdata
.s_axis_tkeep(axis_tcp2rxbuffer_TKEEP), // input wire [7 : 0] s_axis_tkeep
.s_axis_tlast(axis_tcp2rxbuffer_TLAST), // input wire s_axis_tlast
.m_axis_tvalid(axis_rxbuffer2app_TVALID), // output wire m_axis_tvalid
.m_axis_tready(axis_rxbuffer2app_TREADY), // input wire m_axis_tready
.m_axis_tdata(axis_rxbuffer2app_TDATA), // output wire [63 : 0] m_axis_tdata
.m_axis_tkeep(axis_rxbuffer2app_TKEEP), // output wire [7 : 0] m_axis_tkeep
.m_axis_tlast(axis_rxbuffer2app_TLAST), // output wire m_axis_tlast
.axis_data_count(rx_buffer_data_count[11:0])
);
assign rx_buffer_data_count[31:12] = 20'h0;
SmartCamCtl SmartCamCtl_inst
(
.clk(aclk),
.rst(~aresetn),
.led0(sc_led0),
.led1(sc_led1),
.cam_ready(cam_ready),
.lup_req_valid(lup_req_TVALID),
.lup_req_ready(lup_req_TREADY),
.lup_req_din(lup_req_TDATA),
.lup_rsp_valid(lup_rsp_TVALID),
.lup_rsp_ready(lup_rsp_TREADY),
.lup_rsp_dout(lup_rsp_TDATA),
.upd_req_valid(upd_req_TVALID),
.upd_req_ready(upd_req_TREADY),
.upd_req_din(upd_req_TDATA),
.upd_rsp_valid(upd_rsp_TVALID),
.upd_rsp_ready(upd_rsp_TREADY),
.upd_rsp_dout(upd_rsp_TDATA),
.debug(sc_debug)
);
// DHCP port
wire axis_dhcp_open_port_tvalid;
wire axis_dhcp_open_port_tready;
wire[15:0] axis_dhcp_open_port_tdata;
wire axis_dhcp_open_port_status_tvalid;
wire axis_dhcp_open_port_status_tready;
wire[7:0] axis_dhcp_open_port_status_tdata; //actually only [0:0]
// DHCP RX
wire axis_dhcp_rx_data_tvalid;
wire axis_dhcp_rx_data_tready;
wire[63:0] axis_dhcp_rx_data_tdata;
wire[7:0] axis_dhcp_rx_data_tkeep;
wire axis_dhcp_rx_data_tlast;
wire axis_dhcp_rx_metadata_tvalid;
wire axis_dhcp_rx_metadata_tready;
wire[95:0] axis_dhcp_rx_metadata_tdata;
// DHCP TX
wire axis_dhcp_tx_data_tvalid;
wire axis_dhcp_tx_data_tready;
wire[63:0] axis_dhcp_tx_data_tdata;
wire[7:0] axis_dhcp_tx_data_tkeep;
wire axis_dhcp_tx_data_tlast;
wire axis_dhcp_tx_metadata_tvalid;
wire axis_dhcp_tx_metadata_tready;
wire[95:0] axis_dhcp_tx_metadata_tdata;
wire axis_dhcp_tx_length_tvalid;
wire axis_dhcp_tx_length_tready;
wire[15:0] axis_dhcp_tx_length_tdata;
assign axi_udp_slice_to_udp_tready = 1'b1;
assign axi_udp_to_merge_tvalid = 1'b0;
assign axi_udp_to_merge_tdata = 0;
assign axi_udp_to_merge_tkeep = 0;
assign axi_udp_to_merge_tlast = 0;
// UDP Engine
/*udp_ip udp_inst (
.inputPathInData_TVALID(axi_udp_slice_to_udp_tvalid), // input wire inputPathInData_TVALID
.inputPathInData_TREADY(axi_udp_slice_to_udp_tready), // output wire inputPathInData_TREADY
.inputPathInData_TDATA(axi_udp_slice_to_udp_tdata), // input wire [63 : 0] inputPathInData_TDATA
.inputPathInData_TKEEP(axi_udp_slice_to_udp_tkeep), // input wire [7 : 0] inputPathInData_TKEEP
.inputPathInData_TLAST(axi_udp_slice_to_udp_tlast), // input wire [0 : 0] inputPathInData_TLAST
.inputpathOutData_TVALID(axis_dhcp_rx_data_tvalid), // output wire inputpathOutData_V_TVALID
.inputpathOutData_TREADY(axis_dhcp_rx_data_tready), // input wire inputpathOutData_V_TREADY
.inputpathOutData_TDATA(axis_dhcp_rx_data_tdata), // output wire [71 : 0] inputpathOutData_V_TDATA
.inputpathOutData_TKEEP(axis_dhcp_rx_data_tkeep), // output wire [7:0]
.inputpathOutData_TLAST(axis_dhcp_rx_data_tlast), // output wire
.openPort_TVALID(axis_dhcp_open_port_tvalid), // input wire openPort_V_TVALID
.openPort_TREADY(axis_dhcp_open_port_tready), // output wire openPort_V_TREADY
.openPort_TDATA(axis_dhcp_open_port_tdata), // input wire [7 : 0] openPort_V_TDATA
.confirmPortStatus_TVALID(axis_dhcp_open_port_status_tvalid), // output wire confirmPortStatus_V_V_TVALID
.confirmPortStatus_TREADY(axis_dhcp_open_port_status_tready), // input wire confirmPortStatus_V_V_TREADY
.confirmPortStatus_TDATA(axis_dhcp_open_port_status_tdata), // output wire [15 : 0] confirmPortStatus_V_V_TDATA
.inputPathOutputMetadata_TVALID(axis_dhcp_rx_metadata_tvalid), // output wire inputPathOutputMetadata_V_TVALID
.inputPathOutputMetadata_TREADY(axis_dhcp_rx_metadata_tready), // input wire inputPathOutputMetadata_V_TREADY
.inputPathOutputMetadata_TDATA(axis_dhcp_rx_metadata_tdata), // output wire [95 : 0] inputPathOutputMetadata_V_TDATA
.portRelease_TVALID(1'b0), // input wire portRelease_V_V_TVALID
.portRelease_TREADY(), // output wire portRelease_V_V_TREADY
.portRelease_TDATA(15'b0), // input wire [15 : 0] portRelease_V_V_TDATA
.outputPathInData_TVALID(axis_dhcp_tx_data_tvalid), // input wire outputPathInData_V_TVALID
.outputPathInData_TREADY(axis_dhcp_tx_data_tready), // output wire outputPathInData_V_TREADY
.outputPathInData_TDATA(axis_dhcp_tx_data_tdata), // input wire [71 : 0] outputPathInData_V_TDATA
.outputPathInData_TKEEP(axis_dhcp_tx_data_tkeep), // input wire [7 : 0] outputPathInData_TKEEP
.outputPathInData_TLAST(axis_dhcp_tx_data_tlast), // input wire [0 : 0] outputPathInData_TLAST
.outputPathOutData_TVALID(axi_udp_to_merge_tvalid), // output wire outputPathOutData_TVALID
.outputPathOutData_TREADY(axi_udp_to_merge_tready), // input wire outputPathOutData_TREADY
.outputPathOutData_TDATA(axi_udp_to_merge_tdata), // output wire [63 : 0] outputPathOutData_TDATA
.outputPathOutData_TKEEP(axi_udp_to_merge_tkeep), // output wire [7 : 0] outputPathOutData_TKEEP
.outputPathOutData_TLAST(axi_udp_to_merge_tlast), // output wire [0 : 0] outputPathOutData_TLAST
.outputPathInMetadata_TVALID(axis_dhcp_tx_metadata_tvalid), // input wire outputPathInMetadata_V_TVALID
.outputPathInMetadata_TREADY(axis_dhcp_tx_metadata_tready), // output wire outputPathInMetadata_V_TREADY
.outputPathInMetadata_TDATA(axis_dhcp_tx_metadata_tdata), // input wire [95 : 0] outputPathInMetadata_V_TDATA
.outputpathInLength_TVALID(axis_dhcp_tx_length_tvalid), // input wire outputpathInLength_V_V_TVALID
.outputpathInLength_TREADY(axis_dhcp_tx_length_tready), // output wire outputpathInLength_V_V_TREADY
.outputpathInLength_TDATA(axis_dhcp_tx_length_tdata), // input wire [15 : 0] outputpathInLength_V_V_TDATA
.inputPathPortUnreachable_TVALID(), // output wire inputPathPortUnreachable_TVALID
.inputPathPortUnreachable_TREADY(1'b1), // input wire inputPathPortUnreachable_TREADY
.inputPathPortUnreachable_TDATA(), // output wire [63 : 0] inputPathPortUnreachable_TDATA
.inputPathPortUnreachable_TKEEP(), // output wire [7 : 0] inputPathPortUnreachable_TKEEP
.inputPathPortUnreachable_TLAST(), // output wire [0 : 0] inputPathPortUnreachable_TLAST
.aclk(aclk), // input wire ap_clk
.aresetn(aresetn) // input wire ap_rst_n
);
dhcp_client_ip dhcp_client_inst (
.m_axis_open_port_TVALID(axis_dhcp_open_port_tvalid), // output wire m_axis_open_port_TVALID
.m_axis_open_port_TREADY(axis_dhcp_open_port_tready), // input wire m_axis_open_port_TREADY
.m_axis_open_port_TDATA(axis_dhcp_open_port_tdata), // output wire [15 : 0] m_axis_open_port_TDATA
.m_axis_tx_data_TVALID(axis_dhcp_tx_data_tvalid), // output wire m_axis_tx_data_TVALID
.m_axis_tx_data_TREADY(axis_dhcp_tx_data_tready), // input wire m_axis_tx_data_TREADY
.m_axis_tx_data_TDATA(axis_dhcp_tx_data_tdata), // output wire [63 : 0] m_axis_tx_data_TDATA
.m_axis_tx_data_TKEEP(axis_dhcp_tx_data_tkeep), // output wire [7 : 0] m_axis_tx_data_TKEEP
.m_axis_tx_data_TLAST(axis_dhcp_tx_data_tlast), // output wire [0 : 0] m_axis_tx_data_TLAST
.m_axis_tx_length_TVALID(axis_dhcp_tx_length_tvalid), // output wire m_axis_tx_length_TVALID
.m_axis_tx_length_TREADY(axis_dhcp_tx_length_tready), // input wire m_axis_tx_length_TREADY
.m_axis_tx_length_TDATA(axis_dhcp_tx_length_tdata), // output wire [15 : 0] m_axis_tx_length_TDATA
.m_axis_tx_metadata_TVALID(axis_dhcp_tx_metadata_tvalid), // output wire m_axis_tx_metadata_TVALID
.m_axis_tx_metadata_TREADY(axis_dhcp_tx_metadata_tready), // input wire m_axis_tx_metadata_TREADY
.m_axis_tx_metadata_TDATA(axis_dhcp_tx_metadata_tdata), // output wire [95 : 0] m_axis_tx_metadata_TDATA
.s_axis_open_port_status_TVALID(axis_dhcp_open_port_status_tvalid), // input wire s_axis_open_port_status_TVALID
.s_axis_open_port_status_TREADY(axis_dhcp_open_port_status_tready), // output wire s_axis_open_port_status_TREADY
.s_axis_open_port_status_TDATA(axis_dhcp_open_port_status_tdata), // input wire [7 : 0] s_axis_open_port_status_TDATA
.s_axis_rx_data_TVALID(axis_dhcp_rx_data_tvalid), // input wire s_axis_rx_data_TVALID
.s_axis_rx_data_TREADY(axis_dhcp_rx_data_tready), // output wire s_axis_rx_data_TREADY
.s_axis_rx_data_TDATA(axis_dhcp_rx_data_tdata), // input wire [63 : 0] s_axis_rx_data_TDATA
.s_axis_rx_data_TKEEP(axis_dhcp_rx_data_tkeep), // input wire [7 : 0] s_axis_rx_data_TKEEP
.s_axis_rx_data_TLAST(axis_dhcp_rx_data_tlast), // input wire [0 : 0] s_axis_rx_data_TLAST
.s_axis_rx_metadata_TVALID(axis_dhcp_rx_metadata_tvalid), // input wire s_axis_rx_metadata_TVALID
.s_axis_rx_metadata_TREADY(axis_dhcp_rx_metadata_tready), // output wire s_axis_rx_metadata_TREADY
.s_axis_rx_metadata_TDATA(axis_dhcp_rx_metadata_tdata), // input wire [95 : 0] s_axis_rx_metadata_TDATA
.dhcpIpAddressOut_V(dhcp_ip_address), // output wire [31 : 0] dhcpIpAddressOut_V
.dhcpIpAddressOut_V_ap_vld(dhcp_ip_address_en),
.aclk(aclk), // input wire aclk
.aresetn(aresetn) // input wire aresetn
);*/
ip_handler_ip ip_handler_inst (
.m_axis_ARP_TVALID(axi_iph_to_arp_slice_tvalid), // output AXI4Stream_M_TVALID
.m_axis_ARP_TREADY(axi_iph_to_arp_slice_tready), // input AXI4Stream_M_TREADY
.m_axis_ARP_TDATA(axi_iph_to_arp_slice_tdata), // output [63 : 0] AXI4Stream_M_TDATA
.m_axis_ARP_TKEEP(axi_iph_to_arp_slice_tkeep), // output [7 : 0] AXI4Stream_M_TSTRB
.m_axis_ARP_TLAST(axi_iph_to_arp_slice_tlast), // output [0 : 0] AXI4Stream_M_TLAST
.m_axis_ICMP_TVALID(axi_iph_to_icmp_slice_tvalid), // output AXI4Stream_M_TVALID
.m_axis_ICMP_TREADY(axi_iph_to_icmp_slice_tready), // input AXI4Stream_M_TREADY
.m_axis_ICMP_TDATA(axi_iph_to_icmp_slice_tdata), // output [63 : 0] AXI4Stream_M_TDATA
.m_axis_ICMP_TKEEP(axi_iph_to_icmp_slice_tkeep), // output [7 : 0] AXI4Stream_M_TSTRB
.m_axis_ICMP_TLAST(axi_iph_to_icmp_slice_tlast), // output [0 : 0] AXI4Stream_M_TLAST
.m_axis_UDP_TVALID(axi_iph_to_udp_slice_tvalid), // output AXI4Stream_M_TVALID
.m_axis_UDP_TREADY(axi_iph_to_udp_slice_tready), // input AXI4Stream_M_TREADY
.m_axis_UDP_TDATA(axi_iph_to_udp_slice_tdata), // output [63 : 0] AXI4Stream_M_TDATA
.m_axis_UDP_TKEEP(axi_iph_to_udp_slice_tkeep), // output [7 : 0] AXI4Stream_M_TSTRB
.m_axis_UDP_TLAST(axi_iph_to_udp_slice_tlast), // output [0 : 0]
.m_axis_TCP_TVALID(axi_iph_to_toe_slice_tvalid), // output AXI4Stream_M_TVALID
.m_axis_TCP_TREADY(axi_iph_to_toe_slice_tready), // input AXI4Stream_M_TREADY
.m_axis_TCP_TDATA(axi_iph_to_toe_slice_tdata), // output [63 : 0] AXI4Stream_M_TDATA
.m_axis_TCP_TKEEP(axi_iph_to_toe_slice_tkeep), // output [7 : 0] AXI4Stream_M_TSTRB
.m_axis_TCP_TLAST(axi_iph_to_toe_slice_tlast), // output [0 : 0] AXI4Stream_M_TLAST
.s_axis_raw_TVALID(AXI_S_Stream_TVALID), // input AXI4Stream_S_TVALID
.s_axis_raw_TREADY(AXI_S_Stream_TREADY), // output AXI4Stream_S_TREADY
.s_axis_raw_TDATA(AXI_S_Stream_TDATA), // input [63 : 0] AXI4Stream_S_TDATA
.s_axis_raw_TKEEP(AXI_S_Stream_TKEEP), // input [7 : 0] AXI4Stream_S_TSTRB
.s_axis_raw_TLAST(AXI_S_Stream_TLAST), // input [0 : 0] AXI4Stream_S_TLAST
.regIpAddress_V(iph_ip_address),
.aclk(aclk), // input aclk
.aresetn(aresetn) // input aresetn
);
assign debug_out_ips[0] = axi_iph_to_arp_slice_tvalid;
assign debug_out_ips[1] = axi_iph_to_arp_slice_tready;
assign debug_out_ips[2] = axi_iph_to_arp_slice_tlast;
assign debug_out_ips[3] = axi_iph_to_icmp_slice_tvalid;
assign debug_out_ips[4] = axi_iph_to_icmp_slice_tready;
assign debug_out_ips[5] = axi_iph_to_icmp_slice_tlast;
assign debug_out_ips[6] = axi_iph_to_toe_slice_tvalid;
assign debug_out_ips[7] = axi_iph_to_toe_slice_tready;
assign debug_out_ips[8] = axi_iph_to_toe_slice_tlast;
assign debug_out_ips[9] = AXI_S_Stream_TVALID;
assign debug_out_ips[10] = AXI_S_Stream_TREADY;
assign debug_out_ips[11] = AXI_S_Stream_TLAST;
// ARP lookup
wire axis_arp_lookup_request_TVALID;
wire axis_arp_lookup_request_TREADY;
wire[31:0] axis_arp_lookup_request_TDATA;
wire axis_arp_lookup_reply_TVALID;
wire axis_arp_lookup_reply_TREADY;
wire[55:0] axis_arp_lookup_reply_TDATA;
mac_ip_encode_ip mac_ip_encode_inst (
.m_axis_ip_TVALID(axi_mie_to_intercon_tvalid),
.m_axis_ip_TREADY(axi_mie_to_intercon_tready),
.m_axis_ip_TDATA(axi_mie_to_intercon_tdata),
.m_axis_ip_TKEEP(axi_mie_to_intercon_tkeep),
.m_axis_ip_TLAST(axi_mie_to_intercon_tlast),
.m_axis_arp_lookup_request_TVALID(axis_arp_lookup_request_TVALID),
.m_axis_arp_lookup_request_TREADY(axis_arp_lookup_request_TREADY),
.m_axis_arp_lookup_request_TDATA(axis_arp_lookup_request_TDATA),
.s_axis_ip_TVALID(axi_intercon_to_mie_tvalid),
.s_axis_ip_TREADY(axi_intercon_to_mie_tready),
.s_axis_ip_TDATA(axi_intercon_to_mie_tdata),
.s_axis_ip_TKEEP(axi_intercon_to_mie_tkeep),
.s_axis_ip_TLAST(axi_intercon_to_mie_tlast),
.s_axis_arp_lookup_reply_TVALID(axis_arp_lookup_reply_TVALID),
.s_axis_arp_lookup_reply_TREADY(axis_arp_lookup_reply_TREADY),
.s_axis_arp_lookup_reply_TDATA(axis_arp_lookup_reply_TDATA),
.myMacAddress_V(mie_mac_address), // input wire [47 : 0] regMacAddress_V
.regSubNetMask_V(ip_subnet_mask), // input wire [31 : 0] regSubNetMask_V
.regDefaultGateway_V(ip_default_gateway), // input wire [31 : 0] regDefaultGateway_V
.aclk(aclk), // input aclk
.aresetn(aresetn) // input aresetn
);
// merges icmp, udp and tcp
axis_interconnect_3to1 ip_merger (
.ACLK(aclk), // input ACLK
.ARESETN(aresetn), // input ARESETN
// ICMP
.S00_AXIS_ACLK(aclk), // input S00_AXIS_ACLK
.S00_AXIS_ARESETN(aresetn), // input S00_AXIS_ARESETN
.S00_AXIS_TVALID(axi_icmp_to_icmp_slice_tvalid), // input S00_AXIS_TVALID
.S00_AXIS_TREADY(axi_icmp_to_icmp_slice_tready), // output S00_AXIS_TREADY
.S00_AXIS_TDATA(axi_icmp_to_icmp_slice_tdata), // input [63 : 0] S00_AXIS_TDATA
.S00_AXIS_TKEEP(axi_icmp_to_icmp_slice_tkeep), // input [7 : 0] S00_AXIS_TKEEP
.S00_AXIS_TLAST(axi_icmp_to_icmp_slice_tlast), // input S00_AXIS_TLAST
//UDP
.S01_AXIS_ACLK(aclk), // input S01_AXIS_ACLK
.S01_AXIS_ARESETN(aresetn), // input S01_AXIS_ARESETN
.S01_AXIS_TVALID(axi_udp_to_merge_tvalid), // input S01_AXIS_TVALID
.S01_AXIS_TREADY(axi_udp_to_merge_tready), // output S01_AXIS_TREADY
.S01_AXIS_TDATA(axi_udp_to_merge_tdata), // input [63 : 0] S01_AXIS_TDATA
.S01_AXIS_TKEEP(axi_udp_to_merge_tkeep), // input [7 : 0] S01_AXIS_TKEEP
.S01_AXIS_TLAST(axi_udp_to_merge_tlast), // input S01_AXIS_TLAST
//TCP
.S02_AXIS_ACLK(aclk), // input S01_AXIS_ACLK
.S02_AXIS_ARESETN(aresetn), // input S01_AXIS_ARESETN
.S02_AXIS_TVALID(axi_toe_to_toe_slice_tvalid), // input S01_AXIS_TVALID
.S02_AXIS_TREADY(axi_toe_to_toe_slice_tready), // output S01_AXIS_TREADY
.S02_AXIS_TDATA(axi_toe_to_toe_slice_tdata), // input [63 : 0] S01_AXIS_TDATA
.S02_AXIS_TKEEP(axi_toe_to_toe_slice_tkeep), // input [7 : 0] S01_AXIS_TKEEP
.S02_AXIS_TLAST(axi_toe_to_toe_slice_tlast), // input S01_AXIS_TLAST
.M00_AXIS_ACLK(aclk), // input M00_AXIS_ACLK
.M00_AXIS_ARESETN(aresetn), // input M00_AXIS_ARESETN
.M00_AXIS_TVALID(axi_intercon_to_mie_tvalid), // output M00_AXIS_TVALID
.M00_AXIS_TREADY(axi_intercon_to_mie_tready), // input M00_AXIS_TREADY
.M00_AXIS_TDATA(axi_intercon_to_mie_tdata), // output [63 : 0] M00_AXIS_TDATA
.M00_AXIS_TKEEP(axi_intercon_to_mie_tkeep), // output [7 : 0] M00_AXIS_TKEEP
.M00_AXIS_TLAST(axi_intercon_to_mie_tlast), // output M00_AXIS_TLAST
.S00_ARB_REQ_SUPPRESS(1'b0), // input S00_ARB_REQ_SUPPRESS
.S01_ARB_REQ_SUPPRESS(1'b0), // input S01_ARB_REQ_SUPPRESS
.S02_ARB_REQ_SUPPRESS(1'b0) // input S02_ARB_REQ_SUPPRESS
);
// merges ip and arp
axis_interconnect_2to1 mac_merger (
.ACLK(aclk), // input ACLK
.ARESETN(aresetn), // input ARESETN
.S00_AXIS_ACLK(aclk), // input S00_AXIS_ACLK
.S01_AXIS_ACLK(aclk), // input S01_AXIS_ACLK
.S00_AXIS_ARESETN(aresetn), // input S00_AXIS_ARESETN
.S01_AXIS_ARESETN(aresetn), // input S01_AXIS_ARESETN
.S00_AXIS_TVALID(axi_arp_to_arp_slice_tvalid), // input S00_AXIS_TVALID
.S01_AXIS_TVALID(axi_mie_to_intercon_tvalid), // input S01_AXIS_TVALID
.S00_AXIS_TREADY(axi_arp_to_arp_slice_tready), // output S00_AXIS_TREADY
.S01_AXIS_TREADY(axi_mie_to_intercon_tready), // output S01_AXIS_TREADY
.S00_AXIS_TDATA(axi_arp_to_arp_slice_tdata), // input [63 : 0] S00_AXIS_TDATA
.S01_AXIS_TDATA(axi_mie_to_intercon_tdata), // input [63 : 0] S01_AXIS_TDATA
.S00_AXIS_TKEEP(axi_arp_to_arp_slice_tkeep), // input [7 : 0] S00_AXIS_TKEEP
.S01_AXIS_TKEEP(axi_mie_to_intercon_tkeep), // input [7 : 0] S01_AXIS_TKEEP
.S00_AXIS_TLAST(axi_arp_to_arp_slice_tlast), // input S00_AXIS_TLAST
.S01_AXIS_TLAST(axi_mie_to_intercon_tlast), // input S01_AXIS_TLAST
.M00_AXIS_ACLK(aclk), // input M00_AXIS_ACLK
.M00_AXIS_ARESETN(aresetn), // input M00_AXIS_ARESETN
.M00_AXIS_TVALID(AXI_M_Stream_TVALID), // output M00_AXIS_TVALID
.M00_AXIS_TREADY(AXI_M_Stream_TREADY), // input M00_AXIS_TREADY
.M00_AXIS_TDATA(AXI_M_Stream_TDATA), // output [63 : 0] M00_AXIS_TDATA
.M00_AXIS_TKEEP(AXI_M_Stream_TKEEP), // output [7 : 0] M00_AXIS_TKEEP
.M00_AXIS_TLAST(AXI_M_Stream_TLAST), // output M00_AXIS_TLAST
.S00_ARB_REQ_SUPPRESS(1'b0), // input S00_ARB_REQ_SUPPRESS
.S01_ARB_REQ_SUPPRESS(1'b0) // input S01_ARB_REQ_SUPPRESS
);
assign debug_out_ips[12] = axi_arp_to_arp_slice_tvalid;
assign debug_out_ips[13] = axi_arp_to_arp_slice_tready;
assign debug_out_ips[14] = axi_mie_to_intercon_tvalid;
assign debug_out_ips[15] = axi_mie_to_intercon_tready;
assign debug_out_ips[16] = AXI_M_Stream_TVALID;
assign debug_out_ips[17] = AXI_M_Stream_TREADY;
assign debug_out_ips[18] = AXI_M_Stream_TLAST;
// ARP Server
/*arpServerWrapper arpServerInst (
.axi_arp_to_arp_slice_tvalid(axi_arp_to_arp_slice_tvalid),
.axi_arp_to_arp_slice_tready(axi_arp_to_arp_slice_tready),
.axi_arp_to_arp_slice_tdata(axi_arp_to_arp_slice_tdata),
.axi_arp_to_arp_slice_tkeep(axi_arp_to_arp_slice_tkeep),
.axi_arp_to_arp_slice_tlast(axi_arp_to_arp_slice_tlast),
.axis_arp_lookup_reply_TVALID(axis_arp_lookup_reply_TVALID),
.axis_arp_lookup_reply_TREADY(axis_arp_lookup_reply_TREADY),
.axis_arp_lookup_reply_TDATA(axis_arp_lookup_reply_TDATA),
.axi_arp_slice_to_arp_tvalid(axi_arp_slice_to_arp_tvalid),
.axi_arp_slice_to_arp_tready(axi_arp_slice_to_arp_tready),
.axi_arp_slice_to_arp_tdata(axi_arp_slice_to_arp_tdata),
.axi_arp_slice_to_arp_tkeep(axi_arp_slice_to_arp_tkeep),
.axi_arp_slice_to_arp_tlast(axi_arp_slice_to_arp_tlast),
.axis_arp_lookup_request_TVALID(axis_arp_lookup_request_TVALID),
.axis_arp_lookup_request_TREADY(axis_arp_lookup_request_TREADY),
.axis_arp_lookup_request_TDATA(axis_arp_lookup_request_TDATA),
//.ip_address(arp_ip_address),
.aclk(aclk), // input aclk
.aresetn(aresetn)); // input aresetn*/
arp_server_subnet_ip arp_server_inst(
.m_axis_TVALID(axi_arp_to_arp_slice_tvalid),
.m_axis_TREADY(axi_arp_to_arp_slice_tready),
.m_axis_TDATA(axi_arp_to_arp_slice_tdata),
.m_axis_TKEEP(axi_arp_to_arp_slice_tkeep),
.m_axis_TLAST(axi_arp_to_arp_slice_tlast),
.m_axis_arp_lookup_reply_TVALID(axis_arp_lookup_reply_TVALID),
.m_axis_arp_lookup_reply_TREADY(axis_arp_lookup_reply_TREADY),
.m_axis_arp_lookup_reply_TDATA(axis_arp_lookup_reply_TDATA),
.s_axis_TVALID(axi_arp_slice_to_arp_tvalid),
.s_axis_TREADY(axi_arp_slice_to_arp_tready),
.s_axis_TDATA(axi_arp_slice_to_arp_tdata),
.s_axis_TKEEP(axi_arp_slice_to_arp_tkeep),
.s_axis_TLAST(axi_arp_slice_to_arp_tlast),
.s_axis_arp_lookup_request_TVALID(axis_arp_lookup_request_TVALID),
.s_axis_arp_lookup_request_TREADY(axis_arp_lookup_request_TREADY),
.s_axis_arp_lookup_request_TDATA(axis_arp_lookup_request_TDATA),
.regMacAddress_V(arp_mac_address),
.regIpAddress_V(arp_ip_address),
.aclk(aclk), // input aclk
.aresetn(aresetn) // input aresetn
);
icmp_server_ip icmp_server_inst (
.m_axis_TVALID(axi_icmp_to_icmp_slice_tvalid),
.m_axis_TREADY(axi_icmp_to_icmp_slice_tready),
.m_axis_TDATA(axi_icmp_to_icmp_slice_tdata),
.m_axis_TKEEP(axi_icmp_to_icmp_slice_tkeep),
.m_axis_TLAST(axi_icmp_to_icmp_slice_tlast),
.s_axis_TVALID(axi_icmp_slice_to_icmp_tvalid),
.s_axis_TREADY(axi_icmp_slice_to_icmp_tready),
.s_axis_TDATA(axi_icmp_slice_to_icmp_tdata),
.s_axis_TKEEP(axi_icmp_slice_to_icmp_tkeep),
.s_axis_TLAST(axi_icmp_slice_to_icmp_tlast),
.ttlIn_TVALID(1'b0), // input wire ttlIn_TVALID
.ttlIn_TREADY(), // output wire ttlIn_TREADY
.ttlIn_TDATA(64'h0000000000000000), // input wire [63 : 0] ttlIn_TDATA
.ttlIn_TKEEP(8'h00), // input wire [7 : 0] ttlIn_TKEEP
.ttlIn_TLAST(1'b0), // input wire [0 : 0] ttlIn_TLAST
.udpIn_TVALID(1'b0), // input wire udpIn_TVALID
.udpIn_TREADY(), // output wire udpIn_TREADY
.udpIn_TDATA(64'h0000000000000000), // input wire [63 : 0] udpIn_TDATA
.udpIn_TKEEP(8'h00), // input wire [7 : 0] udpIn_TKEEP
.udpIn_TLAST(1'b0), // input wire [0 : 0] udpIn_TLAST
.aclk(aclk), // input aclk
.aresetn(aresetn) // input aresetn
);
/*
* Slices
*/
// ARP Input Slice
axis_register_slice_64 axis_register_arp_in_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_iph_to_arp_slice_tvalid),
.s_axis_tready(axi_iph_to_arp_slice_tready),
.s_axis_tdata(axi_iph_to_arp_slice_tdata),
.s_axis_tkeep(axi_iph_to_arp_slice_tkeep),
.s_axis_tlast(axi_iph_to_arp_slice_tlast),
.m_axis_tvalid(axi_arp_slice_to_arp_tvalid),
.m_axis_tready(axi_arp_slice_to_arp_tready),
.m_axis_tdata(axi_arp_slice_to_arp_tdata),
.m_axis_tkeep(axi_arp_slice_to_arp_tkeep),
.m_axis_tlast(axi_arp_slice_to_arp_tlast)
);
// ARP Output Slice
/*axis_register_slice_64 axis_register_arp_out_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_arp_to_arp_slice_tvalid),
.s_axis_tready(axi_arp_to_arp_slice_tready),
.s_axis_tdata(axi_arp_to_arp_slice_tdata),
.s_axis_tkeep(axi_arp_to_arp_slice_tkeep),
.s_axis_tlast(axi_arp_to_arp_slice_tlast),
.m_axis_tvalid(axi_arp_slice_to_mie_tvalid),
.m_axis_tready(axi_arp_slice_to_mie_tready),
.m_axis_tdata(axi_arp_slice_to_mie_tdata),
.m_axis_tkeep(axi_arp_slice_to_mie_tkeep),
.m_axis_tlast(axi_arp_slice_to_mie_tlast)
);*/
// ICMP Input Slice
axis_register_slice_64 axis_register_icmp_in_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_iph_to_icmp_slice_tvalid),
.s_axis_tready(axi_iph_to_icmp_slice_tready),
.s_axis_tdata(axi_iph_to_icmp_slice_tdata),
.s_axis_tkeep(axi_iph_to_icmp_slice_tkeep),
.s_axis_tlast(axi_iph_to_icmp_slice_tlast),
.m_axis_tvalid(axi_icmp_slice_to_icmp_tvalid),
.m_axis_tready(axi_icmp_slice_to_icmp_tready),
.m_axis_tdata(axi_icmp_slice_to_icmp_tdata),
.m_axis_tkeep(axi_icmp_slice_to_icmp_tkeep),
.m_axis_tlast(axi_icmp_slice_to_icmp_tlast)
);
// ICMP Output Slice
/*axis_register_slice_64 axis_register_icmp_out_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_icmp_to_icmp_slice_tvalid),
.s_axis_tready(axi_icmp_to_icmp_slice_tready),
.s_axis_tdata(axi_icmp_to_icmp_slice_tdata),
.s_axis_tkeep(axi_icmp_to_icmp_slice_tkeep),
.s_axis_tlast(axi_icmp_to_icmp_slice_tlast),
.m_axis_tvalid(axi_icmp_slice_to_mie_tvalid),
.m_axis_tready(axi_icmp_slice_to_mie_tready),
.m_axis_tdata(axi_icmp_slice_to_mie_tdata),
.m_axis_tkeep(axi_icmp_slice_to_mie_tkeep),
.m_axis_tlast(axi_icmp_slice_to_mie_tlast)
);*/
// UDP Input Slice
axis_register_slice_64 axis_register_udp_in_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_iph_to_udp_slice_tvalid),
.s_axis_tready(axi_iph_to_udp_slice_tready),
.s_axis_tdata(axi_iph_to_udp_slice_tdata),
.s_axis_tkeep(axi_iph_to_udp_slice_tkeep),
.s_axis_tlast(axi_iph_to_udp_slice_tlast),
.m_axis_tvalid(axi_udp_slice_to_udp_tvalid),
.m_axis_tready(axi_udp_slice_to_udp_tready),
.m_axis_tdata(axi_udp_slice_to_udp_tdata),
.m_axis_tkeep(axi_udp_slice_to_udp_tkeep),
.m_axis_tlast(axi_udp_slice_to_udp_tlast)
);
// TOE Input Slice
axis_register_slice_64 axis_register_toe_in_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_iph_to_toe_slice_tvalid),
.s_axis_tready(axi_iph_to_toe_slice_tready),
.s_axis_tdata(axi_iph_to_toe_slice_tdata),
.s_axis_tkeep(axi_iph_to_toe_slice_tkeep),
.s_axis_tlast(axi_iph_to_toe_slice_tlast),
.m_axis_tvalid(axi_toe_slice_to_toe_tvalid),
.m_axis_tready(axi_toe_slice_to_toe_tready),
.m_axis_tdata(axi_toe_slice_to_toe_tdata),
.m_axis_tkeep(axi_toe_slice_to_toe_tkeep),
.m_axis_tlast(axi_toe_slice_to_toe_tlast)
);
// TOE Output Slice
/*axis_register_slice_64 axis_register_toe_out_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_toe_to_toe_slice_tvalid),
.s_axis_tready(axi_toe_to_toe_slice_tready),
.s_axis_tdata(axi_toe_to_toe_slice_tdata),
.s_axis_tkeep(axi_toe_to_toe_slice_tkeep),
.s_axis_tlast(axi_toe_to_toe_slice_tlast),
.m_axis_tvalid(axi_toe_slice_to_mie_tvalid),
.m_axis_tready(axi_toe_slice_to_mie_tready),
.m_axis_tdata(axi_toe_slice_to_mie_tdata),
.m_axis_tkeep(axi_toe_slice_to_mie_tkeep),
.m_axis_tlast(axi_toe_slice_to_mie_tlast)
);*/
//debug
/*reg[3:0] pkg_count;
reg[3:0] port_count;
always @(posedge aclk)
begin
if (aresetn == 0) begin
pkg_count <= 0;
port_count <= 0;
end
else begin
if ((axis_dhcp_tx_data_tvalid == 1'b1) && (axis_dhcp_tx_data_tready == 1'b1)) begin// && (axi_toe_to_toe_slice_tlast == 1'b1)) begin
pkg_count <= pkg_count + 1;
end
if ((axis_dhcp_open_port_status_tvalid == 1'b1) && (axis_dhcp_open_port_status_tready == 1'b1)) begin
port_count <= port_count + 1;
end
end
end
reg[255:0] debug_r;
reg[255:0] debug_r2;
always @(posedge aclk)
begin
debug_r[0] <= axis_dhcp_rx_data_tvalid;
debug_r[1] <= axis_dhcp_rx_data_tready;
debug_r[65:2] <= axis_dhcp_rx_data_tdata;
debug_r[73:66] <= axis_dhcp_rx_data_tkeep;
debug_r[74] <= axis_dhcp_rx_data_tlast;
debug_r[75] <= axi_udp_to_merge_tvalid;
debug_r[76] <= axi_udp_to_merge_tready;
debug_r[140:77] <= axi_udp_to_merge_tdata;
debug_r[148:141] <= axi_udp_to_merge_tkeep;
debug_r[149] <= axi_udp_to_merge_tlast;
debug_r[181:150] <= dhcp_ip_address;
debug_r[182] <= dhcp_ip_address_en;
debug_r[214:183] <= arp_ip_address;
/*debug_r[150] <= axi_iph_to_udp_tvalid;
debug_r[151] <= axi_iph_to_udp_tready;
debug_r[215:152] <= axi_iph_to_udp_tdata;
debug_r[223:216] <= axi_iph_to_udp_tkeep;
debug_r[224] <= axi_iph_to_udp_tlast;
debug_r[225] <= axis_dhcp_tx_data_tvalid;
debug_r[226] <= axis_dhcp_tx_data_tready;
debug_r[242:227] <= axis_dhcp_tx_data_tdata[15:0];
debug_r[243] <= axis_dhcp_tx_data_tlast;
debug_r[244] <= axis_dhcp_open_port_tvalid;
debug_r[245] <= axis_dhcp_open_port_tready;
//debug_r[243] <= axis_arp_lookup_request_TDATA),
debug_r[246] <= axis_dhcp_open_port_status_tvalid;
debug_r[247] <= axis_dhcp_open_port_status_tready;
//debug_r[248] <= axis_dhcp_open_port_status_tdata[0];
//debug_r[248] <= axis_txbuffer2tcp_TVALID;
//debug_r[249] <= axis_txbuffer2tcp_TREADY;
//debug_r[247] <= axis_txbuffer2tcp_TDATA;
//debug_r[247] <= axis_txbuffer2tcp_TKEEP;
//debug_r[250] <= axis_txbuffer2tcp_TLAST;*/
/*debug_r[251:248] <= port_count;
debug_r[255:252] <= pkg_count;
debug_r2 <= debug_r;
end
wire [35:0] control0;
wire [35:0] control1;
wire [63:0] vio_signals;
wire [255:0] debug_signal;
assign debug_signal = debug_r2;
icon icon_isnt
(
.CONTROL0 (control0),
.CONTROL1 (control1)
);
ila_256 ila_inst
(
.CLK (aclk),
.CONTROL (control0),
.TRIG0 (debug_signal)
);
vio vio_inst
(
.CLK (aclk),
.CONTROL (control1),
.SYNC_OUT (vio_signals)
);*/
endmodule |
// file: system_clk_wiz_1_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1___200.000______0.000______50.0______114.829_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module system_clk_wiz_1_0_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_system_clk_wiz_1_0;
wire clk_in2_system_clk_wiz_1_0;
IBUF clkin1_ibufg
(.O (clk_in1_system_clk_wiz_1_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_system_clk_wiz_1_0;
wire clk_out2_system_clk_wiz_1_0;
wire clk_out3_system_clk_wiz_1_0;
wire clk_out4_system_clk_wiz_1_0;
wire clk_out5_system_clk_wiz_1_0;
wire clk_out6_system_clk_wiz_1_0;
wire clk_out7_system_clk_wiz_1_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_system_clk_wiz_1_0;
wire clkfbout_buf_system_clk_wiz_1_0;
wire clkfboutb_unused;
wire clkout1_unused;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (10),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (5),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (10.0))
plle2_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_system_clk_wiz_1_0),
.CLKOUT0 (clk_out1_system_clk_wiz_1_0),
.CLKOUT1 (clkout1_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_system_clk_wiz_1_0),
.CLKIN1 (clk_in1_system_clk_wiz_1_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (locked_int),
.PWRDWN (1'b0),
.RST (1'b0));
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_system_clk_wiz_1_0),
.I (clkfbout_system_clk_wiz_1_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_system_clk_wiz_1_0));
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* blackbox *)
module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
addressstall_a, addressstall_b);
parameter clock_enable_input_b = "ALTERNATE";
parameter clock_enable_input_a = "ALTERNATE";
parameter clock_enable_output_b = "NORMAL";
parameter clock_enable_output_a = "NORMAL";
parameter wrcontrol_aclr_a = "NONE";
parameter indata_aclr_a = "NONE";
parameter address_aclr_a = "NONE";
parameter outdata_aclr_a = "NONE";
parameter outdata_reg_a = "UNREGISTERED";
parameter operation_mode = "SINGLE_PORT";
parameter intended_device_family = "MAX 10 FPGA";
parameter outdata_reg_b = "UNREGISTERED";
parameter lpm_type = "altsyncram";
parameter init_type = "unused";
parameter ram_block_type = "AUTO";
parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
parameter power_up_uninitialized = "FALSE";
parameter read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ";
parameter width_byteena_a = 1;
parameter numwords_b = 0;
parameter numwords_a = 0;
parameter widthad_b = 1;
parameter width_b = 1;
parameter widthad_a = 1;
parameter width_a = 1;
// Port A declarations
output [35:0] q_a;
input [35:0] data_a;
input [7:0] address_a;
input wren_a;
input rden_a;
// Port B declarations
output [35:0] q_b;
input [35:0] data_b;
input [7:0] address_b;
input wren_b;
input rden_b;
// Control signals
input clock0, clock1;
input clocken0, clocken1, clocken2, clocken3;
input aclr0, aclr1;
input addressstall_a;
input addressstall_b;
// TODO: Implement the correct simulation model
endmodule // altsyncram
|
/*
--------------------------------------------------------------------------
Pegasus - Copyright (C) 2012 Gregory Matthew James.
This file is part of Pegasus.
Pegasus is free; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Pegasus is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------
-- Project Code : pegasus
-- Module Name : <module_name>
-- Author : mammenx
-- Associated modules:
-- Function :
--------------------------------------------------------------------------
*/
`timescale 1ns / 10ps
module <module_name> (
);
//----------------------- Global parameters Declarations ------------------
//----------------------- Input Declarations ------------------------------
//----------------------- Inout Declarations ------------------------------
//----------------------- Output Declarations -----------------------------
//----------------------- Output Register Declaration ---------------------
//----------------------- Internal Register Declarations ------------------
//----------------------- Internal Wire Declarations ----------------------
//----------------------- FSM Parameters --------------------------------------
//only for FSM state vector representation
parameter [?:0] // synopsys enum fsm_pstate
IDLE = ,
//----------------------- FSM Register Declarations ------------------
reg [?:0] // synopsys enum fsm_pstate
fsm_pstate, next_state;
//----------------------- FSM String Declarations ------------------
//synthesis translate_off
reg [8*?:0] state_name;//"state name" is user defined
//synthesis translate_on
//----------------------- FSM Debugging Logic Declarations ------------------
//synthesis translate_off
always @ (fsm_pstate)
begin
case (fsm_pstate)
<IDLE> : state_name = "IDLE";
<state2> : state_name = "state2";
.
.
.
<default> : state_name = "default";
endcase
end
//synthesis translate_on
//----------------------- Input/Output Registers --------------------------
//----------------------- Start of Code -----------------------------------
//code should be <=200 lines
/* comments for assign statements
*/
//assign statements
/* comments for combinatory logic
Asynchronous part of FSM
*/
/* comments for sequential logic
*/
//<sequential logic>;
endmodule // <module_name>
/*
--------------------------------------------------------------------------
-- <Header>
-- <Log>
[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file
--------------------------------------------------------------------------
*/
|
/**
* ------------------------------------------------------------
* Copyright (c) SILAB , Physics Institute of Bonn University
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "firmware/src/fe65p2_mio.v"
module tb (
input wire FCLK_IN,
//full speed
inout wire [7:0] BUS_DATA,
input wire [15:0] ADD,
input wire RD_B,
input wire WR_B,
//high speed
inout wire [7:0] FD,
input wire FREAD,
input wire FSTROBE,
input wire FMODE,
output wire CLK_BX,
input wire [64*64-1:0] HIT,
input wire TRIGGER,
output wire [1:0] RESET
);
wire [19:0] SRAM_A;
wire [15:0] SRAM_IO;
wire SRAM_BHE_B;
wire SRAM_BLE_B;
wire SRAM_CE1_B;
wire SRAM_OE_B;
wire SRAM_WE_B;
//wire [1:0] RESET;
//wire CLK_BX;
wire TRIGGER_DUT;
wire CLK_CNFG;
wire EN_PIX_SR_CNFG;
wire LD_CNFG;
wire SI_CNFG;
wire SO_CNFG;
wire PIX_D_CONF;
wire CLK_DATA;
wire OUT_DATA;
wire HIT_OR;
wire INJ;
fe65p2_mio fpga (
.FCLK_IN(FCLK_IN),
.BUS_DATA(BUS_DATA),
.ADD(ADD),
.RD_B(RD_B),
.WR_B(WR_B),
.FDATA(FD),
.FREAD(FREAD),
.FSTROBE(FSTROBE),
.FMODE(FMODE),
.SRAM_A(SRAM_A),
.SRAM_IO(SRAM_IO),
.SRAM_BHE_B(SRAM_BHE_B),
.SRAM_BLE_B(SRAM_BLE_B),
.SRAM_CE1_B(SRAM_CE1_B),
.SRAM_OE_B(SRAM_OE_B),
.SRAM_WE_B(SRAM_WE_B),
.DUT_RESET(RESET) ,
.DUT_CLK_BX(CLK_BX),
.DUT_TRIGGER(TRIGGER_DUT),
.DUT_INJ(INJ),
.DUT_CLK_CNFG(CLK_CNFG),
.DUT_EN_PIX_SR_CNFG(EN_PIX_SR_CNFG),
.DUT_LD_CNFG(LD_CNFG),
.DUT_SI_CNFG(SI_CNFG),
.DUT_SO_CNFG(SO_CNFG),
.DUT_PIX_D_CONF(PIX_D_CONF),
.DUT_CLK_DATA(CLK_DATA),
.DUT_OUT_DATA(OUT_DATA),
.DUT_HIT_OR(HIT_OR)
);
wire [64*64-1:0] ANA_HIT;
wire TRIGGER_FE;
assign TRIGGER_FE = TRIGGER_DUT | TRIGGER;
wire PrmpVbp, vthin1, vthin2, vff, VctrCF0, VctrCF1, PrmpVbnFol, vbnLcc, compVbn, preCompVbn, RefVbn;
wire [31:0] test_out1L, test_out1R, test_out2L, test_out2R, test_out2bL, test_out2bR;
wire [63:0] outDiscInvR;
wire HIT_OR_N, OUT_DATA_N;
wire OUT_DATA_P;
fe65p2 dut(
ANA_HIT,
RESET ,
CLK_BX,
TRIGGER_FE,
HIT_OR,
HIT_OR_N,
CLK_CNFG,
EN_PIX_SR_CNFG,
LD_CNFG,
SI_CNFG,
SO_CNFG,
PIX_D_CONF,
CLK_DATA,
OUT_DATA_P,
OUT_DATA_N,
~INJ,
PrmpVbp, vthin1, vthin2, vff, VctrCF0, VctrCF1, PrmpVbnFol, vbnLcc, compVbn, preCompVbn, RefVbn,
test_out1L, test_out1R, test_out2L, test_out2R, test_out2bL, test_out2bR, outDiscInvR
);
assign #5500 OUT_DATA = OUT_DATA_P;
//SRAM Model
reg [15:0] sram [1048576-1:0];
assign SRAM_IO = !SRAM_OE_B ? sram[SRAM_A] : 16'hzzzz;
always@(negedge SRAM_WE_B)
sram[SRAM_A] <= SRAM_IO;
assign ANA_HIT = HIT;
initial begin
$dumpfile("fe65p2.vcd");
$dumpvars(0);
//force dut.i_output_data.iser_div.cnt = 4'b0;
//#10 force CLK_DATA = 4'b0;
//#100000 force CLK_DATA = 4'b1;
//#10000 release CLK_DATA;
//#50000 release dut.i_output_data.iser_div.cnt;
end
endmodule
|
// megafunction wizard: %LPM_CLSHIFT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_CLSHIFT
// ============================================================
// File Name: SHIFT.v
// Megafunction Name(s):
// LPM_CLSHIFT
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module SHIFT (
data,
direction,
distance,
result);
input [15:0] data;
input direction;
input [3:0] distance;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_clshift LPM_CLSHIFT_component (
.data (data),
.direction (direction),
.distance (distance),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock (),
.overflow (),
.underflow ()
// synopsys translate_on
);
defparam
LPM_CLSHIFT_component.lpm_shifttype = "LOGICAL",
LPM_CLSHIFT_component.lpm_type = "LPM_CLSHIFT",
LPM_CLSHIFT_component.lpm_width = 16,
LPM_CLSHIFT_component.lpm_widthdist = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
// Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "16"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: lpm_widthdist NUMERIC "4"
// Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: port_direction NUMERIC "2"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: direction 0 0 0 0 INPUT NODEFVAL "direction"
// Retrieval info: USED_PORT: distance 0 0 4 0 INPUT NODEFVAL "distance[3..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @direction 0 0 0 0 direction 0 0 0 0
// Retrieval info: CONNECT: @distance 0 0 4 0 distance 0 0 4 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT_bb.v TRUE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S6S_1_V
`define SKY130_FD_SC_MS__DLYMETAL6S6S_1_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog wrapper for dlymetal6s6s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlymetal6s6s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlymetal6s6s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlymetal6s6s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlymetal6s6s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlymetal6s6s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S6S_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19.02.2017 01:26:40
// Design Name:
// Module Name: seg_disp
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module seg_disp(
input clk,
input[7:0] d1,
input[7:0] d2,
input[7:0] d3,
input[7:0] d4,
input dp,
output reg[6:0] seg,
output reg[3:0] an,
output dp_pin
);
wire[6:0] seg1;
wire[6:0] seg2;
wire[6:0] seg3;
wire[6:0] seg4;
reg[2:0] state = 0;
assign dp_pin = 1;
number_to_seg dd1(d1, seg1);
number_to_seg dd2(d2, seg2);
number_to_seg dd3(d3, seg3);
number_to_seg dd4(d4, seg4);
wire nd1 = (d1 == 0);
wire nd2 = (d2 == 0);
wire nd3 = (d3 == 0);
always @(posedge clk) begin
case (state)
default: state <= 0;
0: begin
seg <= seg1;
an <= nd1 ? 4'b1111 : 4'b0111;
state <= state + 1;
end
1: begin
seg <= seg2;
an <= nd1 && nd2 ? 4'b1111 : 4'b1011;
state <= state + 1;
end
2: begin
seg <= seg3;
an <= nd1 && nd2 && nd3 ? 4'b1111 : 4'b1101;
state <= state + 1;
end
3: begin
seg <= seg4;
an <= 4'b1110;
state <= 0;
end
endcase
end
endmodule
module number_to_seg(input[7:0] d, output[6:0] seg);
assign seg = (d == 0) ? 7'b1000000 :
(d == 1) ? 7'b1111001 :
(d == 2) ? 7'b0100100 :
(d == 3) ? 7'b0110000 :
(d == 4) ? 7'b0011001 :
(d == 5) ? 7'b0010010 :
(d == 6) ? 7'b0000010 :
(d == 7) ? 7'b1111000 :
(d == 8) ? 7'b0000000 :
(d == 9) ? 7'b0010000 : 7'b1000000;
endmodule
module num_to_digits(input[11:0] _num, output[3:0] _thousands, output [3:0] _hundreds, output [3:0] _tens, output [3:0] _ones);
assign _thousands = (_num % 10000) / 1000;
assign _hundreds = (_num % 1000) / 100;
assign _tens = (_num % 100) / 10;
assign _ones = _num % 10;
endmodule
module num_to_digits1(input[17:0] _num, output[3:0] _thousands, output [3:0] _hundreds, output [3:0] _tens, output [3:0] _ones);
assign _thousands = (_num % 10000) / 1000;
assign _hundreds = (_num % 1000) / 100;
assign _tens = (_num % 100) / 10;
assign _ones = _num % 10;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINV_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__CLKINV_PP_SYMBOL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkinv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINV_PP_SYMBOL_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: CLKPLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module CLKPLL (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [5:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 7,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 50000000,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 41176471,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=CLKPLL",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "70.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "41.176472"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "70.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "41.17647100"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "CLKPLL.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "50000000"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "41176471"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: GEN_FILE: TYPE_NORMAL CLKPLL.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLKPLL.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLKPLL.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLKPLL.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLKPLL.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLKPLL_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLKPLL_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTP_TB_V
`define SKY130_FD_SC_LS__DLRTP_TB_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrtp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ls__dlrtp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTP_TB_V
|
/*
Usage: 3 slices, 13 regs, 8 LUTs, 4 LUTRAMs, for 16-deep 8-bit FIFO
*/
module Fifo #(
parameter WIDTH = 8, ///< Width of data word
parameter LOG2_DEPTH = 4 ///< log2(depth of FIFO). Must be an integer
)
(
// Inputs
input clk, ///< System clock
input rst, ///< Reset FIFO pointer
input write, ///< Write strobe (1 clk)
input read, ///< Read strobe (1 clk)
input [WIDTH-1:0] dataIn, ///< Data to write
// Outputs
output wire [WIDTH-1:0] dataOut, ///< Data from FIFO
output reg dataPresent, ///< Data is present in FIFO
output wire halfFull, ///< FIFO is half full
output wire full ///< FIFO is full
);
reg [WIDTH-1:0] memory[2**LOG2_DEPTH-1:0];
reg [LOG2_DEPTH-1:0] pointer;
wire zero;
integer i;
// Zero out internal memory
initial begin
pointer = 'd0;
dataPresent = 1'b0;
for (i=0; i<(2**LOG2_DEPTH); i=i+1) begin
memory[i] = 'd0;
end
end
// Shift register for FIFO
always @(posedge clk) begin
if (write) begin
memory[0] <= dataIn;
for (i=1; i<(2**LOG2_DEPTH); i=i+1) begin
memory[i] <= memory[i-1];
end
end
end
assign dataOut = memory[pointer];
// Pointer for FIFO
always @(posedge clk) begin
if (rst) begin
pointer <= 'd0;
dataPresent <= 1'b0;
end
else begin
dataPresent <= write
| (dataPresent & ~zero)
| (dataPresent & zero & ~read);
case ({read, write})
2'b00 : pointer <= pointer;
2'b01 : pointer <= (!full && dataPresent) ? pointer + 2'd1 : pointer;
2'b10 : pointer <= (!zero) ? pointer - 2'd1 : pointer;
2'b11 : pointer <= pointer;
endcase
end
end
assign zero = ~|pointer;
assign halfFull = pointer[LOG2_DEPTH-1];
assign full = &pointer;
endmodule
|
/* Basic Gates */
module or2(output Z, input A, B);
wire i;
not(Z, i);
nor(i, A, B);
endmodule
module or4(output Z, input A, B, C, D);
wire [1:0]i;
or2 o0(i[0], A, B),
o1(i[1], C, D),
o2(Z, i[0], i[1]);
endmodule
module and2(output Z, input A, B);
nand(nz, A, B);
not(Z, nz);
endmodule
module and3(output Z, input A, B, C);
wire i;
and2 a0(i, A, B),
a1(Z, i, C);
endmodule
module xnor2(output Z, input A, B);
wire [1:0]i;
not(na, A);
not(nb, B);
and2 a0(i[0], A, B),
a1(i[1], na, nb);
or2 o0(Z, i[0], i[1]);
endmodule
module xor2(output Z, input A, B);
wire [1:0]i;
not (na, A);
not (nb, B);
and2 a0(i[0], A, nb),
a1(i[1], na, B);
or2 o0(Z, i[0], i[1]);
endmodule
/* ALU OP Codes */
module op_00(output Z, input A, B);
or2 o(Z, A, B);
endmodule
module op_01(output Z, input A, B);
xor2 x(Z, A, B);
endmodule
module op_10(output Z, input A, B, C);
wire i;
xnor2 x(i, B, C);
and2 a(Z, i, A);
endmodule
module op_11(output Z, input A, B, C);
wire i;
xor2 x(i, A, B);
nand n(Z, i, C);
endmodule
/* Mux (4) */
module mux_4_1(output Z, input [1:0] sel, input [3:0] i);
wire [1:0]n_s;
wire [3:0]a;
not(n_s[0], sel[0]);
not(n_s[1], sel[1]);
and3 a0(a[0], n_s[1], n_s[0], i[0]),
a1(a[1], n_s[1], sel[0], i[1]),
a2(a[2], sel[1], n_s[0], i[2]),
a3(a[3], sel[1], sel[0], i[3]);
or4 o0(Z, a[0], a[1], a[2], a[3]);
endmodule
/* ALUs */
module alu_01(output Z, input [1:0]op, input A, B, C);
wire [3:0]op_z;
op_00 op00(op_z[0], A, B);
op_01 op01(op_z[1], A, B);
op_10 op10(op_z[2], A, B, C);
op_11 op11(op_z[3], A, B, C);
mux_4_1 mux(Z, op, op_z);
endmodule
module alu_02(output [1:0]Z, input [1:0]op, input [1:0] A, B, C);
alu_01 a0(Z[0], op, A[0], B[0], C[0]),
a1(Z[1], op, A[1], B[1], C[1]);
endmodule
module alu_04(output [3:0]Z, input [1:0]op, input [3:0] A, B, C);
alu_02 a0(Z[1:0], op, A[1:0], B[1:0], C[1:0]),
a1(Z[3:2], op, A[3:2], B[3:2], C[3:2]);
endmodule
module alu_08(output [7:0]Z, input [1:0]op, input [7:0] A, B, C);
alu_04 a0(Z[3:0], op, A[3:0], B[3:0], C[3:0]),
a1(Z[7:4], op, A[7:4], B[7:4], C[7:4]);
endmodule
module alu_16(output [15:0]Z, input [1:0]op, input [15:0] A, B, C);
alu_08 a0(Z[7:0], op, A[7:0], B[7:0], C[7:0]),
a1(Z[15:8], op, A[15:8], B[15:8], C[15:8]);
endmodule
module alu_32(output [31:0]Z, input [1:0]op, input [31:0] A, B, C);
alu_16 a0(Z[15:0], op, A[15:0], B[15:0], C[15:0]),
a1(Z[31:16], op, A[31:16], B[31:16], C[31:16]);
endmodule
/* Testbench */
module p2_tb();
reg [31:0]A, B, C;
reg [1:0]op;
wire [31:0] Z;
alu_32 device(Z, op, A, B, C);
integer op_i, val_i;
initial begin
$dumpfile("p2.vcd");
$dumpvars(0, device);
$monitor("op(%b) A=%b B=%b C=%b => %b", op, A, B, C, Z);
for( op_i = 0; op_i <= 'b11; op_i = op_i + 1) begin
op = op_i[1:0];
for(val_i = 0; val_i <= 'b111; val_i = val_i + 1) begin
A = {32{val_i[2]}};
B = {32{val_i[1]}};
C = {32{val_i[0]}};
#10;
end
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 20:31:40 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n3505, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, left_right_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2,
ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM,
ZERO_FLAG_NRM, SIGN_FLAG_SFG, OP_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n1016, n1017, n1018, n1019,
n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029,
n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039,
n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049,
n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059,
n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069,
n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079,
n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089,
n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099,
n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109,
n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119,
n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129,
n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139,
n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149,
n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159,
n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169,
n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370,
n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380,
n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390,
n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400,
n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1473, n1474, n1476, n1477, n1479, n1480, n1482, n1483, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616,
n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726,
n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736,
n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746,
n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756,
n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766,
n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776,
n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786,
n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796,
n1797, n1798, n1799, n1800, n1801, n1802, n1803,
DP_OP_15J9_123_7955_n11, DP_OP_15J9_123_7955_n10,
DP_OP_15J9_123_7955_n9, DP_OP_15J9_123_7955_n8,
DP_OP_15J9_123_7955_n7, DP_OP_15J9_123_7955_n6, n1804, n1805, n1806,
n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816,
n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826,
n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836,
n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846,
n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856,
n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866,
n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876,
n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886,
n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896,
n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906,
n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916,
n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926,
n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936,
n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946,
n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956,
n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966,
n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976,
n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986,
n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996,
n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006,
n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016,
n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026,
n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036,
n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046,
n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056,
n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066,
n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076,
n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086,
n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096,
n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106,
n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116,
n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126,
n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136,
n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146,
n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156,
n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166,
n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176,
n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186,
n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196,
n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206,
n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216,
n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226,
n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236,
n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246,
n2247, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317,
n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327,
n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337,
n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347,
n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357,
n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367,
n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377,
n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387,
n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397,
n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407,
n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417,
n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427,
n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437,
n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447,
n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457,
n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467,
n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477,
n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487,
n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497,
n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507,
n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517,
n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527,
n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537,
n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547,
n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557,
n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567,
n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577,
n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587,
n2588, n2589, n2590, n2591, n2592, n2594, n2595, n2596, n2597, n2598,
n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608,
n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618,
n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628,
n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638,
n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648,
n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658,
n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668,
n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678,
n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688,
n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698,
n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708,
n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718,
n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728,
n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738,
n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748,
n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758,
n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768,
n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778,
n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788,
n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798,
n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808,
n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818,
n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828,
n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838,
n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848,
n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858,
n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868,
n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878,
n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888,
n2889, n2890, n2891, n2892, n2893, n2895, n2896, n2897, n2898, n2899,
n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909,
n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919,
n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929,
n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939,
n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949,
n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959,
n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969,
n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979,
n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989,
n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999,
n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009,
n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019,
n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029,
n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039,
n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049,
n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059,
n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069,
n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079,
n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089,
n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099,
n3100, n3101, n3102, n3103, n3104, n3105, n3107, n3108, n3109, n3110,
n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120,
n3121, n3122, n3123, n3125, n3126, n3127, n3128, n3129, n3130, n3131,
n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141,
n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151,
n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161,
n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171,
n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181,
n3182, n3183, n3184, n3185, n3186, n3187, n3189, n3190, n3191, n3192,
n3194, n3195, n3196, n3198, n3199, n3200, n3201, n3202, n3203, n3204,
n3205, n3206, n3207, n3208, n3210, n3211, n3212, n3213, n3214, n3215,
n3217, n3218, n3219, n3220, n3221, n3223, n3224, n3225, n3226, n3227,
n3228, n3229, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238,
n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248,
n3249, n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258,
n3259, n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268,
n3269, n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278,
n3279, n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288,
n3289, n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298,
n3299, n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308,
n3309, n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318,
n3319, n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328,
n3329, n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338,
n3339, n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348,
n3349, n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358,
n3359, n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368,
n3369, n3370, n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378,
n3379, n3380, n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388,
n3389, n3390, n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398,
n3399, n3400, n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408,
n3409, n3410, n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418,
n3419, n3420, n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428,
n3429, n3430, n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438,
n3439, n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448,
n3449, n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458,
n3459, n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468,
n3469, n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478,
n3479, n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488,
n3489, n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498,
n3499, n3500, n3501, n3503, n3504;
wire [3:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [63:0] intDY_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [62:0] DMP_SHT1_EWSW;
wire [50:0] DmP_mant_SHT1_SW;
wire [5:1] Shift_amount_SHT1_EWR;
wire [54:0] Raw_mant_NRM_SWR;
wire [44:0] Data_array_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [5:0] LZD_output_NRM2_EW;
wire [5:1] exp_rslt_NRM2_EW1;
wire [62:0] DMP_SFG;
wire [54:2] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n1798), .CK(clk), .RN(n3495), .Q(
Shift_reg_FLAGS_7[3]), .QN(n1886) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1730), .CK(clk), .RN(n3447), .Q(
intAS) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1728), .CK(clk), .RN(n3448),
.Q(intDY_EWSW[0]), .QN(n1820) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1626), .CK(clk), .RN(n3450), .QN(
n1819) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1616), .CK(clk), .RN(n3448), .QN(
n1828) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1614), .CK(clk), .RN(n3451), .QN(
n1827) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1613), .CK(clk), .RN(n3451), .Q(
Data_array_SWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1604), .CK(clk), .RN(n3441),
.QN(n1822) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1603), .CK(clk), .RN(n3452),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1602), .CK(clk), .RN(n3501),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1601), .CK(clk), .RN(n3441),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1600), .CK(clk), .RN(n3452),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1599), .CK(clk), .RN(n3470),
.Q(Shift_amount_SHT1_EWR[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1587), .CK(clk), .RN(n3460), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1586), .CK(clk), .RN(n3501), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1585), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1584), .CK(clk), .RN(n3462), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1583), .CK(clk), .RN(n3441), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1582), .CK(clk), .RN(n3457), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1581), .CK(clk), .RN(n3499), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1580), .CK(clk), .RN(n3452), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1579), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1578), .CK(clk), .RN(n3460), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1577), .CK(clk), .RN(n3501), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1576), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1575), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1574), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1573), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1572), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1571), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1570), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1569), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1568), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1567), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1566), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1565), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1564), .CK(clk), .RN(n3500), .Q(
DMP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1563), .CK(clk), .RN(n3500), .Q(
DMP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1562), .CK(clk), .RN(n3476), .Q(
DMP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1561), .CK(clk), .RN(n3477), .Q(
DMP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1560), .CK(clk), .RN(n3478), .Q(
DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1559), .CK(clk), .RN(n3462), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1558), .CK(clk), .RN(n3499), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1557), .CK(clk), .RN(n3460), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1556), .CK(clk), .RN(n3441), .Q(
DMP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1555), .CK(clk), .RN(n3468), .Q(
DMP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1554), .CK(clk), .RN(n3442), .Q(
DMP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_34_ ( .D(n1553), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1552), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1551), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1550), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_38_ ( .D(n1549), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1548), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1547), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1546), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1545), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1544), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1543), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1542), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1541), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1540), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1539), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1538), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_50_ ( .D(n1537), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1536), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1530), .CK(clk), .RN(n3455), .QN(
n1837) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1529), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[58]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1528), .CK(clk), .RN(n3456), .Q(
DMP_EXP_EWSW[59]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1527), .CK(clk), .RN(n3456), .Q(
DMP_EXP_EWSW[60]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1526), .CK(clk), .RN(n3456), .Q(
DMP_EXP_EWSW[61]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1525), .CK(clk), .RN(n3456), .Q(
DMP_EXP_EWSW[62]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1524), .CK(clk), .RN(n3456), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1523), .CK(clk), .RN(n3456), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1522), .CK(clk), .RN(n3456), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1521), .CK(clk), .RN(n3456), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1520), .CK(clk), .RN(n3456), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_0_ ( .D(n1519), .CK(clk), .RN(n3456), .Q(
DMP_SFG[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1518), .CK(clk), .RN(n3456), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1517), .CK(clk), .RN(n3456), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_1_ ( .D(n1516), .CK(clk), .RN(n3444), .Q(
DMP_SFG[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1515), .CK(clk), .RN(n3498), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1514), .CK(clk), .RN(n3500), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n1513), .CK(clk), .RN(n3460), .Q(
DMP_SFG[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1512), .CK(clk), .RN(n3476), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1511), .CK(clk), .RN(n3500), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n1510), .CK(clk), .RN(n3470), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1509), .CK(clk), .RN(n3477), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1508), .CK(clk), .RN(n3500), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n1507), .CK(clk), .RN(n3448), .Q(
DMP_SFG[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1506), .CK(clk), .RN(n3478), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1505), .CK(clk), .RN(n3500), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_5_ ( .D(n1504), .CK(clk), .RN(n3492), .Q(
DMP_SFG[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1503), .CK(clk), .RN(n3457), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1502), .CK(clk), .RN(n3470), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1501), .CK(clk), .RN(n3468), .Q(
DMP_SFG[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1500), .CK(clk), .RN(n3494), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1499), .CK(clk), .RN(n3481), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1498), .CK(clk), .RN(n3469), .Q(
DMP_SFG[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1497), .CK(clk), .RN(n3492), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1496), .CK(clk), .RN(n3457), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n1495), .CK(clk), .RN(n3470), .Q(
DMP_SFG[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1494), .CK(clk), .RN(n3468), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1493), .CK(clk), .RN(n3481), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_9_ ( .D(n1492), .CK(clk), .RN(n3496), .Q(
DMP_SFG[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1491), .CK(clk), .RN(n3497), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1490), .CK(clk), .RN(n3493), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n1489), .CK(clk), .RN(n3458), .Q(
DMP_SFG[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1488), .CK(clk), .RN(n3474), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1487), .CK(clk), .RN(n3496), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n1486), .CK(clk), .RN(n3497), .Q(
DMP_SFG[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1485), .CK(clk), .RN(n3493), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n3439), .CK(clk), .RN(n3481), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1482), .CK(clk), .RN(n3458), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n3438), .CK(clk), .RN(n3470), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1479), .CK(clk), .RN(n3474), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n3437), .CK(clk), .RN(n3488), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1476), .CK(clk), .RN(n3496), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n3436), .CK(clk), .RN(n3488), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1473), .CK(clk), .RN(n3493), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n3435), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1470), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1469), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1467), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1466), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1464), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1463), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1461), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1460), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1458), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1457), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1455), .CK(clk), .RN(n3459), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1454), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1452), .CK(clk), .RN(n3462), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1451), .CK(clk), .RN(n3499), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1449), .CK(clk), .RN(n3460), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1448), .CK(clk), .RN(n3462), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1446), .CK(clk), .RN(n3499), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1445), .CK(clk), .RN(n3462), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1443), .CK(clk), .RN(n3460), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n3499), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1440), .CK(clk), .RN(n3460), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1439), .CK(clk), .RN(n3462), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1437), .CK(clk), .RN(n3499), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1436), .CK(clk), .RN(n3462), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1434), .CK(clk), .RN(n3461), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1433), .CK(clk), .RN(n3461), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1431), .CK(clk), .RN(n3461), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1430), .CK(clk), .RN(n3461), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1428), .CK(clk), .RN(n3461), .Q(
DMP_SHT1_EWSW[31]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1427), .CK(clk), .RN(n3461), .Q(
DMP_SHT2_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1425), .CK(clk), .RN(n3461), .Q(
DMP_SHT1_EWSW[32]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1424), .CK(clk), .RN(n3461), .Q(
DMP_SHT2_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1422), .CK(clk), .RN(n3461), .Q(
DMP_SHT1_EWSW[33]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1421), .CK(clk), .RN(n3461), .Q(
DMP_SHT2_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1419), .CK(clk), .RN(n3461), .Q(
DMP_SHT1_EWSW[34]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1418), .CK(clk), .RN(n3461), .Q(
DMP_SHT2_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1416), .CK(clk), .RN(n3460), .Q(
DMP_SHT1_EWSW[35]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1415), .CK(clk), .RN(n3462), .Q(
DMP_SHT2_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1413), .CK(clk), .RN(n3499), .Q(
DMP_SHT1_EWSW[36]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1412), .CK(clk), .RN(n3460), .Q(
DMP_SHT2_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1410), .CK(clk), .RN(n3462), .Q(
DMP_SHT1_EWSW[37]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1409), .CK(clk), .RN(n3499), .Q(
DMP_SHT2_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1407), .CK(clk), .RN(n3460), .Q(
DMP_SHT1_EWSW[38]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1406), .CK(clk), .RN(n3462), .Q(
DMP_SHT2_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1404), .CK(clk), .RN(n3499), .Q(
DMP_SHT1_EWSW[39]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1403), .CK(clk), .RN(n3460), .Q(
DMP_SHT2_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1401), .CK(clk), .RN(n3462), .Q(
DMP_SHT1_EWSW[40]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1400), .CK(clk), .RN(n3499), .Q(
DMP_SHT2_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1398), .CK(clk), .RN(n3459), .Q(
DMP_SHT1_EWSW[41]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1397), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1395), .CK(clk), .RN(n3463), .Q(
DMP_SHT1_EWSW[42]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1394), .CK(clk), .RN(n3463), .Q(
DMP_SHT2_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1392), .CK(clk), .RN(n3463), .Q(
DMP_SHT1_EWSW[43]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1391), .CK(clk), .RN(n3463), .Q(
DMP_SHT2_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1389), .CK(clk), .RN(n3463), .Q(
DMP_SHT1_EWSW[44]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1388), .CK(clk), .RN(n3463), .Q(
DMP_SHT2_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1386), .CK(clk), .RN(n3463), .Q(
DMP_SHT1_EWSW[45]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1385), .CK(clk), .RN(n3463), .Q(
DMP_SHT2_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1383), .CK(clk), .RN(n3463), .Q(
DMP_SHT1_EWSW[46]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1382), .CK(clk), .RN(n3463), .Q(
DMP_SHT2_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1380), .CK(clk), .RN(n3464), .Q(
DMP_SHT1_EWSW[47]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1379), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1377), .CK(clk), .RN(n3464), .Q(
DMP_SHT1_EWSW[48]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1376), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1374), .CK(clk), .RN(n3464), .Q(
DMP_SHT1_EWSW[49]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1373), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1371), .CK(clk), .RN(n3464), .Q(
DMP_SHT1_EWSW[50]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1370), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[50]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1368), .CK(clk), .RN(n3464), .Q(
DMP_SHT1_EWSW[51]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1367), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1365), .CK(clk), .RN(n3464), .Q(
DMP_SHT1_EWSW[52]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1364), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[52]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1363), .CK(clk), .RN(n3465), .Q(
DMP_SFG[52]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1362), .CK(clk), .RN(n3465), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1361), .CK(clk), .RN(n3468), .Q(
DMP_exp_NRM2_EW[0]), .QN(n3351) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1360), .CK(clk), .RN(n3465), .Q(
DMP_SHT1_EWSW[53]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1359), .CK(clk), .RN(n3465), .Q(
DMP_SHT2_EWSW[53]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1358), .CK(clk), .RN(n3465), .Q(
DMP_SFG[53]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(n3465), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1355), .CK(clk), .RN(n3465), .Q(
DMP_SHT1_EWSW[54]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1354), .CK(clk), .RN(n3465), .Q(
DMP_SHT2_EWSW[54]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1353), .CK(clk), .RN(n3465), .Q(
DMP_SFG[54]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1352), .CK(clk), .RN(n3465), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1350), .CK(clk), .RN(n3465), .Q(
DMP_SHT1_EWSW[55]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1349), .CK(clk), .RN(n3465), .Q(
DMP_SHT2_EWSW[55]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_55_ ( .D(n1348), .CK(clk), .RN(n3490), .Q(
DMP_SFG[55]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1347), .CK(clk), .RN(n3490), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1345), .CK(clk), .RN(n3466), .Q(
DMP_SHT1_EWSW[56]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1344), .CK(clk), .RN(n3466), .Q(
DMP_SHT2_EWSW[56]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_56_ ( .D(n1343), .CK(clk), .RN(n3466), .Q(
DMP_SFG[56]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1342), .CK(clk), .RN(n3466), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1340), .CK(clk), .RN(n3466), .Q(
DMP_SHT1_EWSW[57]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1339), .CK(clk), .RN(n3466), .Q(
DMP_SHT2_EWSW[57]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1338), .CK(clk), .RN(n3466), .Q(
DMP_SFG[57]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1337), .CK(clk), .RN(n3466), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1335), .CK(clk), .RN(n3466), .Q(
DMP_SHT1_EWSW[58]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1334), .CK(clk), .RN(n3466), .Q(
DMP_SHT2_EWSW[58]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1333), .CK(clk), .RN(n3467), .Q(
DMP_SFG[58]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1332), .CK(clk), .RN(n3459), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1330), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[59]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1329), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[59]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1328), .CK(clk), .RN(n3467), .Q(
DMP_SFG[59]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1327), .CK(clk), .RN(n3459), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1325), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[60]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1324), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[60]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1323), .CK(clk), .RN(n3467), .Q(
DMP_SFG[60]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1322), .CK(clk), .RN(n3459), .Q(
DMP_exp_NRM_EW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1320), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[61]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1319), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[61]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1318), .CK(clk), .RN(n3495), .Q(
DMP_SFG[61]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1317), .CK(clk), .RN(n3496), .Q(
DMP_exp_NRM_EW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1315), .CK(clk), .RN(n3500), .Q(
DMP_SHT1_EWSW[62]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1314), .CK(clk), .RN(n3458), .Q(
DMP_SHT2_EWSW[62]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1313), .CK(clk), .RN(n3497), .Q(
DMP_SFG[62]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1312), .CK(clk), .RN(n3482), .Q(
DMP_exp_NRM_EW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1310), .CK(clk), .RN(n3504), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1308), .CK(clk), .RN(n3484), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1306), .CK(clk), .RN(n3493), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1304), .CK(clk), .RN(n3481), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1302), .CK(clk), .RN(n3469), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1300), .CK(clk), .RN(n3492), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1298), .CK(clk), .RN(n3457), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1296), .CK(clk), .RN(n3470), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1294), .CK(clk), .RN(n3468), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1292), .CK(clk), .RN(n3457), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1290), .CK(clk), .RN(n3470), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1288), .CK(clk), .RN(n3468), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1286), .CK(clk), .RN(n3492), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1284), .CK(clk), .RN(n3469), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1282), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1280), .CK(clk), .RN(n3481), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1278), .CK(clk), .RN(n3469), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1277), .CK(clk), .RN(n3492),
.QN(n1838) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1276), .CK(clk), .RN(n3457), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1274), .CK(clk), .RN(n3470), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1272), .CK(clk), .RN(n3468), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1270), .CK(clk), .RN(n3481), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1269), .CK(clk), .RN(n3469),
.QN(n1834) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1268), .CK(clk), .RN(n3456), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1266), .CK(clk), .RN(n3465), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1264), .CK(clk), .RN(n3461), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1262), .CK(clk), .RN(n3454), .Q(
DmP_EXP_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1261), .CK(clk), .RN(n3490),
.QN(n1812) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1260), .CK(clk), .RN(n3478), .Q(
DmP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1258), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1256), .CK(clk), .RN(n3499), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1254), .CK(clk), .RN(n3444), .Q(
DmP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1252), .CK(clk), .RN(n3462), .Q(
DmP_EXP_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1251), .CK(clk), .RN(n3454),
.QN(n1813) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1250), .CK(clk), .RN(n3441), .Q(
DmP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1248), .CK(clk), .RN(n3441), .Q(
DmP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1246), .CK(clk), .RN(n3454), .Q(
DmP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1244), .CK(clk), .RN(n3449), .Q(
DmP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1242), .CK(clk), .RN(n3468), .Q(
DmP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1240), .CK(clk), .RN(n3443), .Q(
DmP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1238), .CK(clk), .RN(n3465), .Q(
DmP_EXP_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1237), .CK(clk), .RN(n3457),
.QN(n1814) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1236), .CK(clk), .RN(n3443), .Q(
DmP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1234), .CK(clk), .RN(n3487), .Q(
DmP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1232), .CK(clk), .RN(n2009), .Q(
DmP_EXP_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1231), .CK(clk), .RN(n3471),
.QN(n1830) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1230), .CK(clk), .RN(n3471), .Q(
DmP_EXP_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1229), .CK(clk), .RN(n3471),
.QN(n1832) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1228), .CK(clk), .RN(n3471), .Q(
DmP_EXP_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1227), .CK(clk), .RN(n3471),
.QN(n1811) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1226), .CK(clk), .RN(n3471), .Q(
DmP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1224), .CK(clk), .RN(n3471), .Q(
DmP_EXP_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1223), .CK(clk), .RN(n3471),
.QN(n1831) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1222), .CK(clk), .RN(n3471), .Q(
DmP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1220), .CK(clk), .RN(n3472), .Q(
DmP_EXP_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1219), .CK(clk), .RN(n3472),
.QN(n1829) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1218), .CK(clk), .RN(n3472), .Q(
DmP_EXP_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1217), .CK(clk), .RN(n3472),
.QN(n1835) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_47_ ( .D(n1216), .CK(clk), .RN(n3472), .Q(
DmP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1214), .CK(clk), .RN(n3472), .Q(
DmP_EXP_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1213), .CK(clk), .RN(n3472),
.QN(n1836) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1212), .CK(clk), .RN(n3472), .Q(
DmP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1210), .CK(clk), .RN(n3472), .Q(
DmP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1208), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1207), .CK(clk), .RN(n3473),
.QN(n1833) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1205), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[53]), .QN(n3318) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1202), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[56]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1198), .CK(clk), .RN(n3473), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1197), .CK(clk), .RN(n3473), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1196), .CK(clk), .RN(n3458), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1195), .CK(clk), .RN(n3474), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1194), .CK(clk), .RN(n3496),
.Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1192), .CK(clk), .RN(n3493), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n3434), .CK(clk), .RN(n3457), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1189), .CK(clk), .RN(n3458), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1188), .CK(clk), .RN(n3474), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1187), .CK(clk), .RN(n3496), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1186), .CK(clk), .RN(n3493), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1185), .CK(clk), .RN(n3458),
.Q(SIGN_FLAG_SHT1SHT2) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1155), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[43]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1151), .CK(clk), .RN(n3484), .Q(
Raw_mant_NRM_SWR[47]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n1149), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[49]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1141), .CK(clk), .RN(n3494),
.Q(LZD_output_NRM2_EW[5]), .QN(n3364) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1140), .CK(clk), .RN(n3474), .QN(
n1840) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1138), .CK(clk), .RN(n3469),
.Q(LZD_output_NRM2_EW[0]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1137), .CK(clk), .RN(n3493), .QN(
n1839) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1135), .CK(clk), .RN(n3468),
.Q(LZD_output_NRM2_EW[4]), .QN(n3365) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1130), .CK(clk), .RN(n3492),
.Q(LZD_output_NRM2_EW[1]), .QN(n3353) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1129), .CK(clk), .RN(n3475), .QN(
n1841) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n1125), .CK(clk), .RN(n3470),
.Q(LZD_output_NRM2_EW[3]), .QN(n3361) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1122), .CK(clk), .RN(n3457),
.Q(LZD_output_NRM2_EW[2]), .QN(n3352) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1121), .CK(clk), .RN(n3475), .QN(
n1842) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1113), .CK(clk), .RN(n3500), .Q(
DmP_mant_SFG_SWR[12]), .QN(n3432) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1111), .CK(clk), .RN(n3498), .Q(
DmP_mant_SFG_SWR[13]), .QN(n3433) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1053), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[17]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1047), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1046), .CK(clk), .RN(n3473), .Q(
DmP_mant_SFG_SWR[24]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1045), .CK(clk), .RN(n3472), .Q(
DmP_mant_SFG_SWR[25]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1044), .CK(clk), .RN(n3473), .Q(
DmP_mant_SFG_SWR[26]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1043), .CK(clk), .RN(n3472), .Q(
DmP_mant_SFG_SWR[27]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1042), .CK(clk), .RN(n2008), .Q(
DmP_mant_SFG_SWR[28]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1041), .CK(clk), .RN(n3479), .Q(
DmP_mant_SFG_SWR[29]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1027), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[43]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1026), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[44]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1025), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[45]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1024), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[46]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1023), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[47]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1018), .CK(clk), .RN(n3489), .Q(
DmP_mant_SFG_SWR[52]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1017), .CK(clk), .RN(n3489), .Q(
DmP_mant_SFG_SWR[53]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1016), .CK(clk), .RN(n3488), .Q(
DmP_mant_SFG_SWR[54]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1311), .CK(clk), .RN(n3480),
.Q(DMP_exp_NRM2_EW[10]), .QN(n3425) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1316), .CK(clk), .RN(n3484), .Q(
DMP_exp_NRM2_EW[9]), .QN(n3420) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1676), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[52]), .QN(n3415) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1745), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[49]), .QN(n3414) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1698), .CK(clk), .RN(n3504),
.Q(intDY_EWSW[30]), .QN(n3412) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1706), .CK(clk), .RN(n3483),
.Q(intDY_EWSW[22]), .QN(n3411) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1714), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[14]), .QN(n3410) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1679), .CK(clk), .RN(n3487),
.Q(intDY_EWSW[49]), .QN(n3409) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_54_ ( .D(n1664), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[44]), .QN(n3408) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n1663), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[43]), .QN(n3407) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1677), .CK(clk), .RN(n3498),
.Q(intDY_EWSW[51]), .QN(n3406) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1682), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[46]), .QN(n3405) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1686), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[42]), .QN(n3403) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1688), .CK(clk), .RN(n3465),
.Q(intDY_EWSW[40]), .QN(n3402) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1692), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[36]), .QN(n3401) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1694), .CK(clk), .RN(n3460),
.Q(intDY_EWSW[34]), .QN(n3400) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1695), .CK(clk), .RN(n3478),
.Q(intDY_EWSW[33]), .QN(n3399) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1683), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[45]), .QN(n3398) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1689), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[39]), .QN(n3397) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1321), .CK(clk), .RN(n3482), .Q(
DMP_exp_NRM2_EW[8]), .QN(n3394) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1733), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[61]), .QN(n3391) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1802), .CK(clk), .RN(
n3458), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n3390) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1671), .CK(clk), .RN(n3450),
.Q(intDY_EWSW[57]), .QN(n3389) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1678), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[50]), .QN(n3388) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1326), .CK(clk), .RN(n3485), .Q(
DMP_exp_NRM2_EW[7]), .QN(n3385) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1331), .CK(clk), .RN(n3483), .Q(
DMP_exp_NRM2_EW[6]), .QN(n3384) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1696), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[32]), .QN(n3380) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1700), .CK(clk), .RN(n3472),
.Q(intDY_EWSW[28]), .QN(n3379) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1702), .CK(clk), .RN(n3473),
.Q(intDY_EWSW[26]), .QN(n3378) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1704), .CK(clk), .RN(n3484),
.Q(intDY_EWSW[24]), .QN(n3377) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1708), .CK(clk), .RN(n3504),
.Q(intDY_EWSW[20]), .QN(n3376) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1710), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[18]), .QN(n3375) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1716), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[12]), .QN(n3374) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1720), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[8]), .QN(n3373) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1726), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[2]), .QN(n3372) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1707), .CK(clk), .RN(n3504),
.Q(intDY_EWSW[21]), .QN(n3371) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1715), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[13]), .QN(n3370) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1719), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[9]), .QN(n3368) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n1608), .CK(clk), .RN(n3451),
.Q(shift_value_SHT2_EWR[3]), .QN(n3345) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1136), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[0]), .QN(n3329) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1667), .CK(clk), .RN(n3448),
.Q(intDY_EWSW[61]), .QN(n3325) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1531), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[56]), .QN(n3321) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1740), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[54]), .QN(n3320) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1532), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[55]), .QN(n3319) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1533), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[54]), .QN(n3317) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1534), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[53]), .QN(n3316) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1722), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[6]), .QN(n3315) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1697), .CK(clk), .RN(n3463),
.Q(intDY_EWSW[31]), .QN(n3314) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1705), .CK(clk), .RN(n3482),
.Q(intDY_EWSW[23]), .QN(n3313) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1713), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[15]), .QN(n3312) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1685), .CK(clk), .RN(n3456),
.Q(intDY_EWSW[43]), .QN(n3311) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1687), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[41]), .QN(n3310) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1693), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[35]), .QN(n3309) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1681), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[47]), .QN(n3308) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1735), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[59]), .QN(n3307) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1717), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[11]), .QN(n3305) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1699), .CK(clk), .RN(n3485),
.Q(intDY_EWSW[29]), .QN(n3302) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1725), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[3]), .QN(n3301) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1701), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[27]), .QN(n3300) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1703), .CK(clk), .RN(n3488),
.Q(intDY_EWSW[25]), .QN(n3299) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1709), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[19]), .QN(n3298) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1711), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[17]), .QN(n3297) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1771), .CK(clk), .RN(n3452),
.Q(intDX_EWSW[23]), .QN(n3291) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1763), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[31]), .QN(n3290) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1779), .CK(clk), .RN(n3441),
.Q(intDX_EWSW[15]), .QN(n3287) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1116), .CK(clk), .RN(n3495), .Q(
Raw_mant_NRM_SWR[11]), .QN(n3286) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1675), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[53]), .QN(n3284) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1673), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[55]), .QN(n3283) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1674), .CK(clk), .RN(n3455),
.Q(intDY_EWSW[54]), .QN(n3282) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1672), .CK(clk), .RN(n3442),
.Q(intDY_EWSW[56]), .QN(n3281) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n3446),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1200), .CK(clk), .RN(n3473), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n1184), .CK(clk), .RN(n3496), .Q(
final_result_ieee[63]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1193), .CK(clk), .RN(n3493), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1115), .CK(clk), .RN(n3474), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(n1114), .CK(clk), .RN(n3474), .Q(
final_result_ieee[36]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1109), .CK(clk), .RN(n3490), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(n1106), .CK(clk), .RN(n3477), .Q(
final_result_ieee[39]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1101), .CK(clk), .RN(n3498), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(n1100), .CK(clk), .RN(n3476), .Q(
final_result_ieee[38]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1093), .CK(clk), .RN(n3498), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1092), .CK(clk), .RN(n3476), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1088), .CK(clk), .RN(n3477), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(n1087), .CK(clk), .RN(n3478), .Q(
final_result_ieee[40]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1084), .CK(clk), .RN(n3478), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(n1081), .CK(clk), .RN(n3498), .Q(
final_result_ieee[37]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1074), .CK(clk), .RN(n3476), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(n1073), .CK(clk), .RN(n3477), .Q(
final_result_ieee[33]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1072), .CK(clk), .RN(n2008), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(n1071), .CK(clk), .RN(n3491), .Q(
final_result_ieee[32]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1070), .CK(clk), .RN(n3479), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(n1069), .CK(clk), .RN(n2008), .Q(
final_result_ieee[34]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1064), .CK(clk), .RN(n3491), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1063), .CK(clk), .RN(n3479), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1062), .CK(clk), .RN(n2008), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(n1061), .CK(clk), .RN(n3491), .Q(
final_result_ieee[35]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1199), .CK(clk), .RN(n3473), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n1588), .CK(clk), .RN(n3482), .Q(
final_result_ieee[62]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1108), .CK(clk), .RN(n3477), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1107), .CK(clk), .RN(n3478), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1103), .CK(clk), .RN(n3498), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1102), .CK(clk), .RN(n3477), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1099), .CK(clk), .RN(n3478), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1098), .CK(clk), .RN(n3476), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1095), .CK(clk), .RN(n3498), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n1094), .CK(clk), .RN(n3476), .Q(
final_result_ieee[42]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1091), .CK(clk), .RN(n3477), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n1090), .CK(clk), .RN(n3478), .Q(
final_result_ieee[43]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1089), .CK(clk), .RN(n3498), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1086), .CK(clk), .RN(n3476), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n1085), .CK(clk), .RN(n3477), .Q(
final_result_ieee[41]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1083), .CK(clk), .RN(n3478), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1082), .CK(clk), .RN(n3498), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1080), .CK(clk), .RN(n3476), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n1079), .CK(clk), .RN(n3477), .Q(
final_result_ieee[44]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1078), .CK(clk), .RN(n3478), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n1077), .CK(clk), .RN(n3498), .Q(
final_result_ieee[45]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1076), .CK(clk), .RN(n3477), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n1075), .CK(clk), .RN(n3478), .Q(
final_result_ieee[46]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1068), .CK(clk), .RN(n3479), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n1067), .CK(clk), .RN(n2008), .Q(
final_result_ieee[48]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1066), .CK(clk), .RN(n3491), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1065), .CK(clk), .RN(n3479), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n1060), .CK(clk), .RN(n3484), .Q(
final_result_ieee[47]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1059), .CK(clk), .RN(n3480), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n1058), .CK(clk), .RN(n3483), .Q(
final_result_ieee[49]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n1057), .CK(clk), .RN(n3443), .Q(
final_result_ieee[50]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n1056), .CK(clk), .RN(n3485), .Q(
final_result_ieee[51]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n1598), .CK(clk), .RN(n3469), .Q(
final_result_ieee[52]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n1597), .CK(clk), .RN(n3492), .Q(
final_result_ieee[53]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n1596), .CK(clk), .RN(n3457), .Q(
final_result_ieee[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n1595), .CK(clk), .RN(n3470), .Q(
final_result_ieee[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n1594), .CK(clk), .RN(n3484), .Q(
final_result_ieee[56]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n1593), .CK(clk), .RN(n3482), .Q(
final_result_ieee[57]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n1592), .CK(clk), .RN(n3480), .Q(
final_result_ieee[58]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n1591), .CK(clk), .RN(n3483), .Q(
final_result_ieee[59]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n1590), .CK(clk), .RN(n3485), .Q(
final_result_ieee[60]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n1589), .CK(clk), .RN(n3442), .Q(
final_result_ieee[61]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n3481), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n3304) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1096), .CK(clk), .RN(n3477), .Q(
Raw_mant_NRM_SWR[10]), .QN(n3423) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1118), .CK(clk), .RN(n3469), .Q(
Raw_mant_NRM_SWR[8]), .QN(n3292) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1126), .CK(clk), .RN(n3475), .Q(
Raw_mant_NRM_SWR[4]), .QN(n3344) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1133), .CK(clk), .RN(n3475), .Q(
Raw_mant_NRM_SWR[2]), .QN(n3362) );
DFFRX2TS inst_ShiftRegister_Q_reg_0_ ( .D(n1795), .CK(clk), .RN(n3494), .Q(
Shift_reg_FLAGS_7[0]), .QN(n3426) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1180), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[18]), .QN(n3356) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1179), .CK(clk), .RN(n3447), .Q(
Raw_mant_NRM_SWR[19]), .QN(n3355) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1772), .CK(clk), .RN(n3441),
.Q(intDX_EWSW[22]), .QN(n3339) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1773), .CK(clk), .RN(n3452),
.Q(intDX_EWSW[21]), .QN(n3357) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1774), .CK(clk), .RN(n3441),
.Q(intDX_EWSW[20]), .QN(n3337) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1775), .CK(clk), .RN(n3452),
.Q(intDX_EWSW[19]), .QN(n3295) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1776), .CK(clk), .RN(n3441),
.Q(intDX_EWSW[18]), .QN(n3360) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1777), .CK(clk), .RN(n3452),
.Q(intDX_EWSW[17]), .QN(n3348) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1780), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[14]), .QN(n3328) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1724), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[4]), .QN(n3303) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1764), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[30]), .QN(n3338) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1765), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[29]), .QN(n3342) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1766), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[28]), .QN(n3336) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1767), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[27]), .QN(n3294) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1768), .CK(clk), .RN(n3441),
.Q(intDX_EWSW[26]), .QN(n3359) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1769), .CK(clk), .RN(n3452),
.Q(intDX_EWSW[25]), .QN(n3347) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1786), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[8]), .QN(n3349) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1748), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[46]), .QN(n3326) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1791), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[3]), .QN(n3331) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1758), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[36]), .QN(n3340) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1759), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[35]), .QN(n3289) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1761), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[33]), .QN(n3333) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1783), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[11]), .QN(n3330) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1737), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[57]), .QN(n3350) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1743), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[51]), .QN(n3354) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1744), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[50]), .QN(n3293) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1760), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[34]), .QN(n3335) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1684), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[44]), .QN(n3404) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1680), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[48]), .QN(n3381) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1734), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[60]), .QN(n3393) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1718), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[10]), .QN(n3369) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1752), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[42]), .QN(n3334) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1782), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[12]), .QN(n3327) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1749), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[45]), .QN(n3346) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1751), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[43]), .QN(n3288) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1753), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[41]), .QN(n3341) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1781), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[13]), .QN(n3343) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1739), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[55]), .QN(n3429) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1741), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[53]), .QN(n3428) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1712), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[16]), .QN(n3382) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1727), .CK(clk), .RN(n3462),
.Q(intDY_EWSW[1]), .QN(n3421) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1736), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[58]), .QN(n3392) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1690), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[38]), .QN(n3422) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1691), .CK(clk), .RN(n3449),
.Q(intDY_EWSW[37]), .QN(n3396) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1738), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[56]), .QN(n3285) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1163), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[35]), .QN(n3383) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1160), .CK(clk), .RN(n3484), .Q(
Raw_mant_NRM_SWR[38]), .QN(n3296) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1156), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[42]), .QN(n3366) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n1154), .CK(clk), .RN(n3486), .Q(
Raw_mant_NRM_SWR[44]) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1607), .CK(clk), .RN(n3440),
.Q(shift_value_SHT2_EWR[4]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1178), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1789), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1120), .CK(clk), .RN(n3460), .Q(
Raw_mant_NRM_SWR[7]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1169), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[29]) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n1799), .CK(clk), .RN(n3496), .Q(
n3505), .QN(n3503) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1128), .CK(clk), .RN(n3475), .Q(
Raw_mant_NRM_SWR[3]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1139), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1175), .CK(clk), .RN(n3484), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1631), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_26_ ( .D(n1636), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1634), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1756), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[38]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1757), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[37]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1742), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[52]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_27_ ( .D(n1637), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_29_ ( .D(n1639), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1750), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[44]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1747), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[47]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1746), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[48]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1778), .CK(clk), .RN(n3441),
.Q(intDX_EWSW[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1754), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[40]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1784), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1793), .CK(clk), .RN(n3490),
.Q(intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1762), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[32]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1787), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[7]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1770), .CK(clk), .RN(n3452),
.Q(intDX_EWSW[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1182), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1792), .CK(clk), .RN(n3458),
.Q(intDX_EWSW[2]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1164), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[34]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1110), .CK(clk), .RN(n3490), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1183), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1633), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_39_ ( .D(n1649), .CK(clk), .RN(n3501), .Q(
Data_array_SWR[32]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1628), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[14]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1181), .CK(clk), .RN(n3447), .Q(
Raw_mant_NRM_SWR[17]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1668), .CK(clk), .RN(n3440),
.Q(intDY_EWSW[60]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1670), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[58]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1666), .CK(clk), .RN(n3455),
.Q(intDY_EWSW[62]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1803), .CK(clk), .RN(
n3474), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1173), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[25]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1177), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_47_ ( .D(n1657), .CK(clk), .RN(n3451), .Q(
Data_array_SWR[37]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1622), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[10]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_37_ ( .D(n1647), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[30]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1168), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[30]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_42_ ( .D(n1652), .CK(clk), .RN(n3501), .Q(
Data_array_SWR[34]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_40_ ( .D(n1650), .CK(clk), .RN(n3501), .Q(
Data_array_SWR[33]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1609), .CK(clk), .RN(n3451),
.Q(shift_value_SHT2_EWR[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_49_ ( .D(n1659), .CK(clk), .RN(n3456), .Q(
Data_array_SWR[39]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1166), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[32]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1620), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[8]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1618), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1281), .CK(clk), .RN(n3481),
.Q(DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1289), .CK(clk), .RN(n3457),
.Q(DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1245), .CK(clk), .RN(n3487),
.Q(DmP_mant_SHT1_SW[32]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1263), .CK(clk), .RN(n3468),
.Q(DmP_mant_SHT1_SW[23]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1253), .CK(clk), .RN(n3461),
.Q(DmP_mant_SHT1_SW[28]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1257), .CK(clk), .RN(n3460),
.Q(DmP_mant_SHT1_SW[26]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1275), .CK(clk), .RN(n3470),
.Q(DmP_mant_SHT1_SW[17]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1162), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[36]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1731), .CK(clk), .RN(n3445),
.Q(intDX_EWSW[63]) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1190), .CK(clk), .RN(n3470), .Q(
OP_FLAG_SFG) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n1471), .CK(clk), .RN(n3488), .Q(
DMP_SFG[16]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1477), .CK(clk), .RN(n3488), .Q(
DMP_SFG[14]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n1468), .CK(clk), .RN(n3464), .Q(
DMP_SFG[17]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n1474), .CK(clk), .RN(n3488), .Q(
DMP_SFG[15]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n1465), .CK(clk), .RN(n3489), .Q(
DMP_SFG[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1112), .CK(clk), .RN(n3493), .Q(
Raw_mant_NRM_SWR[12]), .QN(n3358) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1297), .CK(clk), .RN(n3492), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1233), .CK(clk), .RN(n3461),
.Q(DmP_mant_SHT1_SW[38]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1243), .CK(clk), .RN(n3453),
.Q(DmP_mant_SHT1_SW[33]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1247), .CK(clk), .RN(n3470),
.Q(DmP_mant_SHT1_SW[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1255), .CK(clk), .RN(n3447),
.Q(DmP_mant_SHT1_SW[27]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1265), .CK(clk), .RN(n3462),
.Q(DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1273), .CK(clk), .RN(n3468),
.Q(DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1279), .CK(clk), .RN(n3481),
.Q(DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1287), .CK(clk), .RN(n3470),
.Q(DmP_mant_SHT1_SW[11]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1206), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[52]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1283), .CK(clk), .RN(n3468),
.Q(DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1285), .CK(clk), .RN(n3492),
.Q(DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1241), .CK(clk), .RN(n3446),
.Q(DmP_mant_SHT1_SW[34]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1259), .CK(clk), .RN(n3455),
.Q(DmP_mant_SHT1_SW[25]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1291), .CK(clk), .RN(n3469), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1303), .CK(clk), .RN(n3494), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1617), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[5]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1293), .CK(clk), .RN(n3481), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1301), .CK(clk), .RN(n3469), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1615), .CK(clk), .RN(n3451), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1295), .CK(clk), .RN(n3492), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1299), .CK(clk), .RN(n3457), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1305), .CK(clk), .RN(n3466), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1307), .CK(clk), .RN(n3504), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1309), .CK(clk), .RN(n3474), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1483), .CK(clk), .RN(n3468), .Q(
DMP_SFG[12]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1117), .CK(clk), .RN(n3496), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1124), .CK(clk), .RN(n3475), .Q(
DmP_mant_SFG_SWR[6]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1127), .CK(clk), .RN(n3475), .Q(
DmP_mant_SFG_SWR[4]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1132), .CK(clk), .RN(n3475), .Q(
DmP_mant_SFG_SWR[5]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1134), .CK(clk), .RN(n3475), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1097), .CK(clk), .RN(n3498), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1105), .CK(clk), .RN(n3476), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1119), .CK(clk), .RN(n3501), .Q(
DmP_mant_SFG_SWR[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1161), .CK(clk), .RN(n3484), .Q(
Raw_mant_NRM_SWR[37]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_28_ ( .D(n1638), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[23]), .QN(n1823) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1366), .CK(clk), .RN(n3491), .Q(
DMP_SFG[51]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1369), .CK(clk), .RN(n3479), .Q(
DMP_SFG[50]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1372), .CK(clk), .RN(n3491), .Q(
DMP_SFG[49]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1204), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[54]), .QN(n1821) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1480), .CK(clk), .RN(n3492), .Q(
DMP_SFG[13]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1378), .CK(clk), .RN(n3479), .Q(
DMP_SFG[47]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1384), .CK(clk), .RN(n3491), .Q(
DMP_SFG[45]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_43_ ( .D(n1390), .CK(clk), .RN(n3479), .Q(
DMP_SFG[43]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_41_ ( .D(n1396), .CK(clk), .RN(n3491), .Q(
DMP_SFG[41]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1402), .CK(clk), .RN(n3495), .Q(
DMP_SFG[39]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1408), .CK(clk), .RN(n3490), .Q(
DMP_SFG[37]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_35_ ( .D(n1414), .CK(clk), .RN(n3490), .Q(
DMP_SFG[35]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_33_ ( .D(n1420), .CK(clk), .RN(n3495), .Q(
DMP_SFG[33]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_31_ ( .D(n1426), .CK(clk), .RN(n3495), .Q(
DMP_SFG[31]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1432), .CK(clk), .RN(n3490), .Q(
DMP_SFG[29]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1438), .CK(clk), .RN(n3464), .Q(
DMP_SFG[27]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n1444), .CK(clk), .RN(n3489), .Q(
DMP_SFG[25]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1450), .CK(clk), .RN(n3464), .Q(
DMP_SFG[23]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1456), .CK(clk), .RN(n3489), .Q(
DMP_SFG[21]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n1462), .CK(clk), .RN(n3464), .Q(
DMP_SFG[19]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1375), .CK(clk), .RN(n3479), .Q(
DMP_SFG[48]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1381), .CK(clk), .RN(n3491), .Q(
DMP_SFG[46]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1387), .CK(clk), .RN(n3479), .Q(
DMP_SFG[44]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1393), .CK(clk), .RN(n2008), .Q(
DMP_SFG[42]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_40_ ( .D(n1399), .CK(clk), .RN(n2008), .Q(
DMP_SFG[40]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1405), .CK(clk), .RN(n3495), .Q(
DMP_SFG[38]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1411), .CK(clk), .RN(n3490), .Q(
DMP_SFG[36]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_34_ ( .D(n1417), .CK(clk), .RN(n3490), .Q(
DMP_SFG[34]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_32_ ( .D(n1423), .CK(clk), .RN(n3495), .Q(
DMP_SFG[32]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1429), .CK(clk), .RN(n3490), .Q(
DMP_SFG[30]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1435), .CK(clk), .RN(n3495), .Q(
DMP_SFG[28]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1441), .CK(clk), .RN(n3489), .Q(
DMP_SFG[26]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1447), .CK(clk), .RN(n3464), .Q(
DMP_SFG[24]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1453), .CK(clk), .RN(n3489), .Q(
DMP_SFG[22]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1459), .CK(clk), .RN(n3489), .Q(
DMP_SFG[20]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1611), .CK(clk), .RN(n3501), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1612), .CK(clk), .RN(n3441), .Q(
Data_array_SWR[2]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1201), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[57]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1049), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[21]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1050), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[20]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1721), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[7]), .QN(n3413) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1723), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[5]), .QN(n3387) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1665), .CK(clk), .RN(n3444),
.Q(intDY_EWSW[63]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1019), .CK(clk), .RN(n3488), .Q(
DmP_mant_SFG_SWR[51]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1020), .CK(clk), .RN(n3488), .Q(
DmP_mant_SFG_SWR[50]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1021), .CK(clk), .RN(n3488), .Q(
DmP_mant_SFG_SWR[49]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1022), .CK(clk), .RN(n3488), .Q(
DmP_mant_SFG_SWR[48]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1028), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[42]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1029), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[41]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1030), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[40]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1031), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[39]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1036), .CK(clk), .RN(n2008), .Q(
DmP_mant_SFG_SWR[34]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1037), .CK(clk), .RN(n3491), .Q(
DmP_mant_SFG_SWR[33]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1038), .CK(clk), .RN(n3479), .Q(
DmP_mant_SFG_SWR[32]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1048), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1605), .CK(clk), .RN(n3478),
.Q(shift_value_SHT2_EWR[5]), .QN(n3332) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1174), .CK(clk), .RN(n3477), .Q(
Raw_mant_NRM_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1104), .CK(clk), .RN(n3478), .Q(
Raw_mant_NRM_SWR[9]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1170), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[28]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1790), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[4]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1785), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1755), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[39]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1176), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[22]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1165), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[33]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_33_ ( .D(n1643), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[26]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1629), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1788), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[6]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1794), .CK(clk), .RN(n3490),
.Q(intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1669), .CK(clk), .RN(n3498),
.Q(intDY_EWSW[59]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_52_ ( .D(n1662), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[42]), .QN(n1826) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1624), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[12]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_44_ ( .D(n1654), .CK(clk), .RN(n3451), .Q(
Data_array_SWR[35]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1625), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[13]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1159), .CK(clk), .RN(n3484),
.QN(n1807) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_35_ ( .D(n1645), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[28]), .QN(n3416) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1619), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1267), .CK(clk), .RN(n3499),
.Q(DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1249), .CK(clk), .RN(n3490),
.Q(DmP_mant_SHT1_SW[30]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1211), .CK(clk), .RN(n3472),
.Q(DmP_mant_SHT1_SW[49]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1271), .CK(clk), .RN(n3457),
.Q(DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1239), .CK(clk), .RN(n3499),
.Q(DmP_mant_SHT1_SW[35]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1235), .CK(clk), .RN(n3457),
.Q(DmP_mant_SHT1_SW[37]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1167), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1215), .CK(clk), .RN(n3472),
.Q(DmP_mant_SHT1_SW[47]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1131), .CK(clk), .RN(n3475), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1123), .CK(clk), .RN(n3475), .Q(
Raw_mant_NRM_SWR[6]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_34_ ( .D(n1644), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[27]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1627), .CK(clk), .RN(n3448), .QN(
n1809) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_36_ ( .D(n1646), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[29]), .QN(n3417) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_38_ ( .D(n1648), .CK(clk), .RN(n3501), .Q(
Data_array_SWR[31]), .QN(n3418) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1225), .CK(clk), .RN(n3471),
.Q(DmP_mant_SHT1_SW[42]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1732), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[62]), .QN(n3306) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1209), .CK(clk), .RN(n3472),
.Q(DmP_mant_SHT1_SW[50]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1221), .CK(clk), .RN(n3471),
.Q(DmP_mant_SHT1_SW[44]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1157), .CK(clk), .RN(n3482),
.QN(n1816) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n1147), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[51]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1158), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[40]), .QN(n3363) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n1144), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[54]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_51_ ( .D(n1661), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[41]), .QN(n3395) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1142), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[14]), .QN(n3427) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1535), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[52]), .QN(n3424) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1040), .CK(clk), .RN(n3504), .Q(
DmP_mant_SFG_SWR[30]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1039), .CK(clk), .RN(n3491), .Q(
DmP_mant_SFG_SWR[31]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1035), .CK(clk), .RN(n3491), .Q(
DmP_mant_SFG_SWR[35]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1356), .CK(clk), .RN(n3481), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1351), .CK(clk), .RN(n3480), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1346), .CK(clk), .RN(n3483), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1341), .CK(clk), .RN(n3485), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1336), .CK(clk), .RN(n3483), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1610), .CK(clk), .RN(n3446), .Q(
Data_array_SWR[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1203), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[55]), .QN(n3322) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1143), .CK(clk), .RN(n3494), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1055), .CK(clk), .RN(n3469), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1054), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1052), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1051), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1034), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[36]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1033), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[37]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1032), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[38]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1635), .CK(clk), .RN(n3449), .QN(
n1825) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_43_ ( .D(n1653), .CK(clk), .RN(n3451), .QN(
n1824) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_30_ ( .D(n1640), .CK(clk), .RN(n3450), .QN(
n1818) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_32_ ( .D(n1642), .CK(clk), .RN(n3448), .QN(
n1817) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_45_ ( .D(n1655), .CK(clk), .RN(n3451), .QN(
n1810) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_41_ ( .D(n1651), .CK(clk), .RN(n3452), .QN(
n1806) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1153), .CK(clk), .RN(n3486), .Q(
Raw_mant_NRM_SWR[45]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1152), .CK(clk), .RN(n3486), .Q(
Raw_mant_NRM_SWR[46]), .QN(n3386) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1150), .CK(clk), .RN(n3500), .Q(
Raw_mant_NRM_SWR[48]), .QN(n3323) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n1146), .CK(clk), .RN(n3491), .Q(
Raw_mant_NRM_SWR[52]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n1145), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[53]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1172), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[26]), .QN(n3419) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1171), .CK(clk), .RN(n3484), .Q(
Raw_mant_NRM_SWR[27]), .QN(n3324) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_31_ ( .D(n1641), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1632), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1630), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[16]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_50_ ( .D(n1660), .CK(clk), .RN(n3441), .Q(
Data_array_SWR[40]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1623), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_46_ ( .D(n1656), .CK(clk), .RN(n3451), .Q(
Data_array_SWR[36]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_48_ ( .D(n1658), .CK(clk), .RN(n3451), .Q(
Data_array_SWR[38]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1621), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[9]) );
ADDFX1TS DP_OP_15J9_123_7955_U10 ( .A(n3352), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J9_123_7955_n10), .CO(DP_OP_15J9_123_7955_n9), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J9_123_7955_U9 ( .A(n3361), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J9_123_7955_n9), .CO(DP_OP_15J9_123_7955_n8), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J9_123_7955_U8 ( .A(n3365), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J9_123_7955_n8), .CO(DP_OP_15J9_123_7955_n7), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n1148), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[50]), .QN(n3367) );
CMPR32X2TS DP_OP_15J9_123_7955_U11 ( .A(n3353), .B(DMP_exp_NRM2_EW[1]), .C(
DP_OP_15J9_123_7955_n11), .CO(DP_OP_15J9_123_7955_n10), .S(
exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J9_123_7955_U7 ( .A(n3364), .B(DMP_exp_NRM2_EW[5]), .C(
DP_OP_15J9_123_7955_n7), .CO(DP_OP_15J9_123_7955_n6), .S(
exp_rslt_NRM2_EW1[5]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n1796), .CK(clk), .RN(n3490), .Q(
Shift_reg_FLAGS_7[1]), .QN(n1884) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1729), .CK(clk), .RN(n3447),
.Q(left_right_SHT2), .QN(n1804) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n1801), .CK(clk), .RN(n2009), .Q(
Shift_reg_FLAGS_7_6), .QN(n1887) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n1797), .CK(clk), .RN(n3468), .Q(
Shift_reg_FLAGS_7[2]), .QN(n3431) );
DFFRX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n1800), .CK(clk), .RN(n2009), .Q(
Shift_reg_FLAGS_7_5), .QN(n3430) );
CMPR32X2TS U1842 ( .A(n2985), .B(DMP_SFG[51]), .C(n2984), .CO(n2988), .S(
n2851) );
CLKINVX6TS U1843 ( .A(n1815), .Y(n1846) );
CMPR32X2TS U1844 ( .A(n2979), .B(DMP_SFG[50]), .C(n2978), .CO(n2984), .S(
n2980) );
OR2X4TS U1845 ( .A(n2482), .B(n2629), .Y(n2560) );
BUFX3TS U1846 ( .A(n2753), .Y(n2829) );
CMPR32X2TS U1847 ( .A(n2982), .B(DMP_SFG[49]), .C(n2981), .CO(n2978), .S(
n2983) );
INVX2TS U1848 ( .A(n3128), .Y(n2002) );
BUFX8TS U1849 ( .A(n2753), .Y(n2816) );
CLKINVX6TS U1850 ( .A(n2653), .Y(n2753) );
NAND2X2TS U1851 ( .A(n2003), .B(Shift_reg_FLAGS_7[1]), .Y(n3128) );
OAI221XLTS U1852 ( .A0(n2477), .A1(n2476), .B0(n2475), .B1(n2474), .C0(n2473), .Y(n2478) );
NAND4X1TS U1853 ( .A(n3123), .B(n2001), .C(n2000), .D(n1999), .Y(n2003) );
NOR2X4TS U1854 ( .A(Shift_reg_FLAGS_7[1]), .B(n3223), .Y(n2659) );
OAI211X1TS U1855 ( .A0(n1895), .A1(n1954), .B0(n1894), .C0(n1893), .Y(n1975)
);
NAND2X1TS U1856 ( .A(Raw_mant_NRM_SWR[15]), .B(n1890), .Y(n1994) );
CMPR32X2TS U1857 ( .A(n3105), .B(DMP_SFG[13]), .C(n3104), .CO(n3102), .S(
n3107) );
NOR2X1TS U1858 ( .A(Raw_mant_NRM_SWR[37]), .B(Raw_mant_NRM_SWR[38]), .Y(
n1916) );
INVX2TS U1859 ( .A(n1987), .Y(n1992) );
NOR2XLTS U1860 ( .A(n2459), .B(n2458), .Y(n2472) );
INVX2TS U1861 ( .A(n1943), .Y(n1935) );
INVX1TS U1862 ( .A(LZD_output_NRM2_EW[0]), .Y(n2835) );
NOR2XLTS U1863 ( .A(n2144), .B(n3241), .Y(n2145) );
INVX2TS U1864 ( .A(n2828), .Y(n1843) );
NAND2X1TS U1865 ( .A(beg_OP), .B(n3133), .Y(n3151) );
OAI211XLTS U1866 ( .A0(n2785), .A1(n2649), .B0(n2784), .C0(n2783), .Y(n1651)
);
OAI211XLTS U1867 ( .A0(n2695), .A1(n2753), .B0(n2694), .C0(n2693), .Y(n1648)
);
OAI211XLTS U1868 ( .A0(n2678), .A1(n2826), .B0(n2648), .C0(n2647), .Y(n1619)
);
OAI211XLTS U1869 ( .A0(n2823), .A1(n2826), .B0(n2791), .C0(n2790), .Y(n1629)
);
OAI211XLTS U1870 ( .A0(n2665), .A1(n2649), .B0(n2652), .C0(n2651), .Y(n1612)
);
OAI211XLTS U1871 ( .A0(n2657), .A1(n2822), .B0(n2656), .C0(n2655), .Y(n1611)
);
OAI211XLTS U1872 ( .A0(n2817), .A1(n2649), .B0(n2814), .C0(n2813), .Y(n1638)
);
OAI211XLTS U1873 ( .A0(n2666), .A1(n2822), .B0(n2661), .C0(n2660), .Y(n1617)
);
OAI211XLTS U1874 ( .A0(n2760), .A1(n2826), .B0(n2759), .C0(n2758), .Y(n1620)
);
OAI211XLTS U1875 ( .A0(n2834), .A1(n2833), .B0(n2832), .C0(n2831), .Y(n1659)
);
OAI211XLTS U1876 ( .A0(n2799), .A1(n2649), .B0(n2798), .C0(n2797), .Y(n1649)
);
OAI211XLTS U1877 ( .A0(n2719), .A1(n2753), .B0(n2718), .C0(n2717), .Y(n1639)
);
OAI211XLTS U1878 ( .A0(n2767), .A1(n2826), .B0(n2766), .C0(n2765), .Y(n1626)
);
CLKINVX6TS U1879 ( .A(n1815), .Y(n1845) );
AOI2BB2X1TS U1880 ( .B0(Raw_mant_NRM_SWR[26]), .B1(n2720), .A0N(n2719),
.A1N(n2833), .Y(n2679) );
OR2X2TS U1881 ( .A(n2736), .B(n2816), .Y(n2828) );
AOI2BB2X1TS U1882 ( .B0(Raw_mant_NRM_SWR[29]), .B1(n2720), .A0N(n2741),
.A1N(n2833), .Y(n2721) );
AOI2BB2X1TS U1883 ( .B0(Raw_mant_NRM_SWR[20]), .B1(n2756), .A0N(n2744),
.A1N(n2833), .Y(n2726) );
AOI2BB2X1TS U1884 ( .B0(Raw_mant_NRM_SWR[24]), .B1(n2720), .A0N(n2716),
.A1N(n2833), .Y(n2717) );
AOI2BB2X1TS U1885 ( .B0(Raw_mant_NRM_SWR[22]), .B1(n2720), .A0N(n2728),
.A1N(n2833), .Y(n2702) );
INVX6TS U1886 ( .A(n2807), .Y(n2649) );
NOR3X4TS U1887 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .C(n1954),
.Y(n1900) );
CLKMX2X2TS U1888 ( .A(Raw_mant_NRM_SWR[49]), .B(n2854), .S0(n3016), .Y(n1149) );
CLKINVX1TS U1889 ( .A(n1953), .Y(n1896) );
NOR3X6TS U1890 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[7]), .C(n3115),
.Y(n1953) );
AOI32X1TS U1891 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1981), .A2(n3292), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1981), .Y(n1984) );
NOR2X6TS U1892 ( .A(Raw_mant_NRM_SWR[10]), .B(n3114), .Y(n1981) );
INVX1TS U1893 ( .A(n1974), .Y(n1977) );
NOR2X4TS U1894 ( .A(Raw_mant_NRM_SWR[16]), .B(n1974), .Y(n1890) );
NAND2X4TS U1895 ( .A(n1901), .B(n1998), .Y(n1974) );
NAND2BX4TS U1896 ( .AN(Raw_mant_NRM_SWR[21]), .B(n1923), .Y(n1945) );
NAND2XLTS U1897 ( .A(n1986), .B(Raw_mant_NRM_SWR[22]), .Y(n1937) );
CLKINVX2TS U1898 ( .A(n1942), .Y(n1917) );
NOR3X4TS U1899 ( .A(Raw_mant_NRM_SWR[28]), .B(Raw_mant_NRM_SWR[29]), .C(
n1942), .Y(n1909) );
NOR2BX2TS U1900 ( .AN(n2125), .B(n3129), .Y(n2126) );
INVX2TS U1901 ( .A(n2127), .Y(n2128) );
NOR3X4TS U1902 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[31]), .C(
n1943), .Y(n1907) );
NAND2X1TS U1903 ( .A(n3394), .B(n2121), .Y(n2123) );
NAND2X1TS U1904 ( .A(n3385), .B(n2115), .Y(n2120) );
INVX1TS U1905 ( .A(n1911), .Y(n1912) );
NAND2X1TS U1906 ( .A(n3384), .B(n2114), .Y(n2118) );
INVX1TS U1907 ( .A(n1961), .Y(n1973) );
AOI21X1TS U1908 ( .A0(n3102), .A1(n2843), .B0(n2842), .Y(n3045) );
INVX4TS U1909 ( .A(n2734), .Y(n2704) );
NOR2X1TS U1910 ( .A(n3049), .B(n3051), .Y(n2843) );
INVX3TS U1911 ( .A(n2907), .Y(n2103) );
NOR2X4TS U1912 ( .A(Raw_mant_NRM_SWR[50]), .B(Raw_mant_NRM_SWR[49]), .Y(
n1965) );
CLKBUFX2TS U1913 ( .A(Raw_mant_NRM_SWR[14]), .Y(n1848) );
NAND2BXLTS U1914 ( .AN(intDY_EWSW[40]), .B(intDX_EWSW[40]), .Y(n2342) );
NAND2BXLTS U1915 ( .AN(intDY_EWSW[41]), .B(intDX_EWSW[41]), .Y(n2343) );
OAI211X1TS U1916 ( .A0(n2827), .A1(n2826), .B0(n2825), .C0(n2824), .Y(n1631)
);
OAI211X1TS U1917 ( .A0(n2786), .A1(n2649), .B0(n2776), .C0(n2775), .Y(n1655)
);
OAI211X1TS U1918 ( .A0(n2796), .A1(n2649), .B0(n2779), .C0(n2778), .Y(n1647)
);
OAI211X1TS U1919 ( .A0(n2830), .A1(n2649), .B0(n2788), .C0(n2787), .Y(n1657)
);
OAI211X1TS U1920 ( .A0(n2802), .A1(n2826), .B0(n2801), .C0(n2800), .Y(n1633)
);
OAI211X1TS U1921 ( .A0(n2763), .A1(n2826), .B0(n2762), .C0(n2761), .Y(n1622)
);
OAI211X1TS U1922 ( .A0(n2794), .A1(n2649), .B0(n2793), .C0(n2792), .Y(n1642)
);
OAI211X1TS U1923 ( .A0(n2782), .A1(n2711), .B0(n2781), .C0(n2780), .Y(n1653)
);
OAI211X1TS U1924 ( .A0(n2820), .A1(n2649), .B0(n2819), .C0(n2818), .Y(n1640)
);
OAI21X1TS U1925 ( .A0(n2816), .A1(n2740), .B0(n2735), .Y(n1664) );
OAI211X1TS U1926 ( .A0(n2826), .A1(n2740), .B0(n2739), .C0(n2738), .Y(n1662)
);
OAI211X1TS U1927 ( .A0(n2812), .A1(n2649), .B0(n2743), .C0(n2742), .Y(n1636)
);
OAI211X1TS U1928 ( .A0(n2764), .A1(n2826), .B0(n2755), .C0(n2754), .Y(n1624)
);
AOI22X1TS U1929 ( .A0(n2795), .A1(Data_array_SWR[15]), .B0(n1844), .B1(
DmP_mant_SHT1_SW[17]), .Y(n2791) );
AOI22X1TS U1930 ( .A0(n2815), .A1(Data_array_SWR[19]), .B0(n1844), .B1(
DmP_mant_SHT1_SW[21]), .Y(n2801) );
AOI22X1TS U1931 ( .A0(n2795), .A1(Data_array_SWR[30]), .B0(n1844), .B1(
DmP_mant_SHT1_SW[35]), .Y(n2779) );
OAI211X1TS U1932 ( .A0(n2777), .A1(n2649), .B0(n2746), .C0(n2745), .Y(n1645)
);
AOI2BB2X1TS U1933 ( .B0(n1846), .B1(n1872), .A0N(n2782), .A1N(n2816), .Y(
n2775) );
OAI211X1TS U1934 ( .A0(n2708), .A1(n2753), .B0(n2707), .C0(n2706), .Y(n1660)
);
OAI211X1TS U1935 ( .A0(n2712), .A1(n2753), .B0(n2689), .C0(n2688), .Y(n1658)
);
AOI2BB2X1TS U1936 ( .B0(n1846), .B1(n1874), .A0N(n2799), .A1N(n2816), .Y(
n2783) );
OAI211X1TS U1937 ( .A0(n2715), .A1(n2753), .B0(n2714), .C0(n2713), .Y(n1656)
);
AOI2BB1X1TS U1938 ( .A0N(n2737), .A1N(n2816), .B0(n1846), .Y(n2738) );
AOI2BB2X1TS U1939 ( .B0(n1846), .B1(DmP_mant_SHT1_SW[32]), .A0N(n2820),
.A1N(n2816), .Y(n2792) );
OAI211X1TS U1940 ( .A0(n2675), .A1(n2822), .B0(n2671), .C0(n2670), .Y(n1623)
);
OAI211X1TS U1941 ( .A0(n2698), .A1(n2822), .B0(n2687), .C0(n2686), .Y(n1632)
);
AOI2BB2X1TS U1942 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n2756), .A0N(n2737), .A1N(
n2711), .Y(n2706) );
OAI211X1TS U1943 ( .A0(n2723), .A1(n2822), .B0(n2722), .C0(n2721), .Y(n1634)
);
AOI2BB2X1TS U1944 ( .B0(Raw_mant_NRM_SWR[40]), .B1(n2720), .A0N(n2683),
.A1N(n2711), .Y(n2670) );
OAI211X1TS U1945 ( .A0(n2701), .A1(n2822), .B0(n2700), .C0(n2699), .Y(n1630)
);
OAI211X1TS U1946 ( .A0(n2729), .A1(n2753), .B0(n2710), .C0(n2709), .Y(n1654)
);
AOI2BB2X1TS U1947 ( .B0(Raw_mant_NRM_SWR[45]), .B1(n2720), .A0N(n2757),
.A1N(n2711), .Y(n2672) );
OAI211X1TS U1948 ( .A0(n2728), .A1(n2753), .B0(n2727), .C0(n2726), .Y(n1643)
);
OAI211X1TS U1949 ( .A0(n2692), .A1(n2753), .B0(n2691), .C0(n2690), .Y(n1650)
);
OAI211X1TS U1950 ( .A0(n2683), .A1(n2822), .B0(n2682), .C0(n2681), .Y(n1625)
);
OAI211X1TS U1951 ( .A0(n2774), .A1(n2753), .B0(n2697), .C0(n2696), .Y(n1646)
);
OAI211X1TS U1952 ( .A0(n2716), .A1(n2753), .B0(n2703), .C0(n2702), .Y(n1641)
);
AOI2BB2X1TS U1953 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n2756), .A0N(n2708), .A1N(
n2711), .Y(n2688) );
AOI2BB2X1TS U1954 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n2756), .A0N(n2712), .A1N(
n2711), .Y(n2713) );
OAI211X1TS U1955 ( .A0(n2733), .A1(n2753), .B0(n2732), .C0(n2731), .Y(n1652)
);
AOI2BB2X1TS U1956 ( .B0(Raw_mant_NRM_SWR[42]), .B1(n2720), .A0N(n2675),
.A1N(n2711), .Y(n2676) );
AOI2BB2X1TS U1957 ( .B0(Raw_mant_NRM_SWR[35]), .B1(n2720), .A0N(n2701),
.A1N(n2833), .Y(n2684) );
AOI2BB2X1TS U1958 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n2756), .A0N(n2692),
.A1N(n2833), .Y(n2693) );
AOI2BB2X1TS U1959 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n2756), .A0N(n2715), .A1N(
n2833), .Y(n2709) );
AOI2BB2X1TS U1960 ( .B0(Raw_mant_NRM_SWR[17]), .B1(n2756), .A0N(n2695),
.A1N(n2833), .Y(n2696) );
AOI2BB2X1TS U1961 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n2756), .A0N(n2733),
.A1N(n2833), .Y(n2690) );
AOI2BB2X1TS U1962 ( .B0(Raw_mant_NRM_SWR[38]), .B1(n2720), .A0N(n2747),
.A1N(n2833), .Y(n2681) );
AOI2BB2X1TS U1963 ( .B0(Raw_mant_NRM_SWR[33]), .B1(n2720), .A0N(n2698),
.A1N(n2833), .Y(n2699) );
AOI2BB2X1TS U1964 ( .B0(Raw_mant_NRM_SWR[48]), .B1(n2720), .A0N(n2826),
.A1N(n2666), .Y(n2667) );
OAI211X1TS U1965 ( .A0(n2669), .A1(n2826), .B0(n2638), .C0(n2637), .Y(n1613)
);
AOI2BB2X1TS U1966 ( .B0(Raw_mant_NRM_SWR[31]), .B1(n2720), .A0N(n2723),
.A1N(n2833), .Y(n2686) );
OAI211X1TS U1967 ( .A0(n2674), .A1(n2826), .B0(n2644), .C0(n2643), .Y(n1616)
);
OAI21X1TS U1968 ( .A0(n3329), .A1(n2730), .B0(n2633), .Y(n1663) );
NOR2X4TS U1969 ( .A(n2631), .B(n2795), .Y(n2653) );
AND2X2TS U1970 ( .A(n2636), .B(n2002), .Y(n2642) );
AOI222X1TS U1971 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[49]), .B0(n2750), .B1(
DmP_mant_SHT1_SW[3]), .C0(n2725), .C1(DmP_mant_SHT1_SW[4]), .Y(n2669)
);
AOI222X1TS U1972 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n2804), .B0(
Raw_mant_NRM_SWR[2]), .B1(n2810), .C0(DmP_mant_SHT1_SW[50]), .C1(n2751), .Y(n2834) );
AOI222X1TS U1973 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n2811), .B0(
Raw_mant_NRM_SWR[23]), .B1(n2810), .C0(n2725), .C1(n1853), .Y(n2817)
);
AOI222X1TS U1974 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n2811), .B0(n2725), .B1(
DmP_mant_SHT1_SW[26]), .C0(n2724), .C1(DmP_mant_SHT1_SW[25]), .Y(n2770) );
AOI222X1TS U1975 ( .A0(Raw_mant_NRM_SWR[35]), .A1(n2811), .B0(
Raw_mant_NRM_SWR[34]), .B1(n2810), .C0(n2751), .C1(
DmP_mant_SHT1_SW[18]), .Y(n2789) );
AOI222X1TS U1976 ( .A0(Raw_mant_NRM_SWR[36]), .A1(n2811), .B0(n2751), .B1(
DmP_mant_SHT1_SW[17]), .C0(n2750), .C1(n1856), .Y(n2767) );
NOR2X6TS U1977 ( .A(n3137), .B(n2003), .Y(n2639) );
CLKMX2X2TS U1978 ( .A(Raw_mant_NRM_SWR[53]), .B(n2851), .S0(n3016), .Y(n1145) );
OAI211XLTS U1979 ( .A0(n3358), .A1(n1956), .B0(n2001), .C0(n3122), .Y(n1957)
);
CLKMX2X2TS U1980 ( .A(Raw_mant_NRM_SWR[52]), .B(n2980), .S0(n3016), .Y(n1146) );
CLKMX2X2TS U1981 ( .A(Raw_mant_NRM_SWR[50]), .B(n2992), .S0(n3016), .Y(n1148) );
OAI21X1TS U1982 ( .A0(Raw_mant_NRM_SWR[8]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1892), .Y(n1893) );
NAND3X1TS U1983 ( .A(n1984), .B(n1983), .C(n1982), .Y(n1985) );
NAND2X4TS U1984 ( .A(n3286), .B(n1952), .Y(n3114) );
OAI211X1TS U1985 ( .A0(n3324), .A1(n1950), .B0(n1949), .C0(n1948), .Y(n1951)
);
AOI31X1TS U1986 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1998), .A2(n3356), .B0(
n1997), .Y(n2000) );
OAI211X1TS U1987 ( .A0(n1996), .A1(n3383), .B0(n1995), .C0(n1994), .Y(n1997)
);
INVX1TS U1988 ( .A(n3247), .Y(n3249) );
OR2X4TS U1989 ( .A(n2126), .B(n3215), .Y(n3247) );
NAND3X1TS U1990 ( .A(n2136), .B(n3129), .C(n2135), .Y(n3226) );
NOR2X1TS U1991 ( .A(n2122), .B(n2129), .Y(n2125) );
NAND4BX1TS U1992 ( .AN(n2130), .B(n2119), .C(n2302), .D(n2306), .Y(n2122) );
NOR2X4TS U1993 ( .A(n1996), .B(Raw_mant_NRM_SWR[35]), .Y(n1934) );
INVX3TS U1994 ( .A(n2590), .Y(n3210) );
INVX3TS U1995 ( .A(n2590), .Y(n2627) );
INVX3TS U1996 ( .A(n2555), .Y(n2589) );
INVX3TS U1997 ( .A(n2555), .Y(n2585) );
INVX3TS U1998 ( .A(n2555), .Y(n2579) );
INVX4TS U1999 ( .A(n1922), .Y(n1996) );
NOR2X4TS U2000 ( .A(Raw_mant_NRM_SWR[36]), .B(n1911), .Y(n1922) );
NAND2X2TS U2001 ( .A(n1889), .B(n1916), .Y(n1911) );
AOI31X1TS U2002 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n3111), .A2(n3386), .B0(
n1993), .Y(n1995) );
NOR3X2TS U2003 ( .A(Raw_mant_NRM_SWR[40]), .B(n1875), .C(n1961), .Y(n1889)
);
NOR2X1TS U2004 ( .A(n2117), .B(exp_rslt_NRM2_EW1[5]), .Y(n2119) );
NAND3X1TS U2005 ( .A(n2216), .B(n2215), .C(n2214), .Y(n2229) );
NAND3X1TS U2006 ( .A(n2209), .B(n2208), .C(n2207), .Y(n2212) );
NAND3X1TS U2007 ( .A(n2151), .B(n2150), .C(n2149), .Y(n2159) );
NAND3BX1TS U2008 ( .AN(n2397), .B(n2390), .C(n2389), .Y(n2410) );
NAND2BX2TS U2009 ( .AN(n1849), .B(n1938), .Y(n1961) );
NOR2BX2TS U2010 ( .AN(n1962), .B(Raw_mant_NRM_SWR[43]), .Y(n1987) );
BUFX3TS U2011 ( .A(n3140), .Y(n3146) );
OAI21X1TS U2012 ( .A0(n2436), .A1(n2435), .B0(n2434), .Y(n2438) );
NOR2X2TS U2013 ( .A(Raw_mant_NRM_SWR[47]), .B(n1888), .Y(n1962) );
MX2X1TS U2014 ( .A(DMP_SFG[37]), .B(DMP_SHT2_EWSW[37]), .S0(n2858), .Y(n1408) );
MX2X1TS U2015 ( .A(DMP_SFG[39]), .B(DMP_SHT2_EWSW[39]), .S0(n3198), .Y(n1402) );
MX2X1TS U2016 ( .A(DMP_SFG[41]), .B(DMP_SHT2_EWSW[41]), .S0(n3258), .Y(n1396) );
MX2X1TS U2017 ( .A(DMP_SFG[43]), .B(DMP_SHT2_EWSW[43]), .S0(n2858), .Y(n1390) );
MX2X1TS U2018 ( .A(DMP_SFG[45]), .B(DMP_SHT2_EWSW[45]), .S0(n3258), .Y(n1384) );
MX2X1TS U2019 ( .A(DMP_SFG[47]), .B(DMP_SHT2_EWSW[47]), .S0(n3246), .Y(n1378) );
INVX4TS U2020 ( .A(n3151), .Y(n3140) );
NAND2X2TS U2021 ( .A(n3110), .B(n3111), .Y(n1888) );
OAI211XLTS U2022 ( .A0(intDY_EWSW[8]), .A1(n3349), .B0(n2374), .C0(n2377),
.Y(n2386) );
NOR2X1TS U2023 ( .A(n1804), .B(n2144), .Y(n2113) );
OAI211X1TS U2024 ( .A0(intDX_EWSW[61]), .A1(n3325), .B0(n2420), .C0(n2419),
.Y(n2421) );
NOR2XLTS U2025 ( .A(n1804), .B(n2111), .Y(n2112) );
NOR2X4TS U2026 ( .A(n1931), .B(n1933), .Y(n3111) );
OAI211X2TS U2027 ( .A0(intDY_EWSW[12]), .A1(n3327), .B0(n2384), .C0(n2358),
.Y(n2388) );
OAI211X2TS U2028 ( .A0(intDY_EWSW[28]), .A1(n3336), .B0(n2356), .C0(n2347),
.Y(n2406) );
NAND3X1TS U2029 ( .A(n3393), .B(n2418), .C(intDY_EWSW[60]), .Y(n2419) );
NAND2X1TS U2030 ( .A(n1965), .B(n3323), .Y(n1933) );
CLKINVX3TS U2031 ( .A(n2086), .Y(n2897) );
INVX1TS U2032 ( .A(n1901), .Y(n1902) );
OAI211X2TS U2033 ( .A0(intDY_EWSW[20]), .A1(n3337), .B0(n2403), .C0(n2357),
.Y(n2397) );
INVX4TS U2034 ( .A(n2258), .Y(n1805) );
INVX3TS U2035 ( .A(n2010), .Y(n3211) );
AOI211X1TS U2036 ( .A0(intDX_EWSW[52]), .A1(n3415), .B0(n2339), .C0(n2458),
.Y(n2460) );
NOR2X4TS U2037 ( .A(n2086), .B(n2144), .Y(n2106) );
NAND2BX1TS U2038 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n2349) );
NAND2X4TS U2039 ( .A(shift_value_SHT2_EWR[4]), .B(n3332), .Y(n2111) );
NAND2BX1TS U2040 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2425) );
OR2X2TS U2041 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2220) );
NAND2BX1TS U2042 ( .AN(intDY_EWSW[59]), .B(intDX_EWSW[59]), .Y(n2414) );
NAND2BX1TS U2043 ( .AN(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(n2422) );
NAND2BX1TS U2044 ( .AN(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n2420) );
NAND2BX1TS U2045 ( .AN(intDY_EWSW[51]), .B(intDX_EWSW[51]), .Y(n2463) );
NOR4X6TS U2046 ( .A(Raw_mant_NRM_SWR[1]), .B(Raw_mant_NRM_SWR[2]), .C(n1925),
.D(n3329), .Y(n1910) );
NAND2BX4TS U2047 ( .AN(Raw_mant_NRM_SWR[15]), .B(n1890), .Y(n1930) );
NOR2X4TS U2048 ( .A(n1848), .B(n1930), .Y(n1899) );
AOI21X1TS U2049 ( .A0(n3091), .A1(n3095), .B0(n2848), .Y(n2849) );
XOR2X1TS U2050 ( .A(n2844), .B(DmP_mant_SFG_SWR[20]), .Y(n2847) );
INVX2TS U2051 ( .A(n1900), .Y(n1925) );
NOR2XLTS U2052 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .Y(n1895)
);
NAND3XLTS U2053 ( .A(n1900), .B(Raw_mant_NRM_SWR[1]), .C(n3362), .Y(n1999)
);
AOI222X1TS U2054 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n2810), .B0(
Raw_mant_NRM_SWR[22]), .B1(n2639), .C0(n2803), .C1(
DmP_mant_SHT1_SW[31]), .Y(n2820) );
AOI222X1TS U2055 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n2810), .B0(
Raw_mant_NRM_SWR[11]), .B1(n2639), .C0(n2704), .C1(
DmP_mant_SHT1_SW[42]), .Y(n2785) );
AOI222X1TS U2056 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n2804), .B0(n2803), .B1(
DmP_mant_SHT1_SW[37]), .C0(n2724), .C1(n1852), .Y(n2695) );
AOI222X1TS U2057 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n2810), .B0(
Raw_mant_NRM_SWR[20]), .B1(n2804), .C0(n2803), .C1(
DmP_mant_SHT1_SW[33]), .Y(n2794) );
AOI222X1TS U2058 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n2804), .B0(n2803), .B1(
DmP_mant_SHT1_SW[35]), .C0(n2724), .C1(DmP_mant_SHT1_SW[34]), .Y(n2774) );
AOI222X1TS U2059 ( .A0(Raw_mant_NRM_SWR[43]), .A1(n2752), .B0(n2725), .B1(
DmP_mant_SHT1_SW[10]), .C0(n2750), .C1(DmP_mant_SHT1_SW[9]), .Y(n2678)
);
AOI222X1TS U2060 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2811), .B0(n2725), .B1(
n1856), .C0(n2750), .C1(DmP_mant_SHT1_SW[15]), .Y(n2747) );
AOI222X1TS U2061 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2804), .B0(n2725), .B1(
n1872), .C0(n2724), .C1(DmP_mant_SHT1_SW[44]), .Y(n2715) );
AOI222X1TS U2062 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n2804), .B0(n2803), .B1(
DmP_mant_SHT1_SW[47]), .C0(n2705), .C1(n1851), .Y(n2712) );
AOI222X1TS U2063 ( .A0(n1849), .A1(n2752), .B0(n2725), .B1(
DmP_mant_SHT1_SW[12]), .C0(n2750), .C1(DmP_mant_SHT1_SW[11]), .Y(n2675) );
AOI222X1TS U2064 ( .A0(n1875), .A1(n2811), .B0(n2803), .B1(
DmP_mant_SHT1_SW[14]), .C0(n2750), .C1(DmP_mant_SHT1_SW[13]), .Y(n2683) );
AOI222X1TS U2065 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n2804), .B0(n2751), .B1(
DmP_mant_SHT1_SW[49]), .C0(n2705), .C1(n1850), .Y(n2708) );
AOI222X1TS U2066 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n2752), .B0(
DmP_mant_SHT1_SW[50]), .B1(n2705), .C0(n2751), .C1(n1862), .Y(n2737)
);
AOI222X1TS U2067 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n2811), .B0(n2751), .B1(
DmP_mant_SHT1_SW[34]), .C0(n2724), .C1(DmP_mant_SHT1_SW[33]), .Y(n2744) );
AOI222X1TS U2068 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2811), .B0(n2751), .B1(
DmP_mant_SHT1_SW[21]), .C0(n2724), .C1(n1855), .Y(n2698) );
AOI222X1TS U2069 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n2811), .B0(n2725), .B1(
DmP_mant_SHT1_SW[32]), .C0(n2724), .C1(DmP_mant_SHT1_SW[31]), .Y(n2728) );
AOI222X1TS U2070 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[47]), .B0(n2750), .B1(
DmP_mant_SHT1_SW[5]), .C0(n2803), .C1(DmP_mant_SHT1_SW[6]), .Y(n2666)
);
AOI222X1TS U2071 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n2752), .B0(n2803), .B1(
DmP_mant_SHT1_SW[9]), .C0(n2750), .C1(DmP_mant_SHT1_SW[8]), .Y(n2757)
);
AOI222X1TS U2072 ( .A0(n1848), .A1(n2804), .B0(n2751), .B1(n1870), .C0(n2724), .C1(DmP_mant_SHT1_SW[38]), .Y(n2692) );
AOI222X1TS U2073 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n2804), .B0(n2704), .B1(
n1873), .C0(n2724), .C1(DmP_mant_SHT1_SW[42]), .Y(n2729) );
AOI222X1TS U2074 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n2804), .B0(
Raw_mant_NRM_SWR[4]), .B1(n2810), .C0(n2751), .C1(n1850), .Y(n2830) );
AOI222X1TS U2075 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2804), .B0(
Raw_mant_NRM_SWR[6]), .B1(n2810), .C0(n2725), .C1(n1851), .Y(n2786) );
AOI222X1TS U2076 ( .A0(Raw_mant_NRM_SWR[34]), .A1(n2811), .B0(n2725), .B1(
DmP_mant_SHT1_SW[19]), .C0(n2750), .C1(DmP_mant_SHT1_SW[18]), .Y(n2701) );
AOI222X1TS U2077 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n2810), .B0(
Raw_mant_NRM_SWR[13]), .B1(n2639), .C0(n2725), .C1(n1863), .Y(n2799)
);
AOI222X1TS U2078 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2811), .B0(n2725), .B1(
DmP_mant_SHT1_SW[30]), .C0(n2724), .C1(n1853), .Y(n2716) );
AOI222X1TS U2079 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n2811), .B0(n2751), .B1(
DmP_mant_SHT1_SW[28]), .C0(n2724), .C1(DmP_mant_SHT1_SW[27]), .Y(n2719) );
AOI222X1TS U2080 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2811), .B0(n2725), .B1(
DmP_mant_SHT1_SW[23]), .C0(n2724), .C1(DmP_mant_SHT1_SW[22]), .Y(n2723) );
AOI222X1TS U2081 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n2811), .B0(n2725), .B1(
DmP_mant_SHT1_SW[25]), .C0(n2724), .C1(n1854), .Y(n2741) );
AOI222X1TS U2082 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2002), .B0(
Raw_mant_NRM_SWR[31]), .B1(n2639), .C0(n2704), .C1(
DmP_mant_SHT1_SW[22]), .Y(n2827) );
AOI222X1TS U2083 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2002), .B0(
Raw_mant_NRM_SWR[33]), .B1(n2639), .C0(n2751), .C1(n1855), .Y(n2823)
);
NAND3XLTS U2084 ( .A(Raw_mant_NRM_SWR[0]), .B(n3128), .C(n2734), .Y(n2740)
);
AOI222X1TS U2085 ( .A0(Raw_mant_NRM_SWR[46]), .A1(n2811), .B0(n2751), .B1(
DmP_mant_SHT1_SW[7]), .C0(n2724), .C1(DmP_mant_SHT1_SW[6]), .Y(n2674)
);
INVX4TS U2086 ( .A(n2828), .Y(n1844) );
OAI211XLTS U2087 ( .A0(n3331), .A1(intDY_EWSW[3]), .B0(n2363), .C0(n2362),
.Y(n2366) );
NAND2BXLTS U2088 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n2375) );
NAND3XLTS U2089 ( .A(n3349), .B(n2374), .C(intDY_EWSW[8]), .Y(n2376) );
OAI21XLTS U2090 ( .A0(intDY_EWSW[15]), .A1(n3287), .B0(intDY_EWSW[14]), .Y(
n2380) );
OAI21XLTS U2091 ( .A0(intDY_EWSW[41]), .A1(n3341), .B0(intDY_EWSW[40]), .Y(
n2428) );
NAND2BXLTS U2092 ( .AN(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n2394) );
NAND2BXLTS U2093 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n2374) );
NAND2BXLTS U2094 ( .AN(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n2358) );
NAND2BXLTS U2095 ( .AN(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n2357) );
NOR2X4TS U2096 ( .A(Raw_mant_NRM_SWR[26]), .B(n3113), .Y(n1919) );
NAND3XLTS U2097 ( .A(n3340), .B(n2440), .C(intDY_EWSW[36]), .Y(n2441) );
OAI21XLTS U2098 ( .A0(intDY_EWSW[43]), .A1(n3288), .B0(intDY_EWSW[42]), .Y(
n2429) );
AOI2BB2XLTS U2099 ( .B0(intDY_EWSW[53]), .B1(n3428), .A0N(intDX_EWSW[52]),
.A1N(n2457), .Y(n2459) );
OAI21XLTS U2100 ( .A0(intDY_EWSW[53]), .A1(n3428), .B0(intDY_EWSW[52]), .Y(
n2457) );
OAI21XLTS U2101 ( .A0(intDY_EWSW[55]), .A1(n3429), .B0(intDY_EWSW[54]), .Y(
n2468) );
OAI21XLTS U2102 ( .A0(intDY_EWSW[31]), .A1(n3290), .B0(intDY_EWSW[30]), .Y(
n2352) );
NAND2BXLTS U2103 ( .AN(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n2347) );
OAI21XLTS U2104 ( .A0(n3417), .A1(n2220), .B0(n2210), .Y(n2211) );
OAI21XLTS U2105 ( .A0(n3416), .A1(n2220), .B0(n2219), .Y(n2221) );
OAI21XLTS U2106 ( .A0(n3418), .A1(n2220), .B0(n2104), .Y(n2105) );
INVX2TS U2107 ( .A(n1965), .Y(n1967) );
INVX2TS U2108 ( .A(n1963), .Y(n1969) );
AOI2BB1XLTS U2109 ( .A0N(n1989), .A1N(Raw_mant_NRM_SWR[52]), .B0(
Raw_mant_NRM_SWR[53]), .Y(n1990) );
NAND4XLTS U2110 ( .A(n3296), .B(n3366), .C(Raw_mant_NRM_SWR[37]), .D(n1988),
.Y(n1991) );
OAI211XLTS U2111 ( .A0(n3333), .A1(intDY_EWSW[33]), .B0(n2344), .C0(n2446),
.Y(n2345) );
NAND2BXLTS U2112 ( .AN(intDY_EWSW[32]), .B(intDX_EWSW[32]), .Y(n2344) );
NOR2XLTS U2113 ( .A(n2412), .B(intDX_EWSW[56]), .Y(n2413) );
NAND4XLTS U2114 ( .A(n2133), .B(exp_rslt_NRM2_EW1[5]), .C(
exp_rslt_NRM2_EW1[4]), .D(n2132), .Y(n2134) );
NAND4BXLTS U2115 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n2116), .C(n2314), .D(n2319), .Y(n2117) );
OAI211XLTS U2116 ( .A0(n2952), .A1(n2939), .B0(n2183), .C0(n2182), .Y(n2184)
);
OAI211XLTS U2117 ( .A0(n2967), .A1(n2111), .B0(n2912), .C0(n2911), .Y(n2913)
);
INVX2TS U2118 ( .A(n1931), .Y(n1932) );
AOI211X1TS U2119 ( .A0(shift_value_SHT2_EWR[5]), .A1(n2875), .B0(n2874),
.C0(n2873), .Y(n3233) );
AO22XLTS U2120 ( .A0(Data_array_SWR[5]), .A1(n2106), .B0(Data_array_SWR[3]),
.B1(n2910), .Y(n2874) );
BUFX4TS U2121 ( .A(left_right_SHT2), .Y(n3241) );
AOI222X1TS U2122 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n2804), .B0(
Raw_mant_NRM_SWR[16]), .B1(n2810), .C0(n2704), .C1(n1852), .Y(n2777)
);
AOI222X1TS U2123 ( .A0(Raw_mant_NRM_SWR[40]), .A1(n2752), .B0(n2751), .B1(
DmP_mant_SHT1_SW[13]), .C0(n2750), .C1(DmP_mant_SHT1_SW[12]), .Y(n2763) );
AOI222X1TS U2124 ( .A0(n1849), .A1(n2002), .B0(Raw_mant_NRM_SWR[42]), .B1(
n2639), .C0(n2725), .C1(DmP_mant_SHT1_SW[11]), .Y(n2760) );
XOR2X1TS U2125 ( .A(n2844), .B(DmP_mant_SFG_SWR[21]), .Y(n3080) );
OAI21X1TS U2126 ( .A0(n3045), .A1(n2850), .B0(n2849), .Y(n3079) );
NAND2X1TS U2127 ( .A(n3092), .B(n3095), .Y(n2850) );
INVX2TS U2128 ( .A(n3099), .Y(n3050) );
INVX2TS U2129 ( .A(n3051), .Y(n3053) );
AOI222X1TS U2130 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n2804), .B0(n1848), .B1(
n2810), .C0(n2803), .C1(DmP_mant_SHT1_SW[38]), .Y(n2796) );
AOI222X1TS U2131 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n2810), .B0(
Raw_mant_NRM_SWR[29]), .B1(n2804), .C0(n2751), .C1(n1854), .Y(n2802)
);
CLKAND2X2TS U2132 ( .A(n2839), .B(DMP_SFG[12]), .Y(n3104) );
INVX2TS U2133 ( .A(n3049), .Y(n3100) );
AOI222X1TS U2134 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n2002), .B0(
Raw_mant_NRM_SWR[26]), .B1(n2639), .C0(n2803), .C1(
DmP_mant_SHT1_SW[27]), .Y(n2812) );
OAI21X1TS U2135 ( .A0(n3085), .A1(n3082), .B0(n3086), .Y(n3091) );
NOR2X1TS U2136 ( .A(n3046), .B(n3085), .Y(n3092) );
INVX2TS U2137 ( .A(n3082), .Y(n3083) );
INVX2TS U2138 ( .A(n3045), .Y(n3093) );
INVX2TS U2139 ( .A(n3046), .Y(n3084) );
OAI211X1TS U2140 ( .A0(n2958), .A1(n3238), .B0(n2925), .C0(n2924), .Y(n3254)
);
AO22XLTS U2141 ( .A0(n2143), .A1(n2961), .B0(n2963), .B1(n2962), .Y(n2204)
);
AO22XLTS U2142 ( .A0(n2954), .A1(n2143), .B0(n2955), .B1(n2962), .Y(n2160)
);
CLKAND2X2TS U2143 ( .A(n3425), .B(n2128), .Y(n2136) );
CLKINVX3TS U2144 ( .A(n3218), .Y(n2274) );
OAI211X1TS U2145 ( .A0(n2946), .A1(n2966), .B0(n2945), .C0(n2944), .Y(n3255)
);
OAI211X1TS U2146 ( .A0(n2958), .A1(n2966), .B0(n2957), .C0(n2956), .Y(n3253)
);
NAND4XLTS U2147 ( .A(n3123), .B(n3122), .C(n3121), .D(n3120), .Y(n3125) );
OAI211XLTS U2148 ( .A0(n3236), .A1(n2866), .B0(n2099), .C0(n2098), .Y(n2100)
);
OAI211XLTS U2149 ( .A0(n3231), .A1(n2866), .B0(n2088), .C0(n2087), .Y(n2089)
);
NAND4BXLTS U2150 ( .AN(n1904), .B(n1948), .C(n1999), .D(n1903), .Y(n1905) );
OAI31X1TS U2151 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n1848), .A2(n1902), .B0(
n1998), .Y(n1903) );
INVX4TS U2152 ( .A(n3218), .Y(n3016) );
BUFX4TS U2153 ( .A(n2010), .Y(n2549) );
AOI222X1TS U2154 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[50]), .B0(n2750), .B1(
DmP_mant_SHT1_SW[2]), .C0(n2751), .C1(DmP_mant_SHT1_SW[3]), .Y(n2665)
);
AOI222X1TS U2155 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2810), .B0(
Raw_mant_NRM_SWR[38]), .B1(n2639), .C0(n2803), .C1(
DmP_mant_SHT1_SW[15]), .Y(n2764) );
BUFX3TS U2156 ( .A(n3430), .Y(n3208) );
OAI21XLTS U2157 ( .A0(n2298), .A1(n2919), .B0(n2297), .Y(n1035) );
OAI211XLTS U2158 ( .A0(n2834), .A1(n2816), .B0(n2809), .C0(n2808), .Y(n1661)
);
MX2X1TS U2159 ( .A(Raw_mant_NRM_SWR[54]), .B(n2989), .S0(n3016), .Y(n1144)
);
MX2X1TS U2160 ( .A(Raw_mant_NRM_SWR[40]), .B(n3010), .S0(n3016), .Y(n1158)
);
MX2X1TS U2161 ( .A(Raw_mant_NRM_SWR[51]), .B(n2983), .S0(n3016), .Y(n1147)
);
MX2X1TS U2162 ( .A(n1849), .B(n3007), .S0(n3016), .Y(n1157) );
AO22XLTS U2163 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[44]), .B0(n3207),
.B1(DmP_mant_SHT1_SW[44]), .Y(n1221) );
AO22XLTS U2164 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[50]), .B0(n3208),
.B1(DmP_mant_SHT1_SW[50]), .Y(n1209) );
AO22XLTS U2165 ( .A0(n3144), .A1(intDX_EWSW[62]), .B0(n3145), .B1(Data_X[62]), .Y(n1732) );
AO22XLTS U2166 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[42]), .B0(n3207),
.B1(DmP_mant_SHT1_SW[42]), .Y(n1225) );
AO22XLTS U2167 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[47]), .B0(n3207),
.B1(DmP_mant_SHT1_SW[47]), .Y(n1215) );
MX2X1TS U2168 ( .A(Raw_mant_NRM_SWR[31]), .B(n3038), .S0(n3065), .Y(n1167)
);
AO22XLTS U2169 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[37]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[37]), .Y(n1235) );
AO22XLTS U2170 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[35]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[35]), .Y(n1239) );
AO22XLTS U2171 ( .A0(n3200), .A1(DmP_EXP_EWSW[19]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1271) );
AO22XLTS U2172 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[49]), .B0(n3207),
.B1(DmP_mant_SHT1_SW[49]), .Y(n1211) );
AO22XLTS U2173 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[30]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[30]), .Y(n1249) );
AO22XLTS U2174 ( .A0(n3204), .A1(DmP_EXP_EWSW[21]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[21]), .Y(n1267) );
OAI211XLTS U2175 ( .A0(n2678), .A1(n2753), .B0(n2677), .C0(n2676), .Y(n1621)
);
MX2X1TS U2176 ( .A(n1875), .B(n3013), .S0(n3016), .Y(n1159) );
AO22XLTS U2177 ( .A0(n3158), .A1(Data_Y[59]), .B0(n3159), .B1(intDY_EWSW[59]), .Y(n1669) );
AO22XLTS U2178 ( .A0(n3143), .A1(Data_X[0]), .B0(n3157), .B1(intDX_EWSW[0]),
.Y(n1794) );
AO22XLTS U2179 ( .A0(n3146), .A1(Data_X[6]), .B0(n3142), .B1(intDX_EWSW[6]),
.Y(n1788) );
MX2X1TS U2180 ( .A(Raw_mant_NRM_SWR[33]), .B(n3032), .S0(n3065), .Y(n1165)
);
AO22XLTS U2181 ( .A0(n3140), .A1(Data_X[39]), .B0(n3147), .B1(intDX_EWSW[39]), .Y(n1755) );
AO22XLTS U2182 ( .A0(n3146), .A1(Data_X[9]), .B0(n3142), .B1(intDX_EWSW[9]),
.Y(n1785) );
AO22XLTS U2183 ( .A0(n3143), .A1(Data_X[4]), .B0(n3150), .B1(intDX_EWSW[4]),
.Y(n1790) );
MX2X1TS U2184 ( .A(n3268), .B(DmP_mant_SFG_SWR[48]), .S0(n2968), .Y(n1022)
);
MX2X1TS U2185 ( .A(n3274), .B(DmP_mant_SFG_SWR[49]), .S0(n2968), .Y(n1021)
);
MX2X1TS U2186 ( .A(n3270), .B(DmP_mant_SFG_SWR[50]), .S0(n2968), .Y(n1020)
);
MX2X1TS U2187 ( .A(n3276), .B(DmP_mant_SFG_SWR[51]), .S0(n3259), .Y(n1019)
);
AO22XLTS U2188 ( .A0(n3160), .A1(Data_Y[63]), .B0(n3159), .B1(intDY_EWSW[63]), .Y(n1665) );
AO22XLTS U2189 ( .A0(n3159), .A1(intDY_EWSW[5]), .B0(n3146), .B1(Data_Y[5]),
.Y(n1723) );
AO22XLTS U2190 ( .A0(n3159), .A1(intDY_EWSW[7]), .B0(n3146), .B1(Data_Y[7]),
.Y(n1721) );
MX2X1TS U2191 ( .A(Raw_mant_NRM_SWR[37]), .B(n3017), .S0(n3016), .Y(n1161)
);
AO22XLTS U2192 ( .A0(n3259), .A1(DmP_mant_SFG_SWR[2]), .B0(n3258), .B1(n3275), .Y(n1134) );
AO22XLTS U2193 ( .A0(n3259), .A1(DmP_mant_SFG_SWR[5]), .B0(n3185), .B1(n3273), .Y(n1132) );
AO22XLTS U2194 ( .A0(n3259), .A1(DmP_mant_SFG_SWR[4]), .B0(n3185), .B1(n3269), .Y(n1127) );
AO22XLTS U2195 ( .A0(n3259), .A1(DmP_mant_SFG_SWR[6]), .B0(n3217), .B1(n3267), .Y(n1124) );
AO22XLTS U2196 ( .A0(n3259), .A1(DmP_mant_SFG_SWR[11]), .B0(n3217), .B1(
n3243), .Y(n1117) );
AO22XLTS U2197 ( .A0(n3204), .A1(DmP_EXP_EWSW[0]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1309) );
AO22XLTS U2198 ( .A0(n3200), .A1(DmP_EXP_EWSW[1]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1307) );
AO22XLTS U2199 ( .A0(n3204), .A1(DmP_EXP_EWSW[2]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1305) );
AO22XLTS U2200 ( .A0(n3200), .A1(DmP_EXP_EWSW[5]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1299) );
AO22XLTS U2201 ( .A0(n3204), .A1(DmP_EXP_EWSW[4]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1301) );
AO22XLTS U2202 ( .A0(n3200), .A1(DmP_EXP_EWSW[3]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[3]), .Y(n1303) );
AO22XLTS U2203 ( .A0(n3204), .A1(DmP_EXP_EWSW[9]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1291) );
AO22XLTS U2204 ( .A0(n3200), .A1(DmP_EXP_EWSW[25]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[25]), .Y(n1259) );
AO22XLTS U2205 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[34]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[34]), .Y(n1241) );
AOI222X1TS U2206 ( .A0(n2567), .A1(intDX_EWSW[52]), .B0(DmP_EXP_EWSW[52]),
.B1(n2629), .C0(intDY_EWSW[52]), .C1(n2555), .Y(n2630) );
AO22XLTS U2207 ( .A0(n3200), .A1(DmP_EXP_EWSW[11]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1287) );
AO22XLTS U2208 ( .A0(n3200), .A1(DmP_EXP_EWSW[15]), .B0(n3220), .B1(
DmP_mant_SHT1_SW[15]), .Y(n1279) );
AO22XLTS U2209 ( .A0(n3204), .A1(DmP_EXP_EWSW[18]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1273) );
AO22XLTS U2210 ( .A0(n3200), .A1(DmP_EXP_EWSW[22]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1265) );
AO22XLTS U2211 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[27]), .B0(n3205),
.B1(DmP_mant_SHT1_SW[27]), .Y(n1255) );
AO22XLTS U2212 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[31]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[31]), .Y(n1247) );
AO22XLTS U2213 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[33]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[33]), .Y(n1243) );
AO22XLTS U2214 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[38]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[38]), .Y(n1233) );
AO22XLTS U2215 ( .A0(n3156), .A1(Data_X[63]), .B0(n3157), .B1(intDX_EWSW[63]), .Y(n1731) );
MX2X1TS U2216 ( .A(Raw_mant_NRM_SWR[36]), .B(n3023), .S0(n3065), .Y(n1162)
);
AO22XLTS U2217 ( .A0(n3200), .A1(DmP_EXP_EWSW[17]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[17]), .Y(n1275) );
AO22XLTS U2218 ( .A0(n3204), .A1(DmP_EXP_EWSW[26]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[26]), .Y(n1257) );
AO22XLTS U2219 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[28]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[28]), .Y(n1253) );
AO22XLTS U2220 ( .A0(n3204), .A1(DmP_EXP_EWSW[23]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[23]), .Y(n1263) );
AO22XLTS U2221 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[32]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[32]), .Y(n1245) );
MX2X1TS U2222 ( .A(Raw_mant_NRM_SWR[32]), .B(n3035), .S0(n3065), .Y(n1166)
);
AO22XLTS U2223 ( .A0(n3158), .A1(Data_Y[62]), .B0(n3157), .B1(intDY_EWSW[62]), .Y(n1666) );
AO22XLTS U2224 ( .A0(n3156), .A1(Data_Y[58]), .B0(n3159), .B1(intDY_EWSW[58]), .Y(n1670) );
AO22XLTS U2225 ( .A0(n3158), .A1(Data_Y[60]), .B0(n3159), .B1(intDY_EWSW[60]), .Y(n1668) );
MX2X1TS U2226 ( .A(Raw_mant_NRM_SWR[34]), .B(n3029), .S0(n3065), .Y(n1164)
);
AO22XLTS U2227 ( .A0(n3140), .A1(Data_X[2]), .B0(n3150), .B1(intDX_EWSW[2]),
.Y(n1792) );
AO22XLTS U2228 ( .A0(n3152), .A1(Data_X[24]), .B0(n3141), .B1(intDX_EWSW[24]), .Y(n1770) );
AO22XLTS U2229 ( .A0(n3140), .A1(Data_X[7]), .B0(n3142), .B1(intDX_EWSW[7]),
.Y(n1787) );
AO22XLTS U2230 ( .A0(n3143), .A1(Data_X[32]), .B0(n3148), .B1(intDX_EWSW[32]), .Y(n1762) );
AO22XLTS U2231 ( .A0(n3156), .A1(Data_X[1]), .B0(n3150), .B1(intDX_EWSW[1]),
.Y(n1793) );
AO22XLTS U2232 ( .A0(n3156), .A1(Data_X[10]), .B0(n3142), .B1(intDX_EWSW[10]), .Y(n1784) );
AO22XLTS U2233 ( .A0(n3140), .A1(Data_X[40]), .B0(n3144), .B1(intDX_EWSW[40]), .Y(n1754) );
AO22XLTS U2234 ( .A0(n3152), .A1(Data_X[16]), .B0(n3142), .B1(intDX_EWSW[16]), .Y(n1778) );
AO22XLTS U2235 ( .A0(n3143), .A1(Data_X[48]), .B0(n3157), .B1(intDX_EWSW[48]), .Y(n1746) );
AO22XLTS U2236 ( .A0(n3143), .A1(Data_X[47]), .B0(n3157), .B1(intDX_EWSW[47]), .Y(n1747) );
AO22XLTS U2237 ( .A0(n3145), .A1(Data_X[44]), .B0(n3157), .B1(intDX_EWSW[44]), .Y(n1750) );
OAI211XLTS U2238 ( .A0(n2770), .A1(n2822), .B0(n2680), .C0(n2679), .Y(n1637)
);
AO22XLTS U2239 ( .A0(n3156), .A1(Data_X[52]), .B0(n3157), .B1(intDX_EWSW[52]), .Y(n1742) );
AO22XLTS U2240 ( .A0(n3140), .A1(Data_X[37]), .B0(n3148), .B1(intDX_EWSW[37]), .Y(n1757) );
AO22XLTS U2241 ( .A0(n3140), .A1(Data_X[38]), .B0(n3147), .B1(intDX_EWSW[38]), .Y(n1756) );
AOI22X1TS U2242 ( .A0(n2795), .A1(Data_array_SWR[17]), .B0(n1844), .B1(
DmP_mant_SHT1_SW[19]), .Y(n2825) );
AO22XLTS U2243 ( .A0(n3143), .A1(Data_X[5]), .B0(n3142), .B1(intDX_EWSW[5]),
.Y(n1789) );
MX2X1TS U2244 ( .A(Raw_mant_NRM_SWR[44]), .B(n2971), .S0(n3065), .Y(n1154)
);
MX2X1TS U2245 ( .A(Raw_mant_NRM_SWR[42]), .B(n3004), .S0(n3016), .Y(n1156)
);
MX2X1TS U2246 ( .A(Raw_mant_NRM_SWR[38]), .B(n3020), .S0(n3065), .Y(n1160)
);
MX2X1TS U2247 ( .A(Raw_mant_NRM_SWR[35]), .B(n3026), .S0(n3065), .Y(n1163)
);
AO22XLTS U2248 ( .A0(n3144), .A1(intDX_EWSW[56]), .B0(n3149), .B1(Data_X[56]), .Y(n1738) );
AO22XLTS U2249 ( .A0(n3155), .A1(intDY_EWSW[37]), .B0(n3149), .B1(Data_Y[37]), .Y(n1691) );
AO22XLTS U2250 ( .A0(n3155), .A1(intDY_EWSW[38]), .B0(n3149), .B1(Data_Y[38]), .Y(n1690) );
AO22XLTS U2251 ( .A0(n3144), .A1(intDX_EWSW[58]), .B0(n3145), .B1(Data_X[58]), .Y(n1736) );
AO22XLTS U2252 ( .A0(n3159), .A1(intDY_EWSW[1]), .B0(n3145), .B1(Data_Y[1]),
.Y(n1727) );
AO22XLTS U2253 ( .A0(n3147), .A1(intDY_EWSW[16]), .B0(n3145), .B1(Data_Y[16]), .Y(n1712) );
AO22XLTS U2254 ( .A0(n3147), .A1(intDX_EWSW[53]), .B0(n3145), .B1(Data_X[53]), .Y(n1741) );
AO22XLTS U2255 ( .A0(n3147), .A1(intDX_EWSW[55]), .B0(n3145), .B1(Data_X[55]), .Y(n1739) );
AO22XLTS U2256 ( .A0(n3149), .A1(Data_X[13]), .B0(n3142), .B1(intDX_EWSW[13]), .Y(n1781) );
AO22XLTS U2257 ( .A0(n3149), .A1(Data_X[41]), .B0(n3147), .B1(intDX_EWSW[41]), .Y(n1753) );
AO22XLTS U2258 ( .A0(n3149), .A1(Data_X[43]), .B0(n3142), .B1(intDX_EWSW[43]), .Y(n1751) );
AO22XLTS U2259 ( .A0(n3149), .A1(Data_X[45]), .B0(n3157), .B1(intDX_EWSW[45]), .Y(n1749) );
AO22XLTS U2260 ( .A0(n3145), .A1(Data_X[12]), .B0(n3142), .B1(intDX_EWSW[12]), .Y(n1782) );
AO22XLTS U2261 ( .A0(n3145), .A1(Data_X[42]), .B0(n3148), .B1(intDX_EWSW[42]), .Y(n1752) );
AO22XLTS U2262 ( .A0(n3144), .A1(intDY_EWSW[10]), .B0(n3139), .B1(Data_Y[10]), .Y(n1718) );
OAI211XLTS U2263 ( .A0(n2316), .A1(n3136), .B0(n3214), .C0(n2315), .Y(n1590)
);
OAI211XLTS U2264 ( .A0(n2306), .A1(n2318), .B0(n3214), .C0(n2305), .Y(n1592)
);
OAI211XLTS U2265 ( .A0(n2310), .A1(n3278), .B0(n3214), .C0(n2309), .Y(n1593)
);
OAI211XLTS U2266 ( .A0(n2319), .A1(n3272), .B0(n3214), .C0(n2317), .Y(n1596)
);
AO22XLTS U2267 ( .A0(n3280), .A1(n3279), .B0(final_result_ieee[51]), .B1(
n3272), .Y(n1056) );
AO22XLTS U2268 ( .A0(n3280), .A1(n3277), .B0(final_result_ieee[50]), .B1(
n3136), .Y(n1057) );
AO22XLTS U2269 ( .A0(n3280), .A1(n3276), .B0(final_result_ieee[49]), .B1(
n3278), .Y(n1058) );
AO22XLTS U2270 ( .A0(n3280), .A1(n3275), .B0(final_result_ieee[0]), .B1(
n2318), .Y(n1059) );
AO22XLTS U2271 ( .A0(n3280), .A1(n3274), .B0(final_result_ieee[47]), .B1(
n3219), .Y(n1060) );
AO22XLTS U2272 ( .A0(n3280), .A1(n3273), .B0(final_result_ieee[3]), .B1(
n3272), .Y(n1065) );
AO22XLTS U2273 ( .A0(n3280), .A1(n3271), .B0(final_result_ieee[1]), .B1(
n3136), .Y(n1066) );
AO22XLTS U2274 ( .A0(n3280), .A1(n3270), .B0(final_result_ieee[48]), .B1(
n3278), .Y(n1067) );
AO22XLTS U2275 ( .A0(n3280), .A1(n3269), .B0(final_result_ieee[2]), .B1(
n2318), .Y(n1068) );
AO22XLTS U2276 ( .A0(n3280), .A1(n3268), .B0(final_result_ieee[46]), .B1(
n3272), .Y(n1075) );
AO22XLTS U2277 ( .A0(n3280), .A1(n3267), .B0(final_result_ieee[4]), .B1(
n3219), .Y(n1076) );
AO22XLTS U2278 ( .A0(n3280), .A1(n3266), .B0(final_result_ieee[45]), .B1(
n3272), .Y(n1077) );
AO22XLTS U2279 ( .A0(n3280), .A1(n3265), .B0(final_result_ieee[5]), .B1(
n3278), .Y(n1078) );
AO22XLTS U2280 ( .A0(n3280), .A1(n3264), .B0(final_result_ieee[44]), .B1(
n3136), .Y(n1079) );
AO22XLTS U2281 ( .A0(n3263), .A1(n3242), .B0(final_result_ieee[6]), .B1(
n2318), .Y(n1080) );
AO22XLTS U2282 ( .A0(n3263), .A1(n3262), .B0(final_result_ieee[29]), .B1(
n2318), .Y(n1082) );
AO22XLTS U2283 ( .A0(n3263), .A1(n3261), .B0(final_result_ieee[21]), .B1(
n3219), .Y(n1083) );
AO22XLTS U2284 ( .A0(n3263), .A1(n2920), .B0(final_result_ieee[41]), .B1(
n3278), .Y(n1085) );
AO22XLTS U2285 ( .A0(n3263), .A1(n3243), .B0(final_result_ieee[9]), .B1(
n3219), .Y(n1086) );
AO22XLTS U2286 ( .A0(n3263), .A1(n3260), .B0(final_result_ieee[25]), .B1(
n3272), .Y(n1089) );
AO22XLTS U2287 ( .A0(n3263), .A1(n2917), .B0(final_result_ieee[43]), .B1(
n3219), .Y(n1090) );
AO22XLTS U2288 ( .A0(n3263), .A1(n3251), .B0(final_result_ieee[7]), .B1(
n3136), .Y(n1091) );
AO22XLTS U2289 ( .A0(n3263), .A1(n2918), .B0(final_result_ieee[42]), .B1(
n3278), .Y(n1094) );
AO22XLTS U2290 ( .A0(n3263), .A1(n3257), .B0(final_result_ieee[8]), .B1(
n2318), .Y(n1095) );
AO22XLTS U2291 ( .A0(n3263), .A1(n3256), .B0(final_result_ieee[26]), .B1(
n3136), .Y(n1098) );
AO22XLTS U2292 ( .A0(n3263), .A1(n3255), .B0(final_result_ieee[24]), .B1(
n3278), .Y(n1099) );
AO22XLTS U2293 ( .A0(n3263), .A1(n3254), .B0(final_result_ieee[28]), .B1(
n2318), .Y(n1102) );
AO22XLTS U2294 ( .A0(n3263), .A1(n3253), .B0(final_result_ieee[22]), .B1(
n3219), .Y(n1103) );
AO22XLTS U2295 ( .A0(n3263), .A1(n3250), .B0(final_result_ieee[27]), .B1(
n3272), .Y(n1107) );
AO22XLTS U2296 ( .A0(n3249), .A1(n3248), .B0(final_result_ieee[23]), .B1(
n3136), .Y(n1108) );
AO22XLTS U2297 ( .A0(n3280), .A1(n3129), .B0(final_result_ieee[62]), .B1(
n3272), .Y(n1588) );
AO22XLTS U2298 ( .A0(n3148), .A1(intDY_EWSW[27]), .B0(n3149), .B1(Data_Y[27]), .Y(n1701) );
AO22XLTS U2299 ( .A0(n3159), .A1(intDY_EWSW[3]), .B0(n3140), .B1(Data_Y[3]),
.Y(n1725) );
AO22XLTS U2300 ( .A0(n3144), .A1(intDX_EWSW[59]), .B0(n3145), .B1(Data_X[59]), .Y(n1735) );
AO22XLTS U2301 ( .A0(n3148), .A1(intDY_EWSW[31]), .B0(n3149), .B1(Data_Y[31]), .Y(n1697) );
AO22XLTS U2302 ( .A0(n3159), .A1(intDY_EWSW[6]), .B0(n3146), .B1(Data_Y[6]),
.Y(n1722) );
OAI222X1TS U2303 ( .A0(n3210), .A1(n3428), .B0(n3316), .B1(n3211), .C0(n3284), .C1(n3213), .Y(n1534) );
AO22XLTS U2304 ( .A0(n3144), .A1(intDX_EWSW[54]), .B0(n3145), .B1(Data_X[54]), .Y(n1740) );
AO22XLTS U2305 ( .A0(n3159), .A1(intDY_EWSW[9]), .B0(n3146), .B1(Data_Y[9]),
.Y(n1719) );
AO22XLTS U2306 ( .A0(n3147), .A1(intDY_EWSW[13]), .B0(n3146), .B1(Data_Y[13]), .Y(n1715) );
AO22XLTS U2307 ( .A0(n3144), .A1(intDY_EWSW[2]), .B0(n3149), .B1(Data_Y[2]),
.Y(n1726) );
AO22XLTS U2308 ( .A0(n3159), .A1(intDY_EWSW[8]), .B0(n3146), .B1(Data_Y[8]),
.Y(n1720) );
AO22XLTS U2309 ( .A0(n3144), .A1(intDY_EWSW[12]), .B0(n3146), .B1(Data_Y[12]), .Y(n1716) );
AO22XLTS U2310 ( .A0(n3150), .A1(intDY_EWSW[32]), .B0(n3149), .B1(Data_Y[32]), .Y(n1696) );
AO22XLTS U2311 ( .A0(n3144), .A1(intDX_EWSW[61]), .B0(n3145), .B1(Data_X[61]), .Y(n1733) );
AO22XLTS U2312 ( .A0(n3148), .A1(intDY_EWSW[33]), .B0(n3149), .B1(Data_Y[33]), .Y(n1695) );
AO22XLTS U2313 ( .A0(n3155), .A1(intDY_EWSW[34]), .B0(n3149), .B1(Data_Y[34]), .Y(n1694) );
AO22XLTS U2314 ( .A0(n3150), .A1(intDY_EWSW[36]), .B0(n3149), .B1(Data_Y[36]), .Y(n1692) );
AO22XLTS U2315 ( .A0(n3148), .A1(intDY_EWSW[30]), .B0(n3149), .B1(Data_Y[30]), .Y(n1698) );
AO22XLTS U2316 ( .A0(n3147), .A1(intDX_EWSW[49]), .B0(n3145), .B1(Data_X[49]), .Y(n1745) );
AO22XLTS U2317 ( .A0(n3259), .A1(n1858), .B0(n2858), .B1(n3271), .Y(n1129)
);
MX2X1TS U2318 ( .A(Raw_mant_NRM_SWR[48]), .B(n2995), .S0(n3016), .Y(n1150)
);
MX2X1TS U2319 ( .A(Raw_mant_NRM_SWR[47]), .B(n2998), .S0(n3016), .Y(n1151)
);
MX2X1TS U2320 ( .A(Raw_mant_NRM_SWR[46]), .B(n2974), .S0(n3225), .Y(n1152)
);
MX2X1TS U2321 ( .A(Raw_mant_NRM_SWR[45]), .B(n2977), .S0(n3016), .Y(n1153)
);
MX2X1TS U2322 ( .A(Raw_mant_NRM_SWR[43]), .B(n3001), .S0(n3016), .Y(n1155)
);
OAI222X1TS U2323 ( .A0(n3213), .A1(n3285), .B0(n3212), .B1(n3211), .C0(n3281), .C1(n3210), .Y(n1202) );
AO22XLTS U2324 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[51]), .B0(n3208),
.B1(n1862), .Y(n1207) );
OAI21XLTS U2325 ( .A0(n3406), .A1(n3210), .B0(n2603), .Y(n1208) );
OAI21XLTS U2326 ( .A0(n3388), .A1(n3210), .B0(n2601), .Y(n1210) );
OAI21XLTS U2327 ( .A0(n3409), .A1(n3210), .B0(n2599), .Y(n1212) );
AO22XLTS U2328 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[48]), .B0(n3207),
.B1(n1850), .Y(n1213) );
OAI21XLTS U2329 ( .A0(n3381), .A1(n3210), .B0(n2598), .Y(n1214) );
OAI21XLTS U2330 ( .A0(n3308), .A1(n2579), .B0(n2566), .Y(n1216) );
AO22XLTS U2331 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[46]), .B0(n3207),
.B1(n1851), .Y(n1217) );
OAI21XLTS U2332 ( .A0(n3405), .A1(n2579), .B0(n2519), .Y(n1218) );
AO22XLTS U2333 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[45]), .B0(n3207),
.B1(n1872), .Y(n1219) );
OAI21XLTS U2334 ( .A0(n3398), .A1(n2579), .B0(n2524), .Y(n1220) );
OAI21XLTS U2335 ( .A0(n3404), .A1(n2579), .B0(n2570), .Y(n1222) );
AO22XLTS U2336 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[43]), .B0(n3207),
.B1(n1873), .Y(n1223) );
OAI21XLTS U2337 ( .A0(n3311), .A1(n2579), .B0(n2520), .Y(n1224) );
OAI21XLTS U2338 ( .A0(n3403), .A1(n2579), .B0(n2523), .Y(n1226) );
AO22XLTS U2339 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[41]), .B0(n3207),
.B1(n1874), .Y(n1227) );
OAI21XLTS U2340 ( .A0(n3310), .A1(n2579), .B0(n2527), .Y(n1228) );
AO22XLTS U2341 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[40]), .B0(n3207),
.B1(n1863), .Y(n1229) );
OAI21XLTS U2342 ( .A0(n3402), .A1(n2579), .B0(n2565), .Y(n1230) );
AO22XLTS U2343 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[39]), .B0(n3207),
.B1(n1870), .Y(n1231) );
OAI21XLTS U2344 ( .A0(n3397), .A1(n2579), .B0(n2578), .Y(n1232) );
OAI21XLTS U2345 ( .A0(n3422), .A1(n2579), .B0(n2569), .Y(n1234) );
OAI21XLTS U2346 ( .A0(n3396), .A1(n2579), .B0(n2568), .Y(n1236) );
AO22XLTS U2347 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[36]), .B0(n3206),
.B1(n1852), .Y(n1237) );
OAI21XLTS U2348 ( .A0(n3401), .A1(n2579), .B0(n2525), .Y(n1238) );
OAI21XLTS U2349 ( .A0(n3309), .A1(n2579), .B0(n2526), .Y(n1240) );
OAI21XLTS U2350 ( .A0(n3400), .A1(n2585), .B0(n2521), .Y(n1242) );
OAI21XLTS U2351 ( .A0(n3399), .A1(n2585), .B0(n2522), .Y(n1244) );
OAI21XLTS U2352 ( .A0(n3380), .A1(n2585), .B0(n2564), .Y(n1246) );
OAI21XLTS U2353 ( .A0(n3314), .A1(n2585), .B0(n2512), .Y(n1248) );
OAI21XLTS U2354 ( .A0(n3412), .A1(n2585), .B0(n2513), .Y(n1250) );
AO22XLTS U2355 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[29]), .B0(n3206),
.B1(n1853), .Y(n1251) );
OAI21XLTS U2356 ( .A0(n3302), .A1(n2585), .B0(n2515), .Y(n1252) );
OAI21XLTS U2357 ( .A0(n3379), .A1(n2585), .B0(n2518), .Y(n1254) );
OAI21XLTS U2358 ( .A0(n3300), .A1(n2585), .B0(n2514), .Y(n1256) );
OAI21XLTS U2359 ( .A0(n3378), .A1(n2585), .B0(n2517), .Y(n1258) );
OAI21XLTS U2360 ( .A0(n3299), .A1(n2585), .B0(n2516), .Y(n1260) );
AO22XLTS U2361 ( .A0(n3200), .A1(DmP_EXP_EWSW[24]), .B0(n3205), .B1(n1854),
.Y(n1261) );
OAI21XLTS U2362 ( .A0(n3377), .A1(n2585), .B0(n2574), .Y(n1262) );
OAI21XLTS U2363 ( .A0(n3313), .A1(n2585), .B0(n2561), .Y(n1264) );
OAI21XLTS U2364 ( .A0(n3411), .A1(n2627), .B0(n2615), .Y(n1266) );
OAI21XLTS U2365 ( .A0(n3371), .A1(n2627), .B0(n2612), .Y(n1268) );
AO22XLTS U2366 ( .A0(n3204), .A1(DmP_EXP_EWSW[20]), .B0(n3205), .B1(n1855),
.Y(n1269) );
OAI21XLTS U2367 ( .A0(n3376), .A1(n2627), .B0(n2611), .Y(n1270) );
OAI21XLTS U2368 ( .A0(n3298), .A1(n2627), .B0(n2610), .Y(n1272) );
OAI21XLTS U2369 ( .A0(n3375), .A1(n2627), .B0(n2621), .Y(n1274) );
OAI21XLTS U2370 ( .A0(n3297), .A1(n2627), .B0(n2609), .Y(n1276) );
OAI21XLTS U2371 ( .A0(n3382), .A1(n2627), .B0(n2624), .Y(n1278) );
OAI21XLTS U2372 ( .A0(n3312), .A1(n2627), .B0(n2614), .Y(n1280) );
OAI21XLTS U2373 ( .A0(n3410), .A1(n2627), .B0(n2608), .Y(n1282) );
OAI21XLTS U2374 ( .A0(n3370), .A1(n2627), .B0(n2613), .Y(n1284) );
OAI21XLTS U2375 ( .A0(n3374), .A1(n2627), .B0(n2616), .Y(n1286) );
OAI21XLTS U2376 ( .A0(n3305), .A1(n2627), .B0(n2617), .Y(n1288) );
OAI21XLTS U2377 ( .A0(n3369), .A1(n2627), .B0(n2620), .Y(n1290) );
OAI21XLTS U2378 ( .A0(n3368), .A1(n2589), .B0(n2575), .Y(n1292) );
OAI21XLTS U2379 ( .A0(n3373), .A1(n2589), .B0(n2562), .Y(n1294) );
OAI21XLTS U2380 ( .A0(n2582), .A1(n2589), .B0(n2581), .Y(n1296) );
OAI21XLTS U2381 ( .A0(n3315), .A1(n2589), .B0(n2573), .Y(n1298) );
OAI21XLTS U2382 ( .A0(n2606), .A1(n2589), .B0(n2586), .Y(n1300) );
OAI21XLTS U2383 ( .A0(n3303), .A1(n2589), .B0(n2580), .Y(n1302) );
OAI21XLTS U2384 ( .A0(n3372), .A1(n2589), .B0(n2576), .Y(n1306) );
OAI21XLTS U2385 ( .A0(n3421), .A1(n2589), .B0(n2583), .Y(n1308) );
OAI21XLTS U2386 ( .A0(n1867), .A1(n2589), .B0(n2588), .Y(n1310) );
OAI21XLTS U2387 ( .A0(n3391), .A1(n2589), .B0(n2572), .Y(n1526) );
OAI21XLTS U2388 ( .A0(n3393), .A1(n2627), .B0(n2626), .Y(n1527) );
OAI21XLTS U2389 ( .A0(n3307), .A1(n2589), .B0(n2587), .Y(n1528) );
OAI21XLTS U2390 ( .A0(n3392), .A1(n3210), .B0(n2600), .Y(n1529) );
OAI21XLTS U2391 ( .A0(n3389), .A1(n3213), .B0(n2607), .Y(n1530) );
OAI21XLTS U2392 ( .A0(n3406), .A1(n3213), .B0(n2510), .Y(n1536) );
OAI21XLTS U2393 ( .A0(n3388), .A1(n3213), .B0(n2509), .Y(n1537) );
OAI21XLTS U2394 ( .A0(n3409), .A1(n2503), .B0(n2490), .Y(n1538) );
OAI21XLTS U2395 ( .A0(n3381), .A1(n2503), .B0(n2488), .Y(n1539) );
OAI21XLTS U2396 ( .A0(n3308), .A1(n2503), .B0(n2496), .Y(n1540) );
OAI21XLTS U2397 ( .A0(n3405), .A1(n2503), .B0(n2501), .Y(n1541) );
OAI21XLTS U2398 ( .A0(n3404), .A1(n2503), .B0(n2491), .Y(n1543) );
OAI21XLTS U2399 ( .A0(n3311), .A1(n2503), .B0(n2497), .Y(n1544) );
OAI21XLTS U2400 ( .A0(n3403), .A1(n2503), .B0(n2502), .Y(n1545) );
OAI21XLTS U2401 ( .A0(n3310), .A1(n2503), .B0(n2500), .Y(n1546) );
OAI21XLTS U2402 ( .A0(n3402), .A1(n2503), .B0(n2498), .Y(n1547) );
OAI21XLTS U2403 ( .A0(n3397), .A1(n2552), .B0(n2545), .Y(n1548) );
OAI21XLTS U2404 ( .A0(n3422), .A1(n2552), .B0(n2529), .Y(n1549) );
OAI21XLTS U2405 ( .A0(n3396), .A1(n2552), .B0(n2533), .Y(n1550) );
OAI21XLTS U2406 ( .A0(n3401), .A1(n2552), .B0(n2544), .Y(n1551) );
OAI21XLTS U2407 ( .A0(n3309), .A1(n2552), .B0(n2546), .Y(n1552) );
OAI21XLTS U2408 ( .A0(n3400), .A1(n2552), .B0(n2551), .Y(n1553) );
OAI21XLTS U2409 ( .A0(n3399), .A1(n2552), .B0(n2548), .Y(n1554) );
OAI21XLTS U2410 ( .A0(n3380), .A1(n2552), .B0(n2543), .Y(n1555) );
OAI21XLTS U2411 ( .A0(n3412), .A1(n2605), .B0(n2532), .Y(n1557) );
OAI21XLTS U2412 ( .A0(n3302), .A1(n2552), .B0(n2542), .Y(n1558) );
OAI21XLTS U2413 ( .A0(n3379), .A1(n3213), .B0(n2507), .Y(n1559) );
OAI21XLTS U2414 ( .A0(n3300), .A1(n2503), .B0(n2495), .Y(n1560) );
OAI21XLTS U2415 ( .A0(n3378), .A1(n2552), .B0(n2535), .Y(n1561) );
OAI21XLTS U2416 ( .A0(n3299), .A1(n3213), .B0(n2508), .Y(n1562) );
OAI21XLTS U2417 ( .A0(n3377), .A1(n2503), .B0(n2493), .Y(n1563) );
OAI21XLTS U2418 ( .A0(n3313), .A1(n2503), .B0(n2489), .Y(n1564) );
OAI21XLTS U2419 ( .A0(n3411), .A1(n2552), .B0(n2528), .Y(n1565) );
OAI21XLTS U2420 ( .A0(n3371), .A1(n2503), .B0(n2492), .Y(n1566) );
OAI21XLTS U2421 ( .A0(n3376), .A1(n3213), .B0(n2506), .Y(n1567) );
OAI21XLTS U2422 ( .A0(n3298), .A1(n3213), .B0(n2505), .Y(n1568) );
OAI21XLTS U2423 ( .A0(n3375), .A1(n2605), .B0(n2538), .Y(n1569) );
OAI21XLTS U2424 ( .A0(n3382), .A1(n2560), .B0(n2487), .Y(n1571) );
OAI21XLTS U2425 ( .A0(n3312), .A1(n2605), .B0(n2531), .Y(n1572) );
OAI21XLTS U2426 ( .A0(n3410), .A1(n2560), .B0(n2483), .Y(n1573) );
OAI21XLTS U2427 ( .A0(n3370), .A1(n2605), .B0(n2536), .Y(n1574) );
OAI21XLTS U2428 ( .A0(n3374), .A1(n3213), .B0(n2504), .Y(n1575) );
OAI21XLTS U2429 ( .A0(n3305), .A1(n2552), .B0(n2539), .Y(n1576) );
OAI21XLTS U2430 ( .A0(n3369), .A1(n2560), .B0(n2594), .Y(n1577) );
OAI21XLTS U2431 ( .A0(n3368), .A1(n2605), .B0(n2592), .Y(n1578) );
OAI21XLTS U2432 ( .A0(n3373), .A1(n2605), .B0(n2537), .Y(n1579) );
OAI21XLTS U2433 ( .A0(n2582), .A1(n2605), .B0(n2553), .Y(n1580) );
OAI21XLTS U2434 ( .A0(n3315), .A1(n2605), .B0(n2591), .Y(n1581) );
OAI21XLTS U2435 ( .A0(n2606), .A1(n2605), .B0(n2604), .Y(n1582) );
OAI21XLTS U2436 ( .A0(n3303), .A1(n2605), .B0(n2596), .Y(n1583) );
OAI21XLTS U2437 ( .A0(n3372), .A1(n2605), .B0(n2595), .Y(n1585) );
OAI21XLTS U2438 ( .A0(n3421), .A1(n2605), .B0(n2597), .Y(n1586) );
OAI21XLTS U2439 ( .A0(n1867), .A1(n3213), .B0(n2511), .Y(n1587) );
AO22XLTS U2440 ( .A0(n3186), .A1(n3165), .B0(n3430), .B1(n1859), .Y(n1604)
);
AO22XLTS U2441 ( .A0(n3144), .A1(n1868), .B0(n3145), .B1(Data_Y[0]), .Y(
n1728) );
OA21XLTS U2442 ( .A0(n3417), .A1(n2907), .B0(n2185), .Y(n1808) );
BUFX3TS U2443 ( .A(n2826), .Y(n2711) );
OR2X2TS U2444 ( .A(n2826), .B(n2736), .Y(n1815) );
NOR2X6TS U2445 ( .A(n3241), .B(n2111), .Y(n2143) );
OAI221X1TS U2446 ( .A0(n3300), .A1(intDX_EWSW[27]), .B0(n3378), .B1(
intDX_EWSW[26]), .C0(n2045), .Y(n2048) );
OAI21XLTS U2447 ( .A0(n2292), .A1(n2919), .B0(n2291), .Y(n1032) );
OAI21XLTS U2448 ( .A0(n2290), .A1(n2919), .B0(n2289), .Y(n1033) );
OAI21XLTS U2449 ( .A0(n2288), .A1(n2919), .B0(n2287), .Y(n1034) );
OAI21XLTS U2450 ( .A0(n2294), .A1(n2919), .B0(n2293), .Y(n1051) );
OAI21XLTS U2451 ( .A0(n2280), .A1(n2919), .B0(n2279), .Y(n1052) );
OAI21XLTS U2452 ( .A0(n2286), .A1(n2919), .B0(n2285), .Y(n1054) );
OAI21XLTS U2453 ( .A0(n2282), .A1(n2919), .B0(n2281), .Y(n1055) );
OAI21XLTS U2454 ( .A0(n2296), .A1(n2919), .B0(n2295), .Y(n1143) );
OAI21X1TS U2455 ( .A0(n3416), .A1(n2907), .B0(n2906), .Y(n2908) );
CLKINVX3TS U2456 ( .A(rst), .Y(n3504) );
NOR4X2TS U2457 ( .A(n2340), .B(n2412), .C(n2424), .D(n2416), .Y(n2469) );
BUFX4TS U2458 ( .A(n3494), .Y(n3461) );
BUFX4TS U2459 ( .A(n3496), .Y(n3462) );
BUFX4TS U2460 ( .A(n3494), .Y(n3499) );
BUFX4TS U2461 ( .A(n3496), .Y(n3460) );
BUFX4TS U2462 ( .A(n3477), .Y(n3456) );
BUFX4TS U2463 ( .A(n3485), .Y(n3453) );
BUFX4TS U2464 ( .A(n3483), .Y(n3454) );
BUFX3TS U2465 ( .A(n2008), .Y(n2009) );
BUFX4TS U2466 ( .A(n3491), .Y(n3473) );
BUFX4TS U2467 ( .A(n3491), .Y(n3472) );
AOI222X1TS U2468 ( .A0(n1935), .A1(Raw_mant_NRM_SWR[32]), .B0(
Raw_mant_NRM_SWR[34]), .B1(n1934), .C0(n1933), .C1(n1932), .Y(n1936)
);
BUFX4TS U2469 ( .A(n3474), .Y(n3487) );
BUFX4TS U2470 ( .A(n3474), .Y(n3465) );
BUFX4TS U2471 ( .A(n3498), .Y(n3455) );
BUFX4TS U2472 ( .A(n2009), .Y(n3468) );
BUFX4TS U2473 ( .A(n2009), .Y(n3470) );
BUFX3TS U2474 ( .A(n2009), .Y(n3494) );
BUFX4TS U2475 ( .A(n2009), .Y(n3457) );
BUFX4TS U2476 ( .A(n3208), .Y(n3191) );
BUFX4TS U2477 ( .A(n3140), .Y(n3153) );
BUFX4TS U2478 ( .A(n3201), .Y(n3203) );
INVX4TS U2479 ( .A(n3505), .Y(n1847) );
AOI21X2TS U2480 ( .A0(n1881), .A1(n2909), .B0(n2190), .Y(n2946) );
OAI21X1TS U2481 ( .A0(n3418), .A1(n2907), .B0(n2189), .Y(n2190) );
BUFX4TS U2482 ( .A(n3207), .Y(n3206) );
BUFX4TS U2483 ( .A(n3478), .Y(n3445) );
BUFX4TS U2484 ( .A(n3140), .Y(n3152) );
BUFX4TS U2485 ( .A(n3452), .Y(n3444) );
BUFX4TS U2486 ( .A(n2649), .Y(n2833) );
BUFX4TS U2487 ( .A(n3441), .Y(n3443) );
BUFX4TS U2488 ( .A(n3501), .Y(n3442) );
BUFX4TS U2489 ( .A(n3500), .Y(n3446) );
BUFX4TS U2490 ( .A(n3500), .Y(n3447) );
BUFX4TS U2491 ( .A(n3450), .Y(n3440) );
BUFX4TS U2492 ( .A(n3445), .Y(n3498) );
BUFX4TS U2493 ( .A(n3495), .Y(n3477) );
BUFX4TS U2494 ( .A(n3495), .Y(n3478) );
BUFX4TS U2495 ( .A(n3160), .Y(n3156) );
BUFX4TS U2496 ( .A(n3139), .Y(n3143) );
BUFX3TS U2497 ( .A(n3504), .Y(n2008) );
BUFX4TS U2498 ( .A(n3504), .Y(n3491) );
AOI211X1TS U2499 ( .A0(shift_value_SHT2_EWR[5]), .A1(n2882), .B0(n2881),
.C0(n2880), .Y(n3235) );
OAI22X2TS U2500 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2235), .B0(n1826), .B1(
n2225), .Y(n2882) );
AOI211X1TS U2501 ( .A0(shift_value_SHT2_EWR[5]), .A1(n2903), .B0(n2902),
.C0(n2901), .Y(n3237) );
OAI22X2TS U2502 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2152), .B0(n3408), .B1(
n2225), .Y(n2903) );
BUFX4TS U2503 ( .A(n3426), .Y(n3219) );
BUFX4TS U2504 ( .A(n3499), .Y(n3441) );
BUFX3TS U2505 ( .A(n3462), .Y(n3501) );
BUFX4TS U2506 ( .A(n3474), .Y(n3449) );
BUFX4TS U2507 ( .A(n3501), .Y(n3450) );
BUFX4TS U2508 ( .A(n3458), .Y(n3448) );
BUFX4TS U2509 ( .A(n2009), .Y(n3483) );
OAI22X2TS U2510 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2226), .B0(n3395), .B1(
n2225), .Y(n2875) );
BUFX4TS U2511 ( .A(n2008), .Y(n3485) );
INVX2TS U2512 ( .A(n1816), .Y(n1849) );
OAI222X1TS U2513 ( .A0(n2560), .A1(n3320), .B0(n1821), .B1(n3211), .C0(n3282), .C1(n3210), .Y(n1204) );
OAI222X1TS U2514 ( .A0(n3210), .A1(n3285), .B0(n3321), .B1(n3211), .C0(n3281), .C1(n3213), .Y(n1531) );
OAI222X1TS U2515 ( .A0(n3210), .A1(n3429), .B0(n3319), .B1(n3211), .C0(n3283), .C1(n3213), .Y(n1532) );
OAI222X1TS U2516 ( .A0(n3210), .A1(n3320), .B0(n3317), .B1(n3211), .C0(n3282), .C1(n3213), .Y(n1533) );
INVX2TS U2517 ( .A(n1836), .Y(n1850) );
INVX2TS U2518 ( .A(n1835), .Y(n1851) );
INVX2TS U2519 ( .A(n1814), .Y(n1852) );
INVX2TS U2520 ( .A(n1813), .Y(n1853) );
INVX2TS U2521 ( .A(n1812), .Y(n1854) );
INVX2TS U2522 ( .A(n1834), .Y(n1855) );
INVX2TS U2523 ( .A(n1838), .Y(n1856) );
INVX2TS U2524 ( .A(n1842), .Y(n1857) );
INVX2TS U2525 ( .A(n1841), .Y(n1858) );
INVX2TS U2526 ( .A(n1822), .Y(n1859) );
INVX2TS U2527 ( .A(n1839), .Y(n1860) );
INVX2TS U2528 ( .A(n1840), .Y(n1861) );
INVX2TS U2529 ( .A(n1833), .Y(n1862) );
BUFX4TS U2530 ( .A(n3426), .Y(n3272) );
BUFX4TS U2531 ( .A(n3426), .Y(n3278) );
BUFX4TS U2532 ( .A(n3426), .Y(n3136) );
BUFX4TS U2533 ( .A(n3426), .Y(n2318) );
AOI222X1TS U2534 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2810), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2639), .C0(n2704), .C1(DmP_mant_SHT1_SW[44]), .Y(n2782) );
INVX2TS U2535 ( .A(n1832), .Y(n1863) );
INVX2TS U2536 ( .A(n1837), .Y(n1864) );
INVX2TS U2537 ( .A(n1827), .Y(n1865) );
INVX2TS U2538 ( .A(n1828), .Y(n1866) );
INVX2TS U2539 ( .A(intDY_EWSW[0]), .Y(n1867) );
INVX2TS U2540 ( .A(n1867), .Y(n1868) );
BUFX4TS U2541 ( .A(n2704), .Y(n2751) );
BUFX4TS U2542 ( .A(n2704), .Y(n2725) );
BUFX3TS U2543 ( .A(n2704), .Y(n2803) );
OAI21XLTS U2544 ( .A0(n2558), .A1(n2629), .B0(n2589), .Y(n2556) );
BUFX4TS U2545 ( .A(n2010), .Y(n2629) );
OAI221X1TS U2546 ( .A0(n3306), .A1(intDY_EWSW[62]), .B0(n3391), .B1(
intDY_EWSW[61]), .C0(n2018), .Y(n2021) );
OAI21XLTS U2547 ( .A0(n3306), .A1(n2589), .B0(n2571), .Y(n1525) );
AOI222X1TS U2548 ( .A0(n2169), .A1(n1804), .B0(n2943), .B1(n2962), .C0(n2942), .C1(n2143), .Y(n3244) );
AOI222X1TS U2549 ( .A0(n2170), .A1(n1804), .B0(n2949), .B1(n2962), .C0(n2948), .C1(n2143), .Y(n3245) );
AOI222X4TS U2550 ( .A0(n2243), .A1(left_right_SHT2), .B0(n2242), .B1(n2143),
.C0(n2241), .C1(n2929), .Y(n2325) );
BUFX4TS U2551 ( .A(n2560), .Y(n2503) );
CLKINVX3TS U2552 ( .A(n3208), .Y(n3187) );
CLKINVX3TS U2553 ( .A(n3208), .Y(n3186) );
BUFX4TS U2554 ( .A(n1887), .Y(n2577) );
BUFX4TS U2555 ( .A(n2549), .Y(n2622) );
AOI222X4TS U2556 ( .A0(n2170), .A1(left_right_SHT2), .B0(n2949), .B1(n2929),
.C0(n2948), .C1(n2960), .Y(n2335) );
AOI222X4TS U2557 ( .A0(n2169), .A1(left_right_SHT2), .B0(n2943), .B1(n2929),
.C0(n2942), .C1(n2960), .Y(n2338) );
AOI222X1TS U2558 ( .A0(n2161), .A1(left_right_SHT2), .B0(n2955), .B1(n2929),
.C0(n2954), .C1(n2960), .Y(n2486) );
AOI222X1TS U2559 ( .A0(n2231), .A1(n3241), .B0(n2963), .B1(n2929), .C0(n2961), .C1(n2960), .Y(n2300) );
BUFX4TS U2560 ( .A(n2112), .Y(n2960) );
NAND2X1TS U2561 ( .A(n3241), .B(n2910), .Y(n3232) );
AOI222X4TS U2562 ( .A0(n2146), .A1(n3241), .B0(n2147), .B1(n2143), .C0(n2148), .C1(n2929), .Y(n2327) );
AOI222X4TS U2563 ( .A0(n2245), .A1(n3241), .B0(n2244), .B1(n2143), .C0(n2869), .C1(n2929), .Y(n2333) );
BUFX3TS U2564 ( .A(n2856), .Y(n2858) );
CLKBUFX3TS U2565 ( .A(n2856), .Y(n2883) );
AOI2BB2X1TS U2566 ( .B0(n1845), .B1(DmP_mant_SHT1_SW[21]), .A0N(n2823),
.A1N(n2822), .Y(n2824) );
OAI211XLTS U2567 ( .A0(n2774), .A1(n2649), .B0(n2773), .C0(n2772), .Y(n1644)
);
BUFX4TS U2568 ( .A(n2815), .Y(n3162) );
BUFX4TS U2569 ( .A(n2815), .Y(n2795) );
INVX2TS U2570 ( .A(n1809), .Y(n1869) );
INVX3TS U2571 ( .A(n3258), .Y(n2336) );
INVX3TS U2572 ( .A(n2962), .Y(n3238) );
INVX3TS U2573 ( .A(n2929), .Y(n2966) );
AOI22X1TS U2574 ( .A0(n2815), .A1(Data_array_SWR[27]), .B0(
Raw_mant_NRM_SWR[17]), .B1(n2771), .Y(n2773) );
INVX3TS U2575 ( .A(n3221), .Y(n3202) );
INVX3TS U2576 ( .A(n3221), .Y(n3200) );
INVX3TS U2577 ( .A(n3221), .Y(n3204) );
OAI2BB2XLTS U2578 ( .B0(n1954), .B1(n3344), .A0N(n1953), .A1N(
Raw_mant_NRM_SWR[6]), .Y(n1955) );
INVX2TS U2579 ( .A(n1830), .Y(n1870) );
INVX2TS U2580 ( .A(n1819), .Y(n1871) );
INVX2TS U2581 ( .A(n1829), .Y(n1872) );
INVX2TS U2582 ( .A(n1831), .Y(n1873) );
INVX2TS U2583 ( .A(n1811), .Y(n1874) );
INVX2TS U2584 ( .A(n1807), .Y(n1875) );
AOI22X2TS U2585 ( .A0(Data_array_SWR[42]), .A1(n2887), .B0(
Data_array_SWR[38]), .B1(n2896), .Y(n3236) );
INVX2TS U2586 ( .A(n1810), .Y(n1876) );
INVX2TS U2587 ( .A(n1806), .Y(n1877) );
INVX2TS U2588 ( .A(n1824), .Y(n1878) );
AOI32X1TS U2589 ( .A0(n3392), .A1(n2414), .A2(intDY_EWSW[58]), .B0(
intDY_EWSW[59]), .B1(n3307), .Y(n2415) );
OAI221XLTS U2590 ( .A0(n3393), .A1(intDY_EWSW[60]), .B0(n3307), .B1(
intDY_EWSW[59]), .C0(n2019), .Y(n2020) );
OAI221XLTS U2591 ( .A0(n1867), .A1(intDX_EWSW[0]), .B0(n3373), .B1(
intDX_EWSW[8]), .C0(n2067), .Y(n2068) );
OAI221X1TS U2592 ( .A0(n3413), .A1(intDX_EWSW[7]), .B0(n3315), .B1(
intDX_EWSW[6]), .C0(n2367), .Y(n2071) );
OAI211X1TS U2593 ( .A0(n2789), .A1(n2826), .B0(n2749), .C0(n2748), .Y(n1627)
);
INVX2TS U2594 ( .A(n1817), .Y(n1879) );
AOI221X1TS U2595 ( .A0(n3422), .A1(intDX_EWSW[38]), .B0(intDX_EWSW[39]),
.B1(n3397), .C0(n2038), .Y(n2041) );
OAI221XLTS U2596 ( .A0(n3368), .A1(intDX_EWSW[9]), .B0(n3382), .B1(
intDX_EWSW[16]), .C0(n2060), .Y(n2061) );
AOI222X1TS U2597 ( .A0(intDX_EWSW[4]), .A1(n3303), .B0(intDX_EWSW[5]), .B1(
n2606), .C0(n2366), .C1(n2365), .Y(n2368) );
OAI221X1TS U2598 ( .A0(n3370), .A1(intDX_EWSW[13]), .B0(n3303), .B1(
intDX_EWSW[4]), .C0(n2058), .Y(n2063) );
INVX2TS U2599 ( .A(n1825), .Y(n1880) );
INVX2TS U2600 ( .A(n1818), .Y(n1881) );
OAI21XLTS U2601 ( .A0(n2484), .A1(n2329), .B0(n2328), .Y(n1048) );
OAI21XLTS U2602 ( .A0(n2484), .A1(n2327), .B0(n2326), .Y(n1038) );
OAI21XLTS U2603 ( .A0(n2484), .A1(n2325), .B0(n2324), .Y(n1037) );
OAI21XLTS U2604 ( .A0(n2484), .A1(n2333), .B0(n2332), .Y(n1036) );
OAI21XLTS U2605 ( .A0(n2919), .A1(n2300), .B0(n2299), .Y(n1031) );
OAI21XLTS U2606 ( .A0(n2919), .A1(n2486), .B0(n2485), .Y(n1030) );
OAI21XLTS U2607 ( .A0(n2919), .A1(n2335), .B0(n2334), .Y(n1029) );
OAI21XLTS U2608 ( .A0(n2919), .A1(n2338), .B0(n2337), .Y(n1028) );
XOR2X1TS U2609 ( .A(n2844), .B(DmP_mant_SFG_SWR[16]), .Y(n2840) );
XOR2X1TS U2610 ( .A(n2844), .B(DmP_mant_SFG_SWR[17]), .Y(n2841) );
XOR2X1TS U2611 ( .A(n2844), .B(DmP_mant_SFG_SWR[18]), .Y(n2845) );
OAI21XLTS U2612 ( .A0(n2484), .A1(n2323), .B0(n2322), .Y(n1050) );
OAI21XLTS U2613 ( .A0(n2484), .A1(n2331), .B0(n2330), .Y(n1049) );
OAI21XLTS U2614 ( .A0(n3389), .A1(n2585), .B0(n2584), .Y(n1201) );
OAI31XLTS U2615 ( .A0(n2559), .A1(n2558), .A2(n2560), .B0(n2557), .Y(n1522)
);
CLKINVX1TS U2616 ( .A(DmP_EXP_EWSW[56]), .Y(n3212) );
BUFX4TS U2617 ( .A(n3146), .Y(n3149) );
NAND2X1TS U2618 ( .A(n1882), .B(n1883), .Y(n2958) );
NAND2X1TS U2619 ( .A(n1808), .B(n2086), .Y(n1882) );
NAND2X1TS U2620 ( .A(n1808), .B(n1823), .Y(n1883) );
OAI211XLTS U2621 ( .A0(n2958), .A1(n2111), .B0(n2187), .C0(n2186), .Y(n2188)
);
XNOR2X2TS U2622 ( .A(DMP_exp_NRM2_EW[10]), .B(n2127), .Y(n3129) );
OAI211XLTS U2623 ( .A0(n2669), .A1(n2822), .B0(n2668), .C0(n2667), .Y(n1615)
);
BUFX4TS U2624 ( .A(n3497), .Y(n3490) );
BUFX4TS U2625 ( .A(n3493), .Y(n3459) );
BUFX4TS U2626 ( .A(n3458), .Y(n3489) );
BUFX3TS U2627 ( .A(n3494), .Y(n3493) );
NAND2X1TS U2628 ( .A(n2847), .B(DMP_SFG[18]), .Y(n3094) );
OAI222X4TS U2629 ( .A0(n3213), .A1(n3428), .B0(n3318), .B1(n3211), .C0(n3284), .C1(n3210), .Y(n1205) );
BUFX4TS U2630 ( .A(n2560), .Y(n3213) );
NOR2X1TS U2631 ( .A(n2840), .B(DMP_SFG[14]), .Y(n3049) );
NAND2X1TS U2632 ( .A(n2840), .B(DMP_SFG[14]), .Y(n3099) );
NOR2X1TS U2633 ( .A(n2845), .B(DMP_SFG[16]), .Y(n3046) );
NAND2X1TS U2634 ( .A(n2845), .B(DMP_SFG[16]), .Y(n3082) );
OAI211XLTS U2635 ( .A0(n2308), .A1(n3219), .B0(n3214), .C0(n2307), .Y(n1598)
);
OAI211XLTS U2636 ( .A0(n2314), .A1(n2318), .B0(n3214), .C0(n2313), .Y(n1595)
);
OAI211XLTS U2637 ( .A0(n2321), .A1(n3278), .B0(n3214), .C0(n2320), .Y(n1597)
);
OAI211XLTS U2638 ( .A0(n2302), .A1(n3219), .B0(n3214), .C0(n2301), .Y(n1591)
);
OAI211XLTS U2639 ( .A0(n2304), .A1(n3136), .B0(n3214), .C0(n2303), .Y(n1594)
);
NAND2X4TS U2640 ( .A(n2126), .B(Shift_reg_FLAGS_7[0]), .Y(n3214) );
OAI211XLTS U2641 ( .A0(n3234), .A1(n2866), .B0(n2865), .C0(n2864), .Y(n2867)
);
AOI22X2TS U2642 ( .A0(Data_array_SWR[44]), .A1(n2887), .B0(
Data_array_SWR[40]), .B1(n2896), .Y(n3234) );
INVX3TS U2643 ( .A(n2220), .Y(n2896) );
BUFX4TS U2644 ( .A(n2897), .Y(n2887) );
BUFX4TS U2645 ( .A(OP_FLAG_SFG), .Y(n2844) );
OAI211XLTS U2646 ( .A0(n2674), .A1(n2822), .B0(n2673), .C0(n2672), .Y(n1618)
);
INVX3TS U2647 ( .A(n2858), .Y(n3224) );
BUFX3TS U2648 ( .A(n2856), .Y(n3185) );
INVX3TS U2649 ( .A(n3218), .Y(n3225) );
AOI22X2TS U2650 ( .A0(Data_array_SWR[39]), .A1(n2905), .B0(
Data_array_SWR[43]), .B1(n2887), .Y(n3231) );
NAND2X2TS U2651 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2907) );
INVX2TS U2652 ( .A(n1884), .Y(n1885) );
NAND2X4TS U2653 ( .A(Shift_reg_FLAGS_7[1]), .B(n2636), .Y(n2837) );
AOI22X2TS U2654 ( .A0(Data_array_SWR[37]), .A1(n2905), .B0(
Data_array_SWR[41]), .B1(n2887), .Y(n3239) );
NOR2X2TS U2655 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3390), .Y(n3130) );
OAI221X1TS U2656 ( .A0(n3392), .A1(intDY_EWSW[58]), .B0(n3389), .B1(
intDX_EWSW[57]), .C0(n2016), .Y(n2023) );
NOR2X2TS U2657 ( .A(Raw_mant_NRM_SWR[18]), .B(Raw_mant_NRM_SWR[17]), .Y(
n1901) );
OAI211XLTS U2658 ( .A0(n2767), .A1(n2822), .B0(n2685), .C0(n2684), .Y(n1628)
);
OAI221X1TS U2659 ( .A0(n3301), .A1(intDX_EWSW[3]), .B0(n3372), .B1(
intDX_EWSW[2]), .C0(n2066), .Y(n2069) );
NOR2XLTS U2660 ( .A(n2404), .B(intDX_EWSW[24]), .Y(n2348) );
OAI221X1TS U2661 ( .A0(n3297), .A1(intDX_EWSW[17]), .B0(n3377), .B1(
intDX_EWSW[24]), .C0(n2053), .Y(n2054) );
OAI221X1TS U2662 ( .A0(n3299), .A1(intDX_EWSW[25]), .B0(n3380), .B1(
intDX_EWSW[32]), .C0(n2046), .Y(n2047) );
NOR2XLTS U2663 ( .A(n2372), .B(intDX_EWSW[10]), .Y(n2373) );
OAI221X1TS U2664 ( .A0(n3369), .A1(intDX_EWSW[10]), .B0(n3374), .B1(
intDX_EWSW[12]), .C0(n2059), .Y(n2062) );
NOR2XLTS U2665 ( .A(n2392), .B(intDX_EWSW[16]), .Y(n2393) );
NOR2XLTS U2666 ( .A(n2461), .B(intDX_EWSW[48]), .Y(n2462) );
OAI221X1TS U2667 ( .A0(n3371), .A1(intDX_EWSW[21]), .B0(n3381), .B1(
intDX_EWSW[48]), .C0(n2051), .Y(n2056) );
AOI211X2TS U2668 ( .A0(intDX_EWSW[44]), .A1(n3404), .B0(n2426), .C0(n2435),
.Y(n2433) );
AOI21X2TS U2669 ( .A0(Data_array_SWR[24]), .A1(n2909), .B0(n2181), .Y(n2952)
);
AOI21X2TS U2670 ( .A0(Data_array_SWR[22]), .A1(n2909), .B0(n2908), .Y(n2967)
);
AOI222X1TS U2671 ( .A0(n2555), .A1(intDX_EWSW[52]), .B0(DMP_EXP_EWSW[52]),
.B1(n2629), .C0(intDY_EWSW[52]), .C1(n2567), .Y(n2628) );
OAI21XLTS U2672 ( .A0(intDX_EWSW[37]), .A1(n3396), .B0(n2441), .Y(n2450) );
OAI221XLTS U2673 ( .A0(n2606), .A1(intDX_EWSW[5]), .B0(n3379), .B1(
intDX_EWSW[28]), .C0(n2065), .Y(n2070) );
NOR3X6TS U2674 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[20]), .C(
n1945), .Y(n1998) );
NAND2X2TS U2675 ( .A(shift_value_SHT2_EWR[4]), .B(n2180), .Y(n2225) );
OAI22X2TS U2676 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2240), .B0(n3407), .B1(
n2225), .Y(n2893) );
INVX2TS U2677 ( .A(Shift_reg_FLAGS_7_6), .Y(n2010) );
OAI21XLTS U2678 ( .A0(intDX_EWSW[1]), .A1(n3421), .B0(intDX_EWSW[0]), .Y(
n2361) );
NOR2XLTS U2679 ( .A(n2131), .B(exp_rslt_NRM2_EW1[1]), .Y(n2116) );
NOR2XLTS U2680 ( .A(n2426), .B(intDX_EWSW[44]), .Y(n2427) );
NOR2XLTS U2681 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[45]), .Y(
n1964) );
OAI21XLTS U2682 ( .A0(intDY_EWSW[29]), .A1(n3342), .B0(intDY_EWSW[28]), .Y(
n2346) );
XOR2X1TS U2683 ( .A(n2844), .B(DmP_mant_SFG_SWR[19]), .Y(n2846) );
INVX2TS U2684 ( .A(n3085), .Y(n3087) );
OAI211XLTS U2685 ( .A0(n2946), .A1(n2939), .B0(n2192), .C0(n2191), .Y(n2193)
);
OR2X1TS U2686 ( .A(n3431), .B(n2844), .Y(n2258) );
OR2X1TS U2687 ( .A(n2847), .B(DMP_SFG[18]), .Y(n3095) );
OAI21XLTS U2688 ( .A0(DmP_EXP_EWSW[53]), .A1(n3316), .B0(n3168), .Y(n3166)
);
OAI211XLTS U2689 ( .A0(n2312), .A1(n2318), .B0(n3214), .C0(n2311), .Y(n1589)
);
OAI211XLTS U2690 ( .A0(DmP_mant_SFG_SWR[11]), .A1(n2277), .B0(n2250), .C0(
n2249), .Y(n1116) );
OAI211XLTS U2691 ( .A0(DmP_mant_SFG_SWR[12]), .A1(n2277), .B0(n2268), .C0(
n2267), .Y(n1112) );
OAI21XLTS U2692 ( .A0(n2284), .A1(n2919), .B0(n2283), .Y(n1053) );
OAI211XLTS U2693 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n2277), .B0(n2264), .C0(
n2263), .Y(n1123) );
OAI21XLTS U2694 ( .A0(n3301), .A1(n2589), .B0(n2563), .Y(n1304) );
OAI21XLTS U2695 ( .A0(n3398), .A1(n2503), .B0(n2499), .Y(n1542) );
OAI21XLTS U2696 ( .A0(n3314), .A1(n2552), .B0(n2534), .Y(n1556) );
OAI21XLTS U2697 ( .A0(n3297), .A1(n2503), .B0(n2494), .Y(n1570) );
OAI21XLTS U2698 ( .A0(n3301), .A1(n2605), .B0(n2540), .Y(n1584) );
OAI211XLTS U2699 ( .A0(n2665), .A1(n2822), .B0(n2664), .C0(n2663), .Y(n1614)
);
INVX2TS U2700 ( .A(n3505), .Y(n3189) );
BUFX3TS U2701 ( .A(n3189), .Y(n3194) );
INVX4TS U2702 ( .A(n3194), .Y(n3223) );
BUFX3TS U2703 ( .A(n2659), .Y(n2815) );
NOR2X2TS U2704 ( .A(Shift_reg_FLAGS_7[1]), .B(n3189), .Y(n3161) );
AOI22X1TS U2705 ( .A0(n2659), .A1(shift_value_SHT2_EWR[5]), .B0(n3161), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n1906) );
NOR3X2TS U2706 ( .A(Raw_mant_NRM_SWR[44]), .B(Raw_mant_NRM_SWR[46]), .C(
Raw_mant_NRM_SWR[45]), .Y(n3110) );
NOR2X2TS U2707 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .Y(
n1963) );
NOR2X2TS U2708 ( .A(Raw_mant_NRM_SWR[52]), .B(Raw_mant_NRM_SWR[51]), .Y(
n1966) );
NAND2X2TS U2709 ( .A(n1963), .B(n1966), .Y(n1931) );
NOR2BX4TS U2710 ( .AN(n1987), .B(Raw_mant_NRM_SWR[42]), .Y(n1938) );
NOR2BX4TS U2711 ( .AN(n1934), .B(Raw_mant_NRM_SWR[34]), .Y(n1918) );
NAND2BX4TS U2712 ( .AN(Raw_mant_NRM_SWR[33]), .B(n1918), .Y(n1943) );
NAND2BX4TS U2713 ( .AN(Raw_mant_NRM_SWR[30]), .B(n1907), .Y(n1942) );
NAND2X4TS U2714 ( .A(n1909), .B(n3324), .Y(n3113) );
NOR2BX4TS U2715 ( .AN(n1919), .B(Raw_mant_NRM_SWR[25]), .Y(n3112) );
NOR2BX4TS U2716 ( .AN(n3112), .B(Raw_mant_NRM_SWR[24]), .Y(n1986) );
NOR3BX4TS U2717 ( .AN(n1986), .B(Raw_mant_NRM_SWR[23]), .C(
Raw_mant_NRM_SWR[22]), .Y(n1923) );
NAND2BX4TS U2718 ( .AN(Raw_mant_NRM_SWR[13]), .B(n1899), .Y(n1956) );
NOR2X6TS U2719 ( .A(Raw_mant_NRM_SWR[12]), .B(n1956), .Y(n1952) );
NAND2BX4TS U2720 ( .AN(Raw_mant_NRM_SWR[9]), .B(n1981), .Y(n3115) );
NOR2X1TS U2721 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .Y(n1898)
);
NAND2X4TS U2722 ( .A(n1953), .B(n1898), .Y(n1954) );
AOI32X1TS U2723 ( .A0(n1994), .A1(n3286), .A2(n3358), .B0(n1956), .B1(n1994),
.Y(n1891) );
INVX2TS U2724 ( .A(n1891), .Y(n1894) );
INVX2TS U2725 ( .A(n3115), .Y(n1892) );
AOI22X1TS U2726 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n1981), .B0(
Raw_mant_NRM_SWR[10]), .B1(n1952), .Y(n1897) );
AOI32X1TS U2727 ( .A0(n1898), .A1(n1897), .A2(n3362), .B0(n1896), .B1(n1897),
.Y(n1904) );
NAND2X1TS U2728 ( .A(Raw_mant_NRM_SWR[13]), .B(n1899), .Y(n1948) );
OAI31X1TS U2729 ( .A0(n1910), .A1(n1975), .A2(n1905), .B0(
Shift_reg_FLAGS_7[1]), .Y(n3108) );
NAND2X1TS U2730 ( .A(n1906), .B(n3108), .Y(n1605) );
BUFX3TS U2731 ( .A(n2815), .Y(n2821) );
AOI22X1TS U2732 ( .A0(n2821), .A1(shift_value_SHT2_EWR[4]), .B0(n3161), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n1928) );
OAI2BB1X1TS U2733 ( .A0N(n1907), .A1N(Raw_mant_NRM_SWR[30]), .B0(n1937), .Y(
n3118) );
OR2X1TS U2734 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[31]), .Y(n1908) );
AOI22X1TS U2735 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n1909), .B0(n1935), .B1(
n1908), .Y(n1915) );
OAI31X1TS U2736 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1910), .A2(
Raw_mant_NRM_SWR[24]), .B0(n3112), .Y(n1914) );
INVX2TS U2737 ( .A(n1945), .Y(n1929) );
OAI21X1TS U2738 ( .A0(Raw_mant_NRM_SWR[19]), .A1(Raw_mant_NRM_SWR[20]), .B0(
n1929), .Y(n3120) );
OAI21X1TS U2739 ( .A0(Raw_mant_NRM_SWR[35]), .A1(Raw_mant_NRM_SWR[36]), .B0(
n1912), .Y(n1913) );
NAND4X2TS U2740 ( .A(n1915), .B(n1914), .C(n3120), .D(n1913), .Y(n1976) );
NOR2XLTS U2741 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[1]), .Y(n1926)
);
NOR2X1TS U2742 ( .A(Raw_mant_NRM_SWR[40]), .B(n1875), .Y(n1988) );
INVX2TS U2743 ( .A(n1988), .Y(n1972) );
NAND2X1TS U2744 ( .A(n1917), .B(Raw_mant_NRM_SWR[28]), .Y(n1980) );
OAI31X1TS U2745 ( .A0(n1916), .A1(n1961), .A2(n1972), .B0(n1980), .Y(n1921)
);
AOI22X1TS U2746 ( .A0(Raw_mant_NRM_SWR[33]), .A1(n1918), .B0(n1917), .B1(
Raw_mant_NRM_SWR[29]), .Y(n1944) );
NAND2X1TS U2747 ( .A(Raw_mant_NRM_SWR[25]), .B(n1919), .Y(n1982) );
OAI211XLTS U2748 ( .A0(n3419), .A1(n1942), .B0(n1944), .C0(n1982), .Y(n1920)
);
AOI211X1TS U2749 ( .A0(n1922), .A1(Raw_mant_NRM_SWR[34]), .B0(n1921), .C0(
n1920), .Y(n1924) );
NAND2X1TS U2750 ( .A(Raw_mant_NRM_SWR[21]), .B(n1923), .Y(n1940) );
OAI211X1TS U2751 ( .A0(n1926), .A1(n1925), .B0(n1924), .C0(n1940), .Y(n1927)
);
OAI31X1TS U2752 ( .A0(n3118), .A1(n1976), .A2(n1927), .B0(
Shift_reg_FLAGS_7[1]), .Y(n3109) );
NAND2X1TS U2753 ( .A(n1928), .B(n3109), .Y(n1607) );
AOI22X1TS U2754 ( .A0(n2821), .A1(shift_value_SHT2_EWR[2]), .B0(
Shift_amount_SHT1_EWR[2]), .B1(n3161), .Y(n1960) );
OAI2BB2XLTS U2755 ( .B0(n1930), .B1(n3427), .A0N(Raw_mant_NRM_SWR[20]),
.A1N(n1929), .Y(n1959) );
OAI211XLTS U2756 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1937), .B0(n1936), .C0(
n1980), .Y(n1958) );
AOI32X1TS U2757 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1953), .A2(n3344), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1953), .Y(n1941) );
AOI32X1TS U2758 ( .A0(n1875), .A1(n1938), .A2(n3363), .B0(n1849), .B1(n1938),
.Y(n1939) );
OAI211X1TS U2759 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1941), .B0(n1940), .C0(
n1939), .Y(n3126) );
OR2X1TS U2760 ( .A(Raw_mant_NRM_SWR[28]), .B(n1942), .Y(n1950) );
NOR3BX1TS U2761 ( .AN(Raw_mant_NRM_SWR[31]), .B(Raw_mant_NRM_SWR[32]), .C(
n1943), .Y(n1947) );
OAI31X1TS U2762 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n3355), .A2(n1945), .B0(
n1944), .Y(n1946) );
AOI211X1TS U2763 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n3111), .B0(n1947), .C0(
n1946), .Y(n1949) );
AOI211X4TS U2764 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n1952), .B0(n3126), .C0(
n1951), .Y(n2001) );
OAI31X1TS U2765 ( .A0(Raw_mant_NRM_SWR[42]), .A1(n1955), .A2(
Raw_mant_NRM_SWR[40]), .B0(n1987), .Y(n3122) );
OAI31X1TS U2766 ( .A0(n1959), .A1(n1958), .A2(n1957), .B0(
Shift_reg_FLAGS_7[1]), .Y(n3127) );
NAND2X1TS U2767 ( .A(n1960), .B(n3127), .Y(n1609) );
INVX4TS U2768 ( .A(Shift_reg_FLAGS_7[1]), .Y(n3137) );
NAND2X1TS U2769 ( .A(Raw_mant_NRM_SWR[43]), .B(n1962), .Y(n1983) );
INVX2TS U2770 ( .A(n1983), .Y(n1971) );
AOI211X1TS U2771 ( .A0(n1964), .A1(Raw_mant_NRM_SWR[44]), .B0(
Raw_mant_NRM_SWR[47]), .C0(Raw_mant_NRM_SWR[48]), .Y(n1968) );
OAI32X1TS U2772 ( .A0(n1969), .A1(n1968), .A2(n1967), .B0(n1966), .B1(n1969),
.Y(n1970) );
AOI211X1TS U2773 ( .A0(n1973), .A1(n1972), .B0(n1971), .C0(n1970), .Y(n1979)
);
AOI211X2TS U2774 ( .A0(n1977), .A1(Raw_mant_NRM_SWR[16]), .B0(n1976), .C0(
n1975), .Y(n1978) );
OAI211X4TS U2775 ( .A0(Raw_mant_NRM_SWR[29]), .A1(n1980), .B0(n1979), .C0(
n1978), .Y(n2636) );
OAI2BB1X4TS U2776 ( .A0N(Shift_amount_SHT1_EWR[1]), .A1N(n3137), .B0(n2837),
.Y(n2631) );
NOR2BX4TS U2777 ( .AN(n2631), .B(n2795), .Y(n2807) );
AOI21X1TS U2778 ( .A0(n1986), .A1(Raw_mant_NRM_SWR[23]), .B0(n1985), .Y(
n3123) );
AOI21X1TS U2779 ( .A0(n3367), .A1(Raw_mant_NRM_SWR[49]), .B0(
Raw_mant_NRM_SWR[51]), .Y(n1989) );
OAI22X1TS U2780 ( .A0(n1992), .A1(n1991), .B0(Raw_mant_NRM_SWR[54]), .B1(
n1990), .Y(n1993) );
NAND2X1TS U2781 ( .A(n1859), .B(n3137), .Y(n2734) );
AOI22X1TS U2782 ( .A0(n2810), .A1(Raw_mant_NRM_SWR[51]), .B0(n2704), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2005) );
BUFX4TS U2783 ( .A(n2639), .Y(n2752) );
OR2X2TS U2784 ( .A(Shift_reg_FLAGS_7[1]), .B(n1859), .Y(n2736) );
INVX4TS U2785 ( .A(n2736), .Y(n2750) );
AOI22X1TS U2786 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[52]), .B0(n2750), .B1(
DmP_mant_SHT1_SW[0]), .Y(n2004) );
NAND2X1TS U2787 ( .A(n2005), .B(n2004), .Y(n2650) );
AOI22X1TS U2788 ( .A0(n3162), .A1(Data_array_SWR[0]), .B0(n2807), .B1(n2650),
.Y(n2007) );
OR2X2TS U2789 ( .A(n2636), .B(n3128), .Y(n2730) );
INVX4TS U2790 ( .A(n2730), .Y(n2720) );
AOI22X1TS U2791 ( .A0(n2720), .A1(Raw_mant_NRM_SWR[53]), .B0(n2752), .B1(
Raw_mant_NRM_SWR[54]), .Y(n2006) );
NAND2X1TS U2792 ( .A(n2007), .B(n2006), .Y(n1610) );
BUFX3TS U2793 ( .A(n3494), .Y(n3496) );
BUFX3TS U2794 ( .A(n3493), .Y(n3467) );
BUFX3TS U2795 ( .A(n3497), .Y(n3466) );
CLKBUFX2TS U2796 ( .A(n3457), .Y(n3497) );
BUFX3TS U2797 ( .A(n3458), .Y(n3464) );
BUFX3TS U2798 ( .A(n3493), .Y(n3463) );
BUFX3TS U2799 ( .A(n2008), .Y(n3471) );
BUFX3TS U2800 ( .A(n3497), .Y(n3495) );
BUFX3TS U2801 ( .A(n2009), .Y(n3469) );
BUFX3TS U2802 ( .A(n3460), .Y(n3452) );
BUFX3TS U2803 ( .A(n3494), .Y(n3458) );
BUFX3TS U2804 ( .A(n3458), .Y(n3488) );
BUFX3TS U2805 ( .A(n3477), .Y(n3500) );
BUFX3TS U2806 ( .A(n2009), .Y(n3482) );
BUFX3TS U2807 ( .A(n2009), .Y(n3481) );
BUFX3TS U2808 ( .A(n3494), .Y(n3480) );
BUFX3TS U2809 ( .A(n3468), .Y(n3475) );
BUFX3TS U2810 ( .A(n3470), .Y(n3474) );
BUFX3TS U2811 ( .A(n3504), .Y(n3486) );
BUFX3TS U2812 ( .A(n3499), .Y(n3451) );
BUFX3TS U2813 ( .A(n2009), .Y(n3492) );
BUFX3TS U2814 ( .A(n2008), .Y(n3484) );
BUFX3TS U2815 ( .A(n3495), .Y(n3476) );
BUFX3TS U2816 ( .A(n3504), .Y(n3479) );
AO22XLTS U2817 ( .A0(n1885), .A1(SIGN_FLAG_NRM), .B0(n3137), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n1185) );
AO22XLTS U2818 ( .A0(n1885), .A1(ZERO_FLAG_NRM), .B0(n3137), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n1194) );
CLKXOR2X2TS U2819 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n2554) );
OAI21XLTS U2820 ( .A0(n2554), .A1(intDX_EWSW[63]), .B0(n3211), .Y(n2011) );
AOI21X1TS U2821 ( .A0(n2554), .A1(intDX_EWSW[63]), .B0(n2011), .Y(n2080) );
AO21XLTS U2822 ( .A0(OP_FLAG_EXP), .A1(n2629), .B0(n2080), .Y(n1524) );
INVX4TS U2823 ( .A(n3194), .Y(busy) );
AOI22X1TS U2824 ( .A0(n3305), .A1(intDX_EWSW[11]), .B0(n3388), .B1(
intDX_EWSW[50]), .Y(n2012) );
OAI221XLTS U2825 ( .A0(n3305), .A1(intDX_EWSW[11]), .B0(n3388), .B1(
intDX_EWSW[50]), .C0(n2012), .Y(n2013) );
AOI221X1TS U2826 ( .A0(intDY_EWSW[49]), .A1(n3414), .B0(n3409), .B1(
intDX_EWSW[49]), .C0(n2013), .Y(n2027) );
OAI22X1TS U2827 ( .A0(n3284), .A1(intDX_EWSW[53]), .B0(n3282), .B1(
intDX_EWSW[54]), .Y(n2014) );
AOI221X1TS U2828 ( .A0(n3284), .A1(intDX_EWSW[53]), .B0(intDX_EWSW[54]),
.B1(n3282), .C0(n2014), .Y(n2026) );
OAI22X1TS U2829 ( .A0(n3406), .A1(intDX_EWSW[51]), .B0(n3415), .B1(
intDX_EWSW[52]), .Y(n2015) );
AOI221X1TS U2830 ( .A0(n3406), .A1(intDX_EWSW[51]), .B0(intDX_EWSW[52]),
.B1(n3415), .C0(n2015), .Y(n2025) );
AOI22X1TS U2831 ( .A0(n3392), .A1(intDY_EWSW[58]), .B0(n3389), .B1(
intDX_EWSW[57]), .Y(n2016) );
AOI22X1TS U2832 ( .A0(n3281), .A1(intDX_EWSW[56]), .B0(n3283), .B1(
intDX_EWSW[55]), .Y(n2017) );
OAI221XLTS U2833 ( .A0(n3281), .A1(intDX_EWSW[56]), .B0(n3283), .B1(
intDX_EWSW[55]), .C0(n2017), .Y(n2022) );
AOI22X1TS U2834 ( .A0(n3306), .A1(intDY_EWSW[62]), .B0(n3391), .B1(
intDY_EWSW[61]), .Y(n2018) );
AOI22X1TS U2835 ( .A0(n3393), .A1(intDY_EWSW[60]), .B0(n3307), .B1(
intDY_EWSW[59]), .Y(n2019) );
NOR4X1TS U2836 ( .A(n2023), .B(n2022), .C(n2021), .D(n2020), .Y(n2024) );
NAND4XLTS U2837 ( .A(n2027), .B(n2026), .C(n2025), .D(n2024), .Y(n2079) );
OAI22X1TS U2838 ( .A0(n3403), .A1(intDX_EWSW[42]), .B0(n3311), .B1(
intDX_EWSW[43]), .Y(n2028) );
AOI221X1TS U2839 ( .A0(n3403), .A1(intDX_EWSW[42]), .B0(intDX_EWSW[43]),
.B1(n3311), .C0(n2028), .Y(n2035) );
OAI22X1TS U2840 ( .A0(n3402), .A1(intDX_EWSW[40]), .B0(n3310), .B1(
intDX_EWSW[41]), .Y(n2029) );
AOI221X1TS U2841 ( .A0(n3402), .A1(intDX_EWSW[40]), .B0(intDX_EWSW[41]),
.B1(n3310), .C0(n2029), .Y(n2034) );
OAI22X1TS U2842 ( .A0(n3405), .A1(intDX_EWSW[46]), .B0(n3308), .B1(
intDX_EWSW[47]), .Y(n2030) );
AOI221X1TS U2843 ( .A0(n3405), .A1(intDX_EWSW[46]), .B0(intDX_EWSW[47]),
.B1(n3308), .C0(n2030), .Y(n2033) );
OAI22X1TS U2844 ( .A0(n3404), .A1(intDX_EWSW[44]), .B0(n3398), .B1(
intDX_EWSW[45]), .Y(n2031) );
AOI221X1TS U2845 ( .A0(n3404), .A1(intDX_EWSW[44]), .B0(intDX_EWSW[45]),
.B1(n3398), .C0(n2031), .Y(n2032) );
NAND4XLTS U2846 ( .A(n2035), .B(n2034), .C(n2033), .D(n2032), .Y(n2078) );
OAI22X1TS U2847 ( .A0(n3400), .A1(intDX_EWSW[34]), .B0(n3309), .B1(
intDX_EWSW[35]), .Y(n2036) );
AOI221X1TS U2848 ( .A0(n3400), .A1(intDX_EWSW[34]), .B0(intDX_EWSW[35]),
.B1(n3309), .C0(n2036), .Y(n2043) );
OAI22X1TS U2849 ( .A0(n3421), .A1(intDX_EWSW[1]), .B0(n3399), .B1(
intDX_EWSW[33]), .Y(n2037) );
AOI221X1TS U2850 ( .A0(n3421), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[33]), .B1(
n3399), .C0(n2037), .Y(n2042) );
OAI22X1TS U2851 ( .A0(n3422), .A1(intDX_EWSW[38]), .B0(n3397), .B1(
intDX_EWSW[39]), .Y(n2038) );
OAI22X1TS U2852 ( .A0(n3401), .A1(intDX_EWSW[36]), .B0(n3396), .B1(
intDX_EWSW[37]), .Y(n2039) );
AOI221X1TS U2853 ( .A0(n3401), .A1(intDX_EWSW[36]), .B0(intDX_EWSW[37]),
.B1(n3396), .C0(n2039), .Y(n2040) );
NAND4XLTS U2854 ( .A(n2043), .B(n2042), .C(n2041), .D(n2040), .Y(n2077) );
OA22X1TS U2855 ( .A0(n3338), .A1(intDY_EWSW[30]), .B0(n3290), .B1(
intDY_EWSW[31]), .Y(n2356) );
OAI221XLTS U2856 ( .A0(n3314), .A1(intDX_EWSW[31]), .B0(n3412), .B1(
intDX_EWSW[30]), .C0(n2356), .Y(n2050) );
AOI22X1TS U2857 ( .A0(n3302), .A1(intDX_EWSW[29]), .B0(n3376), .B1(
intDX_EWSW[20]), .Y(n2044) );
OAI221XLTS U2858 ( .A0(n3302), .A1(intDX_EWSW[29]), .B0(n3376), .B1(
intDX_EWSW[20]), .C0(n2044), .Y(n2049) );
AOI22X1TS U2859 ( .A0(n3300), .A1(intDX_EWSW[27]), .B0(n3378), .B1(
intDX_EWSW[26]), .Y(n2045) );
AOI22X1TS U2860 ( .A0(n3299), .A1(intDX_EWSW[25]), .B0(n3380), .B1(
intDX_EWSW[32]), .Y(n2046) );
NOR4X1TS U2861 ( .A(n2047), .B(n2049), .C(n2048), .D(n2050), .Y(n2075) );
OA22X1TS U2862 ( .A0(n3339), .A1(intDY_EWSW[22]), .B0(n3291), .B1(
intDY_EWSW[23]), .Y(n2403) );
OAI221XLTS U2863 ( .A0(n3313), .A1(intDX_EWSW[23]), .B0(n3411), .B1(
intDX_EWSW[22]), .C0(n2403), .Y(n2057) );
AOI22X1TS U2864 ( .A0(n3371), .A1(intDX_EWSW[21]), .B0(n3381), .B1(
intDX_EWSW[48]), .Y(n2051) );
AOI22X1TS U2865 ( .A0(n3298), .A1(intDX_EWSW[19]), .B0(n3375), .B1(
intDX_EWSW[18]), .Y(n2052) );
OAI221XLTS U2866 ( .A0(n3298), .A1(intDX_EWSW[19]), .B0(n3375), .B1(
intDX_EWSW[18]), .C0(n2052), .Y(n2055) );
AOI22X1TS U2867 ( .A0(n3297), .A1(intDX_EWSW[17]), .B0(n3377), .B1(
intDX_EWSW[24]), .Y(n2053) );
NOR4X1TS U2868 ( .A(n2056), .B(n2057), .C(n2054), .D(n2055), .Y(n2074) );
OA22X1TS U2869 ( .A0(n3328), .A1(intDY_EWSW[14]), .B0(n3287), .B1(
intDY_EWSW[15]), .Y(n2384) );
OAI221XLTS U2870 ( .A0(n3312), .A1(intDX_EWSW[15]), .B0(n3410), .B1(
intDX_EWSW[14]), .C0(n2384), .Y(n2064) );
AOI22X1TS U2871 ( .A0(n3370), .A1(intDX_EWSW[13]), .B0(n3303), .B1(
intDX_EWSW[4]), .Y(n2058) );
AOI22X1TS U2872 ( .A0(n3369), .A1(intDX_EWSW[10]), .B0(n3374), .B1(
intDX_EWSW[12]), .Y(n2059) );
AOI22X1TS U2873 ( .A0(n3368), .A1(intDX_EWSW[9]), .B0(n3382), .B1(
intDX_EWSW[16]), .Y(n2060) );
NOR4X1TS U2874 ( .A(n2063), .B(n2064), .C(n2062), .D(n2061), .Y(n2073) );
INVX2TS U2875 ( .A(intDY_EWSW[7]), .Y(n2582) );
AOI22X1TS U2876 ( .A0(intDX_EWSW[7]), .A1(n2582), .B0(intDX_EWSW[6]), .B1(
n3315), .Y(n2367) );
INVX2TS U2877 ( .A(intDY_EWSW[5]), .Y(n2606) );
AOI22X1TS U2878 ( .A0(n3387), .A1(intDX_EWSW[5]), .B0(n3379), .B1(
intDX_EWSW[28]), .Y(n2065) );
AOI22X1TS U2879 ( .A0(n3301), .A1(intDX_EWSW[3]), .B0(n3372), .B1(
intDX_EWSW[2]), .Y(n2066) );
AOI22X1TS U2880 ( .A0(n1820), .A1(intDX_EWSW[0]), .B0(n3373), .B1(
intDX_EWSW[8]), .Y(n2067) );
NOR4X1TS U2881 ( .A(n2071), .B(n2070), .C(n2069), .D(n2068), .Y(n2072) );
NAND4XLTS U2882 ( .A(n2075), .B(n2074), .C(n2073), .D(n2072), .Y(n2076) );
NOR4X1TS U2883 ( .A(n2079), .B(n2078), .C(n2077), .D(n2076), .Y(n2559) );
AO22XLTS U2884 ( .A0(n2559), .A1(n2080), .B0(ZERO_FLAG_EXP), .B1(n2629), .Y(
n1523) );
AOI22X1TS U2885 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n3130), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n3304), .Y(n3133) );
CLKBUFX2TS U2886 ( .A(n3140), .Y(n3139) );
INVX4TS U2887 ( .A(n3139), .Y(n3141) );
AO22XLTS U2888 ( .A0(n3152), .A1(Data_X[23]), .B0(n3141), .B1(intDX_EWSW[23]), .Y(n1771) );
INVX4TS U2889 ( .A(n3139), .Y(n3142) );
AO22XLTS U2890 ( .A0(n3152), .A1(Data_X[15]), .B0(n3142), .B1(intDX_EWSW[15]), .Y(n1779) );
AO22XLTS U2891 ( .A0(n3152), .A1(Data_X[19]), .B0(n3141), .B1(intDX_EWSW[19]), .Y(n1775) );
AO22XLTS U2892 ( .A0(n3152), .A1(Data_X[17]), .B0(n3142), .B1(intDX_EWSW[17]), .Y(n1777) );
AO22XLTS U2893 ( .A0(n3152), .A1(Data_X[18]), .B0(n3141), .B1(intDX_EWSW[18]), .Y(n1776) );
AO22XLTS U2894 ( .A0(n3152), .A1(Data_X[22]), .B0(n3141), .B1(intDX_EWSW[22]), .Y(n1772) );
AO22XLTS U2895 ( .A0(n3152), .A1(Data_X[20]), .B0(n3141), .B1(intDX_EWSW[20]), .Y(n1774) );
AO22XLTS U2896 ( .A0(n3139), .A1(Data_X[14]), .B0(n3142), .B1(intDX_EWSW[14]), .Y(n1780) );
AO22XLTS U2897 ( .A0(n3152), .A1(Data_X[21]), .B0(n3141), .B1(intDX_EWSW[21]), .Y(n1773) );
INVX4TS U2898 ( .A(n3140), .Y(n3157) );
AO22XLTS U2899 ( .A0(n3157), .A1(intDY_EWSW[41]), .B0(n3153), .B1(Data_Y[41]), .Y(n1687) );
CLKBUFX2TS U2900 ( .A(n3140), .Y(n3158) );
INVX4TS U2901 ( .A(n3158), .Y(n3159) );
AO22XLTS U2902 ( .A0(n3158), .A1(Data_Y[61]), .B0(n3159), .B1(intDY_EWSW[61]), .Y(n1667) );
NOR2X1TS U2903 ( .A(n1886), .B(Shift_reg_FLAGS_7[0]), .Y(n2857) );
BUFX3TS U2904 ( .A(n2857), .Y(n2856) );
NOR2XLTS U2905 ( .A(shift_value_SHT2_EWR[4]), .B(n3332), .Y(n2081) );
BUFX3TS U2906 ( .A(n2081), .Y(n2914) );
NOR2X1TS U2907 ( .A(shift_value_SHT2_EWR[2]), .B(n3345), .Y(n2162) );
INVX2TS U2908 ( .A(n2162), .Y(n2172) );
INVX4TS U2909 ( .A(n2172), .Y(n2884) );
AOI22X1TS U2910 ( .A0(n1876), .A1(n2103), .B0(n1877), .B1(n2884), .Y(n2083)
);
NAND2X1TS U2911 ( .A(n3345), .B(shift_value_SHT2_EWR[2]), .Y(n2086) );
INVX2TS U2912 ( .A(n2220), .Y(n2180) );
AOI22X1TS U2913 ( .A0(Data_array_SWR[30]), .A1(n2887), .B0(
Data_array_SWR[26]), .B1(n2180), .Y(n2082) );
NAND2X1TS U2914 ( .A(n2083), .B(n2082), .Y(n2241) );
INVX4TS U2915 ( .A(n2172), .Y(n2904) );
AOI22X1TS U2916 ( .A0(n1880), .A1(n2904), .B0(Data_array_SWR[24]), .B1(n2103), .Y(n2085) );
AOI22X1TS U2917 ( .A0(Data_array_SWR[17]), .A1(n2887), .B0(n1869), .B1(n2896), .Y(n2084) );
BUFX3TS U2918 ( .A(n2111), .Y(n2939) );
AOI21X1TS U2919 ( .A0(n2085), .A1(n2084), .B0(n2939), .Y(n2090) );
INVX4TS U2920 ( .A(n2220), .Y(n2905) );
NAND2X1TS U2921 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n2866) );
NAND2BX2TS U2922 ( .AN(shift_value_SHT2_EWR[4]), .B(n3332), .Y(n2144) );
NOR2X1TS U2923 ( .A(n2907), .B(n2144), .Y(n2097) );
BUFX3TS U2924 ( .A(n2097), .Y(n2895) );
NOR2X1TS U2925 ( .A(n2220), .B(n2144), .Y(n2091) );
BUFX3TS U2926 ( .A(n2091), .Y(n2933) );
AOI22X1TS U2927 ( .A0(Data_array_SWR[11]), .A1(n2895), .B0(Data_array_SWR[1]), .B1(n2933), .Y(n2088) );
NOR2X1TS U2928 ( .A(n2172), .B(n2144), .Y(n2107) );
BUFX3TS U2929 ( .A(n2107), .Y(n2934) );
AOI22X1TS U2930 ( .A0(Data_array_SWR[7]), .A1(n2934), .B0(Data_array_SWR[4]),
.B1(n2106), .Y(n2087) );
AOI211X1TS U2931 ( .A0(n2914), .A1(n2241), .B0(n2090), .C0(n2089), .Y(n2861)
);
BUFX3TS U2932 ( .A(n2091), .Y(n2910) );
OAI22X1TS U2933 ( .A0(left_right_SHT2), .A1(n2861), .B0(n3407), .B1(n3232),
.Y(n2092) );
AO22XLTS U2934 ( .A0(n3198), .A1(n2092), .B0(n3224), .B1(n1861), .Y(n1140)
);
BUFX3TS U2935 ( .A(n2856), .Y(n3198) );
AOI22X1TS U2936 ( .A0(Data_array_SWR[35]), .A1(n2103), .B0(
Data_array_SWR[33]), .B1(n2884), .Y(n2094) );
AOI22X1TS U2937 ( .A0(n1879), .A1(n2905), .B0(Data_array_SWR[29]), .B1(n2887), .Y(n2093) );
NAND2X1TS U2938 ( .A(n2094), .B(n2093), .Y(n2148) );
AOI22X1TS U2939 ( .A0(Data_array_SWR[23]), .A1(n2103), .B0(
Data_array_SWR[20]), .B1(n2884), .Y(n2096) );
AOI22X1TS U2940 ( .A0(n1871), .A1(n2905), .B0(Data_array_SWR[16]), .B1(n2887), .Y(n2095) );
AOI21X1TS U2941 ( .A0(n2096), .A1(n2095), .B0(n2939), .Y(n2101) );
BUFX3TS U2942 ( .A(n2097), .Y(n2936) );
AOI22X1TS U2943 ( .A0(Data_array_SWR[10]), .A1(n2936), .B0(Data_array_SWR[0]), .B1(n2910), .Y(n2099) );
AOI22X1TS U2944 ( .A0(Data_array_SWR[6]), .A1(n2934), .B0(n1865), .B1(n2106),
.Y(n2098) );
AOI211X1TS U2945 ( .A0(n2914), .A1(n2148), .B0(n2101), .C0(n2100), .Y(n2859)
);
OAI22X1TS U2946 ( .A0(left_right_SHT2), .A1(n2859), .B0(n3408), .B1(n3232),
.Y(n2102) );
AO22XLTS U2947 ( .A0(n3258), .A1(n2102), .B0(n3224), .B1(n1860), .Y(n1137)
);
BUFX3TS U2948 ( .A(n2897), .Y(n2909) );
BUFX3TS U2949 ( .A(n2103), .Y(n2885) );
AOI22X1TS U2950 ( .A0(Data_array_SWR[40]), .A1(n2885), .B0(
Data_array_SWR[36]), .B1(n2884), .Y(n2104) );
AOI21X1TS U2951 ( .A0(Data_array_SWR[34]), .A1(n2909), .B0(n2105), .Y(n2152)
);
BUFX3TS U2952 ( .A(n2106), .Y(n2935) );
AOI22X1TS U2953 ( .A0(Data_array_SWR[21]), .A1(n2935), .B0(
Data_array_SWR[18]), .B1(n2933), .Y(n2110) );
NAND2X1TS U2954 ( .A(n2180), .B(n2914), .Y(n2236) );
CLKBUFX3TS U2955 ( .A(n2107), .Y(n2886) );
OAI2BB2XLTS U2956 ( .B0(n3408), .B1(n2236), .A0N(n1881), .A1N(n2886), .Y(
n2108) );
AOI21X1TS U2957 ( .A0(Data_array_SWR[27]), .A1(n2895), .B0(n2108), .Y(n2109)
);
OAI211X1TS U2958 ( .A0(n2152), .A1(n2939), .B0(n2110), .C0(n2109), .Y(n2146)
);
INVX2TS U2959 ( .A(n3236), .Y(n2147) );
BUFX3TS U2960 ( .A(n2113), .Y(n2962) );
AOI222X1TS U2961 ( .A0(n2146), .A1(n1804), .B0(n2147), .B1(n2960), .C0(n2148), .C1(n2962), .Y(n2329) );
INVX2TS U2962 ( .A(DP_OP_15J9_123_7955_n6), .Y(n2114) );
INVX2TS U2963 ( .A(n2118), .Y(n2115) );
XNOR2X1TS U2964 ( .A(DMP_exp_NRM2_EW[8]), .B(n2120), .Y(n2130) );
XNOR2X1TS U2965 ( .A(DMP_exp_NRM2_EW[0]), .B(n2835), .Y(n2131) );
INVX2TS U2966 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n2314) );
INVX2TS U2967 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n2319) );
CLKXOR2X2TS U2968 ( .A(DMP_exp_NRM2_EW[7]), .B(n2118), .Y(n2302) );
XNOR2X1TS U2969 ( .A(DMP_exp_NRM2_EW[6]), .B(DP_OP_15J9_123_7955_n6), .Y(
n2133) );
INVX2TS U2970 ( .A(n2133), .Y(n2306) );
INVX2TS U2971 ( .A(n2120), .Y(n2121) );
XNOR2X1TS U2972 ( .A(DMP_exp_NRM2_EW[9]), .B(n2123), .Y(n2129) );
INVX2TS U2973 ( .A(n2123), .Y(n2124) );
NAND2X1TS U2974 ( .A(n3420), .B(n2124), .Y(n2127) );
INVX2TS U2975 ( .A(n2129), .Y(n2312) );
INVX2TS U2976 ( .A(n2130), .Y(n2316) );
INVX2TS U2977 ( .A(n2131), .Y(n2308) );
INVX2TS U2978 ( .A(exp_rslt_NRM2_EW1[1]), .Y(n2321) );
NOR4X1TS U2979 ( .A(n2314), .B(n2319), .C(n2308), .D(n2321), .Y(n2132) );
NOR4X1TS U2980 ( .A(n2312), .B(n2316), .C(n2302), .D(n2134), .Y(n2135) );
NAND2X1TS U2981 ( .A(Shift_reg_FLAGS_7[0]), .B(n3226), .Y(n3215) );
OAI2BB2XLTS U2982 ( .B0(n2329), .B1(n3247), .A0N(final_result_ieee[20]),
.A1N(n3278), .Y(n1093) );
AOI222X4TS U2983 ( .A0(Data_array_SWR[42]), .A1(n2904), .B0(
Data_array_SWR[38]), .B1(n2909), .C0(Data_array_SWR[35]), .C1(n2180),
.Y(n2930) );
INVX2TS U2984 ( .A(n2914), .Y(n2199) );
AOI22X1TS U2985 ( .A0(Data_array_SWR[10]), .A1(n2933), .B0(
Data_array_SWR[16]), .B1(n2886), .Y(n2138) );
AOI22X1TS U2986 ( .A0(n1871), .A1(n2935), .B0(Data_array_SWR[20]), .B1(n2895), .Y(n2137) );
OAI211X1TS U2987 ( .A0(n2930), .A1(n2199), .B0(n2138), .C0(n2137), .Y(n2169)
);
AOI22X1TS U2988 ( .A0(Data_array_SWR[44]), .A1(n2885), .B0(
Data_array_SWR[40]), .B1(n2904), .Y(n2140) );
AOI22X1TS U2989 ( .A0(Data_array_SWR[36]), .A1(n2909), .B0(
Data_array_SWR[34]), .B1(n2905), .Y(n2139) );
NAND2X2TS U2990 ( .A(n2140), .B(n2139), .Y(n2943) );
AOI22X1TS U2991 ( .A0(Data_array_SWR[33]), .A1(n2885), .B0(
Data_array_SWR[29]), .B1(n2904), .Y(n2142) );
AOI22X1TS U2992 ( .A0(n1879), .A1(n2897), .B0(Data_array_SWR[23]), .B1(n2905), .Y(n2141) );
NAND2X1TS U2993 ( .A(n2142), .B(n2141), .Y(n2942) );
OAI2BB2XLTS U2994 ( .B0(n3244), .B1(n3247), .A0N(final_result_ieee[10]),
.A1N(n3219), .Y(n1088) );
BUFX3TS U2995 ( .A(n2145), .Y(n2929) );
OAI2BB2XLTS U2996 ( .B0(n2327), .B1(n3247), .A0N(final_result_ieee[30]),
.A1N(n3278), .Y(n1092) );
AOI22X1TS U2997 ( .A0(Data_array_SWR[20]), .A1(n2934), .B0(
Data_array_SWR[16]), .B1(n2106), .Y(n2151) );
AOI22X1TS U2998 ( .A0(Data_array_SWR[23]), .A1(n2936), .B0(n1871), .B1(n2910), .Y(n2150) );
INVX2TS U2999 ( .A(n2939), .Y(n2213) );
AOI22X1TS U3000 ( .A0(n2213), .A1(n2148), .B0(n2914), .B1(n2147), .Y(n2149)
);
NOR2X2TS U3001 ( .A(shift_value_SHT2_EWR[5]), .B(n3241), .Y(n2227) );
AOI22X1TS U3002 ( .A0(left_right_SHT2), .A1(n2159), .B0(n2227), .B1(n2903),
.Y(n2292) );
OAI2BB2XLTS U3003 ( .B0(n2292), .B1(n3247), .A0N(final_result_ieee[36]),
.A1N(n3136), .Y(n1114) );
AOI222X4TS U3004 ( .A0(Data_array_SWR[44]), .A1(n2884), .B0(
Data_array_SWR[40]), .B1(n2909), .C0(Data_array_SWR[36]), .C1(n2180),
.Y(n2923) );
AOI22X1TS U3005 ( .A0(Data_array_SWR[21]), .A1(n2936), .B0(
Data_array_SWR[18]), .B1(n2934), .Y(n2154) );
AOI22X1TS U3006 ( .A0(Data_array_SWR[12]), .A1(n2933), .B0(
Data_array_SWR[14]), .B1(n2935), .Y(n2153) );
OAI211X1TS U3007 ( .A0(n2923), .A1(n2199), .B0(n2154), .C0(n2153), .Y(n2161)
);
AOI22X1TS U3008 ( .A0(Data_array_SWR[42]), .A1(n2885), .B0(
Data_array_SWR[38]), .B1(n2904), .Y(n2156) );
AOI22X1TS U3009 ( .A0(Data_array_SWR[35]), .A1(n2887), .B0(
Data_array_SWR[33]), .B1(n2180), .Y(n2155) );
NAND2X2TS U3010 ( .A(n2156), .B(n2155), .Y(n2955) );
AOI22X1TS U3011 ( .A0(Data_array_SWR[34]), .A1(n2103), .B0(
Data_array_SWR[31]), .B1(n2884), .Y(n2158) );
AOI22X1TS U3012 ( .A0(n1881), .A1(n2905), .B0(Data_array_SWR[27]), .B1(n2887), .Y(n2157) );
NAND2X1TS U3013 ( .A(n2158), .B(n2157), .Y(n2954) );
OAI2BB2XLTS U3014 ( .B0(n2486), .B1(n3247), .A0N(final_result_ieee[38]),
.A1N(n3272), .Y(n1100) );
NOR2X2TS U3015 ( .A(shift_value_SHT2_EWR[5]), .B(n1804), .Y(n2230) );
INVX4TS U3016 ( .A(left_right_SHT2), .Y(n2915) );
AOI22X1TS U3017 ( .A0(n2903), .A1(n2230), .B0(n2159), .B1(n2915), .Y(n2286)
);
OAI2BB2XLTS U3018 ( .B0(n2286), .B1(n3247), .A0N(final_result_ieee[14]),
.A1N(n3219), .Y(n1115) );
AOI21X1TS U3019 ( .A0(n2161), .A1(n2915), .B0(n2160), .Y(n2296) );
OAI2BB2XLTS U3020 ( .B0(n2296), .B1(n3247), .A0N(final_result_ieee[12]),
.A1N(n3278), .Y(n1101) );
AOI222X4TS U3021 ( .A0(Data_array_SWR[39]), .A1(n2909), .B0(n1876), .B1(
n2180), .C0(Data_array_SWR[43]), .C1(n2162), .Y(n2926) );
AOI22X1TS U3022 ( .A0(Data_array_SWR[17]), .A1(n2934), .B0(
Data_array_SWR[11]), .B1(n2933), .Y(n2164) );
AOI22X1TS U3023 ( .A0(n1880), .A1(n2936), .B0(n1869), .B1(n2935), .Y(n2163)
);
OAI211X1TS U3024 ( .A0(n2926), .A1(n2199), .B0(n2164), .C0(n2163), .Y(n2170)
);
AOI22X1TS U3025 ( .A0(Data_array_SWR[39]), .A1(n2904), .B0(
Data_array_SWR[43]), .B1(n2103), .Y(n2166) );
AOI22X1TS U3026 ( .A0(n1876), .A1(n2887), .B0(n1877), .B1(n2905), .Y(n2165)
);
NAND2X2TS U3027 ( .A(n2166), .B(n2165), .Y(n2949) );
AOI22X1TS U3028 ( .A0(n1877), .A1(n2885), .B0(Data_array_SWR[30]), .B1(n2904), .Y(n2168) );
AOI22X1TS U3029 ( .A0(Data_array_SWR[26]), .A1(n2897), .B0(
Data_array_SWR[24]), .B1(n2905), .Y(n2167) );
NAND2X1TS U3030 ( .A(n2168), .B(n2167), .Y(n2948) );
OAI2BB2XLTS U3031 ( .B0(n2335), .B1(n3247), .A0N(final_result_ieee[39]),
.A1N(n3136), .Y(n1106) );
OAI2BB2XLTS U3032 ( .B0(n2338), .B1(n3247), .A0N(final_result_ieee[40]),
.A1N(n3136), .Y(n1087) );
OAI2BB2XLTS U3033 ( .B0(n3245), .B1(n3247), .A0N(final_result_ieee[11]),
.A1N(n2318), .Y(n1109) );
INVX4TS U3034 ( .A(n3247), .Y(n3263) );
AOI22X1TS U3035 ( .A0(Data_array_SWR[37]), .A1(n2897), .B0(n1878), .B1(n2896), .Y(n2171) );
OAI21X1TS U3036 ( .A0(n3395), .A1(n2172), .B0(n2171), .Y(n2178) );
AO22XLTS U3037 ( .A0(Data_array_SWR[15]), .A1(n2886), .B0(Data_array_SWR[13]), .B1(n2106), .Y(n2177) );
AOI22X1TS U3038 ( .A0(Data_array_SWR[32]), .A1(n2885), .B0(
Data_array_SWR[28]), .B1(n2904), .Y(n2175) );
AOI22X1TS U3039 ( .A0(Data_array_SWR[19]), .A1(n2936), .B0(Data_array_SWR[9]), .B1(n2910), .Y(n2174) );
AOI22X1TS U3040 ( .A0(Data_array_SWR[25]), .A1(n2897), .B0(
Data_array_SWR[22]), .B1(n2896), .Y(n2173) );
AOI32X1TS U3041 ( .A0(n2175), .A1(n2174), .A2(n2173), .B0(n2111), .B1(n2174),
.Y(n2176) );
AOI211X1TS U3042 ( .A0(n2914), .A1(n2178), .B0(n2177), .C0(n2176), .Y(n2196)
);
INVX2TS U3043 ( .A(n2178), .Y(n2940) );
OAI22X1TS U3044 ( .A0(n3241), .A1(n2196), .B0(n2940), .B1(n3238), .Y(n3243)
);
AOI22X1TS U3045 ( .A0(Data_array_SWR[30]), .A1(n2885), .B0(
Data_array_SWR[26]), .B1(n2904), .Y(n2179) );
OAI2BB1X1TS U3046 ( .A0N(n1880), .A1N(n2180), .B0(n2179), .Y(n2181) );
AOI22X1TS U3047 ( .A0(n1869), .A1(n2934), .B0(Data_array_SWR[11]), .B1(n2935), .Y(n2183) );
AOI22X1TS U3048 ( .A0(Data_array_SWR[17]), .A1(n2936), .B0(Data_array_SWR[7]), .B1(n2933), .Y(n2182) );
AOI21X1TS U3049 ( .A0(n2914), .A1(n2949), .B0(n2184), .Y(n2195) );
OAI22X1TS U3050 ( .A0(n2195), .A1(n2915), .B0(n2926), .B1(n2966), .Y(n2917)
);
AOI22X1TS U3051 ( .A0(n1879), .A1(n2904), .B0(Data_array_SWR[20]), .B1(n2896), .Y(n2185) );
AOI22X1TS U3052 ( .A0(n1871), .A1(n2934), .B0(Data_array_SWR[10]), .B1(n2106), .Y(n2187) );
AOI22X1TS U3053 ( .A0(Data_array_SWR[16]), .A1(n2936), .B0(Data_array_SWR[6]), .B1(n2910), .Y(n2186) );
AOI21X1TS U3054 ( .A0(n2914), .A1(n2955), .B0(n2188), .Y(n2916) );
OAI22X1TS U3055 ( .A0(n3241), .A1(n2916), .B0(n2923), .B1(n3238), .Y(n3242)
);
AOI22X1TS U3056 ( .A0(Data_array_SWR[27]), .A1(n2904), .B0(
Data_array_SWR[21]), .B1(n2905), .Y(n2189) );
AOI22X1TS U3057 ( .A0(Data_array_SWR[12]), .A1(n2935), .B0(
Data_array_SWR[14]), .B1(n2886), .Y(n2192) );
AOI22X1TS U3058 ( .A0(Data_array_SWR[8]), .A1(n2933), .B0(Data_array_SWR[18]), .B1(n2895), .Y(n2191) );
AOI21X1TS U3059 ( .A0(n2914), .A1(n2943), .B0(n2193), .Y(n2194) );
OAI22X1TS U3060 ( .A0(n3241), .A1(n2194), .B0(n2930), .B1(n3238), .Y(n3257)
);
OAI22X1TS U3061 ( .A0(n2194), .A1(n2915), .B0(n2930), .B1(n2966), .Y(n2918)
);
OAI22X1TS U3062 ( .A0(n3241), .A1(n2195), .B0(n2926), .B1(n3238), .Y(n3251)
);
OAI22X1TS U3063 ( .A0(n2940), .A1(n2966), .B0(n2196), .B1(n1804), .Y(n2920)
);
AOI22X1TS U3064 ( .A0(Data_array_SWR[19]), .A1(n2934), .B0(
Data_array_SWR[13]), .B1(n2910), .Y(n2198) );
AOI22X1TS U3065 ( .A0(Data_array_SWR[15]), .A1(n2935), .B0(
Data_array_SWR[22]), .B1(n2895), .Y(n2197) );
OAI211X1TS U3066 ( .A0(n3239), .A1(n2199), .B0(n2198), .C0(n2197), .Y(n2231)
);
AOI22X1TS U3067 ( .A0(n1878), .A1(n2885), .B0(Data_array_SWR[32]), .B1(n2884), .Y(n2201) );
AOI22X1TS U3068 ( .A0(Data_array_SWR[28]), .A1(n2897), .B0(
Data_array_SWR[25]), .B1(n2896), .Y(n2200) );
NAND2X1TS U3069 ( .A(n2201), .B(n2200), .Y(n2961) );
AOI22X1TS U3070 ( .A0(Data_array_SWR[37]), .A1(n2904), .B0(
Data_array_SWR[41]), .B1(n2103), .Y(n2203) );
AOI22X1TS U3071 ( .A0(n1878), .A1(n2909), .B0(Data_array_SWR[32]), .B1(n2896), .Y(n2202) );
NAND2X2TS U3072 ( .A(n2203), .B(n2202), .Y(n2963) );
AOI21X1TS U3073 ( .A0(n2231), .A1(n2915), .B0(n2204), .Y(n2282) );
BUFX3TS U3074 ( .A(n3247), .Y(n2246) );
OAI2BB2XLTS U3075 ( .B0(n2282), .B1(n2246), .A0N(final_result_ieee[13]),
.A1N(n3272), .Y(n1084) );
AOI22X1TS U3076 ( .A0(Data_array_SWR[21]), .A1(n2934), .B0(
Data_array_SWR[18]), .B1(n2935), .Y(n2209) );
AOI22X1TS U3077 ( .A0(n1881), .A1(n2936), .B0(Data_array_SWR[14]), .B1(n2933), .Y(n2208) );
AOI22X1TS U3078 ( .A0(Data_array_SWR[36]), .A1(n2103), .B0(
Data_array_SWR[34]), .B1(n2884), .Y(n2206) );
AOI22X1TS U3079 ( .A0(Data_array_SWR[27]), .A1(n2905), .B0(
Data_array_SWR[31]), .B1(n2887), .Y(n2205) );
NAND2X1TS U3080 ( .A(n2206), .B(n2205), .Y(n2869) );
INVX2TS U3081 ( .A(n3234), .Y(n2244) );
AOI22X1TS U3082 ( .A0(n2213), .A1(n2869), .B0(n2914), .B1(n2244), .Y(n2207)
);
AOI22X1TS U3083 ( .A0(Data_array_SWR[38]), .A1(n2885), .B0(
Data_array_SWR[35]), .B1(n2884), .Y(n2210) );
AOI21X1TS U3084 ( .A0(Data_array_SWR[33]), .A1(n2887), .B0(n2211), .Y(n2235)
);
AOI22X1TS U3085 ( .A0(left_right_SHT2), .A1(n2212), .B0(n2227), .B1(n2882),
.Y(n2288) );
OAI2BB2XLTS U3086 ( .B0(n2288), .B1(n2246), .A0N(final_result_ieee[34]),
.A1N(n3219), .Y(n1069) );
AOI22X1TS U3087 ( .A0(n2882), .A1(n2230), .B0(n2212), .B1(n2915), .Y(n2280)
);
OAI2BB2XLTS U3088 ( .B0(n2280), .B1(n2246), .A0N(final_result_ieee[16]),
.A1N(n3278), .Y(n1070) );
AOI22X1TS U3089 ( .A0(Data_array_SWR[17]), .A1(n2935), .B0(n1880), .B1(n2886), .Y(n2216) );
AOI22X1TS U3090 ( .A0(n1869), .A1(n2933), .B0(Data_array_SWR[24]), .B1(n2895), .Y(n2215) );
INVX2TS U3091 ( .A(n3231), .Y(n2242) );
AOI22X1TS U3092 ( .A0(n2213), .A1(n2241), .B0(n2914), .B1(n2242), .Y(n2214)
);
AOI22X1TS U3093 ( .A0(n1876), .A1(n2904), .B0(Data_array_SWR[30]), .B1(n2896), .Y(n2217) );
OAI2BB1X1TS U3094 ( .A0N(Data_array_SWR[39]), .A1N(n2103), .B0(n2217), .Y(
n2218) );
AOI21X1TS U3095 ( .A0(n1877), .A1(n2887), .B0(n2218), .Y(n2240) );
AOI22X1TS U3096 ( .A0(left_right_SHT2), .A1(n2229), .B0(n2227), .B1(n2893),
.Y(n2290) );
OAI2BB2XLTS U3097 ( .B0(n2290), .B1(n2246), .A0N(final_result_ieee[35]),
.A1N(n3136), .Y(n1061) );
AOI22X1TS U3098 ( .A0(Data_array_SWR[37]), .A1(n2885), .B0(n1878), .B1(n2884), .Y(n2219) );
AOI21X1TS U3099 ( .A0(Data_array_SWR[32]), .A1(n2909), .B0(n2221), .Y(n2226)
);
AOI22X1TS U3100 ( .A0(Data_array_SWR[19]), .A1(n2935), .B0(
Data_array_SWR[15]), .B1(n2933), .Y(n2224) );
OAI2BB2XLTS U3101 ( .B0(n3395), .B1(n2236), .A0N(Data_array_SWR[22]), .A1N(
n2886), .Y(n2222) );
AOI21X1TS U3102 ( .A0(Data_array_SWR[25]), .A1(n2895), .B0(n2222), .Y(n2223)
);
OAI211X1TS U3103 ( .A0(n2226), .A1(n2939), .B0(n2224), .C0(n2223), .Y(n2228)
);
AOI22X1TS U3104 ( .A0(left_right_SHT2), .A1(n2228), .B0(n2227), .B1(n2875),
.Y(n2298) );
OAI2BB2XLTS U3105 ( .B0(n2298), .B1(n2246), .A0N(final_result_ieee[33]),
.A1N(n2318), .Y(n1073) );
AOI22X1TS U3106 ( .A0(n2228), .A1(n2915), .B0(n2230), .B1(n2875), .Y(n2294)
);
OAI2BB2XLTS U3107 ( .B0(n2294), .B1(n2246), .A0N(final_result_ieee[17]),
.A1N(n3272), .Y(n1074) );
AOI22X1TS U3108 ( .A0(n2230), .A1(n2893), .B0(n2229), .B1(n2915), .Y(n2284)
);
OAI2BB2XLTS U3109 ( .B0(n2284), .B1(n2246), .A0N(final_result_ieee[15]),
.A1N(n3219), .Y(n1062) );
OAI2BB2XLTS U3110 ( .B0(n2300), .B1(n2246), .A0N(final_result_ieee[37]),
.A1N(n3278), .Y(n1081) );
AOI22X1TS U3111 ( .A0(Data_array_SWR[20]), .A1(n2935), .B0(
Data_array_SWR[16]), .B1(n2933), .Y(n2234) );
OAI2BB2XLTS U3112 ( .B0(n1826), .B1(n2236), .A0N(Data_array_SWR[23]), .A1N(
n2886), .Y(n2232) );
AOI21X1TS U3113 ( .A0(n1879), .A1(n2895), .B0(n2232), .Y(n2233) );
OAI211X1TS U3114 ( .A0(n2235), .A1(n2939), .B0(n2234), .C0(n2233), .Y(n2245)
);
OAI2BB2XLTS U3115 ( .B0(n2333), .B1(n2246), .A0N(final_result_ieee[32]),
.A1N(n3136), .Y(n1071) );
AOI22X1TS U3116 ( .A0(Data_array_SWR[17]), .A1(n2933), .B0(n1880), .B1(n2935), .Y(n2239) );
OAI2BB2XLTS U3117 ( .B0(n3407), .B1(n2236), .A0N(Data_array_SWR[24]), .A1N(
n2886), .Y(n2237) );
AOI21X1TS U3118 ( .A0(Data_array_SWR[26]), .A1(n2895), .B0(n2237), .Y(n2238)
);
OAI211X1TS U3119 ( .A0(n2240), .A1(n2939), .B0(n2239), .C0(n2238), .Y(n2243)
);
OAI2BB2XLTS U3120 ( .B0(n2325), .B1(n2246), .A0N(final_result_ieee[31]),
.A1N(n2318), .Y(n1063) );
AOI222X1TS U3121 ( .A0(n2243), .A1(n1804), .B0(n2242), .B1(n2960), .C0(n2241), .C1(n2962), .Y(n2331) );
OAI2BB2XLTS U3122 ( .B0(n2331), .B1(n2246), .A0N(final_result_ieee[19]),
.A1N(n3272), .Y(n1064) );
AOI222X1TS U3123 ( .A0(n2245), .A1(n1804), .B0(n2244), .B1(n2960), .C0(n2869), .C1(n2962), .Y(n2323) );
OAI2BB2XLTS U3124 ( .B0(n2323), .B1(n2246), .A0N(final_result_ieee[18]),
.A1N(n3219), .Y(n1072) );
BUFX4TS U3125 ( .A(OP_FLAG_SFG), .Y(n2986) );
XOR2X1TS U3126 ( .A(n2986), .B(DmP_mant_SFG_SWR[14]), .Y(n2839) );
OAI21XLTS U3127 ( .A0(n2839), .A1(DMP_SFG[12]), .B0(Shift_reg_FLAGS_7[2]),
.Y(n2247) );
OAI21XLTS U3128 ( .A0(Shift_reg_FLAGS_7[2]), .A1(n3427), .B0(n2247), .Y(
n1142) );
OAI21XLTS U3129 ( .A0(n3223), .A1(n1804), .B0(n3137), .Y(n1729) );
BUFX3TS U3130 ( .A(n3431), .Y(n3218) );
NAND2X4TS U3131 ( .A(n2844), .B(n2274), .Y(n2277) );
MXI2X1TS U3132 ( .A(Raw_mant_NRM_SWR[11]), .B(DMP_SFG[9]), .S0(n2274), .Y(
n2250) );
NAND2X1TS U3133 ( .A(n1805), .B(DmP_mant_SFG_SWR[11]), .Y(n2249) );
MXI2X1TS U3134 ( .A(Raw_mant_NRM_SWR[8]), .B(DMP_SFG[6]), .S0(n2274), .Y(
n2252) );
NAND2X1TS U3135 ( .A(n1805), .B(DmP_mant_SFG_SWR[8]), .Y(n2251) );
OAI211XLTS U3136 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n2277), .B0(n2252), .C0(
n2251), .Y(n1118) );
MXI2X1TS U3137 ( .A(Raw_mant_NRM_SWR[10]), .B(DMP_SFG[8]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n2254) );
NAND2X1TS U3138 ( .A(n1805), .B(DmP_mant_SFG_SWR[10]), .Y(n2253) );
OAI211XLTS U3139 ( .A0(DmP_mant_SFG_SWR[10]), .A1(n2277), .B0(n2254), .C0(
n2253), .Y(n1096) );
AOI22X1TS U3140 ( .A0(n1805), .A1(n1860), .B0(Raw_mant_NRM_SWR[0]), .B1(
n3218), .Y(n2255) );
OAI21XLTS U3141 ( .A0(n1860), .A1(n2277), .B0(n2255), .Y(n1136) );
MXI2X1TS U3142 ( .A(Raw_mant_NRM_SWR[9]), .B(DMP_SFG[7]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n2257) );
NAND2X1TS U3143 ( .A(n1805), .B(DmP_mant_SFG_SWR[9]), .Y(n2256) );
OAI211XLTS U3144 ( .A0(DmP_mant_SFG_SWR[9]), .A1(n2277), .B0(n2257), .C0(
n2256), .Y(n1104) );
MXI2X1TS U3145 ( .A(Raw_mant_NRM_SWR[5]), .B(DMP_SFG[3]), .S0(n2274), .Y(
n2260) );
NAND2X1TS U3146 ( .A(n1805), .B(DmP_mant_SFG_SWR[5]), .Y(n2259) );
OAI211XLTS U3147 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n2277), .B0(n2260), .C0(
n2259), .Y(n1131) );
MXI2X1TS U3148 ( .A(Raw_mant_NRM_SWR[3]), .B(DMP_SFG[1]), .S0(n2274), .Y(
n2262) );
NAND2X1TS U3149 ( .A(n1805), .B(n1858), .Y(n2261) );
OAI211XLTS U3150 ( .A0(n1858), .A1(n2277), .B0(n2262), .C0(n2261), .Y(n1128)
);
MXI2X1TS U3151 ( .A(Raw_mant_NRM_SWR[6]), .B(DMP_SFG[4]), .S0(n2274), .Y(
n2264) );
NAND2X1TS U3152 ( .A(n1805), .B(DmP_mant_SFG_SWR[6]), .Y(n2263) );
MXI2X1TS U3153 ( .A(Raw_mant_NRM_SWR[13]), .B(DMP_SFG[11]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n2266) );
NAND2BXLTS U3154 ( .AN(n3433), .B(n1805), .Y(n2265) );
OAI211XLTS U3155 ( .A0(DmP_mant_SFG_SWR[13]), .A1(n2277), .B0(n2266), .C0(
n2265), .Y(n1110) );
MXI2X1TS U3156 ( .A(Raw_mant_NRM_SWR[12]), .B(DMP_SFG[10]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n2268) );
NAND2BXLTS U3157 ( .AN(n3432), .B(n1805), .Y(n2267) );
MXI2X1TS U3158 ( .A(Raw_mant_NRM_SWR[2]), .B(DMP_SFG[0]), .S0(n2274), .Y(
n2270) );
NAND2X1TS U3159 ( .A(n1805), .B(DmP_mant_SFG_SWR[2]), .Y(n2269) );
OAI211XLTS U3160 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n2277), .B0(n2270), .C0(
n2269), .Y(n1133) );
MXI2X1TS U3161 ( .A(Raw_mant_NRM_SWR[4]), .B(DMP_SFG[2]), .S0(n2274), .Y(
n2272) );
NAND2X1TS U3162 ( .A(n1805), .B(DmP_mant_SFG_SWR[4]), .Y(n2271) );
OAI211XLTS U3163 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n2277), .B0(n2272), .C0(
n2271), .Y(n1126) );
AOI22X1TS U3164 ( .A0(n1805), .A1(n1861), .B0(Raw_mant_NRM_SWR[1]), .B1(
n3431), .Y(n2273) );
OAI21XLTS U3165 ( .A0(n1861), .A1(n2277), .B0(n2273), .Y(n1139) );
MXI2X1TS U3166 ( .A(Raw_mant_NRM_SWR[7]), .B(DMP_SFG[5]), .S0(n2274), .Y(
n2276) );
NAND2X1TS U3167 ( .A(n1805), .B(n1857), .Y(n2275) );
OAI211XLTS U3168 ( .A0(n1857), .A1(n2277), .B0(n2276), .C0(n2275), .Y(n1120)
);
AOI2BB2XLTS U3169 ( .B0(beg_OP), .B1(n3304), .A0N(n3304), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2278) );
NAND3XLTS U3170 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3304), .C(
n3390), .Y(n3131) );
OAI21XLTS U3171 ( .A0(n3130), .A1(n2278), .B0(n3131), .Y(n1802) );
INVX4TS U3172 ( .A(n3217), .Y(n2919) );
NAND2X1TS U3173 ( .A(n2336), .B(DmP_mant_SFG_SWR[18]), .Y(n2279) );
NAND2X1TS U3174 ( .A(n2336), .B(DmP_mant_SFG_SWR[15]), .Y(n2281) );
NAND2X1TS U3175 ( .A(DmP_mant_SFG_SWR[17]), .B(n2336), .Y(n2283) );
NAND2X1TS U3176 ( .A(n2336), .B(DmP_mant_SFG_SWR[16]), .Y(n2285) );
INVX4TS U3177 ( .A(n3185), .Y(n2484) );
NAND2X1TS U3178 ( .A(n2484), .B(DmP_mant_SFG_SWR[36]), .Y(n2287) );
NAND2X1TS U3179 ( .A(n2484), .B(DmP_mant_SFG_SWR[37]), .Y(n2289) );
NAND2X1TS U3180 ( .A(n2484), .B(DmP_mant_SFG_SWR[38]), .Y(n2291) );
NAND2X1TS U3181 ( .A(n2336), .B(DmP_mant_SFG_SWR[19]), .Y(n2293) );
NAND2X1TS U3182 ( .A(n2336), .B(DmP_mant_SFG_SWR[14]), .Y(n2295) );
NAND2X1TS U3183 ( .A(n2484), .B(DmP_mant_SFG_SWR[35]), .Y(n2297) );
NAND2X1TS U3184 ( .A(n2484), .B(DmP_mant_SFG_SWR[39]), .Y(n2299) );
NAND2X1TS U3185 ( .A(n3272), .B(final_result_ieee[59]), .Y(n2301) );
INVX2TS U3186 ( .A(exp_rslt_NRM2_EW1[4]), .Y(n2304) );
NAND2X1TS U3187 ( .A(n3278), .B(final_result_ieee[56]), .Y(n2303) );
NAND2X1TS U3188 ( .A(n3278), .B(final_result_ieee[58]), .Y(n2305) );
NAND2X1TS U3189 ( .A(n2318), .B(final_result_ieee[52]), .Y(n2307) );
INVX2TS U3190 ( .A(exp_rslt_NRM2_EW1[5]), .Y(n2310) );
NAND2X1TS U3191 ( .A(n3136), .B(final_result_ieee[57]), .Y(n2309) );
NAND2X1TS U3192 ( .A(n3136), .B(final_result_ieee[61]), .Y(n2311) );
NAND2X1TS U3193 ( .A(n3219), .B(final_result_ieee[55]), .Y(n2313) );
NAND2X1TS U3194 ( .A(n3272), .B(final_result_ieee[60]), .Y(n2315) );
NAND2X1TS U3195 ( .A(n2318), .B(final_result_ieee[54]), .Y(n2317) );
NAND2X1TS U3196 ( .A(n3272), .B(final_result_ieee[53]), .Y(n2320) );
NAND2X1TS U3197 ( .A(n2336), .B(DmP_mant_SFG_SWR[20]), .Y(n2322) );
NAND2X1TS U3198 ( .A(n2336), .B(DmP_mant_SFG_SWR[33]), .Y(n2324) );
NAND2X1TS U3199 ( .A(n2336), .B(DmP_mant_SFG_SWR[32]), .Y(n2326) );
NAND2X1TS U3200 ( .A(n2336), .B(DmP_mant_SFG_SWR[22]), .Y(n2328) );
NAND2X1TS U3201 ( .A(n2336), .B(DmP_mant_SFG_SWR[21]), .Y(n2330) );
NAND2X1TS U3202 ( .A(n2484), .B(DmP_mant_SFG_SWR[34]), .Y(n2332) );
NAND2X1TS U3203 ( .A(n2484), .B(DmP_mant_SFG_SWR[41]), .Y(n2334) );
NAND2X1TS U3204 ( .A(n2336), .B(DmP_mant_SFG_SWR[42]), .Y(n2337) );
NOR2X1TS U3205 ( .A(n3428), .B(intDY_EWSW[53]), .Y(n2339) );
OAI22X1TS U3206 ( .A0(n3429), .A1(intDY_EWSW[55]), .B0(intDY_EWSW[54]), .B1(
n3320), .Y(n2458) );
NOR2BX1TS U3207 ( .AN(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n2340) );
NOR2X1TS U3208 ( .A(n3350), .B(intDY_EWSW[57]), .Y(n2412) );
NAND2X1TS U3209 ( .A(n3325), .B(intDX_EWSW[61]), .Y(n2418) );
OAI211X1TS U3210 ( .A0(intDY_EWSW[60]), .A1(n3393), .B0(n2422), .C0(n2418),
.Y(n2424) );
OAI21X1TS U3211 ( .A0(intDY_EWSW[58]), .A1(n3392), .B0(n2414), .Y(n2416) );
NOR2X1TS U3212 ( .A(n3414), .B(intDY_EWSW[49]), .Y(n2461) );
OAI21X1TS U3213 ( .A0(intDY_EWSW[50]), .A1(n3293), .B0(n2463), .Y(n2467) );
AOI211X1TS U3214 ( .A0(intDX_EWSW[48]), .A1(n3381), .B0(n2461), .C0(n2467),
.Y(n2341) );
NAND3X1TS U3215 ( .A(n2460), .B(n2469), .C(n2341), .Y(n2477) );
NOR2BX1TS U3216 ( .AN(intDX_EWSW[39]), .B(intDY_EWSW[39]), .Y(n2452) );
AOI21X1TS U3217 ( .A0(intDX_EWSW[38]), .A1(n3422), .B0(n2452), .Y(n2451) );
NAND2X1TS U3218 ( .A(n3396), .B(intDX_EWSW[37]), .Y(n2440) );
OAI211X1TS U3219 ( .A0(intDY_EWSW[36]), .A1(n3340), .B0(n2451), .C0(n2440),
.Y(n2442) );
NOR2X1TS U3220 ( .A(n3346), .B(intDY_EWSW[45]), .Y(n2426) );
OAI21X1TS U3221 ( .A0(intDY_EWSW[46]), .A1(n3326), .B0(n2425), .Y(n2435) );
OA22X1TS U3222 ( .A0(n3334), .A1(intDY_EWSW[42]), .B0(n3288), .B1(
intDY_EWSW[43]), .Y(n2431) );
NAND4X1TS U3223 ( .A(n2433), .B(n2431), .C(n2343), .D(n2342), .Y(n2475) );
OA22X1TS U3224 ( .A0(n3335), .A1(intDY_EWSW[34]), .B0(n3289), .B1(
intDY_EWSW[35]), .Y(n2446) );
NOR4X1TS U3225 ( .A(n2477), .B(n2442), .C(n2475), .D(n2345), .Y(n2481) );
OAI2BB2XLTS U3226 ( .B0(intDX_EWSW[28]), .B1(n2346), .A0N(intDY_EWSW[29]),
.A1N(n3342), .Y(n2355) );
OAI21X1TS U3227 ( .A0(intDY_EWSW[26]), .A1(n3359), .B0(n2349), .Y(n2407) );
NOR2X1TS U3228 ( .A(n3347), .B(intDY_EWSW[25]), .Y(n2404) );
AOI22X1TS U3229 ( .A0(n2348), .A1(intDY_EWSW[24]), .B0(intDY_EWSW[25]), .B1(
n3347), .Y(n2351) );
AOI32X1TS U3230 ( .A0(n3359), .A1(n2349), .A2(intDY_EWSW[26]), .B0(
intDY_EWSW[27]), .B1(n3294), .Y(n2350) );
OAI32X1TS U3231 ( .A0(n2407), .A1(n2406), .A2(n2351), .B0(n2350), .B1(n2406),
.Y(n2354) );
OAI2BB2XLTS U3232 ( .B0(intDX_EWSW[30]), .B1(n2352), .A0N(intDY_EWSW[31]),
.A1N(n3290), .Y(n2353) );
AOI211X1TS U3233 ( .A0(n2356), .A1(n2355), .B0(n2354), .C0(n2353), .Y(n2411)
);
OAI2BB1X1TS U3234 ( .A0N(n2606), .A1N(intDX_EWSW[5]), .B0(intDY_EWSW[4]),
.Y(n2359) );
OAI22X1TS U3235 ( .A0(intDX_EWSW[4]), .A1(n2359), .B0(n2606), .B1(
intDX_EWSW[5]), .Y(n2370) );
OAI2BB1X1TS U3236 ( .A0N(n2582), .A1N(intDX_EWSW[7]), .B0(intDY_EWSW[6]),
.Y(n2360) );
OAI22X1TS U3237 ( .A0(intDX_EWSW[6]), .A1(n2360), .B0(n2582), .B1(
intDX_EWSW[7]), .Y(n2369) );
NAND2BXLTS U3238 ( .AN(intDY_EWSW[2]), .B(intDX_EWSW[2]), .Y(n2363) );
AOI2BB2XLTS U3239 ( .B0(intDX_EWSW[1]), .B1(n3421), .A0N(n1868), .A1N(n2361),
.Y(n2362) );
OAI21XLTS U3240 ( .A0(intDY_EWSW[3]), .A1(n3331), .B0(intDY_EWSW[2]), .Y(
n2364) );
AOI2BB2XLTS U3241 ( .B0(intDY_EWSW[3]), .B1(n3331), .A0N(intDX_EWSW[2]),
.A1N(n2364), .Y(n2365) );
OAI32X1TS U3242 ( .A0(n2370), .A1(n2369), .A2(n2368), .B0(n2367), .B1(n2369),
.Y(n2387) );
NOR2X1TS U3243 ( .A(n3330), .B(intDY_EWSW[11]), .Y(n2372) );
AOI21X1TS U3244 ( .A0(intDX_EWSW[10]), .A1(n3369), .B0(n2372), .Y(n2377) );
OAI21XLTS U3245 ( .A0(intDY_EWSW[13]), .A1(n3343), .B0(intDY_EWSW[12]), .Y(
n2371) );
OAI2BB2XLTS U3246 ( .B0(intDX_EWSW[12]), .B1(n2371), .A0N(intDY_EWSW[13]),
.A1N(n3343), .Y(n2383) );
AOI22X1TS U3247 ( .A0(intDY_EWSW[11]), .A1(n3330), .B0(intDY_EWSW[10]), .B1(
n2373), .Y(n2379) );
AOI21X1TS U3248 ( .A0(n2376), .A1(n2375), .B0(n2388), .Y(n2378) );
OAI2BB2XLTS U3249 ( .B0(n2379), .B1(n2388), .A0N(n2378), .A1N(n2377), .Y(
n2382) );
OAI2BB2XLTS U3250 ( .B0(intDX_EWSW[14]), .B1(n2380), .A0N(intDY_EWSW[15]),
.A1N(n3287), .Y(n2381) );
AOI211X1TS U3251 ( .A0(n2384), .A1(n2383), .B0(n2382), .C0(n2381), .Y(n2385)
);
OAI31X1TS U3252 ( .A0(n2388), .A1(n2387), .A2(n2386), .B0(n2385), .Y(n2390)
);
NOR2X1TS U3253 ( .A(n3348), .B(intDY_EWSW[17]), .Y(n2392) );
OAI21X1TS U3254 ( .A0(intDY_EWSW[18]), .A1(n3360), .B0(n2394), .Y(n2398) );
AOI211X1TS U3255 ( .A0(intDX_EWSW[16]), .A1(n3382), .B0(n2392), .C0(n2398),
.Y(n2389) );
OAI21XLTS U3256 ( .A0(intDY_EWSW[21]), .A1(n3357), .B0(intDY_EWSW[20]), .Y(
n2391) );
OAI2BB2XLTS U3257 ( .B0(intDX_EWSW[20]), .B1(n2391), .A0N(intDY_EWSW[21]),
.A1N(n3357), .Y(n2402) );
AOI22X1TS U3258 ( .A0(n2393), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]), .B1(
n3348), .Y(n2396) );
AOI32X1TS U3259 ( .A0(n3360), .A1(n2394), .A2(intDY_EWSW[18]), .B0(
intDY_EWSW[19]), .B1(n3295), .Y(n2395) );
OAI32X1TS U3260 ( .A0(n2398), .A1(n2397), .A2(n2396), .B0(n2395), .B1(n2397),
.Y(n2401) );
OAI21XLTS U3261 ( .A0(intDY_EWSW[23]), .A1(n3291), .B0(intDY_EWSW[22]), .Y(
n2399) );
OAI2BB2XLTS U3262 ( .B0(intDX_EWSW[22]), .B1(n2399), .A0N(intDY_EWSW[23]),
.A1N(n3291), .Y(n2400) );
AOI211X1TS U3263 ( .A0(n2403), .A1(n2402), .B0(n2401), .C0(n2400), .Y(n2409)
);
NOR2BX1TS U3264 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n2405) );
OR4X2TS U3265 ( .A(n2407), .B(n2406), .C(n2405), .D(n2404), .Y(n2408) );
AOI32X1TS U3266 ( .A0(n2411), .A1(n2410), .A2(n2409), .B0(n2408), .B1(n2411),
.Y(n2480) );
AOI22X1TS U3267 ( .A0(intDY_EWSW[57]), .A1(n3350), .B0(intDY_EWSW[56]), .B1(
n2413), .Y(n2417) );
OA21XLTS U3268 ( .A0(n2417), .A1(n2416), .B0(n2415), .Y(n2423) );
OAI2BB2XLTS U3269 ( .B0(n2424), .B1(n2423), .A0N(n2422), .A1N(n2421), .Y(
n2479) );
NOR2BX1TS U3270 ( .AN(n2425), .B(intDX_EWSW[46]), .Y(n2439) );
AOI22X1TS U3271 ( .A0(intDY_EWSW[45]), .A1(n3346), .B0(intDY_EWSW[44]), .B1(
n2427), .Y(n2436) );
OAI2BB2XLTS U3272 ( .B0(intDX_EWSW[40]), .B1(n2428), .A0N(intDY_EWSW[41]),
.A1N(n3341), .Y(n2432) );
OAI2BB2XLTS U3273 ( .B0(intDX_EWSW[42]), .B1(n2429), .A0N(intDY_EWSW[43]),
.A1N(n3288), .Y(n2430) );
AOI32X1TS U3274 ( .A0(n2433), .A1(n2432), .A2(n2431), .B0(n2430), .B1(n2433),
.Y(n2434) );
NOR2BX1TS U3275 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2437) );
AOI211X1TS U3276 ( .A0(intDY_EWSW[46]), .A1(n2439), .B0(n2438), .C0(n2437),
.Y(n2476) );
INVX2TS U3277 ( .A(n2442), .Y(n2448) );
OAI21XLTS U3278 ( .A0(intDY_EWSW[33]), .A1(n3333), .B0(intDY_EWSW[32]), .Y(
n2443) );
OAI2BB2XLTS U3279 ( .B0(intDX_EWSW[32]), .B1(n2443), .A0N(intDY_EWSW[33]),
.A1N(n3333), .Y(n2447) );
OAI21XLTS U3280 ( .A0(intDY_EWSW[35]), .A1(n3289), .B0(intDY_EWSW[34]), .Y(
n2444) );
OAI2BB2XLTS U3281 ( .B0(intDX_EWSW[34]), .B1(n2444), .A0N(intDY_EWSW[35]),
.A1N(n3289), .Y(n2445) );
AOI32X1TS U3282 ( .A0(n2448), .A1(n2447), .A2(n2446), .B0(n2445), .B1(n2448),
.Y(n2449) );
OAI2BB1X1TS U3283 ( .A0N(n2451), .A1N(n2450), .B0(n2449), .Y(n2456) );
NOR2BX1TS U3284 ( .AN(intDY_EWSW[39]), .B(intDX_EWSW[39]), .Y(n2455) );
NOR3X1TS U3285 ( .A(n3422), .B(n2452), .C(intDX_EWSW[38]), .Y(n2454) );
INVX2TS U3286 ( .A(n2477), .Y(n2453) );
OAI31X1TS U3287 ( .A0(n2456), .A1(n2455), .A2(n2454), .B0(n2453), .Y(n2474)
);
INVX2TS U3288 ( .A(n2460), .Y(n2466) );
AOI22X1TS U3289 ( .A0(intDY_EWSW[49]), .A1(n3414), .B0(intDY_EWSW[48]), .B1(
n2462), .Y(n2465) );
AOI32X1TS U3290 ( .A0(n3293), .A1(n2463), .A2(intDY_EWSW[50]), .B0(
intDY_EWSW[51]), .B1(n3354), .Y(n2464) );
OAI32X1TS U3291 ( .A0(n2467), .A1(n2466), .A2(n2465), .B0(n2464), .B1(n2466),
.Y(n2471) );
OAI2BB2XLTS U3292 ( .B0(intDX_EWSW[54]), .B1(n2468), .A0N(intDY_EWSW[55]),
.A1N(n3429), .Y(n2470) );
OAI31X1TS U3293 ( .A0(n2472), .A1(n2471), .A2(n2470), .B0(n2469), .Y(n2473)
);
AOI211X1TS U3294 ( .A0(n2481), .A1(n2480), .B0(n2479), .C0(n2478), .Y(n2482)
);
AND2X4TS U3295 ( .A(n3211), .B(n2482), .Y(n2555) );
BUFX3TS U3296 ( .A(n2555), .Y(n2550) );
AOI22X1TS U3297 ( .A0(intDX_EWSW[14]), .A1(n2550), .B0(DMP_EXP_EWSW[14]),
.B1(n1887), .Y(n2483) );
NAND2X1TS U3298 ( .A(n2484), .B(DmP_mant_SFG_SWR[40]), .Y(n2485) );
BUFX4TS U3299 ( .A(n2555), .Y(n2541) );
AOI22X1TS U3300 ( .A0(intDX_EWSW[16]), .A1(n2541), .B0(DMP_EXP_EWSW[16]),
.B1(n1887), .Y(n2487) );
BUFX3TS U3301 ( .A(n2555), .Y(n2530) );
BUFX3TS U3302 ( .A(n2577), .Y(n2625) );
AOI22X1TS U3303 ( .A0(intDX_EWSW[48]), .A1(n2530), .B0(DMP_EXP_EWSW[48]),
.B1(n2625), .Y(n2488) );
AOI22X1TS U3304 ( .A0(intDX_EWSW[23]), .A1(n2541), .B0(DMP_EXP_EWSW[23]),
.B1(n2549), .Y(n2489) );
BUFX3TS U3305 ( .A(n2577), .Y(n2547) );
AOI22X1TS U3306 ( .A0(intDX_EWSW[49]), .A1(n2530), .B0(DMP_EXP_EWSW[49]),
.B1(n2547), .Y(n2490) );
AOI22X1TS U3307 ( .A0(intDX_EWSW[44]), .A1(n2530), .B0(DMP_EXP_EWSW[44]),
.B1(n2547), .Y(n2491) );
AOI22X1TS U3308 ( .A0(intDX_EWSW[21]), .A1(n2541), .B0(DMP_EXP_EWSW[21]),
.B1(n1887), .Y(n2492) );
AOI22X1TS U3309 ( .A0(intDX_EWSW[24]), .A1(n2541), .B0(DMP_EXP_EWSW[24]),
.B1(n2549), .Y(n2493) );
AOI22X1TS U3310 ( .A0(intDX_EWSW[17]), .A1(n2541), .B0(DMP_EXP_EWSW[17]),
.B1(n1887), .Y(n2494) );
AOI22X1TS U3311 ( .A0(intDX_EWSW[27]), .A1(n2541), .B0(DMP_EXP_EWSW[27]),
.B1(n2549), .Y(n2495) );
AOI22X1TS U3312 ( .A0(intDX_EWSW[47]), .A1(n2530), .B0(DMP_EXP_EWSW[47]),
.B1(n2547), .Y(n2496) );
AOI22X1TS U3313 ( .A0(intDX_EWSW[43]), .A1(n2530), .B0(DMP_EXP_EWSW[43]),
.B1(n2547), .Y(n2497) );
AOI22X1TS U3314 ( .A0(intDX_EWSW[40]), .A1(n2541), .B0(DMP_EXP_EWSW[40]),
.B1(n2547), .Y(n2498) );
AOI22X1TS U3315 ( .A0(intDX_EWSW[45]), .A1(n2530), .B0(DMP_EXP_EWSW[45]),
.B1(n2547), .Y(n2499) );
AOI22X1TS U3316 ( .A0(intDX_EWSW[41]), .A1(n2550), .B0(DMP_EXP_EWSW[41]),
.B1(n2547), .Y(n2500) );
AOI22X1TS U3317 ( .A0(intDX_EWSW[46]), .A1(n2530), .B0(DMP_EXP_EWSW[46]),
.B1(n2547), .Y(n2501) );
AOI22X1TS U3318 ( .A0(intDX_EWSW[42]), .A1(n2550), .B0(DMP_EXP_EWSW[42]),
.B1(n2547), .Y(n2502) );
BUFX3TS U3319 ( .A(n2555), .Y(n2590) );
AOI22X1TS U3320 ( .A0(intDX_EWSW[12]), .A1(n2590), .B0(DMP_EXP_EWSW[12]),
.B1(n1887), .Y(n2504) );
AOI22X1TS U3321 ( .A0(intDX_EWSW[19]), .A1(n2541), .B0(DMP_EXP_EWSW[19]),
.B1(n1887), .Y(n2505) );
AOI22X1TS U3322 ( .A0(intDX_EWSW[20]), .A1(n2530), .B0(DMP_EXP_EWSW[20]),
.B1(n1887), .Y(n2506) );
AOI22X1TS U3323 ( .A0(intDX_EWSW[28]), .A1(n2541), .B0(DMP_EXP_EWSW[28]),
.B1(n2549), .Y(n2507) );
AOI22X1TS U3324 ( .A0(intDX_EWSW[25]), .A1(n2541), .B0(DMP_EXP_EWSW[25]),
.B1(n2625), .Y(n2508) );
AOI22X1TS U3325 ( .A0(intDX_EWSW[50]), .A1(n2530), .B0(DMP_EXP_EWSW[50]),
.B1(n2625), .Y(n2509) );
AOI22X1TS U3326 ( .A0(intDX_EWSW[51]), .A1(n2530), .B0(DMP_EXP_EWSW[51]),
.B1(n2625), .Y(n2510) );
AOI22X1TS U3327 ( .A0(intDX_EWSW[0]), .A1(n2530), .B0(DMP_EXP_EWSW[0]), .B1(
n2629), .Y(n2511) );
INVX4TS U3328 ( .A(n2560), .Y(n2567) );
AOI22X1TS U3329 ( .A0(intDX_EWSW[31]), .A1(n2567), .B0(DmP_EXP_EWSW[31]),
.B1(n2577), .Y(n2512) );
AOI22X1TS U3330 ( .A0(intDX_EWSW[30]), .A1(n2567), .B0(DmP_EXP_EWSW[30]),
.B1(n2622), .Y(n2513) );
AOI22X1TS U3331 ( .A0(intDX_EWSW[27]), .A1(n2567), .B0(DmP_EXP_EWSW[27]),
.B1(n2622), .Y(n2514) );
AOI22X1TS U3332 ( .A0(intDX_EWSW[29]), .A1(n2567), .B0(DmP_EXP_EWSW[29]),
.B1(n2577), .Y(n2515) );
AOI22X1TS U3333 ( .A0(intDX_EWSW[25]), .A1(n2567), .B0(DmP_EXP_EWSW[25]),
.B1(n2625), .Y(n2516) );
AOI22X1TS U3334 ( .A0(intDX_EWSW[26]), .A1(n2567), .B0(DmP_EXP_EWSW[26]),
.B1(n2622), .Y(n2517) );
AOI22X1TS U3335 ( .A0(intDX_EWSW[28]), .A1(n2567), .B0(DmP_EXP_EWSW[28]),
.B1(n2577), .Y(n2518) );
INVX4TS U3336 ( .A(n2560), .Y(n2602) );
BUFX3TS U3337 ( .A(n2622), .Y(n3134) );
AOI22X1TS U3338 ( .A0(intDX_EWSW[46]), .A1(n2602), .B0(DmP_EXP_EWSW[46]),
.B1(n3134), .Y(n2519) );
AOI22X1TS U3339 ( .A0(intDX_EWSW[43]), .A1(n2602), .B0(DmP_EXP_EWSW[43]),
.B1(n3134), .Y(n2520) );
AOI22X1TS U3340 ( .A0(intDX_EWSW[34]), .A1(n2567), .B0(DmP_EXP_EWSW[34]),
.B1(n2577), .Y(n2521) );
AOI22X1TS U3341 ( .A0(intDX_EWSW[33]), .A1(n2567), .B0(DmP_EXP_EWSW[33]),
.B1(n2577), .Y(n2522) );
AOI22X1TS U3342 ( .A0(intDX_EWSW[42]), .A1(n2602), .B0(DmP_EXP_EWSW[42]),
.B1(n3134), .Y(n2523) );
AOI22X1TS U3343 ( .A0(intDX_EWSW[45]), .A1(n2602), .B0(DmP_EXP_EWSW[45]),
.B1(n3134), .Y(n2524) );
AOI22X1TS U3344 ( .A0(intDX_EWSW[36]), .A1(n2567), .B0(DmP_EXP_EWSW[36]),
.B1(n2577), .Y(n2525) );
AOI22X1TS U3345 ( .A0(intDX_EWSW[35]), .A1(n2567), .B0(DmP_EXP_EWSW[35]),
.B1(n2577), .Y(n2526) );
AOI22X1TS U3346 ( .A0(intDX_EWSW[41]), .A1(n2602), .B0(DmP_EXP_EWSW[41]),
.B1(n2577), .Y(n2527) );
BUFX3TS U3347 ( .A(n2560), .Y(n2552) );
AOI22X1TS U3348 ( .A0(intDX_EWSW[22]), .A1(n2550), .B0(DMP_EXP_EWSW[22]),
.B1(n2549), .Y(n2528) );
AOI22X1TS U3349 ( .A0(intDX_EWSW[38]), .A1(n2550), .B0(DMP_EXP_EWSW[38]),
.B1(n2547), .Y(n2529) );
BUFX3TS U3350 ( .A(n2560), .Y(n2605) );
AOI22X1TS U3351 ( .A0(intDX_EWSW[15]), .A1(n2530), .B0(DMP_EXP_EWSW[15]),
.B1(n1887), .Y(n2531) );
AOI22X1TS U3352 ( .A0(intDX_EWSW[30]), .A1(n2541), .B0(DMP_EXP_EWSW[30]),
.B1(n2549), .Y(n2532) );
AOI22X1TS U3353 ( .A0(intDX_EWSW[37]), .A1(n2550), .B0(DMP_EXP_EWSW[37]),
.B1(n2549), .Y(n2533) );
AOI22X1TS U3354 ( .A0(intDX_EWSW[31]), .A1(n2541), .B0(DMP_EXP_EWSW[31]),
.B1(n2549), .Y(n2534) );
AOI22X1TS U3355 ( .A0(intDX_EWSW[26]), .A1(n2541), .B0(DMP_EXP_EWSW[26]),
.B1(n2549), .Y(n2535) );
AOI22X1TS U3356 ( .A0(intDX_EWSW[13]), .A1(n2541), .B0(DMP_EXP_EWSW[13]),
.B1(n1887), .Y(n2536) );
AOI22X1TS U3357 ( .A0(intDX_EWSW[8]), .A1(n2590), .B0(DMP_EXP_EWSW[8]), .B1(
n1887), .Y(n2537) );
AOI22X1TS U3358 ( .A0(intDX_EWSW[18]), .A1(n2550), .B0(DMP_EXP_EWSW[18]),
.B1(n1887), .Y(n2538) );
AOI22X1TS U3359 ( .A0(intDX_EWSW[11]), .A1(n2590), .B0(DMP_EXP_EWSW[11]),
.B1(n1887), .Y(n2539) );
AOI22X1TS U3360 ( .A0(intDX_EWSW[3]), .A1(n2590), .B0(DMP_EXP_EWSW[3]), .B1(
n2629), .Y(n2540) );
AOI22X1TS U3361 ( .A0(intDX_EWSW[29]), .A1(n2541), .B0(DMP_EXP_EWSW[29]),
.B1(n2549), .Y(n2542) );
AOI22X1TS U3362 ( .A0(intDX_EWSW[32]), .A1(n2550), .B0(DMP_EXP_EWSW[32]),
.B1(n2549), .Y(n2543) );
AOI22X1TS U3363 ( .A0(intDX_EWSW[36]), .A1(n2550), .B0(DMP_EXP_EWSW[36]),
.B1(n2547), .Y(n2544) );
AOI22X1TS U3364 ( .A0(intDX_EWSW[39]), .A1(n2550), .B0(DMP_EXP_EWSW[39]),
.B1(n2547), .Y(n2545) );
AOI22X1TS U3365 ( .A0(intDX_EWSW[35]), .A1(n2550), .B0(DMP_EXP_EWSW[35]),
.B1(n2549), .Y(n2546) );
AOI22X1TS U3366 ( .A0(intDX_EWSW[33]), .A1(n2550), .B0(DMP_EXP_EWSW[33]),
.B1(n2547), .Y(n2548) );
AOI22X1TS U3367 ( .A0(intDX_EWSW[34]), .A1(n2550), .B0(DMP_EXP_EWSW[34]),
.B1(n2549), .Y(n2551) );
AOI22X1TS U3368 ( .A0(intDX_EWSW[7]), .A1(n2590), .B0(DMP_EXP_EWSW[7]), .B1(
n2629), .Y(n2553) );
INVX2TS U3369 ( .A(n2554), .Y(n2558) );
AOI22X1TS U3370 ( .A0(intDX_EWSW[63]), .A1(n2556), .B0(SIGN_FLAG_EXP), .B1(
n2625), .Y(n2557) );
INVX4TS U3371 ( .A(n2560), .Y(n2623) );
AOI22X1TS U3372 ( .A0(intDX_EWSW[23]), .A1(n2623), .B0(DmP_EXP_EWSW[23]),
.B1(n2622), .Y(n2561) );
INVX4TS U3373 ( .A(n2560), .Y(n2619) );
BUFX3TS U3374 ( .A(n2622), .Y(n2618) );
AOI22X1TS U3375 ( .A0(intDX_EWSW[8]), .A1(n2619), .B0(DmP_EXP_EWSW[8]), .B1(
n2618), .Y(n2562) );
AOI22X1TS U3376 ( .A0(intDX_EWSW[3]), .A1(n2619), .B0(DmP_EXP_EWSW[3]), .B1(
n2618), .Y(n2563) );
AOI22X1TS U3377 ( .A0(intDX_EWSW[32]), .A1(n2567), .B0(DmP_EXP_EWSW[32]),
.B1(n2577), .Y(n2564) );
AOI22X1TS U3378 ( .A0(intDX_EWSW[40]), .A1(n2602), .B0(DmP_EXP_EWSW[40]),
.B1(n2577), .Y(n2565) );
AOI22X1TS U3379 ( .A0(intDX_EWSW[47]), .A1(n2602), .B0(DmP_EXP_EWSW[47]),
.B1(n3134), .Y(n2566) );
AOI22X1TS U3380 ( .A0(intDX_EWSW[37]), .A1(n2567), .B0(DmP_EXP_EWSW[37]),
.B1(n2577), .Y(n2568) );
AOI22X1TS U3381 ( .A0(intDX_EWSW[38]), .A1(n2602), .B0(DmP_EXP_EWSW[38]),
.B1(n2577), .Y(n2569) );
AOI22X1TS U3382 ( .A0(intDX_EWSW[44]), .A1(n2602), .B0(DmP_EXP_EWSW[44]),
.B1(n3134), .Y(n2570) );
AOI22X1TS U3383 ( .A0(intDY_EWSW[62]), .A1(n2619), .B0(DMP_EXP_EWSW[62]),
.B1(n2625), .Y(n2571) );
AOI22X1TS U3384 ( .A0(intDY_EWSW[61]), .A1(n2602), .B0(DMP_EXP_EWSW[61]),
.B1(n2625), .Y(n2572) );
AOI22X1TS U3385 ( .A0(intDX_EWSW[6]), .A1(n2619), .B0(DmP_EXP_EWSW[6]), .B1(
n2618), .Y(n2573) );
AOI22X1TS U3386 ( .A0(intDX_EWSW[24]), .A1(n2623), .B0(DmP_EXP_EWSW[24]),
.B1(n2622), .Y(n2574) );
AOI22X1TS U3387 ( .A0(intDX_EWSW[9]), .A1(n2619), .B0(DmP_EXP_EWSW[9]), .B1(
n2618), .Y(n2575) );
AOI22X1TS U3388 ( .A0(intDX_EWSW[2]), .A1(n2619), .B0(DmP_EXP_EWSW[2]), .B1(
n2618), .Y(n2576) );
AOI22X1TS U3389 ( .A0(intDX_EWSW[39]), .A1(n2623), .B0(DmP_EXP_EWSW[39]),
.B1(n2577), .Y(n2578) );
AOI22X1TS U3390 ( .A0(intDX_EWSW[4]), .A1(n2619), .B0(DmP_EXP_EWSW[4]), .B1(
n2618), .Y(n2580) );
AOI22X1TS U3391 ( .A0(intDX_EWSW[7]), .A1(n2619), .B0(DmP_EXP_EWSW[7]), .B1(
n2618), .Y(n2581) );
AOI22X1TS U3392 ( .A0(intDX_EWSW[1]), .A1(n2619), .B0(DmP_EXP_EWSW[1]), .B1(
n2625), .Y(n2583) );
AOI22X1TS U3393 ( .A0(DmP_EXP_EWSW[57]), .A1(n3134), .B0(intDX_EWSW[57]),
.B1(n2619), .Y(n2584) );
AOI22X1TS U3394 ( .A0(intDX_EWSW[5]), .A1(n2619), .B0(DmP_EXP_EWSW[5]), .B1(
n2618), .Y(n2586) );
AOI22X1TS U3395 ( .A0(intDY_EWSW[59]), .A1(n2602), .B0(DMP_EXP_EWSW[59]),
.B1(n2625), .Y(n2587) );
AOI22X1TS U3396 ( .A0(intDX_EWSW[0]), .A1(n2619), .B0(DmP_EXP_EWSW[0]), .B1(
n2625), .Y(n2588) );
AOI22X1TS U3397 ( .A0(intDX_EWSW[6]), .A1(n2590), .B0(DMP_EXP_EWSW[6]), .B1(
n2629), .Y(n2591) );
AOI22X1TS U3398 ( .A0(intDX_EWSW[9]), .A1(n2590), .B0(DMP_EXP_EWSW[9]), .B1(
n2629), .Y(n2592) );
AOI22X1TS U3399 ( .A0(intDX_EWSW[10]), .A1(n2555), .B0(DMP_EXP_EWSW[10]),
.B1(n1887), .Y(n2594) );
AOI22X1TS U3400 ( .A0(intDX_EWSW[2]), .A1(n2555), .B0(DMP_EXP_EWSW[2]), .B1(
n2629), .Y(n2595) );
AOI22X1TS U3401 ( .A0(intDX_EWSW[4]), .A1(n2590), .B0(DMP_EXP_EWSW[4]), .B1(
n2629), .Y(n2596) );
AOI22X1TS U3402 ( .A0(intDX_EWSW[1]), .A1(n2555), .B0(DMP_EXP_EWSW[1]), .B1(
n2629), .Y(n2597) );
AOI22X1TS U3403 ( .A0(intDX_EWSW[48]), .A1(n2602), .B0(DmP_EXP_EWSW[48]),
.B1(n3134), .Y(n2598) );
AOI22X1TS U3404 ( .A0(intDX_EWSW[49]), .A1(n2602), .B0(DmP_EXP_EWSW[49]),
.B1(n3134), .Y(n2599) );
AOI22X1TS U3405 ( .A0(intDY_EWSW[58]), .A1(n2623), .B0(DMP_EXP_EWSW[58]),
.B1(n2625), .Y(n2600) );
AOI22X1TS U3406 ( .A0(intDX_EWSW[50]), .A1(n2602), .B0(DmP_EXP_EWSW[50]),
.B1(n3134), .Y(n2601) );
AOI22X1TS U3407 ( .A0(intDX_EWSW[51]), .A1(n2602), .B0(DmP_EXP_EWSW[51]),
.B1(n3134), .Y(n2603) );
AOI22X1TS U3408 ( .A0(intDX_EWSW[5]), .A1(n2530), .B0(DMP_EXP_EWSW[5]), .B1(
n2629), .Y(n2604) );
AOI22X1TS U3409 ( .A0(n1864), .A1(n3134), .B0(intDX_EWSW[57]), .B1(n2555),
.Y(n2607) );
AOI22X1TS U3410 ( .A0(intDX_EWSW[14]), .A1(n2623), .B0(DmP_EXP_EWSW[14]),
.B1(n2622), .Y(n2608) );
AOI22X1TS U3411 ( .A0(intDX_EWSW[17]), .A1(n2623), .B0(DmP_EXP_EWSW[17]),
.B1(n2622), .Y(n2609) );
AOI22X1TS U3412 ( .A0(intDX_EWSW[19]), .A1(n2623), .B0(DmP_EXP_EWSW[19]),
.B1(n2622), .Y(n2610) );
AOI22X1TS U3413 ( .A0(intDX_EWSW[20]), .A1(n2623), .B0(DmP_EXP_EWSW[20]),
.B1(n2622), .Y(n2611) );
AOI22X1TS U3414 ( .A0(intDX_EWSW[21]), .A1(n2623), .B0(DmP_EXP_EWSW[21]),
.B1(n2622), .Y(n2612) );
AOI22X1TS U3415 ( .A0(intDX_EWSW[13]), .A1(n2623), .B0(DmP_EXP_EWSW[13]),
.B1(n2618), .Y(n2613) );
AOI22X1TS U3416 ( .A0(intDX_EWSW[15]), .A1(n2623), .B0(DmP_EXP_EWSW[15]),
.B1(n2618), .Y(n2614) );
AOI22X1TS U3417 ( .A0(intDX_EWSW[22]), .A1(n2623), .B0(DmP_EXP_EWSW[22]),
.B1(n2622), .Y(n2615) );
AOI22X1TS U3418 ( .A0(intDX_EWSW[12]), .A1(n2619), .B0(DmP_EXP_EWSW[12]),
.B1(n2618), .Y(n2616) );
AOI22X1TS U3419 ( .A0(intDX_EWSW[11]), .A1(n2619), .B0(DmP_EXP_EWSW[11]),
.B1(n2618), .Y(n2617) );
AOI22X1TS U3420 ( .A0(intDX_EWSW[10]), .A1(n2619), .B0(DmP_EXP_EWSW[10]),
.B1(n2618), .Y(n2620) );
AOI22X1TS U3421 ( .A0(intDX_EWSW[18]), .A1(n2623), .B0(DmP_EXP_EWSW[18]),
.B1(n2622), .Y(n2621) );
AOI22X1TS U3422 ( .A0(intDX_EWSW[16]), .A1(n2623), .B0(DmP_EXP_EWSW[16]),
.B1(n2622), .Y(n2624) );
AOI22X1TS U3423 ( .A0(intDY_EWSW[60]), .A1(n2623), .B0(DMP_EXP_EWSW[60]),
.B1(n2625), .Y(n2626) );
INVX2TS U3424 ( .A(n2628), .Y(n1535) );
INVX2TS U3425 ( .A(n2630), .Y(n1206) );
AOI22X1TS U3426 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[1]), .B0(n1862), .B1(
n3137), .Y(n2632) );
NAND2X1TS U3427 ( .A(n2632), .B(n2734), .Y(n2806) );
AOI22X1TS U3428 ( .A0(n3162), .A1(Data_array_SWR[43]), .B0(n2653), .B1(n2806), .Y(n2633) );
BUFX8TS U3429 ( .A(n2649), .Y(n2826) );
AOI22X1TS U3430 ( .A0(n2002), .A1(Raw_mant_NRM_SWR[50]), .B0(n2704), .B1(
DmP_mant_SHT1_SW[2]), .Y(n2635) );
AOI22X1TS U3431 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[51]), .B0(n2750), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2634) );
NAND2X1TS U3432 ( .A(n2635), .B(n2634), .Y(n2654) );
AOI22X1TS U3433 ( .A0(n2821), .A1(Data_array_SWR[3]), .B0(n2653), .B1(n2654),
.Y(n2638) );
BUFX4TS U3434 ( .A(n2642), .Y(n2805) );
NAND2X1TS U3435 ( .A(n2805), .B(Raw_mant_NRM_SWR[48]), .Y(n2637) );
BUFX4TS U3436 ( .A(n2639), .Y(n2811) );
INVX4TS U3437 ( .A(n2736), .Y(n2724) );
AOI22X1TS U3438 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2002), .B0(n2704), .B1(
DmP_mant_SHT1_SW[5]), .Y(n2641) );
AOI22X1TS U3439 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[48]), .B0(n2750), .B1(
DmP_mant_SHT1_SW[4]), .Y(n2640) );
NAND2X1TS U3440 ( .A(n2641), .B(n2640), .Y(n2662) );
AOI22X1TS U3441 ( .A0(n3162), .A1(n1866), .B0(n2653), .B1(n2662), .Y(n2644)
);
BUFX4TS U3442 ( .A(n2642), .Y(n2771) );
NAND2X1TS U3443 ( .A(Raw_mant_NRM_SWR[45]), .B(n2771), .Y(n2643) );
AOI22X1TS U3444 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n2002), .B0(n2704), .B1(
DmP_mant_SHT1_SW[8]), .Y(n2646) );
AOI22X1TS U3445 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n2752), .B0(n2750), .B1(
DmP_mant_SHT1_SW[7]), .Y(n2645) );
NAND2X1TS U3446 ( .A(n2646), .B(n2645), .Y(n2658) );
AOI22X1TS U3447 ( .A0(n2795), .A1(Data_array_SWR[7]), .B0(n2653), .B1(n2658),
.Y(n2648) );
NAND2X1TS U3448 ( .A(Raw_mant_NRM_SWR[42]), .B(n2771), .Y(n2647) );
AOI22X1TS U3449 ( .A0(n2815), .A1(Data_array_SWR[2]), .B0(n2653), .B1(n2650),
.Y(n2652) );
NAND2X1TS U3450 ( .A(n2805), .B(Raw_mant_NRM_SWR[49]), .Y(n2651) );
AOI22X1TS U3451 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[53]), .B0(n2803), .B1(
DmP_mant_SHT1_SW[0]), .Y(n2657) );
BUFX4TS U3452 ( .A(n2829), .Y(n2822) );
AOI22X1TS U3453 ( .A0(n2659), .A1(Data_array_SWR[1]), .B0(n2807), .B1(n2654),
.Y(n2656) );
NAND2X1TS U3454 ( .A(n2720), .B(Raw_mant_NRM_SWR[52]), .Y(n2655) );
AOI22X1TS U3455 ( .A0(n2659), .A1(Data_array_SWR[5]), .B0(n2807), .B1(n2658),
.Y(n2661) );
INVX4TS U3456 ( .A(n2730), .Y(n2756) );
NAND2X1TS U3457 ( .A(Raw_mant_NRM_SWR[46]), .B(n2756), .Y(n2660) );
AOI22X1TS U3458 ( .A0(n2659), .A1(n1865), .B0(n2807), .B1(n2662), .Y(n2664)
);
NAND2X1TS U3459 ( .A(n2720), .B(Raw_mant_NRM_SWR[49]), .Y(n2663) );
AOI22X1TS U3460 ( .A0(n2659), .A1(Data_array_SWR[4]), .B0(
Raw_mant_NRM_SWR[46]), .B1(n2771), .Y(n2668) );
AOI22X1TS U3461 ( .A0(n2821), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[38]), .B1(n2805), .Y(n2671) );
AOI22X1TS U3462 ( .A0(n2815), .A1(Data_array_SWR[6]), .B0(
Raw_mant_NRM_SWR[43]), .B1(n2805), .Y(n2673) );
AOI22X1TS U3463 ( .A0(n2821), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[40]), .B1(n2805), .Y(n2677) );
AOI22X1TS U3464 ( .A0(n2659), .A1(Data_array_SWR[22]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n2805), .Y(n2680) );
AOI22X1TS U3465 ( .A0(n3162), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[36]), .B1(n2805), .Y(n2682) );
AOI22X1TS U3466 ( .A0(n2795), .A1(Data_array_SWR[14]), .B0(
Raw_mant_NRM_SWR[33]), .B1(n2805), .Y(n2685) );
AOI22X1TS U3467 ( .A0(n2821), .A1(Data_array_SWR[18]), .B0(
Raw_mant_NRM_SWR[29]), .B1(n2805), .Y(n2687) );
BUFX4TS U3468 ( .A(n2639), .Y(n2804) );
INVX2TS U3469 ( .A(n2736), .Y(n2705) );
AOI22X1TS U3470 ( .A0(n3162), .A1(Data_array_SWR[38]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n2771), .Y(n2689) );
AOI22X1TS U3471 ( .A0(n2795), .A1(Data_array_SWR[33]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n2771), .Y(n2691) );
AOI222X1TS U3472 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n2804), .B0(n2704), .B1(
n1874), .C0(n2724), .C1(n1863), .Y(n2733) );
AOI22X1TS U3473 ( .A0(n2795), .A1(Data_array_SWR[31]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n2771), .Y(n2694) );
AOI22X1TS U3474 ( .A0(n2795), .A1(Data_array_SWR[29]), .B0(
Raw_mant_NRM_SWR[15]), .B1(n2771), .Y(n2697) );
AOI22X1TS U3475 ( .A0(n3162), .A1(Data_array_SWR[16]), .B0(
Raw_mant_NRM_SWR[31]), .B1(n2805), .Y(n2700) );
AOI22X1TS U3476 ( .A0(n2815), .A1(Data_array_SWR[25]), .B0(
Raw_mant_NRM_SWR[20]), .B1(n2771), .Y(n2703) );
AOI22X1TS U3477 ( .A0(n3162), .A1(Data_array_SWR[40]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n2771), .Y(n2707) );
AOI22X1TS U3478 ( .A0(n2821), .A1(Data_array_SWR[35]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n2771), .Y(n2710) );
AOI22X1TS U3479 ( .A0(n2821), .A1(Data_array_SWR[36]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n2771), .Y(n2714) );
AOI22X1TS U3480 ( .A0(n2815), .A1(Data_array_SWR[24]), .B0(
Raw_mant_NRM_SWR[22]), .B1(n2771), .Y(n2718) );
AOI22X1TS U3481 ( .A0(n2815), .A1(Data_array_SWR[20]), .B0(
Raw_mant_NRM_SWR[27]), .B1(n2805), .Y(n2722) );
AOI22X1TS U3482 ( .A0(n2815), .A1(Data_array_SWR[26]), .B0(
Raw_mant_NRM_SWR[18]), .B1(n2771), .Y(n2727) );
AOI22X1TS U3483 ( .A0(n2795), .A1(Data_array_SWR[34]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2771), .Y(n2732) );
OA22X1TS U3484 ( .A0(n3286), .A1(n2730), .B0(n2729), .B1(n2833), .Y(n2731)
);
AOI21X1TS U3485 ( .A0(n3162), .A1(Data_array_SWR[44]), .B0(n1844), .Y(n2735)
);
AOI22X1TS U3486 ( .A0(n3162), .A1(Data_array_SWR[42]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n2756), .Y(n2739) );
AOI22X1TS U3487 ( .A0(n2815), .A1(Data_array_SWR[21]), .B0(
Raw_mant_NRM_SWR[27]), .B1(n2756), .Y(n2743) );
AOI2BB2X1TS U3488 ( .B0(n1845), .B1(DmP_mant_SHT1_SW[26]), .A0N(n2741),
.A1N(n2816), .Y(n2742) );
INVX4TS U3489 ( .A(n3128), .Y(n2810) );
AOI22X1TS U3490 ( .A0(n2821), .A1(Data_array_SWR[28]), .B0(
Raw_mant_NRM_SWR[18]), .B1(n2756), .Y(n2746) );
AOI2BB2X1TS U3491 ( .B0(n1846), .B1(DmP_mant_SHT1_SW[35]), .A0N(n2744),
.A1N(n2829), .Y(n2745) );
AOI22X1TS U3492 ( .A0(n3162), .A1(n1869), .B0(Raw_mant_NRM_SWR[36]), .B1(
n2756), .Y(n2749) );
AOI2BB2X1TS U3493 ( .B0(n1846), .B1(DmP_mant_SHT1_SW[17]), .A0N(n2747),
.A1N(n2822), .Y(n2748) );
AOI22X1TS U3494 ( .A0(n2821), .A1(Data_array_SWR[12]), .B0(n1875), .B1(n2756), .Y(n2755) );
AOI2BB2X1TS U3495 ( .B0(n1846), .B1(DmP_mant_SHT1_SW[14]), .A0N(n2763),
.A1N(n2753), .Y(n2754) );
AOI22X1TS U3496 ( .A0(n2795), .A1(Data_array_SWR[8]), .B0(
Raw_mant_NRM_SWR[43]), .B1(n2756), .Y(n2759) );
AOI2BB2X1TS U3497 ( .B0(n1845), .B1(DmP_mant_SHT1_SW[10]), .A0N(n2757),
.A1N(n2829), .Y(n2758) );
AOI22X1TS U3498 ( .A0(n2795), .A1(Data_array_SWR[10]), .B0(n1875), .B1(n2805), .Y(n2762) );
AOI2BB2X1TS U3499 ( .B0(n1844), .B1(DmP_mant_SHT1_SW[10]), .A0N(n2760),
.A1N(n2829), .Y(n2761) );
AOI22X1TS U3500 ( .A0(n3162), .A1(n1871), .B0(Raw_mant_NRM_SWR[35]), .B1(
n2805), .Y(n2766) );
AOI2BB2X1TS U3501 ( .B0(n1844), .B1(DmP_mant_SHT1_SW[14]), .A0N(n2764),
.A1N(n2829), .Y(n2765) );
AOI22X1TS U3502 ( .A0(n2659), .A1(n1880), .B0(Raw_mant_NRM_SWR[26]), .B1(
n2805), .Y(n2769) );
AOI2BB2X1TS U3503 ( .B0(n1844), .B1(DmP_mant_SHT1_SW[23]), .A0N(n2802),
.A1N(n2829), .Y(n2768) );
OAI211X1TS U3504 ( .A0(n2770), .A1(n2649), .B0(n2769), .C0(n2768), .Y(n1635)
);
AOI2BB2X1TS U3505 ( .B0(n1843), .B1(DmP_mant_SHT1_SW[32]), .A0N(n2794),
.A1N(n2816), .Y(n2772) );
AOI22X1TS U3506 ( .A0(n3162), .A1(n1876), .B0(n1844), .B1(n1873), .Y(n2776)
);
AOI2BB2X1TS U3507 ( .B0(n1845), .B1(DmP_mant_SHT1_SW[37]), .A0N(n2777),
.A1N(n2816), .Y(n2778) );
AOI22X1TS U3508 ( .A0(n2795), .A1(n1878), .B0(n1843), .B1(n1874), .Y(n2781)
);
AOI2BB2X1TS U3509 ( .B0(n1846), .B1(n1873), .A0N(n2785), .A1N(n2816), .Y(
n2780) );
AOI22X1TS U3510 ( .A0(n3162), .A1(n1877), .B0(n1844), .B1(n1870), .Y(n2784)
);
AOI22X1TS U3511 ( .A0(n3162), .A1(Data_array_SWR[37]), .B0(n1843), .B1(n1872), .Y(n2788) );
AOI2BB2X1TS U3512 ( .B0(n1846), .B1(DmP_mant_SHT1_SW[47]), .A0N(n2786),
.A1N(n2822), .Y(n2787) );
AOI2BB2X1TS U3513 ( .B0(n1845), .B1(DmP_mant_SHT1_SW[19]), .A0N(n2789),
.A1N(n2829), .Y(n2790) );
AOI22X1TS U3514 ( .A0(n2659), .A1(n1879), .B0(n1843), .B1(
DmP_mant_SHT1_SW[30]), .Y(n2793) );
AOI22X1TS U3515 ( .A0(n2795), .A1(Data_array_SWR[32]), .B0(n1843), .B1(
DmP_mant_SHT1_SW[37]), .Y(n2798) );
AOI2BB2X1TS U3516 ( .B0(n1845), .B1(n1870), .A0N(n2796), .A1N(n2816), .Y(
n2797) );
AOI2BB2X1TS U3517 ( .B0(n1845), .B1(DmP_mant_SHT1_SW[23]), .A0N(n2827),
.A1N(n2816), .Y(n2800) );
AOI22X1TS U3518 ( .A0(n2821), .A1(Data_array_SWR[41]), .B0(
Raw_mant_NRM_SWR[0]), .B1(n2805), .Y(n2809) );
AOI22X1TS U3519 ( .A0(n2807), .A1(n2806), .B0(DmP_mant_SHT1_SW[49]), .B1(
n1843), .Y(n2808) );
AOI22X1TS U3520 ( .A0(n2659), .A1(Data_array_SWR[23]), .B0(n1843), .B1(
DmP_mant_SHT1_SW[26]), .Y(n2814) );
AOI2BB2X1TS U3521 ( .B0(n1846), .B1(DmP_mant_SHT1_SW[28]), .A0N(n2812),
.A1N(n2816), .Y(n2813) );
AOI22X1TS U3522 ( .A0(n2659), .A1(n1881), .B0(n1843), .B1(
DmP_mant_SHT1_SW[28]), .Y(n2819) );
AOI2BB2X1TS U3523 ( .B0(n1845), .B1(DmP_mant_SHT1_SW[30]), .A0N(n2817),
.A1N(n2816), .Y(n2818) );
AOI22X1TS U3524 ( .A0(n2821), .A1(Data_array_SWR[39]), .B0(
DmP_mant_SHT1_SW[47]), .B1(n1843), .Y(n2832) );
AOI2BB2X1TS U3525 ( .B0(DmP_mant_SHT1_SW[49]), .B1(n1845), .A0N(n2830),
.A1N(n2829), .Y(n2831) );
AO22XLTS U3526 ( .A0(n3223), .A1(OP_FLAG_SHT1), .B0(OP_FLAG_SHT2), .B1(n3194), .Y(n3434) );
AO22XLTS U3527 ( .A0(n3223), .A1(DMP_SHT1_EWSW[16]), .B0(DMP_SHT2_EWSW[16]),
.B1(n3194), .Y(n3435) );
AO22XLTS U3528 ( .A0(n3223), .A1(DMP_SHT1_EWSW[15]), .B0(DMP_SHT2_EWSW[15]),
.B1(n3194), .Y(n3436) );
AO22XLTS U3529 ( .A0(n3223), .A1(DMP_SHT1_EWSW[14]), .B0(DMP_SHT2_EWSW[14]),
.B1(n3194), .Y(n3437) );
AO22XLTS U3530 ( .A0(n3223), .A1(DMP_SHT1_EWSW[13]), .B0(DMP_SHT2_EWSW[13]),
.B1(n3194), .Y(n3438) );
AO22XLTS U3531 ( .A0(n3223), .A1(DMP_SHT1_EWSW[12]), .B0(DMP_SHT2_EWSW[12]),
.B1(n3194), .Y(n3439) );
INVX2TS U3532 ( .A(n2835), .Y(n2836) );
NAND2X1TS U3533 ( .A(n3351), .B(n2836), .Y(DP_OP_15J9_123_7955_n11) );
OAI2BB1X1TS U3534 ( .A0N(LZD_output_NRM2_EW[1]), .A1N(n3137), .B0(n2837),
.Y(n1130) );
XOR2X1TS U3535 ( .A(n2986), .B(DmP_mant_SFG_SWR[53]), .Y(n2985) );
XOR2X1TS U3536 ( .A(n2986), .B(DmP_mant_SFG_SWR[52]), .Y(n2979) );
XOR2X1TS U3537 ( .A(n2986), .B(DmP_mant_SFG_SWR[51]), .Y(n2982) );
XOR2X1TS U3538 ( .A(n2986), .B(DmP_mant_SFG_SWR[50]), .Y(n2991) );
XOR2X1TS U3539 ( .A(n2986), .B(DmP_mant_SFG_SWR[49]), .Y(n2853) );
XOR2X1TS U3540 ( .A(n2986), .B(DmP_mant_SFG_SWR[48]), .Y(n2994) );
XOR2X1TS U3541 ( .A(n2986), .B(DmP_mant_SFG_SWR[47]), .Y(n2997) );
XOR2X1TS U3542 ( .A(n2986), .B(DmP_mant_SFG_SWR[46]), .Y(n2973) );
XOR2X1TS U3543 ( .A(n2986), .B(DmP_mant_SFG_SWR[45]), .Y(n2976) );
XOR2X1TS U3544 ( .A(n2986), .B(DmP_mant_SFG_SWR[44]), .Y(n2970) );
BUFX4TS U3545 ( .A(OP_FLAG_SFG), .Y(n2838) );
XOR2X1TS U3546 ( .A(n2838), .B(DmP_mant_SFG_SWR[43]), .Y(n3000) );
XOR2X1TS U3547 ( .A(n2838), .B(DmP_mant_SFG_SWR[42]), .Y(n3003) );
XOR2X1TS U3548 ( .A(n2838), .B(DmP_mant_SFG_SWR[41]), .Y(n3006) );
XOR2X1TS U3549 ( .A(n2838), .B(DmP_mant_SFG_SWR[40]), .Y(n3009) );
XOR2X1TS U3550 ( .A(n2838), .B(DmP_mant_SFG_SWR[39]), .Y(n3012) );
XOR2X1TS U3551 ( .A(n2838), .B(DmP_mant_SFG_SWR[38]), .Y(n3019) );
XOR2X1TS U3552 ( .A(n2838), .B(DmP_mant_SFG_SWR[37]), .Y(n3015) );
XOR2X1TS U3553 ( .A(n2838), .B(DmP_mant_SFG_SWR[36]), .Y(n3022) );
XOR2X1TS U3554 ( .A(n2838), .B(DmP_mant_SFG_SWR[35]), .Y(n3025) );
XOR2X1TS U3555 ( .A(n2838), .B(DmP_mant_SFG_SWR[34]), .Y(n3028) );
XOR2X1TS U3556 ( .A(n2838), .B(DmP_mant_SFG_SWR[33]), .Y(n3031) );
XOR2X1TS U3557 ( .A(n2838), .B(DmP_mant_SFG_SWR[32]), .Y(n3034) );
XOR2X1TS U3558 ( .A(n2838), .B(DmP_mant_SFG_SWR[31]), .Y(n3037) );
XOR2X1TS U3559 ( .A(n2838), .B(DmP_mant_SFG_SWR[30]), .Y(n3040) );
XOR2X1TS U3560 ( .A(n2844), .B(DmP_mant_SFG_SWR[29]), .Y(n3058) );
XOR2X1TS U3561 ( .A(n2844), .B(DmP_mant_SFG_SWR[28]), .Y(n3043) );
XOR2X1TS U3562 ( .A(n2844), .B(DmP_mant_SFG_SWR[27]), .Y(n3061) );
XOR2X1TS U3563 ( .A(n2844), .B(DmP_mant_SFG_SWR[26]), .Y(n3064) );
XOR2X1TS U3564 ( .A(n2844), .B(DmP_mant_SFG_SWR[25]), .Y(n3068) );
XOR2X1TS U3565 ( .A(n2838), .B(DmP_mant_SFG_SWR[24]), .Y(n3071) );
XOR2X1TS U3566 ( .A(n2844), .B(DmP_mant_SFG_SWR[23]), .Y(n3074) );
XOR2X1TS U3567 ( .A(n2844), .B(DmP_mant_SFG_SWR[22]), .Y(n3077) );
XOR2X1TS U3568 ( .A(n2986), .B(DmP_mant_SFG_SWR[15]), .Y(n3105) );
NOR2X2TS U3569 ( .A(n2841), .B(DMP_SFG[15]), .Y(n3051) );
NAND2X1TS U3570 ( .A(n2841), .B(DMP_SFG[15]), .Y(n3052) );
OAI21X1TS U3571 ( .A0(n3051), .A1(n3099), .B0(n3052), .Y(n2842) );
NOR2X2TS U3572 ( .A(n2846), .B(DMP_SFG[17]), .Y(n3085) );
NAND2X1TS U3573 ( .A(n2846), .B(DMP_SFG[17]), .Y(n3086) );
INVX2TS U3574 ( .A(n3094), .Y(n2848) );
AFHCONX2TS U3575 ( .A(DMP_SFG[47]), .B(n2853), .CI(n2852), .CON(n2990), .S(
n2854) );
NOR2XLTS U3576 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2855) );
AOI32X4TS U3577 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n2855), .B1(n3390), .Y(n3138)
);
MXI2X1TS U3578 ( .A(n3218), .B(n1886), .S0(n3138), .Y(n1797) );
MX2X1TS U3579 ( .A(DMP_SFG[13]), .B(DMP_SHT2_EWSW[13]), .S0(n3185), .Y(n1480) );
BUFX3TS U3580 ( .A(n2856), .Y(n3246) );
MX2X1TS U3581 ( .A(n2986), .B(OP_FLAG_SHT2), .S0(n3246), .Y(n1190) );
MX2X1TS U3582 ( .A(DMP_SFG[12]), .B(DMP_SHT2_EWSW[12]), .S0(n3246), .Y(n1483) );
MX2X1TS U3583 ( .A(DMP_SFG[51]), .B(DMP_SHT2_EWSW[51]), .S0(n3258), .Y(n1366) );
MX2X1TS U3584 ( .A(DMP_SFG[50]), .B(DMP_SHT2_EWSW[50]), .S0(n2858), .Y(n1369) );
MX2X1TS U3585 ( .A(DMP_SFG[49]), .B(DMP_SHT2_EWSW[49]), .S0(n2883), .Y(n1372) );
BUFX3TS U3586 ( .A(n2856), .Y(n3217) );
MX2X1TS U3587 ( .A(DMP_SFG[48]), .B(DMP_SHT2_EWSW[48]), .S0(n2858), .Y(n1375) );
MX2X1TS U3588 ( .A(DMP_SFG[46]), .B(DMP_SHT2_EWSW[46]), .S0(n3246), .Y(n1381) );
MX2X1TS U3589 ( .A(DMP_SFG[44]), .B(DMP_SHT2_EWSW[44]), .S0(n2883), .Y(n1387) );
MX2X1TS U3590 ( .A(DMP_SFG[42]), .B(DMP_SHT2_EWSW[42]), .S0(n2858), .Y(n1393) );
BUFX3TS U3591 ( .A(n2856), .Y(n3258) );
MX2X1TS U3592 ( .A(DMP_SFG[40]), .B(DMP_SHT2_EWSW[40]), .S0(n3246), .Y(n1399) );
MX2X1TS U3593 ( .A(DMP_SFG[38]), .B(DMP_SHT2_EWSW[38]), .S0(n3198), .Y(n1405) );
MX2X1TS U3594 ( .A(DMP_SFG[36]), .B(DMP_SHT2_EWSW[36]), .S0(n2858), .Y(n1411) );
MX2X1TS U3595 ( .A(DMP_SFG[35]), .B(DMP_SHT2_EWSW[35]), .S0(n3258), .Y(n1414) );
MX2X1TS U3596 ( .A(DMP_SFG[34]), .B(DMP_SHT2_EWSW[34]), .S0(n2883), .Y(n1417) );
MX2X1TS U3597 ( .A(DMP_SFG[33]), .B(DMP_SHT2_EWSW[33]), .S0(n2856), .Y(n1420) );
MX2X1TS U3598 ( .A(DMP_SFG[32]), .B(DMP_SHT2_EWSW[32]), .S0(n3246), .Y(n1423) );
MX2X1TS U3599 ( .A(DMP_SFG[31]), .B(DMP_SHT2_EWSW[31]), .S0(n3198), .Y(n1426) );
MX2X1TS U3600 ( .A(DMP_SFG[30]), .B(DMP_SHT2_EWSW[30]), .S0(n3217), .Y(n1429) );
MX2X1TS U3601 ( .A(DMP_SFG[29]), .B(DMP_SHT2_EWSW[29]), .S0(n3217), .Y(n1432) );
MX2X1TS U3602 ( .A(DMP_SFG[28]), .B(DMP_SHT2_EWSW[28]), .S0(n3185), .Y(n1435) );
MX2X1TS U3603 ( .A(DMP_SFG[27]), .B(DMP_SHT2_EWSW[27]), .S0(n3217), .Y(n1438) );
MX2X1TS U3604 ( .A(DMP_SFG[26]), .B(DMP_SHT2_EWSW[26]), .S0(n3185), .Y(n1441) );
MX2X1TS U3605 ( .A(DMP_SFG[25]), .B(DMP_SHT2_EWSW[25]), .S0(n2856), .Y(n1444) );
MX2X1TS U3606 ( .A(DMP_SFG[24]), .B(DMP_SHT2_EWSW[24]), .S0(n2856), .Y(n1447) );
MX2X1TS U3607 ( .A(DMP_SFG[23]), .B(DMP_SHT2_EWSW[23]), .S0(n2856), .Y(n1450) );
MX2X1TS U3608 ( .A(DMP_SFG[22]), .B(DMP_SHT2_EWSW[22]), .S0(n2856), .Y(n1453) );
MX2X1TS U3609 ( .A(DMP_SFG[21]), .B(DMP_SHT2_EWSW[21]), .S0(n2857), .Y(n1456) );
MX2X1TS U3610 ( .A(DMP_SFG[20]), .B(DMP_SHT2_EWSW[20]), .S0(n3217), .Y(n1459) );
MX2X1TS U3611 ( .A(DMP_SFG[19]), .B(DMP_SHT2_EWSW[19]), .S0(n3198), .Y(n1462) );
MX2X1TS U3612 ( .A(DMP_SFG[18]), .B(DMP_SHT2_EWSW[18]), .S0(n3246), .Y(n1465) );
MX2X1TS U3613 ( .A(DMP_SFG[17]), .B(DMP_SHT2_EWSW[17]), .S0(n3185), .Y(n1468) );
MX2X1TS U3614 ( .A(DMP_SFG[16]), .B(DMP_SHT2_EWSW[16]), .S0(n3217), .Y(n1471) );
MX2X1TS U3615 ( .A(DMP_SFG[15]), .B(DMP_SHT2_EWSW[15]), .S0(n3185), .Y(n1474) );
MX2X1TS U3616 ( .A(DMP_SFG[14]), .B(DMP_SHT2_EWSW[14]), .S0(n3185), .Y(n1477) );
NAND2X1TS U3617 ( .A(n2910), .B(n1804), .Y(n2876) );
OAI22X1TS U3618 ( .A0(n2859), .A1(n2915), .B0(n3408), .B1(n2876), .Y(n2860)
);
INVX4TS U3619 ( .A(n3246), .Y(n3259) );
MX2X1TS U3620 ( .A(n2860), .B(DmP_mant_SFG_SWR[54]), .S0(n3259), .Y(n1016)
);
OAI22X1TS U3621 ( .A0(n2861), .A1(n1804), .B0(n3407), .B1(n2876), .Y(n3279)
);
MX2X1TS U3622 ( .A(n3279), .B(DmP_mant_SFG_SWR[53]), .S0(n3259), .Y(n1017)
);
AOI22X1TS U3623 ( .A0(n1881), .A1(n2103), .B0(Data_array_SWR[21]), .B1(n2884), .Y(n2863) );
AOI22X1TS U3624 ( .A0(Data_array_SWR[18]), .A1(n2909), .B0(
Data_array_SWR[14]), .B1(n2896), .Y(n2862) );
AOI21X1TS U3625 ( .A0(n2863), .A1(n2862), .B0(n2939), .Y(n2868) );
AOI22X1TS U3626 ( .A0(Data_array_SWR[12]), .A1(n2895), .B0(Data_array_SWR[2]), .B1(n2910), .Y(n2865) );
AOI22X1TS U3627 ( .A0(Data_array_SWR[8]), .A1(n2934), .B0(n1866), .B1(n2106),
.Y(n2864) );
AOI211X1TS U3628 ( .A0(n2914), .A1(n2869), .B0(n2868), .C0(n2867), .Y(n3228)
);
OAI22X1TS U3629 ( .A0(n3228), .A1(n2915), .B0(n1826), .B1(n2876), .Y(n3277)
);
MX2X1TS U3630 ( .A(n3277), .B(DmP_mant_SFG_SWR[52]), .S0(n3259), .Y(n1018)
);
AOI22X1TS U3631 ( .A0(Data_array_SWR[25]), .A1(n2885), .B0(
Data_array_SWR[22]), .B1(n2884), .Y(n2872) );
AOI22X1TS U3632 ( .A0(Data_array_SWR[13]), .A1(n2936), .B0(Data_array_SWR[9]), .B1(n2886), .Y(n2871) );
AOI22X1TS U3633 ( .A0(Data_array_SWR[19]), .A1(n2897), .B0(
Data_array_SWR[15]), .B1(n2896), .Y(n2870) );
AOI32X1TS U3634 ( .A0(n2872), .A1(n2871), .A2(n2870), .B0(n2111), .B1(n2871),
.Y(n2873) );
OAI22X1TS U3635 ( .A0(n3233), .A1(n2915), .B0(n3395), .B1(n2876), .Y(n3276)
);
AO22XLTS U3636 ( .A0(Data_array_SWR[6]), .A1(n2106), .B0(n1865), .B1(n2910),
.Y(n2881) );
AOI22X1TS U3637 ( .A0(n1879), .A1(n2885), .B0(Data_array_SWR[23]), .B1(n2884), .Y(n2879) );
AOI22X1TS U3638 ( .A0(n1871), .A1(n2936), .B0(Data_array_SWR[10]), .B1(n2886), .Y(n2878) );
AOI22X1TS U3639 ( .A0(Data_array_SWR[20]), .A1(n2897), .B0(
Data_array_SWR[16]), .B1(n2896), .Y(n2877) );
AOI32X1TS U3640 ( .A0(n2879), .A1(n2878), .A2(n2877), .B0(n2111), .B1(n2878),
.Y(n2880) );
OAI22X1TS U3641 ( .A0(n3235), .A1(n2915), .B0(n3234), .B1(n2966), .Y(n3270)
);
INVX4TS U3642 ( .A(n3198), .Y(n2968) );
AO22XLTS U3643 ( .A0(Data_array_SWR[7]), .A1(n2106), .B0(Data_array_SWR[4]),
.B1(n2910), .Y(n2892) );
AOI22X1TS U3644 ( .A0(Data_array_SWR[26]), .A1(n2885), .B0(
Data_array_SWR[24]), .B1(n2884), .Y(n2890) );
AOI22X1TS U3645 ( .A0(n1869), .A1(n2936), .B0(Data_array_SWR[11]), .B1(n2886), .Y(n2889) );
AOI22X1TS U3646 ( .A0(Data_array_SWR[17]), .A1(n2905), .B0(n1880), .B1(n2887), .Y(n2888) );
AOI32X1TS U3647 ( .A0(n2890), .A1(n2889), .A2(n2888), .B0(n2111), .B1(n2889),
.Y(n2891) );
AOI211X1TS U3648 ( .A0(shift_value_SHT2_EWR[5]), .A1(n2893), .B0(n2892),
.C0(n2891), .Y(n3229) );
OAI22X1TS U3649 ( .A0(n3229), .A1(n1804), .B0(n3231), .B1(n2966), .Y(n3274)
);
AO22XLTS U3650 ( .A0(Data_array_SWR[8]), .A1(n2106), .B0(n1866), .B1(n2910),
.Y(n2902) );
AOI22X1TS U3651 ( .A0(n1881), .A1(n2904), .B0(Data_array_SWR[27]), .B1(n2103), .Y(n2900) );
AOI22X1TS U3652 ( .A0(Data_array_SWR[12]), .A1(n2934), .B0(
Data_array_SWR[14]), .B1(n2895), .Y(n2899) );
AOI22X1TS U3653 ( .A0(Data_array_SWR[21]), .A1(n2897), .B0(
Data_array_SWR[18]), .B1(n2896), .Y(n2898) );
AOI32X1TS U3654 ( .A0(n2900), .A1(n2899), .A2(n2898), .B0(n2111), .B1(n2899),
.Y(n2901) );
OAI22X1TS U3655 ( .A0(n3237), .A1(n2915), .B0(n3236), .B1(n2966), .Y(n3268)
);
AOI22X1TS U3656 ( .A0(Data_array_SWR[19]), .A1(n2905), .B0(
Data_array_SWR[25]), .B1(n2904), .Y(n2906) );
AOI22X1TS U3657 ( .A0(Data_array_SWR[13]), .A1(n2934), .B0(Data_array_SWR[9]), .B1(n2106), .Y(n2912) );
AOI22X1TS U3658 ( .A0(Data_array_SWR[15]), .A1(n2936), .B0(Data_array_SWR[5]), .B1(n2910), .Y(n2911) );
AOI21X1TS U3659 ( .A0(n2914), .A1(n2963), .B0(n2913), .Y(n3240) );
OAI22X1TS U3660 ( .A0(n3240), .A1(n2915), .B0(n3239), .B1(n2966), .Y(n3266)
);
MX2X1TS U3661 ( .A(n3266), .B(DmP_mant_SFG_SWR[47]), .S0(n2968), .Y(n1023)
);
OAI22X1TS U3662 ( .A0(n2916), .A1(n2915), .B0(n2923), .B1(n2966), .Y(n3264)
);
MX2X1TS U3663 ( .A(n3264), .B(DmP_mant_SFG_SWR[46]), .S0(n2968), .Y(n1024)
);
MX2X1TS U3664 ( .A(n2917), .B(DmP_mant_SFG_SWR[45]), .S0(n2968), .Y(n1025)
);
MX2X1TS U3665 ( .A(n2918), .B(DmP_mant_SFG_SWR[44]), .S0(n2968), .Y(n1026)
);
MX2X1TS U3666 ( .A(n2920), .B(DmP_mant_SFG_SWR[43]), .S0(n2919), .Y(n1027)
);
AOI22X1TS U3667 ( .A0(n2929), .A1(n2961), .B0(n2960), .B1(n2963), .Y(n2922)
);
INVX2TS U3668 ( .A(n3239), .Y(n2959) );
NAND2X1TS U3669 ( .A(n2143), .B(n2959), .Y(n2921) );
OAI211X1TS U3670 ( .A0(n2967), .A1(n3238), .B0(n2922), .C0(n2921), .Y(n3262)
);
MX2X1TS U3671 ( .A(n3262), .B(DmP_mant_SFG_SWR[31]), .S0(n2968), .Y(n1039)
);
AOI22X1TS U3672 ( .A0(n2929), .A1(n2954), .B0(n2960), .B1(n2955), .Y(n2925)
);
INVX2TS U3673 ( .A(n2923), .Y(n2953) );
NAND2X1TS U3674 ( .A(n2143), .B(n2953), .Y(n2924) );
MX2X1TS U3675 ( .A(n3254), .B(DmP_mant_SFG_SWR[30]), .S0(n3259), .Y(n1040)
);
AOI22X1TS U3676 ( .A0(n2929), .A1(n2948), .B0(n2960), .B1(n2949), .Y(n2928)
);
INVX2TS U3677 ( .A(n2926), .Y(n2947) );
NAND2X1TS U3678 ( .A(n2143), .B(n2947), .Y(n2927) );
OAI211X1TS U3679 ( .A0(n2952), .A1(n3238), .B0(n2928), .C0(n2927), .Y(n3250)
);
MX2X1TS U3680 ( .A(n3250), .B(DmP_mant_SFG_SWR[29]), .S0(n2968), .Y(n1041)
);
AOI22X1TS U3681 ( .A0(n2929), .A1(n2942), .B0(n2960), .B1(n2943), .Y(n2932)
);
INVX2TS U3682 ( .A(n2930), .Y(n2941) );
NAND2X1TS U3683 ( .A(n2143), .B(n2941), .Y(n2931) );
OAI211X1TS U3684 ( .A0(n2946), .A1(n3238), .B0(n2932), .C0(n2931), .Y(n3256)
);
MX2X1TS U3685 ( .A(n3256), .B(DmP_mant_SFG_SWR[28]), .S0(n2968), .Y(n1042)
);
AOI22X1TS U3686 ( .A0(Data_array_SWR[28]), .A1(n2934), .B0(
Data_array_SWR[22]), .B1(n2933), .Y(n2938) );
AOI22X1TS U3687 ( .A0(Data_array_SWR[32]), .A1(n2936), .B0(
Data_array_SWR[25]), .B1(n2935), .Y(n2937) );
OAI211X1TS U3688 ( .A0(n2940), .A1(n2939), .B0(n2938), .C0(n2937), .Y(n3260)
);
MX2X1TS U3689 ( .A(n3260), .B(DmP_mant_SFG_SWR[27]), .S0(n2968), .Y(n1043)
);
AOI22X1TS U3690 ( .A0(n2962), .A1(n2942), .B0(n2960), .B1(n2941), .Y(n2945)
);
NAND2X1TS U3691 ( .A(n2143), .B(n2943), .Y(n2944) );
MX2X1TS U3692 ( .A(n3255), .B(DmP_mant_SFG_SWR[26]), .S0(n2968), .Y(n1044)
);
AOI22X1TS U3693 ( .A0(n2962), .A1(n2948), .B0(n2960), .B1(n2947), .Y(n2951)
);
NAND2X1TS U3694 ( .A(n2143), .B(n2949), .Y(n2950) );
OAI211X1TS U3695 ( .A0(n2952), .A1(n2966), .B0(n2951), .C0(n2950), .Y(n3248)
);
MX2X1TS U3696 ( .A(n3248), .B(DmP_mant_SFG_SWR[25]), .S0(n2968), .Y(n1045)
);
AOI22X1TS U3697 ( .A0(n2962), .A1(n2954), .B0(n2960), .B1(n2953), .Y(n2957)
);
NAND2X1TS U3698 ( .A(n2143), .B(n2955), .Y(n2956) );
MX2X1TS U3699 ( .A(n3253), .B(DmP_mant_SFG_SWR[24]), .S0(n2968), .Y(n1046)
);
AOI22X1TS U3700 ( .A0(n2962), .A1(n2961), .B0(n2960), .B1(n2959), .Y(n2965)
);
NAND2X1TS U3701 ( .A(n2143), .B(n2963), .Y(n2964) );
OAI211X1TS U3702 ( .A0(n2967), .A1(n2966), .B0(n2965), .C0(n2964), .Y(n3261)
);
MX2X1TS U3703 ( .A(n3261), .B(DmP_mant_SFG_SWR[23]), .S0(n2968), .Y(n1047)
);
AFHCINX2TS U3704 ( .CIN(n2969), .B(n2970), .A(DMP_SFG[42]), .S(n2971), .CO(
n2975) );
INVX4TS U3705 ( .A(n3218), .Y(n3065) );
AFHCINX2TS U3706 ( .CIN(n2972), .B(n2973), .A(DMP_SFG[44]), .S(n2974), .CO(
n2996) );
AFHCONX2TS U3707 ( .A(DMP_SFG[43]), .B(n2976), .CI(n2975), .CON(n2972), .S(
n2977) );
XOR2X1TS U3708 ( .A(n2986), .B(DmP_mant_SFG_SWR[54]), .Y(n2987) );
XNOR2X1TS U3709 ( .A(n2988), .B(n2987), .Y(n2989) );
AFHCINX2TS U3710 ( .CIN(n2990), .B(n2991), .A(DMP_SFG[48]), .S(n2992), .CO(
n2981) );
AFHCINX2TS U3711 ( .CIN(n2993), .B(n2994), .A(DMP_SFG[46]), .S(n2995), .CO(
n2852) );
AFHCONX2TS U3712 ( .A(DMP_SFG[45]), .B(n2997), .CI(n2996), .CON(n2993), .S(
n2998) );
AFHCONX2TS U3713 ( .A(DMP_SFG[41]), .B(n3000), .CI(n2999), .CON(n2969), .S(
n3001) );
AFHCINX2TS U3714 ( .CIN(n3002), .B(n3003), .A(DMP_SFG[40]), .S(n3004), .CO(
n2999) );
AFHCONX2TS U3715 ( .A(DMP_SFG[39]), .B(n3006), .CI(n3005), .CON(n3002), .S(
n3007) );
AFHCINX2TS U3716 ( .CIN(n3008), .B(n3009), .A(DMP_SFG[38]), .S(n3010), .CO(
n3005) );
AFHCONX2TS U3717 ( .A(DMP_SFG[37]), .B(n3012), .CI(n3011), .CON(n3008), .S(
n3013) );
AFHCONX2TS U3718 ( .A(DMP_SFG[35]), .B(n3015), .CI(n3014), .CON(n3018), .S(
n3017) );
AFHCINX2TS U3719 ( .CIN(n3018), .B(n3019), .A(DMP_SFG[36]), .S(n3020), .CO(
n3011) );
AFHCINX2TS U3720 ( .CIN(n3021), .B(n3022), .A(DMP_SFG[34]), .S(n3023), .CO(
n3014) );
AFHCONX2TS U3721 ( .A(DMP_SFG[33]), .B(n3025), .CI(n3024), .CON(n3021), .S(
n3026) );
AFHCINX2TS U3722 ( .CIN(n3027), .B(n3028), .A(DMP_SFG[32]), .S(n3029), .CO(
n3024) );
AFHCONX2TS U3723 ( .A(DMP_SFG[31]), .B(n3031), .CI(n3030), .CON(n3027), .S(
n3032) );
AFHCINX2TS U3724 ( .CIN(n3033), .B(n3034), .A(DMP_SFG[30]), .S(n3035), .CO(
n3030) );
AFHCONX2TS U3725 ( .A(DMP_SFG[29]), .B(n3037), .CI(n3036), .CON(n3033), .S(
n3038) );
AFHCINX2TS U3726 ( .CIN(n3039), .B(n3040), .A(DMP_SFG[28]), .S(n3041), .CO(
n3036) );
MX2X1TS U3727 ( .A(Raw_mant_NRM_SWR[30]), .B(n3041), .S0(n3065), .Y(n1168)
);
AFHCINX2TS U3728 ( .CIN(n3042), .B(n3043), .A(DMP_SFG[26]), .S(n3044), .CO(
n3057) );
MX2X1TS U3729 ( .A(Raw_mant_NRM_SWR[28]), .B(n3044), .S0(n3065), .Y(n1170)
);
NAND2X1TS U3730 ( .A(n3084), .B(n3082), .Y(n3047) );
XNOR2X1TS U3731 ( .A(n3093), .B(n3047), .Y(n3048) );
MX2X1TS U3732 ( .A(Raw_mant_NRM_SWR[18]), .B(n3048), .S0(n3065), .Y(n1180)
);
AOI21X1TS U3733 ( .A0(n3102), .A1(n3100), .B0(n3050), .Y(n3055) );
NAND2X1TS U3734 ( .A(n3053), .B(n3052), .Y(n3054) );
XOR2XLTS U3735 ( .A(n3055), .B(n3054), .Y(n3056) );
MX2X1TS U3736 ( .A(Raw_mant_NRM_SWR[17]), .B(n3056), .S0(n3065), .Y(n1181)
);
AFHCONX2TS U3737 ( .A(DMP_SFG[27]), .B(n3058), .CI(n3057), .CON(n3039), .S(
n3059) );
MX2X1TS U3738 ( .A(Raw_mant_NRM_SWR[29]), .B(n3059), .S0(n3065), .Y(n1169)
);
AFHCONX2TS U3739 ( .A(DMP_SFG[25]), .B(n3061), .CI(n3060), .CON(n3042), .S(
n3062) );
MX2X1TS U3740 ( .A(Raw_mant_NRM_SWR[27]), .B(n3062), .S0(n3065), .Y(n1171)
);
AFHCINX2TS U3741 ( .CIN(n3063), .B(n3064), .A(DMP_SFG[24]), .S(n3066), .CO(
n3060) );
MX2X1TS U3742 ( .A(Raw_mant_NRM_SWR[26]), .B(n3066), .S0(n3065), .Y(n1172)
);
AFHCONX2TS U3743 ( .A(DMP_SFG[23]), .B(n3068), .CI(n3067), .CON(n3063), .S(
n3069) );
MX2X1TS U3744 ( .A(Raw_mant_NRM_SWR[25]), .B(n3069), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1173) );
AFHCINX2TS U3745 ( .CIN(n3070), .B(n3071), .A(DMP_SFG[22]), .S(n3072), .CO(
n3067) );
MX2X1TS U3746 ( .A(Raw_mant_NRM_SWR[24]), .B(n3072), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1174) );
AFHCONX2TS U3747 ( .A(DMP_SFG[21]), .B(n3074), .CI(n3073), .CON(n3070), .S(
n3075) );
MX2X1TS U3748 ( .A(Raw_mant_NRM_SWR[23]), .B(n3075), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1175) );
AFHCINX2TS U3749 ( .CIN(n3076), .B(n3077), .A(DMP_SFG[20]), .S(n3078), .CO(
n3073) );
MX2X1TS U3750 ( .A(Raw_mant_NRM_SWR[22]), .B(n3078), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1176) );
AFHCONX2TS U3751 ( .A(DMP_SFG[19]), .B(n3080), .CI(n3079), .CON(n3076), .S(
n3081) );
MX2X1TS U3752 ( .A(Raw_mant_NRM_SWR[21]), .B(n3081), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1177) );
AOI21X1TS U3753 ( .A0(n3093), .A1(n3084), .B0(n3083), .Y(n3089) );
NAND2X1TS U3754 ( .A(n3087), .B(n3086), .Y(n3088) );
XOR2XLTS U3755 ( .A(n3089), .B(n3088), .Y(n3090) );
MX2X1TS U3756 ( .A(Raw_mant_NRM_SWR[19]), .B(n3090), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1179) );
AOI21X1TS U3757 ( .A0(n3093), .A1(n3092), .B0(n3091), .Y(n3097) );
NAND2X1TS U3758 ( .A(n3095), .B(n3094), .Y(n3096) );
XOR2XLTS U3759 ( .A(n3097), .B(n3096), .Y(n3098) );
MX2X1TS U3760 ( .A(Raw_mant_NRM_SWR[20]), .B(n3098), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1178) );
NAND2X1TS U3761 ( .A(n3100), .B(n3099), .Y(n3101) );
XNOR2X1TS U3762 ( .A(n3102), .B(n3101), .Y(n3103) );
MX2X1TS U3763 ( .A(Raw_mant_NRM_SWR[16]), .B(n3103), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1182) );
MX2X1TS U3764 ( .A(Raw_mant_NRM_SWR[15]), .B(n3107), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1183) );
MX2X1TS U3765 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1311) );
MX2X1TS U3766 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1316) );
MX2X1TS U3767 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1321) );
MX2X1TS U3768 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1326) );
MX2X1TS U3769 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1331) );
MX2X1TS U3770 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n1885),
.Y(n1336) );
MX2X1TS U3771 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n1885),
.Y(n1341) );
MX2X1TS U3772 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n1885),
.Y(n1346) );
MX2X1TS U3773 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n1885),
.Y(n1351) );
MX2X1TS U3774 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n1885),
.Y(n1356) );
MX2X1TS U3775 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n1885),
.Y(n1361) );
OAI2BB1X1TS U3776 ( .A0N(LZD_output_NRM2_EW[5]), .A1N(n3137), .B0(n3108),
.Y(n1141) );
OAI2BB1X1TS U3777 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n3137), .B0(n3109),
.Y(n1135) );
NOR3BX1TS U3778 ( .AN(n3111), .B(n3110), .C(Raw_mant_NRM_SWR[47]), .Y(n3119)
);
OAI2BB2XLTS U3779 ( .B0(n3419), .B1(n3113), .A0N(Raw_mant_NRM_SWR[24]),
.A1N(n3112), .Y(n3117) );
OAI22X1TS U3780 ( .A0(n3292), .A1(n3115), .B0(n3423), .B1(n3114), .Y(n3116)
);
NOR4X1TS U3781 ( .A(n3119), .B(n3118), .C(n3117), .D(n3116), .Y(n3121) );
OAI21X1TS U3782 ( .A0(n3126), .A1(n3125), .B0(Shift_reg_FLAGS_7[1]), .Y(
n3163) );
OAI2BB1X1TS U3783 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n3137), .B0(n3163),
.Y(n1125) );
OAI2BB1X1TS U3784 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n3137), .B0(n3127),
.Y(n1122) );
OAI2BB1X1TS U3785 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n3137), .B0(n3128),
.Y(n1138) );
INVX4TS U3786 ( .A(n3247), .Y(n3280) );
INVX2TS U3787 ( .A(n3130), .Y(n3132) );
AOI22X1TS U3788 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n3132), .B1(n3304), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U3789 ( .A(n3132), .B(n3131), .Y(n1803) );
INVX2TS U3790 ( .A(n3138), .Y(n3135) );
AO22XLTS U3791 ( .A0(n3135), .A1(n3211), .B0(n3138), .B1(n3133), .Y(n1801)
);
AOI22X1TS U3792 ( .A0(n3138), .A1(n3134), .B0(n3208), .B1(n3135), .Y(n1800)
);
AOI22X1TS U3793 ( .A0(n3138), .A1(n3208), .B0(n3189), .B1(n3135), .Y(n1799)
);
AO22XLTS U3794 ( .A0(n3138), .A1(busy), .B0(n3135), .B1(Shift_reg_FLAGS_7[3]), .Y(n1798) );
AOI22X1TS U3795 ( .A0(n3138), .A1(n3218), .B0(n3137), .B1(n3135), .Y(n1796)
);
AOI22X1TS U3796 ( .A0(n3138), .A1(n3137), .B0(n3219), .B1(n3135), .Y(n1795)
);
CLKBUFX2TS U3797 ( .A(n3140), .Y(n3160) );
INVX2TS U3798 ( .A(n3139), .Y(n3150) );
AO22XLTS U3799 ( .A0(n3156), .A1(Data_X[3]), .B0(n3150), .B1(intDX_EWSW[3]),
.Y(n1791) );
AO22XLTS U3800 ( .A0(n3143), .A1(Data_X[8]), .B0(n3142), .B1(intDX_EWSW[8]),
.Y(n1786) );
AO22XLTS U3801 ( .A0(n3156), .A1(Data_X[11]), .B0(n3142), .B1(intDX_EWSW[11]), .Y(n1783) );
BUFX3TS U3802 ( .A(n3146), .Y(n3145) );
AO22XLTS U3803 ( .A0(n3143), .A1(Data_X[25]), .B0(n3141), .B1(intDX_EWSW[25]), .Y(n1769) );
AO22XLTS U3804 ( .A0(n3143), .A1(Data_X[26]), .B0(n3141), .B1(intDX_EWSW[26]), .Y(n1768) );
AO22XLTS U3805 ( .A0(n3143), .A1(Data_X[27]), .B0(n3141), .B1(intDX_EWSW[27]), .Y(n1767) );
AO22XLTS U3806 ( .A0(n3143), .A1(Data_X[28]), .B0(n3141), .B1(intDX_EWSW[28]), .Y(n1766) );
AO22XLTS U3807 ( .A0(n3143), .A1(Data_X[29]), .B0(n3141), .B1(intDX_EWSW[29]), .Y(n1765) );
AO22XLTS U3808 ( .A0(n3143), .A1(Data_X[30]), .B0(n3141), .B1(intDX_EWSW[30]), .Y(n1764) );
INVX4TS U3809 ( .A(n3160), .Y(n3144) );
AO22XLTS U3810 ( .A0(n3143), .A1(Data_X[31]), .B0(n3144), .B1(intDX_EWSW[31]), .Y(n1763) );
INVX4TS U3811 ( .A(n3160), .Y(n3148) );
AO22XLTS U3812 ( .A0(n3156), .A1(Data_X[33]), .B0(n3141), .B1(intDX_EWSW[33]), .Y(n1761) );
AO22XLTS U3813 ( .A0(n3156), .A1(Data_X[34]), .B0(n3144), .B1(intDX_EWSW[34]), .Y(n1760) );
AO22XLTS U3814 ( .A0(n3156), .A1(Data_X[35]), .B0(n3142), .B1(intDX_EWSW[35]), .Y(n1759) );
AO22XLTS U3815 ( .A0(n3156), .A1(Data_X[36]), .B0(n3141), .B1(intDX_EWSW[36]), .Y(n1758) );
INVX4TS U3816 ( .A(n3160), .Y(n3147) );
AO22XLTS U3817 ( .A0(n3143), .A1(Data_X[46]), .B0(n3157), .B1(intDX_EWSW[46]), .Y(n1748) );
AO22XLTS U3818 ( .A0(n3156), .A1(Data_X[50]), .B0(n3157), .B1(intDX_EWSW[50]), .Y(n1744) );
AO22XLTS U3819 ( .A0(n3156), .A1(Data_X[51]), .B0(n3157), .B1(intDX_EWSW[51]), .Y(n1743) );
AO22XLTS U3820 ( .A0(n3156), .A1(Data_X[57]), .B0(n3157), .B1(intDX_EWSW[57]), .Y(n1737) );
AO22XLTS U3821 ( .A0(n3144), .A1(intDX_EWSW[60]), .B0(n3146), .B1(Data_X[60]), .Y(n1734) );
AO22XLTS U3822 ( .A0(n3156), .A1(add_subt), .B0(n3157), .B1(intAS), .Y(n1730) );
AO22XLTS U3823 ( .A0(n3159), .A1(intDY_EWSW[4]), .B0(n3152), .B1(Data_Y[4]),
.Y(n1724) );
AO22XLTS U3824 ( .A0(n3144), .A1(intDY_EWSW[11]), .B0(n3153), .B1(Data_Y[11]), .Y(n1717) );
AO22XLTS U3825 ( .A0(n3147), .A1(intDY_EWSW[14]), .B0(n3146), .B1(Data_Y[14]), .Y(n1714) );
AO22XLTS U3826 ( .A0(n3147), .A1(intDY_EWSW[15]), .B0(n3153), .B1(Data_Y[15]), .Y(n1713) );
AO22XLTS U3827 ( .A0(n3147), .A1(intDY_EWSW[17]), .B0(n3153), .B1(Data_Y[17]), .Y(n1711) );
AO22XLTS U3828 ( .A0(n3147), .A1(intDY_EWSW[18]), .B0(n3153), .B1(Data_Y[18]), .Y(n1710) );
BUFX3TS U3829 ( .A(n3140), .Y(n3154) );
AO22XLTS U3830 ( .A0(n3147), .A1(intDY_EWSW[19]), .B0(n3154), .B1(Data_Y[19]), .Y(n1709) );
AO22XLTS U3831 ( .A0(n3148), .A1(intDY_EWSW[20]), .B0(n3153), .B1(Data_Y[20]), .Y(n1708) );
AO22XLTS U3832 ( .A0(n3147), .A1(intDY_EWSW[21]), .B0(n3153), .B1(Data_Y[21]), .Y(n1707) );
AO22XLTS U3833 ( .A0(n3148), .A1(intDY_EWSW[22]), .B0(n3146), .B1(Data_Y[22]), .Y(n1706) );
AO22XLTS U3834 ( .A0(n3147), .A1(intDY_EWSW[23]), .B0(n3154), .B1(Data_Y[23]), .Y(n1705) );
AO22XLTS U3835 ( .A0(n3148), .A1(intDY_EWSW[24]), .B0(n3154), .B1(Data_Y[24]), .Y(n1704) );
AO22XLTS U3836 ( .A0(n3148), .A1(intDY_EWSW[25]), .B0(n3154), .B1(Data_Y[25]), .Y(n1703) );
AO22XLTS U3837 ( .A0(n3148), .A1(intDY_EWSW[26]), .B0(n3153), .B1(Data_Y[26]), .Y(n1702) );
AO22XLTS U3838 ( .A0(n3148), .A1(intDY_EWSW[28]), .B0(n3154), .B1(Data_Y[28]), .Y(n1700) );
AO22XLTS U3839 ( .A0(n3148), .A1(intDY_EWSW[29]), .B0(n3154), .B1(Data_Y[29]), .Y(n1699) );
INVX4TS U3840 ( .A(n3158), .Y(n3155) );
AO22XLTS U3841 ( .A0(n3148), .A1(intDY_EWSW[35]), .B0(n3153), .B1(Data_Y[35]), .Y(n1693) );
AO22XLTS U3842 ( .A0(n3150), .A1(intDY_EWSW[39]), .B0(n3154), .B1(Data_Y[39]), .Y(n1689) );
AO22XLTS U3843 ( .A0(n3159), .A1(intDY_EWSW[40]), .B0(n3153), .B1(Data_Y[40]), .Y(n1688) );
AO22XLTS U3844 ( .A0(n3151), .A1(intDY_EWSW[42]), .B0(n3153), .B1(Data_Y[42]), .Y(n1686) );
AO22XLTS U3845 ( .A0(n3159), .A1(intDY_EWSW[43]), .B0(n3154), .B1(Data_Y[43]), .Y(n1685) );
AO22XLTS U3846 ( .A0(n3155), .A1(intDY_EWSW[44]), .B0(n3154), .B1(Data_Y[44]), .Y(n1684) );
AO22XLTS U3847 ( .A0(n3157), .A1(intDY_EWSW[45]), .B0(n3152), .B1(Data_Y[45]), .Y(n1683) );
AO22XLTS U3848 ( .A0(n3155), .A1(intDY_EWSW[46]), .B0(n3152), .B1(Data_Y[46]), .Y(n1682) );
AO22XLTS U3849 ( .A0(n3151), .A1(intDY_EWSW[47]), .B0(n3154), .B1(Data_Y[47]), .Y(n1681) );
AO22XLTS U3850 ( .A0(n3155), .A1(intDY_EWSW[48]), .B0(n3153), .B1(Data_Y[48]), .Y(n1680) );
AO22XLTS U3851 ( .A0(n3155), .A1(intDY_EWSW[49]), .B0(n3152), .B1(Data_Y[49]), .Y(n1679) );
AO22XLTS U3852 ( .A0(n3155), .A1(intDY_EWSW[50]), .B0(n3153), .B1(Data_Y[50]), .Y(n1678) );
AO22XLTS U3853 ( .A0(n3155), .A1(intDY_EWSW[51]), .B0(n3154), .B1(Data_Y[51]), .Y(n1677) );
AO22XLTS U3854 ( .A0(n3155), .A1(intDY_EWSW[52]), .B0(n3153), .B1(Data_Y[52]), .Y(n1676) );
AO22XLTS U3855 ( .A0(n3155), .A1(intDY_EWSW[53]), .B0(n3152), .B1(Data_Y[53]), .Y(n1675) );
AO22XLTS U3856 ( .A0(n3155), .A1(intDY_EWSW[54]), .B0(n3153), .B1(Data_Y[54]), .Y(n1674) );
AO22XLTS U3857 ( .A0(n3155), .A1(intDY_EWSW[55]), .B0(n3154), .B1(Data_Y[55]), .Y(n1673) );
AO22XLTS U3858 ( .A0(n3155), .A1(intDY_EWSW[56]), .B0(n3154), .B1(Data_Y[56]), .Y(n1672) );
AO22XLTS U3859 ( .A0(n3155), .A1(intDY_EWSW[57]), .B0(n3154), .B1(Data_Y[57]), .Y(n1671) );
AOI22X1TS U3860 ( .A0(n3162), .A1(shift_value_SHT2_EWR[3]), .B0(n3161), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n3164) );
NAND2X1TS U3861 ( .A(n3164), .B(n3163), .Y(n1608) );
NAND2X1TS U3862 ( .A(DmP_EXP_EWSW[52]), .B(n3424), .Y(n3169) );
OAI21XLTS U3863 ( .A0(DmP_EXP_EWSW[52]), .A1(n3424), .B0(n3169), .Y(n3165)
);
NAND2X1TS U3864 ( .A(DmP_EXP_EWSW[53]), .B(n3316), .Y(n3168) );
XNOR2X1TS U3865 ( .A(n3169), .B(n3166), .Y(n3167) );
BUFX3TS U3866 ( .A(n3430), .Y(n3192) );
AO22XLTS U3867 ( .A0(n3186), .A1(n3167), .B0(n3192), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n1603) );
AOI22X1TS U3868 ( .A0(DMP_EXP_EWSW[53]), .A1(n3318), .B0(n3169), .B1(n3168),
.Y(n3172) );
NOR2X1TS U3869 ( .A(n1821), .B(DMP_EXP_EWSW[54]), .Y(n3173) );
AOI21X1TS U3870 ( .A0(DMP_EXP_EWSW[54]), .A1(n1821), .B0(n3173), .Y(n3170)
);
XNOR2X1TS U3871 ( .A(n3172), .B(n3170), .Y(n3171) );
AO22XLTS U3872 ( .A0(n3186), .A1(n3171), .B0(n3192), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n1602) );
OAI22X1TS U3873 ( .A0(n3173), .A1(n3172), .B0(DmP_EXP_EWSW[54]), .B1(n3317),
.Y(n3176) );
NAND2X1TS U3874 ( .A(DmP_EXP_EWSW[55]), .B(n3319), .Y(n3177) );
OAI21XLTS U3875 ( .A0(DmP_EXP_EWSW[55]), .A1(n3319), .B0(n3177), .Y(n3174)
);
XNOR2X1TS U3876 ( .A(n3176), .B(n3174), .Y(n3175) );
AO22XLTS U3877 ( .A0(n3186), .A1(n3175), .B0(n3192), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n1601) );
AOI22X1TS U3878 ( .A0(DMP_EXP_EWSW[55]), .A1(n3322), .B0(n3177), .B1(n3176),
.Y(n3180) );
NOR2X1TS U3879 ( .A(n3212), .B(DMP_EXP_EWSW[56]), .Y(n3181) );
AOI21X1TS U3880 ( .A0(DMP_EXP_EWSW[56]), .A1(n3212), .B0(n3181), .Y(n3178)
);
XNOR2X1TS U3881 ( .A(n3180), .B(n3178), .Y(n3179) );
AO22XLTS U3882 ( .A0(n3186), .A1(n3179), .B0(n3192), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n1600) );
OAI22X1TS U3883 ( .A0(n3181), .A1(n3180), .B0(DmP_EXP_EWSW[56]), .B1(n3321),
.Y(n3183) );
XNOR2X1TS U3884 ( .A(DmP_EXP_EWSW[57]), .B(n1864), .Y(n3182) );
XOR2XLTS U3885 ( .A(n3183), .B(n3182), .Y(n3184) );
AO22XLTS U3886 ( .A0(n3186), .A1(n3184), .B0(n3192), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n1599) );
AO22XLTS U3887 ( .A0(n3186), .A1(DMP_EXP_EWSW[0]), .B0(n3192), .B1(
DMP_SHT1_EWSW[0]), .Y(n1521) );
AO22XLTS U3888 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n3189), .B1(
DMP_SHT2_EWSW[0]), .Y(n1520) );
INVX4TS U3889 ( .A(n2883), .Y(n3252) );
AO22XLTS U3890 ( .A0(n2883), .A1(DMP_SHT2_EWSW[0]), .B0(n3252), .B1(
DMP_SFG[0]), .Y(n1519) );
AO22XLTS U3891 ( .A0(n3186), .A1(DMP_EXP_EWSW[1]), .B0(n3192), .B1(
DMP_SHT1_EWSW[1]), .Y(n1518) );
AO22XLTS U3892 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n3189), .B1(
DMP_SHT2_EWSW[1]), .Y(n1517) );
AO22XLTS U3893 ( .A0(n3185), .A1(DMP_SHT2_EWSW[1]), .B0(n3252), .B1(
DMP_SFG[1]), .Y(n1516) );
AO22XLTS U3894 ( .A0(n3186), .A1(DMP_EXP_EWSW[2]), .B0(n3192), .B1(
DMP_SHT1_EWSW[2]), .Y(n1515) );
AO22XLTS U3895 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n3189), .B1(
DMP_SHT2_EWSW[2]), .Y(n1514) );
AO22XLTS U3896 ( .A0(n3258), .A1(DMP_SHT2_EWSW[2]), .B0(n3252), .B1(
DMP_SFG[2]), .Y(n1513) );
AO22XLTS U3897 ( .A0(n3186), .A1(DMP_EXP_EWSW[3]), .B0(n3192), .B1(
DMP_SHT1_EWSW[3]), .Y(n1512) );
BUFX3TS U3898 ( .A(n3503), .Y(n3190) );
AO22XLTS U3899 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n3190), .B1(
DMP_SHT2_EWSW[3]), .Y(n1511) );
AO22XLTS U3900 ( .A0(n3198), .A1(DMP_SHT2_EWSW[3]), .B0(n3252), .B1(
DMP_SFG[3]), .Y(n1510) );
AO22XLTS U3901 ( .A0(n3186), .A1(DMP_EXP_EWSW[4]), .B0(n3191), .B1(
DMP_SHT1_EWSW[4]), .Y(n1509) );
AO22XLTS U3902 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n3190), .B1(
DMP_SHT2_EWSW[4]), .Y(n1508) );
AO22XLTS U3903 ( .A0(n3217), .A1(DMP_SHT2_EWSW[4]), .B0(n3252), .B1(
DMP_SFG[4]), .Y(n1507) );
AO22XLTS U3904 ( .A0(n3186), .A1(DMP_EXP_EWSW[5]), .B0(n3191), .B1(
DMP_SHT1_EWSW[5]), .Y(n1506) );
AO22XLTS U3905 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n3190), .B1(
DMP_SHT2_EWSW[5]), .Y(n1505) );
AO22XLTS U3906 ( .A0(n3198), .A1(DMP_SHT2_EWSW[5]), .B0(n3224), .B1(
DMP_SFG[5]), .Y(n1504) );
AO22XLTS U3907 ( .A0(n3187), .A1(DMP_EXP_EWSW[6]), .B0(n3191), .B1(
DMP_SHT1_EWSW[6]), .Y(n1503) );
AO22XLTS U3908 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n3190), .B1(
DMP_SHT2_EWSW[6]), .Y(n1502) );
AO22XLTS U3909 ( .A0(n3185), .A1(DMP_SHT2_EWSW[6]), .B0(n3252), .B1(
DMP_SFG[6]), .Y(n1501) );
AO22XLTS U3910 ( .A0(n3187), .A1(DMP_EXP_EWSW[7]), .B0(n3191), .B1(
DMP_SHT1_EWSW[7]), .Y(n1500) );
AO22XLTS U3911 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n3190), .B1(
DMP_SHT2_EWSW[7]), .Y(n1499) );
AO22XLTS U3912 ( .A0(n3258), .A1(DMP_SHT2_EWSW[7]), .B0(n3252), .B1(
DMP_SFG[7]), .Y(n1498) );
AO22XLTS U3913 ( .A0(n3187), .A1(DMP_EXP_EWSW[8]), .B0(n3191), .B1(
DMP_SHT1_EWSW[8]), .Y(n1497) );
AO22XLTS U3914 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n3190), .B1(
DMP_SHT2_EWSW[8]), .Y(n1496) );
AO22XLTS U3915 ( .A0(n3217), .A1(DMP_SHT2_EWSW[8]), .B0(n3224), .B1(
DMP_SFG[8]), .Y(n1495) );
AO22XLTS U3916 ( .A0(n3187), .A1(DMP_EXP_EWSW[9]), .B0(n3191), .B1(
DMP_SHT1_EWSW[9]), .Y(n1494) );
AO22XLTS U3917 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n3190), .B1(
DMP_SHT2_EWSW[9]), .Y(n1493) );
AO22XLTS U3918 ( .A0(n3246), .A1(DMP_SHT2_EWSW[9]), .B0(n3252), .B1(
DMP_SFG[9]), .Y(n1492) );
AO22XLTS U3919 ( .A0(n3187), .A1(DMP_EXP_EWSW[10]), .B0(n3191), .B1(
DMP_SHT1_EWSW[10]), .Y(n1491) );
AO22XLTS U3920 ( .A0(busy), .A1(DMP_SHT1_EWSW[10]), .B0(n3190), .B1(
DMP_SHT2_EWSW[10]), .Y(n1490) );
AO22XLTS U3921 ( .A0(n3198), .A1(DMP_SHT2_EWSW[10]), .B0(n3252), .B1(
DMP_SFG[10]), .Y(n1489) );
AO22XLTS U3922 ( .A0(n3187), .A1(DMP_EXP_EWSW[11]), .B0(n3191), .B1(
DMP_SHT1_EWSW[11]), .Y(n1488) );
AO22XLTS U3923 ( .A0(busy), .A1(DMP_SHT1_EWSW[11]), .B0(n3190), .B1(
DMP_SHT2_EWSW[11]), .Y(n1487) );
AO22XLTS U3924 ( .A0(n2883), .A1(DMP_SHT2_EWSW[11]), .B0(n3252), .B1(
DMP_SFG[11]), .Y(n1486) );
AO22XLTS U3925 ( .A0(n3187), .A1(DMP_EXP_EWSW[12]), .B0(n3191), .B1(
DMP_SHT1_EWSW[12]), .Y(n1485) );
AO22XLTS U3926 ( .A0(n3187), .A1(DMP_EXP_EWSW[13]), .B0(n3191), .B1(
DMP_SHT1_EWSW[13]), .Y(n1482) );
AO22XLTS U3927 ( .A0(n3187), .A1(DMP_EXP_EWSW[14]), .B0(n3191), .B1(
DMP_SHT1_EWSW[14]), .Y(n1479) );
AO22XLTS U3928 ( .A0(n3187), .A1(DMP_EXP_EWSW[15]), .B0(n3430), .B1(
DMP_SHT1_EWSW[15]), .Y(n1476) );
AO22XLTS U3929 ( .A0(n3187), .A1(DMP_EXP_EWSW[16]), .B0(n3208), .B1(
DMP_SHT1_EWSW[16]), .Y(n1473) );
AO22XLTS U3930 ( .A0(n3187), .A1(DMP_EXP_EWSW[17]), .B0(n3208), .B1(
DMP_SHT1_EWSW[17]), .Y(n1470) );
AO22XLTS U3931 ( .A0(busy), .A1(DMP_SHT1_EWSW[17]), .B0(n3190), .B1(
DMP_SHT2_EWSW[17]), .Y(n1469) );
BUFX3TS U3932 ( .A(n3430), .Y(n3207) );
AO22XLTS U3933 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[18]), .B0(n3206),
.B1(DMP_SHT1_EWSW[18]), .Y(n1467) );
AO22XLTS U3934 ( .A0(n3505), .A1(DMP_SHT1_EWSW[18]), .B0(n3190), .B1(
DMP_SHT2_EWSW[18]), .Y(n1466) );
BUFX3TS U3935 ( .A(n3207), .Y(n3205) );
AO22XLTS U3936 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[19]), .B0(n3205),
.B1(DMP_SHT1_EWSW[19]), .Y(n1464) );
AO22XLTS U3937 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1847), .B1(
DMP_SHT2_EWSW[19]), .Y(n1463) );
AO22XLTS U3938 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[20]), .B0(n3208),
.B1(DMP_SHT1_EWSW[20]), .Y(n1461) );
AO22XLTS U3939 ( .A0(n3505), .A1(DMP_SHT1_EWSW[20]), .B0(n3190), .B1(
DMP_SHT2_EWSW[20]), .Y(n1460) );
AO22XLTS U3940 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[21]), .B0(n3206),
.B1(DMP_SHT1_EWSW[21]), .Y(n1458) );
AO22XLTS U3941 ( .A0(n3505), .A1(DMP_SHT1_EWSW[21]), .B0(n1847), .B1(
DMP_SHT2_EWSW[21]), .Y(n1457) );
AO22XLTS U3942 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[22]), .B0(n3205),
.B1(DMP_SHT1_EWSW[22]), .Y(n1455) );
AO22XLTS U3943 ( .A0(n3505), .A1(DMP_SHT1_EWSW[22]), .B0(n3190), .B1(
DMP_SHT2_EWSW[22]), .Y(n1454) );
AO22XLTS U3944 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[23]), .B0(n3206),
.B1(DMP_SHT1_EWSW[23]), .Y(n1452) );
AO22XLTS U3945 ( .A0(n3505), .A1(DMP_SHT1_EWSW[23]), .B0(n1847), .B1(
DMP_SHT2_EWSW[23]), .Y(n1451) );
AO22XLTS U3946 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[24]), .B0(n3205),
.B1(DMP_SHT1_EWSW[24]), .Y(n1449) );
AO22XLTS U3947 ( .A0(n3505), .A1(DMP_SHT1_EWSW[24]), .B0(n3194), .B1(
DMP_SHT2_EWSW[24]), .Y(n1448) );
AO22XLTS U3948 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[25]), .B0(n3206),
.B1(DMP_SHT1_EWSW[25]), .Y(n1446) );
AO22XLTS U3949 ( .A0(n3505), .A1(DMP_SHT1_EWSW[25]), .B0(n3189), .B1(
DMP_SHT2_EWSW[25]), .Y(n1445) );
AO22XLTS U3950 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[26]), .B0(n3191),
.B1(DMP_SHT1_EWSW[26]), .Y(n1443) );
AO22XLTS U3951 ( .A0(n3505), .A1(DMP_SHT1_EWSW[26]), .B0(n3189), .B1(
DMP_SHT2_EWSW[26]), .Y(n1442) );
AO22XLTS U3952 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[27]), .B0(n3191),
.B1(DMP_SHT1_EWSW[27]), .Y(n1440) );
AO22XLTS U3953 ( .A0(n3505), .A1(DMP_SHT1_EWSW[27]), .B0(n3194), .B1(
DMP_SHT2_EWSW[27]), .Y(n1439) );
AO22XLTS U3954 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[28]), .B0(n3191),
.B1(DMP_SHT1_EWSW[28]), .Y(n1437) );
INVX4TS U3955 ( .A(n3189), .Y(n3195) );
AO22XLTS U3956 ( .A0(n3195), .A1(DMP_SHT1_EWSW[28]), .B0(n3190), .B1(
DMP_SHT2_EWSW[28]), .Y(n1436) );
AO22XLTS U3957 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[29]), .B0(n3208),
.B1(DMP_SHT1_EWSW[29]), .Y(n1434) );
AO22XLTS U3958 ( .A0(n3195), .A1(DMP_SHT1_EWSW[29]), .B0(n1847), .B1(
DMP_SHT2_EWSW[29]), .Y(n1433) );
CLKBUFX2TS U3959 ( .A(n3430), .Y(n3220) );
AO22XLTS U3960 ( .A0(n3202), .A1(DMP_EXP_EWSW[30]), .B0(n3208), .B1(
DMP_SHT1_EWSW[30]), .Y(n1431) );
AO22XLTS U3961 ( .A0(n3195), .A1(DMP_SHT1_EWSW[30]), .B0(n1847), .B1(
DMP_SHT2_EWSW[30]), .Y(n1430) );
AO22XLTS U3962 ( .A0(n3202), .A1(DMP_EXP_EWSW[31]), .B0(n3191), .B1(
DMP_SHT1_EWSW[31]), .Y(n1428) );
AO22XLTS U3963 ( .A0(n3195), .A1(DMP_SHT1_EWSW[31]), .B0(n1847), .B1(
DMP_SHT2_EWSW[31]), .Y(n1427) );
AO22XLTS U3964 ( .A0(n3204), .A1(DMP_EXP_EWSW[32]), .B0(n3192), .B1(
DMP_SHT1_EWSW[32]), .Y(n1425) );
AO22XLTS U3965 ( .A0(n3195), .A1(DMP_SHT1_EWSW[32]), .B0(n1847), .B1(
DMP_SHT2_EWSW[32]), .Y(n1424) );
AO22XLTS U3966 ( .A0(n3202), .A1(DMP_EXP_EWSW[33]), .B0(n3192), .B1(
DMP_SHT1_EWSW[33]), .Y(n1422) );
AO22XLTS U3967 ( .A0(n3195), .A1(DMP_SHT1_EWSW[33]), .B0(n1847), .B1(
DMP_SHT2_EWSW[33]), .Y(n1421) );
AO22XLTS U3968 ( .A0(n3200), .A1(DMP_EXP_EWSW[34]), .B0(n3192), .B1(
DMP_SHT1_EWSW[34]), .Y(n1419) );
AO22XLTS U3969 ( .A0(n3195), .A1(DMP_SHT1_EWSW[34]), .B0(n1847), .B1(
DMP_SHT2_EWSW[34]), .Y(n1418) );
AO22XLTS U3970 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[35]), .B0(n3192),
.B1(DMP_SHT1_EWSW[35]), .Y(n1416) );
AO22XLTS U3971 ( .A0(n3195), .A1(DMP_SHT1_EWSW[35]), .B0(n1847), .B1(
DMP_SHT2_EWSW[35]), .Y(n1415) );
AO22XLTS U3972 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[36]), .B0(n3192),
.B1(DMP_SHT1_EWSW[36]), .Y(n1413) );
AO22XLTS U3973 ( .A0(n3195), .A1(DMP_SHT1_EWSW[36]), .B0(n1847), .B1(
DMP_SHT2_EWSW[36]), .Y(n1412) );
BUFX3TS U3974 ( .A(n3430), .Y(n3201) );
AO22XLTS U3975 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[37]), .B0(n3203),
.B1(DMP_SHT1_EWSW[37]), .Y(n1410) );
AO22XLTS U3976 ( .A0(n3195), .A1(DMP_SHT1_EWSW[37]), .B0(n1847), .B1(
DMP_SHT2_EWSW[37]), .Y(n1409) );
AO22XLTS U3977 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[38]), .B0(n3203),
.B1(DMP_SHT1_EWSW[38]), .Y(n1407) );
AO22XLTS U3978 ( .A0(n3195), .A1(DMP_SHT1_EWSW[38]), .B0(n1847), .B1(
DMP_SHT2_EWSW[38]), .Y(n1406) );
AO22XLTS U3979 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[39]), .B0(n3203),
.B1(DMP_SHT1_EWSW[39]), .Y(n1404) );
AO22XLTS U3980 ( .A0(n3195), .A1(DMP_SHT1_EWSW[39]), .B0(n1847), .B1(
DMP_SHT2_EWSW[39]), .Y(n1403) );
AO22XLTS U3981 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[40]), .B0(n3203),
.B1(DMP_SHT1_EWSW[40]), .Y(n1401) );
AO22XLTS U3982 ( .A0(n3195), .A1(DMP_SHT1_EWSW[40]), .B0(n1847), .B1(
DMP_SHT2_EWSW[40]), .Y(n1400) );
AO22XLTS U3983 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[41]), .B0(n3203),
.B1(DMP_SHT1_EWSW[41]), .Y(n1398) );
INVX2TS U3984 ( .A(n3505), .Y(n3196) );
AO22XLTS U3985 ( .A0(n3195), .A1(DMP_SHT1_EWSW[41]), .B0(n3196), .B1(
DMP_SHT2_EWSW[41]), .Y(n1397) );
AO22XLTS U3986 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[42]), .B0(n3203),
.B1(DMP_SHT1_EWSW[42]), .Y(n1395) );
INVX4TS U3987 ( .A(n3194), .Y(n3199) );
AO22XLTS U3988 ( .A0(n3199), .A1(DMP_SHT1_EWSW[42]), .B0(n3196), .B1(
DMP_SHT2_EWSW[42]), .Y(n1394) );
AO22XLTS U3989 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[43]), .B0(n3203),
.B1(DMP_SHT1_EWSW[43]), .Y(n1392) );
AO22XLTS U3990 ( .A0(n3199), .A1(DMP_SHT1_EWSW[43]), .B0(n3194), .B1(
DMP_SHT2_EWSW[43]), .Y(n1391) );
AO22XLTS U3991 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[44]), .B0(n3203),
.B1(DMP_SHT1_EWSW[44]), .Y(n1389) );
AO22XLTS U3992 ( .A0(n3199), .A1(DMP_SHT1_EWSW[44]), .B0(n3196), .B1(
DMP_SHT2_EWSW[44]), .Y(n1388) );
AO22XLTS U3993 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[45]), .B0(n3203),
.B1(DMP_SHT1_EWSW[45]), .Y(n1386) );
AO22XLTS U3994 ( .A0(n3199), .A1(DMP_SHT1_EWSW[45]), .B0(n3503), .B1(
DMP_SHT2_EWSW[45]), .Y(n1385) );
AO22XLTS U3995 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[46]), .B0(n3203),
.B1(DMP_SHT1_EWSW[46]), .Y(n1383) );
AO22XLTS U3996 ( .A0(n3199), .A1(DMP_SHT1_EWSW[46]), .B0(n3196), .B1(
DMP_SHT2_EWSW[46]), .Y(n1382) );
AO22XLTS U3997 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[47]), .B0(n3203),
.B1(DMP_SHT1_EWSW[47]), .Y(n1380) );
AO22XLTS U3998 ( .A0(n3199), .A1(DMP_SHT1_EWSW[47]), .B0(n3196), .B1(
DMP_SHT2_EWSW[47]), .Y(n1379) );
BUFX3TS U3999 ( .A(n3430), .Y(n3221) );
AO22XLTS U4000 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[48]), .B0(n3221),
.B1(DMP_SHT1_EWSW[48]), .Y(n1377) );
AO22XLTS U4001 ( .A0(n3199), .A1(DMP_SHT1_EWSW[48]), .B0(n3196), .B1(
DMP_SHT2_EWSW[48]), .Y(n1376) );
AO22XLTS U4002 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[49]), .B0(n3221),
.B1(DMP_SHT1_EWSW[49]), .Y(n1374) );
AO22XLTS U4003 ( .A0(n3195), .A1(DMP_SHT1_EWSW[49]), .B0(n3196), .B1(
DMP_SHT2_EWSW[49]), .Y(n1373) );
AO22XLTS U4004 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[50]), .B0(n3221),
.B1(DMP_SHT1_EWSW[50]), .Y(n1371) );
AO22XLTS U4005 ( .A0(n3199), .A1(DMP_SHT1_EWSW[50]), .B0(n3196), .B1(
DMP_SHT2_EWSW[50]), .Y(n1370) );
AO22XLTS U4006 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[51]), .B0(n3221),
.B1(DMP_SHT1_EWSW[51]), .Y(n1368) );
AO22XLTS U4007 ( .A0(n3199), .A1(DMP_SHT1_EWSW[51]), .B0(n3196), .B1(
DMP_SHT2_EWSW[51]), .Y(n1367) );
AO22XLTS U4008 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[52]), .B0(n3221),
.B1(DMP_SHT1_EWSW[52]), .Y(n1365) );
AO22XLTS U4009 ( .A0(n3199), .A1(DMP_SHT1_EWSW[52]), .B0(n3503), .B1(
DMP_SHT2_EWSW[52]), .Y(n1364) );
AO22XLTS U4010 ( .A0(n3258), .A1(DMP_SHT2_EWSW[52]), .B0(n3224), .B1(
DMP_SFG[52]), .Y(n1363) );
AO22XLTS U4011 ( .A0(n3225), .A1(DMP_SFG[52]), .B0(n3431), .B1(
DMP_exp_NRM_EW[0]), .Y(n1362) );
AO22XLTS U4012 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[53]), .B0(n3221),
.B1(DMP_SHT1_EWSW[53]), .Y(n1360) );
AO22XLTS U4013 ( .A0(n3199), .A1(DMP_SHT1_EWSW[53]), .B0(n3503), .B1(
DMP_SHT2_EWSW[53]), .Y(n1359) );
AO22XLTS U4014 ( .A0(n3185), .A1(DMP_SHT2_EWSW[53]), .B0(n3252), .B1(
DMP_SFG[53]), .Y(n1358) );
AO22XLTS U4015 ( .A0(n3225), .A1(DMP_SFG[53]), .B0(n3431), .B1(
DMP_exp_NRM_EW[1]), .Y(n1357) );
AO22XLTS U4016 ( .A0(n3202), .A1(DMP_EXP_EWSW[54]), .B0(n3220), .B1(
DMP_SHT1_EWSW[54]), .Y(n1355) );
AO22XLTS U4017 ( .A0(n3199), .A1(DMP_SHT1_EWSW[54]), .B0(n3503), .B1(
DMP_SHT2_EWSW[54]), .Y(n1354) );
AO22XLTS U4018 ( .A0(n2883), .A1(DMP_SHT2_EWSW[54]), .B0(n3224), .B1(
DMP_SFG[54]), .Y(n1353) );
AO22XLTS U4019 ( .A0(n3225), .A1(DMP_SFG[54]), .B0(n3431), .B1(
DMP_exp_NRM_EW[2]), .Y(n1352) );
AO22XLTS U4020 ( .A0(n3202), .A1(DMP_EXP_EWSW[55]), .B0(n3220), .B1(
DMP_SHT1_EWSW[55]), .Y(n1350) );
AO22XLTS U4021 ( .A0(n3199), .A1(DMP_SHT1_EWSW[55]), .B0(n3503), .B1(
DMP_SHT2_EWSW[55]), .Y(n1349) );
AO22XLTS U4022 ( .A0(n3246), .A1(DMP_SHT2_EWSW[55]), .B0(n3252), .B1(
DMP_SFG[55]), .Y(n1348) );
AO22XLTS U4023 ( .A0(n3225), .A1(DMP_SFG[55]), .B0(n3431), .B1(
DMP_exp_NRM_EW[3]), .Y(n1347) );
AO22XLTS U4024 ( .A0(n3202), .A1(DMP_EXP_EWSW[56]), .B0(n3220), .B1(
DMP_SHT1_EWSW[56]), .Y(n1345) );
AO22XLTS U4025 ( .A0(n3199), .A1(DMP_SHT1_EWSW[56]), .B0(n3503), .B1(
DMP_SHT2_EWSW[56]), .Y(n1344) );
AO22XLTS U4026 ( .A0(n3217), .A1(DMP_SHT2_EWSW[56]), .B0(n3224), .B1(
DMP_SFG[56]), .Y(n1343) );
AO22XLTS U4027 ( .A0(n3225), .A1(DMP_SFG[56]), .B0(n3218), .B1(
DMP_exp_NRM_EW[4]), .Y(n1342) );
AO22XLTS U4028 ( .A0(n3200), .A1(n1864), .B0(n3220), .B1(DMP_SHT1_EWSW[57]),
.Y(n1340) );
AO22XLTS U4029 ( .A0(n3199), .A1(DMP_SHT1_EWSW[57]), .B0(n3503), .B1(
DMP_SHT2_EWSW[57]), .Y(n1339) );
AO22XLTS U4030 ( .A0(n3198), .A1(DMP_SHT2_EWSW[57]), .B0(n3252), .B1(
DMP_SFG[57]), .Y(n1338) );
AO22XLTS U4031 ( .A0(n3225), .A1(DMP_SFG[57]), .B0(n3218), .B1(
DMP_exp_NRM_EW[5]), .Y(n1337) );
AO22XLTS U4032 ( .A0(n3204), .A1(DMP_EXP_EWSW[58]), .B0(n3201), .B1(
DMP_SHT1_EWSW[58]), .Y(n1335) );
AO22XLTS U4033 ( .A0(n3223), .A1(DMP_SHT1_EWSW[58]), .B0(n3503), .B1(
DMP_SHT2_EWSW[58]), .Y(n1334) );
AO22XLTS U4034 ( .A0(n3198), .A1(DMP_SHT2_EWSW[58]), .B0(n3224), .B1(
DMP_SFG[58]), .Y(n1333) );
AO22XLTS U4035 ( .A0(n3225), .A1(DMP_SFG[58]), .B0(n3431), .B1(
DMP_exp_NRM_EW[6]), .Y(n1332) );
AO22XLTS U4036 ( .A0(n3200), .A1(DMP_EXP_EWSW[59]), .B0(n3201), .B1(
DMP_SHT1_EWSW[59]), .Y(n1330) );
AO22XLTS U4037 ( .A0(n3223), .A1(DMP_SHT1_EWSW[59]), .B0(n3503), .B1(
DMP_SHT2_EWSW[59]), .Y(n1329) );
AO22XLTS U4038 ( .A0(n2858), .A1(DMP_SHT2_EWSW[59]), .B0(n3224), .B1(
DMP_SFG[59]), .Y(n1328) );
AO22XLTS U4039 ( .A0(n3225), .A1(DMP_SFG[59]), .B0(n3431), .B1(
DMP_exp_NRM_EW[7]), .Y(n1327) );
AO22XLTS U4040 ( .A0(n3204), .A1(DMP_EXP_EWSW[60]), .B0(n3201), .B1(
DMP_SHT1_EWSW[60]), .Y(n1325) );
AO22XLTS U4041 ( .A0(n3223), .A1(DMP_SHT1_EWSW[60]), .B0(n3503), .B1(
DMP_SHT2_EWSW[60]), .Y(n1324) );
AO22XLTS U4042 ( .A0(n3246), .A1(DMP_SHT2_EWSW[60]), .B0(n3224), .B1(
DMP_SFG[60]), .Y(n1323) );
AO22XLTS U4043 ( .A0(n3225), .A1(DMP_SFG[60]), .B0(n3431), .B1(
DMP_exp_NRM_EW[8]), .Y(n1322) );
AO22XLTS U4044 ( .A0(n3200), .A1(DMP_EXP_EWSW[61]), .B0(n3201), .B1(
DMP_SHT1_EWSW[61]), .Y(n1320) );
AO22XLTS U4045 ( .A0(n3223), .A1(DMP_SHT1_EWSW[61]), .B0(n3503), .B1(
DMP_SHT2_EWSW[61]), .Y(n1319) );
AO22XLTS U4046 ( .A0(n3258), .A1(DMP_SHT2_EWSW[61]), .B0(n3224), .B1(
DMP_SFG[61]), .Y(n1318) );
AO22XLTS U4047 ( .A0(n3225), .A1(DMP_SFG[61]), .B0(n3431), .B1(
DMP_exp_NRM_EW[9]), .Y(n1317) );
AO22XLTS U4048 ( .A0(n3204), .A1(DMP_EXP_EWSW[62]), .B0(n3201), .B1(
DMP_SHT1_EWSW[62]), .Y(n1315) );
AO22XLTS U4049 ( .A0(n3223), .A1(DMP_SHT1_EWSW[62]), .B0(n3503), .B1(
DMP_SHT2_EWSW[62]), .Y(n1314) );
AO22XLTS U4050 ( .A0(n3198), .A1(DMP_SHT2_EWSW[62]), .B0(n3224), .B1(
DMP_SFG[62]), .Y(n1313) );
AO22XLTS U4051 ( .A0(n3225), .A1(DMP_SFG[62]), .B0(n3431), .B1(
DMP_exp_NRM_EW[10]), .Y(n1312) );
AO22XLTS U4052 ( .A0(n3202), .A1(DmP_EXP_EWSW[6]), .B0(n3203), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1297) );
AO22XLTS U4053 ( .A0(n3202), .A1(DmP_EXP_EWSW[7]), .B0(n3221), .B1(
DmP_mant_SHT1_SW[7]), .Y(n1295) );
AO22XLTS U4054 ( .A0(n3202), .A1(DmP_EXP_EWSW[8]), .B0(n3221), .B1(
DmP_mant_SHT1_SW[8]), .Y(n1293) );
AO22XLTS U4055 ( .A0(n3202), .A1(DmP_EXP_EWSW[10]), .B0(n3221), .B1(
DmP_mant_SHT1_SW[10]), .Y(n1289) );
AO22XLTS U4056 ( .A0(n3202), .A1(DmP_EXP_EWSW[12]), .B0(n3203), .B1(
DmP_mant_SHT1_SW[12]), .Y(n1285) );
AO22XLTS U4057 ( .A0(n3202), .A1(DmP_EXP_EWSW[13]), .B0(n3203), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1283) );
AO22XLTS U4058 ( .A0(n3202), .A1(DmP_EXP_EWSW[14]), .B0(n3221), .B1(
DmP_mant_SHT1_SW[14]), .Y(n1281) );
AO22XLTS U4059 ( .A0(n3204), .A1(DmP_EXP_EWSW[16]), .B0(n3203), .B1(n1856),
.Y(n1277) );
OAI222X1TS U4060 ( .A0(n2560), .A1(n3429), .B0(n3322), .B1(n3211), .C0(n3283), .C1(n3210), .Y(n1203) );
OAI2BB1X1TS U4061 ( .A0N(underflow_flag), .A1N(n3426), .B0(n3214), .Y(n1200)
);
OA21XLTS U4062 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n3215),
.Y(n1199) );
AO22XLTS U4063 ( .A0(Shift_reg_FLAGS_7_5), .A1(ZERO_FLAG_EXP), .B0(n3430),
.B1(ZERO_FLAG_SHT1), .Y(n1198) );
AO22XLTS U4064 ( .A0(n3223), .A1(ZERO_FLAG_SHT1), .B0(n3503), .B1(
ZERO_FLAG_SHT2), .Y(n1197) );
AO22XLTS U4065 ( .A0(n3198), .A1(ZERO_FLAG_SHT2), .B0(n3224), .B1(
ZERO_FLAG_SFG), .Y(n1196) );
AO22XLTS U4066 ( .A0(n3225), .A1(ZERO_FLAG_SFG), .B0(n3218), .B1(
ZERO_FLAG_NRM), .Y(n1195) );
AO22XLTS U4067 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n2318), .B1(zero_flag), .Y(n1193) );
AO22XLTS U4068 ( .A0(Shift_reg_FLAGS_7_5), .A1(OP_FLAG_EXP), .B0(n3220),
.B1(OP_FLAG_SHT1), .Y(n1192) );
AO22XLTS U4069 ( .A0(Shift_reg_FLAGS_7_5), .A1(SIGN_FLAG_EXP), .B0(n3220),
.B1(SIGN_FLAG_SHT1), .Y(n1189) );
AO22XLTS U4070 ( .A0(n3223), .A1(SIGN_FLAG_SHT1), .B0(n3196), .B1(
SIGN_FLAG_SHT2), .Y(n1188) );
AO22XLTS U4071 ( .A0(n3258), .A1(SIGN_FLAG_SHT2), .B0(n3224), .B1(
SIGN_FLAG_SFG), .Y(n1187) );
AO22XLTS U4072 ( .A0(n3225), .A1(SIGN_FLAG_SFG), .B0(n3431), .B1(
SIGN_FLAG_NRM), .Y(n1186) );
OAI211XLTS U4073 ( .A0(n2126), .A1(SIGN_FLAG_SHT1SHT2), .B0(
Shift_reg_FLAGS_7[0]), .C0(n3226), .Y(n3227) );
OAI2BB1X1TS U4074 ( .A0N(final_result_ieee[63]), .A1N(n3426), .B0(n3227),
.Y(n1184) );
OAI22X1TS U4075 ( .A0(n3241), .A1(n3228), .B0(n1826), .B1(n3232), .Y(n3275)
);
OAI22X1TS U4076 ( .A0(n3231), .A1(n3238), .B0(left_right_SHT2), .B1(n3229),
.Y(n3273) );
OAI22X1TS U4077 ( .A0(left_right_SHT2), .A1(n3233), .B0(n3395), .B1(n3232),
.Y(n3271) );
OAI22X1TS U4078 ( .A0(n3241), .A1(n3235), .B0(n3234), .B1(n3238), .Y(n3269)
);
OAI22X1TS U4079 ( .A0(n3241), .A1(n3237), .B0(n3236), .B1(n3238), .Y(n3267)
);
OAI22X1TS U4080 ( .A0(n3241), .A1(n3240), .B0(n3239), .B1(n3238), .Y(n3265)
);
AO22XLTS U4081 ( .A0(n3259), .A1(n1857), .B0(n3258), .B1(n3265), .Y(n1121)
);
AO22XLTS U4082 ( .A0(n3252), .A1(DmP_mant_SFG_SWR[8]), .B0(n3217), .B1(n3242), .Y(n1119) );
AOI22X1TS U4083 ( .A0(n2858), .A1(n3244), .B0(n3432), .B1(n3259), .Y(n1113)
);
AOI22X1TS U4084 ( .A0(n2858), .A1(n3245), .B0(n3433), .B1(n3259), .Y(n1111)
);
AO22XLTS U4085 ( .A0(n3252), .A1(DmP_mant_SFG_SWR[9]), .B0(n2858), .B1(n3251), .Y(n1105) );
AO22XLTS U4086 ( .A0(n3259), .A1(DmP_mant_SFG_SWR[10]), .B0(n3246), .B1(
n3257), .Y(n1097) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk20.tcl_LOA_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKBUF_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__CLKBUF_PP_BLACKBOX_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkbuf (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKBUF_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_SYMBOL_V
`define SKY130_FD_SC_LP__OR3B_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: JBus Interface
*/
`include "sys.h"
`include "iop.h"
`include "jbi.h"
module jbi (/*AUTOARG*/
// Outputs
jbi_ddr3_scanout18, jbi_clk_tr, jbi_jbusr_so, jbi_jbusr_se,
jbi_sctag0_req, jbi_scbuf0_ecc, jbi_sctag0_req_vld, jbi_sctag1_req,
jbi_scbuf1_ecc, jbi_sctag1_req_vld, jbi_sctag2_req, jbi_scbuf2_ecc,
jbi_sctag2_req_vld, jbi_sctag3_req, jbi_scbuf3_ecc,
jbi_sctag3_req_vld, jbi_iob_pio_vld, jbi_iob_pio_data,
jbi_iob_pio_stall, jbi_iob_mondo_vld, jbi_iob_mondo_data,
jbi_io_ssi_mosi, jbi_io_ssi_sck, jbi_iob_spi_vld, jbi_iob_spi_data,
jbi_iob_spi_stall, jbi_io_j_req0_out_l, jbi_io_j_req0_out_en,
jbi_io_j_adtype, jbi_io_j_adtype_en, jbi_io_j_ad, jbi_io_j_ad_en,
jbi_io_j_pack0, jbi_io_j_pack0_en, jbi_io_j_pack1, jbi_io_j_pack1_en,
jbi_io_j_adp, jbi_io_j_adp_en, jbi_io_config_dtl,
// Inputs
cmp_gclk, cmp_arst_l, cmp_grst_l, jbus_gclk, jbus_arst_l,
jbus_grst_l, ctu_jbi_ssiclk, ctu_jbi_tx_en, ctu_jbi_rx_en,
ctu_jbi_fst_rst_l, clk_jbi_jbus_cken, clk_jbi_cmp_cken,
global_shift_enable, ctu_tst_scanmode, ctu_tst_pre_grst_l,
ctu_tst_scan_disable, ctu_tst_macrotest, ctu_tst_short_chain,
ddr3_jbi_scanin18, jbusr_jbi_si, sctag0_jbi_iq_dequeue,
sctag0_jbi_wib_dequeue, scbuf0_jbi_data, scbuf0_jbi_ctag_vld,
scbuf0_jbi_ue_err, sctag0_jbi_por_req_buf, sctag1_jbi_iq_dequeue,
sctag1_jbi_wib_dequeue, scbuf1_jbi_data, scbuf1_jbi_ctag_vld,
scbuf1_jbi_ue_err, sctag1_jbi_por_req_buf, sctag2_jbi_iq_dequeue,
sctag2_jbi_wib_dequeue, scbuf2_jbi_data, scbuf2_jbi_ctag_vld,
scbuf2_jbi_ue_err, sctag2_jbi_por_req_buf, sctag3_jbi_iq_dequeue,
sctag3_jbi_wib_dequeue, scbuf3_jbi_data, scbuf3_jbi_ctag_vld,
scbuf3_jbi_ue_err, sctag3_jbi_por_req_buf, iob_jbi_pio_stall,
iob_jbi_pio_vld, iob_jbi_pio_data, iob_jbi_mondo_ack,
iob_jbi_mondo_nack, io_jbi_ssi_miso, io_jbi_ext_int_l,
iob_jbi_spi_vld, iob_jbi_spi_data, iob_jbi_spi_stall,
io_jbi_j_req4_in_l, io_jbi_j_req5_in_l, io_jbi_j_adtype, io_jbi_j_ad,
io_jbi_j_pack4, io_jbi_j_pack5, io_jbi_j_adp, io_jbi_j_par,
iob_jbi_dbg_hi_data, iob_jbi_dbg_hi_vld, iob_jbi_dbg_lo_data,
iob_jbi_dbg_lo_vld
);
// Clocks and reset.
input cmp_gclk; // CMP clock.
input cmp_arst_l; // CMP clock domain async reset.
input cmp_grst_l; // CMP clock domain reset.
input jbus_gclk; // JBus clock.
input jbus_arst_l; // JBus clock domain async reset.
input jbus_grst_l; // JBus clock domain reset.
input ctu_jbi_ssiclk; // jbus clk divided by 4
input ctu_jbi_tx_en; // CMP to JBI clock domain crossing synchronization pulse.
input ctu_jbi_rx_en; // JBI to CMP clock domain crossing synchronization pulse.
input ctu_jbi_fst_rst_l; // Fast reset for capturing port present bits (J_RST_L + 1).
// Scan and DFT.
input clk_jbi_jbus_cken; // Jbi clock enable.
input clk_jbi_cmp_cken; // Cmp clock enable.
input global_shift_enable; // Scan shift enable signal.
input ctu_tst_scanmode; // Scan mode.
input ctu_tst_pre_grst_l;
input ctu_tst_scan_disable;
input ctu_tst_macrotest;
input ctu_tst_short_chain;
input ddr3_jbi_scanin18;
output jbi_ddr3_scanout18;
output jbi_clk_tr; // Debug_trigger.
output jbi_jbusr_so;
output jbi_jbusr_se;
input jbusr_jbi_si;
// SCBuf0/SCTag0 Interface.
//
// Inbound Requests and Return Data.
output [31:0] jbi_sctag0_req;
output [6:0] jbi_scbuf0_ecc;
output jbi_sctag0_req_vld; // Next cycle will be Header of a new request packet.
input sctag0_jbi_iq_dequeue; // SCTag is unloading a request from its 2 req queue.
input sctag0_jbi_wib_dequeue; // Write invalidate buffer (size=4) is being unloaded.
//
// Outbound Requests and Return Data.
input [31:0] scbuf0_jbi_data;
input scbuf0_jbi_ctag_vld; // Header cycle of a new response packet.
input scbuf0_jbi_ue_err; // Current data cycle has a uncorrectable error.
input sctag0_jbi_por_req_buf; // Request for DOK_FATAL.
// SCBuf1/SCTag1 Interface.
//
// Inbound Requests and Return Data.
output [31:0] jbi_sctag1_req;
output [6:0] jbi_scbuf1_ecc;
output jbi_sctag1_req_vld; // Next cycle will be Header of a new request packet.
input sctag1_jbi_iq_dequeue; // SCTag is unloading a request from its 2 req queue.
input sctag1_jbi_wib_dequeue; // Write invalidate buffer (size=4) is being unloaded.
//
// Outbound Requests and Return Data.
input [31:0] scbuf1_jbi_data;
input scbuf1_jbi_ctag_vld; // Header cycle of a new response packet.
input scbuf1_jbi_ue_err; // Current data cycle has a uncorrectable error.
input sctag1_jbi_por_req_buf; // Request for DOK_FATAL.
// SCBuf2/SCTag2 Interface.
//
// Inbound Requests and Return Data.
output [31:0] jbi_sctag2_req;
output [6:0] jbi_scbuf2_ecc;
output jbi_sctag2_req_vld; // Next cycle will be Header of a new request packet.
input sctag2_jbi_iq_dequeue; // SCTag is unloading a request from its 2 req queue.
input sctag2_jbi_wib_dequeue; // Write invalidate buffer (size=4) is being unloaded.
//
// Outbound Requests and Return Data.
input [31:0] scbuf2_jbi_data;
input scbuf2_jbi_ctag_vld; // Header cycle of a new response packet.
input scbuf2_jbi_ue_err; // Current data cycle has a uncorrectable error.
input sctag2_jbi_por_req_buf; // Request for DOK_FATAL.
// SCBuf3/SCTag3 Interface.
//
// Inbound Requests and Return Data.
output [31:0] jbi_sctag3_req;
output [6:0] jbi_scbuf3_ecc;
output jbi_sctag3_req_vld; // Next cycle will be Header of a new request packet.
input sctag3_jbi_iq_dequeue; // SCTag is unloading a request from its 2 req queue.
input sctag3_jbi_wib_dequeue; // Write invalidate buffer (size=4) is being unloaded.
//
// Outbound Requests and Return Data.
input [31:0] scbuf3_jbi_data;
input scbuf3_jbi_ctag_vld; // Header cycle of a new response packet.
input scbuf3_jbi_ue_err; // Current data cycle has a uncorrectable error.
input sctag3_jbi_por_req_buf; // Request for DOK_FATAL.
// IOB Interface.
//
// Inbound PIO Interrupt Requests, PIO Responses.
output jbi_iob_pio_vld;
output [`JBI_IOB_WIDTH-1:0] jbi_iob_pio_data;
input iob_jbi_pio_stall;
//
// Outbound PIO Requests.
input iob_jbi_pio_vld;
input [`IOB_JBI_WIDTH-1:0] iob_jbi_pio_data;
output jbi_iob_pio_stall;
//
// Inbound Mondo Interrupt Requests.
output jbi_iob_mondo_vld;
output [`JBI_IOB_MONDO_BUS_WIDTH-1:0] jbi_iob_mondo_data;
//
// Outbound Mondo Interrupt responses.
input iob_jbi_mondo_ack;
input iob_jbi_mondo_nack;
// SPI Interface.
//
// IO Pads.
output jbi_io_ssi_mosi; // Master out slave in to pad.
input io_jbi_ssi_miso; // Master in slave out from pad.
output jbi_io_ssi_sck; // Serial clock to pad.
input io_jbi_ext_int_l;
//
// IOB
input iob_jbi_spi_vld; // Valid packet from IOB.
input [`IOB_SPI_WIDTH-1:0] iob_jbi_spi_data; // Packet data from IOB.
input iob_jbi_spi_stall; // Flow control to stop data.
output jbi_iob_spi_vld; // Valid packet from UCB.
output [`SPI_IOB_WIDTH-1:0] jbi_iob_spi_data; // Packet data from UCB.
output jbi_iob_spi_stall; // Flow control to stop data.
// JBus Interface.
//
// JBUS Arbitration.
output jbi_io_j_req0_out_l;
output jbi_io_j_req0_out_en;
input io_jbi_j_req4_in_l;
input io_jbi_j_req5_in_l;
//
// JBUS Address/Data packet.
input [7:0] io_jbi_j_adtype;
output [7:0] jbi_io_j_adtype;
output jbi_io_j_adtype_en;
input [127:0] io_jbi_j_ad;
output [127:0] jbi_io_j_ad;
output [3:0] jbi_io_j_ad_en;
//
// JBUS Cache Snooping.
output [2:0] jbi_io_j_pack0;
output jbi_io_j_pack0_en;
output [2:0] jbi_io_j_pack1;
output jbi_io_j_pack1_en;
input [2:0] io_jbi_j_pack4;
input [2:0] io_jbi_j_pack5;
//
// JBUS Error Detection.
input [3:0] io_jbi_j_adp;
output [3:0] jbi_io_j_adp;
output jbi_io_j_adp_en;
input io_jbi_j_par;
//
// DTL Control.
output [1:0] jbi_io_config_dtl;
// ENet Interface.
//
// Debug.
input [47:0] iob_jbi_dbg_hi_data;
input iob_jbi_dbg_hi_vld;
input [47:0] iob_jbi_dbg_lo_data;
input iob_jbi_dbg_lo_vld;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire MT_so_0; // From u_test_stub of test_stub_scan.v
wire cmp_rclk; // From u_cmp_header of bw_clk_cl_jbi_cmp.v
wire cmp_rst_l; // From u_cmp_header of bw_clk_cl_jbi_cmp.v
wire [4:0] csr_16x65array_margin; // From u_csr of jbi_csr.v
wire [4:0] csr_16x81array_margin; // From u_csr of jbi_csr.v
wire [`JBI_CSR_WIDTH-1:0]csr_csr_read_data; // From u_csr of jbi_csr.v
wire csr_dok_on; // From u_csr of jbi_csr.v
wire csr_int_req; // From u_csr of jbi_csr.v
wire [31:0] csr_jbi_arb_timeout_timeval;// From u_csr of jbi_csr.v
wire [3:0] csr_jbi_config2_iq_high;// From u_csr of jbi_csr.v
wire [3:0] csr_jbi_config2_iq_low; // From u_csr of jbi_csr.v
wire [3:0] csr_jbi_config2_max_pio;// From u_csr of jbi_csr.v
wire [1:0] csr_jbi_config2_max_rd; // From u_csr of jbi_csr.v
wire [3:0] csr_jbi_config2_max_wr; // From u_csr of jbi_csr.v
wire [1:0] csr_jbi_config2_max_wris;// From u_csr of jbi_csr.v
wire csr_jbi_config2_ord_int;// From u_csr of jbi_csr.v
wire csr_jbi_config2_ord_pio;// From u_csr of jbi_csr.v
wire csr_jbi_config2_ord_rd; // From u_csr of jbi_csr.v
wire csr_jbi_config2_ord_wr; // From u_csr of jbi_csr.v
wire [1:0] csr_jbi_config_arb_mode;// From u_csr of jbi_csr.v
wire [6:0] csr_jbi_config_port_pres;// From u_csr of jbi_csr.v
wire csr_jbi_debug_arb_aggr_arb;// From u_csr of jbi_csr.v
wire csr_jbi_debug_arb_alternate;// From u_csr of jbi_csr.v
wire csr_jbi_debug_arb_alternate_set_l;// From u_csr of jbi_csr.v
wire csr_jbi_debug_arb_data_arb;// From u_csr of jbi_csr.v
wire [4:0] csr_jbi_debug_arb_hi_water;// From u_csr of jbi_csr.v
wire [4:0] csr_jbi_debug_arb_lo_water;// From u_csr of jbi_csr.v
wire [9:0] csr_jbi_debug_arb_max_wait;// From u_csr of jbi_csr.v
wire [6:0] csr_jbi_debug_arb_tstamp_wrap;// From u_csr of jbi_csr.v
wire csr_jbi_debug_info_enb; // From u_csr of jbi_csr.v
wire [23:0] csr_jbi_err_inject_count;// From u_csr of jbi_csr.v
wire csr_jbi_err_inject_errtype;// From u_csr of jbi_csr.v
wire csr_jbi_err_inject_input;// From u_csr of jbi_csr.v
wire csr_jbi_err_inject_output;// From u_csr of jbi_csr.v
wire [3:0] csr_jbi_err_inject_xormask;// From u_csr of jbi_csr.v
wire csr_jbi_error_config_erren;// From u_csr of jbi_csr.v
wire csr_jbi_error_config_fe_enb;// From u_csr of jbi_csr.v
wire csr_jbi_error_config_sigen;// From u_csr of jbi_csr.v
wire csr_jbi_intr_timeout_rst_l;// From u_csr of jbi_csr.v
wire [31:0] csr_jbi_intr_timeout_timeval;// From u_csr of jbi_csr.v
wire [31:0] csr_jbi_l2_timeout_timeval;// From u_csr of jbi_csr.v
wire csr_jbi_log_enb_apar; // From u_csr of jbi_csr.v
wire csr_jbi_log_enb_dpar_o; // From u_csr of jbi_csr.v
wire csr_jbi_log_enb_dpar_rd;// From u_csr of jbi_csr.v
wire csr_jbi_log_enb_dpar_wr;// From u_csr of jbi_csr.v
wire csr_jbi_log_enb_err_cycle;// From u_csr of jbi_csr.v
wire csr_jbi_log_enb_nonex_rd;// From u_csr of jbi_csr.v
wire csr_jbi_log_enb_read_to;// From u_csr of jbi_csr.v
wire csr_jbi_log_enb_rep_ue; // From u_csr of jbi_csr.v
wire csr_jbi_log_enb_unexp_dr;// From u_csr of jbi_csr.v
wire [37:30] csr_jbi_memsize_size; // From u_csr of jbi_csr.v
wire [31:0] csr_jbi_trans_timeout_timeval;// From u_csr of jbi_csr.v
wire [127:0] dbg_data; // From u_dbg of jbi_dbg.v
wire dbg_req_arbitrate; // From u_dbg of jbi_dbg.v
wire dbg_req_priority; // From u_dbg of jbi_dbg.v
wire dbg_req_transparent; // From u_dbg of jbi_dbg.v
wire [6:0] jbi_log_arb_aok; // From u_mout of jbi_mout.v
wire [6:0] jbi_log_arb_dok; // From u_mout of jbi_mout.v
wire [6:0] jbi_log_arb_jreq; // From u_mout of jbi_mout.v
wire [2:0] jbi_log_arb_myreq; // From u_mout of jbi_mout.v
wire [2:0] jbi_log_arb_reqtype; // From u_mout of jbi_mout.v
wire jbus_rclk; // From u_jbus_header of bw_clk_cl_jbi_jbus.v
wire jbus_rst_l; // From u_jbus_header of bw_clk_cl_jbi_jbus.v
wire min_aok_off; // From u_min of jbi_min.v
wire min_aok_on; // From u_min of jbi_min.v
wire min_csr_err_adtype; // From u_min of jbi_min.v
wire min_csr_err_apar; // From u_min of jbi_min.v
wire min_csr_err_dpar_o; // From u_min of jbi_min.v
wire min_csr_err_dpar_rd; // From u_min of jbi_min.v
wire min_csr_err_dpar_wr; // From u_min of jbi_min.v
wire min_csr_err_err_cycle; // From u_min of jbi_min.v
wire min_csr_err_illegal; // From u_min of jbi_min.v
wire min_csr_err_l2_to0; // From u_min of jbi_min.v
wire min_csr_err_l2_to1; // From u_min of jbi_min.v
wire min_csr_err_l2_to2; // From u_min of jbi_min.v
wire min_csr_err_l2_to3; // From u_min of jbi_min.v
wire min_csr_err_nonex_rd; // From u_min of jbi_min.v
wire min_csr_err_nonex_wr; // From u_min of jbi_min.v
wire min_csr_err_rep_ue; // From u_min of jbi_min.v
wire min_csr_err_unexp_dr; // From u_min of jbi_min.v
wire min_csr_err_unmap_wr; // From u_min of jbi_min.v
wire min_csr_err_unsupp; // From u_min of jbi_min.v
wire min_csr_inject_input_done;// From u_min of jbi_min.v
wire [42:0] min_csr_log_addr_addr; // From u_min of jbi_min.v
wire [7:0] min_csr_log_addr_adtype;// From u_min of jbi_min.v
wire [2:0] min_csr_log_addr_owner; // From u_min of jbi_min.v
wire [4:0] min_csr_log_addr_ttype; // From u_min of jbi_min.v
wire [7:0] min_csr_log_ctl_adtype0;// From u_min of jbi_min.v
wire [7:0] min_csr_log_ctl_adtype1;// From u_min of jbi_min.v
wire [7:0] min_csr_log_ctl_adtype2;// From u_min of jbi_min.v
wire [7:0] min_csr_log_ctl_adtype3;// From u_min of jbi_min.v
wire [7:0] min_csr_log_ctl_adtype4;// From u_min of jbi_min.v
wire [7:0] min_csr_log_ctl_adtype5;// From u_min of jbi_min.v
wire [7:0] min_csr_log_ctl_adtype6;// From u_min of jbi_min.v
wire [2:0] min_csr_log_ctl_owner; // From u_min of jbi_min.v
wire [3:0] min_csr_log_ctl_parity; // From u_min of jbi_min.v
wire [63:0] min_csr_log_data0; // From u_min of jbi_min.v
wire [63:0] min_csr_log_data1; // From u_min of jbi_min.v
wire [3:0] min_csr_perf_blk_q0; // From u_min of jbi_min.v
wire [3:0] min_csr_perf_blk_q1; // From u_min of jbi_min.v
wire [3:0] min_csr_perf_blk_q2; // From u_min of jbi_min.v
wire [3:0] min_csr_perf_blk_q3; // From u_min of jbi_min.v
wire min_csr_perf_dma_rd_in; // From u_min of jbi_min.v
wire [4:0] min_csr_perf_dma_rd_latency;// From u_min of jbi_min.v
wire min_csr_perf_dma_wr; // From u_min of jbi_min.v
wire min_csr_perf_dma_wr8; // From u_min of jbi_min.v
wire min_csr_write_log_addr; // From u_min of jbi_min.v
wire min_free; // From u_min of jbi_min.v
wire [`JBI_JID_WIDTH-1:0]min_free_jid; // From u_min of jbi_min.v
wire [127:0] min_j_ad_ff; // From u_min of jbi_min.v
wire min_mondo_data_err; // From u_min of jbi_min.v
wire min_mondo_data_push; // From u_min of jbi_min.v
wire min_mondo_hdr_push; // From u_min of jbi_min.v
wire min_mout_inject_err; // From u_min of jbi_min.v
wire [`JBI_WRI_TAG_WIDTH-1:0]min_oldest_wri_tag;// From u_min of jbi_min.v
wire min_pio_data_err; // From u_min of jbi_min.v
wire min_pio_rtrn_push; // From u_min of jbi_min.v
wire [`JBI_WRI_TAG_WIDTH-1:0]min_pre_wri_tag; // From u_min of jbi_min.v
wire min_snp_launch; // From u_min of jbi_min.v
wire [`JBI_JID_WIDTH-1:0]min_trans_jid; // From u_min of jbi_min.v
wire mout_csr_err_arb_to; // From u_mout of jbi_mout.v
wire mout_csr_err_cpar; // From u_mout of jbi_mout.v
wire [5:4] mout_csr_err_fatal; // From u_mout of jbi_mout.v
wire mout_csr_err_read_to; // From u_mout of jbi_mout.v
wire mout_csr_inject_output_done;// From u_mout of jbi_mout.v
wire [2:0] mout_csr_jbi_log_par_jpack0;// From u_mout of jbi_mout.v
wire [2:0] mout_csr_jbi_log_par_jpack1;// From u_mout of jbi_mout.v
wire [2:0] mout_csr_jbi_log_par_jpack4;// From u_mout of jbi_mout.v
wire [2:0] mout_csr_jbi_log_par_jpack5;// From u_mout of jbi_mout.v
wire mout_csr_jbi_log_par_jpar;// From u_mout of jbi_mout.v
wire [6:0] mout_csr_jbi_log_par_jreq;// From u_mout of jbi_mout.v
wire mout_dbg_pop; // From u_mout of jbi_mout.v
wire mout_dsbl_sampling; // From u_mout of jbi_mout.v
wire mout_min_inject_err_done;// From u_mout of jbi_mout.v
wire [5:0] mout_min_jbus_owner; // From u_mout of jbi_mout.v
wire mout_mondo_pop; // From u_mout of jbi_mout.v
wire mout_nack; // From u_mout of jbi_mout.v
wire [1:0] mout_nack_buf_id; // From u_mout of jbi_mout.v
wire [5:0] mout_nack_thr_id; // From u_mout of jbi_mout.v
wire mout_perf_aok_off; // From u_mout of jbi_mout.v
wire mout_perf_dok_off; // From u_mout of jbi_mout.v
wire mout_pio_pop; // From u_mout of jbi_mout.v
wire mout_pio_req_adv; // From u_mout of jbi_mout.v
wire mout_port_4_present; // From u_mout of jbi_mout.v
wire mout_port_5_present; // From u_mout of jbi_mout.v
wire mout_scb0_jbus_rd_ack; // From u_mout of jbi_mout.v
wire mout_scb0_jbus_wr_ack; // From u_mout of jbi_mout.v
wire mout_scb1_jbus_rd_ack; // From u_mout of jbi_mout.v
wire mout_scb1_jbus_wr_ack; // From u_mout of jbi_mout.v
wire mout_scb2_jbus_rd_ack; // From u_mout of jbi_mout.v
wire mout_scb2_jbus_wr_ack; // From u_mout of jbi_mout.v
wire mout_scb3_jbus_rd_ack; // From u_mout of jbi_mout.v
wire mout_scb3_jbus_wr_ack; // From u_mout of jbi_mout.v
wire mout_trans_valid; // From u_mout of jbi_mout.v
wire [`JBI_YID_WIDTH-1:0]mout_trans_yid; // From u_mout of jbi_mout.v
wire [31:0] ncio_csr_err_intr_to; // From u_ncio of jbi_ncio.v
wire [4:0] ncio_csr_perf_pio_rd_latency;// From u_ncio of jbi_ncio.v
wire ncio_csr_perf_pio_rd_out;// From u_ncio of jbi_ncio.v
wire ncio_csr_perf_pio_wr; // From u_ncio of jbi_ncio.v
wire [`JBI_CSR_ADDR_WIDTH-1:0]ncio_csr_read_addr;// From u_ncio of jbi_ncio.v
wire ncio_csr_write; // From u_ncio of jbi_ncio.v
wire [`JBI_CSR_ADDR_WIDTH-1:0]ncio_csr_write_addr;// From u_ncio of jbi_ncio.v
wire [`JBI_CSR_WIDTH-1:0]ncio_csr_write_data; // From u_ncio of jbi_ncio.v
wire [`JBI_MAKQ_ADDR_WIDTH:0]ncio_makq_level; // From u_ncio of jbi_ncio.v
wire ncio_mondo_ack; // From u_ncio of jbi_ncio.v
wire [`JBI_AD_INT_AGTID_WIDTH-1:0]ncio_mondo_agnt_id;// From u_ncio of jbi_ncio.v
wire [`JBI_AD_INT_CPUID_WIDTH-1:0]ncio_mondo_cpu_id;// From u_ncio of jbi_ncio.v
wire ncio_mondo_req; // From u_ncio of jbi_ncio.v
wire ncio_mout_nack_pop; // From u_ncio of jbi_ncio.v
wire [63:0] ncio_pio_ad; // From u_ncio of jbi_ncio.v
wire [15:0] ncio_pio_be; // From u_ncio of jbi_ncio.v
wire ncio_pio_req; // From u_ncio of jbi_ncio.v
wire [1:0] ncio_pio_req_dest; // From u_ncio of jbi_ncio.v
wire ncio_pio_req_rw; // From u_ncio of jbi_ncio.v
wire ncio_pio_ue; // From u_ncio of jbi_ncio.v
wire [`JBI_PRQQ_ADDR_WIDTH:0]ncio_prqq_level; // From u_ncio of jbi_ncio.v
wire [`JBI_YID_WIDTH-1:0]ncio_yid; // From u_ncio of jbi_ncio.v
wire rst_tri_en; // From u_test_stub of test_stub_scan.v
wire rx_en_local; // From u_sync_header of cluster_header_sync.v
wire se; // From u_test_stub of test_stub_scan.v
wire sehold; // From u_test_stub of test_stub_scan.v
wire testmux_sel; // From u_test_stub of test_stub_scan.v
wire tx_en_local; // From u_sync_header of cluster_header_sync.v
// End of automatics
wire MT_long_chain_so_0;
wire MT_short_chain_so_0;
//*******************************************************************************
// CLUSTER HEADERS
//*******************************************************************************
/* bw_clk_cl_jbi_jbus AUTO_TEMPLATE (
.dbginit_l (),
.cluster_grst_l (jbus_rst_l),
.rclk (jbus_rclk),
.so (),
.gclk (jbus_gclk),
.cluster_cken (clk_jbi_jbus_cken),
.arst_l (jbus_arst_l),
.grst_l (jbus_grst_l),
.adbginit_l (1'b1),
.gdbginit_l (1'b1),
.si (),
); */
bw_clk_cl_jbi_jbus u_jbus_header (/*AUTOINST*/
// Outputs
.so (), // Templated
.dbginit_l(), // Templated
.cluster_grst_l(jbus_rst_l), // Templated
.rclk (jbus_rclk), // Templated
// Inputs
.si (), // Templated
.se (se),
.adbginit_l(1'b1), // Templated
.gdbginit_l(1'b1), // Templated
.arst_l(jbus_arst_l), // Templated
.grst_l(jbus_grst_l), // Templated
.cluster_cken(clk_jbi_jbus_cken), // Templated
.gclk (jbus_gclk)); // Templated
/* bw_clk_cl_jbi_cmp AUTO_TEMPLATE (
.dbginit_l (),
.cluster_grst_l (cmp_rst_l),
.rclk (cmp_rclk),
.so (),
.gclk (cmp_gclk),
.cluster_cken (clk_jbi_cmp_cken),
.arst_l (cmp_arst_l),
.grst_l (cmp_grst_l),
.adbginit_l (1'b1),
.gdbginit_l (1'b1),
.si (),
); */
bw_clk_cl_jbi_cmp u_cmp_header (/*AUTOINST*/
// Outputs
.so (), // Templated
.dbginit_l(), // Templated
.cluster_grst_l(cmp_rst_l), // Templated
.rclk (cmp_rclk), // Templated
// Inputs
.si (), // Templated
.se (se),
.adbginit_l(1'b1), // Templated
.gdbginit_l(1'b1), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (cmp_grst_l), // Templated
.cluster_cken(clk_jbi_cmp_cken), // Templated
.gclk (cmp_gclk)); // Templated
/* cluster_header_sync AUTO_TEMPLATE (
// outputs
.dram_rx_sync_local (),
.dram_tx_sync_local (),
.jbus_rx_sync_local (rx_en_local),
.jbus_tx_sync_local (tx_en_local),
.so (),
// inputs
.dram_rx_sync_global (1'b0),
.dram_tx_sync_global (1'b0),
.jbus_rx_sync_global (ctu_jbi_rx_en),
.jbus_tx_sync_global (ctu_jbi_tx_en),
.si (),
); */
cluster_header_sync u_sync_header (/*AUTOINST*/
// Outputs
.dram_rx_sync_local(), // Templated
.dram_tx_sync_local(), // Templated
.jbus_rx_sync_local(rx_en_local), // Templated
.jbus_tx_sync_local(tx_en_local), // Templated
.so (), // Templated
// Inputs
.dram_rx_sync_global(1'b0), // Templated
.dram_tx_sync_global(1'b0), // Templated
.jbus_rx_sync_global(ctu_jbi_rx_en), // Templated
.jbus_tx_sync_global(ctu_jbi_tx_en), // Templated
.cmp_gclk(cmp_gclk),
.cmp_rclk(cmp_rclk),
.si (), // Templated
.se (se));
//*******************************************************************************
// CMP Reset Flop
//*******************************************************************************
dffrl_async_ns u_dffrl_async_cmp_rst_l_ff0
( .din (cmp_rst_l),
.clk (cmp_rclk),
.rst_l (cmp_arst_l),
.q (cmp_rst_l_ff0)
);
dffrl_async_ns u_dffrl_async_cmp_rst_l_ff1
( .din (cmp_rst_l),
.clk (cmp_rclk),
.rst_l (cmp_arst_l),
.q (cmp_rst_l_ff1)
);
//*******************************************************************************
// Test Stub
//*******************************************************************************
/*test_stub_scan AUTO_TEMPLATE (
.testmode_l (),
.tst_ctu_data_out (test_csr_data_out[2:0]),
.mem_bypass (testmux_sel),
.arst_l (jbus_arst_l),
.mux_drive_disable (), //replaces rst_tri_en for logic
.mem_write_disable (rst_tri_en), //replaces rst_tri_en for memory
// macrotest
.so_0 (MT_so_0),
.long_chain_so_0 (MT_long_chain_so_0),
.short_chain_so_0 (MT_short_chain_so_0),
.so_1 (),
.long_chain_so_1 (1'b0),
.short_chain_so_1 (1'b0),
.so_2 (),
.long_chain_so_2 (1'b0),
.short_chain_so_2 (1'b0),
);*/
test_stub_scan u_test_stub (/*AUTOINST*/
// Outputs
.mux_drive_disable(), // Templated
.mem_write_disable(rst_tri_en), // Templated
.sehold (sehold),
.se (se),
.testmode_l (), // Templated
.mem_bypass (testmux_sel), // Templated
.so_0 (MT_so_0), // Templated
.so_1 (), // Templated
.so_2 (), // Templated
// Inputs
.ctu_tst_pre_grst_l(ctu_tst_pre_grst_l),
.arst_l (jbus_arst_l), // Templated
.global_shift_enable(global_shift_enable),
.ctu_tst_scan_disable(ctu_tst_scan_disable),
.ctu_tst_scanmode(ctu_tst_scanmode),
.ctu_tst_macrotest(ctu_tst_macrotest),
.ctu_tst_short_chain(ctu_tst_short_chain),
.long_chain_so_0(MT_long_chain_so_0), // Templated
.short_chain_so_0(MT_short_chain_so_0), // Templated
.long_chain_so_1(1'b0), // Templated
.short_chain_so_1(1'b0), // Templated
.long_chain_so_2(1'b0), // Templated
.short_chain_so_2(1'b0)); // Templated
//*******************************************************************************
// Memory Inbound Block
//*******************************************************************************
/* jbi_min AUTO_TEMPLATE (
.clk (jbus_rclk),
.rst_l (jbus_rst_l),
.arst_l (jbus_arst_l),
.cpu_clk (cmp_rclk),
.cpu_rst_l (cmp_rst_l),
.hold (sehold),
.cpu_tx_en (tx_en_local),
.cpu_rx_en (rx_en_local),
); */
jbi_min u_min (/*AUTOINST*/
// Outputs
.min_csr_inject_input_done(min_csr_inject_input_done),
.min_csr_err_apar (min_csr_err_apar),
.min_csr_err_adtype (min_csr_err_adtype),
.min_csr_err_dpar_wr (min_csr_err_dpar_wr),
.min_csr_err_dpar_rd (min_csr_err_dpar_rd),
.min_csr_err_dpar_o (min_csr_err_dpar_o),
.min_csr_err_rep_ue (min_csr_err_rep_ue),
.min_csr_err_illegal (min_csr_err_illegal),
.min_csr_err_unsupp (min_csr_err_unsupp),
.min_csr_err_nonex_wr (min_csr_err_nonex_wr),
.min_csr_err_nonex_rd (min_csr_err_nonex_rd),
.min_csr_err_unmap_wr (min_csr_err_unmap_wr),
.min_csr_err_err_cycle (min_csr_err_err_cycle),
.min_csr_err_unexp_dr (min_csr_err_unexp_dr),
.min_csr_err_l2_to0 (min_csr_err_l2_to0),
.min_csr_err_l2_to1 (min_csr_err_l2_to1),
.min_csr_err_l2_to2 (min_csr_err_l2_to2),
.min_csr_err_l2_to3 (min_csr_err_l2_to3),
.min_csr_write_log_addr (min_csr_write_log_addr),
.min_csr_log_addr_owner (min_csr_log_addr_owner[2:0]),
.min_csr_log_addr_adtype (min_csr_log_addr_adtype[7:0]),
.min_csr_log_addr_ttype (min_csr_log_addr_ttype[4:0]),
.min_csr_log_addr_addr (min_csr_log_addr_addr[42:0]),
.min_csr_log_data0 (min_csr_log_data0[63:0]),
.min_csr_log_data1 (min_csr_log_data1[63:0]),
.min_csr_log_ctl_owner (min_csr_log_ctl_owner[2:0]),
.min_csr_log_ctl_parity (min_csr_log_ctl_parity[3:0]),
.min_csr_log_ctl_adtype0 (min_csr_log_ctl_adtype0[7:0]),
.min_csr_log_ctl_adtype1 (min_csr_log_ctl_adtype1[7:0]),
.min_csr_log_ctl_adtype2 (min_csr_log_ctl_adtype2[7:0]),
.min_csr_log_ctl_adtype3 (min_csr_log_ctl_adtype3[7:0]),
.min_csr_log_ctl_adtype4 (min_csr_log_ctl_adtype4[7:0]),
.min_csr_log_ctl_adtype5 (min_csr_log_ctl_adtype5[7:0]),
.min_csr_log_ctl_adtype6 (min_csr_log_ctl_adtype6[7:0]),
.min_csr_perf_dma_rd_in (min_csr_perf_dma_rd_in),
.min_csr_perf_dma_wr (min_csr_perf_dma_wr),
.min_csr_perf_dma_rd_latency(min_csr_perf_dma_rd_latency[4:0]),
.min_csr_perf_dma_wr8 (min_csr_perf_dma_wr8),
.min_csr_perf_blk_q0 (min_csr_perf_blk_q0[3:0]),
.min_csr_perf_blk_q1 (min_csr_perf_blk_q1[3:0]),
.min_csr_perf_blk_q2 (min_csr_perf_blk_q2[3:0]),
.min_csr_perf_blk_q3 (min_csr_perf_blk_q3[3:0]),
.jbi_sctag0_req (jbi_sctag0_req[31:0]),
.jbi_scbuf0_ecc (jbi_scbuf0_ecc[6:0]),
.jbi_sctag0_req_vld (jbi_sctag0_req_vld),
.jbi_sctag1_req (jbi_sctag1_req[31:0]),
.jbi_scbuf1_ecc (jbi_scbuf1_ecc[6:0]),
.jbi_sctag1_req_vld (jbi_sctag1_req_vld),
.jbi_sctag2_req (jbi_sctag2_req[31:0]),
.jbi_scbuf2_ecc (jbi_scbuf2_ecc[6:0]),
.jbi_sctag2_req_vld (jbi_sctag2_req_vld),
.jbi_sctag3_req (jbi_sctag3_req[31:0]),
.jbi_scbuf3_ecc (jbi_scbuf3_ecc[6:0]),
.jbi_sctag3_req_vld (jbi_sctag3_req_vld),
.min_mout_inject_err (min_mout_inject_err),
.min_trans_jid (min_trans_jid[`JBI_JID_WIDTH-1:0]),
.min_snp_launch (min_snp_launch),
.min_free (min_free),
.min_free_jid (min_free_jid[`JBI_JID_WIDTH-1:0]),
.min_aok_on (min_aok_on),
.min_aok_off (min_aok_off),
.min_j_ad_ff (min_j_ad_ff[127:0]),
.min_pio_rtrn_push (min_pio_rtrn_push),
.min_pio_data_err (min_pio_data_err),
.min_mondo_hdr_push (min_mondo_hdr_push),
.min_mondo_data_push (min_mondo_data_push),
.min_mondo_data_err (min_mondo_data_err),
.min_oldest_wri_tag (min_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.min_pre_wri_tag (min_pre_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
// Inputs
.clk (jbus_rclk), // Templated
.rst_l (jbus_rst_l), // Templated
.arst_l (jbus_arst_l), // Templated
.testmux_sel (testmux_sel),
.rst_tri_en (rst_tri_en),
.cpu_clk (cmp_rclk), // Templated
.cpu_rst_l (cmp_rst_l), // Templated
.cpu_tx_en (tx_en_local), // Templated
.cpu_rx_en (rx_en_local), // Templated
.hold (sehold), // Templated
.csr_16x65array_margin (csr_16x65array_margin[4:0]),
.csr_jbi_config_port_pres(csr_jbi_config_port_pres[6:0]),
.csr_jbi_error_config_erren(csr_jbi_error_config_erren),
.csr_jbi_log_enb_apar (csr_jbi_log_enb_apar),
.csr_jbi_log_enb_dpar_wr (csr_jbi_log_enb_dpar_wr),
.csr_jbi_log_enb_dpar_rd (csr_jbi_log_enb_dpar_rd),
.csr_jbi_log_enb_rep_ue (csr_jbi_log_enb_rep_ue),
.csr_jbi_log_enb_nonex_rd(csr_jbi_log_enb_nonex_rd),
.csr_jbi_log_enb_err_cycle(csr_jbi_log_enb_err_cycle),
.csr_jbi_log_enb_dpar_o (csr_jbi_log_enb_dpar_o),
.csr_jbi_log_enb_unexp_dr(csr_jbi_log_enb_unexp_dr),
.csr_jbi_config2_iq_high (csr_jbi_config2_iq_high[3:0]),
.csr_jbi_config2_iq_low (csr_jbi_config2_iq_low[3:0]),
.csr_jbi_config2_max_rd (csr_jbi_config2_max_rd[1:0]),
.csr_jbi_config2_max_wr (csr_jbi_config2_max_wr[3:0]),
.csr_jbi_config2_ord_rd (csr_jbi_config2_ord_rd),
.csr_jbi_config2_ord_wr (csr_jbi_config2_ord_wr),
.csr_jbi_memsize_size (csr_jbi_memsize_size[37:30]),
.csr_jbi_config2_max_wris(csr_jbi_config2_max_wris[1:0]),
.csr_jbi_l2_timeout_timeval(csr_jbi_l2_timeout_timeval[31:0]),
.csr_jbi_err_inject_input(csr_jbi_err_inject_input),
.csr_jbi_err_inject_output(csr_jbi_err_inject_output),
.csr_jbi_err_inject_errtype(csr_jbi_err_inject_errtype),
.csr_jbi_err_inject_xormask(csr_jbi_err_inject_xormask[3:0]),
.csr_jbi_err_inject_count(csr_jbi_err_inject_count[23:0]),
.sctag0_jbi_iq_dequeue (sctag0_jbi_iq_dequeue),
.sctag0_jbi_wib_dequeue (sctag0_jbi_wib_dequeue),
.sctag1_jbi_iq_dequeue (sctag1_jbi_iq_dequeue),
.sctag1_jbi_wib_dequeue (sctag1_jbi_wib_dequeue),
.sctag2_jbi_iq_dequeue (sctag2_jbi_iq_dequeue),
.sctag2_jbi_wib_dequeue (sctag2_jbi_wib_dequeue),
.sctag3_jbi_iq_dequeue (sctag3_jbi_iq_dequeue),
.sctag3_jbi_wib_dequeue (sctag3_jbi_wib_dequeue),
.io_jbi_j_adtype (io_jbi_j_adtype[7:0]),
.io_jbi_j_ad (io_jbi_j_ad[127:0]),
.io_jbi_j_adp (io_jbi_j_adp[3:0]),
.mout_dsbl_sampling (mout_dsbl_sampling),
.mout_scb0_jbus_wr_ack (mout_scb0_jbus_wr_ack),
.mout_scb1_jbus_wr_ack (mout_scb1_jbus_wr_ack),
.mout_scb2_jbus_wr_ack (mout_scb2_jbus_wr_ack),
.mout_scb3_jbus_wr_ack (mout_scb3_jbus_wr_ack),
.mout_scb0_jbus_rd_ack (mout_scb0_jbus_rd_ack),
.mout_scb1_jbus_rd_ack (mout_scb1_jbus_rd_ack),
.mout_scb2_jbus_rd_ack (mout_scb2_jbus_rd_ack),
.mout_scb3_jbus_rd_ack (mout_scb3_jbus_rd_ack),
.mout_trans_valid (mout_trans_valid),
.mout_min_inject_err_done(mout_min_inject_err_done),
.mout_min_jbus_owner (mout_min_jbus_owner[5:0]));
//*******************************************************************************
// Memory Outbound Block
//*******************************************************************************
/* jbi_mout AUTO_TEMPLATE (
.cclk (cmp_rclk),
.crst_l (cmp_rst_l_ff0),
.clk (jbus_rclk),
.rst_l (jbus_rst_l),
.tx_en_local_m1 (tx_en_local),
.hold (sehold),
.arst_l (cmp_arst_l),
); */
jbi_mout u_mout(/*AUTOINST*/
// Outputs
.mout_pio_req_adv (mout_pio_req_adv),
.mout_pio_pop (mout_pio_pop),
.mout_mondo_pop (mout_mondo_pop),
.jbi_io_j_adtype (jbi_io_j_adtype[7:0]),
.jbi_io_j_adtype_en (jbi_io_j_adtype_en),
.jbi_io_j_ad (jbi_io_j_ad[127:0]),
.jbi_io_j_ad_en (jbi_io_j_ad_en[3:0]),
.jbi_io_j_adp (jbi_io_j_adp[3:0]),
.jbi_io_j_adp_en (jbi_io_j_adp_en),
.jbi_io_j_req0_out_l (jbi_io_j_req0_out_l),
.jbi_io_j_req0_out_en (jbi_io_j_req0_out_en),
.jbi_io_j_pack0 (jbi_io_j_pack0[2:0]),
.jbi_io_j_pack0_en (jbi_io_j_pack0_en),
.jbi_io_j_pack1 (jbi_io_j_pack1[2:0]),
.jbi_io_j_pack1_en (jbi_io_j_pack1_en),
.mout_dsbl_sampling (mout_dsbl_sampling),
.mout_trans_yid (mout_trans_yid[`JBI_YID_WIDTH-1:0]),
.mout_trans_valid (mout_trans_valid),
.mout_scb0_jbus_wr_ack (mout_scb0_jbus_wr_ack),
.mout_scb1_jbus_wr_ack (mout_scb1_jbus_wr_ack),
.mout_scb2_jbus_wr_ack (mout_scb2_jbus_wr_ack),
.mout_scb3_jbus_wr_ack (mout_scb3_jbus_wr_ack),
.mout_scb0_jbus_rd_ack (mout_scb0_jbus_rd_ack),
.mout_scb1_jbus_rd_ack (mout_scb1_jbus_rd_ack),
.mout_scb2_jbus_rd_ack (mout_scb2_jbus_rd_ack),
.mout_scb3_jbus_rd_ack (mout_scb3_jbus_rd_ack),
.mout_nack (mout_nack),
.mout_nack_buf_id (mout_nack_buf_id[1:0]),
.mout_nack_thr_id (mout_nack_thr_id[5:0]),
.mout_min_inject_err_done(mout_min_inject_err_done),
.mout_csr_inject_output_done(mout_csr_inject_output_done),
.mout_min_jbus_owner (mout_min_jbus_owner[5:0]),
.mout_port_4_present (mout_port_4_present),
.mout_port_5_present (mout_port_5_present),
.mout_csr_err_cpar (mout_csr_err_cpar),
.mout_csr_jbi_log_par_jpar(mout_csr_jbi_log_par_jpar),
.mout_csr_jbi_log_par_jpack0(mout_csr_jbi_log_par_jpack0[2:0]),
.mout_csr_jbi_log_par_jpack1(mout_csr_jbi_log_par_jpack1[2:0]),
.mout_csr_jbi_log_par_jpack4(mout_csr_jbi_log_par_jpack4[2:0]),
.mout_csr_jbi_log_par_jpack5(mout_csr_jbi_log_par_jpack5[2:0]),
.mout_csr_jbi_log_par_jreq(mout_csr_jbi_log_par_jreq[6:0]),
.mout_csr_err_arb_to (mout_csr_err_arb_to),
.jbi_log_arb_myreq (jbi_log_arb_myreq[2:0]),
.jbi_log_arb_reqtype (jbi_log_arb_reqtype[2:0]),
.jbi_log_arb_aok (jbi_log_arb_aok[6:0]),
.jbi_log_arb_dok (jbi_log_arb_dok[6:0]),
.jbi_log_arb_jreq (jbi_log_arb_jreq[6:0]),
.mout_csr_err_fatal (mout_csr_err_fatal[5:4]),
.mout_csr_err_read_to (mout_csr_err_read_to),
.mout_perf_aok_off (mout_perf_aok_off),
.mout_perf_dok_off (mout_perf_dok_off),
.mout_dbg_pop (mout_dbg_pop),
// Inputs
.scbuf0_jbi_data (scbuf0_jbi_data[31:0]),
.scbuf0_jbi_ctag_vld (scbuf0_jbi_ctag_vld),
.scbuf0_jbi_ue_err (scbuf0_jbi_ue_err),
.sctag0_jbi_por_req_buf (sctag0_jbi_por_req_buf),
.scbuf1_jbi_data (scbuf1_jbi_data[31:0]),
.scbuf1_jbi_ctag_vld (scbuf1_jbi_ctag_vld),
.scbuf1_jbi_ue_err (scbuf1_jbi_ue_err),
.sctag1_jbi_por_req_buf (sctag1_jbi_por_req_buf),
.scbuf2_jbi_data (scbuf2_jbi_data[31:0]),
.scbuf2_jbi_ctag_vld (scbuf2_jbi_ctag_vld),
.scbuf2_jbi_ue_err (scbuf2_jbi_ue_err),
.sctag2_jbi_por_req_buf (sctag2_jbi_por_req_buf),
.scbuf3_jbi_data (scbuf3_jbi_data[31:0]),
.scbuf3_jbi_ctag_vld (scbuf3_jbi_ctag_vld),
.scbuf3_jbi_ue_err (scbuf3_jbi_ue_err),
.sctag3_jbi_por_req_buf (sctag3_jbi_por_req_buf),
.ncio_pio_req (ncio_pio_req),
.ncio_pio_req_rw (ncio_pio_req_rw),
.ncio_pio_req_dest (ncio_pio_req_dest[1:0]),
.ncio_pio_ad (ncio_pio_ad[63:0]),
.ncio_pio_ue (ncio_pio_ue),
.ncio_pio_be (ncio_pio_be[15:0]),
.ncio_yid (ncio_yid[`JBI_YID_WIDTH-1:0]),
.ncio_mondo_req (ncio_mondo_req),
.ncio_mondo_ack (ncio_mondo_ack),
.ncio_mondo_agnt_id (ncio_mondo_agnt_id[`JBI_AD_INT_AGTID_WIDTH-1:0]),
.ncio_mondo_cpu_id (ncio_mondo_cpu_id[`JBI_AD_INT_CPUID_WIDTH-1:0]),
.ncio_prqq_level (ncio_prqq_level[`JBI_PRQQ_ADDR_WIDTH:0]),
.ncio_makq_level (ncio_makq_level[`JBI_MAKQ_ADDR_WIDTH:0]),
.io_jbi_j_pack4 (io_jbi_j_pack4[2:0]),
.io_jbi_j_pack5 (io_jbi_j_pack5[2:0]),
.io_jbi_j_req4_in_l (io_jbi_j_req4_in_l),
.io_jbi_j_req5_in_l (io_jbi_j_req5_in_l),
.io_jbi_j_par (io_jbi_j_par),
.min_free (min_free),
.min_free_jid (min_free_jid[3:0]),
.min_trans_jid (min_trans_jid[`JBI_JID_WIDTH-1:0]),
.min_aok_on (min_aok_on),
.min_aok_off (min_aok_off),
.min_snp_launch (min_snp_launch),
.ncio_mout_nack_pop (ncio_mout_nack_pop),
.min_mout_inject_err (min_mout_inject_err),
.csr_jbi_config_arb_mode(csr_jbi_config_arb_mode[1:0]),
.csr_jbi_arb_timeout_timeval(csr_jbi_arb_timeout_timeval[31:0]),
.csr_jbi_trans_timeout_timeval(csr_jbi_trans_timeout_timeval[31:0]),
.csr_jbi_err_inject_errtype(csr_jbi_err_inject_errtype),
.csr_jbi_err_inject_xormask(csr_jbi_err_inject_xormask[3:0]),
.csr_jbi_debug_info_enb (csr_jbi_debug_info_enb),
.csr_dok_on (csr_dok_on),
.csr_jbi_debug_arb_aggr_arb(csr_jbi_debug_arb_aggr_arb),
.csr_jbi_error_config_fe_enb(csr_jbi_error_config_fe_enb),
.csr_jbi_log_enb_read_to(csr_jbi_log_enb_read_to),
.dbg_req_transparent (dbg_req_transparent),
.dbg_req_arbitrate (dbg_req_arbitrate),
.dbg_req_priority (dbg_req_priority),
.dbg_data (dbg_data[127:0]),
.testmux_sel (testmux_sel),
.hold (sehold), // Templated
.rst_tri_en (rst_tri_en),
.cclk (cmp_rclk), // Templated
.crst_l (cmp_rst_l_ff0), // Templated
.clk (jbus_rclk), // Templated
.rst_l (jbus_rst_l), // Templated
.tx_en_local_m1 (tx_en_local), // Templated
.arst_l (cmp_arst_l)); // Templated
//*******************************************************************************
// NCIO Block (Non-Cached IO)
//*******************************************************************************
/* jbi_ncio AUTO_TEMPLATE (
.clk (jbus_rclk),
.rst_l (jbus_rst_l),
.arst_l (jbus_arst_l),
.cpu_clk (cmp_rclk),
.cpu_rst_l (cmp_rst_l_ff1),
.hold (sehold),
.scan_en (se),
.io_jbi_j_ad_ff (min_j_ad_ff),
.cpu_tx_en (tx_en_local),
.cpu_rx_en (rx_en_local),
); */
jbi_ncio u_ncio (/*AUTOINST*/
// Outputs
.ncio_csr_err_intr_to (ncio_csr_err_intr_to[31:0]),
.ncio_csr_perf_pio_rd_out(ncio_csr_perf_pio_rd_out),
.ncio_csr_perf_pio_wr (ncio_csr_perf_pio_wr),
.ncio_csr_perf_pio_rd_latency(ncio_csr_perf_pio_rd_latency[4:0]),
.ncio_csr_read_addr (ncio_csr_read_addr[`JBI_CSR_ADDR_WIDTH-1:0]),
.ncio_csr_write (ncio_csr_write),
.ncio_csr_write_addr (ncio_csr_write_addr[`JBI_CSR_ADDR_WIDTH-1:0]),
.ncio_csr_write_data (ncio_csr_write_data[`JBI_CSR_WIDTH-1:0]),
.jbi_iob_pio_vld (jbi_iob_pio_vld),
.jbi_iob_pio_data (jbi_iob_pio_data[`JBI_IOB_WIDTH-1:0]),
.jbi_iob_pio_stall (jbi_iob_pio_stall),
.jbi_iob_mondo_vld (jbi_iob_mondo_vld),
.jbi_iob_mondo_data (jbi_iob_mondo_data[`JBI_IOB_MONDO_BUS_WIDTH-1:0]),
.ncio_pio_req (ncio_pio_req),
.ncio_pio_req_rw (ncio_pio_req_rw),
.ncio_pio_req_dest (ncio_pio_req_dest[1:0]),
.ncio_pio_ue (ncio_pio_ue),
.ncio_pio_be (ncio_pio_be[15:0]),
.ncio_pio_ad (ncio_pio_ad[63:0]),
.ncio_yid (ncio_yid[`JBI_YID_WIDTH-1:0]),
.ncio_prqq_level (ncio_prqq_level[`JBI_PRQQ_ADDR_WIDTH:0]),
.ncio_mondo_req (ncio_mondo_req),
.ncio_mondo_ack (ncio_mondo_ack),
.ncio_mondo_agnt_id (ncio_mondo_agnt_id[`JBI_AD_INT_AGTID_WIDTH-1:0]),
.ncio_mondo_cpu_id (ncio_mondo_cpu_id[`JBI_AD_INT_CPUID_WIDTH-1:0]),
.ncio_makq_level (ncio_makq_level[`JBI_MAKQ_ADDR_WIDTH:0]),
.ncio_mout_nack_pop (ncio_mout_nack_pop),
// Inputs
.clk (jbus_rclk), // Templated
.rst_l (jbus_rst_l), // Templated
.arst_l (jbus_arst_l), // Templated
.cpu_clk (cmp_rclk), // Templated
.cpu_rst_l (cmp_rst_l_ff1), // Templated
.cpu_rx_en (rx_en_local), // Templated
.cpu_tx_en (tx_en_local), // Templated
.hold (sehold), // Templated
.testmux_sel (testmux_sel),
.scan_en (se), // Templated
.rst_tri_en (rst_tri_en),
.csr_16x65array_margin (csr_16x65array_margin[4:0]),
.csr_16x81array_margin (csr_16x81array_margin[4:0]),
.csr_jbi_config2_max_pio(csr_jbi_config2_max_pio[3:0]),
.csr_jbi_config2_ord_int(csr_jbi_config2_ord_int),
.csr_jbi_config2_ord_pio(csr_jbi_config2_ord_pio),
.csr_jbi_intr_timeout_timeval(csr_jbi_intr_timeout_timeval[31:0]),
.csr_jbi_intr_timeout_rst_l(csr_jbi_intr_timeout_rst_l),
.csr_int_req (csr_int_req),
.csr_csr_read_data (csr_csr_read_data[`JBI_CSR_WIDTH-1:0]),
.iob_jbi_pio_stall (iob_jbi_pio_stall),
.iob_jbi_pio_vld (iob_jbi_pio_vld),
.iob_jbi_pio_data (iob_jbi_pio_data[`IOB_JBI_WIDTH-1:0]),
.iob_jbi_mondo_ack (iob_jbi_mondo_ack),
.iob_jbi_mondo_nack (iob_jbi_mondo_nack),
.io_jbi_j_ad_ff (min_j_ad_ff), // Templated
.min_pio_rtrn_push (min_pio_rtrn_push),
.min_pio_data_err (min_pio_data_err),
.min_mondo_hdr_push (min_mondo_hdr_push),
.min_mondo_data_push (min_mondo_data_push),
.min_mondo_data_err (min_mondo_data_err),
.min_oldest_wri_tag (min_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.min_pre_wri_tag (min_pre_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.mout_trans_yid (mout_trans_yid[`JBI_YID_WIDTH-1:0]),
.mout_pio_pop (mout_pio_pop),
.mout_pio_req_adv (mout_pio_req_adv),
.mout_mondo_pop (mout_mondo_pop),
.mout_nack (mout_nack),
.mout_nack_buf_id (mout_nack_buf_id[`UCB_BUF_HI-`UCB_BUF_LO:0]),
.mout_nack_thr_id (mout_nack_thr_id[`UCB_THR_HI-`UCB_THR_LO:0]));
//*******************************************************************************
// SSI (System Serial Interface)
//*******************************************************************************
/* jbi_ssi AUTO_TEMPLATE (
.clk (jbus_rclk),
.rst_l (jbus_rst_l),
.arst_l (jbus_arst_l),
); */
jbi_ssi u_ssi (/*AUTOINST*/
// Outputs
.jbi_io_ssi_mosi (jbi_io_ssi_mosi),
.jbi_io_ssi_sck (jbi_io_ssi_sck),
.jbi_iob_spi_vld (jbi_iob_spi_vld),
.jbi_iob_spi_data (jbi_iob_spi_data[3:0]),
.jbi_iob_spi_stall (jbi_iob_spi_stall),
// Inputs
.clk (jbus_rclk), // Templated
.rst_l (jbus_rst_l), // Templated
.arst_l (jbus_arst_l), // Templated
.ctu_jbi_ssiclk (ctu_jbi_ssiclk),
.io_jbi_ssi_miso (io_jbi_ssi_miso),
.io_jbi_ext_int_l (io_jbi_ext_int_l),
.iob_jbi_spi_vld (iob_jbi_spi_vld),
.iob_jbi_spi_data (iob_jbi_spi_data[3:0]),
.iob_jbi_spi_stall (iob_jbi_spi_stall));
//*******************************************************************************
// Debug Port
//*******************************************************************************
/* jbi_dbg AUTO_TEMPLATE (
.clk (jbus_rclk),
.rst_l (jbus_rst_l),
.dbg_rst_l (jbus_rst_l),
.hold (sehold),
.scan_en (se),
); */
jbi_dbg u_dbg (/*AUTOINST*/
// Outputs
.dbg_req_transparent (dbg_req_transparent),
.dbg_req_arbitrate (dbg_req_arbitrate),
.dbg_req_priority (dbg_req_priority),
.dbg_data (dbg_data[127:0]),
// Inputs
.clk (jbus_rclk), // Templated
.rst_l (jbus_rst_l), // Templated
.dbg_rst_l (jbus_rst_l), // Templated
.hold (sehold), // Templated
.testmux_sel (testmux_sel),
.scan_en (se), // Templated
.csr_16x65array_margin (csr_16x65array_margin[4:0]),
.csr_jbi_debug_arb_max_wait(csr_jbi_debug_arb_max_wait[`JBI_CSR_DBG_MAX_WAIT_WIDTH-1:0]),
.csr_jbi_debug_arb_hi_water(csr_jbi_debug_arb_hi_water[`JBI_CSR_DBG_HI_WATER_WIDTH-1:0]),
.csr_jbi_debug_arb_lo_water(csr_jbi_debug_arb_lo_water[`JBI_CSR_DBG_LO_WATER_WIDTH-1:0]),
.csr_jbi_debug_arb_data_arb(csr_jbi_debug_arb_data_arb),
.csr_jbi_debug_arb_tstamp_wrap(csr_jbi_debug_arb_tstamp_wrap[`JBI_CSR_DBG_TSWRAP_WIDTH-1:0]),
.csr_jbi_debug_arb_alternate(csr_jbi_debug_arb_alternate),
.csr_jbi_debug_arb_alternate_set_l(csr_jbi_debug_arb_alternate_set_l),
.iob_jbi_dbg_hi_data (iob_jbi_dbg_hi_data[47:0]),
.iob_jbi_dbg_hi_vld (iob_jbi_dbg_hi_vld),
.iob_jbi_dbg_lo_data (iob_jbi_dbg_lo_data[47:0]),
.iob_jbi_dbg_lo_vld (iob_jbi_dbg_lo_vld),
.mout_dbg_pop (mout_dbg_pop));
//*******************************************************************************
// CSR
//*******************************************************************************
/* jbi_csr AUTO_TEMPLATE (
.clk (jbus_rclk),
.rst_l (jbus_rst_l),
); */
jbi_csr u_csr (/*AUTOINST*/
// Outputs
.csr_csr_read_data (csr_csr_read_data[`JBI_CSR_WIDTH-1:0]),
.csr_jbi_config_port_pres(csr_jbi_config_port_pres[6:0]),
.jbi_io_config_dtl (jbi_io_config_dtl[1:0]),
.csr_jbi_config_arb_mode (csr_jbi_config_arb_mode[1:0]),
.csr_jbi_config2_iq_high (csr_jbi_config2_iq_high[3:0]),
.csr_jbi_config2_iq_low (csr_jbi_config2_iq_low[3:0]),
.csr_jbi_config2_max_rd (csr_jbi_config2_max_rd[1:0]),
.csr_jbi_config2_max_wris(csr_jbi_config2_max_wris[1:0]),
.csr_jbi_config2_max_wr (csr_jbi_config2_max_wr[3:0]),
.csr_jbi_config2_ord_wr (csr_jbi_config2_ord_wr),
.csr_jbi_config2_ord_int (csr_jbi_config2_ord_int),
.csr_jbi_config2_ord_pio (csr_jbi_config2_ord_pio),
.csr_jbi_config2_ord_rd (csr_jbi_config2_ord_rd),
.csr_jbi_config2_max_pio (csr_jbi_config2_max_pio[3:0]),
.csr_16x65array_margin (csr_16x65array_margin[4:0]),
.csr_16x81array_margin (csr_16x81array_margin[4:0]),
.csr_jbi_debug_info_enb (csr_jbi_debug_info_enb),
.csr_jbi_debug_arb_tstamp_wrap(csr_jbi_debug_arb_tstamp_wrap[6:0]),
.csr_jbi_debug_arb_alternate(csr_jbi_debug_arb_alternate),
.csr_jbi_debug_arb_hi_water(csr_jbi_debug_arb_hi_water[4:0]),
.csr_jbi_debug_arb_lo_water(csr_jbi_debug_arb_lo_water[4:0]),
.csr_jbi_debug_arb_data_arb(csr_jbi_debug_arb_data_arb),
.csr_jbi_debug_arb_aggr_arb(csr_jbi_debug_arb_aggr_arb),
.csr_jbi_debug_arb_max_wait(csr_jbi_debug_arb_max_wait[9:0]),
.csr_jbi_debug_arb_alternate_set_l(csr_jbi_debug_arb_alternate_set_l),
.csr_jbi_err_inject_output(csr_jbi_err_inject_output),
.csr_jbi_err_inject_input(csr_jbi_err_inject_input),
.csr_jbi_err_inject_errtype(csr_jbi_err_inject_errtype),
.csr_jbi_err_inject_xormask(csr_jbi_err_inject_xormask[3:0]),
.csr_jbi_err_inject_count(csr_jbi_err_inject_count[23:0]),
.csr_jbi_error_config_fe_enb(csr_jbi_error_config_fe_enb),
.csr_jbi_error_config_erren(csr_jbi_error_config_erren),
.csr_jbi_error_config_sigen(csr_jbi_error_config_sigen),
.csr_jbi_log_enb_apar (csr_jbi_log_enb_apar),
.csr_jbi_log_enb_dpar_wr (csr_jbi_log_enb_dpar_wr),
.csr_jbi_log_enb_dpar_rd (csr_jbi_log_enb_dpar_rd),
.csr_jbi_log_enb_dpar_o (csr_jbi_log_enb_dpar_o),
.csr_jbi_log_enb_rep_ue (csr_jbi_log_enb_rep_ue),
.csr_jbi_log_enb_nonex_rd(csr_jbi_log_enb_nonex_rd),
.csr_jbi_log_enb_read_to (csr_jbi_log_enb_read_to),
.csr_jbi_log_enb_err_cycle(csr_jbi_log_enb_err_cycle),
.csr_jbi_log_enb_unexp_dr(csr_jbi_log_enb_unexp_dr),
.csr_int_req (csr_int_req),
.csr_dok_on (csr_dok_on),
.csr_jbi_l2_timeout_timeval(csr_jbi_l2_timeout_timeval[31:0]),
.csr_jbi_arb_timeout_timeval(csr_jbi_arb_timeout_timeval[31:0]),
.csr_jbi_trans_timeout_timeval(csr_jbi_trans_timeout_timeval[31:0]),
.csr_jbi_intr_timeout_timeval(csr_jbi_intr_timeout_timeval[31:0]),
.csr_jbi_intr_timeout_rst_l(csr_jbi_intr_timeout_rst_l),
.csr_jbi_memsize_size (csr_jbi_memsize_size[37:30]),
.jbi_clk_tr (jbi_clk_tr),
// Inputs
.ncio_csr_read_addr (ncio_csr_read_addr[`JBI_CSR_ADDR_WIDTH-1:0]),
.ncio_csr_write (ncio_csr_write),
.ncio_csr_write_addr (ncio_csr_write_addr[`JBI_CSR_ADDR_WIDTH-1:0]),
.ncio_csr_write_data (ncio_csr_write_data[`JBI_CSR_WIDTH-1:0]),
.mout_port_4_present (mout_port_4_present),
.mout_port_5_present (mout_port_5_present),
.min_csr_inject_input_done(min_csr_inject_input_done),
.mout_csr_inject_output_done(mout_csr_inject_output_done),
.min_csr_err_apar (min_csr_err_apar),
.min_csr_err_adtype (min_csr_err_adtype),
.min_csr_err_dpar_wr (min_csr_err_dpar_wr),
.min_csr_err_dpar_rd (min_csr_err_dpar_rd),
.min_csr_err_dpar_o (min_csr_err_dpar_o),
.min_csr_err_rep_ue (min_csr_err_rep_ue),
.min_csr_err_illegal (min_csr_err_illegal),
.min_csr_err_unsupp (min_csr_err_unsupp),
.min_csr_err_nonex_wr (min_csr_err_nonex_wr),
.min_csr_err_nonex_rd (min_csr_err_nonex_rd),
.min_csr_err_err_cycle (min_csr_err_err_cycle),
.min_csr_err_unexp_dr (min_csr_err_unexp_dr),
.min_csr_err_unmap_wr (min_csr_err_unmap_wr),
.ncio_csr_err_intr_to (ncio_csr_err_intr_to[31:0]),
.min_csr_err_l2_to0 (min_csr_err_l2_to0),
.min_csr_err_l2_to1 (min_csr_err_l2_to1),
.min_csr_err_l2_to2 (min_csr_err_l2_to2),
.min_csr_err_l2_to3 (min_csr_err_l2_to3),
.mout_csr_err_cpar (mout_csr_err_cpar),
.mout_csr_err_arb_to (mout_csr_err_arb_to),
.mout_csr_err_fatal (mout_csr_err_fatal[5:4]),
.mout_csr_err_read_to (mout_csr_err_read_to),
.min_csr_write_log_addr (min_csr_write_log_addr),
.min_csr_log_addr_owner (min_csr_log_addr_owner[2:0]),
.min_csr_log_addr_adtype (min_csr_log_addr_adtype[7:0]),
.min_csr_log_addr_ttype (min_csr_log_addr_ttype[4:0]),
.min_csr_log_addr_addr (min_csr_log_addr_addr[42:0]),
.min_csr_log_ctl_owner (min_csr_log_ctl_owner[2:0]),
.min_csr_log_ctl_parity (min_csr_log_ctl_parity[3:0]),
.min_csr_log_ctl_adtype0 (min_csr_log_ctl_adtype0[7:0]),
.min_csr_log_ctl_adtype1 (min_csr_log_ctl_adtype1[7:0]),
.min_csr_log_ctl_adtype2 (min_csr_log_ctl_adtype2[7:0]),
.min_csr_log_ctl_adtype3 (min_csr_log_ctl_adtype3[7:0]),
.min_csr_log_ctl_adtype4 (min_csr_log_ctl_adtype4[7:0]),
.min_csr_log_ctl_adtype5 (min_csr_log_ctl_adtype5[7:0]),
.min_csr_log_ctl_adtype6 (min_csr_log_ctl_adtype6[7:0]),
.min_csr_log_data0 (min_csr_log_data0[63:0]),
.min_csr_log_data1 (min_csr_log_data1[63:0]),
.mout_csr_jbi_log_par_jpar(mout_csr_jbi_log_par_jpar),
.mout_csr_jbi_log_par_jpack5(mout_csr_jbi_log_par_jpack5[2:0]),
.mout_csr_jbi_log_par_jpack4(mout_csr_jbi_log_par_jpack4[2:0]),
.mout_csr_jbi_log_par_jpack1(mout_csr_jbi_log_par_jpack1[2:0]),
.mout_csr_jbi_log_par_jpack0(mout_csr_jbi_log_par_jpack0[2:0]),
.mout_csr_jbi_log_par_jreq(mout_csr_jbi_log_par_jreq[6:0]),
.jbi_log_arb_myreq (jbi_log_arb_myreq[2:0]),
.jbi_log_arb_reqtype (jbi_log_arb_reqtype[2:0]),
.jbi_log_arb_aok (jbi_log_arb_aok[6:0]),
.jbi_log_arb_dok (jbi_log_arb_dok[6:0]),
.jbi_log_arb_jreq (jbi_log_arb_jreq[6:0]),
.min_csr_perf_dma_rd_in (min_csr_perf_dma_rd_in),
.min_csr_perf_dma_rd_latency(min_csr_perf_dma_rd_latency[4:0]),
.min_csr_perf_dma_wr (min_csr_perf_dma_wr),
.min_csr_perf_dma_wr8 (min_csr_perf_dma_wr8),
.min_csr_perf_blk_q0 (min_csr_perf_blk_q0[3:0]),
.min_csr_perf_blk_q1 (min_csr_perf_blk_q1[3:0]),
.min_csr_perf_blk_q2 (min_csr_perf_blk_q2[3:0]),
.min_csr_perf_blk_q3 (min_csr_perf_blk_q3[3:0]),
.ncio_csr_perf_pio_rd_out(ncio_csr_perf_pio_rd_out),
.ncio_csr_perf_pio_wr (ncio_csr_perf_pio_wr),
.ncio_csr_perf_pio_rd_latency(ncio_csr_perf_pio_rd_latency[4:0]),
.mout_perf_aok_off (mout_perf_aok_off),
.mout_perf_dok_off (mout_perf_dok_off),
.clk (jbus_rclk), // Templated
.rst_l (jbus_rst_l), // Templated
.ctu_jbi_fst_rst_l (ctu_jbi_fst_rst_l),
.sehold (sehold));
endmodule
// Local Variables:
// verilog-library-directories:("." "../jbi_min/rtl" "../jbi_mout/rtl" "../jbi_ncio/rtl" "../jbi_ssi/rtl" "../jbi_dbg/rtl" "../jbi_csr/rtl" "../../common/rtl")
// verilog-library-files: ("../../common/rtl/swrvr_clib.v")
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
parameter CNT = 5;
wire [31:0] w [CNT:0];
generate
for (genvar g=0; g<CNT; g++)
sub sub (.clk(clk), .i(w[g]), .z(w[g+1]));
endgenerate
reg [31:0] w0;
assign w[0] = w0;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
w0 = 32'h1234;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
`define EXPECTED_SUM 32'h1239
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d sum=%x\n",$time, cyc, w[CNT]);
`endif
if (w[CNT] !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (input clk, input [31:0] i, output [31:0] z);
logic [31:0] z_tmp /* verilator public */;
always @(posedge clk)
z_tmp <= i+1+$c("0"); // $c so doesn't optimize away
assign z = z_tmp;
endmodule
|
// synthesis VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
//
// This file is part of multiexp-a5gx.
//
// multiexp-a5gx is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see http://www.gnu.org/licenses/.
module modmult #( parameter n_words = 4
, parameter w_width = 27
, parameter b_offset = 1 // bit offset of MSB for modulo reduction (see note below)
, parameter last_factor = 0 // how many factors are in the modulo reduction? (see note below)
, parameter factor_1 = 0 // factors range from 0 to 15 (represented as 4 bits internally)
, parameter factor_2 = 0
, parameter factor_3 = 0
////////////// BELOW THIS LINE SHOULD BE LOCALAPARAMS - see note ---------------vv
, parameter wbits = $clog2(n_words) // the rest of these should be localparams
, parameter o_width = 2*w_width + wbits + b_offset + 1 // but Quartus follows V2001 strictly and
, parameter m_width = 2*w_width + wbits // does not allow localparams within the
, parameter nres = 2*n_words - 1 // ANSI style parameter list.
, parameter rbits = $clog2(nres) // Do not override these values!!!
)
( output [8:0] m_addr
, output m_rden
, output m_wren
, output [w_width-1:0] m_datao
, input [w_width-1:0] m_datai
, input [w_width-1:0] t_datai
, input aclr
, input clk
, input [2:0] command
, output command_ack
);
/*
*** b_offset explanation ***
We are reducing the product mod a number of bits equal to n_words *
w_width - b_offset. The assumption is that we are reducing a Mersenne or
Crandall prime, which means that we are going to add the MSBs with some
shifts to the LSBs. So that we know where those MSBs start, we
parameterize over b_offset.
After finishing the multiplies, when we read the values out of the
multipliers, we offset the values into the higher-order registers.
When we resolve the carry bits, we simultaneously take the (w_width-
b_offset)th bit from result_reg[n_words-1] and add it into the LSB
of the result_reg[n_words] register, which makes the value stored in
result_reg[n_words-1:0] a (n_words*w_width - b_offset) bit value.
*/
/*
*** last_factor explanation ***
This block assumes that we are reducing the multiplication result mod a
Mersenne or Crandall number, that is, one of the form
2^k - n
for n small and of low Hamming weight. For example, 2^107-1 (Mersenne)
and 2^104 - 17 (Crandall) are both primes.
To reduce mod 2^107-1, note that a product of two 107-bit numbers will
be, at most 214 bits, and further that the result can be viewed as
having two words, w0 and w1, of 107 bits. In other words, the product is
w0 + 2^107*w1. But 2^107 mod 2^107-1 is 1, so the modular reduction
of 2^107*w1 is just w1, and thus the modular reduction of w0 + 2^107*w1
is just w0 + w1.
A similar argument applies to 2^104-17. Now the product is
w0 + 2^104*w1, and 2^104 mod 2^104-17 = 17, so the reduction is
w0 + 17*w1, or w0 + w1 + w1 << 4. (This is why we want n to be of low
Hamming weight.)
factor_0 is always 0. If we are reducing mod a Crandall number, then we
need to add other factors, e.g., 4 in the case above. In this case, also
be sure to change the last_factor parameter.
*/
// last_factor can't be higher than 3; we don't have the support for it
localparam last_factor_int = (last_factor > 3) ? 3 : last_factor;
// '$max' not supported for synthesis even though this is all static data. BOOO.
// add 2 bits for margin in case I've misapprehended the widest possible post-reduction carry.
// TODO: REVISIT if there are problems with synthesis speed.
localparam maxfact_tmp = 2 + ( (factor_3 > factor_2) ?
(factor_3 > factor_1 ?
(factor_3 > 0 ? factor_3 : 0) :
(factor_1 > 0 ? factor_1 : 0)) :
(factor_2 > factor_1 ?
(factor_2 > 0 ? factor_2 : 0) :
(factor_1 > 0 ? factor_1 : 0)) );
localparam maxfactor = (maxfact_tmp < w_width) ? maxfact_tmp : w_width;
localparam r_width = w_width + b_offset + maxfactor;
localparam d_width = w_width + maxfactor;
localparam h_width = w_width + wbits + b_offset + 1;
reg [w_width-1:0] result_reg[n_words-1:0], result_next[n_words-1:0];
reg [w_width-1:0] rshifto_reg[n_words-1:0], rshifto_next[n_words-1:0];
reg [w_width-1:0] mac_y_reg[n_words-1:0], mac_y_next[n_words-1:0];
wire [m_width-1:0] mult_out[n_words-1:0];
reg [w_width-1:0] mac_x, mac_x_reg[n_words-1:0], mac_x_next[n_words-1:0];
wire [n_words-1:0] en_accum;
wire en_mac;
reg [o_width-1:0] mult_o0_reg[n_words-1:0], mult_o0_next[n_words-1:0];
reg [h_width:0] mult_o1h_reg[nres-2:n_words], mult_o1h_next[nres-2:n_words];
reg [o_width-1:0] mult_o1h_n_reg, mult_o1h_n_next;
reg [w_width-1:0] mult_o1l_reg[n_words-1:0], mult_o1l_next[n_words-1:0];
reg [w_width:0] mult_o2_reg[nres-2:n_words], mult_o2_next[nres-2:n_words];
reg [o_width-1:0] mult_o2_n_reg, mult_o2_n_next;
reg [d_width:0] redc_reg[0:last_factor][n_words-2:0], redc_next[0:last_factor][n_words-2:0];
reg [o_width-1:0] redc_n_reg[0:last_factor], redc_n_next[0:last_factor];
reg [w_width:0] carry_o0_reg[n_words-2:0], carry_o0_next[n_words-2:0];
reg [r_width:0] carry_o0_n_reg, carry_o0_n_next;
reg [w_width:0] carry_o1_reg[n_words-2:0], carry_o1_next[n_words-2:0];
reg [r_width:0] carry_o1_n_reg, carry_o1_n_next;
/* *** MULTIPLIERS *** */
genvar MacIter;
generate for(MacIter=0; MacIter<n_words; MacIter++) begin: MacInst
mac_element #( .o_width (m_width)
) mInst ( .data_y (mac_y_reg[MacIter])
, .data_x (mac_x)
, .result (mult_out[MacIter])
, .clk (clk)
, .clken_y (en_mac)
, .clken_x (en_mac)
, .clken_o (en_mac)
, .accumulate (en_accum[MacIter])
, .aclr (aclr)
);
end
endgenerate
/* *** CARRY TREE *** */
wire [n_words-1:2] carry_gen;
wire [n_words-1:2] carry_prop;
wire [n_words-1:2] carry_out;
reg [n_words-1:2] carry_t_reg, carry_t_next;
generate for(MacIter=2; MacIter<n_words; MacIter++) begin: CTreeWires
assign carry_gen[MacIter] = carry_o0_reg[MacIter-1][w_width];
assign carry_prop[MacIter] = &(carry_o0_reg[MacIter-1][w_width-1:0]);
end
endgenerate
carry_tree #( .n_words (n_words-2)
) ctree_inst
( .g (carry_gen[n_words-1:2])
, .p (carry_prop[n_words-1:2])
, .c (carry_out[n_words-1:2])
);
// How many bits could the result after carry tree extend above the "top" of result_reg[n_words-1]?
//
// At maximum, the value in result_reg[2*n_words-2] after multiplication and shifting
// is 2*w_width+b_offset bits wide (because the maximum possible size of the result
// of a multiply is 2*n_words*w_width for n_words*w_width inputs, and we shift that
// up by b_offset). We added that to the low-order words with up to maxfactor shift.
// So we could have as many as maxfactor+b_offset bits above w_width-1, and recall
// that result_reg[n_words-1] is only supposed to be w_width-b_offset bits wide.
wire [2*b_offset+maxfactor:0] reduce_detect = carry_o1_n_reg[w_width+b_offset+maxfactor:w_width-b_offset];
wire continue_reducing = |(reduce_detect);
// In short, if any of these bits are nonzero, we have more reduction to do.
/* *** STATE MACHINE PARAMS *** */
reg [2:0] state_reg, state_next;
reg [wbits-1:0] count_reg, count_next;
reg square_reg, square_next, rammult_reg, rammult_next;
wire last_count = count_reg == (n_words - 1);
`include "mult_commands.vh"
localparam ST_IDLE = 3'b000;
localparam ST_PRELOAD = 3'b001;
localparam ST_STORE = 3'b010;
localparam ST_BEGINMULT = 3'b100;
localparam ST_SHUFFLE = 3'b101;
localparam ST_REDUCE = 3'b110;
localparam ST_CARRY = 3'b111;
wire inST_IDLE = state_reg == ST_IDLE;
wire inST_PRELOAD = state_reg == ST_PRELOAD;
wire inST_STORE = state_reg == ST_STORE;
wire inST_BEGINMULT = state_reg == ST_BEGINMULT;
wire inST_SHUFFLE = state_reg == ST_SHUFFLE;
wire inST_REDUCE = state_reg == ST_REDUCE;
wire inST_CARRY = state_reg == ST_CARRY;
wire nextST_BEGINRAMMULT = inST_IDLE & (command == CMD_BEGINRAMMULT);
wire nextST_BEGINMULT = inST_IDLE & (command == CMD_BEGINMULT);
wire nextST_BEGINSQUARE = inST_IDLE & (command == CMD_BEGINSQUARE);
wire nextST_PRELOAD = inST_IDLE & (command == CMD_PRELOAD);
wire nextST_STORE = inST_IDLE & (command == CMD_STORE);
wire nextST_SHUFFLE = inST_BEGINMULT & last_count;
wire nextST_REDUCE = inST_SHUFFLE & (count_reg == {'0,2'b10});
wire nextST_CARRY = inST_REDUCE & (count_reg == last_factor_int);
/* *** COMBINATIONAL CONTROL SIGNALS *** */
assign command_ack = inST_IDLE;
// address to read/write is determined by state_next and count_next
// such that we are ready to go with our reads/writes immediately
// upon entering a state
assign m_rden = nextST_PRELOAD | inST_PRELOAD | nextST_BEGINRAMMULT | rammult_reg;
assign m_wren = inST_STORE;
assign m_addr = m_wren ? {'0,2'b10,count_reg} : {'0,state_next[1:0],count_next};
assign m_datao = m_wren ? rshifto_reg[0] : '0;
assign en_mac = nextST_BEGINMULT | inST_BEGINMULT | inST_SHUFFLE;
/* Timing sequence for BEGINMULT state
cnt_next cnt_reg inX inY accum output[0] comment
0 X 0 X '0 X ST_IDLE transitioning to ST_BEGINMULT
1 0 d[0] res '1 X ST_BEGINMULT, cnt_reg == 0
2 1 d[1] res<< 'b1110 0
3 2 d[2] res<< 'b1101 d[0]*res
0 3 d[3] res<< 'b1011 d[1]*res<< cnt_next = 0, state_next = ST_SHUFFLE
0 0 0 X '0 d[2]*res<< ST_SHUFFLE
0 1 0 X '0 d[3]*res<<
*/
assign en_accum[n_words-1] = inST_BEGINMULT;
generate for(MacIter=0; MacIter<n_words-1; MacIter++) begin: EnAccInst
assign en_accum[MacIter] = inST_BEGINMULT & (count_reg != MacIter + 1);
end
endgenerate
// as we enter ST_BEGINMULT, mac_x = 0 so that we clear the output registers
// once in ST_BEGINMULT, choose source for X based on multiplication mode
always_comb begin
if (inST_BEGINMULT) begin
if (square_reg) begin
mac_x = mac_x_reg[0];
end else if (rammult_reg) begin
mac_x = m_datai;
end else begin
mac_x = t_datai;
end
end else begin
mac_x = '0;
end
end
// sadly, while Altera's synthesis could handle modmult_v_reduce_step with a task, ModelSim cannot, so we use a `define instead.
`ifndef modmult_v_reduce_step
`define modmult_v_reduce_step(j,k) \
generate if (last_factor_int > (``j``-1)) begin \
always_comb begin \
for (int i=0; i<n_words-1; i++) begin \
redc_next[``j``][i] = redc_reg[``j``][i]; \
end \
redc_n_next[``j``] = redc_n_reg[``j``]; \
if ((state_reg == ST_REDUCE) & (count_reg == ``j``)) begin \
for(int i=0; i<n_words-2; i++) begin \
redc_next[``j``][i] = redc_reg[``j``-1][i] + {mult_o2_reg[n_words+i],{``k``{1'b0}}}; \
end \
redc_next[``j``][n_words-2] = redc_reg[``j``-1][n_words-2] + {'0,mult_o2_n_reg[w_width-1:0],{``k``{1'b0}}}; \
redc_n_next[``j``] = redc_n_reg[``j``-1] + {'0,mult_o2_n_reg[o_width-1:w_width],{``k``{1'b0}}}; \
end \
end \
end \
endgenerate
`else //modmult_v_reduce_step
`error_multmult_v_reduce_step_macro_already_defined
`endif
`modmult_v_reduce_step(1, factor_1)
`modmult_v_reduce_step(2, factor_2)
`modmult_v_reduce_step(3, factor_3)
// careful to undef things once we're done with them
`ifdef modmult_v_reduce_step
`undef modmult_v_reduce_step
`endif //modmult_v_reduce_step
/* *** STATE TRANSITION LOGIC *** */
always_comb begin
result_next = result_reg;
rshifto_next = rshifto_reg;
mac_y_next = mac_y_reg;
mac_x_next = mac_x_reg;
mult_o0_next = mult_o0_reg;
mult_o1l_next = mult_o1l_reg;
mult_o1h_next = mult_o1h_reg;
mult_o1h_n_next = mult_o1h_n_reg;
mult_o2_next = mult_o2_reg;
mult_o2_n_next = mult_o2_n_reg;
carry_o0_next = carry_o0_reg;
carry_o0_n_next = carry_o0_n_reg;
carry_o1_next = carry_o1_reg;
carry_o1_n_next = carry_o1_n_reg;
carry_t_next = carry_t_reg;
state_next = state_reg;
count_next = count_reg;
square_next = square_reg;
rammult_next = rammult_reg;
for (int i=0; i<n_words-1; i++) begin
redc_next[0][i] = redc_reg[0][i];
end
redc_n_next[0] = redc_n_reg[0];
case (state_reg)
ST_IDLE: begin
count_next = '0;
case (command)
CMD_BEGINRAMMULT, CMD_BEGINMULT, CMD_BEGINSQUARE: begin
for (int i=0; i<n_words; i++) begin
mac_y_next[i] = result_reg[i][w_width-1:0];
end
if (command == CMD_BEGINSQUARE) begin
square_next = '1;
rammult_next = '0;
for (int i=0; i<n_words; i++) begin
mac_x_next[i] = result_reg[i][w_width-1:0];
end
end else if (command == CMD_BEGINRAMMULT) begin
square_next = '0;
rammult_next = '1;
end else begin
square_next = '0;
rammult_next = '0;
end
state_next = ST_BEGINMULT;
end
CMD_RESETRESULT: begin
// reset result register to {'0,1'b1}
result_next[0] = {'0,1'b1};
for (int i=1; i<n_words; i++) begin
result_next[i] = '0;
end
//TODO: optimization: remember that result=1, and next time we're
//asked to multiply or square, we can do so quickly by copying
//the input to the result register or no-op, respectively.
end
CMD_STORE: begin
for (int i=0; i<n_words; i++) begin
rshifto_next[i] = result_reg[i];
end
state_next = ST_STORE;
end
CMD_PRELOAD: state_next = ST_PRELOAD;
default: state_next = ST_IDLE;
endcase
end
ST_PRELOAD: begin
for (int i=0; i<n_words; i++) begin
if (count_reg == i) begin
result_next[i][w_width-1:0] = m_datai[w_width-1:0];
end
end
if (last_count) begin // on the last word; we're done
state_next = ST_IDLE;
count_next = '0;
end else begin
count_next = count_reg + 1'b1;
end
end
ST_STORE: begin
for (int i=0; i<n_words-1; i++) begin
rshifto_next[i] = rshifto_reg[i+1];
end
if (last_count) begin
state_next = ST_IDLE;
count_next = '0;
end else begin
count_next = count_reg + 1'b1;
end
end
ST_BEGINMULT: begin
// read out intermediate results as they're available, rippling carries up the chain
if (count_reg == 2) begin
mult_o0_next[0] = mult_out[0];
end
for (int i=3; i<n_words; i++) begin
if (count_reg == i) begin
mult_o0_next[i-2] = mult_out[i-2] + {'0,mult_o0_reg[i-3][o_width-1:w_width]};
mult_o1l_next[i-3] = mult_o0_reg[i-3][w_width-1:0];
end
end
// cyclic shift of y input to multipliers
for (int i=0; i<n_words; i++) begin
automatic int j = i-1 + (i-1 < 0 ? n_words : 0);
mac_y_next[i] = mac_y_reg[j];
end
// if we're squaring, shift the next word of the X operand into mac_x_reg[0]
if (square_reg) begin
for (int i=0; i<n_words-1; i++) begin
mac_x_next[i] = mac_x_reg[i+1];
end
end
if (last_count) begin
state_next = ST_SHUFFLE;
square_next = '0;
rammult_next = '0;
count_next = '0;
end else begin
count_next = count_reg + 1'b1;
end
end
/*
NOTE: in principle, we could save some registers by delaying the offset one cycle,
at the cost of an additional cycle of latency.
TODO: REVISIT if we're having trouble fitting.
*/
ST_SHUFFLE: begin
count_next = count_reg + 1'b1;
case (count_reg)
{'0}: begin
// read out intermediate result, as above, doing ripples
mult_o0_next[n_words-2] = mult_out[n_words-2] + {'0,mult_o0_reg[n_words-3][o_width-1:w_width]};
mult_o1l_next[n_words-3] = mult_o0_reg[n_words-3][w_width-1:0];
end
{'0,1'b1}: begin
// here we finally introduce the offset implied by b_offset
// ripple into nwords-1 register
mult_o0_next[n_words-1] = {'0,mult_out[n_words-1][w_width-b_offset-1:0]} + {'0,mult_o0_reg[n_words-2][o_width-1:w_width]};
mult_o1l_next[n_words-2] = mult_o0_reg[n_words-2][w_width-1:0];
// copy from multout into high registers, resolving one round of saved carries
for(int i=0; i<n_words-1; i++) begin
automatic int j = i-1 + (i-1 < 0 ? n_words : 0);
if (i < n_words - 2) begin
// offset the mult_out into the high registers
mult_o1h_next[i+n_words] = {'0,mult_out[i][w_width-b_offset-1:0],{(b_offset){1'b0}}} + {'0,mult_out[j][m_width-1:w_width-b_offset]};
end else begin
// highest mult_out is a doubleword, so we don't mask its high bits
mult_o1h_n_next = {'0,mult_out[i],{(b_offset){1'b0}}} + {'0,mult_out[j][m_width-1:w_width-b_offset]};
end
end
end
{'0,2'b10}: begin
// mult_o2_reg[n_words-1] is only w_width-b_offset large. We carry everything else up
mult_o1l_next[n_words-1] = {'0,mult_o0_reg[n_words-1][w_width-b_offset-1:0]};
mult_o2_next[n_words] = {'0,mult_o1h_reg[n_words][w_width-1:0]} + {'0,mult_o0_reg[n_words-1][h_width:w_width-b_offset]};
for(int i=n_words+1; i<nres-1; i++) begin
// TODO: REVISIT this optimization; can we add in fewer bits?
// In the previous step, we added numbers of w_width-b_offset and (m_width-(w_width-b_offset)) bits.
// m_width = 2*w_width + wbits, so we have a sum of (w_width - b_offset) + (w_width + wbits + b_offset)
// Max width is thus w_width + wbits + b_offset + 1.
// here we are adding one more bit than this, which should certainly be sufficient
mult_o2_next[i] = {'0,mult_o1h_reg[i][w_width-1:0]} + {'0,mult_o1h_reg[i-1][h_width:w_width]};
end
// the most significant word is actually a double word, so do not mask it
mult_o2_n_next = mult_o1h_n_reg + {'0,mult_o1h_reg[nres-2][h_width:w_width]};
// now we just have to resolve the possible carry-outs with a carry tree (after reducing)
// (carry propagate is result[w_width-1:0]=='1, carry generate is result[w_width]==1'b1
// at this point, the carries have been completely propagated to the higher-order words
// this means we are safe to start the modulo reduction (though be careful because the
// high words can still have carries in the (w_width+1)th bit position. That's OK---
// we'll resolve those during the modular reduction
// NOTE that this approach means that we don't have to bother with the carry tree until
// the very very end. This is pretty sweet.
state_next = ST_REDUCE;
count_next = '0;
end
default: begin
// something wrong here; give up
state_next = ST_IDLE;
count_next = '0;
end
endcase
end
ST_REDUCE: begin
if (count_reg == last_factor_int) begin
state_next = ST_CARRY;
count_next = '0;
end else begin
count_next = count_reg + 1'b1;
end
/* there is danger of overflow here fi result[n_words+i] has excess carry bits or factor is too big */
if (count_reg == 0) begin
for(int i=0; i<n_words-2; i++) begin
redc_next[0][i] = mult_o1l_reg[i] + mult_o2_reg[n_words+i];
end
/* special cases: split lower and upper half of the nres'th register */
redc_next[0][n_words-2] = mult_o1l_reg[n_words-2] + {'0,mult_o2_n_reg[w_width-1:0]};
redc_n_next[0] = mult_o1l_reg[n_words-1] + {'0,mult_o2_n_reg[o_width-1:w_width]};
end
end
ST_CARRY: begin
count_next = count_reg + 1'b1;
case (count_reg)
{'0,2'b00}: begin
// carry width in redc is maxfactor (already includes 2-bit safety margin, see above)
carry_o0_next[0] = {'0,redc_reg[last_factor_int][0][w_width-1:0]};
for(int i=1; i<n_words-1; i++) begin
carry_o0_next[i] = {'0,redc_reg[last_factor_int][i][w_width-1:0]} + {'0,redc_reg[last_factor_int][i-1][d_width:w_width]};
end
carry_o0_n_next = redc_n_reg[last_factor_int] + {'0,redc_reg[last_factor_int][n_words-2][d_width:w_width]};
end
{'0,2'b01}: begin
carry_t_next = carry_out;
end
{'0,2'b10}: begin
// since maxfactor <= w_width (enforced above)
// we know that at this point we have at most 1 bit of carry
// so it's time for the carry tree!
carry_o1_next[0] = carry_o0_reg[0];
carry_o1_next[1] = carry_o0_reg[1] & {w_width{1'b1}};
for(int i=2; i<n_words-1; i++) begin
carry_o1_next[i] = (carry_o0_reg[i] + {'0,carry_t_reg[i]}) & {w_width{1'b1}};
end
carry_o1_n_next = carry_o0_n_reg + {'0,carry_t_reg[n_words-1]};
end
{'0,2'b11}: begin
// clear out high-order result registers
for(int i=n_words+1; i<nres-1; i++) begin
mult_o2_next[i] = '0;
end
mult_o2_n_next = '0;
// any remaining carry coming out of the top of the register gets moved to mult_o2_reg[n_words]
mult_o2_next[n_words] = {'0,reduce_detect};
mult_o1l_next[n_words-1] = {'0,carry_o1_n_reg[w_width-b_offset-1:0]};
// write result registers in case we're done
result_next[n_words-1] = {'0,carry_o1_n_reg[w_width-b_offset-1:0]};
for(int i=0; i<n_words-1; i++) begin
result_next[i] = carry_o1_reg[i][w_width-1:0];
mult_o1l_next[i] = carry_o1_reg[i][w_width-1:0];
end
// Now we detect whether to do another reduction step or not.
if (continue_reducing) begin
state_next = ST_REDUCE;
end else begin
state_next = ST_IDLE;
end
count_next = '0;
end
default: begin
// something wrong here; give up
state_next = ST_IDLE;
count_next = '0;
end
endcase
end
default: begin
// something wrong here; give up
state_next = ST_IDLE;
end
endcase
end
/* *** FLIP-FLOPS *** */
always_ff @(posedge clk or posedge aclr) begin
if (aclr) begin
state_reg <= '0;
count_reg <= '0;
rammult_reg <= '0;
result_reg <= '{default:0};
rshifto_reg <= '{default:0};
square_reg <= '0;
mac_y_reg <= '{default:0};
mac_x_reg <= '{default:0};
mult_o0_reg <= '{default:0};
mult_o1l_reg <= '{default:0};
mult_o1h_reg <= '{default:0};
mult_o1h_n_reg <= '0;
mult_o2_reg <= '{default:0};
mult_o2_n_reg <= '0;
redc_reg <= '{default:0};
redc_n_reg <= '{default:0};
carry_o0_reg <= '{default:0};
carry_o0_n_reg <= '0;
carry_o1_reg <= '{default:0};
carry_o1_n_reg <= '0;
carry_t_reg <= '0;
end else begin
state_reg <= state_next;
count_reg <= count_next;
rammult_reg <= rammult_next;
result_reg <= result_next;
rshifto_reg <= rshifto_next;
square_reg <= square_next;
mac_y_reg <= mac_y_next;
mac_x_reg <= mac_x_next;
mult_o0_reg <= mult_o0_next;
mult_o1l_reg <= mult_o1l_next;
mult_o1h_reg <= mult_o1h_next;
mult_o1h_n_reg <= mult_o1h_n_next;
mult_o2_reg <= mult_o2_next;
mult_o2_n_reg <= mult_o2_n_next;
redc_reg <= redc_next;
redc_n_reg <= redc_n_next;
carry_o0_reg <= carry_o0_next;
carry_o0_n_reg <= carry_o0_n_next;
carry_o1_reg <= carry_o1_next;
carry_o1_n_reg <= carry_o1_n_next;
carry_t_reg <= carry_t_next;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NOR2_PP_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2_PP_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011-2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module axi_hdmi_rx_tpm (
hdmi_clk,
hdmi_sof,
hdmi_de,
hdmi_data,
hdmi_tpm_oos);
input hdmi_clk;
input hdmi_sof;
input hdmi_de;
input [15:0] hdmi_data;
output hdmi_tpm_oos;
wire [15:0] hdmi_tpm_lr_data_s;
wire hdmi_tpm_lr_mismatch_s;
wire [15:0] hdmi_tpm_fr_data_s;
wire hdmi_tpm_fr_mismatch_s;
reg [15:0] hdmi_tpm_data = 'd0;
reg hdmi_tpm_lr_mismatch = 'd0;
reg hdmi_tpm_fr_mismatch = 'd0;
reg hdmi_tpm_oos = 'd0;
// Limited range
assign hdmi_tpm_lr_data_s[15:8] = (hdmi_tpm_data[15:8] < 8'h10) ? 8'h10 :
((hdmi_tpm_data[15:8] > 8'heb) ? 8'heb : hdmi_tpm_data[15:8]);
assign hdmi_tpm_lr_data_s[ 7:0] = (hdmi_tpm_data[ 7:0] < 8'h10) ? 8'h10 :
((hdmi_tpm_data[ 7:0] > 8'heb) ? 8'heb : hdmi_tpm_data[ 7:0]);
assign hdmi_tpm_lr_mismatch_s = (hdmi_tpm_lr_data_s == hdmi_data) ? 1'b0 : 1'b1;
// Full range
assign hdmi_tpm_fr_data_s[15:8] = (hdmi_tpm_data[15:8] < 8'h01) ? 8'h01 :
((hdmi_tpm_data[15:8] > 8'hfe) ? 8'hfe : hdmi_tpm_data[15:8]);
assign hdmi_tpm_fr_data_s[ 7:0] = (hdmi_tpm_data[ 7:0] < 8'h01) ? 8'h01 :
((hdmi_tpm_data[ 7:0] > 8'hfe) ? 8'hfe : hdmi_tpm_data[ 7:0]);
assign hdmi_tpm_fr_mismatch_s = (hdmi_tpm_fr_data_s == hdmi_data) ? 1'b0 : 1'b1;
always @(posedge hdmi_clk) begin
if (hdmi_sof == 1'b1) begin
hdmi_tpm_data <= 16'd0;
hdmi_tpm_lr_mismatch <= 1'd0;
hdmi_tpm_fr_mismatch <= 1'd0;
hdmi_tpm_oos <= hdmi_tpm_lr_mismatch & hdmi_tpm_fr_mismatch;
end else if (hdmi_de == 1'b1) begin
hdmi_tpm_data <= hdmi_tpm_data + 1'b1;
hdmi_tpm_lr_mismatch <= hdmi_tpm_lr_mismatch | hdmi_tpm_lr_mismatch_s;
hdmi_tpm_fr_mismatch <= hdmi_tpm_fr_mismatch | hdmi_tpm_fr_mismatch_s;
end
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
// IP Revision: 10
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dist_mem_gen_1 (
a,
d,
dpra,
clk,
we,
spo,
dpo
);
input wire [11 : 0] a;
input wire [5 : 0] d;
input wire [11 : 0] dpra;
input wire clk;
input wire we;
output wire [5 : 0] spo;
output wire [5 : 0] dpo;
dist_mem_gen_v8_0_10 #(
.C_FAMILY("artix7"),
.C_ADDR_WIDTH(12),
.C_DEFAULT_DATA("0"),
.C_DEPTH(2160),
.C_HAS_CLK(1),
.C_HAS_D(1),
.C_HAS_DPO(1),
.C_HAS_DPRA(1),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_WE(1),
.C_MEM_INIT_FILE("dist_mem_gen_1.mif"),
.C_ELABORATION_DIR("./"),
.C_MEM_TYPE(2),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(6),
.C_PARSER_TYPE(1)
) inst (
.a(a),
.d(d),
.dpra(dpra),
.clk(clk),
.we(we),
.i_ce(1'D1),
.qspo_ce(1'D1),
.qdpo_ce(1'D1),
.qdpo_clk(1'D0),
.qspo_rst(1'D0),
.qdpo_rst(1'D0),
.qspo_srst(1'D0),
.qdpo_srst(1'D0),
.spo(spo),
.dpo(dpo),
.qspo(),
.qdpo()
);
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Generic source synchronous SDR input
*/
module ssio_sdr_in_diff #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire input_clk_p,
input wire input_clk_n,
input wire [WIDTH-1:0] input_d_p,
input wire [WIDTH-1:0] input_d_n,
output wire output_clk,
output wire [WIDTH-1:0] output_q
);
wire input_clk;
wire [WIDTH-1:0] input_d;
genvar n;
generate
if (TARGET == "XILINX") begin
IBUFDS
clk_ibufds_inst (
.I(input_clk_p),
.IB(input_clk_n),
.O(input_clk)
);
for (n = 0; n < WIDTH; n = n + 1) begin
IBUFDS
data_ibufds_inst (
.I(input_d_p[n]),
.IB(input_d_n[n]),
.O(input_d[n])
);
end
end else if (TARGET == "ALTERA") begin
ALT_INBUF_DIFF
clk_inbuf_diff_inst (
.i(input_clk_p),
.ibar(input_clk_n),
.o(input_clk)
);
for (n = 0; n < WIDTH; n = n + 1) begin
ALT_INBUF_DIFF
data_inbuf_diff_inst (
.i(input_d_p[n]),
.ibar(input_d_n[n]),
.o(input_d[n])
);
end
end else begin
assign input_clk = input_clk_p;
assign input_d = input_d_p;
end
endgenerate
ssio_sdr_in #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.WIDTH(WIDTH)
)
ssio_ddr_in_inst(
.input_clk(input_clk),
.input_d(input_d),
.output_clk(output_clk),
.output_q(output_q)
);
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/ppu/ppu_vga.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* VGA output PPU sub-block.
***************************************************************************************************/
/*
* One thing to note about this code is that the image doubles each pixel, so the normal
* resolution of the nes: 256x240 gets scaled up to 512x480, this uses more of the screen on a VGA
*/
`timescale 1ps / 1ps
module ppu_vga
(
input clk_in, // 100MHz system clock signal
input rst_in, // reset signal
//Generated Signals to Drive VGA
output hsync_out, // vga hsync signal
output vsync_out, // vga vsync signal
output [2:0] r_out, // vga red signal
output [2:0] g_out, // vga green signal
output [1:0] b_out, // vga blue signal
//From the below control signal, the PPU returns this value
input [5:0] sys_palette_idx_in, // system palette index (selects output color)
//X, Y, Y Next, pixel clock and a vblank
output [9:0] nes_x_out, // nes x coordinate
output [9:0] nes_y_out, // nes y coordinate
output [9:0] nes_y_next_out, // next line's nes y coordinate
output pix_pulse_out, // 1 clk pulse prior to nes_x update
output vblank_out // indicates a vblank is occuring (no PPU vram access)
);
// Display dimensions (640x480).
localparam [9:0] DISPLAY_W = 10'h280,
DISPLAY_H = 10'h1E0;
// NES screen dimensions (256x240).
localparam [9:0] NES_W = 10'h100,
NES_H = 10'h0F0;
// Border color (surrounding NES screen).
localparam [7:0] BORDER_COLOR = 8'h49;
//
// VGA_SYNC: VGA synchronization control block.
//
wire sync_en; // vga enable signal
wire [9:0] sync_x; // current vga x coordinate
wire [9:0] sync_y; // current vga y coordinate
wire [9:0] sync_x_next; // vga x coordinate for next clock
wire [9:0] sync_y_next; // vga y coordinate for next line
vga_sync vga_sync_blk(
.clk (clk_in ),
.rst (rst_in ),
.hsync (hsync_out ),
.vsync (vsync_out ),
.en (sync_en ),
.x (sync_x ),
.y (sync_y ),
.x_next (sync_x_next ),
.y_next (sync_y_next )
);
//
// Registers.
//
reg [7:0] q_rgb; // output color latch (1 clk delay required by vga_sync)
reg [7:0] d_rgb;
reg q_vblank; // current vblank state
wire d_vblank;
always @(posedge clk_in) begin
if (rst_in)
begin
q_rgb <= 8'h00;
q_vblank <= 1'h0;
end
else
begin
q_rgb <= d_rgb;
q_vblank <= d_vblank;
end
end
//
// Coord and timing signals.
//
wire [9:0] nes_x_next; // nes x coordinate for next clock
wire border; // indicates we are displaying a vga pixel outside the nes extents
/* Why subtract 64 and divide by two
* because each pixel takes up to blocks on a VGA because thye are doubling the pixels then
* we add an offset of 32 to the pixel values (64 / 2) so the image coming out on the VGA
* screen is really 32 pixels shifted to the right, so there is 32 x double pixels before the
* x image (64 real pixels) and 32 after, so this make the 256 bit wide image right in the
* center of the 320 image, or completely expanded out:
* |--------------------| = Image = (320 *2) = 640 pixels wide
* |32|-----256------|32| = 320
* |64|-----512------|64| = 640
*/
assign nes_x_out = (sync_x - 10'h040) >> 1;
assign nes_y_out = sync_y >> 1;
assign nes_x_next = (sync_x_next - 10'h040) >> 1;
assign nes_y_next_out = sync_y_next >> 1;
assign border = (nes_x_out >= NES_W) || (nes_y_out < 8) || (nes_y_out >= (NES_H - 8));
//
// Lookup RGB values based on sys_palette_idx.
//
always @*
begin
if (!sync_en)
begin
d_rgb = 8'h00;
end
else if (border)
begin
d_rgb = BORDER_COLOR;
end
else
begin
// Lookup RGB values based on sys_palette_idx. Table is an approximation of the NES
// system palette. Taken from http://nesdev.parodius.com/NESTechFAQ.htm#nessnescompat.
case (sys_palette_idx_in)
6'h00: d_rgb = { 3'h3, 3'h3, 2'h1 };
6'h01: d_rgb = { 3'h1, 3'h0, 2'h2 };
6'h02: d_rgb = { 3'h0, 3'h0, 2'h2 };
6'h03: d_rgb = { 3'h2, 3'h0, 2'h2 };
6'h04: d_rgb = { 3'h4, 3'h0, 2'h1 };
6'h05: d_rgb = { 3'h5, 3'h0, 2'h0 };
6'h06: d_rgb = { 3'h5, 3'h0, 2'h0 };
6'h07: d_rgb = { 3'h3, 3'h0, 2'h0 };
6'h08: d_rgb = { 3'h2, 3'h1, 2'h0 };
6'h09: d_rgb = { 3'h0, 3'h2, 2'h0 };
6'h0a: d_rgb = { 3'h0, 3'h2, 2'h0 };
6'h0b: d_rgb = { 3'h0, 3'h1, 2'h0 };
6'h0c: d_rgb = { 3'h0, 3'h1, 2'h1 };
6'h0d: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h0e: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h0f: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h10: d_rgb = { 3'h5, 3'h5, 2'h2 };
6'h11: d_rgb = { 3'h0, 3'h3, 2'h3 };
6'h12: d_rgb = { 3'h1, 3'h1, 2'h3 };
6'h13: d_rgb = { 3'h4, 3'h0, 2'h3 };
6'h14: d_rgb = { 3'h5, 3'h0, 2'h2 };
6'h15: d_rgb = { 3'h7, 3'h0, 2'h1 };
6'h16: d_rgb = { 3'h6, 3'h1, 2'h0 };
6'h17: d_rgb = { 3'h6, 3'h2, 2'h0 };
6'h18: d_rgb = { 3'h4, 3'h3, 2'h0 };
6'h19: d_rgb = { 3'h0, 3'h4, 2'h0 };
6'h1a: d_rgb = { 3'h0, 3'h5, 2'h0 };
6'h1b: d_rgb = { 3'h0, 3'h4, 2'h0 };
6'h1c: d_rgb = { 3'h0, 3'h4, 2'h2 };
6'h1d: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h1e: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h1f: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h20: d_rgb = { 3'h7, 3'h7, 2'h3 };
6'h21: d_rgb = { 3'h1, 3'h5, 2'h3 };
6'h22: d_rgb = { 3'h2, 3'h4, 2'h3 };
6'h23: d_rgb = { 3'h5, 3'h4, 2'h3 };
6'h24: d_rgb = { 3'h7, 3'h3, 2'h3 };
6'h25: d_rgb = { 3'h7, 3'h3, 2'h2 };
6'h26: d_rgb = { 3'h7, 3'h3, 2'h1 };
6'h27: d_rgb = { 3'h7, 3'h4, 2'h0 };
6'h28: d_rgb = { 3'h7, 3'h5, 2'h0 };
6'h29: d_rgb = { 3'h4, 3'h6, 2'h0 };
6'h2a: d_rgb = { 3'h2, 3'h6, 2'h1 };
6'h2b: d_rgb = { 3'h2, 3'h7, 2'h2 };
6'h2c: d_rgb = { 3'h0, 3'h7, 2'h3 };
6'h2d: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h2e: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h2f: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h30: d_rgb = { 3'h7, 3'h7, 2'h3 };
6'h31: d_rgb = { 3'h5, 3'h7, 2'h3 };
6'h32: d_rgb = { 3'h6, 3'h6, 2'h3 };
6'h33: d_rgb = { 3'h6, 3'h6, 2'h3 };
6'h34: d_rgb = { 3'h7, 3'h6, 2'h3 };
6'h35: d_rgb = { 3'h7, 3'h6, 2'h3 };
6'h36: d_rgb = { 3'h7, 3'h5, 2'h2 };
6'h37: d_rgb = { 3'h7, 3'h6, 2'h2 };
6'h38: d_rgb = { 3'h7, 3'h7, 2'h2 };
6'h39: d_rgb = { 3'h7, 3'h7, 2'h2 };
6'h3a: d_rgb = { 3'h5, 3'h7, 2'h2 };
6'h3b: d_rgb = { 3'h5, 3'h7, 2'h3 };
6'h3c: d_rgb = { 3'h4, 3'h7, 2'h3 };
6'h3d: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h3e: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h3f: d_rgb = { 3'h0, 3'h0, 2'h0 };
endcase
end
end
assign { r_out, g_out, b_out } = q_rgb;
assign pix_pulse_out = nes_x_next != nes_x_out;
// Clear the VBLANK signal immediately before starting processing of the pre-0 garbage line. From
// here. Set the vblank approximately 2270 CPU cycles before it will be cleared. This is done
// in order to pass vbl_clear_time.nes. It eats into the visible portion of the playfield, but we
// currently hide that portion of the screen anyway.
assign d_vblank = ((sync_x == 730) && (sync_y == 477)) ? 1'b1 :
((sync_x == 64) && (sync_y == 519)) ? 1'b0 : q_vblank;
assign vblank_out = q_vblank;
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:57:54 11/09/2015
// Design Name:
// Module Name: vga_scandoubler
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_scandoubler (
input wire clkvideo,
input wire clkvga,
input wire enable_scandoubling,
input wire disable_scaneffect, // 1 to disable scanlines
input wire [2:0] ri,
input wire [2:0] gi,
input wire [2:0] bi,
input wire hsync_ext_n,
input wire vsync_ext_n,
input wire csync_ext_n,
output reg [2:0] ro,
output reg [2:0] go,
output reg [2:0] bo,
output reg hsync,
output reg vsync
);
parameter [31:0] CLKVIDEO = 12000;
// http://www.epanorama.net/faq/vga2rgb/calc.html
// SVGA 800x600
// HSYNC = 3.36us VSYNC = 114.32us
parameter [63:0] HSYNC_COUNT = (CLKVIDEO * 3360 * 2)/1000000;
parameter [63:0] VSYNC_COUNT = (CLKVIDEO * 114320 * 2)/1000000;
reg [10:0] addrvideo = 11'd0, addrvga = 11'b00000000000;
reg [9:0] totalhor = 10'd0;
wire [2:0] rout, gout, bout;
// Memoria de doble puerto que guarda la información de dos scans
// Cada scan puede ser de hasta 1024 puntos, incluidos aquí los
// puntos en negro que se pintan durante el HBlank
vgascanline_dport memscan (
.clk(clkvga),
.addrwrite(addrvideo),
.addrread(addrvga),
.we(1'b1),
.din({ri,gi,bi}),
.dout({rout,gout,bout})
);
// Para generar scanlines:
reg scaneffect = 1'b0;
wire [2:0] rout_dimmed, gout_dimmed, bout_dimmed;
color_dimmed apply_to_red (rout, rout_dimmed);
color_dimmed apply_to_green (gout, gout_dimmed);
color_dimmed apply_to_blue (bout, bout_dimmed);
wire [2:0] ro_vga = (scaneffect | disable_scaneffect)? rout : rout_dimmed;
wire [2:0] go_vga = (scaneffect | disable_scaneffect)? gout : gout_dimmed;
wire [2:0] bo_vga = (scaneffect | disable_scaneffect)? bout : bout_dimmed;
// Voy alternativamente escribiendo en una mitad o en otra del scan buffer
// Cambio de mitad cada vez que encuentro un pulso de sincronismo horizontal
// En "totalhor" mido el número de ciclos de reloj que hay en un scan
always @(posedge clkvideo) begin
// if (vsync_ext_n == 1'b0) begin
// addrvideo <= 11'd0;
// end
if (hsync_ext_n == 1'b0 && addrvideo[9:7] != 3'b000) begin
totalhor <= addrvideo[9:0];
addrvideo <= {~addrvideo[10],10'b0000000000};
end
else
addrvideo <= addrvideo + 11'd1;
end
// Recorro el scanbuffer al doble de velocidad, generando direcciones para
// el scan buffer. Cada vez que el video original ha terminado una linea,
// cambio de mitad de buffer. Cuando termino de recorrerlo pero aún no
// estoy en un retrazo horizontal, simplemente vuelvo a recorrer el scan buffer
// desde el mismo origen
// Cada vez que termino de recorrer el scan buffer basculo "scaneffect" que
// uso después para mostrar los píxeles a su brillo nominal, o con su brillo
// reducido para un efecto chachi de scanlines en la VGA
always @(posedge clkvga) begin
// if (vsync_ext_n == 1'b0) begin
// addrvga <= 11'b10000000000;
// scaneffect <= 1'b0;
// end
if (addrvga[9:0] == totalhor && hsync_ext_n == 1'b1) begin
addrvga <= {addrvga[10], 10'b000000000};
scaneffect <= ~scaneffect;
end
else if (hsync_ext_n == 1'b0 && addrvga[9:7] != 3'b000) begin
addrvga <= {~addrvga[10],10'b000000000};
scaneffect <= ~scaneffect;
end
else
addrvga <= addrvga + 11'd1;
end
// El HSYNC de la VGA está bajo sólo durante HSYNC_COUNT ciclos a partir del comienzo
// del barrido de un scanline
reg hsync_vga, vsync_vga;
always @* begin
if (addrvga[9:0] < HSYNC_COUNT[9:0])
hsync_vga = 1'b0;
else
hsync_vga = 1'b1;
end
// El VSYNC de la VGA está bajo sólo durante VSYNC_COUNT ciclos a partir del flanco de
// bajada de la señal de sincronismo vertical original
reg [15:0] cntvsync = 16'hFFFF;
initial vsync_vga = 1'b1;
always @(posedge clkvga) begin
if (vsync_ext_n == 1'b0) begin
if (cntvsync == 16'hFFFF) begin
cntvsync <= 16'd0;
vsync_vga <= 1'b0;
end
else if (cntvsync != 16'hFFFE) begin
if (cntvsync == VSYNC_COUNT[15:0]) begin
vsync_vga <= 1'b1;
cntvsync <= 16'hFFFE;
end
else
cntvsync <= cntvsync + 16'd1;
end
end
else if (vsync_ext_n == 1'b1)
cntvsync <= 16'hFFFF;
end
always @* begin
if (enable_scandoubling == 1'b0) begin // 15kHz output
ro = ri;
go = gi;
bo = bi;
hsync = csync_ext_n;
vsync = 1'b1;
end
else begin // VGA output
ro = ro_vga;
go = go_vga;
bo = bo_vga;
hsync = hsync_vga;
vsync = vsync_vga;
end
end
endmodule
// Una memoria de doble puerto: uno para leer, y otro para
// escribir. Es de 2048 direcciones: 1024 se emplean para
// guardar un scan, y otros 1024 para el siguiente scan
module vgascanline_dport (
input wire clk,
input wire [10:0] addrwrite,
input wire [10:0] addrread,
input wire we,
input wire [8:0] din,
output reg [8:0] dout
);
reg [8:0] scan[0:2047]; // two scanlines
always @(posedge clk) begin
dout <= scan[addrread];
if (we == 1'b1)
scan[addrwrite] <= din;
end
endmodule
module color_dimmed (
input wire [2:0] in,
output reg [2:0] out // out is scaled to roughly 70% of in
);
always @* begin // a LUT
case (in)
3'd0 : out = 3'd0;
3'd1 : out = 3'd1;
3'd2 : out = 3'd1;
3'd3 : out = 3'd2;
3'd4 : out = 3'd3;
3'd5 : out = 3'd3;
3'd6 : out = 3'd4;
3'd7 : out = 3'd5;
default: out = 3'd0;
endcase
end
endmodule
|
module LiftControl(sw0,sw1,sw2,sw3,sw4,sw5,reset,k0,k1,k2,k3,CLK
,Up1Dis,Up2Dis,Up3Dis,Dn2Dis,Dn3Dis,Dn4Dis,Stop1Dis,Stop2Dis
,Stop3Dis,Stop4Dis,PosDis/*,choice*/,seg);//核心控制模块,The Top Level
output Up1Dis,Up2Dis,Up3Dis,Dn2Dis,Dn3Dis,Dn4Dis,Stop1Dis,Stop2Dis,Stop3Dis,Stop4Dis;//向上、向下与停靠的请求显示
output[3:0] PosDis;//楼层显示
output[6:0] seg;
//input choice;
input sw0,sw1,sw2,sw3,sw4,sw5,reset,k0,k1,k2,k3,CLK;//向上、向下与停靠的按键输入
wire clk,reset;
reg DoorFlag=1'b0,blink;
reg Up1Dis,Up2Dis,Up3Dis,Dn2Dis,Dn3Dis,Dn4Dis,Stop1Dis,Stop2Dis,Stop3Dis,Stop4Dis;
reg[1:0] UpDnFlag=2'b00;
reg[2:0] count;//门开后要持续4个时钟周期,用count
reg[3:0] pos,PosDis;
wire[6:0] seg;
//reg speedup=1'b0;
reg[3:0] UpReq,DownReq,StopReq;//分别用来合并向上请求的各信号，向下请求的各信号和停靠请求的各信号
reg[6:0] LiftState=7'b0000001,NextState=7'b0000001;//分别表示电梯的当前状态和下一状态
parameter WAIT=7'b0000001, UP=7'b0000010, DOWN=7'b0000100, UPSTOP=7'b0001000
, DOWNSTOP=7'b0010000, OPENDOOR=7'b0100000, CLOSEDOOR=7'b1000000;
parameter IDLE=4'b0000,FLOOR1=4'b0001, FLOOR2=4'b0010, FLOOR3=4'b0100, FLOOR4=4'b1000;
parameter TRUE=1'b1, FALSE=1'b0;
parameter OPEN=1'b1, CLOSED=1'b0;
parameter UPFLAG=2'b01,DNFLAG=2'b10,STATIC=2'b00;
FrequenceDevide fd(.CLK(CLK),.reset(reset),.clk(clk));//降频模块
LEDDisplay led(.pos(pos), .seg(seg));
/*
always @(posedge clk or posedge choice)
if(choice)
FrequenceDevide fd(.CLK(CLK),.reset(reset),.clk(clk));//降频模块
else
FrequenceDevide2 fd(.speedup(speedup),.CLK(CLK),.reset(reset),.clk(clk));//降频模块*/
always @(posedge sw0 or posedge reset or posedge DoorFlag)//一层上升请求
begin
if(reset)
Up1Dis<=1'b0;
if(sw0)
Up1Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0001)
begin
Up1Dis<=1'b0;
end
end
end
always @(posedge sw1 or posedge reset or posedge DoorFlag)//二层上升请求
begin
if(reset)
Up2Dis<=1'b0;
if(sw1)
Up2Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0010)
begin
Up2Dis<=1'b0;
end
end
end
always @(posedge sw2 or posedge reset or posedge DoorFlag)//三层上升请求
begin
if(reset)
Up3Dis<=1'b0;
if(sw2)
Up3Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0100)
begin
Up3Dis<=1'b0;
end
end
end
always @(posedge sw3 or posedge reset or posedge DoorFlag)//二层下降请求
begin
if(reset)
Dn2Dis<=1'b0;
if(sw3)
Dn2Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0010)
begin
Dn2Dis<=1'b0;
end
end
end
always @(posedge sw4 or posedge reset or posedge DoorFlag)//三层下降请求
begin
if(reset)
Dn3Dis<=1'b0;
if(sw4)
Dn3Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0100)
begin
Dn3Dis<=1'b0;
end
end
end
always @(posedge sw5 or posedge reset or posedge DoorFlag)//四层下降请求
begin
if(reset)
Dn4Dis<=1'b0;
if(sw5)
Dn4Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b1000)
begin
Dn4Dis<=1'b0;
end
end
end
always @(posedge k0 or posedge reset or posedge DoorFlag)
begin
if(reset)
Stop1Dis<=1'b0;
if(k0)
Stop1Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0001)
begin
Stop1Dis<=1'b0;
end
end
end
always @(posedge k1 or posedge reset or posedge DoorFlag)
begin
if(reset)
Stop2Dis<=1'b0;
if(k1)
Stop2Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0010)
begin
Stop2Dis<=1'b0;
end
end
end
always @(posedge k2 or posedge reset or posedge DoorFlag)
begin
if(reset)
Stop3Dis<=1'b0;
if(k2)
Stop3Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0100)
begin
Stop3Dis<=1'b0;
end
end
end
always @(posedge k3 or posedge reset or posedge DoorFlag)
begin
if(reset)
Stop4Dis<=1'b0;
if(k3)
Stop4Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b1000)
begin
Stop4Dis<=1'b0;
end
end
end
always @(pos or blink or reset or clk)
begin
if(reset)
PosDis=4'b0001;
else if(blink)//开门LED闪烁
PosDis=IDLE;
else
case(pos)
FLOOR1:
PosDis=FLOOR1;
FLOOR2:
PosDis=FLOOR2;
FLOOR3:
PosDis=FLOOR3;
FLOOR4:
PosDis=FLOOR4;
default:
PosDis=FLOOR1;
endcase
//若使用如下方法，电梯不能正常运行
//同时赋值时钟脉冲紊乱，故单独使用LEDDisplay模块处理楼层LED显示
/*case(pos)
FLOOR1:
begin
PosDis<=FLOOR1;
seg<=7'b1111001;
end
FLOOR2:
begin
PosDis<=FLOOR2;
seg<=7'b0100100;
end
FLOOR3:
begin
PosDis<=FLOOR3;
seg<=7'b0110000;
end
FLOOR4:
begin
PosDis<=FLOOR4;
seg<=7'b0011001;
end
default:
begin
PosDis<=FLOOR1;
seg<=7'b1111001;
end
endcase */
end
always @(Up1Dis or Up2Dis or Up3Dis )
UpReq={1'b0,Up3Dis,Up2Dis,Up1Dis};
always @(Dn2Dis or Dn3Dis or Dn4Dis)
DownReq={Dn4Dis, Dn3Dis, Dn2Dis,1'b0};
always @(Stop1Dis or Stop2Dis or Stop3Dis or Stop4Dis)
StopReq={Stop4Dis,Stop3Dis,Stop2Dis,Stop1Dis};
always @(posedge clk or posedge reset)
if(reset)
begin
LiftState<=WAIT;
end
else
begin
LiftState<=NextState;
end
always @(clk)
begin
if((DoorFlag==OPEN)&&(~clk))//门打开并且时钟信号处于低电平
blink<=1'b1;//开门LED闪烁信号
else
blink<=1'b0;
end
always @(LiftState or UpReq or DownReq or StopReq or pos or count or UpDnFlag or reset)
begin
if(reset)
NextState=WAIT;
else
case(LiftState)
WAIT:
begin
if(StopReq>0)//有停靠请求否
begin
if((StopReq&pos)>0)//停靠请求中有当前楼层停靠请求否
NextState=OPENDOOR;//有当前楼层请求，则下一状态转开门
else if(StopReq>pos)//有当前楼层之上的停靠请求否
NextState=UP;
else
NextState=DOWN;
end
else if((UpReq&pos)||(DownReq&pos))//上下请求中有当前楼层请求否
begin
NextState=OPENDOOR;
end
else if((UpReq>pos)||(DownReq>pos))//上下请求中有当前楼层之上的请求否
NextState=UP;
else if(UpReq||DownReq)//上下请求中有当前楼层之下的请求否
NextState=DOWN;
else
NextState=WAIT;//无任何请求，继续处于WAIT模式
end
UP:
begin
if((StopReq&pos)||(UpReq&pos))//停靠或上升请求中有当前楼层的请求否
NextState=UPSTOP;//有，下一状态转为UPSTOP(停靠后要1s才开门,UPSTOP即为这1s的过渡期)
else if((StopReq>pos)||(UpReq>pos))//停靠或上升请求中有当前楼层之上的请求否
NextState=UP;
else if(DownReq>0)//有下降请求否
begin
if((DownReq>pos)&&((DownReq^pos)>pos))//下降请求中有当前楼层之上的请求否
NextState=UP;
else if((DownReq&pos)&&(pos<FLOOR4))
NextState=DOWNSTOP;
else if((DownReq&pos)&&(pos==FLOOR4))
NextState=DOWNSTOP;
else//下降请求中只有当前楼层之下的请求
NextState=DOWN;
end
else if(StopReq||UpReq)//只有当前楼层之上的停靠或上升请求否
NextState=DOWN;
else
NextState=WAIT;//无任何请求，转为WAIT模式
end
DOWN:
begin
if((StopReq&pos)||(DownReq&pos))
NextState=DOWNSTOP;
else if(((StopReq&FLOOR1)<pos&&(StopReq&FLOOR1))||((StopReq&FLOOR2)<pos&&(StopReq&FLOOR2))||((StopReq&FLOOR3)<pos&&(StopReq&FLOOR3))||((StopReq&FLOOR4)<pos&&(StopReq&FLOOR4)))
NextState=DOWN;
else if(((DownReq&FLOOR1)<pos&&(DownReq&FLOOR1))||((DownReq&FLOOR2)<pos&&(DownReq&FLOOR2))||((DownReq&FLOOR3)<pos&&(DownReq&FLOOR3))||((DownReq&FLOOR4)<pos&&(DownReq&FLOOR4)))
NextState=DOWN;
else if(UpReq>0)
begin
if(((UpReq&FLOOR1)<pos&&(UpReq&FLOOR1))||((UpReq&FLOOR2)<pos&&(UpReq&FLOOR2))||((UpReq&FLOOR3)<pos&&(UpReq&FLOOR3))||((UpReq&FLOOR4)<pos&&(UpReq&FLOOR4)))
NextState=DOWN;
else if((UpReq&pos)&&(pos>FLOOR1))
NextState=UPSTOP;
else if((UpReq&pos)&&(pos==FLOOR1))
NextState=UPSTOP;
else
NextState=UP;
end
else if(StopReq||DownReq)
NextState=UP;
else
NextState=WAIT;
end
UPSTOP:
begin
NextState=OPENDOOR;
end
DOWNSTOP:
begin
NextState=OPENDOOR;
end
OPENDOOR:
begin
if(count<4)//开门不足4周期，则继续转移到开门状态
NextState=OPENDOOR;
else
NextState=CLOSEDOOR;
end
CLOSEDOOR:
begin
if(UpDnFlag==UPFLAG)//开门关门前电梯是处于上升状态
begin
if((StopReq&pos)||(UpReq&pos))//上升或停靠请求中有当前楼层的请求否，有可能关门的瞬间又有新的请求
NextState=OPENDOOR;
else if((StopReq>pos)||(UpReq>pos))//上升或停靠请求中有当前楼层之上的请求否
NextState=UP;
else if(DownReq>0)//有下降请求否
begin
if((DownReq>pos)&&((DownReq^pos)>pos))//有当前楼层之上的下降请求，则下一状态转移上升
NextState=UP;
else if((DownReq&pos)>0)//有当前楼层的下降请求信号，且更上层无下降请求
NextState=OPENDOOR;
else//只有低于当前层的下降请求
NextState=DOWN;
end
else if(StopReq||UpReq)//上升和停靠请求中只有当前层下的请求
NextState=DOWN;
else
NextState=WAIT;//无任何请求，转为WAIT模式
end
else if(UpDnFlag==DNFLAG)
begin
if((StopReq&pos)||(DownReq&pos))
NextState=OPENDOOR;
else if(((StopReq&FLOOR1)<pos&&(StopReq&FLOOR1))||((StopReq&FLOOR2)<pos&&(StopReq&FLOOR2))||((StopReq&FLOOR3)<pos&&(StopReq&FLOOR3))||((StopReq&FLOOR4)<pos&&(StopReq&FLOOR4)))
NextState=DOWN;
else if(((DownReq&FLOOR1)<pos&&(DownReq&FLOOR1))||((DownReq&FLOOR2)<pos&&(DownReq&FLOOR2))||((DownReq&FLOOR3)<pos&&(DownReq&FLOOR3))||((DownReq&FLOOR4)<pos&&(DownReq&FLOOR4)))
NextState=DOWN;
else if(UpReq>0)
begin
if(((UpReq&FLOOR1)<pos&&(UpReq&FLOOR1))||((UpReq&FLOOR2)<pos&&(UpReq&FLOOR2))||((UpReq&FLOOR3)<pos&&(UpReq&FLOOR3))||((UpReq&FLOOR4)<pos&&(UpReq&FLOOR4)))
NextState=DOWN;
else if((UpReq&pos)>0)
NextState=OPENDOOR;
else
NextState=UP;
end
else if(StopReq||DownReq)
NextState=UP;
else
NextState=WAIT;
end
else
begin
if(StopReq>0)
begin
if((StopReq&pos)>0)
NextState=OPENDOOR;
else if(StopReq>pos)
NextState=UP;
else
NextState=DOWN;
end
else if((UpReq&pos)||(DownReq&pos))
begin
NextState=OPENDOOR;
end
else if((UpReq>pos)||(DownReq>pos))
NextState=UP;
else if(UpReq||DownReq)
NextState=DOWN;
else
begin
NextState=WAIT;
end
end
end
default:
NextState=WAIT;
endcase
end
always @(posedge clk or posedge reset)
if(reset)
begin
pos<=FLOOR1;
DoorFlag<=CLOSED;
UpDnFlag<=STATIC;
end
else
begin
case(NextState)
WAIT:
begin
pos<=pos;
DoorFlag<=CLOSED;
UpDnFlag<=STATIC;
end
UP:
begin
pos<=pos<<1;
DoorFlag<=CLOSED;
UpDnFlag<=UPFLAG;
end
DOWN:
begin
pos<=pos>>1;
DoorFlag<=CLOSED;
UpDnFlag<=DNFLAG;
end
UPSTOP:
begin
pos<=pos;
DoorFlag<=CLOSED;
UpDnFlag<=UPFLAG;
end
DOWNSTOP:
begin
pos<=pos;
DoorFlag<=CLOSED;
UpDnFlag<=DNFLAG;
end
OPENDOOR:
begin
pos<=pos;
DoorFlag<=OPEN;
UpDnFlag<=UpDnFlag;
end
CLOSEDOOR:
begin
pos<=pos;
DoorFlag<=CLOSED;
UpDnFlag<=UpDnFlag;
end
default:
begin
pos<=FLOOR1;
DoorFlag<=CLOSED;
UpDnFlag<=STATIC;
end
endcase
end
always @(posedge clk or posedge reset)
if(reset)
count<=0;
else if((NextState==OPENDOOR)&&(count<4))
count<=count+1;
else
count<=0;
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLXTP_FUNCTIONAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_ms__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_ms__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTP_FUNCTIONAL_V |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file GC_fifo.v when simulating
// the core, GC_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module GC_fifo(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
data_count
);
input clk;
input rst;
input [31 : 0] din;
input wr_en;
input rd_en;
output [31 : 0] dout;
output full;
output empty;
output [12 : 0] data_count;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(13),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(1),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("4kx9"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(4095),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(4094),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(13),
.C_RD_DEPTH(4096),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(12),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(13),
.C_WR_DEPTH(4096),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(12),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.RST(rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.DATA_COUNT(data_count),
.BACKUP(),
.BACKUP_MARKER(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
//altasmi_parallel CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DATA_WIDTH="STANDARD" DEVICE_FAMILY="Cyclone V" ENABLE_SIM="FALSE" EPCS_TYPE="EPCS128" PAGE_SIZE=1 PORT_BULK_ERASE="PORT_UNUSED" PORT_DIE_ERASE="PORT_UNUSED" PORT_EN4B_ADDR="PORT_UNUSED" PORT_EX4B_ADDR="PORT_UNUSED" PORT_FAST_READ="PORT_UNUSED" PORT_ILLEGAL_ERASE="PORT_UNUSED" PORT_ILLEGAL_WRITE="PORT_UNUSED" PORT_RDID_OUT="PORT_UNUSED" PORT_READ_ADDRESS="PORT_UNUSED" PORT_READ_DUMMYCLK="PORT_UNUSED" PORT_READ_RDID="PORT_UNUSED" PORT_READ_SID="PORT_UNUSED" PORT_READ_STATUS="PORT_UNUSED" PORT_SECTOR_ERASE="PORT_UNUSED" PORT_SECTOR_PROTECT="PORT_UNUSED" PORT_SHIFT_BYTES="PORT_UNUSED" PORT_WREN="PORT_UNUSED" PORT_WRITE="PORT_UNUSED" USE_ASMIBLOCK="ON" USE_EAB="ON" WRITE_DUMMY_CLK=0 addr busy clkin data_valid dataout rden read reset INTENDED_DEVICE_FAMILY="Cyclone V" ALTERA_INTERNAL_OPTIONS=SUPPRESS_DA_RULE_INTERNAL=C106
//VERSION_BEGIN 14.0 cbx_a_gray2bin 2014:06:05:09:45:41:SJ cbx_a_graycounter 2014:06:05:09:45:41:SJ cbx_altasmi_parallel 2014:06:05:09:45:41:SJ cbx_altdpram 2014:06:05:09:45:41:SJ cbx_altsyncram 2014:06:05:09:45:41:SJ cbx_arriav 2014:06:05:09:45:41:SJ cbx_cyclone 2014:06:05:09:45:41:SJ cbx_cycloneii 2014:06:05:09:45:41:SJ cbx_fifo_common 2014:06:05:09:45:41:SJ cbx_lpm_add_sub 2014:06:05:09:45:41:SJ cbx_lpm_compare 2014:06:05:09:45:41:SJ cbx_lpm_counter 2014:06:05:09:45:41:SJ cbx_lpm_decode 2014:06:05:09:45:41:SJ cbx_lpm_mux 2014:06:05:09:45:41:SJ cbx_mgl 2014:06:05:10:17:12:SJ cbx_nightfury 2014:06:05:09:45:41:SJ cbx_scfifo 2014:06:05:09:45:41:SJ cbx_stratix 2014:06:05:09:45:41:SJ cbx_stratixii 2014:06:05:09:45:41:SJ cbx_stratixiii 2014:06:05:09:45:41:SJ cbx_stratixv 2014:06:05:09:45:41:SJ cbx_util_mgl 2014:06:05:09:45:41:SJ cbx_zippleback 2014:06:17:19:05:45:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = a_graycounter 3 cyclonev_asmiblock 1 lut 6 mux21 1 reg 66
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C106"} *)
module asmi_asmi_parallel_0
(
addr,
busy,
clkin,
data_valid,
dataout,
rden,
read,
reset) /* synthesis synthesis_clearbox=1 */;
input [23:0] addr;
output busy;
input clkin;
output data_valid;
output [7:0] dataout;
input rden;
input read;
input reset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 read;
tri0 reset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [2:0] wire_addbyte_cntr_q;
wire [2:0] wire_gen_cntr_q;
wire [1:0] wire_stage_cntr_q;
wire wire_sd2_data1in;
reg add_msb_reg;
wire wire_add_msb_reg_ena;
wire [23:0] wire_addr_reg_d;
reg [23:0] addr_reg;
wire [23:0] wire_addr_reg_ena;
wire [7:0] wire_asmi_opcode_reg_d;
reg [7:0] asmi_opcode_reg;
wire [7:0] wire_asmi_opcode_reg_ena;
reg busy_det_reg;
reg clr_read_reg;
reg clr_read_reg2;
reg dffe3;
reg dvalid_reg;
wire wire_dvalid_reg_ena;
wire wire_dvalid_reg_sclr;
reg dvalid_reg2;
reg end1_cyc_reg;
reg end1_cyc_reg2;
reg end_op_hdlyreg;
reg end_op_reg;
reg end_rbyte_reg;
wire wire_end_rbyte_reg_ena;
wire wire_end_rbyte_reg_sclr;
reg end_read_reg;
reg ncs_reg;
wire wire_ncs_reg_sclr;
wire [7:0] wire_read_data_reg_d;
reg [7:0] read_data_reg;
wire [7:0] wire_read_data_reg_ena;
wire [7:0] wire_read_dout_reg_d;
reg [7:0] read_dout_reg;
wire [7:0] wire_read_dout_reg_ena;
reg read_reg;
wire wire_read_reg_ena;
reg shift_op_reg;
reg stage2_reg;
reg stage3_reg;
reg stage4_reg;
wire wire_mux211_dataout;
wire addr_overdie;
wire addr_overdie_pos;
wire [23:0] addr_reg_overdie;
wire [7:0] b4addr_opcode;
wire [7:0] berase_opcode;
wire busy_wire;
wire clkin_wire;
wire clr_addmsb_wire;
wire clr_endrbyte_wire;
wire clr_read_wire;
wire clr_read_wire2;
wire clr_rstat_wire;
wire clr_sid_wire;
wire clr_write_wire2;
wire data0out_wire;
wire data_valid_wire;
wire [3:0] dataoe_wire;
wire [3:0] dataout_wire;
wire [7:0] derase_opcode;
wire do_4baddr;
wire do_bulk_erase;
wire do_die_erase;
wire do_ex4baddr;
wire do_fast_read;
wire do_fread_epcq;
wire do_freadwrv_polling;
wire do_memadd;
wire do_polling;
wire do_read;
wire do_read_nonvolatile;
wire do_read_rdid;
wire do_read_sid;
wire do_read_stat;
wire do_read_volatile;
wire do_sec_erase;
wire do_sec_prot;
wire do_sprot_polling;
wire do_wait_dummyclk;
wire do_wren;
wire do_write;
wire do_write_polling;
wire do_write_volatile;
wire end1_cyc_gen_cntr_wire;
wire end1_cyc_normal_in_wire;
wire end1_cyc_reg_in_wire;
wire end_add_cycle;
wire end_add_cycle_mux_datab_wire;
wire end_fast_read;
wire end_one_cyc_pos;
wire end_one_cycle;
wire end_op_wire;
wire end_operation;
wire end_ophdly;
wire end_pgwr_data;
wire end_read;
wire end_read_byte;
wire [7:0] exb4addr_opcode;
wire [7:0] fast_read_opcode;
wire freadwrv_sdoin;
wire in_operation;
wire load_opcode;
wire memadd_sdoin;
wire ncs_reg_ena_wire;
wire not_busy;
wire oe_wire;
wire [0:0] pagewr_buf_not_empty;
wire rden_wire;
wire [7:0] rdid_opcode;
wire [7:0] rdummyclk_opcode;
wire [7:0] read_data_reg_in_wire;
wire [7:0] read_opcode;
wire read_rdid_wire;
wire read_sid_wire;
wire read_wire;
wire [7:0] rflagstat_opcode;
wire [7:0] rnvdummyclk_opcode;
wire [7:0] rsid_opcode;
wire rsid_sdoin;
wire [7:0] rstat_opcode;
wire scein_wire;
wire sdoin_wire;
wire sec_protect_wire;
wire [7:0] secprot_opcode;
wire secprot_sdoin;
wire [7:0] serase_opcode;
wire shift_opcode;
wire shift_opdata;
wire shift_pgwr_data;
wire st_busy_wire;
wire stage2_wire;
wire stage3_wire;
wire stage4_wire;
wire start_frpoll;
wire start_poll;
wire start_sppoll;
wire start_wrpoll;
wire to_sdoin_wire;
wire [7:0] wren_opcode;
wire wren_wire;
wire [7:0] write_opcode;
wire write_prot_true;
wire write_sdoin;
wire [7:0] wrvolatile_opcode;
a_graycounter addbyte_cntr
(
.aclr(reset),
.clk_en((((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & end_one_cyc_pos) & (((((((do_read_sid | do_write) | do_sec_erase) | do_die_erase) | do_read_rdid) | do_read) | do_fast_read) | do_read_nonvolatile)) | addr_overdie) | end_operation)),
.clock((~ clkin_wire)),
.q(wire_addbyte_cntr_q),
.qbin(),
.sclr((end_operation | addr_overdie))
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.cnt_en(1'b1),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addbyte_cntr.width = 3,
addbyte_cntr.lpm_type = "a_graycounter";
a_graycounter gen_cntr
(
.aclr(reset),
.clk_en((((((in_operation & (~ end_ophdly)) & (~ clr_rstat_wire)) & (~ clr_sid_wire)) | do_wait_dummyclk) | addr_overdie)),
.clock(clkin_wire),
.q(wire_gen_cntr_q),
.qbin(),
.sclr(((end1_cyc_reg_in_wire | addr_overdie) | do_wait_dummyclk))
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.cnt_en(1'b1),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
gen_cntr.width = 3,
gen_cntr.lpm_type = "a_graycounter";
a_graycounter stage_cntr
(
.aclr(reset),
.clk_en(((((((((((((((in_operation & end_one_cycle) & (~ (stage3_wire & (~ end_add_cycle)))) & (~ (stage4_wire & (~ end_read)))) & (~ (stage4_wire & (~ end_fast_read)))) & (~ ((((do_write | do_sec_erase) | do_die_erase) | do_bulk_erase) & write_prot_true))) & (~ (do_write & (~ pagewr_buf_not_empty[0])))) & (~ (stage3_wire & st_busy_wire))) & (~ ((do_write & shift_pgwr_data) & (~ end_pgwr_data)))) & (~ (stage2_wire & do_wren))) & (~ ((((stage3_wire & (do_sec_erase | do_die_erase)) & (~ do_wren)) & (~ do_read_stat)) & (~ do_read_rdid)))) & (~ (stage3_wire & ((do_write_volatile | do_read_volatile) | do_read_nonvolatile)))) | ((stage3_wire & do_fast_read) & do_wait_dummyclk)) | addr_overdie) | end_ophdly)),
.clock(clkin_wire),
.q(wire_stage_cntr_q),
.qbin(),
.sclr((end_operation | addr_overdie))
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.cnt_en(1'b1),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
stage_cntr.width = 2,
stage_cntr.lpm_type = "a_graycounter";
cyclonev_asmiblock sd2
(
.data0in(),
.data0oe(dataoe_wire[0]),
.data0out(sdoin_wire),
.data1in(wire_sd2_data1in),
.data1oe(dataoe_wire[1]),
.data2in(),
.data2oe(dataoe_wire[2]),
.data2out(1'b1),
.data3in(),
.data3oe(dataoe_wire[3]),
.data3out(1'b1),
.dclk(clkin_wire),
.oe(oe_wire),
.sce(scein_wire)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.data1out(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
sd2.enable_sim = "false",
sd2.lpm_type = "cyclonev_asmiblock";
// synopsys translate_off
initial
add_msb_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) add_msb_reg <= 1'b0;
else if (wire_add_msb_reg_ena == 1'b1)
if (clr_addmsb_wire == 1'b1) add_msb_reg <= 1'b0;
else add_msb_reg <= addr_reg[23];
assign
wire_add_msb_reg_ena = ((((((((do_read | do_fast_read) | do_write) | do_sec_erase) | do_die_erase) & (~ (((do_write | do_sec_erase) | do_die_erase) & (~ do_memadd)))) & wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) | clr_addmsb_wire);
// synopsys translate_off
initial
addr_reg[0:0] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[0:0] <= 1'b0;
else if (wire_addr_reg_ena[0:0] == 1'b1) addr_reg[0:0] <= wire_addr_reg_d[0:0];
// synopsys translate_off
initial
addr_reg[1:1] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[1:1] <= 1'b0;
else if (wire_addr_reg_ena[1:1] == 1'b1) addr_reg[1:1] <= wire_addr_reg_d[1:1];
// synopsys translate_off
initial
addr_reg[2:2] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[2:2] <= 1'b0;
else if (wire_addr_reg_ena[2:2] == 1'b1) addr_reg[2:2] <= wire_addr_reg_d[2:2];
// synopsys translate_off
initial
addr_reg[3:3] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[3:3] <= 1'b0;
else if (wire_addr_reg_ena[3:3] == 1'b1) addr_reg[3:3] <= wire_addr_reg_d[3:3];
// synopsys translate_off
initial
addr_reg[4:4] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[4:4] <= 1'b0;
else if (wire_addr_reg_ena[4:4] == 1'b1) addr_reg[4:4] <= wire_addr_reg_d[4:4];
// synopsys translate_off
initial
addr_reg[5:5] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[5:5] <= 1'b0;
else if (wire_addr_reg_ena[5:5] == 1'b1) addr_reg[5:5] <= wire_addr_reg_d[5:5];
// synopsys translate_off
initial
addr_reg[6:6] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[6:6] <= 1'b0;
else if (wire_addr_reg_ena[6:6] == 1'b1) addr_reg[6:6] <= wire_addr_reg_d[6:6];
// synopsys translate_off
initial
addr_reg[7:7] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[7:7] <= 1'b0;
else if (wire_addr_reg_ena[7:7] == 1'b1) addr_reg[7:7] <= wire_addr_reg_d[7:7];
// synopsys translate_off
initial
addr_reg[8:8] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[8:8] <= 1'b0;
else if (wire_addr_reg_ena[8:8] == 1'b1) addr_reg[8:8] <= wire_addr_reg_d[8:8];
// synopsys translate_off
initial
addr_reg[9:9] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[9:9] <= 1'b0;
else if (wire_addr_reg_ena[9:9] == 1'b1) addr_reg[9:9] <= wire_addr_reg_d[9:9];
// synopsys translate_off
initial
addr_reg[10:10] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[10:10] <= 1'b0;
else if (wire_addr_reg_ena[10:10] == 1'b1) addr_reg[10:10] <= wire_addr_reg_d[10:10];
// synopsys translate_off
initial
addr_reg[11:11] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[11:11] <= 1'b0;
else if (wire_addr_reg_ena[11:11] == 1'b1) addr_reg[11:11] <= wire_addr_reg_d[11:11];
// synopsys translate_off
initial
addr_reg[12:12] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[12:12] <= 1'b0;
else if (wire_addr_reg_ena[12:12] == 1'b1) addr_reg[12:12] <= wire_addr_reg_d[12:12];
// synopsys translate_off
initial
addr_reg[13:13] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[13:13] <= 1'b0;
else if (wire_addr_reg_ena[13:13] == 1'b1) addr_reg[13:13] <= wire_addr_reg_d[13:13];
// synopsys translate_off
initial
addr_reg[14:14] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[14:14] <= 1'b0;
else if (wire_addr_reg_ena[14:14] == 1'b1) addr_reg[14:14] <= wire_addr_reg_d[14:14];
// synopsys translate_off
initial
addr_reg[15:15] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[15:15] <= 1'b0;
else if (wire_addr_reg_ena[15:15] == 1'b1) addr_reg[15:15] <= wire_addr_reg_d[15:15];
// synopsys translate_off
initial
addr_reg[16:16] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[16:16] <= 1'b0;
else if (wire_addr_reg_ena[16:16] == 1'b1) addr_reg[16:16] <= wire_addr_reg_d[16:16];
// synopsys translate_off
initial
addr_reg[17:17] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[17:17] <= 1'b0;
else if (wire_addr_reg_ena[17:17] == 1'b1) addr_reg[17:17] <= wire_addr_reg_d[17:17];
// synopsys translate_off
initial
addr_reg[18:18] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[18:18] <= 1'b0;
else if (wire_addr_reg_ena[18:18] == 1'b1) addr_reg[18:18] <= wire_addr_reg_d[18:18];
// synopsys translate_off
initial
addr_reg[19:19] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[19:19] <= 1'b0;
else if (wire_addr_reg_ena[19:19] == 1'b1) addr_reg[19:19] <= wire_addr_reg_d[19:19];
// synopsys translate_off
initial
addr_reg[20:20] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[20:20] <= 1'b0;
else if (wire_addr_reg_ena[20:20] == 1'b1) addr_reg[20:20] <= wire_addr_reg_d[20:20];
// synopsys translate_off
initial
addr_reg[21:21] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[21:21] <= 1'b0;
else if (wire_addr_reg_ena[21:21] == 1'b1) addr_reg[21:21] <= wire_addr_reg_d[21:21];
// synopsys translate_off
initial
addr_reg[22:22] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[22:22] <= 1'b0;
else if (wire_addr_reg_ena[22:22] == 1'b1) addr_reg[22:22] <= wire_addr_reg_d[22:22];
// synopsys translate_off
initial
addr_reg[23:23] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[23:23] <= 1'b0;
else if (wire_addr_reg_ena[23:23] == 1'b1) addr_reg[23:23] <= wire_addr_reg_d[23:23];
assign
wire_addr_reg_d = {((({23{not_busy}} & addr[23:1]) | ({23{stage3_wire}} & addr_reg[22:0])) | ({23{addr_overdie}} & addr_reg_overdie[23:1])), ((not_busy & addr[0]) | (addr_overdie & addr_reg_overdie[0]))};
assign
wire_addr_reg_ena = {24{((((rden_wire | wren_wire) & not_busy) | (stage4_wire & addr_overdie)) | (stage3_wire & ((((do_write | do_sec_erase) | do_die_erase) & do_memadd) | (do_read | do_fast_read))))}};
// synopsys translate_off
initial
asmi_opcode_reg[0:0] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[0:0] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[0:0] == 1'b1) asmi_opcode_reg[0:0] <= wire_asmi_opcode_reg_d[0:0];
// synopsys translate_off
initial
asmi_opcode_reg[1:1] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[1:1] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[1:1] == 1'b1) asmi_opcode_reg[1:1] <= wire_asmi_opcode_reg_d[1:1];
// synopsys translate_off
initial
asmi_opcode_reg[2:2] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[2:2] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[2:2] == 1'b1) asmi_opcode_reg[2:2] <= wire_asmi_opcode_reg_d[2:2];
// synopsys translate_off
initial
asmi_opcode_reg[3:3] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[3:3] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[3:3] == 1'b1) asmi_opcode_reg[3:3] <= wire_asmi_opcode_reg_d[3:3];
// synopsys translate_off
initial
asmi_opcode_reg[4:4] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[4:4] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[4:4] == 1'b1) asmi_opcode_reg[4:4] <= wire_asmi_opcode_reg_d[4:4];
// synopsys translate_off
initial
asmi_opcode_reg[5:5] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[5:5] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[5:5] == 1'b1) asmi_opcode_reg[5:5] <= wire_asmi_opcode_reg_d[5:5];
// synopsys translate_off
initial
asmi_opcode_reg[6:6] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[6:6] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[6:6] == 1'b1) asmi_opcode_reg[6:6] <= wire_asmi_opcode_reg_d[6:6];
// synopsys translate_off
initial
asmi_opcode_reg[7:7] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[7:7] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[7:7] == 1'b1) asmi_opcode_reg[7:7] <= wire_asmi_opcode_reg_d[7:7];
assign
wire_asmi_opcode_reg_d = {(((((((((((((((((({7{(load_opcode & do_read_sid)}} & rsid_opcode[7:1]) | ({7{(load_opcode & do_read_rdid)}} & rdid_opcode[7:1])) | ({7{(((load_opcode & do_sec_prot) & (~ do_wren)) & (~ do_read_stat))}} & secprot_opcode[7:1])) | ({7{(load_opcode & do_read)}} & read_opcode[7:1])) | ({7{(load_opcode & do_fast_read)}} & fast_read_opcode[7:1])) | ({7{((((load_opcode & do_read_volatile) & (~ do_write_volatile)) & (~ do_wren)) & (~ do_read_stat))}} & rdummyclk_opcode[7:1])) | ({7{((((load_opcode & do_write_volatile) & (~ do_read_volatile)) & (~ do_wren)) & (~ do_read_stat))}} & wrvolatile_opcode[7:1])) | ({7{(load_opcode & do_read_nonvolatile)}} & rnvdummyclk_opcode[7:1])) | ({7{(load_opcode & ((do_write & (~ do_read_stat)) & (~ do_wren)))}} & write_opcode[7:1])) | ({7{((load_opcode & do_read_stat) & (~ do_polling))}} & rstat_opcode[7:1])) | ({7{((load_opcode & do_read_stat) & do_polling)}} & rflagstat_opcode[7:1])) | ({7{(((load_opcode & do_sec_erase) & (~ do_wren)) & (~ do_read_stat))}} & serase_opcode[7:1])) | ({7{(((load_opcode & do_die_erase) & (~ do_wren)) & (~ do_read_stat))}} & derase_opcode[7:1])) | ({7{(((load_opcode & do_bulk_erase) & (~ do_wren)) & (~ do_read_stat))}} & berase_opcode[7:1])) | ({7{(load_opcode & do_wren)}} & wren_opcode[7:1])) | ({7{(load_opcode & ((do_4baddr & (~ do_read_stat)) & (~ do_wren)))}} & b4addr_opcode[7:1])) | ({7{(load_opcode & ((do_ex4baddr & (~ do_read_stat)) & (~ do_wren)))}} & exb4addr_opcode[7:1])) | ({7{shift_opcode}} & asmi_opcode_reg[6:0])), ((((((((((((((((((load_opcode & do_read_sid) & rsid_opcode[0]) | ((load_opcode & do_read_rdid) & rdid_opcode[0])) | ((((load_opcode & do_sec_prot) & (~ do_wren)) & (~ do_read_stat)) & secprot_opcode[0])) | ((load_opcode & do_read) & read_opcode[0])) | ((load_opcode & do_fast_read) & fast_read_opcode[0])) | (((((load_opcode & do_read_volatile) & (~ do_write_volatile)) & (~ do_wren)) & (~ do_read_stat)) & rdummyclk_opcode[0])) | (((((load_opcode & do_write_volatile) & (~ do_read_volatile)) & (~ do_wren)) & (~ do_read_stat
)) & wrvolatile_opcode[0])) | ((load_opcode & do_read_nonvolatile) & rnvdummyclk_opcode[0])) | ((load_opcode & ((do_write & (~ do_read_stat)) & (~ do_wren))) & write_opcode[0])) | (((load_opcode & do_read_stat) & (~ do_polling)) & rstat_opcode[0])) | (((load_opcode & do_read_stat) & do_polling) & rflagstat_opcode[0])) | ((((load_opcode & do_sec_erase) & (~ do_wren)) & (~ do_read_stat)) & serase_opcode[0])) | ((((load_opcode & do_die_erase) & (~ do_wren)) & (~ do_read_stat)) & derase_opcode[0])) | ((((load_opcode & do_bulk_erase) & (~ do_wren)) & (~ do_read_stat)) & berase_opcode[0])) | ((load_opcode & do_wren) & wren_opcode[0])) | ((load_opcode & ((do_4baddr & (~ do_read_stat)) & (~ do_wren))) & b4addr_opcode[0])) | ((load_opcode & ((do_ex4baddr & (~ do_read_stat)) & (~ do_wren))) & exb4addr_opcode[0]))};
assign
wire_asmi_opcode_reg_ena = {8{(load_opcode | shift_opcode)}};
// synopsys translate_off
initial
busy_det_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) busy_det_reg <= 1'b0;
else busy_det_reg <= (~ busy_wire);
// synopsys translate_off
initial
clr_read_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) clr_read_reg <= 1'b0;
else clr_read_reg <= ((do_read_sid | do_sec_prot) | end_operation);
// synopsys translate_off
initial
clr_read_reg2 = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) clr_read_reg2 <= 1'b0;
else clr_read_reg2 <= clr_read_reg;
// synopsys translate_off
initial
dffe3 = 0;
// synopsys translate_on
// synopsys translate_off
initial
dvalid_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) dvalid_reg <= 1'b0;
else if (wire_dvalid_reg_ena == 1'b1)
if (wire_dvalid_reg_sclr == 1'b1) dvalid_reg <= 1'b0;
else dvalid_reg <= (end_read_byte & end_one_cyc_pos);
assign
wire_dvalid_reg_ena = (do_read | do_fast_read),
wire_dvalid_reg_sclr = (end_op_wire | end_operation);
// synopsys translate_off
initial
dvalid_reg2 = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) dvalid_reg2 <= 1'b0;
else dvalid_reg2 <= dvalid_reg;
// synopsys translate_off
initial
end1_cyc_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) end1_cyc_reg <= 1'b0;
else end1_cyc_reg <= end1_cyc_reg_in_wire;
// synopsys translate_off
initial
end1_cyc_reg2 = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) end1_cyc_reg2 <= 1'b0;
else end1_cyc_reg2 <= end_one_cycle;
// synopsys translate_off
initial
end_op_hdlyreg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) end_op_hdlyreg <= 1'b0;
else end_op_hdlyreg <= end_operation;
// synopsys translate_off
initial
end_op_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) end_op_reg <= 1'b0;
else end_op_reg <= end_op_wire;
// synopsys translate_off
initial
end_rbyte_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) end_rbyte_reg <= 1'b0;
else if (wire_end_rbyte_reg_ena == 1'b1)
if (wire_end_rbyte_reg_sclr == 1'b1) end_rbyte_reg <= 1'b0;
else end_rbyte_reg <= (((do_read | do_fast_read) & wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0]));
assign
wire_end_rbyte_reg_ena = (((wire_gen_cntr_q[2] & (~ wire_gen_cntr_q[1])) & wire_gen_cntr_q[0]) | clr_endrbyte_wire),
wire_end_rbyte_reg_sclr = (clr_endrbyte_wire | addr_overdie);
// synopsys translate_off
initial
end_read_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) end_read_reg <= 1'b0;
else end_read_reg <= ((((~ rden_wire) & (do_read | do_fast_read)) & data_valid_wire) & end_read_byte);
// synopsys translate_off
initial
ncs_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) ncs_reg <= 1'b0;
else if (ncs_reg_ena_wire == 1'b1)
if (wire_ncs_reg_sclr == 1'b1) ncs_reg <= 1'b0;
else ncs_reg <= 1'b1;
assign
wire_ncs_reg_sclr = (end_operation | addr_overdie_pos);
// synopsys translate_off
initial
read_data_reg[0:0] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[0:0] <= 1'b0;
else if (wire_read_data_reg_ena[0:0] == 1'b1) read_data_reg[0:0] <= wire_read_data_reg_d[0:0];
// synopsys translate_off
initial
read_data_reg[1:1] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[1:1] <= 1'b0;
else if (wire_read_data_reg_ena[1:1] == 1'b1) read_data_reg[1:1] <= wire_read_data_reg_d[1:1];
// synopsys translate_off
initial
read_data_reg[2:2] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[2:2] <= 1'b0;
else if (wire_read_data_reg_ena[2:2] == 1'b1) read_data_reg[2:2] <= wire_read_data_reg_d[2:2];
// synopsys translate_off
initial
read_data_reg[3:3] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[3:3] <= 1'b0;
else if (wire_read_data_reg_ena[3:3] == 1'b1) read_data_reg[3:3] <= wire_read_data_reg_d[3:3];
// synopsys translate_off
initial
read_data_reg[4:4] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[4:4] <= 1'b0;
else if (wire_read_data_reg_ena[4:4] == 1'b1) read_data_reg[4:4] <= wire_read_data_reg_d[4:4];
// synopsys translate_off
initial
read_data_reg[5:5] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[5:5] <= 1'b0;
else if (wire_read_data_reg_ena[5:5] == 1'b1) read_data_reg[5:5] <= wire_read_data_reg_d[5:5];
// synopsys translate_off
initial
read_data_reg[6:6] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[6:6] <= 1'b0;
else if (wire_read_data_reg_ena[6:6] == 1'b1) read_data_reg[6:6] <= wire_read_data_reg_d[6:6];
// synopsys translate_off
initial
read_data_reg[7:7] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[7:7] <= 1'b0;
else if (wire_read_data_reg_ena[7:7] == 1'b1) read_data_reg[7:7] <= wire_read_data_reg_d[7:7];
assign
wire_read_data_reg_d = {read_data_reg_in_wire[7:0]};
assign
wire_read_data_reg_ena = {8{(((((do_read | do_fast_read) & wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0])) & end_one_cyc_pos) & end_read_byte)}};
// synopsys translate_off
initial
read_dout_reg[0:0] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[0:0] <= 1'b0;
else if (wire_read_dout_reg_ena[0:0] == 1'b1) read_dout_reg[0:0] <= wire_read_dout_reg_d[0:0];
// synopsys translate_off
initial
read_dout_reg[1:1] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[1:1] <= 1'b0;
else if (wire_read_dout_reg_ena[1:1] == 1'b1) read_dout_reg[1:1] <= wire_read_dout_reg_d[1:1];
// synopsys translate_off
initial
read_dout_reg[2:2] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[2:2] <= 1'b0;
else if (wire_read_dout_reg_ena[2:2] == 1'b1) read_dout_reg[2:2] <= wire_read_dout_reg_d[2:2];
// synopsys translate_off
initial
read_dout_reg[3:3] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[3:3] <= 1'b0;
else if (wire_read_dout_reg_ena[3:3] == 1'b1) read_dout_reg[3:3] <= wire_read_dout_reg_d[3:3];
// synopsys translate_off
initial
read_dout_reg[4:4] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[4:4] <= 1'b0;
else if (wire_read_dout_reg_ena[4:4] == 1'b1) read_dout_reg[4:4] <= wire_read_dout_reg_d[4:4];
// synopsys translate_off
initial
read_dout_reg[5:5] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[5:5] <= 1'b0;
else if (wire_read_dout_reg_ena[5:5] == 1'b1) read_dout_reg[5:5] <= wire_read_dout_reg_d[5:5];
// synopsys translate_off
initial
read_dout_reg[6:6] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[6:6] <= 1'b0;
else if (wire_read_dout_reg_ena[6:6] == 1'b1) read_dout_reg[6:6] <= wire_read_dout_reg_d[6:6];
// synopsys translate_off
initial
read_dout_reg[7:7] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[7:7] <= 1'b0;
else if (wire_read_dout_reg_ena[7:7] == 1'b1) read_dout_reg[7:7] <= wire_read_dout_reg_d[7:7];
assign
wire_read_dout_reg_d = {read_dout_reg[6:0], (data0out_wire | dataout_wire[1])};
assign
wire_read_dout_reg_ena = {8{((stage4_wire & ((do_read | do_fast_read) | do_read_sid)) | (stage3_wire & (((do_read_stat | do_read_rdid) | do_read_volatile) | do_read_nonvolatile)))}};
// synopsys translate_off
initial
read_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_reg <= 1'b0;
else if (wire_read_reg_ena == 1'b1)
if (clr_read_wire == 1'b1) read_reg <= 1'b0;
else read_reg <= read;
assign
wire_read_reg_ena = (((~ busy_wire) & rden_wire) | clr_read_wire);
// synopsys translate_off
initial
shift_op_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) shift_op_reg <= 1'b0;
else shift_op_reg <= ((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]);
// synopsys translate_off
initial
stage2_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) stage2_reg <= 1'b0;
else stage2_reg <= ((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]);
// synopsys translate_off
initial
stage3_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) stage3_reg <= 1'b0;
else stage3_reg <= (wire_stage_cntr_q[1] & wire_stage_cntr_q[0]);
// synopsys translate_off
initial
stage4_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) stage4_reg <= 1'b0;
else stage4_reg <= (wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0]));
assign wire_mux211_dataout = (do_fast_read === 1'b1) ? end_add_cycle_mux_datab_wire : (wire_addbyte_cntr_q[1] & (~ wire_addbyte_cntr_q[0]));
assign
addr_overdie = 1'b0,
addr_overdie_pos = 1'b0,
addr_reg_overdie = {24{1'b0}},
b4addr_opcode = {8{1'b0}},
berase_opcode = {8{1'b0}},
busy = busy_wire,
busy_wire = ((((((((((((((do_read_rdid | do_read_sid) | do_read) | do_fast_read) | do_write) | do_sec_prot) | do_read_stat) | do_sec_erase) | do_bulk_erase) | do_die_erase) | do_4baddr) | do_read_volatile) | do_fread_epcq) | do_read_nonvolatile) | do_ex4baddr),
clkin_wire = clkin,
clr_addmsb_wire = (((((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) & end_add_cycle) & end_one_cyc_pos) | (((~ do_read) & (~ do_fast_read)) & clr_write_wire2)) | ((((do_sec_erase | do_die_erase) & (~ do_wren)) & (~ do_read_stat)) & end_operation)),
clr_endrbyte_wire = (((((do_read | do_fast_read) & (~ wire_gen_cntr_q[2])) & wire_gen_cntr_q[1]) & wire_gen_cntr_q[0]) | clr_read_wire2),
clr_read_wire = clr_read_reg,
clr_read_wire2 = clr_read_reg2,
clr_rstat_wire = 1'b0,
clr_sid_wire = 1'b0,
clr_write_wire2 = 1'b0,
data0out_wire = wire_sd2_data1in,
data_valid = data_valid_wire,
data_valid_wire = dvalid_reg2,
dataoe_wire = {{2{1'b1}}, 1'b0, 1'b1},
dataout = {read_data_reg[7:0]},
dataout_wire = {{4{1'b0}}},
derase_opcode = {8{1'b0}},
do_4baddr = 1'b0,
do_bulk_erase = 1'b0,
do_die_erase = 1'b0,
do_ex4baddr = 1'b0,
do_fast_read = 1'b0,
do_fread_epcq = 1'b0,
do_freadwrv_polling = 1'b0,
do_memadd = 1'b0,
do_polling = ((do_write_polling | do_sprot_polling) | do_freadwrv_polling),
do_read = ((((~ read_rdid_wire) & (~ read_sid_wire)) & (~ sec_protect_wire)) & read_wire),
do_read_nonvolatile = 1'b0,
do_read_rdid = 1'b0,
do_read_sid = 1'b0,
do_read_stat = 1'b0,
do_read_volatile = 1'b0,
do_sec_erase = 1'b0,
do_sec_prot = 1'b0,
do_sprot_polling = 1'b0,
do_wait_dummyclk = 1'b0,
do_wren = 1'b0,
do_write = 1'b0,
do_write_polling = 1'b0,
do_write_volatile = 1'b0,
end1_cyc_gen_cntr_wire = ((wire_gen_cntr_q[2] & (~ wire_gen_cntr_q[1])) & (~ wire_gen_cntr_q[0])),
end1_cyc_normal_in_wire = ((((((((((((~ wire_stage_cntr_q[0]) & (~ wire_stage_cntr_q[1])) & (~ wire_gen_cntr_q[2])) & wire_gen_cntr_q[1]) & wire_gen_cntr_q[0]) | ((~ ((~ wire_stage_cntr_q[0]) & (~ wire_stage_cntr_q[1]))) & end1_cyc_gen_cntr_wire)) | (do_read & end_read)) | (do_fast_read & end_fast_read)) | ((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) & write_prot_true)) | (do_write & (~ pagewr_buf_not_empty[0]))) | ((do_read_stat & start_poll) & (~ st_busy_wire))) | (do_read_rdid & end_op_wire)),
end1_cyc_reg_in_wire = end1_cyc_normal_in_wire,
end_add_cycle = wire_mux211_dataout,
end_add_cycle_mux_datab_wire = (wire_addbyte_cntr_q[2] & wire_addbyte_cntr_q[1]),
end_fast_read = end_read_reg,
end_one_cyc_pos = end1_cyc_reg2,
end_one_cycle = end1_cyc_reg,
end_op_wire = ((((((((((((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) & ((((((~ do_read) & (~ do_fast_read)) & (~ (do_write & shift_pgwr_data))) & end_one_cycle) | (do_read & end_read)) | (do_fast_read & end_fast_read))) | ((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & do_read_stat) & end_one_cycle) & (~ do_polling))) | ((((((do_read_rdid & end_one_cyc_pos) & wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & wire_addbyte_cntr_q[2]) & wire_addbyte_cntr_q[1]) & (~ wire_addbyte_cntr_q[0]))) | (((start_poll & do_read_stat) & do_polling) & (~ st_busy_wire))) | ((((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & (do_wren | (do_4baddr | (do_ex4baddr | (do_bulk_erase & (~ do_read_stat)))))) & end_one_cycle)) | ((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) & write_prot_true)) | ((do_write & shift_pgwr_data) & end_pgwr_data)) | (do_write & (~ pagewr_buf_not_empty[0]))) | (((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & do_sec_prot) & (~ do_wren)) & (~ do_read_stat)) & end_one_cycle)) | ((((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & (do_sec_erase | do_die_erase)) & (~ do_wren)) & (~ do_read_stat)) & end_add_cycle) & end_one_cycle)) | (((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & end_one_cycle) & ((do_write_volatile | do_read_volatile) | (do_read_nonvolatile & wire_addbyte_cntr_q[1])))),
end_operation = end_op_reg,
end_ophdly = end_op_hdlyreg,
end_pgwr_data = 1'b0,
end_read = end_read_reg,
end_read_byte = (end_rbyte_reg & (~ addr_overdie)),
exb4addr_opcode = {8{1'b0}},
fast_read_opcode = {8{1'b0}},
freadwrv_sdoin = 1'b0,
in_operation = busy_wire,
load_opcode = (((((~ wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0])) & (~ wire_gen_cntr_q[2])) & (~ wire_gen_cntr_q[1])) & wire_gen_cntr_q[0]),
memadd_sdoin = add_msb_reg,
ncs_reg_ena_wire = (((((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & end_one_cyc_pos) | addr_overdie_pos) | end_operation),
not_busy = busy_det_reg,
oe_wire = 1'b0,
pagewr_buf_not_empty = {1'b1},
rden_wire = rden,
rdid_opcode = {8{1'b0}},
rdummyclk_opcode = {8{1'b0}},
read_data_reg_in_wire = {read_dout_reg[7:0]},
read_opcode = 8'b00000011,
read_rdid_wire = 1'b0,
read_sid_wire = 1'b0,
read_wire = read_reg,
rflagstat_opcode = {8{1'b0}},
rnvdummyclk_opcode = {8{1'b0}},
rsid_opcode = {8{1'b0}},
rsid_sdoin = 1'b0,
rstat_opcode = {8{1'b0}},
scein_wire = (~ ncs_reg),
sdoin_wire = to_sdoin_wire,
sec_protect_wire = 1'b0,
secprot_opcode = {8{1'b0}},
secprot_sdoin = 1'b0,
serase_opcode = {8{1'b0}},
shift_opcode = shift_op_reg,
shift_opdata = stage2_wire,
shift_pgwr_data = 1'b0,
st_busy_wire = 1'b0,
stage2_wire = stage2_reg,
stage3_wire = stage3_reg,
stage4_wire = stage4_reg,
start_frpoll = 1'b0,
start_poll = ((start_wrpoll | start_sppoll) | start_frpoll),
start_sppoll = 1'b0,
start_wrpoll = 1'b0,
to_sdoin_wire = ((((((shift_opdata & asmi_opcode_reg[7]) | rsid_sdoin) | memadd_sdoin) | write_sdoin) | secprot_sdoin) | freadwrv_sdoin),
wren_opcode = {8{1'b0}},
wren_wire = 1'b1,
write_opcode = {8{1'b0}},
write_prot_true = 1'b0,
write_sdoin = 1'b0,
wrvolatile_opcode = {8{1'b0}};
endmodule //asmi_asmi_parallel_0
//VALID FILE
|
`timescale 1ns / 1ps
module ym09(
input wire clk50,
input wire ext_rst,
// UART pins
input wire uart_rx,
output wire uart_tx,
// YM2151 pins
inout wire [7:0] ym_d,
output wire ym_a0,
output wire ym_wr_n,
output wire ym_rd_n,
output wire ym_cs_n,
output wire ym_ic_n,
input wire ym_irq_n,
input wire ym_ct1,
input wire ym_ct2,
input wire ym_so,
input wire ym_sh1,
input wire ym_sh2,
output wire ym_pm, // system clock
input wire ym_p1, // DAC clock
// level shifters
output wire DIR, // 0 means FPGA writes on YM, 1 means FPGA reads from YM
// LED control
output reg [7:0] led,
input wire [2:0] ledcfg,
input wire uart_speed,
input wire dump_memory
);
/* historial de versiones
6 Separado el estado de la UART de rx y tx en dos posiciones de memoria distintos
9 RAM ampliada a 32 kB. Esta version no sintetizaba a 50MHz.
10 Volcado de memoria por la UART. Esta version no sintetizaba a 50MHz.
11 Control de la velocidad del YM2151 para poder bajarla durante el volcado directo.
12 La velocidad lenta del YM es aun mas lenta.
13 Añade la lectura del audio en formato exponencial directamente por la CPU
14 Añade lectura de datos YM sincronizados con ym_p1
15 Añade el JT51
16 Actualiza el JT51 y trata de medir el OP31
*/
parameter version_number = 8'd16;
wire [15:0] cpu_addr;
wire [ 7:0] cpu_data_i, cpu_data_o, memory_data_o;
wire cpu_rw, cpu_vma;
wire ram_cs;
wire [7:0] uart_rx_byte, uart_tx_byte, uart_error_count;
wire uart_transmit, uart_received;
wire uart_irq, uart_irq_clear;
wire [2:0] uart_status;
wire [ 7:0] led09, led09_alt, fsm_led;
wire [11:0] fsm_addr;
wire fsm_wr;
wire cpu_rst;
wire [15:0] jt51_left, jt51_right;
wire [7:0] jt51_do;
wire jt51_ct1, jt51_ct2, jt51_irq_n, jt51_sh1, jt51_sh2;
wire rst;
always @(*) begin
case( ledcfg )
default: led <= cpu_rst ? fsm_led : led09;
3'b000: led <= { ym_ic_n, 3'd0, ym_cs_n, ym_wr_n, ym_rd_n, ym_a0 };
3'b001: led <= { ym_irq_n, ym_ct2, ym_ct1, ym_pm,
ym_p1, ym_sh2, ym_sh1, ym_so };
3'b010: led <= fsm_addr[ 7:0];
3'b011: led <= { 4'h0, fsm_addr[11:8] };
3'b100: led <= cpu_rst ? fsm_led : led09;
3'b101: led <= cpu_rst ? fsm_led : led09_alt;
3'b110: led <= { uart_irq, 3'b0, 1'b0, uart_status };
3'b111: led <= version_number;
endcase
end
pll u_pll (
.CLKIN_IN(clk50),
.CLKFX_OUT(clk) // 16.67 MHz
//.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),
//.CLK0_OUT(CLK0_OUT),
//.LOCKED_OUT(LOCKED_OUT)
);
fpga_reset u_rst(
.clk ( clk ),
.ext_rst( ext_rst ),
.rst ( rst )
);
wire dump_memory_sync;
debouncer u_debouncer(
.clk ( clk ),
.rst ( rst ),
.PB ( dump_memory ), // "PB" is the glitchy, asynchronous to clk, active low push-button signal
.PB_up ( dump_memory_sync ) // 1 for one clock cycle when the push-button goes up (i.e. just released)
);
system_bus #(version_number) u_bus(
.clk ( clk ),
.rst ( rst ),
.cpu_data_i ( cpu_data_i ),
.cpu_data_o ( cpu_data_o ),
.cpu_rw ( cpu_rw ),
.cpu_vma ( cpu_vma ),
.memory_data_o ( memory_data_o ),
.address ( cpu_addr ),
.ram_cs ( ram_cs ),
// UART
.uart_rx_byte ( uart_rx_byte ),
.uart_transmit ( uart_transmit ),
.uart_tx_byte ( uart_tx_byte ),
.rx_status ( rx_status ), // IRQ handling
.tx_status ( tx_status ),
.rx_status_clear( rx_status_clear),
.tx_status_clear( tx_status_clear),
.uart_speed ( uart_speed ),
// YM2151 pins
.ym_d ( ym_d ),
.ym_a0 ( ym_a0 ),
.ym_wr_n ( ym_wr_n ),
.ym_rd_n ( ym_rd_n ),
.ym_cs_n ( ym_cs_n ),
.ym_ic_n ( ym_ic_n ),
.ym_irq_n ( ym_irq_n ),
.ym_ct1 ( ym_ct1 ),
.ym_ct2 ( ym_ct2 ),
.ym_so ( ym_so ),
.ym_sh1 ( ym_sh1 ),
.ym_sh2 ( ym_sh2 ),
.ym_pm ( ym_pm ),
.ym_p1 ( ym_p1 ),
// JT51 pins
.jt51_cs_n ( jt51_cs_n ),
.jt51_left ( jt51_left ),
.jt51_right ( jt51_right ),
.jt51_do ( jt51_do ),
.jt51_ct1 ( jt51_ct1 ),
.jt51_ct2 ( jt51_ct2 ),
.jt51_irq_n ( jt51_irq_n ),
.jt51_sh1 ( jt51_sh1 ),
.jt51_sh2 ( jt51_sh2 ),
// level shifters
.dir ( DIR ), // 0 means FPGA writes on YM, 1 means FPGA reads from YM
// LED
.led ( led09 ),
.led_alt ( led09_alt )
);
memory #(15)u_memory(
.datain ( fsm_wr ? uart_rx_byte : cpu_data_o ),
.dataout( memory_data_o ),
.clk ( clk ),
.addr ( cpu_rst ? {3'b111, fsm_addr} : cpu_addr[14:0] ),
.en ( cpu_rst | ram_cs ),
.we ( cpu_rst ? fsm_wr : ~cpu_rw ) // high for write, low for read
);
uart09 #(12)u_uart(
.clk ( clk ),
.rst ( rst ),
.uart_rx ( uart_rx ),
.uart_tx ( uart_tx ),
.uart_rx_byte ( uart_rx_byte ),
.uart_transmit ( uart_transmit ),
.uart_tx_byte ( uart_tx_byte ),
.mem_data_o ( memory_data_o ),
.uart_error_count( uart_error_count ),
.uart_received ( uart_received ),
.uart_speed ( uart_speed ),
// IRQ handling
.rx_status ( rx_status ),
.tx_status ( tx_status ),
.rx_status_clear( rx_status_clear ),
.tx_status_clear( tx_status_clear ),
// control RAM load
.fsm_addr ( fsm_addr ),
.fsm_wr ( fsm_wr ),
.cpu_rst ( cpu_rst ),
.led ( fsm_led ),
.dump_memory ( dump_memory_sync )
);
//wire [15:0] pc_out;
cpu09 cpu(
.clk ( clk ),
.rst ( cpu_rst ),
.rw ( cpu_rw ),
.vma ( cpu_vma ),
.address ( cpu_addr ),
.data_in ( cpu_data_i ),
.data_out( cpu_data_o ),
.halt ( 1'b0 ),
.hold ( 1'b0 ),
.irq ( rx_status ),
.firq ( 1'b0 ),
.nmi ( 1'b0 ),
.pc_out ( )
);
jt51 u_jt51(
.clk ( ~clk ), // main clock
.rst ( cpu_rst ), // reset
.cs_n ( jt51_cs_n ), // chip select
.wr_n ( ~cpu_rw ), // write
.a0 ( cpu_addr[0] ),
.d_in ( cpu_data_o), // data in
.d_out ( jt51_do ), // data out
.ct1 ( jt51_ct1 ),
.ct2 ( jt51_ct2 ),
.irq_n ( jt51_irq_n),
.left ( jt51_left ),
.right ( jt51_right)
);
endmodule
|
module spmc_timestamp_counter #(
parameter CLOCK_FREQUENCY = 16000000, //input clock frequency
parameter BASE_ADR = 10'h0) (
//*** Connections to SpartanMC Core (do not change) ***
input wire clk_peri, //System-Clock
input wire [17:0] do_peri, //Data Bus from MC
output wire [17:0] di_peri, //Data Bus to MC
input wire [9:0] addr_peri, //Address Bus from MC
input wire access_peri, //Peripheral Access Signal
input wire wr_peri, //Write Enable Signal
//*** Connections to SpartanMC Core which can be changed ***
input wire reset, //Reset-Signal (could be external)
//*** timestamp counter output ***
output reg [35:0] lpt_counter, //low precision counter input
output reg [35:0] hpt_counter //high precision counter input
);
//register addresses of the module
parameter LPT_LOW = 2'b00; //low precision timestamp low register
parameter LPT_HIGH = 2'b01; //low precision timestamp high register
parameter HPT_LOW = 2'b10; //high precision timestamp low register
parameter HPT_HIGH = 2'b11; //high precision timestamp high register
wire select;
// Address decoder generates the select sinal out of the upper part of the peripheral address.
pselect iCSL (
.addr ( addr_peri[9:2] ),
.activ_peri ( access_peri ),
.select ( select )
);
defparam iCSL.ADDR_WIDTH = 8;
defparam iCSL.BASE_WIDTH = 8;
defparam iCSL.BASE_ADDR = BASE_ADR >> 2; //BASE_ADR has to be divisible by 4
//counter write register
reg [35:0] lpt_counter_write;
reg [35:0] hpt_counter_write;
reg counter_write_req;
//SpartanMC peripheral interface read logic -> no read
assign di_peri = 18'b0;
//SpartanMC peripheral interface write logic
always @(posedge clk_peri) begin
if (reset) begin
counter_write_req <= 1'b0;
end else begin
if (select & wr_peri) begin
case (addr_peri[1:0])
LPT_LOW: lpt_counter_write[17:0] = do_peri[17:0];
LPT_HIGH: lpt_counter_write[35:18] = do_peri[17:0];
HPT_LOW: hpt_counter_write[17:0] = do_peri[17:0];
HPT_HIGH: begin
hpt_counter_write[35:18] = do_peri[17:0];
counter_write_req <= 1'b1;
end
endcase
end else begin
counter_write_req <= 1'b0;
end
end
end
//counter logic
always @(posedge clk_peri) begin
if (reset) begin
hpt_counter <= 18'd0; //reset counters to 0
lpt_counter <= 18'd0;
end else begin
if (counter_write_req == 1'b1)begin
hpt_counter <= hpt_counter_write;
lpt_counter <= lpt_counter_write;
end else begin
if (hpt_counter == CLOCK_FREQUENCY-1) begin
hpt_counter <= 18'd0; //reset high precision counter if max value reached
lpt_counter <= lpt_counter + 1; //increment low precision counter
end else
hpt_counter <= hpt_counter + 1; //otherwise increment high precision counter
end
end
end
endmodule
|
(** * ProofObjects: Working with Explicit Evidence in Coq *)
Require Export MoreLogic.
(* ##################################################### *)
(** We have seen that Coq has mechanisms both for _programming_,
using inductive data types (like [nat] or [list]) and functions
over these types, and for _proving_ properties of these programs,
using inductive propositions (like [ev] or [eq]), implication, and
universal quantification. So far, we have treated these mechanisms
as if they were quite separate, and for many purposes this is
a good way to think. But we have also seen hints that Coq's programming and
proving facilities are closely related. For example, the
keyword [Inductive] is used to declare both data types and
propositions, and [->] is used both to describe the type of
functions on data and logical implication. This is not just a
syntactic accident! In fact, programs and proofs in Coq are almost
the same thing. In this chapter we will study how this works.
We have already seen the fundamental idea: provability in Coq is
represented by concrete _evidence_. When we construct the proof
of a basic proposition, we are actually building a tree of evidence,
which can be thought of as a data structure. If the proposition
is an implication like [A -> B], then its proof will be an
evidence _transformer_: a recipe for converting evidence for
A into evidence for B. So at a fundamental level, proofs are simply
programs that manipulate evidence.
*)
(**
Q. If evidence is data, what are propositions themselves?
A. They are types!
Look again at the formal definition of the [beautiful] property. *)
Print beautiful.
(* ==>
Inductive beautiful : nat -> Prop :=
b_0 : beautiful 0
| b_3 : beautiful 3
| b_5 : beautiful 5
| b_sum : forall n m : nat, beautiful n -> beautiful m -> beautiful (n + m)
*)
(** *** *)
(** The trick is to introduce an alternative pronunciation of "[:]".
Instead of "has type," we can also say "is a proof of." For
example, the second line in the definition of [beautiful] declares
that [b_0 : beautiful 0]. Instead of "[b_0] has type
[beautiful 0]," we can say that "[b_0] is a proof of [beautiful 0]."
Similarly for [b_3] and [b_5]. *)
(** *** *)
(** This pun between types and propositions (between [:] as "has type"
and [:] as "is a proof of" or "is evidence for") is called the
_Curry-Howard correspondence_. It proposes a deep connection
between the world of logic and the world of computation.
<<
propositions ~ types
proofs ~ data values
>>
Many useful insights follow from this connection. To begin with, it
gives us a natural interpretation of the type of [b_sum] constructor: *)
Check b_sum.
(* ===> b_sum : forall n m,
beautiful n ->
beautiful m ->
beautiful (n+m) *)
(** This can be read "[b_sum] is a constructor that takes four
arguments -- two numbers, [n] and [m], and two pieces of evidence,
for the propositions [beautiful n] and [beautiful m], respectively --
and yields evidence for the proposition [beautiful (n+m)]." *)
(** Now let's look again at a previous proof involving [beautiful]. *)
Theorem eight_is_beautiful:
beautiful 8.
Proof.
apply b_sum with (n:=3) (m:=5).
apply b_3.
apply b_5.
Qed.
(** Just as with ordinary data values and functions, we can use the [Print]
command to see the _proof object_ that results from this proof script. *)
Print eight_is_beautiful.
(* ===> eight_is_beautiful = b_sum 3 5 b_3 b_5
: beautiful 8 *)
(** In view of this, we might wonder whether we can write such
an expression ourselves. Indeed, we can: *)
Check (b_sum 3 5 b_3 b_5).
(* ===> beautiful (3 + 5) *)
(** The expression [b_sum 3 5 b_3 b_5] can be thought of as
instantiating the parameterized constructor [b_sum] with the
specific arguments [3] [5] and the corresponding proof objects for
its premises [beautiful 3] and [beautiful 5] (Coq is smart enough
to figure out that 3+5=8). Alternatively, we can think of [b_sum]
as a primitive "evidence constructor" that, when applied to two
particular numbers, wants to be further applied to evidence that
those two numbers are beautiful; its type,
forall n m, beautiful n -> beautiful m -> beautiful (n+m),
expresses this functionality, in the same way that the polymorphic
type [forall X, list X] in the previous chapter expressed the fact
that the constructor [nil] can be thought of as a function from
types to empty lists with elements of that type. *)
(** This gives us an alternative way to write the proof that [8] is
beautiful: *)
Theorem eight_is_beautiful':
beautiful 8.
Proof.
apply (b_sum 3 5 b_3 b_5).
(** Notice that we're using [apply] here in a new way: instead of just
supplying the _name_ of a hypothesis or previously proved theorem
whose type matches the current goal, we are supplying an
_expression_ that directly builds evidence with the required
type. *)
Theorem thirteen_is_beautiful:
beautiful 13.
Proof.
apply b_sum with (n:=5) (m:=8).
apply b_5.
apply eight_is_beautiful.
Qed.
(* ##################################################### *)
(** * Proof Scripts and Proof Objects *)
(** These proof objects lie at the core of how Coq operates.
When Coq is following a proof script, what is happening internally
is that it is gradually constructing a proof object -- a term
whose type is the proposition being proved. The tactics between
the [Proof] command and the [Qed] instruct Coq how to build up a
term of the required type. To see this process in action, let's
use the [Show Proof] command to display the current state of the
proof tree at various points in the following tactic proof. *)
Theorem eight_is_beautiful'': beautiful 8.
Proof.
Show Proof.
apply b_sum with (n:=3) (m:=5).
Show Proof.
apply b_3.
Show Proof.
apply b_5.
Show Proof.
Qed.
(** At any given moment, Coq has constructed a term with some
"holes" (indicated by [?1], [?2], and so on), and it knows what
type of evidence is needed at each hole. *)
(**
Each of the holes corresponds to a subgoal, and the proof is
finished when there are no more subgoals. At this point, the
[Theorem] command gives a name to the evidence we've built and
stores it in the global context. *)
(** Tactic proofs are useful and convenient, but they are not
essential: in principle, we can always construct the required
evidence by hand, as shown above. Then we can use [Definition]
(rather than [Theorem]) to give a global name directly to a
piece of evidence. *)
Definition eight_is_beautiful''' : beautiful 8 :=
b_sum 3 5 b_3 b_5.
(** All these different ways of building the proof lead to exactly the
same evidence being saved in the global environment. *)
Print eight_is_beautiful.
(* ===> eight_is_beautiful = b_sum 3 5 b_3 b_5 : beautiful 8 *)
(* Print eight_is_beautiful'. *)
(* ===> eight_is_beautiful' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
Print eight_is_beautiful''.
(* ===> eight_is_beautiful'' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
Print eight_is_beautiful'''.
(* ===> eight_is_beautiful''' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
(** **** Exercise: 1 star (six_is_beautiful) *)
(** Give a tactic proof and a proof object showing that [6] is [beautiful]. *)
Theorem six_is_beautiful :
beautiful 6.
Proof.
apply b_sum with (n:=3) (m:=3).
apply b_3.
apply b_3.
Qed.
Definition six_is_beautiful' : beautiful 6 :=
b_sum 3 3 b_3 b_3.
(** **** Exercise: 1 star (nine_is_beautiful) *)
(** Give a tactic proof and a proof object showing that [9] is [beautiful]. *)
Theorem nine_is_beautiful :
beautiful 9.
Proof.
apply b_sum with (n:=3) (m:=6).
apply b_3.
apply six_is_beautiful.
Qed.
Definition nine_is_beautiful' : beautiful 9 :=
b_sum 3 6 b_3 six_is_beautiful.
(* ##################################################### *)
(** * Quantification, Implications and Functions *)
(** In Coq's computational universe (where we've mostly been living
until this chapter), there are two sorts of values with arrows in
their types: _constructors_ introduced by [Inductive]-ly defined
data types, and _functions_.
Similarly, in Coq's logical universe, there are two ways of giving
evidence for an implication: constructors introduced by
[Inductive]-ly defined propositions, and... functions!
For example, consider this statement: *)
Theorem b_plus3: forall n,
beautiful n -> beautiful (3+n).
Proof.
intros n H.
apply b_sum.
apply b_3.
apply H.
Qed.
(** What is the proof object corresponding to [b_plus3]?
We're looking for an expression whose _type_ is [forall n,
beautiful n -> beautiful (3+n)] -- that is, a _function_ that
takes two arguments (one number and a piece of evidence) and
returns a piece of evidence! Here it is: *)
Definition b_plus3': forall n, beautiful n -> beautiful (3+n) :=
fun (n:nat) => fun (H : beautiful n) => b_sum 3 n b_3 H.
Check b_plus3'.
(* ===> b_plus3' : forall n : nat, beautiful n -> beautiful (3+n) *)
(** Recall that [fun n => blah] means "the function that, given [n],
yields [blah]." Another equivalent way to write this definition is: *)
Definition b_plus3'' (n : nat) (H : beautiful n) : beautiful (3+n) :=
b_sum 3 n b_3 H.
Check b_plus3''.
(* ===> b_plus3'' : forall n, beautiful n -> beautiful (3+n) *)
(** When we view the proposition being proved by [b_plus3] as a function type,
one aspect of it may seem a little unusual. The second argument's
type, [beautiful n], mentions the _value_ of the first argument, [n].
While such _dependent types_ are not commonly found in programming
languages, even functional ones like ML or Haskell, they can
be useful there too.
Notice that both implication ([->]) and quantification ([forall])
correspond to functions on evidence. In fact, they are really the
same thing: [->] is just a shorthand for a degenerate use of
[forall] where there is no dependency, i.e., no need to give a name
to the type on the LHS of the arrow. *)
(** For example, consider this proposition: *)
Definition beautiful_plus3 : Prop :=
forall n, forall (E : beautiful n), beautiful (n+3).
(** A proof term inhabiting this proposition would be a function
with two arguments: a number [n] and some evidence [E] that [n] is
beautiful. But the name [E] for this evidence is not used in the
rest of the statement of [funny_prop1], so it's a bit silly to
bother making up a name for it. We could write it like this
instead, using the dummy identifier [_] in place of a real
name: *)
Definition beautiful_plus3' : Prop :=
forall n, forall (_ : beautiful n), beautiful (n+3).
(** Or, equivalently, we can write it in more familiar notation: *)
Definition beatiful_plus3'' : Prop :=
forall n, beautiful n -> beautiful (n+3).
(** In general, "[P -> Q]" is just syntactic sugar for
"[forall (_:P), Q]". *)
(** **** Exercise: 2 stars b_times2 *)
(** Give a proof object corresponding to the theorem [b_times2] from Prop.v *)
Check b_sum 3 0 b_3 b_0.
Definition b_times2': forall n, beautiful n -> beautiful (2*n) :=
fun (n : nat) => fun (H : beautiful n) =>
b_sum n (n+0) H (b_sum n 0 H b_0).
(** **** Exercise: 2 stars, optional (gorgeous_plus13_po) *)
(** Give a proof object corresponding to the theorem [gorgeous_plus13] from Prop.v *)
Theorem thirteen_is_gorgeous:
gorgeous 13.
Proof.
apply g_plus5.
apply g_plus5.
apply g_plus3.
apply g_0.
Qed.
Check thirteen_is_gorgeous.
Definition gorgeous_plus3_po: forall n, gorgeous n -> gorgeous (3+n):=
fun (n : nat) => fun (H : gorgeous n) =>
g_plus3 n H.
Definition gorgeous_plus13_po: forall n, gorgeous n -> gorgeous (13+n):=
fun (n : nat) => fun (H : gorgeous n) =>
g_plus3 (10+n) (g_plus5 (5+n) (g_plus5 n H)).
(** It is particularly revealing to look at proof objects involving the
logical connectives that we defined with inductive propositions in Logic.v. *)
Theorem and_example :
(beautiful 0) /\ (beautiful 3).
Proof.
apply conj.
apply b_0.
apply b_3.
Qed.
(** Let's take a look at the proof object for the above theorem. *)
Print and_example.
(* ===> conj (beautiful 0) (beautiful 3) b_0 b_3
: beautiful 0 /\ beautiful 3 *)
(** Note that the proof is of the form
conj (beautiful 0) (beautiful 3)
(...pf of beautiful 3...) (...pf of beautiful 3...)
as you'd expect, given the type of [conj]. *)
(** **** Exercise: 1 star, optional (case_proof_objects) *)
(** The [Case] tactics were commented out in the proof of
[and_example] to avoid cluttering the proof object. What would
you guess the proof object will look like if we uncomment them?
Try it and see. *)
(** [] *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
intros.
destruct H as [HP HQ].
apply conj.
apply HQ. apply HP.
Qed.
(** Once again, we have commented out the [Case] tactics to make the
proof object for this theorem easier to understand. It is still
a little complicated, but after performing some simple reduction
steps, we can see that all that is really happening is taking apart
a record containing evidence for [P] and [Q] and rebuilding it in the
opposite order: *)
Print and_commut.
(* ===>
and_commut =
fun (P Q : Prop) (H : P /\ Q) =>
(fun H0 : Q /\ P => H0)
match H with
| conj HP HQ => (fun (HP0 : P) (HQ0 : Q) => conj Q P HQ0 HP0) HP HQ
end
: forall P Q : Prop, P /\ Q -> Q /\ P *)
(** After simplifying some direct application of [fun] expressions to arguments,
we get: *)
(* ===>
and_commut =
fun (P Q : Prop) (H : P /\ Q) =>
match H with
| conj HP HQ => conj Q P HQ HP
end
: forall P Q : Prop, P /\ Q -> Q /\ P *)
(** **** Exercise: 2 stars, optional (conj_fact) *)
(** Construct a proof object demonstrating the following proposition. *)
Theorem conj_fact': forall P Q R,
P /\ Q -> Q /\ R -> P /\ R.
Proof.
intros.
destruct H as [HP HQ].
destruct H0 as [HHQ HHR].
apply conj.
apply HP. apply HHR.
Qed.
Print conj_fact'.
Definition conj_fact : forall P Q R, P /\ Q -> Q /\ R -> P /\ R :=
fun (P Q R : Prop) (PQ : P /\ Q) (QR : Q /\ R) =>
match PQ with
| conj HP _ => match QR with
| conj _ HHR => conj P R HP HHR
end
end.
(** **** Exercise: 2 stars, advanced, optional (beautiful_iff_gorgeous) *)
(** We have seen that the families of propositions [beautiful] and
[gorgeous] actually characterize the same set of numbers.
Prove that [beautiful n <-> gorgeous n] for all [n]. Just for
fun, write your proof as an explicit proof object, rather than
using tactics. (_Hint_: if you make use of previously defined
theorems, you should only need a single line!) *)
Print beautiful__gorgeous.
Definition beautiful_iff_gorgeous :
forall n, beautiful n <-> gorgeous n :=
fun n => conj _ _ (beautiful__gorgeous n) (gorgeous__beautiful n).
(** **** Exercise: 2 stars, optional (or_commut'') *)
(** Try to write down an explicit proof object for [or_commut] (without
using [Print] to peek at the ones we already defined!). *)
Theorem or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
destruct H as [HP | HQ].
Case "left". apply or_intror. apply HP.
Case "right". apply or_introl. apply HQ.
Qed.
Print or_commut.
Definition or_commut' : forall (P Q : Prop), P \/ Q -> Q \/ P :=
fun (P Q : Prop) (H : P \/ Q) =>
match H with
| or_introl HP => or_intror Q P HP
| or_intror HQ => or_introl Q P HQ
end.
(** Recall that we model an existential for a property as a pair consisting of
a witness value and a proof that the witness obeys that property.
We can choose to construct the proof explicitly.
For example, consider this existentially quantified proposition: *)
Check ex.
Definition some_nat_is_even : Prop :=
ex _ ev.
Print some_nat_is_even.
(** To prove this proposition, we need to choose a particular number
as witness -- say, 4 -- and give some evidence that that number is
even. *)
Definition snie : some_nat_is_even :=
ex_intro _ ev 4 (ev_SS 2 (ev_SS 0 ev_0)).
(** **** Exercise: 2 stars, optional (ex_beautiful_Sn) *)
(** Complete the definition of the following proof object: *)
Definition p : ex _ (fun n => beautiful (S n)) :=
admit.
(* ##################################################### *)
(** * Giving Explicit Arguments to Lemmas and Hypotheses *)
(** Even when we are using tactic-based proof, it can be very useful to
understand the underlying functional nature of implications and quantification.
For example, it is often convenient to [apply] or [rewrite]
using a lemma or hypothesis with one or more quantifiers or
assumptions already instantiated in order to direct what
happens. For example: *)
Check plus_comm.
(* ==>
plus_comm
: forall n m : nat, n + m = m + n *)
Lemma plus_comm_r : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
rewrite (plus_comm b a).
reflexivity.
Qed.
(** In this case, giving just one argument would be sufficient. *)
Lemma plus_comm_r' : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros.
rewrite (plus_comm b).
reflexivity.
Qed.
(** Arguments must be given in order, but wildcards (_)
may be used to skip arguments that Coq can infer. *)
Lemma plus_comm_r'' : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
rewrite (plus_comm b _).
reflexivity.
Qed.
(** The author of a lemma can choose to declare easily inferable arguments
to be implicit, just as with functions and constructors.
The [with] clauses we've already seen is really just a way of
specifying selected arguments by name rather than position: *)
Lemma plus_comm_r''' : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
rewrite plus_comm with (n:=b) (m:=a).
reflexivity.
Qed.
Check trans_eq.
(** **** Exercise: 2 stars (trans_eq_example_redux) *)
(** Redo the proof of the following theorem (from MoreCoq.v) using
an [apply] of [trans_eq] but _not_ using a [with] clause. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros.
inversion H. inversion H0.
reflexivity.
Qed.
(* ##################################################### *)
(** * Programming with Tactics (Advanced) *)
(** If we can build proofs with explicit terms rather than tactics,
you may be wondering if we can build programs using tactics rather
than explicit terms. Sure! *)
Definition add1 : nat -> nat.
intro n.
apply S.
apply n.
Defined.
Print add1.
(* ==>
add1 = fun n : nat => S n
: nat -> nat
*)
Eval compute in add1 2.
(* ==> 3 : nat *)
(** Notice that we terminate the [Definition] with a [.] rather than with
[:=] followed by a term. This tells Coq to enter proof scripting mode
to build an object of type [nat -> nat]. Also, we terminate the proof
with [Defined] rather than [Qed]; this makes the definition _transparent_
so that it can be used in computation like a normally-defined function.
This feature is mainly useful for writing functions with dependent types,
which we won't explore much further in this book.
But it does illustrate the uniformity and orthogonality of the basic ideas in Coq. *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
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