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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DLXTP_BEHAVIORAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_no_pg/sky130_fd_sc_hs__u_dl_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
// Local signals
wire buf_Q GATE_delayed;
wire buf_Q D_delayed ;
reg notifier ;
wire buf_Q ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hs__u_dl_p_no_pg u_dl_p_no_pg0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTP_BEHAVIORAL_V |
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_512x20.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/27 21:24:04 lampret
// Changed instantiation name of VS RAMs.
//
// Revision 1.9 2001/11/27 19:45:04 lampret
// Fixed VS RAM instantiation - again.
//
// Revision 1.8 2001/11/23 21:42:31 simons
// Program counter divided to PPC and NPC.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_512x20(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
//aw was set to 9 which is not consistent with other parameters.
parameter aw = `OR1200_DCTAG;
//dw was set to 20 instead of using the globla settings. Not sure why
parameter dw = `OR1200_DCTAG_W;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [3:0] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [11:0] unconnected;
reg [dw-1:0] di_reg;
reg [aw-1:0] addr_reg;
reg [dw-1:0] ram [(2**aw)-1:0];
reg [dw-1:0] dout;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_512x20_bist artisan_ssp(
`else
art_hssp_512x20 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_512x20_bist vs_ssp(
`else
vs_hdsp_512x20 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S8 ramb4_s8_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:0]),
.EN(ce),
.WE(we),
.DO(doq[7:0])
);
//
// Block 1
//
RAMB4_S8 ramb4_s8_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[15:8]),
.EN(ce),
.WE(we),
.DO(doq[15:8])
);
//
// Block 2
//
RAMB4_S8 ramb4_s8_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI({4'b0000, di[19:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[19:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
//convert to an inferrend ram
/*
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI({12'h000,di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected,doq}),
.DOP()
);
*/
always @(posedge clk)
if (we)
di_reg <= di;
always @(posedge clk)
addr_reg <= addr;
assign doq = dout;
always @(posedge clk)
if (we)
ram[addr_reg] <= di_reg;
generate
begin: dist_ram
reg [dw-1:0] ram_out;
always @(posedge clk)
dout <= ram[addr_reg];
// always @*
// ram_out = ram[addr_reg];
end
endgenerate
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FA_SYMBOL_V
`define SKY130_FD_SC_HD__FA_SYMBOL_V
/**
* fa: Full adder.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fa (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FA_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: serdes_1_to_n_clk_pll_s16_diff.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: September 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: 1-bit generic 1:n clock receiver module where n is 10, 12, 14 or 16
// Instantiates necessary clock buffers and PLL
// Contains state machine to calibrate clock input delay line, and perform bitslip if required.
// The required search pattern for bitslip to function should be modified around line 142
// Takes in 1 bit of differential data and deserialises this to n bits for where this data is required
// data is received LSB first
// 0, 1, 2 ......
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module serdes_1_to_n_clk_pll_s16_diff (clkin_p, clkin_n, rxioclk, rx_serdesstrobe, reset, pattern1, rx_bufg_pll_x1, rx_bufg_pll_x2, bitslip, rx_toggle, rx_bufpll_lckd, datain) ;
parameter integer S = 16 ; // Parameter to set the serdes factor 10,12,14,16
parameter integer BS = "FALSE" ; // Parameter to enable bitslip TRUE or FALSE
parameter PLLX = 2 ; // Parameter to set multiplier for PLL
parameter PLLD = 1 ; // Parameter to set divider for PLL
parameter real CLKIN_PERIOD = 6.000 ;// clock period (ns) of input clock on clkin_p
parameter DIFF_TERM = "FALSE" ; // Parameter to enable internal differential termination
input clkin_p ; // Input from LVDS receiver pin
input clkin_n ; // Input from LVDS receiver pin
output rxioclk ; // IO Clock network
output rx_serdesstrobe ; // Parallel data capture strobe
input reset ; // Reset
input [S-1:0] pattern1 ; // Data to define pattern that bitslip should search for
output rx_bufg_pll_x1 ; // Global clock
output rx_bufg_pll_x2 ; // Global clock x2
output bitslip ; // Bitslip control line
output rx_toggle ; // Control line to data receiver
output rx_bufpll_lckd ; // BUFPLL locked
output [S-1:0] datain ; // Output data
wire P_clk; // P clock out to BUFIO2
wire pll_fb_clk; // PLL feedback clock into BUFIOFB
wire ddly_m; // Master output from IODELAY1
wire ddly_s; // Slave output from IODELAY1
wire [7:0] mdataout ; //
wire busys ; //
wire busym ; //
wire feedback ; //
wire rx_clk_in ; //
reg bslip ; //
reg [S-1:0] clk_iserdes_data ; //
wire [S/2-1:0] clk_iserdes_data_int ; //
reg [3:0] state ; //
reg cal_clk ; //
reg rst_clk ; //
wire not_rx_bufpll_lckd ; //
reg [11:0] counter ;
reg [S/2-1:0] clkh ;
reg busyd ; //
reg [3:0] count ;
reg rx_toggle_int ; //
reg enable ; //
parameter RX_SWAP_CLK = 1'b0 ; // pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
assign busy_clk = busym ;
assign datain = clk_iserdes_data ;
assign rx_toggle = rx_toggle_int ;
// Bitslip and CAL state machine
assign bitslip = bslip ;
always @ (posedge rx_bufg_pll_x1)
begin
clk_iserdes_data <= {clk_iserdes_data_int, clkh} ;
end
always @ (posedge rx_bufg_pll_x2 or posedge not_rx_bufpll_lckd)
if (not_rx_bufpll_lckd == 1'b1) begin
rx_toggle_int <= 1'b0 ;
end
else begin
if (rx_toggle_int == 1'b1) begin // check gearbox is in the right phase
clkh <= clk_iserdes_data_int ;
if (clk_iserdes_data_int == pattern1[S-1 : S/2] && count == 4'hF) begin
rx_toggle_int <= rx_toggle_int ;
end
else begin
rx_toggle_int <= ~rx_toggle_int ;
end
end
else begin
rx_toggle_int <= ~rx_toggle_int ;
end
end
always @ (posedge rx_bufg_pll_x2 or posedge not_rx_bufpll_lckd)
begin
if (not_rx_bufpll_lckd == 1'b1) begin
state <= 0 ;
enable <= 1'b0 ;
cal_clk <= 1'b0 ;
rst_clk <= 1'b0 ;
bslip <= 1'b0 ;
busyd <= 1'b1 ;
counter <= 12'b000000000000 ;
end
else begin
busyd <= busy_clk ;
if (counter[5] == 1'b1) begin
enable <= 1'b1 ;
end
if (counter[11] == 1'b1) begin // re calibrate every 2^11 clocks
state <= 0 ;
cal_clk <= 1'b0 ;
rst_clk <= 1'b0 ;
bslip <= 1'b0 ;
busyd <= 1'b1 ;
counter <= 12'b000000000000 ;
end
else begin
counter <= counter + 12'b000000000001 ;
if (state == 0 && enable == 1'b1 && busyd == 1'b0) begin
state <= 1 ;
end
else if (state == 1) begin // cal high
cal_clk <= 1'b1 ; state <= 2 ;
end
else if (state == 2 && busyd == 1'b1) begin // wait for busy high
cal_clk <= 1'b0 ; state <= 3 ; // cal low
end
else if (state == 3 && busyd == 1'b0) begin // wait for busy low
rst_clk <= 1'b1 ; state <= 4 ; // rst high
end
else if (state == 4) begin // rst low
rst_clk <= 1'b0 ; state <= 5 ;
end
else if (state == 5 && busyd == 1'b0) begin // wait for busy low
state <= 6 ;
count <= 3'b000 ;
end
else if (state == 6) begin // hang around
count <= count + 3'b001 ;
if (count == 3'b111) begin
state <= 7 ;
end
end
else if (state == 7) begin
if (BS == "TRUE" && clk_iserdes_data != pattern1) begin
bslip <= 1'b1 ; // bitslip needed
state <= 8 ;
count <= 3'b000 ;
end
else begin
state <= 9 ;
end
end
else if (state == 8) begin
bslip <= 1'b0 ; // bitslip low
count <= count + 3'b001 ;
if (count == 3'b111) begin
state <= 7 ;
end
end
else if (state == 9) begin
state <= 9 ;
end
end
end
end
IBUFGDS #(
.DIFF_TERM (DIFF_TERM))
iob_clk_in (
.I (clkin_p),
.IB (clkin_n),
.O (rx_clk_in));
assign iob_data_in = rx_clk_in ^ RX_SWAP_CLK ; // Invert clock as required
genvar i ; // Limit the output data bus to the most significant 'S' number of bits
generate
for (i = 0 ; i <= (S/2 - 1) ; i = i + 1)
begin : loop0
assign clk_iserdes_data_int[i] = mdataout[8+i-S/2] ;
end
endgenerate
IODELAY2 #(
.DATA_RATE ("SDR"), // <SDR>, DDR
.SIM_TAPDELAY_VALUE (49), // nominal tap delay (sim parameter only)
.IDELAY_VALUE (0), // {0 ... 255}
.IDELAY2_VALUE (0), // {0 ... 255}
.ODELAY_VALUE (0), // {0 ... 255}
.IDELAY_MODE ("NORMAL"), // "NORMAL", "PCI"
.SERDES_MODE ("MASTER"), // <NONE>, MASTER, SLAVE
.IDELAY_TYPE ("VARIABLE_FROM_HALF_MAX"), // "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT"), // <STAY_AT_LIMIT>, WRAPAROUND
.DELAY_SRC ("IDATAIN")) // "IO", "IDATAIN", "ODATAIN"
iodelay_m (
.IDATAIN (iob_data_in), // data from master IOB
.TOUT (), // tri-state signal to IOB
.DOUT (), // output data to IOB
.T (1'b1), // tri-state control from OLOGIC/OSERDES2
.ODATAIN (1'b0), // data from OLOGIC/OSERDES2
.DATAOUT (ddly_m), // Output data 1 to ILOGIC/ISERDES2
.DATAOUT2 (), // Output data 2 to ILOGIC/ISERDES2
.IOCLK0 (rxioclk), // High speed clock for calibration
.IOCLK1 (1'b0), // High speed clock for calibration
.CLK (rx_bufg_pll_x2), // Fabric clock (GCLK) for control signals
.CAL (cal_clk), // Calibrate enable signal
.INC (1'b0), // Increment counter
.CE (1'b0), // Clock Enable
.RST (rst_clk), // Reset delay line to 1/2 max in this case
.BUSY (busym)) ; // output signal indicating sync circuit has finished / calibration has finished
IODELAY2 #(
.DATA_RATE ("SDR"), // <SDR>, DDR
.SIM_TAPDELAY_VALUE (49), // nominal tap delay (sim parameter only)
.IDELAY_VALUE (0), // {0 ... 255}
.IDELAY2_VALUE (0), // {0 ... 255}
.ODELAY_VALUE (0), // {0 ... 255}
.IDELAY_MODE ("NORMAL"), // "NORMAL", "PCI"
.SERDES_MODE ("SLAVE"), // <NONE>, MASTER, SLAVE
.IDELAY_TYPE ("FIXED"), // "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT"), // <STAY_AT_LIMIT>, WRAPAROUND
.DELAY_SRC ("IDATAIN")) // "IO", "IDATAIN", "ODATAIN"
iodelay_s (
.IDATAIN (iob_data_in), // data from slave IOB
.TOUT (), // tri-state signal to IOB
.DOUT (), // output data to IOB
.T (1'b1), // tri-state control from OLOGIC/OSERDES2
.ODATAIN (1'b0), // data from OLOGIC/OSERDES2
.DATAOUT (ddly_s), // Output data 1 to ILOGIC/ISERDES2
.DATAOUT2 (), // Output data 2 to ILOGIC/ISERDES2
.IOCLK0 (1'b0), // High speed clock for calibration
.IOCLK1 (1'b0), // High speed clock for calibration
.CLK (1'b0), // Fabric clock (GCLK) for control signals
.CAL (1'b0), // Calibrate control signal, never needed as the slave supplies the clock input to the PLL
.INC (1'b0), // Increment counter
.CE (1'b0), // Clock Enable
.RST (1'b0), // Reset delay line
.BUSY ()) ; // output signal indicating sync circuit has finished / calibration has finished
BUFIO2 #(
.DIVIDE (1), // The DIVCLK divider divide-by value; default 1
.DIVIDE_BYPASS ("TRUE")) // DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
P_clk_bufio2_inst (
.I (P_clk), // P_clk input from IDELAY via DFB pin
.IOCLK (), // Output Clock
.DIVCLK (buf_P_clk), // Output Divided Clock
.SERDESSTROBE ()) ; // Output SERDES strobe (Clock Enable)
BUFIO2FB #(
.DIVIDE_BYPASS ("TRUE")) // DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
P_clk_bufio2fb_inst (
.I (feedback), // PLL generated 945 MHz Clock to be fed back from IOI
.O (buf_pll_fb_clk)) ; // PLL Output Feedback Clock
ISERDES2 #(
.DATA_WIDTH (S/2), // SERDES word width. This should match the setting in BUFPLL
.DATA_RATE ("SDR"), // <SDR>, DDR
.BITSLIP_ENABLE ("TRUE"), // <FALSE>, TRUE
.SERDES_MODE ("MASTER"), // <DEFAULT>, MASTER, SLAVE
.INTERFACE_TYPE ("RETIMED")) // NETWORKING, NETWORKING_PIPELINED, <RETIMED>
iserdes_m (
.D (ddly_m),
.CE0 (1'b1),
.CLK0 (rxioclk),
.CLK1 (1'b0),
.IOCE (rx_serdesstrobe),
.RST (reset),
.CLKDIV (rx_bufg_pll_x2),
.SHIFTIN (pd_edge),
.BITSLIP (bitslip),
.FABRICOUT (),
.DFB (),
.CFB0 (),
.CFB1 (),
.Q4 (mdataout[7]),
.Q3 (mdataout[6]),
.Q2 (mdataout[5]),
.Q1 (mdataout[4]),
.VALID (),
.INCDEC (),
.SHIFTOUT (cascade));
ISERDES2 #(
.DATA_WIDTH (S/2), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE ("SDR"), // <SDR>, DDR
.BITSLIP_ENABLE ("TRUE"), // <FALSE>, TRUE
.SERDES_MODE ("SLAVE"), // <DEFAULT>, MASTER, SLAVE
.INTERFACE_TYPE ("RETIMED")) // NETWORKING, NETWORKING_PIPELINED, <RETIMED>
iserdes_s (
.D (ddly_s),
.CE0 (1'b1),
.CLK0 (rxioclk),
.CLK1 (1'b0),
.IOCE (rx_serdesstrobe),
.RST (reset),
.CLKDIV (rx_bufg_pll_x2),
.SHIFTIN (cascade),
.BITSLIP (bitslip),
.FABRICOUT (),
.DFB (P_clk),
.CFB0 (feedback),
.CFB1 (),
.Q4 (mdataout[3]),
.Q3 (mdataout[2]),
.Q2 (mdataout[1]),
.Q1 (mdataout[0]),
.VALID (),
.INCDEC (),
.SHIFTOUT (pd_edge));
PLL_ADV #(
.BANDWIDTH ("OPTIMIZED"), // "high", "low" or "optimized"
.CLKFBOUT_MULT (PLLX), // multiplication factor for all output clocks
.CLKFBOUT_PHASE (0.0), // phase shift (degrees) of all output clocks
.CLKIN1_PERIOD (CLKIN_PERIOD), // clock period (ns) of input clock on clkin1
.CLKIN2_PERIOD (CLKIN_PERIOD), // clock period (ns) of input clock on clkin2
.CLKOUT0_DIVIDE (1), // division factor for clkout0 (1 to 128)
.CLKOUT0_DUTY_CYCLE (0.5), // duty cycle for clkout0 (0.01 to 0.99)
.CLKOUT0_PHASE (0.0), // phase shift (degrees) for clkout0 (0.0 to 360.0)
.CLKOUT1_DIVIDE (S/2), // division factor for clkout1 (1 to 128)
.CLKOUT1_DUTY_CYCLE (0.5), // duty cycle for clkout1 (0.01 to 0.99)
.CLKOUT1_PHASE (0.0), // phase shift (degrees) for clkout1 (0.0 to 360.0)
.CLKOUT2_DIVIDE (S), // division factor for clkout2 (1 to 128)
.CLKOUT2_DUTY_CYCLE (0.5), // duty cycle for clkout2 (0.01 to 0.99)
.CLKOUT2_PHASE (0.0), // phase shift (degrees) for clkout2 (0.0 to 360.0)
.CLKOUT3_DIVIDE (7), // division factor for clkout3 (1 to 128)
.CLKOUT3_DUTY_CYCLE (0.5), // duty cycle for clkout3 (0.01 to 0.99)
.CLKOUT3_PHASE (0.0), // phase shift (degrees) for clkout3 (0.0 to 360.0)
.CLKOUT4_DIVIDE (7), // division factor for clkout4 (1 to 128)
.CLKOUT4_DUTY_CYCLE (0.5), // duty cycle for clkout4 (0.01 to 0.99)
.CLKOUT4_PHASE (0.0), // phase shift (degrees) for clkout4 (0.0 to 360.0)
.CLKOUT5_DIVIDE (7), // division factor for clkout5 (1 to 128)
.CLKOUT5_DUTY_CYCLE (0.5), // duty cycle for clkout5 (0.01 to 0.99)
.CLKOUT5_PHASE (0.0), // phase shift (degrees) for clkout5 (0.0 to 360.0)
.COMPENSATION ("SOURCE_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
.DIVCLK_DIVIDE (PLLD), // division factor for all clocks (1 to 52)
.CLK_FEEDBACK ("CLKOUT0"), //
.REF_JITTER (0.100)) // input reference jitter (0.000 to 0.999 ui%)
rx_pll_adv_inst (
.CLKFBDCM (), // output feedback signal used when pll feeds a dcm
.CLKFBOUT (), // general output feedback signal
.CLKOUT0 (rx_pllout_xs), // xS clock for receiver
.CLKOUT1 (rx_pllout_x2), //
.CLKOUT2 (rx_pllout_x1), // x1 clock for BUFG
.CLKOUT3 (), // one of six general clock output signals
.CLKOUT4 (), // one of six general clock output signals
.CLKOUT5 (), // one of six general clock output signals
.CLKOUTDCM0 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM1 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM2 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM3 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM4 (), // one of six clock outputs to connect to the dcm
.CLKOUTDCM5 (), // one of six clock outputs to connect to the dcm
.DO (), // dynamic reconfig data output (16-bits)
.DRDY (), // dynamic reconfig ready output
.LOCKED (rx_pll_lckd), // active high pll lock signal
.CLKFBIN (buf_pll_fb_clk), // clock feedback input
.CLKIN1 (buf_P_clk), // primary clock input
.CLKIN2 (1'b0), // secondary clock input
.CLKINSEL (1'b1), // selects '1' = clkin1, '0' = clkin2
.DADDR (5'b00000), // dynamic reconfig address input (5-bits)
.DCLK (1'b0), // dynamic reconfig clock input
.DEN (1'b0), // dynamic reconfig enable input
.DI (16'h0000), // dynamic reconfig data input (16-bits)
.DWE (1'b0), // dynamic reconfig write enable input
.RST (reset), // asynchronous pll reset
.REL (1'b0)) ; // used to force the state of the PFD outputs (test only)
BUFG bufg_pll_x1 (.I(rx_pllout_x1), .O(rx_bufg_pll_x1) ) ;
BUFG bufg_pll_x2 (.I(rx_pllout_x2), .O(rx_bufg_pll_x2) ) ;
BUFPLL #(
.DIVIDE (S/2)) // PLLIN0 divide-by value to produce SERDESSTROBE (1 to 8); default 1
rx_bufpll_inst (
.PLLIN (rx_pllout_xs), // PLL Clock input
.GCLK (rx_bufg_pll_x2), // Global Clock input
.LOCKED (rx_pll_lckd), // Clock0 locked input
.IOCLK (rxioclk), // Output PLL Clock
.LOCK (rx_bufplllckd), // BUFPLL Clock and strobe locked
.SERDESSTROBE (rx_serdesstrobe)) ; // Output SERDES strobe
assign rx_bufpll_lckd = rx_pll_lckd & rx_bufplllckd ;
assign not_rx_bufpll_lckd = ~rx_bufpll_lckd ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S50_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DLYGATE4S50_BEHAVIORAL_V
/**
* dlygate4s50: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlygate4s50 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S50_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3_2_V
`define SKY130_FD_SC_HDLL__AND3_2_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3_2_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_io_grant_ff.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx_io_grant_ff(/*AUTOARG*/
// Outputs
cpx_io_grant_cx2, so,
// Inputs
cpx_io_grant_cx, rclk, si, se
);
output [7:0] cpx_io_grant_cx2;
output so;
input [7:0] cpx_io_grant_cx;
input rclk;
input si;
input se;
dff_s #(8) dff_ccx_com_src(
.din (cpx_io_grant_cx[7:0]),
.q (cpx_io_grant_cx2[7:0]),
.clk (rclk),
.se (1'b0),
.si (8'd0),
.so ());
endmodule // cpx_io_grant_ff
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:54:16 2016
/////////////////////////////////////////////////////////////
module GeAr_N8_R1_P2 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37,
n38, n39, n40, n41, n42, n43, n44, n45, n46, n47;
CLKAND2X2TS U31 ( .A(in1[0]), .B(in2[0]), .Y(n47) );
OAI21XLTS U32 ( .A0(in2[2]), .A1(in1[2]), .B0(n44), .Y(n46) );
NOR2XLTS U33 ( .A(in2[6]), .B(in1[6]), .Y(n37) );
NOR2X2TS U34 ( .A(in1[4]), .B(in2[4]), .Y(n34) );
OAI21XLTS U35 ( .A0(n41), .A1(n40), .B0(n39), .Y(n42) );
OAI21XLTS U36 ( .A0(n30), .A1(n40), .B0(n29), .Y(n28) );
NOR2X2TS U37 ( .A(in1[5]), .B(in2[5]), .Y(n40) );
OAI21XLTS U38 ( .A0(n27), .A1(n32), .B0(n26), .Y(n25) );
NOR2X2TS U39 ( .A(in1[3]), .B(in2[3]), .Y(n32) );
OAI211XLTS U40 ( .A0(in2[2]), .A1(in1[2]), .B0(in2[1]), .C0(in1[1]), .Y(n24)
);
OAI21XLTS U41 ( .A0(n36), .A1(n34), .B0(n35), .Y(n33) );
NAND2X1TS U42 ( .A(in1[3]), .B(in2[3]), .Y(n31) );
INVX2TS U43 ( .A(n31), .Y(n27) );
NAND2X1TS U44 ( .A(in2[2]), .B(in1[2]), .Y(n44) );
NAND2X1TS U45 ( .A(n44), .B(n24), .Y(n26) );
OAI31X1TS U46 ( .A0(n27), .A1(n26), .A2(n32), .B0(n25), .Y(res[3]) );
NAND2X1TS U47 ( .A(in1[5]), .B(in2[5]), .Y(n39) );
INVX2TS U48 ( .A(n39), .Y(n30) );
NAND2X1TS U49 ( .A(in1[4]), .B(in2[4]), .Y(n41) );
OAI21X1TS U50 ( .A0(n34), .A1(n31), .B0(n41), .Y(n29) );
OAI31X1TS U51 ( .A0(n30), .A1(n29), .A2(n40), .B0(n28), .Y(res[5]) );
INVX2TS U52 ( .A(n41), .Y(n36) );
OAI21X1TS U53 ( .A0(n32), .A1(n44), .B0(n31), .Y(n35) );
OAI31X1TS U54 ( .A0(n36), .A1(n35), .A2(n34), .B0(n33), .Y(res[4]) );
OAI2BB2XLTS U55 ( .B0(n39), .B1(n37), .A0N(in2[6]), .A1N(in1[6]), .Y(n38) );
CMPR32X2TS U56 ( .A(in1[7]), .B(in2[7]), .C(n38), .CO(res[8]), .S(res[7]) );
XNOR2X1TS U57 ( .A(n42), .B(in2[6]), .Y(n43) );
XNOR2X1TS U58 ( .A(in1[6]), .B(n43), .Y(res[6]) );
CMPR32X2TS U59 ( .A(in2[1]), .B(in1[1]), .C(n47), .CO(n45), .S(res[1]) );
XNOR2X1TS U60 ( .A(n46), .B(n45), .Y(res[2]) );
AOI2BB1XLTS U61 ( .A0N(in1[0]), .A1N(in2[0]), .B0(n47), .Y(res[0]) );
initial $sdf_annotate("GeAr_N8_R1_P2_syn.sdf");
endmodule
|
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 clk locked phasedone read readdata reset write writedata bandwidth_type="AUTO" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="-3000" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
//VERSION_BEGIN 14.0 cbx_altclkbuf 2014:06:17:18:06:03:SJ cbx_altiobuf_bidir 2014:06:17:18:06:03:SJ cbx_altiobuf_in 2014:06:17:18:06:03:SJ cbx_altiobuf_out 2014:06:17:18:06:03:SJ cbx_altpll 2014:06:17:18:06:03:SJ cbx_altpll_avalon 2014:06:17:18:06:03:SJ cbx_cycloneii 2014:06:17:18:06:03:SJ cbx_lpm_add_sub 2014:06:17:18:06:03:SJ cbx_lpm_compare 2014:06:17:18:06:03:SJ cbx_lpm_counter 2014:06:17:18:06:03:SJ cbx_lpm_decode 2014:06:17:18:06:03:SJ cbx_lpm_mux 2014:06:17:18:06:03:SJ cbx_lpm_shiftreg 2014:06:17:18:06:03:SJ cbx_mgl 2014:06:17:18:10:38:SJ cbx_stratix 2014:06:17:18:06:03:SJ cbx_stratixii 2014:06:17:18:06:03:SJ cbx_stratixiii 2014:06:17:18:06:03:SJ cbx_stratixv 2014:06:17:18:06:03:SJ cbx_util_mgl 2014:06:17:18:06:03:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
//VERSION_BEGIN 14.0 cbx_mgl 2014:06:17:18:10:38:SJ cbx_stratixii 2014:06:17:18:06:03:SJ cbx_util_mgl 2014:06:17:18:06:03:SJ VERSION_END
//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 14.0 cbx_mgl 2014:06:17:18:10:38:SJ cbx_stratixii 2014:06:17:18:06:03:SJ cbx_util_mgl 2014:06:17:18:06:03:SJ VERSION_END
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module usb_system_sdram_clk_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //usb_system_sdram_clk_dffpipe_l2c
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module usb_system_sdram_clk_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
usb_system_sdram_clk_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule //usb_system_sdram_clk_stdsync_sv6
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="-3000" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
//VERSION_BEGIN 14.0 cbx_altclkbuf 2014:06:17:18:06:03:SJ cbx_altiobuf_bidir 2014:06:17:18:06:03:SJ cbx_altiobuf_in 2014:06:17:18:06:03:SJ cbx_altiobuf_out 2014:06:17:18:06:03:SJ cbx_altpll 2014:06:17:18:06:03:SJ cbx_cycloneii 2014:06:17:18:06:03:SJ cbx_lpm_add_sub 2014:06:17:18:06:03:SJ cbx_lpm_compare 2014:06:17:18:06:03:SJ cbx_lpm_counter 2014:06:17:18:06:03:SJ cbx_lpm_decode 2014:06:17:18:06:03:SJ cbx_lpm_mux 2014:06:17:18:06:03:SJ cbx_mgl 2014:06:17:18:10:38:SJ cbx_stratix 2014:06:17:18:06:03:SJ cbx_stratixii 2014:06:17:18:06:03:SJ cbx_stratixiii 2014:06:17:18:06:03:SJ cbx_stratixv 2014:06:17:18:06:03:SJ cbx_util_mgl 2014:06:17:18:06:03:SJ VERSION_END
//synthesis_resources = cycloneive_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module usb_system_sdram_clk_altpll_l942
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll7_clk;
wire wire_pll7_fbout;
wire wire_pll7_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll7_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll7
(
.activeclock(),
.areset(areset),
.clk(wire_pll7_clk),
.clkbad(),
.fbin(wire_pll7_fbout),
.fbout(wire_pll7_fbout),
.inclk(inclk),
.locked(wire_pll7_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 1,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 1,
pll7.clk0_phase_shift = "-3000",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 20000,
pll7.operation_mode = "normal",
pll7.pll_type = "auto",
pll7.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll7_clk[4:0]},
locked = (wire_pll7_locked & pll_lock_sync);
endmodule //usb_system_sdram_clk_altpll_l942
//synthesis_resources = cycloneive_pll 1 reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module usb_system_sdram_clk
(
address,
areset,
c0,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
usb_system_sdram_clk_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
usb_system_sdram_clk_altpll_l942 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked));
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule //usb_system_sdram_clk
//VALID FILE
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20
module test_pe;
// Inputs
reg clk;
reg reset;
reg [10:0] ctrl;
reg [197:0] d0;
reg [193:0] d1;
reg [193:0] d2;
reg [193:0] wish;
// Outputs
wire [193:0] out;
// Instantiate the Unit Under Test (UUT)
PE uut (
.clk(clk),
.reset(reset),
.ctrl(ctrl),
.d0(d0),
.d1(d1),
.d2(d2),
.out(out)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
ctrl = 0;
d0 = 0;
d1 = 0;
d2 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// test mult
d0 = 194'h15a25886512165251569195908560596a6695612620504191;
d1 = 194'h159546442405a181195655549614540592955a15a26984015;
d2 = d1;
wish = 194'h21019120440545215a1462a194a24a6019441081402410969;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b00000_111111; #(33*`P);
check;
// test cubic
d0 = {6'b10101, 192'd0};
d1 = 194'h0894286a45940549565566512aa04a15558406850485454a4;
d2 = d1;
wish = 194'h1049480a48a0855a494855810160a90956659914560616652;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=1; #(33*`P);
check;
// test add
d0 = {6'b000101, 192'd0};
d1 = 194'h0994544a41588446516618a14691a545542521a4158868428;
d2 = 194'h1901269451681914415481656104980811a5a555155546949;
wish = 194'h16954a129284915a928a9916a4954141659a96092a11a2165;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b10001; #(33*`P);
check;
// test sub
d0 = {6'b001001, 192'd0};
d1 = 194'h0994544a41588446516618a14691a545542521a4158868428;
d2 = 194'h1901269451681914415481656104980811a5a555155546949;
wish = 194'h209661a62020aa6210125a481599194946404852006625aa2;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b10001; #(33*`P);
check;
$display("Good!");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task check;
begin
if (out !== wish)
begin $display("E %h %h", out, wish); $finish; end
end
endtask
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
`timescale 1ns/100ps
module axi_hdmi_tx_core #(
parameter CR_CB_N = 0,
parameter EMBEDDED_SYNC = 0) (
// hdmi interface
input hdmi_clk,
input hdmi_rst,
// 16-bit interface
output reg hdmi_16_hsync,
output reg hdmi_16_vsync,
output reg hdmi_16_data_e,
output reg [15:0] hdmi_16_data,
output reg [15:0] hdmi_16_es_data,
// 24-bit interface
output reg hdmi_24_hsync,
output reg hdmi_24_vsync,
output reg hdmi_24_data_e,
output reg [23:0] hdmi_24_data,
// 36-bit interface
output reg hdmi_36_hsync,
output reg hdmi_36_vsync,
output reg hdmi_36_data_e,
output reg [35:0] hdmi_36_data,
// control signals
output reg hdmi_fs_toggle,
output reg [ 8:0] hdmi_raddr_g,
output reg hdmi_tpm_oos,
output reg hdmi_status,
// vdma interface
input vdma_clk,
input vdma_wr,
input [ 8:0] vdma_waddr,
input [47:0] vdma_wdata,
input vdma_fs_ret_toggle,
input [ 8:0] vdma_fs_waddr,
// processor interface
input hdmi_csc_bypass,
input hdmi_ss_bypass,
input [ 1:0] hdmi_srcsel,
input [23:0] hdmi_const_rgb,
input [15:0] hdmi_hl_active,
input [15:0] hdmi_hl_width,
input [15:0] hdmi_hs_width,
input [15:0] hdmi_he_max,
input [15:0] hdmi_he_min,
input [15:0] hdmi_vf_active,
input [15:0] hdmi_vf_width,
input [15:0] hdmi_vs_width,
input [15:0] hdmi_ve_max,
input [15:0] hdmi_ve_min,
input [23:0] hdmi_clip_max,
input [23:0] hdmi_clip_min);
// internal registers
reg hdmi_enable = 'd0;
reg [15:0] hdmi_hs_count = 'd0;
reg [15:0] hdmi_vs_count = 'd0;
reg hdmi_fs = 'd0;
reg hdmi_fs_ret_toggle_m1 = 'd0;
reg hdmi_fs_ret_toggle_m2 = 'd0;
reg hdmi_fs_ret_toggle_m3 = 'd0;
reg hdmi_fs_ret = 'd0;
reg [ 8:0] hdmi_fs_waddr = 'd0;
reg hdmi_hs = 'd0;
reg hdmi_vs = 'd0;
reg hdmi_hs_de = 'd0;
reg hdmi_vs_de = 'd0;
reg [ 9:0] hdmi_raddr = 'd0;
reg hdmi_hs_d = 'd0;
reg hdmi_vs_d = 'd0;
reg hdmi_hs_de_d = 'd0;
reg hdmi_vs_de_d = 'd0;
reg hdmi_de_d = 'd0;
reg hdmi_data_sel_d = 'd0;
reg hdmi_hs_2d = 'd0;
reg hdmi_vs_2d = 'd0;
reg hdmi_hs_de_2d = 'd0;
reg hdmi_vs_de_2d = 'd0;
reg hdmi_de_2d = 'd0;
reg hdmi_data_sel_2d = 'd0;
reg [47:0] hdmi_data_2d = 'd0;
reg [23:0] hdmi_tpm_data = 'd0;
reg hdmi_hsync = 'd0;
reg hdmi_vsync = 'd0;
reg hdmi_hsync_data_e = 'd0;
reg hdmi_vsync_data_e = 'd0;
reg hdmi_data_e = 'd0;
reg [23:0] hdmi_data = 'd0;
reg hdmi_24_csc_hsync = 'd0;
reg hdmi_24_csc_vsync = 'd0;
reg hdmi_24_csc_hsync_data_e = 'd0;
reg hdmi_24_csc_vsync_data_e = 'd0;
reg hdmi_24_csc_data_e = 'd0;
reg [23:0] hdmi_24_csc_data = 'd0;
reg hdmi_16_hsync_d = 'd0;
reg hdmi_16_vsync_d = 'd0;
reg hdmi_16_hsync_data_e_d = 'd0;
reg hdmi_16_vsync_data_e_d = 'd0;
reg hdmi_16_data_e_d = 'd0;
reg [15:0] hdmi_16_data_d = 'd0;
reg hdmi_es_hs_de = 'd0;
reg hdmi_es_vs_de = 'd0;
reg [15:0] hdmi_es_data = 'd0;
reg [23:0] hdmi_clip_data = 'd0;
reg hdmi_clip_hs_de_d = 'd0;
reg hdmi_clip_vs_de_d = 'd0;
reg hdmi_clip_hs_d = 'd0;
reg hdmi_clip_vs_d = 'd0;
reg hdmi_clip_de_d = 'd0;
// internal wires
wire [15:0] hdmi_hl_width_s;
wire [15:0] hdmi_vf_width_s;
wire [15:0] hdmi_he_width_s;
wire [15:0] hdmi_ve_width_s;
wire hdmi_fs_ret_s;
wire hdmi_de_s;
wire [47:0] hdmi_rdata_s;
wire [23:0] hdmi_data_2d_s;
wire hdmi_tpm_mismatch_s;
wire [23:0] hdmi_tpg_data_s;
wire hdmi_csc_hsync_s;
wire hdmi_csc_vsync_s;
wire hdmi_csc_hsync_data_e_s;
wire hdmi_csc_vsync_data_e_s;
wire hdmi_csc_data_e_s;
wire [23:0] hdmi_csc_data_s;
wire hdmi_ss_hsync_s;
wire hdmi_ss_vsync_s;
wire hdmi_ss_hsync_data_e_s;
wire hdmi_ss_vsync_data_e_s;
wire hdmi_ss_data_e_s;
wire [15:0] hdmi_ss_data_s;
wire [15:0] hdmi_es_data_s;
// binary to grey conversion
function [8:0] b2g;
input [8:0] b;
reg [8:0] g;
begin
g[8] = b[8];
g[7] = b[8] ^ b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// status and enable
always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
hdmi_status <= 1'b0;
hdmi_enable <= 1'b0;
end else begin
hdmi_status <= 1'b1;
hdmi_enable <= hdmi_srcsel[1] | hdmi_srcsel[0];
end
end
// calculate useful limits
assign hdmi_hl_width_s = hdmi_hl_width - 1'b1;
assign hdmi_vf_width_s = hdmi_vf_width - 1'b1;
assign hdmi_he_width_s = hdmi_hl_width - (hdmi_hl_active + 1'b1);
assign hdmi_ve_width_s = hdmi_vf_width - (hdmi_vf_active + 1'b1);
// hdmi counters
always @(posedge hdmi_clk) begin
if (hdmi_hs_count >= hdmi_hl_width_s) begin
hdmi_hs_count <= 0;
end else begin
hdmi_hs_count <= hdmi_hs_count + 1'b1;
end
if (hdmi_hs_count >= hdmi_hl_width_s) begin
if (hdmi_vs_count >= hdmi_vf_width_s) begin
hdmi_vs_count <= 0;
end else begin
hdmi_vs_count <= hdmi_vs_count + 1'b1;
end
end
end
// hdmi start of frame
always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
hdmi_fs_toggle <= 1'b0;
hdmi_fs <= 1'b0;
end else begin
if (EMBEDDED_SYNC == 1) begin
if ((hdmi_hs_count == 1) && (hdmi_vs_count == hdmi_ve_width_s)) begin
hdmi_fs <= hdmi_enable;
end else begin
hdmi_fs <= 1'b0;
end
end else begin
if ((hdmi_hs_count == 1) && (hdmi_vs_count == hdmi_vs_width)) begin
hdmi_fs <= hdmi_enable;
end else begin
hdmi_fs <= 1'b0;
end
end
if (hdmi_fs == 1'b1) begin
hdmi_fs_toggle <= ~hdmi_fs_toggle;
end
end
end
// hdmi sof write address
assign hdmi_fs_ret_s = hdmi_fs_ret_toggle_m2 ^ hdmi_fs_ret_toggle_m3;
always @(posedge hdmi_clk or posedge hdmi_rst) begin
if (hdmi_rst == 1'b1) begin
hdmi_fs_ret_toggle_m1 <= 1'd0;
hdmi_fs_ret_toggle_m2 <= 1'd0;
hdmi_fs_ret_toggle_m3 <= 1'd0;
end else begin
hdmi_fs_ret_toggle_m1 <= vdma_fs_ret_toggle;
hdmi_fs_ret_toggle_m2 <= hdmi_fs_ret_toggle_m1;
hdmi_fs_ret_toggle_m3 <= hdmi_fs_ret_toggle_m2;
end
end
always @(posedge hdmi_clk) begin
hdmi_fs_ret <= hdmi_fs_ret_s;
hdmi_fs_waddr <= vdma_fs_waddr;
end
// hdmi sync signals
always @(posedge hdmi_clk) begin
if (EMBEDDED_SYNC == 1) begin
hdmi_hs <= 1'b0;
hdmi_vs <= 1'b0;
if (hdmi_hs_count <= hdmi_he_width_s) begin
hdmi_hs_de <= 1'b0;
end else begin
hdmi_hs_de <= hdmi_enable;
end
if (hdmi_vs_count <= hdmi_ve_width_s) begin
hdmi_vs_de <= 1'b0;
end else begin
hdmi_vs_de <= hdmi_enable;
end
end else begin
if (hdmi_hs_count < hdmi_hs_width) begin
hdmi_hs <= hdmi_enable;
end else begin
hdmi_hs <= 1'b0;
end
if (hdmi_vs_count < hdmi_vs_width) begin
hdmi_vs <= hdmi_enable;
end else begin
hdmi_vs <= 1'b0;
end
if ((hdmi_hs_count < hdmi_he_min) || (hdmi_hs_count >= hdmi_he_max)) begin
hdmi_hs_de <= 1'b0;
end else begin
hdmi_hs_de <= hdmi_enable;
end
if ((hdmi_vs_count < hdmi_ve_min) || (hdmi_vs_count >= hdmi_ve_max)) begin
hdmi_vs_de <= 1'b0;
end else begin
hdmi_vs_de <= hdmi_enable;
end
end
end
// hdmi read data
assign hdmi_de_s = hdmi_hs_de & hdmi_vs_de;
always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
hdmi_raddr <= 10'd0;
end else if (hdmi_fs == 1'b1) begin
hdmi_raddr <= {hdmi_fs_waddr, 1'b0};
end else if (hdmi_de_s == 1'b1) begin
hdmi_raddr <= hdmi_raddr + 1'b1;
end
hdmi_raddr_g <= b2g(hdmi_raddr[9:1]);
end
// control and data pipe line
always @(posedge hdmi_clk) begin
hdmi_hs_d <= hdmi_hs;
hdmi_vs_d <= hdmi_vs;
hdmi_hs_de_d <= hdmi_hs_de;
hdmi_vs_de_d <= hdmi_vs_de;
hdmi_de_d <= hdmi_de_s;
hdmi_data_sel_d <= hdmi_raddr[0];
hdmi_hs_2d <= hdmi_hs_d;
hdmi_vs_2d <= hdmi_vs_d;
hdmi_hs_de_2d <= hdmi_hs_de_d;
hdmi_vs_de_2d <= hdmi_vs_de_d;
hdmi_de_2d <= hdmi_de_d;
hdmi_data_sel_2d <= hdmi_data_sel_d;
hdmi_data_2d <= hdmi_rdata_s;
end
// hdmi data count (may be used to monitor or insert)
assign hdmi_data_2d_s = (hdmi_data_sel_2d == 1'b1) ? hdmi_data_2d[47:24] : hdmi_data_2d[23:0];
assign hdmi_tpm_mismatch_s = (hdmi_data_2d_s == hdmi_tpm_data) ? 1'b0 : hdmi_de_2d;
assign hdmi_tpg_data_s = hdmi_tpm_data;
always @(posedge hdmi_clk) begin
if ((hdmi_rst == 1'b1) || (hdmi_fs_ret == 1'b1)) begin
hdmi_tpm_data <= 'd0;
end else if (hdmi_de_2d == 1'b1) begin
hdmi_tpm_data <= hdmi_tpm_data + 1'b1;
end
hdmi_tpm_oos <= hdmi_tpm_mismatch_s;
end
// hdmi data select
always @(posedge hdmi_clk) begin
hdmi_hsync <= hdmi_hs_2d;
hdmi_vsync <= hdmi_vs_2d;
hdmi_hsync_data_e <= hdmi_hs_de_2d;
hdmi_vsync_data_e <= hdmi_vs_de_2d;
hdmi_data_e <= hdmi_de_2d;
case (hdmi_srcsel)
2'b11: hdmi_data <= hdmi_const_rgb;
2'b10: hdmi_data <= hdmi_tpg_data_s;
2'b01: hdmi_data <= hdmi_data_2d_s;
default: hdmi_data <= 24'd0;
endcase
end
// Color space conversion bypass (RGB/YCbCr)
always @(posedge hdmi_clk) begin
if (hdmi_csc_bypass == 1'b1) begin
hdmi_24_csc_hsync <= hdmi_hsync;
hdmi_24_csc_vsync <= hdmi_vsync;
hdmi_24_csc_hsync_data_e <= hdmi_hsync_data_e;
hdmi_24_csc_vsync_data_e <= hdmi_vsync_data_e;
hdmi_24_csc_data_e <= hdmi_data_e;
hdmi_24_csc_data <= hdmi_data;
end else begin
hdmi_24_csc_hsync <= hdmi_csc_hsync_s;
hdmi_24_csc_vsync <= hdmi_csc_vsync_s;
hdmi_24_csc_hsync_data_e <= hdmi_csc_hsync_data_e_s;
hdmi_24_csc_vsync_data_e <= hdmi_csc_vsync_data_e_s;
hdmi_24_csc_data_e <= hdmi_csc_data_e_s;
hdmi_24_csc_data <= hdmi_csc_data_s;
end
end
// hdmi clipping
always @(posedge hdmi_clk) begin
hdmi_clip_hs_d <= hdmi_24_csc_hsync;
hdmi_clip_vs_d <= hdmi_24_csc_vsync;
hdmi_clip_hs_de_d <= hdmi_24_csc_hsync_data_e;
hdmi_clip_vs_de_d <= hdmi_24_csc_vsync_data_e;
hdmi_clip_de_d <= hdmi_24_csc_data_e;
// Cr (red-diff) / red
if (hdmi_24_csc_data[23:16] > hdmi_clip_max[23:16]) begin
hdmi_clip_data[23:16] <= hdmi_clip_max[23:16];
end else if (hdmi_24_csc_data[23:16] < hdmi_clip_min[23:16]) begin
hdmi_clip_data[23:16] <= hdmi_clip_min[23:16];
end else begin
hdmi_clip_data[23:16] <= hdmi_24_csc_data[23:16];
end
// Y (luma) / green
if (hdmi_24_csc_data[15:8] > hdmi_clip_max[15:8]) begin
hdmi_clip_data[15:8] <= hdmi_clip_max[15:8];
end else if (hdmi_24_csc_data[15:8] < hdmi_clip_min[15:8]) begin
hdmi_clip_data[15:8] <= hdmi_clip_min[15:8];
end else begin
hdmi_clip_data[15:8] <= hdmi_24_csc_data[15:8];
end
// Cb (blue-diff) / blue
if (hdmi_24_csc_data[7:0] > hdmi_clip_max[7:0]) begin
hdmi_clip_data[7:0] <= hdmi_clip_max[7:0];
end else if (hdmi_24_csc_data[7:0] < hdmi_clip_min[7:0]) begin
hdmi_clip_data[7:0] <= hdmi_clip_min[7:0];
end else begin
hdmi_clip_data[7:0] <= hdmi_24_csc_data[7:0];
end
end
// hdmi csc 16, 24 and 36 outputs
always @(posedge hdmi_clk) begin
hdmi_36_hsync <= hdmi_clip_hs_d;
hdmi_36_vsync <= hdmi_clip_vs_d;
hdmi_36_data_e <= hdmi_clip_de_d;
hdmi_36_data[35:24] <= {hdmi_clip_data[23:16], hdmi_clip_data[23:20]};
hdmi_36_data[23:12] <= {hdmi_clip_data[15: 8], hdmi_clip_data[15:12]};
hdmi_36_data[11: 0] <= {hdmi_clip_data[ 7: 0], hdmi_clip_data[ 7: 4]};
hdmi_24_hsync <= hdmi_clip_hs_d;
hdmi_24_vsync <= hdmi_clip_vs_d;
hdmi_24_data_e <= hdmi_clip_de_d;
hdmi_24_data <= hdmi_clip_data;
hdmi_16_hsync <= hdmi_16_hsync_d;
hdmi_16_vsync <= hdmi_16_vsync_d;
hdmi_16_data_e <= hdmi_16_data_e_d;
hdmi_16_data <= hdmi_16_data_d;
hdmi_16_es_data <= hdmi_es_data_s;
if (hdmi_ss_bypass == 1'b1) begin
hdmi_16_hsync_d <= hdmi_clip_hs_d;
hdmi_16_vsync_d <= hdmi_clip_vs_d;
hdmi_16_hsync_data_e_d <= hdmi_clip_hs_de_d;
hdmi_16_vsync_data_e_d <= hdmi_clip_vs_de_d;
hdmi_16_data_e_d <= hdmi_clip_de_d;
hdmi_16_data_d <= hdmi_clip_data[15:0]; // Ignore the upper 8 bit
end else begin
hdmi_16_hsync_d <= hdmi_ss_hsync_s;
hdmi_16_vsync_d <= hdmi_ss_vsync_s;
hdmi_16_hsync_data_e_d <= hdmi_ss_hsync_data_e_s;
hdmi_16_vsync_data_e_d <= hdmi_ss_vsync_data_e_s;
hdmi_16_data_e_d <= hdmi_ss_data_e_s;
hdmi_16_data_d <= hdmi_ss_data_s;
end
end
// hdmi embedded sync
always @(posedge hdmi_clk) begin
hdmi_es_hs_de <= hdmi_16_hsync_data_e_d;
hdmi_es_vs_de <= hdmi_16_vsync_data_e_d;
if (hdmi_16_data_e_d == 1'b0) begin
hdmi_es_data[15:8] <= 8'h80;
end else begin
hdmi_es_data[15:8] <= hdmi_16_data_d[15:8];
end
if (hdmi_16_data_e_d == 1'b0) begin
hdmi_es_data[7:0] <= 8'h80;
end else begin
hdmi_es_data[7:0] <= hdmi_16_data_d[7:0];
end
end
// data memory
ad_mem #(.DATA_WIDTH(48), .ADDRESS_WIDTH(9)) i_mem (
.clka (vdma_clk),
.wea (vdma_wr),
.addra (vdma_waddr),
.dina (vdma_wdata),
.clkb (hdmi_clk),
.reb (1'b1),
.addrb (hdmi_raddr[9:1]),
.doutb (hdmi_rdata_s));
// color space coversion, RGB to CrYCb
ad_csc_RGB2CrYCb #(.DELAY_DATA_WIDTH(5)) i_csc_RGB2CrYCb (
.clk (hdmi_clk),
.RGB_sync ({hdmi_hsync,
hdmi_vsync,
hdmi_hsync_data_e,
hdmi_vsync_data_e,
hdmi_data_e}),
.RGB_data (hdmi_data),
.CrYCb_sync ({hdmi_csc_hsync_s,
hdmi_csc_vsync_s,
hdmi_csc_hsync_data_e_s,
hdmi_csc_vsync_data_e_s,
hdmi_csc_data_e_s}),
.CrYCb_data (hdmi_csc_data_s));
// sub sampling, 444 to 422
ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .CR_CB_N(CR_CB_N)) i_ss_444to422 (
.clk (hdmi_clk),
.s444_de (hdmi_clip_de_d),
.s444_sync ({hdmi_clip_hs_d,
hdmi_clip_vs_d,
hdmi_clip_hs_de_d,
hdmi_clip_vs_de_d,
hdmi_clip_de_d}),
.s444_data (hdmi_clip_data),
.s422_sync ({hdmi_ss_hsync_s,
hdmi_ss_vsync_s,
hdmi_ss_hsync_data_e_s,
hdmi_ss_vsync_data_e_s,
hdmi_ss_data_e_s}),
.s422_data (hdmi_ss_data_s));
// embedded sync
axi_hdmi_tx_es #(.DATA_WIDTH(16)) i_es (
.hdmi_clk (hdmi_clk),
.hdmi_hs_de (hdmi_es_hs_de),
.hdmi_vs_de (hdmi_es_vs_de),
.hdmi_data_de (hdmi_es_data),
.hdmi_data (hdmi_es_data_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "bd_350b_slot_2_b_0,xlconcat_v2_1_1_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "bd_350b_slot_2_b_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WI\
DTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_2_b_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O2BB2AI_BLACKBOX_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2AI_BLACKBOX_V
|
`timescale 1ns / 1ps
module RegisterFileSim();
reg clk;
reg init;
reg [4:0] readReg1;
reg [4:0] readReg2;
reg [4:0] writeReg;
reg writeOp;
reg [31:0] writeData;
wire [31:0] readData1;
wire [31:0] readData2;
RegisterFile file(
.clk(clk),
.init(init),
.writeOp(writeOp),
.readReg1(readReg1),
.readReg2(readReg2),
.writeReg(writeReg),
.writeData(writeData),
.readData1(readData1),
.readData2(readData2)
);
always #50 clk = ~clk;
initial begin
clk = 0;
init = 0;
writeOp = 0;
readReg1 = 0;
readReg2 = 0;
writeReg = 0;
writeData = 0;
// write $1 = 1
#100
init = 1;
writeOp = 1;
readReg1 = 0;
readReg2 = 0;
writeReg = 1;
writeData = 1;
// write $2 = 2
#100
init = 1;
writeOp = 1;
readReg1 = 0;
readReg2 = 0;
writeReg = 2;
writeData = 2;
// write $3 = 3
#100
init = 1;
writeOp = 1;
readReg1 = 0;
readReg2 = 0;
writeReg = 3;
writeData = 3;
// read1 $1 == 1
#100
init = 1;
writeOp = 0;
readReg1 = 1;
readReg2 = 0;
writeReg = 0;
writeData = 0;
// read2 $2 == 2
#100
init = 1;
writeOp = 0;
readReg1 = 0;
readReg2 = 2;
writeReg = 0;
writeData = 0;
// read1 $1 == 1, read2 $3 == 3
#100
init = 1;
writeOp = 0;
readReg1 = 1;
readReg2 = 3;
writeReg = 0;
writeData = 0;
#200
// reset
#100
init = 0;
writeOp = 0;
readReg1 = 0;
readReg2 = 0;
writeReg = 0;
writeData = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRBP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__SDFRBP_PP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRBP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRBP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDFRBP_PP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRBP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_2_V
`define SKY130_FD_SC_LP__A2BB2O_2_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_2 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_2 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_2_V
|
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2011-2012, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and [2] Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// KCPSM6 reference design using 'uart_tx6' and 'uart_rx6'macros.
//
//
// Target platform - ATLYS Spartan-6 Board (www.digilentinc.com).
// To be used in conjunction with the PicoTerm terminal.
//
//
// Ken Chapman - Xilinx Ltd.
//
// 19th September 2012 - Conversion from original VHDL version (6th September 2012).
//
//
// This reference design primarily provides an example of UART communication. It also
// includes some simple I/O ports (switches and LEDs) together with a simple example of
// a KCPSM6 interrupt. The KCPSM6 program provided with this hardware design demonstrates
// each of these KCPSM6 features together with features of PicoTerm.
//
// Please see 'UART6_User_Guide_30Sept12.pdf' for more descriptions.
//
// The code in this example is set to implement a 115200 UART baud rate and generates
// interrupts at one second intervals based on a 100MHz clock.
//
// Whilst the design is presented as a working example for the XC6SLX45-2CSG324 device on
// the ATLYS Spartan-6 Board (www.digilentinc.com), it is a simple reference design that
// is easily adapted or incorporated into a design for use with any hardware platform.
//
//
//////////////////////////////////////////////////////////////////////////////////////////-
//
//
module uart6_atlys (
input uart_rx,
output uart_tx,
output [7:0] led,
input [7:0] switch,
input reset_b,
input clk );
//
///////////////////////////////////////////////////////////////////////////////////////////
// Signals
///////////////////////////////////////////////////////////////////////////////////////////
//
// Signals used to connect KCPSM6
wire [11:0] address;
wire [17:0] instruction;
wire bram_enable;
reg [7:0] in_port;
wire [7:0] out_port;
wire [7:0] port_id;
wire write_strobe;
wire k_write_strobe;
wire read_strobe;
reg interrupt;
wire interrupt_ack;
wire kcpsm6_sleep;
wire kcpsm6_reset;
wire rdl;
// Signals used to connect UART_TX6
wire [7:0] uart_tx_data_in;
wire write_to_uart_tx;
wire uart_tx_data_present;
wire uart_tx_half_full;
wire uart_tx_full;
reg uart_tx_reset;
// Signals used to connect UART_RX6
wire [7:0] uart_rx_data_out;
reg read_from_uart_rx;
wire uart_rx_data_present;
wire uart_rx_half_full;
wire uart_rx_full;
reg uart_rx_reset;
// Signals used to define baud rate
reg [5:0] baud_count;
reg en_16_x_baud;
// Signals to drive LEDs
reg [7:0] led_port;
// Signals used to generate interrupt at one second intervals
reg [26:0] int_count;
reg event_1hz;
//
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Start of circuit description
//
///////////////////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////////////////
// Instantiate KCPSM6 and connect to program ROM
/////////////////////////////////////////////////////////////////////////////////////////
//
// The generics can be defined as required. In this case the 'hwbuild' value is used to
// define a version using the ASCII code for the desired letter and the interrupt vector
// has been set to 3C0 to provide 64 instructions for an Interrupt Service Routine (ISR)
// before reaching the end of a 1K memory
//
kcpsm6 #(
.interrupt_vector (12'h3C0),
.scratch_pad_memory_size(64),
.hwbuild (8'h41)) // 41 hex is ASCII Character "A"
processor (
.address (address),
.instruction (instruction),
.bram_enable (bram_enable),
.port_id (port_id),
.write_strobe (write_strobe),
.k_write_strobe (k_write_strobe),
.out_port (out_port),
.read_strobe (read_strobe),
.in_port (in_port),
.interrupt (interrupt),
.interrupt_ack (interrupt_ack),
.reset (kcpsm6_reset),
.sleep (kcpsm6_sleep),
.clk (clk));
// Reset by press button (active Low) or JTAG Loader enabled Program Memory
assign kcpsm6_reset = rdl | ~reset_b;
// Unused signals tied off until required.
// Tying to other signals used to minimise warning messages.
assign kcpsm6_sleep = write_strobe & k_write_strobe; // Always '0'
// Development Program Memory
// JTAG Loader enabled for rapid code development.
atlys_real_time_clock #(
.C_FAMILY ("S6"),
.C_RAM_SIZE_KWORDS (1),
.C_JTAG_LOADER_ENABLE (1))
program_rom (
.rdl (rdl),
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
/////////////////////////////////////////////////////////////////////////////////////////
// Interrupt control
/////////////////////////////////////////////////////////////////////////////////////////
//
// Interrupt is used to provide a 1 second time reference.
//
// A simple binary counter is used to divide the 100MHz clock and provide
// interrupt pulses that remain active until acknowledged by KCPSM6.
//
always @ (posedge clk )
begin
// divide 100MHz by 100,000,000 to form 1Hz pulses
if (int_count == 27'b101111101011110000011111111) begin
int_count <= 27'b000000000000000000000000000;
event_1hz <= 1'b1; // single cycle enable pulse
end
else begin
int_count <= int_count + 27'b000000000000000000000000001;
event_1hz <= 1'b0;
end
// Interrupt becomes active each second and remains active until acknowledged
if (interrupt_ack == 1'b1) begin
interrupt <= 1'b0;
end
else begin
if (event_1hz == 1'b1) begin
interrupt <= 1'b1;
end
else begin
interrupt <= interrupt;
end
end
end
/////////////////////////////////////////////////////////////////////////////////////////
// UART Transmitter with integral 16 byte FIFO buffer
/////////////////////////////////////////////////////////////////////////////////////////
//
// Write to buffer in UART Transmitter at port address 01 hex
//
uart_tx6 tx(
.data_in(uart_tx_data_in),
.en_16_x_baud(en_16_x_baud),
.serial_out(uart_tx),
.buffer_write(write_to_uart_tx),
.buffer_data_present(uart_tx_data_present),
.buffer_half_full(uart_tx_half_full ),
.buffer_full(uart_tx_full),
.buffer_reset(uart_tx_reset),
.clk(clk));
/////////////////////////////////////////////////////////////////////////////////////////
// UART Receiver with integral 16 byte FIFO buffer
/////////////////////////////////////////////////////////////////////////////////////////
//
// Read from buffer in UART Receiver at port address 01 hex.
//
// When KCPMS6 reads data from the receiver a pulse must be generated so that the
// FIFO buffer presents the next character to be read and updates the buffer flags.
//
uart_rx6 rx(
.serial_in(uart_rx),
.en_16_x_baud(en_16_x_baud ),
.data_out(uart_rx_data_out ),
.buffer_read(read_from_uart_rx ),
.buffer_data_present(uart_rx_data_present ),
.buffer_half_full(uart_rx_half_full ),
.buffer_full(uart_rx_full ),
.buffer_reset(uart_rx_reset ),
.clk(clk ));
//
/////////////////////////////////////////////////////////////////////////////////////////
// RS232 (UART) baud rate
/////////////////////////////////////////////////////////////////////////////////////////
//
// To set serial communication baud rate to 115,200 then en_16_x_baud must pulse
// High at 1,843,200Hz which is every 54.28 cycles at 100MHz. In this implementation
// a pulse is generated every 54 cycles resulting is a baud rate of 115,741 baud which
// is only 0.5% high and well within limits.
//
always @ (posedge clk )
begin
if (baud_count == 6'b110101) begin // counts 54 states including zero
baud_count <= 6'b000000;
en_16_x_baud <= 1'b1; // single cycle enable pulse
end
else begin
baud_count <= baud_count + 6'b000001;
en_16_x_baud <= 1'b0;
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Input Ports.
/////////////////////////////////////////////////////////////////////////////////////////
//
// Two input ports are used with the UART macros. The first is used to monitor the flags
// on both the UART transmitter and receiver. The second is used to read the data from
// the UART receiver. Note that the read also requires a 'buffer_read' pulse to be
// generated.
//
// This design includes a third input port to read 8 general purpose switches.
//
always @ (posedge clk)
begin
case (port_id[1:0])
// Read UART status at port address 00 hex
2'b00 : in_port <= { 2'b00,
uart_rx_full,
uart_rx_half_full,
uart_rx_data_present,
uart_tx_full,
uart_tx_half_full,
uart_tx_data_present };
// Read UART_RX6 data at port address 01 hex
// (see 'buffer_read' pulse generation below)
2'b01 : in_port <= uart_rx_data_out;
// Read 8 general purpose switches at port address 02 hex
2'b10 : in_port <= switch;
// Don't Care for unused case(s) ensures minimum logic implementation
default : in_port <= 8'bXXXXXXXX ;
endcase;
// Generate 'buffer_read' pulse following read from port address 01
if ((read_strobe == 1'b1) && (port_id[1:0] == 2'b01)) begin
read_from_uart_rx <= 1'b1;
end
else begin
read_from_uart_rx <= 1'b0;
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
// In this simple example there are two output ports.
// A simple output port used to control a set of 8 general purpose LEDs.
// A port used to write data directly to the FIFO buffer within 'uart_tx6' macro.
//
// LEDs are connected to a typical KCPSM6 output port.
// i.e. A register and associated decode logic to enable data capture.
always @ (posedge clk)
begin
// 'write_strobe' is used to qualify all writes to general output ports.
if (write_strobe == 1'b1) begin
// Write to LEDs at port address 02 hex
if (port_id[1] == 1'b1) begin
led_port <= out_port;
end
end
end
// Connect KCPSM6 port to device output pins
assign led = led_port;
// Write directly to the FIFO buffer within 'uart_tx6' macro at port address 01 hex.
// Note the direct connection of 'out_port' to the UART transmitter macro and the
// way that a single clock cycle write pulse is generated to capture the data.
assign uart_tx_data_in = out_port;
assign write_to_uart_tx = write_strobe & port_id[0];
//
/////////////////////////////////////////////////////////////////////////////////////////
// Constant-Optimised Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
// One constant-optimised output port is used to facilitate resetting of the UART macros.
//
always @ (posedge clk)
begin
if (k_write_strobe == 1'b1) begin
if (port_id[0] == 1'b1) begin
uart_tx_reset <= out_port[0];
uart_rx_reset <= out_port[1];
end
end
end
/////////////////////////////////////////////////////////////////////////////////////////
endmodule
//
///////////////////////////////////////////////////////////////////////////////////////////
// END OF FILE uart6_atlys.v
///////////////////////////////////////////////////////////////////////////////////////////
//
|
// ledtest.v
// Generated using ACDS version 17.0 595
`timescale 1 ps / 1 ps
module ledtest (
input wire clk_clk, // clk.clk
output wire hps_io_hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
output wire jtag_debug_master_reset_reset, // jtag_debug_master_reset.reset
output wire [7:0] led_array_io_export, // led_array_io.export
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
input wire [3:0] switch_array_io_export // switch_array_io.export
);
wire arm_mcu_h2f_reset_reset; // ARM_MCU:h2f_rst_n -> [JTAG_DEBUG:clk_reset_reset, rst_controller:reset_in0, rst_controller_001:reset_in0]
wire [1:0] arm_mcu_h2f_lw_axi_master_awburst; // ARM_MCU:h2f_lw_AWBURST -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awburst
wire [3:0] arm_mcu_h2f_lw_axi_master_arlen; // ARM_MCU:h2f_lw_ARLEN -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arlen
wire [3:0] arm_mcu_h2f_lw_axi_master_wstrb; // ARM_MCU:h2f_lw_WSTRB -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_wstrb
wire arm_mcu_h2f_lw_axi_master_wready; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_wready -> ARM_MCU:h2f_lw_WREADY
wire [11:0] arm_mcu_h2f_lw_axi_master_rid; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_rid -> ARM_MCU:h2f_lw_RID
wire arm_mcu_h2f_lw_axi_master_rready; // ARM_MCU:h2f_lw_RREADY -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_rready
wire [3:0] arm_mcu_h2f_lw_axi_master_awlen; // ARM_MCU:h2f_lw_AWLEN -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awlen
wire [11:0] arm_mcu_h2f_lw_axi_master_wid; // ARM_MCU:h2f_lw_WID -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_wid
wire [3:0] arm_mcu_h2f_lw_axi_master_arcache; // ARM_MCU:h2f_lw_ARCACHE -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arcache
wire arm_mcu_h2f_lw_axi_master_wvalid; // ARM_MCU:h2f_lw_WVALID -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_wvalid
wire [20:0] arm_mcu_h2f_lw_axi_master_araddr; // ARM_MCU:h2f_lw_ARADDR -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_araddr
wire [2:0] arm_mcu_h2f_lw_axi_master_arprot; // ARM_MCU:h2f_lw_ARPROT -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arprot
wire [2:0] arm_mcu_h2f_lw_axi_master_awprot; // ARM_MCU:h2f_lw_AWPROT -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awprot
wire [31:0] arm_mcu_h2f_lw_axi_master_wdata; // ARM_MCU:h2f_lw_WDATA -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_wdata
wire arm_mcu_h2f_lw_axi_master_arvalid; // ARM_MCU:h2f_lw_ARVALID -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arvalid
wire [3:0] arm_mcu_h2f_lw_axi_master_awcache; // ARM_MCU:h2f_lw_AWCACHE -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awcache
wire [11:0] arm_mcu_h2f_lw_axi_master_arid; // ARM_MCU:h2f_lw_ARID -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arid
wire [1:0] arm_mcu_h2f_lw_axi_master_arlock; // ARM_MCU:h2f_lw_ARLOCK -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arlock
wire [1:0] arm_mcu_h2f_lw_axi_master_awlock; // ARM_MCU:h2f_lw_AWLOCK -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awlock
wire [20:0] arm_mcu_h2f_lw_axi_master_awaddr; // ARM_MCU:h2f_lw_AWADDR -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awaddr
wire [1:0] arm_mcu_h2f_lw_axi_master_bresp; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_bresp -> ARM_MCU:h2f_lw_BRESP
wire arm_mcu_h2f_lw_axi_master_arready; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arready -> ARM_MCU:h2f_lw_ARREADY
wire [31:0] arm_mcu_h2f_lw_axi_master_rdata; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_rdata -> ARM_MCU:h2f_lw_RDATA
wire arm_mcu_h2f_lw_axi_master_awready; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awready -> ARM_MCU:h2f_lw_AWREADY
wire [1:0] arm_mcu_h2f_lw_axi_master_arburst; // ARM_MCU:h2f_lw_ARBURST -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arburst
wire [2:0] arm_mcu_h2f_lw_axi_master_arsize; // ARM_MCU:h2f_lw_ARSIZE -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_arsize
wire arm_mcu_h2f_lw_axi_master_bready; // ARM_MCU:h2f_lw_BREADY -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_bready
wire arm_mcu_h2f_lw_axi_master_rlast; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_rlast -> ARM_MCU:h2f_lw_RLAST
wire arm_mcu_h2f_lw_axi_master_wlast; // ARM_MCU:h2f_lw_WLAST -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_wlast
wire [1:0] arm_mcu_h2f_lw_axi_master_rresp; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_rresp -> ARM_MCU:h2f_lw_RRESP
wire [11:0] arm_mcu_h2f_lw_axi_master_awid; // ARM_MCU:h2f_lw_AWID -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awid
wire [11:0] arm_mcu_h2f_lw_axi_master_bid; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_bid -> ARM_MCU:h2f_lw_BID
wire arm_mcu_h2f_lw_axi_master_bvalid; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_bvalid -> ARM_MCU:h2f_lw_BVALID
wire [2:0] arm_mcu_h2f_lw_axi_master_awsize; // ARM_MCU:h2f_lw_AWSIZE -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awsize
wire arm_mcu_h2f_lw_axi_master_awvalid; // ARM_MCU:h2f_lw_AWVALID -> mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_awvalid
wire arm_mcu_h2f_lw_axi_master_rvalid; // mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_rvalid -> ARM_MCU:h2f_lw_RVALID
wire [31:0] mm_interconnect_0_mm_bridge_s0_readdata; // MM_BRIDGE:s0_readdata -> mm_interconnect_0:MM_BRIDGE_s0_readdata
wire mm_interconnect_0_mm_bridge_s0_waitrequest; // MM_BRIDGE:s0_waitrequest -> mm_interconnect_0:MM_BRIDGE_s0_waitrequest
wire mm_interconnect_0_mm_bridge_s0_debugaccess; // mm_interconnect_0:MM_BRIDGE_s0_debugaccess -> MM_BRIDGE:s0_debugaccess
wire [4:0] mm_interconnect_0_mm_bridge_s0_address; // mm_interconnect_0:MM_BRIDGE_s0_address -> MM_BRIDGE:s0_address
wire mm_interconnect_0_mm_bridge_s0_read; // mm_interconnect_0:MM_BRIDGE_s0_read -> MM_BRIDGE:s0_read
wire [3:0] mm_interconnect_0_mm_bridge_s0_byteenable; // mm_interconnect_0:MM_BRIDGE_s0_byteenable -> MM_BRIDGE:s0_byteenable
wire mm_interconnect_0_mm_bridge_s0_readdatavalid; // MM_BRIDGE:s0_readdatavalid -> mm_interconnect_0:MM_BRIDGE_s0_readdatavalid
wire mm_interconnect_0_mm_bridge_s0_write; // mm_interconnect_0:MM_BRIDGE_s0_write -> MM_BRIDGE:s0_write
wire [31:0] mm_interconnect_0_mm_bridge_s0_writedata; // mm_interconnect_0:MM_BRIDGE_s0_writedata -> MM_BRIDGE:s0_writedata
wire [0:0] mm_interconnect_0_mm_bridge_s0_burstcount; // mm_interconnect_0:MM_BRIDGE_s0_burstcount -> MM_BRIDGE:s0_burstcount
wire mm_bridge_m0_waitrequest; // mm_interconnect_1:MM_BRIDGE_m0_waitrequest -> MM_BRIDGE:m0_waitrequest
wire [31:0] mm_bridge_m0_readdata; // mm_interconnect_1:MM_BRIDGE_m0_readdata -> MM_BRIDGE:m0_readdata
wire mm_bridge_m0_debugaccess; // MM_BRIDGE:m0_debugaccess -> mm_interconnect_1:MM_BRIDGE_m0_debugaccess
wire [4:0] mm_bridge_m0_address; // MM_BRIDGE:m0_address -> mm_interconnect_1:MM_BRIDGE_m0_address
wire mm_bridge_m0_read; // MM_BRIDGE:m0_read -> mm_interconnect_1:MM_BRIDGE_m0_read
wire [3:0] mm_bridge_m0_byteenable; // MM_BRIDGE:m0_byteenable -> mm_interconnect_1:MM_BRIDGE_m0_byteenable
wire mm_bridge_m0_readdatavalid; // mm_interconnect_1:MM_BRIDGE_m0_readdatavalid -> MM_BRIDGE:m0_readdatavalid
wire [31:0] mm_bridge_m0_writedata; // MM_BRIDGE:m0_writedata -> mm_interconnect_1:MM_BRIDGE_m0_writedata
wire mm_bridge_m0_write; // MM_BRIDGE:m0_write -> mm_interconnect_1:MM_BRIDGE_m0_write
wire [0:0] mm_bridge_m0_burstcount; // MM_BRIDGE:m0_burstcount -> mm_interconnect_1:MM_BRIDGE_m0_burstcount
wire mm_interconnect_1_led_array_s1_chipselect; // mm_interconnect_1:LED_ARRAY_s1_chipselect -> LED_ARRAY:chipselect
wire [31:0] mm_interconnect_1_led_array_s1_readdata; // LED_ARRAY:readdata -> mm_interconnect_1:LED_ARRAY_s1_readdata
wire [1:0] mm_interconnect_1_led_array_s1_address; // mm_interconnect_1:LED_ARRAY_s1_address -> LED_ARRAY:address
wire mm_interconnect_1_led_array_s1_write; // mm_interconnect_1:LED_ARRAY_s1_write -> LED_ARRAY:write_n
wire [31:0] mm_interconnect_1_led_array_s1_writedata; // mm_interconnect_1:LED_ARRAY_s1_writedata -> LED_ARRAY:writedata
wire [31:0] mm_interconnect_1_switch_array_s1_readdata; // SWITCH_ARRAY:readdata -> mm_interconnect_1:SWITCH_ARRAY_s1_readdata
wire [1:0] mm_interconnect_1_switch_array_s1_address; // mm_interconnect_1:SWITCH_ARRAY_s1_address -> SWITCH_ARRAY:address
wire [31:0] jtag_debug_master_readdata; // mm_interconnect_2:JTAG_DEBUG_master_readdata -> JTAG_DEBUG:master_readdata
wire jtag_debug_master_waitrequest; // mm_interconnect_2:JTAG_DEBUG_master_waitrequest -> JTAG_DEBUG:master_waitrequest
wire [31:0] jtag_debug_master_address; // JTAG_DEBUG:master_address -> mm_interconnect_2:JTAG_DEBUG_master_address
wire jtag_debug_master_read; // JTAG_DEBUG:master_read -> mm_interconnect_2:JTAG_DEBUG_master_read
wire [3:0] jtag_debug_master_byteenable; // JTAG_DEBUG:master_byteenable -> mm_interconnect_2:JTAG_DEBUG_master_byteenable
wire jtag_debug_master_readdatavalid; // mm_interconnect_2:JTAG_DEBUG_master_readdatavalid -> JTAG_DEBUG:master_readdatavalid
wire jtag_debug_master_write; // JTAG_DEBUG:master_write -> mm_interconnect_2:JTAG_DEBUG_master_write
wire [31:0] jtag_debug_master_writedata; // JTAG_DEBUG:master_writedata -> mm_interconnect_2:JTAG_DEBUG_master_writedata
wire [255:0] mm_interconnect_2_arm_mcu_f2h_sdram0_data_readdata; // ARM_MCU:f2h_sdram0_READDATA -> mm_interconnect_2:ARM_MCU_f2h_sdram0_data_readdata
wire mm_interconnect_2_arm_mcu_f2h_sdram0_data_waitrequest; // ARM_MCU:f2h_sdram0_WAITREQUEST -> mm_interconnect_2:ARM_MCU_f2h_sdram0_data_waitrequest
wire [26:0] mm_interconnect_2_arm_mcu_f2h_sdram0_data_address; // mm_interconnect_2:ARM_MCU_f2h_sdram0_data_address -> ARM_MCU:f2h_sdram0_ADDRESS
wire mm_interconnect_2_arm_mcu_f2h_sdram0_data_read; // mm_interconnect_2:ARM_MCU_f2h_sdram0_data_read -> ARM_MCU:f2h_sdram0_READ
wire [31:0] mm_interconnect_2_arm_mcu_f2h_sdram0_data_byteenable; // mm_interconnect_2:ARM_MCU_f2h_sdram0_data_byteenable -> ARM_MCU:f2h_sdram0_BYTEENABLE
wire mm_interconnect_2_arm_mcu_f2h_sdram0_data_readdatavalid; // ARM_MCU:f2h_sdram0_READDATAVALID -> mm_interconnect_2:ARM_MCU_f2h_sdram0_data_readdatavalid
wire mm_interconnect_2_arm_mcu_f2h_sdram0_data_write; // mm_interconnect_2:ARM_MCU_f2h_sdram0_data_write -> ARM_MCU:f2h_sdram0_WRITE
wire [255:0] mm_interconnect_2_arm_mcu_f2h_sdram0_data_writedata; // mm_interconnect_2:ARM_MCU_f2h_sdram0_data_writedata -> ARM_MCU:f2h_sdram0_WRITEDATA
wire [7:0] mm_interconnect_2_arm_mcu_f2h_sdram0_data_burstcount; // mm_interconnect_2:ARM_MCU_f2h_sdram0_data_burstcount -> ARM_MCU:f2h_sdram0_BURSTCOUNT
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LED_ARRAY:reset_n, MM_BRIDGE:reset, SWITCH_ARRAY:reset_n, mm_interconnect_0:MM_BRIDGE_reset_reset_bridge_in_reset_reset, mm_interconnect_1:MM_BRIDGE_reset_reset_bridge_in_reset_reset, mm_interconnect_2:JTAG_DEBUG_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_2:JTAG_DEBUG_master_translator_reset_reset_bridge_in_reset_reset]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [mm_interconnect_0:ARM_MCU_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_2:ARM_MCU_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset]
ledtest_ARM_MCU #(
.F2S_Width (0),
.S2F_Width (0)
) arm_mcu (
.f2h_sdram_ref_clk (clk_clk), // f2h_sdram_ref_clock.clk
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.h2f_rst_n (arm_mcu_h2f_reset_reset), // h2f_reset.reset_n
.f2h_sdram0_clk (clk_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (mm_interconnect_2_arm_mcu_f2h_sdram0_data_address), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (mm_interconnect_2_arm_mcu_f2h_sdram0_data_burstcount), // .burstcount
.f2h_sdram0_WAITREQUEST (mm_interconnect_2_arm_mcu_f2h_sdram0_data_waitrequest), // .waitrequest
.f2h_sdram0_READDATA (mm_interconnect_2_arm_mcu_f2h_sdram0_data_readdata), // .readdata
.f2h_sdram0_READDATAVALID (mm_interconnect_2_arm_mcu_f2h_sdram0_data_readdatavalid), // .readdatavalid
.f2h_sdram0_READ (mm_interconnect_2_arm_mcu_f2h_sdram0_data_read), // .read
.f2h_sdram0_WRITEDATA (mm_interconnect_2_arm_mcu_f2h_sdram0_data_writedata), // .writedata
.f2h_sdram0_BYTEENABLE (mm_interconnect_2_arm_mcu_f2h_sdram0_data_byteenable), // .byteenable
.f2h_sdram0_WRITE (mm_interconnect_2_arm_mcu_f2h_sdram0_data_write), // .write
.h2f_lw_axi_clk (clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (arm_mcu_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (arm_mcu_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (arm_mcu_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (arm_mcu_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (arm_mcu_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (arm_mcu_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (arm_mcu_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (arm_mcu_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (arm_mcu_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (arm_mcu_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (arm_mcu_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (arm_mcu_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (arm_mcu_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (arm_mcu_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (arm_mcu_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (arm_mcu_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (arm_mcu_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (arm_mcu_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (arm_mcu_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (arm_mcu_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (arm_mcu_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (arm_mcu_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (arm_mcu_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (arm_mcu_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (arm_mcu_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (arm_mcu_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (arm_mcu_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (arm_mcu_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (arm_mcu_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (arm_mcu_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (arm_mcu_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (arm_mcu_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (arm_mcu_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (arm_mcu_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (arm_mcu_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (arm_mcu_h2f_lw_axi_master_rready) // .rready
);
ledtest_JTAG_DEBUG #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) jtag_debug (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~arm_mcu_h2f_reset_reset), // clk_reset.reset
.master_address (jtag_debug_master_address), // master.address
.master_readdata (jtag_debug_master_readdata), // .readdata
.master_read (jtag_debug_master_read), // .read
.master_write (jtag_debug_master_write), // .write
.master_writedata (jtag_debug_master_writedata), // .writedata
.master_waitrequest (jtag_debug_master_waitrequest), // .waitrequest
.master_readdatavalid (jtag_debug_master_readdatavalid), // .readdatavalid
.master_byteenable (jtag_debug_master_byteenable), // .byteenable
.master_reset_reset (jtag_debug_master_reset_reset) // master_reset.reset
);
ledtest_LED_ARRAY led_array (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_led_array_s1_address), // s1.address
.write_n (~mm_interconnect_1_led_array_s1_write), // .write_n
.writedata (mm_interconnect_1_led_array_s1_writedata), // .writedata
.chipselect (mm_interconnect_1_led_array_s1_chipselect), // .chipselect
.readdata (mm_interconnect_1_led_array_s1_readdata), // .readdata
.out_port (led_array_io_export) // external_connection.export
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (5),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (1),
.PIPELINE_RESPONSE (1)
) mm_bridge (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.s0_waitrequest (mm_interconnect_0_mm_bridge_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_0_mm_bridge_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_0_mm_bridge_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_0_mm_bridge_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_0_mm_bridge_s0_writedata), // .writedata
.s0_address (mm_interconnect_0_mm_bridge_s0_address), // .address
.s0_write (mm_interconnect_0_mm_bridge_s0_write), // .write
.s0_read (mm_interconnect_0_mm_bridge_s0_read), // .read
.s0_byteenable (mm_interconnect_0_mm_bridge_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_0_mm_bridge_s0_debugaccess), // .debugaccess
.m0_waitrequest (mm_bridge_m0_waitrequest), // m0.waitrequest
.m0_readdata (mm_bridge_m0_readdata), // .readdata
.m0_readdatavalid (mm_bridge_m0_readdatavalid), // .readdatavalid
.m0_burstcount (mm_bridge_m0_burstcount), // .burstcount
.m0_writedata (mm_bridge_m0_writedata), // .writedata
.m0_address (mm_bridge_m0_address), // .address
.m0_write (mm_bridge_m0_write), // .write
.m0_read (mm_bridge_m0_read), // .read
.m0_byteenable (mm_bridge_m0_byteenable), // .byteenable
.m0_debugaccess (mm_bridge_m0_debugaccess), // .debugaccess
.s0_response (), // (terminated)
.m0_response (2'b00) // (terminated)
);
ledtest_SWITCH_ARRAY switch_array (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_switch_array_s1_address), // s1.address
.readdata (mm_interconnect_1_switch_array_s1_readdata), // .readdata
.in_port (switch_array_io_export) // external_connection.export
);
ledtest_mm_interconnect_0 mm_interconnect_0 (
.ARM_MCU_h2f_lw_axi_master_awid (arm_mcu_h2f_lw_axi_master_awid), // ARM_MCU_h2f_lw_axi_master.awid
.ARM_MCU_h2f_lw_axi_master_awaddr (arm_mcu_h2f_lw_axi_master_awaddr), // .awaddr
.ARM_MCU_h2f_lw_axi_master_awlen (arm_mcu_h2f_lw_axi_master_awlen), // .awlen
.ARM_MCU_h2f_lw_axi_master_awsize (arm_mcu_h2f_lw_axi_master_awsize), // .awsize
.ARM_MCU_h2f_lw_axi_master_awburst (arm_mcu_h2f_lw_axi_master_awburst), // .awburst
.ARM_MCU_h2f_lw_axi_master_awlock (arm_mcu_h2f_lw_axi_master_awlock), // .awlock
.ARM_MCU_h2f_lw_axi_master_awcache (arm_mcu_h2f_lw_axi_master_awcache), // .awcache
.ARM_MCU_h2f_lw_axi_master_awprot (arm_mcu_h2f_lw_axi_master_awprot), // .awprot
.ARM_MCU_h2f_lw_axi_master_awvalid (arm_mcu_h2f_lw_axi_master_awvalid), // .awvalid
.ARM_MCU_h2f_lw_axi_master_awready (arm_mcu_h2f_lw_axi_master_awready), // .awready
.ARM_MCU_h2f_lw_axi_master_wid (arm_mcu_h2f_lw_axi_master_wid), // .wid
.ARM_MCU_h2f_lw_axi_master_wdata (arm_mcu_h2f_lw_axi_master_wdata), // .wdata
.ARM_MCU_h2f_lw_axi_master_wstrb (arm_mcu_h2f_lw_axi_master_wstrb), // .wstrb
.ARM_MCU_h2f_lw_axi_master_wlast (arm_mcu_h2f_lw_axi_master_wlast), // .wlast
.ARM_MCU_h2f_lw_axi_master_wvalid (arm_mcu_h2f_lw_axi_master_wvalid), // .wvalid
.ARM_MCU_h2f_lw_axi_master_wready (arm_mcu_h2f_lw_axi_master_wready), // .wready
.ARM_MCU_h2f_lw_axi_master_bid (arm_mcu_h2f_lw_axi_master_bid), // .bid
.ARM_MCU_h2f_lw_axi_master_bresp (arm_mcu_h2f_lw_axi_master_bresp), // .bresp
.ARM_MCU_h2f_lw_axi_master_bvalid (arm_mcu_h2f_lw_axi_master_bvalid), // .bvalid
.ARM_MCU_h2f_lw_axi_master_bready (arm_mcu_h2f_lw_axi_master_bready), // .bready
.ARM_MCU_h2f_lw_axi_master_arid (arm_mcu_h2f_lw_axi_master_arid), // .arid
.ARM_MCU_h2f_lw_axi_master_araddr (arm_mcu_h2f_lw_axi_master_araddr), // .araddr
.ARM_MCU_h2f_lw_axi_master_arlen (arm_mcu_h2f_lw_axi_master_arlen), // .arlen
.ARM_MCU_h2f_lw_axi_master_arsize (arm_mcu_h2f_lw_axi_master_arsize), // .arsize
.ARM_MCU_h2f_lw_axi_master_arburst (arm_mcu_h2f_lw_axi_master_arburst), // .arburst
.ARM_MCU_h2f_lw_axi_master_arlock (arm_mcu_h2f_lw_axi_master_arlock), // .arlock
.ARM_MCU_h2f_lw_axi_master_arcache (arm_mcu_h2f_lw_axi_master_arcache), // .arcache
.ARM_MCU_h2f_lw_axi_master_arprot (arm_mcu_h2f_lw_axi_master_arprot), // .arprot
.ARM_MCU_h2f_lw_axi_master_arvalid (arm_mcu_h2f_lw_axi_master_arvalid), // .arvalid
.ARM_MCU_h2f_lw_axi_master_arready (arm_mcu_h2f_lw_axi_master_arready), // .arready
.ARM_MCU_h2f_lw_axi_master_rid (arm_mcu_h2f_lw_axi_master_rid), // .rid
.ARM_MCU_h2f_lw_axi_master_rdata (arm_mcu_h2f_lw_axi_master_rdata), // .rdata
.ARM_MCU_h2f_lw_axi_master_rresp (arm_mcu_h2f_lw_axi_master_rresp), // .rresp
.ARM_MCU_h2f_lw_axi_master_rlast (arm_mcu_h2f_lw_axi_master_rlast), // .rlast
.ARM_MCU_h2f_lw_axi_master_rvalid (arm_mcu_h2f_lw_axi_master_rvalid), // .rvalid
.ARM_MCU_h2f_lw_axi_master_rready (arm_mcu_h2f_lw_axi_master_rready), // .rready
.CLOCK_clk_clk (clk_clk), // CLOCK_clk.clk
.ARM_MCU_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // ARM_MCU_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.MM_BRIDGE_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // MM_BRIDGE_reset_reset_bridge_in_reset.reset
.MM_BRIDGE_s0_address (mm_interconnect_0_mm_bridge_s0_address), // MM_BRIDGE_s0.address
.MM_BRIDGE_s0_write (mm_interconnect_0_mm_bridge_s0_write), // .write
.MM_BRIDGE_s0_read (mm_interconnect_0_mm_bridge_s0_read), // .read
.MM_BRIDGE_s0_readdata (mm_interconnect_0_mm_bridge_s0_readdata), // .readdata
.MM_BRIDGE_s0_writedata (mm_interconnect_0_mm_bridge_s0_writedata), // .writedata
.MM_BRIDGE_s0_burstcount (mm_interconnect_0_mm_bridge_s0_burstcount), // .burstcount
.MM_BRIDGE_s0_byteenable (mm_interconnect_0_mm_bridge_s0_byteenable), // .byteenable
.MM_BRIDGE_s0_readdatavalid (mm_interconnect_0_mm_bridge_s0_readdatavalid), // .readdatavalid
.MM_BRIDGE_s0_waitrequest (mm_interconnect_0_mm_bridge_s0_waitrequest), // .waitrequest
.MM_BRIDGE_s0_debugaccess (mm_interconnect_0_mm_bridge_s0_debugaccess) // .debugaccess
);
ledtest_mm_interconnect_1 mm_interconnect_1 (
.CLOCK_clk_clk (clk_clk), // CLOCK_clk.clk
.MM_BRIDGE_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // MM_BRIDGE_reset_reset_bridge_in_reset.reset
.MM_BRIDGE_m0_address (mm_bridge_m0_address), // MM_BRIDGE_m0.address
.MM_BRIDGE_m0_waitrequest (mm_bridge_m0_waitrequest), // .waitrequest
.MM_BRIDGE_m0_burstcount (mm_bridge_m0_burstcount), // .burstcount
.MM_BRIDGE_m0_byteenable (mm_bridge_m0_byteenable), // .byteenable
.MM_BRIDGE_m0_read (mm_bridge_m0_read), // .read
.MM_BRIDGE_m0_readdata (mm_bridge_m0_readdata), // .readdata
.MM_BRIDGE_m0_readdatavalid (mm_bridge_m0_readdatavalid), // .readdatavalid
.MM_BRIDGE_m0_write (mm_bridge_m0_write), // .write
.MM_BRIDGE_m0_writedata (mm_bridge_m0_writedata), // .writedata
.MM_BRIDGE_m0_debugaccess (mm_bridge_m0_debugaccess), // .debugaccess
.LED_ARRAY_s1_address (mm_interconnect_1_led_array_s1_address), // LED_ARRAY_s1.address
.LED_ARRAY_s1_write (mm_interconnect_1_led_array_s1_write), // .write
.LED_ARRAY_s1_readdata (mm_interconnect_1_led_array_s1_readdata), // .readdata
.LED_ARRAY_s1_writedata (mm_interconnect_1_led_array_s1_writedata), // .writedata
.LED_ARRAY_s1_chipselect (mm_interconnect_1_led_array_s1_chipselect), // .chipselect
.SWITCH_ARRAY_s1_address (mm_interconnect_1_switch_array_s1_address), // SWITCH_ARRAY_s1.address
.SWITCH_ARRAY_s1_readdata (mm_interconnect_1_switch_array_s1_readdata) // .readdata
);
ledtest_mm_interconnect_2 mm_interconnect_2 (
.CLOCK_clk_clk (clk_clk), // CLOCK_clk.clk
.ARM_MCU_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // ARM_MCU_f2h_sdram0_data_translator_reset_reset_bridge_in_reset.reset
.JTAG_DEBUG_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // JTAG_DEBUG_clk_reset_reset_bridge_in_reset.reset
.JTAG_DEBUG_master_translator_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // JTAG_DEBUG_master_translator_reset_reset_bridge_in_reset.reset
.JTAG_DEBUG_master_address (jtag_debug_master_address), // JTAG_DEBUG_master.address
.JTAG_DEBUG_master_waitrequest (jtag_debug_master_waitrequest), // .waitrequest
.JTAG_DEBUG_master_byteenable (jtag_debug_master_byteenable), // .byteenable
.JTAG_DEBUG_master_read (jtag_debug_master_read), // .read
.JTAG_DEBUG_master_readdata (jtag_debug_master_readdata), // .readdata
.JTAG_DEBUG_master_readdatavalid (jtag_debug_master_readdatavalid), // .readdatavalid
.JTAG_DEBUG_master_write (jtag_debug_master_write), // .write
.JTAG_DEBUG_master_writedata (jtag_debug_master_writedata), // .writedata
.ARM_MCU_f2h_sdram0_data_address (mm_interconnect_2_arm_mcu_f2h_sdram0_data_address), // ARM_MCU_f2h_sdram0_data.address
.ARM_MCU_f2h_sdram0_data_write (mm_interconnect_2_arm_mcu_f2h_sdram0_data_write), // .write
.ARM_MCU_f2h_sdram0_data_read (mm_interconnect_2_arm_mcu_f2h_sdram0_data_read), // .read
.ARM_MCU_f2h_sdram0_data_readdata (mm_interconnect_2_arm_mcu_f2h_sdram0_data_readdata), // .readdata
.ARM_MCU_f2h_sdram0_data_writedata (mm_interconnect_2_arm_mcu_f2h_sdram0_data_writedata), // .writedata
.ARM_MCU_f2h_sdram0_data_burstcount (mm_interconnect_2_arm_mcu_f2h_sdram0_data_burstcount), // .burstcount
.ARM_MCU_f2h_sdram0_data_byteenable (mm_interconnect_2_arm_mcu_f2h_sdram0_data_byteenable), // .byteenable
.ARM_MCU_f2h_sdram0_data_readdatavalid (mm_interconnect_2_arm_mcu_f2h_sdram0_data_readdatavalid), // .readdatavalid
.ARM_MCU_f2h_sdram0_data_waitrequest (mm_interconnect_2_arm_mcu_f2h_sdram0_data_waitrequest) // .waitrequest
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~arm_mcu_h2f_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~arm_mcu_h2f_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
module mcpu( input CLK,
input CLK_MEM,
input RESET,
input RUN,
//External inst memory iface
output [29:0] INST_ADDR,
input [31:0] INST_RD,
//External data memory iface
output DATA_WE,
output [3:0] DATA_BE,
output [29:0] DATA_ADDR,
output [31:0] DATA_WD,
input [31:0] DATA_RD );
wire WRITE_REG, WRITE_MEM, ALUORMEM_WR, MULTIPLY,
ALU_SRC_B, BRANCH_E, BRANCH_NE, JUMP, JUMP_R,
BRANCH_LEZ, BRANCH_LTZ, BRANCH_GEZ, BRANCH_GTZ,
MEM_PARTIAL;
wire [1:0] IMMED_EXT, REG_DST, MFCOP_SEL, MEM_OPTYPE;
wire [6:0] ALU_OP;
wire [5:0] OPCODE;
wire [5:0] FCODE;
wire [4:0] RT;
controller the_controller ( .OPCODE (OPCODE ), //instruction opcode
.FCODE (FCODE ), //instruction fcode
.RT (RT ), //instruction RT
.WRITE_REG (WRITE_REG ), //write to register file
.WRITE_MEM (WRITE_MEM ), //write data memory
.MEM_PARTIAL(MEM_PARTIAL), //memory byte- or halfword access
.MEM_OPTYPE (MEM_OPTYPE ), //mem op: 00-ubyte, 01-uhalf, 10-sb, 11-sh
.ALUORMEM_WR(ALUORMEM_WR), //write regfile from alu or from memory
.MULTIPLY (MULTIPLY ), //multiply and write hi and lo
.BRANCH_E (BRANCH_E ), //branch equal
.BRANCH_NE (BRANCH_NE ), //branch not equal
.BRANCH_LEZ (BRANCH_LEZ ), //branch less than or equal zero
.BRANCH_LTZ (BRANCH_LTZ ), //branch less than zero
.BRANCH_GEZ (BRANCH_GEZ ), //branch greater than or equal zero
.BRANCH_GTZ (BRANCH_GTZ ), //branch greater than zero
.JUMP (JUMP ), //j-type jump
.JUMP_R (JUMP_R ), //r-type jump
.ALU_SRC_B (ALU_SRC_B ), //ALU Operand B 0 - reg_2, 1 - immediate
.ALU_OP (ALU_OP ), //ALU Operation select
.REG_DST (REG_DST ), //write destination in regfile (0 - rt, 1 - rd)
.IMMED_EXT (IMMED_EXT ), //immed-extension type
.MFCOP_SEL (MFCOP_SEL )); //move from coprocessor sel
datapath the_datapath ( .CLK (CLK ),
.CLK_MEM (CLK_MEM ),
.RESET (RESET ),
.RUN (RUN ),
//Controller iface
.OPCODE (OPCODE ), //instruction opcode
.FCODE (FCODE ), //instruction fcode
.RT (RT ), //instruction RT
.WRITE_REG (WRITE_REG ), //write to register file
.WRITE_MEM (WRITE_MEM ), //write data memory
.MEM_PARTIAL (MEM_PARTIAL), //memory byte- or halfword access
.MEM_OPTYPE (MEM_OPTYPE ), //mem op: 00-ubyte, 01-uhalf, 10-sb, 11-sh
.ALUORMEM_WR (ALUORMEM_WR), //write regfile from alu or from memory
.MULTIPLY (MULTIPLY ), //multiply and write hi and lo
.BRANCH_E (BRANCH_E ), //branch equal
.BRANCH_NE (BRANCH_NE ), //branch not equal
.BRANCH_LEZ (BRANCH_LEZ ), //branch less than or equal zero
.BRANCH_LTZ (BRANCH_LTZ ), //branch less than zero
.BRANCH_GEZ (BRANCH_GEZ ), //branch greater than or equal zero
.BRANCH_GTZ (BRANCH_GTZ ), //branch greater than zero
.JUMP (JUMP ), //j-type jump
.JUMP_R (JUMP_R ), //r-type jump
.ALU_SRC_B (ALU_SRC_B ), //ALU Operand B 0 - reg_2, 1 - immediate
.ALU_OP (ALU_OP ), //ALU Operation select
.REG_DST (REG_DST ), //write destination in regfile (0 - rt, 1 - rd)
.IMMED_EXT (IMMED_EXT ), //immed ext (sign, zero, swap)
.MFCOP_SEL (MFCOP_SEL ), //move from coprocessor sel
//External inst memory iface
.inst_mem_addr (INST_ADDR),
.inst_mem_data (INST_RD ),
//External data memory iface
.data_mem_we (DATA_WE ),
.data_mem_be (DATA_BE ),
.data_mem_addr (DATA_ADDR),
.data_mem_wdata (DATA_WD ),
.data_mem_rdata (DATA_RD ) );
endmodule
|
/**
* bsg_mesh_router_decoder_dor.v
*
* Dimension ordered routing decoder
*
* depopulated ruche router.
*/
module bsg_mesh_router_decoder_dor
import bsg_noc_pkg::*;
import bsg_mesh_router_pkg::*;
#(parameter `BSG_INV_PARAM(x_cord_width_p )
, parameter `BSG_INV_PARAM(y_cord_width_p )
, parameter dims_p = 2
, parameter dirs_lp = (2*dims_p)+1
, parameter ruche_factor_X_p=0
, parameter ruche_factor_Y_p=0
// XY_order_p = 1 : X then Y
// XY_order_p = 0 : Y then X
, parameter XY_order_p = 1
, parameter from_p = {dirs_lp{1'b0}} // one-hot, indicates which direction is the input coming from.
, parameter debug_p = 0
)
(
input clk_i // debug only
, input reset_i // debug only
//, input v_i
, input [x_cord_width_p-1:0] x_dirs_i
, input [y_cord_width_p-1:0] y_dirs_i
, input [x_cord_width_p-1:0] my_x_i
, input [y_cord_width_p-1:0] my_y_i
, output [dirs_lp-1:0] req_o
);
// check parameters
// synopsys translate_off
initial begin
if (ruche_factor_X_p > 0) begin
assert(dims_p > 2) else $fatal(1, "ruche in X direction requires dims_p greater than 2.");
end
if (ruche_factor_Y_p > 0) begin
assert(dims_p > 3) else $fatal(1, "ruche in Y direction requires dims_p greater than 3.");
end
assert($countones(from_p) == 1) else $fatal(1, "Must define from_p as one-hot value.");
assert(ruche_factor_X_p < (1<<x_cord_width_p)) else $fatal(1, "ruche factor in X direction is too large");
assert(ruche_factor_Y_p < (1<<y_cord_width_p)) else $fatal(1, "ruche factor in Y direction is too large");
end
// synopsys translate_on
// compare coordinates
wire x_eq = (x_dirs_i == my_x_i);
wire y_eq = (y_dirs_i == my_y_i);
wire x_gt = x_dirs_i > my_x_i;
wire y_gt = y_dirs_i > my_y_i;
wire x_lt = ~x_gt & ~x_eq;
wire y_lt = ~y_gt & ~y_eq;
// valid signal
logic [dirs_lp-1:0] req;
assign req_o = req;
// P-port
assign req[P] = x_eq & y_eq;
if (ruche_factor_X_p > 0) begin
if (XY_order_p) begin
// make sure there is no under/overflow.
wire [x_cord_width_p:0] re_cord = (x_cord_width_p+1)'(my_x_i + ruche_factor_X_p);
wire send_rw = (my_x_i > (x_cord_width_p)'(ruche_factor_X_p)) & (x_dirs_i < (my_x_i - (x_cord_width_p)'(ruche_factor_X_p)));
wire send_re = ~re_cord[x_cord_width_p] & (x_dirs_i > re_cord[0+:x_cord_width_p]);
assign req[W] = x_lt & ~send_rw;
assign req[RW] = send_rw;
assign req[E] = x_gt & ~send_re;
assign req[RE] = send_re;
end
else begin
if (from_p[S] | from_p[N] | from_p[P]) begin
assign req[W] = y_eq & x_lt;
assign req[RW] = 1'b0;
assign req[E] = y_eq & x_gt;
assign req[RE] = 1'b0;
end
else if(from_p[W]) begin
wire [x_cord_width_p-1:0] dx = (x_cord_width_p)'((x_dirs_i - my_x_i) % ruche_factor_X_p);
assign req[RE] = y_eq & x_gt & (dx == '0);
assign req[E] = y_eq & x_gt & (dx != '0);
assign req[RW] = 1'b0;
assign req[W] = 1'b0;
end
else if (from_p[E]) begin
wire [x_cord_width_p-1:0] dx = (x_cord_width_p)'((my_x_i - x_dirs_i) % ruche_factor_X_p);
assign req[RE] = 1'b0;
assign req[E] = 1'b0;
assign req[RW] = y_eq & x_lt & (dx == '0);
assign req[W] = y_eq & x_lt & (dx != '0);
end
else if (from_p[RW]) begin
assign req[RE] = y_eq & x_gt;
assign req[E] = 1'b0;
assign req[RW] = 1'b0;
assign req[W] = 1'b0;
end
else if (from_p[RE]) begin
assign req[RE] = 1'b0;
assign req[E] = 1'b0;
assign req[RW] = y_eq & x_lt;
assign req[W] = 1'b0;
end
end
end
else begin
if (XY_order_p) begin
assign req[W] = x_lt;
assign req[E] = x_gt;
end
else begin
assign req[W] = y_eq & x_lt;
assign req[E] = y_eq & x_gt;
end
end
if (ruche_factor_Y_p > 0) begin
if (XY_order_p == 0) begin
// make sure there is no under/overflow.
wire [y_cord_width_p:0] rs_cord = (y_cord_width_p+1)'(my_y_i + ruche_factor_Y_p);
wire send_rn = (my_y_i > (y_cord_width_p)'(ruche_factor_Y_p)) & (y_dirs_i < (my_y_i - (y_cord_width_p)'(ruche_factor_Y_p)));
wire send_rs = ~rs_cord[y_cord_width_p] & (y_dirs_i > rs_cord[0+:y_cord_width_p]);
assign req[N] = y_lt & ~send_rn;
assign req[RN] = send_rn;
assign req[S] = y_gt & ~send_rs;
assign req[RS] = send_rs;
end
else begin
if (from_p[E] | from_p[W] | from_p[P]) begin
assign req[N] = x_eq & y_lt;
assign req[RN] = 1'b0;
assign req[S] = x_eq & y_gt;
assign req[RS] = 1'b0;
end
else if (from_p[N]) begin
wire [y_cord_width_p-1:0] dy = (y_cord_width_p)'((y_dirs_i - my_y_i) % ruche_factor_Y_p);
assign req[RS] = x_eq & y_gt & (dy == '0);
assign req[S] = x_eq & y_gt & (dy != '0);
assign req[RN] = 1'b0;
assign req[N] = 1'b0;
end
else if (from_p[S]) begin
wire [y_cord_width_p-1:0] dy = (y_cord_width_p)'((my_y_i - y_dirs_i) % ruche_factor_Y_p);
assign req[RS] = 1'b0;
assign req[S] = 1'b0;
assign req[RN] = x_eq & y_lt & (dy == '0);
assign req[N] = x_eq & y_lt & (dy != '0);
end
else if (from_p[RN]) begin
assign req[RS] = x_eq & y_gt;
assign req[S] = 1'b0;
assign req[RN] = 1'b0;
assign req[N] = 1'b0;
end
else if (from_p[RS]) begin
assign req[RS] = 1'b0;
assign req[S] = 1'b0;
assign req[RN] = x_eq & y_lt;
assign req[N] = 1'b0;
end
end
end
else begin
if (XY_order_p == 0) begin
assign req[N] = y_lt;
assign req[S] = y_gt;
end
else begin
assign req[N] = x_eq & y_lt;
assign req[S] = x_eq & y_gt;
end
end
// synopsys translate_off
if (debug_p) begin
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
assert($countones(req_o) < 2)
else $fatal(1, "multiple req_o detected. %b", req_o);
end
end
end
else begin
wire unused0 = clk_i;
wire unused1 = reset_i;
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mesh_router_decoder_dor)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_SYMBOL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_SYMBOL_V
/**
* busdrivernovlpsleep: Bus driver, enable gates pulldown only,
* non-inverted sleep input (on kapwr rail).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlpsleep (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_8_V
`define SKY130_FD_SC_HD__EINVP_8_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__einvp_8 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__einvp_8 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_8_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_LP_V
`define SKY130_FD_SC_LP__OR3B_LP_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_lp (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_lp (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_LP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_dp_maca_r.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx_dp_maca_r(/*AUTOARG*/
// Outputs
data_out_cx_l, scan_out, shiftenable_buf,
// Inputs
arb_cpxdp_qsel1_ca, arb_cpxdp_qsel0_ca, arb_cpxdp_grant_ca,
arb_cpxdp_shift_cx, arb_cpxdp_q0_hold_ca, src_cpx_data_ca, rclk,
scan_in, shiftenable
);
output [149:0] data_out_cx_l; // cpx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_cpxdp_qsel1_ca; // queue write sel
input arb_cpxdp_qsel0_ca; // queue write sel
input arb_cpxdp_grant_ca;//grant signal
input arb_cpxdp_shift_cx;//grant signal
input arb_cpxdp_q0_hold_ca;//grant signal
input [149:0] src_cpx_data_ca; // scache to cpx data
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_cx;
wire [149:0] q0_datain_ca;
wire [149:0] q1_dataout, q0_dataout;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
//HEADER SECTION
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
/*
always @ (clk or arb_cpxdp_qsel1_ca )
begin
if (!clk) //latch opens on rclk low phase
clkenq1 = arb_cpxdp_qsel1_ca ;
end // always @ (clk or arb_cpxdp_qsel1_ca or tmb)
assign clkq1 = clkenq1 & clk;
always @ (clk or arb_cpxdp_q0_hold_ca )
begin
if (!clk) //latch opens on rclk low phase
clkenq0 = !arb_cpxdp_q0_hold_ca ;
end // always @ (clk or arb_cpxdp_q0_hold_ca or tmb)
assign clkq0 = clkenq0 & clk;
*/
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_cpxdp_q0_hold_ca),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_cpxdp_qsel1_ca),
.tmb_l(se_l));
dff_s #(1) dff_cpx_grin_r(
.din (arb_cpxdp_grant_ca),
.q (grant_cx),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(150) dff_cpx_datain_q1(
.din (src_cpx_data_ca[149:0]),
.q (q1_dataout[149:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
assign q0_datain_ca[149:0] =
(arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
(arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
dff_s #(150) dff_cpx_datain_q0(
.din (q0_datain_ca[149:0]),
.q (q0_dataout[149:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_out_cx_l[149:0] = ~(grant_cx ? q0_dataout[149:0] : 150'd0);
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl")
// End:
// Code start here
//
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3_BEHAVIORAL_V
`define SKY130_FD_SC_MS__OR3_BEHAVIORAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3_BEHAVIORAL_V |
// hps_design.v
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design (
input wire clk_clk, // clk.clk
output wire [14:0] hps_ddr3_mem_a, // hps_ddr3.mem_a
output wire [2:0] hps_ddr3_mem_ba, // .mem_ba
output wire hps_ddr3_mem_ck, // .mem_ck
output wire hps_ddr3_mem_ck_n, // .mem_ck_n
output wire hps_ddr3_mem_cke, // .mem_cke
output wire hps_ddr3_mem_cs_n, // .mem_cs_n
output wire hps_ddr3_mem_ras_n, // .mem_ras_n
output wire hps_ddr3_mem_cas_n, // .mem_cas_n
output wire hps_ddr3_mem_we_n, // .mem_we_n
output wire hps_ddr3_mem_reset_n, // .mem_reset_n
inout wire [31:0] hps_ddr3_mem_dq, // .mem_dq
inout wire [3:0] hps_ddr3_mem_dqs, // .mem_dqs
inout wire [3:0] hps_ddr3_mem_dqs_n, // .mem_dqs_n
output wire hps_ddr3_mem_odt, // .mem_odt
output wire [3:0] hps_ddr3_mem_dm, // .mem_dm
input wire hps_ddr3_oct_rzqin, // .oct_rzqin
output wire ledr_export // ledr.export
);
wire pll_0_outclk0_clk; // pll_0:outclk_0 -> [SMP_HPS:h2f_lw_axi_clk, mm_interconnect_0:pll_0_outclk0_clk, pio_0:clk, rst_controller:clk, rst_controller_001:clk]
wire smp_hps_h2f_reset_reset; // SMP_HPS:h2f_rst_n -> [pll_0:rst, rst_controller:reset_in0, rst_controller_001:reset_in0]
wire [1:0] smp_hps_h2f_lw_axi_master_awburst; // SMP_HPS:h2f_lw_AWBURST -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awburst
wire [3:0] smp_hps_h2f_lw_axi_master_arlen; // SMP_HPS:h2f_lw_ARLEN -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arlen
wire [3:0] smp_hps_h2f_lw_axi_master_wstrb; // SMP_HPS:h2f_lw_WSTRB -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wstrb
wire smp_hps_h2f_lw_axi_master_wready; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wready -> SMP_HPS:h2f_lw_WREADY
wire [11:0] smp_hps_h2f_lw_axi_master_rid; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rid -> SMP_HPS:h2f_lw_RID
wire smp_hps_h2f_lw_axi_master_rready; // SMP_HPS:h2f_lw_RREADY -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rready
wire [3:0] smp_hps_h2f_lw_axi_master_awlen; // SMP_HPS:h2f_lw_AWLEN -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awlen
wire [11:0] smp_hps_h2f_lw_axi_master_wid; // SMP_HPS:h2f_lw_WID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wid
wire [3:0] smp_hps_h2f_lw_axi_master_arcache; // SMP_HPS:h2f_lw_ARCACHE -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arcache
wire smp_hps_h2f_lw_axi_master_wvalid; // SMP_HPS:h2f_lw_WVALID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wvalid
wire [20:0] smp_hps_h2f_lw_axi_master_araddr; // SMP_HPS:h2f_lw_ARADDR -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_araddr
wire [2:0] smp_hps_h2f_lw_axi_master_arprot; // SMP_HPS:h2f_lw_ARPROT -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arprot
wire [2:0] smp_hps_h2f_lw_axi_master_awprot; // SMP_HPS:h2f_lw_AWPROT -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awprot
wire [31:0] smp_hps_h2f_lw_axi_master_wdata; // SMP_HPS:h2f_lw_WDATA -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wdata
wire smp_hps_h2f_lw_axi_master_arvalid; // SMP_HPS:h2f_lw_ARVALID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arvalid
wire [3:0] smp_hps_h2f_lw_axi_master_awcache; // SMP_HPS:h2f_lw_AWCACHE -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awcache
wire [11:0] smp_hps_h2f_lw_axi_master_arid; // SMP_HPS:h2f_lw_ARID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arid
wire [1:0] smp_hps_h2f_lw_axi_master_arlock; // SMP_HPS:h2f_lw_ARLOCK -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arlock
wire [1:0] smp_hps_h2f_lw_axi_master_awlock; // SMP_HPS:h2f_lw_AWLOCK -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awlock
wire [20:0] smp_hps_h2f_lw_axi_master_awaddr; // SMP_HPS:h2f_lw_AWADDR -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awaddr
wire [1:0] smp_hps_h2f_lw_axi_master_bresp; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_bresp -> SMP_HPS:h2f_lw_BRESP
wire smp_hps_h2f_lw_axi_master_arready; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arready -> SMP_HPS:h2f_lw_ARREADY
wire [31:0] smp_hps_h2f_lw_axi_master_rdata; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rdata -> SMP_HPS:h2f_lw_RDATA
wire smp_hps_h2f_lw_axi_master_awready; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awready -> SMP_HPS:h2f_lw_AWREADY
wire [1:0] smp_hps_h2f_lw_axi_master_arburst; // SMP_HPS:h2f_lw_ARBURST -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arburst
wire [2:0] smp_hps_h2f_lw_axi_master_arsize; // SMP_HPS:h2f_lw_ARSIZE -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_arsize
wire smp_hps_h2f_lw_axi_master_bready; // SMP_HPS:h2f_lw_BREADY -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_bready
wire smp_hps_h2f_lw_axi_master_rlast; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rlast -> SMP_HPS:h2f_lw_RLAST
wire smp_hps_h2f_lw_axi_master_wlast; // SMP_HPS:h2f_lw_WLAST -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_wlast
wire [1:0] smp_hps_h2f_lw_axi_master_rresp; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rresp -> SMP_HPS:h2f_lw_RRESP
wire [11:0] smp_hps_h2f_lw_axi_master_awid; // SMP_HPS:h2f_lw_AWID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awid
wire [11:0] smp_hps_h2f_lw_axi_master_bid; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_bid -> SMP_HPS:h2f_lw_BID
wire smp_hps_h2f_lw_axi_master_bvalid; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_bvalid -> SMP_HPS:h2f_lw_BVALID
wire [2:0] smp_hps_h2f_lw_axi_master_awsize; // SMP_HPS:h2f_lw_AWSIZE -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awsize
wire smp_hps_h2f_lw_axi_master_awvalid; // SMP_HPS:h2f_lw_AWVALID -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_awvalid
wire smp_hps_h2f_lw_axi_master_rvalid; // mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_rvalid -> SMP_HPS:h2f_lw_RVALID
wire mm_interconnect_0_pio_0_s1_chipselect; // mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
wire [31:0] mm_interconnect_0_pio_0_s1_readdata; // pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
wire [1:0] mm_interconnect_0_pio_0_s1_address; // mm_interconnect_0:pio_0_s1_address -> pio_0:address
wire mm_interconnect_0_pio_0_s1_write; // mm_interconnect_0:pio_0_s1_write -> pio_0:write_n
wire [31:0] mm_interconnect_0_pio_0_s1_writedata; // mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [mm_interconnect_0:pio_0_reset_reset_bridge_in_reset_reset, pio_0:reset_n]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> mm_interconnect_0:SMP_HPS_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset
hps_design_SMP_HPS #(
.F2S_Width (0),
.S2F_Width (0)
) smp_hps (
.mem_a (hps_ddr3_mem_a), // memory.mem_a
.mem_ba (hps_ddr3_mem_ba), // .mem_ba
.mem_ck (hps_ddr3_mem_ck), // .mem_ck
.mem_ck_n (hps_ddr3_mem_ck_n), // .mem_ck_n
.mem_cke (hps_ddr3_mem_cke), // .mem_cke
.mem_cs_n (hps_ddr3_mem_cs_n), // .mem_cs_n
.mem_ras_n (hps_ddr3_mem_ras_n), // .mem_ras_n
.mem_cas_n (hps_ddr3_mem_cas_n), // .mem_cas_n
.mem_we_n (hps_ddr3_mem_we_n), // .mem_we_n
.mem_reset_n (hps_ddr3_mem_reset_n), // .mem_reset_n
.mem_dq (hps_ddr3_mem_dq), // .mem_dq
.mem_dqs (hps_ddr3_mem_dqs), // .mem_dqs
.mem_dqs_n (hps_ddr3_mem_dqs_n), // .mem_dqs_n
.mem_odt (hps_ddr3_mem_odt), // .mem_odt
.mem_dm (hps_ddr3_mem_dm), // .mem_dm
.oct_rzqin (hps_ddr3_oct_rzqin), // .oct_rzqin
.h2f_rst_n (smp_hps_h2f_reset_reset), // h2f_reset.reset_n
.h2f_lw_axi_clk (pll_0_outclk0_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (smp_hps_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (smp_hps_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (smp_hps_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (smp_hps_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (smp_hps_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (smp_hps_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (smp_hps_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (smp_hps_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (smp_hps_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (smp_hps_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (smp_hps_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (smp_hps_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (smp_hps_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (smp_hps_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (smp_hps_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (smp_hps_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (smp_hps_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (smp_hps_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (smp_hps_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (smp_hps_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (smp_hps_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (smp_hps_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (smp_hps_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (smp_hps_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (smp_hps_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (smp_hps_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (smp_hps_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (smp_hps_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (smp_hps_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (smp_hps_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (smp_hps_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (smp_hps_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (smp_hps_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (smp_hps_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (smp_hps_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (smp_hps_h2f_lw_axi_master_rready) // .rready
);
hps_design_pio_0 pio_0 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pio_0_s1_address), // s1.address
.write_n (~mm_interconnect_0_pio_0_s1_write), // .write_n
.writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_pio_0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.out_port (ledr_export) // external_connection.export
);
hps_design_pll_0 pll_0 (
.refclk (clk_clk), // refclk.clk
.rst (~smp_hps_h2f_reset_reset), // reset.reset
.outclk_0 (pll_0_outclk0_clk), // outclk0.clk
.locked () // (terminated)
);
hps_design_mm_interconnect_0 mm_interconnect_0 (
.SMP_HPS_h2f_lw_axi_master_awid (smp_hps_h2f_lw_axi_master_awid), // SMP_HPS_h2f_lw_axi_master.awid
.SMP_HPS_h2f_lw_axi_master_awaddr (smp_hps_h2f_lw_axi_master_awaddr), // .awaddr
.SMP_HPS_h2f_lw_axi_master_awlen (smp_hps_h2f_lw_axi_master_awlen), // .awlen
.SMP_HPS_h2f_lw_axi_master_awsize (smp_hps_h2f_lw_axi_master_awsize), // .awsize
.SMP_HPS_h2f_lw_axi_master_awburst (smp_hps_h2f_lw_axi_master_awburst), // .awburst
.SMP_HPS_h2f_lw_axi_master_awlock (smp_hps_h2f_lw_axi_master_awlock), // .awlock
.SMP_HPS_h2f_lw_axi_master_awcache (smp_hps_h2f_lw_axi_master_awcache), // .awcache
.SMP_HPS_h2f_lw_axi_master_awprot (smp_hps_h2f_lw_axi_master_awprot), // .awprot
.SMP_HPS_h2f_lw_axi_master_awvalid (smp_hps_h2f_lw_axi_master_awvalid), // .awvalid
.SMP_HPS_h2f_lw_axi_master_awready (smp_hps_h2f_lw_axi_master_awready), // .awready
.SMP_HPS_h2f_lw_axi_master_wid (smp_hps_h2f_lw_axi_master_wid), // .wid
.SMP_HPS_h2f_lw_axi_master_wdata (smp_hps_h2f_lw_axi_master_wdata), // .wdata
.SMP_HPS_h2f_lw_axi_master_wstrb (smp_hps_h2f_lw_axi_master_wstrb), // .wstrb
.SMP_HPS_h2f_lw_axi_master_wlast (smp_hps_h2f_lw_axi_master_wlast), // .wlast
.SMP_HPS_h2f_lw_axi_master_wvalid (smp_hps_h2f_lw_axi_master_wvalid), // .wvalid
.SMP_HPS_h2f_lw_axi_master_wready (smp_hps_h2f_lw_axi_master_wready), // .wready
.SMP_HPS_h2f_lw_axi_master_bid (smp_hps_h2f_lw_axi_master_bid), // .bid
.SMP_HPS_h2f_lw_axi_master_bresp (smp_hps_h2f_lw_axi_master_bresp), // .bresp
.SMP_HPS_h2f_lw_axi_master_bvalid (smp_hps_h2f_lw_axi_master_bvalid), // .bvalid
.SMP_HPS_h2f_lw_axi_master_bready (smp_hps_h2f_lw_axi_master_bready), // .bready
.SMP_HPS_h2f_lw_axi_master_arid (smp_hps_h2f_lw_axi_master_arid), // .arid
.SMP_HPS_h2f_lw_axi_master_araddr (smp_hps_h2f_lw_axi_master_araddr), // .araddr
.SMP_HPS_h2f_lw_axi_master_arlen (smp_hps_h2f_lw_axi_master_arlen), // .arlen
.SMP_HPS_h2f_lw_axi_master_arsize (smp_hps_h2f_lw_axi_master_arsize), // .arsize
.SMP_HPS_h2f_lw_axi_master_arburst (smp_hps_h2f_lw_axi_master_arburst), // .arburst
.SMP_HPS_h2f_lw_axi_master_arlock (smp_hps_h2f_lw_axi_master_arlock), // .arlock
.SMP_HPS_h2f_lw_axi_master_arcache (smp_hps_h2f_lw_axi_master_arcache), // .arcache
.SMP_HPS_h2f_lw_axi_master_arprot (smp_hps_h2f_lw_axi_master_arprot), // .arprot
.SMP_HPS_h2f_lw_axi_master_arvalid (smp_hps_h2f_lw_axi_master_arvalid), // .arvalid
.SMP_HPS_h2f_lw_axi_master_arready (smp_hps_h2f_lw_axi_master_arready), // .arready
.SMP_HPS_h2f_lw_axi_master_rid (smp_hps_h2f_lw_axi_master_rid), // .rid
.SMP_HPS_h2f_lw_axi_master_rdata (smp_hps_h2f_lw_axi_master_rdata), // .rdata
.SMP_HPS_h2f_lw_axi_master_rresp (smp_hps_h2f_lw_axi_master_rresp), // .rresp
.SMP_HPS_h2f_lw_axi_master_rlast (smp_hps_h2f_lw_axi_master_rlast), // .rlast
.SMP_HPS_h2f_lw_axi_master_rvalid (smp_hps_h2f_lw_axi_master_rvalid), // .rvalid
.SMP_HPS_h2f_lw_axi_master_rready (smp_hps_h2f_lw_axi_master_rready), // .rready
.pll_0_outclk0_clk (pll_0_outclk0_clk), // pll_0_outclk0.clk
.pio_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // pio_0_reset_reset_bridge_in_reset.reset
.SMP_HPS_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // SMP_HPS_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.pio_0_s1_address (mm_interconnect_0_pio_0_s1_address), // pio_0_s1.address
.pio_0_s1_write (mm_interconnect_0_pio_0_s1_write), // .write
.pio_0_s1_readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.pio_0_s1_writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.pio_0_s1_chipselect (mm_interconnect_0_pio_0_s1_chipselect) // .chipselect
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~smp_hps_h2f_reset_reset), // reset_in0.reset
.clk (pll_0_outclk0_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~smp_hps_h2f_reset_reset), // reset_in0.reset
.clk (pll_0_outclk0_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINVLP_2_V
`define SKY130_FD_SC_LP__CLKINVLP_2_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog wrapper for clkinvlp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinvlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinvlp_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinvlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinvlp_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinvlp base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINVLP_2_V
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.reinterpret-f64.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.reinterpret-f64_tb.vcd");
$dumpvars(0, cpu_tb);
if(HAS_FPU && USE_64B) begin
#30
`assert(result, 64'hc000000000000000);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else if(HAS_FPU) begin
#12
`assert(trap, `NO_64B);
end
else begin
#12
`assert(trap, `NO_FPU);
end
$finish;
end
endmodule
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// A qa_wrapper with a buffer_AA.
module qa_wrapper
#(
parameter WDTH = 32
)
(
input wire clk,
input wire reset,
input wire [WDTH-1:0] in_data,
input wire in_nd,
output reg [WDTH-1:0] out_data,
output reg out_nd
);
wire rst_n;
assign rst_n = ~reset;
reg read_delete;
wire read_full;
wire [WDTH-1:0] read_data;
wire write_error;
wire read_error;
reg [`LOG_BURST_LENGTH-1:0] burst_counter;
buffer_AA #(WDTH, `BUFFER_LENGTH, `LOG_BUFFER_LENGTH)
the_buffer
(.clk(clk),
.rst_n(rst_n),
.write_strobe(in_nd),
.write_data(in_data),
.read_delete(read_delete),
.read_full(read_full),
.read_data(read_data),
.write_error(write_error),
.read_error(read_error)
);
always @ (posedge clk)
begin
if (!rst_n)
begin
read_delete <= 1'b0;
out_data <= {WDTH{1'b0}};
out_nd <= 1'b0;
burst_counter <= {`LOG_BURST_LENGTH{1'b0}};
end
else
if (write_error)
begin
out_nd <= 1'b1;
out_data <= `WRITEERRORCODE;
read_delete <= 1'b0;
end
else if (read_error)
begin
out_nd <= 1'b1;
out_data <= `READERRORCODE;
read_delete <= 1'b0;
end
else
begin
if (!read_delete && read_full && !(|burst_counter))
begin
read_delete <= 1'b1;
out_nd <= 1'b1;
out_data <= read_data;
end
else
begin
if (!read_delete && in_nd)
burst_counter <= burst_counter + 1;
read_delete <= 1'b0;
out_nd <= 1'b0;
end
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_LP_V
`define SKY130_FD_SC_LP__NOR4_LP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4_lp (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4_lp (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_LP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pc_cmp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`include "ifu.h"
`define GOOD_TRAP_COUNTER 32
module pc_cmp(/*AUTOARG*/
// Inputs
clk,
rst_l
);
input clk;
input rst_l;
// trap register
reg [31:0] finish_mask, diag_mask;
reg [39:0] good_trap[`GOOD_TRAP_COUNTER-1:0];
reg [39:0] bad_trap [`GOOD_TRAP_COUNTER-1:0];
reg [31:0] active_thread, back_thread, good_delay;
reg [31:0] good, good_for;
reg [7:0] done;
reg dum;
reg hit_bad;
integer max, time_tmp, trap_count;
//wire spc0_inst_done;
wire [1:0] spc0_thread_id;
wire [63:0] spc0_rtl_pc;
//wire spc1_inst_done;
wire [1:0] spc1_thread_id;
wire [63:0] spc1_rtl_pc;
//wire spc2_inst_done;
wire [1:0] spc2_thread_id;
wire [63:0] spc2_rtl_pc;
//wire spc3_inst_done;
wire [1:0] spc3_thread_id;
wire [63:0] spc3_rtl_pc;
//wire spc4_inst_done;
wire [1:0] spc4_thread_id;
wire [63:0] spc4_rtl_pc;
//wire spc5_inst_done;
wire [1:0] spc5_thread_id;
wire [63:0] spc5_rtl_pc;
//wire spc6_inst_done;
wire [1:0] spc6_thread_id;
wire [63:0] spc6_rtl_pc;
//wire spc7_inst_done;
wire [1:0] spc7_thread_id;
wire [63:0] spc7_rtl_pc;
wire sas_m0, sas_m1, sas_m2, sas_m3, sas_m4, sas_m5, sas_m6, sas_m7;
reg spc0_inst_done, spc1_inst_done, spc2_inst_done, spc3_inst_done,
spc4_inst_done, spc5_inst_done, spc6_inst_done, spc7_inst_done;
reg sas_def;
reg max_cycle;
reg [4:0] thread_status[31:0];
integer good_trap_count;
integer bad_trap_count;
//argment for stub
reg [7:0] stub_mask;
reg [7:0] stub_good;
reg good_flag;
//use this for the second reset.
initial begin
back_thread = 0;
good_delay = 0;
good_for = 0;
stub_good = 0;
if($test$plusargs("use_sas_tasks"))sas_def = 1;
else sas_def = 0;
if($test$plusargs("stop_2nd_good"))good_flag= 1;
else good_flag = 0;
max_cycle = 1;
if($test$plusargs("thread_timeout_off"))max_cycle = 0;
end
//-----------------------------------------------------------
// check bad trap
task check_bad_trap;
input [39:0] pc;
input [2:0] i;
input [4:0] thread;
integer l, j;
begin
if(active_thread[thread])begin
for(l = 0; l < bad_trap_count; l = l + 1)begin
if(bad_trap[l] == pc)begin
hit_bad = 1'b1;
good[l] = 1;
`TOP_MOD.diag_done = 1;
`ifdef INCLUDE_SAS_TASKS
if(sas_def && ($bw_list(`TOP_MOD.list_handle, 1) == 0))begin//wait until drain out.
`else
if(sas_def)begin
`endif $display("%0d: Info - > Hit Bad trap. spc(%0d) thread(%0d)", $time, i, l % 4);
`MONITOR_PATH.fail("HIT BAD TRAP");
end
else begin
$display("%0d: Info - > Hit Bad trap. spc(%0d) thread(%0d)", $time, i, l % 4);
`MONITOR_PATH.fail("HIT BAD TRAP");
end
end
end
end
end // if (active_thread[thread])
endtask // endtask
`ifdef INCLUDE_SAS_TASKS
task get_thread_status;
begin
`ifdef RTL_SPARC0
thread_status[0] = `IFUPATH0.swl.thrfsm0.thr_state;
thread_status[1] = `IFUPATH0.swl.thrfsm1.thr_state;
thread_status[2] = `IFUPATH0.swl.thrfsm2.thr_state;
thread_status[3] = `IFUPATH0.swl.thrfsm3.thr_state;
`endif
`ifdef RTL_SPARC1
thread_status[4] = `IFUPATH1.swl.thrfsm0.thr_state;
thread_status[5] = `IFUPATH1.swl.thrfsm1.thr_state;
thread_status[6] = `IFUPATH1.swl.thrfsm2.thr_state;
thread_status[7] = `IFUPATH1.swl.thrfsm3.thr_state;
`endif
`ifdef RTL_SPARC2
thread_status[8] = `IFUPATH2.swl.thrfsm0.thr_state;
thread_status[9] = `IFUPATH2.swl.thrfsm1.thr_state;
thread_status[10] = `IFUPATH2.swl.thrfsm2.thr_state;
thread_status[11] = `IFUPATH2.swl.thrfsm3.thr_state;
`endif
`ifdef RTL_SPARC3
thread_status[12] = `IFUPATH3.swl.thrfsm0.thr_state;
thread_status[13] = `IFUPATH3.swl.thrfsm1.thr_state;
thread_status[14] = `IFUPATH3.swl.thrfsm2.thr_state;
thread_status[15] = `IFUPATH3.swl.thrfsm3.thr_state;
`endif
`ifdef RTL_SPARC4
thread_status[16] = `IFUPATH4.swl.thrfsm0.thr_state;
thread_status[17] = `IFUPATH4.swl.thrfsm1.thr_state;
thread_status[18] = `IFUPATH4.swl.thrfsm2.thr_state;
thread_status[19] = `IFUPATH4.swl.thrfsm3.thr_state;
`endif
`ifdef RTL_SPARC5
thread_status[20] = `IFUPATH5.swl.thrfsm0.thr_state;
thread_status[21] = `IFUPATH5.swl.thrfsm1.thr_state;
thread_status[22] = `IFUPATH5.swl.thrfsm2.thr_state;
thread_status[23] = `IFUPATH5.swl.thrfsm3.thr_state;
`endif
`ifdef RTL_SPARC6
thread_status[24] = `IFUPATH6.swl.thrfsm0.thr_state;
thread_status[25] = `IFUPATH6.swl.thrfsm1.thr_state;
thread_status[26] = `IFUPATH6.swl.thrfsm2.thr_state;
thread_status[27] = `IFUPATH6.swl.thrfsm3.thr_state;
`endif
`ifdef RTL_SPARC7
thread_status[28] = `IFUPATH7.swl.thrfsm0.thr_state;
thread_status[29] = `IFUPATH7.swl.thrfsm1.thr_state;
thread_status[30] = `IFUPATH7.swl.thrfsm2.thr_state;
thread_status[31] = `IFUPATH7.swl.thrfsm3.thr_state;
`endif
end
endtask // get_thread_status
`endif
`ifdef RTL_SPARC0
`ifdef GATE_SIM_SPARC
assign sas_m0 = `INSTPATH0.runw_ff_u_dff_0_.d &
(~`INSTPATH0.exu_ifu_ecc_ce_m | `INSTPATH0.trapm_ff_u_dff_0_.q);
assign spc0_thread_id = {`PCPATH0.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH0.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH0.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH0.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc0_rtl_pc = `SPCPATH0.ifu_fdp.pc_w[47:0];
`else
assign sas_m0 = `INSTPATH0.inst_vld_m & ~`INSTPATH0.kill_thread_m &
~(`INSTPATH0.exu_ifu_ecc_ce_m & `INSTPATH0.inst_vld_m & ~`INSTPATH0.trap_m);
assign spc0_thread_id = `PCPATH0.fcl.sas_thrid_w;
assign spc0_rtl_pc = `SPCPATH0.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else // !ifdef RTL_SPARC0
assign spc0_rtl_pc = 'h0;
assign spc0_thread_id = 'h0;
assign sas_m0 = 0;
`endif // ifdef RTL_SPARC0
`ifdef RTL_SPARC1
`ifdef GATE_SIM_SPARC
assign sas_m1 = `INSTPATH1.runw_ff_u_dff_0_.d &
(~`INSTPATH1.exu_ifu_ecc_ce_m | `INSTPATH1.trapm_ff_u_dff_0_.q);
assign spc1_thread_id = {`PCPATH1.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH1.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH1.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH1.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc1_rtl_pc = `SPCPATH1.ifu_fdp.pc_w[47:0];
`else
assign spc1_thread_id = `PCPATH1.fcl.sas_thrid_w;
assign sas_m1 = `INSTPATH1.inst_vld_m & ~`INSTPATH1.kill_thread_m &
~(`INSTPATH1.exu_ifu_ecc_ce_m & `INSTPATH1.inst_vld_m & ~`INSTPATH1.trap_m);
assign spc1_rtl_pc = `SPCPATH1.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else // !ifdef RTL_SPARC1
assign spc1_rtl_pc = 'h0;
assign spc1_thread_id = 'h0;
assign sas_m1 = 0;
`endif // !ifdef RTL_SPARC1
`ifdef RTL_SPARC2
`ifdef GATE_SIM_SPARC
assign sas_m2 = `INSTPATH2.runw_ff_u_dff_0_.d &
(~`INSTPATH2.exu_ifu_ecc_ce_m | `INSTPATH2.trapm_ff_u_dff_0_.q);
assign spc2_thread_id = {`PCPATH2.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH2.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH2.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH2.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc2_rtl_pc = `SPCPATH2.ifu_fdp.pc_w[47:0];
`else
assign spc2_thread_id = `PCPATH2.fcl.sas_thrid_w;
assign sas_m2 = `INSTPATH2.inst_vld_m & ~`INSTPATH2.kill_thread_m &
~(`INSTPATH2.exu_ifu_ecc_ce_m & `INSTPATH2.inst_vld_m & ~`INSTPATH2.trap_m);
assign spc2_rtl_pc = `SPCPATH2.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else // !ifdef RTL_SPARC2
assign spc2_rtl_pc = 'h0;
assign spc2_thread_id = 'h0;
assign sas_m2 = 0;
`endif
`ifdef RTL_SPARC3
`ifdef GATE_SIM_SPARC
assign sas_m3 = `INSTPATH3.runw_ff_u_dff_0_.d &
(~`INSTPATH3.exu_ifu_ecc_ce_m | `INSTPATH3.trapm_ff_u_dff_0_.q);
assign spc3_thread_id = {`PCPATH3.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH3.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH3.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH3.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc3_rtl_pc = `SPCPATH3.ifu_fdp.pc_w[47:0];
`else
assign spc3_thread_id = `PCPATH3.fcl.sas_thrid_w;
assign sas_m3 = `INSTPATH3.inst_vld_m & ~`INSTPATH3.kill_thread_m &
~(`INSTPATH3.exu_ifu_ecc_ce_m & `INSTPATH3.inst_vld_m & ~`INSTPATH3.trap_m);
assign spc3_rtl_pc = `SPCPATH3.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else // !ifdef RTL_SPARC3
assign spc3_rtl_pc = 'h0;
assign spc3_thread_id = 'h0;
assign sas_m3 = 0;
`endif
`ifdef RTL_SPARC4
`ifdef GATE_SIM_SPARC
assign sas_m4 = `INSTPATH4.runw_ff_u_dff_0_.d &
(~`INSTPATH4.exu_ifu_ecc_ce_m | `INSTPATH4.trapm_ff_u_dff_0_.q);
assign spc4_thread_id = {`PCPATH4.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH4.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH4.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH4.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc4_rtl_pc = `SPCPATH4.ifu_fdp.pc_w[47:0];
`else
assign spc4_thread_id = `PCPATH4.fcl.sas_thrid_w;
assign sas_m4 = `INSTPATH4.inst_vld_m & ~`INSTPATH4.kill_thread_m &
~(`INSTPATH4.exu_ifu_ecc_ce_m & `INSTPATH4.inst_vld_m & ~`INSTPATH4.trap_m);
assign spc4_rtl_pc = `SPCPATH4.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else
//assign spc4_inst_done = 'h0;
assign spc4_rtl_pc = 'h0;
assign spc4_thread_id = 'h0;
assign sas_m4 = 0;
`endif
`ifdef RTL_SPARC5
`ifdef GATE_SIM_SPARC
assign sas_m5 = `INSTPATH5.runw_ff_u_dff_0_.d &
(~`INSTPATH5.exu_ifu_ecc_ce_m | `INSTPATH5.trapm_ff_u_dff_0_.q);
assign spc5_thread_id = {`PCPATH5.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH5.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH5.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH5.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc5_rtl_pc = `SPCPATH5.ifu_fdp.pc_w[47:0];
`else
assign spc5_thread_id = `PCPATH5.fcl.sas_thrid_w;
assign sas_m5 = `INSTPATH5.inst_vld_m & ~`INSTPATH5.kill_thread_m &
~(`INSTPATH5.exu_ifu_ecc_ce_m & `INSTPATH5.inst_vld_m & ~`INSTPATH5.trap_m);
assign spc5_rtl_pc = `SPCPATH5.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else
assign spc5_rtl_pc = 'h0;
assign spc5_thread_id = 'h0;
assign sas_m5 = 0;
`endif
`ifdef RTL_SPARC6
`ifdef GATE_SIM_SPARC
assign sas_m6 = `INSTPATH6.runw_ff_u_dff_0_.d &
(~`INSTPATH6.exu_ifu_ecc_ce_m | `INSTPATH6.trapm_ff_u_dff_0_.q);
assign spc6_thread_id = {`PCPATH6.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH6.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH6.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH6.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc6_rtl_pc = `SPCPATH6.ifu_fdp.pc_w[47:0];
`else
assign spc6_thread_id = `PCPATH6.fcl.sas_thrid_w;
assign sas_m6 = `INSTPATH6.inst_vld_m & ~`INSTPATH6.kill_thread_m &
~(`INSTPATH6.exu_ifu_ecc_ce_m & `INSTPATH6.inst_vld_m & ~`INSTPATH6.trap_m);
assign spc6_rtl_pc = `SPCPATH6.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else
assign spc6_rtl_pc = 'h0;
assign spc6_thread_id = 'h0;
assign sas_m6 = 0;
`endif
`ifdef RTL_SPARC7
`ifdef GATE_SIM_SPARC
assign sas_m7 = `INSTPATH7.runw_ff_u_dff_0_.d &
(~`INSTPATH7.exu_ifu_ecc_ce_m | `INSTPATH7.trapm_ff_u_dff_0_.q);
assign spc7_thread_id = {`PCPATH7.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH7.ifu_fcl.thrw_reg_q_tmp_2_,
`PCPATH7.ifu_fcl.thrw_reg_q_tmp_3_ | `PCPATH7.ifu_fcl.thrw_reg_q_tmp_1_};
assign spc7_rtl_pc = `SPCPATH7.ifu_fdp.pc_w[47:0];
`else
assign spc7_thread_id = `PCPATH7.fcl.sas_thrid_w;
assign sas_m7 = `INSTPATH7.inst_vld_m & ~`INSTPATH7.kill_thread_m &
~(`INSTPATH7.exu_ifu_ecc_ce_m & `INSTPATH7.inst_vld_m & ~`INSTPATH7.trap_m);
assign spc7_rtl_pc = `SPCPATH7.ifu.fdp.pc_w[47:0];
`endif // ifdef GATE_SIM_SPARC
`else
assign spc7_rtl_pc = 'h0;
assign spc7_thread_id = 'h0;
assign sas_m7 = 0;
`endif // !ifdef SP7
reg [63:0] spc0_phy_pc_w, spc1_phy_pc_w, spc2_phy_pc_w, spc3_phy_pc_w,
spc4_phy_pc_w, spc5_phy_pc_w, spc6_phy_pc_w, spc7_phy_pc_w;
`ifdef RTL_SPARC0
reg [63:0] spc0_phy_pc_d, spc0_phy_pc_e, spc0_phy_pc_m,
spc0_t0pc_s, spc0_t1pc_s, spc0_t2pc_s, spc0_t3pc_s ;
reg [3:0] spc0_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc0_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc0_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc0_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs0 = spc0_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf0 = spc0_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd0 = spc0_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce0 = spc0_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc0_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc0_imiss_paddr_s = {`IFQDP0.itlb_ifq_paddr_s, `IFQDP0.lcl_paddr_s, 2'b0} ;
`else
assign spc0_imiss_paddr_s = `IFQDP0.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif // `ifdef RTL_SPARC0
`ifdef RTL_SPARC1
reg [63:0] spc1_phy_pc_d, spc1_phy_pc_e, spc1_phy_pc_m,
spc1_t0pc_s, spc1_t1pc_s, spc1_t2pc_s, spc1_t3pc_s;
reg [3:0] spc1_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc1_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc1_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc1_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs1 = spc1_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf1 = spc1_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd1 = spc1_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce1 = spc1_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc1_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc1_imiss_paddr_s = {`IFQDP1.itlb_ifq_paddr_s, `IFQDP1.lcl_paddr_s, 2'b0} ;
`else
assign spc1_imiss_paddr_s = `IFQDP1.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif
`ifdef RTL_SPARC2
reg [63:0] spc2_phy_pc_d, spc2_phy_pc_e, spc2_phy_pc_m,
spc2_t0pc_s, spc2_t1pc_s, spc2_t2pc_s, spc2_t3pc_s;
reg [3:0] spc2_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc2_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc2_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc2_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs2 = spc2_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf2 = spc2_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd2 = spc2_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce2 = spc2_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc2_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc2_imiss_paddr_s = {`IFQDP2.itlb_ifq_paddr_s, `IFQDP2.lcl_paddr_s, 2'b0} ;
`else
assign spc2_imiss_paddr_s = `IFQDP2.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif // `ifdef RTL_SPARC0
`ifdef RTL_SPARC3
reg [63:0] spc3_phy_pc_d, spc3_phy_pc_e, spc3_phy_pc_m,
spc3_t0pc_s, spc3_t1pc_s, spc3_t2pc_s, spc3_t3pc_s;
reg [3:0] spc3_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc3_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc3_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc3_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs3 = spc3_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf3 = spc3_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd3 = spc3_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce3 = spc3_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc3_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc3_imiss_paddr_s = {`IFQDP3.itlb_ifq_paddr_s, `IFQDP3.lcl_paddr_s, 2'b0} ;
`else
assign spc3_imiss_paddr_s = `IFQDP3.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif // `ifdef RTL_SPARC3
`ifdef RTL_SPARC4
reg [63:0] spc4_phy_pc_d, spc4_phy_pc_e, spc4_phy_pc_m,
spc4_t0pc_s, spc4_t1pc_s, spc4_t2pc_s, spc4_t3pc_s;
reg [3:0] spc4_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc4_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc4_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc4_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs4 = spc4_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf4 = spc4_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd4 = spc4_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce4 = spc4_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc4_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc4_imiss_paddr_s = {`IFQDP4.itlb_ifq_paddr_s, `IFQDP4.lcl_paddr_s, 2'b0} ;
`else
assign spc4_imiss_paddr_s = `IFQDP4.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif // `ifdef RTL_SPARC4
`ifdef RTL_SPARC5
reg [63:0] spc5_phy_pc_d, spc5_phy_pc_e, spc5_phy_pc_m,
spc5_t0pc_s, spc5_t1pc_s, spc5_t2pc_s, spc5_t3pc_s;
reg [3:0] spc5_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc5_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc5_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc5_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs5 = spc5_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf5 = spc5_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd5 = spc5_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce5 = spc5_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc5_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc5_imiss_paddr_s = {`IFQDP5.itlb_ifq_paddr_s, `IFQDP5.lcl_paddr_s, 2'b0} ;
`else
assign spc5_imiss_paddr_s = `IFQDP5.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif // `ifdef RTL_SPARC5
`ifdef RTL_SPARC6
reg [63:0] spc6_phy_pc_d, spc6_phy_pc_e, spc6_phy_pc_m,
spc6_t0pc_s, spc6_t1pc_s, spc6_t2pc_s, spc6_t3pc_s;
reg [3:0] spc6_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc6_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc6_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc6_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs6 = spc6_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf6 = spc6_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd6 = spc6_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce6 = spc6_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc6_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc6_imiss_paddr_s = {`IFQDP6.itlb_ifq_paddr_s, `IFQDP6.lcl_paddr_s, 2'b0} ;
`else
assign spc6_imiss_paddr_s = `IFQDP6.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif // `ifdef RTL_SPARC6
`ifdef RTL_SPARC7
reg [63:0] spc7_phy_pc_d, spc7_phy_pc_e, spc7_phy_pc_m,
spc7_t0pc_s, spc7_t1pc_s, spc7_t2pc_s, spc7_t3pc_s;
reg [3:0] spc7_fcl_fdp_nextpcs_sel_pcf_f_l_e,
spc7_fcl_fdp_nextpcs_sel_pcs_f_l_e,
spc7_fcl_fdp_nextpcs_sel_pcd_f_l_e,
spc7_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [3:0] pcs7 = spc7_fcl_fdp_nextpcs_sel_pcs_f_l_e;
wire [3:0] pcf7 = spc7_fcl_fdp_nextpcs_sel_pcf_f_l_e;
wire [3:0] pcd7 = spc7_fcl_fdp_nextpcs_sel_pcd_f_l_e;
wire [3:0] pce7 = spc7_fcl_fdp_nextpcs_sel_pce_f_l_e;
wire [63:0] spc7_imiss_paddr_s ;
`ifdef GATE_SIM_SPARC
assign spc7_imiss_paddr_s = {`IFQDP7.itlb_ifq_paddr_s, `IFQDP7.lcl_paddr_s, 2'b0} ;
`else
assign spc7_imiss_paddr_s = `IFQDP7.imiss_paddr_s ;
`endif // GATE_SIM_SPARC
`endif // `ifdef RTL_SPARC7
always @(posedge clk) begin
`ifdef RTL_SPARC0
//done
spc0_inst_done <= sas_m0;
//next pc select
spc0_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH0.fcl_fdp_nextpcs_sel_pcs_f_l;
spc0_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH0.fcl_fdp_nextpcs_sel_pcf_f_l;
spc0_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH0.fcl_fdp_nextpcs_sel_pcd_f_l;
spc0_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH0.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if(pcf0[0] == 0)spc0_t0pc_s <= spc0_imiss_paddr_s;
else if(pcs0[0] == 0)spc0_t0pc_s <= spc0_t0pc_s;
else if(pcd0[0] == 0)spc0_t0pc_s <= spc0_phy_pc_e;
else if(pce0[0] == 0)spc0_t0pc_s <= spc0_phy_pc_m;
if(pcf0[1] == 0)spc0_t1pc_s <= spc0_imiss_paddr_s;
else if(pcs0[1] == 0)spc0_t1pc_s <= spc0_t1pc_s;
else if(pcd0[1] == 0)spc0_t1pc_s <= spc0_phy_pc_e;
else if(pce0[1] == 0)spc0_t1pc_s <= spc0_phy_pc_m;
if(pcf0[2] == 0)spc0_t2pc_s <= spc0_imiss_paddr_s;
else if(pcs0[2] == 0)spc0_t2pc_s <= spc0_t2pc_s;
else if(pcd0[2] == 0)spc0_t2pc_s <= spc0_phy_pc_e;
else if(pce0[2] == 0)spc0_t2pc_s <= spc0_phy_pc_m;
if(pcf0[3] == 0)spc0_t3pc_s <= spc0_imiss_paddr_s;
else if(pcs0[3] == 0)spc0_t3pc_s <= spc0_t3pc_s;
else if(pcd0[3] == 0)spc0_t3pc_s <= spc0_phy_pc_e;
else if(pce0[3] == 0)spc0_t3pc_s <= spc0_phy_pc_m;
if(~`DTUPATH0.fcl_fdp_thr_s2_l[0]) spc0_phy_pc_d <= pcf0[0] ? spc0_t0pc_s : spc0_imiss_paddr_s;
else if(~`DTUPATH0.fcl_fdp_thr_s2_l[1])spc0_phy_pc_d <= pcf0[1] ? spc0_t1pc_s : spc0_imiss_paddr_s;
else if(~`DTUPATH0.fcl_fdp_thr_s2_l[2])spc0_phy_pc_d <= pcf0[2] ? spc0_t2pc_s : spc0_imiss_paddr_s;
else if(~`DTUPATH0.fcl_fdp_thr_s2_l[3])spc0_phy_pc_d <= pcf0[3] ? spc0_t3pc_s : spc0_imiss_paddr_s;
spc0_phy_pc_e <= spc0_phy_pc_d;
spc0_phy_pc_m <= spc0_phy_pc_e;
spc0_phy_pc_w <= {{8{spc0_phy_pc_m[39]}}, spc0_phy_pc_m[39:0]};
if(spc0_inst_done &&
active_thread[{3'b000,spc0_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH0.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b000, spc0_thread_id[1:0], `DTUPATH0.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC0
`ifdef RTL_SPARC1
//done
spc1_inst_done <= sas_m1;
//next pc select
spc1_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH1.fcl_fdp_nextpcs_sel_pcs_f_l;
spc1_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH1.fcl_fdp_nextpcs_sel_pcf_f_l;
spc1_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH1.fcl_fdp_nextpcs_sel_pcd_f_l;
spc1_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH1.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if( pcf1[0] == 0)spc1_t0pc_s <= spc1_imiss_paddr_s;
else if(pcs1[0] == 0)spc1_t0pc_s <= spc1_t0pc_s;
else if(pcd1[0] == 0)spc1_t0pc_s <= spc1_phy_pc_e;
else if(pce1[0] == 0)spc1_t0pc_s <= spc1_phy_pc_m;
if( pcf1[1] == 0)spc1_t1pc_s <= spc1_imiss_paddr_s;
else if(pcs1[1] == 0)spc1_t1pc_s <= spc1_t1pc_s;
else if(pcd1[1] == 0)spc1_t1pc_s <= spc1_phy_pc_e;
else if(pce1[1] == 0)spc1_t1pc_s <= spc1_phy_pc_m;
if( pcf1[2] == 0)spc1_t2pc_s <= spc1_imiss_paddr_s;
else if(pcs1[2] == 0)spc1_t2pc_s <= spc1_t2pc_s;
else if(pcd1[2] == 0)spc1_t2pc_s <= spc1_phy_pc_e;
else if(pce1[2] == 0)spc1_t2pc_s <= spc1_phy_pc_m;
if( pcf1[3] == 0)spc1_t3pc_s <= spc1_imiss_paddr_s;
else if(pcs1[3] == 0)spc1_t3pc_s <= spc1_t3pc_s;
else if(pcd1[3] == 0)spc1_t3pc_s <= spc1_phy_pc_e;
else if(pce1[3] == 0)spc1_t3pc_s <= spc1_phy_pc_m;
if( ~`DTUPATH1.fcl_fdp_thr_s2_l[0])spc1_phy_pc_d <= pcf1[0] ? spc1_t0pc_s : spc1_imiss_paddr_s;
else if(~`DTUPATH1.fcl_fdp_thr_s2_l[1])spc1_phy_pc_d <= pcf1[1] ? spc1_t1pc_s : spc1_imiss_paddr_s;
else if(~`DTUPATH1.fcl_fdp_thr_s2_l[2])spc1_phy_pc_d <= pcf1[2] ? spc1_t2pc_s : spc1_imiss_paddr_s;
else if(~`DTUPATH1.fcl_fdp_thr_s2_l[3])spc1_phy_pc_d <= pcf1[3] ? spc1_t3pc_s : spc1_imiss_paddr_s;
spc1_phy_pc_e <= spc1_phy_pc_d;
spc1_phy_pc_m <= spc1_phy_pc_e;
spc1_phy_pc_w <= {{8{spc1_phy_pc_m[39]}}, spc1_phy_pc_m[39:0]};
if(spc1_inst_done &&
active_thread[{3'b001,spc1_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH1.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b001, spc1_thread_id[1:0], `DTUPATH1.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC1
`ifdef RTL_SPARC2
//done
spc2_inst_done <= sas_m2;
//next pc select
spc2_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH2.fcl_fdp_nextpcs_sel_pcs_f_l;
spc2_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH2.fcl_fdp_nextpcs_sel_pcf_f_l;
spc2_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH2.fcl_fdp_nextpcs_sel_pcd_f_l;
spc2_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH2.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if(pcf2[0] == 0)spc2_t0pc_s <= spc2_imiss_paddr_s;
else if(pcs2[0] == 0)spc2_t0pc_s <= spc2_t0pc_s;
else if(pcd2[0] == 0)spc2_t0pc_s <= spc2_phy_pc_e;
else if(pce2[0] == 0)spc2_t0pc_s <= spc2_phy_pc_m;
if(pcf2[1] == 0)spc2_t1pc_s <= spc2_imiss_paddr_s;
else if(pcs2[1] == 0)spc2_t1pc_s <= spc2_t1pc_s;
else if(pcd2[1] == 0)spc2_t1pc_s <= spc2_phy_pc_e;
else if(pce2[1] == 0)spc2_t1pc_s <= spc2_phy_pc_m;
if(pcf2[2] == 0)spc2_t2pc_s <= spc2_imiss_paddr_s;
else if(pcs2[2] == 0)spc2_t2pc_s <= spc2_t2pc_s;
else if(pcd2[2] == 0)spc2_t2pc_s <= spc2_phy_pc_e;
else if(pce2[2] == 0)spc2_t2pc_s <= spc2_phy_pc_m;
if(pcf2[3] == 0)spc2_t3pc_s <= spc2_imiss_paddr_s;
else if(pcs2[3] == 0)spc2_t3pc_s <= spc2_t3pc_s;
else if(pcd2[3] == 0)spc2_t3pc_s <= spc2_phy_pc_e;
else if(pce2[3] == 0)spc2_t3pc_s <= spc2_phy_pc_m;
if(~`DTUPATH2.fcl_fdp_thr_s2_l[0]) spc2_phy_pc_d <= pcf2[0] ? spc2_t0pc_s : spc2_imiss_paddr_s;
else if(~`DTUPATH2.fcl_fdp_thr_s2_l[1])spc2_phy_pc_d <= pcf2[1] ? spc2_t1pc_s : spc2_imiss_paddr_s;
else if(~`DTUPATH2.fcl_fdp_thr_s2_l[2])spc2_phy_pc_d <= pcf2[2] ? spc2_t2pc_s : spc2_imiss_paddr_s;
else if(~`DTUPATH2.fcl_fdp_thr_s2_l[3])spc2_phy_pc_d <= pcf2[3] ? spc2_t3pc_s : spc2_imiss_paddr_s;
spc2_phy_pc_e <= spc2_phy_pc_d;
spc2_phy_pc_m <= spc2_phy_pc_e;
spc2_phy_pc_w <= {{8{spc2_phy_pc_m[39]}}, spc2_phy_pc_m[39:0]};
if(spc2_inst_done &&
active_thread[{3'b010,spc2_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH2.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b010, spc2_thread_id[1:0], `DTUPATH2.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC2
`ifdef RTL_SPARC3
//done
spc3_inst_done <= sas_m3;
//next pc select
spc3_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH3.fcl_fdp_nextpcs_sel_pcs_f_l;
spc3_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH3.fcl_fdp_nextpcs_sel_pcf_f_l;
spc3_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH3.fcl_fdp_nextpcs_sel_pcd_f_l;
spc3_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH3.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if(pcf3[0] == 0)spc3_t0pc_s <= spc3_imiss_paddr_s;
else if(pcs3[0] == 0)spc3_t0pc_s <= spc3_t0pc_s;
else if(pcd3[0] == 0)spc3_t0pc_s <= spc3_phy_pc_e;
else if(pce3[0] == 0)spc3_t0pc_s <= spc3_phy_pc_m;
if(pcf3[1] == 0)spc3_t1pc_s <= spc3_imiss_paddr_s;
else if(pcs3[1] == 0)spc3_t1pc_s <= spc3_t1pc_s;
else if(pcd3[1] == 0)spc3_t1pc_s <= spc3_phy_pc_e;
else if(pce3[1] == 0)spc3_t1pc_s <= spc3_phy_pc_m;
if(pcf3[2] == 0)spc3_t2pc_s <= spc3_imiss_paddr_s;
else if(pcs3[2] == 0)spc3_t2pc_s <= spc3_t2pc_s;
else if(pcd3[2] == 0)spc3_t2pc_s <= spc3_phy_pc_e;
else if(pce3[2] == 0)spc3_t2pc_s <= spc3_phy_pc_m;
if(pcf3[3] == 0)spc3_t3pc_s <= spc3_imiss_paddr_s;
else if(pcs3[3] == 0)spc3_t3pc_s <= spc3_t3pc_s;
else if(pcd3[3] == 0)spc3_t3pc_s <= spc3_phy_pc_e;
else if(pce3[3] == 0)spc3_t3pc_s <= spc3_phy_pc_m;
if(~`DTUPATH3.fcl_fdp_thr_s2_l[0]) spc3_phy_pc_d <= pcf3[0] ? spc3_t0pc_s : spc3_imiss_paddr_s;
else if(~`DTUPATH3.fcl_fdp_thr_s2_l[1])spc3_phy_pc_d <= pcf3[1] ? spc3_t1pc_s : spc3_imiss_paddr_s;
else if(~`DTUPATH3.fcl_fdp_thr_s2_l[2])spc3_phy_pc_d <= pcf3[2] ? spc3_t2pc_s : spc3_imiss_paddr_s;
else if(~`DTUPATH3.fcl_fdp_thr_s2_l[3])spc3_phy_pc_d <= pcf3[3] ? spc3_t3pc_s : spc3_imiss_paddr_s;
spc3_phy_pc_e <= spc3_phy_pc_d;
spc3_phy_pc_m <= spc3_phy_pc_e;
spc3_phy_pc_w <= {{8{spc3_phy_pc_m[39]}}, spc3_phy_pc_m[39:0]};
if(spc3_inst_done &&
active_thread[{3'b011,spc3_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH3.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b011, spc3_thread_id[1:0], `DTUPATH3.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC3
`ifdef RTL_SPARC4
//done
spc4_inst_done <= sas_m4;
//next pc select
spc4_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH4.fcl_fdp_nextpcs_sel_pcs_f_l;
spc4_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH4.fcl_fdp_nextpcs_sel_pcf_f_l;
spc4_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH4.fcl_fdp_nextpcs_sel_pcd_f_l;
spc4_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH4.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if(pcf4[0] == 0)spc4_t0pc_s <= spc4_imiss_paddr_s;
else if(pcs4[0] == 0)spc4_t0pc_s <= spc4_t0pc_s;
else if(pcd4[0] == 0)spc4_t0pc_s <= spc4_phy_pc_e;
else if(pce4[0] == 0)spc4_t0pc_s <= spc4_phy_pc_m;
if(pcf4[1] == 0)spc4_t1pc_s <= spc4_imiss_paddr_s;
else if(pcs4[1] == 0)spc4_t1pc_s <= spc4_t1pc_s;
else if(pcd4[1] == 0)spc4_t1pc_s <= spc4_phy_pc_e;
else if(pce4[1] == 0)spc4_t1pc_s <= spc4_phy_pc_m;
if(pcf4[2] == 0)spc4_t2pc_s <= spc4_imiss_paddr_s;
else if(pcs4[2] == 0)spc4_t2pc_s <= spc4_t2pc_s;
else if(pcd4[2] == 0)spc4_t2pc_s <= spc4_phy_pc_e;
else if(pce4[2] == 0)spc4_t2pc_s <= spc4_phy_pc_m;
if(pcf4[3] == 0)spc4_t3pc_s <= spc4_imiss_paddr_s;
else if(pcs4[3] == 0)spc4_t3pc_s <= spc4_t3pc_s;
else if(pcd4[3] == 0)spc4_t3pc_s <= spc4_phy_pc_e;
else if(pce4[3] == 0)spc4_t3pc_s <= spc4_phy_pc_m;
if(~`DTUPATH4.fcl_fdp_thr_s2_l[0]) spc4_phy_pc_d <= pcf4[0] ? spc4_t0pc_s : spc4_imiss_paddr_s;
else if(~`DTUPATH4.fcl_fdp_thr_s2_l[1])spc4_phy_pc_d <= pcf4[1] ? spc4_t1pc_s : spc4_imiss_paddr_s;
else if(~`DTUPATH4.fcl_fdp_thr_s2_l[2])spc4_phy_pc_d <= pcf4[2] ? spc4_t2pc_s : spc4_imiss_paddr_s;
else if(~`DTUPATH4.fcl_fdp_thr_s2_l[3])spc4_phy_pc_d <= pcf4[3] ? spc4_t3pc_s : spc4_imiss_paddr_s;
spc4_phy_pc_e <= spc4_phy_pc_d;
spc4_phy_pc_m <= spc4_phy_pc_e;
spc4_phy_pc_w <= {{8{spc4_phy_pc_m[39]}}, spc4_phy_pc_m[39:0]};
if(spc4_inst_done &&
active_thread[{3'b100,spc4_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH4.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b100, spc4_thread_id[1:0], `DTUPATH4.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC4
`ifdef RTL_SPARC5
//done
spc5_inst_done <= sas_m5;
//next pc select
spc5_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH5.fcl_fdp_nextpcs_sel_pcs_f_l;
spc5_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH5.fcl_fdp_nextpcs_sel_pcf_f_l;
spc5_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH5.fcl_fdp_nextpcs_sel_pcd_f_l;
spc5_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH5.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if(pcf5[0] == 0)spc5_t0pc_s <= spc5_imiss_paddr_s;
else if(pcs5[0] == 0)spc5_t0pc_s <= spc5_t0pc_s;
else if(pcd5[0] == 0)spc5_t0pc_s <= spc5_phy_pc_e;
else if(pce5[0] == 0)spc5_t0pc_s <= spc5_phy_pc_m;
if(pcf5[1] == 0)spc5_t1pc_s <= spc5_imiss_paddr_s;
else if(pcs5[1] == 0)spc5_t1pc_s <= spc5_t1pc_s;
else if(pcd5[1] == 0)spc5_t1pc_s <= spc5_phy_pc_e;
else if(pce5[1] == 0)spc5_t1pc_s <= spc5_phy_pc_m;
if(pcf5[2] == 0)spc5_t2pc_s <= spc5_imiss_paddr_s;
else if(pcs5[2] == 0)spc5_t2pc_s <= spc5_t2pc_s;
else if(pcd5[2] == 0)spc5_t2pc_s <= spc5_phy_pc_e;
else if(pce5[2] == 0)spc5_t2pc_s <= spc5_phy_pc_m;
if(pcf5[3] == 0)spc5_t3pc_s <= spc5_imiss_paddr_s;
else if(pcs5[3] == 0)spc5_t3pc_s <= spc5_t3pc_s;
else if(pcd5[3] == 0)spc5_t3pc_s <= spc5_phy_pc_e;
else if(pce5[3] == 0)spc5_t3pc_s <= spc5_phy_pc_m;
if(~`DTUPATH5.fcl_fdp_thr_s2_l[0]) spc5_phy_pc_d <= pcf5[0] ? spc5_t0pc_s : spc5_imiss_paddr_s;
else if(~`DTUPATH5.fcl_fdp_thr_s2_l[1])spc5_phy_pc_d <= pcf5[1] ? spc5_t1pc_s : spc5_imiss_paddr_s;
else if(~`DTUPATH5.fcl_fdp_thr_s2_l[2])spc5_phy_pc_d <= pcf5[2] ? spc5_t2pc_s : spc5_imiss_paddr_s;
else if(~`DTUPATH5.fcl_fdp_thr_s2_l[3])spc5_phy_pc_d <= pcf5[3] ? spc5_t3pc_s : spc5_imiss_paddr_s;
spc5_phy_pc_e <= spc5_phy_pc_d;
spc5_phy_pc_m <= spc5_phy_pc_e;
spc5_phy_pc_w <= {{8{spc5_phy_pc_m[39]}}, spc5_phy_pc_m[39:0]};
if(spc5_inst_done &&
active_thread[{3'b101,spc5_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH5.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b101, spc5_thread_id[1:0], `DTUPATH5.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC5
`ifdef RTL_SPARC6
//done
spc6_inst_done <= sas_m6;
//next pc select
spc6_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH6.fcl_fdp_nextpcs_sel_pcs_f_l;
spc6_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH6.fcl_fdp_nextpcs_sel_pcf_f_l;
spc6_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH6.fcl_fdp_nextpcs_sel_pcd_f_l;
spc6_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH6.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if(pcf6[0] == 0)spc6_t0pc_s <= spc6_imiss_paddr_s;
else if(pcs6[0] == 0)spc6_t0pc_s <= spc6_t0pc_s;
else if(pcd6[0] == 0)spc6_t0pc_s <= spc6_phy_pc_e;
else if(pce6[0] == 0)spc6_t0pc_s <= spc6_phy_pc_m;
if(pcf6[1] == 0)spc6_t1pc_s <= spc6_imiss_paddr_s;
else if(pcs6[1] == 0)spc6_t1pc_s <= spc6_t1pc_s;
else if(pcd6[1] == 0)spc6_t1pc_s <= spc6_phy_pc_e;
else if(pce6[1] == 0)spc6_t1pc_s <= spc6_phy_pc_m;
if(pcf6[2] == 0)spc6_t2pc_s <= spc6_imiss_paddr_s;
else if(pcs6[2] == 0)spc6_t2pc_s <= spc6_t2pc_s;
else if(pcd6[2] == 0)spc6_t2pc_s <= spc6_phy_pc_e;
else if(pce6[2] == 0)spc6_t2pc_s <= spc6_phy_pc_m;
if(pcf6[3] == 0)spc6_t3pc_s <= spc6_imiss_paddr_s;
else if(pcs6[3] == 0)spc6_t3pc_s <= spc6_t3pc_s;
else if(pcd6[3] == 0)spc6_t3pc_s <= spc6_phy_pc_e;
else if(pce6[3] == 0)spc6_t3pc_s <= spc6_phy_pc_m;
if(~`DTUPATH6.fcl_fdp_thr_s2_l[0]) spc6_phy_pc_d <= pcf6[0] ? spc6_t0pc_s : spc6_imiss_paddr_s;
else if(~`DTUPATH6.fcl_fdp_thr_s2_l[1])spc6_phy_pc_d <= pcf6[1] ? spc6_t1pc_s : spc6_imiss_paddr_s;
else if(~`DTUPATH6.fcl_fdp_thr_s2_l[2])spc6_phy_pc_d <= pcf6[2] ? spc6_t2pc_s : spc6_imiss_paddr_s;
else if(~`DTUPATH6.fcl_fdp_thr_s2_l[3])spc6_phy_pc_d <= pcf6[3] ? spc6_t3pc_s : spc6_imiss_paddr_s;
spc6_phy_pc_e <= spc6_phy_pc_d;
spc6_phy_pc_m <= spc6_phy_pc_e;
spc6_phy_pc_w <= {{8{spc6_phy_pc_m[39]}}, spc6_phy_pc_m[39:0]};
if(spc6_inst_done &&
active_thread[{3'b110,spc6_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH6.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b110, spc6_thread_id[1:0], `DTUPATH6.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC6
`ifdef RTL_SPARC7
//done
spc7_inst_done <= sas_m7;
spc7_fcl_fdp_nextpcs_sel_pcs_f_l_e <= `DTUPATH7.fcl_fdp_nextpcs_sel_pcs_f_l;
spc7_fcl_fdp_nextpcs_sel_pcf_f_l_e <= `DTUPATH7.fcl_fdp_nextpcs_sel_pcf_f_l;
spc7_fcl_fdp_nextpcs_sel_pcd_f_l_e <= `DTUPATH7.fcl_fdp_nextpcs_sel_pcd_f_l;
spc7_fcl_fdp_nextpcs_sel_pce_f_l_e <= `DTUPATH7.fcl_fdp_nextpcs_sel_pce_f_l;
//pipe physical pc
if(pcf7[0] == 0)spc7_t0pc_s <= spc7_imiss_paddr_s;
else if(pcs7[0] == 0)spc7_t0pc_s <= spc7_t0pc_s;
else if(pcd7[0] == 0)spc7_t0pc_s <= spc7_phy_pc_e;
else if(pce7[0] == 0)spc7_t0pc_s <= spc7_phy_pc_m;
if(pcf7[1] == 0)spc7_t1pc_s <= spc7_imiss_paddr_s;
else if(pcs7[1] == 0)spc7_t1pc_s <= spc7_t1pc_s;
else if(pcd7[1] == 0)spc7_t1pc_s <= spc7_phy_pc_e;
else if(pce7[1] == 0)spc7_t1pc_s <= spc7_phy_pc_m;
if(pcf7[2] == 0)spc7_t2pc_s <= spc7_imiss_paddr_s;
else if(pcs7[2] == 0)spc7_t2pc_s <= spc7_t2pc_s;
else if(pcd7[2] == 0)spc7_t2pc_s <= spc7_phy_pc_e;
else if(pce7[2] == 0)spc7_t2pc_s <= spc7_phy_pc_m;
if(pcf7[3] == 0)spc7_t3pc_s <= spc7_imiss_paddr_s;
else if(pcs7[3] == 0)spc7_t3pc_s <= spc7_t3pc_s;
else if(pcd7[3] == 0)spc7_t3pc_s <= spc7_phy_pc_e;
else if(pce7[3] == 0)spc7_t3pc_s <= spc7_phy_pc_m;
if(~`DTUPATH7.fcl_fdp_thr_s2_l[0]) spc7_phy_pc_d <= pcf7[0] ? spc7_t0pc_s : spc7_imiss_paddr_s;
else if(~`DTUPATH7.fcl_fdp_thr_s2_l[1])spc7_phy_pc_d <= pcf7[1] ? spc7_t1pc_s : spc7_imiss_paddr_s;
else if(~`DTUPATH7.fcl_fdp_thr_s2_l[2])spc7_phy_pc_d <= pcf7[2] ? spc7_t2pc_s : spc7_imiss_paddr_s;
else if(~`DTUPATH7.fcl_fdp_thr_s2_l[3])spc7_phy_pc_d <= pcf7[3] ? spc7_t3pc_s : spc7_imiss_paddr_s;
spc7_phy_pc_e <= spc7_phy_pc_d;
spc7_phy_pc_m <= spc7_phy_pc_e;
spc7_phy_pc_w <= {{8{spc7_phy_pc_m[39]}}, spc7_phy_pc_m[39:0]};
if(spc7_inst_done &&
active_thread[{3'b111,spc7_thread_id[1:0]}])begin
/*
if(0 & $x_checker(`DTUPATH7.pc_w))begin
$display("%0d: Detected unkown pc value spc(%d) thread(%x) value(%x)",
$time, 3'b111, spc7_thread_id[1:0], `DTUPATH7.pc_w);
`MONITOR_PATH.fail("Detected unkown pc");
end
*/
end
`endif // ifdef RTL_SPARC7
end
reg dummy;
task trap_extract;
reg [2048:0] pc_str;
reg [63:0] tmp_val;
integer i;
begin
bad_trap_count = 0;
finish_mask = 1;
diag_mask = 0;
stub_mask = 0;
if($value$plusargs("finish_mask=%h", finish_mask))$display ("%t: finish_mask %h", $time, finish_mask);
if($value$plusargs("good_trap=%s", pc_str)) $display ("%t: good_trap list %s", $time, pc_str);
if($value$plusargs("stub_mask=%h", stub_mask)) $display ("%t: stub_mask %h", $time, stub_mask);
for(i = 0; i < 32;i = i + 1)if(finish_mask[i] === 1'bx)finish_mask[i] = 1'b0;
if(sas_def)dummy = $bw_good_trap(1, finish_mask);
for(i = 0; i < 8;i = i + 1) if(stub_mask[i] === 1'bx)stub_mask[i] = 1'b0;
good_trap_count = 0;
while ($parse (pc_str, "%h:", tmp_val))
begin
good_trap[good_trap_count] = tmp_val;
$display ("%t: good_trap %h", $time, good_trap[good_trap_count]);
good_trap_count = good_trap_count + 1;
if (good_trap_count > `GOOD_TRAP_COUNTER)
begin
$display ("%t: good_trap_count more than max-count %d.", $time, `GOOD_TRAP_COUNTER);
`MONITOR_PATH.fail("good_trap_count more than max-count");
end
end
if($value$plusargs("bad_trap=%s", pc_str))$display ("%t: bad_trap list %s", $time, pc_str);
bad_trap_count = 0;
while ($parse (pc_str, "%h:", tmp_val))
begin
bad_trap[bad_trap_count] = tmp_val;
$display ("%t: bad_trap %h", $time, bad_trap[bad_trap_count]);
bad_trap_count = bad_trap_count + 1;
if (bad_trap_count > `GOOD_TRAP_COUNTER)
begin
$display ("%t: bad_trap_count more than max-count %d.", $time,`GOOD_TRAP_COUNTER);
`MONITOR_PATH.fail("bad_trap_count more than max-count.");
end
end // while ($parse (pc_str, "%h:", tmp_val))
trap_count = good_trap_count > bad_trap_count ? good_trap_count : bad_trap_count;
end
endtask // trap_extract
// deceide pass or fail
reg [31:0] timeout [31:0];
reg [63:0] rpc;
integer ind;
//post-silicon request
reg [63:0] last_hit [31:0];
//indicate the 2nd time hit.
reg [31:0] hitted;
initial hitted = 0;
task check_done;
input [7:0] cpu;
integer j, l;
reg [63:0]pc;
reg [4:0] i;
begin
for(i = 0; i < 8; i = i + 1)begin
if(cpu[i])begin
case(i)
0 : begin j = {i[2:0], spc0_thread_id};pc = spc0_phy_pc_w;rpc = spc0_rtl_pc;end
1 : begin j = {i[2:0], spc1_thread_id};pc = spc1_phy_pc_w;rpc = spc1_rtl_pc;end
2 : begin j = {i[2:0], spc2_thread_id};pc = spc2_phy_pc_w;rpc = spc2_rtl_pc;end
3 : begin j = {i[2:0], spc3_thread_id};pc = spc3_phy_pc_w;rpc = spc3_rtl_pc;end
4 : begin j = {i[2:0], spc4_thread_id};pc = spc4_phy_pc_w;rpc = spc4_rtl_pc;end
5 : begin j = {i[2:0], spc5_thread_id};pc = spc5_phy_pc_w;rpc = spc5_rtl_pc;end
6 : begin j = {i[2:0], spc6_thread_id};pc = spc6_phy_pc_w;rpc = spc6_rtl_pc;end
7 : begin j = {i[2:0], spc7_thread_id};pc = spc7_phy_pc_w;rpc = spc7_rtl_pc;end
endcase
timeout[j] = 0;
check_bad_trap(pc, i, j);
if(active_thread[j])begin
for(l = 0; l < good_trap_count; l = l + 1)begin
if(good_trap[l] == pc[39:0])begin
if(sas_def && (good[j] == 0))dummy = $bw_good_trap(2, j, rpc);//command thread, pc
if(good[j] == 0)$display("Info: spc(%0x) thread(%0x) Hit Good trap", j / 4, j % 4);
//post-silicon debug
if((sas_def == 0) && finish_mask[j])begin
if(good_flag)begin
if(!hitted[j])begin
last_hit[j] = pc[39:0];
hitted[j] = 1;
end
else if(last_hit[j] == pc[39:0])good[j] = 1'b1;
end
else good[j] = 1'b1;
end
if(sas_def && active_thread[j])good[j] = 1'b1;
if(sas_def && finish_mask[j])good_for[j] = 1'b1;
end
if((sas_def == 0) &&
(good == finish_mask) &&
(hit_bad == 0) &&
(stub_mask == stub_good))begin
`TOP_MOD.diag_done = 1;
@(posedge clk);
$display("%0d: Simulation -> PASS (HIT GOOD TRAP)", $time);
$finish;
end
if(sas_def && (good == active_thread))`TOP_MOD.diag_done = 1;
if(sas_def)
if($bw_good_trap(3, j) &&
(hit_bad == 0) &&
(stub_mask == stub_good))begin
`TOP_MOD.diag_done = 1;
if(`TOP_MOD.fail_flag == 1'b0)begin
repeat(2) @(posedge clk);
$display("%0d: Simulation -> PASS (HIT GOOD TRAP)", $time);
dum = $bw_sas_send(`PLI_QUIT);
$finish;
end
end
end // for (l = 0; l < good_trap_count; l = l + 1)
end // if (active_thread[j])
end // if (cpu[i])
end
end
endtask
// get done signal;
task gen_done;
begin
done[0] = spc0_inst_done;//sparc 0
done[1] = spc1_inst_done;//sparc 1
done[2] = spc2_inst_done;//sparc 2
done[3] = spc3_inst_done;//sparc 3
done[4] = spc4_inst_done;//sparc 4
done[5] = spc5_inst_done;//sparc 5
done[6] = spc6_inst_done;//sparc 6
done[7] = spc7_inst_done;//sparc 7
end
endtask // gen_done
reg first_rst;
initial begin
if($value$plusargs("TIMEOUT=%d", time_tmp))max = time_tmp;
else max = 1000;
#20//need to wait for socket initializing.
trap_extract;
done = 0;
good = 0;
active_thread = 0;
hit_bad = 0;
first_rst = 1;
for(ind = 0;ind < 32; ind = ind + 1)timeout[ind] = 0;
end // initial begin
always @(posedge rst_l)begin
if(first_rst)begin
active_thread = 0;
first_rst = 0;
done = 0;
good = 0;
hit_bad = 0;
end
end
//speed up checkeing
task check_time;
input [5:0] head;
input [5:0] tail;
integer ind;
begin
for(ind = head; ind < tail; ind = ind + 1)begin
if(timeout[ind] > max && (good[ind] == 0))begin
if((max_cycle == 0 || finish_mask[ind] == 0) && (thread_status[ind] == `THRFSM_HALT)
)begin
timeout[ind] = 0;
end
else begin
$display("Info: spc(%0d) thread(%0d) -> timeout happen", ind / 4, ind % 4);
`MONITOR_PATH.fail("TIMEOUT");
end
end
else if(active_thread[ind] != good[ind])begin
timeout[ind] = timeout[ind] + 1;
end // if (finish_mask[ind] != good[ind])
end // for (ind = head; ind < tail; ind = ind + 1)
end
endtask // check_time
//check good trap status after threads hit the good trap.
//The reason for this is that the threads stay on halt status.
task check_good;
begin
if($bw_good_trap(3, 0) && (hit_bad == 0))begin
`TOP_MOD.diag_done = 1;
if(!`TOP_MOD.fail_flag)begin
repeat(2) @(posedge clk);
$display("%0d: Simulation -> PASS (HIT GOOD TRAP)", $time);
dum = $bw_sas_send(`PLI_QUIT);
$finish;
end
end
end
endtask // check_good
//deceide whether stub done or not.
task check_stub;
reg [3:0] i;
begin
for(i = 0; i < 8; i = i + 1)begin
if(stub_mask[i] &&
`TOP_MOD.stub_done[i] &&
`TOP_MOD.stub_pass[i])stub_good[i] = 1'b1;
else if(stub_mask[i] &&
`TOP_MOD.stub_done[i] &&
`TOP_MOD.stub_pass[i] == 0)begin
$display("Info->Simulation terminated by stub.");
`MONITOR_PATH.fail("HIT BAD TRAP");
end
end
if (sas_def) begin
if(stub_mask &&
(stub_mask == stub_good) &&
(active_thread && $bw_good_trap(3, 0) ||
active_thread == 0))begin
`TOP_MOD.diag_done = 1;
@(posedge clk);
$display("Info->Simulation terminated by stub.");
$display("%0d: Simulation -> PASS (HIT GOOD TRAP)", $time);
$finish;
end
end
else if ((good == finish_mask) && (stub_mask == stub_good)) begin
`TOP_MOD.diag_done = 1;
@(posedge clk);
$display("Info->Simulation terminated by stub.");
$display("%0d: Simulation -> PASS (HIT GOOD TRAP)", $time);
$finish;
end
end
endtask // check_stub
//main routine of pc cmp to finish the simulation.
always @(posedge clk)begin
if(rst_l)begin
if(`TOP_MOD.stub_done)check_stub;
gen_done;
if(|done[7:0])check_done(done);
else if(sas_def && (good_for == finish_mask))check_good;
`ifdef INCLUDE_SAS_TASKS
get_thread_status;
`endif
if(active_thread[3:0])check_time(0, 4);
if(active_thread[7:4])check_time(4, 8);
if(active_thread[19:8])check_time(8, 20);
if(active_thread[31:20])check_time(20, 32);
end // if (rst_l)
end // always @ (posedge clk)
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFINV_SYMBOL_V
`define SKY130_FD_SC_HD__BUFINV_SYMBOL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__bufinv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFINV_SYMBOL_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file side.v when simulating
// the core, side. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module side(
clka,
addra,
douta
);
input clka;
input [16 : 0] addra;
output [11 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(17),
.C_ADDRB_WIDTH(17),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("artix7"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("side.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(76800),
.C_READ_DEPTH_B(76800),
.C_READ_WIDTH_A(12),
.C_READ_WIDTH_B(12),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(76800),
.C_WRITE_DEPTH_B(76800),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_WRITE_WIDTH_B(12),
.C_XDEVICEFAMILY("artix7")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
// Closed loop solution
module cdc_reset_sync (
input wire clk_in,
input wire pulse_in,
input wire clk_out,
output wire pulse_out
);
wire aq_sync;
reg [1:0] in_pre_sync;
always @(posedge clk_in) begin
in_pre_sync[0] <= pulse_in;
in_pre_sync[1] <= in_pre_sync[0];
end
reg in_sync_pulse;
initial in_sync_pulse = 0; // works only in FPGA
always @(posedge clk_in) begin
if (in_pre_sync[1])
in_sync_pulse <= 1;
else if (aq_sync)
in_sync_pulse <= 0;
end
(* ASYNC_REG = "TRUE" *) reg out_sync_ff_1;
(* ASYNC_REG = "TRUE" *) reg out_sync_ff_2;
always @(posedge clk_out) begin
out_sync_ff_1 <= in_sync_pulse;
out_sync_ff_2 <= out_sync_ff_1;
end
assign pulse_out = out_sync_ff_2;
(* ASYNC_REG = "TRUE" *) reg aq_sync_ff_1;
(* ASYNC_REG = "TRUE" *) reg aq_sync_ff_2;
always @(posedge clk_in) begin
aq_sync_ff_1 <= out_sync_ff_2;
aq_sync_ff_2 <= aq_sync_ff_1;
end
assign aq_sync = aq_sync_ff_2;
endmodule
|
// Testbench for m6502 ALU.
module tb_m6502_alu;
reg [7 : 0] tb_operation;
reg [7 : 0] tb_op_a;
reg [7 : 0] tb_op_b;
reg tb_carry_in;
wire [7 : 0] tb_result;
wire tb_carry;
wire tb_zero;
wire tb_overflow;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
//----------------------------------------------------------------
// dut
//----------------------------------------------------------------
m6502_alu dut(
.operation(tb_operation),
.op_a(tb_op_a),
.op_b(tb_op_b),
.carry_in(tb_carry_in),
.result(tb_result),
.carry(tb_carry),
.zero(tb_zero),
.overflow(tb_overflow)
);
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// init_sim()
//----------------------------------------------------------------
task init_sim;
begin
tc_ctr = 0;
error_ctr = 0;
tb_operation = 8'h0;
tb_op_a = 8'h0;
tb_op_b = 8'h0;
tb_carry_in = 0;
end
endtask // init_sim
//----------------------------------------------------------------
// main
//----------------------------------------------------------------
initial
begin : main
$display(" -= Testbench for m6502 ALU started =-");
$display(" ====================================");
$display("");
init_sim();
display_test_results();
$display("");
$display("*** m6502 ALU simulation done. ***");
$finish;
end // main
endmodule // tb_m6502_alu
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_dac_if (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
// internal interface, a low speed dac clock is used by the internal logic
// sample 0 is transmitted first
dac_div3_clk,
dds_data_00,
dds_data_01,
dds_data_02,
dds_data_03,
dds_data_04,
dds_data_05,
dds_data_06,
dds_data_07,
dds_data_08,
dds_data_09,
dds_data_10,
dds_data_11,
// processor signals
up_dds_enable);
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output [13:0] dac_data_out_a_p;
output [13:0] dac_data_out_a_n;
output [13:0] dac_data_out_b_p;
output [13:0] dac_data_out_b_n;
// internal interface, a low speed dac clock is used by the internal logic
// sample 0 is transmitted first
output dac_div3_clk;
input [13:0] dds_data_00;
input [13:0] dds_data_01;
input [13:0] dds_data_02;
input [13:0] dds_data_03;
input [13:0] dds_data_04;
input [13:0] dds_data_05;
input [13:0] dds_data_06;
input [13:0] dds_data_07;
input [13:0] dds_data_08;
input [13:0] dds_data_09;
input [13:0] dds_data_10;
input [13:0] dds_data_11;
// processor signals
input up_dds_enable;
reg [ 5:0] dds_data_a[13:0];
reg [ 5:0] dds_data_b[13:0];
wire dac_clk_in_s;
wire dac_clk_out_s;
wire [13:0] dac_data_out_a_s;
wire [13:0] dac_data_out_b_s;
wire serdes_clk_preset_s;
wire serdes_clk_rst_s;
wire serdes_preset_s;
wire serdes_rst_s;
wire dac_clk;
wire dac_div3_clk_s;
// The OSERDES modules drive data bit-wise. That is, samples are first need to be
// bit selected, then passed to the OSERDES. The same for parity.
always @(posedge dac_div3_clk) begin
dds_data_a[13] <= {dds_data_10[13], dds_data_08[13], dds_data_06[13],
dds_data_04[13], dds_data_02[13], dds_data_00[13]};
dds_data_a[12] <= {dds_data_10[12], dds_data_08[12], dds_data_06[12],
dds_data_04[12], dds_data_02[12], dds_data_00[12]};
dds_data_a[11] <= {dds_data_10[11], dds_data_08[11], dds_data_06[11],
dds_data_04[11], dds_data_02[11], dds_data_00[11]};
dds_data_a[10] <= {dds_data_10[10], dds_data_08[10], dds_data_06[10],
dds_data_04[10], dds_data_02[10], dds_data_00[10]};
dds_data_a[ 9] <= {dds_data_10[ 9], dds_data_08[ 9], dds_data_06[ 9],
dds_data_04[ 9], dds_data_02[ 9], dds_data_00[ 9]};
dds_data_a[ 8] <= {dds_data_10[ 8], dds_data_08[ 8], dds_data_06[ 8],
dds_data_04[ 8], dds_data_02[ 8], dds_data_00[ 8]};
dds_data_a[ 7] <= {dds_data_10[ 7], dds_data_08[ 7], dds_data_06[ 7],
dds_data_04[ 7], dds_data_02[ 7], dds_data_00[ 7]};
dds_data_a[ 6] <= {dds_data_10[ 6], dds_data_08[ 6], dds_data_06[ 6],
dds_data_04[ 6], dds_data_02[ 6], dds_data_00[ 6]};
dds_data_a[ 5] <= {dds_data_10[ 5], dds_data_08[ 5], dds_data_06[ 5],
dds_data_04[ 5], dds_data_02[ 5], dds_data_00[ 5]};
dds_data_a[ 4] <= {dds_data_10[ 4], dds_data_08[ 4], dds_data_06[ 4],
dds_data_04[ 4], dds_data_02[ 4], dds_data_00[ 4]};
dds_data_a[ 3] <= {dds_data_10[ 3], dds_data_08[ 3], dds_data_06[ 3],
dds_data_04[ 3], dds_data_02[ 3], dds_data_00[ 3]};
dds_data_a[ 2] <= {dds_data_10[ 2], dds_data_08[ 2], dds_data_06[ 2],
dds_data_04[ 2], dds_data_02[ 2], dds_data_00[ 2]};
dds_data_a[ 1] <= {dds_data_10[ 1], dds_data_08[ 1], dds_data_06[ 1],
dds_data_04[ 1], dds_data_02[ 1], dds_data_00[ 1]};
dds_data_a[ 0] <= {dds_data_10[ 0], dds_data_08[ 0], dds_data_06[ 0],
dds_data_04[ 0], dds_data_02[ 0], dds_data_00[ 0]};
dds_data_b[13] <= {dds_data_11[13], dds_data_09[13], dds_data_07[13],
dds_data_05[13], dds_data_03[13], dds_data_01[13]};
dds_data_b[12] <= {dds_data_11[12], dds_data_09[12], dds_data_07[12],
dds_data_05[12], dds_data_03[12], dds_data_01[12]};
dds_data_b[11] <= {dds_data_11[11], dds_data_09[11], dds_data_07[11],
dds_data_05[11], dds_data_03[11], dds_data_01[11]};
dds_data_b[10] <= {dds_data_11[10], dds_data_09[10], dds_data_07[10],
dds_data_05[10], dds_data_03[10], dds_data_01[10]};
dds_data_b[ 9] <= {dds_data_11[ 9], dds_data_09[ 9], dds_data_07[ 9],
dds_data_05[ 9], dds_data_03[ 9], dds_data_01[ 9]};
dds_data_b[ 8] <= {dds_data_11[ 8], dds_data_09[ 8], dds_data_07[ 8],
dds_data_05[ 8], dds_data_03[ 8], dds_data_01[ 8]};
dds_data_b[ 7] <= {dds_data_11[ 7], dds_data_09[ 7], dds_data_07[ 7],
dds_data_05[ 7], dds_data_03[ 7], dds_data_01[ 7]};
dds_data_b[ 6] <= {dds_data_11[ 6], dds_data_09[ 6], dds_data_07[ 6],
dds_data_05[ 6], dds_data_03[ 6], dds_data_01[ 6]};
dds_data_b[ 5] <= {dds_data_11[ 5], dds_data_09[ 5], dds_data_07[ 5],
dds_data_05[ 5], dds_data_03[ 5], dds_data_01[ 5]};
dds_data_b[ 4] <= {dds_data_11[ 4], dds_data_09[ 4], dds_data_07[ 4],
dds_data_05[ 4], dds_data_03[ 4], dds_data_01[ 4]};
dds_data_b[ 3] <= {dds_data_11[ 3], dds_data_09[ 3], dds_data_07[ 3],
dds_data_05[ 3], dds_data_03[ 3], dds_data_01[ 3]};
dds_data_b[ 2] <= {dds_data_11[ 2], dds_data_09[ 2], dds_data_07[ 2],
dds_data_05[ 2], dds_data_03[ 2], dds_data_01[ 2]};
dds_data_b[ 1] <= {dds_data_11[ 1], dds_data_09[ 1], dds_data_07[ 1],
dds_data_05[ 1], dds_data_03[ 1], dds_data_01[ 1]};
dds_data_b[ 0] <= {dds_data_11[ 0], dds_data_09[ 0], dds_data_07[ 0],
dds_data_05[ 0], dds_data_03[ 0], dds_data_01[ 0]};
end
// The resets for SERDES data/clock are separately controlled.
// They are held in reset until software enabled.
assign serdes_clk_preset_s = 1'b0;
FDPE #(.INIT(1'b1)) i_serdes_clk_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (serdes_clk_preset_s),
.C (dac_div3_clk),
.Q (serdes_clk_rst_s));
assign serdes_preset_s = ~up_dds_enable;
FDPE #(.INIT(1'b1)) i_serdes_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (serdes_preset_s),
.C (dac_div3_clk),
.Q (serdes_rst_s));
// dac data output serdes(s) & buffers
// The SERDES is used here to get the lowest clock possible for the internal logic.
// Since Xilinx SERDES is 3:1 DDR, this clock is DAC-CLK/3. This may seem a bit
// challenging (being an odd number as divider) to generate samples. It is possible
// to lower the DAC clock and reduce the OSERDES to be 2:1 or even 1:1. If further
// reductions are required, it is recommended NOT to use master/slave OSERDES
// configuration (as this combination is very sensitive to the output and divided
// clocks). You can lower the clocks at the single OSERDES's divided clock.
genvar l_inst;
generate
for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin: g_dac_data
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (6),
.INTERFACE_TYPE ("DEFAULT"),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER"))
i_dac_data_out_a_oserdes (
.D1 (dds_data_a[l_inst][0]),
.D2 (dds_data_a[l_inst][1]),
.D3 (dds_data_a[l_inst][2]),
.D4 (dds_data_a[l_inst][3]),
.D5 (dds_data_a[l_inst][4]),
.D6 (dds_data_a[l_inst][5]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (1'b1),
.CLK (dac_clk),
.CLKDIV (dac_div3_clk),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.WC (1'b0),
.ODV (1'b0),
.OQ (dac_data_out_a_s[l_inst]),
.TQ (),
.OCBEXTEND (),
.OFB (),
.TFB (),
.TCE (1'b0),
.RST (serdes_rst_s));
OBUFDS i_dac_data_out_a_buf (
.I (dac_data_out_a_s[l_inst]),
.O (dac_data_out_a_p[l_inst]),
.OB (dac_data_out_a_n[l_inst]));
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (6),
.INTERFACE_TYPE ("DEFAULT"),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER"))
i_dac_data_out_b_oserdes (
.D1 (dds_data_b[l_inst][0]),
.D2 (dds_data_b[l_inst][1]),
.D3 (dds_data_b[l_inst][2]),
.D4 (dds_data_b[l_inst][3]),
.D5 (dds_data_b[l_inst][4]),
.D6 (dds_data_b[l_inst][5]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (1'b1),
.CLK (dac_clk),
.CLKDIV (dac_div3_clk),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.WC (1'b0),
.ODV (1'b0),
.OQ (dac_data_out_b_s[l_inst]),
.TQ (),
.OCBEXTEND (),
.OFB (),
.TFB (),
.TCE (1'b0),
.RST (serdes_rst_s));
OBUFDS i_dac_data_out_b_buf (
.I (dac_data_out_b_s[l_inst]),
.O (dac_data_out_b_p[l_inst]),
.OB (dac_data_out_b_n[l_inst]));
end
endgenerate
// dac clock output serdes & buffer
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (6),
.INTERFACE_TYPE ("DEFAULT"),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER"))
i_dac_clk_out_oserdes (
.D1 (1'b0),
.D2 (1'b1),
.D3 (1'b0),
.D4 (1'b1),
.D5 (1'b0),
.D6 (1'b1),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (1'b1),
.CLK (dac_clk),
.CLKDIV (dac_div3_clk),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.WC (1'b0),
.ODV (1'b0),
.OQ (dac_clk_out_s),
.TQ (),
.OCBEXTEND (),
.OFB (),
.TFB (),
.TCE (1'b0),
.RST (serdes_clk_rst_s));
OBUFDS i_dac_clk_out_obuf (
.I (dac_clk_out_s),
.O (dac_clk_out_p),
.OB (dac_clk_out_n));
// dac clock input buffers (can't use MMCM or BUFIO due to pin placements).
// It may be possible to use BUFIO/BUFR on some carriers (where the GCLK and
// data are on the same banks.
IBUFGDS i_dac_clk_in_ibuf (
.I (dac_clk_in_p),
.IB (dac_clk_in_n),
.O (dac_clk_in_s));
BUFG i_dac_clk_in_gbuf (
.I (dac_clk_in_s),
.O (dac_clk));
BUFR #(.BUFR_DIVIDE("3")) i_dac_div3_clk_rbuf (
.CLR (1'b0),
.CE (1'b1),
.I (dac_clk),
.O (dac_div3_clk_s));
BUFG i_dac_div3_clk_gbuf (
.I (dac_div3_clk_s),
.O (dac_div3_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: ram_controller_phy_alt_mem_phy_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_controller_phy_alt_mem_phy_pll (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
locked,
phasedone);
input areset;
input inclk0;
input [2:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [2:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire6;
wire sub_wire7;
wire [0:0] sub_wire10 = 1'h0;
wire [4:4] sub_wire5 = sub_wire0[4:4];
wire [3:3] sub_wire4 = sub_wire0[3:3];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire c3 = sub_wire4;
wire c4 = sub_wire5;
wire locked = sub_wire6;
wire phasedone = sub_wire7;
wire sub_wire8 = inclk0;
wire [1:0] sub_wire9 = {sub_wire10, sub_wire8};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire9),
.phasecounterselect (phasecounterselect),
.phasestep (phasestep),
.phaseupdown (phaseupdown),
.scanclk (scanclk),
.clk (sub_wire0),
.locked (sub_wire6),
.phasedone (sub_wire7),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 100,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 133,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 50,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 133,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 50,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 133,
altpll_component.clk2_phase_shift = "-1880",
altpll_component.clk3_divide_by = 50,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 133,
altpll_component.clk3_phase_shift = "0",
altpll_component.clk4_divide_by = 50,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 133,
altpll_component.clk4_phase_shift = "0",
altpll_component.compensate_clock = "CLK1",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_USED",
altpll_component.port_phasedone = "PORT_USED",
altpll_component.port_phasestep = "PORT_USED",
altpll_component.port_phaseupdown = "PORT_USED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_USED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.vco_frequency_control = "MANUAL_PHASE",
altpll_component.vco_phase_shift_step = 117,
altpll_component.width_clock = 5,
altpll_component.width_phasecounterselect = 3;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "66.500000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "133.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "133.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "133.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "133.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "117.00000000"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "66.50000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "133.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_mem_phy_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "100"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "133"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "133"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "133"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1880"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "133"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "133"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE"
// Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "117"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_PHASECOUNTERSELECT NUMERIC "3"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: phasecounterselect 0 0 3 0 INPUT GND "phasecounterselect[2..0]"
// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @phasecounterselect 0 0 3 0 phasecounterselect 0 0 3 0
// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_controller_phy_alt_mem_phy_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_controller_phy_alt_mem_phy_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_controller_phy_alt_mem_phy_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_controller_phy_alt_mem_phy_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_controller_phy_alt_mem_phy_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_controller_phy_alt_mem_phy_pll_bb.v TRUE
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [15:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR_early, // requested address from SNES
input SNES_WRITE_early,
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // ROMSEL from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
output IS_PATCH, // linear address map (C0-FF, Ex/Fx)
input [7:0] SAVERAM_BASE,
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
input map_unlock,
input map_Ex_rd_unlock,
input map_Ex_wr_unlock,
input map_Fx_rd_unlock,
input map_Fx_wr_unlock,
input snescmd_unlock,
output msu_enable,
output dma_enable,
output srtc_enable,
output use_bsx,
output bsx_tristate,
input [14:0] bsx_regs,
output r213f_enable,
output r2100_hit,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable,
output branch3_enable,
output exe_enable,
output map_enable,
input [8:0] bs_page_offset,
input [9:0] bs_page,
input bs_page_enable
);
/* feature bits. see src/fpga_spi.c for mapping */
parameter [3:0]
FEAT_SRTC = 2,
FEAT_MSU1 = 3,
FEAT_213F = 4,
FEAT_SNESUNLOCK = 5,
FEAT_2100 = 6,
FEAT_DMA1 = 11
;
integer i;
reg [7:0] MAPPER_DEC; always @(posedge CLK) for (i = 0; i < 8; i = i + 1) MAPPER_DEC[i] <= (MAPPER == i);
reg [23:0] SNES_ADDR; always @(posedge CLK) SNES_ADDR <= SNES_ADDR_early;
wire [23:0] SRAM_SNES_ADDR;
wire [23:0] SAVERAM_ADDR = {4'hE,1'b0,SAVERAM_BASE,11'h0};
/* currently supported mappers:
Index Mapper
000 HiROM
001 LoROM
010 ExHiROM (48-64Mbit)
011 BS-X
110 brainfuck interleaved 96MBit Star Ocean =)
111 menu (ROM in upper SRAM)
*/
/* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
Offset 6000-7fff */
assign IS_ROM = ~SNES_ROMSEL;
// Calculate pre IS_SAVERAM to relax timing. Uses
// early SNES_ADDR from main.
assign IS_SAVERAM_pre = (~map_unlock & SAVERAM_MASK[0])
&((MAPPER_DEC[3'b000]
|| MAPPER_DEC[3'b010]
|| MAPPER_DEC[3'b110])
? (!SNES_ADDR_early[22]
& SNES_ADDR_early[21]
& &SNES_ADDR_early[14:13]
& !SNES_ADDR_early[15]
)
/* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xff
* Offset 0000-7fff for ROM >= 32 MBit, otherwise 0000-ffff */
:(MAPPER_DEC[3'b001])
? (&SNES_ADDR_early[22:20]
& (~SNES_ROMSEL)
& (~SNES_ADDR_early[15] | ~ROM_MASK[21])
)
/* BS-X: SRAM @ Bank 0x10-0x17 Offset 5000-5fff */
:(MAPPER_DEC[3'b011])
? ((SNES_ADDR_early[23:19] == 5'b00010)
& (SNES_ADDR_early[15:12] == 4'b0101)
)
/* Menu mapper: 8Mbit "SRAM" @ Bank 0xf0-0xff (entire banks!) */
:(MAPPER_DEC[3'b111])
? (&SNES_ADDR_early[23:20])
: 1'b0);
reg IS_SAVERAM_r; always @(posedge CLK) IS_SAVERAM_r <= IS_SAVERAM_pre;
assign IS_SAVERAM = IS_SAVERAM_r;
// give the patch free reign over $F0-$FF banks
// map_unlock: F0-FF
// map_Ex: E0-EF
// map_Fx: F0-FF
// snescmd_unlock: C0-FF
assign IS_PATCH = ( (map_unlock
| (map_Fx_rd_unlock & SNES_WRITE_early)
| (map_Fx_wr_unlock & ~SNES_WRITE_early)
) & (&SNES_ADDR[23:20])
)
| ( ((map_Ex_rd_unlock & SNES_WRITE_early)
|(map_Ex_wr_unlock & ~SNES_WRITE_early)
) & ({SNES_ADDR[23:20]} == 4'hE)
)
| (snescmd_unlock & &SNES_ADDR[23:22]); // full access to C0-FF
/* BS-X has 4 MBits of extra RAM that can be mapped to various places */
// LoROM: A23 = r03/r04 A22 = r06 A21 = r05 A20 = 0 A19 = d/c
// HiROM: A23 = r03/r04 A22 = d/c A21 = r06 A20 = r05 A19 = 0
wire [2:0] BSX_PSRAM_BANK = {bsx_regs[6], bsx_regs[5], 1'b0};
wire [2:0] SNES_PSRAM_BANK = bsx_regs[2] ? SNES_ADDR[21:19] : SNES_ADDR[22:20];
wire BSX_PSRAM_LOHI = (bsx_regs[3] & ~SNES_ADDR[23]) | (bsx_regs[4] & SNES_ADDR[23]);
reg BSX_IS_PSRAMr;
wire BSX_IS_PSRAM = BSX_IS_PSRAMr;
always @(posedge CLK) begin
BSX_IS_PSRAMr <= BSX_PSRAM_LOHI
& (( IS_ROM & (SNES_PSRAM_BANK == BSX_PSRAM_BANK)
&(SNES_ADDR[15] | bsx_regs[2])
&(~(SNES_ADDR[19] & bsx_regs[2])))
| (bsx_regs[2]
? (SNES_ADDR[22:21] == 2'b01 & SNES_ADDR[15:13] == 3'b011)
: (~SNES_ROMSEL & &SNES_ADDR[22:20] & ~SNES_ADDR[15]))
);
end
wire BSX_IS_CARTROM = ((bsx_regs[7] & (SNES_ADDR[23:22] == 2'b00))
|(bsx_regs[8] & (SNES_ADDR[23:22] == 2'b10)))
& SNES_ADDR[15];
wire BSX_HOLE_LOHI = (bsx_regs[9] & ~SNES_ADDR[23]) | (bsx_regs[10] & SNES_ADDR[23]);
wire BSX_IS_HOLE = BSX_HOLE_LOHI
& (bsx_regs[2] ? (SNES_ADDR[21:20] == {bsx_regs[11], 1'b0})
: (SNES_ADDR[22:21] == {bsx_regs[11], 1'b0}));
assign bsx_tristate = (MAPPER_DEC[3'b011]) & ~BSX_IS_CARTROM & ~BSX_IS_PSRAM & BSX_IS_HOLE;
assign IS_WRITABLE = IS_SAVERAM
|IS_PATCH // allow writing of the patch region
|((MAPPER_DEC[3'b011]) & BSX_IS_PSRAM);
wire [23:0] BSX_ADDR = bsx_regs[2] ? {1'b0, SNES_ADDR[22:0]}
: {2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]};
assign SRAM_SNES_ADDR = IS_PATCH
? SNES_ADDR
: ((MAPPER_DEC[3'b000])
?(IS_SAVERAM
? SAVERAM_ADDR + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
& SAVERAM_MASK)
: ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
:(MAPPER_DEC[3'b001])
?(IS_SAVERAM
? SAVERAM_ADDR + ({SNES_ADDR[20:16], SNES_ADDR[14:0]}
& SAVERAM_MASK)
: ({1'b0, ~SNES_ADDR[23], SNES_ADDR[22:16], SNES_ADDR[14:0]}
& ROM_MASK))
:(MAPPER_DEC[3'b010])
?(IS_SAVERAM
? SAVERAM_ADDR + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
& SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
& ROM_MASK))
:(MAPPER_DEC[3'b011])
?( IS_SAVERAM
? SAVERAM_ADDR + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
: BSX_IS_CARTROM
? (24'h800000 + ({SNES_ADDR[22:16], SNES_ADDR[14:0]} & 24'h0fffff))
: BSX_IS_PSRAM
? (24'h400000 + (BSX_ADDR & 24'h07FFFF))
: bs_page_enable
? (24'h900000 + {bs_page,bs_page_offset})
: (BSX_ADDR & 24'h0fffff)
)
:(MAPPER_DEC[3'b110])
?(IS_SAVERAM
? SAVERAM_ADDR + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
:(SNES_ADDR[15]
?({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
:({2'b10,
SNES_ADDR[23],
SNES_ADDR[21:16],
SNES_ADDR[14:0]}
)
)
)
:(MAPPER_DEC[3'b111])
?(IS_SAVERAM
? SNES_ADDR
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
+ 24'hC00000)
)
: 24'b0);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_HIT = IS_ROM | IS_WRITABLE | bs_page_enable;
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign dma_enable = (featurebits[FEAT_DMA1] | map_unlock | snescmd_unlock) & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff0) == 16'h2020));
assign use_bsx = (MAPPER_DEC[3'b011]);
assign srtc_enable = featurebits[FEAT_SRTC] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h2800));
assign exe_enable = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hffff) == 16'h2C00));
assign map_enable = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hffff) == 16'h2BB2));
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign r2100_hit = (SNES_PA == 8'h00);
// snescmd covers $2A00-$2FFF. This overlaps with at least one hardware cheat device address range.
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:11]} == 6'b0_00101) && (SNES_ADDR[10:9] != 2'b00);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A6C);
assign branch1_enable = (SNES_ADDR == 24'h002A1F);
assign branch2_enable = (SNES_ADDR == 24'h002A59);
assign branch3_enable = (SNES_ADDR == 24'h002A5E);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_engine_ultrascale.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TX Engine takes unformatted request and completions,
// formats these packets into AXI packets for the Xilinx Core. These packets
// must meet max-request, max-payload, and payload termination requirements (see
// Read Completion Boundary). The TX Engine does not check these requirements
// during operation, but may do so during simulation.
//
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "ultrascale.vh"
module tx_engine_ultrascale
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: CC
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER,
// Interface: TXC Engine
input TXC_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
input TXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
input TXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
output TXC_DATA_READY,
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY,
output TXC_SENT,
// Interface: RQ
input S_AXIS_RQ_TREADY,
output S_AXIS_RQ_TVALID,
output S_AXIS_RQ_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_RQ_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_RQ_TKEEP,
output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER,
// Interface: TXR Engine
input TXR_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
input TXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
input TXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
output TXR_DATA_READY,
input TXR_META_VALID,
input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
input [`SIG_TAG_W-1:0] TXR_META_TAG,
input [`SIG_TC_W-1:0] TXR_META_TC,
input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP,
output TXR_META_READY,
output TXR_SENT
);
localparam C_DEPTH_PACKETS = 10;
/*AUTOWIRE*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
reg rTxcSent;
reg rTxrSent;
assign TXC_SENT = rTxcSent;
assign TXR_SENT = rTxrSent;
always @(posedge CLK) begin
rTxcSent <= S_AXIS_CC_TLAST & S_AXIS_CC_TVALID & S_AXIS_CC_TREADY;
rTxrSent <= S_AXIS_RQ_TLAST & S_AXIS_RQ_TVALID & S_AXIS_RQ_TREADY;
end
txr_engine_ultrascale
#(
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
txr_engine_inst
(/*AUTOINST*/
// Outputs
.S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID),
.S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST),
.S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY),
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP));
txc_engine_ultrascale
#(
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
txc_engine_inst
(/*AUTOINST*/
// Outputs
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
.TXC_DATA_READY (TXC_DATA_READY),
.TXC_META_READY (TXC_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY),
.TXC_DATA_VALID (TXC_DATA_VALID),
.TXC_DATA (TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4BB_1_V
`define SKY130_FD_SC_HDLL__NAND4BB_1_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4bb_1 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4bb_1 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4BB_1_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_SHARED_CODE
reg window = 0;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (!window && start_event == 1'b1)
window <= 1'b1;
else if (window && end_event == 1'b1)
window <= 1'b0;
end
else begin
window <= 1'b0;
end
end
`endif // OVL_SHARED_CODE
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
wire xzdetect_test_expr;
assign xzdetect_test_expr = ((^test_expr) ^ (^test_expr) == 1'b0);
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_win_unchange_assert #(
.width(width))
assert_win_unchange_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_event(start_event),
.end_event(end_event),
.test_expr(test_expr),
.window(window),
.xzdetect_test_expr(xzdetect_test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_win_unchange_assume #(
.width(width))
assert_win_unchange_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_event(start_event),
.end_event(end_event),
.test_expr(test_expr),
.window(window),
.xzdetect_test_expr(xzdetect_test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_win_unchange_cover #(
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON))
assert_win_unchange_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_event(start_event),
.end_event(end_event),
.window(window));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_win_unchange.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_win_unchange_assert (clk, reset_n, start_event, end_event, test_expr, window,
xzdetect_test_expr, xzcheck_enable);
parameter width = 8;
input clk, reset_n, start_event, end_event, window;
input [width-1:0] test_expr;
input xzdetect_test_expr, xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_win_unchange_assume (clk, reset_n, start_event, end_event, test_expr, window,
xzdetect_test_expr, xzcheck_enable);
parameter width = 8;
input clk, reset_n, start_event, end_event, window;
input [width-1:0] test_expr;
input xzdetect_test_expr, xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_win_unchange_cover (clk, reset_n, start_event, end_event, window);
parameter OVL_COVER_BASIC_ON = 1;
input clk, reset_n, start_event, end_event, window;
endmodule
|
module ptp(
input wire clk,
input wire reset,
/* IO bus */
input wire iobus_iob_poweron,
input wire iobus_iob_reset,
input wire iobus_datao_clear,
input wire iobus_datao_set,
input wire iobus_cono_clear,
input wire iobus_cono_set,
input wire iobus_iob_fm_datai,
input wire iobus_iob_fm_status,
input wire iobus_rdi_pulse, // unused on 6
input wire [3:9] iobus_ios,
input wire [0:35] iobus_iob_in,
output wire [1:7] iobus_pi_req,
output wire [0:35] iobus_iob_out,
output wire iobus_dr_split,
output wire iobus_rdi_data, // unused on 6
/* Console panel */
input wire key_tape_feed,
output wire [7:0] ptp_ind,
output wire [6:0] status_ind, // also includes motor on
/* Avalon slave */
input wire s_read,
output wire [31:0] s_readdata,
output wire fe_data_rq
);
assign iobus_dr_split = 0;
assign iobus_rdi_data = 0;
assign ptp_ind = ptp;
assign status_ind = { ptp_speed, ptp_b, ptp_busy, ptp_flag, ptp_pia };
wire ptp_sel = iobus_ios == 7'b001_000_0;
wire ptp_data_clr;
wire ptp_data_set;
wire ptp_ic_clr;
wire ptp_ic_set;
wire iob_reset;
wire ptp_datai = ptp_sel & iobus_iob_fm_datai;
wire ptp_status = ptp_sel & iobus_iob_fm_status;
wire ptp_start_clr, ptp_stop_clr;
wire ptp_busy_set;
pa ptp_pa0(clk, reset, ptp_sel & iobus_datao_clear, ptp_data_clr);
pa ptp_pa1(clk, reset, ptp_sel & iobus_datao_set, ptp_data_set);
pa ptp_pa2(clk, reset, ptp_sel & iobus_cono_clear | iob_reset, ptp_ic_clr);
pa ptp_pa3(clk, reset, ptp_sel & iobus_cono_set, ptp_ic_set);
pa ptp_pa4(clk, reset, iobus_iob_reset, iob_reset);
reg [8:1] ptp;
assign iobus_iob_out =
ptp_status ? { 30'b0, ptp_b, ptp_busy, ptp_flag, ptp_pia } :
36'b0;
wire [1:7] ptp_req = { ptp_flag, 7'b0 } >> ptp_pia;
assign iobus_pi_req = ptp_req;
reg [33:35] ptp_pia;
reg ptp_busy;
reg ptp_flag;
reg ptp_b;
`ifdef simulation
initial begin
ptp_busy <= 0;
ptp_flag <= 0;
ptp_b <= 0;
end
`endif
always @(posedge clk) begin
if(ptp_ic_clr) begin
ptp_pia <= 0;
ptp_busy <= 0;
ptp_flag <= 0;
ptp_b <= 0;
end
if(ptp_ic_set) begin
ptp_pia <= iobus_iob_in[33:35];
if(iobus_iob_in[32])
ptp_flag <= 1;
if(iobus_iob_in[31])
ptp_busy <= 1;
if(iobus_iob_in[30])
ptp_b <= 1;
end
if(ptp_data_clr) begin
ptp_busy <= 1;
ptp_flag <= 0;
end
if(ptp_done) begin
ptp_busy <= 0;
ptp_flag <= 1;
end
if(ptp_b)
ptp[8:7] <= 2'b10;
if(ptp_data_clr)
ptp <= 0;
if(ptp_data_set)
ptp <= ptp | iobus_iob_in[28:35];
end
wire ptp_go = ptp_busy | key_tape_feed;
wire start_dly;
wire motor_on, on_pulse;
wire scr_driver = motor_on; // TODO: PWR CLR
wire ptp_done;
wire ptp_speed = ~start_dly & motor_on_dly[1];
wire ptp_ready = ptp_speed & ptp_busy;
`ifdef simulation
ldly2us ptp_dly0(.clk(clk), .reset(reset), .in(ptp_go), .l(motor_on));
ldly1us ptp_dly1(.clk(clk), .reset(reset), .in(on_pulse), .l(start_dly));
`else
ldly5s ptp_dly0(.clk(clk), .reset(reset), .in(ptp_go), .l(motor_on));
ldly1s ptp_dly1(.clk(clk), .reset(reset), .in(on_pulse), .l(start_dly));
`endif
pa ptp_pa5(clk, reset, motor_on, on_pulse);
/* Have to delay the signal a bit so we don't get a glitch in ptp_speed */
reg [1:0] motor_on_dly;
always @(posedge clk)
if(reset)
motor_on_dly <= 0;
else
motor_on_dly <= { motor_on_dly[0], motor_on };
// front end interface
assign fe_data_rq = fe_req;
assign s_readdata = (ptp_busy & ptp_write_sync) ? ptp : 0;
reg fe_req;
reg fe_rs;
wire ptp_clk;
// write gates buffer to solenoid drivers, done_pulse when done
wire ptp_write;
wire ptp_done_pulse;
// want to synchronize with the FE, so we'll actually use these two
reg ptp_write_sync;
reg ptp_done_sync;
`ifdef simulation
clk50khz ptp_clk0(clk, ptp_clk);
ldly2us ptp_dly2(clk, reset, ptp_clk & ptp_ready, ptp_done_pulse, ptp_write);
`else
clk63_3hz ptp_clk0(clk, ptp_clk);
ldly5ms ptp_dly2(clk, reset, ptp_clk & ptp_ready, ptp_done_pulse, ptp_write);
`endif
pa ptp_pa6(clk, reset, fe_rs & ptp_done_sync, ptp_done);
always @(posedge clk) begin
if(reset) begin
ptp_write_sync <= 0;
ptp_done_sync <= 0;
fe_req <= 0;
fe_rs <= 0;
end else begin
if(ptp_clk & (ptp_ready | key_tape_feed & ptp_speed)) begin
fe_req <= 1;
fe_rs <= 0;
end
if(s_read) begin
fe_req <= 0;
fe_rs <= 1;
end
if(ptp_done_pulse)
ptp_done_sync <= 1;
if(ptp_done) begin
ptp_write_sync <= 0;
ptp_done_sync <= 0;
end
if(ptp_write)
ptp_write_sync <= 1;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_gtp_pipe_reset.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : gtp_pipe_reset.v
// Description : GTP PIPE Reset Module for 7 Series Transceiver
// Version : 19.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Reset Module -------------------------------------------------
module PCIEBus_gtp_pipe_reset #
(
//---------- Global ------------------------------------
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_LANE = 1, // PCIe number of lanes
//---------- Local -------------------------------------
parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max
parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK
)
(
//---------- Input -------------------------------------
input RST_CLK,
input RST_RXUSRCLK,
input RST_DCLK,
input RST_RST_N,
input [PCIE_LANE-1:0] RST_DRP_DONE,
input [PCIE_LANE-1:0] RST_RXPMARESETDONE,
input RST_PLLLOCK,
input [PCIE_LANE-1:0] RST_RATE_IDLE,
input [PCIE_LANE-1:0] RST_RXCDRLOCK,
input RST_MMCM_LOCK,
input [PCIE_LANE-1:0] RST_RESETDONE,
input [PCIE_LANE-1:0] RST_PHYSTATUS,
input [PCIE_LANE-1:0] RST_TXSYNC_DONE,
//---------- Output ------------------------------------
output RST_CPLLRESET,
output RST_CPLLPD,
output reg RST_DRP_START,
output reg RST_DRP_X16,
output RST_RXUSRCLK_RESET,
output RST_DCLK_RESET,
output RST_GTRESET,
output RST_USERRDY,
output RST_TXSYNC_START,
output RST_IDLE,
output [ 4:0] RST_FSM
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2;
//---------- Internal Signal ---------------------------
reg [ 5:0] cfg_wait_cnt = 6'd0;
//---------- Output Register ---------------------------
reg pllreset = 1'd0;
reg pllpd = 1'd0;
reg rxusrclk_rst_reg1 = 1'd0;
reg rxusrclk_rst_reg2 = 1'd0;
reg dclk_rst_reg1 = 1'd0;
reg dclk_rst_reg2 = 1'd0;
reg gtreset = 1'd0;
reg userrdy = 1'd0;
reg [ 4:0] fsm = 5'h1;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 5'h0;
localparam FSM_CFG_WAIT = 5'h1;
localparam FSM_PLLRESET = 5'h2;
localparam FSM_DRP_X16_START = 5'h3;
localparam FSM_DRP_X16_DONE = 5'h4;
localparam FSM_PLLLOCK = 5'h5;
localparam FSM_GTRESET = 5'h6;
localparam FSM_RXPMARESETDONE_1 = 5'h7;
localparam FSM_RXPMARESETDONE_2 = 5'h8;
localparam FSM_DRP_X20_START = 5'h9;
localparam FSM_DRP_X20_DONE = 5'hA;
localparam FSM_MMCM_LOCK = 5'hB;
localparam FSM_RESETDONE = 5'hC;
localparam FSM_TXSYNC_START = 5'hD;
localparam FSM_TXSYNC_DONE = 5'hE;
//---------- Input FF ----------------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
//---------- 1st Stage FF --------------------------
drp_done_reg1 <= {PCIE_LANE{1'd0}};
rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}};
plllock_reg1 <= 1'd0;
rate_idle_reg1 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg1 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg1 <= 1'd0;
resetdone_reg1 <= {PCIE_LANE{1'd0}};
phystatus_reg1 <= {PCIE_LANE{1'd0}};
txsync_done_reg1 <= {PCIE_LANE{1'd0}};
//---------- 2nd Stage FF --------------------------
drp_done_reg2 <= {PCIE_LANE{1'd0}};
rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}};
plllock_reg2 <= 1'd0;
rate_idle_reg2 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg2 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg2 <= 1'd0;
resetdone_reg2 <= {PCIE_LANE{1'd0}};
phystatus_reg2 <= {PCIE_LANE{1'd0}};
txsync_done_reg2 <= {PCIE_LANE{1'd0}};
end
else
begin
//---------- 1st Stage FF --------------------------
drp_done_reg1 <= RST_DRP_DONE;
rxpmaresetdone_reg1 <= RST_RXPMARESETDONE;
plllock_reg1 <= RST_PLLLOCK;
rate_idle_reg1 <= RST_RATE_IDLE;
rxcdrlock_reg1 <= RST_RXCDRLOCK;
mmcm_lock_reg1 <= RST_MMCM_LOCK;
resetdone_reg1 <= RST_RESETDONE;
phystatus_reg1 <= RST_PHYSTATUS;
txsync_done_reg1 <= RST_TXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
drp_done_reg2 <= drp_done_reg1;
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
plllock_reg2 <= plllock_reg1;
rate_idle_reg2 <= rate_idle_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
resetdone_reg2 <= resetdone_reg1;
phystatus_reg2 <= phystatus_reg1;
txsync_done_reg2 <= txsync_done_reg1;
end
end
//---------- Configuration Reset Wait Counter ----------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
cfg_wait_cnt <= 6'd0;
else
//---------- Increment Configuration Reset Wait Counter
if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt + 6'd1;
//---------- Hold Configuration Reset Wait Counter -
else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt;
//---------- Reset Configuration Reset Wait Counter
else
cfg_wait_cnt <= 6'd0;
end
//---------- PIPE Reset FSM ----------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
pllreset <= 1'd0;
pllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
pllreset <= 1'd0;
pllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
end
//---------- Wait for Configuration Reset Delay ---
FSM_CFG_WAIT :
begin
fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_PLLRESET : FSM_CFG_WAIT);
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Hold PLL and GTP Channel in Reset ----
FSM_PLLRESET :
begin
fsm <= (((~plllock_reg2) && (&(~resetdone_reg2))) ? FSM_DRP_X16_START : FSM_PLLRESET);
pllreset <= 1'd1;
pllpd <= pllpd;
gtreset <= 1'd1;
userrdy <= userrdy;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_START :
begin
fsm <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_DONE :
begin
fsm <= (&drp_done_reg2) ? FSM_PLLLOCK : FSM_DRP_X16_DONE;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for PLL Lock --------------------
FSM_PLLLOCK :
begin
fsm <= (plllock_reg2 ? FSM_GTRESET : FSM_PLLLOCK);
pllreset <= 1'd0;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Release GTRESET -----------------------
FSM_GTRESET :
begin
fsm <= FSM_RXPMARESETDONE_1;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= 1'b0;
userrdy <= userrdy;
end
//---------- Wait for RXPMARESETDONE Assertion -----
FSM_RXPMARESETDONE_1 :
begin
fsm <= (&rxpmaresetdone_reg2 || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for RXPMARESETDONE De-assertion --
FSM_RXPMARESETDONE_2 :
begin
fsm <= (&(~rxpmaresetdone_reg2) || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start DRP x20 -------------------------
FSM_DRP_X20_START :
begin
fsm <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP x20 Done -----------------
FSM_DRP_X20_DONE :
begin
fsm <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for MMCM and RX CDR Lock ---------
FSM_MMCM_LOCK :
begin
if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)))
begin
fsm <= FSM_RESETDONE;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= 1'd1;
end
else
begin
fsm <= FSM_MMCM_LOCK;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= 1'd0;
end
end
//---------- Wait for [TX/RX]RESETDONE and PHYSTATUS
FSM_RESETDONE :
begin
fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_TXSYNC_START : FSM_RESETDONE);
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START :
begin
fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE :
begin
fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE);
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_CFG_WAIT;
pllreset <= 1'd0;
pllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
endcase
end
end
//---------- RXUSRCLK Reset Synchronizer ---------------------------------------
always @ (posedge RST_RXUSRCLK)
begin
if (pllreset)
begin
rxusrclk_rst_reg1 <= 1'd1;
rxusrclk_rst_reg2 <= 1'd1;
end
else
begin
rxusrclk_rst_reg1 <= 1'd0;
rxusrclk_rst_reg2 <= rxusrclk_rst_reg1;
end
end
//---------- DCLK Reset Synchronizer -------------------------------------------
always @ (posedge RST_DCLK)
begin
if (fsm == FSM_CFG_WAIT)
begin
dclk_rst_reg1 <= 1'd1;
dclk_rst_reg2 <= dclk_rst_reg1;
end
else
begin
dclk_rst_reg1 <= 1'd0;
dclk_rst_reg2 <= dclk_rst_reg1;
end
end
//---------- PIPE Reset Output -------------------------------------------------
assign RST_CPLLRESET = pllreset;
assign RST_CPLLPD = pllpd;
assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
assign RST_DCLK_RESET = dclk_rst_reg2;
assign RST_GTRESET = gtreset;
assign RST_USERRDY = userrdy;
assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RST_IDLE = (fsm == FSM_IDLE);
assign RST_FSM = fsm;
//--------------------------------------------------------------------------------------------------
// Register Output
//--------------------------------------------------------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
RST_DRP_START <= 1'd0;
RST_DRP_X16 <= 1'd0;
end
else
begin
RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
end
end
endmodule
|
module recibo ( input clk,
input rw,
input reset,
input Rx,
output busy,
output clk_blu,
output reg[7:0]dout
);
wire clk_f;
Divisor_frecuencia div(.clk(clk), .clk_f(clk_f), .reset(reset));
reg[1:0]estado, estado_sig;
parameter inactivo =2'b00;
parameter inicio =2'b01;
reg control;
reg done = 0;
reg[8:0]tmp=9'b000000000;
reg[3:0]contador=4'b0000;
//maquina de estados
always@(posedge clk_f, posedge reset)
if(reset)estado <= inactivo;
else estado <= estado_sig;
always@(*)
begin
case(estado)
inactivo:
if(Rx==1 && done==0)
begin
control=0;
estado_sig = inactivo;
end
else if (Rx==0 && done==0 && rw==1)
begin
control=1;
estado_sig = inicio;
end
else
begin
control=0;
estado_sig = inactivo;
end
inicio:
begin
if(done==0)
begin
control=1;
estado_sig = inicio;
end
else
begin
control=0;
estado_sig = inactivo;
end
end
default
estado_sig = inactivo;
endcase
end
//hasta aqui se describe como se pasa de un estado a otro
//ahora viene el bloque de decision que descibe de que manera capturamos la informacion
always@(posedge clk_f)
begin
if(control==1 && done==0)
begin
tmp<={Rx,tmp[8:1]};
end
end
always@(posedge clk_f)
begin
if(control)
if(contador>=10)
begin
contador=0;
done=1;
dout<=tmp[8:1];
end
else
begin
contador=contador+1;
done=0;
end
else
done=0;
end
endmodule
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(* $Id: FSetDecide.v 13199 2010-06-25 22:36:22Z letouzey $ *)
(**************************************************************)
(* FSetDecide.v *)
(* *)
(* Author: Aaron Bohannon *)
(**************************************************************)
(** This file implements a decision procedure for a certain
class of propositions involving finite sets. *)
Require Import Decidable DecidableTypeEx FSetFacts.
(** First, a version for Weak Sets in functorial presentation *)
Module WDecide_fun (E : DecidableType)(Import M : WSfun E).
Module F := FSetFacts.WFacts_fun E M.
(** * Overview
This functor defines the tactic [fsetdec], which will
solve any valid goal of the form
<<
forall s1 ... sn,
forall x1 ... xm,
P1 -> ... -> Pk -> P
>>
where [P]'s are defined by the grammar:
<<
P ::=
| Q
| Empty F
| Subset F F'
| Equal F F'
Q ::=
| E.eq X X'
| In X F
| Q /\ Q'
| Q \/ Q'
| Q -> Q'
| Q <-> Q'
| ~ Q
| True
| False
F ::=
| S
| empty
| singleton X
| add X F
| remove X F
| union F F'
| inter F F'
| diff F F'
X ::= x1 | ... | xm
S ::= s1 | ... | sn
>>
The tactic will also work on some goals that vary slightly from
the above form:
- The variables and hypotheses may be mixed in any order and may
have already been introduced into the context. Moreover,
there may be additional, unrelated hypotheses mixed in (these
will be ignored).
- A conjunction of hypotheses will be handled as easily as
separate hypotheses, i.e., [P1 /\ P2 -> P] can be solved iff
[P1 -> P2 -> P] can be solved.
- [fsetdec] should solve any goal if the FSet-related hypotheses
are contradictory.
- [fsetdec] will first perform any necessary zeta and beta
reductions and will invoke [subst] to eliminate any Coq
equalities between finite sets or their elements.
- If [E.eq] is convertible with Coq's equality, it will not
matter which one is used in the hypotheses or conclusion.
- The tactic can solve goals where the finite sets or set
elements are expressed by Coq terms that are more complicated
than variables. However, non-local definitions are not
expanded, and Coq equalities between non-variable terms are
not used. For example, this goal will be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2)
>>
This one will not be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2)
>>
*)
(** * Facts and Tactics for Propositional Logic
These lemmas and tactics are in a module so that they do
not affect the namespace if you import the enclosing
module [Decide]. *)
Module FSetLogicalFacts.
Require Export Decidable.
Require Export Setoid.
(** ** Lemmas and Tactics About Decidable Propositions *)
(** ** Propositional Equivalences Involving Negation
These are all written with the unfolded form of
negation, since I am not sure if setoid rewriting will
always perform conversion. *)
(** ** Tactics for Negations *)
Tactic Notation "fold" "any" "not" :=
repeat (
match goal with
| H: context [?P -> False] |- _ =>
fold (~ P) in H
| |- context [?P -> False] =>
fold (~ P)
end).
(** [push not using db] will pushes all negations to the
leaves of propositions in the goal, using the lemmas in
[db] to assist in checking the decidability of the
propositions involved. If [using db] is omitted, then
[core] will be used. Additional versions are provided
to manipulate the hypotheses or the hypotheses and goal
together.
XXX: This tactic and the similar subsequent ones should
have been defined using [autorewrite]. However, dealing
with multiples rewrite sites and side-conditions is
done more cleverly with the following explicit
analysis of goals. *)
Ltac or_not_l_iff P Q tac :=
(rewrite (or_not_l_iff_1 P Q) by tac) ||
(rewrite (or_not_l_iff_2 P Q) by tac).
Ltac or_not_r_iff P Q tac :=
(rewrite (or_not_r_iff_1 P Q) by tac) ||
(rewrite (or_not_r_iff_2 P Q) by tac).
Ltac or_not_l_iff_in P Q H tac :=
(rewrite (or_not_l_iff_1 P Q) in H by tac) ||
(rewrite (or_not_l_iff_2 P Q) in H by tac).
Ltac or_not_r_iff_in P Q H tac :=
(rewrite (or_not_r_iff_1 P Q) in H by tac) ||
(rewrite (or_not_r_iff_2 P Q) in H by tac).
Tactic Notation "push" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [?P \/ ?Q -> False] => rewrite (not_or_iff P Q)
| |- context [?P /\ ?Q -> False] => rewrite (not_and_iff P Q)
| |- context [(?P -> ?Q) -> False] => rewrite (not_imp_iff P Q) by dec
end);
fold any not.
Tactic Notation "push" "not" :=
push not using core.
Tactic Notation
"push" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [?P \/ ?Q -> False] |- _ => rewrite (not_or_iff P Q) in H
| H: context [?P /\ ?Q -> False] |- _ => rewrite (not_and_iff P Q) in H
| H: context [(?P -> ?Q) -> False] |- _ =>
rewrite (not_imp_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "push" "not" "in" "*" "|-" :=
push not in * |- using core.
Tactic Notation "push" "not" "in" "*" "using" ident(db) :=
push not using db; push not in * |- using db.
Tactic Notation "push" "not" "in" "*" :=
push not in * using core.
(** A simple test case to see how this works. *)
Lemma test_push : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ ((R -> P) \/ (Q -> R))) ->
(~ (P /\ R)) ->
(~ (P -> R)) ->
True.
Proof.
intros. push not in *.
(* note that ~(R->P) remains (since R isnt decidable) *)
tauto.
Qed.
(** [pull not using db] will pull as many negations as
possible toward the top of the propositions in the goal,
using the lemmas in [db] to assist in checking the
decidability of the propositions involved. If [using
db] is omitted, then [core] will be used. Additional
versions are provided to manipulate the hypotheses or
the hypotheses and goal together. *)
Tactic Notation "pull" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [(?P -> False) /\ (?Q -> False)] =>
rewrite <- (not_or_iff P Q)
| |- context [?P -> ?Q -> False] => rewrite <- (not_and_iff P Q)
| |- context [?P /\ (?Q -> False)] => rewrite <- (not_imp_iff P Q) by dec
| |- context [(?Q -> False) /\ ?P] =>
rewrite <- (not_imp_rev_iff P Q) by dec
end);
fold any not.
Tactic Notation "pull" "not" :=
pull not using core.
Tactic Notation
"pull" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [(?P -> False) /\ (?Q -> False)] |- _ =>
rewrite <- (not_or_iff P Q) in H
| H: context [?P -> ?Q -> False] |- _ =>
rewrite <- (not_and_iff P Q) in H
| H: context [?P /\ (?Q -> False)] |- _ =>
rewrite <- (not_imp_iff P Q) in H by dec
| H: context [(?Q -> False) /\ ?P] |- _ =>
rewrite <- (not_imp_rev_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "pull" "not" "in" "*" "|-" :=
pull not in * |- using core.
Tactic Notation "pull" "not" "in" "*" "using" ident(db) :=
pull not using db; pull not in * |- using db.
Tactic Notation "pull" "not" "in" "*" :=
pull not in * using core.
(** A simple test case to see how this works. *)
Lemma test_pull : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ (R -> P) /\ ~ (Q -> R)) ->
(~ P \/ ~ R) ->
(P /\ ~ R) ->
(~ R /\ P) ->
True.
Proof.
intros. pull not in *. tauto.
Qed.
End FSetLogicalFacts.
Import FSetLogicalFacts.
(** * Auxiliary Tactics
Again, these lemmas and tactics are in a module so that
they do not affect the namespace if you import the
enclosing module [Decide]. *)
Module FSetDecideAuxiliary.
(** ** Generic Tactics
We begin by defining a few generic, useful tactics. *)
(** remove logical hypothesis inter-dependencies (fix #2136). *)
Ltac no_logical_interdep :=
match goal with
| H : ?P |- _ =>
match type of P with
| Prop =>
match goal with H' : context [ H ] |- _ => clear dependent H' end
| _ => fail
end; no_logical_interdep
| _ => idtac
end.
(** [if t then t1 else t2] executes [t] and, if it does not
fail, then [t1] will be applied to all subgoals
produced. If [t] fails, then [t2] is executed. *)
Tactic Notation
"if" tactic(t)
"then" tactic(t1)
"else" tactic(t2) :=
first [ t; first [ t1 | fail 2 ] | t2 ].
(** [prop P holds by t] succeeds (but does not modify the
goal or context) if the proposition [P] can be proved by
[t] in the current context. Otherwise, the tactic
fails. *)
Tactic Notation "prop" constr(P) "holds" "by" tactic(t) :=
let H := fresh in
assert P as H by t;
clear H.
(** This tactic acts just like [assert ... by ...] but will
fail if the context already contains the proposition. *)
Tactic Notation "assert" "new" constr(e) "by" tactic(t) :=
match goal with
| H: e |- _ => fail 1
| _ => assert e by t
end.
(** [subst++] is similar to [subst] except that
- it never fails (as [subst] does on recursive
equations),
- it substitutes locally defined variable for their
definitions,
- it performs beta reductions everywhere, which may
arise after substituting a locally defined function
for its definition.
*)
Tactic Notation "subst" "++" :=
repeat (
match goal with
| x : _ |- _ => subst x
end);
cbv zeta beta in *.
(** [decompose records] calls [decompose record H] on every
relevant hypothesis [H]. *)
Tactic Notation "decompose" "records" :=
repeat (
match goal with
| H: _ |- _ => progress (decompose record H); clear H
end).
(** ** Discarding Irrelevant Hypotheses
We will want to clear the context of any
non-FSet-related hypotheses in order to increase the
speed of the tactic. To do this, we will need to be
able to decide which are relevant. We do this by making
a simple inductive definition classifying the
propositions of interest. *)
Inductive FSet_elt_Prop : Prop -> Prop :=
| eq_Prop : forall (S : Type) (x y : S),
FSet_elt_Prop (x = y)
| eq_elt_prop : forall x y,
FSet_elt_Prop (E.eq x y)
| In_elt_prop : forall x s,
FSet_elt_Prop (In x s)
| True_elt_prop :
FSet_elt_Prop True
| False_elt_prop :
FSet_elt_Prop False
| conj_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P /\ Q)
| disj_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P \/ Q)
| impl_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P -> Q)
| not_elt_prop : forall P,
FSet_elt_Prop P ->
FSet_elt_Prop (~ P).
Inductive FSet_Prop : Prop -> Prop :=
| elt_FSet_Prop : forall P,
FSet_elt_Prop P ->
FSet_Prop P
| Empty_FSet_Prop : forall s,
FSet_Prop (Empty s)
| Subset_FSet_Prop : forall s1 s2,
FSet_Prop (Subset s1 s2)
| Equal_FSet_Prop : forall s1 s2,
FSet_Prop (Equal s1 s2).
(** Here is the tactic that will throw away hypotheses that
are not useful (for the intended scope of the [fsetdec]
tactic). *)
Hint Constructors FSet_elt_Prop FSet_Prop : FSet_Prop.
Ltac discard_nonFSet :=
decompose records;
repeat (
match goal with
| H : ?P |- _ =>
if prop (FSet_Prop P) holds by
(auto 100 with FSet_Prop)
then fail
else clear H
end).
(** ** Turning Set Operators into Propositional Connectives
The lemmas from [FSetFacts] will be used to break down
set operations into propositional formulas built over
the predicates [In] and [E.eq] applied only to
variables. We are going to use them with [autorewrite].
*)
Hint Rewrite
F.empty_iff F.singleton_iff F.add_iff F.remove_iff
F.union_iff F.inter_iff F.diff_iff
: set_simpl.
(** ** Decidability of FSet Propositions *)
(** [In] is decidable. *)
Lemma dec_In : forall x s,
decidable (In x s).
Proof.
red; intros; generalize (F.mem_iff s x); case (mem x s); intuition.
Qed.
(** [E.eq] is decidable. *)
Lemma dec_eq : forall (x y : E.t),
decidable (E.eq x y).
Proof.
red; intros x y; destruct (E.eq_dec x y); auto.
Qed.
(** The hint database [FSet_decidability] will be given to
the [push_neg] tactic from the module [Negation]. *)
Hint Resolve dec_In dec_eq : FSet_decidability.
(** ** Normalizing Propositions About Equality
We have to deal with the fact that [E.eq] may be
convertible with Coq's equality. Thus, we will find the
following tactics useful to replace one form with the
other everywhere. *)
(** The next tactic, [Logic_eq_to_E_eq], mentions the term
[E.t]; thus, we must ensure that [E.t] is used in favor
of any other convertible but syntactically distinct
term. *)
Ltac change_to_E_t :=
repeat (
match goal with
| H : ?T |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
| H : forall x : ?T, _ |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
end).
(** These two tactics take us from Coq's built-in equality
to [E.eq] (and vice versa) when possible. *)
Ltac Logic_eq_to_E_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change (@Logic.eq E.t) with E.eq in H)
| |- _ =>
progress (change (@Logic.eq E.t) with E.eq)
end).
Ltac E_eq_to_Logic_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change E.eq with (@Logic.eq E.t) in H)
| |- _ =>
progress (change E.eq with (@Logic.eq E.t))
end).
(** This tactic works like the built-in tactic [subst], but
at the level of set element equality (which may not be
the convertible with Coq's equality). *)
Ltac substFSet :=
repeat (
match goal with
| H: E.eq ?x ?y |- _ => rewrite H in *; clear H
end).
(** ** Considering Decidability of Base Propositions
This tactic adds assertions about the decidability of
[E.eq] and [In] to the context. This is necessary for
the completeness of the [fsetdec] tactic. However, in
order to minimize the cost of proof search, we should be
careful to not add more than we need. Once negations
have been pushed to the leaves of the propositions, we
only need to worry about decidability for those base
propositions that appear in a negated form. *)
Ltac assert_decidability :=
(** We actually don't want these rules to fire if the
syntactic context in the patterns below is trivially
empty, but we'll just do some clean-up at the
afterward. *)
repeat (
match goal with
| H: context [~ E.eq ?x ?y] |- _ =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| H: context [~ In ?x ?s] |- _ =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
| |- context [~ E.eq ?x ?y] =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| |- context [~ In ?x ?s] =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
end);
(** Now we eliminate the useless facts we added (because
they would likely be very harmful to performance). *)
repeat (
match goal with
| _: ~ ?P, H : ?P \/ ~ ?P |- _ => clear H
end).
(** ** Handling [Empty], [Subset], and [Equal]
This tactic instantiates universally quantified
hypotheses (which arise from the unfolding of [Empty],
[Subset], and [Equal]) for each of the set element
expressions that is involved in some membership or
equality fact. Then it throws away those hypotheses,
which should no longer be needed. *)
Ltac inst_FSet_hypotheses :=
repeat (
match goal with
| H : forall a : E.t, _,
_ : context [ In ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ In ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq _ ?x ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq _ ?x ] =>
let P := type of (H x) in
assert new P by (exact (H x))
end);
repeat (
match goal with
| H : forall a : E.t, _ |- _ =>
clear H
end).
(** ** The Core [fsetdec] Auxiliary Tactics *)
(** Here is the crux of the proof search. Recursion through
[intuition]! (This will terminate if I correctly
understand the behavior of [intuition].) *)
Ltac fsetdec_rec :=
try (match goal with
| H: E.eq ?x ?x -> False |- _ => destruct H
end);
(reflexivity ||
contradiction ||
(progress substFSet; intuition fsetdec_rec)).
(** If we add [unfold Empty, Subset, Equal in *; intros;] to
the beginning of this tactic, it will satisfy the same
specification as the [fsetdec] tactic; however, it will
be much slower than necessary without the pre-processing
done by the wrapper tactic [fsetdec]. *)
Ltac fsetdec_body :=
inst_FSet_hypotheses;
autorewrite with set_simpl in *;
push not in * using FSet_decidability;
substFSet;
assert_decidability;
auto using E.eq_refl;
(intuition fsetdec_rec) ||
fail 1
"because the goal is beyond the scope of this tactic".
End FSetDecideAuxiliary.
Import FSetDecideAuxiliary.
(** * The [fsetdec] Tactic
Here is the top-level tactic (the only one intended for
clients of this library). It's specification is given at
the top of the file. *)
Ltac fsetdec :=
(** We first unfold any occurrences of [iff]. *)
unfold iff in *;
(** We remove dependencies to logical hypothesis. This way,
later "clear" will work nicely (see bug #2136) *)
no_logical_interdep;
(** We fold occurrences of [not] because it is better for
[intros] to leave us with a goal of [~ P] than a goal of
[False]. *)
fold any not; intros;
(** Now we decompose conjunctions, which will allow the
[discard_nonFSet] and [assert_decidability] tactics to
do a much better job. *)
decompose records;
discard_nonFSet;
(** We unfold these defined propositions on finite sets. If
our goal was one of them, then have one more item to
introduce now. *)
unfold Empty, Subset, Equal in *; intros;
(** We now want to get rid of all uses of [=] in favor of
[E.eq]. However, the best way to eliminate a [=] is in
the context is with [subst], so we will try that first.
In fact, we may as well convert uses of [E.eq] into [=]
when possible before we do [subst] so that we can even
more mileage out of it. Then we will convert all
remaining uses of [=] back to [E.eq] when possible. We
use [change_to_E_t] to ensure that we have a canonical
name for set elements, so that [Logic_eq_to_E_eq] will
work properly. *)
change_to_E_t; E_eq_to_Logic_eq; subst++; Logic_eq_to_E_eq;
(** The next optimization is to swap a negated goal with a
negated hypothesis when possible. Any swap will improve
performance by eliminating the total number of
negations, but we will get the maximum benefit if we
swap the goal with a hypotheses mentioning the same set
element, so we try that first. If we reach the fourth
branch below, we attempt any swap. However, to maintain
completeness of this tactic, we can only perform such a
swap with a decidable proposition; hence, we first test
whether the hypothesis is an [FSet_elt_Prop], noting
that any [FSet_elt_Prop] is decidable. *)
pull not using FSet_decidability;
unfold not in *;
match goal with
| H: (In ?x ?r) -> False |- (In ?x ?s) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?x ?y) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?y ?x) -> False =>
contradict H; fsetdec_body
| H: ?P -> False |- ?Q -> False =>
if prop (FSet_elt_Prop P) holds by
(auto 100 with FSet_Prop)
then (contradict H; fsetdec_body)
else fsetdec_body
| |- _ =>
fsetdec_body
end.
(** * Examples *)
Module FSetDecideTestCases.
Lemma test_eq_trans_1 : forall x y z s,
E.eq x y ->
~ ~ E.eq z y ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_trans_2 : forall x y z r s,
In x (singleton y) ->
~ In z r ->
~ ~ In z (add y r) ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_1 : forall w x y z s,
E.eq x w ->
~ ~ E.eq x y ->
~ E.eq y z ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_2 : forall w x y z r1 r2 s,
In x (singleton w) ->
~ In x r1 ->
In x (add y r1) ->
In y r2 ->
In y (remove z r2) ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_In_singleton : forall x,
In x (singleton x).
Proof. fsetdec. Qed.
Lemma test_add_In : forall x y s,
In x (add y s) ->
~ E.eq x y ->
In x s.
Proof. fsetdec. Qed.
Lemma test_Subset_add_remove : forall x s,
s [<=] (add x (remove x s)).
Proof. fsetdec. Qed.
Lemma test_eq_disjunction : forall w x y z,
In w (add x (add y (singleton z))) ->
E.eq w x \/ E.eq w y \/ E.eq w z.
Proof. fsetdec. Qed.
Lemma test_not_In_disj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ (In x s1 \/ In x s4 \/ E.eq y x).
Proof. fsetdec. Qed.
Lemma test_not_In_conj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ In x s1 /\ ~ In x s4 /\ ~ E.eq y x.
Proof. fsetdec. Qed.
Lemma test_iff_conj : forall a x s s',
(In a s' <-> E.eq x a \/ In a s) ->
(In a s' <-> In a (add x s)).
Proof. fsetdec. Qed.
Lemma test_set_ops_1 : forall x q r s,
(singleton x) [<=] s ->
Empty (union q r) ->
Empty (inter (diff s q) (diff s r)) ->
~ In x s.
Proof. fsetdec. Qed.
Lemma eq_chain_test : forall x1 x2 x3 x4 s1 s2 s3 s4,
Empty s1 ->
In x2 (add x1 s1) ->
In x3 s2 ->
~ In x3 (remove x2 s2) ->
~ In x4 s3 ->
In x4 (add x3 s3) ->
In x1 s4 ->
Subset (add x4 s4) s4.
Proof. fsetdec. Qed.
Lemma test_too_complex : forall x y z r s,
E.eq x y ->
(In x (singleton y) -> r [<=] s) ->
In z r ->
In z s.
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until s; intros Heq H Hr; lapply H; fsetdec.
Qed.
Lemma function_test_1 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2).
Proof. fsetdec. Qed.
Lemma function_test_2 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2).
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until 3. intros g_eq. rewrite <- g_eq. fsetdec.
Qed.
Lemma test_baydemir :
forall (f : t -> t),
forall (s : t),
forall (x y : elt),
In x (add y (f s)) ->
~ E.eq x y ->
In x (f s).
Proof.
fsetdec.
Qed.
End FSetDecideTestCases.
End WDecide_fun.
Require Import FSetInterface.
(** Now comes variants for self-contained weak sets and for full sets.
For these variants, only one argument is necessary. Thanks to
the subtyping [WS<=S], the [Decide] functor which is meant to be
used on modules [(M:S)] can simply be an alias of [WDecide]. *)
Module WDecide (M:WS) := WDecide_fun M.E M.
Module Decide := WDecide.
|
/**
# SmallLpf2nd - 2-pole IIR Low-Pass Filter #
Small 2-Pole IIR low-pass filter, made using just adders and bit shifts. Set
the frequency using the K0_SHIFT and K1_SHIFT parameters. It can be slowed down by
strobing the `en` bit to run at a lower rate.
By using power of two feedback terms, this filter is alsways stable and is
immune to limit cycling.
Clamping is necessary if the full input range will be used. Clamping is
unnecessary if the input word will never go beyond '+/- (2^(WIDTH-2)-1)'. Keep
in mind that clamping will cause nonlinear distortion in high-amplitude signals.
## Design Equations ##
Let w0 be the desired cutoff frequency in radians/second, let f_clk be the
filter run rate (defined by clk and en), and let Q be the desired quality
factor.
```
w0^2
H(s) = -----------------------
s^2 + (w0/Q)*s + w0^2
w0 = 2*pi*f0
K0_SHIFT = -log2(w0/Q / f_clk)
K1_SHIFT = -log2(w0*Q / f_clk)
w0/Q = 2^-K0_SHIFT * f_clk
w0*Q = 2^-K1_SHIFT * f_clk
w0 = sqrt(2^-K0_SHIFT * 2^-K1_SHIFT * f_clk^2)
Q = sqrt(2^-K1_SHIFT / 2^-K0_SHIFT)
```
Since the SHIFT parameters must be integers, the final filter will not perfectly
match the desired one. The true filter response will also be different from the
continuous-time approximation.
## Block Diagram ##
Key:
- ACCUM: accumulator
- SUB: subtract signal on bottom from the signal on the left
- 2^-X: Right arithmetic shift by X
```
dataIn --->(SUB)--->(SUB)--->[ACCUM]--->[2^-K0_SHIFT]--\
^ ^ |
| | |
| +--------------------------------+
| |
| \----->[ACCUM]--->[2^-K1_SHIFT]--+-> dataOut
| |
\-----------------------------------------/
```
*/
module SmallLpf2nd #(
parameter K0_SHIFT = 8, ///< K0 filter term = 2^-K0_SHIFT
parameter K1_SHIFT = 8, ///< K1 filter term = 2^-K1_SHIFT
parameter WIDTH = 16, ///< Width of data path
parameter CLAMP = 1 ///< Set to 1 to clamp the accumulators
)
(
input clk, ///< System clock
input rst, ///< Reset, synchronous & active high
input en, ///< Filter strobe
input signed [WIDTH-1:0] dataIn, ///< Filter input
output signed [WIDTH-1:0] dataOut ///< Filter input
);
reg signed [WIDTH+K0_SHIFT-1:0] acc0;
reg signed [WIDTH+K1_SHIFT-1:0] acc1;
reg signed [WIDTH+1:0] forwardIn;
wire signed [WIDTH-1:0] acc0Out;
wire signed [WIDTH+K0_SHIFT:0] acc0In;
wire signed [WIDTH+K1_SHIFT:0] acc1In;
assign acc0In = acc0 + forwardIn;
assign acc1In = acc1 + acc0Out;
always @(posedge clk) begin
if (rst) begin
forwardIn <= 'd0;
acc0 <= 'd0;
acc1 <= 'd0;
end
else if (en) begin
forwardIn <= dataIn - acc0Out - dataOut;
if (CLAMP) begin
acc0 <= (^acc0In[WIDTH+K0_SHIFT-:2])
? {acc0In[WIDTH+K0_SHIFT], {(WIDTH+K0_SHIFT-1){acc0In[WIDTH+K0_SHIFT-1]}}}
: acc0In;
acc1 <= (^acc1In[WIDTH+K1_SHIFT-:2])
? {acc1In[WIDTH+K1_SHIFT], {(WIDTH+K1_SHIFT-1){acc1In[WIDTH+K1_SHIFT-1]}}}
: acc1In;
end
else begin
acc0 <= acc0In;
acc1 <= acc1In;
end
end
end
assign acc0Out = acc0 >>> K0_SHIFT;
assign dataOut = acc1 >>> K1_SHIFT;
// Test Code: Check to see if clamping ever occurs
/*
reg clamp0;
reg clamp1;
always @(posedge clk) begin
if (rst) begin
clamp0 <= 1'b0;
clamp1 <= 1'b0;
end
else begin
clamp0 <= clamp0 | (^acc0In[WIDTH+K0_SHIFT-:2]);
clamp1 <= clamp1 | (^acc1In[WIDTH+K1_SHIFT-:2]);
end
end
*/
endmodule
|
//*************************************************************************
// XLR8_XF module
// Version 1.0
// Designed by Steve Phillips
//*************************************************************************
//
// The xlr8_xf module interfaces the custom functional units created
// by users to the AVR core. The avr regs are visible to the xlr8_xf,
// such that thet xlr8_xf can pull the two operands directly from the
// regs. The regs are read-only for the xlr8_xf
//
// The AVR core wites the ctrl_reg to specify the
// operation and set the function enable bit. the operands are already
// be copied to all funtional units, so when the functional unit
// latency is complete, the result is latched into the result reg. The
// AVR core then reads the result back using load commands, one byte
// at a time.
//
// After the result is written to memory the status_reg is updated
// with completion status and any status bits that are output by the
// functional units. The status reg holds this value until read by the
// AVR, at which point it is cleared on read.
//
// Control Reg
// [7] = Unused
// [6] = Function Enable. When set, this bit starts the operation
// indicated by the Function Option field
// [5:0] = Function Option. This field indicates what operation to
// initiate when the Function Enable is set.
//
// Status Reg
// [7] = Completion/Interrupt Flag
// [6] = Error/Function not supported
// [5:0] = Status Bits. Read only bits set by this module
//
`timescale 1 ns / 1 ns
module xlr8_xf #(
// Address mapped control and data registers
parameter STGI_XF_CTRL_ADR = 8'h10,
parameter STGI_XF_STATUS_ADR = 8'h11,
parameter STGI_XF_R0_ADR = 8'h0C, // 32b result
parameter STGI_XF_R1_ADR = 8'h0D,
parameter STGI_XF_R2_ADR = 8'h0E,
parameter STGI_XF_R3_ADR = 8'h0F,
// Functional Unit Latencies. Latency=0 means function not implemented
parameter STGI_XF_PRELOAD_DELTA = 8'h03,
parameter STGI_XF_P0_LATENCY = 8'h01, // COMPARE
parameter STGI_XF_P1_LATENCY = 8'h02, // ADD
parameter STGI_XF_P2_LATENCY = 8'h05, // SUB
parameter STGI_XF_P3_LATENCY = 8'h03, // MULT
parameter STGI_XF_P4_LATENCY = 8'h1C, // DIV
parameter STGI_XF_P5_LATENCY = 8'h06, // SQRT
parameter STGI_XF_P6_LATENCY = 8'h01, // CONVERT2FLOAT
parameter STGI_XF_P7_LATENCY = 8'h01 // CONVERT2FIXED
)
(cp2,
ireset,
adr,
dbus_in,
dbus_out,
iore,
iowe,
out_en,
core_ramadr,
core_ramre,
core_ramwe,
core_dm_sel,
gprf,
xf_dataa,
xf_datab,
xf_en,
xf_p0_result,
xf_p1_result,
xf_p2_result,
xf_p3_result,
xf_p4_result,
xf_p5_result,
xf_p6_result,
xf_p7_result
);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
// clock and reset
input ireset;
input cp2;
// AVR Control
input [5:0] adr;
input [7:0] dbus_in;
output[7:0] dbus_out;
input iore;
input iowe;
output out_en;
// DM control from AVR core
input [7:0] core_ramadr;
input core_ramre;
input core_ramwe;
input core_dm_sel;
// Register file (read-only access)
input [8*32-1:0] gprf;
// Port interface
output [31:0] xf_dataa;
output [31:0] xf_datab;
output [7:0] xf_en;
input [31:0] xf_p0_result;
input [31:0] xf_p1_result;
input [31:0] xf_p2_result;
input [31:0] xf_p3_result;
input [31:0] xf_p4_result;
input [31:0] xf_p5_result;
input [31:0] xf_p6_result;
input [31:0] xf_p7_result;
// Control reg definitions
localparam STGI_XF_P0_CMD = 3'h0;
localparam STGI_XF_P1_CMD = 3'h1;
localparam STGI_XF_P2_CMD = 3'h2;
localparam STGI_XF_P3_CMD = 3'h3;
localparam STGI_XF_P4_CMD = 3'h4;
localparam STGI_XF_P5_CMD = 3'h5;
localparam STGI_XF_P6_CMD = 3'h6;
localparam STGI_XF_P7_CMD = 3'h7;
localparam CTRL_DM_LOC = (STGI_XF_CTRL_ADR >= 16'h60) ? 1 : 0;
localparam STATUS_DM_LOC = (STGI_XF_STATUS_ADR >= 16'h60) ? 1 : 0;
localparam R_DM_LOC = (STGI_XF_R0_ADR >= 16'h60) ? 1 : 0;
//***********************************************************************
//-------------------------------------------------------
// Reg/Wire Declarations
//-------------------------------------------------------
/*AUTOWIRE*/
/*AUTOREG*/
logic [31:0] result;
logic [7:0] ctrl_reg;
logic [7:0] status_reg;
logic [31:0] xf_dataa;
logic [31:0] xf_datab;
logic [7:0] xf_sel;
logic [2:0] current_cmd;
logic [7:0] port_complete;
logic fp_complete;
logic function_start;
logic function_active;
logic [7:0] result_tc;
logic ctrl_adr;
logic status_adr;
logic r0_adr;
logic r1_adr;
logic r2_adr;
logic r3_adr;
logic ctrl_re;
logic ctrl_we;
logic status_re;
logic r0_re;
logic r1_re;
logic r2_re;
logic r3_re;
logic [7:0] xf_en;
// Determine which address we are receiving
assign ctrl_adr = CTRL_DM_LOC ?
(core_dm_sel && core_ramadr == STGI_XF_CTRL_ADR) :
({2'h0,adr} == STGI_XF_CTRL_ADR);
assign status_adr = STATUS_DM_LOC ?
(core_dm_sel && core_ramadr == STGI_XF_STATUS_ADR) :
({2'h0,adr} == STGI_XF_STATUS_ADR);
assign r0_adr = R_DM_LOC ?
(core_dm_sel && core_ramadr == STGI_XF_R0_ADR) :
({2'h0,adr} == STGI_XF_R0_ADR);
assign r1_adr = R_DM_LOC ?
(core_dm_sel && core_ramadr == STGI_XF_R1_ADR) :
({2'h0,adr} == STGI_XF_R1_ADR);
assign r2_adr = R_DM_LOC ?
(core_dm_sel && core_ramadr == STGI_XF_R2_ADR) :
({2'h0,adr} == STGI_XF_R2_ADR);
assign r3_adr = R_DM_LOC ?
(core_dm_sel && core_ramadr == STGI_XF_R3_ADR) :
({2'h0,adr} == STGI_XF_R3_ADR);
// Set appropriate Read Enable and Write Enable bits
assign ctrl_re = ctrl_adr && (CTRL_DM_LOC ? core_ramre : iore);
assign ctrl_we = ctrl_adr && (CTRL_DM_LOC ? core_ramwe : iowe);
assign status_re = status_adr && (STATUS_DM_LOC ? core_ramre : iore);
//assign status_we = status_adr && (STATUS_DM_LOC ? core_ramwe : iowe);
assign r0_re = r0_adr && (R_DM_LOC ? core_ramre : iore);
//assign r0_we = r0_adr && (R_DM_LOC ? core_ramwe : iowe);
assign r1_re = r1_adr && (R_DM_LOC ? core_ramre : iore);
//assign r1_we = r1_adr && (R_DM_LOC ? core_ramwe : iowe);
assign r2_re = r2_adr && (R_DM_LOC ? core_ramre : iore);
//assign r2_we = r2_adr && (R_DM_LOC ? core_ramwe : iowe);
assign r3_re = r3_adr && (R_DM_LOC ? core_ramre : iore);
//assign r3_we = r3_adr && (R_DM_LOC ? core_ramwe : iowe);
// Latch up the appropriate reg when a read is requested
assign dbus_out = ({8{ctrl_re}} & ctrl_reg) |
({8{status_re}} & status_reg) |
({8{r0_re}} & result[7:0]) |
({8{r1_re}} & result[15:8]) |
({8{r2_re}} & result[23:16]) |
({8{r3_re}} & result[31:24]);
assign out_en = ctrl_re ||
status_re ||
r0_re ||
r1_re ||
r2_re ||
r3_re;
always@(posedge cp2 or negedge ireset) begin: ctrlreg
if (!ireset) begin
ctrl_reg <= 8'h00;
end
else begin
// We are now using ctrl_reg[7] in the C library to trick the
// compiler, so we never want bit 7 to get set. See the
// XLR8Float.cpp file for details on the compiler trick
ctrl_reg <= (ctrl_we) ? {1'b0, dbus_in[6:0]} : ctrl_reg;
end
end
assign current_cmd = (ctrl_we) ? dbus_in[2:0] : ctrl_reg[2:0];
assign function_start = ctrl_we & (dbus_in[6] == 1'b1);
always@(posedge cp2 or negedge ireset)
begin
if (!ireset) begin
function_active <= 1'h0;
end
else begin
if (function_start && ~fp_complete) begin
function_active <= 1'b1;
end else if (fp_complete) begin
function_active = 1'b0;
end
end
end
always@(posedge cp2 or negedge ireset)
begin
if (!ireset) begin
status_reg <= 8'h00;
end
else begin
// Handle the status return value. Latch up the status when
// Function is complete. Then when AVR
// reads status, latch it into the output reg, clear the
// status reg, and hold the output reg until iore goes
// away.
if (fp_complete) begin
status_reg[7] <= 1'b1;
status_reg[6] <= ~|xf_sel; // if selected unit is not enabled return failure condition
status_reg[5:0] <= 6'h0;
end else if (function_start) begin // clear when a new ctrl reg is written
status_reg <= 8'h00;
end else if (dbus_out[7] && status_re) begin // clear completion flag when status is read
status_reg[7] <= 1'b0;
end
end // else: !if(!ireset)
end // always@ (posedge cp2 or negedge ireset)
// Extract operand data from the AVR registers
always@(posedge cp2 or negedge ireset)
begin
if (!ireset) begin
xf_dataa <= 32'h00000000;
xf_datab <= 32'h00000000;
end
else begin
xf_dataa <= gprf[22*8 +: 4*8];
xf_datab <= gprf[18*8 +: 4*8];
end
end // always@ (posedge cp2 or negedge ireset)
// set enable bits based on current command. Use latency=-1 to indicate unsupported functions
always_comb begin
xf_sel[0] = (current_cmd == STGI_XF_P0_CMD) && (STGI_XF_P0_LATENCY != 8'd0);
xf_sel[1] = (current_cmd == STGI_XF_P1_CMD) && (STGI_XF_P1_LATENCY != 8'd0);
xf_sel[2] = (current_cmd == STGI_XF_P2_CMD) && (STGI_XF_P2_LATENCY != 8'd0);
xf_sel[3] = (current_cmd == STGI_XF_P3_CMD) && (STGI_XF_P3_LATENCY != 8'd0);
xf_sel[4] = (current_cmd == STGI_XF_P4_CMD) && (STGI_XF_P4_LATENCY != 8'd0);
xf_sel[5] = (current_cmd == STGI_XF_P5_CMD) && (STGI_XF_P5_LATENCY != 8'd0);
xf_sel[6] = (current_cmd == STGI_XF_P6_CMD) && (STGI_XF_P6_LATENCY != 8'd0);
xf_sel[7] = (current_cmd == STGI_XF_P7_CMD) && (STGI_XF_P7_LATENCY != 8'd0);
end
always_comb xf_en = xf_sel & {8{function_start}};
// Set complete valid bits on a per port basis
always_comb begin
port_complete[0] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P0_LATENCY) && function_start) ||
((result_tc == STGI_XF_P0_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P0_CMD);
port_complete[1] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P1_LATENCY) && function_start) ||
((result_tc == STGI_XF_P1_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P1_CMD);
port_complete[2] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P2_LATENCY) && function_start) ||
((result_tc == STGI_XF_P2_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P2_CMD);
port_complete[3] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P3_LATENCY) && function_start) ||
((result_tc == STGI_XF_P3_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P3_CMD);
port_complete[4] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P4_LATENCY) && function_start) ||
((result_tc == STGI_XF_P4_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P4_CMD);
port_complete[5] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P5_LATENCY) && function_start) ||
((result_tc == STGI_XF_P5_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P5_CMD);
port_complete[6] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P6_LATENCY) && function_start) ||
((result_tc == STGI_XF_P6_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P6_CMD);
port_complete[7] = (((STGI_XF_PRELOAD_DELTA >= STGI_XF_P7_LATENCY) && function_start) ||
((result_tc == STGI_XF_P7_LATENCY) && function_active)) &&
(current_cmd == STGI_XF_P7_CMD);
end
assign fp_complete = |port_complete;
// Result timing chain. Reset whenever we launch a function start
always@(posedge cp2 or negedge ireset)
begin: resulttimingchain
if (!ireset) begin
result_tc <= STGI_XF_PRELOAD_DELTA;
result <= 32'h00000000;
end
else begin
if ((result_tc > STGI_XF_PRELOAD_DELTA) || function_start) begin
result_tc <= result_tc + 1;
end
// Capture result from FP units
if (fp_complete) begin: snagresults
result_tc <= STGI_XF_PRELOAD_DELTA;
// ASSERT: port_complete should be a one shot
case (port_complete)
8'h01: result <= xf_p0_result;
8'h02: result <= xf_p1_result;
8'h04: result <= xf_p2_result;
8'h08: result <= xf_p3_result;
8'h10: result <= xf_p4_result;
8'h20: result <= xf_p5_result;
8'h40: result <= xf_p6_result;
8'h80: result <= xf_p7_result;
default: result <= result;
endcase // case (port_complete)
end // block: snagresults
end
end // block: resulttimingchain
wire _unused_ok = &{1'b0,
gprf[255:208],gprf[143:0], // only use regs 18-25
1'b0};
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Top Level Test Bench ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: test_bench_top.v,v 1.5 2002-02-01 01:55:44 rudi Exp $
//
// $Date: 2002-02-01 01:55:44 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/10/19 04:47:31 rudi
//
// - Made the core parameterized
//
// Revision 1.3 2001/09/07 15:34:36 rudi
//
// Changed reset to active high.
//
// Revision 1.2 2001/08/15 05:40:29 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.1.1.1 2001/03/19 13:11:22 rudi
// Initial Release
//
//
//
`include "wb_dma_defines.v"
`define CH_COUNT 4
module test;
reg clk;
reg rst;
// IO Prototypes
wire [31:0] wb0s_data_i;
wire [31:0] wb0s_data_o;
wire [31:0] wb0_addr_i;
wire [3:0] wb0_sel_i;
wire wb0_we_i;
wire wb0_cyc_i;
wire wb0_stb_i;
wire wb0_ack_o;
wire wb0_err_o;
wire wb0_rty_o;
wire [31:0] wb0m_data_i;
wire [31:0] wb0m_data_o;
wire [31:0] wb0_addr_o;
wire [3:0] wb0_sel_o;
wire wb0_we_o;
wire wb0_cyc_o;
wire wb0_stb_o;
wire wb0_ack_i;
wire wb0_err_i;
wire wb0_rty_i;
wire [31:0] wb1s_data_i;
wire [31:0] wb1s_data_o;
wire [31:0] wb1_addr_i;
wire [3:0] wb1_sel_i;
wire wb1_we_i;
wire wb1_cyc_i;
wire wb1_stb_i;
wire wb1_ack_o;
wire wb1_err_o;
wire wb1_rty_o;
wire [31:0] wb1m_data_i;
wire [31:0] wb1m_data_o;
wire [31:0] wb1_addr_o;
wire [3:0] wb1_sel_o;
wire wb1_we_o;
wire wb1_cyc_o;
wire wb1_stb_o;
wire wb1_ack_i;
wire wb1_err_i;
wire wb1_rty_i;
reg [`CH_COUNT-1:0] req_i;
wire [`CH_COUNT-1:0] ack_o;
reg [`CH_COUNT-1:0] nd_i;
reg [`CH_COUNT-1:0] rest_i;
wire inta_o;
wire intb_o;
wire [31:0] wb0_data_o_mast;
wire [31:0] wb1_data_o_mast;
wire [31:0] wb0_data_o_slv;
wire [31:0] wb1_data_o_slv;
// Test Bench Variables
reg [31:0] wd_cnt;
integer error_cnt;
reg ack_cnt_clr;
reg [31:0] ack_cnt;
// Misc Variables
/////////////////////////////////////////////////////////////////////
//
// Defines
//
`define MEM 32'h0002_0000
`define REG_BASE 32'hb000_0000
`define COR 8'h0
`define INT_MASKA 8'h4
`define INT_MASKB 8'h8
`define INT_SRCA 8'hc
`define INT_SRCB 8'h10
`define CH0_CSR 8'h20
`define CH0_TXSZ 8'h24
`define CH0_ADR0 8'h28
`define CH0_AM0 8'h2c
`define CH0_ADR1 8'h30
`define CH0_AM1 8'h34
`define PTR0 8'h38
`define CH1_CSR 8'h40
`define CH1_TXSZ 8'h44
`define CH1_ADR0 8'h48
`define CH1_AM0 8'h4c
`define CH1_ADR1 8'h50
`define CH1_AM1 8'h54
`define PTR1 8'h58
`define CH2_CSR 8'h60
`define CH2_TXSZ 8'h64
`define CH2_ADR0 8'h68
`define CH2_AM0 8'h6c
`define CH2_ADR1 8'h70
`define CH2_AM1 8'h74
`define PTR2 8'h78
`define CH3_CSR 8'h80
`define CH3_TXSZ 8'h84
`define CH3_ADR0 8'h88
`define CH3_AM0 8'h8c
`define CH3_ADR1 8'h90
`define CH3_AM1 8'h94
`define PTR3 8'h98
/////////////////////////////////////////////////////////////////////
//
// Simulation Initialization and Start up Section
//
initial
begin
$display("\n\n");
$display("**********************************************");
$display("* WISHBONE DMA/BRIDGE Simulation started ... *");
$display("**********************************************");
$display("\n");
`ifdef WAVES
$shm_open("waves");
$shm_probe("AS",test,"AS");
$display("INFO: Signal dump enabled ...\n\n");
`endif
req_i = 0;
nd_i = 0;
wd_cnt = 0;
ack_cnt = 0;
ack_cnt_clr = 0;
error_cnt = 0;
clk = 0;
rst = 1;
rest_i = 0;
repeat(10) @(posedge clk);
rst = 0;
repeat(10) @(posedge clk);
// HERE IS WHERE THE TEST CASES GO ...
if(1) // Full Regression Run
begin
$display(" ......................................................");
$display(" : :");
$display(" : Long Regression Run ... :");
$display(" :....................................................:");
pt10_rd;
pt01_wr;
pt01_rd;
pt10_wr;
sw_dma1(0);
sw_dma2(0);
hw_dma1(0);
hw_dma2(0);
arb_test1;
sw_ext_desc1(0);
hw_dma3(0);
hw_dma4(0);
end
else
if(1) // Quick Regression Run
begin
$display(" ......................................................");
$display(" : :");
$display(" : Short Regression Run ... :");
$display(" :....................................................:");
pt10_rd;
pt01_wr;
pt01_rd;
pt10_wr;
sw_dma1(2);
sw_dma2(2);
hw_dma1(1);
hw_dma2(2);
hw_dma3(2);
hw_dma4(2);
arb_test1;
sw_ext_desc1(1);
end
else
begin
//
// TEST DEVELOPMENT AREA
//
sw_dma1(3);
//arb_test1;
repeat(100) @(posedge clk);
end
repeat(100) @(posedge clk);
$finish;
end
/////////////////////////////////////////////////////////////////////
//
// ack counter
//
always @(posedge clk)
if(ack_cnt_clr) ack_cnt <= #1 0;
else
if(wb0_ack_i | wb1_ack_i) ack_cnt <= #1 ack_cnt + 1;
/////////////////////////////////////////////////////////////////////
//
// Watchdog Counter
//
always @(posedge clk)
if(wb0_cyc_i | wb1_cyc_i | wb0_ack_i | wb1_ack_i) wd_cnt <= #1 0;
else wd_cnt <= #1 wd_cnt + 1;
always @(wd_cnt)
if(wd_cnt>5000)
begin
$display("\n\n*************************************\n");
$display("ERROR: Watch Dog Counter Expired\n");
$display("*************************************\n\n\n");
$finish;
end
always #5 clk = ~clk;
/////////////////////////////////////////////////////////////////////
//
// WISHBONE DMA IP Core
//
// Module Prototype
wb_dma_top
#( 4'hb, // register file address
2'd1, // Number of priorities (4)
`CH_COUNT, // Number of channels
4'hf,
4'hf,
4'hf,
4'hf,
4'hf,
4'hf,
4'hf,
4'hf
)
u0(
.clk_i( clk ),
.rst_i( rst ),
.wb0s_data_i( wb0s_data_i ),
.wb0s_data_o( wb0s_data_o ),
.wb0_addr_i( wb0_addr_i ),
.wb0_sel_i( wb0_sel_i ),
.wb0_we_i( wb0_we_i ),
.wb0_cyc_i( wb0_cyc_i ),
.wb0_stb_i( wb0_stb_i ),
.wb0_ack_o( wb0_ack_o ),
.wb0_err_o( wb0_err_o ),
.wb0_rty_o( wb0_rty_o ),
.wb0m_data_i( wb0m_data_i ),
.wb0m_data_o( wb0m_data_o ),
.wb0_addr_o( wb0_addr_o ),
.wb0_sel_o( wb0_sel_o ),
.wb0_we_o( wb0_we_o ),
.wb0_cyc_o( wb0_cyc_o ),
.wb0_stb_o( wb0_stb_o ),
.wb0_ack_i( wb0_ack_i ),
.wb0_err_i( wb0_err_i ),
.wb0_rty_i( wb0_rty_i ),
.wb1s_data_i( wb1s_data_i ),
.wb1s_data_o( wb1s_data_o ),
.wb1_addr_i( wb1_addr_i ),
.wb1_sel_i( wb1_sel_i ),
.wb1_we_i( wb1_we_i ),
.wb1_cyc_i( wb1_cyc_i ),
.wb1_stb_i( wb1_stb_i ),
.wb1_ack_o( wb1_ack_o ),
.wb1_err_o( wb1_err_o ),
.wb1_rty_o( wb1_rty_o ),
.wb1m_data_i( wb1m_data_i ),
.wb1m_data_o( wb1m_data_o ),
.wb1_addr_o( wb1_addr_o ),
.wb1_sel_o( wb1_sel_o ),
.wb1_we_o( wb1_we_o ),
.wb1_cyc_o( wb1_cyc_o ),
.wb1_stb_o( wb1_stb_o ),
.wb1_ack_i( wb1_ack_i ),
.wb1_err_i( wb1_err_i ),
.wb1_rty_i( wb1_rty_i ),
.dma_req_i( req_i ),
.dma_ack_o( ack_o ),
.dma_nd_i( nd_i ),
.dma_rest_i( rest_i ),
.inta_o( inta_o ),
.intb_o( intb_o )
);
wb_slv #(14) s0(
.clk( clk ),
.rst( ~rst ),
.adr( wb0_addr_o ),
.din( wb0s_data_o ),
.dout( wb0s_data_i ),
.cyc( wb0_cyc_o ),
.stb( wb0_stb_o ),
.sel( wb0_sel_o ),
.we( wb0_we_o ),
.ack( wb0_ack_i ),
.err( wb0_err_i ),
.rty( wb0_rty_i )
);
wb_slv #(14) s1(
.clk( clk ),
.rst( ~rst ),
.adr( wb1_addr_o ),
.din( wb1s_data_o ),
.dout( wb1s_data_i ),
.cyc( wb1_cyc_o ),
.stb( wb1_stb_o ),
.sel( wb1_sel_o ),
.we( wb1_we_o ),
.ack( wb1_ack_i ),
.err( wb1_err_i ),
.rty( wb1_rty_i )
);
wb_mast m0(
.clk( clk ),
.rst( ~rst ),
.adr( wb0_addr_i ),
.din( wb0m_data_o ),
.dout( wb0m_data_i ),
.cyc( wb0_cyc_i ),
.stb( wb0_stb_i ),
.sel( wb0_sel_i ),
.we( wb0_we_i ),
.ack( wb0_ack_o ),
.err( wb0_err_o ),
.rty( wb0_rty_o )
);
wb_mast m1(
.clk( clk ),
.rst( ~rst ),
.adr( wb1_addr_i ),
.din( wb1m_data_o ),
.dout( wb1m_data_i ),
.cyc( wb1_cyc_i ),
.stb( wb1_stb_i ),
.sel( wb1_sel_i ),
.we( wb1_we_i ),
.ack( wb1_ack_o ),
.err( wb1_err_o ),
.rty( wb1_rty_o )
);
`include "tests.v"
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4B_TB_V
`define SKY130_FD_SC_LP__AND4B_TB_V
/**
* and4b: 4-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_lp__and4b dut (.A_N(A_N), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4B_TB_V
|
module soc_system (
button_pio_external_connection_export,
clk_clk,
dipsw_pio_external_connection_export,
hps_0_h2f_reset_reset_n,
hps_0_hps_io_hps_io_emac1_inst_TX_CLK,
hps_0_hps_io_hps_io_emac1_inst_TXD0,
hps_0_hps_io_hps_io_emac1_inst_TXD1,
hps_0_hps_io_hps_io_emac1_inst_TXD2,
hps_0_hps_io_hps_io_emac1_inst_TXD3,
hps_0_hps_io_hps_io_emac1_inst_RXD0,
hps_0_hps_io_hps_io_emac1_inst_MDIO,
hps_0_hps_io_hps_io_emac1_inst_MDC,
hps_0_hps_io_hps_io_emac1_inst_RX_CTL,
hps_0_hps_io_hps_io_emac1_inst_TX_CTL,
hps_0_hps_io_hps_io_emac1_inst_RX_CLK,
hps_0_hps_io_hps_io_emac1_inst_RXD1,
hps_0_hps_io_hps_io_emac1_inst_RXD2,
hps_0_hps_io_hps_io_emac1_inst_RXD3,
hps_0_hps_io_hps_io_sdio_inst_CMD,
hps_0_hps_io_hps_io_sdio_inst_D0,
hps_0_hps_io_hps_io_sdio_inst_D1,
hps_0_hps_io_hps_io_sdio_inst_CLK,
hps_0_hps_io_hps_io_sdio_inst_D2,
hps_0_hps_io_hps_io_sdio_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D0,
hps_0_hps_io_hps_io_usb1_inst_D1,
hps_0_hps_io_hps_io_usb1_inst_D2,
hps_0_hps_io_hps_io_usb1_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D4,
hps_0_hps_io_hps_io_usb1_inst_D5,
hps_0_hps_io_hps_io_usb1_inst_D6,
hps_0_hps_io_hps_io_usb1_inst_D7,
hps_0_hps_io_hps_io_usb1_inst_CLK,
hps_0_hps_io_hps_io_usb1_inst_STP,
hps_0_hps_io_hps_io_usb1_inst_DIR,
hps_0_hps_io_hps_io_usb1_inst_NXT,
hps_0_hps_io_hps_io_spim1_inst_CLK,
hps_0_hps_io_hps_io_spim1_inst_MOSI,
hps_0_hps_io_hps_io_spim1_inst_MISO,
hps_0_hps_io_hps_io_spim1_inst_SS0,
hps_0_hps_io_hps_io_uart0_inst_RX,
hps_0_hps_io_hps_io_uart0_inst_TX,
hps_0_hps_io_hps_io_i2c0_inst_SDA,
hps_0_hps_io_hps_io_i2c0_inst_SCL,
hps_0_hps_io_hps_io_i2c1_inst_SDA,
hps_0_hps_io_hps_io_i2c1_inst_SCL,
hps_0_hps_io_hps_io_gpio_inst_GPIO09,
hps_0_hps_io_hps_io_gpio_inst_GPIO35,
hps_0_hps_io_hps_io_gpio_inst_GPIO40,
hps_0_hps_io_hps_io_gpio_inst_GPIO53,
hps_0_hps_io_hps_io_gpio_inst_GPIO54,
hps_0_hps_io_hps_io_gpio_inst_GPIO61,
led_pio_external_connection_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
reset_reset_n);
input [3:0] button_pio_external_connection_export;
input clk_clk;
input [3:0] dipsw_pio_external_connection_export;
output hps_0_h2f_reset_reset_n;
output hps_0_hps_io_hps_io_emac1_inst_TX_CLK;
output hps_0_hps_io_hps_io_emac1_inst_TXD0;
output hps_0_hps_io_hps_io_emac1_inst_TXD1;
output hps_0_hps_io_hps_io_emac1_inst_TXD2;
output hps_0_hps_io_hps_io_emac1_inst_TXD3;
input hps_0_hps_io_hps_io_emac1_inst_RXD0;
inout hps_0_hps_io_hps_io_emac1_inst_MDIO;
output hps_0_hps_io_hps_io_emac1_inst_MDC;
input hps_0_hps_io_hps_io_emac1_inst_RX_CTL;
output hps_0_hps_io_hps_io_emac1_inst_TX_CTL;
input hps_0_hps_io_hps_io_emac1_inst_RX_CLK;
input hps_0_hps_io_hps_io_emac1_inst_RXD1;
input hps_0_hps_io_hps_io_emac1_inst_RXD2;
input hps_0_hps_io_hps_io_emac1_inst_RXD3;
inout hps_0_hps_io_hps_io_sdio_inst_CMD;
inout hps_0_hps_io_hps_io_sdio_inst_D0;
inout hps_0_hps_io_hps_io_sdio_inst_D1;
output hps_0_hps_io_hps_io_sdio_inst_CLK;
inout hps_0_hps_io_hps_io_sdio_inst_D2;
inout hps_0_hps_io_hps_io_sdio_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D0;
inout hps_0_hps_io_hps_io_usb1_inst_D1;
inout hps_0_hps_io_hps_io_usb1_inst_D2;
inout hps_0_hps_io_hps_io_usb1_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D4;
inout hps_0_hps_io_hps_io_usb1_inst_D5;
inout hps_0_hps_io_hps_io_usb1_inst_D6;
inout hps_0_hps_io_hps_io_usb1_inst_D7;
input hps_0_hps_io_hps_io_usb1_inst_CLK;
output hps_0_hps_io_hps_io_usb1_inst_STP;
input hps_0_hps_io_hps_io_usb1_inst_DIR;
input hps_0_hps_io_hps_io_usb1_inst_NXT;
output hps_0_hps_io_hps_io_spim1_inst_CLK;
output hps_0_hps_io_hps_io_spim1_inst_MOSI;
input hps_0_hps_io_hps_io_spim1_inst_MISO;
output hps_0_hps_io_hps_io_spim1_inst_SS0;
input hps_0_hps_io_hps_io_uart0_inst_RX;
output hps_0_hps_io_hps_io_uart0_inst_TX;
inout hps_0_hps_io_hps_io_i2c0_inst_SDA;
inout hps_0_hps_io_hps_io_i2c0_inst_SCL;
inout hps_0_hps_io_hps_io_i2c1_inst_SDA;
inout hps_0_hps_io_hps_io_i2c1_inst_SCL;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO09;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO35;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO40;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO53;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO54;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO61;
output [7:0] led_pio_external_connection_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input reset_reset_n;
endmodule
|
module IDEX_Reg (
input clk,
input flush,
input stall,
input [5-1:0] EX_ctrl_i,
output [5-1:0] EX_ctrl_o,
input [2-1:0] MEM_ctrl_i,
output [2-1:0] MEM_ctrl_o,
input [2-1:0] WB_ctrl_i,
output [2-1:0] WB_ctrl_o,
input [32-1:0] Rs_data_i,
output [32-1:0] Rs_data_o,
input [32-1:0] Rt_data_i,
output [32-1:0] Rt_data_o,
input [32-1:0] imm_data_i,
output [32-1:0] imm_data_o,
input [5-1:0] Rs_i,
output [5-1:0] Rs_o,
input [5-1:0] Rt_i,
output [5-1:0] Rt_o,
input [5-1:0] Rd_i,
output [5-1:0] Rd_o
);
Latch #(.width(5)) IDEX_EX_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (EX_ctrl_i),
.data_o (EX_ctrl_o)
);
Latch #(.width(2)) IDEX_MEM_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (MEM_ctrl_i),
.data_o (MEM_ctrl_o)
);
Latch #(.width(2)) IDEX_WB_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (WB_ctrl_i),
.data_o (WB_ctrl_o)
);
Latch IDEX_Rs_data (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rs_data_i),
.data_o (Rs_data_o)
);
Latch IDEX_Rt_data (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rt_data_i),
.data_o (Rt_data_o)
);
Latch IDEX_imm_data (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (imm_data_i),
.data_o (imm_data_o)
);
Latch #(.width(5)) IDEX_Rs (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rs_i),
.data_o (Rs_o)
);
Latch #(.width(5)) IDEX_Rt (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rt_i),
.data_o (Rt_o)
);
Latch #(.width(5)) IDEX_Rd (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rd_i),
.data_o (Rd_o)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__EINVP_PP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_PP_SYMBOL_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module softusb_sie(
input usb_clk,
input usb_rst,
input io_re,
input io_we,
input [5:0] io_a,
input [7:0] io_di,
output reg [7:0] io_do,
output usba_spd,
output usba_oe_n,
input usba_rcv,
inout usba_vp,
inout usba_vm,
output usbb_spd,
output usbb_oe_n,
input usbb_rcv,
inout usbb_vp,
inout usbb_vm
);
wire [1:0] line_state_a;
wire [1:0] line_state_b;
wire discon_a;
wire discon_b;
reg port_sel_rx;
reg [1:0] port_sel_tx;
reg [7:0] tx_data;
reg tx_valid;
wire tx_ready;
reg tx_pending;
reg [1:0] generate_reset;
wire [7:0] rx_data;
wire rx_valid;
wire rx_active;
wire tx_busy;
reg [7:0] data_in;
reg rx_pending;
reg tx_low_speed;
reg [1:0] low_speed;
reg generate_eop;
always @(posedge usb_clk) begin
if(usb_rst) begin
port_sel_rx <= 1'b0;
port_sel_tx <= 2'b00;
tx_valid <= 1'b0;
tx_pending <= 1'b0;
generate_reset <= 2'd0;
rx_pending <= 1'b0;
tx_low_speed <= 1'b0;
low_speed <= 2'b00;
generate_eop <= 1'b0;
io_do <= 8'd0;
end else begin
io_do <= 8'd0;
generate_eop <= 1'b0;
case(io_a)
6'h00: io_do <= line_state_a;
6'h01: io_do <= line_state_b;
6'h02: io_do <= discon_a;
6'h03: io_do <= discon_b;
6'h04: io_do <= port_sel_rx;
6'h05: io_do <= port_sel_tx;
6'h06: io_do <= tx_data;
6'h07: io_do <= tx_pending;
6'h08: io_do <= tx_valid;
6'h09: io_do <= tx_busy;
6'h0a: io_do <= generate_reset;
6'h0b: begin
io_do <= data_in;
if(io_re)
rx_pending <= 1'b0;
end
6'h0c: io_do <= rx_pending;
6'h0d: io_do <= rx_active;
6'h0e: io_do <= tx_low_speed;
6'h0f: io_do <= low_speed;
6'h10: io_do <= 8'hxx;
endcase
if(io_we) begin
$display("USB SIE W: a=%x dat=%x", io_a, io_di);
case(io_a)
6'h04: port_sel_rx <= io_di[0];
6'h05: port_sel_tx <= io_di[1:0];
6'h06: begin
tx_valid <= 1'b1;
tx_data <= io_di;
tx_pending <= 1'b1;
end
6'h08: tx_valid <= 1'b0;
6'h0a: generate_reset <= io_di[1:0];
6'h0e: tx_low_speed <= io_di[0];
6'h0f: low_speed <= io_di[1:0];
6'h10: generate_eop <= 1'b1;
endcase
end
if(tx_ready)
tx_pending <= 1'b0;
if(rx_valid) begin
data_in <= rx_data;
rx_pending <= 1'b1;
end
if(io_re) // must be at the end because of the delay!
#1 $display("USB SIE R: a=%x dat=%x", io_a, io_do);
end
end
softusb_phy phy(
.usb_clk(usb_clk),
.usb_rst(usb_rst),
.usba_spd(usba_spd),
.usba_oe_n(usba_oe_n),
.usba_rcv(usba_rcv),
.usba_vp(usba_vp),
.usba_vm(usba_vm),
.usbb_spd(usbb_spd),
.usbb_oe_n(usbb_oe_n),
.usbb_rcv(usbb_rcv),
.usbb_vp(usbb_vp),
.usbb_vm(usbb_vm),
.usba_discon(discon_a),
.usbb_discon(discon_b),
.line_state_a(line_state_a),
.line_state_b(line_state_b),
.port_sel_rx(port_sel_rx),
.port_sel_tx(port_sel_tx),
.tx_data(tx_data),
.tx_valid(tx_valid),
.tx_ready(tx_ready),
.tx_busy(tx_busy),
.generate_reset(generate_reset),
.rx_data(rx_data),
.rx_valid(rx_valid),
.rx_active(rx_active),
.tx_low_speed(tx_low_speed),
.low_speed(low_speed),
.generate_eop(generate_eop)
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module cf_adc_if (
// adc interface (clk, data, over-range)
adc_clk_in,
adc_data_in,
adc_or_in,
// interface outputs
adc_clk,
adc_data,
adc_or,
// processor control signals
up_delay_sel,
up_delay_rwn,
up_delay_addr,
up_delay_wdata,
// delay control signals
delay_clk,
delay_ack,
delay_rdata,
delay_locked);
// This parameter controls the buffer type based on the target device.
parameter C_CF_BUFTYPE = 0;
parameter C_CF_7SERIES = 0;
parameter C_CF_VIRTEX6 = 1;
// adc interface (clk, data, over-range)
input adc_clk_in;
input [13:0] adc_data_in;
input adc_or_in;
// interface outputs
output adc_clk;
output [13:0] adc_data;
output adc_or;
// processor control signals
input up_delay_sel;
input up_delay_rwn;
input [ 3:0] up_delay_addr;
input [ 4:0] up_delay_wdata;
// delay control signals
input delay_clk;
output delay_ack;
output [ 4:0] delay_rdata;
output delay_locked;
reg [13:0] adc_data = 'd0;
reg adc_or_d = 'd0;
reg [ 4:0] adc_or_count = 'd0;
reg adc_or = 'd0;
reg [ 7:0] delay_rst_cnt = 'd0;
reg delay_sel_m1 = 'd0;
reg delay_sel_m2 = 'd0;
reg delay_sel_m3 = 'd0;
reg delay_sel = 'd0;
reg delay_rwn = 'd0;
reg [ 3:0] delay_addr = 'd0;
reg [ 4:0] delay_wdata = 'd0;
reg [14:0] delay_ld = 'd0;
reg delay_sel_d = 'd0;
reg delay_sel_2d = 'd0;
reg delay_sel_3d = 'd0;
reg delay_ack = 'd0;
reg [ 4:0] delay_rdata = 'd0;
reg delay_locked = 'd0;
wire delay_preset_s;
wire delay_rst_s;
wire [ 4:0] delay_rdata_s[14:0];
wire delay_locked_s;
wire [13:0] adc_data_ibuf_s;
wire [13:0] adc_data_idelay_s;
wire [13:0] adc_data_s;
wire adc_or_ibuf_s;
wire adc_or_idelay_s;
wire adc_or_s;
wire adc_clk_ibuf_s;
genvar l_inst;
always @(posedge adc_clk) begin
adc_data <= adc_data_s;
adc_or_d <= adc_or_s;
if (adc_or_d == 1'b1) begin
adc_or_count <= 5'h10;
end else if (adc_or_count[4] == 1'b1) begin
adc_or_count <= adc_or_count + 1'b1;
end
adc_or <= adc_or_count[4];
end
// The delay control interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no INC/DEC stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0) && (delay_addr == 4'hf)) begin
delay_rst_cnt <= 'd0;
end else if (delay_rst_cnt[7] == 1'b0) begin
delay_rst_cnt <= delay_rst_cnt + 1'b1;
end
delay_sel_m1 <= up_delay_sel;
delay_sel_m2 <= delay_sel_m1;
delay_sel_m3 <= delay_sel_m2;
delay_sel <= delay_sel_m2 & ~delay_sel_m3;
if ((delay_sel_m2 == 1'b1) && (delay_sel_m3 == 1'b0)) begin
delay_rwn <= up_delay_rwn;
delay_addr <= up_delay_addr;
delay_wdata <= up_delay_wdata[4:0];
end
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
4'b1110: delay_ld <= 15'h4000;
4'b1101: delay_ld <= 15'h2000;
4'b1100: delay_ld <= 15'h1000;
4'b1011: delay_ld <= 15'h0800;
4'b1010: delay_ld <= 15'h0400;
4'b1001: delay_ld <= 15'h0200;
4'b1000: delay_ld <= 15'h0100;
4'b0111: delay_ld <= 15'h0080;
4'b0110: delay_ld <= 15'h0040;
4'b0101: delay_ld <= 15'h0020;
4'b0100: delay_ld <= 15'h0010;
4'b0011: delay_ld <= 15'h0008;
4'b0010: delay_ld <= 15'h0004;
4'b0001: delay_ld <= 15'h0002;
4'b0000: delay_ld <= 15'h0001;
default: delay_ld <= 15'h0000;
endcase
end else begin
delay_ld <= 15'h0000;
end
delay_sel_d <= delay_sel;
delay_sel_2d <= delay_sel_d;
delay_sel_3d <= delay_sel_2d;
if (delay_sel_3d == 1'b1) begin
delay_ack <= ~delay_ack;
end
case (delay_addr)
4'b1110: delay_rdata <= delay_rdata_s[14];
4'b1101: delay_rdata <= delay_rdata_s[13];
4'b1100: delay_rdata <= delay_rdata_s[12];
4'b1011: delay_rdata <= delay_rdata_s[11];
4'b1010: delay_rdata <= delay_rdata_s[10];
4'b1001: delay_rdata <= delay_rdata_s[ 9];
4'b1000: delay_rdata <= delay_rdata_s[ 8];
4'b0111: delay_rdata <= delay_rdata_s[ 7];
4'b0110: delay_rdata <= delay_rdata_s[ 6];
4'b0101: delay_rdata <= delay_rdata_s[ 5];
4'b0100: delay_rdata <= delay_rdata_s[ 4];
4'b0011: delay_rdata <= delay_rdata_s[ 3];
4'b0010: delay_rdata <= delay_rdata_s[ 2];
4'b0001: delay_rdata <= delay_rdata_s[ 1];
4'b0000: delay_rdata <= delay_rdata_s[ 0];
default: delay_rdata <= 5'd0;
endcase
delay_locked <= delay_locked_s;
end
// The delay elements need calibration from a delay controller and it needs a
// reset (it also asserts locked after the controller is up and running).
assign delay_preset_s = ~delay_rst_cnt[7];
FDPE #(.INIT(1'b1)) i_delayctrl_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (delay_preset_s),
.C (delay_clk),
.Q (delay_rst_s));
// The data buffers -
generate
for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : g_adc_if
IBUF i_data_ibuf (
.I (adc_data_in[l_inst]),
.O (adc_data_ibuf_s[l_inst]));
(* IODELAY_GROUP = "adc_if_delay_group" *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_data_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.IDATAIN (adc_data_ibuf_s[l_inst]),
.DATAOUT (adc_data_idelay_s[l_inst]),
.LD (delay_ld[l_inst]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[l_inst]));
(* IOB = "true" *)
FDRE i_data_reg (
.R (1'b0),
.CE (1'b1),
.C (adc_clk),
.D (adc_data_idelay_s[l_inst]),
.Q (adc_data_s[l_inst]));
end
endgenerate
// The or buffers -
IBUF i_or_ibuf (
.I (adc_or_in),
.O (adc_or_ibuf_s));
(* IODELAY_GROUP = "adc_if_delay_group" *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_or_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.IDATAIN (adc_or_ibuf_s),
.DATAOUT (adc_or_idelay_s),
.LD (delay_ld[14]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[14]));
(* IOB = "true" *)
FDRE i_or_reg (
.R (1'b0),
.CE (1'b1),
.C (adc_clk),
.D (adc_or_idelay_s),
.Q (adc_or_s));
// The clock buffers -
IBUFG i_clk_ibuf (
.I (adc_clk_in),
.O (adc_clk_ibuf_s));
BUFG i_clk_gbuf (
.I (adc_clk_ibuf_s),
.O (adc_clk));
// The delay controller. Refer to Xilinx doc. for details.
// The GROUP directive controls which delay elements this is associated with.
(* IODELAY_GROUP = "adc_if_delay_group" *)
IDELAYCTRL i_delay_ctrl (
.RST (delay_rst_s),
.REFCLK (delay_clk),
.RDY (delay_locked_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:01:50 03/29/2015
// Design Name:
// Module Name: aluparam_behav
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module aluparam_behav
#( parameter BITSIZE = 16)
( output [BITSIZE-1:0] Y,
output [15:0] flags,
input [BITSIZE-1:0] A,
input [BITSIZE-1:0] B,
input [3:0] sel
);
reg [BITSIZE-1:0] outreg;
reg [15:0] flagreg;
reg carry;
reg overflow;
reg trash;
always @(A, B, sel) begin
flagreg = 0;
carry = 0;
trash = 0;
overflow = 0;
case(sel)
4'b0000: begin
outreg = A ^ B;
end
4'b0010: begin
outreg = A ~^ B;
end
4'b1000: begin
outreg = A & B;
end
4'b1010: begin
outreg = A | B;
end
4'b0100: begin
{carry, outreg} = A + B;
overflow = (($signed(A) >= 0 && $signed(B) >= 0 && $signed(outreg) < 0) || ($signed(A) < 0 && $signed(B) < 0 && $signed(outreg) >= 0)) ? 1 : 0;
end
4'b0101: begin
{trash, outreg} = A + ~B + 1;
overflow = (($signed(A) >= 0 && $signed(B) < 0 && $signed(outreg) < 0) || ($signed(A) < 0 && $signed(B) >= 0 && $signed(outreg) >= 0)) ? 1 : 0;
end
4'b0111: begin
outreg = ~A;
end
default: begin
outreg = 0;
flagreg = 0;
end
endcase
flagreg[0] = carry; // Carry
flagreg[2] = (A < B) && (sel == 4'b0101); // Low
flagreg[5] = overflow; // Overflow
flagreg[6] = (outreg == 16'b0); // Zero Flag
flagreg[7] = outreg[BITSIZE-1]; // Negative (Sign) Flag
end
assign Y = outreg;
assign flags = flagreg;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXTP_TB_V
`define SKY130_FD_SC_HS__DFXTP_TB_V
/**
* dfxtp: Delay flop, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfxtp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 D = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 D = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 D = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__dfxtp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXTP_TB_V
|
/* Module: vga_stripes
Description: Generates an "image" on
screen when VIDON is enabled */
module vga_stripes(
VIDON,
HC,
VC,
R,
G,
B,
SW
);
// |--------------------|
// | Port Declarations |
// | -------------------|
input VIDON;
input [9:0] HC;
input [9:0] VC;
output [7:0] R;
output [7:0] G;
output [7:0] B;
input [17:0] SW;
// |---------------------|
// | Signal Declarations |
// | --------------------|
reg [7:0] Rr, Gg, Bb;
assign R = Rr;
assign G = Gg;
assign B = Bb;
always @ (VIDON, VC)
begin
Rr <= 8'b00000000;
Gg <= 8'b00000000;
Bb <= 8'b00000000;
if( VIDON == 1'b1 )
begin
/*if (VC > 400) begin
Bb <= 0;
Rr <= 233;
Gg <= 0;
end
else if (VC > 300 && VC < 400)begin
Bb <= 0;
Rr <= 0;
Gg <= 244;
end
else if (VC > 200 && VC < 300)begin
Bb <= 254;
Rr <= 0;
Gg <= 0;
end
else begin
Bb <= 0;
Rr <= 0;
Gg <= 0;
end*/
/*if( (VC > 250 && VC < 350) && (HC > 450 && HC < 550 ))
begin
/* Switch-Color test. Works!
Rr <= SW[17:10];
Bb <= SW[9:2];
Gg[1:0] <= {SW[1:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0};
end*/
Gg <= VC;
Rr <= HC;
Bb <= VC;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2A_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O2BB2A_PP_SYMBOL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o2bb2a (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2A_PP_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 64-Deep by 4-bit Wide Multi Port RAM
// /___/ /\ Filename : RAM64M.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/21/06 - Initial version.
// 12/01/06 - Fix the cut/past error for port C and D (CR 430051)
// 05/07/08 - Add negative setup/hold support (CR468872)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAM64M #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT_A = 64'h0000000000000000,
parameter [63:0] INIT_B = 64'h0000000000000000,
parameter [63:0] INIT_C = 64'h0000000000000000,
parameter [63:0] INIT_D = 64'h0000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output DOA,
output DOB,
output DOC,
output DOD,
input [5:0] ADDRA,
input [5:0] ADDRB,
input [5:0] ADDRC,
input [5:0] ADDRD,
input DIA,
input DIB,
input DIC,
input DID,
input WCLK,
input WE
);
// define constants
localparam MODULE_NAME = "RAM64M";
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire IS_WCLK_INVERTED_BIN;
wire [5:0] ADDRD_in;
wire DIA_in;
wire DIB_in;
wire DIC_in;
wire DID_in;
wire WCLK_in;
wire WE_in;
`ifdef XIL_TIMING
wire [5:0] ADDRD_dly;
wire DIA_dly;
wire DIB_dly;
wire DIC_dly;
wire DID_dly;
wire WCLK_dly;
wire WE_dly;
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_we_clk_en_p;
wire sh_we_clk_en_n;
assign ADDRD_in = ADDRD_dly;
assign DIA_in = DIA_dly;
assign DIB_in = DIB_dly;
assign DIC_in = DIC_dly;
assign DID_in = DID_dly;
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE_dly; // rv 1
`else
assign ADDRD_in = ADDRD;
assign DIA_in = DIA;
assign DIB_in = DIB;
assign DIC_in = DIC;
assign DID_in = DID;
assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE; // rv 1
`endif
assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((INIT_A < 64'h0000000000000000) || (INIT_A > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-101] INIT_A attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_A);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_B < 64'h0000000000000000) || (INIT_B > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-102] INIT_B attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_B);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_C < 64'h0000000000000000) || (INIT_C > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-103] INIT_C attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_C);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_D < 64'h0000000000000000) || (INIT_D > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-104] INIT_D attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_D);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_WCLK_INVERTED !== 1'b0) && (IS_WCLK_INVERTED !== 1'b1))) begin
$display("Error: [Unisim %s-109] IS_WCLK_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_WCLK_INVERTED);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
reg [63:0] mem_a, mem_b, mem_c, mem_d;
initial begin
mem_a = INIT_A;
mem_b = INIT_B;
mem_c = INIT_C;
mem_d = INIT_D;
end
always @(posedge WCLK_in)
if (WE_in) begin
mem_a[ADDRD_in] <= #100 DIA_in;
mem_b[ADDRD_in] <= #100 DIB_in;
mem_c[ADDRD_in] <= #100 DIC_in;
mem_d[ADDRD_in] <= #100 DID_in;
end
assign DOA = mem_a[ADDRA];
assign DOB = mem_b[ADDRB];
assign DOC = mem_c[ADDRC];
assign DOD = mem_d[ADDRD_in];
`ifdef XIL_TIMING
always @(notifier) begin
mem_a[ADDRD_in] <= 1'bx;
mem_b[ADDRD_in] <= 1'bx;
mem_c[ADDRD_in] <= 1'bx;
mem_d[ADDRD_in] <= 1'bx;
end
assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN;
assign sh_clk_en_n = IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN;
specify
(WCLK => DOA) = (0:0:0, 0:0:0);
(WCLK => DOB) = (0:0:0, 0:0:0);
(WCLK => DOC) = (0:0:0, 0:0:0);
(WCLK => DOD) = (0:0:0, 0:0:0);
(ADDRA *> DOA) = (0:0:0, 0:0:0);
(ADDRB *> DOB) = (0:0:0, 0:0:0);
(ADDRC *> DOC) = (0:0:0, 0:0:0);
(ADDRD *> DOD) = (0:0:0, 0:0:0);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, negedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[0]);
$setuphold (negedge WCLK, negedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[1]);
$setuphold (negedge WCLK, negedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[2]);
$setuphold (negedge WCLK, negedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[3]);
$setuphold (negedge WCLK, negedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[4]);
$setuphold (negedge WCLK, negedge ADDRD[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[5]);
$setuphold (negedge WCLK, negedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly);
$setuphold (negedge WCLK, negedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly);
$setuphold (negedge WCLK, negedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly);
$setuphold (negedge WCLK, negedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, posedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[0]);
$setuphold (negedge WCLK, posedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[1]);
$setuphold (negedge WCLK, posedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[2]);
$setuphold (negedge WCLK, posedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[3]);
$setuphold (negedge WCLK, posedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[4]);
$setuphold (negedge WCLK, posedge ADDRD[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[5]);
$setuphold (negedge WCLK, posedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly);
$setuphold (negedge WCLK, posedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly);
$setuphold (negedge WCLK, posedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly);
$setuphold (negedge WCLK, posedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[0]);
$setuphold (posedge WCLK, negedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[1]);
$setuphold (posedge WCLK, negedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[2]);
$setuphold (posedge WCLK, negedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[3]);
$setuphold (posedge WCLK, negedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[4]);
$setuphold (posedge WCLK, negedge ADDRD[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[5]);
$setuphold (posedge WCLK, negedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly);
$setuphold (posedge WCLK, negedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly);
$setuphold (posedge WCLK, negedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly);
$setuphold (posedge WCLK, negedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, posedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[0]);
$setuphold (posedge WCLK, posedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[1]);
$setuphold (posedge WCLK, posedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[2]);
$setuphold (posedge WCLK, posedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[3]);
$setuphold (posedge WCLK, posedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[4]);
$setuphold (posedge WCLK, posedge ADDRD[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[5]);
$setuphold (posedge WCLK, posedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly);
$setuphold (posedge WCLK, posedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly);
$setuphold (posedge WCLK, posedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly);
$setuphold (posedge WCLK, posedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013, David M. Lloyd
//
// This file is part of the PBIBox suite.
//
// PBIBox is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// PBIBox is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with PBIBox. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
module EtherPBI(
inout tri [15:0] SysAddr,
input wire Phi2,
// 28Mhz (phi2 times 16)
input wire CLK1,
// ignored for now
input wire CLK2,
// always 1
output wire S0,
// always 0
output wire S1,
output tri MPD,
inout tri RdWr,
output wire OE,
output wire RamCS,
output wire RomCS,
// Addr 0-9 on W5300; bank address 0-4 on RAM and 0-7 on ROM
output wire [9:0] AddrOut,
inout tri [7:0] Data,
input wire [2:0] ID,
output tri IRQ,
output tri DmaReqOut,
input wire DmaAckIn,
input wire Halt,
input wire Reset,
input wire SpiDI,
output wire SpiDO,
output wire SpiCK,
output wire SpiCS,
output wire DeviceWr,
output wire DeviceRd,
output wire DeviceCS,
output tri EXTSEL,
input wire DeviceInt
);
reg [3:0] ClkPhase;
reg [2:0] DevID;
reg [5:0] RamBank;
reg [7:0] RomBank;
reg [3:0] DeviceBank;
reg [15:0] DmaAddr;
reg [15:0] DmaCount;
reg DmaReq;
reg DmaCycle;
reg DmaRead; /* Read from device, write to RAM if 1, Write to device, read from RAM if 0 */
reg DmaOdd;
reg DmaOddPickup; /* Blank read/write to align FIFO access */
reg ReadWrite; /* 1 = read, 0 = write, latched */
reg W5300Sel; /* 1 = selected */
reg RamSel; /* 1 = selected */
reg RomSel; /* 1 = selected */
reg Selected;
reg SpiBit;
reg SpiSel;
reg SpiClkSig;
// There are three parts of the clock we care about
// 1: Start of phase 1 (negative edge phi2) - all input data should be sampled at this time
// 2: Phase 1 plus 35 nS - all latched or held output data should be dropped at this time
// 8: Start of phase 2 (positive edge phi2) - addresses should be sampled at this time, and chip selects enabled
// 15: Just before start of phase 1 (negative edge phi2) - update DmaCycle latch
always @(negedge CLK1) begin
if (Reset == 1'b0) begin
/* sync clock */
if (Phi2 == 1'b0 && ClkPhase[3] != 1'b0) begin
ClkPhase <= {Phi2,3'b0};
end
/* Reset! */
DeviceBank <= 0;
DmaAddr <= 0;
DmaCount <= 0;
DmaCycle <= 0;
RamAddr <= 0;
RomAddr <= 0;
Selected <= 0;
DmaReq <= 0;
SpiBit <= 0;
SpiSel <= 0;
DevID <= ID;
end else begin
/* next clock phase */
ClkPhase <= ClkPhase + 1;
/* test current clock phase */
if (ClkPhase == 4'b0000) begin
if (DmaCycle) begin
if (DmaRead == 1'b0) begin
if (DmaCount == 1) begin
DmaCount <= 0;
if (DmaOdd) begin
// one dummy cycle needed
DmaOdd <= 0;
end else begin
// last cycle
DmaReq <= 0;
end
end else begin
DmaOdd <= ! DmaOdd;
DmaCount <= DmaCount - 1;
DmaAddr <= DmaAddr + 1;
end
end
end else if (ReadWrite == 1'b0) begin
// sample inputs and perform write operation
if (SysAddr[15:7] == 9'b110100010 && Selected) begin // First 127 bytes
RomBank[7:0] <= SysAddr[7:0];
end else if (SysAddr[15:4] == 12'b110100011100 && Selected) begin // D1Cx
DeviceBank[3:0] <= SysAddr[3:0];
end else if (SysAddr[15:3] == 13'b1101000111010 && Selected) begin // D1D0-7
SpiBit <= Data[SysAddr[2:0]];
end else if (SysAddr[15:0] == 16'b1101000111010100 && Selected) begin // D1D8
DmaAddr[7:0] <= Data[7:0];
end else if (SysAddr[15:0] == 16'b1101000111010101 && Selected) begin // D1D9
DmaAddr[15:8] <= Data[7:0];
end else if (SysAddr[15:0] == 16'b1101000111010110 && Selected) begin // D1DA
DmaCount[7:0] <= Data[7:0];
end else if (SysAddr[15:0] == 16'b1101000111010111 && Selected) begin // D1DB
DmaCount[15:8] <= Data[7:0];
end else if (SysAddr[15:1] == 15'b110100011101100 && Selected) begin // D1DC-DD
// Start DMA
DmaReq <= 1;
DmaRead <= SysAddr[0];
DmaOdd <= DmaCount[0];
end else if (SysAddr[15:1] == 15'b110100011101101 && Selected) begin // D1DE-DF
SpiClkSig <= SysAddr[0];
end else if (SysAddr[15:0] == 16'b1101000111111111) begin
Selected <= Data == 8'b1 << DevID; // disable on conflict
end else if (SysAddr[15:5] == 11'b11010001111 && Selected) begin // D1E0-D1FE
RamBank[4:0] <= SysAddr[4:0];
end
end
end else if (ClkPhase == 4'b0001 && ReadWrite == 1'b1) begin
// clear holds from read operation
W5300Sel <= 0;
RamSel <= 0;
RomSel <= 0;
end else if (ClkPhase == 4'b1000) begin
// Sample all address info and enable read operation
ReadWrite <= RdWr;
end else if (ClkPhase == 4'b1111) begin
// Check if the next cycle will be a DMA cycle
DmaCycle <= DmaReq && DmaAckIn && Halt;
end
end
end
always @(negedge Phi2) begin
if (Reset == 1'b0) begin
DeviceBank <= 0;
DmaAddr <= 0;
DmaCount <= 0;
DmaCycle <= 0;
RamAddr <= 0;
RomAddr <= 0;
Selected <= 0;
DmaReq <= 0;
SpiBit <= 0;
SpiSel <= 0;
end else begin
if ((DmaReq & !Halt) == 1'b1) begin
/* Just *starting* a DMA cycle */
DmaCycle <= 1'b1;
if (DmaOddPickup == 1'b1 || DmaCount == 16'h1 && DmaOdd == 1'b0) begin
/* Will be the last cycle */
DmaReq <= 0;
end
end else begin
DmaCycle <= 1'b0;
end
if (DmaCycle == 1'b1) begin
/* Just *finishing* a DMA cycle */
if (DmaOddPickup == 1'b0) begin
/* actual cycle */
if (DmaCount == 16'h1) begin
/* Last DMA cycle (maybe) */
if (DmaOdd == 1'b1) begin
/* One more cycle to align */
DmaOdd <= 0;
DmaOddPickup <= 1'b1;
end else begin
/* Next cycle is the last DMA cycle */
DmaRead <= 0;
DmaReq <= 0;
end
end
DmaAddr <= DmaAddr + 1;
DmaCount <= DmaCount - 1;
end
end else if ((Selected & RdWr) == 1'b0) begin
/* Just *finishing* a non-DMA cycle */
/* register loads */
if (SysAddr[15:6] == ('hD100 >> 6)) begin
RamAddr[13:8] <= SysAddr[5:0];
end else if (SysAddr[15:6] == ('hD140 >> 6)) begin
RomAddr[15:10] <= SysAddr[5:0];
// D180..D1BF = W5300 access
end else if (SysAddr[15:4] == ('hD1E0 >> 4)) begin
DeviceBank[3:0] <= SysAddr[3:0];
end else if (SysAddr == 'hD1F7) begin
DmaAddr[7:0] <= Data[7:0];
end else if (SysAddr == 'hD1F8) begin
DmaAddr[15:8] <= Data[7:0];
end else if (SysAddr == 'hD1F9) begin
DmaCount[7:0] <= Data[7:0];
end else if (SysAddr == 'hD1FA) begin
DmaCount[15:8] <= Data[7:0];
end else if (SysAddr == 'hD1FB) begin
// initiate DMA transfer, bit 0 = R/!W
DmaRead <= Data[0];
DmaOddPickup <= 0;
DmaOdd <= DmaCount[0];
DmaReq <= 1'b1;
// D1FC = /HALT detect (read only)
end else if (SysAddr == 'hD1FD) begin
SpiSel <= Data[0]; // Write 1 to select SPI, 0 to deselect
end else if (SysAddr == 'hD1FE) begin
SpiBit <= Data[7]; // MSB first, left shift to empty register
SpiClkSig <= 1'b1;
end else if (SysAddr == 'hD1FF) begin
Selected <= Dx;
end
end
end
if (SpiBit == 1'b1) begin
SpiBit <= 0;
end
if (SpiClkSig == 1'b1) begin
SpiClkSig <= 0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO1N_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__ISO1N_FUNCTIONAL_PP_V
/**
* iso1n: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__iso1n (
X ,
A ,
SLEEP_B,
VPWR ,
KAGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input KAGND ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_SLEEP;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, KAGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SLEEP, SLEEP, VPWR, KAGND );
or or0 (X , pwrgood_pp0_out_A, pwrgood_pp1_out_SLEEP);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO1N_FUNCTIONAL_PP_V |
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
Command Opcode encoding:
*/
///////////////////////////////////////////////////////////////////////////////////////////////////
`include "../spl_defines.vh"
`include "../framework_defines.vh"
module FThread_controller #(parameter MAX_NUM_CONFIG_CL = 2,
parameter USER_RD_TAG = 2,
parameter USER_WR_TAG = 9) (
input wire clk,
input wire rst_n,
//--------------- channel <--> scheduler
input wire cmd_valid,
input wire [`CMD_LINE_WIDTH-1:0] cmd_line,
output reg fthread_job_done,
output wire reset_user_logic,
//--------------- channel <--> arbiter
//- TX RD, RX RD
output wire tx_rd_valid,
output wire [67:0] tx_rd_hdr,
input wire tx_rd_ready,
input wire rx_rd_valid,
input wire [`FTHREAD_TAG-1:0] rx_rd_tag,
input wire [511:0] rx_data,
//- TX WR, RX WR
output wire [71:0] tx_wr_hdr,
output wire [511:0] tx_data,
output wire tx_wr_valid,
input wire tx_wr_ready,
input wire [`FTHREAD_TAG-1:0] rx_wr_tag,
input wire rx_wr_valid,
//------------------------ Pipeline Interfaces ---------------------//
// Left Pipe
output wire left_pipe_tx_rd_valid,
output wire [`IF_TAG-1:0] left_pipe_tx_rd_tag,
input wire left_pipe_tx_rd_ready,
input wire left_pipe_rx_rd_valid,
input wire [`IF_TAG-1:0] left_pipe_rx_rd_tag,
input wire [511:0] left_pipe_rx_data,
output wire left_pipe_rx_rd_ready,
// Right Pipe
input wire right_pipe_tx_rd_valid,
input wire [`IF_TAG-1:0] right_pipe_tx_rd_tag,
output wire right_pipe_tx_rd_ready,
output wire right_pipe_rx_rd_valid,
output wire [`IF_TAG-1:0] right_pipe_rx_rd_tag,
output wire [511:0] right_pipe_rx_data,
input wire right_pipe_rx_rd_ready,
//------------------------ User Module interface -------------------//
output reg start_um,
output reg [(MAX_NUM_CONFIG_CL*512)-1:0] um_params,
input wire um_done,
input wire [`NUM_USER_STATE_COUNTERS*32-1:0] um_state_counters,
input wire um_state_counters_valid,
// User Module TX RD
input wire [57:0] um_tx_rd_addr,
input wire [USER_RD_TAG-1:0] um_tx_rd_tag,
input wire um_tx_rd_valid,
output wire um_tx_rd_ready,
// User Module TX WR
input wire [57:0] um_tx_wr_addr,
input wire [USER_WR_TAG-1:0] um_tx_wr_tag,
input wire um_tx_wr_valid,
input wire [511:0] um_tx_data,
output wire um_tx_wr_ready,
// User Module RX RD
output wire [USER_RD_TAG-1:0] um_rx_rd_tag,
output wire [511:0] um_rx_data,
output wire um_rx_rd_valid,
input wire um_rx_rd_ready,
// User Module RX WR
output wire um_rx_wr_valid,
output wire [USER_WR_TAG-1:0] um_rx_wr_tag
);
localparam [2:0]
CHANNEL_IDLE_STATE = 3'b000,
CHANNEL_STARTING_STATE = 3'b001,
CHANNEL_CONFIG_STATE = 3'b010,
CHANNEL_RUN_STATE = 3'b011,
CHANNEL_DONE_STATE = 3'b100,
CHANNEL_DRAIN_WR_FIFO_STATE = 3'b101,
CHANNEL_WRFENCE_STATE = 3'b110,
CHANNEL_DONE_RESP_STATE = 3'b111;
reg [2:0] ch_status_state;
wire ft_tx_wr_ready;
reg ft_tx_wr_valid;
reg [57:0] ft_tx_wr_addr;
reg [`FTHREAD_TAG-1:0] ft_tx_wr_tag;
reg [511:0] ft_tx_data;
reg ft_tx_rd_valid;
reg [57:0] ft_tx_rd_addr;
reg [`FTHREAD_TAG-1:0] ft_tx_rd_tag;
wire ft_tx_rd_ready;
reg [(MAX_NUM_CONFIG_CL*512)-1:0] config_param_line;
wire [57:0] cfg_tx_rd_addr;
wire cfg_tx_rd_ready;
wire [`IF_TAG-1:0] cfg_tx_rd_tag;
wire cfg_tx_rd_valid;
reg [`IF_TAG-1:0] cfg_rx_rd_tag;
reg [511:0] cfg_rx_data;
reg cfg_rx_rd_valid;
reg cmd_buff_valid;
reg [`CMD_LINE_WIDTH-1:0] cmd_buff;
reg reserved_cmd_valid;
reg [`CMD_LINE_WIDTH-1:0] reserved_cmd;
wire [3:0] wr_cmd;
reg [31:0] writes_sent;
reg [31:0] writes_done;
reg [31:0] finishCycles;
reg [31:0] RdReqCnt;
reg [31:0] GRdReqCnt;
reg [31:0] WrReqCnt;
reg [31:0] exeCycles;
reg [31:0] ConfigCycles;
reg [31:0] ReadCycles;
reg [31:0] ReadyCycles;
reg rx_rd_valid_reg;
reg [`FTHREAD_TAG-1:0] rx_rd_tag_reg;
reg [511:0] rx_data_reg;
reg [`FTHREAD_TAG-1:0] rx_wr_tag_reg;
reg rx_wr_valid_reg;
wire [(MAX_NUM_CONFIG_CL*512)-1:0] afu_config_struct;
wire afu_config_struct_valid;
wire flush_cmd;
wire read_reserved_cmd;
wire tx_rd_fifo_full;
wire tx_wr_fifo_full;
wire tx_wr_fifo_empty;
reg set_wr_if_direct_pipelined;
reg set_wr_if_mem_pipelined;
reg [57:0] wr_mem_pipeline_addr;
reg set_rd_if_direct_pipelined;
reg set_rd_if_mem_pipelined;
reg [57:0] rd_mem_pipeline_addr;
reg [3:0] rd_direct_pipeline_addr_code;
reg [3:0] rd_mem_pipeline_addr_code;
wire user_tx_wr_if_empty;
wire usr_arb_tx_wr_valid;
wire [57:0] usr_arb_tx_wr_addr;
wire [`IF_TAG-1:0] usr_arb_tx_wr_tag;
wire [511:0] usr_arb_tx_data;
wire usr_arb_tx_wr_ready;
reg usr_arb_rx_wr_valid;
reg [`IF_TAG-1:0] usr_arb_rx_wr_tag;
wire rif_tx_wr_valid;
wire [57:0] rif_tx_wr_addr;
wire [`IF_TAG-1:0] rif_tx_wr_tag;
wire [511:0] rif_tx_data;
wire rif_tx_wr_ready;
reg rif_rx_wr_valid;
reg [`IF_TAG-1:0] rif_rx_wr_tag;
wire wif_tx_rd_valid;
wire [57:0] wif_tx_rd_addr;
wire [`IF_TAG-1:0] wif_tx_rd_tag;
wire wif_tx_rd_ready;
reg wif_rx_rd_valid;
reg [`IF_TAG-1:0] wif_rx_rd_tag;
reg [511:0] wif_rx_data;
wire usr_arb_tx_rd_valid;
wire [57:0] usr_arb_tx_rd_addr;
wire [`IF_TAG-1:0] usr_arb_tx_rd_tag;
wire usr_arb_tx_rd_ready;
reg usr_arb_rx_rd_valid;
reg [`IF_TAG-1:0] usr_arb_rx_rd_tag;
reg [511:0] usr_arb_rx_data;
reg run_rd_tx;
reg run_wr_tx;
reg rif_done;
reg wif_done;
reg start_d0;
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// FThread IO ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// Register RX RD,WR: Data, tags
always@(posedge clk)begin
rx_rd_tag_reg <= rx_rd_tag;
rx_data_reg <= rx_data;
rx_wr_tag_reg <= rx_wr_tag;
end
// Register RX RD,WR: Valids
always@(posedge clk)begin
if(~rst_n) begin
rx_rd_valid_reg <= 0;
rx_wr_valid_reg <= 0;
end
else begin
rx_rd_valid_reg <= rx_rd_valid;
rx_wr_valid_reg <= rx_wr_valid;
end
end
// RX RD: used by the user module and configurator
// data
always@(posedge clk) begin
usr_arb_rx_rd_tag <= rx_rd_tag_reg[`IF_TAG-1:0];
usr_arb_rx_data <= rx_data_reg;
wif_rx_data <= rx_data_reg;
wif_rx_rd_tag <= rx_rd_tag_reg[`IF_TAG-1:0];
cfg_rx_data <= rx_data_reg;
cfg_rx_rd_tag <= rx_rd_tag_reg[`IF_TAG-1:0];
end
//valids
always@(posedge clk) begin
if(~ rst_n)begin
usr_arb_rx_rd_valid <= 0;
wif_rx_rd_valid <= 0;
cfg_rx_rd_valid <= 0;
end
else begin
usr_arb_rx_rd_valid <= rx_rd_valid_reg & rx_rd_tag_reg[`FTHREAD_TAG-1] & run_rd_tx;
wif_rx_rd_valid <= rx_rd_valid_reg & ~rx_rd_tag_reg[`FTHREAD_TAG-1] & run_rd_tx;
cfg_rx_rd_valid <= rx_rd_valid_reg & ~run_rd_tx;
end
end
//assign cfg_rx_data = rx_data_reg;
//assign cfg_rx_rd_valid = rx_rd_valid_reg & ~run_rd_tx;
//assign cfg_rx_rd_tag = rx_rd_tag_reg[`IF_TAG-1:0];
//////////////////////////////////////////////////////////// TX RD FIFO
quick_fifo #(.FIFO_WIDTH(68),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD(32)
) tx_rd_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({ft_tx_rd_addr, ft_tx_rd_tag}),
.we (ft_tx_rd_valid),
.re (tx_rd_ready),
.dout (tx_rd_hdr),
.empty (),
.valid (tx_rd_valid),
.full (tx_rd_fifo_full),
.count (),
.almostfull ()
);
///////////////////////////////////////////////////////////////////////////////////////////////////
// RX WR: used by the user module
// tag
always@(posedge clk) begin
usr_arb_rx_wr_tag <= rx_wr_tag_reg[`IF_TAG-1:0];
rif_rx_wr_tag <= rx_wr_tag_reg[`IF_TAG-1:0];
end
// valid
always@(posedge clk) begin
if(~ rst_n)begin
usr_arb_rx_wr_valid <= 0;
rif_rx_wr_valid <= 0;
end
else begin
usr_arb_rx_wr_valid <= rx_wr_valid_reg & rx_wr_tag_reg[`FTHREAD_TAG-1] & run_wr_tx;
rif_rx_wr_valid <= rx_wr_valid_reg & ~rx_wr_tag_reg[`FTHREAD_TAG-1] & run_wr_tx;
end
end
//////////////////////////////////////////////////////////// TX WR FIFO
assign wr_cmd = (run_wr_tx)? `CCI_REQ_WR_LINE : `CCI_REQ_WR_THRU;
quick_fifo #(.FIFO_WIDTH(512+72),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD(32)
) tx_wr_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({ wr_cmd, ft_tx_wr_addr, ft_tx_wr_tag, ft_tx_data}),
.we (ft_tx_wr_valid),
.re (tx_wr_ready),
.dout ({tx_wr_hdr, tx_data}),
.empty (tx_wr_fifo_empty),
.valid (tx_wr_valid),
.full (tx_wr_fifo_full),
.count (),
.almostfull ()
);
/////////////////////////////////////////////////////////////////////////////////
// Track All Write requests that are finished
always@(posedge clk) begin
if( ~rst_n | (ch_status_state == CHANNEL_IDLE_STATE) )begin
writes_sent <= 0;
writes_done <= 0;
end
else begin
writes_sent <= (tx_wr_valid & tx_wr_ready)? (writes_sent + 1'b1) : writes_sent;
writes_done <= (rx_wr_valid_reg)? (writes_done + 1'b1) : writes_done;
end
end
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// Command Buffer ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// communicate with the scheduler
assign flush_cmd = (ch_status_state == CHANNEL_DONE_STATE);
// cmd_line
always@(posedge clk) begin
if(~cmd_buff_valid) begin
cmd_buff <= reserved_cmd;
end
end
// valid
always@(posedge clk) begin
if(~rst_n) begin
cmd_buff_valid <= 1'b0;
end
else if(flush_cmd) begin
cmd_buff_valid <= 1'b0;
end
else if(reserved_cmd_valid & (ch_status_state == CHANNEL_IDLE_STATE)) begin
cmd_buff_valid <= 1'b1;
end
end
// reserved cmd
// cmd_line
always@(posedge clk) begin
if(~reserved_cmd_valid) begin
reserved_cmd <= cmd_line;
end
end
// valid
always@(posedge clk) begin
if(~rst_n) begin
reserved_cmd_valid <= 1'b0;
end
else if(read_reserved_cmd) begin
reserved_cmd_valid <= 1'b0;
end
else if(cmd_valid) begin
reserved_cmd_valid <= 1'b1;
end
end
assign read_reserved_cmd = reserved_cmd_valid & (ch_status_state == CHANNEL_IDLE_STATE);
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// FThread State Machine ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk) begin
if(~rst_n) begin
ch_status_state <= 3'b0;
set_wr_if_direct_pipelined <= 0;
set_wr_if_mem_pipelined <= 0;
wr_mem_pipeline_addr <= 0;
set_rd_if_direct_pipelined <= 0;
set_rd_if_mem_pipelined <= 0;
rd_mem_pipeline_addr <= 0;
rd_mem_pipeline_addr_code <= 0;
rd_direct_pipeline_addr_code <= 0;
fthread_job_done <= 0;
start_d0 <= 0;
rif_done <= 0;
wif_done <= 0;
config_param_line <= 0;
run_rd_tx <= 0;
run_wr_tx <= 0;
ft_tx_wr_valid <= 0;
ft_tx_data <= 0;
ft_tx_wr_addr <= 0;
ft_tx_wr_tag <= 0;
ft_tx_rd_valid <= 0;
ft_tx_rd_addr <= 0;
ft_tx_rd_tag <= 0;
end
else begin
case (ch_status_state)
CHANNEL_IDLE_STATE: begin
/* If a valid job request is available in the command buffer, then we issue a status update that the job is starting
and compute some necessary flags for the configuration of the FThread Controller */
ft_tx_wr_valid <= 1'b0;
fthread_job_done <= 0;
start_d0 <= 0;
ft_tx_rd_valid <= 0;
rif_done <= 0;
wif_done <= 0;
if(cmd_buff_valid) begin
// Go to start state, set some flags
ch_status_state <= CHANNEL_STARTING_STATE;
// WR IF Config
set_wr_if_direct_pipelined <= (cmd_buff[121:120] == `WR_IF_DIRECT_PIPELINE_CODE);
set_wr_if_mem_pipelined <= (cmd_buff[121:120] == `WR_IF_MEM_PIPELINE_CODE);
wr_mem_pipeline_addr <= cmd_buff[179:122];
// RD IF Config
set_rd_if_direct_pipelined <= cmd_buff[180];
set_rd_if_mem_pipelined <= cmd_buff[181];
rd_mem_pipeline_addr <= cmd_buff[239:182];
rd_mem_pipeline_addr_code <= cmd_buff[243:240];
rd_direct_pipeline_addr_code <= cmd_buff[247:244];
// write fthread status as starting to the SW to see.
ft_tx_wr_valid <= 1'b1;
ft_tx_data <= {um_state_counters[255:0], ReadyCycles, ReadCycles, finishCycles, ConfigCycles, exeCycles, WrReqCnt, RdReqCnt, 29'b0, CHANNEL_STARTING_STATE};
ft_tx_wr_addr <= cmd_buff[57:0];
ft_tx_wr_tag <= 0;
end
end
CHANNEL_STARTING_STATE: begin
/* This state is just a stopby state until the starting status update request is sent to memory*/
if(ft_tx_wr_ready) begin
ch_status_state <= CHANNEL_CONFIG_STATE;
ft_tx_wr_valid <= 1'b0;
end
end
CHANNEL_CONFIG_STATE: begin
/* During this state the Config struct reader is started to read the user AFU configuration data structure.
When the configuration is obtained we switch to the Run state and trigger the user AFU*/
if (afu_config_struct_valid) begin
ch_status_state <= CHANNEL_RUN_STATE;
start_d0 <= 1'b1;
run_rd_tx <= 1'b1;
run_wr_tx <= 1'b1;
end
config_param_line <= afu_config_struct;
//
if(ft_tx_rd_ready) begin
ft_tx_rd_valid <= cfg_tx_rd_valid;
ft_tx_rd_addr <= cfg_tx_rd_addr;
ft_tx_rd_tag <= {1'b0, cfg_tx_rd_tag};
end
end
CHANNEL_RUN_STATE: begin
/* In this state the user AFU is active, we stay in this state until the user declares it finished processing and producing
all the results. Then we move to the Drain WR FIFO state, to make sure all user generated write requests are submitted to
memory*/
start_d0 <= 1'b0;
if(um_done) begin
ch_status_state <= CHANNEL_DRAIN_WR_FIFO_STATE;
config_param_line <= 0;
wif_done <= 1'b1;
rif_done <= 1'b1;
set_rd_if_direct_pipelined <= 0;
set_rd_if_mem_pipelined <= 0;
rd_mem_pipeline_addr <= 0;
rd_mem_pipeline_addr_code <= 0;
rd_direct_pipeline_addr_code <= 0;
end
//
// TX RD
if(ft_tx_rd_ready) begin
if(wif_tx_rd_valid) begin
ft_tx_rd_valid <= 1'b1;
ft_tx_rd_addr <= wif_tx_rd_addr;
ft_tx_rd_tag <= {1'b0, wif_tx_rd_tag};
end
else begin
ft_tx_rd_valid <= usr_arb_tx_rd_valid;
ft_tx_rd_addr <= usr_arb_tx_rd_addr;
ft_tx_rd_tag <= {1'b1, usr_arb_tx_rd_tag};
end
end
// TX WR
if(ft_tx_wr_ready) begin
if(rif_tx_wr_valid) begin
ft_tx_wr_valid <= 1'b1;
ft_tx_wr_addr <= rif_tx_wr_addr;
ft_tx_wr_tag <= {1'b0, rif_tx_wr_tag};
ft_tx_data <= rif_tx_data;
end
else begin
ft_tx_wr_valid <= usr_arb_tx_wr_valid;
ft_tx_wr_addr <= usr_arb_tx_wr_addr;
ft_tx_wr_tag <= {1'b1, usr_arb_tx_wr_tag};
ft_tx_data <= usr_arb_tx_data;
end
end
end
CHANNEL_DRAIN_WR_FIFO_STATE: begin
/* In this state we make sure all the write requests in the different FIFOs are submitted to memory*/
if (user_tx_wr_if_empty & tx_wr_fifo_empty & ~ft_tx_wr_valid) begin
ch_status_state <= CHANNEL_WRFENCE_STATE;
end
if(tx_wr_fifo_empty) begin
set_wr_if_direct_pipelined <= 0;
set_wr_if_mem_pipelined <= 0;
wr_mem_pipeline_addr <= 0;
end
// TX RD
if(ft_tx_rd_ready) begin
ft_tx_rd_valid <= wif_tx_rd_valid;
ft_tx_rd_addr <= wif_tx_rd_addr;
ft_tx_rd_tag <= {1'b0, wif_tx_rd_tag};
end
// TX WR
if(ft_tx_wr_ready) begin
if(rif_tx_wr_valid) begin
ft_tx_wr_valid <= 1'b1;
ft_tx_wr_addr <= rif_tx_wr_addr;
ft_tx_wr_tag <= {1'b0, rif_tx_wr_tag};
ft_tx_data <= rif_tx_data;
end
else begin
ft_tx_wr_valid <= usr_arb_tx_wr_valid;
ft_tx_wr_addr <= usr_arb_tx_wr_addr;
ft_tx_wr_tag <= {1'b1, usr_arb_tx_wr_tag};
ft_tx_data <= usr_arb_tx_data;
end
end
end
CHANNEL_WRFENCE_STATE: begin
run_rd_tx <= 0;
run_wr_tx <= 0;
if (writes_sent == writes_done) begin
ch_status_state <= CHANNEL_DONE_STATE;
//
ft_tx_wr_valid <= 1'b1;
ft_tx_data <= {um_state_counters[255:0], ReadyCycles, ReadCycles, finishCycles, ConfigCycles, exeCycles, WrReqCnt, RdReqCnt, 29'b0, CHANNEL_DONE_STATE};
ft_tx_wr_addr <= cmd_buff[57:0];
ft_tx_wr_tag <= 0;
end
end
CHANNEL_DONE_STATE: begin
if(ft_tx_wr_ready) begin
ch_status_state <= CHANNEL_DONE_RESP_STATE;
ft_tx_wr_valid <= 1'b0;
end
end
CHANNEL_DONE_RESP_STATE: begin
if(rx_wr_valid_reg) begin
ch_status_state <= CHANNEL_IDLE_STATE;
fthread_job_done <= 1'b1;
end
end
endcase
end
end
assign ft_tx_rd_ready = ~tx_rd_fifo_full;
assign wif_tx_rd_ready = ft_tx_rd_ready & run_rd_tx;
assign usr_arb_tx_rd_ready = ft_tx_rd_ready & run_rd_tx & ~wif_tx_rd_valid;
assign cfg_tx_rd_ready = ft_tx_rd_ready;
assign ft_tx_wr_ready = ~tx_wr_fifo_full;
assign rif_tx_wr_ready = ft_tx_wr_ready & run_wr_tx;
assign usr_arb_tx_wr_ready = ft_tx_wr_ready & run_wr_tx & ~rif_tx_wr_valid;
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// Configurer ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
ReadConfigStruct #(.MAX_NUM_CONFIG_CL(MAX_NUM_CONFIG_CL))
ReadConfigStruct (
.clk (clk),
.rst_n (rst_n & ~(ch_status_state == CHANNEL_DONE_RESP_STATE)),
//-------------------------------------------------//
.get_config_struct ( ch_status_state == CHANNEL_CONFIG_STATE ),
.base_addr (cmd_buff[115:58]),
.config_struct_length ( {28'b0, cmd_buff[119:116]}),
// User Module TX RD
.cs_tx_rd_addr (cfg_tx_rd_addr),
.cs_tx_rd_tag (cfg_tx_rd_tag),
.cs_tx_rd_valid (cfg_tx_rd_valid),
.cs_tx_rd_free (cfg_tx_rd_ready),
// User Module RX RD
.cs_rx_rd_tag (cfg_rx_rd_tag),
.cs_rx_rd_data (cfg_rx_data),
.cs_rx_rd_valid (cfg_rx_rd_valid),
//
.afu_config_struct (afu_config_struct),
.afu_config_struct_valid (afu_config_struct_valid)
);
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// ///////////////////////////////////
////////////////////////////// User Module Control Interface ///////////////////////////////
////////////////////////////////// ///////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
//
always@(posedge clk) begin
um_params <= config_param_line;
end
always@(posedge clk) begin
if( ~rst_n) begin
start_um <= 0;
end
else begin
start_um <= start_d0;
end
end
//assign um_params = config_param_line;
assign reset_user_logic = (ch_status_state == CHANNEL_IDLE_STATE);
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// User Module IO Interfaces ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// RD Interface
user_tx_rd_if #(.USER_TAG(USER_RD_TAG))
user_tx_rd_if(
.clk (clk),
.rst_n (rst_n),
.reset_interface ( (ch_status_state == CHANNEL_IDLE_STATE) ),
.set_if_mem_pipelined (set_rd_if_mem_pipelined),
.set_if_direct_pipelined (set_rd_if_direct_pipelined),
.mem_pipeline_addr (rd_mem_pipeline_addr),
.mem_pipeline_addr_code (rd_mem_pipeline_addr_code),
.direct_pipeline_addr_code (rd_direct_pipeline_addr_code),
.reads_finished (rif_done),
//--------------------- User RD Request -----------------------------//
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
//-------------------- to Fthread Controller ------------------------//
.usr_arb_tx_rd_valid (usr_arb_tx_rd_valid),
.usr_arb_tx_rd_addr (usr_arb_tx_rd_addr),
.usr_arb_tx_rd_tag (usr_arb_tx_rd_tag),
.usr_arb_tx_rd_ready (usr_arb_tx_rd_ready),
.usr_arb_rx_rd_valid (usr_arb_rx_rd_valid),
.usr_arb_rx_rd_tag (usr_arb_rx_rd_tag),
.usr_arb_rx_data (usr_arb_rx_data),
.rif_tx_wr_addr (rif_tx_wr_addr),
.rif_tx_wr_tag (rif_tx_wr_tag),
.rif_tx_wr_valid (rif_tx_wr_valid),
.rif_tx_data (rif_tx_data),
.rif_tx_wr_ready (rif_tx_wr_ready),
.rif_rx_wr_tag (rif_rx_wr_tag),
.rif_rx_wr_valid (rif_rx_wr_valid),
//-------------------- to pipeline writer ---------------------------//
.usr_pipe_tx_rd_valid (left_pipe_tx_rd_valid),
.usr_pipe_tx_rd_tag (left_pipe_tx_rd_tag),
.usr_pipe_tx_rd_ready (left_pipe_tx_rd_ready),
.usr_pipe_rx_rd_valid (left_pipe_rx_rd_valid),
.usr_pipe_rx_rd_tag (left_pipe_rx_rd_tag),
.usr_pipe_rx_data (left_pipe_rx_data),
.usr_pipe_rx_rd_ready (left_pipe_rx_rd_ready)
);
// WR Interface
user_tx_wr_if #(.USER_TAG(USER_WR_TAG) )
user_tx_wr_if(
.clk (clk),
.rst_n (rst_n),
.reset_interface ( (ch_status_state == CHANNEL_IDLE_STATE) ),
.set_if_pipelined (set_wr_if_direct_pipelined),
.user_tx_wr_if_empty (user_tx_wr_if_empty),
.set_if_mem_pipelined (set_wr_if_mem_pipelined),
.mem_pipeline_addr (wr_mem_pipeline_addr),
.writes_finished (wif_done),
//--------------------- User RD Request -----------------------------//
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag),
//-------------------- to Fthread Controller ------------------------//
.usr_arb_tx_wr_valid (usr_arb_tx_wr_valid),
.usr_arb_tx_wr_addr (usr_arb_tx_wr_addr),
.usr_arb_tx_wr_tag (usr_arb_tx_wr_tag),
.usr_arb_tx_wr_ready (usr_arb_tx_wr_ready),
.usr_arb_tx_data (usr_arb_tx_data),
.usr_arb_rx_wr_valid (usr_arb_rx_wr_valid),
.usr_arb_rx_wr_tag (usr_arb_rx_wr_tag),
.wif_tx_rd_addr (wif_tx_rd_addr),
.wif_tx_rd_tag (wif_tx_rd_tag),
.wif_tx_rd_valid (wif_tx_rd_valid),
.wif_tx_rd_ready (wif_tx_rd_ready),
.wif_rx_rd_tag (wif_rx_rd_tag),
.wif_rx_data (wif_rx_data),
.wif_rx_rd_valid (wif_rx_rd_valid),
//-------------------- To pipeline reader
.usr_pipe_tx_rd_valid (right_pipe_tx_rd_valid),
.usr_pipe_tx_rd_tag (right_pipe_tx_rd_tag),
.usr_pipe_tx_rd_ready (right_pipe_tx_rd_ready),
.usr_pipe_rx_rd_valid (right_pipe_rx_rd_valid),
.usr_pipe_rx_rd_tag (right_pipe_rx_rd_tag),
.usr_pipe_rx_data (right_pipe_rx_data),
.usr_pipe_rx_rd_ready (right_pipe_rx_rd_ready)
);
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// Profiling Counters ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk) begin
if(~rst_n | (ch_status_state == CHANNEL_IDLE_STATE)) begin
RdReqCnt <= 32'b0;
GRdReqCnt <= 32'b0;
WrReqCnt <= 32'b0;
exeCycles <= 32'b0;
finishCycles <= 32'b0;
ConfigCycles <= 32'b0;
ReadCycles <= 0;
ReadyCycles <= 0;
end
else begin
exeCycles <= exeCycles + 1'b1;
if(tx_rd_valid & tx_rd_ready) begin
GRdReqCnt <= GRdReqCnt + 1'b1;
end
if(um_tx_rd_valid & um_tx_rd_ready) begin
RdReqCnt <= RdReqCnt + 1'b1;
end
//
if(um_tx_wr_valid & um_tx_wr_ready) begin
WrReqCnt <= WrReqCnt + 1'b1;
end
//
if( ch_status_state[2] ) begin
finishCycles <= finishCycles + 1'b1;
end
//
if(ch_status_state == CHANNEL_CONFIG_STATE) begin
ConfigCycles <= ConfigCycles + 1'b1;
end
//
if(um_tx_rd_valid) begin
ReadCycles <= ReadCycles + 1'b1;
end
//
if(tx_rd_ready) begin
ReadyCycles <= ReadyCycles + 1'b1;
end
end
end
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:22:09 04/08/2015
// Design Name:
// Module Name: IntegerMultiplication
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module IntegerMultiplication(
input [31:0] A,
input [31:0] B,
output [63:0] product,
input start,
input clk
);
reg [65:0] accumulator;
reg [6:0] cnt;
reg oldStart;
wire [32:0] B2n,B1n,B1,B2,addend;
wire [63:0] result;
assign B1n[31:0] = -B,
B2n[31:0] = (-B)<<1,
B1[31:0] = B,
B2[31:0] = B<<1,
B1n[32] = ~B[31],
B2n[32] = ~B[31],
B1[32] = B[31],
B2[32] = B[31];
initial begin
accumulator[65:33] <= 0;
accumulator[32:1] <= A;
accumulator[0] <=0;
cnt <= 32;
end
AdderAndSubber64 adder({31'b0,accumulator[65:33]},{31'b0,addend},1'b0,result,SF,CF,OF,PF,ZF);
assign addend = {33{~accumulator[2]&~accumulator[1]&~accumulator[0]}}&33'b0|
{33{~accumulator[2]&~accumulator[1]& accumulator[0]}}&B1|
{33{~accumulator[2]& accumulator[1]&~accumulator[0]}}&B1|
{33{~accumulator[2]& accumulator[1]& accumulator[0]}}&B2|
{33{ accumulator[2]&~accumulator[1]&~accumulator[0]}}&B2n|
{33{ accumulator[2]&~accumulator[1]& accumulator[0]}}&B1n|
{33{ accumulator[2]& accumulator[1]&~accumulator[0]}}&B1n|
{33{ accumulator[2]& accumulator[1]& accumulator[0]}}&33'b0
;
always @(posedge clk) begin
if (cnt < 32) begin //accmulating
if(cnt[0]) begin
accumulator[63:0] <= accumulator>>>2;
accumulator[64] <= accumulator[65];
accumulator[65] <= accumulator[65];
end
else begin
accumulator[65:33] <= result[32:0];
end
cnt <= cnt + 1;
end
else if ( cnt == 32 && (start != old Start) ) begin //initial
accumulator[65:33] <= 0;
accumulator[32:1] <= A;
accumulator[0] <=0;
cnt <= 0;
end
else begin
accumulator <= accumulator;
cnt <= 6'd32;
end
oldStart <= start;
end
assign product = accumulator[64:1];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A41OI_BEHAVIORAL_PP_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41OI_BEHAVIORAL_PP_V |
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: mul_19_12.v
// /___/ /\ Timestamp: Tue Mar 31 01:42:14 2015
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/zlozony/ipcore_dir/mul_19_12/tmp/_cg/mul_19_12.ngc C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/zlozony/ipcore_dir/mul_19_12/tmp/_cg/mul_19_12.v
// Device : 6slx45csg324-2
// Input file : C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/zlozony/ipcore_dir/mul_19_12/tmp/_cg/mul_19_12.ngc
// Output file : C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/zlozony/ipcore_dir/mul_19_12/tmp/_cg/mul_19_12.v
// # of Modules : 1
// Design Name : mul_19_12
// Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module mul_19_12 (
clk, ce, a, b, p
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input ce;
input [18 : 0] a;
input [11 : 0] b;
output [30 : 0] p;
// synthesis translate_off
wire \blk00000001/sig000000f7 ;
wire \blk00000001/sig000000f6 ;
wire \blk00000001/sig000000f5 ;
wire \blk00000001/sig000000f4 ;
wire \blk00000001/sig000000f3 ;
wire \blk00000001/sig000000f2 ;
wire \blk00000001/sig000000f1 ;
wire \blk00000001/sig000000f0 ;
wire \blk00000001/sig000000ef ;
wire \blk00000001/sig000000ee ;
wire \blk00000001/sig000000ed ;
wire \blk00000001/sig000000ec ;
wire \blk00000001/sig000000eb ;
wire \blk00000001/sig000000ea ;
wire \blk00000001/sig000000e9 ;
wire \blk00000001/sig000000e8 ;
wire \blk00000001/sig000000e7 ;
wire \blk00000001/sig000000e6 ;
wire \blk00000001/sig000000e5 ;
wire \blk00000001/sig000000e4 ;
wire \blk00000001/sig000000e3 ;
wire \blk00000001/sig000000e2 ;
wire \blk00000001/sig000000e1 ;
wire \blk00000001/sig000000e0 ;
wire \blk00000001/sig000000df ;
wire \blk00000001/sig000000de ;
wire \blk00000001/sig000000dd ;
wire \blk00000001/sig000000dc ;
wire \blk00000001/sig000000db ;
wire \blk00000001/sig000000da ;
wire \blk00000001/sig000000d9 ;
wire \blk00000001/sig000000d8 ;
wire \blk00000001/sig000000d7 ;
wire \blk00000001/sig000000d6 ;
wire \blk00000001/sig000000d5 ;
wire \blk00000001/sig000000d4 ;
wire \blk00000001/sig000000d3 ;
wire \blk00000001/sig000000d2 ;
wire \blk00000001/sig000000d1 ;
wire \blk00000001/sig000000d0 ;
wire \blk00000001/sig000000cf ;
wire \blk00000001/sig000000ce ;
wire \blk00000001/sig000000cd ;
wire \blk00000001/sig000000cc ;
wire \blk00000001/sig000000cb ;
wire \blk00000001/sig000000ca ;
wire \blk00000001/sig000000c9 ;
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/sig00000044 ;
wire \blk00000001/sig00000043 ;
wire \blk00000001/sig00000042 ;
wire \blk00000001/sig00000041 ;
wire \NLW_blk00000001/blk00000005_CARRYOUTF_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_CARRYOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_C<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_M<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_CARRYOUTF_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_CARRYOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_M<0>_UNCONNECTED ;
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000029 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f7 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[0])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000028 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f6 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[1])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000027 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f5 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[2])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000026 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f4 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[3])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000025 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f3 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[4])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000024 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f2 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[5])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000023 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f1 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[6])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000022 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000f0 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[7])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000021 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000ef ),
.R(\blk00000001/sig000000e4 ),
.Q(p[8])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000020 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000ee ),
.R(\blk00000001/sig000000e4 ),
.Q(p[9])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000ed ),
.R(\blk00000001/sig000000e4 ),
.Q(p[10])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000ec ),
.R(\blk00000001/sig000000e4 ),
.Q(p[11])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000eb ),
.R(\blk00000001/sig000000e4 ),
.Q(p[12])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000ea ),
.R(\blk00000001/sig000000e4 ),
.Q(p[13])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000e9 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[14])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000e8 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[15])
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000019 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000e7 ),
.R(\blk00000001/sig000000e4 ),
.Q(p[16])
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000018 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c1 ),
.Q(\blk00000001/sig000000f7 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000017 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c2 ),
.Q(\blk00000001/sig000000f6 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000016 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c3 ),
.Q(\blk00000001/sig000000f5 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000015 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c4 ),
.Q(\blk00000001/sig000000f4 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000014 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c5 ),
.Q(\blk00000001/sig000000f3 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000013 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c6 ),
.Q(\blk00000001/sig000000f2 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000012 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c7 ),
.Q(\blk00000001/sig000000f1 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000011 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c8 ),
.Q(\blk00000001/sig000000f0 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000010 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000c9 ),
.Q(\blk00000001/sig000000ef )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000000f (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000ca ),
.Q(\blk00000001/sig000000ee )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000000e (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000cb ),
.Q(\blk00000001/sig000000ed )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000000d (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000cc ),
.Q(\blk00000001/sig000000ec )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000000c (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000cd ),
.Q(\blk00000001/sig000000eb )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000000b (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000ce ),
.Q(\blk00000001/sig000000ea )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000000a (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000cf ),
.Q(\blk00000001/sig000000e9 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000009 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000d0 ),
.Q(\blk00000001/sig000000e8 )
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000008 (
.A0(\blk00000001/sig000000e4 ),
.A1(\blk00000001/sig000000e4 ),
.A2(\blk00000001/sig000000e4 ),
.A3(\blk00000001/sig000000e4 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000d1 ),
.Q(\blk00000001/sig000000e7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000007 (
.C(clk),
.CE(ce),
.D(a[17]),
.Q(\blk00000001/sig000000e5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000006 (
.C(clk),
.CE(ce),
.D(a[18]),
.Q(\blk00000001/sig000000e6 )
);
DSP48A1 #(
.A0REG ( 0 ),
.A1REG ( 1 ),
.B0REG ( 0 ),
.B1REG ( 1 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 0 ),
.DREG ( 0 ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PREG ( 1 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
\blk00000001/blk00000005 (
.CECARRYIN(\blk00000001/sig000000e4 ),
.RSTC(\blk00000001/sig000000e4 ),
.RSTCARRYIN(\blk00000001/sig000000e4 ),
.CED(\blk00000001/sig000000e4 ),
.RSTD(\blk00000001/sig000000e4 ),
.CEOPMODE(\blk00000001/sig000000e4 ),
.CEC(\blk00000001/sig000000e4 ),
.CARRYOUTF(\NLW_blk00000001/blk00000005_CARRYOUTF_UNCONNECTED ),
.RSTOPMODE(\blk00000001/sig000000e4 ),
.RSTM(\blk00000001/sig000000e4 ),
.CLK(clk),
.RSTB(\blk00000001/sig000000e4 ),
.CEM(ce),
.CEB(ce),
.CARRYIN(\blk00000001/sig000000e4 ),
.CEP(ce),
.CEA(ce),
.CARRYOUT(\NLW_blk00000001/blk00000005_CARRYOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000000e4 ),
.RSTP(\blk00000001/sig000000e4 ),
.B({b[11], b[11], b[11], b[11], b[11], b[11], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
.BCOUT({\blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 , \blk00000001/sig000000e0 , \blk00000001/sig000000df ,
\blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc , \blk00000001/sig000000db , \blk00000001/sig000000da ,
\blk00000001/sig000000d9 , \blk00000001/sig000000d8 , \blk00000001/sig000000d7 , \blk00000001/sig000000d6 , \blk00000001/sig000000d5 ,
\blk00000001/sig000000d4 , \blk00000001/sig000000d3 , \blk00000001/sig000000d2 }),
.PCIN({\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 }),
.C({\NLW_blk00000001/blk00000005_C<47>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<46>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<45>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<44>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<43>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<42>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<41>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<40>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<39>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<38>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<37>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<36>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<35>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<33>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<32>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<30>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<29>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<27>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<26>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<24>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<23>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<21>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<20>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<18>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<17>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<15>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<14>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<13>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<12>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<11>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<9>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<8>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<7>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<6>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<5>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<3>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<2>_UNCONNECTED , \NLW_blk00000001/blk00000005_C<1>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_C<0>_UNCONNECTED }),
.P({\blk00000001/sig000000c0 , \blk00000001/sig000000bf , \blk00000001/sig000000be , \blk00000001/sig000000bd , \blk00000001/sig000000bc ,
\blk00000001/sig000000bb , \blk00000001/sig000000ba , \blk00000001/sig000000b9 , \blk00000001/sig000000b8 , \blk00000001/sig000000b7 ,
\blk00000001/sig000000b6 , \blk00000001/sig000000b5 , \blk00000001/sig000000b4 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 ,
\blk00000001/sig000000b1 , \blk00000001/sig000000b0 , \blk00000001/sig000000af , \blk00000001/sig000000ae , \blk00000001/sig000000ad ,
\blk00000001/sig000000ac , \blk00000001/sig000000ab , \blk00000001/sig000000aa , \blk00000001/sig000000a9 , \blk00000001/sig000000a8 ,
\blk00000001/sig000000a7 , \blk00000001/sig000000a6 , \blk00000001/sig000000a5 , \blk00000001/sig000000a4 , \blk00000001/sig000000a3 ,
\blk00000001/sig000000a2 , \blk00000001/sig000000d1 , \blk00000001/sig000000d0 , \blk00000001/sig000000cf , \blk00000001/sig000000ce ,
\blk00000001/sig000000cd , \blk00000001/sig000000cc , \blk00000001/sig000000cb , \blk00000001/sig000000ca , \blk00000001/sig000000c9 ,
\blk00000001/sig000000c8 , \blk00000001/sig000000c7 , \blk00000001/sig000000c6 , \blk00000001/sig000000c5 , \blk00000001/sig000000c4 ,
\blk00000001/sig000000c3 , \blk00000001/sig000000c2 , \blk00000001/sig000000c1 }),
.OPMODE({\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig00000071 }),
.D({\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 }),
.PCOUT({\blk00000001/sig000000a1 , \blk00000001/sig000000a0 , \blk00000001/sig0000009f , \blk00000001/sig0000009e , \blk00000001/sig0000009d ,
\blk00000001/sig0000009c , \blk00000001/sig0000009b , \blk00000001/sig0000009a , \blk00000001/sig00000099 , \blk00000001/sig00000098 ,
\blk00000001/sig00000097 , \blk00000001/sig00000096 , \blk00000001/sig00000095 , \blk00000001/sig00000094 , \blk00000001/sig00000093 ,
\blk00000001/sig00000092 , \blk00000001/sig00000091 , \blk00000001/sig00000090 , \blk00000001/sig0000008f , \blk00000001/sig0000008e ,
\blk00000001/sig0000008d , \blk00000001/sig0000008c , \blk00000001/sig0000008b , \blk00000001/sig0000008a , \blk00000001/sig00000089 ,
\blk00000001/sig00000088 , \blk00000001/sig00000087 , \blk00000001/sig00000086 , \blk00000001/sig00000085 , \blk00000001/sig00000084 ,
\blk00000001/sig00000083 , \blk00000001/sig00000082 , \blk00000001/sig00000081 , \blk00000001/sig00000080 , \blk00000001/sig0000007f ,
\blk00000001/sig0000007e , \blk00000001/sig0000007d , \blk00000001/sig0000007c , \blk00000001/sig0000007b , \blk00000001/sig0000007a ,
\blk00000001/sig00000079 , \blk00000001/sig00000078 , \blk00000001/sig00000077 , \blk00000001/sig00000076 , \blk00000001/sig00000075 ,
\blk00000001/sig00000074 , \blk00000001/sig00000073 , \blk00000001/sig00000072 }),
.A({\blk00000001/sig000000e4 , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
.M({\NLW_blk00000001/blk00000005_M<35>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<33>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<32>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<30>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<29>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<27>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<26>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<24>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<23>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<21>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<20>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<18>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<17>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<15>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<14>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<13>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<12>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<11>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<9>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<8>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<7>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<6>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<5>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<3>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<2>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<1>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_M<0>_UNCONNECTED })
);
DSP48A1 #(
.A0REG ( 1 ),
.A1REG ( 1 ),
.B0REG ( 1 ),
.B1REG ( 1 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 1 ),
.DREG ( 0 ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PREG ( 1 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
\blk00000001/blk00000004 (
.CECARRYIN(\blk00000001/sig000000e4 ),
.RSTC(\blk00000001/sig000000e4 ),
.RSTCARRYIN(\blk00000001/sig000000e4 ),
.CED(\blk00000001/sig000000e4 ),
.RSTD(\blk00000001/sig000000e4 ),
.CEOPMODE(\blk00000001/sig000000e4 ),
.CEC(ce),
.CARRYOUTF(\NLW_blk00000001/blk00000004_CARRYOUTF_UNCONNECTED ),
.RSTOPMODE(\blk00000001/sig000000e4 ),
.RSTM(\blk00000001/sig000000e4 ),
.CLK(clk),
.RSTB(\blk00000001/sig000000e4 ),
.CEM(ce),
.CEB(ce),
.CARRYIN(\blk00000001/sig000000e4 ),
.CEP(ce),
.CEA(ce),
.CARRYOUT(\NLW_blk00000001/blk00000004_CARRYOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000000e4 ),
.RSTP(\blk00000001/sig000000e4 ),
.B({\blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 , \blk00000001/sig000000e0 , \blk00000001/sig000000df ,
\blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc , \blk00000001/sig000000db , \blk00000001/sig000000da ,
\blk00000001/sig000000d9 , \blk00000001/sig000000d8 , \blk00000001/sig000000d7 , \blk00000001/sig000000d6 , \blk00000001/sig000000d5 ,
\blk00000001/sig000000d4 , \blk00000001/sig000000d3 , \blk00000001/sig000000d2 }),
.BCOUT({\NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED }),
.PCIN({\blk00000001/sig000000a1 , \blk00000001/sig000000a0 , \blk00000001/sig0000009f , \blk00000001/sig0000009e , \blk00000001/sig0000009d ,
\blk00000001/sig0000009c , \blk00000001/sig0000009b , \blk00000001/sig0000009a , \blk00000001/sig00000099 , \blk00000001/sig00000098 ,
\blk00000001/sig00000097 , \blk00000001/sig00000096 , \blk00000001/sig00000095 , \blk00000001/sig00000094 , \blk00000001/sig00000093 ,
\blk00000001/sig00000092 , \blk00000001/sig00000091 , \blk00000001/sig00000090 , \blk00000001/sig0000008f , \blk00000001/sig0000008e ,
\blk00000001/sig0000008d , \blk00000001/sig0000008c , \blk00000001/sig0000008b , \blk00000001/sig0000008a , \blk00000001/sig00000089 ,
\blk00000001/sig00000088 , \blk00000001/sig00000087 , \blk00000001/sig00000086 , \blk00000001/sig00000085 , \blk00000001/sig00000084 ,
\blk00000001/sig00000083 , \blk00000001/sig00000082 , \blk00000001/sig00000081 , \blk00000001/sig00000080 , \blk00000001/sig0000007f ,
\blk00000001/sig0000007e , \blk00000001/sig0000007d , \blk00000001/sig0000007c , \blk00000001/sig0000007b , \blk00000001/sig0000007a ,
\blk00000001/sig00000079 , \blk00000001/sig00000078 , \blk00000001/sig00000077 , \blk00000001/sig00000076 , \blk00000001/sig00000075 ,
\blk00000001/sig00000074 , \blk00000001/sig00000073 , \blk00000001/sig00000072 }),
.C({\blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 ,
\blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 ,
\blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 ,
\blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000c0 , \blk00000001/sig000000bf , \blk00000001/sig000000be ,
\blk00000001/sig000000bd , \blk00000001/sig000000bc , \blk00000001/sig000000bb , \blk00000001/sig000000ba , \blk00000001/sig000000b9 ,
\blk00000001/sig000000b8 , \blk00000001/sig000000b7 , \blk00000001/sig000000b6 , \blk00000001/sig000000b5 , \blk00000001/sig000000b4 ,
\blk00000001/sig000000b3 , \blk00000001/sig000000b2 , \blk00000001/sig000000b1 , \blk00000001/sig000000b0 , \blk00000001/sig000000af ,
\blk00000001/sig000000ae , \blk00000001/sig000000ad , \blk00000001/sig000000ac , \blk00000001/sig000000ab , \blk00000001/sig000000aa ,
\blk00000001/sig000000a9 , \blk00000001/sig000000a8 , \blk00000001/sig000000a7 , \blk00000001/sig000000a6 , \blk00000001/sig000000a5 ,
\blk00000001/sig000000a4 , \blk00000001/sig000000a3 , \blk00000001/sig000000a2 }),
.P({\NLW_blk00000001/blk00000004_P<47>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<45>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<44>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<42>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<41>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<39>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<38>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<36>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<18>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<14>_UNCONNECTED , p[30], p[29], p[28], p[27], p[26], p[25], p[24],
p[23], p[22], p[21], p[20], p[19], p[18], p[17]}),
.OPMODE({\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig00000071 ,
\blk00000001/sig00000071 , \blk00000001/sig000000e4 , \blk00000001/sig00000071 }),
.D({\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 ,
\blk00000001/sig000000e4 , \blk00000001/sig000000e4 , \blk00000001/sig000000e4 }),
.PCOUT({\blk00000001/sig00000041 , \blk00000001/sig00000042 , \blk00000001/sig00000043 , \blk00000001/sig00000044 , \blk00000001/sig00000045 ,
\blk00000001/sig00000046 , \blk00000001/sig00000047 , \blk00000001/sig00000048 , \blk00000001/sig00000049 , \blk00000001/sig0000004a ,
\blk00000001/sig0000004b , \blk00000001/sig0000004c , \blk00000001/sig0000004d , \blk00000001/sig0000004e , \blk00000001/sig0000004f ,
\blk00000001/sig00000050 , \blk00000001/sig00000051 , \blk00000001/sig00000052 , \blk00000001/sig00000053 , \blk00000001/sig00000054 ,
\blk00000001/sig00000055 , \blk00000001/sig00000056 , \blk00000001/sig00000057 , \blk00000001/sig00000058 , \blk00000001/sig00000059 ,
\blk00000001/sig0000005a , \blk00000001/sig0000005b , \blk00000001/sig0000005c , \blk00000001/sig0000005d , \blk00000001/sig0000005e ,
\blk00000001/sig0000005f , \blk00000001/sig00000060 , \blk00000001/sig00000061 , \blk00000001/sig00000062 , \blk00000001/sig00000063 ,
\blk00000001/sig00000064 , \blk00000001/sig00000065 , \blk00000001/sig00000066 , \blk00000001/sig00000067 , \blk00000001/sig00000068 ,
\blk00000001/sig00000069 , \blk00000001/sig0000006a , \blk00000001/sig0000006b , \blk00000001/sig0000006c , \blk00000001/sig0000006d ,
\blk00000001/sig0000006e , \blk00000001/sig0000006f , \blk00000001/sig00000070 }),
.A({\blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 ,
\blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 ,
\blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e6 ,
\blk00000001/sig000000e6 , \blk00000001/sig000000e6 , \blk00000001/sig000000e5 }),
.M({\NLW_blk00000001/blk00000004_M<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<32>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<30>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<29>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<27>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<26>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<24>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<23>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<21>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<20>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<18>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<14>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<13>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<12>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<8>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<7>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<6>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<2>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<1>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_M<0>_UNCONNECTED })
);
GND \blk00000001/blk00000003 (
.G(\blk00000001/sig000000e4 )
);
VCC \blk00000001/blk00000002 (
.P(\blk00000001/sig00000071 )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
module note2dds_5st_gen(clk, note, adder);
input wire clk;
input wire [6:0] note;
output [31:0] adder;
(* romstyle = "logic" *) reg [31:0] table_values;
reg [4:0] addr_reg;
wire [3:0] diap = (note < 12) ? 4'd00 :
(note < 24) ? 4'd01 :
(note < 36) ? 4'd02 :
(note < 48) ? 4'd03 :
(note < 60) ? 4'd04 :
(note < 72) ? 4'd05 :
(note < 84) ? 4'd06 :
(note < 96) ? 4'd07 :
(note < 108) ? 4'd08 :
(note < 120) ? 4'd09 : 4'd010 ;
wire [6:0] c_addr = note - (diap * 4'd012);
wire [3:0] divider = 4'd010 - diap;
always@(posedge clk) begin
addr_reg <= c_addr[3:0];
case(addr_reg)
4'd00: table_values <= 32'd0359575;
4'd01: table_values <= 32'd0380957;
4'd02: table_values <= 32'd0403610;
4'd03: table_values <= 32'd0427610;
4'd04: table_values <= 32'd0453037;
4'd05: table_values <= 32'd0479976;
4'd06: table_values <= 32'd0508516;
4'd07: table_values <= 32'd0538754;
4'd08: table_values <= 32'd0570790;
4'd09: table_values <= 32'd0604731;
4'd10: table_values <= 32'd0640691;
4'd11: table_values <= 32'd0678788;
4'd12: table_values <= 32'd0;
4'd13: table_values <= 32'd0;
4'd14: table_values <= 32'd0;
4'd15: table_values <= 32'd0;
endcase
end
assign adder = table_values >> divider;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// XESS Flash interface ////
//// ////
//// This file is part of the OR1K test application ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Connects the SoC to the Flash found on XSV board. It also ////
//// implements a generic flash model for simulations. ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Lior Shtram, [email protected] ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: flash_top.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.4 2002/09/16 02:51:23 lampret
// Delayed wb_err_o. Disabled wb_ack_o when wb_err_o is asserted.
//
// Revision 1.3 2002/08/14 06:24:43 lampret
// Fixed size of generic flash/sram to exactly 2MB
//
// Revision 1.2 2002/08/12 05:33:50 lampret
// Changed logic when FLASH_GENERIC_REGISTERED
//
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.4 2002/02/11 04:41:01 lampret
// Allow flash writes. Ugly workaround for something else...
//
// Revision 1.3 2002/01/23 07:50:44 lampret
// Added wb_err_o to flash and sram i/f for testing the buserr exception.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1.1.1 2001/11/04 19:00:09 lampret
// First import.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
//`include "bench_define.v"
`ifdef FLASH_GENERIC
module flash_top (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
flash_rstn, cen, oen, wen, rdy, d, a, a_oe
);
//
// I/O Ports
//
//
// Common WB signals
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Flash i/f
//
output flash_rstn;
output oen;
output cen;
output wen;
input rdy;
inout [7:0] d;
output [20:0] a;
output a_oe;
//
// Internal wires and regs
//
reg [7:0] mem [2097151:0];
wire [31:0] adr;
`ifdef FLASH_GENERIC_REGISTERED
reg wb_err_o;
reg [31:0] prev_adr;
reg [1:0] delay;
`else
wire [1:0] delay;
`endif
wire wb_err;
//
// Aliases and simple assignments
//
assign flash_rstn = 1'b1;
assign oen = 1'b1;
assign cen = 1'b1;
assign wen = 1'b1;
assign a = 21'b0;
assign a_oe = 1'b1;
assign wb_err = wb_cyc_i & wb_stb_i & (delay == 2'd0) & (|wb_adr_i[23:21]); // If Access to > 2MB (8-bit leading prefix ignored)
assign adr = {8'h00, wb_adr_i[23:2], 2'b00};
//
// For simulation only
//
initial $readmemh("../src/flash.in", mem, 0);
//
// Reading from flash model
//
assign wb_dat_o[7:0] = wb_adr_i[23:0] < 65535 ? mem[adr+3] : 8'h00;
assign wb_dat_o[15:8] = wb_adr_i[23:0] < 65535 ? mem[adr+2] : 8'h00;
assign wb_dat_o[23:16] = wb_adr_i[23:0] < 65535 ? mem[adr+1] : 8'h00;
assign wb_dat_o[31:24] = wb_adr_i[23:0] < 65535 ? mem[adr+0] : 8'h00;
`ifdef FLASH_GENERIC_REGISTERED
//
// WB Acknowledge
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) begin
delay <= #1 2'd3;
prev_adr <= #1 32'h0000_0000;
end
else if (delay && (wb_adr_i == prev_adr) && wb_cyc_i && wb_stb_i)
delay <= #1 delay - 2'd1;
else if (wb_ack_o || wb_err_o || (wb_adr_i != prev_adr) || ~wb_stb_i) begin
delay <= #1 2'd0; // delay ... can range from 3 to 0
prev_adr <= #1 wb_adr_i;
end
`else
assign delay = 2'd0;
`endif
assign wb_ack_o = wb_cyc_i & wb_stb_i & ~wb_err & (delay == 2'd0)
`ifdef FLASH_GENERIC_REGISTERED
& (wb_adr_i == prev_adr)
`endif
;
`ifdef FLASH_GENERIC_REGISTERED
//
// WB Error
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_err_o <= #1 1'b0;
else
wb_err_o <= #1 wb_err & !wb_err_o;
`else
assign wb_err_o = wb_err;
`endif
//
// Flash i/f monitor
//
// synopsys translate_off
integer fflash;
initial fflash = $fopen("flash.log");
always @(posedge wb_clk_i)
if (wb_cyc_i)
if (wb_stb_i & wb_we_i) begin
// $fdisplay(fflash, "%t Trying to write into flash at %h (%b)", $time, wb_adr_i, wb_we_i);
// #100 $finish;
if (wb_sel_i[3])
mem[{wb_adr_i[23:2], 2'b00}+0] = wb_dat_i[31:24];
if (wb_sel_i[2])
mem[{wb_adr_i[23:2], 2'b00}+1] = wb_dat_i[23:16];
if (wb_sel_i[1])
mem[{wb_adr_i[23:2], 2'b00}+2] = wb_dat_i[15:8];
if (wb_sel_i[0])
mem[{wb_adr_i[23:2], 2'b00}+3] = wb_dat_i[7:0];
$fdisplay(fflash, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);
end else if (wb_ack_o)
$fdisplay(fflash, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);
// synopsys translate_on
endmodule
`else
module flash_top (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
flash_rstn, cen, oen, wen, rdy, d, a, a_oe
);
//
// I/O Ports
//
//
// Common WB signals
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Flash i/f
//
output flash_rstn;
output oen;
output cen;
output wen;
input rdy;
inout [7:0] d;
output [20:0] a;
output a_oe;
//
// Internal wires and regs
//
reg ack;
reg [3:0] middle_tphqv;
reg [31:0] wb_dat_o;
reg [4:0] counter;
//
// Aliases and simple assignments
//
assign wb_ack_o = ~wb_err_o & ack;
assign wb_err_o = 1'b0;
assign flash_rstn = ~wb_rst_i;
assign a = { ~wb_adr_i[20], wb_adr_i[19:2], counter[3:2] }; // Lower 1MB is used by FPGA design conf.
assign a_oe = (wb_cyc_i &! (|middle_tphqv));
assign oen = |middle_tphqv;
assign wen = 1'b1;
assign cen = ~wb_cyc_i | ~wb_stb_i | (|middle_tphqv) | (counter[1:0] == 2'b00);
//
// Flash access time counter
//
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
counter <= #1 5'h0;
else
if (!wb_cyc_i | (counter == 5'h10) | (|middle_tphqv))
counter <= #1 5'h0;
else
counter <= #1 counter + 1;
end
//
// Acknowledge
//
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack <= #1 1'h0;
else
if (counter == 5'h0f && !(|middle_tphqv))
ack <= #1 1'h1;
else
ack <= #1 1'h0;
end
//
// Flash i/f monitor
//
// synopsys translate_off
integer fflash;
initial fflash = $fopen("flash.log");
always @(posedge wb_clk_i)
begin
if (wb_cyc_i & !(|middle_tphqv)) begin
if (wb_stb_i & wb_we_i) begin
$fdisplay(fflash, "%t Trying to write into flash at %h", $time, wb_adr_i);
// #100 $finish;
end
else if (ack)
$fdisplay(fflash, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);
end
end
// synopsys translate_on
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
middle_tphqv <= #1 4'hf;
else if (middle_tphqv)
middle_tphqv <= #1 middle_tphqv - 1;
//
// Flash 8-bit data expand into 32-bit WB data
//
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wb_dat_o <= #1 32'h0000_0000;
else
if (counter[1:0] == 2'h3)
begin
case (counter[3:2])
2'h0 : wb_dat_o[31:24] <= #1 d;
2'h1 : wb_dat_o[23:16] <= #1 d;
2'h2 : wb_dat_o[15:8] <= #1 d;
2'h3 : wb_dat_o[7:0] <= #1 d;
endcase
end
end
endmodule
`endif
|
(* src = "../../verilog/adt7310.v:1" *)
module ADT7310 (
(* intersynth_port = "Reset_n_i", src = "../../verilog/adt7310.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/adt7310.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/adt7310.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/adt7310.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/adt7310.v:11" *)
output ADT7310CS_n_o,
(* intersynth_conntype = "Byte", intersynth_port = "SPI_DataOut", src = "../../verilog/adt7310.v:13" *)
input[7:0] SPI_Data_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_Write", src = "../../verilog/adt7310.v:15" *)
output SPI_Write_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_ReadNext", src = "../../verilog/adt7310.v:17" *)
output SPI_ReadNext_o,
(* intersynth_conntype = "Byte", intersynth_port = "SPI_DataIn", src = "../../verilog/adt7310.v:19" *)
output[7:0] SPI_Data_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_FIFOFull", src = "../../verilog/adt7310.v:21" *)
input SPI_FIFOFull_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_FIFOEmpty", src = "../../verilog/adt7310.v:23" *)
input SPI_FIFOEmpty_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_Transmission", src = "../../verilog/adt7310.v:25" *)
input SPI_Transmission_i,
(* intersynth_conntype = "Word", intersynth_param = "SPICounterPresetH_i", src = "../../verilog/adt7310.v:27" *)
input[15:0] SPICounterPresetH_i,
(* intersynth_conntype = "Word", intersynth_param = "SPICounterPresetL_i", src = "../../verilog/adt7310.v:29" *)
input[15:0] SPICounterPresetL_i,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/adt7310.v:31" *)
input[15:0] Threshold_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPreset_i", src = "../../verilog/adt7310.v:33" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/adt7310.v:35" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_CPOL", src = "../../verilog/adt7310.v:37" *)
output SPI_CPOL_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_CPHA", src = "../../verilog/adt7310.v:39" *)
output SPI_CPHA_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_LSBFE", src = "../../verilog/adt7310.v:41" *)
output SPI_LSBFE_o
);
(* src = "../../verilog/spifsm.v:187" *)
wire [7:0] \$techmap\SPIFSM_1.$0\Byte0_o[7:0] ;
(* src = "../../verilog/spifsm.v:187" *)
wire [7:0] \$techmap\SPIFSM_1.$0\Byte1_o[7:0] ;
(* src = "../../verilog/spifsm.v:217" *)
wire [31:0] \$techmap\SPIFSM_1.$0\SPI_FSM_Timer[31:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire \$techmap\SPIFSM_1.$2\ADT7310CS_n_o[0:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire \$techmap\SPIFSM_1.$2\SPI_FSM_TimerEnable[0:0] ;
(* src = "../../verilog/spifsm.v:65" *)
wire \$techmap\SPIFSM_1.$2\SPI_ReadNext_o[0:0] ;
wire \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2453 ;
wire \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2455 ;
wire \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2457 ;
wire \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2459 ;
wire \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2461 ;
wire \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2477 ;
wire \$techmap\SPIFSM_1.$procmux$297_CMP ;
wire \$techmap\SPIFSM_1.$procmux$298_CMP ;
wire \$techmap\SPIFSM_1.$procmux$301_CMP ;
wire \$techmap\SPIFSM_1.$procmux$302_CMP ;
wire \$techmap\SPIFSM_1.$procmux$305_CMP ;
wire \$techmap\SPIFSM_1.$procmux$334_CMP ;
wire \$techmap\SPIFSM_1.$procmux$335_CMP ;
wire \$techmap\SPIFSM_1.$procmux$336_CMP ;
wire [31:0] \$techmap\SPIFSM_1.$procmux$80_Y ;
(* src = "../../verilog/spifsm.v:231" *)
wire [31:0] \$techmap\SPIFSM_1.$sub$../../verilog/spifsm.v:231$46_Y ;
(* src = "../../verilog/sensorfsm.v:130" *)
wire [15:0] \$techmap\SensorFSM_1.$0\SensorFSM_Timer[15:0] ;
(* src = "../../verilog/sensorfsm.v:153" *)
wire [15:0] \$techmap\SensorFSM_1.$0\Word0[15:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$techmap\SensorFSM_1.$2\MeasureFSM_Start_o[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$techmap\SensorFSM_1.$2\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$techmap\SensorFSM_1.$2\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$techmap\SensorFSM_1.$3\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:57" *)
wire \$techmap\SensorFSM_1.$4\SensorFSM_TimerPreset[0:0] ;
wire \$techmap\SensorFSM_1.$auto$opt_reduce.cc:126:opt_mux$2463 ;
wire \$techmap\SensorFSM_1.$procmux$1004_CMP ;
wire \$techmap\SensorFSM_1.$procmux$1007_CMP ;
wire \$techmap\SensorFSM_1.$procmux$1129_CMP ;
wire [15:0] \$techmap\SensorFSM_1.$procmux$826_Y ;
(* src = "../../verilog/sensorfsm.v:144" *)
wire [15:0] \$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:144$59_Y ;
(* src = "../../verilog/spifsm.v:24" *)
wire \SPIFSM_1.ADT7310CS_n_o ;
(* src = "../../verilog/spifsm.v:13" *)
wire [7:0] \SPIFSM_1.Byte0_o ;
(* src = "../../verilog/spifsm.v:14" *)
wire [7:0] \SPIFSM_1.Byte1_o ;
(* src = "../../verilog/spifsm.v:9" *)
wire \SPIFSM_1.Clk_i ;
(* src = "../../verilog/spifsm.v:12" *)
wire \SPIFSM_1.Done_o ;
(* src = "../../verilog/spifsm.v:26" *)
wire [31:0] \SPIFSM_1.ParamCounterPreset_i ;
(* src = "../../verilog/spifsm.v:8" *)
wire \SPIFSM_1.Reset_n_i ;
(* src = "../../verilog/spifsm.v:20" *)
wire [7:0] \SPIFSM_1.SPI_Data_i ;
(* src = "../../verilog/spifsm.v:19" *)
wire [7:0] \SPIFSM_1.SPI_Data_o ;
(* src = "../../verilog/spifsm.v:22" *)
wire \SPIFSM_1.SPI_FIFOEmpty_i ;
(* src = "../../verilog/spifsm.v:21" *)
wire \SPIFSM_1.SPI_FIFOFull_i ;
(* src = "../../verilog/spifsm.v:215" *)
wire [31:0] \SPIFSM_1.SPI_FSM_Timer ;
(* src = "../../verilog/spifsm.v:45" *)
wire \SPIFSM_1.SPI_FSM_TimerEnable ;
(* src = "../../verilog/spifsm.v:43" *)
wire \SPIFSM_1.SPI_FSM_TimerOvfl ;
(* src = "../../verilog/spifsm.v:44" *)
wire \SPIFSM_1.SPI_FSM_TimerPreset ;
(* src = "../../verilog/spifsm.v:47" *)
wire \SPIFSM_1.SPI_FSM_Wr0 ;
(* src = "../../verilog/spifsm.v:46" *)
wire \SPIFSM_1.SPI_FSM_Wr1 ;
(* src = "../../verilog/spifsm.v:18" *)
wire \SPIFSM_1.SPI_ReadNext_o ;
(* src = "../../verilog/spifsm.v:16" *)
wire \SPIFSM_1.SPI_Transmission_i ;
(* src = "../../verilog/spifsm.v:17" *)
wire \SPIFSM_1.SPI_Write_o ;
(* src = "../../verilog/spifsm.v:11" *)
wire \SPIFSM_1.Start_i ;
(* keep = 1, src = "../../verilog/adt7310.v:56" *)
wire [7:0] SPIFSM_Byte0_s;
(* keep = 1, src = "../../verilog/adt7310.v:58" *)
wire [7:0] SPIFSM_Byte1_s;
(* keep = 1, src = "../../verilog/adt7310.v:54" *)
wire SPIFSM_Done_s;
(* keep = 1, src = "../../verilog/adt7310.v:52" *)
wire SPIFSM_Start_s;
(* src = "../../verilog/sensorfsm.v:39" *)
wire [15:0] \SensorFSM_1.AbsDiffResult ;
(* src = "../../verilog/sensorfsm.v:7" *)
wire \SensorFSM_1.Clk_i ;
(* src = "../../verilog/sensorfsm.v:10" *)
wire \SensorFSM_1.CpuIntr_o ;
(* src = "../../verilog/sensorfsm.v:168" *)
wire [16:0] \SensorFSM_1.DiffAB ;
(* src = "../../verilog/sensorfsm.v:169" *)
wire [15:0] \SensorFSM_1.DiffBA ;
(* src = "../../verilog/sensorfsm.v:9" *)
wire \SensorFSM_1.Enable_i ;
(* src = "../../verilog/sensorfsm.v:15" *)
wire [7:0] \SensorFSM_1.MeasureFSM_Byte0_i ;
(* src = "../../verilog/sensorfsm.v:16" *)
wire [7:0] \SensorFSM_1.MeasureFSM_Byte1_i ;
(* src = "../../verilog/sensorfsm.v:14" *)
wire \SensorFSM_1.MeasureFSM_Done_i ;
(* src = "../../verilog/sensorfsm.v:13" *)
wire \SensorFSM_1.MeasureFSM_Start_o ;
(* src = "../../verilog/sensorfsm.v:19" *)
wire [15:0] \SensorFSM_1.ParamCounterPreset_i ;
(* src = "../../verilog/sensorfsm.v:18" *)
wire [15:0] \SensorFSM_1.ParamThreshold_i ;
(* src = "../../verilog/sensorfsm.v:6" *)
wire \SensorFSM_1.Reset_n_i ;
(* src = "../../verilog/sensorfsm.v:32" *)
wire \SensorFSM_1.SensorFSM_DiffTooLarge ;
(* src = "../../verilog/sensorfsm.v:33" *)
wire \SensorFSM_1.SensorFSM_StoreNewValue ;
(* src = "../../verilog/sensorfsm.v:128" *)
wire [15:0] \SensorFSM_1.SensorFSM_Timer ;
(* src = "../../verilog/sensorfsm.v:31" *)
wire \SensorFSM_1.SensorFSM_TimerEnable ;
(* src = "../../verilog/sensorfsm.v:29" *)
wire \SensorFSM_1.SensorFSM_TimerOvfl ;
(* src = "../../verilog/sensorfsm.v:30" *)
wire \SensorFSM_1.SensorFSM_TimerPreset ;
(* src = "../../verilog/sensorfsm.v:37" *)
wire [15:0] \SensorFSM_1.SensorValue ;
(* src = "../../verilog/sensorfsm.v:11" *)
wire [15:0] \SensorFSM_1.SensorValue_o ;
(* src = "../../verilog/sensorfsm.v:38" *)
wire [15:0] \SensorFSM_1.Word0 ;
wire SPIFSM_1_Out10_s;
wire SPIFSM_1_Out11_s;
wire SPIFSM_1_Out12_s;
wire SPIFSM_1_Out13_s;
wire SPIFSM_1_Out14_s;
wire SPIFSM_1_CfgMode_s;
wire SPIFSM_1_CfgClk_s;
wire SPIFSM_1_CfgShift_s;
wire SPIFSM_1_CfgDataIn_s;
wire SPIFSM_1_CfgDataOut_s;
wire SensorFSM_1_Out3_s;
wire SensorFSM_1_Out4_s;
wire SensorFSM_1_Out5_s;
wire SensorFSM_1_Out6_s;
wire SensorFSM_1_Out7_s;
wire SensorFSM_1_Out8_s;
wire SensorFSM_1_Out9_s;
wire SensorFSM_1_CfgMode_s;
wire SensorFSM_1_CfgClk_s;
wire SensorFSM_1_CfgShift_s;
wire SensorFSM_1_CfgDataIn_s;
wire SensorFSM_1_CfgDataOut_s;
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(3),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$auto$opt_reduce.cc:130:opt_mux$2454 (
.A({ \SPIFSM_1.SPI_FSM_Wr1 , \SPIFSM_1.SPI_FSM_Wr0 , \$techmap\SPIFSM_1.$procmux$298_CMP }),
.Y(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2453 )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(6),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$auto$opt_reduce.cc:130:opt_mux$2456 (
.A({ \$techmap\SPIFSM_1.$procmux$336_CMP , \$techmap\SPIFSM_1.$procmux$335_CMP , \$techmap\SPIFSM_1.$procmux$334_CMP , \$techmap\SPIFSM_1.$procmux$302_CMP , \$techmap\SPIFSM_1.$procmux$301_CMP , \$techmap\SPIFSM_1.$procmux$298_CMP }),
.Y(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2455 )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(9),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$auto$opt_reduce.cc:130:opt_mux$2458 (
.A({ \SPIFSM_1.SPI_FSM_Wr1 , \SPIFSM_1.SPI_FSM_Wr0 , \$techmap\SPIFSM_1.$procmux$336_CMP , \$techmap\SPIFSM_1.$procmux$335_CMP , \$techmap\SPIFSM_1.$procmux$334_CMP , \$techmap\SPIFSM_1.$procmux$302_CMP , \$techmap\SPIFSM_1.$procmux$301_CMP , \$techmap\SPIFSM_1.$procmux$298_CMP , \$techmap\SPIFSM_1.$procmux$297_CMP }),
.Y(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2457 )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(2),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$auto$opt_reduce.cc:130:opt_mux$2460 (
.A({ \$techmap\SPIFSM_1.$procmux$336_CMP , \$techmap\SPIFSM_1.$procmux$335_CMP }),
.Y(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2459 )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(3),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$auto$opt_reduce.cc:130:opt_mux$2462 (
.A({ \$techmap\SPIFSM_1.$procmux$336_CMP , \$techmap\SPIFSM_1.$procmux$335_CMP , \$techmap\SPIFSM_1.$procmux$302_CMP }),
.Y(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2461 )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(2),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$auto$opt_reduce.cc:130:opt_mux$2478 (
.A({ \$techmap\SPIFSM_1.$procmux$334_CMP , \$techmap\SPIFSM_1.$procmux$301_CMP }),
.Y(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2477 )
);
(* src = "../../verilog/spifsm.v:236" *)
\$eq #(
.A_SIGNED(0),
.A_WIDTH(32),
.B_SIGNED(0),
.B_WIDTH(32),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$eq$../../verilog/spifsm.v:236$47 (
.A(\SPIFSM_1.SPI_FSM_Timer ),
.B(0),
.Y(\SPIFSM_1.SPI_FSM_TimerOvfl )
);
SPIFSM SPIFSM_1 (
.Reset_n_i(\SPIFSM_1.Reset_n_i ),
.Clk_i(\SPIFSM_1.Clk_i ),
.In0_i(\SPIFSM_1.SPI_FSM_TimerOvfl ),
.In1_i(\SPIFSM_1.SPI_Transmission_i ),
.In2_i(\SPIFSM_1.Start_i ),
.In3_i(1'b0),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.Out0_o(\$techmap\SPIFSM_1.$procmux$297_CMP ),
.Out1_o(\$techmap\SPIFSM_1.$procmux$298_CMP ),
.Out2_o(\$techmap\SPIFSM_1.$procmux$301_CMP ),
.Out3_o(\$techmap\SPIFSM_1.$procmux$302_CMP ),
.Out4_o(\$techmap\SPIFSM_1.$procmux$305_CMP ),
.Out5_o(\$techmap\SPIFSM_1.$procmux$334_CMP ),
.Out6_o(\$techmap\SPIFSM_1.$procmux$335_CMP ),
.Out7_o(\$techmap\SPIFSM_1.$procmux$336_CMP ),
.Out8_o(\SPIFSM_1.SPI_FSM_Wr0 ),
.Out9_o(\SPIFSM_1.SPI_FSM_Wr1 ),
.Out10_o(SPIFSM_1_Out10_s),
.Out11_o(SPIFSM_1_Out11_s),
.Out12_o(SPIFSM_1_Out12_s),
.Out13_o(SPIFSM_1_Out13_s),
.Out14_o(SPIFSM_1_Out14_s),
.CfgMode_i(SPIFSM_1_CfgMode_s),
.CfgClk_i(SPIFSM_1_CfgClk_s),
.CfgShift_i(SPIFSM_1_CfgShift_s),
.CfgDataIn_i(SPIFSM_1_CfgDataIn_s),
.CfgDataOut_o(SPIFSM_1_CfgDataOut_s)
);
(* src = "../../verilog/spifsm.v:187" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(8)
) \$techmap\SPIFSM_1.$procdff$2439 (
.ARST(\SPIFSM_1.Reset_n_i ),
.CLK(\SPIFSM_1.Clk_i ),
.D(\$techmap\SPIFSM_1.$0\Byte0_o[7:0] ),
.Q(\SPIFSM_1.Byte0_o )
);
(* src = "../../verilog/spifsm.v:187" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(8)
) \$techmap\SPIFSM_1.$procdff$2440 (
.ARST(\SPIFSM_1.Reset_n_i ),
.CLK(\SPIFSM_1.Clk_i ),
.D(\$techmap\SPIFSM_1.$0\Byte1_o[7:0] ),
.Q(\SPIFSM_1.Byte1_o )
);
(* src = "../../verilog/spifsm.v:217" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(0),
.CLK_POLARITY(1'b1),
.WIDTH(32)
) \$techmap\SPIFSM_1.$procdff$2441 (
.ARST(\SPIFSM_1.Reset_n_i ),
.CLK(\SPIFSM_1.Clk_i ),
.D(\$techmap\SPIFSM_1.$0\SPI_FSM_Timer[31:0] ),
.Q(\SPIFSM_1.SPI_FSM_Timer )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$296 (
.A(1'b0),
.B({ 1'b1, \$techmap\SPIFSM_1.$2\SPI_FSM_TimerEnable[0:0] }),
.S({ \$techmap\SPIFSM_1.$procmux$298_CMP , \$techmap\SPIFSM_1.$procmux$297_CMP }),
.Y(\SPIFSM_1.SPI_FSM_TimerEnable )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$317 (
.A(1'b1),
.B({ 1'b0, \SPIFSM_1.SPI_FSM_TimerOvfl }),
.S({ \$techmap\SPIFSM_1.$procmux$298_CMP , \$techmap\SPIFSM_1.$procmux$297_CMP }),
.Y(\SPIFSM_1.SPI_FSM_TimerPreset )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$371 (
.A(1'b0),
.B({ \$techmap\SPIFSM_1.$2\SPI_ReadNext_o[0:0] , 1'b1 }),
.S({ \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2477 , \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2453 }),
.Y(\SPIFSM_1.SPI_ReadNext_o )
);
\$pmux #(
.S_WIDTH(3),
.WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$396 (
.A(1'b1),
.B({ \$techmap\SPIFSM_1.$2\ADT7310CS_n_o[0:0] , \$techmap\SPIFSM_1.$2\SPI_FSM_TimerEnable[0:0] , 1'b0 }),
.S({ \$techmap\SPIFSM_1.$procmux$305_CMP , \$techmap\SPIFSM_1.$procmux$297_CMP , \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2455 }),
.Y(\SPIFSM_1.ADT7310CS_n_o )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$413 (
.A(1'b1),
.B({ \$techmap\SPIFSM_1.$2\ADT7310CS_n_o[0:0] , 1'b0 }),
.S({ \$techmap\SPIFSM_1.$procmux$305_CMP , \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2457 }),
.Y(\SPIFSM_1.Done_o )
);
\$pmux #(
.S_WIDTH(3),
.WIDTH(8)
) \$techmap\SPIFSM_1.$procmux$439 (
.A(8'b00001000),
.B(24'b001000000101000011111111),
.S({ \$techmap\SPIFSM_1.$procmux$302_CMP , \$techmap\SPIFSM_1.$procmux$297_CMP , \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2459 }),
.Y(\SPIFSM_1.SPI_Data_o )
);
\$pmux #(
.S_WIDTH(3),
.WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$481 (
.A(1'b0),
.B({ \SPIFSM_1.Start_i , \SPIFSM_1.SPI_FSM_TimerOvfl , 1'b1 }),
.S({ \$techmap\SPIFSM_1.$procmux$305_CMP , \$techmap\SPIFSM_1.$procmux$297_CMP , \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2461 }),
.Y(\SPIFSM_1.SPI_Write_o )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$535 (
.A(\SPIFSM_1.Start_i ),
.Y(\$techmap\SPIFSM_1.$2\ADT7310CS_n_o[0:0] )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$641 (
.A(\SPIFSM_1.SPI_Transmission_i ),
.Y(\$techmap\SPIFSM_1.$2\SPI_ReadNext_o[0:0] )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SPIFSM_1.$procmux$659 (
.A(\SPIFSM_1.SPI_FSM_TimerOvfl ),
.Y(\$techmap\SPIFSM_1.$2\SPI_FSM_TimerEnable[0:0] )
);
\$mux #(
.WIDTH(8)
) \$techmap\SPIFSM_1.$procmux$70 (
.A(\SPIFSM_1.Byte0_o ),
.B(\SPIFSM_1.SPI_Data_i ),
.S(\SPIFSM_1.SPI_FSM_Wr0 ),
.Y(\$techmap\SPIFSM_1.$0\Byte0_o[7:0] )
);
\$mux #(
.WIDTH(8)
) \$techmap\SPIFSM_1.$procmux$77 (
.A(\SPIFSM_1.Byte1_o ),
.B(\SPIFSM_1.SPI_Data_i ),
.S(\SPIFSM_1.SPI_FSM_Wr1 ),
.Y(\$techmap\SPIFSM_1.$0\Byte1_o[7:0] )
);
\$mux #(
.WIDTH(32)
) \$techmap\SPIFSM_1.$procmux$80 (
.A(\SPIFSM_1.SPI_FSM_Timer ),
.B(\$techmap\SPIFSM_1.$sub$../../verilog/spifsm.v:231$46_Y ),
.S(\SPIFSM_1.SPI_FSM_TimerEnable ),
.Y(\$techmap\SPIFSM_1.$procmux$80_Y )
);
\$mux #(
.WIDTH(32)
) \$techmap\SPIFSM_1.$procmux$83 (
.A(\$techmap\SPIFSM_1.$procmux$80_Y ),
.B(\SPIFSM_1.ParamCounterPreset_i ),
.S(\SPIFSM_1.SPI_FSM_TimerPreset ),
.Y(\$techmap\SPIFSM_1.$0\SPI_FSM_Timer[31:0] )
);
(* src = "../../verilog/spifsm.v:231" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(32),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(32)
) \$techmap\SPIFSM_1.$sub$../../verilog/spifsm.v:231$46 (
.A(\SPIFSM_1.SPI_FSM_Timer ),
.B(1'b1),
.Y(\$techmap\SPIFSM_1.$sub$../../verilog/spifsm.v:231$46_Y )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(3),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$auto$opt_reduce.cc:130:opt_mux$2464 (
.A({ \$techmap\SensorFSM_1.$procmux$1129_CMP , \$techmap\SensorFSM_1.$procmux$1007_CMP , \$techmap\SensorFSM_1.$procmux$1004_CMP }),
.Y(\$techmap\SensorFSM_1.$auto$opt_reduce.cc:126:opt_mux$2463 )
);
(* src = "../../verilog/sensorfsm.v:149" *)
\$eq #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$eq$../../verilog/sensorfsm.v:149$60 (
.A(\SensorFSM_1.SensorFSM_Timer ),
.B(16'b0000000000000000),
.Y(\SensorFSM_1.SensorFSM_TimerOvfl )
);
SensorFSM SensorFSM_1 (
.Reset_n_i(\SensorFSM_1.Reset_n_i ),
.Clk_i(\SensorFSM_1.Clk_i ),
.In0_i(\SensorFSM_1.Enable_i ),
.In1_i(\SensorFSM_1.MeasureFSM_Done_i ),
.In2_i(\SensorFSM_1.SensorFSM_DiffTooLarge ),
.In3_i(\SensorFSM_1.SensorFSM_TimerOvfl ),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.In8_i(1'b0),
.In9_i(1'b0),
.Out0_o(\$techmap\SensorFSM_1.$procmux$1004_CMP ),
.Out1_o(\$techmap\SensorFSM_1.$procmux$1007_CMP ),
.Out2_o(\$techmap\SensorFSM_1.$procmux$1129_CMP ),
.Out3_o(SensorFSM_1_Out3_s),
.Out4_o(SensorFSM_1_Out4_s),
.Out5_o(SensorFSM_1_Out5_s),
.Out6_o(SensorFSM_1_Out6_s),
.Out7_o(SensorFSM_1_Out7_s),
.Out8_o(SensorFSM_1_Out8_s),
.Out9_o(SensorFSM_1_Out9_s),
.CfgMode_i(SensorFSM_1_CfgMode_s),
.CfgClk_i(SensorFSM_1_CfgClk_s),
.CfgShift_i(SensorFSM_1_CfgShift_s),
.CfgDataIn_i(SensorFSM_1_CfgDataIn_s),
.CfgDataOut_o(SensorFSM_1_CfgDataOut_s)
);
(* src = "../../verilog/sensorfsm.v:174" *)
\$gt #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$gt$../../verilog/sensorfsm.v:174$67 (
.A(\SensorFSM_1.AbsDiffResult ),
.B(\SensorFSM_1.ParamThreshold_i ),
.Y(\SensorFSM_1.SensorFSM_DiffTooLarge )
);
(* src = "../../verilog/sensorfsm.v:130" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(16)
) \$techmap\SensorFSM_1.$procdff$2443 (
.ARST(\SensorFSM_1.Reset_n_i ),
.CLK(\SensorFSM_1.Clk_i ),
.D(\$techmap\SensorFSM_1.$0\SensorFSM_Timer[15:0] ),
.Q(\SensorFSM_1.SensorFSM_Timer )
);
(* src = "../../verilog/sensorfsm.v:153" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(16)
) \$techmap\SensorFSM_1.$procdff$2444 (
.ARST(\SensorFSM_1.Reset_n_i ),
.CLK(\SensorFSM_1.Clk_i ),
.D(\$techmap\SensorFSM_1.$0\Word0[15:0] ),
.Q(\SensorFSM_1.Word0 )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$1036 (
.A(\SensorFSM_1.Enable_i ),
.Y(\$techmap\SensorFSM_1.$2\SensorFSM_TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$1065 (
.A(\SensorFSM_1.Enable_i ),
.B(\SensorFSM_1.SensorFSM_TimerOvfl ),
.Y(\$techmap\SensorFSM_1.$2\MeasureFSM_Start_o[0:0] )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$1142 (
.A(\SensorFSM_1.MeasureFSM_Done_i ),
.B(\SensorFSM_1.SensorFSM_DiffTooLarge ),
.Y(\$techmap\SensorFSM_1.$2\SensorFSM_StoreNewValue[0:0] )
);
\$mux #(
.WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$1174 (
.A(1'b1),
.B(\$techmap\SensorFSM_1.$4\SensorFSM_TimerPreset[0:0] ),
.S(\SensorFSM_1.MeasureFSM_Done_i ),
.Y(\$techmap\SensorFSM_1.$3\SensorFSM_TimerPreset[0:0] )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$1206 (
.A(\SensorFSM_1.SensorFSM_DiffTooLarge ),
.Y(\$techmap\SensorFSM_1.$4\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(16)
) \$techmap\SensorFSM_1.$procmux$826 (
.A(\SensorFSM_1.SensorFSM_Timer ),
.B(\$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:144$59_Y ),
.S(\SensorFSM_1.SensorFSM_TimerEnable ),
.Y(\$techmap\SensorFSM_1.$procmux$826_Y )
);
\$mux #(
.WIDTH(16)
) \$techmap\SensorFSM_1.$procmux$829 (
.A(\$techmap\SensorFSM_1.$procmux$826_Y ),
.B(\SensorFSM_1.ParamCounterPreset_i ),
.S(\SensorFSM_1.SensorFSM_TimerPreset ),
.Y(\$techmap\SensorFSM_1.$0\SensorFSM_Timer[15:0] )
);
\$mux #(
.WIDTH(16)
) \$techmap\SensorFSM_1.$procmux$832 (
.A(\SensorFSM_1.Word0 ),
.B({ \SensorFSM_1.MeasureFSM_Byte1_i , \SensorFSM_1.MeasureFSM_Byte0_i }),
.S(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Y(\$techmap\SensorFSM_1.$0\Word0[15:0] )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$923 (
.A(\$techmap\SensorFSM_1.$auto$opt_reduce.cc:126:opt_mux$2463 ),
.Y(\SensorFSM_1.CpuIntr_o )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$943 (
.A(\$techmap\SensorFSM_1.$procmux$1004_CMP ),
.B(\$techmap\SensorFSM_1.$2\MeasureFSM_Start_o[0:0] ),
.Y(\SensorFSM_1.MeasureFSM_Start_o )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$953 (
.A(\$techmap\SensorFSM_1.$procmux$1129_CMP ),
.B(\$techmap\SensorFSM_1.$2\SensorFSM_StoreNewValue[0:0] ),
.Y(\SensorFSM_1.SensorFSM_StoreNewValue )
);
\$pmux #(
.S_WIDTH(3),
.WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$983 (
.A(1'b0),
.B({ \SensorFSM_1.Enable_i , 1'b1, \$techmap\SensorFSM_1.$2\SensorFSM_StoreNewValue[0:0] }),
.S({ \$techmap\SensorFSM_1.$procmux$1007_CMP , \$techmap\SensorFSM_1.$procmux$1004_CMP , \$techmap\SensorFSM_1.$procmux$1129_CMP }),
.Y(\SensorFSM_1.SensorFSM_TimerEnable )
);
\$pmux #(
.S_WIDTH(3),
.WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$998 (
.A(1'b1),
.B({ \$techmap\SensorFSM_1.$2\SensorFSM_TimerPreset[0:0] , 1'b0, \$techmap\SensorFSM_1.$3\SensorFSM_TimerPreset[0:0] }),
.S({ \$techmap\SensorFSM_1.$procmux$1007_CMP , \$techmap\SensorFSM_1.$procmux$1004_CMP , \$techmap\SensorFSM_1.$procmux$1129_CMP }),
.Y(\SensorFSM_1.SensorFSM_TimerPreset )
);
(* src = "../../verilog/sensorfsm.v:144" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(16)
) \$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:144$59 (
.A(\SensorFSM_1.SensorFSM_Timer ),
.B(1'b1),
.Y(\$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:144$59_Y )
);
(* src = "../../verilog/sensorfsm.v:170" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(17),
.B_SIGNED(0),
.B_WIDTH(17),
.Y_WIDTH(17)
) \$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:170$64 (
.A({ 1'b0, \SensorFSM_1.MeasureFSM_Byte1_i , \SensorFSM_1.MeasureFSM_Byte0_i }),
.B({ 1'b0, \SensorFSM_1.Word0 }),
.Y(\SensorFSM_1.DiffAB )
);
(* src = "../../verilog/sensorfsm.v:171" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(16)
) \$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:171$65 (
.A(\SensorFSM_1.Word0 ),
.B({ \SensorFSM_1.MeasureFSM_Byte1_i , \SensorFSM_1.MeasureFSM_Byte0_i }),
.Y(\SensorFSM_1.DiffBA )
);
(* src = "../../verilog/sensorfsm.v:172" *)
\$mux #(
.WIDTH(16)
) \$techmap\SensorFSM_1.$ternary$../../verilog/sensorfsm.v:172$66 (
.A(\SensorFSM_1.DiffAB [15:0]),
.B(\SensorFSM_1.DiffBA ),
.S(\SensorFSM_1.DiffAB [16]),
.Y(\SensorFSM_1.AbsDiffResult )
);
assign SPI_CPHA_o = 1'b1;
assign SPI_CPOL_o = 1'b1;
assign SPI_LSBFE_o = 1'b0;
assign ADT7310CS_n_o = \SPIFSM_1.ADT7310CS_n_o ;
assign SPIFSM_Byte0_s = \SPIFSM_1.Byte0_o ;
assign SPIFSM_Byte1_s = \SPIFSM_1.Byte1_o ;
assign \SPIFSM_1.Clk_i = Clk_i;
assign SPIFSM_Done_s = \SPIFSM_1.Done_o ;
assign \SPIFSM_1.ParamCounterPreset_i = { SPICounterPresetH_i, SPICounterPresetL_i };
assign \SPIFSM_1.Reset_n_i = Reset_n_i;
assign \SPIFSM_1.SPI_Data_i = SPI_Data_i;
assign SPI_Data_o = \SPIFSM_1.SPI_Data_o ;
assign \SPIFSM_1.SPI_FIFOEmpty_i = SPI_FIFOEmpty_i;
assign \SPIFSM_1.SPI_FIFOFull_i = SPI_FIFOFull_i;
assign SPI_ReadNext_o = \SPIFSM_1.SPI_ReadNext_o ;
assign \SPIFSM_1.SPI_Transmission_i = SPI_Transmission_i;
assign SPI_Write_o = \SPIFSM_1.SPI_Write_o ;
assign \SPIFSM_1.Start_i = SPIFSM_Start_s;
assign \SensorFSM_1.Clk_i = Clk_i;
assign CpuIntr_o = \SensorFSM_1.CpuIntr_o ;
assign \SensorFSM_1.Enable_i = Enable_i;
assign \SensorFSM_1.MeasureFSM_Byte0_i = SPIFSM_Byte0_s;
assign \SensorFSM_1.MeasureFSM_Byte1_i = SPIFSM_Byte1_s;
assign \SensorFSM_1.MeasureFSM_Done_i = SPIFSM_Done_s;
assign SPIFSM_Start_s = \SensorFSM_1.MeasureFSM_Start_o ;
assign \SensorFSM_1.ParamCounterPreset_i = PeriodCounterPreset_i;
assign \SensorFSM_1.ParamThreshold_i = Threshold_i;
assign \SensorFSM_1.Reset_n_i = Reset_n_i;
assign SensorValue_o = \SensorFSM_1.SensorValue_o ;
assign \SensorFSM_1.SensorValue = { \SensorFSM_1.MeasureFSM_Byte1_i , \SensorFSM_1.MeasureFSM_Byte0_i };
assign \SensorFSM_1.SensorValue_o = \SensorFSM_1.Word0 ;
assign SPIFSM_1_CfgMode_s = 1'b0;
assign SPIFSM_1_CfgClk_s = 1'b0;
assign SPIFSM_1_CfgShift_s = 1'b0;
assign SPIFSM_1_CfgDataIn_s = 1'b0;
assign SensorFSM_1_CfgMode_s = 1'b0;
assign SensorFSM_1_CfgClk_s = 1'b0;
assign SensorFSM_1_CfgShift_s = 1'b0;
assign SensorFSM_1_CfgDataIn_s = 1'b0;
endmodule
|
//****************************************************//
//Author: |Wei.Shen
//Edit: |edit the CORDIC arithmetic
//Edit Date:|2005.04.26
//Update: |
//Edit Date:|
//Descript: |this module used to caculate the amplitude and
// |angle of a signal. the angle have divide with PI
//****************************************************//
module coordinate_cordic
(
realIn,
imagIn,
clk,
amplitude,
angle,
test1,
test2
);
//==================================================
// Input/Output Ports
//==================================================
input signed [INWIDTH-1:0]realIn,imagIn;
input clk;
output signed [OUTWIDTH-1:0]amplitude;
output signed [ANGLEWIDTH-1:0]angle;
input [9:0] test1;
output [9:0] test2;
assign test2 = {11{test1}};
//==================================================
// Parameter Declaration
//==================================================
parameter INWIDTH = 18, //input data width
OUTWIDTH = 20, //output data width
MIDWIDTH = 21, //the temporary data width
ANGLEWIDTH =15;//the angle width,use degree unit and four bits precision
//in fraction part,highest is sign bit
///180degree respect to 10000 for angle
// amplititude with a factor of 1.647 for iteration >10 times
parameter ARCTANG_0 = 12'b10_01110_00100,//0.7854 expand with 10000*/PI times is +7854 = +2500
ARCTANG_1 = 11'b1_01110_00100,//0.4636 expand with 10000*/PI times is +4636 = +1476
ARCTANG_2 = 10'b11000_01100,//0.2450 expand with 10000*/PI times is +2450 = +780
ARCTANG_3 = 9'b1100_01100,//0.1244 expand with 10000*/PI times is +1244 = +396
ARCTANG_4 = 8'b110_00111,//0.0624 expand with 10000*/PI times is +624 = +199
ARCTANG_5 = 7'b11_00011,//0.0312 expand with 10000*/PI times is +312 = +99
ARCTANG_6 = 6'b1_10010,//0.0156 expand with 10000*/PI times is +156 = +50
ARCTANG_7 = 5'b11001,//0.0078 expand with 10000*/PI times is +78 = +25
ARCTANG_8 = 4'b1100,//0.0039 expand with 10000*/PI times is +39 = +12
ARCTANG_9 = 3'b110,//0.0020 expand with 10000*/PI times is +20 = +6
ARCTANG_10 = 2'b11,//0.0010 expand with 10000*/PI times is +10 = +3
ARCTANG_11 = 2'b10;//0.0005 expand with 10000*/PI times is +5 = +2
parameter HALFPI = 13'b100_11100_01000;//+15708/PI = +5000
//==================================================
// Register Declaration
//==================================================
reg signed [MIDWIDTH-1:0]xData1,xData2,xData3,xData4,xData5,xData6,
xData7,xData8,xData9,xData10,xData11,xData12,
xData13,xData14,xData15,xData16,
yData1,yData2,yData3,yData4,yData5,yData6,
yData7,yData8,yData9,yData10,yData11,yData12,
yData13,yData14,yData15,yData16;
reg signed [ANGLEWIDTH-1:0]angle1,angle2,angle3,angle4,angle5,angle6,
angle7,angle8,angle9,angle10,angle11,angle12,
angle13,angle14,angle15,angle16;
//==================================================
// Wire Declaration
//==================================================
wire signed [MIDWIDTH-1:0]reIn,imIn;
wire signed [ANGLEWIDTH-1:0]ang;
//==================================================
// Integer Declaration
//==================================================
//==================================================
// Concurrent Assignment
//==================================================
assign reIn = realIn[INWIDTH-1]?(imagIn[INWIDTH-1]?-imagIn:imagIn):realIn;
assign imIn = realIn[INWIDTH-1]?(imagIn[INWIDTH-1]?realIn:-realIn):imagIn;
assign ang = realIn[INWIDTH-1]?(imagIn[INWIDTH-1]?-HALFPI:HALFPI):1'b0;
/*
//change 23 bits to 22 bits
assign amplitude = {xData13[MIDWIDTH-1],xData13[MIDWIDTH-3:0]};
//angle have expand with 10000 times
assign angle = angle13;
*/
assign amplitude = {xData12[MIDWIDTH-1],xData12[MIDWIDTH-3:0]};
assign angle = angle12;
//==================================================
// Always Construct
//==================================================
always@(posedge clk)
begin
// if y < 0 then d = 1;
// x = x - y.d.2^-i;
// y = y + x.d.2^-i;
// z = z - d.arctan(2^-i);
// i = 0
xData1 <= imIn[MIDWIDTH-1]?(reIn - imIn):(reIn + imIn);
yData1 <= imIn[MIDWIDTH-1]?(imIn + reIn):(imIn - reIn);
angle1 <= imIn[MIDWIDTH-1]?(ang - ARCTANG_0):(ang + ARCTANG_0);
// i = 1
xData2 <= yData1[MIDWIDTH-1]?(xData1 - {{2{yData1[MIDWIDTH-1]}},yData1[MIDWIDTH-2:1]}):(xData1 + {{2{yData1[MIDWIDTH-1]}},yData1[MIDWIDTH-2:1]});
yData2 <= yData1[MIDWIDTH-1]?(yData1 + {{2{xData1[MIDWIDTH-1]}},xData1[MIDWIDTH-2:1]}):(yData1 - {{2{xData1[MIDWIDTH-1]}},xData1[MIDWIDTH-2:1]});
angle2 <= yData1[MIDWIDTH-1]?(angle1 - ARCTANG_1):(angle1 + ARCTANG_1);
// i = 2
xData3 <= yData2[MIDWIDTH-1]?(xData2 - {{3{yData2[MIDWIDTH-1]}},yData2[MIDWIDTH-2:2]}):(xData2 + {{3{yData2[MIDWIDTH-1]}},yData2[MIDWIDTH-2:2]});
yData3 <= yData2[MIDWIDTH-1]?(yData2 + {{3{xData2[MIDWIDTH-1]}},xData2[MIDWIDTH-2:2]}):(yData2 - {{3{xData2[MIDWIDTH-1]}},xData2[MIDWIDTH-2:2]});
angle3 <= yData2[MIDWIDTH-1]?(angle2 - ARCTANG_2):(angle2 + ARCTANG_2);
// i = 3
xData4 <= yData3[MIDWIDTH-1]?(xData3 - {{4{yData3[MIDWIDTH-1]}},yData3[MIDWIDTH-2:3]}):(xData3 + {{4{yData3[MIDWIDTH-1]}},yData3[MIDWIDTH-2:3]});
yData4 <= yData3[MIDWIDTH-1]?(yData3 + {{4{xData3[MIDWIDTH-1]}},xData3[MIDWIDTH-2:3]}):(yData3 - {{4{xData3[MIDWIDTH-1]}},xData3[MIDWIDTH-2:3]});
angle4 <= yData3[MIDWIDTH-1]?(angle3 - ARCTANG_3):(angle3 + ARCTANG_3);
// i = 4
xData5 <= yData4[MIDWIDTH-1]?(xData4 - {{5{yData4[MIDWIDTH-1]}},yData4[MIDWIDTH-2:4]}):(xData4 + {{5{yData4[MIDWIDTH-1]}},yData4[MIDWIDTH-2:4]});
yData5 <= yData4[MIDWIDTH-1]?(yData4 + {{5{xData4[MIDWIDTH-1]}},xData4[MIDWIDTH-2:4]}):(yData4 - {{5{xData4[MIDWIDTH-1]}},xData4[MIDWIDTH-2:4]});
angle5 <= yData4[MIDWIDTH-1]?(angle4 - ARCTANG_4):(angle4 + ARCTANG_4);
// i = 5
xData6 <= yData5[MIDWIDTH-1]?(xData5 - {{6{yData5[MIDWIDTH-1]}},yData5[MIDWIDTH-2:5]}):(xData5 + {{6{yData5[MIDWIDTH-1]}},yData5[MIDWIDTH-2:5]});
yData6 <= yData5[MIDWIDTH-1]?(yData5 + {{6{xData5[MIDWIDTH-1]}},xData5[MIDWIDTH-2:5]}):(yData5 - {{6{xData5[MIDWIDTH-1]}},xData5[MIDWIDTH-2:5]});
angle6 <= yData5[MIDWIDTH-1]?(angle5 - ARCTANG_5):(angle5 + ARCTANG_5);
// i = 6
xData7 <= yData6[MIDWIDTH-1]?(xData6 - {{7{yData6[MIDWIDTH-1]}},yData6[MIDWIDTH-2:6]}):(xData6 + {{7{yData6[MIDWIDTH-1]}},yData6[MIDWIDTH-2:6]});
yData7 <= yData6[MIDWIDTH-1]?(yData6 + {{7{xData6[MIDWIDTH-1]}},xData6[MIDWIDTH-2:6]}):(yData6 - {{7{xData6[MIDWIDTH-1]}},xData6[MIDWIDTH-2:6]});
angle7 <= yData6[MIDWIDTH-1]?(angle6 - ARCTANG_6):(angle6 + ARCTANG_6);
// i = 7
xData8 <= yData7[MIDWIDTH-1]?(xData7 - {{8{yData7[MIDWIDTH-1]}},yData7[MIDWIDTH-2:7]}):(xData7 + {{8{yData7[MIDWIDTH-1]}},yData7[MIDWIDTH-2:7]});
yData8 <= yData7[MIDWIDTH-1]?(yData7 + {{8{xData7[MIDWIDTH-1]}},xData7[MIDWIDTH-2:7]}):(yData7 - {{8{xData7[MIDWIDTH-1]}},xData7[MIDWIDTH-2:7]});
angle8 <= yData7[MIDWIDTH-1]?(angle7 - ARCTANG_7):(angle7 + ARCTANG_7);
// i = 8
xData9 <= yData8[MIDWIDTH-1]?(xData8 - {{9{yData8[MIDWIDTH-1]}},yData8[MIDWIDTH-2:8]}):(xData8 + {{9{yData8[MIDWIDTH-1]}},yData8[MIDWIDTH-2:8]});
yData9 <= yData8[MIDWIDTH-1]?(yData8 + {{9{xData8[MIDWIDTH-1]}},xData8[MIDWIDTH-2:8]}):(yData8 - {{9{xData8[MIDWIDTH-1]}},xData8[MIDWIDTH-2:8]});
angle9 <= yData8[MIDWIDTH-1]?(angle8 - ARCTANG_8):(angle8 + ARCTANG_8);
// i = 9
xData10 <= yData9[MIDWIDTH-1]?(xData9 - {{10{yData9[MIDWIDTH-1]}},yData9[MIDWIDTH-2:9]}):(xData9 + {{10{yData9[MIDWIDTH-1]}},yData9[MIDWIDTH-2:9]});
yData10 <= yData9[MIDWIDTH-1]?(yData9 + {{10{xData9[MIDWIDTH-1]}},xData9[MIDWIDTH-2:9]}):(yData9 - {{10{xData9[MIDWIDTH-1]}},xData9[MIDWIDTH-2:9]});
angle10 <= yData9[MIDWIDTH-1]?(angle9 - ARCTANG_9):(angle9 + ARCTANG_9);
// i = 10
xData11 <= yData10[MIDWIDTH-1]?(xData10 - {{11{yData10[MIDWIDTH-1]}},yData10[MIDWIDTH-2:10]}):(xData10 + {{11{yData10[MIDWIDTH-1]}},yData10[MIDWIDTH-2:10]});
yData11 <= yData10[MIDWIDTH-1]?(yData10 + {{11{xData10[MIDWIDTH-1]}},xData10[MIDWIDTH-2:10]}):(yData10 - {{11{xData10[MIDWIDTH-1]}},xData10[MIDWIDTH-2:10]});
angle11 <= yData10[MIDWIDTH-1]?(angle10 - ARCTANG_10):(angle10 + ARCTANG_10);
// i = 11
xData12 <= yData11[MIDWIDTH-1]?(xData11 - {{12{yData11[MIDWIDTH-1]}},yData11[MIDWIDTH-2:11]}):(xData11 + {{12{yData11[MIDWIDTH-1]}},yData11[MIDWIDTH-2:11]});
yData12 <= yData11[MIDWIDTH-1]?(yData11 + {{12{xData11[MIDWIDTH-1]}},xData11[MIDWIDTH-2:11]}):(yData11 - {{12{xData11[MIDWIDTH-1]}},xData11[MIDWIDTH-2:11]});
angle12 <= yData11[MIDWIDTH-1]?(angle11 - ARCTANG_11):(angle11 + ARCTANG_11);
end
//==================================================
// Module Instantiation
//==================================================
//==================================================
// Task Declaration
//==================================================
//==================================================
// Function Declaration
//==================================================
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__AND3_PP_BLACKBOX_V
/**
* and3: 3-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_PP_BLACKBOX_V
|
/*
length first last
Visible porch 480 0 479 low
front porch 10 480 489 low
sync pulse 2 490 491 HI
back porch 33 492 524 low
length first last
visible porch 640 0 639 low
front porch 16 640 655 low
sync pulse 96 656 751 HI
back porch 48 752 799 low
*/
module vga_timing(
clk25mhz,
hindex,
vindex,
hsync,
vsync
);
// Input
input wire clk25mhz;
// Output
output reg[9:0] hindex = 0;
output reg[9:0] vindex = 0;
output reg hsync;
output reg vsync;
// Process
always @ (posedge clk25mhz) begin: indexes
if(hindex == 799) begin
hindex <= 0;
if(vindex == 524) begin
vindex <= 0;
end else begin
vindex <= vindex + 1;
end
end else begin
hindex <= hindex + 1;
end
end
always @ (posedge clk25mhz) begin: vsync_output
if(vindex >= 490 && vindex <= 491) begin
vsync <= 0;
end else begin
vsync <= 1;
end
end
always @ (posedge clk25mhz) begin: hsync_output
// Both hsync and color output are delayed by one pixel
if(hindex >= 657 && hindex <= 752) begin
hsync <= 0;
end else begin
hsync <= 1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221O_TB_V
`define SKY130_FD_SC_LS__A221O_TB_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a221o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__a221o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221O_TB_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / _no_description_
// /___/ /\ Filename : GTYE3_COMMON.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTYE3_COMMON #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000,
parameter [8:0] A_SDM1DATA1_1 = 9'b000000000,
parameter [15:0] BIAS_CFG0 = 16'h0000,
parameter [15:0] BIAS_CFG1 = 16'h0000,
parameter [15:0] BIAS_CFG2 = 16'h0000,
parameter [15:0] BIAS_CFG3 = 16'h0000,
parameter [15:0] BIAS_CFG4 = 16'h0000,
parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000,
parameter [15:0] COMMON_CFG0 = 16'h0000,
parameter [15:0] COMMON_CFG1 = 16'h0000,
parameter [15:0] POR_CFG = 16'h0004,
parameter [15:0] PPF0_CFG = 16'h0FFF,
parameter [15:0] PPF1_CFG = 16'h0FFF,
parameter QPLL0CLKOUT_RATE = "FULL",
parameter [15:0] QPLL0_CFG0 = 16'h301C,
parameter [15:0] QPLL0_CFG1 = 16'h0000,
parameter [15:0] QPLL0_CFG1_G3 = 16'h0020,
parameter [15:0] QPLL0_CFG2 = 16'h0780,
parameter [15:0] QPLL0_CFG2_G3 = 16'h0780,
parameter [15:0] QPLL0_CFG3 = 16'h0120,
parameter [15:0] QPLL0_CFG4 = 16'h0021,
parameter [9:0] QPLL0_CP = 10'b0000011111,
parameter [9:0] QPLL0_CP_G3 = 10'b0000011111,
parameter integer QPLL0_FBDIV = 66,
parameter integer QPLL0_FBDIV_G3 = 80,
parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000,
parameter [7:0] QPLL0_INIT_CFG1 = 8'h00,
parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8,
parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8,
parameter [9:0] QPLL0_LPF = 10'b1011111111,
parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111,
parameter integer QPLL0_REFCLK_DIV = 2,
parameter [15:0] QPLL0_SDM_CFG0 = 16'h0000,
parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000,
parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000,
parameter QPLL1CLKOUT_RATE = "FULL",
parameter [15:0] QPLL1_CFG0 = 16'h301C,
parameter [15:0] QPLL1_CFG1 = 16'h0000,
parameter [15:0] QPLL1_CFG1_G3 = 16'h0020,
parameter [15:0] QPLL1_CFG2 = 16'h0780,
parameter [15:0] QPLL1_CFG2_G3 = 16'h0780,
parameter [15:0] QPLL1_CFG3 = 16'h0120,
parameter [15:0] QPLL1_CFG4 = 16'h0021,
parameter [9:0] QPLL1_CP = 10'b0000011111,
parameter [9:0] QPLL1_CP_G3 = 10'b0000011111,
parameter integer QPLL1_FBDIV = 66,
parameter integer QPLL1_FBDIV_G3 = 80,
parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000,
parameter [7:0] QPLL1_INIT_CFG1 = 8'h00,
parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8,
parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8,
parameter [9:0] QPLL1_LPF = 10'b1011111111,
parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111,
parameter integer QPLL1_REFCLK_DIV = 2,
parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000,
parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000,
parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000,
parameter [15:0] RSVD_ATTR0 = 16'h0000,
parameter [15:0] RSVD_ATTR1 = 16'h0000,
parameter [15:0] RSVD_ATTR2 = 16'h0000,
parameter [15:0] RSVD_ATTR3 = 16'h0000,
parameter [1:0] RXRECCLKOUT0_SEL = 2'b00,
parameter [1:0] RXRECCLKOUT1_SEL = 2'b00,
parameter [0:0] SARC_EN = 1'b1,
parameter [0:0] SARC_SEL = 1'b0,
parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000,
parameter [8:0] SDM0INITSEED0_1 = 9'b000000000,
parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000,
parameter [8:0] SDM1INITSEED0_1 = 9'b000000000,
parameter SIM_MODE = "FAST",
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter integer SIM_VERSION = 2
)(
output [15:0] DRPDO,
output DRPRDY,
output [7:0] PMARSVDOUT0,
output [7:0] PMARSVDOUT1,
output QPLL0FBCLKLOST,
output QPLL0LOCK,
output QPLL0OUTCLK,
output QPLL0OUTREFCLK,
output QPLL0REFCLKLOST,
output QPLL1FBCLKLOST,
output QPLL1LOCK,
output QPLL1OUTCLK,
output QPLL1OUTREFCLK,
output QPLL1REFCLKLOST,
output [7:0] QPLLDMONITOR0,
output [7:0] QPLLDMONITOR1,
output REFCLKOUTMONITOR0,
output REFCLKOUTMONITOR1,
output [1:0] RXRECCLK0_SEL,
output [1:0] RXRECCLK1_SEL,
output [3:0] SDM0FINALOUT,
output [14:0] SDM0TESTDATA,
output [3:0] SDM1FINALOUT,
output [14:0] SDM1TESTDATA,
input BGBYPASSB,
input BGMONITORENB,
input BGPDB,
input [4:0] BGRCALOVRD,
input BGRCALOVRDENB,
input [9:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
input DRPEN,
input DRPWE,
input GTGREFCLK0,
input GTGREFCLK1,
input GTNORTHREFCLK00,
input GTNORTHREFCLK01,
input GTNORTHREFCLK10,
input GTNORTHREFCLK11,
input GTREFCLK00,
input GTREFCLK01,
input GTREFCLK10,
input GTREFCLK11,
input GTSOUTHREFCLK00,
input GTSOUTHREFCLK01,
input GTSOUTHREFCLK10,
input GTSOUTHREFCLK11,
input [7:0] PMARSVD0,
input [7:0] PMARSVD1,
input QPLL0CLKRSVD0,
input QPLL0LOCKDETCLK,
input QPLL0LOCKEN,
input QPLL0PD,
input [2:0] QPLL0REFCLKSEL,
input QPLL0RESET,
input QPLL1CLKRSVD0,
input QPLL1LOCKDETCLK,
input QPLL1LOCKEN,
input QPLL1PD,
input [2:0] QPLL1REFCLKSEL,
input QPLL1RESET,
input [7:0] QPLLRSVD1,
input [4:0] QPLLRSVD2,
input [4:0] QPLLRSVD3,
input [7:0] QPLLRSVD4,
input RCALENB,
input [24:0] SDM0DATA,
input SDM0RESET,
input [1:0] SDM0WIDTH,
input [24:0] SDM1DATA,
input SDM1RESET,
input [1:0] SDM1WIDTH
);
// define constants
localparam MODULE_NAME = "GTYE3_COMMON";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
`ifdef XIL_DR
`include "GTYE3_COMMON_dr.v"
`else
localparam [15:0] A_SDM1DATA1_0_REG = A_SDM1DATA1_0;
localparam [8:0] A_SDM1DATA1_1_REG = A_SDM1DATA1_1;
localparam [15:0] BIAS_CFG0_REG = BIAS_CFG0;
localparam [15:0] BIAS_CFG1_REG = BIAS_CFG1;
localparam [15:0] BIAS_CFG2_REG = BIAS_CFG2;
localparam [15:0] BIAS_CFG3_REG = BIAS_CFG3;
localparam [15:0] BIAS_CFG4_REG = BIAS_CFG4;
localparam [9:0] BIAS_CFG_RSVD_REG = BIAS_CFG_RSVD;
localparam [15:0] COMMON_CFG0_REG = COMMON_CFG0;
localparam [15:0] COMMON_CFG1_REG = COMMON_CFG1;
localparam [15:0] POR_CFG_REG = POR_CFG;
localparam [15:0] PPF0_CFG_REG = PPF0_CFG;
localparam [15:0] PPF1_CFG_REG = PPF1_CFG;
localparam [32:1] QPLL0CLKOUT_RATE_REG = QPLL0CLKOUT_RATE;
localparam [15:0] QPLL0_CFG0_REG = QPLL0_CFG0;
localparam [15:0] QPLL0_CFG1_REG = QPLL0_CFG1;
localparam [15:0] QPLL0_CFG1_G3_REG = QPLL0_CFG1_G3;
localparam [15:0] QPLL0_CFG2_REG = QPLL0_CFG2;
localparam [15:0] QPLL0_CFG2_G3_REG = QPLL0_CFG2_G3;
localparam [15:0] QPLL0_CFG3_REG = QPLL0_CFG3;
localparam [15:0] QPLL0_CFG4_REG = QPLL0_CFG4;
localparam [9:0] QPLL0_CP_REG = QPLL0_CP;
localparam [9:0] QPLL0_CP_G3_REG = QPLL0_CP_G3;
localparam [7:0] QPLL0_FBDIV_REG = QPLL0_FBDIV;
localparam [7:0] QPLL0_FBDIV_G3_REG = QPLL0_FBDIV_G3;
localparam [15:0] QPLL0_INIT_CFG0_REG = QPLL0_INIT_CFG0;
localparam [7:0] QPLL0_INIT_CFG1_REG = QPLL0_INIT_CFG1;
localparam [15:0] QPLL0_LOCK_CFG_REG = QPLL0_LOCK_CFG;
localparam [15:0] QPLL0_LOCK_CFG_G3_REG = QPLL0_LOCK_CFG_G3;
localparam [9:0] QPLL0_LPF_REG = QPLL0_LPF;
localparam [9:0] QPLL0_LPF_G3_REG = QPLL0_LPF_G3;
localparam [4:0] QPLL0_REFCLK_DIV_REG = QPLL0_REFCLK_DIV;
localparam [15:0] QPLL0_SDM_CFG0_REG = QPLL0_SDM_CFG0;
localparam [15:0] QPLL0_SDM_CFG1_REG = QPLL0_SDM_CFG1;
localparam [15:0] QPLL0_SDM_CFG2_REG = QPLL0_SDM_CFG2;
localparam [32:1] QPLL1CLKOUT_RATE_REG = QPLL1CLKOUT_RATE;
localparam [15:0] QPLL1_CFG0_REG = QPLL1_CFG0;
localparam [15:0] QPLL1_CFG1_REG = QPLL1_CFG1;
localparam [15:0] QPLL1_CFG1_G3_REG = QPLL1_CFG1_G3;
localparam [15:0] QPLL1_CFG2_REG = QPLL1_CFG2;
localparam [15:0] QPLL1_CFG2_G3_REG = QPLL1_CFG2_G3;
localparam [15:0] QPLL1_CFG3_REG = QPLL1_CFG3;
localparam [15:0] QPLL1_CFG4_REG = QPLL1_CFG4;
localparam [9:0] QPLL1_CP_REG = QPLL1_CP;
localparam [9:0] QPLL1_CP_G3_REG = QPLL1_CP_G3;
localparam [7:0] QPLL1_FBDIV_REG = QPLL1_FBDIV;
localparam [7:0] QPLL1_FBDIV_G3_REG = QPLL1_FBDIV_G3;
localparam [15:0] QPLL1_INIT_CFG0_REG = QPLL1_INIT_CFG0;
localparam [7:0] QPLL1_INIT_CFG1_REG = QPLL1_INIT_CFG1;
localparam [15:0] QPLL1_LOCK_CFG_REG = QPLL1_LOCK_CFG;
localparam [15:0] QPLL1_LOCK_CFG_G3_REG = QPLL1_LOCK_CFG_G3;
localparam [9:0] QPLL1_LPF_REG = QPLL1_LPF;
localparam [9:0] QPLL1_LPF_G3_REG = QPLL1_LPF_G3;
localparam [4:0] QPLL1_REFCLK_DIV_REG = QPLL1_REFCLK_DIV;
localparam [15:0] QPLL1_SDM_CFG0_REG = QPLL1_SDM_CFG0;
localparam [15:0] QPLL1_SDM_CFG1_REG = QPLL1_SDM_CFG1;
localparam [15:0] QPLL1_SDM_CFG2_REG = QPLL1_SDM_CFG2;
localparam [15:0] RSVD_ATTR0_REG = RSVD_ATTR0;
localparam [15:0] RSVD_ATTR1_REG = RSVD_ATTR1;
localparam [15:0] RSVD_ATTR2_REG = RSVD_ATTR2;
localparam [15:0] RSVD_ATTR3_REG = RSVD_ATTR3;
localparam [1:0] RXRECCLKOUT0_SEL_REG = RXRECCLKOUT0_SEL;
localparam [1:0] RXRECCLKOUT1_SEL_REG = RXRECCLKOUT1_SEL;
localparam [0:0] SARC_EN_REG = SARC_EN;
localparam [0:0] SARC_SEL_REG = SARC_SEL;
localparam [15:0] SDM0INITSEED0_0_REG = SDM0INITSEED0_0;
localparam [8:0] SDM0INITSEED0_1_REG = SDM0INITSEED0_1;
localparam [15:0] SDM1INITSEED0_0_REG = SDM1INITSEED0_0;
localparam [8:0] SDM1INITSEED0_1_REG = SDM1INITSEED0_1;
// localparam [80:1] SIM_MODE_REG = SIM_MODE;
// localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
// localparam [1:0] SIM_VERSION_REG = SIM_VERSION;
`endif
localparam [0:0] AEN_BGBS0_REG = 1'b0;
localparam [0:0] AEN_BGBS1_REG = 1'b0;
localparam [0:0] AEN_MASTER0_REG = 1'b0;
localparam [0:0] AEN_MASTER1_REG = 1'b0;
localparam [0:0] AEN_PD0_REG = 1'b0;
localparam [0:0] AEN_PD1_REG = 1'b0;
localparam [0:0] AEN_QPLL0_REG = 1'b0;
localparam [0:0] AEN_QPLL1_REG = 1'b0;
localparam [0:0] AEN_REFCLK0_REG = 1'b0;
localparam [0:0] AEN_REFCLK1_REG = 1'b0;
localparam [0:0] AEN_RESET0_REG = 1'b0;
localparam [0:0] AEN_RESET1_REG = 1'b0;
localparam [0:0] AEN_SDMDATA0_REG = 1'b0;
localparam [0:0] AEN_SDMDATA1_REG = 1'b0;
localparam [0:0] AEN_SDMRESET0_REG = 1'b0;
localparam [0:0] AEN_SDMRESET1_REG = 1'b0;
localparam [0:0] AEN_SDMWIDTH0_REG = 1'b0;
localparam [0:0] AEN_SDMWIDTH1_REG = 1'b0;
localparam [3:0] AQDMUXSEL1_REG = 4'b0000;
localparam [3:0] AVCC_SENSE_SEL_REG = 4'b0000;
localparam [3:0] AVTT_SENSE_SEL_REG = 4'b0000;
localparam [0:0] A_BGMONITOREN_REG = 1'b0;
localparam [0:0] A_BGPD_REG = 1'b0;
localparam [0:0] A_GTREFCLKPD0_REG = 1'b0;
localparam [0:0] A_GTREFCLKPD1_REG = 1'b0;
localparam [0:0] A_QPLL0LOCKEN_REG = 1'b0;
localparam [0:0] A_QPLL0PD_REG = 1'b0;
localparam [0:0] A_QPLL0RESET_REG = 1'b0;
localparam [0:0] A_QPLL1LOCKEN_REG = 1'b0;
localparam [0:0] A_QPLL1PD_REG = 1'b0;
localparam [0:0] A_QPLL1RESET_REG = 1'b0;
localparam [15:0] A_SDM0DATA1_0_REG = 16'b0000000000000000;
localparam [8:0] A_SDM0DATA1_1_REG = 9'b000000000;
localparam [0:0] A_SDMRESET0_REG = 1'b0;
localparam [0:0] A_SDMRESET1_REG = 1'b0;
localparam [1:0] COMMON_AMUX_SEL0_REG = 2'b00;
localparam [1:0] COMMON_AMUX_SEL1_REG = 2'b00;
localparam [0:0] COMMON_INSTANTIATED_REG = 1'b1;
localparam [2:0] QPLL0_AMONITOR_SEL_REG = 3'b000;
localparam [2:0] QPLL1_AMONITOR_SEL_REG = 3'b000;
localparam [0:0] RCALSAP_TESTEN_REG = 1'b0;
localparam [0:0] RCAL_APROBE_REG = 1'b0;
localparam [0:0] REFCLK0_EN_DC_COUP_REG = 1'b0;
localparam [0:0] REFCLK0_VCM_HIGH_REG = 1'b0;
localparam [0:0] REFCLK0_VCM_LOW_REG = 1'b0;
localparam [0:0] REFCLK1_EN_DC_COUP_REG = 1'b0;
localparam [0:0] REFCLK1_VCM_HIGH_REG = 1'b0;
localparam [0:0] REFCLK1_VCM_LOW_REG = 1'b0;
localparam [1:0] VCCAUX_SENSE_SEL_REG = 2'b00;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire DRPRDY_out;
wire QPLL0FBCLKLOST_out;
wire QPLL0LOCK_out;
wire QPLL0OUTCLK_out;
wire QPLL0OUTREFCLK_out;
wire QPLL0REFCLKLOST_out;
wire QPLL1FBCLKLOST_out;
wire QPLL1LOCK_out;
wire QPLL1OUTCLK_out;
wire QPLL1OUTREFCLK_out;
wire QPLL1REFCLKLOST_out;
wire REFCLKOUTMONITOR0_out;
wire REFCLKOUTMONITOR1_out;
wire [14:0] SDM0TESTDATA_out;
wire [14:0] SDM1TESTDATA_out;
wire [15:0] DRPDO_out;
wire [1:0] RXRECCLK0_SEL_out;
wire [1:0] RXRECCLK1_SEL_out;
wire [3:0] SARCCLK_out;
wire [3:0] SDM0FINALOUT_out;
wire [3:0] SDM1FINALOUT_out;
wire [7:0] PMARSVDOUT0_out;
wire [7:0] PMARSVDOUT1_out;
wire [7:0] PMASCANOUT_out;
wire [7:0] QPLLDMONITOR0_out;
wire [7:0] QPLLDMONITOR1_out;
wire DRPRDY_delay;
wire QPLL0FBCLKLOST_delay;
wire QPLL0LOCK_delay;
wire QPLL0OUTCLK_delay;
wire QPLL0OUTREFCLK_delay;
wire QPLL0REFCLKLOST_delay;
wire QPLL1FBCLKLOST_delay;
wire QPLL1LOCK_delay;
wire QPLL1OUTCLK_delay;
wire QPLL1OUTREFCLK_delay;
wire QPLL1REFCLKLOST_delay;
wire REFCLKOUTMONITOR0_delay;
wire REFCLKOUTMONITOR1_delay;
wire [14:0] SDM0TESTDATA_delay;
wire [14:0] SDM1TESTDATA_delay;
wire [15:0] DRPDO_delay;
wire [1:0] RXRECCLK0_SEL_delay;
wire [1:0] RXRECCLK1_SEL_delay;
wire [3:0] SDM0FINALOUT_delay;
wire [3:0] SDM1FINALOUT_delay;
wire [7:0] PMARSVDOUT0_delay;
wire [7:0] PMARSVDOUT1_delay;
wire [7:0] QPLLDMONITOR0_delay;
wire [7:0] QPLLDMONITOR1_delay;
wire BGBYPASSB_in;
wire BGMONITORENB_in;
wire BGPDB_in;
wire BGRCALOVRDENB_in;
wire DRPCLK_in;
wire DRPEN_in;
wire DRPWE_in;
wire GTGREFCLK0_in;
wire GTGREFCLK1_in;
wire GTNORTHREFCLK00_in;
wire GTNORTHREFCLK01_in;
wire GTNORTHREFCLK10_in;
wire GTNORTHREFCLK11_in;
wire GTREFCLK00_in;
wire GTREFCLK01_in;
wire GTREFCLK10_in;
wire GTREFCLK11_in;
wire GTSOUTHREFCLK00_in;
wire GTSOUTHREFCLK01_in;
wire GTSOUTHREFCLK10_in;
wire GTSOUTHREFCLK11_in;
wire PMASCANENB_in;
wire QDPMASCANMODEB_in;
wire QDPMASCANRSTEN_in;
wire QPLL0CLKRSVD0_in;
wire QPLL0LOCKDETCLK_in;
wire QPLL0LOCKEN_in;
wire QPLL0PD_in;
wire QPLL0RESET_in;
wire QPLL1CLKRSVD0_in;
wire QPLL1LOCKDETCLK_in;
wire QPLL1LOCKEN_in;
wire QPLL1PD_in;
wire QPLL1RESET_in;
wire RCALENB_in;
wire SDM0RESET_in;
wire SDM1RESET_in;
wire [15:0] DRPDI_in;
wire [1:0] SDM0WIDTH_in;
wire [1:0] SDM1WIDTH_in;
wire [24:0] SDM0DATA_in;
wire [24:0] SDM1DATA_in;
wire [2:0] QPLL0REFCLKSEL_in;
wire [2:0] QPLL1REFCLKSEL_in;
wire [3:0] RXRECCLK_in;
wire [4:0] BGRCALOVRD_in;
wire [4:0] QPLLRSVD2_in;
wire [4:0] QPLLRSVD3_in;
wire [7:0] PMARSVD0_in;
wire [7:0] PMARSVD1_in;
wire [7:0] PMASCANCLK_in;
wire [7:0] PMASCANIN_in;
wire [7:0] QPLLRSVD1_in;
wire [7:0] QPLLRSVD4_in;
wire [9:0] DRPADDR_in;
wire BGBYPASSB_delay;
wire BGMONITORENB_delay;
wire BGPDB_delay;
wire BGRCALOVRDENB_delay;
wire DRPCLK_delay;
wire DRPEN_delay;
wire DRPWE_delay;
wire GTGREFCLK0_delay;
wire GTGREFCLK1_delay;
wire GTNORTHREFCLK00_delay;
wire GTNORTHREFCLK01_delay;
wire GTNORTHREFCLK10_delay;
wire GTNORTHREFCLK11_delay;
wire GTREFCLK00_delay;
wire GTREFCLK01_delay;
wire GTREFCLK10_delay;
wire GTREFCLK11_delay;
wire GTSOUTHREFCLK00_delay;
wire GTSOUTHREFCLK01_delay;
wire GTSOUTHREFCLK10_delay;
wire GTSOUTHREFCLK11_delay;
wire QPLL0CLKRSVD0_delay;
wire QPLL0LOCKDETCLK_delay;
wire QPLL0LOCKEN_delay;
wire QPLL0PD_delay;
wire QPLL0RESET_delay;
wire QPLL1CLKRSVD0_delay;
wire QPLL1LOCKDETCLK_delay;
wire QPLL1LOCKEN_delay;
wire QPLL1PD_delay;
wire QPLL1RESET_delay;
wire RCALENB_delay;
wire SDM0RESET_delay;
wire SDM1RESET_delay;
wire [15:0] DRPDI_delay;
wire [1:0] SDM0WIDTH_delay;
wire [1:0] SDM1WIDTH_delay;
wire [24:0] SDM0DATA_delay;
wire [24:0] SDM1DATA_delay;
wire [2:0] QPLL0REFCLKSEL_delay;
wire [2:0] QPLL1REFCLKSEL_delay;
wire [4:0] BGRCALOVRD_delay;
wire [4:0] QPLLRSVD2_delay;
wire [4:0] QPLLRSVD3_delay;
wire [7:0] PMARSVD0_delay;
wire [7:0] PMARSVD1_delay;
wire [7:0] QPLLRSVD1_delay;
wire [7:0] QPLLRSVD4_delay;
wire [9:0] DRPADDR_delay;
assign #(out_delay) DRPDO = DRPDO_delay;
assign #(out_delay) DRPRDY = DRPRDY_delay;
assign #(out_delay) PMARSVDOUT0 = PMARSVDOUT0_delay;
assign #(out_delay) PMARSVDOUT1 = PMARSVDOUT1_delay;
assign #(out_delay) QPLL0FBCLKLOST = QPLL0FBCLKLOST_delay;
assign #(out_delay) QPLL0LOCK = QPLL0LOCK_delay;
assign #(out_delay) QPLL0OUTCLK = QPLL0OUTCLK_delay;
assign #(out_delay) QPLL0OUTREFCLK = QPLL0OUTREFCLK_delay;
assign #(out_delay) QPLL0REFCLKLOST = QPLL0REFCLKLOST_delay;
assign #(out_delay) QPLL1FBCLKLOST = QPLL1FBCLKLOST_delay;
assign #(out_delay) QPLL1LOCK = QPLL1LOCK_delay;
assign #(out_delay) QPLL1OUTCLK = QPLL1OUTCLK_delay;
assign #(out_delay) QPLL1OUTREFCLK = QPLL1OUTREFCLK_delay;
assign #(out_delay) QPLL1REFCLKLOST = QPLL1REFCLKLOST_delay;
assign #(out_delay) QPLLDMONITOR0 = QPLLDMONITOR0_delay;
assign #(out_delay) QPLLDMONITOR1 = QPLLDMONITOR1_delay;
assign #(out_delay) REFCLKOUTMONITOR0 = REFCLKOUTMONITOR0_delay;
assign #(out_delay) REFCLKOUTMONITOR1 = REFCLKOUTMONITOR1_delay;
assign #(out_delay) RXRECCLK0_SEL = RXRECCLK0_SEL_delay;
assign #(out_delay) RXRECCLK1_SEL = RXRECCLK1_SEL_delay;
assign #(out_delay) SDM0FINALOUT = SDM0FINALOUT_delay;
assign #(out_delay) SDM0TESTDATA = SDM0TESTDATA_delay;
assign #(out_delay) SDM1FINALOUT = SDM1FINALOUT_delay;
assign #(out_delay) SDM1TESTDATA = SDM1TESTDATA_delay;
`ifdef XIL_TIMING
reg notifier;
`endif
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) DRPCLK_delay = DRPCLK;
assign #(in_delay) DRPADDR_delay = DRPADDR;
assign #(in_delay) DRPDI_delay = DRPDI;
assign #(in_delay) DRPEN_delay = DRPEN;
assign #(in_delay) DRPWE_delay = DRPWE;
`endif
// inputs with no timing checks
assign #(inclk_delay) GTGREFCLK0_delay = GTGREFCLK0;
assign #(inclk_delay) GTGREFCLK1_delay = GTGREFCLK1;
assign #(inclk_delay) GTNORTHREFCLK00_delay = GTNORTHREFCLK00;
assign #(inclk_delay) GTNORTHREFCLK01_delay = GTNORTHREFCLK01;
assign #(inclk_delay) GTNORTHREFCLK10_delay = GTNORTHREFCLK10;
assign #(inclk_delay) GTNORTHREFCLK11_delay = GTNORTHREFCLK11;
assign #(inclk_delay) GTREFCLK00_delay = GTREFCLK00;
assign #(inclk_delay) GTREFCLK01_delay = GTREFCLK01;
assign #(inclk_delay) GTREFCLK10_delay = GTREFCLK10;
assign #(inclk_delay) GTREFCLK11_delay = GTREFCLK11;
assign #(inclk_delay) GTSOUTHREFCLK00_delay = GTSOUTHREFCLK00;
assign #(inclk_delay) GTSOUTHREFCLK01_delay = GTSOUTHREFCLK01;
assign #(inclk_delay) GTSOUTHREFCLK10_delay = GTSOUTHREFCLK10;
assign #(inclk_delay) GTSOUTHREFCLK11_delay = GTSOUTHREFCLK11;
assign #(inclk_delay) QPLL0CLKRSVD0_delay = QPLL0CLKRSVD0;
assign #(inclk_delay) QPLL0LOCKDETCLK_delay = QPLL0LOCKDETCLK;
assign #(inclk_delay) QPLL1CLKRSVD0_delay = QPLL1CLKRSVD0;
assign #(inclk_delay) QPLL1LOCKDETCLK_delay = QPLL1LOCKDETCLK;
assign #(in_delay) BGBYPASSB_delay = BGBYPASSB;
assign #(in_delay) BGMONITORENB_delay = BGMONITORENB;
assign #(in_delay) BGPDB_delay = BGPDB;
assign #(in_delay) BGRCALOVRDENB_delay = BGRCALOVRDENB;
assign #(in_delay) BGRCALOVRD_delay = BGRCALOVRD;
assign #(in_delay) PMARSVD0_delay = PMARSVD0;
assign #(in_delay) PMARSVD1_delay = PMARSVD1;
assign #(in_delay) QPLL0LOCKEN_delay = QPLL0LOCKEN;
assign #(in_delay) QPLL0PD_delay = QPLL0PD;
assign #(in_delay) QPLL0REFCLKSEL_delay = QPLL0REFCLKSEL;
assign #(in_delay) QPLL0RESET_delay = QPLL0RESET;
assign #(in_delay) QPLL1LOCKEN_delay = QPLL1LOCKEN;
assign #(in_delay) QPLL1PD_delay = QPLL1PD;
assign #(in_delay) QPLL1REFCLKSEL_delay = QPLL1REFCLKSEL;
assign #(in_delay) QPLL1RESET_delay = QPLL1RESET;
assign #(in_delay) QPLLRSVD1_delay = QPLLRSVD1;
assign #(in_delay) QPLLRSVD2_delay = QPLLRSVD2;
assign #(in_delay) QPLLRSVD3_delay = QPLLRSVD3;
assign #(in_delay) QPLLRSVD4_delay = QPLLRSVD4;
assign #(in_delay) RCALENB_delay = RCALENB;
assign #(in_delay) SDM0DATA_delay = SDM0DATA;
assign #(in_delay) SDM0RESET_delay = SDM0RESET;
assign #(in_delay) SDM0WIDTH_delay = SDM0WIDTH;
assign #(in_delay) SDM1DATA_delay = SDM1DATA;
assign #(in_delay) SDM1RESET_delay = SDM1RESET;
assign #(in_delay) SDM1WIDTH_delay = SDM1WIDTH;
assign DRPDO_delay = DRPDO_out;
assign DRPRDY_delay = DRPRDY_out;
assign PMARSVDOUT0_delay = PMARSVDOUT0_out;
assign PMARSVDOUT1_delay = PMARSVDOUT1_out;
assign QPLL0FBCLKLOST_delay = QPLL0FBCLKLOST_out;
assign QPLL0LOCK_delay = QPLL0LOCK_out;
assign QPLL0OUTCLK_delay = QPLL0OUTCLK_out;
assign QPLL0OUTREFCLK_delay = QPLL0OUTREFCLK_out;
assign QPLL0REFCLKLOST_delay = QPLL0REFCLKLOST_out;
assign QPLL1FBCLKLOST_delay = QPLL1FBCLKLOST_out;
assign QPLL1LOCK_delay = QPLL1LOCK_out;
assign QPLL1OUTCLK_delay = QPLL1OUTCLK_out;
assign QPLL1OUTREFCLK_delay = QPLL1OUTREFCLK_out;
assign QPLL1REFCLKLOST_delay = QPLL1REFCLKLOST_out;
assign QPLLDMONITOR0_delay = QPLLDMONITOR0_out;
assign QPLLDMONITOR1_delay = QPLLDMONITOR1_out;
assign REFCLKOUTMONITOR0_delay = REFCLKOUTMONITOR0_out;
assign REFCLKOUTMONITOR1_delay = REFCLKOUTMONITOR1_out;
assign RXRECCLK0_SEL_delay = RXRECCLK0_SEL_out;
assign RXRECCLK1_SEL_delay = RXRECCLK1_SEL_out;
assign SDM0FINALOUT_delay = SDM0FINALOUT_out;
assign SDM0TESTDATA_delay = SDM0TESTDATA_out;
assign SDM1FINALOUT_delay = SDM1FINALOUT_out;
assign SDM1TESTDATA_delay = SDM1TESTDATA_out;
assign BGBYPASSB_in = BGBYPASSB_delay;
assign BGMONITORENB_in = BGMONITORENB_delay;
assign BGPDB_in = BGPDB_delay;
assign BGRCALOVRDENB_in = BGRCALOVRDENB_delay;
assign BGRCALOVRD_in = BGRCALOVRD_delay;
assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0
assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0
assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0
assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0
assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0
assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0
assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0
assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0
assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0
assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0
assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0
assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0
assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0
assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0
assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0
assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0
assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0
assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0
assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0
assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0
assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0
assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0
assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0
assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0
assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0
assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0
assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0
assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0
assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0
assign GTGREFCLK0_in = GTGREFCLK0_delay;
assign GTGREFCLK1_in = GTGREFCLK1_delay;
assign GTNORTHREFCLK00_in = GTNORTHREFCLK00_delay;
assign GTNORTHREFCLK01_in = GTNORTHREFCLK01_delay;
assign GTNORTHREFCLK10_in = GTNORTHREFCLK10_delay;
assign GTNORTHREFCLK11_in = GTNORTHREFCLK11_delay;
assign GTREFCLK00_in = GTREFCLK00_delay;
assign GTREFCLK01_in = GTREFCLK01_delay;
assign GTREFCLK10_in = GTREFCLK10_delay;
assign GTREFCLK11_in = GTREFCLK11_delay;
assign GTSOUTHREFCLK00_in = GTSOUTHREFCLK00_delay;
assign GTSOUTHREFCLK01_in = GTSOUTHREFCLK01_delay;
assign GTSOUTHREFCLK10_in = GTSOUTHREFCLK10_delay;
assign GTSOUTHREFCLK11_in = GTSOUTHREFCLK11_delay;
assign PMARSVD0_in[0] = (PMARSVD0[0] !== 1'bz) && PMARSVD0_delay[0]; // rv 0
assign PMARSVD0_in[1] = (PMARSVD0[1] !== 1'bz) && PMARSVD0_delay[1]; // rv 0
assign PMARSVD0_in[2] = (PMARSVD0[2] !== 1'bz) && PMARSVD0_delay[2]; // rv 0
assign PMARSVD0_in[3] = (PMARSVD0[3] !== 1'bz) && PMARSVD0_delay[3]; // rv 0
assign PMARSVD0_in[4] = (PMARSVD0[4] !== 1'bz) && PMARSVD0_delay[4]; // rv 0
assign PMARSVD0_in[5] = (PMARSVD0[5] !== 1'bz) && PMARSVD0_delay[5]; // rv 0
assign PMARSVD0_in[6] = (PMARSVD0[6] !== 1'bz) && PMARSVD0_delay[6]; // rv 0
assign PMARSVD0_in[7] = (PMARSVD0[7] !== 1'bz) && PMARSVD0_delay[7]; // rv 0
assign PMARSVD1_in[0] = (PMARSVD1[0] !== 1'bz) && PMARSVD1_delay[0]; // rv 0
assign PMARSVD1_in[1] = (PMARSVD1[1] !== 1'bz) && PMARSVD1_delay[1]; // rv 0
assign PMARSVD1_in[2] = (PMARSVD1[2] !== 1'bz) && PMARSVD1_delay[2]; // rv 0
assign PMARSVD1_in[3] = (PMARSVD1[3] !== 1'bz) && PMARSVD1_delay[3]; // rv 0
assign PMARSVD1_in[4] = (PMARSVD1[4] !== 1'bz) && PMARSVD1_delay[4]; // rv 0
assign PMARSVD1_in[5] = (PMARSVD1[5] !== 1'bz) && PMARSVD1_delay[5]; // rv 0
assign PMARSVD1_in[6] = (PMARSVD1[6] !== 1'bz) && PMARSVD1_delay[6]; // rv 0
assign PMARSVD1_in[7] = (PMARSVD1[7] !== 1'bz) && PMARSVD1_delay[7]; // rv 0
assign QPLL0CLKRSVD0_in = (QPLL0CLKRSVD0 === 1'bz) || QPLL0CLKRSVD0_delay; // rv 1
assign QPLL0LOCKDETCLK_in = (QPLL0LOCKDETCLK === 1'bz) || QPLL0LOCKDETCLK_delay; // rv 1
assign QPLL0LOCKEN_in = (QPLL0LOCKEN !== 1'bz) && QPLL0LOCKEN_delay; // rv 0
assign QPLL0PD_in = (QPLL0PD !== 1'bz) && QPLL0PD_delay; // rv 0
assign QPLL0REFCLKSEL_in[0] = (QPLL0REFCLKSEL[0] === 1'bz) || QPLL0REFCLKSEL_delay[0]; // rv 1
assign QPLL0REFCLKSEL_in[1] = (QPLL0REFCLKSEL[1] !== 1'bz) && QPLL0REFCLKSEL_delay[1]; // rv 0
assign QPLL0REFCLKSEL_in[2] = (QPLL0REFCLKSEL[2] !== 1'bz) && QPLL0REFCLKSEL_delay[2]; // rv 0
assign QPLL0RESET_in = (QPLL0RESET !== 1'bz) && QPLL0RESET_delay; // rv 0
assign QPLL1CLKRSVD0_in = (QPLL1CLKRSVD0 === 1'bz) || QPLL1CLKRSVD0_delay; // rv 1
assign QPLL1LOCKDETCLK_in = (QPLL1LOCKDETCLK === 1'bz) || QPLL1LOCKDETCLK_delay; // rv 1
assign QPLL1LOCKEN_in = (QPLL1LOCKEN !== 1'bz) && QPLL1LOCKEN_delay; // rv 0
assign QPLL1PD_in = (QPLL1PD !== 1'bz) && QPLL1PD_delay; // rv 0
assign QPLL1REFCLKSEL_in[0] = (QPLL1REFCLKSEL[0] === 1'bz) || QPLL1REFCLKSEL_delay[0]; // rv 1
assign QPLL1REFCLKSEL_in[1] = (QPLL1REFCLKSEL[1] !== 1'bz) && QPLL1REFCLKSEL_delay[1]; // rv 0
assign QPLL1REFCLKSEL_in[2] = (QPLL1REFCLKSEL[2] !== 1'bz) && QPLL1REFCLKSEL_delay[2]; // rv 0
assign QPLL1RESET_in = (QPLL1RESET !== 1'bz) && QPLL1RESET_delay; // rv 0
assign QPLLRSVD1_in[0] = (QPLLRSVD1[0] !== 1'bz) && QPLLRSVD1_delay[0]; // rv 0
assign QPLLRSVD1_in[1] = (QPLLRSVD1[1] !== 1'bz) && QPLLRSVD1_delay[1]; // rv 0
assign QPLLRSVD1_in[2] = (QPLLRSVD1[2] !== 1'bz) && QPLLRSVD1_delay[2]; // rv 0
assign QPLLRSVD1_in[3] = (QPLLRSVD1[3] !== 1'bz) && QPLLRSVD1_delay[3]; // rv 0
assign QPLLRSVD1_in[4] = (QPLLRSVD1[4] !== 1'bz) && QPLLRSVD1_delay[4]; // rv 0
assign QPLLRSVD1_in[5] = (QPLLRSVD1[5] !== 1'bz) && QPLLRSVD1_delay[5]; // rv 0
assign QPLLRSVD1_in[6] = (QPLLRSVD1[6] !== 1'bz) && QPLLRSVD1_delay[6]; // rv 0
assign QPLLRSVD1_in[7] = (QPLLRSVD1[7] !== 1'bz) && QPLLRSVD1_delay[7]; // rv 0
assign QPLLRSVD2_in[0] = (QPLLRSVD2[0] !== 1'bz) && QPLLRSVD2_delay[0]; // rv 0
assign QPLLRSVD2_in[1] = (QPLLRSVD2[1] !== 1'bz) && QPLLRSVD2_delay[1]; // rv 0
assign QPLLRSVD2_in[2] = (QPLLRSVD2[2] !== 1'bz) && QPLLRSVD2_delay[2]; // rv 0
assign QPLLRSVD2_in[3] = (QPLLRSVD2[3] !== 1'bz) && QPLLRSVD2_delay[3]; // rv 0
assign QPLLRSVD2_in[4] = (QPLLRSVD2[4] !== 1'bz) && QPLLRSVD2_delay[4]; // rv 0
assign QPLLRSVD3_in[0] = (QPLLRSVD3[0] !== 1'bz) && QPLLRSVD3_delay[0]; // rv 0
assign QPLLRSVD3_in[1] = (QPLLRSVD3[1] !== 1'bz) && QPLLRSVD3_delay[1]; // rv 0
assign QPLLRSVD3_in[2] = (QPLLRSVD3[2] !== 1'bz) && QPLLRSVD3_delay[2]; // rv 0
assign QPLLRSVD3_in[3] = (QPLLRSVD3[3] !== 1'bz) && QPLLRSVD3_delay[3]; // rv 0
assign QPLLRSVD3_in[4] = (QPLLRSVD3[4] !== 1'bz) && QPLLRSVD3_delay[4]; // rv 0
assign QPLLRSVD4_in[0] = (QPLLRSVD4[0] !== 1'bz) && QPLLRSVD4_delay[0]; // rv 0
assign QPLLRSVD4_in[1] = (QPLLRSVD4[1] !== 1'bz) && QPLLRSVD4_delay[1]; // rv 0
assign QPLLRSVD4_in[2] = (QPLLRSVD4[2] !== 1'bz) && QPLLRSVD4_delay[2]; // rv 0
assign QPLLRSVD4_in[3] = (QPLLRSVD4[3] !== 1'bz) && QPLLRSVD4_delay[3]; // rv 0
assign QPLLRSVD4_in[4] = (QPLLRSVD4[4] !== 1'bz) && QPLLRSVD4_delay[4]; // rv 0
assign QPLLRSVD4_in[5] = (QPLLRSVD4[5] !== 1'bz) && QPLLRSVD4_delay[5]; // rv 0
assign QPLLRSVD4_in[6] = (QPLLRSVD4[6] !== 1'bz) && QPLLRSVD4_delay[6]; // rv 0
assign QPLLRSVD4_in[7] = (QPLLRSVD4[7] !== 1'bz) && QPLLRSVD4_delay[7]; // rv 0
assign RCALENB_in = RCALENB_delay;
assign SDM0DATA_in[0] = (SDM0DATA[0] !== 1'bz) && SDM0DATA_delay[0]; // rv 0
assign SDM0DATA_in[10] = (SDM0DATA[10] !== 1'bz) && SDM0DATA_delay[10]; // rv 0
assign SDM0DATA_in[11] = (SDM0DATA[11] !== 1'bz) && SDM0DATA_delay[11]; // rv 0
assign SDM0DATA_in[12] = (SDM0DATA[12] !== 1'bz) && SDM0DATA_delay[12]; // rv 0
assign SDM0DATA_in[13] = (SDM0DATA[13] !== 1'bz) && SDM0DATA_delay[13]; // rv 0
assign SDM0DATA_in[14] = (SDM0DATA[14] !== 1'bz) && SDM0DATA_delay[14]; // rv 0
assign SDM0DATA_in[15] = (SDM0DATA[15] !== 1'bz) && SDM0DATA_delay[15]; // rv 0
assign SDM0DATA_in[16] = (SDM0DATA[16] !== 1'bz) && SDM0DATA_delay[16]; // rv 0
assign SDM0DATA_in[17] = (SDM0DATA[17] !== 1'bz) && SDM0DATA_delay[17]; // rv 0
assign SDM0DATA_in[18] = (SDM0DATA[18] !== 1'bz) && SDM0DATA_delay[18]; // rv 0
assign SDM0DATA_in[19] = (SDM0DATA[19] !== 1'bz) && SDM0DATA_delay[19]; // rv 0
assign SDM0DATA_in[1] = (SDM0DATA[1] !== 1'bz) && SDM0DATA_delay[1]; // rv 0
assign SDM0DATA_in[20] = (SDM0DATA[20] !== 1'bz) && SDM0DATA_delay[20]; // rv 0
assign SDM0DATA_in[21] = (SDM0DATA[21] !== 1'bz) && SDM0DATA_delay[21]; // rv 0
assign SDM0DATA_in[22] = (SDM0DATA[22] !== 1'bz) && SDM0DATA_delay[22]; // rv 0
assign SDM0DATA_in[23] = (SDM0DATA[23] !== 1'bz) && SDM0DATA_delay[23]; // rv 0
assign SDM0DATA_in[24] = (SDM0DATA[24] !== 1'bz) && SDM0DATA_delay[24]; // rv 0
assign SDM0DATA_in[2] = (SDM0DATA[2] !== 1'bz) && SDM0DATA_delay[2]; // rv 0
assign SDM0DATA_in[3] = (SDM0DATA[3] !== 1'bz) && SDM0DATA_delay[3]; // rv 0
assign SDM0DATA_in[4] = (SDM0DATA[4] !== 1'bz) && SDM0DATA_delay[4]; // rv 0
assign SDM0DATA_in[5] = (SDM0DATA[5] !== 1'bz) && SDM0DATA_delay[5]; // rv 0
assign SDM0DATA_in[6] = (SDM0DATA[6] !== 1'bz) && SDM0DATA_delay[6]; // rv 0
assign SDM0DATA_in[7] = (SDM0DATA[7] !== 1'bz) && SDM0DATA_delay[7]; // rv 0
assign SDM0DATA_in[8] = (SDM0DATA[8] !== 1'bz) && SDM0DATA_delay[8]; // rv 0
assign SDM0DATA_in[9] = (SDM0DATA[9] !== 1'bz) && SDM0DATA_delay[9]; // rv 0
assign SDM0RESET_in = (SDM0RESET !== 1'bz) && SDM0RESET_delay; // rv 0
assign SDM0WIDTH_in[0] = (SDM0WIDTH[0] !== 1'bz) && SDM0WIDTH_delay[0]; // rv 0
assign SDM0WIDTH_in[1] = (SDM0WIDTH[1] !== 1'bz) && SDM0WIDTH_delay[1]; // rv 0
assign SDM1DATA_in[0] = (SDM1DATA[0] !== 1'bz) && SDM1DATA_delay[0]; // rv 0
assign SDM1DATA_in[10] = (SDM1DATA[10] !== 1'bz) && SDM1DATA_delay[10]; // rv 0
assign SDM1DATA_in[11] = (SDM1DATA[11] !== 1'bz) && SDM1DATA_delay[11]; // rv 0
assign SDM1DATA_in[12] = (SDM1DATA[12] !== 1'bz) && SDM1DATA_delay[12]; // rv 0
assign SDM1DATA_in[13] = (SDM1DATA[13] !== 1'bz) && SDM1DATA_delay[13]; // rv 0
assign SDM1DATA_in[14] = (SDM1DATA[14] !== 1'bz) && SDM1DATA_delay[14]; // rv 0
assign SDM1DATA_in[15] = (SDM1DATA[15] !== 1'bz) && SDM1DATA_delay[15]; // rv 0
assign SDM1DATA_in[16] = (SDM1DATA[16] !== 1'bz) && SDM1DATA_delay[16]; // rv 0
assign SDM1DATA_in[17] = (SDM1DATA[17] !== 1'bz) && SDM1DATA_delay[17]; // rv 0
assign SDM1DATA_in[18] = (SDM1DATA[18] !== 1'bz) && SDM1DATA_delay[18]; // rv 0
assign SDM1DATA_in[19] = (SDM1DATA[19] !== 1'bz) && SDM1DATA_delay[19]; // rv 0
assign SDM1DATA_in[1] = (SDM1DATA[1] !== 1'bz) && SDM1DATA_delay[1]; // rv 0
assign SDM1DATA_in[20] = (SDM1DATA[20] !== 1'bz) && SDM1DATA_delay[20]; // rv 0
assign SDM1DATA_in[21] = (SDM1DATA[21] !== 1'bz) && SDM1DATA_delay[21]; // rv 0
assign SDM1DATA_in[22] = (SDM1DATA[22] !== 1'bz) && SDM1DATA_delay[22]; // rv 0
assign SDM1DATA_in[23] = (SDM1DATA[23] !== 1'bz) && SDM1DATA_delay[23]; // rv 0
assign SDM1DATA_in[24] = (SDM1DATA[24] !== 1'bz) && SDM1DATA_delay[24]; // rv 0
assign SDM1DATA_in[2] = (SDM1DATA[2] !== 1'bz) && SDM1DATA_delay[2]; // rv 0
assign SDM1DATA_in[3] = (SDM1DATA[3] !== 1'bz) && SDM1DATA_delay[3]; // rv 0
assign SDM1DATA_in[4] = (SDM1DATA[4] !== 1'bz) && SDM1DATA_delay[4]; // rv 0
assign SDM1DATA_in[5] = (SDM1DATA[5] !== 1'bz) && SDM1DATA_delay[5]; // rv 0
assign SDM1DATA_in[6] = (SDM1DATA[6] !== 1'bz) && SDM1DATA_delay[6]; // rv 0
assign SDM1DATA_in[7] = (SDM1DATA[7] !== 1'bz) && SDM1DATA_delay[7]; // rv 0
assign SDM1DATA_in[8] = (SDM1DATA[8] !== 1'bz) && SDM1DATA_delay[8]; // rv 0
assign SDM1DATA_in[9] = (SDM1DATA[9] !== 1'bz) && SDM1DATA_delay[9]; // rv 0
assign SDM1RESET_in = (SDM1RESET !== 1'bz) && SDM1RESET_delay; // rv 0
assign SDM1WIDTH_in[0] = (SDM1WIDTH[0] !== 1'bz) && SDM1WIDTH_delay[0]; // rv 0
assign SDM1WIDTH_in[1] = (SDM1WIDTH[1] !== 1'bz) && SDM1WIDTH_delay[1]; // rv 0
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((QPLL0CLKOUT_RATE_REG != "FULL") &&
(QPLL0CLKOUT_RATE_REG != "HALF"))) begin
$display("Error: [Unisim %s-152] QPLL0CLKOUT_RATE attribute is set to %s. Legal values for this attribute are FULL or HALF. Instance: %m", MODULE_NAME, QPLL0CLKOUT_RATE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((QPLL0_FBDIV_REG < 16) || (QPLL0_FBDIV_REG > 160))) begin
$display("Error: [Unisim %s-163] QPLL0_FBDIV attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL0_FBDIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((QPLL0_FBDIV_G3_REG < 16) || (QPLL0_FBDIV_G3_REG > 160))) begin
$display("Error: [Unisim %s-164] QPLL0_FBDIV_G3 attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL0_FBDIV_G3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((QPLL0_REFCLK_DIV_REG != 2) &&
(QPLL0_REFCLK_DIV_REG != 1) &&
(QPLL0_REFCLK_DIV_REG != 3) &&
(QPLL0_REFCLK_DIV_REG != 4) &&
(QPLL0_REFCLK_DIV_REG != 5) &&
(QPLL0_REFCLK_DIV_REG != 6) &&
(QPLL0_REFCLK_DIV_REG != 8) &&
(QPLL0_REFCLK_DIV_REG != 10) &&
(QPLL0_REFCLK_DIV_REG != 12) &&
(QPLL0_REFCLK_DIV_REG != 16) &&
(QPLL0_REFCLK_DIV_REG != 20))) begin
$display("Error: [Unisim %s-171] QPLL0_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 2, 1, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, QPLL0_REFCLK_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((QPLL1CLKOUT_RATE_REG != "FULL") &&
(QPLL1CLKOUT_RATE_REG != "HALF"))) begin
$display("Error: [Unisim %s-175] QPLL1CLKOUT_RATE attribute is set to %s. Legal values for this attribute are FULL or HALF. Instance: %m", MODULE_NAME, QPLL1CLKOUT_RATE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((QPLL1_FBDIV_REG < 16) || (QPLL1_FBDIV_REG > 160))) begin
$display("Error: [Unisim %s-186] QPLL1_FBDIV attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL1_FBDIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((QPLL1_FBDIV_G3_REG < 16) || (QPLL1_FBDIV_G3_REG > 160))) begin
$display("Error: [Unisim %s-187] QPLL1_FBDIV_G3 attribute is set to %d. Legal values for this attribute are 16 to 160. Instance: %m", MODULE_NAME, QPLL1_FBDIV_G3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((QPLL1_REFCLK_DIV_REG != 2) &&
(QPLL1_REFCLK_DIV_REG != 1) &&
(QPLL1_REFCLK_DIV_REG != 3) &&
(QPLL1_REFCLK_DIV_REG != 4) &&
(QPLL1_REFCLK_DIV_REG != 5) &&
(QPLL1_REFCLK_DIV_REG != 6) &&
(QPLL1_REFCLK_DIV_REG != 8) &&
(QPLL1_REFCLK_DIV_REG != 10) &&
(QPLL1_REFCLK_DIV_REG != 12) &&
(QPLL1_REFCLK_DIV_REG != 16) &&
(QPLL1_REFCLK_DIV_REG != 20))) begin
$display("Error: [Unisim %s-194] QPLL1_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 2, 1, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, QPLL1_REFCLK_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(SIM_MODE != "FAST")) begin
$display("Error: [Unisim %s-218] SIM_MODE attribute is set to %s. Legal values for this attribute are FAST. Instance: %m", MODULE_NAME, SIM_MODE);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_RESET_SPEEDUP != "TRUE") &&
(SIM_RESET_SPEEDUP != "FALSE"))) begin
$display("Error: [Unisim %s-219] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_VERSION != 2) &&
(SIM_VERSION != 1) &&
(SIM_VERSION != 3))) begin
$display("Error: [Unisim %s-220] SIM_VERSION attribute is set to %d. Legal values for this attribute are 2, 1 or 3. Instance: %m", MODULE_NAME, SIM_VERSION);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
assign PMASCANCLK_in = 8'b11111111; // tie off
assign PMASCANENB_in = 1'b1; // tie off
assign PMASCANIN_in = 8'b11111111; // tie off
assign QDPMASCANMODEB_in = 1'b1; // tie off
assign QDPMASCANRSTEN_in = 1'b1; // tie off
assign RXRECCLK_in = 4'b1111; // tie off
SIP_GTYE3_COMMON #(
.SIM_MODE (SIM_MODE),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_VERSION (SIM_VERSION)
) SIP_GTYE3_COMMON_INST (
.AEN_BGBS0 (AEN_BGBS0_REG),
.AEN_BGBS1 (AEN_BGBS1_REG),
.AEN_MASTER0 (AEN_MASTER0_REG),
.AEN_MASTER1 (AEN_MASTER1_REG),
.AEN_PD0 (AEN_PD0_REG),
.AEN_PD1 (AEN_PD1_REG),
.AEN_QPLL0 (AEN_QPLL0_REG),
.AEN_QPLL1 (AEN_QPLL1_REG),
.AEN_REFCLK0 (AEN_REFCLK0_REG),
.AEN_REFCLK1 (AEN_REFCLK1_REG),
.AEN_RESET0 (AEN_RESET0_REG),
.AEN_RESET1 (AEN_RESET1_REG),
.AEN_SDMDATA0 (AEN_SDMDATA0_REG),
.AEN_SDMDATA1 (AEN_SDMDATA1_REG),
.AEN_SDMRESET0 (AEN_SDMRESET0_REG),
.AEN_SDMRESET1 (AEN_SDMRESET1_REG),
.AEN_SDMWIDTH0 (AEN_SDMWIDTH0_REG),
.AEN_SDMWIDTH1 (AEN_SDMWIDTH1_REG),
.AQDMUXSEL1 (AQDMUXSEL1_REG),
.AVCC_SENSE_SEL (AVCC_SENSE_SEL_REG),
.AVTT_SENSE_SEL (AVTT_SENSE_SEL_REG),
.A_BGMONITOREN (A_BGMONITOREN_REG),
.A_BGPD (A_BGPD_REG),
.A_GTREFCLKPD0 (A_GTREFCLKPD0_REG),
.A_GTREFCLKPD1 (A_GTREFCLKPD1_REG),
.A_QPLL0LOCKEN (A_QPLL0LOCKEN_REG),
.A_QPLL0PD (A_QPLL0PD_REG),
.A_QPLL0RESET (A_QPLL0RESET_REG),
.A_QPLL1LOCKEN (A_QPLL1LOCKEN_REG),
.A_QPLL1PD (A_QPLL1PD_REG),
.A_QPLL1RESET (A_QPLL1RESET_REG),
.A_SDM0DATA1_0 (A_SDM0DATA1_0_REG),
.A_SDM0DATA1_1 (A_SDM0DATA1_1_REG),
.A_SDM1DATA1_0 (A_SDM1DATA1_0_REG),
.A_SDM1DATA1_1 (A_SDM1DATA1_1_REG),
.A_SDMRESET0 (A_SDMRESET0_REG),
.A_SDMRESET1 (A_SDMRESET1_REG),
.BIAS_CFG0 (BIAS_CFG0_REG),
.BIAS_CFG1 (BIAS_CFG1_REG),
.BIAS_CFG2 (BIAS_CFG2_REG),
.BIAS_CFG3 (BIAS_CFG3_REG),
.BIAS_CFG4 (BIAS_CFG4_REG),
.BIAS_CFG_RSVD (BIAS_CFG_RSVD_REG),
.COMMON_AMUX_SEL0 (COMMON_AMUX_SEL0_REG),
.COMMON_AMUX_SEL1 (COMMON_AMUX_SEL1_REG),
.COMMON_CFG0 (COMMON_CFG0_REG),
.COMMON_CFG1 (COMMON_CFG1_REG),
.COMMON_INSTANTIATED (COMMON_INSTANTIATED_REG),
.POR_CFG (POR_CFG_REG),
.PPF0_CFG (PPF0_CFG_REG),
.PPF1_CFG (PPF1_CFG_REG),
.QPLL0CLKOUT_RATE (QPLL0CLKOUT_RATE_REG),
.QPLL0_AMONITOR_SEL (QPLL0_AMONITOR_SEL_REG),
.QPLL0_CFG0 (QPLL0_CFG0_REG),
.QPLL0_CFG1 (QPLL0_CFG1_REG),
.QPLL0_CFG1_G3 (QPLL0_CFG1_G3_REG),
.QPLL0_CFG2 (QPLL0_CFG2_REG),
.QPLL0_CFG2_G3 (QPLL0_CFG2_G3_REG),
.QPLL0_CFG3 (QPLL0_CFG3_REG),
.QPLL0_CFG4 (QPLL0_CFG4_REG),
.QPLL0_CP (QPLL0_CP_REG),
.QPLL0_CP_G3 (QPLL0_CP_G3_REG),
.QPLL0_FBDIV (QPLL0_FBDIV_REG),
.QPLL0_FBDIV_G3 (QPLL0_FBDIV_G3_REG),
.QPLL0_INIT_CFG0 (QPLL0_INIT_CFG0_REG),
.QPLL0_INIT_CFG1 (QPLL0_INIT_CFG1_REG),
.QPLL0_LOCK_CFG (QPLL0_LOCK_CFG_REG),
.QPLL0_LOCK_CFG_G3 (QPLL0_LOCK_CFG_G3_REG),
.QPLL0_LPF (QPLL0_LPF_REG),
.QPLL0_LPF_G3 (QPLL0_LPF_G3_REG),
.QPLL0_REFCLK_DIV (QPLL0_REFCLK_DIV_REG),
.QPLL0_SDM_CFG0 (QPLL0_SDM_CFG0_REG),
.QPLL0_SDM_CFG1 (QPLL0_SDM_CFG1_REG),
.QPLL0_SDM_CFG2 (QPLL0_SDM_CFG2_REG),
.QPLL1CLKOUT_RATE (QPLL1CLKOUT_RATE_REG),
.QPLL1_AMONITOR_SEL (QPLL1_AMONITOR_SEL_REG),
.QPLL1_CFG0 (QPLL1_CFG0_REG),
.QPLL1_CFG1 (QPLL1_CFG1_REG),
.QPLL1_CFG1_G3 (QPLL1_CFG1_G3_REG),
.QPLL1_CFG2 (QPLL1_CFG2_REG),
.QPLL1_CFG2_G3 (QPLL1_CFG2_G3_REG),
.QPLL1_CFG3 (QPLL1_CFG3_REG),
.QPLL1_CFG4 (QPLL1_CFG4_REG),
.QPLL1_CP (QPLL1_CP_REG),
.QPLL1_CP_G3 (QPLL1_CP_G3_REG),
.QPLL1_FBDIV (QPLL1_FBDIV_REG),
.QPLL1_FBDIV_G3 (QPLL1_FBDIV_G3_REG),
.QPLL1_INIT_CFG0 (QPLL1_INIT_CFG0_REG),
.QPLL1_INIT_CFG1 (QPLL1_INIT_CFG1_REG),
.QPLL1_LOCK_CFG (QPLL1_LOCK_CFG_REG),
.QPLL1_LOCK_CFG_G3 (QPLL1_LOCK_CFG_G3_REG),
.QPLL1_LPF (QPLL1_LPF_REG),
.QPLL1_LPF_G3 (QPLL1_LPF_G3_REG),
.QPLL1_REFCLK_DIV (QPLL1_REFCLK_DIV_REG),
.QPLL1_SDM_CFG0 (QPLL1_SDM_CFG0_REG),
.QPLL1_SDM_CFG1 (QPLL1_SDM_CFG1_REG),
.QPLL1_SDM_CFG2 (QPLL1_SDM_CFG2_REG),
.RCALSAP_TESTEN (RCALSAP_TESTEN_REG),
.RCAL_APROBE (RCAL_APROBE_REG),
.REFCLK0_EN_DC_COUP (REFCLK0_EN_DC_COUP_REG),
.REFCLK0_VCM_HIGH (REFCLK0_VCM_HIGH_REG),
.REFCLK0_VCM_LOW (REFCLK0_VCM_LOW_REG),
.REFCLK1_EN_DC_COUP (REFCLK1_EN_DC_COUP_REG),
.REFCLK1_VCM_HIGH (REFCLK1_VCM_HIGH_REG),
.REFCLK1_VCM_LOW (REFCLK1_VCM_LOW_REG),
.RSVD_ATTR0 (RSVD_ATTR0_REG),
.RSVD_ATTR1 (RSVD_ATTR1_REG),
.RSVD_ATTR2 (RSVD_ATTR2_REG),
.RSVD_ATTR3 (RSVD_ATTR3_REG),
.RXRECCLKOUT0_SEL (RXRECCLKOUT0_SEL_REG),
.RXRECCLKOUT1_SEL (RXRECCLKOUT1_SEL_REG),
.SARC_EN (SARC_EN_REG),
.SARC_SEL (SARC_SEL_REG),
.SDM0INITSEED0_0 (SDM0INITSEED0_0_REG),
.SDM0INITSEED0_1 (SDM0INITSEED0_1_REG),
.SDM1INITSEED0_0 (SDM1INITSEED0_0_REG),
.SDM1INITSEED0_1 (SDM1INITSEED0_1_REG),
.VCCAUX_SENSE_SEL (VCCAUX_SENSE_SEL_REG),
.DRPDO (DRPDO_out),
.DRPRDY (DRPRDY_out),
.PMARSVDOUT0 (PMARSVDOUT0_out),
.PMARSVDOUT1 (PMARSVDOUT1_out),
.PMASCANOUT (PMASCANOUT_out),
.QPLL0FBCLKLOST (QPLL0FBCLKLOST_out),
.QPLL0LOCK (QPLL0LOCK_out),
.QPLL0OUTCLK (QPLL0OUTCLK_out),
.QPLL0OUTREFCLK (QPLL0OUTREFCLK_out),
.QPLL0REFCLKLOST (QPLL0REFCLKLOST_out),
.QPLL1FBCLKLOST (QPLL1FBCLKLOST_out),
.QPLL1LOCK (QPLL1LOCK_out),
.QPLL1OUTCLK (QPLL1OUTCLK_out),
.QPLL1OUTREFCLK (QPLL1OUTREFCLK_out),
.QPLL1REFCLKLOST (QPLL1REFCLKLOST_out),
.QPLLDMONITOR0 (QPLLDMONITOR0_out),
.QPLLDMONITOR1 (QPLLDMONITOR1_out),
.REFCLKOUTMONITOR0 (REFCLKOUTMONITOR0_out),
.REFCLKOUTMONITOR1 (REFCLKOUTMONITOR1_out),
.RXRECCLK0_SEL (RXRECCLK0_SEL_out),
.RXRECCLK1_SEL (RXRECCLK1_SEL_out),
.SARCCLK (SARCCLK_out),
.SDM0FINALOUT (SDM0FINALOUT_out),
.SDM0TESTDATA (SDM0TESTDATA_out),
.SDM1FINALOUT (SDM1FINALOUT_out),
.SDM1TESTDATA (SDM1TESTDATA_out),
.BGBYPASSB (BGBYPASSB_in),
.BGMONITORENB (BGMONITORENB_in),
.BGPDB (BGPDB_in),
.BGRCALOVRD (BGRCALOVRD_in),
.BGRCALOVRDENB (BGRCALOVRDENB_in),
.DRPADDR (DRPADDR_in),
.DRPCLK (DRPCLK_in),
.DRPDI (DRPDI_in),
.DRPEN (DRPEN_in),
.DRPWE (DRPWE_in),
.GTGREFCLK0 (GTGREFCLK0_in),
.GTGREFCLK1 (GTGREFCLK1_in),
.GTNORTHREFCLK00 (GTNORTHREFCLK00_in),
.GTNORTHREFCLK01 (GTNORTHREFCLK01_in),
.GTNORTHREFCLK10 (GTNORTHREFCLK10_in),
.GTNORTHREFCLK11 (GTNORTHREFCLK11_in),
.GTREFCLK00 (GTREFCLK00_in),
.GTREFCLK01 (GTREFCLK01_in),
.GTREFCLK10 (GTREFCLK10_in),
.GTREFCLK11 (GTREFCLK11_in),
.GTSOUTHREFCLK00 (GTSOUTHREFCLK00_in),
.GTSOUTHREFCLK01 (GTSOUTHREFCLK01_in),
.GTSOUTHREFCLK10 (GTSOUTHREFCLK10_in),
.GTSOUTHREFCLK11 (GTSOUTHREFCLK11_in),
.PMARSVD0 (PMARSVD0_in),
.PMARSVD1 (PMARSVD1_in),
.PMASCANCLK (PMASCANCLK_in),
.PMASCANENB (PMASCANENB_in),
.PMASCANIN (PMASCANIN_in),
.QDPMASCANMODEB (QDPMASCANMODEB_in),
.QDPMASCANRSTEN (QDPMASCANRSTEN_in),
.QPLL0CLKRSVD0 (QPLL0CLKRSVD0_in),
.QPLL0LOCKDETCLK (QPLL0LOCKDETCLK_in),
.QPLL0LOCKEN (QPLL0LOCKEN_in),
.QPLL0PD (QPLL0PD_in),
.QPLL0REFCLKSEL (QPLL0REFCLKSEL_in),
.QPLL0RESET (QPLL0RESET_in),
.QPLL1CLKRSVD0 (QPLL1CLKRSVD0_in),
.QPLL1LOCKDETCLK (QPLL1LOCKDETCLK_in),
.QPLL1LOCKEN (QPLL1LOCKEN_in),
.QPLL1PD (QPLL1PD_in),
.QPLL1REFCLKSEL (QPLL1REFCLKSEL_in),
.QPLL1RESET (QPLL1RESET_in),
.QPLLRSVD1 (QPLLRSVD1_in),
.QPLLRSVD2 (QPLLRSVD2_in),
.QPLLRSVD3 (QPLLRSVD3_in),
.QPLLRSVD4 (QPLLRSVD4_in),
.RCALENB (RCALENB_in),
.RXRECCLK (RXRECCLK_in),
.SDM0DATA (SDM0DATA_in),
.SDM0RESET (SDM0RESET_in),
.SDM0WIDTH (SDM0WIDTH_in),
.SDM1DATA (SDM1DATA_in),
.SDM1RESET (SDM1RESET_in),
.SDM1WIDTH (SDM1WIDTH_in),
.GSR (glblGSR)
);
specify
(DRPCLK => DRPDO[0]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[10]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[11]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[12]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[13]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[14]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[15]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[1]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[2]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[3]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[4]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[5]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[6]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[7]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[8]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[9]) = (100:100:100, 100:100:100);
(DRPCLK => DRPRDY) = (100:100:100, 100:100:100);
(DRPCLK => RXRECCLK0_SEL[0]) = (100:100:100, 100:100:100);
(DRPCLK => RXRECCLK0_SEL[1]) = (100:100:100, 100:100:100);
(GTGREFCLK0 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0);
(GTGREFCLK1 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0);
(GTNORTHREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0);
(GTNORTHREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0);
(GTNORTHREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0);
(GTNORTHREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0);
(GTREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0);
(GTREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0);
(GTREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0);
(GTREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK00 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK01 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK10 => QPLL0OUTREFCLK) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK11 => QPLL1OUTREFCLK) = (0:0:0, 0:0:0);
// (QPLL0OUTREFCLK => REFCLKOUTMONITOR0) = (0:0:0, 0:0:0); // error prop output to output
// (QPLL1OUTREFCLK => REFCLKOUTMONITOR1) = (0:0:0, 0:0:0); // error prop output to output
`ifdef XIL_TIMING
$period (negedge DRPCLK, 0:0:0, notifier);
$period (posedge DRPCLK, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay);
$setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]);
$setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay);
$width (negedge DRPCLK, 0:0:0, 0, notifier);
$width (posedge DRPCLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
`include "common.vh"
`timescale 1ns/10ps
module Gpio(clk, strobe, rw, reset, addr, data_i, data_o, gpio);
// four registers
// 0 : enable (1 for enable)
// 1 : read-write (1 for write)
// 2 : read state (1 for high)
// 3 : write state (1 for high)
parameter COUNT = 32;
localparam SIZE = 4;
input wire clk, strobe, rw, reset;
input wire[31:0] addr, data_i;
output reg [31:0] data_o;
inout wire[COUNT-1:0] gpio;
localparam EN = 0, RW = 1, RS = 2, WS = 3;
reg [COUNT-1:0] state[SIZE-1:0];
integer k;
initial for (k = 0; k < SIZE; k = k + 1) state[k] = 0;
genvar i;
generate for (i = 0; i < COUNT; i = i + 1)
assign gpio[i] = (state[EN][i] & state[RW][i]) ? state[WS][i] : 1'bz;
endgenerate
always @(posedge clk) begin
state[RS] <= state[EN] & ~state[RW] & gpio;
if (reset) begin
for (k = 0; k < SIZE; k = k + 1)
state[k] <= 0;
end else if (strobe) begin
if (rw)
state[addr] <= data_i[COUNT-1:0];
else
data_o <= {{32-COUNT{1'b0}},state[addr]};
end
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon Jan 26 10:14:21 2015
// Host : xilinxvivadotools running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/ece532/testing/ov7670/nexys4ddr_ov7670/nexys4ddr_ov7670.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_funcsim.v
// Design : clk_wiz_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_wiz_0
(clk_in1,
clk_out1,
clk_out2);
input clk_in1;
output clk_out1;
output clk_out2;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire clk_out2;
clk_wiz_0clk_wiz_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.clk_out2(clk_out2));
endmodule
(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *)
module clk_wiz_0clk_wiz_0_clk_wiz
(clk_in1,
clk_out1,
clk_out2);
input clk_in1;
output clk_out1;
output clk_out2;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_in1_clk_wiz_0;
wire clk_out1;
wire clk_out1_clk_wiz_0;
wire clk_out2;
wire clk_out2_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfbout_clk_wiz_0;
wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED;
wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_wiz_0),
.O(clkfbout_buf_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_clk_wiz_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_out2_clk_wiz_0),
.O(clk_out2));
(* BOX_TYPE = "PRIMITIVE" *)
PLLE2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(8),
.CLKFBOUT_PHASE(0.000000),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE(16),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT1_DIVIDE(32),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.STARTUP_WAIT("FALSE"))
plle2_adv_inst
(.CLKFBIN(clkfbout_buf_clk_wiz_0),
.CLKFBOUT(clkfbout_clk_wiz_0),
.CLKIN1(clk_in1_clk_wiz_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKOUT0(clk_out1_clk_wiz_0),
.CLKOUT1(clk_out2_clk_wiz_0),
.CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module tlu_controller_fsm #(
parameter DIVISOR = 8,
parameter TLU_TRIGGER_MAX_CLOCK_CYCLES = 17,
parameter TIMESTAMP_N_OF_BIT = 32
) (
input wire RESET,
input wire TRIGGER_CLK,
output reg TRIGGER_DATA_WRITE,
output reg [31:0] TRIGGER_DATA,
output reg FIFO_PREEMPT_REQ,
input wire FIFO_ACKNOWLEDGE,
output reg [TIMESTAMP_N_OF_BIT-1:0] TIMESTAMP,
output reg [31:0] TIMESTAMP_DATA,
output reg [31:0] TLU_TRIGGER_NUMBER_DATA,
output reg [31:0] TRIGGER_COUNTER_DATA,
input wire [31:0] TRIGGER_COUNTER,
input wire CONF_EXT_TIMESTAMP,
input wire [TIMESTAMP_N_OF_BIT-1:0] EXT_TIMESTAMP,
input wire [1:0] TRIGGER_MODE,
input wire [7:0] TRIGGER_THRESHOLD,
input wire TRIGGER,
input wire TRIGGER_VETO,
input wire TRIGGER_ENABLE,
input wire TRIGGER_ACKNOWLEDGE,
output reg TRIGGER_ACCEPTED_FLAG,
input wire TIMESTAMP_RESET_FLAG,
input wire [7:0] TLU_TRIGGER_LOW_TIME_OUT,
// input wire [4:0] TLU_TRIGGER_CLOCK_CYCLES,
input wire [7:0] TLU_TRIGGER_DATA_DELAY,
input wire TLU_TRIGGER_DATA_MSB_FIRST,
input wire TLU_ENABLE_VETO,
input wire TLU_RESET_FLAG,
input wire [1:0] CONF_DATA_FORMAT,
output reg TLU_BUSY,
output reg TLU_CLOCK_ENABLE,
output reg TLU_ASSERT_VETO,
input wire [7:0] TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES,
input wire [7:0] TLU_HANDSHAKE_BUSY_VETO_WAIT_CYCLES,
output wire TLU_TRIGGER_LOW_TIMEOUT_ERROR_FLAG, // error flag
output wire TLU_TRIGGER_ACCEPT_ERROR_FLAG // error flag
);
//assign TRIGGER_DATA[31:0] = (WRITE_TIMESTAMP==1'b1) ? {1'b1, TIMESTAMP_DATA[30:0]} : ((TRIGGER_MODE==2'b11) ? {1'b1, TLU_TRIGGER_NUMBER_DATA[30:0]} : ({1'b1, TRIGGER_COUNTER_DATA[30:0]}));
always @(*)
begin
if(TRIGGER_MODE == 2'b11) // TLU trigger number
begin
if(CONF_DATA_FORMAT == 2'b01) // time stamp only
TRIGGER_DATA[31:0] = {1'b1, TIMESTAMP_DATA[30:0]};
else if(CONF_DATA_FORMAT == 2'b10) // combined
TRIGGER_DATA[31:0] = {1'b1, TIMESTAMP_DATA[14:0], TLU_TRIGGER_NUMBER_DATA[15:0]};
else
TRIGGER_DATA[31:0] = {1'b1, TLU_TRIGGER_NUMBER_DATA[30:0]};
end
else // internally generated trigger number
begin
if(CONF_DATA_FORMAT == 2'b01) // time stamp only
TRIGGER_DATA[31:0] = {1'b1, TIMESTAMP_DATA[30:0]};
else if(CONF_DATA_FORMAT == 2'b10) // combined
TRIGGER_DATA[31:0] = {1'b1, TIMESTAMP_DATA[14:0], TRIGGER_COUNTER_DATA[15:0]};
else
TRIGGER_DATA[31:0] = {1'b1, TRIGGER_COUNTER_DATA[30:0]};
end
end
// shift register, serial to parallel, length of TLU_TRIGGER_MAX_CLOCK_CYCLES
reg [((TLU_TRIGGER_MAX_CLOCK_CYCLES+1)*DIVISOR)-1:0] tlu_data_sr;
always @(posedge TRIGGER_CLK)
begin
if (RESET | TRIGGER_ACCEPTED_FLAG)
tlu_data_sr <= 0;
else
tlu_data_sr[((TLU_TRIGGER_MAX_CLOCK_CYCLES)*DIVISOR)-1:0] <= {tlu_data_sr[((TLU_TRIGGER_MAX_CLOCK_CYCLES)*DIVISOR)-2:0], TRIGGER};
end
// Trigger flag
reg TRIGGER_FF;
always @(posedge TRIGGER_CLK)
TRIGGER_FF <= TRIGGER;
wire TRIGGER_FLAG;
assign TRIGGER_FLAG = ~TRIGGER_FF & TRIGGER;
// Trigger enable flag
reg TRIGGER_ENABLE_FF;
always @(posedge TRIGGER_CLK)
TRIGGER_ENABLE_FF <= TRIGGER_ENABLE;
wire TRIGGER_ENABLE_FLAG;
assign TRIGGER_ENABLE_FLAG = ~TRIGGER_ENABLE_FF & TRIGGER_ENABLE;
// FSM
// workaround for TLU bug where short szintillator pulses lead to glitches on TLU trigger
reg TRIGGER_ACCEPT;
reg TLU_TRIGGER_HANDSHAKE_ACCEPT;
reg [7:0] counter_trigger_high;
// additional wait cycles for TLU veto after TLU handshake
reg [7:0] counter_tlu_handshake_veto;
// other
reg [7:0] counter_trigger_low_time_out;
integer counter_tlu_clock;
integer counter_sr_wait_cycles;
integer n; // for for-loop
reg TRIGGER_ACKNOWLEDGED, FIFO_ACKNOWLEDGED;
reg TLU_TRIGGER_LOW_TIMEOUT_ERROR;
reg TLU_TRIGGER_ACCEPT_ERROR;
reg TLU_TRIGGER_LOW_TIMEOUT_ERROR_FF;
always @(posedge TRIGGER_CLK)
TLU_TRIGGER_LOW_TIMEOUT_ERROR_FF <= TLU_TRIGGER_LOW_TIMEOUT_ERROR;
assign TLU_TRIGGER_LOW_TIMEOUT_ERROR_FLAG = ~TLU_TRIGGER_LOW_TIMEOUT_ERROR_FF & TLU_TRIGGER_LOW_TIMEOUT_ERROR;
reg TLU_TRIGGER_ACCEPT_ERROR_FF;
always @(posedge TRIGGER_CLK)
TLU_TRIGGER_ACCEPT_ERROR_FF <= TLU_TRIGGER_ACCEPT_ERROR;
assign TLU_TRIGGER_ACCEPT_ERROR_FLAG = ~TLU_TRIGGER_ACCEPT_ERROR_FF & TLU_TRIGGER_ACCEPT_ERROR;
// standard state encoding
reg [2:0] state;
reg [2:0] next;
localparam [2:0]
IDLE = 3'b000,
SEND_COMMAND = 3'b001,
SEND_COMMAND_WAIT_FOR_TRIGGER_LOW = 3'b010,
SEND_TLU_CLOCK = 3'b011,
WAIT_BEFORE_LATCH = 3'b100,
LATCH_DATA = 3'b101,
WAIT_FOR_TLU_DATA_SAVED_CMD_READY = 3'b110;
// sequential always block, non-blocking assignments
always @(posedge TRIGGER_CLK)
begin
if (RESET) state <= IDLE; // get D-FF for state
else state <= next;
end
// combinational always block, blocking assignments
always @(state or TRIGGER_ACKNOWLEDGE or TRIGGER_ACKNOWLEDGED or FIFO_ACKNOWLEDGE or FIFO_ACKNOWLEDGED or TRIGGER_ENABLE or TRIGGER_ENABLE_FLAG or TRIGGER_FLAG or TRIGGER or TRIGGER_MODE or TLU_TRIGGER_LOW_TIMEOUT_ERROR or counter_tlu_clock /*or TLU_TRIGGER_CLOCK_CYCLES*/ or counter_sr_wait_cycles or counter_trigger_high or counter_tlu_handshake_veto or counter_trigger_low_time_out or TLU_TRIGGER_DATA_DELAY or TRIGGER_VETO or TRIGGER_ACCEPT or TLU_TRIGGER_HANDSHAKE_ACCEPT or TRIGGER_THRESHOLD or TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES or TLU_TRIGGER_MAX_CLOCK_CYCLES or DIVISOR)
begin
case (state)
IDLE:
begin
if ((TRIGGER_MODE == 2'b00 || TRIGGER_MODE == 2'b01)
&& (TRIGGER_ACKNOWLEDGE == 1'b0)
&& (FIFO_ACKNOWLEDGE == 1'b0)
&& (TRIGGER_ENABLE == 1'b1)
&& (TRIGGER_VETO == 1'b0)
&& ((TRIGGER_FLAG == 1'b1 && TRIGGER_THRESHOLD == 0) // trigger threshold disabled
|| (TRIGGER_ACCEPT == 1'b1 && TRIGGER_THRESHOLD != 0) // trigger threshold enabled
)
)
next = SEND_COMMAND;
else if ((TRIGGER_MODE == 2'b10 || TRIGGER_MODE == 2'b11)
&& (TRIGGER_ACKNOWLEDGE == 1'b0)
&& (FIFO_ACKNOWLEDGE == 1'b0)
&& (TRIGGER_ENABLE == 1'b1)
&& ((TRIGGER == 1'b1 && TRIGGER_ENABLE_FLAG == 1'b1) // workaround TLU trigger high when FSM enabled
|| (TRIGGER_FLAG == 1'b1 && TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES == 0) // trigger accept counter disabled
|| (TLU_TRIGGER_HANDSHAKE_ACCEPT == 1'b1 && TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES != 0) // trigger accept counter enabled
)
)
next = SEND_COMMAND_WAIT_FOR_TRIGGER_LOW;
else
next = IDLE;
end
SEND_COMMAND:
begin
next = LATCH_DATA; // do not wait for trigger becoming low
end
SEND_COMMAND_WAIT_FOR_TRIGGER_LOW:
begin
if (TRIGGER_MODE == 2'b10 && (TRIGGER == 1'b0 || TLU_TRIGGER_LOW_TIMEOUT_ERROR == 1'b1))
next = LATCH_DATA; // wait for trigger low
else if (TRIGGER_MODE == 2'b11 && (TRIGGER == 1'b0 || TLU_TRIGGER_LOW_TIMEOUT_ERROR == 1'b1))
next = SEND_TLU_CLOCK; // wait for trigger low
else
next = SEND_COMMAND_WAIT_FOR_TRIGGER_LOW;
end
SEND_TLU_CLOCK:
begin
//if (TLU_TRIGGER_CLOCK_CYCLES == 5'b0) // send 32 clock cycles
if (counter_tlu_clock >= TLU_TRIGGER_MAX_CLOCK_CYCLES * DIVISOR)
next = WAIT_BEFORE_LATCH;
else
next = SEND_TLU_CLOCK;
/*
else
if (counter_tlu_clock == TLU_TRIGGER_CLOCK_CYCLES * DIVISOR)
next = WAIT_BEFORE_LATCH;
else
next = SEND_TLU_CLOCK;
*/
end
WAIT_BEFORE_LATCH:
begin
if (counter_sr_wait_cycles == TLU_TRIGGER_DATA_DELAY + 5) // wait at least 3 (2 + next state) clock cycles for sync of the signal
next = LATCH_DATA;
else
next = WAIT_BEFORE_LATCH;
end
LATCH_DATA:
begin
next = WAIT_FOR_TLU_DATA_SAVED_CMD_READY;
end
WAIT_FOR_TLU_DATA_SAVED_CMD_READY:
begin
if (TRIGGER_ACKNOWLEDGED == 1'b1 && FIFO_ACKNOWLEDGED == 1'b1)
next = IDLE;
else
next = WAIT_FOR_TLU_DATA_SAVED_CMD_READY;
end
// inferring FF
default:
begin
next = IDLE;
end
endcase
end
// sequential always block, non-blocking assignments, registered outputs
always @(posedge TRIGGER_CLK)
begin
if (RESET) // get D-FF
begin
FIFO_PREEMPT_REQ <= 1'b0;
TRIGGER_DATA_WRITE <= 1'b0;
TLU_TRIGGER_NUMBER_DATA <= 32'b0;
TIMESTAMP_DATA <= 32'b0;
TRIGGER_COUNTER_DATA <= 32'b0;
TLU_ASSERT_VETO <= 1'b0;
TLU_BUSY <= 1'b0;
TLU_CLOCK_ENABLE <= 1'b0;
counter_trigger_high <= 8'b0;
counter_tlu_handshake_veto <= TLU_HANDSHAKE_BUSY_VETO_WAIT_CYCLES;
TRIGGER_ACCEPT <= 1'b0;
TLU_TRIGGER_HANDSHAKE_ACCEPT <= 1'b0;
counter_trigger_low_time_out <= 8'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TLU_TRIGGER_LOW_TIMEOUT_ERROR <= 1'b0;
TLU_TRIGGER_ACCEPT_ERROR <= 1'b0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
TRIGGER_ACKNOWLEDGED <= 1'b0;
FIFO_ACKNOWLEDGED <= 1'b0;
end
else
begin
FIFO_PREEMPT_REQ <= 1'b0;
TRIGGER_DATA_WRITE <= 1'b0;
TLU_TRIGGER_NUMBER_DATA <= TLU_TRIGGER_NUMBER_DATA;
TIMESTAMP_DATA <= TIMESTAMP_DATA;
TRIGGER_COUNTER_DATA <= TRIGGER_COUNTER_DATA;
TLU_ASSERT_VETO <= 1'b0;
TLU_BUSY <= 1'b0;
TLU_CLOCK_ENABLE <= 1'b0;
counter_trigger_high <= 8'b0;
counter_tlu_handshake_veto <= TLU_HANDSHAKE_BUSY_VETO_WAIT_CYCLES;
TRIGGER_ACCEPT <= 1'b0;
TLU_TRIGGER_HANDSHAKE_ACCEPT <= 1'b0;
counter_trigger_low_time_out <= 8'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TLU_TRIGGER_LOW_TIMEOUT_ERROR <= 1'b0;
TLU_TRIGGER_ACCEPT_ERROR <= 1'b0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
TRIGGER_ACKNOWLEDGED <= TRIGGER_ACKNOWLEDGED;
FIFO_ACKNOWLEDGED <= FIFO_ACKNOWLEDGED;
case (next)
IDLE:
begin
if (TRIGGER_FLAG && TRIGGER_THRESHOLD != 0)
if (CONF_EXT_TIMESTAMP == 1'b1)
TIMESTAMP_DATA <= EXT_TIMESTAMP[31:0]; // timestamp from external source
else
TIMESTAMP_DATA <= TIMESTAMP[31:0];
if (TRIGGER_ENABLE == 1'b1
&& TRIGGER == 1'b1
&& (((TRIGGER_MODE == 2'b10 || TRIGGER_MODE == 2'b11) && (counter_trigger_high != 0 && TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES != 0))
|| ((TRIGGER_MODE == 2'b00 || TRIGGER_MODE == 2'b01) && (counter_trigger_high != 0 && TRIGGER_THRESHOLD != 0))
)
)
FIFO_PREEMPT_REQ <= 1'b1;
else
FIFO_PREEMPT_REQ <= 1'b0;
TRIGGER_DATA_WRITE <= 1'b0;
if ((TRIGGER_ENABLE == 1'b0 || (TRIGGER_ENABLE == 1'b1 && TRIGGER_VETO == 1'b1 && counter_tlu_handshake_veto == 0)) && TLU_ENABLE_VETO == 1'b1 && (TRIGGER_MODE == 2'b10 || TRIGGER_MODE == 2'b11))
TLU_ASSERT_VETO <= 1'b1; // assert only outside Trigger/Busy handshake
else
TLU_ASSERT_VETO <= 1'b0;
// if (TRIGGER_ENABLE == 1'b0)
// TLU_BUSY <= 1'b1; // FIXME: temporary fix for accepting first TLU trigger
// else
// TLU_BUSY <= 1'b0;
TLU_BUSY <= 1'b0;
TLU_CLOCK_ENABLE <= 1'b0;
if (TRIGGER_ENABLE == 1'b1 && counter_trigger_high != 8'b1111_1111 && ((counter_trigger_high > 0 && TRIGGER == 1'b1) || (counter_trigger_high == 0 && TRIGGER_FLAG == 1'b1)))
counter_trigger_high <= counter_trigger_high + 1;
else if (TRIGGER_ENABLE == 1'b1 && counter_trigger_high == 8'b1111_1111 && TRIGGER == 1'b1)
counter_trigger_high <= counter_trigger_high;
else
counter_trigger_high <= 8'b0;
if (TRIGGER_ENABLE == 1'b0)
counter_tlu_handshake_veto <= 8'b0;
else if (counter_tlu_handshake_veto == 8'b0)
counter_tlu_handshake_veto <= counter_tlu_handshake_veto;
else
counter_tlu_handshake_veto <= counter_tlu_handshake_veto - 1;
if (counter_trigger_high >= TRIGGER_THRESHOLD && TRIGGER_THRESHOLD != 0)
TRIGGER_ACCEPT <= 1'b1;
else
TRIGGER_ACCEPT <= 1'b0;
if (counter_trigger_high >= TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES && TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES != 0)
TLU_TRIGGER_HANDSHAKE_ACCEPT <= 1'b1;
else
TLU_TRIGGER_HANDSHAKE_ACCEPT <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
TRIGGER_ACKNOWLEDGED <= 1'b0;
FIFO_ACKNOWLEDGED <= 1'b0;
end
SEND_COMMAND:
begin
// send flag at beginning of state
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
// get timestamp closest to the trigger
if (state != next && TRIGGER_THRESHOLD == 0) begin
if (CONF_EXT_TIMESTAMP == 1'b1)
TIMESTAMP_DATA <= EXT_TIMESTAMP[31:0]; // timestamp from external source
else
TIMESTAMP_DATA <= TIMESTAMP[31:0];
end
if (state != next) begin
TRIGGER_COUNTER_DATA <= TRIGGER_COUNTER;
end
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
// send flag at beginning of state
if (state != next)
TRIGGER_ACCEPTED_FLAG <= 1'b1;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
end
SEND_COMMAND_WAIT_FOR_TRIGGER_LOW:
begin
// send flag at beginning of state
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
// get timestamp closest to the trigger
if (state != next && TRIGGER_THRESHOLD == 0) begin
if (CONF_EXT_TIMESTAMP == 1'b1)
TIMESTAMP_DATA <= EXT_TIMESTAMP[31:0]; // timestamp from external source
else
TIMESTAMP_DATA <= TIMESTAMP[31:0];
end
if (state != next) begin
TRIGGER_COUNTER_DATA <= TRIGGER_COUNTER;
end
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b0;
counter_trigger_low_time_out <= counter_trigger_low_time_out + 1;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
if ((counter_trigger_low_time_out >= TLU_TRIGGER_LOW_TIME_OUT) && (TLU_TRIGGER_LOW_TIME_OUT != 8'b0))
TLU_TRIGGER_LOW_TIMEOUT_ERROR <= 1'b1;
else
TLU_TRIGGER_LOW_TIMEOUT_ERROR <= 1'b0;
if (state != next)
TRIGGER_ACCEPTED_FLAG <= 1'b1;
else
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
end
SEND_TLU_CLOCK:
begin
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b1;
counter_tlu_clock <= counter_tlu_clock + 1;
counter_sr_wait_cycles <= 0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
if (state != next && TRIGGER == 1'b0 && counter_trigger_low_time_out < 4) // 4 clocks cycles = 1 for output + 3 for sync
TLU_TRIGGER_ACCEPT_ERROR <= 1'b1;
end
WAIT_BEFORE_LATCH:
begin
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= counter_sr_wait_cycles + 1;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
end
LATCH_DATA:
begin
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b1;
if (TLU_TRIGGER_DATA_MSB_FIRST == 1'b0) begin // reverse bit order
for ( n=0 ; n < TLU_TRIGGER_MAX_CLOCK_CYCLES ; n = n+1 ) begin
if (n > 31-1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((TLU_TRIGGER_MAX_CLOCK_CYCLES-n)*DIVISOR)-1];
end
end
else begin // do not reverse
for ( n=0 ; n < TLU_TRIGGER_MAX_CLOCK_CYCLES ; n = n+1 ) begin
if (n > 31-1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((n+2)*DIVISOR)-1];
end
end
/*
if (TLU_TRIGGER_CLOCK_CYCLES == 5'b0_0000) begin // 0 results in 32 clock cycles -> 31bit trigger number
if (TLU_TRIGGER_DATA_MSB_FIRST == 1'b0) begin // reverse bit order
for ( n=0 ; n < 32 ; n = n+1 ) begin
if (n > 31-1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((32-n)*DIVISOR)-1];
end
end
else begin // do not reverse
for ( n=0 ; n < 32 ; n = n+1 ) begin
if (n > 31-1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((n+2)*DIVISOR)-1];
end
end
end
else begin // specific number of clock cycles
if (TLU_TRIGGER_DATA_MSB_FIRST == 1'b0) begin // reverse bit order
for ( n=31 ; n >= 0 ; n = n-1 ) begin
if (n + 1 > TLU_TRIGGER_CLOCK_CYCLES - 1)
TLU_TRIGGER_NUMBER_DATA[n] = 1'b0;
else if (n + 1 == TLU_TRIGGER_CLOCK_CYCLES - 1) begin
for ( i=0 ; i < 32 ; i = i+1 ) begin
if (i < TLU_TRIGGER_CLOCK_CYCLES-1)
TLU_TRIGGER_NUMBER_DATA[n-i] = tlu_data_sr[((i+2)*DIVISOR)-1];
end
end
end
end
else begin // do not reverse
for ( n=0 ; n < 32 ; n = n+1 ) begin
if (n + 1 > TLU_TRIGGER_CLOCK_CYCLES - 1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((n+2)*DIVISOR)-1];
end
end
end
*/
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
if (state != next && TRIGGER == 1'b0 && counter_trigger_low_time_out < 4 && TRIGGER_MODE == 2'b10) // 4 clocks cycles = 1 for output + 3 for sync
TLU_TRIGGER_ACCEPT_ERROR <= 1'b1;
end
WAIT_FOR_TLU_DATA_SAVED_CMD_READY:
begin
//if ()
// FIFO_PREEMPT_REQ <= 1'b0;
//else
// FIFO_PREEMPT_REQ <= FIFO_PREEMPT_REQ;
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
// de-assert TLU busy as soon as possible
//if (TRIGGER_ACKNOWLEDGED == 1'b1 && FIFO_ACKNOWLEDGED == 1'b1)
// TLU_BUSY <= 1'b0;
//else
TLU_BUSY <= TLU_BUSY;
TLU_CLOCK_ENABLE <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
end
endcase
end
end
// time stamp
always @(posedge TRIGGER_CLK)
begin
if (RESET || (TLU_RESET_FLAG && (TRIGGER_MODE == 2'b10 || TRIGGER_MODE == 2'b11)) || TIMESTAMP_RESET_FLAG)
TIMESTAMP <= 0;
else
TIMESTAMP <= TIMESTAMP + 1;
end
// Chipscope
`ifdef SYNTHESIS_NOT
//`ifdef SYNTHESIS
wire [35:0] control_bus;
chipscope_icon ichipscope_icon
(
.CONTROL0(control_bus)
);
chipscope_ila ichipscope_ila
(
.CONTROL(control_bus),
.TRIGGER_CLK(TRIGGER_CLK),
.TRIG0({TRIGGER_ENABLE, TRIGGER_DATA_WRITE, TRIGGER_ACCEPTED_FLAG, TLU_CLOCK_ENABLE, TLU_ASSERT_VETO, TLU_BUSY, TRIGGER_ACKNOWLEDGE, TRIGGER_VETO, TLU_TRIGGER_ACCEPT_ERROR, TLU_TRIGGER_LOW_TIMEOUT_ERROR, TRIGGER_FLAG, TRIGGER, TRIGGER_MODE, state})
//.TRIGGER_CLK(CLK_160),
//.TRIG0({FMODE, FSTROBE, FREAD, CMD_BUS_WR, RX_BUS_WR, FIFO_WR, BUS_DATA_IN, FE_RX ,WR_B, RD_B})
);
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A22OI_BEHAVIORAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_BEHAVIORAL_PP_V |
module MPUC1307 ( CLK,DS ,ED, MPYJ,DR,DI ,DOR ,DOI );
parameter total_bits = 32;
input CLK ;
wire CLK ;
input DS ;
wire DS ;
input ED; //data strobe
input MPYJ ; //the result is multiplied by -j
wire MPYJ ;
input [total_bits-1:0] DR ;
wire signed [total_bits-1:0] DR ;
input [total_bits-1:0] DI ;
wire signed [total_bits-1:0] DI ;
output [total_bits:0] DOR ;
reg [total_bits:0] DOR ;
output [total_bits:0] DOI ;
reg [total_bits:0] DOI ;
reg signed [total_bits+2 :0] dx5;
reg signed [total_bits-1 :0] dx7;
reg signed [total_bits-1 :0] dii;
reg signed [total_bits : 0] dt;
wire signed [total_bits+3 : 0] dx5p;
wire signed [total_bits+3 : 0] dot;
reg edd,edd2, edd3; //delayed data enable impulse
reg mpyjd,mpyjd2,mpyjd3;
reg [total_bits:0] doo ;
reg [total_bits:0] droo ;
always @(posedge CLK)
begin
if (ED) begin
edd<=DS;
edd2<=edd;
edd3<=edd2;
mpyjd<=MPYJ;
mpyjd2<=mpyjd;
mpyjd3<=mpyjd2; //1_0100_1110_0111_1011
if (DS) begin // 1_0101_00T0_1000_0T0T
dx5<=DR+(DR <<2); //multiply by 5
dx7<=DR-(DR>>>3); //multiply by 7, shifted right to 2
dt<=DR;
dii<=DI;
end
else begin
dx5<=dii+(dii <<2); //multiply by 5
dx7<=dii-(dii>>>3); //multiply by 7, shifted right to 3
dt<=dii;
end
doo<=dot >>>3;
droo<=doo;
if (edd3)
if (mpyjd3) begin
DOR<=doo;
DOI<= - droo; end
else begin
DOR<=droo;
DOI<= doo; end
end
end
assign dx5p=(dx5<<1)+(dx7>>>1); // multiply by 1_0101_00T
assign dot= (dx5p+(dt>>>6) -(dx5>>>13));// multiply by 1_0101_00T0_1000_0T0T
endmodule
|
/*
* Author : Tom Stanway-Mayers
* Description : Pre-Fetch Unit
* Version: :
* License : Apache License Version 2.0, January 2004
* License URL : http://www.apache.org/licenses/
*/
`include "riscv_defs.v"
module merlin_pfu
#(
parameter C_FIFO_PASSTHROUGH = 0,
parameter C_FIFO_DEPTH_X = 2, // depth >= read latency + 2
parameter C_WORD_RESET_VECTOR = { `RV_XLEN-2 {1'b0} }
)
(
// global
input wire clk_i,
input wire reset_i,
// instruction cache interface
input wire ireqready_i,
output wire ireqvalid_o,
output wire [1:0] ireqhpl_o,
output wire [`RV_XLEN-1:0] ireqaddr_o, // TODO - consider bypassing the pc on a jump
output wire irspready_o,
input wire irspvalid_i,
input wire irsprerr_i,
input wire [`RV_XLEN-1:0] irspdata_i,
// decoder interface
output wire ids_dav_o, // new fetch available
input wire ids_ack_i, // ack this fetch
input wire [1:0] ids_ack_size_i, // size of this ack TODO
output wire [`RV_SOFID_RANGE] ids_sofid_o, // first fetch since vectoring
output wire [31:0] ids_ins_o, // instruction fetched
output wire ids_ferr_o, // this instruction fetch resulted in error
output wire [`RV_XLEN-1:0] ids_pc_o, // address of this instruction
// ex stage vectoring interface
input wire exs_pc_wr_i,
input wire [`RV_XLEN-1:0] exs_pc_din_i,
// pfu stage interface
input wire [1:0] exs_hpl_i
);
//--------------------------------------------------------------
// interface assignments
// ibus debt
reg ibus_debt;
wire request;
wire response;
// fifo level counter
reg [C_FIFO_DEPTH_X:0] fifo_level_q;
reg fifo_accepting;
// program counter
reg [`RV_XLEN-1:0] pc_q;
reg [`RV_XLEN-1:0] request_addr_q;
// vectoring flag register
reg vectoring_q;
// sofid register
reg [`RV_SOFID_RANGE] sofid_q;
// fifo
parameter C_SOFID_SZ = `RV_SOFID_SZ;
parameter C_FIFO_WIDTH = C_SOFID_SZ + 1 + `RV_XLEN + `RV_XLEN;
//
parameter C_SOFID_LSB = 1 + 2 * `RV_XLEN;
parameter C_FERR_LSB = 2 * `RV_XLEN;
parameter C_FIFO_PC_LSB = `RV_XLEN;
parameter C_FIFO_INS_LSB = 0;
//
wire fifo_empty;
wire [C_FIFO_WIDTH-1:0] fifo_din;
wire [C_FIFO_WIDTH-1:0] fifo_dout;
wire [`RV_XLEN-1:0] fifo_dout_data;
//--------------------------------------------------------------
//--------------------------------------------------------------
// interface assignments
//--------------------------------------------------------------
assign ireqhpl_o = exs_hpl_i;
assign ireqvalid_o = fifo_accepting & ~exs_pc_wr_i & (~ibus_debt | response);
assign ireqaddr_o = { pc_q[`RV_XLEN-1:`RV_XLEN_X-3], { `RV_XLEN_X-3 {1'b0} } };
assign irspready_o = 1'b1; //irspvalid_i; // always ready
//
assign ids_dav_o = ~fifo_empty;
assign ids_ins_o = fifo_dout_data[31:0];
//--------------------------------------------------------------
// ibus debt
//--------------------------------------------------------------
assign request = ireqvalid_o & ireqready_i;
assign response = irspvalid_i & irspready_o;
//
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
ibus_debt <= 1'b0;
end else begin
if (request & ~response) begin
ibus_debt <= 1'b1;
end else if (~request & response) begin
ibus_debt <= 1'b0;
end
end
end
//--------------------------------------------------------------
// fifo level counter
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
fifo_level_q <= { 1'b1, { C_FIFO_DEPTH_X {1'b0} } };
end else begin
//*
if (exs_pc_wr_i) begin
fifo_level_q <= { 1'b1, { C_FIFO_DEPTH_X {1'b0} } };
end else
/**/
if (request & ~ids_ack_i) begin
fifo_level_q <= fifo_level_q - { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
end else if (~request & ids_ack_i) begin
fifo_level_q <= fifo_level_q + { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
end
end
end
always @ (*) begin
if (|fifo_level_q) begin
fifo_accepting = 1'b1;
end else begin
fifo_accepting = 1'b0;
end
end
//--------------------------------------------------------------
// program counter
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
pc_q <= { C_WORD_RESET_VECTOR, 2'b0 };
end else begin
if (exs_pc_wr_i) begin
pc_q <= exs_pc_din_i;
end else if (request) begin
pc_q <= pc_q + { { `RV_XLEN-(`RV_XLEN_X-2) {1'b0} }, 1'b1, { `RV_XLEN_X-3 {1'b0} } };
end
end
end
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
if (request) begin
request_addr_q <= pc_q;
end
end
//--------------------------------------------------------------
// vectoring flag register
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
vectoring_q <= 1'b0;
end else begin
if (exs_pc_wr_i) begin
vectoring_q <= 1'b1;
end else if (request) begin
vectoring_q <= 1'b0;
end
end
end
//--------------------------------------------------------------
// sofid register
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
sofid_q <= `RV_SOFID_RUN;
end else begin
if (vectoring_q & request) begin
sofid_q <= `RV_SOFID_JUMP;
end else if (response) begin
sofid_q <= `RV_SOFID_RUN;
end
end
end
//--------------------------------------------------------------
// fifo
//--------------------------------------------------------------
assign fifo_din[ C_SOFID_LSB +: C_SOFID_SZ] = sofid_q; // TODO
assign fifo_din[ C_FERR_LSB +: 1] = irsprerr_i;
assign fifo_din[ C_FIFO_PC_LSB +: `RV_XLEN] = request_addr_q;
assign fifo_din[C_FIFO_INS_LSB +: `RV_XLEN] = irspdata_i;
//
assign ids_sofid_o = fifo_dout[ C_SOFID_LSB +: C_SOFID_SZ];
assign ids_ferr_o = fifo_dout[ C_FERR_LSB +: 1];
assign ids_pc_o = fifo_dout[ C_FIFO_PC_LSB +: `RV_XLEN];
assign fifo_dout_data = fifo_dout[C_FIFO_INS_LSB +: `RV_XLEN];
//
merlin_fifo
#(
.C_FIFO_PASSTHROUGH (C_FIFO_PASSTHROUGH),
.C_FIFO_WIDTH (C_FIFO_WIDTH),
.C_FIFO_DEPTH_X (C_FIFO_DEPTH_X)
) i_merlin_fifo (
// global
.clk_i (clk_i),
.reset_i (reset_i),
// control and status
.flush_i (exs_pc_wr_i | vectoring_q),
.empty_o (fifo_empty),
.full_o (),
// write port
.wr_i (response),
.din_i (fifo_din),
// read port
.rd_i (ids_ack_i),
.dout_o (fifo_dout)
);
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module CvtColor_1 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
p_src_rows_V_dout,
p_src_rows_V_empty_n,
p_src_rows_V_read,
p_src_cols_V_dout,
p_src_cols_V_empty_n,
p_src_cols_V_read,
p_src_data_stream_0_V_dout,
p_src_data_stream_0_V_empty_n,
p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout,
p_src_data_stream_1_V_empty_n,
p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout,
p_src_data_stream_2_V_empty_n,
p_src_data_stream_2_V_read,
p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n,
p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n,
p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n,
p_dst_data_stream_2_V_write
);
parameter ap_ST_fsm_state1 = 4'd1;
parameter ap_ST_fsm_state2 = 4'd2;
parameter ap_ST_fsm_pp0_stage0 = 4'd4;
parameter ap_ST_fsm_state14 = 4'd8;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] p_src_rows_V_dout;
input p_src_rows_V_empty_n;
output p_src_rows_V_read;
input [15:0] p_src_cols_V_dout;
input p_src_cols_V_empty_n;
output p_src_cols_V_read;
input [7:0] p_src_data_stream_0_V_dout;
input p_src_data_stream_0_V_empty_n;
output p_src_data_stream_0_V_read;
input [7:0] p_src_data_stream_1_V_dout;
input p_src_data_stream_1_V_empty_n;
output p_src_data_stream_1_V_read;
input [7:0] p_src_data_stream_2_V_dout;
input p_src_data_stream_2_V_empty_n;
output p_src_data_stream_2_V_read;
output [7:0] p_dst_data_stream_0_V_din;
input p_dst_data_stream_0_V_full_n;
output p_dst_data_stream_0_V_write;
output [7:0] p_dst_data_stream_1_V_din;
input p_dst_data_stream_1_V_full_n;
output p_dst_data_stream_1_V_write;
output [7:0] p_dst_data_stream_2_V_din;
input p_dst_data_stream_2_V_full_n;
output p_dst_data_stream_2_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg p_src_rows_V_read;
reg p_src_cols_V_read;
reg p_src_data_stream_0_V_read;
reg p_src_data_stream_1_V_read;
reg p_src_data_stream_2_V_read;
reg p_dst_data_stream_0_V_write;
reg p_dst_data_stream_1_V_write;
reg p_dst_data_stream_2_V_write;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
wire [2:0] sector_data_0_address0;
reg sector_data_0_ce0;
wire [1:0] sector_data_0_q0;
wire [2:0] sector_data_1_address0;
reg sector_data_1_ce0;
wire [1:0] sector_data_1_q0;
wire [2:0] sector_data_2_address0;
reg sector_data_2_ce0;
wire [1:0] sector_data_2_q0;
reg p_src_rows_V_blk_n;
reg p_src_cols_V_blk_n;
reg p_src_data_stream_0_V_blk_n;
wire ap_CS_fsm_pp0_stage0;
reg ap_enable_reg_pp0_iter1;
wire ap_block_pp0_stage0;
reg [0:0] tmp_53_i_reg_783;
reg p_src_data_stream_1_V_blk_n;
reg p_src_data_stream_2_V_blk_n;
reg p_dst_data_stream_0_V_blk_n;
reg ap_enable_reg_pp0_iter10;
reg [0:0] ap_reg_pp0_iter9_tmp_53_i_reg_783;
reg p_dst_data_stream_1_V_blk_n;
reg p_dst_data_stream_2_V_blk_n;
reg [10:0] j_i_reg_226;
reg [15:0] p_src_cols_V_read_reg_764;
reg ap_block_state1;
reg [15:0] p_src_rows_V_read_reg_769;
wire [0:0] tmp_i_fu_241_p2;
wire ap_CS_fsm_state2;
wire [10:0] i_fu_246_p2;
reg [10:0] i_reg_778;
wire [0:0] tmp_53_i_fu_256_p2;
wire ap_block_state3_pp0_stage0_iter0;
reg ap_block_state4_pp0_stage0_iter1;
wire ap_block_state5_pp0_stage0_iter2;
wire ap_block_state6_pp0_stage0_iter3;
wire ap_block_state7_pp0_stage0_iter4;
wire ap_block_state8_pp0_stage0_iter5;
wire ap_block_state9_pp0_stage0_iter6;
wire ap_block_state10_pp0_stage0_iter7;
wire ap_block_state11_pp0_stage0_iter8;
wire ap_block_state12_pp0_stage0_iter9;
reg ap_block_state13_pp0_stage0_iter10;
reg ap_block_pp0_stage0_11001;
reg [0:0] ap_reg_pp0_iter1_tmp_53_i_reg_783;
reg [0:0] ap_reg_pp0_iter2_tmp_53_i_reg_783;
reg [0:0] ap_reg_pp0_iter3_tmp_53_i_reg_783;
reg [0:0] ap_reg_pp0_iter4_tmp_53_i_reg_783;
reg [0:0] ap_reg_pp0_iter5_tmp_53_i_reg_783;
reg [0:0] ap_reg_pp0_iter6_tmp_53_i_reg_783;
reg [0:0] ap_reg_pp0_iter7_tmp_53_i_reg_783;
reg [0:0] ap_reg_pp0_iter8_tmp_53_i_reg_783;
wire [10:0] j_fu_261_p2;
reg ap_enable_reg_pp0_iter0;
reg [7:0] tmp_26_reg_792;
reg [7:0] ap_reg_pp0_iter2_tmp_26_reg_792;
reg [7:0] tmp_27_reg_797;
reg [7:0] ap_reg_pp0_iter2_tmp_27_reg_797;
reg [7:0] ap_reg_pp0_iter3_tmp_27_reg_797;
reg [7:0] tmp_28_reg_804;
reg [7:0] ap_reg_pp0_iter2_tmp_28_reg_804;
reg [0:0] tmp_reg_811;
reg [0:0] ap_reg_pp0_iter2_tmp_reg_811;
wire [6:0] tmp_10_fu_275_p1;
reg [6:0] tmp_10_reg_816;
reg [6:0] ap_reg_pp0_iter2_tmp_10_reg_816;
wire [26:0] p_Val2_i_fu_752_p2;
reg [26:0] p_Val2_i_reg_821;
wire [23:0] r_V_3_fu_758_p2;
reg [23:0] r_V_3_reg_827;
wire [27:0] tab_0_V_fu_346_p3;
reg [27:0] tab_0_V_reg_833;
reg [27:0] ap_reg_pp0_iter4_tab_0_V_reg_833;
reg [27:0] ap_reg_pp0_iter5_tab_0_V_reg_833;
reg [27:0] ap_reg_pp0_iter6_tab_0_V_reg_833;
reg [27:0] ap_reg_pp0_iter7_tab_0_V_reg_833;
reg [27:0] ap_reg_pp0_iter8_tab_0_V_reg_833;
wire [4:0] tmp_s_fu_356_p4;
reg [4:0] tmp_s_reg_843;
reg [4:0] ap_reg_pp0_iter5_tmp_s_reg_843;
wire [24:0] f_V_fu_377_p2;
reg [24:0] f_V_reg_850;
wire [27:0] tab_1_V_fu_390_p2;
reg [27:0] tab_1_V_reg_855;
reg [27:0] ap_reg_pp0_iter5_tab_1_V_reg_855;
reg [27:0] ap_reg_pp0_iter6_tab_1_V_reg_855;
reg [27:0] ap_reg_pp0_iter7_tab_1_V_reg_855;
reg [27:0] ap_reg_pp0_iter8_tab_1_V_reg_855;
wire [28:0] r_V_fu_402_p2;
reg signed [28:0] r_V_reg_863;
wire [4:0] h_i_1_fu_434_p3;
reg [4:0] h_i_1_reg_878;
wire [46:0] grp_fu_418_p2;
reg [46:0] p_Val2_4_i_reg_883;
reg [27:0] tab_2_V_reg_904;
reg [27:0] tab_3_V_reg_911;
reg [1:0] sector_data_0_load_reg_918;
reg [1:0] sector_data_1_load_reg_923;
reg [1:0] sector_data_2_load_reg_928;
wire [7:0] p_Val2_20_fu_570_p3;
reg [7:0] p_Val2_20_reg_933;
wire [7:0] p_Val2_21_fu_657_p3;
reg [7:0] p_Val2_21_reg_938;
wire [7:0] p_Val2_22_fu_744_p3;
reg [7:0] p_Val2_22_reg_943;
reg ap_block_pp0_stage0_subdone;
reg ap_condition_pp0_exit_iter0_state3;
reg ap_enable_reg_pp0_iter2;
reg ap_enable_reg_pp0_iter3;
reg ap_enable_reg_pp0_iter4;
reg ap_enable_reg_pp0_iter5;
reg ap_enable_reg_pp0_iter6;
reg ap_enable_reg_pp0_iter7;
reg ap_enable_reg_pp0_iter8;
reg ap_enable_reg_pp0_iter9;
reg [10:0] i_i_reg_215;
wire ap_CS_fsm_state14;
wire [63:0] tmp_79_i_fu_441_p1;
reg ap_block_pp0_stage0_01001;
wire [15:0] i_cast_i_cast_fu_237_p1;
wire [15:0] j_cast_i_cast_fu_252_p1;
wire [18:0] r_V_4_fu_279_p4;
wire [8:0] tmp_62_i_fu_303_p1;
wire [8:0] tmp_61_i_fu_300_p1;
wire [8:0] tmp_63_i_fu_306_p2;
wire [27:0] tmp_65_i_fu_312_p3;
wire [27:0] p_Val2_cast_i_fu_297_p1;
wire [25:0] tmp_66_i_fu_326_p3;
wire [26:0] tmp_66_cast_i_fu_333_p1;
(* use_dsp48 = "no" *) wire [26:0] p_Val2_2_i_fu_337_p2;
wire [27:0] p_Val2_1_i_fu_320_p2;
wire [27:0] p_Val2_2_cast_i_fu_342_p1;
wire [23:0] tmp_55_i_fu_365_p3;
wire [24:0] r_V_10_cast1_i_cast_fu_353_p1;
wire [24:0] tmp_55_cast_i_cast_fu_373_p1;
wire [27:0] tmp_67_i_fu_383_p3;
wire [28:0] tmp_68_i_fu_395_p1;
wire [28:0] tmp_69_i_fu_398_p1;
wire signed [27:0] f_V_cast_fu_408_p1;
wire [27:0] grp_fu_418_p1;
wire [0:0] tmp_58_i_fu_424_p2;
wire [4:0] h_i_fu_429_p2;
wire [46:0] tmp_71_i_fu_447_p3;
wire [46:0] p_Val2_5_fu_454_p2;
wire [46:0] tmp_76_i_fu_469_p3;
wire [46:0] p_Val2_6_fu_476_p2;
wire [27:0] p_Val2_7_fu_491_p6;
wire [0:0] tmp_11_fu_510_p3;
wire [7:0] p_Val2_8_fu_500_p4;
wire [7:0] tmp_i_i_i_fu_518_p1;
wire [7:0] p_Val2_9_fu_530_p2;
wire [0:0] tmp_13_fu_536_p3;
wire [0:0] tmp_12_fu_522_p3;
wire [0:0] tmp_14_i_i_i_fu_544_p2;
wire [0:0] carry_fu_550_p2;
wire [0:0] lD_fu_556_p3;
wire [0:0] Range1_all_ones_fu_564_p2;
wire [27:0] p_Val2_11_fu_578_p6;
wire [0:0] tmp_15_fu_597_p3;
wire [7:0] p_Val2_12_fu_587_p4;
wire [7:0] tmp_i_i109_i_fu_605_p1;
wire [7:0] p_Val2_13_fu_617_p2;
wire [0:0] tmp_17_fu_623_p3;
wire [0:0] tmp_16_fu_609_p3;
wire [0:0] tmp_14_i_i113_i_fu_631_p2;
wire [0:0] carry_1_fu_637_p2;
wire [0:0] lD_1_fu_643_p3;
wire [0:0] Range1_all_ones_6_fu_651_p2;
wire [27:0] p_Val2_s_fu_665_p6;
wire [0:0] tmp_19_fu_684_p3;
wire [7:0] p_Val2_17_fu_674_p4;
wire [7:0] tmp_i_i122_i_fu_692_p1;
wire [7:0] p_Val2_18_fu_704_p2;
wire [0:0] tmp_21_fu_710_p3;
wire [0:0] tmp_20_fu_696_p3;
wire [0:0] tmp_14_i_i126_i_fu_718_p2;
wire [0:0] carry_2_fu_724_p2;
wire [0:0] lD_2_fu_730_p3;
wire [0:0] Range1_all_ones_7_fu_738_p2;
wire [18:0] p_Val2_i_fu_752_p0;
wire [7:0] p_Val2_i_fu_752_p1;
wire [15:0] r_V_3_fu_758_p0;
wire [7:0] r_V_3_fu_758_p1;
reg grp_fu_418_ce;
reg [3:0] ap_NS_fsm;
reg ap_idle_pp0;
wire ap_enable_pp0;
wire [46:0] grp_fu_418_p10;
wire [26:0] p_Val2_i_fu_752_p00;
wire [26:0] p_Val2_i_fu_752_p10;
wire [23:0] r_V_3_fu_758_p10;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 4'd1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter10 = 1'b0;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
#0 ap_enable_reg_pp0_iter5 = 1'b0;
#0 ap_enable_reg_pp0_iter6 = 1'b0;
#0 ap_enable_reg_pp0_iter7 = 1'b0;
#0 ap_enable_reg_pp0_iter8 = 1'b0;
#0 ap_enable_reg_pp0_iter9 = 1'b0;
end
CvtColor_1_sectormb6 #(
.DataWidth( 2 ),
.AddressRange( 6 ),
.AddressWidth( 3 ))
sector_data_0_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(sector_data_0_address0),
.ce0(sector_data_0_ce0),
.q0(sector_data_0_q0)
);
CvtColor_1_sectorncg #(
.DataWidth( 2 ),
.AddressRange( 6 ),
.AddressWidth( 3 ))
sector_data_1_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(sector_data_1_address0),
.ce0(sector_data_1_ce0),
.q0(sector_data_1_q0)
);
CvtColor_1_sectorocq #(
.DataWidth( 2 ),
.AddressRange( 6 ),
.AddressWidth( 3 ))
sector_data_2_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(sector_data_2_address0),
.ce0(sector_data_2_ce0),
.q0(sector_data_2_q0)
);
hls_saturation_enpcA #(
.ID( 1 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 29 ),
.din1_WIDTH( 28 ),
.dout_WIDTH( 47 ))
hls_saturation_enpcA_U60(
.clk(ap_clk),
.reset(ap_rst),
.din0(r_V_reg_863),
.din1(grp_fu_418_p1),
.ce(grp_fu_418_ce),
.dout(grp_fu_418_p2)
);
hls_saturation_enqcK #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 28 ),
.din1_WIDTH( 28 ),
.din2_WIDTH( 28 ),
.din3_WIDTH( 28 ),
.din4_WIDTH( 2 ),
.dout_WIDTH( 28 ))
hls_saturation_enqcK_U61(
.din0(ap_reg_pp0_iter8_tab_0_V_reg_833),
.din1(ap_reg_pp0_iter8_tab_1_V_reg_855),
.din2(tab_2_V_reg_904),
.din3(tab_3_V_reg_911),
.din4(sector_data_0_load_reg_918),
.dout(p_Val2_7_fu_491_p6)
);
hls_saturation_enqcK #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 28 ),
.din1_WIDTH( 28 ),
.din2_WIDTH( 28 ),
.din3_WIDTH( 28 ),
.din4_WIDTH( 2 ),
.dout_WIDTH( 28 ))
hls_saturation_enqcK_U62(
.din0(ap_reg_pp0_iter8_tab_0_V_reg_833),
.din1(ap_reg_pp0_iter8_tab_1_V_reg_855),
.din2(tab_2_V_reg_904),
.din3(tab_3_V_reg_911),
.din4(sector_data_1_load_reg_923),
.dout(p_Val2_11_fu_578_p6)
);
hls_saturation_enqcK #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 28 ),
.din1_WIDTH( 28 ),
.din2_WIDTH( 28 ),
.din3_WIDTH( 28 ),
.din4_WIDTH( 2 ),
.dout_WIDTH( 28 ))
hls_saturation_enqcK_U63(
.din0(ap_reg_pp0_iter8_tab_0_V_reg_833),
.din1(ap_reg_pp0_iter8_tab_1_V_reg_855),
.din2(tab_2_V_reg_904),
.din3(tab_3_V_reg_911),
.din4(sector_data_2_load_reg_928),
.dout(p_Val2_s_fu_665_p6)
);
hls_saturation_enrcU #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 19 ),
.din1_WIDTH( 8 ),
.dout_WIDTH( 27 ))
hls_saturation_enrcU_U64(
.din0(p_Val2_i_fu_752_p0),
.din1(p_Val2_i_fu_752_p1),
.dout(p_Val2_i_fu_752_p2)
);
hls_saturation_ensc4 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 16 ),
.din1_WIDTH( 8 ),
.dout_WIDTH( 24 ))
hls_saturation_ensc4_U65(
.din0(r_V_3_fu_758_p0),
.din1(r_V_3_fu_758_p1),
.dout(r_V_3_fu_758_p2)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_241_p2 == 1'd0))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else begin
if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_241_p2 == 1'd1))) begin
ap_enable_reg_pp0_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
if ((1'b1 == ap_condition_pp0_exit_iter0_state3)) begin
ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state3);
end else if ((1'b1 == 1'b1)) begin
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter10 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_241_p2 == 1'd1))) begin
ap_enable_reg_pp0_iter10 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter5 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter6 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter7 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter8 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter9 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state14)) begin
i_i_reg_215 <= i_reg_778;
end else if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
i_i_reg_215 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (tmp_53_i_fu_256_p2 == 1'd1))) begin
j_i_reg_226 <= j_fu_261_p2;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_241_p2 == 1'd1))) begin
j_i_reg_226 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
ap_reg_pp0_iter1_tmp_53_i_reg_783 <= tmp_53_i_reg_783;
tmp_53_i_reg_783 <= tmp_53_i_fu_256_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b0 == ap_block_pp0_stage0_11001)) begin
ap_reg_pp0_iter2_tmp_10_reg_816 <= tmp_10_reg_816;
ap_reg_pp0_iter2_tmp_26_reg_792 <= tmp_26_reg_792;
ap_reg_pp0_iter2_tmp_27_reg_797 <= tmp_27_reg_797;
ap_reg_pp0_iter2_tmp_28_reg_804 <= tmp_28_reg_804;
ap_reg_pp0_iter2_tmp_53_i_reg_783 <= ap_reg_pp0_iter1_tmp_53_i_reg_783;
ap_reg_pp0_iter2_tmp_reg_811 <= tmp_reg_811;
ap_reg_pp0_iter3_tmp_27_reg_797 <= ap_reg_pp0_iter2_tmp_27_reg_797;
ap_reg_pp0_iter3_tmp_53_i_reg_783 <= ap_reg_pp0_iter2_tmp_53_i_reg_783;
ap_reg_pp0_iter4_tab_0_V_reg_833 <= tab_0_V_reg_833;
ap_reg_pp0_iter4_tmp_53_i_reg_783 <= ap_reg_pp0_iter3_tmp_53_i_reg_783;
ap_reg_pp0_iter5_tab_0_V_reg_833 <= ap_reg_pp0_iter4_tab_0_V_reg_833;
ap_reg_pp0_iter5_tab_1_V_reg_855 <= tab_1_V_reg_855;
ap_reg_pp0_iter5_tmp_53_i_reg_783 <= ap_reg_pp0_iter4_tmp_53_i_reg_783;
ap_reg_pp0_iter5_tmp_s_reg_843 <= tmp_s_reg_843;
ap_reg_pp0_iter6_tab_0_V_reg_833 <= ap_reg_pp0_iter5_tab_0_V_reg_833;
ap_reg_pp0_iter6_tab_1_V_reg_855 <= ap_reg_pp0_iter5_tab_1_V_reg_855;
ap_reg_pp0_iter6_tmp_53_i_reg_783 <= ap_reg_pp0_iter5_tmp_53_i_reg_783;
ap_reg_pp0_iter7_tab_0_V_reg_833 <= ap_reg_pp0_iter6_tab_0_V_reg_833;
ap_reg_pp0_iter7_tab_1_V_reg_855 <= ap_reg_pp0_iter6_tab_1_V_reg_855;
ap_reg_pp0_iter7_tmp_53_i_reg_783 <= ap_reg_pp0_iter6_tmp_53_i_reg_783;
ap_reg_pp0_iter8_tab_0_V_reg_833 <= ap_reg_pp0_iter7_tab_0_V_reg_833;
ap_reg_pp0_iter8_tab_1_V_reg_855 <= ap_reg_pp0_iter7_tab_1_V_reg_855;
ap_reg_pp0_iter8_tmp_53_i_reg_783 <= ap_reg_pp0_iter7_tmp_53_i_reg_783;
ap_reg_pp0_iter9_tmp_53_i_reg_783 <= ap_reg_pp0_iter8_tmp_53_i_reg_783;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter3_tmp_53_i_reg_783 == 1'd1))) begin
f_V_reg_850 <= f_V_fu_377_p2;
r_V_reg_863 <= r_V_fu_402_p2;
tab_1_V_reg_855 <= tab_1_V_fu_390_p2;
tmp_s_reg_843 <= {{r_V_3_reg_827[23:19]}};
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter5_tmp_53_i_reg_783 == 1'd1))) begin
h_i_1_reg_878 <= h_i_1_fu_434_p3;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
i_reg_778 <= i_fu_246_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter8_tmp_53_i_reg_783 == 1'd1))) begin
p_Val2_20_reg_933 <= p_Val2_20_fu_570_p3;
p_Val2_21_reg_938 <= p_Val2_21_fu_657_p3;
p_Val2_22_reg_943 <= p_Val2_22_fu_744_p3;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter6_tmp_53_i_reg_783 == 1'd1))) begin
p_Val2_4_i_reg_883 <= grp_fu_418_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter1_tmp_53_i_reg_783 == 1'd1))) begin
p_Val2_i_reg_821 <= p_Val2_i_fu_752_p2;
end
end
always @ (posedge ap_clk) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_read_reg_764 <= p_src_cols_V_dout;
p_src_rows_V_read_reg_769 <= p_src_rows_V_dout;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter2_tmp_53_i_reg_783 == 1'd1))) begin
r_V_3_reg_827 <= r_V_3_fu_758_p2;
tab_0_V_reg_833 <= tab_0_V_fu_346_p3;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter7_tmp_53_i_reg_783 == 1'd1))) begin
sector_data_0_load_reg_918 <= sector_data_0_q0;
sector_data_1_load_reg_923 <= sector_data_1_q0;
sector_data_2_load_reg_928 <= sector_data_2_q0;
tab_2_V_reg_904 <= {{p_Val2_5_fu_454_p2[46:19]}};
tab_3_V_reg_911 <= {{p_Val2_6_fu_476_p2[46:19]}};
end
end
always @ (posedge ap_clk) begin
if (((tmp_53_i_reg_783 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
tmp_10_reg_816 <= tmp_10_fu_275_p1;
tmp_26_reg_792 <= p_src_data_stream_0_V_dout;
tmp_27_reg_797 <= p_src_data_stream_1_V_dout;
tmp_28_reg_804 <= p_src_data_stream_2_V_dout;
tmp_reg_811 <= p_src_data_stream_1_V_dout[32'd7];
end
end
always @ (*) begin
if ((tmp_53_i_fu_256_p2 == 1'd0)) begin
ap_condition_pp0_exit_iter0_state3 = 1'b1;
end else begin
ap_condition_pp0_exit_iter0_state3 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_241_p2 == 1'd0))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter9 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0) & (ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter10 == 1'b0))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_241_p2 == 1'd0))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
grp_fu_418_ce = 1'b1;
end else begin
grp_fu_418_ce = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1))) begin
p_dst_data_stream_0_V_blk_n = p_dst_data_stream_0_V_full_n;
end else begin
p_dst_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter10 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1))) begin
p_dst_data_stream_0_V_write = 1'b1;
end else begin
p_dst_data_stream_0_V_write = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1))) begin
p_dst_data_stream_1_V_blk_n = p_dst_data_stream_1_V_full_n;
end else begin
p_dst_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter10 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1))) begin
p_dst_data_stream_1_V_write = 1'b1;
end else begin
p_dst_data_stream_1_V_write = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter10 == 1'b1) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1))) begin
p_dst_data_stream_2_V_blk_n = p_dst_data_stream_2_V_full_n;
end else begin
p_dst_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter10 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1))) begin
p_dst_data_stream_2_V_write = 1'b1;
end else begin
p_dst_data_stream_2_V_write = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_blk_n = p_src_cols_V_empty_n;
end else begin
p_src_cols_V_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_read = 1'b1;
end else begin
p_src_cols_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_53_i_reg_783 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_0_V_blk_n = p_src_data_stream_0_V_empty_n;
end else begin
p_src_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_53_i_reg_783 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_0_V_read = 1'b1;
end else begin
p_src_data_stream_0_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_53_i_reg_783 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_1_V_blk_n = p_src_data_stream_1_V_empty_n;
end else begin
p_src_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_53_i_reg_783 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_1_V_read = 1'b1;
end else begin
p_src_data_stream_1_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_53_i_reg_783 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_2_V_blk_n = p_src_data_stream_2_V_empty_n;
end else begin
p_src_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_53_i_reg_783 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_2_V_read = 1'b1;
end else begin
p_src_data_stream_2_V_read = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_rows_V_blk_n = p_src_rows_V_empty_n;
end else begin
p_src_rows_V_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_rows_V_read = 1'b1;
end else begin
p_src_rows_V_read = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
sector_data_0_ce0 = 1'b1;
end else begin
sector_data_0_ce0 = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
sector_data_1_ce0 = 1'b1;
end else begin
sector_data_1_ce0 = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter7 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
sector_data_2_ce0 = 1'b1;
end else begin
sector_data_2_ce0 = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_241_p2 == 1'd0))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_pp0_stage0 : begin
if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (tmp_53_i_fu_256_p2 == 1'd0)) & ~((ap_enable_reg_pp0_iter9 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter10 == 1'b1)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else if ((((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (tmp_53_i_fu_256_p2 == 1'd0)) | ((ap_enable_reg_pp0_iter9 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter10 == 1'b1)))) begin
ap_NS_fsm = ap_ST_fsm_state14;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_state14 : begin
ap_NS_fsm = ap_ST_fsm_state2;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign Range1_all_ones_6_fu_651_p2 = (lD_1_fu_643_p3 | carry_1_fu_637_p2);
assign Range1_all_ones_7_fu_738_p2 = (lD_2_fu_730_p3 | carry_2_fu_724_p2);
assign Range1_all_ones_fu_564_p2 = (lD_fu_556_p3 | carry_fu_550_p2);
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state14 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage0_01001 = (((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))) | ((ap_enable_reg_pp0_iter10 == 1'b1) & (((p_dst_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)))));
end
always @ (*) begin
ap_block_pp0_stage0_11001 = (((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))) | ((ap_enable_reg_pp0_iter10 == 1'b1) & (((p_dst_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)))));
end
always @ (*) begin
ap_block_pp0_stage0_subdone = (((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))) | ((ap_enable_reg_pp0_iter10 == 1'b1) & (((p_dst_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)))));
end
always @ (*) begin
ap_block_state1 = ((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_block_state10_pp0_stage0_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state11_pp0_stage0_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state12_pp0_stage0_iter9 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state13_pp0_stage0_iter10 = (((p_dst_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)) | ((p_dst_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter9_tmp_53_i_reg_783 == 1'd1)));
end
assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state4_pp0_stage0_iter1 = (((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_53_i_reg_783 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)));
end
assign ap_block_state5_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state6_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state7_pp0_stage0_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state8_pp0_stage0_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state9_pp0_stage0_iter6 = ~(1'b1 == 1'b1);
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign carry_1_fu_637_p2 = (tmp_16_fu_609_p3 & tmp_14_i_i113_i_fu_631_p2);
assign carry_2_fu_724_p2 = (tmp_20_fu_696_p3 & tmp_14_i_i126_i_fu_718_p2);
assign carry_fu_550_p2 = (tmp_14_i_i_i_fu_544_p2 & tmp_12_fu_522_p3);
assign f_V_cast_fu_408_p1 = $signed(f_V_reg_850);
assign f_V_fu_377_p2 = (r_V_10_cast1_i_cast_fu_353_p1 - tmp_55_cast_i_cast_fu_373_p1);
assign grp_fu_418_p1 = grp_fu_418_p10;
assign grp_fu_418_p10 = $unsigned(f_V_cast_fu_408_p1);
assign h_i_1_fu_434_p3 = ((tmp_58_i_fu_424_p2[0:0] === 1'b1) ? h_i_fu_429_p2 : ap_reg_pp0_iter5_tmp_s_reg_843);
assign h_i_fu_429_p2 = ($signed(5'd26) + $signed(ap_reg_pp0_iter5_tmp_s_reg_843));
assign i_cast_i_cast_fu_237_p1 = i_i_reg_215;
assign i_fu_246_p2 = (i_i_reg_215 + 11'd1);
assign j_cast_i_cast_fu_252_p1 = j_i_reg_226;
assign j_fu_261_p2 = (j_i_reg_226 + 11'd1);
assign lD_1_fu_643_p3 = p_Val2_11_fu_578_p6[32'd27];
assign lD_2_fu_730_p3 = p_Val2_s_fu_665_p6[32'd27];
assign lD_fu_556_p3 = p_Val2_7_fu_491_p6[32'd27];
assign p_Val2_12_fu_587_p4 = {{p_Val2_11_fu_578_p6[26:19]}};
assign p_Val2_13_fu_617_p2 = (p_Val2_12_fu_587_p4 + tmp_i_i109_i_fu_605_p1);
assign p_Val2_17_fu_674_p4 = {{p_Val2_s_fu_665_p6[26:19]}};
assign p_Val2_18_fu_704_p2 = (p_Val2_17_fu_674_p4 + tmp_i_i122_i_fu_692_p1);
assign p_Val2_1_i_fu_320_p2 = (tmp_65_i_fu_312_p3 - p_Val2_cast_i_fu_297_p1);
assign p_Val2_20_fu_570_p3 = ((Range1_all_ones_fu_564_p2[0:0] === 1'b1) ? 8'd255 : p_Val2_9_fu_530_p2);
assign p_Val2_21_fu_657_p3 = ((Range1_all_ones_6_fu_651_p2[0:0] === 1'b1) ? 8'd255 : p_Val2_13_fu_617_p2);
assign p_Val2_22_fu_744_p3 = ((Range1_all_ones_7_fu_738_p2[0:0] === 1'b1) ? 8'd255 : p_Val2_18_fu_704_p2);
assign p_Val2_2_cast_i_fu_342_p1 = p_Val2_2_i_fu_337_p2;
assign p_Val2_2_i_fu_337_p2 = (p_Val2_i_reg_821 + tmp_66_cast_i_fu_333_p1);
assign p_Val2_5_fu_454_p2 = (tmp_71_i_fu_447_p3 - p_Val2_4_i_reg_883);
assign p_Val2_6_fu_476_p2 = (tmp_76_i_fu_469_p3 + p_Val2_4_i_reg_883);
assign p_Val2_8_fu_500_p4 = {{p_Val2_7_fu_491_p6[26:19]}};
assign p_Val2_9_fu_530_p2 = (p_Val2_8_fu_500_p4 + tmp_i_i_i_fu_518_p1);
assign p_Val2_cast_i_fu_297_p1 = p_Val2_i_reg_821;
assign p_Val2_i_fu_752_p0 = p_Val2_i_fu_752_p00;
assign p_Val2_i_fu_752_p00 = r_V_4_fu_279_p4;
assign p_Val2_i_fu_752_p1 = p_Val2_i_fu_752_p10;
assign p_Val2_i_fu_752_p10 = tmp_27_reg_797;
assign p_dst_data_stream_0_V_din = p_Val2_20_reg_933;
assign p_dst_data_stream_1_V_din = p_Val2_21_reg_938;
assign p_dst_data_stream_2_V_din = p_Val2_22_reg_943;
assign r_V_10_cast1_i_cast_fu_353_p1 = r_V_3_reg_827;
assign r_V_3_fu_758_p0 = 24'd17476;
assign r_V_3_fu_758_p1 = r_V_3_fu_758_p10;
assign r_V_3_fu_758_p10 = ap_reg_pp0_iter2_tmp_26_reg_792;
assign r_V_4_fu_279_p4 = {{{tmp_28_reg_804}, {tmp_28_reg_804}}, {3'd0}};
assign r_V_fu_402_p2 = (tmp_68_i_fu_395_p1 - tmp_69_i_fu_398_p1);
assign sector_data_0_address0 = tmp_79_i_fu_441_p1;
assign sector_data_1_address0 = tmp_79_i_fu_441_p1;
assign sector_data_2_address0 = tmp_79_i_fu_441_p1;
assign tab_0_V_fu_346_p3 = ((ap_reg_pp0_iter2_tmp_reg_811[0:0] === 1'b1) ? p_Val2_1_i_fu_320_p2 : p_Val2_2_cast_i_fu_342_p1);
assign tab_1_V_fu_390_p2 = (tmp_67_i_fu_383_p3 - tab_0_V_reg_833);
assign tmp_10_fu_275_p1 = p_src_data_stream_1_V_dout[6:0];
assign tmp_11_fu_510_p3 = p_Val2_7_fu_491_p6[32'd18];
assign tmp_12_fu_522_p3 = p_Val2_7_fu_491_p6[32'd26];
assign tmp_13_fu_536_p3 = p_Val2_9_fu_530_p2[32'd7];
assign tmp_14_i_i113_i_fu_631_p2 = (tmp_17_fu_623_p3 ^ 1'd1);
assign tmp_14_i_i126_i_fu_718_p2 = (tmp_21_fu_710_p3 ^ 1'd1);
assign tmp_14_i_i_i_fu_544_p2 = (tmp_13_fu_536_p3 ^ 1'd1);
assign tmp_15_fu_597_p3 = p_Val2_11_fu_578_p6[32'd18];
assign tmp_16_fu_609_p3 = p_Val2_11_fu_578_p6[32'd26];
assign tmp_17_fu_623_p3 = p_Val2_13_fu_617_p2[32'd7];
assign tmp_19_fu_684_p3 = p_Val2_s_fu_665_p6[32'd18];
assign tmp_20_fu_696_p3 = p_Val2_s_fu_665_p6[32'd26];
assign tmp_21_fu_710_p3 = p_Val2_18_fu_704_p2[32'd7];
assign tmp_53_i_fu_256_p2 = ((j_cast_i_cast_fu_252_p1 < p_src_cols_V_read_reg_764) ? 1'b1 : 1'b0);
assign tmp_55_cast_i_cast_fu_373_p1 = tmp_55_i_fu_365_p3;
assign tmp_55_i_fu_365_p3 = {{tmp_s_fu_356_p4}, {19'd0}};
assign tmp_58_i_fu_424_p2 = ((ap_reg_pp0_iter5_tmp_s_reg_843 > 5'd5) ? 1'b1 : 1'b0);
assign tmp_61_i_fu_300_p1 = ap_reg_pp0_iter2_tmp_28_reg_804;
assign tmp_62_i_fu_303_p1 = ap_reg_pp0_iter2_tmp_27_reg_797;
assign tmp_63_i_fu_306_p2 = (tmp_62_i_fu_303_p1 + tmp_61_i_fu_300_p1);
assign tmp_65_i_fu_312_p3 = {{tmp_63_i_fu_306_p2}, {19'd0}};
assign tmp_66_cast_i_fu_333_p1 = tmp_66_i_fu_326_p3;
assign tmp_66_i_fu_326_p3 = {{ap_reg_pp0_iter2_tmp_10_reg_816}, {19'd0}};
assign tmp_67_i_fu_383_p3 = {{ap_reg_pp0_iter3_tmp_27_reg_797}, {20'd0}};
assign tmp_68_i_fu_395_p1 = tab_0_V_reg_833;
assign tmp_69_i_fu_398_p1 = tab_1_V_fu_390_p2;
assign tmp_71_i_fu_447_p3 = {{ap_reg_pp0_iter7_tab_0_V_reg_833}, {19'd0}};
assign tmp_76_i_fu_469_p3 = {{ap_reg_pp0_iter7_tab_1_V_reg_855}, {19'd0}};
assign tmp_79_i_fu_441_p1 = h_i_1_reg_878;
assign tmp_i_fu_241_p2 = ((i_cast_i_cast_fu_237_p1 < p_src_rows_V_read_reg_769) ? 1'b1 : 1'b0);
assign tmp_i_i109_i_fu_605_p1 = tmp_15_fu_597_p3;
assign tmp_i_i122_i_fu_692_p1 = tmp_19_fu_684_p3;
assign tmp_i_i_i_fu_518_p1 = tmp_11_fu_510_p3;
assign tmp_s_fu_356_p4 = {{r_V_3_reg_827[23:19]}};
endmodule //CvtColor_1
|
// frame_decoder.v
`timescale 1 ns / 1 ps
module frame_detector
(
input clk400,
input clk80,
input reset,
input enable,
input sdata,
output reg [4:0]pdata,
output reg error
);
reg [5:0]s; // shift register
reg detect; // 000001 pattern detected
reg [2:0]c; // frame pos counter
wire sync = c[2]; // periodic frame sync signal
reg [4:0]p; // parallel data register
reg e; // error flag
always @(posedge clk400 or posedge reset)
begin
if (reset)
begin
s <= 0;
detect <= 0;
c <= 0;
p <= 0;
e <= 0;
end
else if (enable)
begin
s <= {s[4:0],sdata};
detect <= (s[5:0] == 6'b100000) || (s[5:0] == 6'b011111);
if (sync || detect) c <= 3'd0; else c <= c + 3'd1;
if (sync) p <= s[5:1];
if (sync) e <= 0; else if (detect) e <= 1;
end
end
always @(posedge clk80 or posedge reset)
begin
if (reset)
begin
pdata <= 5'd0;
error <= 0;
end
else if (enable)
begin
pdata <= p;
error <= e;
end
else
begin
pdata <= 5'd0;
error <= 0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__SDFXBP_BEHAVIORAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hdll__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXBP_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBEC_P_TB_V
`define SKY130_FD_SC_HD__PROBEC_P_TB_V
/**
* probec_p: Virtual current probe point.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__probec_p.v"
module top();
// Inputs are registered
reg A;
reg VGND;
reg VNB;
reg VPB;
reg VPWR;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__probec_p dut (.A(A), .VGND(VGND), .VNB(VNB), .VPB(VPB), .VPWR(VPWR), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBEC_P_TB_V
|
/*
* Baseband Processor
*
* Must read EPC Gen2 UHF RFID protocols
*
* All of the input and output signals depend on your whole RFID Tag design
* In this case, we use the delayed PIE code to clock the received PIE code. So we should input PIE code (pie_code) and delayed PIE code (clk_dpie)
* we use the clock signal in 200 KHz generated by Multivinrator to generate the clock signal in BLF. (clk_200K)
* rst is generated by POR circuit in our analog front-end circuit to reset the baseband processor. (rst)
* output the backscattered data after processing and computing to control the Backscatter circuit in our analog front-end circuit. (bs_data)
*
* Output signals package_complete and crc_check_pass are not necessary for our RFID Tag design
* it's just for test
*/
`timescale 1us / 1ns
module bb_proc
(
output bs_data,
output package_complete,
output crc_check_pass,
input clk_200K,
input pie_code,
input clk_dpie,
input rst
);
wire clk_crc5;
wire clk_crc16;
wire clk_blf;
wire clk_cp;
wire clk_prng;
wire clk_frm;
wire clk_fm0;
wire clk_mil;
wire clk_mem;
wire rst_n;
wire rst_for_new_package;
wire rst_crc16;
wire start_working;
wire dr;
wire [1:0]m;
wire en_crc5;
wire en_crc16;
wire en_2nd_clk_cp;
wire en_prng_idol;
wire en_prng_act;
wire en_tx;
wire en_if;
wire packet_complete_sync;
wire en_crc16_for_rpy;
wire reply_complete;
wire rd_complete;
wire bs_complete;
wire [7:0]cmd;
wire [51:0]param;
wire [15:0]crc_16;
wire reply_data;
wire trext;
wire [18:0]addr;
wire [15:0]prn;
wire rd_data;
wire pre_p_complete;
wire p_complete;
wire [5:0]A;
wire [15:0]Q;
wire CEN;
// --- Clock/Reset Generator ---
crg crg_1
(
.clk_crc5(clk_crc5),
.clk_crc16(clk_crc16),
.clk_blf(clk_blf),
.clk_cp(clk_cp),
.clk_prng(clk_prng),
.clk_frm(clk_frm),
.clk_fm0(clk_fm0),
.clk_mil(clk_mil),
.clk_if(clk_mem),
.rst_n(rst_n),
.clk_200K(clk_200K),
.clk_dpie(clk_dpie),
.pie_code(pie_code),
.rst(rst),
.rst_for_new_package(rst_for_new_package),
.rst_crc16(rst_crc16),
.start_working(start_working),
.dr(dr),
.m(m),
.en_crc5(en_crc5),
.en_crc16(en_crc16),
.en_2nd_clk_cp(en_2nd_clk_cp),
.en_prng_idol(en_prng_idol),
.en_prng_act(en_prng_act),
.en_tx(en_tx),
.en_if(en_if),
.packet_complete_sync(packet_complete_sync),
.en_crc16_for_rpy(en_crc16_for_rpy),
.reply_complete(reply_complete),
.rd_complete(rd_complete),
.bs_complete(bs_complete)
);
// --- RX (including Frame-Sync Detector, CRC-5, CRC-16 and Command Buffer) ---
rx rx_1
(
.cmd(cmd),
.param(param),
.package_complete(package_complete),
.crc_check_pass(crc_check_pass),
.crc_16(crc_16),
.en_crc5(en_crc5),
.en_crc16(en_crc16),
.pie_code(pie_code),
.clk_dpie(clk_dpie),
.clk_crc5(clk_crc5),
.clk_crc16(clk_crc16),
.rst_n(rst_n),
.rst_for_new_package(rst_for_new_package),
.rst_crc16(rst_crc16),
.reply_data(reply_data),
.en_crc16_for_rpy(en_crc16_for_rpy)
);
// --- Synchronizer (convential two flip-flop) ---
two_dff_sync two_dff_sync_1
(
.data_out(packet_complete_sync),
.clk_ad(clk_dpie),
.clk_bd(clk_blf),
.rst_n(rst_n),
.data_in(package_complete)
);
// --- Command Processor ---
cmd_proc cmd_proc_1
(
.reply_data(reply_data),
.reply_complete(reply_complete),
.dr(dr),
.m(m),
.trext(trext),
.en_2nd_clk_cp(en_2nd_clk_cp),
.en_tx(en_tx),
.en_prng_idol(en_prng_idol),
.en_prng_act(en_prng_act),
.en_crc16_for_rpy(en_crc16_for_rpy),
.en_if(en_if),
.addr(addr),
.clk_cp(clk_cp),
.clk_frm(clk_frm),
.rst_n(rst_n),
.rst_for_new_package(rst_for_new_package),
.cmd(cmd),
.param(param),
.prn(prn),
.crc_check_pass(crc_check_pass),
.rd_data(rd_data),
.pre_p_complete(pre_p_complete),
.p_complete(p_complete),
.rd_complete(rd_complete)
);
// --- Pseudo Ramdon Number Generator ---
prng prng_1
(
.prn(prn),
.clk_prng(clk_prng),
.rst_n(rst_n)
);
// --- Memory Interface ---
mem_if mem_if_1
(
.rd_data(rd_data),
.rd_complete(rd_complete),
.A(A),
.CEN(CEN),
.addr(addr),
.Q(Q),
.clk_if(clk_mem),
.rst_for_new_package(rst_for_new_package)
);
// --- ROM (64 words, 16 bits per word) ---
rom_64x16 rom_64x16_1
(
.Q(Q),
.CLK(clk_mem),
.CEN(CEN),
.A(A)
);
// --- TX (including Frame Generator, FM0 Encoder, Miller Encoder) ---
tx tx_1
(
.bs_data(bs_data),
.pre_p_complete(pre_p_complete),
.p_complete(p_complete),
.bs_complete(bs_complete),
.clk_blf(clk_blf),
.clk_frm(clk_frm),
.clk_fm0(clk_fm0),
.clk_mil(clk_mil),
.rst_for_new_package(rst_for_new_package),
.reply_data(reply_data),
.crc_16(crc_16),
.m(m),
.trext(trext),
.reply_complete(reply_complete),
.en_crc16_for_rpy(en_crc16_for_rpy),
.start_working(start_working)
);
endmodule
|
`timescale 1ns / 1ps
// sonic_sensor.v ver 1.0
// Description by Kazushi Yamashina
// Utsunomiya University
// [email protected]
// _ _ _ _
//clk _| |__| |__ ........... __| |__| |_
// ___
//req __| |____________________________
// ____ ___
//busy ______| ........... |_______
// ____
//finish ____________________________| |_
// ______________
//out_data ____________ ....... __result______
//
// req : If you wanna get sensor value, assert req.
// busy : Module is processing while "busy" asserts.
// sig : assign to ultra sonic distance sensor.
// out_data : If "busy" negates, value is publisehd.
module sonic_sensor(
input clk,
input rst,
input req,
output [0:0] busy,
inout sig,
output finish,
output [31:0] out_data
);
parameter STATE_INIT = 0,
STATE_IDLE = 1,
STATE_OUT_SIG = 2,
STATE_OUT_END = 3,
STATE_WAIT750 = 4,
STATE_IN_SIG_WAIT = 5,
STATE_IN_SIG = 6,
STATE_IN_SIG_END = 7,
STATE_WAIT200 = 8,
STATE_PROCESS_END = 9;
reg [3:0] state;
reg [31:0] echo;
reg [32:0] counter;
reg [31:0] result;
wire count_5u;
wire count_750u;
wire count_200u;
wire echo_fl;
reg busy_reg;
reg finish_reg;
//for debug
// assign count_5u = counter == 5;
// assign count_750u = counter == 75;
// assign count_200u = counter == 20;
// assign echo_fl = (counter > 100)? 1 : 0;
assign count_5u = counter == 499;
assign count_750u = counter == 74998;
assign count_200u = counter == 19999;
assign echo_fl = (echo == 1850000)? 1 : 0; // 18.5ms @ 100MHz
assign sig = (state == STATE_OUT_SIG)? 1 : 1'bZ;
assign busy = busy_reg;
assign finish = finish_reg;
always @(posedge clk)
begin
if(rst) begin
busy_reg <= 0;
finish_reg <= 0;
end
else
case(state)
STATE_INIT: begin
busy_reg <= 0;
finish_reg <= 0;
end
STATE_IDLE: begin
if(req)
busy_reg <= 1;
else begin
busy_reg <= 0;
finish_reg <= 0;
end
end
STATE_PROCESS_END: begin
busy_reg <= 0;
finish_reg <= 1;
end
endcase
end
//state unit
always @(posedge clk)
begin
if(rst)
state <= 0;
else case(state)
STATE_INIT: state <= STATE_IDLE;
STATE_IDLE: if(req) state <= STATE_OUT_SIG;
STATE_OUT_SIG:if(count_5u) state <= STATE_OUT_END;
STATE_OUT_END: state <= STATE_WAIT750;
STATE_WAIT750:if(count_750u) state <= STATE_IN_SIG_WAIT;
STATE_IN_SIG_WAIT: state <= STATE_IN_SIG;
STATE_IN_SIG:begin
if(echo_fl || sig == 0) state <= STATE_IN_SIG_END;
end
STATE_IN_SIG_END: state <= STATE_WAIT200;
STATE_WAIT200:if(count_200u) state <= STATE_PROCESS_END;
STATE_PROCESS_END: state <= STATE_IDLE;
default: state <= STATE_INIT;
endcase
end
//counter
always @(posedge clk)
begin
if(rst)
counter <= 0;
else
case(state)
STATE_OUT_SIG: counter <= counter + 1;
STATE_WAIT750: counter <= counter + 1;
STATE_IN_SIG : counter <= counter + 1;
STATE_WAIT200: counter <= counter + 1;
default: counter <= 0;
endcase
end
//output
always @(posedge clk)
begin
if(rst)
echo <= 0;
else if(state == STATE_IN_SIG)begin
echo <= echo + 1;
end
else if (state == STATE_PROCESS_END)
echo <= 0;
end
always @(posedge clk)begin
if(rst)
result <= 0;
else if(state == STATE_PROCESS_END)
result <= echo;
end
assign out_data = result[31:0];
endmodule
|
`ifndef __mod_regs_write
`define __mod_regs_write
// Нумерация регистров в регистровом файле
`define REG_C 3'b000
`define REG_B 3'b001
`define REG_E 3'b010
`define REG_D 3'b011
`define REG_L 3'b100
`define REG_H 3'b101
`define REG_RES 3'b110
`define REG_A 3'b111
// Запись в регистры на обратном фронте CLOCK \_ из АЛУ-результата
always @(negedge clock) begin
// Писать результат в AF
if (w_r16af) begin
if (bank_af) begin f_ <= w_r16[7:0]; a_ <= w_r16[15:8]; end
else begin f <= w_r16[7:0]; a <= w_r16[15:8]; end
end
// Сохранение в 16-разрядные регистры
else if (w_reg16) begin
case (w_num16)
/* BC */ 2'b00: if (bank_r) begin c_ <= w_r16[7:0]; b_ <= w_r16[15:8]; end
else begin c <= w_r16[7:0]; b <= w_r16[15:8]; end
/* DE */ 2'b01: if (bank_r) begin e_ <= w_r16[7:0]; d_ <= w_r16[15:8]; end
else begin e <= w_r16[7:0]; d <= w_r16[15:8]; end
/* HL, IX, IY */
// Было выбрано сохранение в IX/IY
2'b10: if (postpref) begin
if (prefix) begin yl <= w_r16[7:0]; yh <= w_r16[15:8]; end
else begin xl <= w_r16[7:0]; xh <= w_r16[15:8]; end
end else begin
if (bank_r) begin l_ <= w_r16[7:0]; h_ <= w_r16[15:8]; end
else begin l <= w_r16[7:0]; h <= w_r16[15:8]; end
end
/* SP */ 2'b11: begin sp <= w_r16; end
endcase
end
// Разрешено сохранять 8-битный регистр
else if (w_reg) begin
// Что сохранять
case (w_num)
// Обратный порядок 0=C, 1=B, 2=E, 3=D, 4=L, 5=H
`REG_C: if (bank_r) c_ <= w_r; else c <= w_r;
`REG_B: if (bank_r) b_ <= w_r; else b <= w_r;
`REG_E: if (bank_r) e_ <= w_r; else e <= w_r;
`REG_D: if (bank_r) d_ <= w_r; else d <= w_r;
`REG_L: if (postpref) begin if (prefix) yl <= w_r; else xl <= w_r; end
else if (bank_r) l_ <= w_r; else l <= w_r;
`REG_H: if (postpref) begin if (prefix) yh <= w_r; else xh <= w_r; end
else if (bank_r) h_ <= w_r; else h <= w_r;
// При сохранении может использоваться обратный порядок младшего бита
default: if (bank_af) a_ <= w_r; else a <= w_r;
endcase
end
// Запись флагов при разрешенном w_flag
if (w_flag) if ( bank_af ) f_[7:0] <= flags; else f [7:0] <= flags;
end
`endif |
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
// Date : Tue Mar 29 14:16:28 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/SKL/Desktop/ECE532/quadencoder/encoder_ip_prj2/encoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_16kb/dcfifo_32in_32out_16kb_stub.v
// Design : dcfifo_32in_32out_16kb
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2015.1" *)
module dcfifo_32in_32out_16kb(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, wr_data_count)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,wr_data_count[0:0]" */;
input rst;
input wr_clk;
input rd_clk;
input [31:0]din;
input wr_en;
input rd_en;
output [31:0]dout;
output full;
output empty;
output [0:0]wr_data_count;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2010/11/09 17:40:54 $
// \ \ / \ Date Created: 05/12/10
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: This PRBS module uses many to one feedback mechanism for 2^n
// sequence generation because the levels of logic are the same
// compared to one to many feedback mechanism for 2^n sequence
// generation. The advantage with many to one is that all 8 bits
// can be accessed for staggered output generation. The feedback
// TAP is chosen from the table that is listed in xapp052.
//
//Reference:
//Revision History:
//
//*****************************************************************************
/******************************************************************************
**$Id: prbs_gen.v,v 1.1 2010/11/09 17:40:54 mishra Exp $
**$Date: 2010/11/09 17:40:54 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_1/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/prbs_gen.v,v $
******************************************************************************/
`timescale 1ps/1ps
module prbs_gen #
(
parameter PRBS_WIDTH = 4
)
(
input clk,
input clk_en,
input rst,
output [PRBS_WIDTH-1:0] prbs_o
// output reg [3:0] prbs_shift_value
);
localparam PRBS_OFFSET = 0;
reg [PRBS_WIDTH - 1:0] Next_LFSR_Reg;
reg [PRBS_WIDTH - 1:0] LFSR_Reg;
reg [3:0] prbs_shift_value;
reg Bits_all, Feedback;
integer i;
always @ (posedge clk)
begin
if (rst )
LFSR_Reg <= {{PRBS_WIDTH-1{1'b0}},1'b1};
else if (clk_en) begin
if ( PRBS_OFFSET == 0)
// $display("prbs_value = 0x%h",LFSR_Reg);
LFSR_Reg <= Next_LFSR_Reg;
prbs_shift_value <= {prbs_shift_value[2:0],LFSR_Reg[PRBS_WIDTH-1]};
end
end
always @ (LFSR_Reg)
begin :LFSR_Next
Bits_all = ~| LFSR_Reg[PRBS_WIDTH-2:0];
Feedback = LFSR_Reg[PRBS_WIDTH-1]^Bits_all;
for (i = PRBS_WIDTH - 1; i >= 1 ; i = i-1)
Next_LFSR_Reg[i] = LFSR_Reg[i-1];
// Many to one feedback taps for 2^n sequence
// 4 logic levels required for PRBS_WIDTH = 64
case (PRBS_WIDTH)
32'd4:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[2];
32'd8:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[3]^LFSR_Reg[4]^LFSR_Reg[5];
32'd10:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[6];
32'd14:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[0]^LFSR_Reg[2]^LFSR_Reg[4];
32'd24:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[16]^LFSR_Reg[21]^LFSR_Reg[22];
32'd32:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[0]^LFSR_Reg[1]^LFSR_Reg[21];
32'd42:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[18]^LFSR_Reg[19]^LFSR_Reg[40];
32'd56:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[33]^LFSR_Reg[34]^LFSR_Reg[54];
32'd64:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[59]^LFSR_Reg[60]^LFSR_Reg[62];
32'd72:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[18]^LFSR_Reg[24]^LFSR_Reg[65];
default:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[59]^LFSR_Reg[60]^LFSR_Reg[62];
endcase
end
assign prbs_o = LFSR_Reg;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41OI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A41OI_FUNCTIONAL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a41oi (
Y ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41OI_FUNCTIONAL_V |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bomb.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bomb (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/bomb.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/bomb.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/bomb.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`include "m14k_const.vh"
module udi_top (
input [31:0] UDI_ir_e , // full 32 bit Spec2 Instruction
input UDI_irvalid_e , // Instruction reg. valid signal.
input [31:0] UDI_rs_e , // edp_abus_e data from register file
input [31:0] UDI_rt_e , // edp_bbus_e data from register file
input UDI_endianb_e , // Endian - 0=little, 1=big
input UDI_kd_mode_e , // Mode - 0=user, 1=kernel or debug
input UDI_kill_m , // Kill signal
input UDI_start_e , // mpc_run_ie signal to start the UDI.
input UDI_run_m , // mpc_run_m signal to qualify kill_m.
input UDI_greset , // greset signal to reset state machine.
input UDI_gclk , // Clock
input UDI_gscanenable , /* Outputs */
output [31:0] UDI_rd_m , // Result of the UDI in M stage
output [4:0] UDI_wrreg_e ,
output UDI_ri_e , // Illegal Spec2 Instn.
output UDI_stall_m , // Stall the pipeline. E stage signal
output UDI_present , // Indicate whether UDI is implemented
output UDI_honor_cee , // Indicate whether UDI has local state
input [`M14K_UDI_EXT_TOUDI_WIDTH-1:0] UDI_toudi , // External input to UDI module
output [`M14K_UDI_EXT_FROMUDI_WIDTH-1:0] UDI_fromudi // Output from UDI module to external system
);
//// BEGIN Wire declarations made by MVP
//wire [`M14K_UDI_EXT_FROMUDI_WIDTH-1:0] /*[0:0]*/ UDI_fromudi ;
//// END Wire declarations made by MVP
wire [31:0] udi_res ;
wire [1:0] udi_ctl_sum_mode_d ; //0- none 1- + 2- +>> 3- bypass
wire udi_ctl_res_sel_d ; //1- comparing
wire udi_ctl_thr_wr ; //1- wr_thr
wire [1:0] udi_ctl_sum_mode ; //0- none 1- + 2- +>> 3- bypass
wire udi_ctl_res_sel ; //1- comparing
wire udi_stall ;
wire udi_stall_1 ;
wire udi_stall_1_d ;
wire udi_stall_2_d ;
wire udi_stall_dd ;
localparam UDI_MAJ_OP = 6'd28 ; //RD = RS[31:16]^2 + RT[31:16]^2
localparam UDI_0 = 6'd16 ; //RD = RS[31:16]^2 + RT[31:16]^2
localparam UDI_1 = 6'd17 ; //RD = (RS[31:16]^2 + RT[31:16]^2) >> 1
localparam UDI_2 = 6'd18 ; //RD = RS[31:16]^2
localparam UDI_3 = 6'd19 ; //stored_threshold = RS
localparam UDI_4 = 6'd20 ; //RD = ( (RS[31:16]^2 + RT[31:16]^2) > stored_threshold ) ? 1 : 0
localparam UDI_5 = 6'd21 ; //RD = ( ((RS[31:16]^2 + RT[31:16]^2) >> 1) > stored_threshold ) ? 1 : 0
localparam UDI_6 = 6'd22 ; //RD = (RS[31:16]^2 > stored_threshold ) ? 1 : 0
localparam CTL_THR_WR_OFF = 1'b0 ;
localparam CTL_THR_WR_ON = 1'b1 ;
localparam CTL_SUM_MODE_NONE = 2'b00 ;
localparam CTL_SUM_MODE_SUM = 2'b01 ;
localparam CTL_SUM_MODE_SUMSHIFT = 2'b10 ;
localparam CTL_SUM_MODE_BYPASS = 2'b11 ;
localparam CTL_RES_CALC = 1'b0 ;
localparam CTL_RES_COMP = 1'b1 ;
assign UDI_fromudi[`M14K_UDI_EXT_FROMUDI_WIDTH-1:0] = {`M14K_UDI_EXT_FROMUDI_WIDTH{1'b0}} ;
assign UDI_ri_e = (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && UDI_ir_e[5:4] == 2'b01 &&
( UDI_ir_e[5:0] != UDI_0 &&
UDI_ir_e[5:0] != UDI_1 &&
UDI_ir_e[5:0] != UDI_2 &&
UDI_ir_e[5:0] != UDI_3 &&
UDI_ir_e[5:0] != UDI_4 &&
UDI_ir_e[5:0] != UDI_5 &&
UDI_ir_e[5:0] != UDI_6
)
) ? 1'b1 : 1'b0 ; // Illegal Spec2 Instn.
assign UDI_present = 1'b1 ;
assign UDI_honor_cee = 1'b0 ;
assign UDI_rd_m = udi_res ;
assign UDI_wrreg_e = (UDI_ir_e[5:0] == UDI_3) ? 5'd0 : UDI_ir_e[15:11] ;
assign udi_ctl_thr_wr = (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && UDI_ir_e[5:0] == UDI_3) ? CTL_THR_WR_ON : CTL_THR_WR_OFF ;
assign udi_ctl_sum_mode = (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && (UDI_ir_e[5:0] == UDI_0 || UDI_ir_e[5:0] == UDI_4))
? CTL_SUM_MODE_SUM : (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && (UDI_ir_e[5:0] == UDI_1 || UDI_ir_e[5:0] == UDI_5))
? CTL_SUM_MODE_SUMSHIFT : (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && (UDI_ir_e[5:0] == UDI_2 || UDI_ir_e[5:0] == UDI_6))
? CTL_SUM_MODE_BYPASS : CTL_SUM_MODE_NONE ;
assign udi_ctl_res_sel = (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP &&
(UDI_ir_e[5:0] == UDI_0 || UDI_ir_e[5:0] == UDI_1 || UDI_ir_e[5:0] == UDI_2 || UDI_ir_e[5:0] == UDI_3))
? CTL_RES_CALC : CTL_RES_COMP ;
assign UDI_stall_m = ~UDI_kill_m & (udi_stall_1_d | udi_stall_dd) ;
assign udi_stall_1 = (UDI_ir_e[5:0] == UDI_2 || UDI_ir_e[5:0] == UDI_6) ? 1'b0 : 1'b1 ;
assign udi_stall = (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP && UDI_ir_e[5:4] == 2'b01 &&
( UDI_ir_e[5:0] == UDI_0 ||
UDI_ir_e[5:0] == UDI_1 ||
UDI_ir_e[5:0] == UDI_2 ||
UDI_ir_e[5:0] == UDI_4 ||
UDI_ir_e[5:0] == UDI_5 ||
UDI_ir_e[5:0] == UDI_6
)
) ? 1'b1 : 1'b0 ;
udi_inst_pow udi_inst_pow_u(
.gclk ( UDI_gclk ), //input
.gscanenable ( UDI_gscanenable ), //input
.in_rs ( UDI_rs_e ), //input [31:0]
.in_rt ( UDI_rt_e[31:16] ), //input [15:0]
.out_rd ( udi_res ), //output [31:0]
.udi_ctl_thr_wr ( udi_ctl_thr_wr ), //input
.udi_ctl_sum_mode ( udi_ctl_sum_mode_d ), //input [1:0]
.udi_ctl_res_sel ( udi_ctl_res_sel_d ) //input
);
mvp_cregister_wide #(2) _udi_ctl_sum_mode_1_0_(udi_ctl_sum_mode_d,UDI_gscanenable, (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP), UDI_gclk, udi_ctl_sum_mode);
mvp_cregister_wide #(1) _udi_ctl_res_sel_(udi_ctl_res_sel_d,UDI_gscanenable, (UDI_irvalid_e && UDI_ir_e[31:26] == UDI_MAJ_OP), UDI_gclk, udi_ctl_res_sel);
mvp_register #(1) _udi_stall_0_(udi_stall_1_d, UDI_gclk, udi_stall);
mvp_register #(1) _udi_stall_1_(udi_stall_2_d, UDI_gclk, udi_stall_1);
mvp_register #(1) _udi_stall_2_(udi_stall_dd, UDI_gclk, udi_stall_1_d & udi_stall_2_d);
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: txuart.v
// {{{
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: Transmit outputs over a single UART line.
//
// To interface with this module, connect it to your system clock,
// pass it the 32 bit setup register (defined below) and the byte
// of data you wish to transmit. Strobe the i_wr line high for one
// clock cycle, and your data will be off. Wait until the 'o_busy'
// line is low before strobing the i_wr line again--this implementation
// has NO BUFFER, so strobing i_wr while the core is busy will just
// cause your data to be lost. The output will be placed on the o_txuart
// output line. If you wish to set/send a break condition, assert the
// i_break line otherwise leave it low.
//
// There is a synchronous reset line, logic high.
//
// Now for the setup register. The register is 32 bits, so that this
// UART may be set up over a 32-bit bus.
//
// i_setup[30] Set this to zero to use hardware flow control, and to
// one to ignore hardware flow control. Only works if the hardware
// flow control has been properly wired.
//
// If you don't want hardware flow control, fix the i_rts bit to
// 1'b1, and let the synthesys tools optimize out the logic.
//
// i_setup[29:28] Indicates the number of data bits per word. This will
// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
// for a six bit word, or 2'b11 for a five bit word.
//
// i_setup[27] Indicates whether or not to use one or two stop bits.
// Set this to one to expect two stop bits, zero for one.
//
// i_setup[26] Indicates whether or not a parity bit exists. Set this
// to 1'b1 to include parity.
//
// i_setup[25] Indicates whether or not the parity bit is fixed. Set
// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
// parity to be set based upon data. (Both assume the parity
// enable value is set.)
//
// i_setup[24] This bit is ignored if parity is not used. Otherwise,
// in the case of a fixed parity bit, this bit indicates whether
// mark (1'b1) or space (1'b0) parity is used. Likewise if the
// parity is not fixed, a 1'b1 selects even parity, and 1'b0
// selects odd.
//
// i_setup[23:0] Indicates the speed of the UART in terms of clocks.
// So, for example, if you have a 200 MHz clock and wish to
// run your UART at 9600 baud, you would take 200 MHz and divide
// by 9600 to set this value to 24'd20834. Likewise if you wished
// to run this serial port at 115200 baud from a 200 MHz clock,
// you would set the value to 24'd1736
//
// Thus, to set the UART for the common setting of an 8-bit word,
// one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
// would want to set the setup value to:
//
// 32'h0006c8 // For 115,200 baud, 8 bit, no parity
// 32'h005161 // For 9600 baud, 8 bit, no parity
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2015-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
// }}}
module txuart #(
// {{{
parameter [30:0] INITIAL_SETUP = 31'd868,
//
localparam [3:0] TXU_BIT_ZERO = 4'h0,
localparam [3:0] TXU_BIT_ONE = 4'h1,
localparam [3:0] TXU_BIT_TWO = 4'h2,
localparam [3:0] TXU_BIT_THREE = 4'h3,
// localparam [3:0] TXU_BIT_FOUR = 4'h4,
// localparam [3:0] TXU_BIT_FIVE = 4'h5,
// localparam [3:0] TXU_BIT_SIX = 4'h6,
localparam [3:0] TXU_BIT_SEVEN = 4'h7,
localparam [3:0] TXU_PARITY = 4'h8,
localparam [3:0] TXU_STOP = 4'h9,
localparam [3:0] TXU_SECOND_STOP = 4'ha,
//
localparam [3:0] TXU_BREAK = 4'he,
localparam [3:0] TXU_IDLE = 4'hf
// }}}
) (
// {{{
input wire i_clk, i_reset,
input wire [30:0] i_setup,
input wire i_break,
input wire i_wr,
input wire [7:0] i_data,
// Hardware flow control Ready-To-Send bit. Set this to one to
// use the core without flow control. (A more appropriate name
// would be the Ready-To-Receive bit ...)
input wire i_cts_n,
// And the UART input line itself
output reg o_uart_tx,
// A line to tell others when we are ready to accept data. If
// (i_wr)&&(!o_busy) is ever true, then the core has accepted a
// byte for transmission.
output wire o_busy
// }}}
);
// Signal declarations
// {{{
wire [27:0] clocks_per_baud, break_condition;
wire [1:0] i_data_bits, data_bits;
wire use_parity, parity_odd, dblstop, fixd_parity,
fixdp_value, hw_flow_control, i_parity_odd;
reg [30:0] r_setup;
assign clocks_per_baud = { 4'h0, r_setup[23:0] };
assign break_condition = { r_setup[23:0], 4'h0 };
assign hw_flow_control = !r_setup[30];
assign i_data_bits = i_setup[29:28];
assign data_bits = r_setup[29:28];
assign dblstop = r_setup[27];
assign use_parity = r_setup[26];
assign fixd_parity = r_setup[25];
assign i_parity_odd = i_setup[24];
assign parity_odd = r_setup[24];
assign fixdp_value = r_setup[24];
reg [27:0] baud_counter;
reg [3:0] state;
reg [7:0] lcl_data;
reg calc_parity, r_busy, zero_baud_counter, last_state;
reg q_cts_n, qq_cts_n, ck_cts;
// }}}
// CTS: ck_cts
// {{{
// First step ... handle any hardware flow control, if so enabled.
//
// Clock in the flow control data, two clocks to avoid metastability
// Default to using hardware flow control (uart_setup[30]==0 to use it).
// Set this high order bit off if you do not wish to use it.
//
// While we might wish to give initial values to q_rts and ck_cts,
// 1) it's not required since the transmitter starts in a long wait
// state, and 2) doing so will prevent the synthesizer from optimizing
// this pin in the case it is hard set to 1'b1 external to this
// peripheral.
//
// initial q_cts_n = 1'b1;
// initial qq_cts_n = 1'b1;
// initial ck_cts = 1'b0;
always @(posedge i_clk)
{ qq_cts_n, q_cts_n } <= { q_cts_n, i_cts_n };
always @(posedge i_clk)
ck_cts <= (!qq_cts_n)||(!hw_flow_control);
// }}}
// r_busy, state
// {{{
initial r_busy = 1'b1;
initial state = TXU_IDLE;
always @(posedge i_clk)
if (i_reset)
begin
r_busy <= 1'b1;
state <= TXU_IDLE;
end else if (i_break)
begin
state <= TXU_BREAK;
r_busy <= 1'b1;
end else if (!zero_baud_counter)
begin // r_busy needs to be set coming into here
r_busy <= 1'b1;
end else if (state == TXU_BREAK)
begin
state <= TXU_IDLE;
r_busy <= !ck_cts;
end else if (state == TXU_IDLE) // STATE_IDLE
begin
if ((i_wr)&&(!r_busy))
begin // Immediately start us off with a start bit
r_busy <= 1'b1;
case(i_data_bits)
2'b00: state <= TXU_BIT_ZERO;
2'b01: state <= TXU_BIT_ONE;
2'b10: state <= TXU_BIT_TWO;
2'b11: state <= TXU_BIT_THREE;
endcase
end else begin // Stay in idle
r_busy <= !ck_cts;
end
end else begin
// One clock tick in each of these states ...
// baud_counter <= clocks_per_baud - 28'h01;
r_busy <= 1'b1;
if (state[3] == 0) // First 8 bits
begin
if (state == TXU_BIT_SEVEN)
state <= (use_parity)? TXU_PARITY:TXU_STOP;
else
state <= state + 1;
end else if (state == TXU_PARITY)
begin
state <= TXU_STOP;
end else if (state == TXU_STOP)
begin // two stop bit(s)
if (dblstop)
state <= TXU_SECOND_STOP;
else
state <= TXU_IDLE;
end else // `TXU_SECOND_STOP and default:
begin
state <= TXU_IDLE; // Go back to idle
// Still r_busy, since we need to wait
// for the baud clock to finish counting
// out this last bit.
end
end
// }}}
// o_busy
// {{{
// This is a wire, designed to be true is we are ever busy above.
// originally, this was going to be true if we were ever not in the
// idle state. The logic has since become more complex, hence we have
// a register dedicated to this and just copy out that registers value.
assign o_busy = (r_busy);
// }}}
// r_setup
// {{{
// Our setup register. Accept changes between any pair of transmitted
// words. The register itself has many fields to it. These are
// broken out up top, and indicate what 1) our baud rate is, 2) our
// number of stop bits, 3) what type of parity we are using, and 4)
// the size of our data word.
initial r_setup = INITIAL_SETUP;
always @(posedge i_clk)
if (!o_busy)
r_setup <= i_setup;
// }}}
// lcl_data
// {{{
// This is our working copy of the i_data register which we use
// when transmitting. It is only of interest during transmit, and is
// allowed to be whatever at any other time. Hence, if r_busy isn't
// true, we can always set it. On the one clock where r_busy isn't
// true and i_wr is, we set it and r_busy is true thereafter.
// Then, on any zero_baud_counter (i.e. change between baud intervals)
// we simple logically shift the register right to grab the next bit.
initial lcl_data = 8'hff;
always @(posedge i_clk)
if (!r_busy)
lcl_data <= i_data;
else if (zero_baud_counter)
lcl_data <= { 1'b0, lcl_data[7:1] };
// }}}
// o_uart_tx
// {{{
// This is the final result/output desired of this core. It's all
// centered about o_uart_tx. This is what finally needs to follow
// the UART protocol.
//
// Ok, that said, our rules are:
// 1'b0 on any break condition
// 1'b0 on a start bit (IDLE, write, and not busy)
// lcl_data[0] during any data transfer, but only at the baud
// change
// PARITY -- During the parity bit. This depends upon whether or
// not the parity bit is fixed, then what it's fixed to,
// or changing, and hence what it's calculated value is.
// 1'b1 at all other times (stop bits, idle, etc)
initial o_uart_tx = 1'b1;
always @(posedge i_clk)
if (i_reset)
o_uart_tx <= 1'b1;
else if ((i_break)||((i_wr)&&(!r_busy)))
o_uart_tx <= 1'b0;
else if (zero_baud_counter)
casez(state)
4'b0???: o_uart_tx <= lcl_data[0];
TXU_PARITY: o_uart_tx <= calc_parity;
default: o_uart_tx <= 1'b1;
endcase
// }}}
// calc_parity
// {{{
// Calculate the parity to be placed into the parity bit. If the
// parity is fixed, then the parity bit is given by the fixed parity
// value (r_setup[24]). Otherwise the parity is given by the GF2
// sum of all the data bits (plus one for even parity).
initial calc_parity = 1'b0;
always @(posedge i_clk)
if (!o_busy)
calc_parity <= i_setup[24];
else if (fixd_parity)
calc_parity <= fixdp_value;
else if (zero_baud_counter)
begin
if (state[3] == 0) // First 8 bits of msg
calc_parity <= calc_parity ^ lcl_data[0];
else if (state == TXU_IDLE)
calc_parity <= parity_odd;
end else if (!r_busy)
calc_parity <= parity_odd;
// }}}
// baud_counter, zero_baud_counter
// {{{
// All of the above logic is driven by the baud counter. Bits must last
// {{{
// clocks_per_baud in length, and this baud counter is what we use to
// make certain of that.
//
// The basic logic is this: at the beginning of a bit interval, start
// the baud counter and set it to count clocks_per_baud. When it gets
// to zero, restart it.
//
// However, comparing a 28'bit number to zero can be rather complex--
// especially if we wish to do anything else on that same clock. For
// that reason, we create "zero_baud_counter". zero_baud_counter is
// nothing more than a flag that is true anytime baud_counter is zero.
// It's true when the logic (above) needs to step to the next bit.
// Simple enough?
//
// I wish we could stop there, but there are some other (ugly)
// conditions to deal with that offer exceptions to this basic logic.
//
// 1. When the user has commanded a BREAK across the line, we need to
// wait several baud intervals following the break before we start
// transmitting, to give any receiver a chance to recognize that we are
// out of the break condition, and to know that the next bit will be
// a stop bit.
//
// 2. A reset is similar to a break condition--on both we wait several
// baud intervals before allowing a start bit.
//
// 3. In the idle state, we stop our counter--so that upon a request
// to transmit when idle we can start transmitting immediately, rather
// than waiting for the end of the next (fictitious and arbitrary) baud
// interval.
//
// When (i_wr)&&(!r_busy)&&(state == TXU_IDLE) then we're not only in
// the idle state, but we also just accepted a command to start writing
// the next word. At this point, the baud counter needs to be reset
// to the number of clocks per baud, and zero_baud_counter set to zero.
//
// The logic is a bit twisted here, in that it will only check for the
// above condition when zero_baud_counter is false--so as to make
// certain the STOP bit is complete.
// }}}
initial zero_baud_counter = 1'b0;
initial baud_counter = 28'h05;
always @(posedge i_clk)
begin
zero_baud_counter <= (baud_counter == 28'h01);
if ((i_reset)||(i_break))
begin
// Give ourselves 16 bauds before being ready
baud_counter <= break_condition;
zero_baud_counter <= 1'b0;
end else if (!zero_baud_counter)
baud_counter <= baud_counter - 28'h01;
else if (state == TXU_BREAK)
begin
baud_counter <= 0;
zero_baud_counter <= 1'b1;
end else if (state == TXU_IDLE)
begin
baud_counter <= 28'h0;
zero_baud_counter <= 1'b1;
if ((i_wr)&&(!r_busy))
begin
baud_counter <= { 4'h0, i_setup[23:0]} - 28'h01;
zero_baud_counter <= 1'b0;
end
end else if (last_state)
baud_counter <= clocks_per_baud - 28'h02;
else
baud_counter <= clocks_per_baud - 28'h01;
end
// }}}
// last_state
// {{{
initial last_state = 1'b0;
always @(posedge i_clk)
if (dblstop)
last_state <= (state == TXU_SECOND_STOP);
else
last_state <= (state == TXU_STOP);
// }}}
// Make Verilator happy
// {{{
// Verilator lint_off UNUSED
wire unused;
assign unused = &{ 1'b0, i_parity_odd, data_bits };
// Verilator lint_on UNUSED
// }}}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// Formal properties
// {{{
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
`ifdef FORMAL
// Declarations
// {{{
reg fsv_parity;
reg [30:0] fsv_setup;
reg [7:0] fsv_data;
reg f_past_valid;
//
// Our various sequence data declarations
reg [5:0] f_five_seq;
reg [6:0] f_six_seq;
reg [7:0] f_seven_seq;
reg [8:0] f_eight_seq;
reg [2:0] f_stop_seq; // parity bit, stop bit, double stop bit
// }}}
initial f_past_valid = 1'b0;
always @(posedge i_clk)
f_past_valid <= 1'b1;
always @(posedge i_clk)
if ((i_wr)&&(!o_busy))
fsv_data <= i_data;
initial fsv_setup = INITIAL_SETUP;
always @(posedge i_clk)
if (!o_busy)
fsv_setup <= i_setup;
always @(*)
assert(r_setup == fsv_setup);
always @(posedge i_clk)
assert(zero_baud_counter == (baud_counter == 0));
always @(*)
if (!o_busy)
assert(zero_baud_counter);
/*
*
* Will only pass if !i_break && !i_reset, otherwise the setup can
* change in the middle of this operation
*
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(i_reset))&&(!$past(i_break))
&&(($past(o_busy))||($past(i_wr))))
assert(baud_counter <= { fsv_setup[23:0], 4'h0 });
*/
// A single baud interval
always @(posedge i_clk)
if ((f_past_valid)&&(!$past(zero_baud_counter))
&&(!$past(i_reset))&&(!$past(i_break)))
begin
assert($stable(o_uart_tx));
assert($stable(state));
assert($stable(lcl_data));
if ((state != TXU_IDLE)&&(state != TXU_BREAK))
assert($stable(calc_parity));
assert(baud_counter == $past(baud_counter)-1'b1);
end
//
// One byte transmitted
//
// DATA = the byte that is sent
// CKS = the number of clocks per bit
//
////////////////////////////////////////////////////////////////////////
//
// Five bit data
// {{{
////////////////////////////////////////////////////////////////////////
//
//
initial f_five_seq = 0;
always @(posedge i_clk)
if ((i_reset)||(i_break))
f_five_seq = 0;
else if ((state == TXU_IDLE)&&(i_wr)&&(!o_busy)
&&(i_data_bits == 2'b11)) // five data bits
f_five_seq <= 1;
else if (zero_baud_counter)
f_five_seq <= f_five_seq << 1;
always @(*)
if (|f_five_seq)
begin
assert(fsv_setup[29:28] == data_bits);
assert(data_bits == 2'b11);
assert(baud_counter < fsv_setup[23:0]);
assert(1'b0 == |f_six_seq);
assert(1'b0 == |f_seven_seq);
assert(1'b0 == |f_eight_seq);
assert(r_busy);
assert(state > 4'h2);
end
always @(*)
case(f_five_seq)
6'h00: begin assert(1); end
6'h01: begin
assert(state == 4'h3);
assert(o_uart_tx == 1'b0);
assert(lcl_data[4:0] == fsv_data[4:0]);
if (!fixd_parity)
assert(calc_parity == parity_odd);
end
6'h02: begin
assert(state == 4'h4);
assert(o_uart_tx == fsv_data[0]);
assert(lcl_data[3:0] == fsv_data[4:1]);
if (!fixd_parity)
assert(calc_parity == fsv_data[0] ^ parity_odd);
end
6'h04: begin
assert(state == 4'h5);
assert(o_uart_tx == fsv_data[1]);
assert(lcl_data[2:0] == fsv_data[4:2]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[1:0]) ^ parity_odd);
end
6'h08: begin
assert(state == 4'h6);
assert(o_uart_tx == fsv_data[2]);
assert(lcl_data[1:0] == fsv_data[4:3]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[2:0]) ^ parity_odd);
end
6'h10: begin
assert(state == 4'h7);
assert(o_uart_tx == fsv_data[3]);
assert(lcl_data[0] == fsv_data[4]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[3:0]) ^ parity_odd);
end
6'h20: begin
if (use_parity)
assert(state == 4'h8);
else
assert(state == 4'h9);
assert(o_uart_tx == fsv_data[4]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[4:0]) ^ parity_odd);
end
default: begin assert(0); end
endcase
// }}}
////////////////////////////////////////////////////////////////////////
//
// Six bit data
// {{{
////////////////////////////////////////////////////////////////////////
//
//
initial f_six_seq = 0;
always @(posedge i_clk)
if ((i_reset)||(i_break))
f_six_seq = 0;
else if ((state == TXU_IDLE)&&(i_wr)&&(!o_busy)
&&(i_data_bits == 2'b10)) // six data bits
f_six_seq <= 1;
else if (zero_baud_counter)
f_six_seq <= f_six_seq << 1;
always @(*)
if (|f_six_seq)
begin
assert(fsv_setup[29:28] == 2'b10);
assert(fsv_setup[29:28] == data_bits);
assert(baud_counter < fsv_setup[23:0]);
assert(1'b0 == |f_five_seq);
assert(1'b0 == |f_seven_seq);
assert(1'b0 == |f_eight_seq);
assert(r_busy);
assert(state > 4'h1);
end
always @(*)
case(f_six_seq)
7'h00: begin assert(1); end
7'h01: begin
assert(state == 4'h2);
assert(o_uart_tx == 1'b0);
assert(lcl_data[5:0] == fsv_data[5:0]);
if (!fixd_parity)
assert(calc_parity == parity_odd);
end
7'h02: begin
assert(state == 4'h3);
assert(o_uart_tx == fsv_data[0]);
assert(lcl_data[4:0] == fsv_data[5:1]);
if (!fixd_parity)
assert(calc_parity == fsv_data[0] ^ parity_odd);
end
7'h04: begin
assert(state == 4'h4);
assert(o_uart_tx == fsv_data[1]);
assert(lcl_data[3:0] == fsv_data[5:2]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[1:0]) ^ parity_odd);
end
7'h08: begin
assert(state == 4'h5);
assert(o_uart_tx == fsv_data[2]);
assert(lcl_data[2:0] == fsv_data[5:3]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[2:0]) ^ parity_odd);
end
7'h10: begin
assert(state == 4'h6);
assert(o_uart_tx == fsv_data[3]);
assert(lcl_data[1:0] == fsv_data[5:4]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[3:0]) ^ parity_odd);
end
7'h20: begin
assert(state == 4'h7);
assert(lcl_data[0] == fsv_data[5]);
assert(o_uart_tx == fsv_data[4]);
if (!fixd_parity)
assert(calc_parity == ((^fsv_data[4:0]) ^ parity_odd));
end
7'h40: begin
if (use_parity)
assert(state == 4'h8);
else
assert(state == 4'h9);
assert(o_uart_tx == fsv_data[5]);
if (!fixd_parity)
assert(calc_parity == ((^fsv_data[5:0]) ^ parity_odd));
end
default: begin if (f_past_valid) assert(0); end
endcase
// }}}
////////////////////////////////////////////////////////////////////////
//
// Seven bit data
// {{{
////////////////////////////////////////////////////////////////////////
//
//
initial f_seven_seq = 0;
always @(posedge i_clk)
if ((i_reset)||(i_break))
f_seven_seq = 0;
else if ((state == TXU_IDLE)&&(i_wr)&&(!o_busy)
&&(i_data_bits == 2'b01)) // seven data bits
f_seven_seq <= 1;
else if (zero_baud_counter)
f_seven_seq <= f_seven_seq << 1;
always @(*)
if (|f_seven_seq)
begin
assert(fsv_setup[29:28] == 2'b01);
assert(fsv_setup[29:28] == data_bits);
assert(baud_counter < fsv_setup[23:0]);
assert(1'b0 == |f_five_seq);
assert(1'b0 == |f_six_seq);
assert(1'b0 == |f_eight_seq);
assert(r_busy);
assert(state != 4'h0);
end
always @(*)
case(f_seven_seq)
8'h00: begin assert(1); end
8'h01: begin
assert(state == 4'h1);
assert(o_uart_tx == 1'b0);
assert(lcl_data[6:0] == fsv_data[6:0]);
if (!fixd_parity)
assert(calc_parity == parity_odd);
end
8'h02: begin
assert(state == 4'h2);
assert(o_uart_tx == fsv_data[0]);
assert(lcl_data[5:0] == fsv_data[6:1]);
if (!fixd_parity)
assert(calc_parity == fsv_data[0] ^ parity_odd);
end
8'h04: begin
assert(state == 4'h3);
assert(o_uart_tx == fsv_data[1]);
assert(lcl_data[4:0] == fsv_data[6:2]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[1:0]) ^ parity_odd);
end
8'h08: begin
assert(state == 4'h4);
assert(o_uart_tx == fsv_data[2]);
assert(lcl_data[3:0] == fsv_data[6:3]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[2:0]) ^ parity_odd);
end
8'h10: begin
assert(state == 4'h5);
assert(o_uart_tx == fsv_data[3]);
assert(lcl_data[2:0] == fsv_data[6:4]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[3:0]) ^ parity_odd);
end
8'h20: begin
assert(state == 4'h6);
assert(o_uart_tx == fsv_data[4]);
assert(lcl_data[1:0] == fsv_data[6:5]);
if (!fixd_parity)
assert(calc_parity == ((^fsv_data[4:0]) ^ parity_odd));
end
8'h40: begin
assert(state == 4'h7);
assert(lcl_data[0] == fsv_data[6]);
assert(o_uart_tx == fsv_data[5]);
if (!fixd_parity)
assert(calc_parity == ((^fsv_data[5:0]) ^ parity_odd));
end
8'h80: begin
if (use_parity)
assert(state == 4'h8);
else
assert(state == 4'h9);
assert(o_uart_tx == fsv_data[6]);
if (!fixd_parity)
assert(calc_parity == ((^fsv_data[6:0]) ^ parity_odd));
end
default: begin if (f_past_valid) assert(0); end
endcase
// }}}
////////////////////////////////////////////////////////////////////////
//
// Eight bit data
// {{{
////////////////////////////////////////////////////////////////////////
initial f_eight_seq = 0;
always @(posedge i_clk)
if ((i_reset)||(i_break))
f_eight_seq = 0;
else if ((state == TXU_IDLE)&&(i_wr)&&(!o_busy)
&&(i_data_bits == 2'b00)) // Eight data bits
f_eight_seq <= 1;
else if (zero_baud_counter)
f_eight_seq <= f_eight_seq << 1;
always @(*)
if (|f_eight_seq)
begin
assert(fsv_setup[29:28] == 2'b00);
assert(fsv_setup[29:28] == data_bits);
assert(baud_counter < { 6'h0, fsv_setup[23:0]});
assert(1'b0 == |f_five_seq);
assert(1'b0 == |f_six_seq);
assert(1'b0 == |f_seven_seq);
assert(r_busy);
end
always @(*)
case(f_eight_seq)
9'h000: begin assert(1); end
9'h001: begin
assert(state == 4'h0);
assert(o_uart_tx == 1'b0);
assert(lcl_data[7:0] == fsv_data[7:0]);
if (!fixd_parity)
assert(calc_parity == parity_odd);
end
9'h002: begin
assert(state == 4'h1);
assert(o_uart_tx == fsv_data[0]);
assert(lcl_data[6:0] == fsv_data[7:1]);
if (!fixd_parity)
assert(calc_parity == fsv_data[0] ^ parity_odd);
end
9'h004: begin
assert(state == 4'h2);
assert(o_uart_tx == fsv_data[1]);
assert(lcl_data[5:0] == fsv_data[7:2]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[1:0]) ^ parity_odd);
end
9'h008: begin
assert(state == 4'h3);
assert(o_uart_tx == fsv_data[2]);
assert(lcl_data[4:0] == fsv_data[7:3]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[2:0]) ^ parity_odd);
end
9'h010: begin
assert(state == 4'h4);
assert(o_uart_tx == fsv_data[3]);
assert(lcl_data[3:0] == fsv_data[7:4]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[3:0]) ^ parity_odd);
end
9'h020: begin
assert(state == 4'h5);
assert(o_uart_tx == fsv_data[4]);
assert(lcl_data[2:0] == fsv_data[7:5]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[4:0]) ^ parity_odd);
end
9'h040: begin
assert(state == 4'h6);
assert(o_uart_tx == fsv_data[5]);
assert(lcl_data[1:0] == fsv_data[7:6]);
if (!fixd_parity)
assert(calc_parity == (^fsv_data[5:0]) ^ parity_odd);
end
9'h080: begin
assert(state == 4'h7);
assert(o_uart_tx == fsv_data[6]);
assert(lcl_data[0] == fsv_data[7]);
if (!fixd_parity)
assert(calc_parity == ((^fsv_data[6:0]) ^ parity_odd));
end
9'h100: begin
if (use_parity)
assert(state == 4'h8);
else
assert(state == 4'h9);
assert(o_uart_tx == fsv_data[7]);
if (!fixd_parity)
assert(calc_parity == ((^fsv_data[7:0]) ^ parity_odd));
end
default: begin if (f_past_valid) assert(0); end
endcase
// }}}
////////////////////////////////////////////////////////////////////////
//
// Combined properties for all of the data sequences
// {{{
////////////////////////////////////////////////////////////////////////
//
always @(posedge i_clk)
if (((|f_five_seq[5:0]) || (|f_six_seq[6:0]) || (|f_seven_seq[7:0])
|| (|f_eight_seq[8:0]))
&& ($past(zero_baud_counter)))
assert(baud_counter == { 4'h0, fsv_setup[23:0] }-1);
// }}}
////////////////////////////////////////////////////////////////////////
//
// The stop sequence
// {{{
////////////////////////////////////////////////////////////////////////
//
// This consists of any parity bit, as well as one or two stop bits
//
initial f_stop_seq = 1'b0;
always @(posedge i_clk)
if ((i_reset)||(i_break))
f_stop_seq <= 0;
else if (zero_baud_counter)
begin
f_stop_seq <= 0;
if (f_stop_seq[0]) // Coming from a parity bit
begin
if (dblstop)
f_stop_seq[1] <= 1'b1;
else
f_stop_seq[2] <= 1'b1;
end
if (f_stop_seq[1])
f_stop_seq[2] <= 1'b1;
if (f_eight_seq[8] | f_seven_seq[7] | f_six_seq[6]
| f_five_seq[5])
begin
if (use_parity)
f_stop_seq[0] <= 1'b1;
else if (dblstop)
f_stop_seq[1] <= 1'b1;
else
f_stop_seq[2] <= 1'b1;
end
end
always @(*)
if (|f_stop_seq)
begin
assert(1'b0 == |f_five_seq[4:0]);
assert(1'b0 == |f_six_seq[5:0]);
assert(1'b0 == |f_seven_seq[6:0]);
assert(1'b0 == |f_eight_seq[7:0]);
assert(r_busy);
end
always @(*)
if (f_stop_seq[0])
begin
// 9 if dblstop and use_parity
if (dblstop)
assert(state == TXU_STOP);
else
assert(state == TXU_STOP);
assert(use_parity);
assert(o_uart_tx == fsv_parity);
end
always @(*)
if (f_stop_seq[1])
begin
// if (!use_parity)
assert(state == TXU_SECOND_STOP);
assert(dblstop);
assert(o_uart_tx);
end
always @(*)
if (f_stop_seq[2])
begin
assert(state == 4'hf);
assert(o_uart_tx);
assert(baud_counter < fsv_setup[23:0]-1'b1);
end
always @(*)
if (fsv_setup[25])
fsv_parity <= fsv_setup[24];
else
case(fsv_setup[29:28])
2'b00: fsv_parity = (^fsv_data[7:0]) ^ fsv_setup[24];
2'b01: fsv_parity = (^fsv_data[6:0]) ^ fsv_setup[24];
2'b10: fsv_parity = (^fsv_data[5:0]) ^ fsv_setup[24];
2'b11: fsv_parity = (^fsv_data[4:0]) ^ fsv_setup[24];
endcase
// }}}
//////////////////////////////////////////////////////////////////////
//
// The break sequence
// {{{
//////////////////////////////////////////////////////////////////////
reg [1:0] f_break_seq;
initial f_break_seq = 2'b00;
always @(posedge i_clk)
if (i_reset)
f_break_seq <= 2'b00;
else if (i_break)
f_break_seq <= 2'b01;
else if (!zero_baud_counter)
f_break_seq <= { |f_break_seq, 1'b0 };
else
f_break_seq <= 0;
always @(posedge i_clk)
if (f_break_seq[0])
assert(baud_counter == { $past(fsv_setup[23:0]), 4'h0 });
always @(posedge i_clk)
if ((f_past_valid)&&($past(f_break_seq[1]))&&(state != TXU_BREAK))
begin
assert(state == TXU_IDLE);
assert(o_uart_tx == 1'b1);
end
always @(*)
if (|f_break_seq)
begin
assert(state == TXU_BREAK);
assert(r_busy);
assert(o_uart_tx == 1'b0);
end
// }}}
//////////////////////////////////////////////////////////////////////
//
// Properties for use during induction if we are made a submodule of
// the rxuart
// {{{
//////////////////////////////////////////////////////////////////////
//
// Need enough bits for reset (24+4) plus enough bits for all of the
// various characters, 24+4, so 24+5 is a minimum of this counter
//
`ifndef TXUART
reg [28:0] f_counter;
initial f_counter = 0;
always @(posedge i_clk)
if (!o_busy)
f_counter <= 1'b0;
else
f_counter <= f_counter + 1'b1;
always @(*)
if (f_five_seq[0]|f_six_seq[0]|f_seven_seq[0]|f_eight_seq[0])
// {{{
assert(f_counter == (fsv_setup[23:0] - baud_counter - 1));
// }}}
else if (f_five_seq[1]|f_six_seq[1]|f_seven_seq[1]|f_eight_seq[1])
// {{{
assert(f_counter == ({4'h0, fsv_setup[23:0], 1'b0} - baud_counter - 1));
// }}}
else if (f_five_seq[2]|f_six_seq[2]|f_seven_seq[2]|f_eight_seq[2])
// {{{
assert(f_counter == ({4'h0, fsv_setup[23:0], 1'b0}
+{5'h0, fsv_setup[23:0]}
- baud_counter - 1));
// }}}
else if (f_five_seq[3]|f_six_seq[3]|f_seven_seq[3]|f_eight_seq[3])
// {{{
assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0}
- baud_counter - 1));
// }}}
else if (f_five_seq[4]|f_six_seq[4]|f_seven_seq[4]|f_eight_seq[4])
// {{{
assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0}
+{5'h0, fsv_setup[23:0]}
- baud_counter - 1));
// }}}
else if (f_five_seq[5]|f_six_seq[5]|f_seven_seq[5]|f_eight_seq[5])
// {{{
assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0}
+{4'h0, fsv_setup[23:0], 1'b0}
- baud_counter - 1));
// }}}
else if (f_six_seq[6]|f_seven_seq[6]|f_eight_seq[6])
// {{{
assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0}
+{5'h0, fsv_setup[23:0]}
+{4'h0, fsv_setup[23:0], 1'b0}
- baud_counter - 1));
// }}}
else if (f_seven_seq[7]|f_eight_seq[7])
// {{{
assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} // 8
- baud_counter - 1));
// }}}
else if (f_eight_seq[8])
// {{{
assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} // 9
+{5'h0, fsv_setup[23:0]}
- baud_counter - 1));
// }}}
else if (f_stop_seq[0] || (!use_parity && f_stop_seq[1]))
begin
// {{{
// Parity bit, or first of two stop bits
case(data_bits)
2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{4'h0, fsv_setup[23:0], 1'b0} // 10
- baud_counter - 1));
2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 9
- baud_counter - 1));
2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
- baud_counter - 1)); // 8
2'b11: assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0}
+{5'h0, fsv_setup[23:0]} // 7
+{4'h0, fsv_setup[23:0], 1'b0}
- baud_counter - 1));
endcase
// }}}
end else if (!use_parity && !dblstop && f_stop_seq[2])
begin
// {{{
// No parity, single stop bit
// Different from the one above, since the last counter is has
// one fewer items within it
case(data_bits)
2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{4'h0, fsv_setup[23:0], 1'b0} // 10
- baud_counter - 2));
2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 9
- baud_counter - 2));
2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
- baud_counter - 2)); // 8
2'b11: assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0}
+{5'h0, fsv_setup[23:0]} // 7
+{4'h0, fsv_setup[23:0], 1'b0}
- baud_counter - 2));
endcase
// }}}
end else if (f_stop_seq[1])
begin
// {{{
// Parity and the first of two stop bits
assert(dblstop && use_parity);
case(data_bits)
2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 11
+{4'h0, fsv_setup[23:0], 1'b0}
- baud_counter - 1));
2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{4'h0, fsv_setup[23:0], 1'b0} // 10
- baud_counter - 1));
2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 9
- baud_counter - 1));
2'b11: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
- baud_counter - 1)); // 8
endcase
// }}}
end else if ((dblstop ^ use_parity) && f_stop_seq[2])
begin
// {{{
// Parity and one stop bit
// assert(!dblstop && use_parity);
case(data_bits)
2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 11
+{4'h0, fsv_setup[23:0], 1'b0}
- baud_counter - 2));
2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{4'h0, fsv_setup[23:0], 1'b0} // 10
- baud_counter - 2));
2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 9
- baud_counter - 2));
2'b11: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
- baud_counter - 2)); // 8
endcase
// }}}
end else if (f_stop_seq[2])
begin
// {{{
assert(dblstop);
assert(use_parity);
// Parity and two stop bits
case(data_bits)
2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{3'h0, fsv_setup[23:0], 2'b00} // 12
- baud_counter - 2));
2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 11
+{4'h0, fsv_setup[23:0], 1'b0}
- baud_counter - 2));
2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{4'h0, fsv_setup[23:0], 1'b0} // 10
- baud_counter - 2));
2'b11: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0}
+{5'h0, fsv_setup[23:0]} // 9
- baud_counter - 2));
endcase
// }}}
end
`endif
// }}}
//////////////////////////////////////////////////////////////////////
//
// Other properties, not necessarily associated with any sequences
//
//////////////////////////////////////////////////////////////////////
always @(*)
assert((state < 4'hb)||(state >= 4'he));
//////////////////////////////////////////////////////////////////////
//
// Careless/limiting assumption section
//
//////////////////////////////////////////////////////////////////////
always @(*)
assume(i_setup[23:0] > 2);
always @(*)
assert(fsv_setup[23:0] > 2);
`endif // FORMAL
// }}}
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
wire awake ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pipe_user.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_pipe_user.v
// Description : PIPE User Module for 7 Series Transceiver
// Version : 15.3.3
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE User Module --------------------------------------------------
module pcie3_7x_0_pipe_user #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_USE_MODE = "3.0", // PCIe sim version
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter RXCDRLOCK_MAX = 4'd15, // RXCDRLOCK max count
parameter RXVALID_MAX = 4'd15, // RXVALID max count
parameter CONVERGE_MAX = 22'd3125000 // Convergence max count
)
(
//---------- Input -------------------------------------
input USER_TXUSRCLK,
input USER_RXUSRCLK,
input USER_OOBCLK_IN,
input USER_RST_N,
input USER_RXUSRCLK_RST_N,
input USER_PCLK_SEL,
input USER_RESETOVRD_START,
input USER_TXRESETDONE,
input USER_RXRESETDONE,
input USER_TXELECIDLE,
input USER_TXCOMPLIANCE,
input USER_RXCDRLOCK_IN,
input USER_RXVALID_IN,
input USER_RXSTATUS_IN,
input USER_PHYSTATUS_IN,
input USER_RATE_DONE,
input USER_RST_IDLE,
input USER_RATE_RXSYNC,
input USER_RATE_IDLE,
input USER_RATE_GEN3,
input USER_RXEQ_ADAPT_DONE,
//---------- Output ------------------------------------
output USER_OOBCLK,
output USER_RESETOVRD,
output USER_TXPMARESET,
output USER_RXPMARESET,
output USER_RXCDRRESET,
output USER_RXCDRFREQRESET,
output USER_RXDFELPMRESET,
output USER_EYESCANRESET,
output USER_TXPCSRESET,
output USER_RXPCSRESET,
output USER_RXBUFRESET,
output USER_RESETOVRD_DONE,
output USER_RESETDONE,
output USER_ACTIVE_LANE,
output USER_RXCDRLOCK_OUT,
output USER_RXVALID_OUT,
output USER_PHYSTATUS_OUT,
output USER_PHYSTATUS_RST,
output USER_GEN3_RDY,
output USER_RX_CONVERGE
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg2;
//---------- Internal Signal ---------------------------
reg [ 1:0] oobclk_cnt = 2'd0;
reg [ 7:0] reset_cnt = 8'd127;
reg [ 3:0] rxcdrlock_cnt = 4'd0;
reg [ 3:0] rxvalid_cnt = 4'd0;
reg [21:0] converge_cnt = 22'd0;
reg converge_gen3 = 1'd0;
//---------- Output Registers --------------------------
reg oobclk = 1'd0;
reg [ 7:0] reset = 8'h00;
reg gen3_rdy = 1'd0;
reg [ 1:0] fsm = 2'd0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 2'd0;
localparam FSM_RESETOVRD = 2'd1;
localparam FSM_RESET_INIT = 2'd2;
localparam FSM_RESET = 2'd3;
//---------- Simulation Speedup ------------------------
localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd100 : CONVERGE_MAX;
//---------- Input FF ----------------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= 1'd0;
resetovrd_start_reg1 <= 1'd0;
txresetdone_reg1 <= 1'd0;
rxresetdone_reg1 <= 1'd0;
txelecidle_reg1 <= 1'd0;
txcompliance_reg1 <= 1'd0;
rxcdrlock_reg1 <= 1'd0;
rxeq_adapt_done_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= 1'd0;
resetovrd_start_reg2 <= 1'd0;
txresetdone_reg2 <= 1'd0;
rxresetdone_reg2 <= 1'd0;
txelecidle_reg2 <= 1'd0;
txcompliance_reg2 <= 1'd0;
rxcdrlock_reg2 <= 1'd0;
rxeq_adapt_done_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= USER_PCLK_SEL;
resetovrd_start_reg1 <= USER_RESETOVRD_START;
txresetdone_reg1 <= USER_TXRESETDONE;
rxresetdone_reg1 <= USER_RXRESETDONE;
txelecidle_reg1 <= USER_TXELECIDLE;
txcompliance_reg1 <= USER_TXCOMPLIANCE;
rxcdrlock_reg1 <= USER_RXCDRLOCK_IN;
rxeq_adapt_done_reg1 <= USER_RXEQ_ADAPT_DONE;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= pclk_sel_reg1;
resetovrd_start_reg2 <= resetovrd_start_reg1;
txresetdone_reg2 <= txresetdone_reg1;
rxresetdone_reg2 <= rxresetdone_reg1;
txelecidle_reg2 <= txelecidle_reg1;
txcompliance_reg2 <= txcompliance_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
rxeq_adapt_done_reg2 <= rxeq_adapt_done_reg1;
end
end
//---------- Input FF ----------------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
begin
//---------- 1st Stage FF --------------------------
rxvalid_reg1 <= 1'd0;
rxstatus_reg1 <= 1'd0;
rst_idle_reg1 <= 1'd0;
rate_done_reg1 <= 1'd0;
rate_rxsync_reg1 <= 1'd0;
rate_idle_reg1 <= 1'd0;
rate_gen3_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
rxvalid_reg2 <= 1'd0;
rxstatus_reg2 <= 1'd0;
rst_idle_reg2 <= 1'd0;
rate_done_reg2 <= 1'd0;
rate_rxsync_reg2 <= 1'd0;
rate_idle_reg2 <= 1'd0;
rate_gen3_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
rxvalid_reg1 <= USER_RXVALID_IN;
rxstatus_reg1 <= USER_RXSTATUS_IN;
rst_idle_reg1 <= USER_RST_IDLE;
rate_done_reg1 <= USER_RATE_DONE;
rate_rxsync_reg1 <= USER_RATE_RXSYNC;
rate_idle_reg1 <= USER_RATE_IDLE;
rate_gen3_reg1 <= USER_RATE_GEN3;
//---------- 2nd Stage FF --------------------------
rxvalid_reg2 <= rxvalid_reg1;
rxstatus_reg2 <= rxstatus_reg1;
rst_idle_reg2 <= rst_idle_reg1;
rate_done_reg2 <= rate_done_reg1;
rate_rxsync_reg2 <= rate_rxsync_reg1;
rate_idle_reg2 <= rate_idle_reg1;
rate_gen3_reg2 <= rate_gen3_reg1;
end
end
//---------- Generate Reset Override -------------------------------------------
generate if (PCIE_USE_MODE == "1.0")
begin : resetovrd
//---------- Reset Counter -------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
reset_cnt <= 8'd127;
else
//---------- Decrement Counter ---------------------
if (((fsm == FSM_RESETOVRD) || (fsm == FSM_RESET)) && (reset_cnt != 8'd0))
reset_cnt <= reset_cnt - 8'd1;
//---------- Reset Counter -------------------------
else
case (reset)
8'b00000000 : reset_cnt <= 8'd127; // Programmable PMARESET time
8'b11111111 : reset_cnt <= 8'd127; // Programmable RXCDRRESET time
8'b11111110 : reset_cnt <= 8'd127; // Programmable RXCDRFREQRESET time
8'b11111100 : reset_cnt <= 8'd127; // Programmable RXDFELPMRESET time
8'b11111000 : reset_cnt <= 8'd127; // Programmable EYESCANRESET time
8'b11110000 : reset_cnt <= 8'd127; // Programmable PCSRESET time
8'b11100000 : reset_cnt <= 8'd127; // Programmable RXBUFRESET time
8'b11000000 : reset_cnt <= 8'd127; // Programmable RESETOVRD deassertion time
8'b10000000 : reset_cnt <= 8'd127;
default : reset_cnt <= 8'd127;
endcase
end
//---------- Reset Shift Register ------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
reset <= 8'h00;
else
//---------- Initialize Reset Register ---------
if (fsm == FSM_RESET_INIT)
reset <= 8'hFF;
//---------- Shift Reset Register --------------
else if ((fsm == FSM_RESET) && (reset_cnt == 8'd0))
reset <= {reset[6:0], 1'd0};
//---------- Hold Reset Register ---------------
else
reset <= reset;
end
//---------- Reset Override FSM --------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
fsm <= FSM_IDLE;
else
begin
case (fsm)
//---------- Idle State ------------------------
FSM_IDLE : fsm <= resetovrd_start_reg2 ? FSM_RESETOVRD : FSM_IDLE;
//---------- Assert RESETOVRD ------------------
FSM_RESETOVRD : fsm <= (reset_cnt == 8'd0) ? FSM_RESET_INIT : FSM_RESETOVRD;
//---------- Initialize Reset ------------------
FSM_RESET_INIT : fsm <= FSM_RESET;
//---------- Shift Reset -----------------------
FSM_RESET : fsm <= ((reset == 8'd0) && rxresetdone_reg2) ? FSM_IDLE : FSM_RESET;
//---------- Default State ---------------------
default : fsm <= FSM_IDLE;
endcase
end
end
end
//---------- Disable Reset Override --------------------------------------------
else
begin : resetovrd_disble
//---------- Generate Default Signals --------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
begin
reset_cnt <= 8'hFF;
reset <= 8'd0;
fsm <= 2'd0;
end
else
begin
reset_cnt <= 8'hFF;
reset <= 8'd0;
fsm <= 2'd0;
end
end
end
endgenerate
//---------- Generate OOB Clock Divider ------------------------
generate if (PCIE_OOBCLK_MODE == 1)
begin : oobclk_div
//---------- OOB Clock Divider -----------------------------
always @ (posedge USER_OOBCLK_IN)
begin
if (!USER_RST_N)
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
else
begin
oobclk_cnt <= oobclk_cnt + 2'd1;
oobclk <= pclk_sel_reg2 ? oobclk_cnt[1] : oobclk_cnt[0];
end
end
end
else
begin : oobclk_div_disable
//---------- OOB Clock Default -------------------------
always @ (posedge USER_OOBCLK_IN)
begin
if (!USER_RST_N)
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
else
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
end
end
endgenerate
//---------- RXCDRLOCK Filter --------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
rxcdrlock_cnt <= 4'd0;
else
//---------- Increment RXCDRLOCK Counter -----------
if (rxcdrlock_reg2 && (rxcdrlock_cnt != RXCDRLOCK_MAX))
rxcdrlock_cnt <= rxcdrlock_cnt + 4'd1;
//---------- Hold RXCDRLOCK Counter ----------------
else if (rxcdrlock_reg2 && (rxcdrlock_cnt == RXCDRLOCK_MAX))
rxcdrlock_cnt <= rxcdrlock_cnt;
//---------- Reset RXCDRLOCK Counter ---------------
else
rxcdrlock_cnt <= 4'd0;
end
//---------- RXVALID Filter ----------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
rxvalid_cnt <= 4'd0;
else
//---------- Increment RXVALID Counter -------------
if (rxvalid_reg2 && (rxvalid_cnt != RXVALID_MAX) && (!rxstatus_reg2))
rxvalid_cnt <= rxvalid_cnt + 4'd1;
//---------- Hold RXVALID Counter ------------------
else if (rxvalid_reg2 && (rxvalid_cnt == RXVALID_MAX))
rxvalid_cnt <= rxvalid_cnt;
//---------- Reset RXVALID Counter -----------------
else
rxvalid_cnt <= 4'd0;
end
//---------- Converge Counter --------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
converge_cnt <= 22'd0;
else
//---------- Enter Gen1/Gen2 -----------------------
if (rst_idle_reg2 && rate_idle_reg2 && !rate_gen3_reg2)
begin
//---------- Increment Converge Counter --------
if (converge_cnt < converge_max_cnt)
converge_cnt <= converge_cnt + 22'd1;
//---------- Hold Converge Counter -------------
else
converge_cnt <= converge_cnt;
end
//---------- Reset Converge Counter ----------------
else
converge_cnt <= 22'd0;
end
//---------- Converge ----------------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
converge_gen3 <= 1'd0;
else
//---------- Enter Gen3 ----------------------------
if (rate_gen3_reg2)
//---------- Wait for RX equalization adapt done
if (rxeq_adapt_done_reg2)
converge_gen3 <= 1'd1;
else
converge_gen3 <= converge_gen3;
//-------- Exit Gen3 -------------------------------
else
converge_gen3 <= 1'd0;
end
//---------- GEN3_RDY Generator ------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
gen3_rdy <= 1'd0;
else
gen3_rdy <= rate_idle_reg2 && rate_gen3_reg2;
end
//---------- PIPE User Override Reset Output -----------------------------------
assign USER_RESETOVRD = (fsm != FSM_IDLE);
assign USER_TXPMARESET = 1'd0;
assign USER_RXPMARESET = reset[0];
assign USER_RXCDRRESET = reset[1];
assign USER_RXCDRFREQRESET = reset[2];
assign USER_RXDFELPMRESET = reset[3];
assign USER_EYESCANRESET = reset[4];
assign USER_TXPCSRESET = 1'd0;
assign USER_RXPCSRESET = reset[5];
assign USER_RXBUFRESET = reset[6];
assign USER_RESETOVRD_DONE = (fsm == FSM_IDLE);
//---------- PIPE User Output --------------------------------------------------
assign USER_OOBCLK = oobclk;
assign USER_RESETDONE = (txresetdone_reg2 && rxresetdone_reg2);
assign USER_ACTIVE_LANE = !(txelecidle_reg2 && txcompliance_reg2);
//----------------------------------------------------------
assign USER_RXCDRLOCK_OUT = (USER_RXCDRLOCK_IN && (rxcdrlock_cnt == RXCDRLOCK_MAX)); // Filtered RXCDRLOCK
//----------------------------------------------------------
assign USER_RXVALID_OUT = ((USER_RXVALID_IN && (rxvalid_cnt == RXVALID_MAX)) && // Filtered RXVALID
rst_idle_reg2 && // Force RXVALID = 0 during reset
rate_idle_reg2); // Force RXVALID = 0 during rate change
//----------------------------------------------------------
assign USER_PHYSTATUS_OUT = (!rst_idle_reg2 || // Force PHYSTATUS = 1 during reset
((rate_idle_reg2 || rate_rxsync_reg2) && USER_PHYSTATUS_IN) || // Raw PHYSTATUS
rate_done_reg2); // Gated PHYSTATUS for rate change
//----------------------------------------------------------
assign USER_PHYSTATUS_RST = !rst_idle_reg2; // Filtered PHYSTATUS for reset
//----------------------------------------------------------
assign USER_GEN3_RDY = gen3_rdy;
//----------------------------------------------------------
assign USER_RX_CONVERGE = (converge_cnt == converge_max_cnt) || converge_gen3;
endmodule
|
module VGA_Ctrl ( // Host Side
iRed,
iGreen,
iBlue,
oCurrent_X,
oCurrent_Y,
oAddress,
oRequest,
// VGA Side
oVGA_R,
oVGA_G,
oVGA_B,
oVGA_HS,
oVGA_VS,
oVGA_SYNC,
oVGA_BLANK,
oVGA_CLOCK,
// Control Signal
iCLK,
iRST_N );
// Host Side
input [9:0] iRed;
input [9:0] iGreen;
input [9:0] iBlue;
output [21:0] oAddress;
output [10:0] oCurrent_X;
output [10:0] oCurrent_Y;
output oRequest;
// VGA Side
output [9:0] oVGA_R;
output [9:0] oVGA_G;
output [9:0] oVGA_B;
output reg oVGA_HS;
output reg oVGA_VS;
output oVGA_SYNC;
output oVGA_BLANK;
output oVGA_CLOCK;
// Control Signal
input iCLK;
input iRST_N;
// Internal Registers
reg [10:0] H_Cont;
reg [10:0] V_Cont;
////////////////////////////////////////////////////////////
// Horizontal Parameter
parameter H_FRONT = 16;
parameter H_SYNC = 96;
parameter H_BACK = 48;
parameter H_ACT = 640;
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK; //160
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT; //800
////////////////////////////////////////////////////////////
// Vertical Parameter
parameter V_FRONT = 11;
parameter V_SYNC = 2;
parameter V_BACK = 31;
parameter V_ACT = 480;
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK; //44
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT; //524
////////////////////////////////////////////////////////////
assign oVGA_SYNC = 1'b1; // This pin is unused.
assign oVGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK));
assign oVGA_CLOCK = ~iCLK;
assign oVGA_R = iRed;
assign oVGA_G = iGreen;
assign oVGA_B = iBlue;
assign oAddress = oCurrent_Y*H_ACT+oCurrent_X;
assign oRequest = ((H_Cont>=H_BLANK && H_Cont<H_TOTAL) &&
(V_Cont>=V_BLANK && V_Cont<V_TOTAL));
assign oCurrent_X = (H_Cont>=H_BLANK) ? H_Cont-H_BLANK : 11'h0 ;
assign oCurrent_Y = (V_Cont>=V_BLANK) ? V_Cont-V_BLANK : 11'h0 ;
// Horizontal Generator: Refer to the pixel clock
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
H_Cont <= 0;
oVGA_HS <= 1;
end
else
begin
if(H_Cont<H_TOTAL)
H_Cont <= H_Cont+1'b1;
else
H_Cont <= 0;
// Horizontal Sync
if(H_Cont==H_FRONT-1) // Front porch end
oVGA_HS <= 1'b0;
if(H_Cont==H_FRONT+H_SYNC-1) // Sync pulse end
oVGA_HS <= 1'b1;
end
end
// Vertical Generator: Refer to the horizontal sync
always@(posedge oVGA_HS or negedge iRST_N)
begin
if(!iRST_N)
begin
V_Cont <= 0;
oVGA_VS <= 1;
end
else
begin
if(V_Cont<V_TOTAL)
V_Cont <= V_Cont+1'b1;
else
V_Cont <= 0;
// Vertical Sync
if(V_Cont==V_FRONT-1) // Front porch end
oVGA_VS <= 1'b0;
if(V_Cont==V_FRONT+V_SYNC-1) // Sync pulse end
oVGA_VS <= 1'b1;
end
end
endmodule
|
module test_mem_dev #(
parameter READ_FIFO_SIZE = 8,
parameter WRITE_FIFO_SIZE = 8,
parameter ADDRESS_WIDTH = 8
)(
input clk,
input rst,
//Write Side
input write_enable,
input [63:0] write_addr,
input write_addr_inc,
input write_addr_dec,
output write_finished,
input [23:0] write_count,
input write_flush,
output [1:0] write_ready,
input [1:0] write_activate,
output [23:0] write_size,
input write_strobe,
input [31:0] write_data,
//Read Side
input read_enable,
input [63:0] read_addr,
input read_addr_inc,
input read_addr_dec,
output read_busy,
output read_error,
input [23:0] read_count,
input read_flush,
output read_ready,
output read_activate,
output [23:0] read_size,
output [31:0] read_data,
input read_strobe
);
//Local Parameters
//Registers/Wires
reg [ADDRESS_WIDTH - 1:0] mem_addr_in;
reg [ADDRESS_WIDTH - 1:0] mem_addr_out;
reg [23:0] local_write_count;
reg [23:0] mem_write_count;
wire mem_write_overflow;
reg [23:0] local_read_size;
reg [23:0] mem_read_count;
reg mem_read_strobe;
reg mem_write_strobe;
reg prev_write_enable;
wire posedge_write_enable;
reg prev_read_enable;
wire posedge_read_enable;
reg [31:0] prev_f2m_data;
reg f2m_data_error;
reg [31:0] prev_m2f_data;
reg m2f_data_error;
reg f2m_strobe;
wire f2m_ready;
reg f2m_activate;
wire [23:0] f2m_size;
wire [31:0] f2m_data;
reg [23:0] f2m_count;
wire [1:0] m2f_ready;
reg [1:0] m2f_activate;
wire [23:0] m2f_size;
reg m2f_strobe;
wire [31:0] m2f_data;
reg [23:0] m2f_count;
reg first_write;
wire [31:0] din;
wire wea;
reg fill_mem;
reg [31:0] fill_mem_data;
reg fill_mem_wea;
wire write_fifo_empty;
//Submodules
blk_mem #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (ADDRESS_WIDTH ),
.INC_NUM_PATTERN (1 )
) mem (
.clka (clk ),
.wea (wea ),
.dina (din ),
.addra (mem_addr_in ),
.clkb (clk ),
.doutb (m2f_data ),
.addrb (mem_addr_out )
);
ppfifo#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (WRITE_FIFO_SIZE)
)fifo_to_mem (
.reset (rst ),
//Write
.write_clock (clk ),
.write_ready (write_ready ),
.write_activate (write_activate ),
.write_fifo_size (write_size ),
.write_strobe (write_strobe ),
.write_data (write_data ),
.starved (write_fifo_empty),
//Read
.read_clock (clk ),
.read_strobe (f2m_strobe ),
.read_ready (f2m_ready ),
.read_activate (f2m_activate ),
.read_count (f2m_size ),
.read_data (f2m_data )
//.inactive ( )
);
ppfifo#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (READ_FIFO_SIZE )
)mem_to_fifo (
.reset (rst ),
//Write
.write_clock (clk ),
.write_ready (m2f_ready ),
.write_activate (m2f_activate ),
.write_fifo_size (m2f_size ),
.write_strobe (m2f_strobe ),
.write_data (m2f_data ),
//.starved ( ),
//Read
.read_clock (clk ),
.read_strobe (read_strobe ),
.read_ready (read_ready ),
.read_activate (read_activate ),
.read_count (read_size ),
.read_data (read_data )
//.inactive ( )
);
//Asynchronous Logic
assign posedge_write_enable = !prev_write_enable && write_enable;
assign posedge_read_enable = !prev_read_enable && read_enable;
assign mem_write_overflow = (mem_write_count > local_write_count);
assign write_finished = ((mem_write_count >= local_write_count) && write_fifo_empty);
assign mem_read_overflow = (mem_read_count > local_read_size);
assign read_finished = (mem_read_count >= local_read_size);
assign din = fill_mem ? fill_mem_data: f2m_data;
assign wea = fill_mem ? fill_mem_wea: f2m_strobe;
assign read_error = m2f_data_error;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
mem_addr_in <= 0;
mem_addr_out <= 0;
f2m_strobe <= 0;
f2m_activate <= 0;
f2m_count <= 0;
m2f_activate <= 0;
m2f_strobe <= 0;
m2f_count <= 0;
prev_write_enable <= 0;
prev_read_enable <= 0;
local_write_count <= 0;
local_read_size <= 0;
mem_write_count <= 0;
mem_read_count <= 0;
mem_read_strobe <= 0;
mem_write_strobe <= 0;
f2m_data_error <= 0;
m2f_data_error <= 0;
prev_f2m_data <= 0;
first_write <= 0;
fill_mem <= 1;
fill_mem_data <= 0;
fill_mem_wea <= 1;
prev_m2f_data <= 0;
end
//Fill Memory Device
else if (fill_mem) begin
fill_mem_wea <= 1;
if (mem_addr_in < (2 ** ADDRESS_WIDTH - 1)) begin
fill_mem_data <= mem_addr_in + 1;
mem_addr_in <= mem_addr_in + 1;
end
else begin
fill_mem <= 0;
fill_mem_wea <= 0;
end
end
else begin
//Strobes
f2m_strobe <= 0;
m2f_strobe <= 0;
mem_read_strobe <= 0;
mem_write_strobe <= 0;
f2m_data_error <= 0;
first_write <= 0;
m2f_data_error <= 0;
//Errors (Incomming)
if ((f2m_count > 0) && mem_write_strobe && !write_flush) begin
if ((prev_f2m_data == (2 ** ADDRESS_WIDTH) - 1) && (f2m_data != 0)) begin
//if ((mem_addr_in == (2 ** ADDRESS_WIDTH) - 1) && (f2m_data != 0)) begin
f2m_data_error <= 1;
$display ("Write: Wrap Error @ 0x%h: 0x%h != 0x%h", mem_addr_in, prev_f2m_data + 1, f2m_data);
end
else if ((prev_f2m_data + 1) != f2m_data) begin
if (first_write) begin
if (prev_f2m_data != f2m_data) begin
f2m_data_error <= 1;
$display ("Write: First Write Error @ 0x%h: 0x%h != 0x%h", mem_addr_in, prev_f2m_data + 1, f2m_data);
end
end
else begin
f2m_data_error <= 1;
$display ("Write: Error @ 0x%h: 0x%h != 0x%h", mem_addr_in, prev_f2m_data + 1, f2m_data);
end
end
end
//Error (Outgoing)
//if ((m2f_count > 0) && mem_read_strobe && !read_flush) begin
if ((m2f_count > 0) && m2f_strobe && !read_flush && ((m2f_activate & m2f_ready) == 0)) begin
if (((prev_m2f_data + 1)== (2 ** ADDRESS_WIDTH)) && (m2f_data != 0))begin
m2f_data_error <= 1;
$display ("Read: Wrap Error @ 0x%h should be 0", prev_m2f_data);
end
else if ((prev_m2f_data + 1) != m2f_data) begin
m2f_data_error <= 1;
$display ("Read: Error @ 0x%h: 0x%h != 0x%h", mem_addr_out, m2f_data, (prev_m2f_data + 1));
end
end
//Store Memory Address
if (posedge_write_enable) begin
mem_addr_in <= write_addr[ADDRESS_WIDTH - 1: 0];
local_write_count <= write_count;
mem_write_count <= 0;
end
if (posedge_read_enable) begin
mem_addr_out <= read_addr[ADDRESS_WIDTH - 1: 0];
local_read_size <= read_count;
mem_read_count <= 0;
end
//If available get a peice of the FIFO that I can write data to the memory
if (!f2m_activate && f2m_ready) begin
f2m_activate <= 1;
f2m_count <= 0;
end
//If there is an available FIFO to write to grab it
if ((m2f_activate == 0) && (m2f_ready > 0)) begin
m2f_count <= 0;
if (m2f_ready[0]) begin
m2f_activate[0] <= 1;
end
else begin
m2f_activate[1] <= 1;
end
end
if (mem_read_strobe) begin
if (read_addr_inc) begin
mem_addr_out <= mem_addr_out + 1;
end
else if (read_addr_dec) begin
mem_addr_out <= mem_addr_out - 1;
end
m2f_strobe <= 1;
end
if (!m2f_strobe &&
!mem_read_strobe && (m2f_activate > 0) &&
((m2f_count >= m2f_size) ||
(mem_read_count > 0 &&
m2f_count >= mem_read_count))) begin
m2f_activate <= 0;
end
if (mem_write_strobe) begin
mem_write_count <= mem_write_count + 1;
if (write_addr_inc) begin
mem_addr_in <= mem_addr_in + 1;
end
else if (write_addr_dec) begin
mem_addr_in <= mem_addr_in - 1;
end
end
//if (write_enable) begin
if (f2m_count < f2m_size) begin
if (f2m_activate) begin
f2m_strobe <= 1;
mem_write_strobe <= 1;
f2m_count <= f2m_count + 1;
if (f2m_count == 0) begin
first_write <= 1;
end
end
end
else begin
f2m_activate <= 0;
end
//end
if (mem_read_count < local_read_size) begin
if (read_enable) begin
if ((m2f_activate > 0) && (m2f_count < m2f_size)) begin
m2f_count <= m2f_count + 1;
mem_read_strobe <= 1;
mem_read_count <= mem_read_count + 1;
end
end
end
if (m2f_strobe) begin
prev_m2f_data <= m2f_data;
end
prev_f2m_data <= f2m_data;
prev_write_enable <= write_enable;
prev_read_enable <= read_enable;
end
end
endmodule
|
// niosii_mm_interconnect_0_avalon_st_adapter_005.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii_mm_interconnect_0_avalon_st_adapter_005 #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
niosii_mm_interconnect_0_avalon_st_adapter_005_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module c1_wait(
input CLK_68KCLK, nAS,
input nROM_ZONE, nPORT_ZONE, nCARD_ZONE,
input nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
output nDTACK
);
reg [1:0] WAIT_CNT;
//assign nPDTACK = ~(nPORT_ZONE | PDTACK); // Really a NOR ? May stall CPU if PDTACK = GND
assign nDTACK = nAS | |{WAIT_CNT}; // Is it nVALID instead of nAS ?
//assign nCLK_68KCLK = ~nCLK_68KCLK;
always @(negedge CLK_68KCLK)
begin
if (!nAS)
begin
// Count down only when nAS low
if (WAIT_CNT) WAIT_CNT <= WAIT_CNT - 1'b1;
end
else
begin
if (!nROM_ZONE)
WAIT_CNT <= ~nROMWAIT; // 0~1 or 1~2 wait cycles ?
else if (!nPORT_ZONE)
WAIT_CNT <= ~{nPWAIT0, nPWAIT1}; // Needs checking
else if (!nCARD_ZONE)
WAIT_CNT <= 2; // MAME and mvstech says so, to check
else
WAIT_CNT <= 0;
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: fr_cycle_shifter.v
//
// The fr-cycle shifter shifts the input data by X number of full-rate-cycles, where X is specified by the shift_by port.
// datain is a bus that combines data of multiple full rate cycles, in specific time order. For example,
// in a quarter-rate system, the datain bus must be ordered as {T3, T2, T1, T0}, where Ty represents the y'th fr-cycle
// data item, of width DATA_WIDTH. The following illustrates outputs at the dataout port for various values of shift_by.
// "__" means don't-care.
//
// shift_by dataout in current cycle dataout in next clock cycle
// 00 {T3, T2, T1, T0} {__, __, __, __}
// 01 {T2, T1, T0, __} {__, __, __, T3}
// 10 {T1, T0, __, __} {__, __, T3, T2}
// 11 {T0, __, __, __} {__, T3, T2, T1}
//
// In full-rate or half-rate systems, only the least-significant bit of shift-by has an effect
// (i.e. you can only shift by 0 or 1 fr-cycle).
// In quarter-rate systems, all bits of shift_by are used (i.e. you can shift by 0, 1, 2, or 3 fr-cycles).
//
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module altera_mem_if_ddr3_phy_0001_fr_cycle_shifter(
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DATA_WIDTH = "";
parameter REG_POST_RESET_HIGH = "false";
localparam RATE_MULT = 2;
localparam FULL_DATA_WIDTH = DATA_WIDTH*RATE_MULT;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input clk;
input reset_n;
input [1:0] shift_by;
input [FULL_DATA_WIDTH-1:0] datain;
output [FULL_DATA_WIDTH-1:0] dataout;
reg [FULL_DATA_WIDTH-1:0] datain_r;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n) begin
if (REG_POST_RESET_HIGH == "true")
datain_r <= {FULL_DATA_WIDTH{1'b1}};
else
datain_r <= {FULL_DATA_WIDTH{1'b0}};
end else begin
datain_r <= datain;
end
end
wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
assign dataout = (shift_by[0] == 1'b1) ? {datain_t0, datain_r_t1} : {datain_t1, datain_t0};
endmodule
|
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