text
stringlengths 938
1.05M
|
|---|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4BB_TB_V
`define SKY130_FD_SC_HS__AND4BB_TB_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and4bb.v"
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A_N = 1'b1;
#160 B_N = 1'b1;
#180 C = 1'b1;
#200 D = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A_N = 1'b0;
#280 B_N = 1'b0;
#300 C = 1'b0;
#320 D = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 D = 1'b1;
#440 C = 1'b1;
#460 B_N = 1'b1;
#480 A_N = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 D = 1'bx;
#560 C = 1'bx;
#580 B_N = 1'bx;
#600 A_N = 1'bx;
end
sky130_fd_sc_hs__and4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4BB_TB_V
|
`include "constants.vh"
`default_nettype none
module ram_sync_nolatch_2r1w #(
parameter BRAM_ADDR_WIDTH = `ADDR_LEN,
parameter BRAM_DATA_WIDTH = `DATA_LEN,
parameter DATA_DEPTH = 32
)
(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
input wire [BRAM_ADDR_WIDTH-1:0] waddr,
input wire [BRAM_DATA_WIDTH-1:0] wdata,
input wire we
);
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
integer i;
assign rdata1 = mem[raddr1];
assign rdata2 = mem[raddr2];
always @ (posedge clk) begin
if (we)
mem[waddr] <= wdata;
end
endmodule // ram_sync_nolatch_2r1w
module ram_sync_nolatch_2r2w #(
parameter BRAM_ADDR_WIDTH = `ADDR_LEN,
parameter BRAM_DATA_WIDTH = `DATA_LEN,
parameter DATA_DEPTH = 32
)
(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
input wire [BRAM_ADDR_WIDTH-1:0] waddr1,
input wire [BRAM_ADDR_WIDTH-1:0] waddr2,
input wire [BRAM_DATA_WIDTH-1:0] wdata1,
input wire [BRAM_DATA_WIDTH-1:0] wdata2,
input wire we1,
input wire we2
);
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
assign rdata1 = mem[raddr1];
assign rdata2 = mem[raddr2];
always @ (posedge clk) begin
if (we1)
mem[waddr1] <= wdata1;
if (we2)
mem[waddr2] <= wdata2;
end
endmodule // ram_sync_nolatch_2r2w
/*
module ram_sync_nolatch_4r1w(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
input wire [BRAM_ADDR_WIDTH-1:0] raddr3,
input wire [BRAM_ADDR_WIDTH-1:0] raddr4,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
input wire [BRAM_ADDR_WIDTH-1:0] waddr,
input wire [BRAM_DATA_WIDTH-1:0] wdata,
input wire we
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
ram_sync_nolatch_2r1w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr(waddr),
.wdata(wdata),
.we(we)
);
ram_sync_nolatch_2r1w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr(waddr),
.wdata(wdata),
.we(we)
);
endmodule //ram_sync_nolatch_4r1w
*/
module ram_sync_nolatch_4r2w #(
parameter BRAM_ADDR_WIDTH = `ADDR_LEN,
parameter BRAM_DATA_WIDTH = `DATA_LEN,
parameter DATA_DEPTH = 32
)
(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
input wire [BRAM_ADDR_WIDTH-1:0] raddr3,
input wire [BRAM_ADDR_WIDTH-1:0] raddr4,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
input wire [BRAM_ADDR_WIDTH-1:0] waddr1,
input wire [BRAM_ADDR_WIDTH-1:0] waddr2,
input wire [BRAM_DATA_WIDTH-1:0] wdata1,
input wire [BRAM_DATA_WIDTH-1:0] wdata2,
input wire we1,
input wire we2
);
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
assign rdata1 = mem[raddr1];
assign rdata2 = mem[raddr2];
assign rdata3 = mem[raddr3];
assign rdata4 = mem[raddr4];
always @ (posedge clk) begin
if (we1)
mem[waddr1] <= wdata1;
if (we2)
mem[waddr2] <= wdata2;
end
endmodule // ram_sync_nolatch_4r2w
/*
module ram_sync_nolatch_6r2w(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
input wire [BRAM_ADDR_WIDTH-1:0] raddr3,
input wire [BRAM_ADDR_WIDTH-1:0] raddr4,
input wire [BRAM_ADDR_WIDTH-1:0] raddr5,
input wire [BRAM_ADDR_WIDTH-1:0] raddr6,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
output wire [BRAM_DATA_WIDTH-1:0] rdata5,
output wire [BRAM_DATA_WIDTH-1:0] rdata6,
input wire [BRAM_ADDR_WIDTH-1:0] waddr1,
input wire [BRAM_ADDR_WIDTH-1:0] waddr2,
input wire [BRAM_DATA_WIDTH-1:0] wdata1,
input wire [BRAM_DATA_WIDTH-1:0] wdata2,
input wire we1,
input wire we2
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
ram_sync_nolatch_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_nolatch_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_nolatch_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem2(
.clk(clk),
.raddr1(raddr5),
.raddr2(raddr6),
.rdata1(rdata5),
.rdata2(rdata6),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
endmodule // ram_sync_nolatch_6r2w
*/
`default_nettype wire
|
module Prescaler(ins_o,ins_i,icm_i,rst_i,clk_i);
output ins_o;
input ins_i;
input [2:0] icm_i;
input rst_i;
input clk_i;
reg ins_o;
reg next_ins_o_reg;
reg [4:0] threshold_reg;
reg [4:0] next_counter_reg;
reg [4:0] counter_reg;
//threshold:
always @(icm_i )
begin
case(icm_i )
'h1, 'h2, 'h3 :
begin
threshold_reg =('h1);
end
'h4, 'h6 :
begin
threshold_reg =('h4);
end
'h5, 'h7 :
begin
threshold_reg =('h10);
end
default:
begin
threshold_reg =('h0);
end
endcase
end
//on_change:
always @(threshold_reg or counter_reg or ins_i )
begin
if (counter_reg ==threshold_reg )
begin
next_ins_o_reg =(0);
next_counter_reg =(0);
end
else if (ins_i )
begin
next_ins_o_reg =(1);
next_counter_reg =(counter_reg +1);
end
end
//registers:
always @(posedge clk_i or posedge rst_i )
begin
if (!rst_i &&clk_i )
begin
counter_reg <=(next_counter_reg );
ins_o <=(next_ins_o_reg );
end
else
begin
counter_reg <=(0);
ins_o <=(0);
end
end
endmodule
|
//Circuit which generates Fibonacci numbers
module fibonacci (
clk, //clock
reset, //reset the Multiplier
n, //Fibonacci number to calculate
result, //result of fibonacci calculation
ready //signals if the result is ready
);
parameter inBits = 8; //No of bits for n
parameter outBits = 16; //No of bits of Fib number
//----Input Ports---
input clk;
input reset;
input [inBits-1:0] n;
//---Output Ports---
output reg [outBits-1:0] result;
output reg ready;
//---Internal Registers---
reg [outBits-1:0] last;
reg [inBits-1:0] no;
reg [inBits-1:0] count;
always @(posedge clk) begin
if (reset) begin
result <= 16'b0;
last <= 16'b0;
no <= n;
count <= 16'b0;
//0th fibonacci number is 0, need to generate 1 afterwards
end else begin
if (result == 0 && !ready) begin
result <= 1;
end else if (ready) begin
result <= result;
end else begin
result <= result + last;
end
last <= result;
count <= count + 1;
end
ready <= count >= no;
$display("reset %b, count %d, result %d, ready %b, no %d, last %d",reset, count, result, ready, no, last);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
//
// Create Date: 07/11/2012
// Module Name: digit_select
// Project Name: PmodGYRO_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: Selects current digit to display on SSD.
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added Comments and Converted to Verilog (Josh Sackos)
//////////////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module digit_select(
d1,
d2,
d3,
d4,
control,
digit
);
// ==============================================================================
// Port Declarations
// ==============================================================================
input [3:0] d1;
input [3:0] d2;
input [3:0] d3;
input [3:0] d4;
input [1:0] control;
output [3:0] digit;
// ==============================================================================
// Implementation
// ==============================================================================
// Assign digit to display on SSD cathodes
assign digit = (control == 2'b11) ? d1 :
(control == 2'b10) ? d2 :
(control == 2'b01) ? d3 :
d4;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_4_V
`define SKY130_FD_SC_LP__O32A_4_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_4 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_4_V
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_processing_system7_bfm.v
*
* Date : 2012-11
*
* Description : Processing_system7_bfm Top (zynq_bfm top)
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_processing_system7_bfm
(
CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_EXT_INTIN,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_EXT_INTIN,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TD_I,
PJTAG_TD_T,
PJTAG_TD_O,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
USB0_PORT_INDCTL,
USB1_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB1_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_AWREADY,
S_AXI_ACP_ARREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA0_DRTYPE,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA1_DRTYPE,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_DRVALID,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA2_DRTYPE,
DMA3_DRTYPE,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG,
FTMT_F2P_TRIGACK,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK,
FTMT_P2F_TRIG,
FTMT_P2F_DEBUG,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FPGA_IDLE_N,
DDR_ARB,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
MIO,
DDR_Clk,
DDR_Clk_n,
DDR_CKE,
DDR_CS_n,
DDR_RAS_n,
DDR_CAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_ODT,
DDR_DRSTB,
DDR_DQ,
DDR_DM,
DDR_DQS,
DDR_DQS_n,
DDR_VRN,
DDR_VRP,
PS_SRSTB,
PS_CLK,
PS_PORB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1
);
/* parameters for gen_clk */
parameter C_FCLK_CLK0_FREQ = 50;
parameter C_FCLK_CLK1_FREQ = 50;
parameter C_FCLK_CLK3_FREQ = 50;
parameter C_FCLK_CLK2_FREQ = 50;
parameter C_HIGH_OCM_EN = 0;
/* parameters for HP ports */
parameter C_USE_S_AXI_HP0 = 0;
parameter C_USE_S_AXI_HP1 = 0;
parameter C_USE_S_AXI_HP2 = 0;
parameter C_USE_S_AXI_HP3 = 0;
parameter C_S_AXI_HP0_DATA_WIDTH = 32;
parameter C_S_AXI_HP1_DATA_WIDTH = 32;
parameter C_S_AXI_HP2_DATA_WIDTH = 32;
parameter C_S_AXI_HP3_DATA_WIDTH = 32;
parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12;
parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12;
parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0;
parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0;
/* Do we need these
parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */
parameter C_S_AXI_HP0_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP1_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP2_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP3_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP0_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_HP1_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_HP2_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_HP3_HIGHADDR = 32'hFFFF_FFFF;
/* parameters for GP and ACP ports */
parameter C_USE_M_AXI_GP0 = 0;
parameter C_USE_M_AXI_GP1 = 0;
parameter C_USE_S_AXI_GP0 = 1;
parameter C_USE_S_AXI_GP1 = 1;
/* Do we need this?
parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0;
parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/
parameter C_S_AXI_GP0_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_GP1_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_GP0_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_GP1_HIGHADDR = 32'hFFFF_FFFF;
parameter C_USE_S_AXI_ACP = 1;
parameter C_S_AXI_ACP_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_ACP_HIGHADDR = 32'hFFFF_FFFF;
`include "processing_system7_bfm_v2_0_local_params.v"
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0] ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_EXT_INTIN;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input [7:0] ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0] ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_EXT_INTIN;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input [7:0] ENET1_GMII_RXD;
input [63:0] GPIO_I;
output [63:0] GPIO_O;
output [63:0] GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TD_I;
output PJTAG_TD_T;
output PJTAG_TD_O;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0] SDIO0_DATA_I;
output [3:0] SDIO0_DATA_O;
output [3:0] SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0] SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0] SDIO1_DATA_I;
output [3:0] SDIO1_DATA_O;
output [3:0] SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0] SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [31:0] TRACE_DATA;
output [1:0] USB0_PORT_INDCTL;
output [1:0] USB1_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
output USB1_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID;
output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID;
output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID;
output [1:0] M_AXI_GP0_ARBURST;
output [1:0] M_AXI_GP0_ARLOCK;
output [2:0] M_AXI_GP0_ARSIZE;
output [1:0] M_AXI_GP0_AWBURST;
output [1:0] M_AXI_GP0_AWLOCK;
output [2:0] M_AXI_GP0_AWSIZE;
output [2:0] M_AXI_GP0_ARPROT;
output [2:0] M_AXI_GP0_AWPROT;
output [31:0] M_AXI_GP0_ARADDR;
output [31:0] M_AXI_GP0_AWADDR;
output [31:0] M_AXI_GP0_WDATA;
output [3:0] M_AXI_GP0_ARCACHE;
output [3:0] M_AXI_GP0_ARLEN;
output [3:0] M_AXI_GP0_ARQOS;
output [3:0] M_AXI_GP0_AWCACHE;
output [3:0] M_AXI_GP0_AWLEN;
output [3:0] M_AXI_GP0_AWQOS;
output [3:0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID;
input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID;
input [1:0] M_AXI_GP0_BRESP;
input [1:0] M_AXI_GP0_RRESP;
input [31:0] M_AXI_GP0_RDATA;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID;
output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID;
output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID;
output [1:0] M_AXI_GP1_ARBURST;
output [1:0] M_AXI_GP1_ARLOCK;
output [2:0] M_AXI_GP1_ARSIZE;
output [1:0] M_AXI_GP1_AWBURST;
output [1:0] M_AXI_GP1_AWLOCK;
output [2:0] M_AXI_GP1_AWSIZE;
output [2:0] M_AXI_GP1_ARPROT;
output [2:0] M_AXI_GP1_AWPROT;
output [31:0] M_AXI_GP1_ARADDR;
output [31:0] M_AXI_GP1_AWADDR;
output [31:0] M_AXI_GP1_WDATA;
output [3:0] M_AXI_GP1_ARCACHE;
output [3:0] M_AXI_GP1_ARLEN;
output [3:0] M_AXI_GP1_ARQOS;
output [3:0] M_AXI_GP1_AWCACHE;
output [3:0] M_AXI_GP1_AWLEN;
output [3:0] M_AXI_GP1_AWQOS;
output [3:0] M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID;
input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID;
input [1:0] M_AXI_GP1_BRESP;
input [1:0] M_AXI_GP1_RRESP;
input [31:0] M_AXI_GP1_RDATA;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0] S_AXI_GP0_BRESP;
output [1:0] S_AXI_GP0_RRESP;
output [31:0] S_AXI_GP0_RDATA;
output [5:0] S_AXI_GP0_BID;
output [5:0] S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0] S_AXI_GP0_ARBURST;
input [1:0] S_AXI_GP0_ARLOCK;
input [2:0] S_AXI_GP0_ARSIZE;
input [1:0] S_AXI_GP0_AWBURST;
input [1:0] S_AXI_GP0_AWLOCK;
input [2:0] S_AXI_GP0_AWSIZE;
input [2:0] S_AXI_GP0_ARPROT;
input [2:0] S_AXI_GP0_AWPROT;
input [31:0] S_AXI_GP0_ARADDR;
input [31:0] S_AXI_GP0_AWADDR;
input [31:0] S_AXI_GP0_WDATA;
input [3:0] S_AXI_GP0_ARCACHE;
input [3:0] S_AXI_GP0_ARLEN;
input [3:0] S_AXI_GP0_ARQOS;
input [3:0] S_AXI_GP0_AWCACHE;
input [3:0] S_AXI_GP0_AWLEN;
input [3:0] S_AXI_GP0_AWQOS;
input [3:0] S_AXI_GP0_WSTRB;
input [5:0] S_AXI_GP0_ARID;
input [5:0] S_AXI_GP0_AWID;
input [5:0] S_AXI_GP0_WID;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0] S_AXI_GP1_BRESP;
output [1:0] S_AXI_GP1_RRESP;
output [31:0] S_AXI_GP1_RDATA;
output [5:0] S_AXI_GP1_BID;
output [5:0] S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0] S_AXI_GP1_ARBURST;
input [1:0] S_AXI_GP1_ARLOCK;
input [2:0] S_AXI_GP1_ARSIZE;
input [1:0] S_AXI_GP1_AWBURST;
input [1:0] S_AXI_GP1_AWLOCK;
input [2:0] S_AXI_GP1_AWSIZE;
input [2:0] S_AXI_GP1_ARPROT;
input [2:0] S_AXI_GP1_AWPROT;
input [31:0] S_AXI_GP1_ARADDR;
input [31:0] S_AXI_GP1_AWADDR;
input [31:0] S_AXI_GP1_WDATA;
input [3:0] S_AXI_GP1_ARCACHE;
input [3:0] S_AXI_GP1_ARLEN;
input [3:0] S_AXI_GP1_ARQOS;
input [3:0] S_AXI_GP1_AWCACHE;
input [3:0] S_AXI_GP1_AWLEN;
input [3:0] S_AXI_GP1_AWQOS;
input [3:0] S_AXI_GP1_WSTRB;
input [5:0] S_AXI_GP1_ARID;
input [5:0] S_AXI_GP1_AWID;
input [5:0] S_AXI_GP1_WID;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0] S_AXI_ACP_BRESP;
output [1:0] S_AXI_ACP_RRESP;
output [2:0] S_AXI_ACP_BID;
output [2:0] S_AXI_ACP_RID;
output [63:0] S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0] S_AXI_ACP_ARID;
input [2:0] S_AXI_ACP_ARPROT;
input [2:0] S_AXI_ACP_AWID;
input [2:0] S_AXI_ACP_AWPROT;
input [2:0] S_AXI_ACP_WID;
input [31:0] S_AXI_ACP_ARADDR;
input [31:0] S_AXI_ACP_AWADDR;
input [3:0] S_AXI_ACP_ARCACHE;
input [3:0] S_AXI_ACP_ARLEN;
input [3:0] S_AXI_ACP_ARQOS;
input [3:0] S_AXI_ACP_AWCACHE;
input [3:0] S_AXI_ACP_AWLEN;
input [3:0] S_AXI_ACP_AWQOS;
input [1:0] S_AXI_ACP_ARBURST;
input [1:0] S_AXI_ACP_ARLOCK;
input [2:0] S_AXI_ACP_ARSIZE;
input [1:0] S_AXI_ACP_AWBURST;
input [1:0] S_AXI_ACP_AWLOCK;
input [2:0] S_AXI_ACP_AWSIZE;
input [4:0] S_AXI_ACP_ARUSER;
input [4:0] S_AXI_ACP_AWUSER;
input [63:0] S_AXI_ACP_WDATA;
input [7:0] S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0] S_AXI_HP0_BRESP;
output [1:0] S_AXI_HP0_RRESP;
output [5:0] S_AXI_HP0_BID;
output [5:0] S_AXI_HP0_RID;
output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA;
output [7:0] S_AXI_HP0_RCOUNT;
output [7:0] S_AXI_HP0_WCOUNT;
output [2:0] S_AXI_HP0_RACOUNT;
output [5:0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0] S_AXI_HP0_ARBURST;
input [1:0] S_AXI_HP0_ARLOCK;
input [2:0] S_AXI_HP0_ARSIZE;
input [1:0] S_AXI_HP0_AWBURST;
input [1:0] S_AXI_HP0_AWLOCK;
input [2:0] S_AXI_HP0_AWSIZE;
input [2:0] S_AXI_HP0_ARPROT;
input [2:0] S_AXI_HP0_AWPROT;
input [31:0] S_AXI_HP0_ARADDR;
input [31:0] S_AXI_HP0_AWADDR;
input [3:0] S_AXI_HP0_ARCACHE;
input [3:0] S_AXI_HP0_ARLEN;
input [3:0] S_AXI_HP0_ARQOS;
input [3:0] S_AXI_HP0_AWCACHE;
input [3:0] S_AXI_HP0_AWLEN;
input [3:0] S_AXI_HP0_AWQOS;
input [5:0] S_AXI_HP0_ARID;
input [5:0] S_AXI_HP0_AWID;
input [5:0] S_AXI_HP0_WID;
input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA;
input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0] S_AXI_HP1_BRESP;
output [1:0] S_AXI_HP1_RRESP;
output [5:0] S_AXI_HP1_BID;
output [5:0] S_AXI_HP1_RID;
output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA;
output [7:0] S_AXI_HP1_RCOUNT;
output [7:0] S_AXI_HP1_WCOUNT;
output [2:0] S_AXI_HP1_RACOUNT;
output [5:0] S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0] S_AXI_HP1_ARBURST;
input [1:0] S_AXI_HP1_ARLOCK;
input [2:0] S_AXI_HP1_ARSIZE;
input [1:0] S_AXI_HP1_AWBURST;
input [1:0] S_AXI_HP1_AWLOCK;
input [2:0] S_AXI_HP1_AWSIZE;
input [2:0] S_AXI_HP1_ARPROT;
input [2:0] S_AXI_HP1_AWPROT;
input [31:0] S_AXI_HP1_ARADDR;
input [31:0] S_AXI_HP1_AWADDR;
input [3:0] S_AXI_HP1_ARCACHE;
input [3:0] S_AXI_HP1_ARLEN;
input [3:0] S_AXI_HP1_ARQOS;
input [3:0] S_AXI_HP1_AWCACHE;
input [3:0] S_AXI_HP1_AWLEN;
input [3:0] S_AXI_HP1_AWQOS;
input [5:0] S_AXI_HP1_ARID;
input [5:0] S_AXI_HP1_AWID;
input [5:0] S_AXI_HP1_WID;
input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA;
input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0] S_AXI_HP2_BRESP;
output [1:0] S_AXI_HP2_RRESP;
output [5:0] S_AXI_HP2_BID;
output [5:0] S_AXI_HP2_RID;
output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA;
output [7:0] S_AXI_HP2_RCOUNT;
output [7:0] S_AXI_HP2_WCOUNT;
output [2:0] S_AXI_HP2_RACOUNT;
output [5:0] S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0] S_AXI_HP2_ARBURST;
input [1:0] S_AXI_HP2_ARLOCK;
input [2:0] S_AXI_HP2_ARSIZE;
input [1:0] S_AXI_HP2_AWBURST;
input [1:0] S_AXI_HP2_AWLOCK;
input [2:0] S_AXI_HP2_AWSIZE;
input [2:0] S_AXI_HP2_ARPROT;
input [2:0] S_AXI_HP2_AWPROT;
input [31:0] S_AXI_HP2_ARADDR;
input [31:0] S_AXI_HP2_AWADDR;
input [3:0] S_AXI_HP2_ARCACHE;
input [3:0] S_AXI_HP2_ARLEN;
input [3:0] S_AXI_HP2_ARQOS;
input [3:0] S_AXI_HP2_AWCACHE;
input [3:0] S_AXI_HP2_AWLEN;
input [3:0] S_AXI_HP2_AWQOS;
input [5:0] S_AXI_HP2_ARID;
input [5:0] S_AXI_HP2_AWID;
input [5:0] S_AXI_HP2_WID;
input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA;
input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0] S_AXI_HP3_BRESP;
output [1:0] S_AXI_HP3_RRESP;
output [5:0] S_AXI_HP3_BID;
output [5:0] S_AXI_HP3_RID;
output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA;
output [7:0] S_AXI_HP3_RCOUNT;
output [7:0] S_AXI_HP3_WCOUNT;
output [2:0] S_AXI_HP3_RACOUNT;
output [5:0] S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0] S_AXI_HP3_ARBURST;
input [1:0] S_AXI_HP3_ARLOCK;
input [2:0] S_AXI_HP3_ARSIZE;
input [1:0] S_AXI_HP3_AWBURST;
input [1:0] S_AXI_HP3_AWLOCK;
input [2:0] S_AXI_HP3_AWSIZE;
input [2:0] S_AXI_HP3_ARPROT;
input [2:0] S_AXI_HP3_AWPROT;
input [31:0] S_AXI_HP3_ARADDR;
input [31:0] S_AXI_HP3_AWADDR;
input [3:0] S_AXI_HP3_ARCACHE;
input [3:0] S_AXI_HP3_ARLEN;
input [3:0] S_AXI_HP3_ARQOS;
input [3:0] S_AXI_HP3_AWCACHE;
input [3:0] S_AXI_HP3_AWLEN;
input [3:0] S_AXI_HP3_AWQOS;
input [5:0] S_AXI_HP3_ARID;
input [5:0] S_AXI_HP3_AWID;
input [5:0] S_AXI_HP3_WID;
input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA;
input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB;
output [1:0] DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input [1:0] DMA0_DRTYPE;
output [1:0] DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input [1:0] DMA1_DRTYPE;
output [1:0] DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_DRVALID;
output [1:0] DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input [1:0] DMA2_DRTYPE;
input [1:0] DMA3_DRTYPE;
input [31:0] FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0] FTMD_TRACEIN_ATID;
input [3:0] FTMT_F2P_TRIG;
output [3:0] FTMT_F2P_TRIGACK;
input [31:0] FTMT_F2P_DEBUG;
input [3:0] FTMT_P2F_TRIGACK;
output [3:0] FTMT_P2F_TRIG;
output [31:0] FTMT_P2F_DEBUG;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input FPGA_IDLE_N;
input [3:0] DDR_ARB;
input [irq_width-1:0] IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output EVENT_EVENTO;
output [1:0] EVENT_STANDBYWFE;
output [1:0] EVENT_STANDBYWFI;
input EVENT_EVENTI;
inout [53:0] MIO;
inout DDR_Clk;
inout DDR_Clk_n;
inout DDR_CKE;
inout DDR_CS_n;
inout DDR_RAS_n;
inout DDR_CAS_n;
output DDR_WEB;
inout [2:0] DDR_BankAddr;
inout [14:0] DDR_Addr;
inout DDR_ODT;
inout DDR_DRSTB;
inout [31:0] DDR_DQ;
inout [3:0] DDR_DM;
inout [3:0] DDR_DQS;
inout [3:0] DDR_DQS_n;
inout DDR_VRN;
inout DDR_VRP;
/* Reset Input & Clock Input */
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
/* Internal wires/nets used for connectivity */
wire net_rstn;
wire net_sw_clk;
wire net_ocm_clk;
wire net_arbiter_clk;
wire net_axi_mgp0_rstn;
wire net_axi_mgp1_rstn;
wire net_axi_gp0_rstn;
wire net_axi_gp1_rstn;
wire net_axi_hp0_rstn;
wire net_axi_hp1_rstn;
wire net_axi_hp2_rstn;
wire net_axi_hp3_rstn;
wire net_axi_acp_rstn;
wire [4:0] net_axi_acp_awuser;
wire [4:0] net_axi_acp_aruser;
/* Dummy */
assign net_axi_acp_awuser = S_AXI_ACP_AWUSER;
assign net_axi_acp_aruser = S_AXI_ACP_ARUSER;
/* Global variables */
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1;
/* local variable acting as semaphore for wait_mem_update and wait_reg_update task */
reg mem_update_key = 1;
reg reg_update_key_0 = 1;
reg reg_update_key_1 = 1;
/* assignments and semantic checks for unused ports */
`include "processing_system7_bfm_v2_0_unused_ports.v"
/* include api definition */
`include "processing_system7_bfm_v2_0_apis.v"
/* Reset Generator */
processing_system7_bfm_v2_0_gen_reset gen_rst(.por_rst_n(PS_PORB),
.sys_rst_n(PS_SRSTB),
.rst_out_n(net_rstn),
.m_axi_gp0_clk(M_AXI_GP0_ACLK),
.m_axi_gp1_clk(M_AXI_GP1_ACLK),
.s_axi_gp0_clk(S_AXI_GP0_ACLK),
.s_axi_gp1_clk(S_AXI_GP1_ACLK),
.s_axi_hp0_clk(S_AXI_HP0_ACLK),
.s_axi_hp1_clk(S_AXI_HP1_ACLK),
.s_axi_hp2_clk(S_AXI_HP2_ACLK),
.s_axi_hp3_clk(S_AXI_HP3_ACLK),
.s_axi_acp_clk(S_AXI_ACP_ACLK),
.m_axi_gp0_rstn(net_axi_mgp0_rstn),
.m_axi_gp1_rstn(net_axi_mgp1_rstn),
.s_axi_gp0_rstn(net_axi_gp0_rstn),
.s_axi_gp1_rstn(net_axi_gp1_rstn),
.s_axi_hp0_rstn(net_axi_hp0_rstn),
.s_axi_hp1_rstn(net_axi_hp1_rstn),
.s_axi_hp2_rstn(net_axi_hp2_rstn),
.s_axi_hp3_rstn(net_axi_hp3_rstn),
.s_axi_acp_rstn(net_axi_acp_rstn),
.fclk_reset3_n(FCLK_RESET3_N),
.fclk_reset2_n(FCLK_RESET2_N),
.fclk_reset1_n(FCLK_RESET1_N),
.fclk_reset0_n(FCLK_RESET0_N),
.fpga_acp_reset_n(), ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP)
.fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN),
.fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN),
.fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN),
.fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN),
.fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN),
.fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN),
.fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN),
.fpga_hp_s3_reset_n() ////S_AXI_HP3_ARESETN)
);
/* Clock Generator */
processing_system7_bfm_v2_0_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ)
gen_clk(.ps_clk(PS_CLK),
.sw_clk(net_sw_clk),
.fclk_clk3(FCLK_CLK3),
.fclk_clk2(FCLK_CLK2),
.fclk_clk1(FCLK_CLK1),
.fclk_clk0(FCLK_CLK0)
);
wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1;
wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1;
wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1;
wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1;
wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1;
wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1;
wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1;
wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1;
wire net_rd_req_reg_gp0, net_rd_req_reg_gp1;
wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1;
wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1;
wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1;
wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1;
wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1;
wire net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1;
wire net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1;
wire net_rd_dv_reg_gp0, net_rd_dv_reg_gp1;
wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1;
wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3;
wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3;
wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3;
wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3;
wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3;
wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3;
wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3;
wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3;
wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3;
wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3;
wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3;
wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3;
wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3;
wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3;
wire net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3;
wire net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3;
wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3;
wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp;
wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp;
wire [max_burst_bits-1:0] net_wr_data_acp;
wire [addr_width-1:0] net_wr_addr_acp;
wire [max_burst_bytes_width:0] net_wr_bytes_acp;
wire [axi_qos_width-1:0] net_wr_qos_acp;
wire net_rd_req_ddr_acp, net_rd_req_ocm_acp;
wire [addr_width-1:0] net_rd_addr_acp;
wire [max_burst_bytes_width:0] net_rd_bytes_acp;
wire [max_burst_bits-1:0] net_rd_data_ddr_acp;
wire [max_burst_bits-1:0] net_rd_data_ocm_acp;
wire net_rd_dv_ddr_acp,net_rd_dv_ocm_acp;
wire [axi_qos_width-1:0] net_rd_qos_acp;
wire ocm_wr_ack_port0;
wire ocm_wr_dv_port0;
wire ocm_rd_req_port0;
wire ocm_rd_dv_port0;
wire [addr_width-1:0] ocm_wr_addr_port0;
wire [max_burst_bits-1:0] ocm_wr_data_port0;
wire [max_burst_bytes_width:0] ocm_wr_bytes_port0;
wire [addr_width-1:0] ocm_rd_addr_port0;
wire [max_burst_bits-1:0] ocm_rd_data_port0;
wire [max_burst_bytes_width:0] ocm_rd_bytes_port0;
wire [axi_qos_width-1:0] ocm_wr_qos_port0;
wire [axi_qos_width-1:0] ocm_rd_qos_port0;
wire ocm_wr_ack_port1;
wire ocm_wr_dv_port1;
wire ocm_rd_req_port1;
wire ocm_rd_dv_port1;
wire [addr_width-1:0] ocm_wr_addr_port1;
wire [max_burst_bits-1:0] ocm_wr_data_port1;
wire [max_burst_bytes_width:0] ocm_wr_bytes_port1;
wire [addr_width-1:0] ocm_rd_addr_port1;
wire [max_burst_bits-1:0] ocm_rd_data_port1;
wire [max_burst_bytes_width:0] ocm_rd_bytes_port1;
wire [axi_qos_width-1:0] ocm_wr_qos_port1;
wire [axi_qos_width-1:0] ocm_rd_qos_port1;
wire ddr_wr_ack_port0;
wire ddr_wr_dv_port0;
wire ddr_rd_req_port0;
wire ddr_rd_dv_port0;
wire[addr_width-1:0] ddr_wr_addr_port0;
wire[max_burst_bits-1:0] ddr_wr_data_port0;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port0;
wire[addr_width-1:0] ddr_rd_addr_port0;
wire[max_burst_bits-1:0] ddr_rd_data_port0;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port0;
wire [axi_qos_width-1:0] ddr_wr_qos_port0;
wire [axi_qos_width-1:0] ddr_rd_qos_port0;
wire ddr_wr_ack_port1;
wire ddr_wr_dv_port1;
wire ddr_rd_req_port1;
wire ddr_rd_dv_port1;
wire[addr_width-1:0] ddr_wr_addr_port1;
wire[max_burst_bits-1:0] ddr_wr_data_port1;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port1;
wire[addr_width-1:0] ddr_rd_addr_port1;
wire[max_burst_bits-1:0] ddr_rd_data_port1;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port1;
wire[axi_qos_width-1:0] ddr_wr_qos_port1;
wire[axi_qos_width-1:0] ddr_rd_qos_port1;
wire ddr_wr_ack_port2;
wire ddr_wr_dv_port2;
wire ddr_rd_req_port2;
wire ddr_rd_dv_port2;
wire[addr_width-1:0] ddr_wr_addr_port2;
wire[max_burst_bits-1:0] ddr_wr_data_port2;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port2;
wire[addr_width-1:0] ddr_rd_addr_port2;
wire[max_burst_bits-1:0] ddr_rd_data_port2;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port2;
wire[axi_qos_width-1:0] ddr_wr_qos_port2;
wire[axi_qos_width-1:0] ddr_rd_qos_port2;
wire ddr_wr_ack_port3;
wire ddr_wr_dv_port3;
wire ddr_rd_req_port3;
wire ddr_rd_dv_port3;
wire[addr_width-1:0] ddr_wr_addr_port3;
wire[max_burst_bits-1:0] ddr_wr_data_port3;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port3;
wire[addr_width-1:0] ddr_rd_addr_port3;
wire[max_burst_bits-1:0] ddr_rd_data_port3;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port3;
wire[axi_qos_width-1:0] ddr_wr_qos_port3;
wire[axi_qos_width-1:0] ddr_rd_qos_port3;
wire reg_rd_req_port0;
wire reg_rd_dv_port0;
wire[addr_width-1:0] reg_rd_addr_port0;
wire[max_burst_bits-1:0] reg_rd_data_port0;
wire[max_burst_bytes_width:0] reg_rd_bytes_port0;
wire [axi_qos_width-1:0] reg_rd_qos_port0;
wire reg_rd_req_port1;
wire reg_rd_dv_port1;
wire[addr_width-1:0] reg_rd_addr_port1;
wire[max_burst_bits-1:0] reg_rd_data_port1;
wire[max_burst_bytes_width:0] reg_rd_bytes_port1;
wire [axi_qos_width-1:0] reg_rd_qos_port1;
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
function [5:0] compress_id;
input [11:0] id;
begin
compress_id = id[5:0];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
uncompress_id = {6'b110000, id[5:0]};
end
endfunction
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
processing_system7_bfm_v2_0_interconnect_model icm (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
.w_qos_gp0(net_wr_qos_gp0),
.w_qos_gp1(net_wr_qos_gp1),
.w_qos_hp0(net_wr_qos_hp0),
.w_qos_hp1(net_wr_qos_hp1),
.w_qos_hp2(net_wr_qos_hp2),
.w_qos_hp3(net_wr_qos_hp3),
.r_qos_gp0(net_rd_qos_gp0),
.r_qos_gp1(net_rd_qos_gp1),
.r_qos_hp0(net_rd_qos_hp0),
.r_qos_hp1(net_rd_qos_hp1),
.r_qos_hp2(net_rd_qos_hp2),
.r_qos_hp3(net_rd_qos_hp3),
/* GP Slave ports access */
.wr_ack_ddr_gp0(net_wr_ack_ddr_gp0),
.wr_ack_ocm_gp0(net_wr_ack_ocm_gp0),
.wr_data_gp0(net_wr_data_gp0),
.wr_addr_gp0(net_wr_addr_gp0),
.wr_bytes_gp0(net_wr_bytes_gp0),
.wr_dv_ddr_gp0(net_wr_dv_ddr_gp0),
.wr_dv_ocm_gp0(net_wr_dv_ocm_gp0),
.rd_req_ddr_gp0(net_rd_req_ddr_gp0),
.rd_req_ocm_gp0(net_rd_req_ocm_gp0),
.rd_req_reg_gp0(net_rd_req_reg_gp0),
.rd_addr_gp0(net_rd_addr_gp0),
.rd_bytes_gp0(net_rd_bytes_gp0),
.rd_data_ddr_gp0(net_rd_data_ddr_gp0),
.rd_data_ocm_gp0(net_rd_data_ocm_gp0),
.rd_data_reg_gp0(net_rd_data_reg_gp0),
.rd_dv_ddr_gp0(net_rd_dv_ddr_gp0),
.rd_dv_ocm_gp0(net_rd_dv_ocm_gp0),
.rd_dv_reg_gp0(net_rd_dv_reg_gp0),
.wr_ack_ddr_gp1(net_wr_ack_ddr_gp1),
.wr_ack_ocm_gp1(net_wr_ack_ocm_gp1),
.wr_data_gp1(net_wr_data_gp1),
.wr_addr_gp1(net_wr_addr_gp1),
.wr_bytes_gp1(net_wr_bytes_gp1),
.wr_dv_ddr_gp1(net_wr_dv_ddr_gp1),
.wr_dv_ocm_gp1(net_wr_dv_ocm_gp1),
.rd_req_ddr_gp1(net_rd_req_ddr_gp1),
.rd_req_ocm_gp1(net_rd_req_ocm_gp1),
.rd_req_reg_gp1(net_rd_req_reg_gp1),
.rd_addr_gp1(net_rd_addr_gp1),
.rd_bytes_gp1(net_rd_bytes_gp1),
.rd_data_ddr_gp1(net_rd_data_ddr_gp1),
.rd_data_ocm_gp1(net_rd_data_ocm_gp1),
.rd_data_reg_gp1(net_rd_data_reg_gp1),
.rd_dv_ddr_gp1(net_rd_dv_ddr_gp1),
.rd_dv_ocm_gp1(net_rd_dv_ocm_gp1),
.rd_dv_reg_gp1(net_rd_dv_reg_gp1),
/* HP Slave ports access */
.wr_ack_ddr_hp0(net_wr_ack_ddr_hp0),
.wr_ack_ocm_hp0(net_wr_ack_ocm_hp0),
.wr_data_hp0(net_wr_data_hp0),
.wr_addr_hp0(net_wr_addr_hp0),
.wr_bytes_hp0(net_wr_bytes_hp0),
.wr_dv_ddr_hp0(net_wr_dv_ddr_hp0),
.wr_dv_ocm_hp0(net_wr_dv_ocm_hp0),
.rd_req_ddr_hp0(net_rd_req_ddr_hp0),
.rd_req_ocm_hp0(net_rd_req_ocm_hp0),
.rd_addr_hp0(net_rd_addr_hp0),
.rd_bytes_hp0(net_rd_bytes_hp0),
.rd_data_ddr_hp0(net_rd_data_ddr_hp0),
.rd_data_ocm_hp0(net_rd_data_ocm_hp0),
.rd_dv_ddr_hp0(net_rd_dv_ddr_hp0),
.rd_dv_ocm_hp0(net_rd_dv_ocm_hp0),
.wr_ack_ddr_hp1(net_wr_ack_ddr_hp1),
.wr_ack_ocm_hp1(net_wr_ack_ocm_hp1),
.wr_data_hp1(net_wr_data_hp1),
.wr_addr_hp1(net_wr_addr_hp1),
.wr_bytes_hp1(net_wr_bytes_hp1),
.wr_dv_ddr_hp1(net_wr_dv_ddr_hp1),
.wr_dv_ocm_hp1(net_wr_dv_ocm_hp1),
.rd_req_ddr_hp1(net_rd_req_ddr_hp1),
.rd_req_ocm_hp1(net_rd_req_ocm_hp1),
.rd_addr_hp1(net_rd_addr_hp1),
.rd_bytes_hp1(net_rd_bytes_hp1),
.rd_data_ddr_hp1(net_rd_data_ddr_hp1),
.rd_data_ocm_hp1(net_rd_data_ocm_hp1),
.rd_dv_ocm_hp1(net_rd_dv_ocm_hp1),
.rd_dv_ddr_hp1(net_rd_dv_ddr_hp1),
.wr_ack_ddr_hp2(net_wr_ack_ddr_hp2),
.wr_ack_ocm_hp2(net_wr_ack_ocm_hp2),
.wr_data_hp2(net_wr_data_hp2),
.wr_addr_hp2(net_wr_addr_hp2),
.wr_bytes_hp2(net_wr_bytes_hp2),
.wr_dv_ocm_hp2(net_wr_dv_ocm_hp2),
.wr_dv_ddr_hp2(net_wr_dv_ddr_hp2),
.rd_req_ddr_hp2(net_rd_req_ddr_hp2),
.rd_req_ocm_hp2(net_rd_req_ocm_hp2),
.rd_addr_hp2(net_rd_addr_hp2),
.rd_bytes_hp2(net_rd_bytes_hp2),
.rd_data_ddr_hp2(net_rd_data_ddr_hp2),
.rd_data_ocm_hp2(net_rd_data_ocm_hp2),
.rd_dv_ddr_hp2(net_rd_dv_ddr_hp2),
.rd_dv_ocm_hp2(net_rd_dv_ocm_hp2),
.wr_ack_ocm_hp3(net_wr_ack_ocm_hp3),
.wr_ack_ddr_hp3(net_wr_ack_ddr_hp3),
.wr_data_hp3(net_wr_data_hp3),
.wr_addr_hp3(net_wr_addr_hp3),
.wr_bytes_hp3(net_wr_bytes_hp3),
.wr_dv_ddr_hp3(net_wr_dv_ddr_hp3),
.wr_dv_ocm_hp3(net_wr_dv_ocm_hp3),
.rd_req_ddr_hp3(net_rd_req_ddr_hp3),
.rd_req_ocm_hp3(net_rd_req_ocm_hp3),
.rd_addr_hp3(net_rd_addr_hp3),
.rd_bytes_hp3(net_rd_bytes_hp3),
.rd_data_ddr_hp3(net_rd_data_ddr_hp3),
.rd_data_ocm_hp3(net_rd_data_ocm_hp3),
.rd_dv_ddr_hp3(net_rd_dv_ddr_hp3),
.rd_dv_ocm_hp3(net_rd_dv_ocm_hp3),
/* Goes to port 1 of DDR */
.ddr_wr_ack_port1(ddr_wr_ack_port1),
.ddr_wr_dv_port1(ddr_wr_dv_port1),
.ddr_rd_req_port1(ddr_rd_req_port1),
.ddr_rd_dv_port1 (ddr_rd_dv_port1),
.ddr_wr_addr_port1(ddr_wr_addr_port1),
.ddr_wr_data_port1(ddr_wr_data_port1),
.ddr_wr_bytes_port1(ddr_wr_bytes_port1),
.ddr_rd_addr_port1(ddr_rd_addr_port1),
.ddr_rd_data_port1(ddr_rd_data_port1),
.ddr_rd_bytes_port1(ddr_rd_bytes_port1),
.ddr_wr_qos_port1(ddr_wr_qos_port1),
.ddr_rd_qos_port1(ddr_rd_qos_port1),
/* Goes to port2 of DDR */
.ddr_wr_ack_port2 (ddr_wr_ack_port2),
.ddr_wr_dv_port2 (ddr_wr_dv_port2),
.ddr_rd_req_port2 (ddr_rd_req_port2),
.ddr_rd_dv_port2 (ddr_rd_dv_port2),
.ddr_wr_addr_port2(ddr_wr_addr_port2),
.ddr_wr_data_port2(ddr_wr_data_port2),
.ddr_wr_bytes_port2(ddr_wr_bytes_port2),
.ddr_rd_addr_port2(ddr_rd_addr_port2),
.ddr_rd_data_port2(ddr_rd_data_port2),
.ddr_rd_bytes_port2(ddr_rd_bytes_port2),
.ddr_wr_qos_port2 (ddr_wr_qos_port2),
.ddr_rd_qos_port2 (ddr_rd_qos_port2),
/* Goes to port3 of DDR */
.ddr_wr_ack_port3 (ddr_wr_ack_port3),
.ddr_wr_dv_port3 (ddr_wr_dv_port3),
.ddr_rd_req_port3 (ddr_rd_req_port3),
.ddr_rd_dv_port3 (ddr_rd_dv_port3),
.ddr_wr_addr_port3(ddr_wr_addr_port3),
.ddr_wr_data_port3(ddr_wr_data_port3),
.ddr_wr_bytes_port3(ddr_wr_bytes_port3),
.ddr_rd_addr_port3(ddr_rd_addr_port3),
.ddr_rd_data_port3(ddr_rd_data_port3),
.ddr_rd_bytes_port3(ddr_rd_bytes_port3),
.ddr_wr_qos_port3 (ddr_wr_qos_port3),
.ddr_rd_qos_port3 (ddr_rd_qos_port3),
/* Goes to port 0 of OCM */
.ocm_wr_ack_port1 (ocm_wr_ack_port1),
.ocm_wr_dv_port1 (ocm_wr_dv_port1),
.ocm_rd_req_port1 (ocm_rd_req_port1),
.ocm_rd_dv_port1 (ocm_rd_dv_port1),
.ocm_wr_addr_port1(ocm_wr_addr_port1),
.ocm_wr_data_port1(ocm_wr_data_port1),
.ocm_wr_bytes_port1(ocm_wr_bytes_port1),
.ocm_rd_addr_port1(ocm_rd_addr_port1),
.ocm_rd_data_port1(ocm_rd_data_port1),
.ocm_rd_bytes_port1(ocm_rd_bytes_port1),
.ocm_wr_qos_port1(ocm_wr_qos_port1),
.ocm_rd_qos_port1(ocm_rd_qos_port1),
/* Goes to port 0 of REG */
.reg_rd_qos_port1 (reg_rd_qos_port1) ,
.reg_rd_req_port1 (reg_rd_req_port1),
.reg_rd_dv_port1 (reg_rd_dv_port1),
.reg_rd_addr_port1(reg_rd_addr_port1),
.reg_rd_data_port1(reg_rd_data_port1),
.reg_rd_bytes_port1(reg_rd_bytes_port1)
);
processing_system7_bfm_v2_0_ddrc ddrc (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
/* Goes to port 0 of DDR */
.ddr_wr_ack_port0 (ddr_wr_ack_port0),
.ddr_wr_dv_port0 (ddr_wr_dv_port0),
.ddr_rd_req_port0 (ddr_rd_req_port0),
.ddr_rd_dv_port0 (ddr_rd_dv_port0),
.ddr_wr_addr_port0(net_wr_addr_acp),
.ddr_wr_data_port0(net_wr_data_acp),
.ddr_wr_bytes_port0(net_wr_bytes_acp),
.ddr_rd_addr_port0(net_rd_addr_acp),
.ddr_rd_bytes_port0(net_rd_bytes_acp),
.ddr_rd_data_port0(ddr_rd_data_port0),
.ddr_wr_qos_port0 (net_wr_qos_acp),
.ddr_rd_qos_port0 (net_rd_qos_acp),
/* Goes to port 1 of DDR */
.ddr_wr_ack_port1 (ddr_wr_ack_port1),
.ddr_wr_dv_port1 (ddr_wr_dv_port1),
.ddr_rd_req_port1 (ddr_rd_req_port1),
.ddr_rd_dv_port1 (ddr_rd_dv_port1),
.ddr_wr_addr_port1(ddr_wr_addr_port1),
.ddr_wr_data_port1(ddr_wr_data_port1),
.ddr_wr_bytes_port1(ddr_wr_bytes_port1),
.ddr_rd_addr_port1(ddr_rd_addr_port1),
.ddr_rd_data_port1(ddr_rd_data_port1),
.ddr_rd_bytes_port1(ddr_rd_bytes_port1),
.ddr_wr_qos_port1 (ddr_wr_qos_port1),
.ddr_rd_qos_port1 (ddr_rd_qos_port1),
/* Goes to port2 of DDR */
.ddr_wr_ack_port2 (ddr_wr_ack_port2),
.ddr_wr_dv_port2 (ddr_wr_dv_port2),
.ddr_rd_req_port2 (ddr_rd_req_port2),
.ddr_rd_dv_port2 (ddr_rd_dv_port2),
.ddr_wr_addr_port2(ddr_wr_addr_port2),
.ddr_wr_data_port2(ddr_wr_data_port2),
.ddr_wr_bytes_port2(ddr_wr_bytes_port2),
.ddr_rd_addr_port2(ddr_rd_addr_port2),
.ddr_rd_data_port2(ddr_rd_data_port2),
.ddr_rd_bytes_port2(ddr_rd_bytes_port2),
.ddr_wr_qos_port2 (ddr_wr_qos_port2),
.ddr_rd_qos_port2 (ddr_rd_qos_port2),
/* Goes to port3 of DDR */
.ddr_wr_ack_port3 (ddr_wr_ack_port3),
.ddr_wr_dv_port3 (ddr_wr_dv_port3),
.ddr_rd_req_port3 (ddr_rd_req_port3),
.ddr_rd_dv_port3 (ddr_rd_dv_port3),
.ddr_wr_addr_port3(ddr_wr_addr_port3),
.ddr_wr_data_port3(ddr_wr_data_port3),
.ddr_wr_bytes_port3(ddr_wr_bytes_port3),
.ddr_rd_addr_port3(ddr_rd_addr_port3),
.ddr_rd_data_port3(ddr_rd_data_port3),
.ddr_rd_bytes_port3(ddr_rd_bytes_port3),
.ddr_wr_qos_port3 (ddr_wr_qos_port3),
.ddr_rd_qos_port3 (ddr_rd_qos_port3)
);
processing_system7_bfm_v2_0_ocmc ocmc (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
/* Goes to port 0 of OCM */
.ocm_wr_ack_port0 (ocm_wr_ack_port0),
.ocm_wr_dv_port0 (ocm_wr_dv_port0),
.ocm_rd_req_port0 (ocm_rd_req_port0),
.ocm_rd_dv_port0 (ocm_rd_dv_port0),
.ocm_wr_addr_port0(net_wr_addr_acp),
.ocm_wr_data_port0(net_wr_data_acp),
.ocm_wr_bytes_port0(net_wr_bytes_acp),
.ocm_rd_addr_port0(net_rd_addr_acp),
.ocm_rd_bytes_port0(net_rd_bytes_acp),
.ocm_rd_data_port0(ocm_rd_data_port0),
.ocm_wr_qos_port0 (net_wr_qos_acp),
.ocm_rd_qos_port0 (net_rd_qos_acp),
/* Goes to port 1 of OCM */
.ocm_wr_ack_port1 (ocm_wr_ack_port1),
.ocm_wr_dv_port1 (ocm_wr_dv_port1),
.ocm_rd_req_port1 (ocm_rd_req_port1),
.ocm_rd_dv_port1 (ocm_rd_dv_port1),
.ocm_wr_addr_port1(ocm_wr_addr_port1),
.ocm_wr_data_port1(ocm_wr_data_port1),
.ocm_wr_bytes_port1(ocm_wr_bytes_port1),
.ocm_rd_addr_port1(ocm_rd_addr_port1),
.ocm_rd_data_port1(ocm_rd_data_port1),
.ocm_rd_bytes_port1(ocm_rd_bytes_port1),
.ocm_wr_qos_port1(ocm_wr_qos_port1),
.ocm_rd_qos_port1(ocm_rd_qos_port1)
);
processing_system7_bfm_v2_0_regc regc (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
/* Goes to port 0 of REG */
.reg_rd_req_port0 (reg_rd_req_port0),
.reg_rd_dv_port0 (reg_rd_dv_port0),
.reg_rd_addr_port0(net_rd_addr_acp),
.reg_rd_bytes_port0(net_rd_bytes_acp),
.reg_rd_data_port0(reg_rd_data_port0),
.reg_rd_qos_port0 (net_rd_qos_acp),
/* Goes to port 1 of REG */
.reg_rd_req_port1 (reg_rd_req_port1),
.reg_rd_dv_port1 (reg_rd_dv_port1),
.reg_rd_addr_port1(reg_rd_addr_port1),
.reg_rd_data_port1(reg_rd_data_port1),
.reg_rd_bytes_port1(reg_rd_bytes_port1),
.reg_rd_qos_port1(reg_rd_qos_port1)
);
/* include axi_gp port instantiations */
`include "processing_system7_bfm_v2_0_axi_gp.v"
/* include axi_hp port instantiations */
`include "processing_system7_bfm_v2_0_axi_hp.v"
/* include axi_acp port instantiations */
`include "processing_system7_bfm_v2_0_axi_acp.v"
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFBBP_SYMBOL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBP_SYMBOL_V
|
// Library - static, Cell - th22r, View - schematic
// LAST TIME SAVED: May 23 16:33:04 2014
// NETLIST TIME: May 23 16:33:10 2014
`timescale 1ns / 1ns
module th22r ( y, a, b, rsb );
output y;
input a, b, rsb;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th22r";
specparam CDS_VIEWNAME = "schematic";
endspecify
pfet_b P7 ( .b(cds_globals.vdd_), .g(rsb), .s(cds_globals.vdd_),
.d(net15));
pfet_b P4 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net24));
pfet_b P3 ( .b(cds_globals.vdd_), .g(y), .s(net24), .d(net15));
pfet_b P2 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net24));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net35), .d(net15));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net35));
nfet_b N7 ( .d(net023), .g(rsb), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N4 ( .d(net22), .g(b), .s(net023), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net22), .g(a), .s(net023), .b(cds_globals.gnd_));
nfet_b N2 ( .d(net15), .g(y), .s(net22), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net34), .g(a), .s(net023), .b(cds_globals.gnd_));
nfet_b N0 ( .d(net15), .g(b), .s(net34), .b(cds_globals.gnd_));
inv I2 ( y, net15);
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_instruction_unit.v
// Title : Instruction unit
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : Support for static branch prediction is added. Fetching of
// : instructions can also be altered by branches predicted in D
// : stage of pipeline, and mispredicted branches in the X and M
// : stages of the pipeline.
// Version : 3.2
// : EBRs use SYNC resets instead of ASYNC resets.
// Version : 3.3
// : Support for a non-cacheable Instruction Memory that has a
// : single-cycle access latency. This memory can be accessed by
// : data port of LM32 (so that debugger has access to it).
// Version : 3.4
// : No change
// Version : 3.5
// : Bug fix: Inline memory is correctly generated if it is not a
// : power-of-two.
// : Bug fix: Fixed a bug that caused LM32 (configured without
// : instruction cache) to lock up in to an infinite loop due to a
// : instruction bus error when EBA was set to instruction inline
// : memory.
// Version : 3.8
// : Feature: Support for dynamically switching EBA to DEBA via a
// : GPIO.
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_instruction_unit (
// ----- Inputs -------
clk_i,
rst_i,
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
at_debug,
`endif
`endif
// From pipeline
stall_a,
stall_f,
stall_d,
stall_x,
stall_m,
valid_f,
valid_d,
kill_f,
branch_predict_taken_d,
branch_predict_address_d,
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
branch_taken_x,
branch_target_x,
`endif
exception_m,
branch_taken_m,
branch_mispredict_taken_m,
branch_target_m,
`ifdef CFG_ICACHE_ENABLED
iflush,
`endif
`ifdef CFG_DCACHE_ENABLED
dcache_restart_request,
dcache_refill_request,
dcache_refilling,
`endif
`ifdef CFG_IROM_ENABLED
irom_store_data_m,
irom_address_xm,
irom_we_xm,
`endif
`ifdef CFG_IWB_ENABLED
// From Wishbone
i_dat_i,
i_ack_i,
i_err_i,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
jtag_read_enable,
jtag_write_enable,
jtag_write_data,
jtag_address,
`endif
// ----- Outputs -------
// To pipeline
pc_f,
pc_d,
pc_x,
pc_m,
pc_w,
`ifdef CFG_ICACHE_ENABLED
icache_stall_request,
icache_restart_request,
icache_refill_request,
icache_refilling,
`endif
`ifdef CFG_IROM_ENABLED
irom_data_m,
`endif
`ifdef CFG_IWB_ENABLED
// To Wishbone
i_dat_o,
i_adr_o,
i_cyc_o,
i_sel_o,
i_stb_o,
i_we_o,
i_cti_o,
i_lock_o,
i_bte_o,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
jtag_read_data,
jtag_access_complete,
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_d,
`endif
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
instruction_f,
`endif
instruction_d
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter associativity = 1; // Associativity of the cache (Number of ways)
parameter sets = 512; // Number of sets
parameter bytes_per_line = 16; // Number of bytes per cache line
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory
// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
localparam addr_offset_lsb = 2;
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
input at_debug; // GPIO input that maps EBA to DEBA
`endif
`endif
input stall_a; // Stall A stage instruction
input stall_f; // Stall F stage instruction
input stall_d; // Stall D stage instruction
input stall_x; // Stall X stage instruction
input stall_m; // Stall M stage instruction
input valid_f; // Instruction in F stage is valid
input valid_d; // Instruction in D stage is valid
input kill_f; // Kill instruction in F stage
input branch_predict_taken_d; // Branch is predicted taken in D stage
input [`LM32_PC_RNG] branch_predict_address_d; // Branch target address
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
input branch_taken_x; // Branch instruction in X stage is taken
input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction
`endif
input exception_m;
input branch_taken_m; // Branch instruction in M stage is taken
input branch_mispredict_taken_m; // Branch instruction in M stage is mispredicted as taken
input [`LM32_PC_RNG] branch_target_m; // Target PC of M stage branch instruction
`ifdef CFG_ICACHE_ENABLED
input iflush; // Flush instruction cache
`endif
`ifdef CFG_DCACHE_ENABLED
input dcache_restart_request; // Restart instruction that caused a data cache miss
input dcache_refill_request; // Request to refill data cache
input dcache_refilling;
`endif
`ifdef CFG_IROM_ENABLED
input [`LM32_WORD_RNG] irom_store_data_m; // Data from load-store unit
input [`LM32_WORD_RNG] irom_address_xm; // Address from load-store unit
input irom_we_xm; // Indicates if memory operation is load or store
`endif
`ifdef CFG_IWB_ENABLED
input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data
input i_ack_i; // Instruction Wishbone interface acknowledgement
input i_err_i; // Instruction Wishbone interface error
`endif
`ifdef CFG_HW_DEBUG_ENABLED
input jtag_read_enable; // JTAG read memory request
input jtag_write_enable; // JTAG write memory request
input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data
input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address
`endif
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_PC_RNG] pc_f; // F stage PC
reg [`LM32_PC_RNG] pc_f;
output [`LM32_PC_RNG] pc_d; // D stage PC
reg [`LM32_PC_RNG] pc_d;
output [`LM32_PC_RNG] pc_x; // X stage PC
reg [`LM32_PC_RNG] pc_x;
output [`LM32_PC_RNG] pc_m; // M stage PC
reg [`LM32_PC_RNG] pc_m;
output [`LM32_PC_RNG] pc_w; // W stage PC
reg [`LM32_PC_RNG] pc_w;
`ifdef CFG_ICACHE_ENABLED
output icache_stall_request; // Instruction cache stall request
wire icache_stall_request;
output icache_restart_request; // Request to restart instruction that cached instruction cache miss
wire icache_restart_request;
output icache_refill_request; // Instruction cache refill request
wire icache_refill_request;
output icache_refilling; // Indicates the icache is refilling
wire icache_refilling;
`endif
`ifdef CFG_IROM_ENABLED
output [`LM32_WORD_RNG] irom_data_m; // Data to load-store unit on load
wire [`LM32_WORD_RNG] irom_data_m;
`endif
`ifdef CFG_IWB_ENABLED
output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data
`ifdef CFG_HW_DEBUG_ENABLED
reg [`LM32_WORD_RNG] i_dat_o;
`else
wire [`LM32_WORD_RNG] i_dat_o;
`endif
output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address
reg [`LM32_WORD_RNG] i_adr_o;
output i_cyc_o; // Instruction Wishbone interface cycle
reg i_cyc_o;
output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select
`ifdef CFG_HW_DEBUG_ENABLED
reg [`LM32_BYTE_SELECT_RNG] i_sel_o;
`else
wire [`LM32_BYTE_SELECT_RNG] i_sel_o;
`endif
output i_stb_o; // Instruction Wishbone interface strobe
reg i_stb_o;
output i_we_o; // Instruction Wishbone interface write enable
`ifdef CFG_HW_DEBUG_ENABLED
reg i_we_o;
`else
wire i_we_o;
`endif
output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type
reg [`LM32_CTYPE_RNG] i_cti_o;
output i_lock_o; // Instruction Wishbone interface lock bus
reg i_lock_o;
output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type
wire [`LM32_BTYPE_RNG] i_bte_o;
`endif
`ifdef CFG_HW_DEBUG_ENABLED
output [`LM32_BYTE_RNG] jtag_read_data; // Data read for JTAG interface
reg [`LM32_BYTE_RNG] jtag_read_data;
output jtag_access_complete; // Requested memory access by JTAG interface is complete
wire jtag_access_complete;
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
output bus_error_d; // Indicates a bus error occured while fetching the instruction
reg bus_error_d;
`endif
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
output [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction (only to have register indices extracted from)
wire [`LM32_INSTRUCTION_RNG] instruction_f;
`endif
output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded
reg [`LM32_INSTRUCTION_RNG] instruction_d;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg [`LM32_PC_RNG] pc_a; // A stage PC
`ifdef LM32_CACHE_ENABLED
reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss
`endif
`ifdef CFG_ICACHE_ENABLED
wire icache_read_enable_f; // Indicates if instruction cache miss is valid
wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss
reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache
reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone
wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache
wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
wire last_word; // Indicates if this is the last word in the cache line
wire [`LM32_PC_RNG] first_address; // First cache refill address
`else
`ifdef CFG_IWB_ENABLED
reg [`LM32_INSTRUCTION_RNG] wb_data_f; // Instruction fetched from Wishbone
`endif
`endif
`ifdef CFG_IROM_ENABLED
wire irom_select_a; // Indicates if A stage PC maps to a ROM address
reg irom_select_f; // Indicates if F stage PC maps to a ROM address
wire [`LM32_INSTRUCTION_RNG] irom_data_f; // Instruction fetched from ROM
`endif
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
`else
wire [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
reg bus_error_f; // Indicates if a bus error occured while fetching the instruction in the F stage
`endif
`ifdef CFG_HW_DEBUG_ENABLED
reg jtag_access; // Indicates if a JTAG WB access is in progress
`endif
`ifdef CFG_ALTERNATE_EBA
reg alternate_eba_taken;
`endif
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
`include "lm32_functions.v"
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
// Instruction ROM
`ifdef CFG_IROM_ENABLED
pmi_ram_dp_true
#(
// ----- Parameters -------
.pmi_family (`LATTICE_FAMILY),
//.pmi_addr_depth_a (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
//.pmi_addr_width_a ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
//.pmi_data_width_a (`LM32_WORD_WIDTH),
//.pmi_addr_depth_b (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
//.pmi_addr_width_b ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
//.pmi_data_width_b (`LM32_WORD_WIDTH),
.pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
.pmi_addr_width_a (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
.pmi_data_width_a (`LM32_WORD_WIDTH),
.pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
.pmi_addr_width_b (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
.pmi_data_width_b (`LM32_WORD_WIDTH),
.pmi_regmode_a ("noreg"),
.pmi_regmode_b ("noreg"),
.pmi_gsr ("enable"),
.pmi_resetmode ("sync"),
.pmi_init_file (`CFG_IROM_INIT_FILE),
.pmi_init_file_format (`CFG_IROM_INIT_FILE_FORMAT),
.module_type ("pmi_ram_dp_true")
)
ram (
// ----- Inputs -------
.ClockA (clk_i),
.ClockB (clk_i),
.ResetA (rst_i),
.ResetB (rst_i),
.DataInA ({32{1'b0}}),
.DataInB (irom_store_data_m),
.AddressA (pc_a[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
.AddressB (irom_address_xm[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
.ClockEnA (!stall_a),
.ClockEnB (!stall_x || !stall_m),
.WrA (`FALSE),
.WrB (irom_we_xm),
// ----- Outputs -------
.QA (irom_data_f),
.QB (irom_data_m)
);
`endif
`ifdef CFG_ICACHE_ENABLED
// Instruction cache
lm32_icache #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
.base_address (base_address),
.limit (limit)
) icache (
// ----- Inputs -----
.clk_i (clk_i),
.rst_i (rst_i),
.stall_a (stall_a),
.stall_f (stall_f),
.branch_predict_taken_d (branch_predict_taken_d),
.valid_d (valid_d),
.address_a (pc_a),
.address_f (pc_f),
.read_enable_f (icache_read_enable_f),
.refill_ready (icache_refill_ready),
.refill_data (icache_refill_data),
.iflush (iflush),
// ----- Outputs -----
.stall_request (icache_stall_request),
.restart_request (icache_restart_request),
.refill_request (icache_refill_request),
.refill_address (icache_refill_address),
.refilling (icache_refilling),
.inst (icache_data_f)
);
`endif
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
`ifdef CFG_ICACHE_ENABLED
// Generate signal that indicates when instruction cache misses are valid
assign icache_read_enable_f = (valid_f == `TRUE)
&& (kill_f == `FALSE)
`ifdef CFG_DCACHE_ENABLED
&& (dcache_restart_request == `FALSE)
`endif
`ifdef CFG_IROM_ENABLED
&& (irom_select_f == `FALSE)
`endif
;
`endif
// Compute address of next instruction to fetch
always @(*)
begin
// The request from the latest pipeline stage must take priority
`ifdef CFG_DCACHE_ENABLED
if (dcache_restart_request == `TRUE)
pc_a = restart_address;
else
`endif
if (branch_taken_m == `TRUE)
if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE))
pc_a = pc_x;
else
pc_a = branch_target_m;
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
else if (branch_taken_x == `TRUE)
pc_a = branch_target_x;
`endif
else
if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) )
pc_a = branch_predict_address_d;
else
`ifdef CFG_ICACHE_ENABLED
if (icache_restart_request == `TRUE)
pc_a = restart_address;
else
`endif
pc_a = pc_f + 1'b1;
end
// Select where instruction should be fetched from
`ifdef CFG_IROM_ENABLED
assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT);
`endif
// Select instruction from selected source
`ifdef CFG_ICACHE_ENABLED
`ifdef CFG_IROM_ENABLED
assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f;
`else
assign instruction_f = icache_data_f;
`endif
`else
`ifdef CFG_IROM_ENABLED
`ifdef CFG_IWB_ENABLED
assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f;
`else
assign instruction_f = irom_data_f;
`endif
`else
assign instruction_f = wb_data_f;
`endif
`endif
// Unused/constant Wishbone signals
`ifdef CFG_IWB_ENABLED
`ifdef CFG_HW_DEBUG_ENABLED
`else
assign i_dat_o = 32'd0;
assign i_we_o = `FALSE;
assign i_sel_o = 4'b1111;
`endif
assign i_bte_o = `LM32_BTYPE_LINEAR;
`endif
`ifdef CFG_ICACHE_ENABLED
// Determine parameters for next cache refill Wishbone access
generate
case (bytes_per_line)
4:
begin
assign first_cycle_type = `LM32_CTYPE_END;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = `TRUE;
assign first_address = icache_refill_address;
end
8:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
end
16:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
end
endcase
endgenerate
`endif
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// PC
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
if (at_debug == `TRUE)
pc_f <= #1 (`CFG_DEBA_RESET-4)/4;
else
pc_f <= #1 (`CFG_EBA_RESET-4)/4;
`else
pc_f <= #1 (`CFG_EBA_RESET-4)/4;
`endif
`else
pc_f <= #1 (`CFG_EBA_RESET-4)/4;
`endif
pc_d <= #1 {`LM32_PC_WIDTH{1'b0}};
pc_x <= #1 {`LM32_PC_WIDTH{1'b0}};
pc_m <= #1 {`LM32_PC_WIDTH{1'b0}};
pc_w <= #1 {`LM32_PC_WIDTH{1'b0}};
end
else
begin
if (stall_f == `FALSE)
pc_f <= #1 pc_a;
if (stall_d == `FALSE)
pc_d <= #1 pc_f;
if (stall_x == `FALSE)
pc_x <= #1 pc_d;
if (stall_m == `FALSE)
pc_m <= #1 pc_x;
pc_w <= #1 pc_m;
end
end
`ifdef LM32_CACHE_ENABLED
// Address to restart from after a cache miss has been handled
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
restart_address <= #1 {`LM32_PC_WIDTH{1'b0}};
else
begin
`ifdef CFG_DCACHE_ENABLED
`ifdef CFG_ICACHE_ENABLED
// D-cache restart address must take priority, otherwise instructions will be lost
if (dcache_refill_request == `TRUE)
restart_address <= #1 pc_w;
else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request))
restart_address <= #1 icache_refill_address;
`else
if (dcache_refill_request == `TRUE)
restart_address <= #1 pc_w;
`endif
`else
`ifdef CFG_ICACHE_ENABLED
if (icache_refill_request == `TRUE)
restart_address <= #1 icache_refill_address;
`endif
`endif
end
end
`endif
// Record where instruction was fetched from
`ifdef CFG_IROM_ENABLED
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
irom_select_f <= #1 `FALSE;
else
begin
if (stall_f == `FALSE)
irom_select_f <= #1 irom_select_a;
end
end
`endif
`ifdef CFG_HW_DEBUG_ENABLED
assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE);
always @(*)
begin
case (jtag_address[1:0])
2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG];
2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG];
2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG];
2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG];
endcase
end
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone interface
`ifdef CFG_ICACHE_ENABLED
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
i_cyc_o <= #1 `FALSE;
i_stb_o <= #1 `FALSE;
i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
i_cti_o <= #1 `LM32_CTYPE_END;
i_lock_o <= #1 `FALSE;
icache_refill_data <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}};
icache_refill_ready <= #1 `FALSE;
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_f <= #1 `FALSE;
`endif
`ifdef CFG_HW_DEBUG_ENABLED
i_we_o <= #1 `FALSE;
i_sel_o <= #1 4'b1111;
jtag_access <= #1 `FALSE;
`endif
end
else
begin
icache_refill_ready <= #1 `FALSE;
// Is a cycle in progress?
if (i_cyc_o == `TRUE)
begin
// Has cycle completed?
if ((i_ack_i == `TRUE) || (i_err_i == `TRUE))
begin
`ifdef CFG_HW_DEBUG_ENABLED
if (jtag_access == `TRUE)
begin
i_cyc_o <= #1 `FALSE;
i_stb_o <= #1 `FALSE;
i_we_o <= #1 `FALSE;
jtag_access <= #1 `FALSE;
end
else
`endif
begin
if (last_word == `TRUE)
begin
// Cache line fill complete
i_cyc_o <= #1 `FALSE;
i_stb_o <= #1 `FALSE;
i_lock_o <= #1 `FALSE;
end
// Fetch next word in cache line
i_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
i_cti_o <= #1 next_cycle_type;
// Write fetched data into instruction cache
icache_refill_ready <= #1 `TRUE;
icache_refill_data <= #1 i_dat_i;
end
end
`ifdef CFG_BUS_ERRORS_ENABLED
if (i_err_i == `TRUE)
begin
bus_error_f <= #1 `TRUE;
$display ("Instruction bus error. Address: %x", i_adr_o);
end
`endif
end
else
begin
if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE))
begin
// Read first word of cache line
`ifdef CFG_HW_DEBUG_ENABLED
i_sel_o <= #1 4'b1111;
`endif
i_adr_o <= #1 {first_address, 2'b00};
i_cyc_o <= #1 `TRUE;
i_stb_o <= #1 `TRUE;
i_cti_o <= #1 first_cycle_type;
//i_lock_o <= #1 `TRUE;
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_f <= #1 `FALSE;
`endif
end
`ifdef CFG_HW_DEBUG_ENABLED
else
begin
if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE))
begin
case (jtag_address[1:0])
2'b00: i_sel_o <= #1 4'b1000;
2'b01: i_sel_o <= #1 4'b0100;
2'b10: i_sel_o <= #1 4'b0010;
2'b11: i_sel_o <= #1 4'b0001;
endcase
i_adr_o <= #1 jtag_address;
i_dat_o <= #1 {4{jtag_write_data}};
i_cyc_o <= #1 `TRUE;
i_stb_o <= #1 `TRUE;
i_we_o <= #1 jtag_write_enable;
i_cti_o <= #1 `LM32_CTYPE_END;
jtag_access <= #1 `TRUE;
end
end
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
// Clear bus error when exception taken, otherwise they would be
// continually generated if exception handler is cached
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
if (branch_taken_x == `TRUE)
bus_error_f <= #1 `FALSE;
`endif
if (branch_taken_m == `TRUE)
bus_error_f <= #1 `FALSE;
`endif
end
end
end
`else
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
i_cyc_o <= #1 `FALSE;
i_stb_o <= #1 `FALSE;
i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
i_cti_o <= #1 `LM32_CTYPE_END;
i_lock_o <= #1 `FALSE;
wb_data_f <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}};
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_f <= #1 `FALSE;
`endif
end
else
begin
// Is a cycle in progress?
if (i_cyc_o == `TRUE)
begin
// Has cycle completed?
if((i_ack_i == `TRUE) || (i_err_i == `TRUE))
begin
// Cycle complete
i_cyc_o <= #1 `FALSE;
i_stb_o <= #1 `FALSE;
// Register fetched instruction
wb_data_f <= #1 i_dat_i;
end
`ifdef CFG_BUS_ERRORS_ENABLED
if (i_err_i == `TRUE)
begin
bus_error_f <= #1 `TRUE;
$display ("Instruction bus error. Address: %x", i_adr_o);
end
`endif
end
else
begin
// Wait for an instruction fetch from an external address
if ( (stall_a == `FALSE)
`ifdef CFG_IROM_ENABLED
&& (irom_select_a == `FALSE)
`endif
)
begin
// Fetch instruction
`ifdef CFG_HW_DEBUG_ENABLED
i_sel_o <= #1 4'b1111;
`endif
i_adr_o <= #1 {pc_a, 2'b00};
i_cyc_o <= #1 `TRUE;
i_stb_o <= #1 `TRUE;
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_f <= #1 `FALSE;
`endif
end
else
begin
if ( (stall_a == `FALSE)
`ifdef CFG_IROM_ENABLED
&& (irom_select_a == `TRUE)
`endif
)
begin
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_f <= #1 `FALSE;
`endif
end
end
end
end
end
`endif
`endif
// Instruction register
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
instruction_d <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}};
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_d <= #1 `FALSE;
`endif
end
else
begin
if (stall_d == `FALSE)
begin
instruction_d <= #1 instruction_f;
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_d <= #1 bus_error_f;
`endif
end
end
end
endmodule
|
/*
* This module sends commands to the PS2 interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse_cmdout (
input clk,
input reset,
input [7:0] the_command,
input send_command,
input ps2_clk_posedge,
input ps2_clk_negedge,
inout ps2_clk,
inout ps2_dat,
output reg command_was_sent,
output reg error_communication_timed_out
);
// --------------------------------------------------------------------
// Parameter Declarations , 1/12.5mhz => 0.08us
// --------------------------------------------------------------------
parameter CLOCK_CYCLES_FOR_101US = 1262; // Timing info for initiating
parameter NUMBER_OF_BITS_FOR_101US = 13; // Host-to-Device communication
parameter COUNTER_INCREMENT_FOR_101US = 13'h0001; // when using a 12.5MHz system clock
parameter CLOCK_CYCLES_FOR_15MS = 187500; // Timing info for start of
parameter NUMBER_OF_BITS_FOR_15MS = 20; // transmission error when
parameter COUNTER_INCREMENT_FOR_15MS = 20'h00001; // using a 12.5MHz system clock
parameter CLOCK_CYCLES_FOR_2MS = 25000; // Timing info for sending
parameter NUMBER_OF_BITS_FOR_2MS = 17; // data error when
parameter COUNTER_INCREMENT_FOR_2MS = 17'h00001; // using a 12.5MHz system clock
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
parameter PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_INITIATE_COMMUNICATION = 3'h1,
PS2_STATE_2_WAIT_FOR_CLOCK = 3'h2,
PS2_STATE_3_TRANSMIT_DATA = 3'h3,
PS2_STATE_4_TRANSMIT_STOP_BIT = 3'h4,
PS2_STATE_5_RECEIVE_ACK_BIT = 3'h5,
PS2_STATE_6_COMMAND_WAS_SENT = 3'h6,
PS2_STATE_7_TRANSMISSION_ERROR = 3'h7;
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
reg [3:0] cur_bit; // Internal Registers
reg [8:0] ps2_command;
reg [NUMBER_OF_BITS_FOR_101US:1] command_initiate_counter;
reg [NUMBER_OF_BITS_FOR_15MS:1] waiting_counter;
reg [NUMBER_OF_BITS_FOR_2MS:1] transfer_counter;
reg [2:0] ns_ps2_transmitter; // State Machine Registers
reg [2:0] s_ps2_transmitter;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transmitter <= PS2_STATE_0_IDLE;
else s_ps2_transmitter <= ns_ps2_transmitter;
end
always @(*) begin // Defaults
ns_ps2_transmitter = PS2_STATE_0_IDLE;
case (s_ps2_transmitter)
PS2_STATE_0_IDLE:
begin
if (send_command == 1'b1) ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
else ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
PS2_STATE_1_INITIATE_COMMUNICATION:
begin
if (command_initiate_counter == CLOCK_CYCLES_FOR_101US)
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
else
ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
end
PS2_STATE_2_WAIT_FOR_CLOCK:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
else if (waiting_counter == CLOCK_CYCLES_FOR_15MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
end
PS2_STATE_3_TRANSMIT_DATA:
begin
if ((cur_bit == 4'd8) && (ps2_clk_negedge == 1'b1))
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
end
PS2_STATE_4_TRANSMIT_STOP_BIT:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
end
PS2_STATE_5_RECEIVE_ACK_BIT:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
end
PS2_STATE_6_COMMAND_WAS_SENT:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
end
PS2_STATE_7_TRANSMISSION_ERROR:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
end
default:
begin
ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) ps2_command <= 9'h000;
else if(s_ps2_transmitter == PS2_STATE_0_IDLE)
ps2_command <= {(^the_command) ^ 1'b1, the_command};
end
always @(posedge clk) begin
if(reset == 1'b1) command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
else if((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter != CLOCK_CYCLES_FOR_101US))
command_initiate_counter <=
command_initiate_counter + COUNTER_INCREMENT_FOR_101US;
else if(s_ps2_transmitter != PS2_STATE_1_INITIATE_COMMUNICATION)
command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
end
always @(posedge clk) begin
if(reset == 1'b1) waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
else if((s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) &&
(waiting_counter != CLOCK_CYCLES_FOR_15MS))
waiting_counter <= waiting_counter + COUNTER_INCREMENT_FOR_15MS;
else if(s_ps2_transmitter != PS2_STATE_2_WAIT_FOR_CLOCK)
waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
end
always @(posedge clk) begin
if(reset == 1'b1) transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
else begin
if((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ||
(s_ps2_transmitter == PS2_STATE_4_TRANSMIT_STOP_BIT) ||
(s_ps2_transmitter == PS2_STATE_5_RECEIVE_ACK_BIT))
begin
if(transfer_counter != CLOCK_CYCLES_FOR_2MS)
transfer_counter <= transfer_counter + COUNTER_INCREMENT_FOR_2MS;
end
else transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
end
end
always @(posedge clk) begin
if(reset == 1'b1) cur_bit <= 4'h0;
else if((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) &&
(ps2_clk_negedge == 1'b1))
cur_bit <= cur_bit + 4'h1;
else if(s_ps2_transmitter != PS2_STATE_3_TRANSMIT_DATA)
cur_bit <= 4'h0;
end
always @(posedge clk) begin
if(reset == 1'b1) command_was_sent <= 1'b0;
else if(s_ps2_transmitter == PS2_STATE_6_COMMAND_WAS_SENT)
command_was_sent <= 1'b1;
else if(send_command == 1'b0) command_was_sent <= 1'b0;
end
always @(posedge clk) begin
if(reset == 1'b1) error_communication_timed_out <= 1'b0;
else if(s_ps2_transmitter == PS2_STATE_7_TRANSMISSION_ERROR)
error_communication_timed_out <= 1'b1;
else if(send_command == 1'b0)
error_communication_timed_out <= 1'b0;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk = (s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) ? 1'b0 : 1'bz;
assign ps2_dat = (s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ? ps2_command[cur_bit] :
(s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) ? 1'b0 :
((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter[NUMBER_OF_BITS_FOR_101US] == 1'b1)) ? 1'b0 : 1'bz;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:02:09 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4_32 ( CLK, EN, ENCLK, TE
);
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_21 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_23 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_26 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_27 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_29 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_32 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module CORDIC_Arch3v1_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, add_subt_dataA, add_subt_dataB,
result_add_subt, op_add_subt, ready_add_subt, enab_cont_iter );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
output [31:0] add_subt_dataA;
output [31:0] add_subt_dataB;
input [31:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, op_add_subt, enab_cont_iter;
wire enab_d_ff4_Zn, enab_d_ff_RB1, enab_RB3, enab_d_ff5_data_out,
d_ff1_operation_out, d_ff1_shift_region_flag_out_0_, d_ff3_sign_out,
enab_d_ff4_Yn, enab_d_ff4_Xn, fmtted_Result_31_, ITER_CONT_net3608262,
ITER_CONT_N5, ITER_CONT_N4, ITER_CONT_N3, d_ff5_data_out_net3608226,
reg_Z0_net3608226, reg_val_muxZ_2stage_net3608226,
reg_shift_y_net3608226, d_ff4_Xn_net3608226, d_ff4_Yn_net3608226,
d_ff4_Zn_net3608226, n154, n518, n519, n520, n521, n522, n523, n524,
n525, n526, n527, n528, n529, n531, n532, n533, n534, n535, n536,
n537, intadd_421_CI, intadd_421_n3, intadd_421_n2, intadd_421_n1,
intadd_422_CI, intadd_422_n3, intadd_422_n2, intadd_422_n1, n604,
n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626,
n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637,
n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648,
n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, n659,
n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670,
n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681,
n682, n683, n684, n685, n686, n687, n688, n689, n690, n691, n692,
n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703,
n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714,
n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725,
n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736,
n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758,
n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769,
n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780,
n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791,
n792, n793, n794, n795;
wire [3:0] cont_iter_out;
wire [1:0] cont_var_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] first_mux_X;
wire [31:0] d_ff_Yn;
wire [31:0] first_mux_Y;
wire [31:0] d_ff_Zn;
wire [31:0] first_mux_Z;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [7:0] sh_exp_x;
wire [7:0] sh_exp_y;
wire [25:4] data_out_LUT;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [30:0] mux_sal;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4_32 ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(enab_cont_iter), .ENCLK(ITER_CONT_net3608262), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_21 d_ff5_data_out_clk_gate_Q_reg ( .CLK(
clk), .EN(enab_d_ff5_data_out), .ENCLK(d_ff5_data_out_net3608226),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_32 reg_Z0_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff_RB1), .ENCLK(reg_Z0_net3608226), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_29 reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(n612), .ENCLK(reg_val_muxZ_2stage_net3608226), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_27 reg_shift_y_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_RB3), .ENCLK(reg_shift_y_net3608226), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_26 d_ff4_Xn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Xn), .ENCLK(d_ff4_Xn_net3608226), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_24 d_ff4_Yn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Yn), .ENCLK(d_ff4_Yn_net3608226), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_23 d_ff4_Zn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Zn), .ENCLK(d_ff4_Zn_net3608226), .TE(1'b0) );
DFFRXLTS reg_region_flag_Q_reg_0_ ( .D(shift_region_flag[0]), .CK(
reg_Z0_net3608226), .RN(n793), .Q(d_ff1_shift_region_flag_out_0_),
.QN(n615) );
DFFRXLTS reg_region_flag_Q_reg_1_ ( .D(shift_region_flag[1]), .CK(
reg_Z0_net3608226), .RN(n793), .QN(n606) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n524), .CK(reg_shift_y_net3608226), .RN(n788),
.Q(d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n534), .CK(reg_shift_y_net3608226), .RN(n789),
.Q(d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n528), .CK(reg_shift_y_net3608226), .RN(n789),
.Q(d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n536), .CK(reg_shift_y_net3608226), .RN(n788),
.Q(d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(data_out_LUT[4]), .CK(reg_shift_y_net3608226),
.RN(n793), .Q(d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n525), .CK(reg_shift_y_net3608226), .RN(n787),
.Q(d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n527), .CK(reg_shift_y_net3608226), .RN(n792),
.Q(d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n531), .CK(reg_shift_y_net3608226), .RN(n793),
.Q(d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n761), .CK(reg_shift_y_net3608226), .RN(n793),
.Q(d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n533), .CK(reg_shift_y_net3608226), .RN(n788),
.Q(d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n526), .CK(reg_shift_y_net3608226), .RN(n793), .Q(d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n532), .CK(reg_shift_y_net3608226), .RN(n787), .Q(d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n523), .CK(reg_shift_y_net3608226), .RN(n785), .Q(d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n535), .CK(reg_shift_y_net3608226), .RN(n792), .Q(d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n537), .CK(reg_shift_y_net3608226), .RN(n789), .Q(d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n522), .CK(reg_shift_y_net3608226), .RN(n789), .Q(d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n521), .CK(reg_shift_y_net3608226), .RN(n788), .Q(d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n520), .CK(reg_shift_y_net3608226), .RN(n789), .Q(d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(data_out_LUT[25]), .CK(
reg_shift_y_net3608226), .RN(n622), .Q(d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n529), .CK(reg_shift_y_net3608226), .RN(n794), .Q(d_ff3_LUT_out[26]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(data_in[0]), .CK(reg_Z0_net3608226), .RN(n622),
.Q(d_ff1_Z[0]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(data_in[1]), .CK(reg_Z0_net3608226), .RN(n786),
.Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(data_in[2]), .CK(reg_Z0_net3608226), .RN(n784),
.Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(data_in[3]), .CK(reg_Z0_net3608226), .RN(n783),
.Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(data_in[4]), .CK(reg_Z0_net3608226), .RN(n791),
.Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(data_in[5]), .CK(reg_Z0_net3608226), .RN(n794),
.Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(data_in[6]), .CK(reg_Z0_net3608226), .RN(n622),
.Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(data_in[7]), .CK(reg_Z0_net3608226), .RN(n786),
.Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(data_in[8]), .CK(reg_Z0_net3608226), .RN(n784),
.Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(data_in[9]), .CK(reg_Z0_net3608226), .RN(n783),
.Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(data_in[10]), .CK(reg_Z0_net3608226), .RN(
n790), .Q(d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(data_in[11]), .CK(reg_Z0_net3608226), .RN(
n788), .Q(d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(data_in[12]), .CK(reg_Z0_net3608226), .RN(
n789), .Q(d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(data_in[13]), .CK(reg_Z0_net3608226), .RN(
n787), .Q(d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(data_in[14]), .CK(reg_Z0_net3608226), .RN(
n785), .Q(d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(data_in[15]), .CK(reg_Z0_net3608226), .RN(
n792), .Q(d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(data_in[16]), .CK(reg_Z0_net3608226), .RN(
n790), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(data_in[17]), .CK(reg_Z0_net3608226), .RN(
n789), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(data_in[18]), .CK(reg_Z0_net3608226), .RN(
n788), .Q(d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(data_in[19]), .CK(reg_Z0_net3608226), .RN(
n790), .Q(d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(data_in[20]), .CK(reg_Z0_net3608226), .RN(
n787), .Q(d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(data_in[21]), .CK(reg_Z0_net3608226), .RN(
n785), .Q(d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(data_in[22]), .CK(reg_Z0_net3608226), .RN(
n790), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(data_in[23]), .CK(reg_Z0_net3608226), .RN(
n787), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(data_in[24]), .CK(reg_Z0_net3608226), .RN(
n785), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(data_in[25]), .CK(reg_Z0_net3608226), .RN(
n792), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(data_in[26]), .CK(reg_Z0_net3608226), .RN(
n789), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(data_in[27]), .CK(reg_Z0_net3608226), .RN(
n790), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(data_in[28]), .CK(reg_Z0_net3608226), .RN(
n788), .Q(d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(data_in[29]), .CK(reg_Z0_net3608226), .RN(
n793), .Q(d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(data_in[30]), .CK(reg_Z0_net3608226), .RN(
n787), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(data_in[31]), .CK(reg_Z0_net3608226), .RN(
n785), .Q(d_ff1_Z[31]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(sh_exp_x[0]), .CK(reg_shift_y_net3608226), .RN(n792), .Q(d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(sh_exp_x[1]), .CK(reg_shift_y_net3608226), .RN(n790), .Q(d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(sh_exp_x[2]), .CK(reg_shift_y_net3608226), .RN(n785), .Q(d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(sh_exp_x[3]), .CK(reg_shift_y_net3608226), .RN(n792), .Q(d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(sh_exp_x[4]), .CK(reg_shift_y_net3608226), .RN(n790), .Q(d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(sh_exp_x[5]), .CK(reg_shift_y_net3608226), .RN(n790), .Q(d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(sh_exp_x[6]), .CK(reg_shift_y_net3608226), .RN(n788), .Q(d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(sh_exp_x[7]), .CK(reg_shift_y_net3608226), .RN(n789), .Q(d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(sh_exp_y[0]), .CK(reg_shift_y_net3608226), .RN(n787), .Q(d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(sh_exp_y[1]), .CK(reg_shift_y_net3608226), .RN(n785), .Q(d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(sh_exp_y[2]), .CK(reg_shift_y_net3608226), .RN(n792), .Q(d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(sh_exp_y[3]), .CK(reg_shift_y_net3608226), .RN(n793), .Q(d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(sh_exp_y[4]), .CK(reg_shift_y_net3608226), .RN(n793), .Q(d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(sh_exp_y[5]), .CK(reg_shift_y_net3608226), .RN(n793), .Q(d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(sh_exp_y[6]), .CK(reg_shift_y_net3608226), .RN(n788), .Q(d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(sh_exp_y[7]), .CK(reg_shift_y_net3608226), .RN(n793), .Q(d_ff3_sh_y_out[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Xn_net3608226), .RN(n787), .Q(d_ff_Xn[0]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_0_ ( .D(first_mux_X[0]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n785), .Q(d_ff2_X[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(d_ff2_X[0]), .CK(reg_shift_y_net3608226),
.RN(n792), .Q(d_ff3_sh_x_out[0]) );
DFFRXLTS d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Xn_net3608226), .RN(n789), .Q(d_ff_Xn[1]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_1_ ( .D(first_mux_X[1]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n793), .Q(d_ff2_X[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(d_ff2_X[1]), .CK(reg_shift_y_net3608226),
.RN(n788), .Q(d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Xn_net3608226), .RN(n789), .Q(d_ff_Xn[2]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_2_ ( .D(first_mux_X[2]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n787), .Q(d_ff2_X[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(d_ff2_X[2]), .CK(reg_shift_y_net3608226),
.RN(n785), .Q(d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Xn_net3608226), .RN(n792), .Q(d_ff_Xn[3]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_3_ ( .D(first_mux_X[3]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n786), .Q(d_ff2_X[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(d_ff2_X[3]), .CK(reg_shift_y_net3608226),
.RN(n784), .Q(d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Xn_net3608226), .RN(n783), .Q(d_ff_Xn[4]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(first_mux_X[4]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n791), .Q(d_ff2_X[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(d_ff2_X[4]), .CK(reg_shift_y_net3608226),
.RN(n794), .Q(d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Xn_net3608226), .RN(n786), .Q(d_ff_Xn[5]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(first_mux_X[5]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n784), .Q(d_ff2_X[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(d_ff2_X[5]), .CK(reg_shift_y_net3608226),
.RN(n783), .Q(d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Xn_net3608226), .RN(n791), .Q(d_ff_Xn[6]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(first_mux_X[6]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n794), .Q(d_ff2_X[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(d_ff2_X[6]), .CK(reg_shift_y_net3608226),
.RN(n786), .Q(d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Xn_net3608226), .RN(n784), .Q(d_ff_Xn[7]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(first_mux_X[7]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n787), .Q(d_ff2_X[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(d_ff2_X[7]), .CK(reg_shift_y_net3608226),
.RN(n785), .Q(d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Xn_net3608226), .RN(n792), .Q(d_ff_Xn[8]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(first_mux_X[8]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n790), .Q(d_ff2_X[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(d_ff2_X[8]), .CK(reg_shift_y_net3608226),
.RN(n790), .Q(d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Xn_net3608226), .RN(n788), .Q(d_ff_Xn[9]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(first_mux_X[9]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n790), .Q(d_ff2_X[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(d_ff2_X[9]), .CK(reg_shift_y_net3608226),
.RN(n787), .Q(d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Xn_net3608226), .RN(n785), .Q(d_ff_Xn[10]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_10_ ( .D(first_mux_X[10]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n792), .Q(d_ff2_X[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(d_ff2_X[10]), .CK(reg_shift_y_net3608226), .RN(n793), .Q(d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Xn_net3608226), .RN(n793), .Q(d_ff_Xn[11]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_11_ ( .D(first_mux_X[11]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n791), .Q(d_ff2_X[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(d_ff2_X[11]), .CK(reg_shift_y_net3608226), .RN(n794), .Q(d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Xn_net3608226), .RN(n786), .Q(d_ff_Xn[12]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_12_ ( .D(first_mux_X[12]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n784), .Q(d_ff2_X[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(d_ff2_X[12]), .CK(reg_shift_y_net3608226), .RN(n783), .Q(d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Xn_net3608226), .RN(n791), .Q(d_ff_Xn[13]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_13_ ( .D(first_mux_X[13]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n794), .Q(d_ff2_X[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(d_ff2_X[13]), .CK(reg_shift_y_net3608226), .RN(n786), .Q(d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Xn_net3608226), .RN(n784), .Q(d_ff_Xn[14]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_14_ ( .D(first_mux_X[14]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n783), .Q(d_ff2_X[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(d_ff2_X[14]), .CK(reg_shift_y_net3608226), .RN(n791), .Q(d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Xn_net3608226), .RN(n794), .Q(d_ff_Xn[15]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_15_ ( .D(first_mux_X[15]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n791), .Q(d_ff2_X[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(d_ff2_X[15]), .CK(reg_shift_y_net3608226), .RN(n794), .Q(d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Xn_net3608226), .RN(n622), .Q(d_ff_Xn[16]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_16_ ( .D(first_mux_X[16]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n786), .Q(d_ff2_X[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(d_ff2_X[16]), .CK(reg_shift_y_net3608226), .RN(n784), .Q(d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Xn_net3608226), .RN(n783), .Q(d_ff_Xn[17]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_17_ ( .D(first_mux_X[17]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n791), .Q(d_ff2_X[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(d_ff2_X[17]), .CK(reg_shift_y_net3608226), .RN(n794), .Q(d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Xn_net3608226), .RN(n622), .Q(d_ff_Xn[18]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_18_ ( .D(first_mux_X[18]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n786), .Q(d_ff2_X[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(d_ff2_X[18]), .CK(reg_shift_y_net3608226), .RN(n784), .Q(d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Xn_net3608226), .RN(n783), .Q(d_ff_Xn[19]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_19_ ( .D(first_mux_X[19]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n622), .Q(d_ff2_X[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(d_ff2_X[19]), .CK(reg_shift_y_net3608226), .RN(n775), .Q(d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Xn_net3608226), .RN(n604), .Q(d_ff_Xn[20]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_20_ ( .D(first_mux_X[20]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n792), .Q(d_ff2_X[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(d_ff2_X[20]), .CK(reg_shift_y_net3608226), .RN(n780), .Q(d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Xn_net3608226), .RN(n779), .Q(d_ff_Xn[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_21_ ( .D(first_mux_X[21]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n775), .Q(d_ff2_X[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(d_ff2_X[21]), .CK(reg_shift_y_net3608226), .RN(n604), .Q(d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Xn_net3608226), .RN(n776), .Q(d_ff_Xn[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(first_mux_X[22]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n792), .Q(d_ff2_X[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(d_ff2_X[22]), .CK(reg_shift_y_net3608226), .RN(n770), .Q(d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Xn_net3608226), .RN(n775), .Q(d_ff_Xn[23]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(first_mux_X[23]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_X[23]), .QN(n616)
);
DFFRXLTS d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Xn_net3608226), .RN(n780), .Q(d_ff_Xn[24]) );
DFFRXLTS d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Xn_net3608226), .RN(n781), .Q(d_ff_Xn[25]) );
DFFRXLTS d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Xn_net3608226), .RN(n776), .Q(d_ff_Xn[26]) );
DFFRXLTS d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Xn_net3608226), .RN(n780), .Q(d_ff_Xn[27]) );
DFFRXLTS d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Xn_net3608226), .RN(n781), .Q(d_ff_Xn[28]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(first_mux_X[28]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_X[28]), .QN(n768)
);
DFFRXLTS d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Xn_net3608226), .RN(n777), .Q(d_ff_Xn[29]) );
DFFRXLTS d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Xn_net3608226), .RN(n779), .Q(d_ff_Xn[30]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(first_mux_X[30]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n780), .Q(d_ff2_X[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Xn_net3608226), .RN(n781), .Q(d_ff_Xn[31]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(first_mux_X[31]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n782), .Q(d_ff2_X[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(d_ff2_X[31]), .CK(reg_shift_y_net3608226), .RN(n782), .Q(d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Yn_net3608226), .RN(n778), .Q(d_ff_Yn[0]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(first_mux_Y[0]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n776), .Q(d_ff2_Y[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(d_ff2_Y[0]), .CK(reg_shift_y_net3608226),
.RN(n779), .Q(d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Yn_net3608226), .RN(n780), .Q(d_ff_Yn[1]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_1_ ( .D(first_mux_Y[1]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n781), .Q(d_ff2_Y[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(d_ff2_Y[1]), .CK(reg_shift_y_net3608226),
.RN(n773), .Q(d_ff3_sh_y_out[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Yn_net3608226), .RN(n771), .Q(d_ff_Yn[2]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_2_ ( .D(first_mux_Y[2]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n621), .Q(d_ff2_Y[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(d_ff2_Y[2]), .CK(reg_shift_y_net3608226),
.RN(n775), .Q(d_ff3_sh_y_out[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Yn_net3608226), .RN(n154), .Q(d_ff_Yn[3]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_3_ ( .D(first_mux_Y[3]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n774), .Q(d_ff2_Y[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(d_ff2_Y[3]), .CK(reg_shift_y_net3608226),
.RN(n771), .Q(d_ff3_sh_y_out[3]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Yn_net3608226), .RN(n773), .Q(d_ff_Yn[4]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_4_ ( .D(first_mux_Y[4]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n621), .Q(d_ff2_Y[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(d_ff2_Y[4]), .CK(reg_shift_y_net3608226),
.RN(n777), .Q(d_ff3_sh_y_out[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Yn_net3608226), .RN(n779), .Q(d_ff_Yn[5]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_5_ ( .D(first_mux_Y[5]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n780), .Q(d_ff2_Y[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(d_ff2_Y[5]), .CK(reg_shift_y_net3608226),
.RN(n781), .Q(d_ff3_sh_y_out[5]) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Yn_net3608226), .RN(n777), .Q(d_ff_Yn[6]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(first_mux_Y[6]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_Y[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(d_ff2_Y[6]), .CK(reg_shift_y_net3608226),
.RN(n778), .Q(d_ff3_sh_y_out[6]) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Yn_net3608226), .RN(n782), .Q(d_ff_Yn[7]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_7_ ( .D(first_mux_Y[7]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n779), .Q(d_ff2_Y[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(d_ff2_Y[7]), .CK(reg_shift_y_net3608226),
.RN(n782), .Q(d_ff3_sh_y_out[7]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Yn_net3608226), .RN(n778), .Q(d_ff_Yn[8]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(first_mux_Y[8]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_Y[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(d_ff2_Y[8]), .CK(reg_shift_y_net3608226),
.RN(n782), .Q(d_ff3_sh_y_out[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Yn_net3608226), .RN(n780), .Q(d_ff_Yn[9]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_9_ ( .D(first_mux_Y[9]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n781), .Q(d_ff2_Y[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(d_ff2_Y[9]), .CK(reg_shift_y_net3608226),
.RN(n776), .Q(d_ff3_sh_y_out[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Yn_net3608226), .RN(n776), .Q(d_ff_Yn[10]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_10_ ( .D(first_mux_Y[10]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n778), .Q(d_ff2_Y[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(d_ff2_Y[10]), .CK(reg_shift_y_net3608226), .RN(n781), .Q(d_ff3_sh_y_out[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Yn_net3608226), .RN(n777), .Q(d_ff_Yn[11]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_11_ ( .D(first_mux_Y[11]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_Y[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(d_ff2_Y[11]), .CK(reg_shift_y_net3608226), .RN(n778), .Q(d_ff3_sh_y_out[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Yn_net3608226), .RN(n777), .Q(d_ff_Yn[12]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_12_ ( .D(first_mux_Y[12]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n779), .Q(d_ff2_Y[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(d_ff2_Y[12]), .CK(reg_shift_y_net3608226), .RN(n780), .Q(d_ff3_sh_y_out[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Yn_net3608226), .RN(n781), .Q(d_ff_Yn[13]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_13_ ( .D(first_mux_Y[13]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n782), .Q(d_ff2_Y[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(d_ff2_Y[13]), .CK(reg_shift_y_net3608226), .RN(n779), .Q(d_ff3_sh_y_out[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Yn_net3608226), .RN(n780), .Q(d_ff_Yn[14]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_14_ ( .D(first_mux_Y[14]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n781), .Q(d_ff2_Y[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(d_ff2_Y[14]), .CK(reg_shift_y_net3608226), .RN(n782), .Q(d_ff3_sh_y_out[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Yn_net3608226), .RN(n782), .Q(d_ff_Yn[15]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_15_ ( .D(first_mux_Y[15]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n778), .Q(d_ff2_Y[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(d_ff2_Y[15]), .CK(reg_shift_y_net3608226), .RN(n782), .Q(d_ff3_sh_y_out[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Yn_net3608226), .RN(n779), .Q(d_ff_Yn[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_16_ ( .D(first_mux_Y[16]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n780), .Q(d_ff2_Y[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(d_ff2_Y[16]), .CK(reg_shift_y_net3608226), .RN(n787), .Q(d_ff3_sh_y_out[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Yn_net3608226), .RN(n774), .Q(d_ff_Yn[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(first_mux_Y[17]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n621), .Q(d_ff2_Y[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(d_ff2_Y[17]), .CK(reg_shift_y_net3608226), .RN(n775), .Q(d_ff3_sh_y_out[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Yn_net3608226), .RN(n621), .Q(d_ff_Yn[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(first_mux_Y[18]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n780), .Q(d_ff2_Y[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(d_ff2_Y[18]), .CK(reg_shift_y_net3608226), .RN(n777), .Q(d_ff3_sh_y_out[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Yn_net3608226), .RN(n781), .Q(d_ff_Yn[19]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(first_mux_Y[19]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n621), .Q(d_ff2_Y[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(d_ff2_Y[19]), .CK(reg_shift_y_net3608226), .RN(n778), .Q(d_ff3_sh_y_out[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Yn_net3608226), .RN(n782), .Q(d_ff_Yn[20]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_20_ ( .D(first_mux_Y[20]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n779), .Q(d_ff2_Y[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(d_ff2_Y[20]), .CK(reg_shift_y_net3608226), .RN(n780), .Q(d_ff3_sh_y_out[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Yn_net3608226), .RN(n781), .Q(d_ff_Yn[21]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_21_ ( .D(first_mux_Y[21]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_Y[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(d_ff2_Y[21]), .CK(reg_shift_y_net3608226), .RN(n782), .Q(d_ff3_sh_y_out[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Yn_net3608226), .RN(n778), .Q(d_ff_Yn[22]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_22_ ( .D(first_mux_Y[22]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n776), .Q(d_ff2_Y[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(d_ff2_Y[22]), .CK(reg_shift_y_net3608226), .RN(n780), .Q(d_ff3_sh_y_out[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Yn_net3608226), .RN(n621), .Q(d_ff_Yn[23]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_23_ ( .D(first_mux_Y[23]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n775), .Q(d_ff2_Y[23]), .QN(n767)
);
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Yn_net3608226), .RN(n782), .Q(d_ff_Yn[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Yn_net3608226), .RN(n787), .Q(d_ff_Yn[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Yn_net3608226), .RN(n781), .Q(d_ff_Yn[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Yn_net3608226), .RN(n775), .Q(d_ff_Yn[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Yn_net3608226), .RN(n778), .Q(d_ff_Yn[28]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Yn_net3608226), .RN(n778), .Q(d_ff_Yn[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Yn_net3608226), .RN(n787), .Q(d_ff_Yn[30]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_30_ ( .D(first_mux_Y[30]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n774), .Q(d_ff2_Y[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Yn_net3608226), .RN(n774), .Q(d_ff_Yn[31]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_31_ ( .D(first_mux_Y[31]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n774), .Q(d_ff2_Y[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(d_ff2_Y[31]), .CK(reg_shift_y_net3608226), .RN(n774), .Q(d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Zn_net3608226), .RN(n774), .Q(d_ff_Zn[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(first_mux_Z[0]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n774), .Q(d_ff2_Z[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Zn_net3608226), .RN(n774), .Q(d_ff_Zn[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(first_mux_Z[1]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n774), .Q(d_ff2_Z[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Zn_net3608226), .RN(n774), .Q(d_ff_Zn[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(first_mux_Z[2]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n774), .Q(d_ff2_Z[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Zn_net3608226), .RN(n773), .Q(d_ff_Zn[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(first_mux_Z[3]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n773), .Q(d_ff2_Z[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Zn_net3608226), .RN(n773), .Q(d_ff_Zn[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(first_mux_Z[4]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n773), .Q(d_ff2_Z[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Zn_net3608226), .RN(n773), .Q(d_ff_Zn[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(first_mux_Z[5]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n773), .Q(d_ff2_Z[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Zn_net3608226), .RN(n773), .Q(d_ff_Zn[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(first_mux_Z[6]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n773), .Q(d_ff2_Z[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Zn_net3608226), .RN(n773), .Q(d_ff_Zn[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(first_mux_Z[7]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n773), .Q(d_ff2_Z[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Zn_net3608226), .RN(n773), .Q(d_ff_Zn[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(first_mux_Z[8]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n773), .Q(d_ff2_Z[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Zn_net3608226), .RN(n772), .Q(d_ff_Zn[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(first_mux_Z[9]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n795), .Q(d_ff2_Z[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Zn_net3608226), .RN(n770), .Q(d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(first_mux_Z[10]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n772), .Q(d_ff2_Z[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Zn_net3608226), .RN(n795), .Q(d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(first_mux_Z[11]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n770), .Q(d_ff2_Z[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Zn_net3608226), .RN(n772), .Q(d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(first_mux_Z[12]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n795), .Q(d_ff2_Z[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Zn_net3608226), .RN(n770), .Q(d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(first_mux_Z[13]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n772), .Q(d_ff2_Z[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Zn_net3608226), .RN(n795), .Q(d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(first_mux_Z[14]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n770), .Q(d_ff2_Z[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Zn_net3608226), .RN(n771), .Q(d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(first_mux_Z[15]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n771), .Q(d_ff2_Z[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Zn_net3608226), .RN(n771), .Q(d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(first_mux_Z[16]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n771), .Q(d_ff2_Z[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Zn_net3608226), .RN(n771), .Q(d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(first_mux_Z[17]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n771), .Q(d_ff2_Z[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Zn_net3608226), .RN(n771), .Q(d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(first_mux_Z[18]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n771), .Q(d_ff2_Z[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Zn_net3608226), .RN(n771), .Q(d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(first_mux_Z[19]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n771), .Q(d_ff2_Z[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Zn_net3608226), .RN(n771), .Q(d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(first_mux_Z[20]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n771), .Q(d_ff2_Z[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Zn_net3608226), .RN(n772), .Q(d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(first_mux_Z[21]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n795), .Q(d_ff2_Z[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Zn_net3608226), .RN(n770), .Q(d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(first_mux_Z[22]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n604), .Q(d_ff2_Z[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Zn_net3608226), .RN(n154), .Q(d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(first_mux_Z[23]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n154), .Q(d_ff2_Z[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Zn_net3608226), .RN(n154), .Q(d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(first_mux_Z[24]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n154), .Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Zn_net3608226), .RN(n154), .Q(d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(first_mux_Z[25]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n604), .Q(d_ff2_Z[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Zn_net3608226), .RN(n604), .Q(d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(first_mux_Z[26]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n772), .Q(d_ff2_Z[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Zn_net3608226), .RN(n795), .Q(d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(first_mux_Z[27]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n770), .Q(d_ff2_Z[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Zn_net3608226), .RN(n772), .Q(d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(first_mux_Z[28]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n795), .Q(d_ff2_Z[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Zn_net3608226), .RN(n770), .Q(d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(first_mux_Z[29]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n772), .Q(d_ff2_Z[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Zn_net3608226), .RN(n795), .Q(d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(first_mux_Z[30]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n770), .Q(d_ff2_Z[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Zn_net3608226), .RN(n772), .Q(d_ff_Zn[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(first_mux_Z[31]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n795), .Q(d_ff2_Z[31]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(reg_shift_y_net3608226), .RN(n770), .Q(d_ff3_LUT_out[27]) );
DFFRX1TS VAR_CONT_temp_reg_1_ ( .D(n519), .CK(clk), .RN(n784), .Q(
cont_var_out[1]), .QN(n766) );
DFFRX2TS VAR_CONT_temp_reg_0_ ( .D(n518), .CK(clk), .RN(n622), .Q(
cont_var_out[0]), .QN(n765) );
DFFRX2TS ITER_CONT_temp_reg_0_ ( .D(n763), .CK(ITER_CONT_net3608262), .RN(
n784), .Q(cont_iter_out[0]), .QN(n763) );
DFFRX2TS ITER_CONT_temp_reg_3_ ( .D(ITER_CONT_N5), .CK(ITER_CONT_net3608262),
.RN(n791), .Q(cont_iter_out[3]), .QN(n762) );
DFFRX2TS ITER_CONT_temp_reg_2_ ( .D(ITER_CONT_N4), .CK(ITER_CONT_net3608262),
.RN(n783), .Q(cont_iter_out[2]), .QN(n761) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(mux_sal[0]), .CK(
d_ff5_data_out_net3608226), .RN(n778), .Q(data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(mux_sal[1]), .CK(
d_ff5_data_out_net3608226), .RN(n771), .Q(data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(mux_sal[2]), .CK(
d_ff5_data_out_net3608226), .RN(n604), .Q(data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(mux_sal[3]), .CK(
d_ff5_data_out_net3608226), .RN(n775), .Q(data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(mux_sal[4]), .CK(
d_ff5_data_out_net3608226), .RN(n778), .Q(data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(mux_sal[5]), .CK(
d_ff5_data_out_net3608226), .RN(n776), .Q(data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(mux_sal[6]), .CK(
d_ff5_data_out_net3608226), .RN(n776), .Q(data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(mux_sal[7]), .CK(
d_ff5_data_out_net3608226), .RN(n782), .Q(data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(mux_sal[8]), .CK(
d_ff5_data_out_net3608226), .RN(n781), .Q(data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(mux_sal[9]), .CK(
d_ff5_data_out_net3608226), .RN(n780), .Q(data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(mux_sal[10]), .CK(
d_ff5_data_out_net3608226), .RN(n780), .Q(data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(mux_sal[11]), .CK(
d_ff5_data_out_net3608226), .RN(n779), .Q(data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(mux_sal[12]), .CK(
d_ff5_data_out_net3608226), .RN(n776), .Q(data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(mux_sal[13]), .CK(
d_ff5_data_out_net3608226), .RN(n776), .Q(data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(mux_sal[14]), .CK(
d_ff5_data_out_net3608226), .RN(n778), .Q(data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(mux_sal[15]), .CK(
d_ff5_data_out_net3608226), .RN(n777), .Q(data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(mux_sal[16]), .CK(
d_ff5_data_out_net3608226), .RN(n781), .Q(data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(mux_sal[17]), .CK(
d_ff5_data_out_net3608226), .RN(n604), .Q(data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(mux_sal[18]), .CK(
d_ff5_data_out_net3608226), .RN(n775), .Q(data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(mux_sal[19]), .CK(
d_ff5_data_out_net3608226), .RN(n776), .Q(data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(mux_sal[20]), .CK(
d_ff5_data_out_net3608226), .RN(n776), .Q(data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(mux_sal[21]), .CK(
d_ff5_data_out_net3608226), .RN(n781), .Q(data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(mux_sal[22]), .CK(
d_ff5_data_out_net3608226), .RN(n774), .Q(data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(mux_sal[23]), .CK(
d_ff5_data_out_net3608226), .RN(n773), .Q(data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(mux_sal[24]), .CK(
d_ff5_data_out_net3608226), .RN(n776), .Q(data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(mux_sal[25]), .CK(
d_ff5_data_out_net3608226), .RN(n775), .Q(data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(mux_sal[26]), .CK(
d_ff5_data_out_net3608226), .RN(n795), .Q(data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(mux_sal[27]), .CK(
d_ff5_data_out_net3608226), .RN(n778), .Q(data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(mux_sal[28]), .CK(
d_ff5_data_out_net3608226), .RN(n785), .Q(data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(mux_sal[29]), .CK(
d_ff5_data_out_net3608226), .RN(n785), .Q(data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(mux_sal[30]), .CK(
d_ff5_data_out_net3608226), .RN(n774), .Q(data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(fmtted_Result_31_), .CK(
d_ff5_data_out_net3608226), .RN(n774), .Q(data_output[31]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n612), .CK(clk), .RN(n785),
.Q(inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n791), .Q(
inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n783), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n786), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n792), .Q(
inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(d_ff2_Z[31]), .CK(reg_shift_y_net3608226),
.RN(n772), .Q(d_ff3_sign_out) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n787), .Q(
inst_CORDIC_FSM_v3_state_reg[2]) );
DFFSX1TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n622), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(first_mux_X[27]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n778), .Q(d_ff2_X[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(first_mux_Y[27]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n621), .Q(d_ff2_Y[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(first_mux_X[29]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n782), .Q(d_ff2_X[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(first_mux_Y[29]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n779), .Q(d_ff2_Y[29]) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(operation), .CK(reg_Z0_net3608226),
.RN(n793), .Q(d_ff1_operation_out) );
DFFRX4TS ITER_CONT_temp_reg_1_ ( .D(ITER_CONT_N3), .CK(ITER_CONT_net3608262),
.RN(n794), .Q(cont_iter_out[1]), .QN(n764) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(first_mux_X[24]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n776), .Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(first_mux_X[26]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n776), .Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(first_mux_X[25]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(first_mux_Y[26]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n785), .Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(first_mux_Y[25]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(first_mux_Y[24]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n775), .Q(d_ff2_Y[24]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(first_mux_Y[28]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n782), .Q(d_ff2_Y[28]), .QN(n769)
);
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n786), .Q(
inst_CORDIC_FSM_v3_state_reg[7]) );
ADDFX1TS intadd_422_U4 ( .A(d_ff2_Y[24]), .B(n764), .CI(intadd_422_CI), .CO(
intadd_422_n3), .S(sh_exp_y[1]) );
ADDFX1TS intadd_421_U4 ( .A(n764), .B(d_ff2_X[24]), .CI(intadd_421_CI), .CO(
intadd_421_n3), .S(sh_exp_x[1]) );
ADDFX1TS intadd_422_U3 ( .A(d_ff2_Y[25]), .B(n761), .CI(intadd_422_n3), .CO(
intadd_422_n2), .S(sh_exp_y[2]) );
ADDFX1TS intadd_421_U3 ( .A(d_ff2_X[25]), .B(n761), .CI(intadd_421_n3), .CO(
intadd_421_n2), .S(sh_exp_x[2]) );
ADDFX1TS intadd_421_U2 ( .A(d_ff2_X[26]), .B(n762), .CI(intadd_421_n2), .CO(
intadd_421_n1), .S(sh_exp_x[3]) );
ADDFX1TS intadd_422_U2 ( .A(d_ff2_Y[26]), .B(n762), .CI(intadd_422_n2), .CO(
intadd_422_n1), .S(sh_exp_y[3]) );
AOI222X1TS U407 ( .A0(n685), .A1(d_ff2_X[30]), .B0(n668), .B1(d_ff2_Y[30]),
.C0(n731), .C1(d_ff2_Z[30]), .Y(n671) );
AOI222X1TS U408 ( .A0(n744), .A1(d_ff2_X[6]), .B0(n743), .B1(d_ff2_Y[6]),
.C0(n609), .C1(d_ff2_Z[6]), .Y(n673) );
AOI222X1TS U409 ( .A0(n744), .A1(d_ff2_X[5]), .B0(n739), .B1(d_ff2_Y[5]),
.C0(n609), .C1(d_ff2_Z[5]), .Y(n675) );
OAI21XLTS U410 ( .A0(d_ff1_operation_out), .A1(n613), .B0(n698), .Y(n696) );
BUFX3TS U411 ( .A(n709), .Y(n614) );
INVX4TS U412 ( .A(n716), .Y(n646) );
AOI222X1TS U413 ( .A0(n685), .A1(d_ff2_X[27]), .B0(n668), .B1(d_ff2_Y[27]),
.C0(n609), .C1(d_ff2_Z[27]), .Y(n652) );
AOI222X1TS U414 ( .A0(n685), .A1(d_ff2_X[25]), .B0(n743), .B1(d_ff2_Y[25]),
.C0(n609), .C1(d_ff2_Z[25]), .Y(n653) );
AOI222X1TS U415 ( .A0(n669), .A1(d_ff2_X[23]), .B0(n739), .B1(d_ff2_Y[23]),
.C0(n609), .C1(d_ff2_Z[23]), .Y(n647) );
AOI222X1TS U416 ( .A0(n669), .A1(d_ff2_X[15]), .B0(n684), .B1(d_ff2_Y[15]),
.C0(n609), .C1(d_ff2_Z[15]), .Y(n659) );
NAND3X1TS U417 ( .A(enab_cont_iter), .B(n747), .C(n720), .Y(n635) );
INVX3TS U418 ( .A(n703), .Y(n702) );
NAND3BX1TS U419 ( .AN(inst_CORDIC_FSM_v3_state_reg[6]), .B(n624), .C(
inst_CORDIC_FSM_v3_state_reg[4]), .Y(n717) );
INVX3TS U420 ( .A(n640), .Y(n740) );
INVX3TS U421 ( .A(n640), .Y(n722) );
INVX3TS U422 ( .A(n640), .Y(n744) );
OR2X4TS U423 ( .A(cont_iter_out[2]), .B(n695), .Y(n703) );
NAND4BXLTS U424 ( .AN(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[3]), .C(n632), .D(n631), .Y(n636) );
OR2X2TS U425 ( .A(n765), .B(cont_var_out[1]), .Y(n640) );
OR2X2TS U426 ( .A(n766), .B(cont_var_out[0]), .Y(n620) );
BUFX3TS U427 ( .A(n154), .Y(n604) );
NAND2BXLTS U428 ( .AN(inst_CORDIC_FSM_v3_state_reg[3]), .B(n631), .Y(n619)
);
NAND3BXLTS U429 ( .AN(n619), .B(inst_CORDIC_FSM_v3_state_reg[1]), .C(n632),
.Y(n629) );
NAND3XLTS U430 ( .A(n717), .B(n641), .C(n694), .Y(n753) );
AOI222X1TS U431 ( .A0(n722), .A1(d_ff3_sh_y_out[6]), .B0(n721), .B1(
d_ff3_sh_x_out[6]), .C0(n746), .C1(d_ff3_LUT_out[6]), .Y(n683) );
AOI222X1TS U432 ( .A0(n722), .A1(d_ff3_sh_y_out[9]), .B0(n668), .B1(
d_ff3_sh_x_out[9]), .C0(n746), .C1(d_ff3_LUT_out[9]), .Y(n682) );
AOI222X1TS U433 ( .A0(n722), .A1(d_ff3_sh_y_out[10]), .B0(n684), .B1(
d_ff3_sh_x_out[10]), .C0(n746), .C1(d_ff3_LUT_out[10]), .Y(n687) );
AOI222X1TS U434 ( .A0(n722), .A1(d_ff3_sh_y_out[21]), .B0(n668), .B1(
d_ff3_sh_x_out[21]), .C0(n746), .C1(d_ff3_LUT_out[21]), .Y(n688) );
AOI222X1TS U435 ( .A0(n722), .A1(d_ff3_sh_y_out[23]), .B0(n668), .B1(
d_ff3_sh_x_out[23]), .C0(n746), .C1(d_ff3_LUT_out[23]), .Y(n693) );
AOI222X1TS U436 ( .A0(n722), .A1(d_ff3_sh_y_out[26]), .B0(n684), .B1(
d_ff3_sh_x_out[26]), .C0(n731), .C1(d_ff3_LUT_out[26]), .Y(n643) );
AOI222X1TS U437 ( .A0(n744), .A1(d_ff2_X[3]), .B0(n684), .B1(d_ff2_Y[3]),
.C0(n731), .C1(d_ff2_Z[3]), .Y(n674) );
AOI222X1TS U438 ( .A0(n669), .A1(d_ff2_X[12]), .B0(n739), .B1(d_ff2_Y[12]),
.C0(n731), .C1(d_ff2_Z[12]), .Y(n649) );
AOI222X1TS U439 ( .A0(n669), .A1(d_ff2_X[18]), .B0(n684), .B1(d_ff2_Y[18]),
.C0(n731), .C1(d_ff2_Z[18]), .Y(n662) );
AOI222X1TS U440 ( .A0(n685), .A1(d_ff2_X[24]), .B0(n743), .B1(d_ff2_Y[24]),
.C0(n608), .C1(d_ff2_Z[24]), .Y(n667) );
AOI222X1TS U441 ( .A0(n685), .A1(d_ff2_X[26]), .B0(n739), .B1(d_ff2_Y[26]),
.C0(n731), .C1(d_ff2_Z[26]), .Y(n651) );
AOI222X1TS U442 ( .A0(n685), .A1(d_ff2_X[29]), .B0(n721), .B1(d_ff2_Y[29]),
.C0(n731), .C1(d_ff2_Z[29]), .Y(n661) );
OR2X1TS U443 ( .A(d_ff_Xn[25]), .B(n633), .Y(first_mux_X[25]) );
OR2X1TS U444 ( .A(d_ff_Xn[26]), .B(n633), .Y(first_mux_X[26]) );
OR2X1TS U445 ( .A(d_ff_Xn[24]), .B(n633), .Y(first_mux_X[24]) );
NOR2XLTS U446 ( .A(n720), .B(n628), .Y(ITER_CONT_N3) );
OR2X1TS U447 ( .A(d_ff_Xn[29]), .B(n633), .Y(first_mux_X[29]) );
OR2X1TS U448 ( .A(d_ff_Xn[27]), .B(n633), .Y(first_mux_X[27]) );
OAI21XLTS U449 ( .A0(beg_fsm_cordic), .A1(n715), .B0(n639), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
OAI21XLTS U450 ( .A0(n630), .A1(n641), .B0(n629), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
AO22XLTS U451 ( .A0(n712), .A1(d_ff_Yn[30]), .B0(n711), .B1(d_ff_Xn[30]),
.Y(mux_sal[30]) );
AO22XLTS U452 ( .A0(n712), .A1(d_ff_Yn[29]), .B0(n711), .B1(d_ff_Xn[29]),
.Y(mux_sal[29]) );
AO22XLTS U453 ( .A0(n712), .A1(d_ff_Yn[28]), .B0(n711), .B1(d_ff_Xn[28]),
.Y(mux_sal[28]) );
AO22XLTS U454 ( .A0(n712), .A1(d_ff_Yn[27]), .B0(n711), .B1(d_ff_Xn[27]),
.Y(mux_sal[27]) );
AO22XLTS U455 ( .A0(n614), .A1(d_ff_Yn[26]), .B0(n711), .B1(d_ff_Xn[26]),
.Y(mux_sal[26]) );
AO22XLTS U456 ( .A0(n614), .A1(d_ff_Yn[25]), .B0(n711), .B1(d_ff_Xn[25]),
.Y(mux_sal[25]) );
AO22XLTS U457 ( .A0(n614), .A1(d_ff_Yn[24]), .B0(n711), .B1(d_ff_Xn[24]),
.Y(mux_sal[24]) );
AO22XLTS U458 ( .A0(n614), .A1(d_ff_Yn[23]), .B0(n711), .B1(d_ff_Xn[23]),
.Y(mux_sal[23]) );
AO22XLTS U459 ( .A0(n614), .A1(d_ff_Yn[22]), .B0(n711), .B1(d_ff_Xn[22]),
.Y(mux_sal[22]) );
AO22XLTS U460 ( .A0(n614), .A1(d_ff_Yn[21]), .B0(n711), .B1(d_ff_Xn[21]),
.Y(mux_sal[21]) );
AO22XLTS U461 ( .A0(n614), .A1(d_ff_Yn[20]), .B0(n711), .B1(d_ff_Xn[20]),
.Y(mux_sal[20]) );
AO22XLTS U462 ( .A0(n614), .A1(d_ff_Yn[19]), .B0(n711), .B1(d_ff_Xn[19]),
.Y(mux_sal[19]) );
AO22XLTS U463 ( .A0(n614), .A1(d_ff_Yn[18]), .B0(n708), .B1(d_ff_Xn[18]),
.Y(mux_sal[18]) );
AO22XLTS U464 ( .A0(n614), .A1(d_ff_Yn[17]), .B0(n710), .B1(d_ff_Xn[17]),
.Y(mux_sal[17]) );
AO22XLTS U465 ( .A0(n614), .A1(d_ff_Yn[16]), .B0(n710), .B1(d_ff_Xn[16]),
.Y(mux_sal[16]) );
AO22XLTS U466 ( .A0(n614), .A1(d_ff_Yn[15]), .B0(n710), .B1(d_ff_Xn[15]),
.Y(mux_sal[15]) );
AO22XLTS U467 ( .A0(n614), .A1(d_ff_Yn[14]), .B0(n710), .B1(d_ff_Xn[14]),
.Y(mux_sal[14]) );
AO22XLTS U468 ( .A0(n614), .A1(d_ff_Yn[13]), .B0(n710), .B1(d_ff_Xn[13]),
.Y(mux_sal[13]) );
AO22XLTS U469 ( .A0(n709), .A1(d_ff_Yn[12]), .B0(n710), .B1(d_ff_Xn[12]),
.Y(mux_sal[12]) );
AO22XLTS U470 ( .A0(n709), .A1(d_ff_Yn[11]), .B0(n710), .B1(d_ff_Xn[11]),
.Y(mux_sal[11]) );
AO22XLTS U471 ( .A0(n709), .A1(d_ff_Yn[10]), .B0(n708), .B1(d_ff_Xn[10]),
.Y(mux_sal[10]) );
AO22XLTS U472 ( .A0(n709), .A1(d_ff_Yn[9]), .B0(n708), .B1(d_ff_Xn[9]), .Y(
mux_sal[9]) );
AO22XLTS U473 ( .A0(n709), .A1(d_ff_Yn[8]), .B0(n708), .B1(d_ff_Xn[8]), .Y(
mux_sal[8]) );
AO22XLTS U474 ( .A0(n709), .A1(d_ff_Yn[7]), .B0(n708), .B1(d_ff_Xn[7]), .Y(
mux_sal[7]) );
AO22XLTS U475 ( .A0(n709), .A1(d_ff_Yn[6]), .B0(n708), .B1(d_ff_Xn[6]), .Y(
mux_sal[6]) );
AO22XLTS U476 ( .A0(n709), .A1(d_ff_Yn[5]), .B0(n708), .B1(d_ff_Xn[5]), .Y(
mux_sal[5]) );
AO22XLTS U477 ( .A0(n709), .A1(d_ff_Yn[4]), .B0(n708), .B1(d_ff_Xn[4]), .Y(
mux_sal[4]) );
AO22XLTS U478 ( .A0(n709), .A1(d_ff_Yn[3]), .B0(n708), .B1(d_ff_Xn[3]), .Y(
mux_sal[3]) );
AO22XLTS U479 ( .A0(n709), .A1(d_ff_Yn[2]), .B0(n708), .B1(d_ff_Xn[2]), .Y(
mux_sal[2]) );
AO22XLTS U480 ( .A0(n709), .A1(d_ff_Yn[1]), .B0(n708), .B1(d_ff_Xn[1]), .Y(
mux_sal[1]) );
AO22XLTS U481 ( .A0(n709), .A1(d_ff_Yn[0]), .B0(n711), .B1(d_ff_Xn[0]), .Y(
mux_sal[0]) );
NOR2XLTS U482 ( .A(n630), .B(n529), .Y(ITER_CONT_N5) );
OAI211XLTS U483 ( .A0(n754), .A1(n640), .B0(n620), .C0(n642), .Y(n519) );
AO22XLTS U484 ( .A0(n714), .A1(d_ff1_Z[31]), .B0(n707), .B1(d_ff_Zn[31]),
.Y(first_mux_Z[31]) );
AO22XLTS U485 ( .A0(n714), .A1(d_ff1_Z[30]), .B0(n705), .B1(d_ff_Zn[30]),
.Y(first_mux_Z[30]) );
AO22XLTS U486 ( .A0(n714), .A1(d_ff1_Z[29]), .B0(n705), .B1(d_ff_Zn[29]),
.Y(first_mux_Z[29]) );
AO22XLTS U487 ( .A0(n714), .A1(d_ff1_Z[28]), .B0(n705), .B1(d_ff_Zn[28]),
.Y(first_mux_Z[28]) );
AO22XLTS U488 ( .A0(n706), .A1(d_ff1_Z[27]), .B0(n705), .B1(d_ff_Zn[27]),
.Y(first_mux_Z[27]) );
AO22XLTS U489 ( .A0(n706), .A1(d_ff1_Z[26]), .B0(n705), .B1(d_ff_Zn[26]),
.Y(first_mux_Z[26]) );
AO22XLTS U490 ( .A0(n706), .A1(d_ff1_Z[25]), .B0(n705), .B1(d_ff_Zn[25]),
.Y(first_mux_Z[25]) );
AO22XLTS U491 ( .A0(n706), .A1(d_ff1_Z[24]), .B0(n705), .B1(d_ff_Zn[24]),
.Y(first_mux_Z[24]) );
AO22XLTS U492 ( .A0(n706), .A1(d_ff1_Z[23]), .B0(n705), .B1(d_ff_Zn[23]),
.Y(first_mux_Z[23]) );
AO22XLTS U493 ( .A0(n706), .A1(d_ff1_Z[22]), .B0(n705), .B1(d_ff_Zn[22]),
.Y(first_mux_Z[22]) );
AO22XLTS U494 ( .A0(n706), .A1(d_ff1_Z[21]), .B0(n705), .B1(d_ff_Zn[21]),
.Y(first_mux_Z[21]) );
AO22XLTS U495 ( .A0(n706), .A1(d_ff1_Z[20]), .B0(n705), .B1(d_ff_Zn[20]),
.Y(first_mux_Z[20]) );
AO22XLTS U496 ( .A0(n706), .A1(d_ff1_Z[19]), .B0(n705), .B1(d_ff_Zn[19]),
.Y(first_mux_Z[19]) );
AO22XLTS U497 ( .A0(n706), .A1(d_ff1_Z[18]), .B0(n705), .B1(d_ff_Zn[18]),
.Y(first_mux_Z[18]) );
AO22XLTS U498 ( .A0(n706), .A1(d_ff1_Z[17]), .B0(n705), .B1(d_ff_Zn[17]),
.Y(first_mux_Z[17]) );
AO22XLTS U499 ( .A0(n706), .A1(d_ff1_Z[16]), .B0(n707), .B1(d_ff_Zn[16]),
.Y(first_mux_Z[16]) );
AO22XLTS U500 ( .A0(n706), .A1(d_ff1_Z[15]), .B0(n707), .B1(d_ff_Zn[15]),
.Y(first_mux_Z[15]) );
AO22XLTS U501 ( .A0(n704), .A1(d_ff1_Z[14]), .B0(n707), .B1(d_ff_Zn[14]),
.Y(first_mux_Z[14]) );
AO22XLTS U502 ( .A0(n704), .A1(d_ff1_Z[13]), .B0(n707), .B1(d_ff_Zn[13]),
.Y(first_mux_Z[13]) );
AO22XLTS U503 ( .A0(n704), .A1(d_ff1_Z[12]), .B0(n707), .B1(d_ff_Zn[12]),
.Y(first_mux_Z[12]) );
AO22XLTS U504 ( .A0(n704), .A1(d_ff1_Z[11]), .B0(n707), .B1(d_ff_Zn[11]),
.Y(first_mux_Z[11]) );
AO22XLTS U505 ( .A0(n704), .A1(d_ff1_Z[10]), .B0(n707), .B1(d_ff_Zn[10]),
.Y(first_mux_Z[10]) );
AO22XLTS U506 ( .A0(n704), .A1(d_ff1_Z[9]), .B0(n707), .B1(d_ff_Zn[9]), .Y(
first_mux_Z[9]) );
AO22XLTS U507 ( .A0(n704), .A1(d_ff1_Z[8]), .B0(n707), .B1(d_ff_Zn[8]), .Y(
first_mux_Z[8]) );
AO22XLTS U508 ( .A0(n704), .A1(d_ff1_Z[7]), .B0(n707), .B1(d_ff_Zn[7]), .Y(
first_mux_Z[7]) );
AO22XLTS U509 ( .A0(n704), .A1(d_ff1_Z[6]), .B0(n707), .B1(d_ff_Zn[6]), .Y(
first_mux_Z[6]) );
AO22XLTS U510 ( .A0(n704), .A1(d_ff1_Z[5]), .B0(n707), .B1(d_ff_Zn[5]), .Y(
first_mux_Z[5]) );
AO22XLTS U511 ( .A0(n704), .A1(d_ff1_Z[4]), .B0(n707), .B1(d_ff_Zn[4]), .Y(
first_mux_Z[4]) );
AO22XLTS U512 ( .A0(n704), .A1(d_ff1_Z[3]), .B0(n703), .B1(d_ff_Zn[3]), .Y(
first_mux_Z[3]) );
AO22XLTS U513 ( .A0(n702), .A1(d_ff1_Z[2]), .B0(n703), .B1(d_ff_Zn[2]), .Y(
first_mux_Z[2]) );
AO22XLTS U514 ( .A0(n704), .A1(d_ff1_Z[1]), .B0(n703), .B1(d_ff_Zn[1]), .Y(
first_mux_Z[1]) );
AO22XLTS U515 ( .A0(n714), .A1(d_ff1_Z[0]), .B0(n703), .B1(d_ff_Zn[0]), .Y(
first_mux_Z[0]) );
OR2X1TS U516 ( .A(d_ff_Xn[28]), .B(n633), .Y(first_mux_X[28]) );
OR2X1TS U517 ( .A(d_ff_Xn[20]), .B(n702), .Y(first_mux_X[20]) );
OR2X1TS U518 ( .A(d_ff_Xn[19]), .B(n702), .Y(first_mux_X[19]) );
OR2X1TS U519 ( .A(d_ff_Xn[17]), .B(n702), .Y(first_mux_X[17]) );
OR2X1TS U520 ( .A(d_ff_Xn[14]), .B(n702), .Y(first_mux_X[14]) );
OR2X1TS U521 ( .A(d_ff_Xn[13]), .B(n633), .Y(first_mux_X[13]) );
OR2X1TS U522 ( .A(d_ff_Xn[7]), .B(n633), .Y(first_mux_X[7]) );
OR2X1TS U523 ( .A(d_ff_Xn[6]), .B(n702), .Y(first_mux_X[6]) );
OR2X1TS U524 ( .A(d_ff_Xn[5]), .B(n702), .Y(first_mux_X[5]) );
OR2X1TS U525 ( .A(d_ff_Xn[2]), .B(n702), .Y(first_mux_X[2]) );
XOR2XLTS U526 ( .A(d_ff2_Y[30]), .B(n755), .Y(sh_exp_y[7]) );
OAI21XLTS U527 ( .A0(n757), .A1(n769), .B0(n756), .Y(sh_exp_y[5]) );
XOR2XLTS U528 ( .A(d_ff2_X[30]), .B(n758), .Y(sh_exp_x[7]) );
OAI21XLTS U529 ( .A0(n760), .A1(n768), .B0(n759), .Y(sh_exp_x[5]) );
OAI21XLTS U530 ( .A0(ack_cordic), .A1(n637), .B0(n635), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
OR4X2TS U531 ( .A(inst_CORDIC_FSM_v3_state_reg[3]), .B(
inst_CORDIC_FSM_v3_state_reg[1]), .C(inst_CORDIC_FSM_v3_state_reg[0]),
.D(inst_CORDIC_FSM_v3_state_reg[5]), .Y(n605) );
BUFX4TS U532 ( .A(n646), .Y(n731) );
INVX2TS U533 ( .A(n697), .Y(n710) );
INVX2TS U534 ( .A(n731), .Y(n607) );
INVX2TS U535 ( .A(n607), .Y(n608) );
INVX2TS U536 ( .A(n607), .Y(n609) );
INVX2TS U537 ( .A(n620), .Y(n739) );
INVX4TS U538 ( .A(n620), .Y(n668) );
INVX2TS U539 ( .A(n605), .Y(n610) );
OAI21XLTS U540 ( .A0(cont_iter_out[0]), .A1(n537), .B0(n752), .Y(n521) );
INVX2TS U541 ( .A(n752), .Y(n751) );
OAI21XLTS U542 ( .A0(n609), .A1(n717), .B0(n636), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
NAND3X2TS U543 ( .A(n762), .B(n763), .C(n764), .Y(n695) );
BUFX4TS U544 ( .A(n772), .Y(n773) );
BUFX4TS U545 ( .A(n621), .Y(n781) );
BUFX4TS U546 ( .A(n621), .Y(n780) );
BUFX3TS U547 ( .A(n621), .Y(n622) );
BUFX3TS U548 ( .A(n604), .Y(n621) );
BUFX4TS U549 ( .A(n604), .Y(n775) );
BUFX4TS U550 ( .A(n775), .Y(n777) );
BUFX4TS U551 ( .A(n775), .Y(n782) );
BUFX4TS U552 ( .A(n775), .Y(n776) );
BUFX4TS U553 ( .A(n792), .Y(n778) );
BUFX4TS U554 ( .A(n622), .Y(n793) );
BUFX4TS U555 ( .A(n794), .Y(n787) );
BUFX4TS U556 ( .A(n791), .Y(n785) );
BUFX4TS U557 ( .A(n783), .Y(n792) );
NOR2X4TS U558 ( .A(n761), .B(n762), .Y(n747) );
AOI222X1TS U559 ( .A0(n722), .A1(d_ff3_sh_y_out[8]), .B0(n668), .B1(
d_ff3_sh_x_out[8]), .C0(n746), .C1(d_ff3_LUT_out[8]), .Y(n691) );
AOI222X1TS U560 ( .A0(n722), .A1(d_ff3_sh_y_out[12]), .B0(n668), .B1(
d_ff3_sh_x_out[12]), .C0(n746), .C1(d_ff3_LUT_out[12]), .Y(n692) );
AOI222X1TS U561 ( .A0(n722), .A1(d_ff3_sh_y_out[25]), .B0(n668), .B1(
d_ff3_sh_x_out[25]), .C0(n746), .C1(d_ff3_LUT_out[25]), .Y(n690) );
AOI222X1TS U562 ( .A0(n722), .A1(d_ff3_sh_y_out[24]), .B0(n743), .B1(
d_ff3_sh_x_out[24]), .C0(n746), .C1(d_ff3_LUT_out[24]), .Y(n689) );
BUFX4TS U563 ( .A(n646), .Y(n746) );
INVX2TS U564 ( .A(inst_CORDIC_FSM_v3_state_next[3]), .Y(n611) );
INVX2TS U565 ( .A(n611), .Y(n612) );
INVX2TS U566 ( .A(n606), .Y(n613) );
INVX4TS U567 ( .A(n620), .Y(n721) );
CLKINVX3TS U568 ( .A(n620), .Y(n684) );
INVX4TS U569 ( .A(n620), .Y(n743) );
NOR2X2TS U570 ( .A(n694), .B(n620), .Y(enab_d_ff4_Zn) );
NOR2X4TS U571 ( .A(n763), .B(n764), .Y(n720) );
BUFX4TS U572 ( .A(n770), .Y(n771) );
BUFX4TS U573 ( .A(n795), .Y(n774) );
BUFX3TS U574 ( .A(n604), .Y(n795) );
NOR3BX2TS U575 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n617), .Y(ready_cordic) );
OAI32X4TS U576 ( .A0(n615), .A1(d_ff1_operation_out), .A2(n613), .B0(
d_ff1_shift_region_flag_out_0_), .B1(n698), .Y(n699) );
OAI21XLTS U577 ( .A0(cont_iter_out[1]), .A1(n749), .B0(n634), .Y(n534) );
OAI21XLTS U578 ( .A0(n747), .A1(cont_iter_out[1]), .B0(n634), .Y(n536) );
AOI21X2TS U579 ( .A0(cont_iter_out[2]), .A1(n762), .B0(n623), .Y(n634) );
OR2X1TS U580 ( .A(d_ff_Xn[3]), .B(n702), .Y(first_mux_X[3]) );
OR2X1TS U581 ( .A(d_ff_Xn[12]), .B(n702), .Y(first_mux_X[12]) );
OR2X1TS U582 ( .A(d_ff_Xn[1]), .B(n702), .Y(first_mux_X[1]) );
INVX4TS U583 ( .A(n710), .Y(n709) );
NOR2XLTS U584 ( .A(n694), .B(n640), .Y(enab_d_ff4_Yn) );
OR2X1TS U585 ( .A(d_ff_Xn[16]), .B(n702), .Y(first_mux_X[16]) );
OR2X1TS U586 ( .A(d_ff_Xn[10]), .B(n702), .Y(first_mux_X[10]) );
OAI211XLTS U587 ( .A0(n628), .A1(n627), .B0(n626), .C0(n695), .Y(n527) );
NOR2X1TS U588 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[6]), .Y(n618) );
NAND2X1TS U589 ( .A(n610), .B(n618), .Y(n617) );
NOR3BX1TS U590 ( .AN(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[7]), .C(n617), .Y(
inst_CORDIC_FSM_v3_state_next[3]) );
INVX2TS U591 ( .A(n747), .Y(n537) );
NAND2X1TS U592 ( .A(n761), .B(cont_iter_out[3]), .Y(n627) );
INVX2TS U593 ( .A(n627), .Y(n623) );
NAND2X1TS U594 ( .A(n537), .B(cont_iter_out[0]), .Y(n752) );
NOR2X1TS U595 ( .A(n623), .B(n751), .Y(n748) );
OAI211X1TS U596 ( .A0(cont_iter_out[3]), .A1(n763), .B0(n761), .C0(n764),
.Y(n750) );
OAI21XLTS U597 ( .A0(n748), .A1(n764), .B0(n750), .Y(n526) );
NAND2X1TS U598 ( .A(n720), .B(n761), .Y(n626) );
OAI31X1TS U599 ( .A0(cont_iter_out[3]), .A1(cont_iter_out[1]), .A2(n761),
.B0(n626), .Y(n528) );
OAI31X4TS U600 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[3]), .A2(n763),
.B0(n537), .Y(n749) );
OAI21XLTS U601 ( .A0(n747), .A1(n764), .B0(n749), .Y(n531) );
OAI21XLTS U602 ( .A0(n764), .A1(n749), .B0(n627), .Y(n532) );
NOR3BX1TS U603 ( .AN(n618), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[2]), .Y(n631) );
NOR2X1TS U604 ( .A(inst_CORDIC_FSM_v3_state_reg[0]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .Y(n632) );
NOR2X1TS U605 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(n619), .Y(n625) );
NAND3BX1TS U606 ( .AN(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(n625), .Y(n715) );
NAND2X1TS U607 ( .A(n629), .B(n715), .Y(enab_d_ff_RB1) );
INVX2TS U608 ( .A(ready_add_subt), .Y(n694) );
INVX2TS U609 ( .A(rst), .Y(n154) );
BUFX3TS U610 ( .A(n621), .Y(n786) );
BUFX3TS U611 ( .A(n621), .Y(n784) );
BUFX3TS U612 ( .A(n795), .Y(n783) );
BUFX3TS U613 ( .A(n770), .Y(n791) );
BUFX3TS U614 ( .A(n775), .Y(n779) );
BUFX3TS U615 ( .A(n622), .Y(n790) );
BUFX3TS U616 ( .A(n772), .Y(n794) );
BUFX3TS U617 ( .A(n604), .Y(n770) );
BUFX3TS U618 ( .A(n622), .Y(n789) );
BUFX3TS U619 ( .A(n604), .Y(n772) );
BUFX3TS U620 ( .A(n622), .Y(n788) );
NAND2X1TS U621 ( .A(n634), .B(n752), .Y(n523) );
NOR3BX1TS U622 ( .AN(n610), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[2]), .Y(n624) );
NAND3BX1TS U623 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[6]), .C(n624), .Y(n641) );
INVX2TS U624 ( .A(n641), .Y(enab_cont_iter) );
INVX2TS U625 ( .A(ready_cordic), .Y(n637) );
NAND2X1TS U626 ( .A(n637), .B(n635), .Y(enab_d_ff5_data_out) );
NAND3BX1TS U627 ( .AN(inst_CORDIC_FSM_v3_state_reg[0]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(n625), .Y(n718) );
NAND2X1TS U628 ( .A(n717), .B(n718), .Y(beg_add_subt) );
NAND2X1TS U629 ( .A(n767), .B(cont_iter_out[0]), .Y(intadd_422_CI) );
OAI21XLTS U630 ( .A0(cont_iter_out[0]), .A1(n767), .B0(intadd_422_CI), .Y(
sh_exp_y[0]) );
NAND2X1TS U631 ( .A(n616), .B(cont_iter_out[0]), .Y(intadd_421_CI) );
OAI21XLTS U632 ( .A0(cont_iter_out[0]), .A1(n616), .B0(intadd_421_CI), .Y(
sh_exp_x[0]) );
NOR2X1TS U633 ( .A(cont_iter_out[0]), .B(cont_iter_out[1]), .Y(n628) );
NOR2X1TS U634 ( .A(d_ff2_X[27]), .B(intadd_421_n1), .Y(n760) );
OR3X1TS U635 ( .A(d_ff2_X[28]), .B(d_ff2_X[27]), .C(intadd_421_n1), .Y(n759)
);
NOR2X1TS U636 ( .A(d_ff2_Y[27]), .B(intadd_422_n1), .Y(n757) );
OR3X1TS U637 ( .A(d_ff2_Y[28]), .B(d_ff2_Y[27]), .C(intadd_422_n1), .Y(n756)
);
NAND2X1TS U638 ( .A(cont_iter_out[2]), .B(n720), .Y(n719) );
CLKAND2X2TS U639 ( .A(n719), .B(n762), .Y(n529) );
NOR2X1TS U640 ( .A(n762), .B(n719), .Y(n630) );
NAND2X1TS U641 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .Y(n716) );
BUFX3TS U642 ( .A(n703), .Y(n705) );
INVX2TS U643 ( .A(n703), .Y(n633) );
OAI21X1TS U644 ( .A0(n747), .A1(n764), .B0(n634), .Y(n535) );
OR2X1TS U645 ( .A(n535), .B(n751), .Y(n522) );
INVX2TS U646 ( .A(n636), .Y(enab_RB3) );
NOR4X1TS U647 ( .A(enab_cont_iter), .B(enab_RB3), .C(enab_d_ff_RB1), .D(
beg_add_subt), .Y(n638) );
AOI32X1TS U648 ( .A0(n638), .A1(n637), .A2(n611), .B0(ready_cordic), .B1(
ack_cordic), .Y(n639) );
INVX2TS U649 ( .A(n753), .Y(n754) );
NAND2X1TS U650 ( .A(n754), .B(cont_var_out[1]), .Y(n642) );
INVX2TS U651 ( .A(n643), .Y(add_subt_dataB[26]) );
INVX4TS U652 ( .A(n640), .Y(n669) );
AOI222X1TS U653 ( .A0(n669), .A1(d_ff2_X[11]), .B0(n668), .B1(d_ff2_Y[11]),
.C0(n646), .C1(d_ff2_Z[11]), .Y(n644) );
INVX2TS U654 ( .A(n644), .Y(add_subt_dataA[11]) );
AOI222X1TS U655 ( .A0(n669), .A1(d_ff2_X[17]), .B0(n721), .B1(d_ff2_Y[17]),
.C0(n646), .C1(d_ff2_Z[17]), .Y(n645) );
INVX2TS U656 ( .A(n645), .Y(add_subt_dataA[17]) );
INVX2TS U657 ( .A(n647), .Y(add_subt_dataA[23]) );
AOI222X1TS U658 ( .A0(n669), .A1(d_ff2_X[19]), .B0(n668), .B1(d_ff2_Y[19]),
.C0(n646), .C1(d_ff2_Z[19]), .Y(n648) );
INVX2TS U659 ( .A(n648), .Y(add_subt_dataA[19]) );
INVX2TS U660 ( .A(n649), .Y(add_subt_dataA[12]) );
INVX4TS U661 ( .A(n640), .Y(n685) );
AOI222X1TS U662 ( .A0(n685), .A1(d_ff3_sh_y_out[2]), .B0(n743), .B1(
d_ff3_sh_x_out[2]), .C0(n608), .C1(d_ff3_LUT_out[2]), .Y(n650) );
INVX2TS U663 ( .A(n650), .Y(add_subt_dataB[2]) );
INVX2TS U664 ( .A(n651), .Y(add_subt_dataA[26]) );
INVX2TS U665 ( .A(n652), .Y(add_subt_dataA[27]) );
INVX2TS U666 ( .A(n653), .Y(add_subt_dataA[25]) );
AOI222X1TS U667 ( .A0(n669), .A1(d_ff2_X[14]), .B0(n668), .B1(d_ff2_Y[14]),
.C0(n646), .C1(d_ff2_Z[14]), .Y(n654) );
INVX2TS U668 ( .A(n654), .Y(add_subt_dataA[14]) );
AOI222X1TS U669 ( .A0(n685), .A1(d_ff2_X[0]), .B0(n684), .B1(d_ff2_Y[0]),
.C0(n608), .C1(d_ff2_Z[0]), .Y(n655) );
INVX2TS U670 ( .A(n655), .Y(add_subt_dataA[0]) );
AOI222X1TS U671 ( .A0(n669), .A1(d_ff2_X[21]), .B0(n684), .B1(d_ff2_Y[21]),
.C0(n646), .C1(d_ff2_Z[21]), .Y(n656) );
INVX2TS U672 ( .A(n656), .Y(add_subt_dataA[21]) );
AOI222X1TS U673 ( .A0(n685), .A1(d_ff3_sh_y_out[0]), .B0(n739), .B1(
d_ff3_sh_x_out[0]), .C0(n608), .C1(d_ff3_LUT_out[0]), .Y(n657) );
INVX2TS U674 ( .A(n657), .Y(add_subt_dataB[0]) );
AOI222X1TS U675 ( .A0(n685), .A1(d_ff3_sh_y_out[1]), .B0(n743), .B1(
d_ff3_sh_x_out[1]), .C0(n608), .C1(d_ff3_LUT_out[1]), .Y(n658) );
INVX2TS U676 ( .A(n658), .Y(add_subt_dataB[1]) );
INVX2TS U677 ( .A(n659), .Y(add_subt_dataA[15]) );
AOI222X1TS U678 ( .A0(n669), .A1(d_ff2_X[16]), .B0(n668), .B1(d_ff2_Y[16]),
.C0(n646), .C1(d_ff2_Z[16]), .Y(n660) );
INVX2TS U679 ( .A(n660), .Y(add_subt_dataA[16]) );
INVX2TS U680 ( .A(n661), .Y(add_subt_dataA[29]) );
INVX2TS U681 ( .A(n662), .Y(add_subt_dataA[18]) );
AOI222X1TS U682 ( .A0(n685), .A1(d_ff2_X[31]), .B0(n743), .B1(d_ff2_Y[31]),
.C0(n731), .C1(d_ff2_Z[31]), .Y(n663) );
INVX2TS U683 ( .A(n663), .Y(add_subt_dataA[31]) );
AOI222X1TS U684 ( .A0(n669), .A1(d_ff2_X[20]), .B0(n668), .B1(d_ff2_Y[20]),
.C0(n646), .C1(d_ff2_Z[20]), .Y(n664) );
INVX2TS U685 ( .A(n664), .Y(add_subt_dataA[20]) );
AOI222X1TS U686 ( .A0(n685), .A1(d_ff2_X[28]), .B0(n721), .B1(d_ff2_Y[28]),
.C0(n731), .C1(d_ff2_Z[28]), .Y(n665) );
INVX2TS U687 ( .A(n665), .Y(add_subt_dataA[28]) );
AOI222X1TS U688 ( .A0(n669), .A1(d_ff2_X[22]), .B0(n739), .B1(d_ff2_Y[22]),
.C0(n646), .C1(d_ff2_Z[22]), .Y(n666) );
INVX2TS U689 ( .A(n666), .Y(add_subt_dataA[22]) );
INVX2TS U690 ( .A(n667), .Y(add_subt_dataA[24]) );
AOI222X1TS U691 ( .A0(n669), .A1(d_ff2_X[13]), .B0(n668), .B1(d_ff2_Y[13]),
.C0(n646), .C1(d_ff2_Z[13]), .Y(n670) );
INVX2TS U692 ( .A(n670), .Y(add_subt_dataA[13]) );
INVX2TS U693 ( .A(n671), .Y(add_subt_dataA[30]) );
AOI222X1TS U694 ( .A0(n744), .A1(d_ff2_X[10]), .B0(n721), .B1(d_ff2_Y[10]),
.C0(n731), .C1(d_ff2_Z[10]), .Y(n672) );
INVX2TS U695 ( .A(n672), .Y(add_subt_dataA[10]) );
INVX2TS U696 ( .A(n673), .Y(add_subt_dataA[6]) );
INVX2TS U697 ( .A(n674), .Y(add_subt_dataA[3]) );
INVX2TS U698 ( .A(n675), .Y(add_subt_dataA[5]) );
AOI222X1TS U699 ( .A0(n744), .A1(d_ff2_X[2]), .B0(n743), .B1(d_ff2_Y[2]),
.C0(n608), .C1(d_ff2_Z[2]), .Y(n676) );
INVX2TS U700 ( .A(n676), .Y(add_subt_dataA[2]) );
AOI222X1TS U701 ( .A0(n744), .A1(d_ff2_X[8]), .B0(n721), .B1(d_ff2_Y[8]),
.C0(n608), .C1(d_ff2_Z[8]), .Y(n677) );
INVX2TS U702 ( .A(n677), .Y(add_subt_dataA[8]) );
AOI222X1TS U703 ( .A0(n744), .A1(d_ff2_X[4]), .B0(n743), .B1(d_ff2_Y[4]),
.C0(n731), .C1(d_ff2_Z[4]), .Y(n678) );
INVX2TS U704 ( .A(n678), .Y(add_subt_dataA[4]) );
AOI222X1TS U705 ( .A0(n744), .A1(d_ff2_X[9]), .B0(n739), .B1(d_ff2_Y[9]),
.C0(n608), .C1(d_ff2_Z[9]), .Y(n679) );
INVX2TS U706 ( .A(n679), .Y(add_subt_dataA[9]) );
AOI222X1TS U707 ( .A0(n744), .A1(d_ff2_X[1]), .B0(n684), .B1(d_ff2_Y[1]),
.C0(n731), .C1(d_ff2_Z[1]), .Y(n680) );
INVX2TS U708 ( .A(n680), .Y(add_subt_dataA[1]) );
AOI222X1TS U709 ( .A0(n744), .A1(d_ff2_X[7]), .B0(n721), .B1(d_ff2_Y[7]),
.C0(n608), .C1(d_ff2_Z[7]), .Y(n681) );
INVX2TS U710 ( .A(n681), .Y(add_subt_dataA[7]) );
INVX2TS U711 ( .A(n682), .Y(add_subt_dataB[9]) );
INVX2TS U712 ( .A(n683), .Y(add_subt_dataB[6]) );
AOI222X1TS U713 ( .A0(n685), .A1(d_ff3_sh_y_out[4]), .B0(n668), .B1(
d_ff3_sh_x_out[4]), .C0(n746), .C1(d_ff3_LUT_out[4]), .Y(n686) );
INVX2TS U714 ( .A(n686), .Y(add_subt_dataB[4]) );
INVX2TS U715 ( .A(n687), .Y(add_subt_dataB[10]) );
INVX2TS U716 ( .A(n688), .Y(add_subt_dataB[21]) );
INVX2TS U717 ( .A(n689), .Y(add_subt_dataB[24]) );
INVX2TS U718 ( .A(n690), .Y(add_subt_dataB[25]) );
INVX2TS U719 ( .A(n691), .Y(add_subt_dataB[8]) );
INVX2TS U720 ( .A(n692), .Y(add_subt_dataB[12]) );
INVX2TS U721 ( .A(n693), .Y(add_subt_dataB[23]) );
NOR3XLTS U722 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .C(n694), .Y(
enab_d_ff4_Xn) );
AOI32X1TS U724 ( .A0(cont_iter_out[3]), .A1(n695), .A2(n764), .B0(
cont_iter_out[2]), .B1(n695), .Y(data_out_LUT[4]) );
OAI22X1TS U725 ( .A0(cont_iter_out[3]), .A1(n719), .B0(cont_iter_out[2]),
.B1(n720), .Y(data_out_LUT[25]) );
NAND2X1TS U726 ( .A(d_ff1_operation_out), .B(n613), .Y(n698) );
XOR2X1TS U727 ( .A(n615), .B(n696), .Y(n697) );
BUFX3TS U728 ( .A(n710), .Y(n708) );
AOI22X1TS U729 ( .A0(n709), .A1(d_ff_Yn[31]), .B0(d_ff_Xn[31]), .B1(n708),
.Y(n700) );
XNOR2X1TS U730 ( .A(n700), .B(n699), .Y(fmtted_Result_31_) );
INVX4TS U731 ( .A(n703), .Y(n704) );
NOR2BX1TS U732 ( .AN(d_ff_Yn[0]), .B(n704), .Y(first_mux_Y[0]) );
NOR2BX1TS U733 ( .AN(d_ff_Yn[1]), .B(n704), .Y(first_mux_Y[1]) );
INVX4TS U734 ( .A(n703), .Y(n714) );
NOR2BX1TS U735 ( .AN(d_ff_Yn[2]), .B(n714), .Y(first_mux_Y[2]) );
INVX4TS U736 ( .A(n703), .Y(n706) );
NOR2BX1TS U737 ( .AN(d_ff_Yn[3]), .B(n706), .Y(first_mux_Y[3]) );
NOR2BX1TS U738 ( .AN(d_ff_Yn[4]), .B(n714), .Y(first_mux_Y[4]) );
NOR2BX1TS U739 ( .AN(d_ff_Yn[5]), .B(n706), .Y(first_mux_Y[5]) );
INVX4TS U740 ( .A(n703), .Y(n713) );
NOR2BX1TS U741 ( .AN(d_ff_Yn[6]), .B(n713), .Y(first_mux_Y[6]) );
NOR2BX1TS U742 ( .AN(d_ff_Yn[7]), .B(n713), .Y(first_mux_Y[7]) );
NOR2BX1TS U743 ( .AN(d_ff_Yn[8]), .B(n713), .Y(first_mux_Y[8]) );
INVX4TS U744 ( .A(n703), .Y(n701) );
NOR2BX1TS U745 ( .AN(d_ff_Yn[9]), .B(n701), .Y(first_mux_Y[9]) );
NOR2BX1TS U746 ( .AN(d_ff_Yn[10]), .B(n701), .Y(first_mux_Y[10]) );
NOR2BX1TS U747 ( .AN(d_ff_Yn[11]), .B(n701), .Y(first_mux_Y[11]) );
NOR2BX1TS U748 ( .AN(d_ff_Yn[12]), .B(n701), .Y(first_mux_Y[12]) );
NOR2BX1TS U749 ( .AN(d_ff_Yn[13]), .B(n701), .Y(first_mux_Y[13]) );
NOR2BX1TS U750 ( .AN(d_ff_Yn[14]), .B(n701), .Y(first_mux_Y[14]) );
NOR2BX1TS U751 ( .AN(d_ff_Yn[15]), .B(n701), .Y(first_mux_Y[15]) );
NOR2BX1TS U752 ( .AN(d_ff_Yn[16]), .B(n701), .Y(first_mux_Y[16]) );
NOR2BX1TS U753 ( .AN(d_ff_Yn[17]), .B(n701), .Y(first_mux_Y[17]) );
NOR2BX1TS U754 ( .AN(d_ff_Yn[18]), .B(n701), .Y(first_mux_Y[18]) );
NOR2BX1TS U755 ( .AN(d_ff_Yn[19]), .B(n701), .Y(first_mux_Y[19]) );
NOR2BX1TS U756 ( .AN(d_ff_Yn[20]), .B(n701), .Y(first_mux_Y[20]) );
NOR2BX1TS U757 ( .AN(d_ff_Yn[21]), .B(n701), .Y(first_mux_Y[21]) );
NOR2BX1TS U758 ( .AN(d_ff_Yn[22]), .B(n701), .Y(first_mux_Y[22]) );
NOR2BX1TS U759 ( .AN(d_ff_Yn[23]), .B(n701), .Y(first_mux_Y[23]) );
NOR2BX1TS U760 ( .AN(d_ff_Yn[24]), .B(n713), .Y(first_mux_Y[24]) );
NOR2BX1TS U761 ( .AN(d_ff_Yn[25]), .B(n713), .Y(first_mux_Y[25]) );
NOR2BX1TS U762 ( .AN(d_ff_Yn[26]), .B(n713), .Y(first_mux_Y[26]) );
NOR2BX1TS U763 ( .AN(d_ff_Yn[27]), .B(n713), .Y(first_mux_Y[27]) );
NOR2BX1TS U764 ( .AN(d_ff_Yn[28]), .B(n713), .Y(first_mux_Y[28]) );
NOR2BX1TS U765 ( .AN(d_ff_Yn[29]), .B(n713), .Y(first_mux_Y[29]) );
NOR2BX1TS U766 ( .AN(d_ff_Yn[30]), .B(n713), .Y(first_mux_Y[30]) );
NOR2BX1TS U767 ( .AN(d_ff_Yn[31]), .B(n713), .Y(first_mux_Y[31]) );
BUFX3TS U768 ( .A(n703), .Y(n707) );
BUFX3TS U769 ( .A(n708), .Y(n711) );
INVX2TS U770 ( .A(n708), .Y(n712) );
NOR2BX1TS U771 ( .AN(d_ff_Xn[0]), .B(n714), .Y(first_mux_X[0]) );
NOR2BX1TS U772 ( .AN(d_ff_Xn[4]), .B(n714), .Y(first_mux_X[4]) );
NOR2BX1TS U773 ( .AN(d_ff_Xn[8]), .B(n714), .Y(first_mux_X[8]) );
NOR2BX1TS U774 ( .AN(d_ff_Xn[9]), .B(n714), .Y(first_mux_X[9]) );
NOR2BX1TS U775 ( .AN(d_ff_Xn[11]), .B(n714), .Y(first_mux_X[11]) );
NOR2BX1TS U776 ( .AN(d_ff_Xn[15]), .B(n714), .Y(first_mux_X[15]) );
NOR2BX1TS U777 ( .AN(d_ff_Xn[18]), .B(n714), .Y(first_mux_X[18]) );
NOR2BX1TS U778 ( .AN(d_ff_Xn[21]), .B(n713), .Y(first_mux_X[21]) );
NOR2BX1TS U779 ( .AN(d_ff_Xn[22]), .B(n713), .Y(first_mux_X[22]) );
NOR2BX1TS U780 ( .AN(d_ff_Xn[23]), .B(n713), .Y(first_mux_X[23]) );
NOR2BX1TS U781 ( .AN(d_ff_Xn[30]), .B(n713), .Y(first_mux_X[30]) );
NOR2BX1TS U782 ( .AN(d_ff_Xn[31]), .B(n714), .Y(first_mux_X[31]) );
NOR2BX1TS U783 ( .AN(beg_fsm_cordic), .B(n715), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U784 ( .A0(enab_d_ff4_Zn), .A1(n718), .B0(n717), .B1(n716), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U785 ( .AN(enab_d_ff4_Zn), .B(n718), .Y(
inst_CORDIC_FSM_v3_state_next[6]) );
OA21XLTS U786 ( .A0(cont_iter_out[2]), .A1(n720), .B0(n719), .Y(ITER_CONT_N4) );
XOR2XLTS U787 ( .A(d_ff3_sign_out), .B(cont_var_out[0]), .Y(op_add_subt) );
AO22XLTS U788 ( .A0(n722), .A1(d_ff3_sh_y_out[31]), .B0(n721), .B1(
d_ff3_sh_x_out[31]), .Y(add_subt_dataB[31]) );
AO22XLTS U789 ( .A0(n722), .A1(d_ff3_sh_y_out[30]), .B0(n743), .B1(
d_ff3_sh_x_out[30]), .Y(add_subt_dataB[30]) );
AOI22X1TS U790 ( .A0(n740), .A1(d_ff3_sh_y_out[29]), .B0(n721), .B1(
d_ff3_sh_x_out[29]), .Y(n723) );
NAND2X1TS U791 ( .A(n646), .B(d_ff3_LUT_out[27]), .Y(n725) );
NAND2X1TS U792 ( .A(n723), .B(n725), .Y(add_subt_dataB[29]) );
AOI22X1TS U793 ( .A0(n740), .A1(d_ff3_sh_y_out[28]), .B0(n721), .B1(
d_ff3_sh_x_out[28]), .Y(n724) );
NAND2X1TS U794 ( .A(n724), .B(n725), .Y(add_subt_dataB[28]) );
AOI22X1TS U795 ( .A0(n740), .A1(d_ff3_sh_y_out[27]), .B0(n739), .B1(
d_ff3_sh_x_out[27]), .Y(n726) );
NAND2X1TS U796 ( .A(n726), .B(n725), .Y(add_subt_dataB[27]) );
AOI22X1TS U797 ( .A0(n740), .A1(d_ff3_sh_y_out[22]), .B0(n743), .B1(
d_ff3_sh_x_out[22]), .Y(n727) );
OAI2BB1X1TS U798 ( .A0N(n609), .A1N(d_ff3_LUT_out[19]), .B0(n727), .Y(
add_subt_dataB[22]) );
AOI22X1TS U799 ( .A0(n740), .A1(d_ff3_sh_y_out[20]), .B0(n721), .B1(
d_ff3_sh_x_out[20]), .Y(n728) );
NAND2X1TS U800 ( .A(n646), .B(d_ff3_LUT_out[15]), .Y(n734) );
NAND2X1TS U801 ( .A(n728), .B(n734), .Y(add_subt_dataB[20]) );
AOI22X1TS U802 ( .A0(n740), .A1(d_ff3_sh_y_out[19]), .B0(n721), .B1(
d_ff3_sh_x_out[19]), .Y(n729) );
OAI2BB1X1TS U803 ( .A0N(n746), .A1N(d_ff3_LUT_out[19]), .B0(n729), .Y(
add_subt_dataB[19]) );
AOI22X1TS U804 ( .A0(n740), .A1(d_ff3_sh_y_out[18]), .B0(n743), .B1(
d_ff3_sh_x_out[18]), .Y(n730) );
OAI2BB1X1TS U805 ( .A0N(n731), .A1N(d_ff3_LUT_out[13]), .B0(n730), .Y(
add_subt_dataB[18]) );
AOI22X1TS U806 ( .A0(n740), .A1(d_ff3_sh_y_out[17]), .B0(n684), .B1(
d_ff3_sh_x_out[17]), .Y(n732) );
NAND2X1TS U807 ( .A(n732), .B(n734), .Y(add_subt_dataB[17]) );
AOI22X1TS U808 ( .A0(n740), .A1(d_ff3_sh_y_out[16]), .B0(n743), .B1(
d_ff3_sh_x_out[16]), .Y(n733) );
OAI2BB1X1TS U809 ( .A0N(n746), .A1N(d_ff3_LUT_out[3]), .B0(n733), .Y(
add_subt_dataB[16]) );
AOI22X1TS U810 ( .A0(n740), .A1(d_ff3_sh_y_out[15]), .B0(n739), .B1(
d_ff3_sh_x_out[15]), .Y(n735) );
NAND2X1TS U811 ( .A(n735), .B(n734), .Y(add_subt_dataB[15]) );
AOI22X1TS U812 ( .A0(n740), .A1(d_ff3_sh_y_out[14]), .B0(n721), .B1(
d_ff3_sh_x_out[14]), .Y(n736) );
OAI2BB1X1TS U813 ( .A0N(n609), .A1N(d_ff3_LUT_out[5]), .B0(n736), .Y(
add_subt_dataB[14]) );
AOI22X1TS U814 ( .A0(n744), .A1(d_ff3_sh_y_out[13]), .B0(n684), .B1(
d_ff3_sh_x_out[13]), .Y(n737) );
OAI2BB1X1TS U815 ( .A0N(n609), .A1N(d_ff3_LUT_out[13]), .B0(n737), .Y(
add_subt_dataB[13]) );
AOI22X1TS U816 ( .A0(n740), .A1(d_ff3_sh_y_out[11]), .B0(n743), .B1(
d_ff3_sh_x_out[11]), .Y(n738) );
OAI2BB1X1TS U817 ( .A0N(n746), .A1N(d_ff3_LUT_out[7]), .B0(n738), .Y(
add_subt_dataB[11]) );
AOI22X1TS U818 ( .A0(n740), .A1(d_ff3_sh_y_out[7]), .B0(n721), .B1(
d_ff3_sh_x_out[7]), .Y(n741) );
OAI2BB1X1TS U819 ( .A0N(n731), .A1N(d_ff3_LUT_out[7]), .B0(n741), .Y(
add_subt_dataB[7]) );
AOI22X1TS U820 ( .A0(n744), .A1(d_ff3_sh_y_out[5]), .B0(n721), .B1(
d_ff3_sh_x_out[5]), .Y(n742) );
OAI2BB1X1TS U821 ( .A0N(n746), .A1N(d_ff3_LUT_out[5]), .B0(n742), .Y(
add_subt_dataB[5]) );
AOI22X1TS U822 ( .A0(n744), .A1(d_ff3_sh_y_out[3]), .B0(n743), .B1(
d_ff3_sh_x_out[3]), .Y(n745) );
OAI2BB1X1TS U823 ( .A0N(n746), .A1N(d_ff3_LUT_out[3]), .B0(n745), .Y(
add_subt_dataB[3]) );
AOI22X1TS U824 ( .A0(cont_iter_out[1]), .A1(n749), .B0(n747), .B1(n764), .Y(
n533) );
AOI22X1TS U825 ( .A0(cont_iter_out[1]), .A1(n749), .B0(n748), .B1(n764), .Y(
n525) );
OAI2BB1X1TS U826 ( .A0N(cont_iter_out[1]), .A1N(n523), .B0(n750), .Y(n524)
);
AOI22X1TS U827 ( .A0(cont_iter_out[1]), .A1(n752), .B0(n751), .B1(n764), .Y(
n520) );
AOI22X1TS U828 ( .A0(n754), .A1(n765), .B0(cont_var_out[0]), .B1(n753), .Y(
n518) );
NOR2XLTS U830 ( .A(d_ff2_Y[29]), .B(n756), .Y(n755) );
XNOR2X1TS U831 ( .A(d_ff2_Y[29]), .B(n756), .Y(sh_exp_y[6]) );
AO21XLTS U832 ( .A0(intadd_422_n1), .A1(d_ff2_Y[27]), .B0(n757), .Y(
sh_exp_y[4]) );
NOR2XLTS U833 ( .A(d_ff2_X[29]), .B(n759), .Y(n758) );
XNOR2X1TS U834 ( .A(d_ff2_X[29]), .B(n759), .Y(sh_exp_x[6]) );
AO21XLTS U835 ( .A0(intadd_421_n1), .A1(d_ff2_X[27]), .B0(n760), .Y(
sh_exp_x[4]) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__INV_PP_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__inv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:53:07 07/01/2014
// Design Name:
// Module Name: cheat
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cheat(
input clk,
input [7:0] SNES_PA,
input [23:0] SNES_ADDR,
input [7:0] SNES_DATA,
input SNES_wr_strobe,
input SNES_rd_strobe,
input SNES_reset_strobe,
input snescmd_enable,
input nmicmd_enable,
input return_vector_enable,
input branch1_enable,
input branch2_enable,
input branch3_enable,
input pad_latch,
input snes_ajr,
input SNES_cycle_start,
input [2:0] pgm_idx,
input pgm_we,
input [31:0] pgm_in,
output [7:0] data_out,
output cheat_hit,
output snescmd_unlock
);
//`define IRQ_HOOK_ENABLE
wire snescmd_wr_strobe = snescmd_enable & SNES_wr_strobe;
reg cheat_enable = 0;
reg nmi_enable = 0;
reg irq_enable = 0;
reg holdoff_enable = 0; // temp disable hooks after reset
reg buttons_enable = 0;
reg wram_present = 0;
wire branch_wram = cheat_enable & wram_present;
reg auto_nmi_enable = 1;
reg auto_nmi_enable_sync = 0;
`ifdef IRQ_HOOK_ENABLE
reg auto_irq_enable = 0;
reg auto_irq_enable_sync = 0;
`endif
reg hook_enable_sync = 0;
reg [1:0] sync_delay = 2'b10;
reg [4:0] nmi_usage = 5'h00;
`ifdef IRQ_HOOK_ENABLE
reg [4:0] irq_usage = 5'h00;
`endif
reg [20:0] usage_count = 21'h1fffff;
reg [29:0] hook_enable_count = 0;
reg hook_disable = 0;
reg [1:0] vector_unlock_r = 0;
wire vector_unlock = |vector_unlock_r;
reg [1:0] reset_unlock_r = 2'b10;
wire reset_unlock = |reset_unlock_r;
reg [23:0] cheat_addr[5:0];
reg [7:0] cheat_data[5:0];
reg [5:0] cheat_enable_mask;
reg snescmd_unlock_r = 0;
assign snescmd_unlock = snescmd_unlock_r;
reg [7:0] nmicmd = 0;
reg [7:0] return_vector = 8'hea;
reg [7:0] branch1_offset = 8'h00;
reg [7:0] branch2_offset = 8'h00;
reg [7:0] branch3_offset = 8'h04;
reg [15:0] pad_data = 0;
wire [5:0] cheat_match_bits ={(cheat_enable_mask[5] & (SNES_ADDR == cheat_addr[5])),
(cheat_enable_mask[4] & (SNES_ADDR == cheat_addr[4])),
(cheat_enable_mask[3] & (SNES_ADDR == cheat_addr[3])),
(cheat_enable_mask[2] & (SNES_ADDR == cheat_addr[2])),
(cheat_enable_mask[1] & (SNES_ADDR == cheat_addr[1])),
(cheat_enable_mask[0] & (SNES_ADDR == cheat_addr[0]))};
wire cheat_addr_match = |cheat_match_bits;
wire [1:0] nmi_match_bits = {SNES_ADDR == 24'h00FFEA, SNES_ADDR == 24'h00FFEB};
`ifdef IRQ_HOOK_ENABLE
wire [1:0] irq_match_bits = {SNES_ADDR == 24'h00FFEE, SNES_ADDR == 24'h00FFEF};
`endif
wire [1:0] rst_match_bits = {SNES_ADDR == 24'h00FFFC, SNES_ADDR == 24'h00FFFD};
wire nmi_addr_match = |nmi_match_bits;
`ifdef IRQ_HOOK_ENABLE
wire irq_addr_match = |irq_match_bits;
`endif
wire rst_addr_match = |rst_match_bits;
wire hook_enable = ~|hook_enable_count;
assign data_out = cheat_match_bits[0] ? cheat_data[0]
: cheat_match_bits[1] ? cheat_data[1]
: cheat_match_bits[2] ? cheat_data[2]
: cheat_match_bits[3] ? cheat_data[3]
: cheat_match_bits[4] ? cheat_data[4]
: cheat_match_bits[5] ? cheat_data[5]
: nmi_match_bits[1] ? 8'h10
`ifdef IRQ_HOOK_ENABLE
: irq_match_bits[1] ? 8'h10
`endif
: rst_match_bits[1] ? 8'h7D
: nmicmd_enable ? nmicmd
: return_vector_enable ? return_vector
: branch1_enable ? branch1_offset
: branch2_enable ? branch2_offset
: branch3_enable ? branch3_offset
: 8'h2a;
assign cheat_hit = (snescmd_unlock & hook_enable_sync & (nmicmd_enable | return_vector_enable | branch1_enable | branch2_enable | branch3_enable))
| (reset_unlock & rst_addr_match)
| (cheat_enable & cheat_addr_match)
| (hook_enable_sync & (((auto_nmi_enable_sync & nmi_enable) & nmi_addr_match & vector_unlock)
`ifdef IRQ_HOOK_ENABLE
|((auto_irq_enable_sync & irq_enable) & irq_addr_match & vector_unlock)
`endif
));
// irq/nmi detect based on CPU access pattern
// 4 writes (mirrored to B bus) signify that the CPU pushes PB, PC and
// SR to the stack and is going to read the vector address in the next
// two cycles.
// B bus mirror is used (combined with A BUS /WR!) so the write pattern
// cannot be confused with backwards DMA transfers.
reg [7:0] next_pa_addr = 0;
reg [2:0] cpu_push_cnt = 0;
always @(posedge clk) begin
if(SNES_reset_strobe) begin
cpu_push_cnt <= 0;
end else if(SNES_wr_strobe) begin
cpu_push_cnt <= cpu_push_cnt + 1;
if(cpu_push_cnt == 3'b0) begin
next_pa_addr <= SNES_PA - 1;
end else begin
if(SNES_PA == next_pa_addr) begin
next_pa_addr <= next_pa_addr - 1;
end else begin
cpu_push_cnt <= 3'b0;
end
end
end else if(SNES_rd_strobe) begin
cpu_push_cnt <= 3'b0;
end
end
// make patched vectors visible for last cycles of NMI/IRQ handling only
always @(posedge clk) begin
if(SNES_reset_strobe) begin
vector_unlock_r <= 2'b00;
end else if(SNES_rd_strobe) begin
if(hook_enable_sync
& ((auto_nmi_enable_sync & nmi_enable & nmi_match_bits[1])
`ifdef IRQ_HOOK_ENABLE
|(auto_irq_enable_sync & irq_enable & irq_match_bits[1])
`endif
)
& cpu_push_cnt == 4) begin
vector_unlock_r <= 2'b11;
end else if(|vector_unlock_r) begin
vector_unlock_r <= vector_unlock_r - 1;
end
end
end
// make patched reset vector visible for first fetch only
// (including masked read by Ultra16)
always @(posedge clk) begin
if(SNES_reset_strobe) begin
reset_unlock_r <= 2'b11;
end else if(SNES_cycle_start) begin
if(rst_addr_match & |reset_unlock_r) begin
reset_unlock_r <= reset_unlock_r - 1;
end
end
end
reg snescmd_unlock_disable_strobe = 1'b0;
reg [6:0] snescmd_unlock_disable_countdown = 0;
reg snescmd_unlock_disable = 0;
always @(posedge clk) begin
if(SNES_reset_strobe) begin
snescmd_unlock_r <= 0;
snescmd_unlock_disable <= 0;
end else begin
if(SNES_rd_strobe) begin
// *** GAME -> INGAME HOOK ***
if(hook_enable_sync
& ((auto_nmi_enable_sync & nmi_enable & nmi_match_bits[1])
`ifdef IRQ_HOOK_ENABLE
|(auto_irq_enable_sync & irq_enable & irq_match_bits[1])
`endif
)
& cpu_push_cnt == 4) begin
// remember where we came from (IRQ/NMI) for hook exit
return_vector <= SNES_ADDR[7:0];
snescmd_unlock_r <= 1;
end
if(rst_match_bits[1] & |reset_unlock_r) begin
snescmd_unlock_r <= 1;
end
end
// give some time to exit snescmd memory and jump to original vector
// sta @NMI_VECT_DISABLE 1-2 (after effective write)
// jmp ($ffxx) 3 (excluding address fetch)
// *** (INGAME HOOK -> GAME) ***
if(SNES_cycle_start) begin
if(snescmd_unlock_disable) begin
if(|snescmd_unlock_disable_countdown) begin
snescmd_unlock_disable_countdown <= snescmd_unlock_disable_countdown - 1;
end else if(snescmd_unlock_disable_countdown == 0) begin
snescmd_unlock_r <= 0;
snescmd_unlock_disable <= 0;
end
end
end
if(snescmd_unlock_disable_strobe) begin
snescmd_unlock_disable_countdown <= 7'd6;
snescmd_unlock_disable <= 1;
end
end
end
always @(posedge clk) usage_count <= usage_count - 1;
// Try and autoselect NMI or IRQ hook
always @(posedge clk) begin
if(usage_count == 21'b0) begin
nmi_usage <= SNES_cycle_start & nmi_match_bits[1];
`ifdef IRQ_HOOK_ENABLE
irq_usage <= SNES_cycle_start & irq_match_bits[1];
`endif
`ifdef IRQ_HOOK_ENABLE
if(|nmi_usage & |irq_usage) begin
auto_nmi_enable <= 1'b1;
auto_irq_enable <= 1'b0;
end else if(irq_usage == 5'b0) begin
auto_nmi_enable <= 1'b1;
auto_irq_enable <= 1'b0;
end else if(nmi_usage == 5'b0) begin
auto_nmi_enable <= 1'b0;
auto_irq_enable <= 1'b1;
end
`else
auto_nmi_enable <= |nmi_usage;
`endif
end else begin
if(SNES_cycle_start & nmi_match_bits[0]) nmi_usage <= nmi_usage + 1;
`ifdef IRQ_HOOK_ENABLE
if(SNES_cycle_start & irq_match_bits[0]) irq_usage <= irq_usage + 1;
`endif
end
end
// Do not change vectors while they are being read
always @(posedge clk) begin
if(SNES_cycle_start) begin
if(nmi_addr_match
`ifdef IRQ_HOOK_ENABLE
| irq_addr_match
`endif
) sync_delay <= 2'b10;
else begin
if (|sync_delay) sync_delay <= sync_delay - 1;
if (sync_delay == 2'b00) begin
auto_nmi_enable_sync <= auto_nmi_enable;
`ifdef IRQ_HOOK_ENABLE
auto_irq_enable_sync <= auto_irq_enable;
`endif
hook_enable_sync <= hook_enable;
end
end
end
end
// CMD 0x85: disable hooks for 10 seconds
always @(posedge clk) begin
if((snescmd_unlock & snescmd_wr_strobe & ~|SNES_ADDR[8:0] & (SNES_DATA == 8'h85))
| (holdoff_enable & SNES_reset_strobe)) begin
hook_enable_count <= 30'd960000000;
end else if (|hook_enable_count) begin
hook_enable_count <= hook_enable_count - 1;
end
end
always @(posedge clk) begin
if(SNES_reset_strobe) begin
snescmd_unlock_disable_strobe <= 1'b0;
end else begin
snescmd_unlock_disable_strobe <= 1'b0;
if(snescmd_unlock & snescmd_wr_strobe) begin
if(~|SNES_ADDR[8:0]) begin
case(SNES_DATA)
8'h82: cheat_enable <= 1;
8'h83: cheat_enable <= 0;
8'h84: {nmi_enable, irq_enable} <= 2'b00;
endcase
end else if(SNES_ADDR[8:0] == 9'h1fd) begin
snescmd_unlock_disable_strobe <= 1'b1;
end
end else if(pgm_we) begin
if(pgm_idx < 6) begin
cheat_addr[pgm_idx] <= pgm_in[31:8];
cheat_data[pgm_idx] <= pgm_in[7:0];
end else if(pgm_idx == 6) begin // set rom patch enable
cheat_enable_mask <= pgm_in[5:0];
end else if(pgm_idx == 7) begin // set/reset global enable / hooks
// pgm_in[13:8] are reset bit flags
// pgm_in[5:0] are set bit flags
{wram_present, buttons_enable, holdoff_enable, irq_enable, nmi_enable, cheat_enable}
<= ({wram_present, buttons_enable, holdoff_enable, irq_enable, nmi_enable, cheat_enable}
& ~pgm_in[13:8])
| pgm_in[5:0];
end
end
end
end
// map controller input to cmd output
// check button combinations
// L+R+Start+Select : $3030
// L+R+Select+X : $2070
// L+R+Start+A : $10b0
// L+R+Start+B : $9030
// L+R+Start+Y : $5030
// L+R+Start+X : $1070
always @(posedge clk) begin
if(snescmd_wr_strobe) begin
if(SNES_ADDR[8:0] == 9'h1f0) begin
pad_data[7:0] <= SNES_DATA;
end else if(SNES_ADDR[8:0] == 9'h1f1) begin
pad_data[15:8] <= SNES_DATA;
end
end
end
always @* begin
case(pad_data)
16'h3030: nmicmd = 8'h80;
16'h2070: nmicmd = 8'h81;
16'h10b0: nmicmd = 8'h82;
16'h9030: nmicmd = 8'h83;
16'h5030: nmicmd = 8'h84;
16'h1070: nmicmd = 8'h85;
default: nmicmd = 8'h00;
endcase
end
always @* begin
if(buttons_enable) begin
if(snes_ajr) begin
if(nmicmd) begin
branch1_offset = 8'h30; // nmi_echocmd
end else begin
if(branch_wram) begin
branch1_offset = 8'h3a; // nmi_patches
end else begin
branch1_offset = 8'h43; // nmi_exit
end
end
end else begin
if(pad_latch) begin
if(branch_wram) begin
branch1_offset = 8'h3a; // nmi_patches
end else begin
branch1_offset = 8'h43; // nmi_exit
end
end else begin
branch1_offset = 8'h00; // continue with MJR
end
end
end else begin
if(branch_wram) begin
branch1_offset = 8'h3a; // nmi_patches
end else begin
branch1_offset = 8'h43; // nmi_exit
end
end
end
always @* begin
if(nmicmd == 8'h81) begin
branch2_offset = 8'h14; // nmi_stop
end else if(branch_wram) begin
branch2_offset = 8'h00; // nmi_patches
end else begin
branch2_offset = 8'h09; // nmi_exit
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_gt_es (
// drp interface
up_rstn,
up_clk,
up_es_drp_sel,
up_es_drp_wr,
up_es_drp_addr,
up_es_drp_wdata,
up_es_drp_rdata,
up_es_drp_ready,
// axi4 interface
axi_awvalid,
axi_awaddr,
axi_awprot,
axi_awready,
axi_wvalid,
axi_wdata,
axi_wstrb,
axi_wready,
axi_bvalid,
axi_bresp,
axi_bready,
axi_arvalid,
axi_araddr,
axi_arprot,
axi_arready,
axi_rvalid,
axi_rresp,
axi_rdata,
axi_rready,
// processor interface
up_lpm_dfe_n,
up_es_start,
up_es_stop,
up_es_init,
up_es_sdata0,
up_es_sdata1,
up_es_sdata2,
up_es_sdata3,
up_es_sdata4,
up_es_qdata0,
up_es_qdata1,
up_es_qdata2,
up_es_qdata3,
up_es_qdata4,
up_es_prescale,
up_es_hoffset_min,
up_es_hoffset_max,
up_es_hoffset_step,
up_es_voffset_min,
up_es_voffset_max,
up_es_voffset_step,
up_es_voffset_range,
up_es_start_addr,
up_es_dmaerr,
up_es_status);
// parameters
parameter GTH_GTX_N = 0;
// gt address
localparam ES_DRP_CTRL_ADDR = (GTH_GTX_N == 1) ? 12'h03c : 12'h03d; // GTH-7 12'h03d
localparam ES_DRP_SDATA0_ADDR = (GTH_GTX_N == 1) ? 12'h049 : 12'h036; // GTH-7 12'h036
localparam ES_DRP_SDATA1_ADDR = (GTH_GTX_N == 1) ? 12'h04a : 12'h037; // GTH-7 12'h037
localparam ES_DRP_SDATA2_ADDR = (GTH_GTX_N == 1) ? 12'h04b : 12'h038; // GTH-7 12'h038
localparam ES_DRP_SDATA3_ADDR = (GTH_GTX_N == 1) ? 12'h04c : 12'h039; // GTH-7 12'h039
localparam ES_DRP_SDATA4_ADDR = (GTH_GTX_N == 1) ? 12'h04d : 12'h03a; // GTH-7 12'h03a
localparam ES_DRP_QDATA0_ADDR = (GTH_GTX_N == 1) ? 12'h044 : 12'h031; // GTH-7 12'h031
localparam ES_DRP_QDATA1_ADDR = (GTH_GTX_N == 1) ? 12'h045 : 12'h032; // GTH-7 12'h032
localparam ES_DRP_QDATA2_ADDR = (GTH_GTX_N == 1) ? 12'h046 : 12'h033; // GTH-7 12'h033
localparam ES_DRP_QDATA3_ADDR = (GTH_GTX_N == 1) ? 12'h047 : 12'h034; // GTH-7 12'h034
localparam ES_DRP_QDATA4_ADDR = (GTH_GTX_N == 1) ? 12'h048 : 12'h035; // GTH-7 12'h035
localparam ES_DRP_HOFFSET_ADDR = (GTH_GTX_N == 1) ? 12'h04f : 12'h03c; // GTH-7 12'h03c
localparam ES_DRP_VOFFSET_ADDR = (GTH_GTX_N == 1) ? 12'h097 : 12'h03b; // GTH-7 12'h03b
localparam ES_DRP_STATUS_ADDR = (GTH_GTX_N == 1) ? 12'h153 : 12'h151; // GTH-7 12'h153
localparam ES_DRP_SCNT_ADDR = (GTH_GTX_N == 1) ? 12'h152 : 12'h150; // GTH-7 12'h152
localparam ES_DRP_ECNT_ADDR = (GTH_GTX_N == 1) ? 12'h151 : 12'h14f; // GTH-7 12'h151
// state machine
localparam ES_FSM_IDLE = 6'h00;
localparam ES_FSM_STATUS = 6'h01;
localparam ES_FSM_INIT = 6'h02;
localparam ES_FSM_CTRLINIT_READ = 6'h03;
localparam ES_FSM_CTRLINIT_RRDY = 6'h04;
localparam ES_FSM_CTRLINIT_WRITE = 6'h05;
localparam ES_FSM_CTRLINIT_WRDY = 6'h06;
localparam ES_FSM_SDATA0_WRITE = 6'h07;
localparam ES_FSM_SDATA0_WRDY = 6'h08;
localparam ES_FSM_SDATA1_WRITE = 6'h09;
localparam ES_FSM_SDATA1_WRDY = 6'h0a;
localparam ES_FSM_SDATA2_WRITE = 6'h0b;
localparam ES_FSM_SDATA2_WRDY = 6'h0c;
localparam ES_FSM_SDATA3_WRITE = 6'h0d;
localparam ES_FSM_SDATA3_WRDY = 6'h0e;
localparam ES_FSM_SDATA4_WRITE = 6'h0f;
localparam ES_FSM_SDATA4_WRDY = 6'h10;
localparam ES_FSM_QDATA0_WRITE = 6'h11;
localparam ES_FSM_QDATA0_WRDY = 6'h12;
localparam ES_FSM_QDATA1_WRITE = 6'h13;
localparam ES_FSM_QDATA1_WRDY = 6'h14;
localparam ES_FSM_QDATA2_WRITE = 6'h15;
localparam ES_FSM_QDATA2_WRDY = 6'h16;
localparam ES_FSM_QDATA3_WRITE = 6'h17;
localparam ES_FSM_QDATA3_WRDY = 6'h18;
localparam ES_FSM_QDATA4_WRITE = 6'h19;
localparam ES_FSM_QDATA4_WRDY = 6'h1a;
localparam ES_FSM_HOFFSET_READ = 6'h1b;
localparam ES_FSM_HOFFSET_RRDY = 6'h1c;
localparam ES_FSM_HOFFSET_WRITE = 6'h1d;
localparam ES_FSM_HOFFSET_WRDY = 6'h1e;
localparam ES_FSM_VOFFSET_READ = 6'h1f;
localparam ES_FSM_VOFFSET_RRDY = 6'h20;
localparam ES_FSM_VOFFSET_WRITE = 6'h21;
localparam ES_FSM_VOFFSET_WRDY = 6'h22;
localparam ES_FSM_CTRLSTART_READ = 6'h23;
localparam ES_FSM_CTRLSTART_RRDY = 6'h24;
localparam ES_FSM_CTRLSTART_WRITE = 6'h25;
localparam ES_FSM_CTRLSTART_WRDY = 6'h26;
localparam ES_FSM_STATUS_READ = 6'h27;
localparam ES_FSM_STATUS_RRDY = 6'h28;
localparam ES_FSM_CTRLSTOP_READ = 6'h29;
localparam ES_FSM_CTRLSTOP_RRDY = 6'h2a;
localparam ES_FSM_CTRLSTOP_WRITE = 6'h2b;
localparam ES_FSM_CTRLSTOP_WRDY = 6'h2c;
localparam ES_FSM_SCNT_READ = 6'h2d;
localparam ES_FSM_SCNT_RRDY = 6'h2e;
localparam ES_FSM_ECNT_READ = 6'h2f;
localparam ES_FSM_ECNT_RRDY = 6'h30;
localparam ES_FSM_DMA_WRITE = 6'h31;
localparam ES_FSM_DMA_READY = 6'h32;
localparam ES_FSM_UPDATE = 6'h33;
// drp interface
input up_rstn;
input up_clk;
output up_es_drp_sel;
output up_es_drp_wr;
output [11:0] up_es_drp_addr;
output [15:0] up_es_drp_wdata;
input [15:0] up_es_drp_rdata;
input up_es_drp_ready;
// axi4 interface
output axi_awvalid;
output [31:0] axi_awaddr;
output [ 2:0] axi_awprot;
input axi_awready;
output axi_wvalid;
output [31:0] axi_wdata;
output [ 3:0] axi_wstrb;
input axi_wready;
input axi_bvalid;
input [ 1:0] axi_bresp;
output axi_bready;
output axi_arvalid;
output [31:0] axi_araddr;
output [ 2:0] axi_arprot;
input axi_arready;
input axi_rvalid;
input [31:0] axi_rdata;
input [ 1:0] axi_rresp;
output axi_rready;
// processor interface
input up_lpm_dfe_n;
input up_es_start;
input up_es_stop;
input up_es_init;
input [15:0] up_es_sdata0;
input [15:0] up_es_sdata1;
input [15:0] up_es_sdata2;
input [15:0] up_es_sdata3;
input [15:0] up_es_sdata4;
input [15:0] up_es_qdata0;
input [15:0] up_es_qdata1;
input [15:0] up_es_qdata2;
input [15:0] up_es_qdata3;
input [15:0] up_es_qdata4;
input [ 4:0] up_es_prescale;
input [11:0] up_es_hoffset_min;
input [11:0] up_es_hoffset_max;
input [11:0] up_es_hoffset_step;
input [ 7:0] up_es_voffset_min;
input [ 7:0] up_es_voffset_max;
input [ 7:0] up_es_voffset_step;
input [ 1:0] up_es_voffset_range;
input [31:0] up_es_start_addr;
output up_es_dmaerr;
output up_es_status;
// internal registers
reg axi_awvalid = 'd0;
reg [31:0] axi_awaddr = 'd0;
reg axi_wvalid = 'd0;
reg [31:0] axi_wdata = 'd0;
reg up_es_dmaerr = 'd0;
reg up_es_status = 'd0;
reg up_es_ut = 'd0;
reg [31:0] up_es_dma_addr = 'd0;
reg [11:0] up_es_hoffset = 'd0;
reg [ 7:0] up_es_voffset = 'd0;
reg [15:0] up_es_hoffset_rdata = 'd0;
reg [15:0] up_es_voffset_rdata = 'd0;
reg [15:0] up_es_ctrl_rdata = 'd0;
reg [15:0] up_es_scnt_rdata = 'd0;
reg [15:0] up_es_ecnt_rdata = 'd0;
reg [ 5:0] up_es_fsm = 'd0;
reg up_es_drp_sel = 'd0;
reg up_es_drp_wr = 'd0;
reg [11:0] up_es_drp_addr = 'd0;
reg [15:0] up_es_drp_wdata = 'd0;
// internal signals
wire up_es_heos_s;
wire up_es_eos_s;
wire up_es_ut_s;
wire [ 7:0] up_es_voffset_2_s;
wire [ 7:0] up_es_voffset_n_s;
wire [ 7:0] up_es_voffset_s;
// axi write interface
assign axi_awprot = 3'd0;
assign axi_wstrb = 4'hf;
assign axi_bready = 1'd1;
assign axi_arvalid = 1'd0;
assign axi_araddr = 32'd0;
assign axi_arprot = 3'd0;
assign axi_rready = 1'd1;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
axi_awvalid <= 'b0;
axi_awaddr <= 'd0;
axi_wvalid <= 'b0;
axi_wdata <= 'd0;
end else begin
if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
axi_awvalid <= 1'b0;
axi_awaddr <= 32'd0;
end else if (up_es_fsm == ES_FSM_DMA_WRITE) begin
axi_awvalid <= 1'b1;
axi_awaddr <= up_es_dma_addr;
end
if ((axi_wvalid == 1'b1) && (axi_wready == 1'b1)) begin
axi_wvalid <= 1'b0;
axi_wdata <= 32'd0;
end else if (up_es_fsm == ES_FSM_DMA_WRITE) begin
axi_wvalid <= 1'b1;
axi_wdata <= {up_es_scnt_rdata, up_es_ecnt_rdata};
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_dmaerr <= 'd0;
end else begin
if (axi_bvalid == 1'b1) begin
up_es_dmaerr <= axi_bresp[1] | axi_bresp[0];
end
end
end
// prescale, horizontal and vertical offsets
assign up_es_heos_s = (up_es_hoffset == up_es_hoffset_max) ? up_es_ut : 1'b0;
assign up_es_eos_s = (up_es_voffset == up_es_voffset_max) ? up_es_heos_s : 1'b0;
assign up_es_ut_s = up_es_ut & ~up_lpm_dfe_n;
assign up_es_voffset_2_s = ~up_es_voffset + 1'b1;
assign up_es_voffset_n_s = {1'b1, up_es_voffset_2_s[6:0]};
assign up_es_voffset_s = (up_es_voffset[7] == 1'b1) ? up_es_voffset_n_s : up_es_voffset;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_status <= 1'b0;
up_es_ut <= 'd0;
up_es_dma_addr <= 'd0;
up_es_hoffset <= 'd0;
up_es_voffset <= 'd0;
end else begin
if (up_es_fsm == ES_FSM_IDLE) begin
up_es_status <= 1'b0;
end else begin
up_es_status <= 1'b1;
end
if (up_es_fsm == ES_FSM_IDLE) begin
up_es_ut <= up_lpm_dfe_n;
up_es_dma_addr <= up_es_start_addr;
up_es_hoffset <= up_es_hoffset_min;
up_es_voffset <= up_es_voffset_min;
end else if (up_es_fsm == ES_FSM_UPDATE) begin
up_es_ut <= ~up_es_ut | up_lpm_dfe_n;
up_es_dma_addr <= up_es_dma_addr + 3'd4;
if (up_es_heos_s == 1'b1) begin
up_es_hoffset <= up_es_hoffset_min;
end else if (up_es_ut == 1'b1) begin
up_es_hoffset <= up_es_hoffset + up_es_hoffset_step;
end
if (up_es_heos_s == 1'b1) begin
up_es_voffset <= up_es_voffset + up_es_voffset_step;
end
end
end
end
// read-modify-write parameters (gt's are full of mixed up controls)
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_hoffset_rdata <= 'd0;
up_es_voffset_rdata <= 'd0;
up_es_ctrl_rdata <= 'd0;
up_es_scnt_rdata <= 'd0;
up_es_ecnt_rdata <= 'd0;
end else begin
if ((up_es_fsm == ES_FSM_HOFFSET_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_hoffset_rdata <= up_es_drp_rdata;
end
if ((up_es_fsm == ES_FSM_VOFFSET_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_voffset_rdata <= up_es_drp_rdata;
end
if (((up_es_fsm == ES_FSM_CTRLINIT_RRDY) || (up_es_fsm == ES_FSM_CTRLSTART_RRDY) ||
(up_es_fsm == ES_FSM_CTRLSTOP_RRDY)) && (up_es_drp_ready == 1'b1)) begin
up_es_ctrl_rdata <= up_es_drp_rdata;
end
if ((up_es_fsm == ES_FSM_SCNT_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_scnt_rdata <= up_es_drp_rdata;
end
if ((up_es_fsm == ES_FSM_ECNT_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_ecnt_rdata <= up_es_drp_rdata;
end
end
end
// eye scan state machine- write vertical and horizontal offsets
// and read back sample and error counters
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_fsm <= ES_FSM_IDLE;
end else begin
if (up_es_stop == 1'b1) begin
up_es_fsm <= ES_FSM_IDLE;
end else begin
case (up_es_fsm)
ES_FSM_IDLE: begin // idle
if (up_es_start == 1'b1) begin
up_es_fsm <= ES_FSM_STATUS;
end else begin
up_es_fsm <= ES_FSM_IDLE;
end
end
ES_FSM_STATUS: begin // set status
up_es_fsm <= ES_FSM_INIT;
end
ES_FSM_INIT: begin // initialize
if (up_es_init == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLINIT_READ;
end else begin
up_es_fsm <= ES_FSM_HOFFSET_READ;
end
end
ES_FSM_CTRLINIT_READ: begin // control read
up_es_fsm <= ES_FSM_CTRLINIT_RRDY;
end
ES_FSM_CTRLINIT_RRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLINIT_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLINIT_RRDY;
end
end
ES_FSM_CTRLINIT_WRITE: begin // control write
up_es_fsm <= ES_FSM_CTRLINIT_WRDY;
end
ES_FSM_CTRLINIT_WRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA0_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLINIT_WRDY;
end
end
ES_FSM_SDATA0_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA0_WRDY;
end
ES_FSM_SDATA0_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA1_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA0_WRDY;
end
end
ES_FSM_SDATA1_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA1_WRDY;
end
ES_FSM_SDATA1_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA2_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA1_WRDY;
end
end
ES_FSM_SDATA2_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA2_WRDY;
end
ES_FSM_SDATA2_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA3_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA2_WRDY;
end
end
ES_FSM_SDATA3_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA3_WRDY;
end
ES_FSM_SDATA3_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA4_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA3_WRDY;
end
end
ES_FSM_SDATA4_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA4_WRDY;
end
ES_FSM_SDATA4_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA0_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA4_WRDY;
end
end
ES_FSM_QDATA0_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA0_WRDY;
end
ES_FSM_QDATA0_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA1_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA0_WRDY;
end
end
ES_FSM_QDATA1_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA1_WRDY;
end
ES_FSM_QDATA1_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA2_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA1_WRDY;
end
end
ES_FSM_QDATA2_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA2_WRDY;
end
ES_FSM_QDATA2_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA3_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA2_WRDY;
end
end
ES_FSM_QDATA3_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA3_WRDY;
end
ES_FSM_QDATA3_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA4_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA3_WRDY;
end
end
ES_FSM_QDATA4_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA4_WRDY;
end
ES_FSM_QDATA4_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_HOFFSET_READ;
end else begin
up_es_fsm <= ES_FSM_QDATA4_WRDY;
end
end
ES_FSM_HOFFSET_READ: begin // horizontal offset read
up_es_fsm <= ES_FSM_HOFFSET_RRDY;
end
ES_FSM_HOFFSET_RRDY: begin // horizontal offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_HOFFSET_WRITE;
end else begin
up_es_fsm <= ES_FSM_HOFFSET_RRDY;
end
end
ES_FSM_HOFFSET_WRITE: begin // horizontal offset write
up_es_fsm <= ES_FSM_HOFFSET_WRDY;
end
ES_FSM_HOFFSET_WRDY: begin // horizontal offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_VOFFSET_READ;
end else begin
up_es_fsm <= ES_FSM_HOFFSET_WRDY;
end
end
ES_FSM_VOFFSET_READ: begin // vertical offset read
up_es_fsm <= ES_FSM_VOFFSET_RRDY;
end
ES_FSM_VOFFSET_RRDY: begin // vertical offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_VOFFSET_WRITE;
end else begin
up_es_fsm <= ES_FSM_VOFFSET_RRDY;
end
end
ES_FSM_VOFFSET_WRITE: begin // vertical offset write
up_es_fsm <= ES_FSM_VOFFSET_WRDY;
end
ES_FSM_VOFFSET_WRDY: begin // vertical offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLSTART_READ;
end else begin
up_es_fsm <= ES_FSM_VOFFSET_WRDY;
end
end
ES_FSM_CTRLSTART_READ: begin // control read
up_es_fsm <= ES_FSM_CTRLSTART_RRDY;
end
ES_FSM_CTRLSTART_RRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLSTART_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLSTART_RRDY;
end
end
ES_FSM_CTRLSTART_WRITE: begin // control write
up_es_fsm <= ES_FSM_CTRLSTART_WRDY;
end
ES_FSM_CTRLSTART_WRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_STATUS_READ;
end else begin
up_es_fsm <= ES_FSM_CTRLSTART_WRDY;
end
end
ES_FSM_STATUS_READ: begin // status read
up_es_fsm <= ES_FSM_STATUS_RRDY;
end
ES_FSM_STATUS_RRDY: begin // status ready
if (up_es_drp_ready == 1'b0) begin
up_es_fsm <= ES_FSM_STATUS_RRDY;
end else if (up_es_drp_rdata[3:0] == 4'b0101) begin
up_es_fsm <= ES_FSM_CTRLSTOP_READ;
end else begin
up_es_fsm <= ES_FSM_STATUS_READ;
end
end
ES_FSM_CTRLSTOP_READ: begin // control read
up_es_fsm <= ES_FSM_CTRLSTOP_RRDY;
end
ES_FSM_CTRLSTOP_RRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLSTOP_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLSTOP_RRDY;
end
end
ES_FSM_CTRLSTOP_WRITE: begin // control write
up_es_fsm <= ES_FSM_CTRLSTOP_WRDY;
end
ES_FSM_CTRLSTOP_WRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SCNT_READ;
end else begin
up_es_fsm <= ES_FSM_CTRLSTOP_WRDY;
end
end
ES_FSM_SCNT_READ: begin // read sample count
up_es_fsm <= ES_FSM_SCNT_RRDY;
end
ES_FSM_SCNT_RRDY: begin // sample count ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_ECNT_READ;
end else begin
up_es_fsm <= ES_FSM_SCNT_RRDY;
end
end
ES_FSM_ECNT_READ: begin // read error count
up_es_fsm <= ES_FSM_ECNT_RRDY;
end
ES_FSM_ECNT_RRDY: begin // error count ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_DMA_WRITE;
end else begin
up_es_fsm <= ES_FSM_ECNT_RRDY;
end
end
ES_FSM_DMA_WRITE: begin // dma write
up_es_fsm <= ES_FSM_DMA_READY;
end
ES_FSM_DMA_READY: begin // dma ack
if (axi_bvalid == 1'b1) begin
up_es_fsm <= ES_FSM_UPDATE;
end else begin
up_es_fsm <= ES_FSM_DMA_READY;
end
end
ES_FSM_UPDATE: begin // update
if (up_es_eos_s == 1'b1) begin
up_es_fsm <= ES_FSM_IDLE;
end else if (up_es_ut == 1'b1) begin
up_es_fsm <= ES_FSM_HOFFSET_READ;
end else begin
up_es_fsm <= ES_FSM_VOFFSET_READ;
end
end
default: begin
up_es_fsm <= ES_FSM_IDLE;
end
endcase
end
end
end
// drp signals controlled by the fsm
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_drp_sel <= 'd0;
up_es_drp_wr <= 'd0;
up_es_drp_addr <= 'd0;
up_es_drp_wdata <= 'd0;
end else begin
case (up_es_fsm)
ES_FSM_CTRLINIT_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLINIT_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
if (GTH_GTX_N == 1) begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:10], 2'b11, up_es_ctrl_rdata[7:5], up_es_prescale};
end else begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:10], 2'b11, up_es_ctrl_rdata[7:0]};
end
end
ES_FSM_SDATA0_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA0_ADDR;
up_es_drp_wdata <= up_es_sdata0;
end
ES_FSM_SDATA1_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA1_ADDR;
up_es_drp_wdata <= up_es_sdata1;
end
ES_FSM_SDATA2_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA2_ADDR;
up_es_drp_wdata <= up_es_sdata2;
end
ES_FSM_SDATA3_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA3_ADDR;
up_es_drp_wdata <= up_es_sdata3;
end
ES_FSM_SDATA4_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA4_ADDR;
up_es_drp_wdata <= up_es_sdata4;
end
ES_FSM_QDATA0_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA0_ADDR;
up_es_drp_wdata <= up_es_qdata0;
end
ES_FSM_QDATA1_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA1_ADDR;
up_es_drp_wdata <= up_es_qdata1;
end
ES_FSM_QDATA2_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA2_ADDR;
up_es_drp_wdata <= up_es_qdata2;
end
ES_FSM_QDATA3_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA3_ADDR;
up_es_drp_wdata <= up_es_qdata3;
end
ES_FSM_QDATA4_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA4_ADDR;
up_es_drp_wdata <= up_es_qdata4;
end
ES_FSM_HOFFSET_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_HOFFSET_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_HOFFSET_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_HOFFSET_ADDR;
if (GTH_GTX_N == 1) begin
up_es_drp_wdata <= {up_es_hoffset, up_es_hoffset_rdata[3:0]};
end else begin
up_es_drp_wdata <= {up_es_hoffset_rdata[15:12], up_es_hoffset};
end
end
ES_FSM_VOFFSET_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_VOFFSET_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_VOFFSET_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_VOFFSET_ADDR;
if (GTH_GTX_N == 1) begin
up_es_drp_wdata <= {up_es_voffset_rdata[15:11], up_es_voffset_s[7], up_es_ut_s, up_es_voffset_s[6:0], up_es_voffset_range};
end else begin
up_es_drp_wdata <= {up_es_prescale, up_es_voffset_rdata[10:9], up_es_ut_s, up_es_voffset_s};
end
end
ES_FSM_CTRLSTART_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLSTART_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
if (GTH_GTX_N == 1) begin
up_es_drp_wdata <= {6'd1, up_es_ctrl_rdata[9:0]};
end else begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:6], 6'd1};
end
end
ES_FSM_STATUS_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_STATUS_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLSTOP_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLSTOP_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
if (GTH_GTX_N == 1) begin
up_es_drp_wdata <= {6'd0, up_es_ctrl_rdata[9:0]};
end else begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:6], 6'd0};
end
end
ES_FSM_SCNT_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_SCNT_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_ECNT_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_ECNT_ADDR;
up_es_drp_wdata <= 16'h0000;
end
default: begin
up_es_drp_sel <= 1'b0;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= 9'h000;
up_es_drp_wdata <= 16'h0000;
end
endcase
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
module axi_hdmi_tx_vdma (
// hdmi interface
hdmi_fs_toggle,
hdmi_raddr_g,
// vdma interface
vdma_clk,
vdma_rst,
vdma_fs,
vdma_fs_ret,
vdma_valid,
vdma_data,
vdma_ready,
vdma_wr,
vdma_waddr,
vdma_wdata,
vdma_fs_ret_toggle,
vdma_fs_waddr,
vdma_tpm_oos,
vdma_ovf,
vdma_unf);
// parameters
localparam BUF_THRESHOLD_LO = 9'd3;
localparam BUF_THRESHOLD_HI = 9'd509;
localparam RDY_THRESHOLD_LO = 9'd450;
localparam RDY_THRESHOLD_HI = 9'd500;
// hdmi interface
input hdmi_fs_toggle;
input [ 8:0] hdmi_raddr_g;
// vdma interface
input vdma_clk;
input vdma_rst;
output vdma_fs;
input vdma_fs_ret;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
output vdma_wr;
output [ 8:0] vdma_waddr;
output [47:0] vdma_wdata;
output vdma_fs_ret_toggle;
output [ 8:0] vdma_fs_waddr;
output vdma_tpm_oos;
output vdma_ovf;
output vdma_unf;
// internal registers
reg vdma_fs_toggle_m1 = 'd0;
reg vdma_fs_toggle_m2 = 'd0;
reg vdma_fs_toggle_m3 = 'd0;
reg vdma_fs = 'd0;
reg [ 8:0] vdma_fs_waddr = 'd0;
reg vdma_fs_ret_toggle = 'd0;
reg vdma_wr = 'd0;
reg [ 8:0] vdma_waddr = 'd0;
reg [47:0] vdma_wdata = 'd0;
reg [22:0] vdma_tpm_data = 'd0;
reg vdma_tpm_oos = 'd0;
reg [ 8:0] vdma_raddr_g_m1 = 'd0;
reg [ 8:0] vdma_raddr_g_m2 = 'd0;
reg [ 8:0] vdma_raddr = 'd0;
reg [ 8:0] vdma_addr_diff = 'd0;
reg vdma_ready = 'd0;
reg vdma_almost_full = 'd0;
reg vdma_almost_empty = 'd0;
reg vdma_ovf = 'd0;
reg vdma_unf = 'd0;
// internal wires
wire [47:0] vdma_tpm_data_s;
wire vdma_tpm_oos_s;
wire [ 9:0] vdma_addr_diff_s;
wire vdma_ovf_s;
wire vdma_unf_s;
// grey to binary conversion
function [8:0] g2b;
input [8:0] g;
reg [8:0] b;
begin
b[8] = g[8];
b[7] = b[8] ^ g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// get fs from hdmi side, return fs and sof write address back
always @(posedge vdma_clk or posedge vdma_rst) begin
if (vdma_rst == 1'b1) begin
vdma_fs_toggle_m1 <= 'd0;
vdma_fs_toggle_m2 <= 'd0;
vdma_fs_toggle_m3 <= 'd0;
end else begin
vdma_fs_toggle_m1 <= hdmi_fs_toggle;
vdma_fs_toggle_m2 <= vdma_fs_toggle_m1;
vdma_fs_toggle_m3 <= vdma_fs_toggle_m2;
end
end
always @(posedge vdma_clk) begin
vdma_fs <= vdma_fs_toggle_m2 ^ vdma_fs_toggle_m3;
if (vdma_fs_ret == 1'b1) begin
vdma_fs_waddr <= vdma_waddr;
vdma_fs_ret_toggle <= ~vdma_fs_ret_toggle;
end
end
// vdma write
always @(posedge vdma_clk) begin
vdma_wr <= vdma_valid & vdma_ready;
if (vdma_rst == 1'b1) begin
vdma_waddr <= 9'd0;
end else if (vdma_wr == 1'b1) begin
vdma_waddr <= vdma_waddr + 1'b1;
end
vdma_wdata <= {vdma_data[55:32], vdma_data[23:0]};
end
// test error conditions
assign vdma_tpm_data_s = {vdma_tpm_data, 1'b1, vdma_tpm_data, 1'b0};
assign vdma_tpm_oos_s = (vdma_wdata == vdma_tpm_data_s) ? 1'b0 : vdma_wr;
always @(posedge vdma_clk) begin
if ((vdma_rst == 1'b1) || (vdma_fs_ret == 1'b1)) begin
vdma_tpm_data <= 23'd0;
vdma_tpm_oos <= 1'd0;
end else if (vdma_wr == 1'b1) begin
vdma_tpm_data <= vdma_tpm_data + 1'b1;
vdma_tpm_oos <= vdma_tpm_oos_s;
end
end
// overflow or underflow status
assign vdma_addr_diff_s = {1'b1, vdma_waddr} - vdma_raddr;
assign vdma_ovf_s = (vdma_addr_diff < BUF_THRESHOLD_LO) ? vdma_almost_full : 1'b0;
assign vdma_unf_s = (vdma_addr_diff > BUF_THRESHOLD_HI) ? vdma_almost_empty : 1'b0;
always @(posedge vdma_clk or posedge vdma_rst) begin
if (vdma_rst == 1'b1) begin
vdma_raddr_g_m1 <= 9'd0;
vdma_raddr_g_m2 <= 9'd0;
end else begin
vdma_raddr_g_m1 <= hdmi_raddr_g;
vdma_raddr_g_m2 <= vdma_raddr_g_m1;
end
end
always @(posedge vdma_clk) begin
vdma_raddr <= g2b(vdma_raddr_g_m2);
vdma_addr_diff <= vdma_addr_diff_s[8:0];
if (vdma_addr_diff >= RDY_THRESHOLD_HI) begin
vdma_ready <= 1'b0;
end else if (vdma_addr_diff <= RDY_THRESHOLD_LO) begin
vdma_ready <= 1'b1;
end
if (vdma_addr_diff > BUF_THRESHOLD_HI) begin
vdma_almost_full <= 1'b1;
end else begin
vdma_almost_full <= 1'b0;
end
if (vdma_addr_diff < BUF_THRESHOLD_LO) begin
vdma_almost_empty <= 1'b1;
end else begin
vdma_almost_empty <= 1'b0;
end
vdma_ovf <= vdma_ovf_s;
vdma_unf <= vdma_unf_s;
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR3_2_V
`define SKY130_FD_SC_HDLL__XOR3_2_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog wrapper for xor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__xor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR3_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BO_TB_V
`define SKY130_FD_SC_HS__A21BO_TB_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21bo.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A1 = 1'b1;
#140 A2 = 1'b1;
#160 B1_N = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A1 = 1'b0;
#240 A2 = 1'b0;
#260 B1_N = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 B1_N = 1'b1;
#380 A2 = 1'b1;
#400 A1 = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 B1_N = 1'bx;
#480 A2 = 1'bx;
#500 A1 = 1'bx;
end
sky130_fd_sc_hs__a21bo dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BO_TB_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun May 28 18:34:35 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_debounce_0_0 -prefix
// system_debounce_0_0_ system_debounce_0_0_stub.v
// Design : system_debounce_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "debounce,Vivado 2016.4" *)
module system_debounce_0_0(clk, signal_in, signal_out)
/* synthesis syn_black_box black_box_pad_pin="clk,signal_in,signal_out" */;
input clk;
input signal_in;
output signal_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__EINVP_BLACKBOX_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__einvp (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVP_BLACKBOX_V
|
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 32-bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Tue Feb 03 17:24:18 2015"
module ALU_Cell_1bit(
A,
B,
A_from_next_bit,
C_in,
FS,
F,
C_out
);
input wire A;
input wire B;
input wire A_from_next_bit;
input wire C_in;
input wire [4:0] FS;
output wire F;
output wire C_out;
wire [1:0] logic_S;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
assign SYNTHESIZED_WIRE_6 = 0;
assign SYNTHESIZED_WIRE_7 = 1;
Mux_4_to_1 b2v_inst(
.I1(FS[0]),
.I2(FS[1]),
.I3(FS[2]),
.I4(FS[3]),
.S(logic_S),
.OUT(SYNTHESIZED_WIRE_2));
Mux_2_to_1 b2v_inst11(
.S(FS[3]),
.I1(SYNTHESIZED_WIRE_0),
.I2(SYNTHESIZED_WIRE_1),
.OUT(SYNTHESIZED_WIRE_3));
Mux_2_to_1 b2v_inst13(
.S(FS[4]),
.I1(SYNTHESIZED_WIRE_2),
.I2(SYNTHESIZED_WIRE_3),
.OUT(F));
Mux_2_to_1 b2v_inst14(
.S(FS[3]),
.I1(SYNTHESIZED_WIRE_4),
.I2(logic_S[1]),
.OUT(C_out));
Mux_2_to_1 b2v_inst2(
.S(FS[0]),
.I1(logic_S[1]),
.I2(SYNTHESIZED_WIRE_5),
.OUT(SYNTHESIZED_WIRE_9));
assign SYNTHESIZED_WIRE_5 = ~logic_S[1];
Mux_4_to_1 b2v_inst4(
.I1(SYNTHESIZED_WIRE_6),
.I2(SYNTHESIZED_WIRE_7),
.I3(logic_S[0]),
.I4(SYNTHESIZED_WIRE_8),
.S(FS[2:1]),
.OUT(SYNTHESIZED_WIRE_10));
assign SYNTHESIZED_WIRE_8 = ~logic_S[0];
Mux_2_to_1 b2v_inst8(
.S(FS[0]),
.I1(C_in),
.I2(A_from_next_bit),
.OUT(SYNTHESIZED_WIRE_1));
Full_adder b2v_inst9(
.B(SYNTHESIZED_WIRE_9),
.A(SYNTHESIZED_WIRE_10),
.C_in(C_in),
.S(SYNTHESIZED_WIRE_0),
.C_out(SYNTHESIZED_WIRE_4));
assign logic_S[0] = B;
assign logic_S[1] = A;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O22A_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O22A_BEHAVIORAL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B2 or0_out ;
wire B2 or1_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O22A_BEHAVIORAL_V |
//
// user_io.v
//
// user_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <[email protected]>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// parameter STRLEN and the actual length of conf_str have to match
module user_io #(parameter STRLEN=0) (
input [(8*STRLEN)-1:0] conf_str,
input SPI_CLK,
input SPI_SS_IO,
output reg SPI_MISO,
input SPI_MOSI,
output reg [7:0] joystick_0,
output reg [7:0] joystick_1,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output reg [7:0] status,
// connection to sd card emulation
input [31:0] sd_lba,
input sd_rd,
input sd_wr,
output reg sd_ack,
input sd_conf,
input sd_sdhc,
output [7:0] sd_dout, // valid on rising edge of sd_dout_strobe
output reg sd_dout_strobe,
input [7:0] sd_din,
output reg sd_din_strobe,
output reg sd_change,
// ps2 keyboard emulation
input ps2_clk, // 12-16khz provided by core
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
// serial com port
input [7:0] serial_data,
input serial_strobe
);
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [7:0] byte_cnt; // counts bytes
reg [5:0] joystick0;
reg [5:0] joystick1;
reg [7:0] but_sw;
reg [2:0] stick_idx;
assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
assign sd_dout = { sbuf, SPI_MOSI};
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
// filter spi clock. the 8 bit gate delay is ~2.5ns in total
wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */;
wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
// drive MISO only when transmitting core id
always@(negedge spi_sck or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
SPI_MISO <= 1'bZ;
end else begin
// first byte returned is always core type, further bytes are
// command dependent
if(byte_cnt == 0) begin
SPI_MISO <= core_type[~bit_cnt];
end else begin
// reading serial fifo
if(cmd == 8'h1b) begin
// send alternating flag byte and data
if(byte_cnt[0]) SPI_MISO <= serial_out_status[~bit_cnt];
else SPI_MISO <= serial_out_byte[~bit_cnt];
end
// reading config string
else if(cmd == 8'h14) begin
// returning a byte from string
if(byte_cnt < STRLEN + 1)
SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
else
SPI_MISO <= 1'b0;
end
// reading sd card status
else if(cmd == 8'h16) begin
if(byte_cnt == 1)
SPI_MISO <= sd_cmd[~bit_cnt];
else if((byte_cnt >= 2) && (byte_cnt < 6))
SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}];
else
SPI_MISO <= 1'b0;
end
// reading sd card write data
else if(cmd == 8'h18)
SPI_MISO <= sd_din[~bit_cnt];
else
SPI_MISO <= 1'b0;
end
end
end
// ---------------- PS2 ---------------------
// 8 byte fifos to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
// keyboard
reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0];
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_kbd_tx_state;
reg [7:0] ps2_kbd_tx_byte;
reg ps2_kbd_parity;
assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_kbd_r_inc;
always@(posedge ps2_clk) begin
ps2_kbd_r_inc <= 1'b0;
if(ps2_kbd_r_inc)
ps2_kbd_rptr <= ps2_kbd_rptr + 1;
// transmitter is idle?
if(ps2_kbd_tx_state == 0) begin
// data in fifo present?
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
// load tx register from fifo
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
ps2_kbd_r_inc <= 1'b1;
// reset parity
ps2_kbd_parity <= 1'b1;
// start transmitter
ps2_kbd_tx_state <= 4'd1;
// put start bit on data line
ps2_kbd_data <= 1'b0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
if(ps2_kbd_tx_byte[0])
ps2_kbd_parity <= !ps2_kbd_parity;
end
// transmission of parity
if(ps2_kbd_tx_state == 9)
ps2_kbd_data <= ps2_kbd_parity;
// transmission of stop bit
if(ps2_kbd_tx_state == 10)
ps2_kbd_data <= 1'b1; // stop bit is 1
// advance state machine
if(ps2_kbd_tx_state < 11)
ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1;
else
ps2_kbd_tx_state <= 4'd0;
end
end
// mouse
reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0];
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_mouse_tx_state;
reg [7:0] ps2_mouse_tx_byte;
reg ps2_mouse_parity;
assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_mouse_r_inc;
always@(posedge ps2_clk) begin
ps2_mouse_r_inc <= 1'b0;
if(ps2_mouse_r_inc)
ps2_mouse_rptr <= ps2_mouse_rptr + 1;
// transmitter is idle?
if(ps2_mouse_tx_state == 0) begin
// data in fifo present?
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
// load tx register from fifo
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
ps2_mouse_r_inc <= 1'b1;
// reset parity
ps2_mouse_parity <= 1'b1;
// start transmitter
ps2_mouse_tx_state <= 4'd1;
// put start bit on data line
ps2_mouse_data <= 1'b0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
if(ps2_mouse_tx_byte[0])
ps2_mouse_parity <= !ps2_mouse_parity;
end
// transmission of parity
if(ps2_mouse_tx_state == 9)
ps2_mouse_data <= ps2_mouse_parity;
// transmission of stop bit
if(ps2_mouse_tx_state == 10)
ps2_mouse_data <= 1'b1; // stop bit is 1
// advance state machine
if(ps2_mouse_tx_state < 11)
ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1;
else
ps2_mouse_tx_state <= 4'd0;
end
end
// fifo to receive serial data from core to be forwarded to io controller
// 16 byte fifo to store serial bytes
localparam SERIAL_OUT_FIFO_BITS = 6;
reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0];
reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr;
reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr;
wire serial_out_data_available = serial_out_wptr != serial_out_rptr;
wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */;
wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available};
// status[0] is reset signal from io controller and is thus used to flush
// the fifo
always @(posedge serial_strobe or posedge status[0]) begin
if(status[0] == 1) begin
serial_out_wptr <= 0;
end else begin
serial_out_fifo[serial_out_wptr] <= serial_data;
serial_out_wptr <= serial_out_wptr + 1;
end
end
always@(negedge spi_sck or posedge status[0]) begin
if(status[0] == 1) begin
serial_out_rptr <= 0;
end else begin
if((byte_cnt != 0) && (cmd == 8'h1b)) begin
// read last bit -> advance read pointer
if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available)
serial_out_rptr <= serial_out_rptr + 1;
end
end
end
// SPI receiver
always@(posedge spi_sck or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
bit_cnt <= 3'd0;
byte_cnt <= 8'd0;
sd_ack <= 1'b0;
sd_dout_strobe <= 1'b0;
sd_din_strobe <= 1'b0;
sd_change <= 1'b0;
end else begin
sd_dout_strobe <= 1'b0;
sd_din_strobe <= 1'b0;
if(bit_cnt != 7)
sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
bit_cnt <= bit_cnt + 3'd1;
if((bit_cnt == 7)&&(byte_cnt != 8'd255))
byte_cnt <= byte_cnt + 8'd1;
// finished reading command byte
if(bit_cnt == 7) begin
if(byte_cnt == 0) begin
cmd <= { sbuf, SPI_MOSI};
// fetch first byte when sectore FPGA->IO command has been seen
if({ sbuf, SPI_MOSI} == 8'h18)
sd_din_strobe <= 1'b1;
if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18))
sd_ack <= 1'b1;
end else begin
// buttons and switches
if(cmd == 8'h01)
but_sw <= { sbuf, SPI_MOSI };
if(cmd == 8'h02)
joystick_0 <= { sbuf, SPI_MOSI };
if(cmd == 8'h03)
joystick_1 <= { sbuf, SPI_MOSI };
if(cmd == 8'h04) begin
// store incoming ps2 mouse bytes
ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI };
ps2_mouse_wptr <= ps2_mouse_wptr + 1;
end
if(cmd == 8'h05) begin
// store incoming ps2 keyboard bytes
ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI };
ps2_kbd_wptr <= ps2_kbd_wptr + 1;
end
if(cmd == 8'h15)
status <= { sbuf[6:0], SPI_MOSI };
// send sector IO -> FPGA
if(cmd == 8'h17) begin
// flag that download begins
sd_dout_strobe <= 1'b1;
end
// send sector FPGA -> IO
if(cmd == 8'h18)
sd_din_strobe <= 1'b1;
// send SD config IO -> FPGA
if(cmd == 8'h19) begin
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
sd_dout_strobe <= 1'b1;
end
// joystick analog
if(cmd == 8'h1a) begin
// first byte is joystick indes
if(byte_cnt == 1)
stick_idx <= { sbuf[1:0], SPI_MOSI };
else if(byte_cnt == 2) begin
// second byte is x axis
if(stick_idx == 0)
joystick_analog_0[15:8] <= { sbuf, SPI_MOSI };
else if(stick_idx == 1)
joystick_analog_1[15:8] <= { sbuf, SPI_MOSI };
end else if(byte_cnt == 3) begin
// third byte is y axis
if(stick_idx == 0)
joystick_analog_0[7:0] <= { sbuf, SPI_MOSI };
else if(stick_idx == 1)
joystick_analog_1[7:0] <= { sbuf, SPI_MOSI };
end
end
// set sd card status. The fact that this register is being
// set by the arm controller indicates a possible disk change
if(cmd == 8'h1c)
sd_change <= 1'b1;
end
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: LKB
// Engineer: Leonhard Neuhaus
//
// Create Date: 18.02.2016 11:42:49
// Design Name:
// Module Name: red_pitaya_filter_block
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
module red_pitaya_filter_block
#(
parameter STAGES = 1, //max. 4 stages
parameter SHIFTBITS = 4, //shift can be from 0 to 15 bits
parameter SIGNALBITS = 14, //bit width of the signals
parameter MINBW = 10
)
(
input clk_i,
input rstn_i ,
input [32-1:0] set_filter,
input signed [SIGNALBITS-1:0] dat_i,
output signed [SIGNALBITS-1:0] dat_o
);
//-----------------------------
// cascaded set of FILTERSTAGES low- or high-pass filters
wire signed [SIGNALBITS-1:0] filter_in[STAGES-1:0];
wire signed [SIGNALBITS-1:0] filter_out[STAGES-1:0];
assign filter_in[0] = dat_i;
assign dat_o = filter_out[STAGES-1];
genvar j;
generate for (j = 0; j < STAGES-1; j = j+1) begin
assign filter_in[j+1] = filter_out[j];
end endgenerate
generate for (j = 0; j < STAGES; j = j+1)
red_pitaya_lpf_block #(
.SHIFTBITS(SHIFTBITS),
.SIGNALBITS(SIGNALBITS),
.MINBW(MINBW)
)
lpf
(
.clk_i(clk_i),
.rstn_i(rstn_i),
.shift(set_filter[j*8+SHIFTBITS-1:j*8]),
.filter_on(set_filter[j*8+7]),
.highpass(set_filter[j*8+6]),
.signal_i(filter_in[j]),
.signal_o(filter_out[j])
);
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRBP_2_V
`define SKY130_FD_SC_LS__DFRBP_2_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog wrapper for dfrbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfrbp_2 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfrbp_2 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRBP_2_V
|
/*------------------------------------------------------------------------------
Purpose
CP0 coprocessor of MIPS architecture.
------------------------------------------------------------------------------*/
module mips_cop0 (
input clk,
input rst,
input[4:0] rd_addr,
output[31:0] rd_data,
output[31:0] rd_epc,
output rd_int,
output rd_status_exl,
input[4:0] wr_addr,
input wr_en,
input[31:0] wr_data,
input wr_status_exl_reset,
input wr_status_exl_set,
input wr_cause_en,
input wr_cause_bd,
input[5:0] wr_cause_int,
input[3:0] wr_cause_excode,
input wr_badvaddr_en,
input[31:0] wr_badvaddr_data
);
reg[31:0] epc;
reg[31:0] badvaddr;
reg cause_bd;
reg[5:0] cause_ip;
reg[3:0] cause_excode;
reg[5:0] status_im;
reg status_exl;
reg status_ie;
assign rd_epc= epc;
assign rd_status_exl= status_exl;
assign rd_data= rd_addr==5'd14 ? epc :
rd_addr==5'd13 ? {cause_bd,15'd0,
cause_ip,4'd0,
cause_excode,2'd0} :
rd_addr==5'd8 ? badvaddr :
{16'd0,
status_im,
8'd0,
status_exl,
status_ie};
assign rd_int= |(cause_ip & status_im) & status_ie & !status_exl;
always @(posedge clk)
if(rst)
begin
epc<= 32'd0;
cause_bd<= 1'b0;
cause_ip<= 6'd0;
cause_excode<= 4'd0;
status_im<= 6'd0;
status_exl<= 1'b1;
status_ie<= 1'b0;
badvaddr<= 32'd0;
end
else
begin
epc<= wr_en & wr_addr==5'd14 ? wr_data : epc;
cause_bd<= wr_cause_en ? wr_cause_bd : cause_bd;//31
cause_ip<= wr_cause_int;//15:10
cause_excode<= wr_cause_en ? wr_cause_excode :
cause_excode;//6:2
status_im<= wr_en & wr_addr==5'd12 ? wr_data[15:10] : status_im;
status_exl<= wr_status_exl_reset ? 1'b0 :
wr_status_exl_set ? 1'b1 :
wr_en & wr_addr==5'd12 ? wr_data[1] : status_exl;
status_ie<= wr_en & wr_addr==5'd12 ? wr_data[0] : status_ie;
badvaddr<= wr_badvaddr_en ? wr_badvaddr_data : badvaddr;
end
endmodule
|
(** * MoreInd: More on Induction *)
Require Export ProofObjects.
(* ##################################################### *)
(** * Induction Principles *)
(** This is a good point to pause and take a deeper look at induction
principles.
Every time we declare a new [Inductive] datatype, Coq
automatically generates and proves an _induction principle_
for this type.
The induction principle for a type [t] is called [t_ind]. Here is
the one for natural numbers: *)
Check nat_ind.
(* ===> nat_ind :
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** The [induction] tactic is a straightforward wrapper that, at
its core, simply performs [apply t_ind]. To see this more
clearly, let's experiment a little with using [apply nat_ind]
directly, instead of the [induction] tactic, to carry out some
proofs. Here, for example, is an alternate proof of a theorem
that we saw in the [Basics] chapter. *)
Theorem mult_0_r' : forall n:nat,
n * 0 = 0.
Proof.
apply nat_ind.
Case "O". reflexivity.
Case "S". simpl. intros n IHn. rewrite -> IHn.
reflexivity. Qed.
(** This proof is basically the same as the earlier one, but a
few minor differences are worth noting. First, in the induction
step of the proof (the ["S"] case), we have to do a little
bookkeeping manually (the [intros]) that [induction] does
automatically.
Second, we do not introduce [n] into the context before applying
[nat_ind] -- the conclusion of [nat_ind] is a quantified formula,
and [apply] needs this conclusion to exactly match the shape of
the goal state, including the quantifier. The [induction] tactic
works either with a variable in the context or a quantified
variable in the goal.
Third, the [apply] tactic automatically chooses variable names for
us (in the second subgoal, here), whereas [induction] lets us
specify (with the [as...] clause) what names should be used. The
automatic choice is actually a little unfortunate, since it
re-uses the name [n] for a variable that is different from the [n]
in the original theorem. This is why the [Case] annotation is
just [S] -- if we tried to write it out in the more explicit form
that we've been using for most proofs, we'd have to write [n = S
n], which doesn't make a lot of sense! All of these conveniences
make [induction] nicer to use in practice than applying induction
principles like [nat_ind] directly. But it is important to
realize that, modulo this little bit of bookkeeping, applying
[nat_ind] is what we are really doing. *)
(** **** Exercise: 2 stars, optional (plus_one_r') *)
(** Complete this proof as we did [mult_0_r'] above, without using
the [induction] tactic. *)
Theorem plus_one_r' : forall n:nat,
n + 1 = S n.
Proof.
apply nat_ind.
reflexivity.
intros n H.
simpl. rewrite H.
reflexivity.
Qed.
(** [] *)
(** Coq generates induction principles for every datatype defined with
[Inductive], including those that aren't recursive. (Although
we don't need induction to prove properties of non-recursive
datatypes, the idea of an induction principle still makes sense
for them: it gives a way to prove that a property holds for all
values of the type.)
These generated principles follow a similar pattern. If we define a
type [t] with constructors [c1] ... [cn], Coq generates a theorem
with this shape:
t_ind :
forall P : t -> Prop,
... case for c1 ... ->
... case for c2 ... ->
...
... case for cn ... ->
forall n : t, P n
The specific shape of each case depends on the arguments to the
corresponding constructor. Before trying to write down a general
rule, let's look at some more examples. First, an example where
the constructors take no arguments: *)
Inductive yesno : Type :=
| yes : yesno
| no : yesno.
Check yesno_ind.
(* ===> yesno_ind : forall P : yesno -> Prop,
P yes ->
P no ->
forall y : yesno, P y *)
(** **** Exercise: 1 star, optional (rgb) *)
(** Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
Inductive rgb : Type :=
| red : rgb
| green : rgb
| blue : rgb.
Check rgb_ind.
(** [] *)
(** Here's another example, this time with one of the constructors
taking some arguments. *)
Inductive natlist : Type :=
| nnil : natlist
| ncons : nat -> natlist -> natlist.
Check natlist_ind.
(* ===> (modulo a little variable renaming for clarity)
natlist_ind :
forall P : natlist -> Prop,
P nnil ->
(forall (n : nat) (l : natlist), P l -> P (ncons n l)) ->
forall n : natlist, P n *)
(** **** Exercise: 1 star, optional (natlist1) *)
(** Suppose we had written the above definition a little
differently: *)
Inductive natlist1 : Type :=
| nnil1 : natlist1
| nsnoc1 : natlist1 -> nat -> natlist1.
(** Now what will the induction principle look like? *)
Check natlist1_ind.
(** [] *)
(** From these examples, we can extract this general rule:
- The type declaration gives several constructors; each
corresponds to one clause of the induction principle.
- Each constructor [c] takes argument types [a1]...[an].
- Each [ai] can be either [t] (the datatype we are defining) or
some other type [s].
- The corresponding case of the induction principle
says (in English):
- "for all values [x1]...[xn] of types [a1]...[an], if [P]
holds for each of the inductive arguments (each [xi] of
type [t]), then [P] holds for [c x1 ... xn]".
*)
(** **** Exercise: 1 star, optional (byntree_ind) *)
(** Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
Inductive byntree : Type :=
| bempty : byntree
| bleaf : yesno -> byntree
| nbranch : yesno -> byntree -> byntree -> byntree.
(** [] *)
(** **** Exercise: 1 star, optional (ex_set) *)
(** Here is an induction principle for an inductively defined
set.
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
Give an [Inductive] definition of [ExSet]: *)
Inductive ExSet : Type :=
| con1: bool -> ExSet
| con2: nat -> ExSet -> ExSet.
Check ExSet_ind.
(** [] *)
(** What about polymorphic datatypes?
The inductive definition of polymorphic lists
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
is very similar to that of [natlist]. The main difference is
that, here, the whole definition is _parameterized_ on a set [X]:
that is, we are defining a _family_ of inductive types [list X],
one for each [X]. (Note that, wherever [list] appears in the body
of the declaration, it is always applied to the parameter [X].)
The induction principle is likewise parameterized on [X]:
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
Note the wording here (and, accordingly, the form of [list_ind]):
The _whole_ induction principle is parameterized on [X]. That is,
[list_ind] can be thought of as a polymorphic function that, when
applied to a type [X], gives us back an induction principle
specialized to the type [list X]. *)
(** **** Exercise: 1 star, optional (tree) *)
(** Write out the induction principle that Coq will generate for
the following datatype. Compare your answer with what Coq
prints. *)
Inductive tree (X:Type) : Type :=
| leaf : X -> tree X
| node : tree X -> tree X -> tree X.
Check tree_ind.
(** [] *)
(** **** Exercise: 1 star, optional (mytype) *)
(** Find an inductive definition that gives rise to the
following induction principle:
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
*)
(** [] *)
(** **** Exercise: 1 star, optional (foo) *)
(** Find an inductive definition that gives rise to the
following induction principle:
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
*)
(** [] *)
(** **** Exercise: 1 star, optional (foo') *)
(** Consider the following inductive definition: *)
Inductive foo' (X:Type) : Type :=
| C1 : list X -> foo' X -> foo' X
| C2 : foo' X.
(** What induction principle will Coq generate for [foo']? Fill
in the blanks, then check your answer with Coq.)
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
*)
(** [] *)
(* ##################################################### *)
(** ** Induction Hypotheses *)
(** Where does the phrase "induction hypothesis" fit into this story?
The induction principle for numbers
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
is a generic statement that holds for all propositions
[P] (strictly speaking, for all families of propositions [P]
indexed by a number [n]). Each time we use this principle, we
are choosing [P] to be a particular expression of type
[nat->Prop].
We can make the proof more explicit by giving this expression a
name. For example, instead of stating the theorem [mult_0_r] as
"[forall n, n * 0 = 0]," we can write it as "[forall n, P_m0r
n]", where [P_m0r] is defined as... *)
Definition P_m0r (n:nat) : Prop :=
n * 0 = 0.
(** ... or equivalently... *)
Definition P_m0r' : nat->Prop :=
fun n => n * 0 = 0.
(** Now when we do the proof it is easier to see where [P_m0r]
appears. *)
Theorem mult_0_r'' : forall n:nat,
P_m0r n.
Proof.
apply nat_ind.
Case "n = O". reflexivity.
Case "n = S n'".
(* Note the proof state at this point! *)
intros n IHn.
unfold P_m0r in IHn. unfold P_m0r. simpl. apply IHn. Qed.
(** This extra naming step isn't something that we'll do in
normal proofs, but it is useful to do it explicitly for an example
or two, because it allows us to see exactly what the induction
hypothesis is. If we prove [forall n, P_m0r n] by induction on
[n] (using either [induction] or [apply nat_ind]), we see that the
first subgoal requires us to prove [P_m0r 0] ("[P] holds for
zero"), while the second subgoal requires us to prove [forall n',
P_m0r n' -> P_m0r n' (S n')] (that is "[P] holds of [S n'] if it
holds of [n']" or, more elegantly, "[P] is preserved by [S]").
The _induction hypothesis_ is the premise of this latter
implication -- the assumption that [P] holds of [n'], which we are
allowed to use in proving that [P] holds for [S n']. *)
(* ##################################################### *)
(** ** More on the [induction] Tactic *)
(** The [induction] tactic actually does even more low-level
bookkeeping for us than we discussed above.
Recall the informal statement of the induction principle for
natural numbers:
- If [P n] is some proposition involving a natural number n, and
we want to show that P holds for _all_ numbers n, we can
reason like this:
- show that [P O] holds
- show that, if [P n'] holds, then so does [P (S n')]
- conclude that [P n] holds for all n.
So, when we begin a proof with [intros n] and then [induction n],
we are first telling Coq to consider a _particular_ [n] (by
introducing it into the context) and then telling it to prove
something about _all_ numbers (by using induction).
What Coq actually does in this situation, internally, is to
"re-generalize" the variable we perform induction on. For
example, in our original proof that [plus] is associative...
*)
Theorem plus_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
(* ...we first introduce all 3 variables into the context,
which amounts to saying "Consider an arbitrary [n], [m], and
[p]..." *)
intros n m p.
(* ...We now use the [induction] tactic to prove [P n] (that
is, [n + (m + p) = (n + m) + p]) for _all_ [n],
and hence also for the particular [n] that is in the context
at the moment. *)
induction n as [| n'].
Case "n = O". reflexivity.
Case "n = S n'".
(* In the second subgoal generated by [induction] -- the
"inductive step" -- we must prove that [P n'] implies
[P (S n')] for all [n']. The [induction] tactic
automatically introduces [n'] and [P n'] into the context
for us, leaving just [P (S n')] as the goal. *)
simpl. rewrite -> IHn'. reflexivity. Qed.
(** It also works to apply [induction] to a variable that is
quantified in the goal. *)
Theorem plus_comm' : forall n m : nat,
n + m = m + n.
Proof.
induction n as [| n'].
Case "n = O". intros m. rewrite -> plus_0_r. reflexivity.
Case "n = S n'". intros m. simpl. rewrite -> IHn'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** Note that [induction n] leaves [m] still bound in the goal --
i.e., what we are proving inductively is a statement beginning
with [forall m].
If we do [induction] on a variable that is quantified in the goal
_after_ some other quantifiers, the [induction] tactic will
automatically introduce the variables bound by these quantifiers
into the context. *)
Theorem plus_comm'' : forall n m : nat,
n + m = m + n.
Proof.
(* Let's do induction on [m] this time, instead of [n]... *)
induction m as [| m'].
Case "m = O". simpl. rewrite -> plus_0_r. reflexivity.
Case "m = S m'". simpl. rewrite <- IHm'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** **** Exercise: 1 star, optional (plus_explicit_prop) *)
(** Rewrite both [plus_assoc'] and [plus_comm'] and their proofs in
the same style as [mult_0_r''] above -- that is, for each theorem,
give an explicit [Definition] of the proposition being proved by
induction, and state the theorem and proof in terms of this
defined proposition. *)
(* FILL IN HERE *)
(** [] *)
(** ** Generalizing Inductions. *)
(** One potentially confusing feature of the [induction] tactic is
that it happily lets you try to set up an induction over a term
that isn't sufficiently general. The net effect of this will be
do lose information (much as [destruct] can do), and leave
you unable to complete the proof. Here's an example: *)
Lemma one_not_beautiful_FAILED: ~ beautiful 1.
Proof.
intro H.
(* Just doing an [inversion] on [H] won't get us very far in the [b_sum]
case. (Try it!). So we'll need induction. A naive first attempt: *)
induction H.
(* But now, although we get four cases, as we would expect from
the definition of [beautiful], we lose all information about [H] ! *)
Abort.
(** The problem is that [induction] over a Prop only works properly over
completely general instances of the Prop, i.e. one in which all
the arguments are free (unconstrained) variables.
In this respect it behaves more
like [destruct] than like [inversion].
When you're tempted to do use [induction] like this, it is generally
an indication that you need to be proving something more general.
But in some cases, it suffices to pull out any concrete arguments
into separate equations, like this: *)
Lemma one_not_beautiful: forall n, n = 1 -> ~ beautiful n.
Proof.
intros n E H.
induction H as [| | | p q Hp IHp Hq IHq].
Case "b_0".
inversion E.
Case "b_3".
inversion E.
Case "b_5".
inversion E.
Case "b_sum".
(* the rest is a tedious case analysis *)
destruct p as [|p'].
SCase "p = 0".
destruct q as [|q'].
SSCase "q = 0".
inversion E.
SSCase "q = S q'".
apply IHq. apply E.
SCase "p = S p'".
destruct q as [|q'].
SSCase "q = 0".
apply IHp. rewrite plus_0_r in E. apply E.
SSCase "q = S q'".
simpl in E. inversion E. destruct p'. inversion H0. inversion H0.
Qed.
(** There's a handy [remember] tactic that can generate the second
proof state out of the original one. *)
Lemma one_not_beautiful': ~ beautiful 1.
Proof.
intros H.
remember 1 as n eqn:E.
(* now carry on as above *)
induction H.
Admitted.
(* ####################################################### *)
(** * Informal Proofs (Advanced) *)
(** Q: What is the relation between a formal proof of a proposition
[P] and an informal proof of the same proposition [P]?
A: The latter should _teach_ the reader how to produce the
former.
Q: How much detail is needed??
Unfortunately, There is no single right answer; rather, there is a
range of choices.
At one end of the spectrum, we can essentially give the reader the
whole formal proof (i.e., the informal proof amounts to just
transcribing the formal one into words). This gives the reader
the _ability_ to reproduce the formal one for themselves, but it
doesn't _teach_ them anything.
At the other end of the spectrum, we can say "The theorem is true
and you can figure out why for yourself if you think about it hard
enough." This is also not a good teaching strategy, because
usually writing the proof requires some deep insights into the
thing we're proving, and most readers will give up before they
rediscover all the same insights as we did.
In the middle is the golden mean -- a proof that includes all of
the essential insights (saving the reader the hard part of work
that we went through to find the proof in the first place) and
clear high-level suggestions for the more routine parts to save the
reader from spending too much time reconstructing these
parts (e.g., what the IH says and what must be shown in each case
of an inductive proof), but not so much detail that the main ideas
are obscured.
Another key point: if we're comparing a formal proof of a
proposition [P] and an informal proof of [P], the proposition [P]
doesn't change. That is, formal and informal proofs are _talking
about the same world_ and they _must play by the same rules_. *)
(** ** Informal Proofs by Induction *)
(** Since we've spent much of this chapter looking "under the hood" at
formal proofs by induction, now is a good moment to talk a little
about _informal_ proofs by induction.
In the real world of mathematical communication, written proofs
range from extremely longwinded and pedantic to extremely brief
and telegraphic. The ideal is somewhere in between, of course,
but while you are getting used to the style it is better to start
out at the pedantic end. Also, during the learning phase, it is
probably helpful to have a clear standard to compare against.
With this in mind, we offer two templates below -- one for proofs
by induction over _data_ (i.e., where the thing we're doing
induction on lives in [Type]) and one for proofs by induction over
_evidence_ (i.e., where the inductively defined thing lives in
[Prop]). In the rest of this course, please follow one of the two
for _all_ of your inductive proofs. *)
(** *** Induction Over an Inductively Defined Set *)
(** _Template_:
- _Theorem_: <Universally quantified proposition of the form
"For all [n:S], [P(n)]," where [S] is some inductively defined
set.>
_Proof_: By induction on [n].
<one case for each constructor [c] of [S]...>
- Suppose [n = c a1 ... ak], where <...and here we state
the IH for each of the [a]'s that has type [S], if any>.
We must show <...and here we restate [P(c a1 ... ak)]>.
<go on and prove [P(n)] to finish the case...>
- <other cases similarly...> []
_Example_:
- _Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_: By induction on [l].
- Suppose [l = []]. We must show, for all numbers [n],
that, if length [[] = n], then [index (S n) [] =
None].
This follows immediately from the definition of index.
- Suppose [l = x :: l'] for some [x] and [l'], where
[length l' = n'] implies [index (S n') l' = None], for
any number [n']. We must show, for all [n], that, if
[length (x::l') = n] then [index (S n) (x::l') =
None].
Let [n] be a number with [length l = n]. Since
length l = length (x::l') = S (length l'),
it suffices to show that
index (S (length l')) l' = None.
]]
But this follows directly from the induction hypothesis,
picking [n'] to be length [l']. [] *)
(** *** Induction Over an Inductively Defined Proposition *)
(** Since inductively defined proof objects are often called
"derivation trees," this form of proof is also known as _induction
on derivations_.
_Template_:
- _Theorem_: <Proposition of the form "[Q -> P]," where [Q] is
some inductively defined proposition (more generally,
"For all [x] [y] [z], [Q x y z -> P x y z]")>
_Proof_: By induction on a derivation of [Q]. <Or, more
generally, "Suppose we are given [x], [y], and [z]. We
show that [Q x y z] implies [P x y z], by induction on a
derivation of [Q x y z]"...>
<one case for each constructor [c] of [Q]...>
- Suppose the final rule used to show [Q] is [c]. Then
<...and here we state the types of all of the [a]'s
together with any equalities that follow from the
definition of the constructor and the IH for each of
the [a]'s that has type [Q], if there are any>. We must
show <...and here we restate [P]>.
<go on and prove [P] to finish the case...>
- <other cases similarly...> []
_Example_
- _Theorem_: The [<=] relation is transitive -- i.e., for all
numbers [n], [m], and [o], if [n <= m] and [m <= o], then
[n <= o].
_Proof_: By induction on a derivation of [m <= o].
- Suppose the final rule used to show [m <= o] is
[le_n]. Then [m = o] and we must show that [n <= m],
which is immediate by hypothesis.
- Suppose the final rule used to show [m <= o] is
[le_S]. Then [o = S o'] for some [o'] with [m <= o'].
We must show that [n <= S o'].
By induction hypothesis, [n <= o'].
But then, by [le_S], [n <= S o']. [] *)
(* ##################################################### *)
(** * Optional Material *)
(** The remainder of this chapter offers some additional details on
how induction works in Coq, the process of building proof
trees, and the "trusted computing base" that underlies
Coq proofs. It can safely be skimmed on a first reading. (We
recommend skimming rather than skipping over it outright: it
answers some questions that occur to many Coq users at some point,
so it is useful to have a rough idea of what's here.) *)
(* ##################################################### *)
(** ** Induction Principles in [Prop] *)
(** Earlier, we looked in detail at the induction principles that Coq
generates for inductively defined _sets_. The induction
principles for inductively defined _propositions_ like [gorgeous]
are a tiny bit more complicated. As with all induction
principles, we want to use the induction principle on [gorgeous]
to prove things by inductively considering the possible shapes
that something in [gorgeous] can have -- either it is evidence
that [0] is gorgeous, or it is evidence that, for some [n], [3+n]
is gorgeous, or it is evidence that, for some [n], [5+n] is
gorgeous and it includes evidence that [n] itself is. Intuitively
speaking, however, what we want to prove are not statements about
_evidence_ but statements about _numbers_. So we want an
induction principle that lets us prove properties of numbers by
induction on evidence.
For example, from what we've said so far, you might expect the
inductive definition of [gorgeous]...
Inductive gorgeous : nat -> Prop :=
g_0 : gorgeous 0
| g_plus3 : forall n, gorgeous n -> gorgeous (3+m)
| g_plus5 : forall n, gorgeous n -> gorgeous (5+m).
...to give rise to an induction principle that looks like this...
gorgeous_ind_max :
forall P : (forall n : nat, gorgeous n -> Prop),
P O g_0 ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (3+m) (g_plus3 m e) ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (5+m) (g_plus5 m e) ->
forall (n : nat) (e : gorgeous n), P n e
... because:
- Since [gorgeous] is indexed by a number [n] (every [gorgeous]
object [e] is a piece of evidence that some particular number
[n] is gorgeous), the proposition [P] is parameterized by both
[n] and [e] -- that is, the induction principle can be used to
prove assertions involving both a gorgeous number and the
evidence that it is gorgeous.
- Since there are three ways of giving evidence of gorgeousness
([gorgeous] has three constructors), applying the induction
principle generates three subgoals:
- We must prove that [P] holds for [O] and [b_0].
- We must prove that, whenever [n] is a gorgeous
number and [e] is an evidence of its gorgeousness,
if [P] holds of [n] and [e],
then it also holds of [3+m] and [g_plus3 n e].
- We must prove that, whenever [n] is a gorgeous
number and [e] is an evidence of its gorgeousness,
if [P] holds of [n] and [e],
then it also holds of [5+m] and [g_plus5 n e].
- If these subgoals can be proved, then the induction principle
tells us that [P] is true for _all_ gorgeous numbers [n] and
evidence [e] of their gorgeousness.
But this is a little more flexibility than we actually need or
want: it is giving us a way to prove logical assertions where the
assertion involves properties of some piece of _evidence_ of
gorgeousness, while all we really care about is proving
properties of _numbers_ that are gorgeous -- we are interested in
assertions about numbers, not about evidence. It would therefore
be more convenient to have an induction principle for proving
propositions [P] that are parameterized just by [n] and whose
conclusion establishes [P] for all gorgeous numbers [n]:
forall P : nat -> Prop,
... ->
forall n : nat, gorgeous n -> P n
For this reason, Coq actually generates the following simplified
induction principle for [gorgeous]: *)
Check gorgeous_ind.
(* ===> gorgeous_ind
: forall P : nat -> Prop,
P 0 ->
(forall n : nat, gorgeous n -> P n -> P (3 + n)) ->
(forall n : nat, gorgeous n -> P n -> P (5 + n)) ->
forall n : nat, gorgeous n -> P n *)
(** In particular, Coq has dropped the evidence term [e] as a
parameter of the the proposition [P], and consequently has
rewritten the assumption [forall (n : nat) (e: gorgeous n), ...]
to be [forall (n : nat), gorgeous n -> ...]; i.e., we no longer
require explicit evidence of the provability of [gorgeous n]. *)
(** In English, [gorgeous_ind] says:
- Suppose, [P] is a property of natural numbers (that is, [P n] is
a [Prop] for every [n]). To show that [P n] holds whenever [n]
is gorgeous, it suffices to show:
- [P] holds for [0],
- for any [n], if [n] is gorgeous and [P] holds for
[n], then [P] holds for [3+n],
- for any [n], if [n] is gorgeous and [P] holds for
[n], then [P] holds for [5+n]. *)
(** As expected, we can apply [gorgeous_ind] directly instead of using [induction]. *)
Theorem gorgeous__beautiful' : forall n, gorgeous n -> beautiful n.
Proof.
intros.
apply gorgeous_ind.
Case "g_0".
apply b_0.
Case "g_plus3".
intros.
apply b_sum. apply b_3.
apply H1.
Case "g_plus5".
intros.
apply b_sum. apply b_5.
apply H1.
apply H.
Qed.
(** The precise form of an Inductive definition can affect the
induction principle Coq generates.
For example, in [Logic], we have defined [<=] as: *)
(* Inductive le : nat -> nat -> Prop :=
| le_n : forall n, le n n
| le_S : forall n m, (le n m) -> (le n (S m)). *)
(** This definition can be streamlined a little by observing that the
left-hand argument [n] is the same everywhere in the definition,
so we can actually make it a "general parameter" to the whole
definition, rather than an argument to each constructor. *)
Inductive le (n:nat) : nat -> Prop :=
| le_n : le n n
| le_S : forall m, (le n m) -> (le n (S m)).
Notation "m <= n" := (le m n).
(** The second one is better, even though it looks less symmetric.
Why? Because it gives us a simpler induction principle. *)
Check le_ind.
(* ===> forall (n : nat) (P : nat -> Prop),
P n ->
(forall m : nat, n <= m -> P m -> P (S m)) ->
forall n0 : nat, n <= n0 -> P n0 *)
(** By contrast, the induction principle that Coq calculates for the
first definition has a lot of extra quantifiers, which makes it
messier to work with when proving things by induction. Here is
the induction principle for the first [le]: *)
(* le_ind :
forall P : nat -> nat -> Prop,
(forall n : nat, P n n) ->
(forall n m : nat, le n m -> P n m -> P n (S m)) ->
forall n n0 : nat, le n n0 -> P n n0 *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars, optional (foo_ind_principle) *)
(** Suppose we make the following inductive definition:
Inductive foo (X : Set) (Y : Set) : Set :=
| foo1 : X -> foo X Y
| foo2 : Y -> foo X Y
| foo3 : foo X Y -> foo X Y.
Fill in the blanks to complete the induction principle that will be
generated by Coq.
foo_ind
: forall (X Y : Set) (P : foo X Y -> Prop),
(forall x : X, __________________________________) ->
(forall y : Y, __________________________________) ->
(________________________________________________) ->
________________________________________________
*)
(** [] *)
(** **** Exercise: 2 stars, optional (bar_ind_principle) *)
(** Consider the following induction principle:
bar_ind
: forall P : bar -> Prop,
(forall n : nat, P (bar1 n)) ->
(forall b : bar, P b -> P (bar2 b)) ->
(forall (b : bool) (b0 : bar), P b0 -> P (bar3 b b0)) ->
forall b : bar, P b
Write out the corresponding inductive set definition.
Inductive bar : Set :=
| bar1 : ________________________________________
| bar2 : ________________________________________
| bar3 : ________________________________________.
*)
(** [] *)
(** **** Exercise: 2 stars, optional (no_longer_than_ind) *)
(** Given the following inductively defined proposition:
Inductive no_longer_than (X : Set) : (list X) -> nat -> Prop :=
| nlt_nil : forall n, no_longer_than X [] n
| nlt_cons : forall x l n, no_longer_than X l n ->
no_longer_than X (x::l) (S n)
| nlt_succ : forall l n, no_longer_than X l n ->
no_longer_than X l (S n).
write the induction principle generated by Coq.
no_longer_than_ind
: forall (X : Set) (P : list X -> nat -> Prop),
(forall n : nat, ____________________) ->
(forall (x : X) (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
(forall (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
forall (l : list X) (n : nat), no_longer_than X l n ->
____________________
*)
(** [] *)
(* ##################################################### *)
(** ** Induction Principles for other Logical Propositions *)
(** Similarly, in [Logic] we have defined [eq] as: *)
(* Inductive eq (X:Type) : X -> X -> Prop :=
refl_equal : forall x, eq X x x. *)
(** In the Coq standard library, the definition of equality is
slightly different: *)
Inductive eq' (X:Type) (x:X) : X -> Prop :=
refl_equal' : eq' X x x.
(** The advantage of this definition is that the induction
principle that Coq derives for it is precisely the familiar
principle of _Leibniz equality_: what we mean when we say "[x] and
[y] are equal" is that every property on [P] that is true of [x]
is also true of [y]. *)
Check eq'_ind.
(* ===>
forall (X : Type) (x : X) (P : X -> Prop),
P x -> forall y : X, x =' y -> P y
===> (i.e., after a little reorganization)
forall (X : Type) (x : X) forall y : X,
x =' y ->
forall P : X -> Prop, P x -> P y *)
(** The induction principles for conjunction and disjunction are a
good illustration of Coq's way of generating simplified induction
principles for [Inductive]ly defined propositions, which we
discussed above. You try first: *)
(** **** Exercise: 1 star, optional (and_ind_principle) *)
(** See if you can predict the induction principle for conjunction. *)
(* Check and_ind. *)
(** [] *)
(** **** Exercise: 1 star, optional (or_ind_principle) *)
(** See if you can predict the induction principle for disjunction. *)
(* Check or_ind. *)
(** [] *)
Check and_ind.
(** From the inductive definition of the proposition [and P Q]
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
we might expect Coq to generate this induction principle
and_ind_max :
forall (P Q : Prop) (P0 : P /\ Q -> Prop),
(forall (a : P) (b : Q), P0 (conj P Q a b)) ->
forall a : P /\ Q, P0 a
but actually it generates this simpler and more useful one:
and_ind :
forall P Q P0 : Prop,
(P -> Q -> P0) ->
P /\ Q -> P0
In the same way, when given the inductive definition of [or P Q]
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
instead of the "maximal induction principle"
or_ind_max :
forall (P Q : Prop) (P0 : P \/ Q -> Prop),
(forall a : P, P0 (or_introl P Q a)) ->
(forall b : Q, P0 (or_intror P Q b)) ->
forall o : P \/ Q, P0 o
what Coq actually generates is this:
or_ind :
forall P Q P0 : Prop,
(P -> P0) ->
(Q -> P0) ->
P \/ Q -> P0
]]
*)
(** **** Exercise: 1 star, optional (False_ind_principle) *)
(** Can you predict the induction principle for falsehood? *)
(* Check False_ind. *)
(** [] *)
(** Here's the induction principle that Coq generates for existentials: *)
Check ex_ind.
(* ===> forall (X:Type) (P: X->Prop) (Q: Prop),
(forall witness:X, P witness -> Q) ->
ex X P ->
Q *)
(** This induction principle can be understood as follows: If we have
a function [f] that can construct evidence for [Q] given _any_
witness of type [X] together with evidence that this witness has
property [P], then from a proof of [ex X P] we can extract the
witness and evidence that must have been supplied to the
constructor, give these to [f], and thus obtain a proof of [Q]. *)
(* ######################################################### *)
(** ** Explicit Proof Objects for Induction *)
(** Although tactic-based proofs are normally much easier to
work with, the ability to write a proof term directly is sometimes
very handy, particularly when we want Coq to do something slightly
non-standard. *)
(** Recall the induction principle on naturals that Coq generates for
us automatically from the Inductive declation for [nat]. *)
Check nat_ind.
(* ===>
nat_ind : forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** There's nothing magic about this induction lemma: it's just
another Coq lemma that requires a proof. Coq generates the proof
automatically too... *)
Print nat_ind.
Print nat_rect.
(* ===> (after some manual inlining and tidying)
nat_ind =
fun (P : nat -> Prop)
(f : P 0)
(f0 : forall n : nat, P n -> P (S n)) =>
fix F (n : nat) : P n :=
match n with
| 0 => f
| S n0 => f0 n0 (F n0)
end.
*)
(** We can read this as follows:
Suppose we have evidence [f] that [P] holds on 0, and
evidence [f0] that [forall n:nat, P n -> P (S n)].
Then we can prove that [P] holds of an arbitrary nat [n] via
a recursive function [F] (here defined using the expression
form [Fix] rather than by a top-level [Fixpoint]
declaration). [F] pattern matches on [n]:
- If it finds 0, [F] uses [f] to show that [P n] holds.
- If it finds [S n0], [F] applies itself recursively on [n0]
to obtain evidence that [P n0] holds; then it applies [f0]
on that evidence to show that [P (S n)] holds.
[F] is just an ordinary recursive function that happens to
operate on evidence in [Prop] rather than on terms in [Set].
*)
(** We can adapt this approach to proving [nat_ind] to help prove
_non-standard_ induction principles too. Recall our desire to
prove that
[forall n : nat, even n -> ev n].
Attempts to do this by standard induction on [n] fail, because the
induction principle only lets us proceed when we can prove that
[even n -> even (S n)] -- which is of course never provable. What
we did in [Logic] was a bit of a hack:
[Theorem even__ev : forall n : nat,
(even n -> ev n) /\ (even (S n) -> ev (S n))].
We can make a much better proof by defining and proving a
non-standard induction principle that goes "by twos":
*)
Definition nat_ind2 :
forall (P : nat -> Prop),
P 0 ->
P 1 ->
(forall n : nat, P n -> P (S(S n))) ->
forall n : nat , P n :=
fun P => fun P0 => fun P1 => fun PSS =>
fix f (n:nat) := match n with
0 => P0
| 1 => P1
| S (S n') => PSS n' (f n')
end.
(** Once you get the hang of it, it is entirely straightforward to
give an explicit proof term for induction principles like this.
Proving this as a lemma using tactics is much less intuitive (try
it!).
The [induction ... using] tactic variant gives a convenient way to
specify a non-standard induction principle like this. *)
Lemma even__ev' : forall n, even n -> ev n.
Proof.
intros.
induction n as [ | |n'] using nat_ind2.
Case "even 0".
apply ev_0.
Case "even 1".
inversion H.
Case "even (S(S n'))".
apply ev_SS.
apply IHn'. unfold even. unfold even in H. simpl in H. apply H.
Qed.
(* ######################################################### *)
(** ** The Coq Trusted Computing Base *)
(** One issue that arises with any automated proof assistant is "why
trust it?": what if there is a bug in the implementation that
renders all its reasoning suspect?
While it is impossible to allay such concerns completely, the fact
that Coq is based on the Curry-Howard correspondence gives it a
strong foundation. Because propositions are just types and proofs
are just terms, checking that an alleged proof of a proposition is
valid just amounts to _type-checking_ the term. Type checkers are
relatively small and straightforward programs, so the "trusted
computing base" for Coq -- the part of the code that we have to
believe is operating correctly -- is small too.
What must a typechecker do? Its primary job is to make sure that
in each function application the expected and actual argument
types match, that the arms of a [match] expression are constructor
patterns belonging to the inductive type being matched over and
all arms of the [match] return the same type, and so on.
There are a few additional wrinkles:
- Since Coq types can themselves be expressions, the checker must
normalize these (by using the computation rules) before
comparing them.
- The checker must make sure that [match] expressions are
_exhaustive_. That is, there must be an arm for every possible
constructor. To see why, consider the following alleged proof
object:
Definition or_bogus : forall P Q, P \/ Q -> P :=
fun (P Q : Prop) (A : P \/ Q) =>
match A with
| or_introl H => H
end.
All the types here match correctly, but the [match] only
considers one of the possible constructors for [or]. Coq's
exhaustiveness check will reject this definition.
- The checker must make sure that each [fix] expression
terminates. It does this using a syntactic check to make sure
that each recursive call is on a subexpression of the original
argument. To see why this is essential, consider this alleged
proof:
Definition nat_false : forall (n:nat), False :=
fix f (n:nat) : False := f n.
Again, this is perfectly well-typed, but (fortunately) Coq will
reject it. *)
(** Note that the soundness of Coq depends only on the correctness of
this typechecking engine, not on the tactic machinery. If there
is a bug in a tactic implementation (and this certainly does
happen!), that tactic might construct an invalid proof term. But
when you type [Qed], Coq checks the term for validity from
scratch. Only lemmas whose proofs pass the type-checker can be
used in further proof developments. *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
// Computer_System_mm_interconnect_5.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module Computer_System_mm_interconnect_5 (
input wire System_PLL_sys_clk_clk, // System_PLL_sys_clk.clk
input wire Expansion_JP2_reset_reset_bridge_in_reset_reset, // Expansion_JP2_reset_reset_bridge_in_reset.reset
input wire Video_In_Subsystem_sys_reset_reset_bridge_in_reset_reset, // Video_In_Subsystem_sys_reset_reset_bridge_in_reset.reset
input wire [3:0] Video_In_Subsystem_top_io_gpi2_streamin_address, // Video_In_Subsystem_top_io_gpi2_streamin.address
input wire Video_In_Subsystem_top_io_gpi2_streamin_chipselect, // .chipselect
input wire Video_In_Subsystem_top_io_gpi2_streamin_read, // .read
output wire [31:0] Video_In_Subsystem_top_io_gpi2_streamin_readdata, // .readdata
input wire [3:0] Video_In_Subsystem_top_io_gpo2_streamout_address, // Video_In_Subsystem_top_io_gpo2_streamout.address
input wire Video_In_Subsystem_top_io_gpo2_streamout_chipselect, // .chipselect
input wire Video_In_Subsystem_top_io_gpo2_streamout_write, // .write
input wire [31:0] Video_In_Subsystem_top_io_gpo2_streamout_writedata, // .writedata
output wire [1:0] Expansion_JP2_s1_address, // Expansion_JP2_s1.address
output wire Expansion_JP2_s1_write, // .write
input wire [31:0] Expansion_JP2_s1_readdata, // .readdata
output wire [31:0] Expansion_JP2_s1_writedata, // .writedata
output wire Expansion_JP2_s1_chipselect // .chipselect
);
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_waitrequest; // Video_In_Subsystem_top_io_gpi2_streamin_agent:av_waitrequest -> Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_waitrequest
wire [31:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdata; // Video_In_Subsystem_top_io_gpi2_streamin_agent:av_readdata -> Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_readdata
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_debugaccess; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_debugaccess -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_debugaccess
wire [3:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_address; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_address -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_address
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_read; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_read -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_read
wire [3:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_byteenable; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_byteenable -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_byteenable
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdatavalid; // Video_In_Subsystem_top_io_gpi2_streamin_agent:av_readdatavalid -> Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_readdatavalid
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_lock; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_lock -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_lock
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_write; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_write -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_write
wire [31:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_writedata; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_writedata -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_writedata
wire [2:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_burstcount; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_burstcount -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_valid
wire [73:0] rsp_mux_src_data; // rsp_mux:src_data -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_data
wire rsp_mux_src_ready; // Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_endofpacket
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_waitrequest; // Video_In_Subsystem_top_io_gpo2_streamout_agent:av_waitrequest -> Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_waitrequest
wire [31:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdata; // Video_In_Subsystem_top_io_gpo2_streamout_agent:av_readdata -> Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_readdata
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_debugaccess; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_debugaccess -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_debugaccess
wire [3:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_address; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_address -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_address
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_read; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_read -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_read
wire [3:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_byteenable; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_byteenable -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_byteenable
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdatavalid; // Video_In_Subsystem_top_io_gpo2_streamout_agent:av_readdatavalid -> Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_readdatavalid
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_lock; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_lock -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_lock
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_write; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_write -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_write
wire [31:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_writedata; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_writedata -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_writedata
wire [2:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_burstcount; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_burstcount -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_valid
wire [73:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_data
wire rsp_mux_001_src_ready; // Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_ready -> rsp_mux_001:src_ready
wire [1:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_endofpacket
wire [31:0] expansion_jp2_s1_agent_m0_readdata; // Expansion_JP2_s1_translator:uav_readdata -> Expansion_JP2_s1_agent:m0_readdata
wire expansion_jp2_s1_agent_m0_waitrequest; // Expansion_JP2_s1_translator:uav_waitrequest -> Expansion_JP2_s1_agent:m0_waitrequest
wire expansion_jp2_s1_agent_m0_debugaccess; // Expansion_JP2_s1_agent:m0_debugaccess -> Expansion_JP2_s1_translator:uav_debugaccess
wire [3:0] expansion_jp2_s1_agent_m0_address; // Expansion_JP2_s1_agent:m0_address -> Expansion_JP2_s1_translator:uav_address
wire [3:0] expansion_jp2_s1_agent_m0_byteenable; // Expansion_JP2_s1_agent:m0_byteenable -> Expansion_JP2_s1_translator:uav_byteenable
wire expansion_jp2_s1_agent_m0_read; // Expansion_JP2_s1_agent:m0_read -> Expansion_JP2_s1_translator:uav_read
wire expansion_jp2_s1_agent_m0_readdatavalid; // Expansion_JP2_s1_translator:uav_readdatavalid -> Expansion_JP2_s1_agent:m0_readdatavalid
wire expansion_jp2_s1_agent_m0_lock; // Expansion_JP2_s1_agent:m0_lock -> Expansion_JP2_s1_translator:uav_lock
wire [31:0] expansion_jp2_s1_agent_m0_writedata; // Expansion_JP2_s1_agent:m0_writedata -> Expansion_JP2_s1_translator:uav_writedata
wire expansion_jp2_s1_agent_m0_write; // Expansion_JP2_s1_agent:m0_write -> Expansion_JP2_s1_translator:uav_write
wire [2:0] expansion_jp2_s1_agent_m0_burstcount; // Expansion_JP2_s1_agent:m0_burstcount -> Expansion_JP2_s1_translator:uav_burstcount
wire expansion_jp2_s1_agent_rf_source_valid; // Expansion_JP2_s1_agent:rf_source_valid -> Expansion_JP2_s1_agent_rsp_fifo:in_valid
wire [74:0] expansion_jp2_s1_agent_rf_source_data; // Expansion_JP2_s1_agent:rf_source_data -> Expansion_JP2_s1_agent_rsp_fifo:in_data
wire expansion_jp2_s1_agent_rf_source_ready; // Expansion_JP2_s1_agent_rsp_fifo:in_ready -> Expansion_JP2_s1_agent:rf_source_ready
wire expansion_jp2_s1_agent_rf_source_startofpacket; // Expansion_JP2_s1_agent:rf_source_startofpacket -> Expansion_JP2_s1_agent_rsp_fifo:in_startofpacket
wire expansion_jp2_s1_agent_rf_source_endofpacket; // Expansion_JP2_s1_agent:rf_source_endofpacket -> Expansion_JP2_s1_agent_rsp_fifo:in_endofpacket
wire expansion_jp2_s1_agent_rsp_fifo_out_valid; // Expansion_JP2_s1_agent_rsp_fifo:out_valid -> Expansion_JP2_s1_agent:rf_sink_valid
wire [74:0] expansion_jp2_s1_agent_rsp_fifo_out_data; // Expansion_JP2_s1_agent_rsp_fifo:out_data -> Expansion_JP2_s1_agent:rf_sink_data
wire expansion_jp2_s1_agent_rsp_fifo_out_ready; // Expansion_JP2_s1_agent:rf_sink_ready -> Expansion_JP2_s1_agent_rsp_fifo:out_ready
wire expansion_jp2_s1_agent_rsp_fifo_out_startofpacket; // Expansion_JP2_s1_agent_rsp_fifo:out_startofpacket -> Expansion_JP2_s1_agent:rf_sink_startofpacket
wire expansion_jp2_s1_agent_rsp_fifo_out_endofpacket; // Expansion_JP2_s1_agent_rsp_fifo:out_endofpacket -> Expansion_JP2_s1_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> Expansion_JP2_s1_agent:cp_valid
wire [73:0] cmd_mux_src_data; // cmd_mux:src_data -> Expansion_JP2_s1_agent:cp_data
wire cmd_mux_src_ready; // Expansion_JP2_s1_agent:cp_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> Expansion_JP2_s1_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> Expansion_JP2_s1_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> Expansion_JP2_s1_agent:cp_endofpacket
wire video_in_subsystem_top_io_gpi2_streamin_agent_cp_valid; // Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_valid -> router:sink_valid
wire [73:0] video_in_subsystem_top_io_gpi2_streamin_agent_cp_data; // Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_data -> router:sink_data
wire video_in_subsystem_top_io_gpi2_streamin_agent_cp_ready; // router:sink_ready -> Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_ready
wire video_in_subsystem_top_io_gpi2_streamin_agent_cp_startofpacket; // Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_startofpacket -> router:sink_startofpacket
wire video_in_subsystem_top_io_gpi2_streamin_agent_cp_endofpacket; // Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [73:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire video_in_subsystem_top_io_gpo2_streamout_agent_cp_valid; // Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_valid -> router_001:sink_valid
wire [73:0] video_in_subsystem_top_io_gpo2_streamout_agent_cp_data; // Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_data -> router_001:sink_data
wire video_in_subsystem_top_io_gpo2_streamout_agent_cp_ready; // router_001:sink_ready -> Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_ready
wire video_in_subsystem_top_io_gpo2_streamout_agent_cp_startofpacket; // Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_startofpacket -> router_001:sink_startofpacket
wire video_in_subsystem_top_io_gpo2_streamout_agent_cp_endofpacket; // Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [73:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire expansion_jp2_s1_agent_rp_valid; // Expansion_JP2_s1_agent:rp_valid -> router_002:sink_valid
wire [73:0] expansion_jp2_s1_agent_rp_data; // Expansion_JP2_s1_agent:rp_data -> router_002:sink_data
wire expansion_jp2_s1_agent_rp_ready; // router_002:sink_ready -> Expansion_JP2_s1_agent:rp_ready
wire expansion_jp2_s1_agent_rp_startofpacket; // Expansion_JP2_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
wire expansion_jp2_s1_agent_rp_endofpacket; // Expansion_JP2_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [73:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [73:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [73:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [1:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [73:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [73:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [1:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire expansion_jp2_s1_agent_rdata_fifo_src_valid; // Expansion_JP2_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] expansion_jp2_s1_agent_rdata_fifo_src_data; // Expansion_JP2_s1_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire expansion_jp2_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> Expansion_JP2_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> Expansion_JP2_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> Expansion_JP2_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // Expansion_JP2_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> Expansion_JP2_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (1),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_in_subsystem_top_io_gpi2_streamin_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_read), // .read
.uav_write (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Video_In_Subsystem_top_io_gpi2_streamin_address), // avalon_anti_master_0.address
.av_chipselect (Video_In_Subsystem_top_io_gpi2_streamin_chipselect), // .chipselect
.av_read (Video_In_Subsystem_top_io_gpi2_streamin_read), // .read
.av_readdata (Video_In_Subsystem_top_io_gpi2_streamin_readdata), // .readdata
.av_waitrequest (), // (terminated)
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.USE_READ (0),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (1),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_in_subsystem_top_io_gpo2_streamout_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_read), // .read
.uav_write (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Video_In_Subsystem_top_io_gpo2_streamout_address), // avalon_anti_master_0.address
.av_chipselect (Video_In_Subsystem_top_io_gpo2_streamout_chipselect), // .chipselect
.av_write (Video_In_Subsystem_top_io_gpo2_streamout_write), // .write
.av_writedata (Video_In_Subsystem_top_io_gpo2_streamout_writedata), // .writedata
.av_waitrequest (), // (terminated)
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_read (1'b0), // (terminated)
.av_readdata (), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) expansion_jp2_s1_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (expansion_jp2_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (expansion_jp2_s1_agent_m0_burstcount), // .burstcount
.uav_read (expansion_jp2_s1_agent_m0_read), // .read
.uav_write (expansion_jp2_s1_agent_m0_write), // .write
.uav_waitrequest (expansion_jp2_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (expansion_jp2_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (expansion_jp2_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (expansion_jp2_s1_agent_m0_readdata), // .readdata
.uav_writedata (expansion_jp2_s1_agent_m0_writedata), // .writedata
.uav_lock (expansion_jp2_s1_agent_m0_lock), // .lock
.uav_debugaccess (expansion_jp2_s1_agent_m0_debugaccess), // .debugaccess
.av_address (Expansion_JP2_s1_address), // avalon_anti_slave_0.address
.av_write (Expansion_JP2_s1_write), // .write
.av_readdata (Expansion_JP2_s1_readdata), // .readdata
.av_writedata (Expansion_JP2_s1_writedata), // .writedata
.av_chipselect (Expansion_JP2_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_QOS_H (58),
.PKT_QOS_L (58),
.PKT_DATA_SIDEBAND_H (56),
.PKT_DATA_SIDEBAND_L (56),
.PKT_ADDR_SIDEBAND_H (55),
.PKT_ADDR_SIDEBAND_L (55),
.PKT_BURST_TYPE_H (54),
.PKT_BURST_TYPE_L (53),
.PKT_CACHE_H (68),
.PKT_CACHE_L (65),
.PKT_THREAD_ID_H (61),
.PKT_THREAD_ID_L (61),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_EXCLUSIVE (45),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.ST_DATA_W (74),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) video_in_subsystem_top_io_gpi2_streamin_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_address), // av.address
.av_write (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_write), // .write
.av_read (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_in_subsystem_top_io_gpi2_streamin_agent_cp_valid), // cp.valid
.cp_data (video_in_subsystem_top_io_gpi2_streamin_agent_cp_data), // .data
.cp_startofpacket (video_in_subsystem_top_io_gpi2_streamin_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_in_subsystem_top_io_gpi2_streamin_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_in_subsystem_top_io_gpi2_streamin_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_QOS_H (58),
.PKT_QOS_L (58),
.PKT_DATA_SIDEBAND_H (56),
.PKT_DATA_SIDEBAND_L (56),
.PKT_ADDR_SIDEBAND_H (55),
.PKT_ADDR_SIDEBAND_L (55),
.PKT_BURST_TYPE_H (54),
.PKT_BURST_TYPE_L (53),
.PKT_CACHE_H (68),
.PKT_CACHE_L (65),
.PKT_THREAD_ID_H (61),
.PKT_THREAD_ID_L (61),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_EXCLUSIVE (45),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.ST_DATA_W (74),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) video_in_subsystem_top_io_gpo2_streamout_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_address), // av.address
.av_write (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_write), // .write
.av_read (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_in_subsystem_top_io_gpo2_streamout_agent_cp_valid), // cp.valid
.cp_data (video_in_subsystem_top_io_gpo2_streamout_agent_cp_data), // .data
.cp_startofpacket (video_in_subsystem_top_io_gpo2_streamout_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_in_subsystem_top_io_gpo2_streamout_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_in_subsystem_top_io_gpo2_streamout_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (2),
.ST_DATA_W (74),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) expansion_jp2_s1_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (expansion_jp2_s1_agent_m0_address), // m0.address
.m0_burstcount (expansion_jp2_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (expansion_jp2_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (expansion_jp2_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (expansion_jp2_s1_agent_m0_lock), // .lock
.m0_readdata (expansion_jp2_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (expansion_jp2_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (expansion_jp2_s1_agent_m0_read), // .read
.m0_waitrequest (expansion_jp2_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (expansion_jp2_s1_agent_m0_writedata), // .writedata
.m0_write (expansion_jp2_s1_agent_m0_write), // .write
.rp_endofpacket (expansion_jp2_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (expansion_jp2_s1_agent_rp_ready), // .ready
.rp_valid (expansion_jp2_s1_agent_rp_valid), // .valid
.rp_data (expansion_jp2_s1_agent_rp_data), // .data
.rp_startofpacket (expansion_jp2_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (expansion_jp2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (expansion_jp2_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (expansion_jp2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (expansion_jp2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (expansion_jp2_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (expansion_jp2_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (expansion_jp2_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (expansion_jp2_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (expansion_jp2_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (expansion_jp2_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (expansion_jp2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (expansion_jp2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (expansion_jp2_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (75),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) expansion_jp2_s1_agent_rsp_fifo (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (expansion_jp2_s1_agent_rf_source_data), // in.data
.in_valid (expansion_jp2_s1_agent_rf_source_valid), // .valid
.in_ready (expansion_jp2_s1_agent_rf_source_ready), // .ready
.in_startofpacket (expansion_jp2_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (expansion_jp2_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (expansion_jp2_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (expansion_jp2_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (expansion_jp2_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (expansion_jp2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (expansion_jp2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
Computer_System_mm_interconnect_4_router router (
.sink_ready (video_in_subsystem_top_io_gpi2_streamin_agent_cp_ready), // sink.ready
.sink_valid (video_in_subsystem_top_io_gpi2_streamin_agent_cp_valid), // .valid
.sink_data (video_in_subsystem_top_io_gpi2_streamin_agent_cp_data), // .data
.sink_startofpacket (video_in_subsystem_top_io_gpi2_streamin_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_in_subsystem_top_io_gpi2_streamin_agent_cp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_router router_001 (
.sink_ready (video_in_subsystem_top_io_gpo2_streamout_agent_cp_ready), // sink.ready
.sink_valid (video_in_subsystem_top_io_gpo2_streamout_agent_cp_valid), // .valid
.sink_data (video_in_subsystem_top_io_gpo2_streamout_agent_cp_data), // .data
.sink_startofpacket (video_in_subsystem_top_io_gpo2_streamout_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_in_subsystem_top_io_gpo2_streamout_agent_cp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_router_002 router_002 (
.sink_ready (expansion_jp2_s1_agent_rp_ready), // sink.ready
.sink_valid (expansion_jp2_s1_agent_rp_valid), // .valid
.sink_data (expansion_jp2_s1_agent_rp_data), // .data
.sink_startofpacket (expansion_jp2_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (expansion_jp2_s1_agent_rp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_demux cmd_demux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_demux cmd_demux_001 (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_mux cmd_mux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_demux rsp_demux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_mux rsp_mux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_mux rsp_mux_001 (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (System_PLL_sys_clk_clk), // in_clk_0.clk
.in_rst_0_reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (expansion_jp2_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (expansion_jp2_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (expansion_jp2_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0N_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__INPUTISO0N_BEHAVIORAL_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__inputiso0n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
and and0 (X , A, SLEEP_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0N_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V |
module Tx8b10b #(
parameter FILL_WORD_RD0 = 10'b0011111010, // Send when no data present & RD=-1
parameter FILL_WORD_RD1 = 10'b1100000101, // Send when no data present & RD=1
parameter FILL_WORD_FLIP = 1'b1, // Flip status of Running Disparity when using fill word
parameter LOG2_DEPTH = 4 // log2(depth of FIFO buffer). Must be an integer.
)
(
input clk, // System clock
input rst, // Reset, synchronous and active high
input en, // Enable strobe for transmitting
input [7:0] dataIn, // Data to transmit
input writeStrobe, // Write data to transmit FIFO
output dataPresent, // FIFO has data still in it
output halfFull, // FIFO halfway full
output full, // FIFO is completely full. Don't write to it.
output tx // Transmit bit
);
wire [7:0] dataToEncode;
reg [3:0] outCounter;
reg [1:9] shiftOut;
reg readStrobe;
reg runDisparity6b; // 1=RD is +1, 0=RD is -1
reg runDisparity4b; // 1=RD is +1, 0=RD is -1
reg useAlt;
reg dataPresentLatch;
reg busy; // Only used when no FIFO is present
if (LOG2_DEPTH > 0) begin
Fifo #(
.WIDTH(8), ///< Width of data word
.LOG2_DEPTH(LOG2_DEPTH) ///< log2(depth of FIFO). Must be an integer
)
txFifo
(
// Inputs
.clk(clk), ///< System clock
.rst(rst), ///< Reset FIFO pointer
.write(writeStrobe), ///< Write strobe (1 clk)
.read(readStrobe), ///< Read strobe (1 clk)
.dataIn(dataIn), ///< [WIDTH-1:0] Data to write
// Outputs
.dataOut(dataToEncode), ///< [WIDTH-1:0] Data from FIFO
.dataPresent(dataPresent), ///< Data is present in FIFO
.halfFull(halfFull), ///< FIFO is half full
.full(full) ///< FIFO is full
);
end
else begin
assign dataToEncode = dataIn;
always @(posedge clk) begin
if (rst) begin
busy <= 1'b0;
end
else begin
busy <= busy ? (~readStrobe & busy) : writeStrobe;
end
end
end
assign tx = shiftOut[1];
initial begin
busy = 1'b0;
runDisparity6b = 1'b0;
runDisparity4b = 1'b0;
outCounter = 'd0;
shiftOut = 'd0;
useAlt = 1'b0;
dataPresentLatch = 1'b0;
end
always @(posedge clk) begin
if (rst) begin
runDisparity6b <= 1'b0;
runDisparity4b <= 1'b0;
outCounter <= 'd0;
shiftOut <= 'd0;
useAlt <= 1'b0;
dataPresentLatch <= 1'b0;
end
else if (en) begin
if (outCounter == 'd0) begin
readStrobe <= 1'b0;
outCounter <= 'd9;
shiftOut[7:9] <= {shiftOut[8:9], 1'b0};
// 5b/6b Encoder
useAlt <= 1'b0;
dataPresentLatch <= dataPresent;
if (dataPresent) begin
case ({dataToEncode[4:0], runDisparity6b})
6'b000000 : begin shiftOut[1:6] <= 6'b100111; runDisparity4b <= 1'b1; end
6'b000001 : begin shiftOut[1:6] <= 6'b011000; runDisparity4b <= 1'b0; end
6'b000010 : begin shiftOut[1:6] <= 6'b011101; runDisparity4b <= 1'b1; end
6'b000011 : begin shiftOut[1:6] <= 6'b100010; runDisparity4b <= 1'b0; end
6'b000100 : begin shiftOut[1:6] <= 6'b101101; runDisparity4b <= 1'b1; end
6'b000101 : begin shiftOut[1:6] <= 6'b010010; runDisparity4b <= 1'b0; end
6'b000110 : begin shiftOut[1:6] <= 6'b110001; runDisparity4b <= 1'b0; end
6'b000111 : begin shiftOut[1:6] <= 6'b110001; runDisparity4b <= 1'b1; end
6'b001000 : begin shiftOut[1:6] <= 6'b110101; runDisparity4b <= 1'b1; end
6'b001001 : begin shiftOut[1:6] <= 6'b001010; runDisparity4b <= 1'b0; end
6'b001010 : begin shiftOut[1:6] <= 6'b101001; runDisparity4b <= 1'b0; end
6'b001011 : begin shiftOut[1:6] <= 6'b101001; runDisparity4b <= 1'b1; end
6'b001100 : begin shiftOut[1:6] <= 6'b011001; runDisparity4b <= 1'b0; end
6'b001101 : begin shiftOut[1:6] <= 6'b011001; runDisparity4b <= 1'b1; end
6'b001110 : begin shiftOut[1:6] <= 6'b111000; runDisparity4b <= 1'b0; end
6'b001111 : begin shiftOut[1:6] <= 6'b000111; runDisparity4b <= 1'b1; end
6'b010000 : begin shiftOut[1:6] <= 6'b111001; runDisparity4b <= 1'b1; end
6'b010001 : begin shiftOut[1:6] <= 6'b000110; runDisparity4b <= 1'b0; end
6'b010010 : begin shiftOut[1:6] <= 6'b100101; runDisparity4b <= 1'b0; end
6'b010011 : begin shiftOut[1:6] <= 6'b100101; runDisparity4b <= 1'b1; end
6'b010100 : begin shiftOut[1:6] <= 6'b010101; runDisparity4b <= 1'b0; end
6'b010101 : begin shiftOut[1:6] <= 6'b010101; runDisparity4b <= 1'b1; end
6'b010110 : begin shiftOut[1:6] <= 6'b110100; runDisparity4b <= 1'b0; end
6'b010111 : begin shiftOut[1:6] <= 6'b110100; runDisparity4b <= 1'b1; useAlt <= 1'b1; end
6'b011000 : begin shiftOut[1:6] <= 6'b001101; runDisparity4b <= 1'b0; end
6'b011001 : begin shiftOut[1:6] <= 6'b001101; runDisparity4b <= 1'b1; end
6'b011010 : begin shiftOut[1:6] <= 6'b101100; runDisparity4b <= 1'b0; end
6'b011011 : begin shiftOut[1:6] <= 6'b101100; runDisparity4b <= 1'b1; useAlt <= 1'b1; end
6'b011100 : begin shiftOut[1:6] <= 6'b011100; runDisparity4b <= 1'b0; end
6'b011101 : begin shiftOut[1:6] <= 6'b011100; runDisparity4b <= 1'b1; useAlt <= 1'b1; end
6'b011110 : begin shiftOut[1:6] <= 6'b010111; runDisparity4b <= 1'b1; end
6'b011111 : begin shiftOut[1:6] <= 6'b101000; runDisparity4b <= 1'b0; end
6'b100000 : begin shiftOut[1:6] <= 6'b011011; runDisparity4b <= 1'b1; end
6'b100001 : begin shiftOut[1:6] <= 6'b100100; runDisparity4b <= 1'b0; end
6'b100010 : begin shiftOut[1:6] <= 6'b100011; runDisparity4b <= 1'b0; useAlt <= 1'b1; end
6'b100011 : begin shiftOut[1:6] <= 6'b100011; runDisparity4b <= 1'b1; end
6'b100100 : begin shiftOut[1:6] <= 6'b010011; runDisparity4b <= 1'b0; useAlt <= 1'b1; end
6'b100101 : begin shiftOut[1:6] <= 6'b010011; runDisparity4b <= 1'b1; end
6'b100110 : begin shiftOut[1:6] <= 6'b110010; runDisparity4b <= 1'b0; end
6'b100111 : begin shiftOut[1:6] <= 6'b110010; runDisparity4b <= 1'b1; end
6'b101000 : begin shiftOut[1:6] <= 6'b001011; runDisparity4b <= 1'b0; useAlt <= 1'b1; end
6'b101001 : begin shiftOut[1:6] <= 6'b001011; runDisparity4b <= 1'b1; end
6'b101010 : begin shiftOut[1:6] <= 6'b101010; runDisparity4b <= 1'b0; end
6'b101011 : begin shiftOut[1:6] <= 6'b101010; runDisparity4b <= 1'b1; end
6'b101100 : begin shiftOut[1:6] <= 6'b011010; runDisparity4b <= 1'b0; end
6'b101101 : begin shiftOut[1:6] <= 6'b011010; runDisparity4b <= 1'b1; end
6'b101110 : begin shiftOut[1:6] <= 6'b111010; runDisparity4b <= 1'b1; end
6'b101111 : begin shiftOut[1:6] <= 6'b000101; runDisparity4b <= 1'b0; end
6'b110000 : begin shiftOut[1:6] <= 6'b110011; runDisparity4b <= 1'b1; end
6'b110001 : begin shiftOut[1:6] <= 6'b001100; runDisparity4b <= 1'b0; end
6'b110010 : begin shiftOut[1:6] <= 6'b100110; runDisparity4b <= 1'b0; end
6'b110011 : begin shiftOut[1:6] <= 6'b100110; runDisparity4b <= 1'b1; end
6'b110100 : begin shiftOut[1:6] <= 6'b010110; runDisparity4b <= 1'b0; end
6'b110101 : begin shiftOut[1:6] <= 6'b010110; runDisparity4b <= 1'b1; end
6'b110110 : begin shiftOut[1:6] <= 6'b110110; runDisparity4b <= 1'b1; end
6'b110111 : begin shiftOut[1:6] <= 6'b001001; runDisparity4b <= 1'b0; end
6'b111000 : begin shiftOut[1:6] <= 6'b001110; runDisparity4b <= 1'b0; end
6'b111001 : begin shiftOut[1:6] <= 6'b001110; runDisparity4b <= 1'b1; end
6'b111010 : begin shiftOut[1:6] <= 6'b101110; runDisparity4b <= 1'b1; end
6'b111011 : begin shiftOut[1:6] <= 6'b010001; runDisparity4b <= 1'b0; end
6'b111100 : begin shiftOut[1:6] <= 6'b011110; runDisparity4b <= 1'b1; end
6'b111101 : begin shiftOut[1:6] <= 6'b100001; runDisparity4b <= 1'b0; end
6'b111110 : begin shiftOut[1:6] <= 6'b101011; runDisparity4b <= 1'b1; end
6'b111111 : begin shiftOut[1:6] <= 6'b010100; runDisparity4b <= 1'b0; end
endcase
end
else begin
shiftOut[1:6] <= (runDisparity4b) ? FILL_WORD_RD1[9:4] : FILL_WORD_RD0[9:4];
runDisparity6b <= runDisparity4b;
end
end
else if (outCounter == 'd9) begin
outCounter <= outCounter - 2'd1;
shiftOut[1:5] <= shiftOut[2:6];
// 3b/4b Encoder
if (dataPresentLatch) begin
readStrobe <= 1'b1;
case ({dataToEncode[7:5], runDisparity4b})
4'b0000 : begin shiftOut[6:9] <= 4'b1011; runDisparity6b <= 1'b1; end
4'b0001 : begin shiftOut[6:9] <= 4'b0100; runDisparity6b <= 1'b0; end
4'b0010 : begin shiftOut[6:9] <= 4'b1001; runDisparity6b <= 1'b0; end
4'b0011 : begin shiftOut[6:9] <= 4'b1001; runDisparity6b <= 1'b1; end
4'b0100 : begin shiftOut[6:9] <= 4'b0101; runDisparity6b <= 1'b0; end
4'b0101 : begin shiftOut[6:9] <= 4'b0101; runDisparity6b <= 1'b1; end
4'b0110 : begin shiftOut[6:9] <= 4'b1100; runDisparity6b <= 1'b0; end
4'b0111 : begin shiftOut[6:9] <= 4'b0011; runDisparity6b <= 1'b1; end
4'b1000 : begin shiftOut[6:9] <= 4'b1101; runDisparity6b <= 1'b1; end
4'b1001 : begin shiftOut[6:9] <= 4'b0010; runDisparity6b <= 1'b0; end
4'b1010 : begin shiftOut[6:9] <= 4'b1010; runDisparity6b <= 1'b0; end
4'b1011 : begin shiftOut[6:9] <= 4'b1010; runDisparity6b <= 1'b1; end
4'b1100 : begin shiftOut[6:9] <= 4'b0110; runDisparity6b <= 1'b0; end
4'b1101 : begin shiftOut[6:9] <= 4'b0110; runDisparity6b <= 1'b1; end
4'b1110 : begin shiftOut[6:9] <= (useAlt) ? 4'b0111 : 4'b1110; runDisparity6b <= 1'b1; end
4'b1111 : begin shiftOut[6:9] <= (useAlt) ? 4'b1000 : 4'b0001; runDisparity6b <= 1'b0; end
endcase
end
else begin
readStrobe <= 1'b0;
shiftOut[6:9] <= (runDisparity4b) ? FILL_WORD_RD1[3:0] : FILL_WORD_RD0[3:0];
runDisparity4b <= FILL_WORD_FLIP ^ runDisparity6b;
end
end
else begin
readStrobe <= 1'b0;
outCounter <= outCounter - 2'd1;
shiftOut <= {shiftOut[2:9], 1'b0};
end
end
else begin
readStrobe <= 1'b0;
end
end
endmodule
|
module incrementCounter (pcprev, newpc); //increments value from PC counter to next instruction
input [31:0] pcprev; //setting up inputs and outputs
reg [31:0] newpcreg;
output [31:0] newpc;
always@ (pcprev) begin //whenever pcprev changes, do the following
assign newpcreg = pcprev + 1; //add 1 to pcprev and assign that value as the output, as memory is an array of 32 bit elements
end
assign newpc = newpcreg; //assigning actual output
endmodule
module ProgramCounter(clk, in, out, rst); //keeps track of the current address in I-mem
input clk; //clock as input
input rst; //reset value
input [31:0] in; //in as input
output [31:0] out; //out as output
reg signed [31:0] out;//out register
always @(posedge clk)//run when at clock positive edge
out = rst ? 32'b00000000000000000000000000000000 : in ; // reset state
endmodule
module InstrMemory(addr, out);
input [31:0] addr;
output [31:0] out;
reg [31:0] out;
reg[31:0] mem [0:1000]; //hard coded to 1000 elements, just for simplicity's sake
initial $readmemb("prog2.bin",mem); //reading in memory
always @(*) //output the memory at the desired address
out = mem[addr];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_M_V
`define SKY130_FD_SC_LP__NAND4_M_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4_m (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4_m (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_M_V
|
`include "shifter.v"
`ifndef TESTS
`define TESTS 32
`endif
module test;
reg[`WIDTH-1:0] data;
reg[`SHIFT_WIDTH-1:0] shift;
reg[`OPS-1:0] op;
wire[`WIDTH-1:0] result;
reg[`WIDTH-1:0] corr_result;
reg[`WIDTH-1:0] test_vals[0:`TESTS-1];
reg[`SHIFT_WIDTH-1:0] test_shifts[0:`TESTS-1];
reg start;
reg[`WIDTH-1:0] tests;
initial begin
$dumpfile("dump.vcd");
$dumpvars;
data = $random;
op = 2'b00;
for (tests = 0; tests < `TESTS; ++tests) begin
test_vals[tests] = $random;//32'b10000000000000000000000000000000;
test_shifts[tests] = $random % 32;
end
data = 0;
shift = test_shifts[0];
tests = 0;
start = 1'b0;
end
reg clk_reg = 1'b0;
wire clk;
assign clk = clk_reg;
always #5 clk_reg <= ~clk_reg;
shifter uut(data, shift, op, start, result);
always @(negedge clk) begin
#2 start <= 1'b0;
if (corr_result != result)
$display("Invalid result : expected - %d, got - %d", corr_result, result);
end
always @(posedge clk) begin
tests <= tests + 1;
data <= test_vals[tests];
shift <= test_shifts[tests];
start <= 1'b1;
case (op)
`LEFT_SHIFTA: corr_result <= $signed(test_vals[tests]) <<< test_shifts[tests];
`LEFT_SHIFTL: corr_result <= test_vals[tests] << test_shifts[tests];
`RIGHT_SHIFTA: corr_result <= $signed(test_vals[tests]) >>> test_shifts[tests];
`RIGHT_SHIFTL: corr_result <= test_vals[tests] >> test_shifts[tests];
default: $display("Invalid op");
endcase
if (tests >= `TESTS-1)
#20 $finish;
end
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_frame_fifo;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast);
// dump file
$dumpfile("test_axis_frame_fifo.lxt");
$dumpvars(0, test_axis_frame_fifo);
end
axis_frame_fifo #(
.ADDR_WIDTH(9),
.DATA_WIDTH(8),
.DROP_WHEN_FULL(0)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast)
);
endmodule
|
`timescale 1ns/1ps
//Reads from accumulate buffer and writes directly to indexed location in DRAM
module dram_read #(
parameter DDR_BASE=31'h00000000,
parameter ADDRESS_WIDTH=31,
parameter TOTAL_DATA=8
) (
clk,
reset,
//External writes to dram
dram_fifo_readdata,
dram_fifo_read,
dram_fifo_empty,
//Write interface to write into DDR memory
control_fixed_location,
control_read_base,
control_read_length,
control_go,
control_done,
user_read_buffer,
user_buffer_output_data,
user_data_available,
dram_flush, //the op_lut_process module will assert this signal, following which dram contents will be available in the fifo
num_keys
);
localparam NUM_STATES=5;
localparam STATE_IDLE=1;
localparam STATE_START_FLUSH=2;
localparam STATE_WAIT_READ=4;
localparam STATE_READ_DATA=8;
localparam STATE_WRITE_FIFO=16;
////////////Ports///////////////////
input clk;
input reset;
//Interface for external writes//
output [63:0] dram_fifo_readdata;
input dram_fifo_read;
output dram_fifo_empty;
// Write control inputs and outputs
output wire control_fixed_location;
output reg [ADDRESS_WIDTH-1:0] control_read_base;
output wire [ADDRESS_WIDTH-1:0] control_read_length;
output reg control_go;
input wire control_done;
// Write user logic inputs and outputs
output reg user_read_buffer;
input wire [255:0] user_buffer_output_data;
input wire user_data_available;
input dram_flush;
input [31:0] num_keys;
///////////Registers/////////////////////
reg [ADDRESS_WIDTH-1:0] control_read_base_next;
reg [ADDRESS_WIDTH-1:0] control_read_length_next;
reg control_go_next;
reg user_read_buffer_next;
reg [NUM_STATES-1:0] state, state_next;
reg [31:0] counter,counter_next;
reg [63:0] dram_wr_val, dram_wr_val_next;
assign control_fixed_location=1'b0;
assign control_read_length = 32;
wire dram_fifo_full;
reg dram_fifo_write, dram_fifo_write_next;
always@(*)
begin
dram_fifo_write_next = 1'b0;
control_read_base_next = control_read_base;
control_go_next = 1'b0;
user_read_buffer_next = 1'b0;
state_next = state;
counter_next = counter;
dram_wr_val_next = dram_wr_val;
case(state)
STATE_IDLE: begin
if(dram_flush) begin //if fifo is not empty, start reading first key
counter_next = 0;
state_next = STATE_START_FLUSH;
end
end
STATE_START_FLUSH: begin
control_read_base_next = DDR_BASE+(counter<<5);
control_go_next = 1'b1;
state_next = STATE_WAIT_READ;
end
STATE_WAIT_READ: begin
if(user_data_available) begin
state_next = STATE_READ_DATA;
user_read_buffer_next = 1'b1;
end
end
STATE_READ_DATA: begin
dram_wr_val_next = {user_buffer_output_data[31:0],user_buffer_output_data[63:32]}; //write 64 bits [key and value]
counter_next = counter+1;
state_next = STATE_WRITE_FIFO;
end
STATE_WRITE_FIFO: begin
if(!dram_fifo_full) begin
dram_fifo_write_next = 1'b1;
//state_next = (counter==TOTAL_DATA)?STATE_IDLE:STATE_START_FLUSH;
state_next = (counter==num_keys)?STATE_IDLE:STATE_START_FLUSH;
end
end
endcase
end
always@(posedge clk or posedge reset)
begin
if(reset) begin
state <= STATE_IDLE;
dram_fifo_write <= 1'b0;
control_read_base <= 0;
control_go <= 0;
user_read_buffer <= 1'b0;
counter <= 0;
dram_wr_val <= 0;
end
else begin
state <= state_next;
dram_fifo_write <= dram_fifo_write_next;
control_read_base <= control_read_base_next;
control_go <= control_go_next;
user_read_buffer <= user_read_buffer_next;
counter <= counter_next;
dram_wr_val <= dram_wr_val_next;
end
end
//External accumulator FIFO (receives external updates from netfpga pipeline)
txfifo #(
.DATA_WIDTH(64),
.LOCAL_FIFO_DEPTH(32)
)fifo (
.clock (clk),
.aclr (reset),
.data (dram_wr_val), //write key and value
.rdreq (dram_fifo_read),
.wrreq (dram_fifo_write),
.q (dram_fifo_readdata),
.empty (dram_fifo_empty),
.full (dram_fifo_full),
.usedw (),
.almost_full ()
);
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_cpu_s1_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_srl_register;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 8'd0;
reg input_axis_tvalid = 1'b0;
reg input_axis_tlast = 1'b0;
reg input_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_srl_register.lxt");
$dumpvars(0, test_axis_srl_register);
end
axis_srl_register #(
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// axi input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off WIDTH
typedef enum logic[2:0] {P=0, W=1'b1, E, N, S} Dirs;
typedef enum integer {UP=0, UW=1'b1} UNSIZED;
// verilator lint_on WIDTH
localparam LEN = 3;
localparam COL = 4;
localparam [59:0] SEQ = {LEN'(N), LEN'(E), LEN'(W), LEN'(P)
,LEN'(S), LEN'(E), LEN'(W), LEN'(P)
,LEN'(S), LEN'(N), LEN'(W), LEN'(P)
,LEN'(S), LEN'(N), LEN'(E), LEN'(P)
,LEN'(S), LEN'(N), LEN'(E), LEN'(W)};
bit [59:0] SE2 = {N, E, W, P
,S, E, W, P
,S, N, W, P
,S, N, E, P
,S, N, E, W};
initial begin
if (SEQ != 60'o32104210431043204321) $stop;
if (SE2 != 60'o32104210431043204321) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3B_TB_V
`define SKY130_FD_SC_HD__NOR3B_TB_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor3b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C_N = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C_N = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__nor3b dut (.A(A), .B(B), .C_N(C_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3B_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR3B_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor3b (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_BLACKBOX_V
|
// module_decoder
`timescale 1 ns / 1 ps
module module_decoder
(
input clk,
input reset,
input davail,
input [3:0]din,
input tbm_hdr,
input tbm_trl,
input roc_hdr,
input idle_in,
output idle_out,
output reg running,
input [7:0]xorsum,
input [1:0]error_in,
output [1:0]error_out,
output reg write,
output reg [15:0]data
);
// --- error flags -----------------------------------------------------
reg [1:0]sme; // state machine error
reg [2:0]ef; // external error flags
wire [4:0]error_flags = {ef, sme};
/*
bit 0: no TBM trailer or ROC header after TBM header
bit 1: idle pattern detected during readout
bit 2: code error
bit 3: frame error
bit 4: one of the four errors detected
*/
// --- idle detector ---------------------------------------------------
reg [2:0]idle_reg;
reg idle_data;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
idle_reg <= 0;
idle_data <= 0;
end
else if (davail)
begin
idle_reg <= {idle_reg[1:0], &din};
idle_data <= &idle_reg;
end
end
assign idle_out = idle_data;
wire idle = idle_data & idle_in;
// --- data delay chain
reg [3:0]d0;
reg [3:0]d1;
reg [3:0]d2;
always @(posedge clk or posedge reset)
begin
if (reset) {d2, d1, d0} <= 12'd0;
else if (davail) {d2, d1, d0} <= {d1, d0, din};
end
// --- decoder FSM -----------------------------------------------------
localparam SM_IDLE = 6'd0;
localparam SM_H0 = 6'd1;
localparam SM_H1 = 6'd2;
localparam SM_H2 = 6'd3; // writeH
localparam SM_H3 = 6'd4;
localparam SM_H4 = 6'd5; // writeH
localparam SM_H5 = 6'd6;
localparam SM_H6 = 6'd7;
localparam SM_H7 = 6'd8;
localparam SM_H8 = 6'd9;
localparam SM_R0 = 6'd10; // writeR
localparam SM_R1 = 6'd11;
localparam SM_R2 = 6'd12;
localparam SM_R3 = 6'd13; // writeP
localparam SM_R4 = 6'd14;
localparam SM_R5 = 6'd15;
localparam SM_R6 = 6'd16; // writeP
localparam SM_T0 = 6'd20;
localparam SM_T1 = 6'd21;
localparam SM_T2 = 6'd22; // writeT
localparam SM_T3 = 6'd23;
localparam SM_T4 = 6'd24; // writeT
localparam SM_T5 = 6'd25;
localparam SM_ERR = 6'd26;
reg [5:0]sm;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
sm <= SM_IDLE;
sme <= 0;
end
else
begin if (davail)
case (sm)
// --- TBM header detection
SM_IDLE: if (tbm_hdr)
begin
sme <= 2'b00; sm <= SM_H0;
end
SM_H0: sm <= SM_H1; // D0
SM_H1: sm <= SM_H2; // D1
SM_H2: sm <= SM_H3; // D2
SM_H3: sm <= SM_H4; // D3
SM_H4: sm <= SM_H5;
SM_H5: sm <= SM_H6;
// earliest possible position for TT or RH
SM_H6: if (tbm_trl) sm <= SM_T0;
else if (roc_hdr) sm <= SM_R0;
else sm <= SM_H7;
// delayed position
SM_H7: if (tbm_trl) sm <= SM_T0;
else if (roc_hdr) sm <= SM_R0;
else sm <= SM_H8;
// delayed position
SM_H8: if (tbm_trl) sm <= SM_T0;
else if (roc_hdr) sm <= SM_R0;
else
begin
sme[0] <= 1'b1; sm <= SM_ERR;
end
// --- ROC data
SM_R0: sm <= SM_R1;
SM_R1: if (tbm_trl) sm <= SM_T0;
else sm <= SM_R2;
SM_R2: if (tbm_trl) sm <= SM_T0;
else if (roc_hdr) sm <= SM_R0;
else sm <= SM_R3;
SM_R3: if (tbm_trl) sm <= SM_T0;
else if (roc_hdr) sm <= SM_R0;
else sm <= SM_R4;
SM_R4: if (tbm_trl) sm <= SM_T0;
else if (roc_hdr) sm <= SM_R0;
else sm <= SM_R5;
SM_R5: if (tbm_trl) sm <= SM_T0;
else sm <= SM_R6;
SM_R6: if (tbm_trl) sm <= SM_T0;
else if (idle)
begin
sme[1] <= 1'b1; sm <= SM_ERR;
end
else sm <= SM_R1;
SM_ERR: sm <= SM_T0; // set error flags
SM_T0: sm <= SM_T1; // D0
SM_T1: sm <= SM_T2; // D1
SM_T2: sm <= SM_T3; // D2
SM_T3: sm <= SM_T4; // D3
SM_T4: sm <= SM_T5;
default: sm <= SM_IDLE;
endcase
end
end // always
always @(posedge clk or posedge reset)
begin
if (reset) running <= 0;
else running = |sm;
end
// --- error handling --------------------------------------------------
assign error_out = error_flags[1:0];
always @(posedge clk or posedge reset)
begin
if (reset) ef <= 0;
else
begin
if (sm==SM_IDLE) ef <= 0;
else
begin
if (error_in[0]) ef[0] <= 1'b1;
if (error_in[1]) ef[1] <= 1'b1;
ef[2] <= |{ef[1:0], sme};
end
end
end
// --- data handling ---------------------------------------------------
reg [1:0]send;
reg [15:0]data2;
wire writeH = davail && (sm==SM_H2 || sm==SM_H4); // write TBM header
wire writeR = davail && sm==SM_R0; // write ROC header
wire writeP = davail && (sm==SM_R3 || sm==SM_R6); // write ROC data
wire writeT = davail && (sm==SM_T2 || sm==SM_T4); // write TBM trailer
always @(posedge clk or posedge reset)
begin
if (reset)
begin
send <= 0;
write <= 0;
data <= 16'd0;
end
else
begin
write <= writeH || writeR || writeT || (|send && davail);
case (sm)
SM_H2: data <= {4'b1010, 4'b0000, d1, d0};
SM_H4: data <= {4'b1000, 4'b0000, d1, d0};
SM_R0: data <= {4'b0100, xorsum, 2'b00, d0[1:0]};
SM_R3: data <= {4'b0000, d2, d1, d0};
SM_R6:
begin
data2 <= {4'b0010, d2, d1, d0};
if (!(tbm_trl || roc_hdr || idle_data)) send <= 2'b11;
end
SM_T2: data <= error_flags[4] ?
{3'b111, error_flags, 4'd0, 4'd0} :
{3'b111, error_flags, d1, d0};
SM_T4: data <= error_flags[4] ?
{3'b110, error_flags, 4'd0, 4'd0} :
{3'b110, error_flags, d1, d0};
default:
begin
if (tbm_trl || roc_hdr) send <= 2'b00;
else if (send[1]) begin send[1] <= 0; data <= data2; end
else if (send[0]) send[0] <= 0;
end
endcase
end
end
endmodule
|
//======================================
//
// intra mode desicion compare
// luyanheng
//
//======================================
module compare(
clk,
rstn,
cnt,
blockcnt,
bestmode,
bestmode16,
bestmode32,
modebest,
modebest16,
modebest32,
mode2,
mode3,
mode4,
mode5,
mode6,
mode7,
mode8,
mode9,
mode10,
mode11,
mode12,
mode13,
mode14,
mode15,
mode16,
mode17,
mode18,
mode19,
mode20,
mode21,
mode22,
mode23,
mode24,
mode25,
mode26,
mode27,
mode28,
mode29,
mode30,
mode31,
mode32,
mode33
);
parameter MODE=21;
parameter DIGIT=0;
input clk;
input rstn;
input [5:0] cnt;
input [6:0] blockcnt;
output [5:0] bestmode;
output [5:0] bestmode16;
output [5:0] bestmode32;
output [MODE-DIGIT:0] modebest;
output [MODE-DIGIT+2:0] modebest16;
output [MODE-DIGIT+4:0] modebest32;
input [MODE:0] mode2;
input [MODE:0] mode3;
input [MODE:0] mode4;
input [MODE:0] mode5;
input [MODE:0] mode6;
input [MODE:0] mode7;
input [MODE:0] mode8;
input [MODE:0] mode9;
input [MODE:0] mode10;
input [MODE:0] mode11;
input [MODE:0] mode12;
input [MODE:0] mode13;
input [MODE:0] mode14;
input [MODE:0] mode15;
input [MODE:0] mode16;
input [MODE:0] mode17;
input [MODE:0] mode18;
input [MODE:0] mode19;
input [MODE:0] mode20;
input [MODE:0] mode21;
input [MODE:0] mode22;
input [MODE:0] mode23;
input [MODE:0] mode24;
input [MODE:0] mode25;
input [MODE:0] mode26;
input [MODE:0] mode27;
input [MODE:0] mode28;
input [MODE:0] mode29;
input [MODE:0] mode30;
input [MODE:0] mode31;
input [MODE:0] mode32;
input [MODE:0] mode33;
//===================state============================
reg comparebegin;
reg comparebegin16;
reg comparerun16;
reg comparebegin32;
reg comparerun32;
reg comparerun32_reg;
always@(posedge clk or negedge rstn)
if(!rstn)
comparerun16 <= 1'b0;
else if((cnt == 'd5) && (blockcnt[1:0]==2'b00) && blockcnt[6:2])
comparerun16 <= 1'b1;
else if(cnt == 'd37)
comparerun16 <= 1'b0;
always@(posedge clk or negedge rstn)
if(!rstn)
comparerun32 <= 1'b0;
else if((blockcnt[3:0]=='d0)&&(cnt == 'd6) && blockcnt[6:4])
comparerun32 <= 1'b1;
else if(cnt == 'd38)
comparerun32 <= 1'b0;
always@(posedge clk or negedge rstn)
if(!rstn)
comparerun32_reg <= 1'b0;
else
comparerun32_reg <= comparerun32;
always@(posedge clk or negedge rstn)
if(!rstn)
comparebegin <= 1'b0;
else if((cnt == 'd2) && blockcnt)
comparebegin <= 1'b1;
else
comparebegin <= 1'b0;
always@(posedge clk or negedge rstn)
if(!rstn)
comparebegin16 <= 1'b0;
else
comparebegin16 <= comparebegin;
always@(posedge clk or negedge rstn)
if(!rstn)
comparebegin32 <= 1'b0;
else if(blockcnt[3:0]=='d0)
comparebegin32 <= comparebegin16;
//=======================8*8=========================
reg [5:0] bestmode;
reg [MODE-DIGIT:0] modebest;
reg [MODE-DIGIT:0] mode_reg;
reg [MODE-DIGIT:0] mode2_reg;
reg [MODE-DIGIT:0] mode3_reg;
reg [MODE-DIGIT:0] mode4_reg;
reg [MODE-DIGIT:0] mode5_reg;
reg [MODE-DIGIT:0] mode6_reg;
reg [MODE-DIGIT:0] mode7_reg;
reg [MODE-DIGIT:0] mode8_reg;
reg [MODE-DIGIT:0] mode9_reg;
reg [MODE-DIGIT:0] mode10_reg;
reg [MODE-DIGIT:0] mode11_reg;
reg [MODE-DIGIT:0] mode12_reg;
reg [MODE-DIGIT:0] mode13_reg;
reg [MODE-DIGIT:0] mode14_reg;
reg [MODE-DIGIT:0] mode15_reg;
reg [MODE-DIGIT:0] mode16_reg;
reg [MODE-DIGIT:0] mode17_reg;
reg [MODE-DIGIT:0] mode18_reg;
reg [MODE-DIGIT:0] mode19_reg;
reg [MODE-DIGIT:0] mode20_reg;
reg [MODE-DIGIT:0] mode21_reg;
reg [MODE-DIGIT:0] mode22_reg;
reg [MODE-DIGIT:0] mode23_reg;
reg [MODE-DIGIT:0] mode24_reg;
reg [MODE-DIGIT:0] mode25_reg;
reg [MODE-DIGIT:0] mode26_reg;
reg [MODE-DIGIT:0] mode27_reg;
reg [MODE-DIGIT:0] mode28_reg;
reg [MODE-DIGIT:0] mode29_reg;
reg [MODE-DIGIT:0] mode30_reg;
reg [MODE-DIGIT:0] mode31_reg;
reg [MODE-DIGIT:0] mode32_reg;
reg [MODE-DIGIT:0] mode33_reg;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
mode2_reg <= 'd0;
mode3_reg <= 'd0;
mode4_reg <= 'd0;
mode5_reg <= 'd0;
mode6_reg <= 'd0;
mode7_reg <= 'd0;
mode8_reg <= 'd0;
mode9_reg <= 'd0;
mode10_reg <= 'd0;
mode11_reg <= 'd0;
mode12_reg <= 'd0;
mode13_reg <= 'd0;
mode14_reg <= 'd0;
mode15_reg <= 'd0;
mode16_reg <= 'd0;
mode17_reg <= 'd0;
mode18_reg <= 'd0;
mode19_reg <= 'd0;
mode20_reg <= 'd0;
mode21_reg <= 'd0;
mode22_reg <= 'd0;
mode23_reg <= 'd0;
mode24_reg <= 'd0;
mode25_reg <= 'd0;
mode26_reg <= 'd0;
mode27_reg <= 'd0;
mode28_reg <= 'd0;
mode29_reg <= 'd0;
mode30_reg <= 'd0;
mode31_reg <= 'd0;
mode32_reg <= 'd0;
mode33_reg <= 'd0;
end
else if(comparebegin)
begin
mode2_reg <= mode2[MODE:DIGIT];
mode3_reg <= mode3[MODE:DIGIT];
mode4_reg <= mode4[MODE:DIGIT];
mode5_reg <= mode5[MODE:DIGIT];
mode6_reg <= mode6[MODE:DIGIT];
mode7_reg <= mode7[MODE:DIGIT];
mode8_reg <= mode8[MODE:DIGIT];
mode9_reg <= mode9[MODE:DIGIT];
mode10_reg <= mode10[MODE:DIGIT];
mode11_reg <= mode11[MODE:DIGIT];
mode12_reg <= mode12[MODE:DIGIT];
mode13_reg <= mode13[MODE:DIGIT];
mode14_reg <= mode14[MODE:DIGIT];
mode15_reg <= mode15[MODE:DIGIT];
mode16_reg <= mode16[MODE:DIGIT];
mode17_reg <= mode17[MODE:DIGIT];
mode18_reg <= mode18[MODE:DIGIT];
mode19_reg <= mode19[MODE:DIGIT];
mode20_reg <= mode20[MODE:DIGIT];
mode21_reg <= mode21[MODE:DIGIT];
mode22_reg <= mode22[MODE:DIGIT];
mode23_reg <= mode23[MODE:DIGIT];
mode24_reg <= mode24[MODE:DIGIT];
mode25_reg <= mode25[MODE:DIGIT];
mode26_reg <= mode26[MODE:DIGIT];
mode27_reg <= mode27[MODE:DIGIT];
mode28_reg <= mode28[MODE:DIGIT];
mode29_reg <= mode29[MODE:DIGIT];
mode30_reg <= mode30[MODE:DIGIT];
mode31_reg <= mode31[MODE:DIGIT];
mode32_reg <= mode32[MODE:DIGIT];
mode33_reg <= mode33[MODE:DIGIT];
end
always@(posedge clk or negedge rstn)
if(!rstn)
mode_reg <= 'd0;
else
case(cnt)
'd3:mode_reg <= mode3[MODE:DIGIT];
'd4:mode_reg <= mode4_reg;
'd5:mode_reg <= mode5_reg;
'd6:mode_reg <= mode6_reg;
'd7:mode_reg <= mode7_reg;
'd8:mode_reg <= mode8_reg;
'd9:mode_reg <= mode9_reg;
'd10:mode_reg <= mode10_reg;
'd11:mode_reg <= mode11_reg;
'd12:mode_reg <= mode12_reg;
'd13:mode_reg <= mode13_reg;
'd14:mode_reg <= mode14_reg;
'd15:mode_reg <= mode15_reg;
'd16:mode_reg <= mode16_reg;
'd17:mode_reg <= mode17_reg;
'd18:mode_reg <= mode18_reg;
'd19:mode_reg <= mode19_reg;
'd20:mode_reg <= mode20_reg;
'd21:mode_reg <= mode21_reg;
'd22:mode_reg <= mode22_reg;
'd23:mode_reg <= mode23_reg;
'd24:mode_reg <= mode24_reg;
'd25:mode_reg <= mode25_reg;
'd26:mode_reg <= mode26_reg;
'd27:mode_reg <= mode27_reg;
'd28:mode_reg <= mode28_reg;
'd29:mode_reg <= mode29_reg;
'd30:mode_reg <= mode30_reg;
'd31:mode_reg <= mode31_reg;
'd32:mode_reg <= mode32_reg;
'd33:mode_reg <= mode33_reg;
default:mode_reg <= {(MODE-DIGIT+1){1'b1}};
endcase
always@(posedge clk or negedge rstn)
if(!rstn)
begin
bestmode <= 'd0;
modebest <= {(MODE-DIGIT+1){1'b1}};
end
else if(comparebegin)
begin
bestmode <= 'd2;
modebest <= mode2[MODE:DIGIT];
end
else if (modebest > mode_reg)
begin
bestmode <= cnt-1;
modebest <= mode_reg;
end
else
begin
bestmode <= bestmode;
modebest <= modebest;
end
//=======================16*16=======================
reg [5:0] bestmode16;
reg [MODE-DIGIT+2:0] modebest16;
reg [MODE-DIGIT+2:0] mode_reg16;
reg [MODE-DIGIT+2:0] mode2_reg16;
reg [MODE-DIGIT+2:0] mode3_reg16;
reg [MODE-DIGIT+2:0] mode4_reg16;
reg [MODE-DIGIT+2:0] mode5_reg16;
reg [MODE-DIGIT+2:0] mode6_reg16;
reg [MODE-DIGIT+2:0] mode7_reg16;
reg [MODE-DIGIT+2:0] mode8_reg16;
reg [MODE-DIGIT+2:0] mode9_reg16;
reg [MODE-DIGIT+2:0] mode10_reg16;
reg [MODE-DIGIT+2:0] mode11_reg16;
reg [MODE-DIGIT+2:0] mode12_reg16;
reg [MODE-DIGIT+2:0] mode13_reg16;
reg [MODE-DIGIT+2:0] mode14_reg16;
reg [MODE-DIGIT+2:0] mode15_reg16;
reg [MODE-DIGIT+2:0] mode16_reg16;
reg [MODE-DIGIT+2:0] mode17_reg16;
reg [MODE-DIGIT+2:0] mode18_reg16;
reg [MODE-DIGIT+2:0] mode19_reg16;
reg [MODE-DIGIT+2:0] mode20_reg16;
reg [MODE-DIGIT+2:0] mode21_reg16;
reg [MODE-DIGIT+2:0] mode22_reg16;
reg [MODE-DIGIT+2:0] mode23_reg16;
reg [MODE-DIGIT+2:0] mode24_reg16;
reg [MODE-DIGIT+2:0] mode25_reg16;
reg [MODE-DIGIT+2:0] mode26_reg16;
reg [MODE-DIGIT+2:0] mode27_reg16;
reg [MODE-DIGIT+2:0] mode28_reg16;
reg [MODE-DIGIT+2:0] mode29_reg16;
reg [MODE-DIGIT+2:0] mode30_reg16;
reg [MODE-DIGIT+2:0] mode31_reg16;
reg [MODE-DIGIT+2:0] mode32_reg16;
reg [MODE-DIGIT+2:0] mode33_reg16;
reg [MODE-DIGIT+2:0] adda16;
reg [MODE-DIGIT:0] addb16;
wire [MODE-DIGIT+2:0] sum16;
always@(posedge clk or negedge rstn)
if(!rstn)
adda16 <= 'd0;
else
case(cnt)
'd4 : adda16 <= mode2_reg16 ;
'd5 : adda16 <= mode3_reg16 ;
'd6 : adda16 <= mode4_reg16 ;
'd7 : adda16 <= mode5_reg16 ;
'd8 : adda16 <= mode6_reg16 ;
'd9 : adda16 <= mode7_reg16 ;
'd10 : adda16 <= mode8_reg16 ;
'd11 : adda16 <= mode9_reg16 ;
'd12 : adda16 <= mode10_reg16 ;
'd13 : adda16 <= mode11_reg16 ;
'd14 : adda16 <= mode12_reg16 ;
'd15 : adda16 <= mode13_reg16 ;
'd16 : adda16 <= mode14_reg16 ;
'd17 : adda16 <= mode15_reg16 ;
'd18 : adda16 <= mode16_reg16 ;
'd19 : adda16 <= mode17_reg16 ;
'd20 : adda16 <= mode18_reg16 ;
'd21 : adda16 <= mode19_reg16 ;
'd22 : adda16 <= mode20_reg16 ;
'd23 : adda16 <= mode21_reg16 ;
'd24 : adda16 <= mode22_reg16 ;
'd25 : adda16 <= mode23_reg16 ;
'd26 : adda16 <= mode24_reg16 ;
'd27 : adda16 <= mode25_reg16 ;
'd28 : adda16 <= mode26_reg16 ;
'd29 : adda16 <= mode27_reg16 ;
'd30 : adda16 <= mode28_reg16 ;
'd31 : adda16 <= mode29_reg16 ;
'd32 : adda16 <= mode30_reg16 ;
'd33 : adda16 <= mode31_reg16 ;
'd34 : adda16 <= mode32_reg16 ;
'd35 : adda16 <= mode33_reg16 ;
default: adda16 <= 'd0;
endcase
always@(posedge clk or negedge rstn)
if(!rstn)
addb16 <= 'd0;
else
case(cnt)
'd4 : addb16 <= mode2_reg ;
'd5 : addb16 <= mode3_reg ;
'd6 : addb16 <= mode4_reg ;
'd7 : addb16 <= mode5_reg ;
'd8 : addb16 <= mode6_reg ;
'd9 : addb16 <= mode7_reg ;
'd10 : addb16 <= mode8_reg ;
'd11 : addb16 <= mode9_reg ;
'd12 : addb16 <= mode10_reg ;
'd13 : addb16 <= mode11_reg ;
'd14 : addb16 <= mode12_reg ;
'd15 : addb16 <= mode13_reg ;
'd16 : addb16 <= mode14_reg ;
'd17 : addb16 <= mode15_reg ;
'd18 : addb16 <= mode16_reg ;
'd19 : addb16 <= mode17_reg ;
'd20 : addb16 <= mode18_reg ;
'd21 : addb16 <= mode19_reg ;
'd22 : addb16 <= mode20_reg ;
'd23 : addb16 <= mode21_reg ;
'd24 : addb16 <= mode22_reg ;
'd25 : addb16 <= mode23_reg ;
'd26 : addb16 <= mode24_reg ;
'd27 : addb16 <= mode25_reg ;
'd28 : addb16 <= mode26_reg ;
'd29 : addb16 <= mode27_reg ;
'd30 : addb16 <= mode28_reg ;
'd31 : addb16 <= mode29_reg ;
'd32 : addb16 <= mode30_reg ;
'd33 : addb16 <= mode31_reg ;
'd34 : addb16 <= mode32_reg ;
'd35 : addb16 <= mode33_reg ;
default: addb16 <= 'd0;
endcase
assign sum16=adda16+addb16;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
mode2_reg16 <= 'd0;
mode3_reg16 <= 'd0;
mode4_reg16 <= 'd0;
mode5_reg16 <= 'd0;
mode6_reg16 <= 'd0;
mode7_reg16 <= 'd0;
mode8_reg16 <= 'd0;
mode9_reg16 <= 'd0;
mode10_reg16 <= 'd0;
mode11_reg16 <= 'd0;
mode12_reg16 <= 'd0;
mode13_reg16 <= 'd0;
mode14_reg16 <= 'd0;
mode15_reg16 <= 'd0;
mode16_reg16 <= 'd0;
mode17_reg16 <= 'd0;
mode18_reg16 <= 'd0;
mode19_reg16 <= 'd0;
mode20_reg16 <= 'd0;
mode21_reg16 <= 'd0;
mode22_reg16 <= 'd0;
mode23_reg16 <= 'd0;
mode24_reg16 <= 'd0;
mode25_reg16 <= 'd0;
mode26_reg16 <= 'd0;
mode27_reg16 <= 'd0;
mode28_reg16 <= 'd0;
mode29_reg16 <= 'd0;
mode30_reg16 <= 'd0;
mode31_reg16 <= 'd0;
mode32_reg16 <= 'd0;
mode33_reg16 <= 'd0;
end
else if(comparebegin && (blockcnt[1:0]==2'b01))
begin
mode2_reg16 <= 'd0;
mode3_reg16 <= 'd0;
mode4_reg16 <= 'd0;
mode5_reg16 <= 'd0;
mode6_reg16 <= 'd0;
mode7_reg16 <= 'd0;
mode8_reg16 <= 'd0;
mode9_reg16 <= 'd0;
mode10_reg16 <= 'd0;
mode11_reg16 <= 'd0;
mode12_reg16 <= 'd0;
mode13_reg16 <= 'd0;
mode14_reg16 <= 'd0;
mode15_reg16 <= 'd0;
mode16_reg16 <= 'd0;
mode17_reg16 <= 'd0;
mode18_reg16 <= 'd0;
mode19_reg16 <= 'd0;
mode20_reg16 <= 'd0;
mode21_reg16 <= 'd0;
mode22_reg16 <= 'd0;
mode23_reg16 <= 'd0;
mode24_reg16 <= 'd0;
mode25_reg16 <= 'd0;
mode26_reg16 <= 'd0;
mode27_reg16 <= 'd0;
mode28_reg16 <= 'd0;
mode29_reg16 <= 'd0;
mode30_reg16 <= 'd0;
mode31_reg16 <= 'd0;
mode32_reg16 <= 'd0;
mode33_reg16 <= 'd0;
end
else
begin
case(cnt)
'd5 :mode2_reg16 <= sum16;
'd6 :mode3_reg16 <= sum16;
'd7 :mode4_reg16 <= sum16;
'd8 :mode5_reg16 <= sum16;
'd9 :mode6_reg16 <= sum16;
'd10 :mode7_reg16 <= sum16;
'd11 :mode8_reg16 <= sum16;
'd12 :mode9_reg16 <= sum16;
'd13 :mode10_reg16 <= sum16;
'd14 :mode11_reg16 <= sum16;
'd15 :mode12_reg16 <= sum16;
'd16 :mode13_reg16 <= sum16;
'd17 :mode14_reg16 <= sum16;
'd18 :mode15_reg16 <= sum16;
'd19 :mode16_reg16 <= sum16;
'd20 :mode17_reg16 <= sum16;
'd21 :mode18_reg16 <= sum16;
'd22 :mode19_reg16 <= sum16;
'd23 :mode20_reg16 <= sum16;
'd24 :mode21_reg16 <= sum16;
'd25 :mode22_reg16 <= sum16;
'd26 :mode23_reg16 <= sum16;
'd27 :mode24_reg16 <= sum16;
'd28 :mode25_reg16 <= sum16;
'd29 :mode26_reg16 <= sum16;
'd30 :mode27_reg16 <= sum16;
'd31 :mode28_reg16 <= sum16;
'd32 :mode29_reg16 <= sum16;
'd33 :mode30_reg16 <= sum16;
'd34 :mode31_reg16 <= sum16;
'd35 :mode32_reg16 <= sum16;
'd36 :mode33_reg16 <= sum16;
default:
begin
mode2_reg16 <= mode2_reg16 ;
mode3_reg16 <= mode3_reg16 ;
mode4_reg16 <= mode4_reg16 ;
mode5_reg16 <= mode5_reg16 ;
mode6_reg16 <= mode6_reg16 ;
mode7_reg16 <= mode7_reg16 ;
mode8_reg16 <= mode8_reg16 ;
mode9_reg16 <= mode9_reg16 ;
mode10_reg16 <= mode10_reg16;
mode11_reg16 <= mode11_reg16;
mode12_reg16 <= mode12_reg16;
mode13_reg16 <= mode13_reg16;
mode14_reg16 <= mode14_reg16;
mode15_reg16 <= mode15_reg16;
mode16_reg16 <= mode16_reg16;
mode17_reg16 <= mode17_reg16;
mode18_reg16 <= mode18_reg16;
mode19_reg16 <= mode19_reg16;
mode20_reg16 <= mode20_reg16;
mode21_reg16 <= mode21_reg16;
mode22_reg16 <= mode22_reg16;
mode23_reg16 <= mode23_reg16;
mode24_reg16 <= mode24_reg16;
mode25_reg16 <= mode25_reg16;
mode26_reg16 <= mode26_reg16;
mode27_reg16 <= mode27_reg16;
mode28_reg16 <= mode28_reg16;
mode29_reg16 <= mode29_reg16;
mode30_reg16 <= mode30_reg16;
mode31_reg16 <= mode31_reg16;
mode32_reg16 <= mode32_reg16;
mode33_reg16 <= mode33_reg16;
end
endcase
end
always@(posedge clk or negedge rstn)
if(!rstn)
mode_reg16 <= 'd0;
else
mode_reg16 <= sum16 ;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
bestmode16 <= 'd0;
modebest16 <= {(MODE-DIGIT+3){1'b1}};
end
else if(comparebegin16)
begin
bestmode16 <= 'd2;
modebest16 <= {(MODE-DIGIT+3){1'b1}};
end
else if ((modebest16 > mode_reg16) & comparerun16)
begin
bestmode16 <= cnt-4;
modebest16 <= mode_reg16;
end
else
begin
bestmode16 <= bestmode16;
modebest16 <= modebest16;
end
//=======================32*32=======================
reg [5:0] bestmode32;
reg [MODE-DIGIT+4:0] modebest32;
reg [MODE-DIGIT+4:0] mode_reg32;
reg [MODE-DIGIT+4:0] mode2_reg32;
reg [MODE-DIGIT+4:0] mode3_reg32;
reg [MODE-DIGIT+4:0] mode4_reg32;
reg [MODE-DIGIT+4:0] mode5_reg32;
reg [MODE-DIGIT+4:0] mode6_reg32;
reg [MODE-DIGIT+4:0] mode7_reg32;
reg [MODE-DIGIT+4:0] mode8_reg32;
reg [MODE-DIGIT+4:0] mode9_reg32;
reg [MODE-DIGIT+4:0] mode10_reg32;
reg [MODE-DIGIT+4:0] mode11_reg32;
reg [MODE-DIGIT+4:0] mode12_reg32;
reg [MODE-DIGIT+4:0] mode13_reg32;
reg [MODE-DIGIT+4:0] mode14_reg32;
reg [MODE-DIGIT+4:0] mode15_reg32;
reg [MODE-DIGIT+4:0] mode16_reg32;
reg [MODE-DIGIT+4:0] mode17_reg32;
reg [MODE-DIGIT+4:0] mode18_reg32;
reg [MODE-DIGIT+4:0] mode19_reg32;
reg [MODE-DIGIT+4:0] mode20_reg32;
reg [MODE-DIGIT+4:0] mode21_reg32;
reg [MODE-DIGIT+4:0] mode22_reg32;
reg [MODE-DIGIT+4:0] mode23_reg32;
reg [MODE-DIGIT+4:0] mode24_reg32;
reg [MODE-DIGIT+4:0] mode25_reg32;
reg [MODE-DIGIT+4:0] mode26_reg32;
reg [MODE-DIGIT+4:0] mode27_reg32;
reg [MODE-DIGIT+4:0] mode28_reg32;
reg [MODE-DIGIT+4:0] mode29_reg32;
reg [MODE-DIGIT+4:0] mode30_reg32;
reg [MODE-DIGIT+4:0] mode31_reg32;
reg [MODE-DIGIT+4:0] mode32_reg32;
reg [MODE-DIGIT+4:0] mode33_reg32;
reg [MODE-DIGIT+4:0] adda32;
reg [MODE-DIGIT+2:0] addb32;
wire [MODE-DIGIT+4:0] sum32;
always@(posedge clk or negedge rstn)
if(!rstn)
adda32 <= 'd0;
else
case(cnt)
'd6 : adda32 <= mode2_reg32 ;
'd7 : adda32 <= mode3_reg32 ;
'd8 : adda32 <= mode4_reg32 ;
'd9 : adda32 <= mode5_reg32 ;
'd10 : adda32 <= mode6_reg32 ;
'd11 : adda32 <= mode7_reg32 ;
'd12 : adda32 <= mode8_reg32 ;
'd13 : adda32 <= mode9_reg32 ;
'd14 : adda32 <= mode10_reg32 ;
'd15 : adda32 <= mode11_reg32 ;
'd16 : adda32 <= mode12_reg32 ;
'd17 : adda32 <= mode13_reg32 ;
'd18 : adda32 <= mode14_reg32 ;
'd19 : adda32 <= mode15_reg32 ;
'd20 : adda32 <= mode16_reg32 ;
'd21 : adda32 <= mode17_reg32 ;
'd22 : adda32 <= mode18_reg32 ;
'd23 : adda32 <= mode19_reg32 ;
'd24 : adda32 <= mode20_reg32 ;
'd25 : adda32 <= mode21_reg32 ;
'd26 : adda32 <= mode22_reg32 ;
'd27 : adda32 <= mode23_reg32 ;
'd28 : adda32 <= mode24_reg32 ;
'd29 : adda32 <= mode25_reg32 ;
'd30 : adda32 <= mode26_reg32 ;
'd31 : adda32 <= mode27_reg32 ;
'd32 : adda32 <= mode28_reg32 ;
'd33 : adda32 <= mode29_reg32 ;
'd34 : adda32 <= mode30_reg32 ;
'd35 : adda32 <= mode31_reg32 ;
'd36 : adda32 <= mode32_reg32 ;
'd37 : adda32 <= mode33_reg32 ;
default: adda32 <= 'd0;
endcase
always@(posedge clk or negedge rstn)
if(!rstn)
addb32 <= 'd0;
else if(comparerun16)
addb32 <= mode_reg16;
assign sum32=adda32+addb32;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
mode2_reg32 <= 'd0;
mode3_reg32 <= 'd0;
mode4_reg32 <= 'd0;
mode5_reg32 <= 'd0;
mode6_reg32 <= 'd0;
mode7_reg32 <= 'd0;
mode8_reg32 <= 'd0;
mode9_reg32 <= 'd0;
mode10_reg32 <= 'd0;
mode11_reg32 <= 'd0;
mode12_reg32 <= 'd0;
mode13_reg32 <= 'd0;
mode14_reg32 <= 'd0;
mode15_reg32 <= 'd0;
mode16_reg32 <= 'd0;
mode17_reg32 <= 'd0;
mode18_reg32 <= 'd0;
mode19_reg32 <= 'd0;
mode20_reg32 <= 'd0;
mode21_reg32 <= 'd0;
mode22_reg32 <= 'd0;
mode23_reg32 <= 'd0;
mode24_reg32 <= 'd0;
mode25_reg32 <= 'd0;
mode26_reg32 <= 'd0;
mode27_reg32 <= 'd0;
mode28_reg32 <= 'd0;
mode29_reg32 <= 'd0;
mode30_reg32 <= 'd0;
mode31_reg32 <= 'd0;
mode32_reg32 <= 'd0;
mode33_reg32 <= 'd0;
end
else if(comparebegin && (blockcnt[3:0]=='d3))
begin
mode2_reg32 <= 'd0;
mode3_reg32 <= 'd0;
mode4_reg32 <= 'd0;
mode5_reg32 <= 'd0;
mode6_reg32 <= 'd0;
mode7_reg32 <= 'd0;
mode8_reg32 <= 'd0;
mode9_reg32 <= 'd0;
mode10_reg32 <= 'd0;
mode11_reg32 <= 'd0;
mode12_reg32 <= 'd0;
mode13_reg32 <= 'd0;
mode14_reg32 <= 'd0;
mode15_reg32 <= 'd0;
mode16_reg32 <= 'd0;
mode17_reg32 <= 'd0;
mode18_reg32 <= 'd0;
mode19_reg32 <= 'd0;
mode20_reg32 <= 'd0;
mode21_reg32 <= 'd0;
mode22_reg32 <= 'd0;
mode23_reg32 <= 'd0;
mode24_reg32 <= 'd0;
mode25_reg32 <= 'd0;
mode26_reg32 <= 'd0;
mode27_reg32 <= 'd0;
mode28_reg32 <= 'd0;
mode29_reg32 <= 'd0;
mode30_reg32 <= 'd0;
mode31_reg32 <= 'd0;
mode32_reg32 <= 'd0;
mode33_reg32 <= 'd0;
end
else if(blockcnt[1:0]=='d0)
begin
case(cnt)
'd7 :mode2_reg32 <= sum32;
'd8 :mode3_reg32 <= sum32;
'd9 :mode4_reg32 <= sum32;
'd10 :mode5_reg32 <= sum32;
'd11 :mode6_reg32 <= sum32;
'd12 :mode7_reg32 <= sum32;
'd13 :mode8_reg32 <= sum32;
'd14 :mode9_reg32 <= sum32;
'd15 :mode10_reg32 <= sum32;
'd16 :mode11_reg32 <= sum32;
'd17 :mode12_reg32 <= sum32;
'd18 :mode13_reg32 <= sum32;
'd19 :mode14_reg32 <= sum32;
'd20 :mode15_reg32 <= sum32;
'd21 :mode16_reg32 <= sum32;
'd22 :mode17_reg32 <= sum32;
'd23 :mode18_reg32 <= sum32;
'd24 :mode19_reg32 <= sum32;
'd25 :mode20_reg32 <= sum32;
'd26 :mode21_reg32 <= sum32;
'd27 :mode22_reg32 <= sum32;
'd28 :mode23_reg32 <= sum32;
'd29 :mode24_reg32 <= sum32;
'd30 :mode25_reg32 <= sum32;
'd31 :mode26_reg32 <= sum32;
'd32 :mode27_reg32 <= sum32;
'd33 :mode28_reg32 <= sum32;
'd34 :mode29_reg32 <= sum32;
'd35 :mode30_reg32 <= sum32;
'd36 :mode31_reg32 <= sum32;
'd37 :mode32_reg32 <= sum32;
'd38 :mode33_reg32 <= sum32;
default:
begin
mode2_reg32 <= mode2_reg32 ;
mode3_reg32 <= mode3_reg32 ;
mode4_reg32 <= mode4_reg32 ;
mode5_reg32 <= mode5_reg32 ;
mode6_reg32 <= mode6_reg32 ;
mode7_reg32 <= mode7_reg32 ;
mode8_reg32 <= mode8_reg32 ;
mode9_reg32 <= mode9_reg32 ;
mode10_reg32 <= mode10_reg32;
mode11_reg32 <= mode11_reg32;
mode12_reg32 <= mode12_reg32;
mode13_reg32 <= mode13_reg32;
mode14_reg32 <= mode14_reg32;
mode15_reg32 <= mode15_reg32;
mode16_reg32 <= mode16_reg32;
mode17_reg32 <= mode17_reg32;
mode18_reg32 <= mode18_reg32;
mode19_reg32 <= mode19_reg32;
mode20_reg32 <= mode20_reg32;
mode21_reg32 <= mode21_reg32;
mode22_reg32 <= mode22_reg32;
mode23_reg32 <= mode23_reg32;
mode24_reg32 <= mode24_reg32;
mode25_reg32 <= mode25_reg32;
mode26_reg32 <= mode26_reg32;
mode27_reg32 <= mode27_reg32;
mode28_reg32 <= mode28_reg32;
mode29_reg32 <= mode29_reg32;
mode30_reg32 <= mode30_reg32;
mode31_reg32 <= mode31_reg32;
mode32_reg32 <= mode32_reg32;
mode33_reg32 <= mode33_reg32;
end
endcase
end
always@(posedge clk or negedge rstn)
if(!rstn)
mode_reg32 <= 'd0;
else if(comparerun32)
mode_reg32 <= sum32;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
bestmode32 <= 'd0;
modebest32 <= {(MODE-DIGIT+5){1'b1}};
end
else if(comparebegin32)
begin
bestmode32 <= 'd2;
modebest32 <= {(MODE-DIGIT+5){1'b1}};
end
else if ((modebest32 > mode_reg32) & comparerun32_reg)
begin
bestmode32 <= cnt-6;
modebest32 <= mode_reg32;
end
else
begin
bestmode32 <= bestmode32;
modebest32 <= modebest32;
end
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(128'H0000000042c100000000000042c00000),
.C_M_AXI_ADDR_WIDTH(64'H0000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_M_AXI_READ_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(64'H0000000100000001),
.C_M_AXI_READ_ISSUING(64'H0000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(2'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(2'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(2'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(2'H3),
.m_axi_ruser(2'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DFBBN_FUNCTIONAL_PP_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_lp__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_lp__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBN_FUNCTIONAL_PP_V |
/*
ORSoC GFX accelerator core
Copyright 2012, ORSoC, Per Lenander, Anton Fosselius.
INTERPOLATION MODULE - DIVIDER
This file is part of orgfx.
orgfx is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
orgfx is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with orgfx. If not, see <http://www.gnu.org/licenses/>.
*/
/*
This module interpolates by using div_uu division units
One division takes exactly point_width+1 ticks to complete, but many divisions can be pipelined at the same time.
*/
module gfx_interp(clk_i, rst_i,
ack_i, ack_o,
write_i,
// Variables needed for interpolation
edge0_i, edge1_i, area_i,
// Raster position
x_i, y_i, x_o, y_o,
factor0_o, factor1_o,
write_o
);
parameter point_width = 16;
parameter delay_width = 5;
parameter div_delay = point_width+1;
parameter result_width = 4;
input clk_i;
input rst_i;
input ack_i;
output reg ack_o;
input write_i;
input [2*point_width-1:0] edge0_i;
input [2*point_width-1:0] edge1_i;
input [2*point_width-1:0] area_i;
input [point_width-1:0] x_i;
input [point_width-1:0] y_i;
output [point_width-1:0] x_o;
output [point_width-1:0] y_o;
// Generated pixel coordinates
output [point_width-1:0] factor0_o;
output [point_width-1:0] factor1_o;
// Write pixel output signal
output write_o;
// calculates factor0
wire [point_width-1:0] interp0_quotient; // result
wire [point_width-1:0] interp0_reminder;
wire interp0_div_by_zero;
wire interp0_overflow;
// calculates factor1
wire [point_width-1:0] interp1_quotient; // result
wire [point_width-1:0] interp1_reminder;
wire interp1_div_by_zero;
wire interp1_overflow;
reg [delay_width-1:0] phase_counter;
wire division_enable;
always @(posedge clk_i or posedge rst_i)
if(rst_i)
phase_counter <= 1'b0;
else if(division_enable)
phase_counter <= (phase_counter + 1'b1 == div_delay) ? 1'b0 : phase_counter + 1'b1;
// State machine
reg state;
parameter wait_state = 1'b0,
write_state = 1'b1;
// Manage states
always @(posedge clk_i or posedge rst_i)
if(rst_i)
state <= wait_state;
else
case (state)
wait_state:
if(write_o)
state <= write_state;
write_state:
if(ack_i)
state <= wait_state;
endcase
always @(posedge clk_i or posedge rst_i)
begin
// Reset
if(rst_i)
ack_o <= 1'b0;
else
case (state)
wait_state:
ack_o <= 1'b0;
write_state:
if(ack_i)
ack_o <= 1'b1;
endcase
end
wire [point_width-1:0] zeroes = 1'b0;
// division unit 0
div_uu #(2*point_width) dut0 (
.clk (clk_i),
.ena (division_enable),
.z ({edge0_i[point_width-1:0], zeroes}),
.d (area_i[point_width-1:0]),
.q (interp0_quotient),
.s (interp0_reminder),
.div0 (interp0_div_by_zero),
.ovf (interp0_overflow)
);
// division unit 1
div_uu #(2*point_width) dut1 (
.clk (clk_i),
.ena (division_enable),
.z ({edge1_i[point_width-1:0], zeroes}),
.d (area_i[point_width-1:0]),
.q (interp1_quotient),
.s (interp1_reminder),
.div0 (interp1_div_by_zero),
.ovf (interp1_overflow)
);
wire result_full;
wire result_valid;
wire [result_width:0] result_count;
wire result_deque = result_valid & (state == wait_state);
assign write_o = result_deque;
assign division_enable = ~result_full;
wire delay_valid;
wire [delay_width-1:0] delay_phase_counter;
wire division_complete = division_enable & delay_valid & (phase_counter == delay_phase_counter);
wire [point_width-1:0] delay_x, delay_y;
// Fifo for finished results
basic_fifo result_fifo(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( {interp0_quotient, interp1_quotient, delay_x, delay_y} ),
.enq_i ( division_complete ),
.full_o ( result_full ), // TODO: use?
.count_o ( result_count ),
.data_o ( {factor0_o, factor1_o, x_o, y_o} ),
.valid_o ( result_valid ),
.deq_i ( result_deque )
);
defparam result_fifo.fifo_width = 4*point_width;
defparam result_fifo.fifo_bit_depth = result_width;
// Another Fifo for current calculations
basic_fifo queue_fifo(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( {phase_counter, x_i, y_i} ),
.enq_i ( write_i ),
.full_o ( ), // TODO: use?
.count_o ( ),
.data_o ( {delay_phase_counter, delay_x, delay_y} ),
.valid_o ( delay_valid ),
.deq_i ( division_complete )
);
defparam queue_fifo.fifo_width = delay_width + 2*point_width;
defparam queue_fifo.fifo_bit_depth = delay_width;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EBUFN_2_V
`define SKY130_FD_SC_MS__EBUFN_2_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ebufn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ebufn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__EBUFN_2_V
|
/*
-- TESTBENCH_TEMPLATE_VERSION = 2.0
*/
// $Revision: 1.1.8.1 $ $Date: 2012/07/23 16:09:31 $
//-----------------------------------------------------------------------------
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------
/*
Module Description:
This is the testbench for the Video Output bridge core. Test the
functionality of the core using several line standards.
*/
`timescale 1ns / 1ps
//
// This is the test bench top module.
//
module tb_tutorial_v_axi4s_vid_out_0_0;
parameter VDATA_WIDTH = 16;
parameter TDATA_WIDTH = 16;
parameter DLY = 1 ; // Delay to account for global clock routing in post-PAR timing sim
parameter NUM_TESTS = 3; // The number of line standards to run
parameter INTERLACE = 0; // Produce interlaced line standards or not 1= interlace
parameter VID_HALFPERIOD = 3.33; // nom 3.03
parameter AXIS_HALFPERIOD = 3.03; // nom 3.33
reg video_clk = 0;
reg aclk = 0 ;
wire rst;
wire ce;
wire de;
wire vtg_locked;
wire [13:0] active_pixels ;
wire [13:0] total_pixels ;
wire [13:0] hsync_start ;
wire [13:0] hsync_end ;
wire [13:0] active_lines ;
wire [13:0] total_lines ;
wire [13:0] vsync_start ;
wire [13:0] vsync_end ;
wire [VDATA_WIDTH-1:0] video_data ;
wire [TDATA_WIDTH-1:0] axis_video ;
wire axis_tvalid ;
wire axis_tready ;
wire axis_eol ;
wire axis_sof ;
wire wr_error;
wire rd_error;
wire error;
wire frame_complete;
wire aclken = 1;
wire aresetn = 1;
wire vsync;
wire hsync;
wire vblank;
wire hblank;
wire vtg_vsync;
wire vtg_hsync;
wire vtg_vblank;
wire vtg_hblank;
wire vtg_act_vid;
wire fid;
wire vid_field_id;
wire vtg_field_id;
reg vid_ce = 1;
reg [3:0] clk_count = 0;
// clock generators
//
initial forever #VID_HALFPERIOD video_clk = ~video_clk;
initial forever #AXIS_HALFPERIOD aclk = ~aclk;
// clock enable generator
always @ (posedge video_clk) begin
if (clk_count >= 2) begin
clk_count <= 0;
vid_ce <= 1;
end
else begin
clk_count <= clk_count + 1;
vid_ce <= 0;
end
end
//
// This module generates the video timing based on the parameters specified
// by the test program.
//
axis_gen #(
.DLY (DLY),
.INTERLACE (INTERLACE),
.DATA_WIDTH (TDATA_WIDTH)
)
axis_gen_i (
.aclk (aclk ),
.rst (rst ),
.axis_tready (axis_tready ),
.axis_tvalid (axis_tvalid),
.axis_tdata_video (axis_video),
.axis_tlast (axis_eol ),
.axis_tuser_sof (axis_sof ),
.fid (fid),
.active_pixels (active_pixels),
.active_lines (active_lines )
);
timing_gen #(
.DLY (DLY),
.INTERLACE (INTERLACE),
.DATA_WIDTH (VDATA_WIDTH)
)
timing_gen_i (
.clk (video_clk),
.rst (rst),
.ce (ce),
.active_lines (active_lines ),
.total_lines (total_lines ),
.vsync_start (vsync_start ),
.vsync_end (vsync_end ),
.active_pixels (active_pixels),
.total_pixels (total_pixels ),
.hsync_start (hsync_start ),
.hsync_end (hsync_end ),
.hsync (vtg_hsync ),
.vsync (vtg_vsync ),
.hblank (vtg_hblank ),
.vblank (vtg_vblank ),
.de (vtg_act_vid ),
.field_id (vtg_field_id ),
.video_data ()
);
//------------------------------------------------------------------------------
// Top level Video output bridge -- DUT
//
tutorial_v_axi4s_vid_out_0_0
dut (
.aclk (aclk),
.rst (rst),
.aclken (aclken ),
.aresetn (aresetn),
.s_axis_video_tdata (axis_video ),
.s_axis_video_tvalid (axis_tvalid),
.s_axis_video_tready (axis_tready),
.s_axis_video_tuser (axis_sof ),
.s_axis_video_tlast (axis_eol ),
.fid (fid),
.vid_io_out_clk (video_clk),
.vid_io_out_ce (vid_ce),
.vid_active_video (de),
.vid_vsync (vsync),
.vid_hsync (hsync),
.vid_vblank (hblank),
.vid_hblank (vblank),
.vid_field_id (vid_field_id),
.vid_data (video_data),
.vtg_vsync (vtg_vsync ),
.vtg_hsync (vtg_hsync ),
.vtg_vblank (vtg_vblank),
.vtg_hblank (vtg_hblank),
.vtg_active_video (vtg_act_vid),
.vtg_field_id (vtg_field_id),
.vtg_ce (ce),
.locked (vtg_locked), //out
.wr_error (wr_error ), //out
.empty (rd_error ) //out
);
//
// Test program : This program controls the operation of the test bench.
//
test_vid_out #(
.DLY (DLY),
.NUM_TESTS (NUM_TESTS)
)
test_vid_out_i (
.clk (video_clk),
.error (error),
.frame_complete (frame_complete),
.rst (rst),
.total_lines (total_lines),
.active_lines (active_lines),
.vsync_start (vsync_start ),
.vsync_end (vsync_end ),
.total_pixels (total_pixels ),
.active_pixels (active_pixels),
.hsync_start (hsync_start ),
.hsync_end (hsync_end )
);
phy_emulation #(
.DLY (DLY),
.INTERLACE (INTERLACE),
.DATA_WIDTH (VDATA_WIDTH)
)
phy_emulation_i (
.clk (video_clk),
.rst (rst),
.vid_ce (vid_ce),
.hsync (hsync),
.vsync (vsync),
.de (de),
.vid_field_id (vid_field_id),
.video_data (video_data),
.error_out (error),
.frame_complete (frame_complete)
);
endmodule
//****************************************************************************
//------------------------------------------------------------------------------
// This module simulates the AXI-4 streaming interface to the video bridge
// it generates handshaking, and regenerates the x,y pixel location based on eol and
// sof.
//
module axis_gen #(
parameter DLY = 1,
parameter INTERLACE = 0,
parameter DATA_WIDTH = 24
)
(
input wire aclk,
input wire rst,
input wire axis_tready,
output wire axis_tvalid,
output reg [DATA_WIDTH-1:0] axis_tdata_video,
output reg axis_tlast,
output reg fid,
output reg axis_tuser_sof,
input wire [13:0] active_pixels,
input wire [13:0] active_lines
);
// variable declarations
reg [13:0] pixel_count = 0;
reg [13:0] line_count = 0;
wire eol;
wire sof;
reg eol_1;
wire set_axis_tvalid;
real duty_cycle_phase_accum;
assign eol = pixel_count == active_pixels - 1;
assign sof = line_count == 0 && pixel_count == 0;
assign axis_tvalid = 1;
// delay eol
always @ (posedge aclk)
eol_1 <= eol;
//
// pixel counter
//
// Cleared to 0 on reset and at active pixels - 1. Otherwise
// increments every clock cycle.
//
always @ (posedge aclk) begin
if (axis_tready & axis_tvalid)
begin
if (rst || eol)
pixel_count <= 0;
else
pixel_count <= pixel_count + 1;
end
end
//
// Line counter
//
// Set to line 0 on reset or max lines. Increments coincident with pixel 0.
//
always @ (posedge aclk)
if (axis_tready)
begin
if (rst || ((line_count >= active_lines - 1) && eol) )begin
line_count <= 0;
end
else if (eol)
line_count <= line_count + 1;
end
// Generate the video outputs. The video is gengerated procedurally
// according to the line and pixel number. This makes it so the checking
// side can reconstruct the expected data by the same procedure.
always @ (posedge aclk) begin
if (rst) begin
axis_tlast <= 0;
axis_tuser_sof <= 0;
if (INTERLACE)
fid <= 1;
else
fid <= 0;
end
else if (axis_tready) begin
axis_tdata_video <= INTERLACE && ((!fid && sof) || (fid && !sof))?
{~line_count, ~pixel_count[11:0]}:
{line_count, pixel_count[11:0]};
axis_tlast <= eol;
axis_tuser_sof <= sof;
// set field ID bit
if (INTERLACE) begin
if (sof)
fid <= ~fid;
end
else begin
fid <= 0; // always field 0 if not interlaced
end
end
end
endmodule
//****************************************************************************
//------------------------------------------------------------------------------
// This module simulates the generation of the video timing signals. It
// generates the hsync and vsync and blank timing signals.
//
module timing_gen #(
parameter DLY = 1,
parameter INTERLACE = 0,
parameter DATA_WIDTH = 24
)
(
input wire clk,
input wire rst,
input wire ce,
input wire [13:0] active_lines,
input wire [13:0] total_lines,
input wire [13:0] vsync_start,
input wire [13:0] vsync_end,
input wire [13:0] active_pixels,
input wire [13:0] total_pixels,
input wire [13:0] hsync_start,
input wire [13:0] hsync_end,
output wire hsync,
output wire vsync,
output wire hblank,
output wire vblank,
output reg field_id = 0,
output wire de,
output wire [DATA_WIDTH-1:0] video_data
);
// variable declarations
reg [13:0] pixel_count = 0;
reg [13:0] line_count = 0;
reg [8:0] frame_count = 0;
//
// pixel counter
//
// Cleared to 0 on reset. Rolls over when it reaches total_pixels-1. Otherwise
// increments every clock cycle.
//
always @ (posedge clk) begin
if (rst)
# DLY pixel_count <= 0;
else if (ce) begin
if (pixel_count == total_pixels-1)
# DLY pixel_count <= 0;
else
# DLY pixel_count <= pixel_count + 1;
end
end
//
// Line counter
//
// Set to line 0 on reset. Increments coincident with pixel 0.
//
always @ (posedge clk) begin
if (rst) begin
line_count <= # DLY 0;
frame_count <= # DLY 0;
field_id <= # DLY 0;
end
else if (ce) begin
if (frame_count >= 13)
begin
$display ("Frame counter timed out. Test error.");
$display("*******************************");
$display("** ERROR. TEST FAILED !!!");
$display("*******************************");
$stop;
end
else if (pixel_count == total_pixels - 1)
if (line_count == total_lines - 1) begin
line_count <= 0;
frame_count <= frame_count +1;
if (INTERLACE)
field_id <= ~field_id;
else
field_id <= 0; // for non interlace, always field 0
end
else
line_count <= # DLY line_count + 1;
end
end
//
// Generate the hasync, vsync and data enable timing signals at the appropriate place on each line
// by examining the pixel counter.
//
assign hsync = pixel_count >= hsync_start && pixel_count <= hsync_end;
assign vsync = line_count >= vsync_start && line_count <= vsync_end;
assign hblank = !(pixel_count <= (active_pixels-1));
assign vblank = !(line_count <= (active_lines -1));
assign de = line_count <= (active_lines -1) && pixel_count <= (active_pixels - 1);
// Generate the video outputs. The video is generated procedurally
// according to the line and pixel number. This makes it so the checking
// side can reconstruct the expected data by the same procedure.
assign video_data = {line_count , pixel_count[11:0]};
endmodule
//****************************************************************************
//------------------------------------------------------------------------------
// This is the main test program that runs the simulation
//
module test_vid_out #(
parameter DLY = 1,
parameter NUM_TESTS = 2
)
(
input wire clk,
input wire error,
input wire frame_complete,
output reg rst,
output reg [13:0] total_lines,
output reg [13:0] active_lines,
output reg [13:0] vsync_start,
output reg [13:0] vsync_end,
output reg [13:0] total_pixels,
output reg [13:0] active_pixels,
output reg [13:0] hsync_start,
output reg [13:0] hsync_end
);
integer i;
reg [11:0] h_size = 103;
reg [11:0] v_size = 81;
reg [9:0] h_blank = 15;
reg [9:0] v_blank = 8;
reg [9:0] h_sync = 8;
reg [9:0] v_sync = 3;
reg [9:0] h_fp = 3;
reg [9:0] v_fp = 2;
// Task to test one line standard
task test_a_line_std;
input [11:0] h_size;
input [11:0] v_size;
begin
$display("Frame Size is %d x %d ", h_size, v_size);
// Hold reset for several cycles,
rst <= 1;
repeat (10) @ (posedge clk);
rst <= # DLY 0;
wait (frame_complete);
$display("frame_complete");
end
endtask
//
// Stimulus loop
//
// Calls test_a_line_std task for a certain number of line standards
//
initial begin
for (i = 0; i< NUM_TESTS; i= i+1) begin
total_lines = v_size + v_blank;
active_lines = v_size;
vsync_start = v_size + v_fp -1;
vsync_end = vsync_start + v_sync;
total_pixels = h_size + h_blank;
active_pixels = h_size;
hsync_start = h_size + h_fp -1;
hsync_end = hsync_start + h_sync;
$display("Format # %0d", i);
test_a_line_std (
h_size,
v_size
);
h_size= h_size +33;
v_size = v_size + 27;
end
$display("Test passed after testing %0d video formats.", NUM_TESTS);
$display("***************************************");
$display("** Test completed successfully **");
$display("** Simulation finished successfully **");
$display("***************************************");
$stop;
end
endmodule
//****************************************************************************
//------------------------------------------------------------------------------
// This module simulates the PHY interface from the video bridge
// it regenerates the x,y pixel location based on syncs and blanks.
// From the pixel location, it creates an expected data value and compares
// this to the incoming video data.
//
`timescale 1ns / 1ps
module phy_emulation #(
parameter DLY = 1,
parameter INTERLACE = 0,
parameter DATA_WIDTH = 24
)
(
input wire clk,
input wire rst,
input wire vid_ce,
input wire hsync,
input wire vsync,
input wire de,
input wire vid_field_id,
input wire [DATA_WIDTH-1:0] video_data,
output reg error_out,
output reg frame_complete
);
// variable declarations
reg [13:0] pixel_count;
reg [13:0] line_count;
reg [DATA_WIDTH-1:0] video_data_1;
reg de_1;
reg de_2;
reg hsync_1;
reg vsync_1;
wire[DATA_WIDTH-1:0] expected_video_data;
reg count_valid = 0;
wire vsync_rising;
reg vblank;
wire compare_valid;
assign vsync_rising = vsync & !vsync_1;
assign compare_valid = de & count_valid & !frame_complete;
// Delay data and eol to match with pixel and line numbers
always @ (posedge clk) begin
if (vid_ce) begin
video_data_1 <= video_data;
de_1 <= de;
de_2 <= de_1;
hsync_1 <= hsync;
vsync_1 <= vsync;
end
end
//
// pixel counter
//
// Cleared to 0 on reset and hsync. Rolls over when it reaches total_pixels-1. Otherwise
// increments every data enable.
//
always @ (posedge clk) begin
if (vid_ce) begin
if (rst || hsync)
pixel_count <= 0;
else if (de_1)
pixel_count <= pixel_count + 1;
end
end
//
// Line counter
//
// Set to line 0 on reset or vsync. Increments coincident with rising edge
// of de.
//
always @ (posedge clk) begin
if (rst)begin
line_count <= 0;
count_valid <= 0;
frame_complete <= 0;
end
else if (vid_ce) begin
if (vsync_rising) begin // count is valid after 1st vsync
vblank <= 1; // set flag to indicate this is during vert. blank
line_count <= 0;
if ( !INTERLACE || vid_field_id) // for interlace start with field 1
count_valid <= 1;
// if count_valid is already asserted, the frame is complete
// For interlace, additionally, wait for field 2
if ( count_valid && (!INTERLACE || vid_field_id))
frame_complete <= 1;
end
else if (&line_count)
begin
$display ("Line counter reached maximum value. Test error.");
$stop;
end
else if (de & !de_1) begin// increment on every rising de after vblank
if (!vblank)
line_count <= line_count + 1;
vblank <= 0;
end
end
end
// Generate the video outputs. The video is gengerated procedurally
// according to the line and pixel number. This makes it so the checking
// side can reconstruct the expected data by the same procedure.
assign expected_video_data = vid_field_id?
{~line_count, ~pixel_count[11:0]}: //invert data for field 1
{line_count, pixel_count[11:0]};
always @ (posedge clk) begin
if (vid_ce) begin
error_out <= 0;
if (compare_valid) begin
# DLY #DLY if (video_data_1 != expected_video_data) begin
$display ("Data Mismatch. Expected: %h, received: %h. Test error.",
expected_video_data, video_data_1);
error_out <= 1;
$display("*******************************");
$display("** ERROR. TEST FAILED !!!");
$display("*******************************");
$stop;
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_0_V
`define SKY130_FD_SC_LP__O221AI_0_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221ai_0 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221ai_0 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_0_V
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1500949681 : 255;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / HBM_ONE_STACK_INTF
// /___/ /\ Filename : HBM_ONE_STACK_INTF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module HBM_ONE_STACK_INTF #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CLK_SEL_00 = "FALSE",
parameter CLK_SEL_01 = "FALSE",
parameter CLK_SEL_02 = "FALSE",
parameter CLK_SEL_03 = "FALSE",
parameter CLK_SEL_04 = "FALSE",
parameter CLK_SEL_05 = "FALSE",
parameter CLK_SEL_06 = "FALSE",
parameter CLK_SEL_07 = "FALSE",
parameter CLK_SEL_08 = "FALSE",
parameter CLK_SEL_09 = "FALSE",
parameter CLK_SEL_10 = "FALSE",
parameter CLK_SEL_11 = "FALSE",
parameter CLK_SEL_12 = "FALSE",
parameter CLK_SEL_13 = "FALSE",
parameter CLK_SEL_14 = "FALSE",
parameter CLK_SEL_15 = "FALSE",
parameter integer DATARATE_00 = 1800,
parameter integer DATARATE_01 = 1800,
parameter integer DATARATE_02 = 1800,
parameter integer DATARATE_03 = 1800,
parameter integer DATARATE_04 = 1800,
parameter integer DATARATE_05 = 1800,
parameter integer DATARATE_06 = 1800,
parameter integer DATARATE_07 = 1800,
parameter DA_LOCKOUT = "FALSE",
parameter [0:0] IS_APB_0_PCLK_INVERTED = 1'b0,
parameter [0:0] IS_APB_0_PRESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_00_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_00_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_01_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_01_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_02_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_02_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_03_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_03_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_04_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_04_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_05_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_05_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_06_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_06_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_07_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_07_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_08_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_08_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_09_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_09_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_10_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_10_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_11_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_11_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_12_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_12_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_13_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_13_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_14_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_14_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_15_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_15_ARESET_N_INVERTED = 1'b0,
parameter MC_ENABLE_0 = "FALSE",
parameter MC_ENABLE_1 = "FALSE",
parameter MC_ENABLE_2 = "FALSE",
parameter MC_ENABLE_3 = "FALSE",
parameter MC_ENABLE_4 = "FALSE",
parameter MC_ENABLE_5 = "FALSE",
parameter MC_ENABLE_6 = "FALSE",
parameter MC_ENABLE_7 = "FALSE",
parameter MC_ENABLE_APB = "FALSE",
parameter integer PAGEHIT_PERCENT_00 = 75,
parameter PHY_ENABLE_00 = "FALSE",
parameter PHY_ENABLE_01 = "FALSE",
parameter PHY_ENABLE_02 = "FALSE",
parameter PHY_ENABLE_03 = "FALSE",
parameter PHY_ENABLE_04 = "FALSE",
parameter PHY_ENABLE_05 = "FALSE",
parameter PHY_ENABLE_06 = "FALSE",
parameter PHY_ENABLE_07 = "FALSE",
parameter PHY_ENABLE_08 = "FALSE",
parameter PHY_ENABLE_09 = "FALSE",
parameter PHY_ENABLE_10 = "FALSE",
parameter PHY_ENABLE_11 = "FALSE",
parameter PHY_ENABLE_12 = "FALSE",
parameter PHY_ENABLE_13 = "FALSE",
parameter PHY_ENABLE_14 = "FALSE",
parameter PHY_ENABLE_15 = "FALSE",
parameter PHY_ENABLE_APB = "FALSE",
parameter PHY_PCLK_INVERT_01 = "FALSE",
parameter integer READ_PERCENT_00 = 50,
parameter integer READ_PERCENT_01 = 50,
parameter integer READ_PERCENT_02 = 50,
parameter integer READ_PERCENT_03 = 50,
parameter integer READ_PERCENT_04 = 50,
parameter integer READ_PERCENT_05 = 50,
parameter integer READ_PERCENT_06 = 50,
parameter integer READ_PERCENT_07 = 50,
parameter integer READ_PERCENT_08 = 50,
parameter integer READ_PERCENT_09 = 50,
parameter integer READ_PERCENT_10 = 50,
parameter integer READ_PERCENT_11 = 50,
parameter integer READ_PERCENT_12 = 50,
parameter integer READ_PERCENT_13 = 50,
parameter integer READ_PERCENT_14 = 50,
parameter integer READ_PERCENT_15 = 50,
parameter SIM_DEVICE = "ULTRASCALE_PLUS",
parameter integer STACK_LOCATION = 0,
parameter SWITCH_ENABLE = "FALSE",
parameter integer WRITE_PERCENT_00 = 50,
parameter integer WRITE_PERCENT_01 = 50,
parameter integer WRITE_PERCENT_02 = 50,
parameter integer WRITE_PERCENT_03 = 50,
parameter integer WRITE_PERCENT_04 = 50,
parameter integer WRITE_PERCENT_05 = 50,
parameter integer WRITE_PERCENT_06 = 50,
parameter integer WRITE_PERCENT_07 = 50,
parameter integer WRITE_PERCENT_08 = 50,
parameter integer WRITE_PERCENT_09 = 50,
parameter integer WRITE_PERCENT_10 = 50,
parameter integer WRITE_PERCENT_11 = 50,
parameter integer WRITE_PERCENT_12 = 50,
parameter integer WRITE_PERCENT_13 = 50,
parameter integer WRITE_PERCENT_14 = 50,
parameter integer WRITE_PERCENT_15 = 50
)(
output [31:0] APB_0_PRDATA,
output APB_0_PREADY,
output APB_0_PSLVERR,
output AXI_00_ARREADY,
output AXI_00_AWREADY,
output [5:0] AXI_00_BID,
output [1:0] AXI_00_BRESP,
output AXI_00_BVALID,
output [1:0] AXI_00_DFI_AW_AERR_N,
output AXI_00_DFI_CLK_BUF,
output [7:0] AXI_00_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_00_DFI_DW_RDDATA_DBI,
output [7:0] AXI_00_DFI_DW_RDDATA_DERR,
output [1:0] AXI_00_DFI_DW_RDDATA_VALID,
output AXI_00_DFI_INIT_COMPLETE,
output AXI_00_DFI_PHYUPD_REQ,
output AXI_00_DFI_PHY_LP_STATE,
output AXI_00_DFI_RST_N_BUF,
output [5:0] AXI_00_MC_STATUS,
output [7:0] AXI_00_PHY_STATUS,
output [255:0] AXI_00_RDATA,
output [31:0] AXI_00_RDATA_PARITY,
output [5:0] AXI_00_RID,
output AXI_00_RLAST,
output [1:0] AXI_00_RRESP,
output AXI_00_RVALID,
output AXI_00_WREADY,
output AXI_01_ARREADY,
output AXI_01_AWREADY,
output [5:0] AXI_01_BID,
output [1:0] AXI_01_BRESP,
output AXI_01_BVALID,
output [1:0] AXI_01_DFI_AW_AERR_N,
output AXI_01_DFI_CLK_BUF,
output [7:0] AXI_01_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_01_DFI_DW_RDDATA_DBI,
output [7:0] AXI_01_DFI_DW_RDDATA_DERR,
output [1:0] AXI_01_DFI_DW_RDDATA_VALID,
output AXI_01_DFI_INIT_COMPLETE,
output AXI_01_DFI_PHYUPD_REQ,
output AXI_01_DFI_PHY_LP_STATE,
output AXI_01_DFI_RST_N_BUF,
output [255:0] AXI_01_RDATA,
output [31:0] AXI_01_RDATA_PARITY,
output [5:0] AXI_01_RID,
output AXI_01_RLAST,
output [1:0] AXI_01_RRESP,
output AXI_01_RVALID,
output AXI_01_WREADY,
output AXI_02_ARREADY,
output AXI_02_AWREADY,
output [5:0] AXI_02_BID,
output [1:0] AXI_02_BRESP,
output AXI_02_BVALID,
output [1:0] AXI_02_DFI_AW_AERR_N,
output AXI_02_DFI_CLK_BUF,
output [7:0] AXI_02_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_02_DFI_DW_RDDATA_DBI,
output [7:0] AXI_02_DFI_DW_RDDATA_DERR,
output [1:0] AXI_02_DFI_DW_RDDATA_VALID,
output AXI_02_DFI_INIT_COMPLETE,
output AXI_02_DFI_PHYUPD_REQ,
output AXI_02_DFI_PHY_LP_STATE,
output AXI_02_DFI_RST_N_BUF,
output [5:0] AXI_02_MC_STATUS,
output [7:0] AXI_02_PHY_STATUS,
output [255:0] AXI_02_RDATA,
output [31:0] AXI_02_RDATA_PARITY,
output [5:0] AXI_02_RID,
output AXI_02_RLAST,
output [1:0] AXI_02_RRESP,
output AXI_02_RVALID,
output AXI_02_WREADY,
output AXI_03_ARREADY,
output AXI_03_AWREADY,
output [5:0] AXI_03_BID,
output [1:0] AXI_03_BRESP,
output AXI_03_BVALID,
output [1:0] AXI_03_DFI_AW_AERR_N,
output AXI_03_DFI_CLK_BUF,
output [7:0] AXI_03_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_03_DFI_DW_RDDATA_DBI,
output [7:0] AXI_03_DFI_DW_RDDATA_DERR,
output [1:0] AXI_03_DFI_DW_RDDATA_VALID,
output AXI_03_DFI_INIT_COMPLETE,
output AXI_03_DFI_PHYUPD_REQ,
output AXI_03_DFI_PHY_LP_STATE,
output AXI_03_DFI_RST_N_BUF,
output [255:0] AXI_03_RDATA,
output [31:0] AXI_03_RDATA_PARITY,
output [5:0] AXI_03_RID,
output AXI_03_RLAST,
output [1:0] AXI_03_RRESP,
output AXI_03_RVALID,
output AXI_03_WREADY,
output AXI_04_ARREADY,
output AXI_04_AWREADY,
output [5:0] AXI_04_BID,
output [1:0] AXI_04_BRESP,
output AXI_04_BVALID,
output [1:0] AXI_04_DFI_AW_AERR_N,
output AXI_04_DFI_CLK_BUF,
output [7:0] AXI_04_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_04_DFI_DW_RDDATA_DBI,
output [7:0] AXI_04_DFI_DW_RDDATA_DERR,
output [1:0] AXI_04_DFI_DW_RDDATA_VALID,
output AXI_04_DFI_INIT_COMPLETE,
output AXI_04_DFI_PHYUPD_REQ,
output AXI_04_DFI_PHY_LP_STATE,
output AXI_04_DFI_RST_N_BUF,
output [5:0] AXI_04_MC_STATUS,
output [7:0] AXI_04_PHY_STATUS,
output [255:0] AXI_04_RDATA,
output [31:0] AXI_04_RDATA_PARITY,
output [5:0] AXI_04_RID,
output AXI_04_RLAST,
output [1:0] AXI_04_RRESP,
output AXI_04_RVALID,
output AXI_04_WREADY,
output AXI_05_ARREADY,
output AXI_05_AWREADY,
output [5:0] AXI_05_BID,
output [1:0] AXI_05_BRESP,
output AXI_05_BVALID,
output [1:0] AXI_05_DFI_AW_AERR_N,
output AXI_05_DFI_CLK_BUF,
output [7:0] AXI_05_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_05_DFI_DW_RDDATA_DBI,
output [7:0] AXI_05_DFI_DW_RDDATA_DERR,
output [1:0] AXI_05_DFI_DW_RDDATA_VALID,
output AXI_05_DFI_INIT_COMPLETE,
output AXI_05_DFI_PHYUPD_REQ,
output AXI_05_DFI_PHY_LP_STATE,
output AXI_05_DFI_RST_N_BUF,
output [255:0] AXI_05_RDATA,
output [31:0] AXI_05_RDATA_PARITY,
output [5:0] AXI_05_RID,
output AXI_05_RLAST,
output [1:0] AXI_05_RRESP,
output AXI_05_RVALID,
output AXI_05_WREADY,
output AXI_06_ARREADY,
output AXI_06_AWREADY,
output [5:0] AXI_06_BID,
output [1:0] AXI_06_BRESP,
output AXI_06_BVALID,
output [1:0] AXI_06_DFI_AW_AERR_N,
output AXI_06_DFI_CLK_BUF,
output [7:0] AXI_06_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_06_DFI_DW_RDDATA_DBI,
output [7:0] AXI_06_DFI_DW_RDDATA_DERR,
output [1:0] AXI_06_DFI_DW_RDDATA_VALID,
output AXI_06_DFI_INIT_COMPLETE,
output AXI_06_DFI_PHYUPD_REQ,
output AXI_06_DFI_PHY_LP_STATE,
output AXI_06_DFI_RST_N_BUF,
output [5:0] AXI_06_MC_STATUS,
output [7:0] AXI_06_PHY_STATUS,
output [255:0] AXI_06_RDATA,
output [31:0] AXI_06_RDATA_PARITY,
output [5:0] AXI_06_RID,
output AXI_06_RLAST,
output [1:0] AXI_06_RRESP,
output AXI_06_RVALID,
output AXI_06_WREADY,
output AXI_07_ARREADY,
output AXI_07_AWREADY,
output [5:0] AXI_07_BID,
output [1:0] AXI_07_BRESP,
output AXI_07_BVALID,
output [1:0] AXI_07_DFI_AW_AERR_N,
output AXI_07_DFI_CLK_BUF,
output [7:0] AXI_07_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_07_DFI_DW_RDDATA_DBI,
output [7:0] AXI_07_DFI_DW_RDDATA_DERR,
output [1:0] AXI_07_DFI_DW_RDDATA_VALID,
output AXI_07_DFI_INIT_COMPLETE,
output AXI_07_DFI_PHYUPD_REQ,
output AXI_07_DFI_PHY_LP_STATE,
output AXI_07_DFI_RST_N_BUF,
output [255:0] AXI_07_RDATA,
output [31:0] AXI_07_RDATA_PARITY,
output [5:0] AXI_07_RID,
output AXI_07_RLAST,
output [1:0] AXI_07_RRESP,
output AXI_07_RVALID,
output AXI_07_WREADY,
output AXI_08_ARREADY,
output AXI_08_AWREADY,
output [5:0] AXI_08_BID,
output [1:0] AXI_08_BRESP,
output AXI_08_BVALID,
output [1:0] AXI_08_DFI_AW_AERR_N,
output AXI_08_DFI_CLK_BUF,
output [7:0] AXI_08_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_08_DFI_DW_RDDATA_DBI,
output [7:0] AXI_08_DFI_DW_RDDATA_DERR,
output [1:0] AXI_08_DFI_DW_RDDATA_VALID,
output AXI_08_DFI_INIT_COMPLETE,
output AXI_08_DFI_PHYUPD_REQ,
output AXI_08_DFI_PHY_LP_STATE,
output AXI_08_DFI_RST_N_BUF,
output [5:0] AXI_08_MC_STATUS,
output [7:0] AXI_08_PHY_STATUS,
output [255:0] AXI_08_RDATA,
output [31:0] AXI_08_RDATA_PARITY,
output [5:0] AXI_08_RID,
output AXI_08_RLAST,
output [1:0] AXI_08_RRESP,
output AXI_08_RVALID,
output AXI_08_WREADY,
output AXI_09_ARREADY,
output AXI_09_AWREADY,
output [5:0] AXI_09_BID,
output [1:0] AXI_09_BRESP,
output AXI_09_BVALID,
output [1:0] AXI_09_DFI_AW_AERR_N,
output AXI_09_DFI_CLK_BUF,
output [7:0] AXI_09_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_09_DFI_DW_RDDATA_DBI,
output [7:0] AXI_09_DFI_DW_RDDATA_DERR,
output [1:0] AXI_09_DFI_DW_RDDATA_VALID,
output AXI_09_DFI_INIT_COMPLETE,
output AXI_09_DFI_PHYUPD_REQ,
output AXI_09_DFI_PHY_LP_STATE,
output AXI_09_DFI_RST_N_BUF,
output [255:0] AXI_09_RDATA,
output [31:0] AXI_09_RDATA_PARITY,
output [5:0] AXI_09_RID,
output AXI_09_RLAST,
output [1:0] AXI_09_RRESP,
output AXI_09_RVALID,
output AXI_09_WREADY,
output AXI_10_ARREADY,
output AXI_10_AWREADY,
output [5:0] AXI_10_BID,
output [1:0] AXI_10_BRESP,
output AXI_10_BVALID,
output [1:0] AXI_10_DFI_AW_AERR_N,
output AXI_10_DFI_CLK_BUF,
output [7:0] AXI_10_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_10_DFI_DW_RDDATA_DBI,
output [7:0] AXI_10_DFI_DW_RDDATA_DERR,
output [1:0] AXI_10_DFI_DW_RDDATA_VALID,
output AXI_10_DFI_INIT_COMPLETE,
output AXI_10_DFI_PHYUPD_REQ,
output AXI_10_DFI_PHY_LP_STATE,
output AXI_10_DFI_RST_N_BUF,
output [5:0] AXI_10_MC_STATUS,
output [7:0] AXI_10_PHY_STATUS,
output [255:0] AXI_10_RDATA,
output [31:0] AXI_10_RDATA_PARITY,
output [5:0] AXI_10_RID,
output AXI_10_RLAST,
output [1:0] AXI_10_RRESP,
output AXI_10_RVALID,
output AXI_10_WREADY,
output AXI_11_ARREADY,
output AXI_11_AWREADY,
output [5:0] AXI_11_BID,
output [1:0] AXI_11_BRESP,
output AXI_11_BVALID,
output [1:0] AXI_11_DFI_AW_AERR_N,
output AXI_11_DFI_CLK_BUF,
output [7:0] AXI_11_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_11_DFI_DW_RDDATA_DBI,
output [7:0] AXI_11_DFI_DW_RDDATA_DERR,
output [1:0] AXI_11_DFI_DW_RDDATA_VALID,
output AXI_11_DFI_INIT_COMPLETE,
output AXI_11_DFI_PHYUPD_REQ,
output AXI_11_DFI_PHY_LP_STATE,
output AXI_11_DFI_RST_N_BUF,
output [255:0] AXI_11_RDATA,
output [31:0] AXI_11_RDATA_PARITY,
output [5:0] AXI_11_RID,
output AXI_11_RLAST,
output [1:0] AXI_11_RRESP,
output AXI_11_RVALID,
output AXI_11_WREADY,
output AXI_12_ARREADY,
output AXI_12_AWREADY,
output [5:0] AXI_12_BID,
output [1:0] AXI_12_BRESP,
output AXI_12_BVALID,
output [1:0] AXI_12_DFI_AW_AERR_N,
output AXI_12_DFI_CLK_BUF,
output [7:0] AXI_12_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_12_DFI_DW_RDDATA_DBI,
output [7:0] AXI_12_DFI_DW_RDDATA_DERR,
output [1:0] AXI_12_DFI_DW_RDDATA_VALID,
output AXI_12_DFI_INIT_COMPLETE,
output AXI_12_DFI_PHYUPD_REQ,
output AXI_12_DFI_PHY_LP_STATE,
output AXI_12_DFI_RST_N_BUF,
output [5:0] AXI_12_MC_STATUS,
output [7:0] AXI_12_PHY_STATUS,
output [255:0] AXI_12_RDATA,
output [31:0] AXI_12_RDATA_PARITY,
output [5:0] AXI_12_RID,
output AXI_12_RLAST,
output [1:0] AXI_12_RRESP,
output AXI_12_RVALID,
output AXI_12_WREADY,
output AXI_13_ARREADY,
output AXI_13_AWREADY,
output [5:0] AXI_13_BID,
output [1:0] AXI_13_BRESP,
output AXI_13_BVALID,
output [1:0] AXI_13_DFI_AW_AERR_N,
output AXI_13_DFI_CLK_BUF,
output [7:0] AXI_13_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_13_DFI_DW_RDDATA_DBI,
output [7:0] AXI_13_DFI_DW_RDDATA_DERR,
output [1:0] AXI_13_DFI_DW_RDDATA_VALID,
output AXI_13_DFI_INIT_COMPLETE,
output AXI_13_DFI_PHYUPD_REQ,
output AXI_13_DFI_PHY_LP_STATE,
output AXI_13_DFI_RST_N_BUF,
output [255:0] AXI_13_RDATA,
output [31:0] AXI_13_RDATA_PARITY,
output [5:0] AXI_13_RID,
output AXI_13_RLAST,
output [1:0] AXI_13_RRESP,
output AXI_13_RVALID,
output AXI_13_WREADY,
output AXI_14_ARREADY,
output AXI_14_AWREADY,
output [5:0] AXI_14_BID,
output [1:0] AXI_14_BRESP,
output AXI_14_BVALID,
output [1:0] AXI_14_DFI_AW_AERR_N,
output AXI_14_DFI_CLK_BUF,
output [7:0] AXI_14_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_14_DFI_DW_RDDATA_DBI,
output [7:0] AXI_14_DFI_DW_RDDATA_DERR,
output [1:0] AXI_14_DFI_DW_RDDATA_VALID,
output AXI_14_DFI_INIT_COMPLETE,
output AXI_14_DFI_PHYUPD_REQ,
output AXI_14_DFI_PHY_LP_STATE,
output AXI_14_DFI_RST_N_BUF,
output [5:0] AXI_14_MC_STATUS,
output [7:0] AXI_14_PHY_STATUS,
output [255:0] AXI_14_RDATA,
output [31:0] AXI_14_RDATA_PARITY,
output [5:0] AXI_14_RID,
output AXI_14_RLAST,
output [1:0] AXI_14_RRESP,
output AXI_14_RVALID,
output AXI_14_WREADY,
output AXI_15_ARREADY,
output AXI_15_AWREADY,
output [5:0] AXI_15_BID,
output [1:0] AXI_15_BRESP,
output AXI_15_BVALID,
output [1:0] AXI_15_DFI_AW_AERR_N,
output AXI_15_DFI_CLK_BUF,
output [7:0] AXI_15_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_15_DFI_DW_RDDATA_DBI,
output [7:0] AXI_15_DFI_DW_RDDATA_DERR,
output [1:0] AXI_15_DFI_DW_RDDATA_VALID,
output AXI_15_DFI_INIT_COMPLETE,
output AXI_15_DFI_PHYUPD_REQ,
output AXI_15_DFI_PHY_LP_STATE,
output AXI_15_DFI_RST_N_BUF,
output [255:0] AXI_15_RDATA,
output [31:0] AXI_15_RDATA_PARITY,
output [5:0] AXI_15_RID,
output AXI_15_RLAST,
output [1:0] AXI_15_RRESP,
output AXI_15_RVALID,
output AXI_15_WREADY,
output DRAM_0_STAT_CATTRIP,
output [2:0] DRAM_0_STAT_TEMP,
input [21:0] APB_0_PADDR,
input APB_0_PCLK,
input APB_0_PENABLE,
input APB_0_PRESET_N,
input APB_0_PSEL,
input [31:0] APB_0_PWDATA,
input APB_0_PWRITE,
input AXI_00_ACLK,
input [36:0] AXI_00_ARADDR,
input [1:0] AXI_00_ARBURST,
input AXI_00_ARESET_N,
input [5:0] AXI_00_ARID,
input [3:0] AXI_00_ARLEN,
input [2:0] AXI_00_ARSIZE,
input AXI_00_ARVALID,
input [36:0] AXI_00_AWADDR,
input [1:0] AXI_00_AWBURST,
input [5:0] AXI_00_AWID,
input [3:0] AXI_00_AWLEN,
input [2:0] AXI_00_AWSIZE,
input AXI_00_AWVALID,
input AXI_00_BREADY,
input AXI_00_DFI_LP_PWR_X_REQ,
input AXI_00_RREADY,
input [255:0] AXI_00_WDATA,
input [31:0] AXI_00_WDATA_PARITY,
input AXI_00_WLAST,
input [31:0] AXI_00_WSTRB,
input AXI_00_WVALID,
input AXI_01_ACLK,
input [36:0] AXI_01_ARADDR,
input [1:0] AXI_01_ARBURST,
input AXI_01_ARESET_N,
input [5:0] AXI_01_ARID,
input [3:0] AXI_01_ARLEN,
input [2:0] AXI_01_ARSIZE,
input AXI_01_ARVALID,
input [36:0] AXI_01_AWADDR,
input [1:0] AXI_01_AWBURST,
input [5:0] AXI_01_AWID,
input [3:0] AXI_01_AWLEN,
input [2:0] AXI_01_AWSIZE,
input AXI_01_AWVALID,
input AXI_01_BREADY,
input AXI_01_DFI_LP_PWR_X_REQ,
input AXI_01_RREADY,
input [255:0] AXI_01_WDATA,
input [31:0] AXI_01_WDATA_PARITY,
input AXI_01_WLAST,
input [31:0] AXI_01_WSTRB,
input AXI_01_WVALID,
input AXI_02_ACLK,
input [36:0] AXI_02_ARADDR,
input [1:0] AXI_02_ARBURST,
input AXI_02_ARESET_N,
input [5:0] AXI_02_ARID,
input [3:0] AXI_02_ARLEN,
input [2:0] AXI_02_ARSIZE,
input AXI_02_ARVALID,
input [36:0] AXI_02_AWADDR,
input [1:0] AXI_02_AWBURST,
input [5:0] AXI_02_AWID,
input [3:0] AXI_02_AWLEN,
input [2:0] AXI_02_AWSIZE,
input AXI_02_AWVALID,
input AXI_02_BREADY,
input AXI_02_DFI_LP_PWR_X_REQ,
input AXI_02_RREADY,
input [255:0] AXI_02_WDATA,
input [31:0] AXI_02_WDATA_PARITY,
input AXI_02_WLAST,
input [31:0] AXI_02_WSTRB,
input AXI_02_WVALID,
input AXI_03_ACLK,
input [36:0] AXI_03_ARADDR,
input [1:0] AXI_03_ARBURST,
input AXI_03_ARESET_N,
input [5:0] AXI_03_ARID,
input [3:0] AXI_03_ARLEN,
input [2:0] AXI_03_ARSIZE,
input AXI_03_ARVALID,
input [36:0] AXI_03_AWADDR,
input [1:0] AXI_03_AWBURST,
input [5:0] AXI_03_AWID,
input [3:0] AXI_03_AWLEN,
input [2:0] AXI_03_AWSIZE,
input AXI_03_AWVALID,
input AXI_03_BREADY,
input AXI_03_DFI_LP_PWR_X_REQ,
input AXI_03_RREADY,
input [255:0] AXI_03_WDATA,
input [31:0] AXI_03_WDATA_PARITY,
input AXI_03_WLAST,
input [31:0] AXI_03_WSTRB,
input AXI_03_WVALID,
input AXI_04_ACLK,
input [36:0] AXI_04_ARADDR,
input [1:0] AXI_04_ARBURST,
input AXI_04_ARESET_N,
input [5:0] AXI_04_ARID,
input [3:0] AXI_04_ARLEN,
input [2:0] AXI_04_ARSIZE,
input AXI_04_ARVALID,
input [36:0] AXI_04_AWADDR,
input [1:0] AXI_04_AWBURST,
input [5:0] AXI_04_AWID,
input [3:0] AXI_04_AWLEN,
input [2:0] AXI_04_AWSIZE,
input AXI_04_AWVALID,
input AXI_04_BREADY,
input AXI_04_DFI_LP_PWR_X_REQ,
input AXI_04_RREADY,
input [255:0] AXI_04_WDATA,
input [31:0] AXI_04_WDATA_PARITY,
input AXI_04_WLAST,
input [31:0] AXI_04_WSTRB,
input AXI_04_WVALID,
input AXI_05_ACLK,
input [36:0] AXI_05_ARADDR,
input [1:0] AXI_05_ARBURST,
input AXI_05_ARESET_N,
input [5:0] AXI_05_ARID,
input [3:0] AXI_05_ARLEN,
input [2:0] AXI_05_ARSIZE,
input AXI_05_ARVALID,
input [36:0] AXI_05_AWADDR,
input [1:0] AXI_05_AWBURST,
input [5:0] AXI_05_AWID,
input [3:0] AXI_05_AWLEN,
input [2:0] AXI_05_AWSIZE,
input AXI_05_AWVALID,
input AXI_05_BREADY,
input AXI_05_DFI_LP_PWR_X_REQ,
input AXI_05_RREADY,
input [255:0] AXI_05_WDATA,
input [31:0] AXI_05_WDATA_PARITY,
input AXI_05_WLAST,
input [31:0] AXI_05_WSTRB,
input AXI_05_WVALID,
input AXI_06_ACLK,
input [36:0] AXI_06_ARADDR,
input [1:0] AXI_06_ARBURST,
input AXI_06_ARESET_N,
input [5:0] AXI_06_ARID,
input [3:0] AXI_06_ARLEN,
input [2:0] AXI_06_ARSIZE,
input AXI_06_ARVALID,
input [36:0] AXI_06_AWADDR,
input [1:0] AXI_06_AWBURST,
input [5:0] AXI_06_AWID,
input [3:0] AXI_06_AWLEN,
input [2:0] AXI_06_AWSIZE,
input AXI_06_AWVALID,
input AXI_06_BREADY,
input AXI_06_DFI_LP_PWR_X_REQ,
input AXI_06_RREADY,
input [255:0] AXI_06_WDATA,
input [31:0] AXI_06_WDATA_PARITY,
input AXI_06_WLAST,
input [31:0] AXI_06_WSTRB,
input AXI_06_WVALID,
input AXI_07_ACLK,
input [36:0] AXI_07_ARADDR,
input [1:0] AXI_07_ARBURST,
input AXI_07_ARESET_N,
input [5:0] AXI_07_ARID,
input [3:0] AXI_07_ARLEN,
input [2:0] AXI_07_ARSIZE,
input AXI_07_ARVALID,
input [36:0] AXI_07_AWADDR,
input [1:0] AXI_07_AWBURST,
input [5:0] AXI_07_AWID,
input [3:0] AXI_07_AWLEN,
input [2:0] AXI_07_AWSIZE,
input AXI_07_AWVALID,
input AXI_07_BREADY,
input AXI_07_DFI_LP_PWR_X_REQ,
input AXI_07_RREADY,
input [255:0] AXI_07_WDATA,
input [31:0] AXI_07_WDATA_PARITY,
input AXI_07_WLAST,
input [31:0] AXI_07_WSTRB,
input AXI_07_WVALID,
input AXI_08_ACLK,
input [36:0] AXI_08_ARADDR,
input [1:0] AXI_08_ARBURST,
input AXI_08_ARESET_N,
input [5:0] AXI_08_ARID,
input [3:0] AXI_08_ARLEN,
input [2:0] AXI_08_ARSIZE,
input AXI_08_ARVALID,
input [36:0] AXI_08_AWADDR,
input [1:0] AXI_08_AWBURST,
input [5:0] AXI_08_AWID,
input [3:0] AXI_08_AWLEN,
input [2:0] AXI_08_AWSIZE,
input AXI_08_AWVALID,
input AXI_08_BREADY,
input AXI_08_DFI_LP_PWR_X_REQ,
input AXI_08_RREADY,
input [255:0] AXI_08_WDATA,
input [31:0] AXI_08_WDATA_PARITY,
input AXI_08_WLAST,
input [31:0] AXI_08_WSTRB,
input AXI_08_WVALID,
input AXI_09_ACLK,
input [36:0] AXI_09_ARADDR,
input [1:0] AXI_09_ARBURST,
input AXI_09_ARESET_N,
input [5:0] AXI_09_ARID,
input [3:0] AXI_09_ARLEN,
input [2:0] AXI_09_ARSIZE,
input AXI_09_ARVALID,
input [36:0] AXI_09_AWADDR,
input [1:0] AXI_09_AWBURST,
input [5:0] AXI_09_AWID,
input [3:0] AXI_09_AWLEN,
input [2:0] AXI_09_AWSIZE,
input AXI_09_AWVALID,
input AXI_09_BREADY,
input AXI_09_DFI_LP_PWR_X_REQ,
input AXI_09_RREADY,
input [255:0] AXI_09_WDATA,
input [31:0] AXI_09_WDATA_PARITY,
input AXI_09_WLAST,
input [31:0] AXI_09_WSTRB,
input AXI_09_WVALID,
input AXI_10_ACLK,
input [36:0] AXI_10_ARADDR,
input [1:0] AXI_10_ARBURST,
input AXI_10_ARESET_N,
input [5:0] AXI_10_ARID,
input [3:0] AXI_10_ARLEN,
input [2:0] AXI_10_ARSIZE,
input AXI_10_ARVALID,
input [36:0] AXI_10_AWADDR,
input [1:0] AXI_10_AWBURST,
input [5:0] AXI_10_AWID,
input [3:0] AXI_10_AWLEN,
input [2:0] AXI_10_AWSIZE,
input AXI_10_AWVALID,
input AXI_10_BREADY,
input AXI_10_DFI_LP_PWR_X_REQ,
input AXI_10_RREADY,
input [255:0] AXI_10_WDATA,
input [31:0] AXI_10_WDATA_PARITY,
input AXI_10_WLAST,
input [31:0] AXI_10_WSTRB,
input AXI_10_WVALID,
input AXI_11_ACLK,
input [36:0] AXI_11_ARADDR,
input [1:0] AXI_11_ARBURST,
input AXI_11_ARESET_N,
input [5:0] AXI_11_ARID,
input [3:0] AXI_11_ARLEN,
input [2:0] AXI_11_ARSIZE,
input AXI_11_ARVALID,
input [36:0] AXI_11_AWADDR,
input [1:0] AXI_11_AWBURST,
input [5:0] AXI_11_AWID,
input [3:0] AXI_11_AWLEN,
input [2:0] AXI_11_AWSIZE,
input AXI_11_AWVALID,
input AXI_11_BREADY,
input AXI_11_DFI_LP_PWR_X_REQ,
input AXI_11_RREADY,
input [255:0] AXI_11_WDATA,
input [31:0] AXI_11_WDATA_PARITY,
input AXI_11_WLAST,
input [31:0] AXI_11_WSTRB,
input AXI_11_WVALID,
input AXI_12_ACLK,
input [36:0] AXI_12_ARADDR,
input [1:0] AXI_12_ARBURST,
input AXI_12_ARESET_N,
input [5:0] AXI_12_ARID,
input [3:0] AXI_12_ARLEN,
input [2:0] AXI_12_ARSIZE,
input AXI_12_ARVALID,
input [36:0] AXI_12_AWADDR,
input [1:0] AXI_12_AWBURST,
input [5:0] AXI_12_AWID,
input [3:0] AXI_12_AWLEN,
input [2:0] AXI_12_AWSIZE,
input AXI_12_AWVALID,
input AXI_12_BREADY,
input AXI_12_DFI_LP_PWR_X_REQ,
input AXI_12_RREADY,
input [255:0] AXI_12_WDATA,
input [31:0] AXI_12_WDATA_PARITY,
input AXI_12_WLAST,
input [31:0] AXI_12_WSTRB,
input AXI_12_WVALID,
input AXI_13_ACLK,
input [36:0] AXI_13_ARADDR,
input [1:0] AXI_13_ARBURST,
input AXI_13_ARESET_N,
input [5:0] AXI_13_ARID,
input [3:0] AXI_13_ARLEN,
input [2:0] AXI_13_ARSIZE,
input AXI_13_ARVALID,
input [36:0] AXI_13_AWADDR,
input [1:0] AXI_13_AWBURST,
input [5:0] AXI_13_AWID,
input [3:0] AXI_13_AWLEN,
input [2:0] AXI_13_AWSIZE,
input AXI_13_AWVALID,
input AXI_13_BREADY,
input AXI_13_DFI_LP_PWR_X_REQ,
input AXI_13_RREADY,
input [255:0] AXI_13_WDATA,
input [31:0] AXI_13_WDATA_PARITY,
input AXI_13_WLAST,
input [31:0] AXI_13_WSTRB,
input AXI_13_WVALID,
input AXI_14_ACLK,
input [36:0] AXI_14_ARADDR,
input [1:0] AXI_14_ARBURST,
input AXI_14_ARESET_N,
input [5:0] AXI_14_ARID,
input [3:0] AXI_14_ARLEN,
input [2:0] AXI_14_ARSIZE,
input AXI_14_ARVALID,
input [36:0] AXI_14_AWADDR,
input [1:0] AXI_14_AWBURST,
input [5:0] AXI_14_AWID,
input [3:0] AXI_14_AWLEN,
input [2:0] AXI_14_AWSIZE,
input AXI_14_AWVALID,
input AXI_14_BREADY,
input AXI_14_DFI_LP_PWR_X_REQ,
input AXI_14_RREADY,
input [255:0] AXI_14_WDATA,
input [31:0] AXI_14_WDATA_PARITY,
input AXI_14_WLAST,
input [31:0] AXI_14_WSTRB,
input AXI_14_WVALID,
input AXI_15_ACLK,
input [36:0] AXI_15_ARADDR,
input [1:0] AXI_15_ARBURST,
input AXI_15_ARESET_N,
input [5:0] AXI_15_ARID,
input [3:0] AXI_15_ARLEN,
input [2:0] AXI_15_ARSIZE,
input AXI_15_ARVALID,
input [36:0] AXI_15_AWADDR,
input [1:0] AXI_15_AWBURST,
input [5:0] AXI_15_AWID,
input [3:0] AXI_15_AWLEN,
input [2:0] AXI_15_AWSIZE,
input AXI_15_AWVALID,
input AXI_15_BREADY,
input AXI_15_DFI_LP_PWR_X_REQ,
input AXI_15_RREADY,
input [255:0] AXI_15_WDATA,
input [31:0] AXI_15_WDATA_PARITY,
input AXI_15_WLAST,
input [31:0] AXI_15_WSTRB,
input AXI_15_WVALID,
input BSCAN_DRCK,
input BSCAN_TCK,
input HBM_REF_CLK,
input MBIST_EN_00,
input MBIST_EN_01,
input MBIST_EN_02,
input MBIST_EN_03,
input MBIST_EN_04,
input MBIST_EN_05,
input MBIST_EN_06,
input MBIST_EN_07
);
// define constants
localparam MODULE_NAME = "HBM_ONE_STACK_INTF";
// Parameter encodings and registers
localparam PHY_PCLK_INVERT_01_FALSE = 0;
localparam PHY_PCLK_INVERT_01_TRUE = 1;
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "HBM_ONE_STACK_INTF_dr.v"
`else
localparam [40:1] CLK_SEL_00_REG = CLK_SEL_00;
localparam [40:1] CLK_SEL_01_REG = CLK_SEL_01;
localparam [40:1] CLK_SEL_02_REG = CLK_SEL_02;
localparam [40:1] CLK_SEL_03_REG = CLK_SEL_03;
localparam [40:1] CLK_SEL_04_REG = CLK_SEL_04;
localparam [40:1] CLK_SEL_05_REG = CLK_SEL_05;
localparam [40:1] CLK_SEL_06_REG = CLK_SEL_06;
localparam [40:1] CLK_SEL_07_REG = CLK_SEL_07;
localparam [40:1] CLK_SEL_08_REG = CLK_SEL_08;
localparam [40:1] CLK_SEL_09_REG = CLK_SEL_09;
localparam [40:1] CLK_SEL_10_REG = CLK_SEL_10;
localparam [40:1] CLK_SEL_11_REG = CLK_SEL_11;
localparam [40:1] CLK_SEL_12_REG = CLK_SEL_12;
localparam [40:1] CLK_SEL_13_REG = CLK_SEL_13;
localparam [40:1] CLK_SEL_14_REG = CLK_SEL_14;
localparam [40:1] CLK_SEL_15_REG = CLK_SEL_15;
localparam [10:0] DATARATE_00_REG = DATARATE_00;
localparam [10:0] DATARATE_01_REG = DATARATE_01;
localparam [10:0] DATARATE_02_REG = DATARATE_02;
localparam [10:0] DATARATE_03_REG = DATARATE_03;
localparam [10:0] DATARATE_04_REG = DATARATE_04;
localparam [10:0] DATARATE_05_REG = DATARATE_05;
localparam [10:0] DATARATE_06_REG = DATARATE_06;
localparam [10:0] DATARATE_07_REG = DATARATE_07;
localparam [40:1] DA_LOCKOUT_REG = DA_LOCKOUT;
localparam [0:0] IS_APB_0_PCLK_INVERTED_REG = IS_APB_0_PCLK_INVERTED;
localparam [0:0] IS_APB_0_PRESET_N_INVERTED_REG = IS_APB_0_PRESET_N_INVERTED;
localparam [0:0] IS_AXI_00_ACLK_INVERTED_REG = IS_AXI_00_ACLK_INVERTED;
localparam [0:0] IS_AXI_00_ARESET_N_INVERTED_REG = IS_AXI_00_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_01_ACLK_INVERTED_REG = IS_AXI_01_ACLK_INVERTED;
localparam [0:0] IS_AXI_01_ARESET_N_INVERTED_REG = IS_AXI_01_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_02_ACLK_INVERTED_REG = IS_AXI_02_ACLK_INVERTED;
localparam [0:0] IS_AXI_02_ARESET_N_INVERTED_REG = IS_AXI_02_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_03_ACLK_INVERTED_REG = IS_AXI_03_ACLK_INVERTED;
localparam [0:0] IS_AXI_03_ARESET_N_INVERTED_REG = IS_AXI_03_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_04_ACLK_INVERTED_REG = IS_AXI_04_ACLK_INVERTED;
localparam [0:0] IS_AXI_04_ARESET_N_INVERTED_REG = IS_AXI_04_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_05_ACLK_INVERTED_REG = IS_AXI_05_ACLK_INVERTED;
localparam [0:0] IS_AXI_05_ARESET_N_INVERTED_REG = IS_AXI_05_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_06_ACLK_INVERTED_REG = IS_AXI_06_ACLK_INVERTED;
localparam [0:0] IS_AXI_06_ARESET_N_INVERTED_REG = IS_AXI_06_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_07_ACLK_INVERTED_REG = IS_AXI_07_ACLK_INVERTED;
localparam [0:0] IS_AXI_07_ARESET_N_INVERTED_REG = IS_AXI_07_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_08_ACLK_INVERTED_REG = IS_AXI_08_ACLK_INVERTED;
localparam [0:0] IS_AXI_08_ARESET_N_INVERTED_REG = IS_AXI_08_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_09_ACLK_INVERTED_REG = IS_AXI_09_ACLK_INVERTED;
localparam [0:0] IS_AXI_09_ARESET_N_INVERTED_REG = IS_AXI_09_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_10_ACLK_INVERTED_REG = IS_AXI_10_ACLK_INVERTED;
localparam [0:0] IS_AXI_10_ARESET_N_INVERTED_REG = IS_AXI_10_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_11_ACLK_INVERTED_REG = IS_AXI_11_ACLK_INVERTED;
localparam [0:0] IS_AXI_11_ARESET_N_INVERTED_REG = IS_AXI_11_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_12_ACLK_INVERTED_REG = IS_AXI_12_ACLK_INVERTED;
localparam [0:0] IS_AXI_12_ARESET_N_INVERTED_REG = IS_AXI_12_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_13_ACLK_INVERTED_REG = IS_AXI_13_ACLK_INVERTED;
localparam [0:0] IS_AXI_13_ARESET_N_INVERTED_REG = IS_AXI_13_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_14_ACLK_INVERTED_REG = IS_AXI_14_ACLK_INVERTED;
localparam [0:0] IS_AXI_14_ARESET_N_INVERTED_REG = IS_AXI_14_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_15_ACLK_INVERTED_REG = IS_AXI_15_ACLK_INVERTED;
localparam [0:0] IS_AXI_15_ARESET_N_INVERTED_REG = IS_AXI_15_ARESET_N_INVERTED;
localparam [40:1] MC_ENABLE_0_REG = MC_ENABLE_0;
localparam [40:1] MC_ENABLE_1_REG = MC_ENABLE_1;
localparam [40:1] MC_ENABLE_2_REG = MC_ENABLE_2;
localparam [40:1] MC_ENABLE_3_REG = MC_ENABLE_3;
localparam [40:1] MC_ENABLE_4_REG = MC_ENABLE_4;
localparam [40:1] MC_ENABLE_5_REG = MC_ENABLE_5;
localparam [40:1] MC_ENABLE_6_REG = MC_ENABLE_6;
localparam [40:1] MC_ENABLE_7_REG = MC_ENABLE_7;
localparam [40:1] MC_ENABLE_APB_REG = MC_ENABLE_APB;
localparam [6:0] PAGEHIT_PERCENT_00_REG = PAGEHIT_PERCENT_00;
localparam [40:1] PHY_ENABLE_00_REG = PHY_ENABLE_00;
localparam [40:1] PHY_ENABLE_01_REG = PHY_ENABLE_01;
localparam [40:1] PHY_ENABLE_02_REG = PHY_ENABLE_02;
localparam [40:1] PHY_ENABLE_03_REG = PHY_ENABLE_03;
localparam [40:1] PHY_ENABLE_04_REG = PHY_ENABLE_04;
localparam [40:1] PHY_ENABLE_05_REG = PHY_ENABLE_05;
localparam [40:1] PHY_ENABLE_06_REG = PHY_ENABLE_06;
localparam [40:1] PHY_ENABLE_07_REG = PHY_ENABLE_07;
localparam [40:1] PHY_ENABLE_08_REG = PHY_ENABLE_08;
localparam [40:1] PHY_ENABLE_09_REG = PHY_ENABLE_09;
localparam [40:1] PHY_ENABLE_10_REG = PHY_ENABLE_10;
localparam [40:1] PHY_ENABLE_11_REG = PHY_ENABLE_11;
localparam [40:1] PHY_ENABLE_12_REG = PHY_ENABLE_12;
localparam [40:1] PHY_ENABLE_13_REG = PHY_ENABLE_13;
localparam [40:1] PHY_ENABLE_14_REG = PHY_ENABLE_14;
localparam [40:1] PHY_ENABLE_15_REG = PHY_ENABLE_15;
localparam [40:1] PHY_ENABLE_APB_REG = PHY_ENABLE_APB;
localparam [40:1] PHY_PCLK_INVERT_01_REG = PHY_PCLK_INVERT_01;
localparam [6:0] READ_PERCENT_00_REG = READ_PERCENT_00;
localparam [6:0] READ_PERCENT_01_REG = READ_PERCENT_01;
localparam [6:0] READ_PERCENT_02_REG = READ_PERCENT_02;
localparam [6:0] READ_PERCENT_03_REG = READ_PERCENT_03;
localparam [6:0] READ_PERCENT_04_REG = READ_PERCENT_04;
localparam [6:0] READ_PERCENT_05_REG = READ_PERCENT_05;
localparam [6:0] READ_PERCENT_06_REG = READ_PERCENT_06;
localparam [6:0] READ_PERCENT_07_REG = READ_PERCENT_07;
localparam [6:0] READ_PERCENT_08_REG = READ_PERCENT_08;
localparam [6:0] READ_PERCENT_09_REG = READ_PERCENT_09;
localparam [6:0] READ_PERCENT_10_REG = READ_PERCENT_10;
localparam [6:0] READ_PERCENT_11_REG = READ_PERCENT_11;
localparam [6:0] READ_PERCENT_12_REG = READ_PERCENT_12;
localparam [6:0] READ_PERCENT_13_REG = READ_PERCENT_13;
localparam [6:0] READ_PERCENT_14_REG = READ_PERCENT_14;
localparam [6:0] READ_PERCENT_15_REG = READ_PERCENT_15;
localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE;
localparam [0:0] STACK_LOCATION_REG = STACK_LOCATION;
localparam [40:1] SWITCH_ENABLE_REG = SWITCH_ENABLE;
localparam [6:0] WRITE_PERCENT_00_REG = WRITE_PERCENT_00;
localparam [6:0] WRITE_PERCENT_01_REG = WRITE_PERCENT_01;
localparam [6:0] WRITE_PERCENT_02_REG = WRITE_PERCENT_02;
localparam [6:0] WRITE_PERCENT_03_REG = WRITE_PERCENT_03;
localparam [6:0] WRITE_PERCENT_04_REG = WRITE_PERCENT_04;
localparam [6:0] WRITE_PERCENT_05_REG = WRITE_PERCENT_05;
localparam [6:0] WRITE_PERCENT_06_REG = WRITE_PERCENT_06;
localparam [6:0] WRITE_PERCENT_07_REG = WRITE_PERCENT_07;
localparam [6:0] WRITE_PERCENT_08_REG = WRITE_PERCENT_08;
localparam [6:0] WRITE_PERCENT_09_REG = WRITE_PERCENT_09;
localparam [6:0] WRITE_PERCENT_10_REG = WRITE_PERCENT_10;
localparam [6:0] WRITE_PERCENT_11_REG = WRITE_PERCENT_11;
localparam [6:0] WRITE_PERCENT_12_REG = WRITE_PERCENT_12;
localparam [6:0] WRITE_PERCENT_13_REG = WRITE_PERCENT_13;
localparam [6:0] WRITE_PERCENT_14_REG = WRITE_PERCENT_14;
localparam [6:0] WRITE_PERCENT_15_REG = WRITE_PERCENT_15;
`endif
localparam [7:0] ANALOG_MUX_SEL_0_REG = 8'h00;
localparam [40:1] APB_BYPASS_EN_REG = "FALSE";
localparam [40:1] AXI_BYPASS_EN_REG = "FALSE";
localparam [40:1] BLI_TESTMODE_SEL_REG = "FALSE";
localparam [51:0] DBG_BYPASS_VAL_REG = 52'hFFFFFFFFFFFFF;
localparam [40:1] DEBUG_MODE_REG = "FALSE";
localparam [51:0] DFI_BYPASS_VAL_REG = 52'h0000000000000;
localparam [40:1] DLL_TESTMODE_SEL_0_REG = "FALSE";
localparam [40:1] IO_TESTMODE_SEL_0_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_0_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_1_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_2_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_3_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_4_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_5_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_6_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_7_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_0_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_1_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_2_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_3_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_4_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_5_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_6_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_7_REG = "FALSE";
localparam [40:1] PHY_CSSD_SEL_0_REG = "FALSE";
localparam [40:1] PHY_TESTMODE_SEL_0_REG = "FALSE";
localparam [40:1] SW_TESTMODE_SEL_0_REG = "FALSE";
`ifdef XIL_XECLIB
wire PHY_PCLK_INVERT_01_BIN;
`else
reg PHY_PCLK_INVERT_01_BIN;
`endif
reg attr_test;
reg attr_err;
tri0 glblGSR = glbl.GSR;
wire APB_0_PREADY_out;
wire APB_0_PSLVERR_out;
wire AXI_00_ARREADY_out;
wire AXI_00_AWREADY_out;
wire AXI_00_BVALID_out;
wire AXI_00_DFI_CLK_BUF_out;
wire AXI_00_DFI_INIT_COMPLETE_out;
wire AXI_00_DFI_PHYUPD_REQ_out;
wire AXI_00_DFI_PHY_LP_STATE_out;
wire AXI_00_DFI_RST_N_BUF_out;
wire AXI_00_RLAST_out;
wire AXI_00_RVALID_out;
wire AXI_00_WREADY_out;
wire AXI_01_ARREADY_out;
wire AXI_01_AWREADY_out;
wire AXI_01_BVALID_out;
wire AXI_01_DFI_CLK_BUF_out;
wire AXI_01_DFI_INIT_COMPLETE_out;
wire AXI_01_DFI_PHYUPD_REQ_out;
wire AXI_01_DFI_PHY_LP_STATE_out;
wire AXI_01_DFI_RST_N_BUF_out;
wire AXI_01_RLAST_out;
wire AXI_01_RVALID_out;
wire AXI_01_WREADY_out;
wire AXI_02_ARREADY_out;
wire AXI_02_AWREADY_out;
wire AXI_02_BVALID_out;
wire AXI_02_DFI_CLK_BUF_out;
wire AXI_02_DFI_INIT_COMPLETE_out;
wire AXI_02_DFI_PHYUPD_REQ_out;
wire AXI_02_DFI_PHY_LP_STATE_out;
wire AXI_02_DFI_RST_N_BUF_out;
wire AXI_02_RLAST_out;
wire AXI_02_RVALID_out;
wire AXI_02_WREADY_out;
wire AXI_03_ARREADY_out;
wire AXI_03_AWREADY_out;
wire AXI_03_BVALID_out;
wire AXI_03_DFI_CLK_BUF_out;
wire AXI_03_DFI_INIT_COMPLETE_out;
wire AXI_03_DFI_PHYUPD_REQ_out;
wire AXI_03_DFI_PHY_LP_STATE_out;
wire AXI_03_DFI_RST_N_BUF_out;
wire AXI_03_RLAST_out;
wire AXI_03_RVALID_out;
wire AXI_03_WREADY_out;
wire AXI_04_ARREADY_out;
wire AXI_04_AWREADY_out;
wire AXI_04_BVALID_out;
wire AXI_04_DFI_CLK_BUF_out;
wire AXI_04_DFI_INIT_COMPLETE_out;
wire AXI_04_DFI_PHYUPD_REQ_out;
wire AXI_04_DFI_PHY_LP_STATE_out;
wire AXI_04_DFI_RST_N_BUF_out;
wire AXI_04_RLAST_out;
wire AXI_04_RVALID_out;
wire AXI_04_WREADY_out;
wire AXI_05_ARREADY_out;
wire AXI_05_AWREADY_out;
wire AXI_05_BVALID_out;
wire AXI_05_DFI_CLK_BUF_out;
wire AXI_05_DFI_INIT_COMPLETE_out;
wire AXI_05_DFI_PHYUPD_REQ_out;
wire AXI_05_DFI_PHY_LP_STATE_out;
wire AXI_05_DFI_RST_N_BUF_out;
wire AXI_05_RLAST_out;
wire AXI_05_RVALID_out;
wire AXI_05_WREADY_out;
wire AXI_06_ARREADY_out;
wire AXI_06_AWREADY_out;
wire AXI_06_BVALID_out;
wire AXI_06_DFI_CLK_BUF_out;
wire AXI_06_DFI_INIT_COMPLETE_out;
wire AXI_06_DFI_PHYUPD_REQ_out;
wire AXI_06_DFI_PHY_LP_STATE_out;
wire AXI_06_DFI_RST_N_BUF_out;
wire AXI_06_RLAST_out;
wire AXI_06_RVALID_out;
wire AXI_06_WREADY_out;
wire AXI_07_ARREADY_out;
wire AXI_07_AWREADY_out;
wire AXI_07_BVALID_out;
wire AXI_07_DFI_CLK_BUF_out;
wire AXI_07_DFI_INIT_COMPLETE_out;
wire AXI_07_DFI_PHYUPD_REQ_out;
wire AXI_07_DFI_PHY_LP_STATE_out;
wire AXI_07_DFI_RST_N_BUF_out;
wire AXI_07_RLAST_out;
wire AXI_07_RVALID_out;
wire AXI_07_WREADY_out;
wire AXI_08_ARREADY_out;
wire AXI_08_AWREADY_out;
wire AXI_08_BVALID_out;
wire AXI_08_DFI_CLK_BUF_out;
wire AXI_08_DFI_INIT_COMPLETE_out;
wire AXI_08_DFI_PHYUPD_REQ_out;
wire AXI_08_DFI_PHY_LP_STATE_out;
wire AXI_08_DFI_RST_N_BUF_out;
wire AXI_08_RLAST_out;
wire AXI_08_RVALID_out;
wire AXI_08_WREADY_out;
wire AXI_09_ARREADY_out;
wire AXI_09_AWREADY_out;
wire AXI_09_BVALID_out;
wire AXI_09_DFI_CLK_BUF_out;
wire AXI_09_DFI_INIT_COMPLETE_out;
wire AXI_09_DFI_PHYUPD_REQ_out;
wire AXI_09_DFI_PHY_LP_STATE_out;
wire AXI_09_DFI_RST_N_BUF_out;
wire AXI_09_RLAST_out;
wire AXI_09_RVALID_out;
wire AXI_09_WREADY_out;
wire AXI_10_ARREADY_out;
wire AXI_10_AWREADY_out;
wire AXI_10_BVALID_out;
wire AXI_10_DFI_CLK_BUF_out;
wire AXI_10_DFI_INIT_COMPLETE_out;
wire AXI_10_DFI_PHYUPD_REQ_out;
wire AXI_10_DFI_PHY_LP_STATE_out;
wire AXI_10_DFI_RST_N_BUF_out;
wire AXI_10_RLAST_out;
wire AXI_10_RVALID_out;
wire AXI_10_WREADY_out;
wire AXI_11_ARREADY_out;
wire AXI_11_AWREADY_out;
wire AXI_11_BVALID_out;
wire AXI_11_DFI_CLK_BUF_out;
wire AXI_11_DFI_INIT_COMPLETE_out;
wire AXI_11_DFI_PHYUPD_REQ_out;
wire AXI_11_DFI_PHY_LP_STATE_out;
wire AXI_11_DFI_RST_N_BUF_out;
wire AXI_11_RLAST_out;
wire AXI_11_RVALID_out;
wire AXI_11_WREADY_out;
wire AXI_12_ARREADY_out;
wire AXI_12_AWREADY_out;
wire AXI_12_BVALID_out;
wire AXI_12_DFI_CLK_BUF_out;
wire AXI_12_DFI_INIT_COMPLETE_out;
wire AXI_12_DFI_PHYUPD_REQ_out;
wire AXI_12_DFI_PHY_LP_STATE_out;
wire AXI_12_DFI_RST_N_BUF_out;
wire AXI_12_RLAST_out;
wire AXI_12_RVALID_out;
wire AXI_12_WREADY_out;
wire AXI_13_ARREADY_out;
wire AXI_13_AWREADY_out;
wire AXI_13_BVALID_out;
wire AXI_13_DFI_CLK_BUF_out;
wire AXI_13_DFI_INIT_COMPLETE_out;
wire AXI_13_DFI_PHYUPD_REQ_out;
wire AXI_13_DFI_PHY_LP_STATE_out;
wire AXI_13_DFI_RST_N_BUF_out;
wire AXI_13_RLAST_out;
wire AXI_13_RVALID_out;
wire AXI_13_WREADY_out;
wire AXI_14_ARREADY_out;
wire AXI_14_AWREADY_out;
wire AXI_14_BVALID_out;
wire AXI_14_DFI_CLK_BUF_out;
wire AXI_14_DFI_INIT_COMPLETE_out;
wire AXI_14_DFI_PHYUPD_REQ_out;
wire AXI_14_DFI_PHY_LP_STATE_out;
wire AXI_14_DFI_RST_N_BUF_out;
wire AXI_14_RLAST_out;
wire AXI_14_RVALID_out;
wire AXI_14_WREADY_out;
wire AXI_15_ARREADY_out;
wire AXI_15_AWREADY_out;
wire AXI_15_BVALID_out;
wire AXI_15_DFI_CLK_BUF_out;
wire AXI_15_DFI_INIT_COMPLETE_out;
wire AXI_15_DFI_PHYUPD_REQ_out;
wire AXI_15_DFI_PHY_LP_STATE_out;
wire AXI_15_DFI_RST_N_BUF_out;
wire AXI_15_RLAST_out;
wire AXI_15_RVALID_out;
wire AXI_15_WREADY_out;
wire DRAM_0_STAT_CATTRIP_out;
wire [17:0] DBG_OUT_00_out;
wire [17:0] DBG_OUT_01_out;
wire [17:0] DBG_OUT_02_out;
wire [17:0] DBG_OUT_03_out;
wire [17:0] DBG_OUT_04_out;
wire [17:0] DBG_OUT_05_out;
wire [17:0] DBG_OUT_06_out;
wire [17:0] DBG_OUT_07_out;
wire [17:0] DBG_OUT_08_out;
wire [17:0] DBG_OUT_09_out;
wire [17:0] DBG_OUT_10_out;
wire [17:0] DBG_OUT_11_out;
wire [17:0] DBG_OUT_12_out;
wire [17:0] DBG_OUT_13_out;
wire [17:0] DBG_OUT_14_out;
wire [17:0] DBG_OUT_15_out;
wire [1:0] AXI_00_BRESP_out;
wire [1:0] AXI_00_DFI_AW_AERR_N_out;
wire [1:0] AXI_00_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_00_RRESP_out;
wire [1:0] AXI_01_BRESP_out;
wire [1:0] AXI_01_DFI_AW_AERR_N_out;
wire [1:0] AXI_01_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_01_RRESP_out;
wire [1:0] AXI_02_BRESP_out;
wire [1:0] AXI_02_DFI_AW_AERR_N_out;
wire [1:0] AXI_02_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_02_RRESP_out;
wire [1:0] AXI_03_BRESP_out;
wire [1:0] AXI_03_DFI_AW_AERR_N_out;
wire [1:0] AXI_03_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_03_RRESP_out;
wire [1:0] AXI_04_BRESP_out;
wire [1:0] AXI_04_DFI_AW_AERR_N_out;
wire [1:0] AXI_04_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_04_RRESP_out;
wire [1:0] AXI_05_BRESP_out;
wire [1:0] AXI_05_DFI_AW_AERR_N_out;
wire [1:0] AXI_05_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_05_RRESP_out;
wire [1:0] AXI_06_BRESP_out;
wire [1:0] AXI_06_DFI_AW_AERR_N_out;
wire [1:0] AXI_06_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_06_RRESP_out;
wire [1:0] AXI_07_BRESP_out;
wire [1:0] AXI_07_DFI_AW_AERR_N_out;
wire [1:0] AXI_07_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_07_RRESP_out;
wire [1:0] AXI_08_BRESP_out;
wire [1:0] AXI_08_DFI_AW_AERR_N_out;
wire [1:0] AXI_08_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_08_RRESP_out;
wire [1:0] AXI_09_BRESP_out;
wire [1:0] AXI_09_DFI_AW_AERR_N_out;
wire [1:0] AXI_09_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_09_RRESP_out;
wire [1:0] AXI_10_BRESP_out;
wire [1:0] AXI_10_DFI_AW_AERR_N_out;
wire [1:0] AXI_10_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_10_RRESP_out;
wire [1:0] AXI_11_BRESP_out;
wire [1:0] AXI_11_DFI_AW_AERR_N_out;
wire [1:0] AXI_11_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_11_RRESP_out;
wire [1:0] AXI_12_BRESP_out;
wire [1:0] AXI_12_DFI_AW_AERR_N_out;
wire [1:0] AXI_12_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_12_RRESP_out;
wire [1:0] AXI_13_BRESP_out;
wire [1:0] AXI_13_DFI_AW_AERR_N_out;
wire [1:0] AXI_13_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_13_RRESP_out;
wire [1:0] AXI_14_BRESP_out;
wire [1:0] AXI_14_DFI_AW_AERR_N_out;
wire [1:0] AXI_14_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_14_RRESP_out;
wire [1:0] AXI_15_BRESP_out;
wire [1:0] AXI_15_DFI_AW_AERR_N_out;
wire [1:0] AXI_15_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_15_RRESP_out;
wire [1:0] DLL_SCAN_OUT_00_out;
wire [1:0] IO_SCAN_OUT_00_out;
wire [1:0] MC_SCAN_OUT_00_out;
wire [1:0] MC_SCAN_OUT_01_out;
wire [1:0] MC_SCAN_OUT_02_out;
wire [1:0] MC_SCAN_OUT_03_out;
wire [1:0] MC_SCAN_OUT_04_out;
wire [1:0] MC_SCAN_OUT_05_out;
wire [1:0] MC_SCAN_OUT_06_out;
wire [1:0] MC_SCAN_OUT_07_out;
wire [1:0] PHY_SCAN_OUT_00_out;
wire [1:0] STATUS_00_out;
wire [1:0] STATUS_01_out;
wire [1:0] STATUS_02_out;
wire [1:0] STATUS_03_out;
wire [1:0] STATUS_04_out;
wire [1:0] STATUS_05_out;
wire [1:0] STATUS_06_out;
wire [1:0] STATUS_07_out;
wire [1:0] SW_SCAN_OUT_00_out;
wire [1:0] SW_SCAN_OUT_01_out;
wire [1:0] SW_SCAN_OUT_02_out;
wire [1:0] SW_SCAN_OUT_03_out;
wire [20:0] AXI_00_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_01_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_02_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_03_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_04_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_05_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_06_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_07_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_08_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_09_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_10_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_11_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_12_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_13_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_14_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_15_DFI_DW_RDDATA_DBI_out;
wire [255:0] AXI_00_RDATA_out;
wire [255:0] AXI_01_RDATA_out;
wire [255:0] AXI_02_RDATA_out;
wire [255:0] AXI_03_RDATA_out;
wire [255:0] AXI_04_RDATA_out;
wire [255:0] AXI_05_RDATA_out;
wire [255:0] AXI_06_RDATA_out;
wire [255:0] AXI_07_RDATA_out;
wire [255:0] AXI_08_RDATA_out;
wire [255:0] AXI_09_RDATA_out;
wire [255:0] AXI_10_RDATA_out;
wire [255:0] AXI_11_RDATA_out;
wire [255:0] AXI_12_RDATA_out;
wire [255:0] AXI_13_RDATA_out;
wire [255:0] AXI_14_RDATA_out;
wire [255:0] AXI_15_RDATA_out;
wire [2:0] DRAM_0_STAT_TEMP_out;
wire [31:0] APB_0_PRDATA_out;
wire [31:0] AXI_00_RDATA_PARITY_out;
wire [31:0] AXI_01_RDATA_PARITY_out;
wire [31:0] AXI_02_RDATA_PARITY_out;
wire [31:0] AXI_03_RDATA_PARITY_out;
wire [31:0] AXI_04_RDATA_PARITY_out;
wire [31:0] AXI_05_RDATA_PARITY_out;
wire [31:0] AXI_06_RDATA_PARITY_out;
wire [31:0] AXI_07_RDATA_PARITY_out;
wire [31:0] AXI_08_RDATA_PARITY_out;
wire [31:0] AXI_09_RDATA_PARITY_out;
wire [31:0] AXI_10_RDATA_PARITY_out;
wire [31:0] AXI_11_RDATA_PARITY_out;
wire [31:0] AXI_12_RDATA_PARITY_out;
wire [31:0] AXI_13_RDATA_PARITY_out;
wire [31:0] AXI_14_RDATA_PARITY_out;
wire [31:0] AXI_15_RDATA_PARITY_out;
wire [5:0] AXI_00_BID_out;
wire [5:0] AXI_00_MC_STATUS_out;
wire [5:0] AXI_00_RID_out;
wire [5:0] AXI_01_BID_out;
wire [5:0] AXI_01_RID_out;
wire [5:0] AXI_02_BID_out;
wire [5:0] AXI_02_MC_STATUS_out;
wire [5:0] AXI_02_RID_out;
wire [5:0] AXI_03_BID_out;
wire [5:0] AXI_03_RID_out;
wire [5:0] AXI_04_BID_out;
wire [5:0] AXI_04_MC_STATUS_out;
wire [5:0] AXI_04_RID_out;
wire [5:0] AXI_05_BID_out;
wire [5:0] AXI_05_RID_out;
wire [5:0] AXI_06_BID_out;
wire [5:0] AXI_06_MC_STATUS_out;
wire [5:0] AXI_06_RID_out;
wire [5:0] AXI_07_BID_out;
wire [5:0] AXI_07_RID_out;
wire [5:0] AXI_08_BID_out;
wire [5:0] AXI_08_MC_STATUS_out;
wire [5:0] AXI_08_RID_out;
wire [5:0] AXI_09_BID_out;
wire [5:0] AXI_09_RID_out;
wire [5:0] AXI_10_BID_out;
wire [5:0] AXI_10_MC_STATUS_out;
wire [5:0] AXI_10_RID_out;
wire [5:0] AXI_11_BID_out;
wire [5:0] AXI_11_RID_out;
wire [5:0] AXI_12_BID_out;
wire [5:0] AXI_12_MC_STATUS_out;
wire [5:0] AXI_12_RID_out;
wire [5:0] AXI_13_BID_out;
wire [5:0] AXI_13_RID_out;
wire [5:0] AXI_14_BID_out;
wire [5:0] AXI_14_MC_STATUS_out;
wire [5:0] AXI_14_RID_out;
wire [5:0] AXI_15_BID_out;
wire [5:0] AXI_15_RID_out;
wire [7:0] AXI_00_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_00_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_00_PHY_STATUS_out;
wire [7:0] AXI_01_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_01_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_02_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_02_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_02_PHY_STATUS_out;
wire [7:0] AXI_03_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_03_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_04_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_04_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_04_PHY_STATUS_out;
wire [7:0] AXI_05_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_05_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_06_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_06_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_06_PHY_STATUS_out;
wire [7:0] AXI_07_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_07_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_08_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_08_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_08_PHY_STATUS_out;
wire [7:0] AXI_09_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_09_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_10_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_10_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_10_PHY_STATUS_out;
wire [7:0] AXI_11_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_11_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_12_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_12_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_12_PHY_STATUS_out;
wire [7:0] AXI_13_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_13_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_14_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_14_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_14_PHY_STATUS_out;
wire [7:0] AXI_15_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_15_DFI_DW_RDDATA_DERR_out;
wire [7:0] BLI_SCAN_OUT_00_out;
wire [7:0] BLI_SCAN_OUT_01_out;
wire [7:0] BLI_SCAN_OUT_02_out;
wire [7:0] BLI_SCAN_OUT_03_out;
wire [7:0] BLI_SCAN_OUT_04_out;
wire [7:0] BLI_SCAN_OUT_05_out;
wire [7:0] BLI_SCAN_OUT_06_out;
wire [7:0] BLI_SCAN_OUT_07_out;
wire [7:0] BLI_SCAN_OUT_08_out;
wire [7:0] BLI_SCAN_OUT_09_out;
wire [7:0] BLI_SCAN_OUT_10_out;
wire [7:0] BLI_SCAN_OUT_11_out;
wire [7:0] BLI_SCAN_OUT_12_out;
wire [7:0] BLI_SCAN_OUT_13_out;
wire [7:0] BLI_SCAN_OUT_14_out;
wire [7:0] BLI_SCAN_OUT_15_out;
wire ANALOG_HBM_SEL_00_in;
wire APB_0_PCLK_in;
wire APB_0_PENABLE_in;
wire APB_0_PRESET_N_in;
wire APB_0_PSEL_in;
wire APB_0_PWRITE_in;
wire AXI_00_ACLK_in;
wire AXI_00_ARESET_N_in;
wire AXI_00_ARVALID_in;
wire AXI_00_AWVALID_in;
wire AXI_00_BREADY_in;
wire AXI_00_DFI_LP_PWR_X_REQ_in;
wire AXI_00_RREADY_in;
wire AXI_00_WLAST_in;
wire AXI_00_WVALID_in;
wire AXI_01_ACLK_in;
wire AXI_01_ARESET_N_in;
wire AXI_01_ARVALID_in;
wire AXI_01_AWVALID_in;
wire AXI_01_BREADY_in;
wire AXI_01_DFI_LP_PWR_X_REQ_in;
wire AXI_01_RREADY_in;
wire AXI_01_WLAST_in;
wire AXI_01_WVALID_in;
wire AXI_02_ACLK_in;
wire AXI_02_ARESET_N_in;
wire AXI_02_ARVALID_in;
wire AXI_02_AWVALID_in;
wire AXI_02_BREADY_in;
wire AXI_02_DFI_LP_PWR_X_REQ_in;
wire AXI_02_RREADY_in;
wire AXI_02_WLAST_in;
wire AXI_02_WVALID_in;
wire AXI_03_ACLK_in;
wire AXI_03_ARESET_N_in;
wire AXI_03_ARVALID_in;
wire AXI_03_AWVALID_in;
wire AXI_03_BREADY_in;
wire AXI_03_DFI_LP_PWR_X_REQ_in;
wire AXI_03_RREADY_in;
wire AXI_03_WLAST_in;
wire AXI_03_WVALID_in;
wire AXI_04_ACLK_in;
wire AXI_04_ARESET_N_in;
wire AXI_04_ARVALID_in;
wire AXI_04_AWVALID_in;
wire AXI_04_BREADY_in;
wire AXI_04_DFI_LP_PWR_X_REQ_in;
wire AXI_04_RREADY_in;
wire AXI_04_WLAST_in;
wire AXI_04_WVALID_in;
wire AXI_05_ACLK_in;
wire AXI_05_ARESET_N_in;
wire AXI_05_ARVALID_in;
wire AXI_05_AWVALID_in;
wire AXI_05_BREADY_in;
wire AXI_05_DFI_LP_PWR_X_REQ_in;
wire AXI_05_RREADY_in;
wire AXI_05_WLAST_in;
wire AXI_05_WVALID_in;
wire AXI_06_ACLK_in;
wire AXI_06_ARESET_N_in;
wire AXI_06_ARVALID_in;
wire AXI_06_AWVALID_in;
wire AXI_06_BREADY_in;
wire AXI_06_DFI_LP_PWR_X_REQ_in;
wire AXI_06_RREADY_in;
wire AXI_06_WLAST_in;
wire AXI_06_WVALID_in;
wire AXI_07_ACLK_in;
wire AXI_07_ARESET_N_in;
wire AXI_07_ARVALID_in;
wire AXI_07_AWVALID_in;
wire AXI_07_BREADY_in;
wire AXI_07_DFI_LP_PWR_X_REQ_in;
wire AXI_07_RREADY_in;
wire AXI_07_WLAST_in;
wire AXI_07_WVALID_in;
wire AXI_08_ACLK_in;
wire AXI_08_ARESET_N_in;
wire AXI_08_ARVALID_in;
wire AXI_08_AWVALID_in;
wire AXI_08_BREADY_in;
wire AXI_08_DFI_LP_PWR_X_REQ_in;
wire AXI_08_RREADY_in;
wire AXI_08_WLAST_in;
wire AXI_08_WVALID_in;
wire AXI_09_ACLK_in;
wire AXI_09_ARESET_N_in;
wire AXI_09_ARVALID_in;
wire AXI_09_AWVALID_in;
wire AXI_09_BREADY_in;
wire AXI_09_DFI_LP_PWR_X_REQ_in;
wire AXI_09_RREADY_in;
wire AXI_09_WLAST_in;
wire AXI_09_WVALID_in;
wire AXI_10_ACLK_in;
wire AXI_10_ARESET_N_in;
wire AXI_10_ARVALID_in;
wire AXI_10_AWVALID_in;
wire AXI_10_BREADY_in;
wire AXI_10_DFI_LP_PWR_X_REQ_in;
wire AXI_10_RREADY_in;
wire AXI_10_WLAST_in;
wire AXI_10_WVALID_in;
wire AXI_11_ACLK_in;
wire AXI_11_ARESET_N_in;
wire AXI_11_ARVALID_in;
wire AXI_11_AWVALID_in;
wire AXI_11_BREADY_in;
wire AXI_11_DFI_LP_PWR_X_REQ_in;
wire AXI_11_RREADY_in;
wire AXI_11_WLAST_in;
wire AXI_11_WVALID_in;
wire AXI_12_ACLK_in;
wire AXI_12_ARESET_N_in;
wire AXI_12_ARVALID_in;
wire AXI_12_AWVALID_in;
wire AXI_12_BREADY_in;
wire AXI_12_DFI_LP_PWR_X_REQ_in;
wire AXI_12_RREADY_in;
wire AXI_12_WLAST_in;
wire AXI_12_WVALID_in;
wire AXI_13_ACLK_in;
wire AXI_13_ARESET_N_in;
wire AXI_13_ARVALID_in;
wire AXI_13_AWVALID_in;
wire AXI_13_BREADY_in;
wire AXI_13_DFI_LP_PWR_X_REQ_in;
wire AXI_13_RREADY_in;
wire AXI_13_WLAST_in;
wire AXI_13_WVALID_in;
wire AXI_14_ACLK_in;
wire AXI_14_ARESET_N_in;
wire AXI_14_ARVALID_in;
wire AXI_14_AWVALID_in;
wire AXI_14_BREADY_in;
wire AXI_14_DFI_LP_PWR_X_REQ_in;
wire AXI_14_RREADY_in;
wire AXI_14_WLAST_in;
wire AXI_14_WVALID_in;
wire AXI_15_ACLK_in;
wire AXI_15_ARESET_N_in;
wire AXI_15_ARVALID_in;
wire AXI_15_AWVALID_in;
wire AXI_15_BREADY_in;
wire AXI_15_DFI_LP_PWR_X_REQ_in;
wire AXI_15_RREADY_in;
wire AXI_15_WLAST_in;
wire AXI_15_WVALID_in;
wire BLI_SCAN_ENABLE_00_in;
wire BLI_SCAN_ENABLE_01_in;
wire BLI_SCAN_ENABLE_02_in;
wire BLI_SCAN_ENABLE_03_in;
wire BLI_SCAN_ENABLE_04_in;
wire BLI_SCAN_ENABLE_05_in;
wire BLI_SCAN_ENABLE_06_in;
wire BLI_SCAN_ENABLE_07_in;
wire BLI_SCAN_ENABLE_08_in;
wire BLI_SCAN_ENABLE_09_in;
wire BLI_SCAN_ENABLE_10_in;
wire BLI_SCAN_ENABLE_11_in;
wire BLI_SCAN_ENABLE_12_in;
wire BLI_SCAN_ENABLE_13_in;
wire BLI_SCAN_ENABLE_14_in;
wire BLI_SCAN_ENABLE_15_in;
wire BSCAN_DRCK_in;
wire BSCAN_TCK_in;
wire DLL_SCAN_CK_00_in;
wire DLL_SCAN_ENABLE_00_in;
wire DLL_SCAN_MODE_00_in;
wire DLL_SCAN_RST_N_00_in;
wire HBM_REF_CLK_in;
wire IO_SCAN_CK_00_in;
wire IO_SCAN_ENABLE_00_in;
wire IO_SCAN_MODE_00_in;
wire IO_SCAN_RST_N_00_in;
wire MBIST_EN_00_in;
wire MBIST_EN_01_in;
wire MBIST_EN_02_in;
wire MBIST_EN_03_in;
wire MBIST_EN_04_in;
wire MBIST_EN_05_in;
wire MBIST_EN_06_in;
wire MBIST_EN_07_in;
wire MC_SCAN_CK_00_in;
wire MC_SCAN_CK_01_in;
wire MC_SCAN_CK_02_in;
wire MC_SCAN_CK_03_in;
wire MC_SCAN_CK_04_in;
wire MC_SCAN_CK_05_in;
wire MC_SCAN_CK_06_in;
wire MC_SCAN_CK_07_in;
wire MC_SCAN_ENABLE_00_in;
wire MC_SCAN_ENABLE_01_in;
wire MC_SCAN_ENABLE_02_in;
wire MC_SCAN_ENABLE_03_in;
wire MC_SCAN_ENABLE_04_in;
wire MC_SCAN_ENABLE_05_in;
wire MC_SCAN_ENABLE_06_in;
wire MC_SCAN_ENABLE_07_in;
wire MC_SCAN_MODE_00_in;
wire MC_SCAN_MODE_01_in;
wire MC_SCAN_MODE_02_in;
wire MC_SCAN_MODE_03_in;
wire MC_SCAN_MODE_04_in;
wire MC_SCAN_MODE_05_in;
wire MC_SCAN_MODE_06_in;
wire MC_SCAN_MODE_07_in;
wire MC_SCAN_RST_N_00_in;
wire MC_SCAN_RST_N_01_in;
wire MC_SCAN_RST_N_02_in;
wire MC_SCAN_RST_N_03_in;
wire MC_SCAN_RST_N_04_in;
wire MC_SCAN_RST_N_05_in;
wire MC_SCAN_RST_N_06_in;
wire MC_SCAN_RST_N_07_in;
wire PHY_SCAN_CK_00_in;
wire PHY_SCAN_ENABLE_00_in;
wire PHY_SCAN_MODE_00_in;
wire PHY_SCAN_RST_N_00_in;
wire SW_SCAN_CK_00_in;
wire SW_SCAN_ENABLE_00_in;
wire SW_SCAN_MODE_00_in;
wire SW_SCAN_RST_N_00_in;
wire [1:0] AXI_00_ARBURST_in;
wire [1:0] AXI_00_AWBURST_in;
wire [1:0] AXI_01_ARBURST_in;
wire [1:0] AXI_01_AWBURST_in;
wire [1:0] AXI_02_ARBURST_in;
wire [1:0] AXI_02_AWBURST_in;
wire [1:0] AXI_03_ARBURST_in;
wire [1:0] AXI_03_AWBURST_in;
wire [1:0] AXI_04_ARBURST_in;
wire [1:0] AXI_04_AWBURST_in;
wire [1:0] AXI_05_ARBURST_in;
wire [1:0] AXI_05_AWBURST_in;
wire [1:0] AXI_06_ARBURST_in;
wire [1:0] AXI_06_AWBURST_in;
wire [1:0] AXI_07_ARBURST_in;
wire [1:0] AXI_07_AWBURST_in;
wire [1:0] AXI_08_ARBURST_in;
wire [1:0] AXI_08_AWBURST_in;
wire [1:0] AXI_09_ARBURST_in;
wire [1:0] AXI_09_AWBURST_in;
wire [1:0] AXI_10_ARBURST_in;
wire [1:0] AXI_10_AWBURST_in;
wire [1:0] AXI_11_ARBURST_in;
wire [1:0] AXI_11_AWBURST_in;
wire [1:0] AXI_12_ARBURST_in;
wire [1:0] AXI_12_AWBURST_in;
wire [1:0] AXI_13_ARBURST_in;
wire [1:0] AXI_13_AWBURST_in;
wire [1:0] AXI_14_ARBURST_in;
wire [1:0] AXI_14_AWBURST_in;
wire [1:0] AXI_15_ARBURST_in;
wire [1:0] AXI_15_AWBURST_in;
wire [1:0] DLL_SCAN_IN_00_in;
wire [1:0] IO_SCAN_IN_00_in;
wire [1:0] MC_SCAN_IN_00_in;
wire [1:0] MC_SCAN_IN_01_in;
wire [1:0] MC_SCAN_IN_02_in;
wire [1:0] MC_SCAN_IN_03_in;
wire [1:0] MC_SCAN_IN_04_in;
wire [1:0] MC_SCAN_IN_05_in;
wire [1:0] MC_SCAN_IN_06_in;
wire [1:0] MC_SCAN_IN_07_in;
wire [1:0] PHY_SCAN_IN_00_in;
wire [1:0] SW_SCAN_IN_00_in;
wire [1:0] SW_SCAN_IN_01_in;
wire [1:0] SW_SCAN_IN_02_in;
wire [1:0] SW_SCAN_IN_03_in;
wire [21:0] APB_0_PADDR_in;
wire [23:0] DBG_IN_00_in;
wire [23:0] DBG_IN_01_in;
wire [23:0] DBG_IN_02_in;
wire [23:0] DBG_IN_03_in;
wire [23:0] DBG_IN_04_in;
wire [23:0] DBG_IN_05_in;
wire [23:0] DBG_IN_06_in;
wire [23:0] DBG_IN_07_in;
wire [23:0] DBG_IN_08_in;
wire [23:0] DBG_IN_09_in;
wire [23:0] DBG_IN_10_in;
wire [23:0] DBG_IN_11_in;
wire [23:0] DBG_IN_12_in;
wire [23:0] DBG_IN_13_in;
wire [23:0] DBG_IN_14_in;
wire [23:0] DBG_IN_15_in;
wire [255:0] AXI_00_WDATA_in;
wire [255:0] AXI_01_WDATA_in;
wire [255:0] AXI_02_WDATA_in;
wire [255:0] AXI_03_WDATA_in;
wire [255:0] AXI_04_WDATA_in;
wire [255:0] AXI_05_WDATA_in;
wire [255:0] AXI_06_WDATA_in;
wire [255:0] AXI_07_WDATA_in;
wire [255:0] AXI_08_WDATA_in;
wire [255:0] AXI_09_WDATA_in;
wire [255:0] AXI_10_WDATA_in;
wire [255:0] AXI_11_WDATA_in;
wire [255:0] AXI_12_WDATA_in;
wire [255:0] AXI_13_WDATA_in;
wire [255:0] AXI_14_WDATA_in;
wire [255:0] AXI_15_WDATA_in;
wire [2:0] AXI_00_ARSIZE_in;
wire [2:0] AXI_00_AWSIZE_in;
wire [2:0] AXI_01_ARSIZE_in;
wire [2:0] AXI_01_AWSIZE_in;
wire [2:0] AXI_02_ARSIZE_in;
wire [2:0] AXI_02_AWSIZE_in;
wire [2:0] AXI_03_ARSIZE_in;
wire [2:0] AXI_03_AWSIZE_in;
wire [2:0] AXI_04_ARSIZE_in;
wire [2:0] AXI_04_AWSIZE_in;
wire [2:0] AXI_05_ARSIZE_in;
wire [2:0] AXI_05_AWSIZE_in;
wire [2:0] AXI_06_ARSIZE_in;
wire [2:0] AXI_06_AWSIZE_in;
wire [2:0] AXI_07_ARSIZE_in;
wire [2:0] AXI_07_AWSIZE_in;
wire [2:0] AXI_08_ARSIZE_in;
wire [2:0] AXI_08_AWSIZE_in;
wire [2:0] AXI_09_ARSIZE_in;
wire [2:0] AXI_09_AWSIZE_in;
wire [2:0] AXI_10_ARSIZE_in;
wire [2:0] AXI_10_AWSIZE_in;
wire [2:0] AXI_11_ARSIZE_in;
wire [2:0] AXI_11_AWSIZE_in;
wire [2:0] AXI_12_ARSIZE_in;
wire [2:0] AXI_12_AWSIZE_in;
wire [2:0] AXI_13_ARSIZE_in;
wire [2:0] AXI_13_AWSIZE_in;
wire [2:0] AXI_14_ARSIZE_in;
wire [2:0] AXI_14_AWSIZE_in;
wire [2:0] AXI_15_ARSIZE_in;
wire [2:0] AXI_15_AWSIZE_in;
wire [31:0] APB_0_PWDATA_in;
wire [31:0] AXI_00_WDATA_PARITY_in;
wire [31:0] AXI_00_WSTRB_in;
wire [31:0] AXI_01_WDATA_PARITY_in;
wire [31:0] AXI_01_WSTRB_in;
wire [31:0] AXI_02_WDATA_PARITY_in;
wire [31:0] AXI_02_WSTRB_in;
wire [31:0] AXI_03_WDATA_PARITY_in;
wire [31:0] AXI_03_WSTRB_in;
wire [31:0] AXI_04_WDATA_PARITY_in;
wire [31:0] AXI_04_WSTRB_in;
wire [31:0] AXI_05_WDATA_PARITY_in;
wire [31:0] AXI_05_WSTRB_in;
wire [31:0] AXI_06_WDATA_PARITY_in;
wire [31:0] AXI_06_WSTRB_in;
wire [31:0] AXI_07_WDATA_PARITY_in;
wire [31:0] AXI_07_WSTRB_in;
wire [31:0] AXI_08_WDATA_PARITY_in;
wire [31:0] AXI_08_WSTRB_in;
wire [31:0] AXI_09_WDATA_PARITY_in;
wire [31:0] AXI_09_WSTRB_in;
wire [31:0] AXI_10_WDATA_PARITY_in;
wire [31:0] AXI_10_WSTRB_in;
wire [31:0] AXI_11_WDATA_PARITY_in;
wire [31:0] AXI_11_WSTRB_in;
wire [31:0] AXI_12_WDATA_PARITY_in;
wire [31:0] AXI_12_WSTRB_in;
wire [31:0] AXI_13_WDATA_PARITY_in;
wire [31:0] AXI_13_WSTRB_in;
wire [31:0] AXI_14_WDATA_PARITY_in;
wire [31:0] AXI_14_WSTRB_in;
wire [31:0] AXI_15_WDATA_PARITY_in;
wire [31:0] AXI_15_WSTRB_in;
wire [36:0] AXI_00_ARADDR_in;
wire [36:0] AXI_00_AWADDR_in;
wire [36:0] AXI_01_ARADDR_in;
wire [36:0] AXI_01_AWADDR_in;
wire [36:0] AXI_02_ARADDR_in;
wire [36:0] AXI_02_AWADDR_in;
wire [36:0] AXI_03_ARADDR_in;
wire [36:0] AXI_03_AWADDR_in;
wire [36:0] AXI_04_ARADDR_in;
wire [36:0] AXI_04_AWADDR_in;
wire [36:0] AXI_05_ARADDR_in;
wire [36:0] AXI_05_AWADDR_in;
wire [36:0] AXI_06_ARADDR_in;
wire [36:0] AXI_06_AWADDR_in;
wire [36:0] AXI_07_ARADDR_in;
wire [36:0] AXI_07_AWADDR_in;
wire [36:0] AXI_08_ARADDR_in;
wire [36:0] AXI_08_AWADDR_in;
wire [36:0] AXI_09_ARADDR_in;
wire [36:0] AXI_09_AWADDR_in;
wire [36:0] AXI_10_ARADDR_in;
wire [36:0] AXI_10_AWADDR_in;
wire [36:0] AXI_11_ARADDR_in;
wire [36:0] AXI_11_AWADDR_in;
wire [36:0] AXI_12_ARADDR_in;
wire [36:0] AXI_12_AWADDR_in;
wire [36:0] AXI_13_ARADDR_in;
wire [36:0] AXI_13_AWADDR_in;
wire [36:0] AXI_14_ARADDR_in;
wire [36:0] AXI_14_AWADDR_in;
wire [36:0] AXI_15_ARADDR_in;
wire [36:0] AXI_15_AWADDR_in;
wire [3:0] AXI_00_ARLEN_in;
wire [3:0] AXI_00_AWLEN_in;
wire [3:0] AXI_01_ARLEN_in;
wire [3:0] AXI_01_AWLEN_in;
wire [3:0] AXI_02_ARLEN_in;
wire [3:0] AXI_02_AWLEN_in;
wire [3:0] AXI_03_ARLEN_in;
wire [3:0] AXI_03_AWLEN_in;
wire [3:0] AXI_04_ARLEN_in;
wire [3:0] AXI_04_AWLEN_in;
wire [3:0] AXI_05_ARLEN_in;
wire [3:0] AXI_05_AWLEN_in;
wire [3:0] AXI_06_ARLEN_in;
wire [3:0] AXI_06_AWLEN_in;
wire [3:0] AXI_07_ARLEN_in;
wire [3:0] AXI_07_AWLEN_in;
wire [3:0] AXI_08_ARLEN_in;
wire [3:0] AXI_08_AWLEN_in;
wire [3:0] AXI_09_ARLEN_in;
wire [3:0] AXI_09_AWLEN_in;
wire [3:0] AXI_10_ARLEN_in;
wire [3:0] AXI_10_AWLEN_in;
wire [3:0] AXI_11_ARLEN_in;
wire [3:0] AXI_11_AWLEN_in;
wire [3:0] AXI_12_ARLEN_in;
wire [3:0] AXI_12_AWLEN_in;
wire [3:0] AXI_13_ARLEN_in;
wire [3:0] AXI_13_AWLEN_in;
wire [3:0] AXI_14_ARLEN_in;
wire [3:0] AXI_14_AWLEN_in;
wire [3:0] AXI_15_ARLEN_in;
wire [3:0] AXI_15_AWLEN_in;
wire [5:0] AXI_00_ARID_in;
wire [5:0] AXI_00_AWID_in;
wire [5:0] AXI_01_ARID_in;
wire [5:0] AXI_01_AWID_in;
wire [5:0] AXI_02_ARID_in;
wire [5:0] AXI_02_AWID_in;
wire [5:0] AXI_03_ARID_in;
wire [5:0] AXI_03_AWID_in;
wire [5:0] AXI_04_ARID_in;
wire [5:0] AXI_04_AWID_in;
wire [5:0] AXI_05_ARID_in;
wire [5:0] AXI_05_AWID_in;
wire [5:0] AXI_06_ARID_in;
wire [5:0] AXI_06_AWID_in;
wire [5:0] AXI_07_ARID_in;
wire [5:0] AXI_07_AWID_in;
wire [5:0] AXI_08_ARID_in;
wire [5:0] AXI_08_AWID_in;
wire [5:0] AXI_09_ARID_in;
wire [5:0] AXI_09_AWID_in;
wire [5:0] AXI_10_ARID_in;
wire [5:0] AXI_10_AWID_in;
wire [5:0] AXI_11_ARID_in;
wire [5:0] AXI_11_AWID_in;
wire [5:0] AXI_12_ARID_in;
wire [5:0] AXI_12_AWID_in;
wire [5:0] AXI_13_ARID_in;
wire [5:0] AXI_13_AWID_in;
wire [5:0] AXI_14_ARID_in;
wire [5:0] AXI_14_AWID_in;
wire [5:0] AXI_15_ARID_in;
wire [5:0] AXI_15_AWID_in;
wire [7:0] BLI_SCAN_IN_00_in;
wire [7:0] BLI_SCAN_IN_01_in;
wire [7:0] BLI_SCAN_IN_02_in;
wire [7:0] BLI_SCAN_IN_03_in;
wire [7:0] BLI_SCAN_IN_04_in;
wire [7:0] BLI_SCAN_IN_05_in;
wire [7:0] BLI_SCAN_IN_06_in;
wire [7:0] BLI_SCAN_IN_07_in;
wire [7:0] BLI_SCAN_IN_08_in;
wire [7:0] BLI_SCAN_IN_09_in;
wire [7:0] BLI_SCAN_IN_10_in;
wire [7:0] BLI_SCAN_IN_11_in;
wire [7:0] BLI_SCAN_IN_12_in;
wire [7:0] BLI_SCAN_IN_13_in;
wire [7:0] BLI_SCAN_IN_14_in;
wire [7:0] BLI_SCAN_IN_15_in;
assign APB_0_PRDATA = APB_0_PRDATA_out;
assign APB_0_PREADY = APB_0_PREADY_out;
assign APB_0_PSLVERR = APB_0_PSLVERR_out;
assign AXI_00_ARREADY = AXI_00_ARREADY_out;
assign AXI_00_AWREADY = AXI_00_AWREADY_out;
assign AXI_00_BID = AXI_00_BID_out;
assign AXI_00_BRESP = AXI_00_BRESP_out;
assign AXI_00_BVALID = AXI_00_BVALID_out;
assign AXI_00_DFI_AW_AERR_N = AXI_00_DFI_AW_AERR_N_out;
assign AXI_00_DFI_CLK_BUF = AXI_00_DFI_CLK_BUF_out;
assign AXI_00_DFI_DBI_BYTE_DISABLE = AXI_00_DFI_DBI_BYTE_DISABLE_out;
assign AXI_00_DFI_DW_RDDATA_DBI = AXI_00_DFI_DW_RDDATA_DBI_out;
assign AXI_00_DFI_DW_RDDATA_DERR = AXI_00_DFI_DW_RDDATA_DERR_out;
assign AXI_00_DFI_DW_RDDATA_VALID = AXI_00_DFI_DW_RDDATA_VALID_out;
assign AXI_00_DFI_INIT_COMPLETE = AXI_00_DFI_INIT_COMPLETE_out;
assign AXI_00_DFI_PHYUPD_REQ = AXI_00_DFI_PHYUPD_REQ_out;
assign AXI_00_DFI_PHY_LP_STATE = AXI_00_DFI_PHY_LP_STATE_out;
assign AXI_00_DFI_RST_N_BUF = AXI_00_DFI_RST_N_BUF_out;
assign AXI_00_MC_STATUS = AXI_00_MC_STATUS_out;
assign AXI_00_PHY_STATUS = AXI_00_PHY_STATUS_out;
assign AXI_00_RDATA = AXI_00_RDATA_out;
assign AXI_00_RDATA_PARITY = AXI_00_RDATA_PARITY_out;
assign AXI_00_RID = AXI_00_RID_out;
assign AXI_00_RLAST = AXI_00_RLAST_out;
assign AXI_00_RRESP = AXI_00_RRESP_out;
assign AXI_00_RVALID = AXI_00_RVALID_out;
assign AXI_00_WREADY = AXI_00_WREADY_out;
assign AXI_01_ARREADY = AXI_01_ARREADY_out;
assign AXI_01_AWREADY = AXI_01_AWREADY_out;
assign AXI_01_BID = AXI_01_BID_out;
assign AXI_01_BRESP = AXI_01_BRESP_out;
assign AXI_01_BVALID = AXI_01_BVALID_out;
assign AXI_01_DFI_AW_AERR_N = AXI_01_DFI_AW_AERR_N_out;
assign AXI_01_DFI_CLK_BUF = AXI_01_DFI_CLK_BUF_out;
assign AXI_01_DFI_DBI_BYTE_DISABLE = AXI_01_DFI_DBI_BYTE_DISABLE_out;
assign AXI_01_DFI_DW_RDDATA_DBI = AXI_01_DFI_DW_RDDATA_DBI_out;
assign AXI_01_DFI_DW_RDDATA_DERR = AXI_01_DFI_DW_RDDATA_DERR_out;
assign AXI_01_DFI_DW_RDDATA_VALID = AXI_01_DFI_DW_RDDATA_VALID_out;
assign AXI_01_DFI_INIT_COMPLETE = AXI_01_DFI_INIT_COMPLETE_out;
assign AXI_01_DFI_PHYUPD_REQ = AXI_01_DFI_PHYUPD_REQ_out;
assign AXI_01_DFI_PHY_LP_STATE = AXI_01_DFI_PHY_LP_STATE_out;
assign AXI_01_DFI_RST_N_BUF = AXI_01_DFI_RST_N_BUF_out;
assign AXI_01_RDATA = AXI_01_RDATA_out;
assign AXI_01_RDATA_PARITY = AXI_01_RDATA_PARITY_out;
assign AXI_01_RID = AXI_01_RID_out;
assign AXI_01_RLAST = AXI_01_RLAST_out;
assign AXI_01_RRESP = AXI_01_RRESP_out;
assign AXI_01_RVALID = AXI_01_RVALID_out;
assign AXI_01_WREADY = AXI_01_WREADY_out;
assign AXI_02_ARREADY = AXI_02_ARREADY_out;
assign AXI_02_AWREADY = AXI_02_AWREADY_out;
assign AXI_02_BID = AXI_02_BID_out;
assign AXI_02_BRESP = AXI_02_BRESP_out;
assign AXI_02_BVALID = AXI_02_BVALID_out;
assign AXI_02_DFI_AW_AERR_N = AXI_02_DFI_AW_AERR_N_out;
assign AXI_02_DFI_CLK_BUF = AXI_02_DFI_CLK_BUF_out;
assign AXI_02_DFI_DBI_BYTE_DISABLE = AXI_02_DFI_DBI_BYTE_DISABLE_out;
assign AXI_02_DFI_DW_RDDATA_DBI = AXI_02_DFI_DW_RDDATA_DBI_out;
assign AXI_02_DFI_DW_RDDATA_DERR = AXI_02_DFI_DW_RDDATA_DERR_out;
assign AXI_02_DFI_DW_RDDATA_VALID = AXI_02_DFI_DW_RDDATA_VALID_out;
assign AXI_02_DFI_INIT_COMPLETE = AXI_02_DFI_INIT_COMPLETE_out;
assign AXI_02_DFI_PHYUPD_REQ = AXI_02_DFI_PHYUPD_REQ_out;
assign AXI_02_DFI_PHY_LP_STATE = AXI_02_DFI_PHY_LP_STATE_out;
assign AXI_02_DFI_RST_N_BUF = AXI_02_DFI_RST_N_BUF_out;
assign AXI_02_MC_STATUS = AXI_02_MC_STATUS_out;
assign AXI_02_PHY_STATUS = AXI_02_PHY_STATUS_out;
assign AXI_02_RDATA = AXI_02_RDATA_out;
assign AXI_02_RDATA_PARITY = AXI_02_RDATA_PARITY_out;
assign AXI_02_RID = AXI_02_RID_out;
assign AXI_02_RLAST = AXI_02_RLAST_out;
assign AXI_02_RRESP = AXI_02_RRESP_out;
assign AXI_02_RVALID = AXI_02_RVALID_out;
assign AXI_02_WREADY = AXI_02_WREADY_out;
assign AXI_03_ARREADY = AXI_03_ARREADY_out;
assign AXI_03_AWREADY = AXI_03_AWREADY_out;
assign AXI_03_BID = AXI_03_BID_out;
assign AXI_03_BRESP = AXI_03_BRESP_out;
assign AXI_03_BVALID = AXI_03_BVALID_out;
assign AXI_03_DFI_AW_AERR_N = AXI_03_DFI_AW_AERR_N_out;
assign AXI_03_DFI_CLK_BUF = AXI_03_DFI_CLK_BUF_out;
assign AXI_03_DFI_DBI_BYTE_DISABLE = AXI_03_DFI_DBI_BYTE_DISABLE_out;
assign AXI_03_DFI_DW_RDDATA_DBI = AXI_03_DFI_DW_RDDATA_DBI_out;
assign AXI_03_DFI_DW_RDDATA_DERR = AXI_03_DFI_DW_RDDATA_DERR_out;
assign AXI_03_DFI_DW_RDDATA_VALID = AXI_03_DFI_DW_RDDATA_VALID_out;
assign AXI_03_DFI_INIT_COMPLETE = AXI_03_DFI_INIT_COMPLETE_out;
assign AXI_03_DFI_PHYUPD_REQ = AXI_03_DFI_PHYUPD_REQ_out;
assign AXI_03_DFI_PHY_LP_STATE = AXI_03_DFI_PHY_LP_STATE_out;
assign AXI_03_DFI_RST_N_BUF = AXI_03_DFI_RST_N_BUF_out;
assign AXI_03_RDATA = AXI_03_RDATA_out;
assign AXI_03_RDATA_PARITY = AXI_03_RDATA_PARITY_out;
assign AXI_03_RID = AXI_03_RID_out;
assign AXI_03_RLAST = AXI_03_RLAST_out;
assign AXI_03_RRESP = AXI_03_RRESP_out;
assign AXI_03_RVALID = AXI_03_RVALID_out;
assign AXI_03_WREADY = AXI_03_WREADY_out;
assign AXI_04_ARREADY = AXI_04_ARREADY_out;
assign AXI_04_AWREADY = AXI_04_AWREADY_out;
assign AXI_04_BID = AXI_04_BID_out;
assign AXI_04_BRESP = AXI_04_BRESP_out;
assign AXI_04_BVALID = AXI_04_BVALID_out;
assign AXI_04_DFI_AW_AERR_N = AXI_04_DFI_AW_AERR_N_out;
assign AXI_04_DFI_CLK_BUF = AXI_04_DFI_CLK_BUF_out;
assign AXI_04_DFI_DBI_BYTE_DISABLE = AXI_04_DFI_DBI_BYTE_DISABLE_out;
assign AXI_04_DFI_DW_RDDATA_DBI = AXI_04_DFI_DW_RDDATA_DBI_out;
assign AXI_04_DFI_DW_RDDATA_DERR = AXI_04_DFI_DW_RDDATA_DERR_out;
assign AXI_04_DFI_DW_RDDATA_VALID = AXI_04_DFI_DW_RDDATA_VALID_out;
assign AXI_04_DFI_INIT_COMPLETE = AXI_04_DFI_INIT_COMPLETE_out;
assign AXI_04_DFI_PHYUPD_REQ = AXI_04_DFI_PHYUPD_REQ_out;
assign AXI_04_DFI_PHY_LP_STATE = AXI_04_DFI_PHY_LP_STATE_out;
assign AXI_04_DFI_RST_N_BUF = AXI_04_DFI_RST_N_BUF_out;
assign AXI_04_MC_STATUS = AXI_04_MC_STATUS_out;
assign AXI_04_PHY_STATUS = AXI_04_PHY_STATUS_out;
assign AXI_04_RDATA = AXI_04_RDATA_out;
assign AXI_04_RDATA_PARITY = AXI_04_RDATA_PARITY_out;
assign AXI_04_RID = AXI_04_RID_out;
assign AXI_04_RLAST = AXI_04_RLAST_out;
assign AXI_04_RRESP = AXI_04_RRESP_out;
assign AXI_04_RVALID = AXI_04_RVALID_out;
assign AXI_04_WREADY = AXI_04_WREADY_out;
assign AXI_05_ARREADY = AXI_05_ARREADY_out;
assign AXI_05_AWREADY = AXI_05_AWREADY_out;
assign AXI_05_BID = AXI_05_BID_out;
assign AXI_05_BRESP = AXI_05_BRESP_out;
assign AXI_05_BVALID = AXI_05_BVALID_out;
assign AXI_05_DFI_AW_AERR_N = AXI_05_DFI_AW_AERR_N_out;
assign AXI_05_DFI_CLK_BUF = AXI_05_DFI_CLK_BUF_out;
assign AXI_05_DFI_DBI_BYTE_DISABLE = AXI_05_DFI_DBI_BYTE_DISABLE_out;
assign AXI_05_DFI_DW_RDDATA_DBI = AXI_05_DFI_DW_RDDATA_DBI_out;
assign AXI_05_DFI_DW_RDDATA_DERR = AXI_05_DFI_DW_RDDATA_DERR_out;
assign AXI_05_DFI_DW_RDDATA_VALID = AXI_05_DFI_DW_RDDATA_VALID_out;
assign AXI_05_DFI_INIT_COMPLETE = AXI_05_DFI_INIT_COMPLETE_out;
assign AXI_05_DFI_PHYUPD_REQ = AXI_05_DFI_PHYUPD_REQ_out;
assign AXI_05_DFI_PHY_LP_STATE = AXI_05_DFI_PHY_LP_STATE_out;
assign AXI_05_DFI_RST_N_BUF = AXI_05_DFI_RST_N_BUF_out;
assign AXI_05_RDATA = AXI_05_RDATA_out;
assign AXI_05_RDATA_PARITY = AXI_05_RDATA_PARITY_out;
assign AXI_05_RID = AXI_05_RID_out;
assign AXI_05_RLAST = AXI_05_RLAST_out;
assign AXI_05_RRESP = AXI_05_RRESP_out;
assign AXI_05_RVALID = AXI_05_RVALID_out;
assign AXI_05_WREADY = AXI_05_WREADY_out;
assign AXI_06_ARREADY = AXI_06_ARREADY_out;
assign AXI_06_AWREADY = AXI_06_AWREADY_out;
assign AXI_06_BID = AXI_06_BID_out;
assign AXI_06_BRESP = AXI_06_BRESP_out;
assign AXI_06_BVALID = AXI_06_BVALID_out;
assign AXI_06_DFI_AW_AERR_N = AXI_06_DFI_AW_AERR_N_out;
assign AXI_06_DFI_CLK_BUF = AXI_06_DFI_CLK_BUF_out;
assign AXI_06_DFI_DBI_BYTE_DISABLE = AXI_06_DFI_DBI_BYTE_DISABLE_out;
assign AXI_06_DFI_DW_RDDATA_DBI = AXI_06_DFI_DW_RDDATA_DBI_out;
assign AXI_06_DFI_DW_RDDATA_DERR = AXI_06_DFI_DW_RDDATA_DERR_out;
assign AXI_06_DFI_DW_RDDATA_VALID = AXI_06_DFI_DW_RDDATA_VALID_out;
assign AXI_06_DFI_INIT_COMPLETE = AXI_06_DFI_INIT_COMPLETE_out;
assign AXI_06_DFI_PHYUPD_REQ = AXI_06_DFI_PHYUPD_REQ_out;
assign AXI_06_DFI_PHY_LP_STATE = AXI_06_DFI_PHY_LP_STATE_out;
assign AXI_06_DFI_RST_N_BUF = AXI_06_DFI_RST_N_BUF_out;
assign AXI_06_MC_STATUS = AXI_06_MC_STATUS_out;
assign AXI_06_PHY_STATUS = AXI_06_PHY_STATUS_out;
assign AXI_06_RDATA = AXI_06_RDATA_out;
assign AXI_06_RDATA_PARITY = AXI_06_RDATA_PARITY_out;
assign AXI_06_RID = AXI_06_RID_out;
assign AXI_06_RLAST = AXI_06_RLAST_out;
assign AXI_06_RRESP = AXI_06_RRESP_out;
assign AXI_06_RVALID = AXI_06_RVALID_out;
assign AXI_06_WREADY = AXI_06_WREADY_out;
assign AXI_07_ARREADY = AXI_07_ARREADY_out;
assign AXI_07_AWREADY = AXI_07_AWREADY_out;
assign AXI_07_BID = AXI_07_BID_out;
assign AXI_07_BRESP = AXI_07_BRESP_out;
assign AXI_07_BVALID = AXI_07_BVALID_out;
assign AXI_07_DFI_AW_AERR_N = AXI_07_DFI_AW_AERR_N_out;
assign AXI_07_DFI_CLK_BUF = AXI_07_DFI_CLK_BUF_out;
assign AXI_07_DFI_DBI_BYTE_DISABLE = AXI_07_DFI_DBI_BYTE_DISABLE_out;
assign AXI_07_DFI_DW_RDDATA_DBI = AXI_07_DFI_DW_RDDATA_DBI_out;
assign AXI_07_DFI_DW_RDDATA_DERR = AXI_07_DFI_DW_RDDATA_DERR_out;
assign AXI_07_DFI_DW_RDDATA_VALID = AXI_07_DFI_DW_RDDATA_VALID_out;
assign AXI_07_DFI_INIT_COMPLETE = AXI_07_DFI_INIT_COMPLETE_out;
assign AXI_07_DFI_PHYUPD_REQ = AXI_07_DFI_PHYUPD_REQ_out;
assign AXI_07_DFI_PHY_LP_STATE = AXI_07_DFI_PHY_LP_STATE_out;
assign AXI_07_DFI_RST_N_BUF = AXI_07_DFI_RST_N_BUF_out;
assign AXI_07_RDATA = AXI_07_RDATA_out;
assign AXI_07_RDATA_PARITY = AXI_07_RDATA_PARITY_out;
assign AXI_07_RID = AXI_07_RID_out;
assign AXI_07_RLAST = AXI_07_RLAST_out;
assign AXI_07_RRESP = AXI_07_RRESP_out;
assign AXI_07_RVALID = AXI_07_RVALID_out;
assign AXI_07_WREADY = AXI_07_WREADY_out;
assign AXI_08_ARREADY = AXI_08_ARREADY_out;
assign AXI_08_AWREADY = AXI_08_AWREADY_out;
assign AXI_08_BID = AXI_08_BID_out;
assign AXI_08_BRESP = AXI_08_BRESP_out;
assign AXI_08_BVALID = AXI_08_BVALID_out;
assign AXI_08_DFI_AW_AERR_N = AXI_08_DFI_AW_AERR_N_out;
assign AXI_08_DFI_CLK_BUF = AXI_08_DFI_CLK_BUF_out;
assign AXI_08_DFI_DBI_BYTE_DISABLE = AXI_08_DFI_DBI_BYTE_DISABLE_out;
assign AXI_08_DFI_DW_RDDATA_DBI = AXI_08_DFI_DW_RDDATA_DBI_out;
assign AXI_08_DFI_DW_RDDATA_DERR = AXI_08_DFI_DW_RDDATA_DERR_out;
assign AXI_08_DFI_DW_RDDATA_VALID = AXI_08_DFI_DW_RDDATA_VALID_out;
assign AXI_08_DFI_INIT_COMPLETE = AXI_08_DFI_INIT_COMPLETE_out;
assign AXI_08_DFI_PHYUPD_REQ = AXI_08_DFI_PHYUPD_REQ_out;
assign AXI_08_DFI_PHY_LP_STATE = AXI_08_DFI_PHY_LP_STATE_out;
assign AXI_08_DFI_RST_N_BUF = AXI_08_DFI_RST_N_BUF_out;
assign AXI_08_MC_STATUS = AXI_08_MC_STATUS_out;
assign AXI_08_PHY_STATUS = AXI_08_PHY_STATUS_out;
assign AXI_08_RDATA = AXI_08_RDATA_out;
assign AXI_08_RDATA_PARITY = AXI_08_RDATA_PARITY_out;
assign AXI_08_RID = AXI_08_RID_out;
assign AXI_08_RLAST = AXI_08_RLAST_out;
assign AXI_08_RRESP = AXI_08_RRESP_out;
assign AXI_08_RVALID = AXI_08_RVALID_out;
assign AXI_08_WREADY = AXI_08_WREADY_out;
assign AXI_09_ARREADY = AXI_09_ARREADY_out;
assign AXI_09_AWREADY = AXI_09_AWREADY_out;
assign AXI_09_BID = AXI_09_BID_out;
assign AXI_09_BRESP = AXI_09_BRESP_out;
assign AXI_09_BVALID = AXI_09_BVALID_out;
assign AXI_09_DFI_AW_AERR_N = AXI_09_DFI_AW_AERR_N_out;
assign AXI_09_DFI_CLK_BUF = AXI_09_DFI_CLK_BUF_out;
assign AXI_09_DFI_DBI_BYTE_DISABLE = AXI_09_DFI_DBI_BYTE_DISABLE_out;
assign AXI_09_DFI_DW_RDDATA_DBI = AXI_09_DFI_DW_RDDATA_DBI_out;
assign AXI_09_DFI_DW_RDDATA_DERR = AXI_09_DFI_DW_RDDATA_DERR_out;
assign AXI_09_DFI_DW_RDDATA_VALID = AXI_09_DFI_DW_RDDATA_VALID_out;
assign AXI_09_DFI_INIT_COMPLETE = AXI_09_DFI_INIT_COMPLETE_out;
assign AXI_09_DFI_PHYUPD_REQ = AXI_09_DFI_PHYUPD_REQ_out;
assign AXI_09_DFI_PHY_LP_STATE = AXI_09_DFI_PHY_LP_STATE_out;
assign AXI_09_DFI_RST_N_BUF = AXI_09_DFI_RST_N_BUF_out;
assign AXI_09_RDATA = AXI_09_RDATA_out;
assign AXI_09_RDATA_PARITY = AXI_09_RDATA_PARITY_out;
assign AXI_09_RID = AXI_09_RID_out;
assign AXI_09_RLAST = AXI_09_RLAST_out;
assign AXI_09_RRESP = AXI_09_RRESP_out;
assign AXI_09_RVALID = AXI_09_RVALID_out;
assign AXI_09_WREADY = AXI_09_WREADY_out;
assign AXI_10_ARREADY = AXI_10_ARREADY_out;
assign AXI_10_AWREADY = AXI_10_AWREADY_out;
assign AXI_10_BID = AXI_10_BID_out;
assign AXI_10_BRESP = AXI_10_BRESP_out;
assign AXI_10_BVALID = AXI_10_BVALID_out;
assign AXI_10_DFI_AW_AERR_N = AXI_10_DFI_AW_AERR_N_out;
assign AXI_10_DFI_CLK_BUF = AXI_10_DFI_CLK_BUF_out;
assign AXI_10_DFI_DBI_BYTE_DISABLE = AXI_10_DFI_DBI_BYTE_DISABLE_out;
assign AXI_10_DFI_DW_RDDATA_DBI = AXI_10_DFI_DW_RDDATA_DBI_out;
assign AXI_10_DFI_DW_RDDATA_DERR = AXI_10_DFI_DW_RDDATA_DERR_out;
assign AXI_10_DFI_DW_RDDATA_VALID = AXI_10_DFI_DW_RDDATA_VALID_out;
assign AXI_10_DFI_INIT_COMPLETE = AXI_10_DFI_INIT_COMPLETE_out;
assign AXI_10_DFI_PHYUPD_REQ = AXI_10_DFI_PHYUPD_REQ_out;
assign AXI_10_DFI_PHY_LP_STATE = AXI_10_DFI_PHY_LP_STATE_out;
assign AXI_10_DFI_RST_N_BUF = AXI_10_DFI_RST_N_BUF_out;
assign AXI_10_MC_STATUS = AXI_10_MC_STATUS_out;
assign AXI_10_PHY_STATUS = AXI_10_PHY_STATUS_out;
assign AXI_10_RDATA = AXI_10_RDATA_out;
assign AXI_10_RDATA_PARITY = AXI_10_RDATA_PARITY_out;
assign AXI_10_RID = AXI_10_RID_out;
assign AXI_10_RLAST = AXI_10_RLAST_out;
assign AXI_10_RRESP = AXI_10_RRESP_out;
assign AXI_10_RVALID = AXI_10_RVALID_out;
assign AXI_10_WREADY = AXI_10_WREADY_out;
assign AXI_11_ARREADY = AXI_11_ARREADY_out;
assign AXI_11_AWREADY = AXI_11_AWREADY_out;
assign AXI_11_BID = AXI_11_BID_out;
assign AXI_11_BRESP = AXI_11_BRESP_out;
assign AXI_11_BVALID = AXI_11_BVALID_out;
assign AXI_11_DFI_AW_AERR_N = AXI_11_DFI_AW_AERR_N_out;
assign AXI_11_DFI_CLK_BUF = AXI_11_DFI_CLK_BUF_out;
assign AXI_11_DFI_DBI_BYTE_DISABLE = AXI_11_DFI_DBI_BYTE_DISABLE_out;
assign AXI_11_DFI_DW_RDDATA_DBI = AXI_11_DFI_DW_RDDATA_DBI_out;
assign AXI_11_DFI_DW_RDDATA_DERR = AXI_11_DFI_DW_RDDATA_DERR_out;
assign AXI_11_DFI_DW_RDDATA_VALID = AXI_11_DFI_DW_RDDATA_VALID_out;
assign AXI_11_DFI_INIT_COMPLETE = AXI_11_DFI_INIT_COMPLETE_out;
assign AXI_11_DFI_PHYUPD_REQ = AXI_11_DFI_PHYUPD_REQ_out;
assign AXI_11_DFI_PHY_LP_STATE = AXI_11_DFI_PHY_LP_STATE_out;
assign AXI_11_DFI_RST_N_BUF = AXI_11_DFI_RST_N_BUF_out;
assign AXI_11_RDATA = AXI_11_RDATA_out;
assign AXI_11_RDATA_PARITY = AXI_11_RDATA_PARITY_out;
assign AXI_11_RID = AXI_11_RID_out;
assign AXI_11_RLAST = AXI_11_RLAST_out;
assign AXI_11_RRESP = AXI_11_RRESP_out;
assign AXI_11_RVALID = AXI_11_RVALID_out;
assign AXI_11_WREADY = AXI_11_WREADY_out;
assign AXI_12_ARREADY = AXI_12_ARREADY_out;
assign AXI_12_AWREADY = AXI_12_AWREADY_out;
assign AXI_12_BID = AXI_12_BID_out;
assign AXI_12_BRESP = AXI_12_BRESP_out;
assign AXI_12_BVALID = AXI_12_BVALID_out;
assign AXI_12_DFI_AW_AERR_N = AXI_12_DFI_AW_AERR_N_out;
assign AXI_12_DFI_CLK_BUF = AXI_12_DFI_CLK_BUF_out;
assign AXI_12_DFI_DBI_BYTE_DISABLE = AXI_12_DFI_DBI_BYTE_DISABLE_out;
assign AXI_12_DFI_DW_RDDATA_DBI = AXI_12_DFI_DW_RDDATA_DBI_out;
assign AXI_12_DFI_DW_RDDATA_DERR = AXI_12_DFI_DW_RDDATA_DERR_out;
assign AXI_12_DFI_DW_RDDATA_VALID = AXI_12_DFI_DW_RDDATA_VALID_out;
assign AXI_12_DFI_INIT_COMPLETE = AXI_12_DFI_INIT_COMPLETE_out;
assign AXI_12_DFI_PHYUPD_REQ = AXI_12_DFI_PHYUPD_REQ_out;
assign AXI_12_DFI_PHY_LP_STATE = AXI_12_DFI_PHY_LP_STATE_out;
assign AXI_12_DFI_RST_N_BUF = AXI_12_DFI_RST_N_BUF_out;
assign AXI_12_MC_STATUS = AXI_12_MC_STATUS_out;
assign AXI_12_PHY_STATUS = AXI_12_PHY_STATUS_out;
assign AXI_12_RDATA = AXI_12_RDATA_out;
assign AXI_12_RDATA_PARITY = AXI_12_RDATA_PARITY_out;
assign AXI_12_RID = AXI_12_RID_out;
assign AXI_12_RLAST = AXI_12_RLAST_out;
assign AXI_12_RRESP = AXI_12_RRESP_out;
assign AXI_12_RVALID = AXI_12_RVALID_out;
assign AXI_12_WREADY = AXI_12_WREADY_out;
assign AXI_13_ARREADY = AXI_13_ARREADY_out;
assign AXI_13_AWREADY = AXI_13_AWREADY_out;
assign AXI_13_BID = AXI_13_BID_out;
assign AXI_13_BRESP = AXI_13_BRESP_out;
assign AXI_13_BVALID = AXI_13_BVALID_out;
assign AXI_13_DFI_AW_AERR_N = AXI_13_DFI_AW_AERR_N_out;
assign AXI_13_DFI_CLK_BUF = AXI_13_DFI_CLK_BUF_out;
assign AXI_13_DFI_DBI_BYTE_DISABLE = AXI_13_DFI_DBI_BYTE_DISABLE_out;
assign AXI_13_DFI_DW_RDDATA_DBI = AXI_13_DFI_DW_RDDATA_DBI_out;
assign AXI_13_DFI_DW_RDDATA_DERR = AXI_13_DFI_DW_RDDATA_DERR_out;
assign AXI_13_DFI_DW_RDDATA_VALID = AXI_13_DFI_DW_RDDATA_VALID_out;
assign AXI_13_DFI_INIT_COMPLETE = AXI_13_DFI_INIT_COMPLETE_out;
assign AXI_13_DFI_PHYUPD_REQ = AXI_13_DFI_PHYUPD_REQ_out;
assign AXI_13_DFI_PHY_LP_STATE = AXI_13_DFI_PHY_LP_STATE_out;
assign AXI_13_DFI_RST_N_BUF = AXI_13_DFI_RST_N_BUF_out;
assign AXI_13_RDATA = AXI_13_RDATA_out;
assign AXI_13_RDATA_PARITY = AXI_13_RDATA_PARITY_out;
assign AXI_13_RID = AXI_13_RID_out;
assign AXI_13_RLAST = AXI_13_RLAST_out;
assign AXI_13_RRESP = AXI_13_RRESP_out;
assign AXI_13_RVALID = AXI_13_RVALID_out;
assign AXI_13_WREADY = AXI_13_WREADY_out;
assign AXI_14_ARREADY = AXI_14_ARREADY_out;
assign AXI_14_AWREADY = AXI_14_AWREADY_out;
assign AXI_14_BID = AXI_14_BID_out;
assign AXI_14_BRESP = AXI_14_BRESP_out;
assign AXI_14_BVALID = AXI_14_BVALID_out;
assign AXI_14_DFI_AW_AERR_N = AXI_14_DFI_AW_AERR_N_out;
assign AXI_14_DFI_CLK_BUF = AXI_14_DFI_CLK_BUF_out;
assign AXI_14_DFI_DBI_BYTE_DISABLE = AXI_14_DFI_DBI_BYTE_DISABLE_out;
assign AXI_14_DFI_DW_RDDATA_DBI = AXI_14_DFI_DW_RDDATA_DBI_out;
assign AXI_14_DFI_DW_RDDATA_DERR = AXI_14_DFI_DW_RDDATA_DERR_out;
assign AXI_14_DFI_DW_RDDATA_VALID = AXI_14_DFI_DW_RDDATA_VALID_out;
assign AXI_14_DFI_INIT_COMPLETE = AXI_14_DFI_INIT_COMPLETE_out;
assign AXI_14_DFI_PHYUPD_REQ = AXI_14_DFI_PHYUPD_REQ_out;
assign AXI_14_DFI_PHY_LP_STATE = AXI_14_DFI_PHY_LP_STATE_out;
assign AXI_14_DFI_RST_N_BUF = AXI_14_DFI_RST_N_BUF_out;
assign AXI_14_MC_STATUS = AXI_14_MC_STATUS_out;
assign AXI_14_PHY_STATUS = AXI_14_PHY_STATUS_out;
assign AXI_14_RDATA = AXI_14_RDATA_out;
assign AXI_14_RDATA_PARITY = AXI_14_RDATA_PARITY_out;
assign AXI_14_RID = AXI_14_RID_out;
assign AXI_14_RLAST = AXI_14_RLAST_out;
assign AXI_14_RRESP = AXI_14_RRESP_out;
assign AXI_14_RVALID = AXI_14_RVALID_out;
assign AXI_14_WREADY = AXI_14_WREADY_out;
assign AXI_15_ARREADY = AXI_15_ARREADY_out;
assign AXI_15_AWREADY = AXI_15_AWREADY_out;
assign AXI_15_BID = AXI_15_BID_out;
assign AXI_15_BRESP = AXI_15_BRESP_out;
assign AXI_15_BVALID = AXI_15_BVALID_out;
assign AXI_15_DFI_AW_AERR_N = AXI_15_DFI_AW_AERR_N_out;
assign AXI_15_DFI_CLK_BUF = AXI_15_DFI_CLK_BUF_out;
assign AXI_15_DFI_DBI_BYTE_DISABLE = AXI_15_DFI_DBI_BYTE_DISABLE_out;
assign AXI_15_DFI_DW_RDDATA_DBI = AXI_15_DFI_DW_RDDATA_DBI_out;
assign AXI_15_DFI_DW_RDDATA_DERR = AXI_15_DFI_DW_RDDATA_DERR_out;
assign AXI_15_DFI_DW_RDDATA_VALID = AXI_15_DFI_DW_RDDATA_VALID_out;
assign AXI_15_DFI_INIT_COMPLETE = AXI_15_DFI_INIT_COMPLETE_out;
assign AXI_15_DFI_PHYUPD_REQ = AXI_15_DFI_PHYUPD_REQ_out;
assign AXI_15_DFI_PHY_LP_STATE = AXI_15_DFI_PHY_LP_STATE_out;
assign AXI_15_DFI_RST_N_BUF = AXI_15_DFI_RST_N_BUF_out;
assign AXI_15_RDATA = AXI_15_RDATA_out;
assign AXI_15_RDATA_PARITY = AXI_15_RDATA_PARITY_out;
assign AXI_15_RID = AXI_15_RID_out;
assign AXI_15_RLAST = AXI_15_RLAST_out;
assign AXI_15_RRESP = AXI_15_RRESP_out;
assign AXI_15_RVALID = AXI_15_RVALID_out;
assign AXI_15_WREADY = AXI_15_WREADY_out;
assign DRAM_0_STAT_CATTRIP = DRAM_0_STAT_CATTRIP_out;
assign DRAM_0_STAT_TEMP = DRAM_0_STAT_TEMP_out;
assign APB_0_PADDR_in = APB_0_PADDR;
assign APB_0_PCLK_in = APB_0_PCLK;
assign APB_0_PENABLE_in = APB_0_PENABLE;
assign APB_0_PRESET_N_in = APB_0_PRESET_N;
assign APB_0_PSEL_in = APB_0_PSEL;
assign APB_0_PWDATA_in = APB_0_PWDATA;
assign APB_0_PWRITE_in = APB_0_PWRITE;
assign AXI_00_ACLK_in = AXI_00_ACLK;
assign AXI_00_ARADDR_in = AXI_00_ARADDR;
assign AXI_00_ARBURST_in = AXI_00_ARBURST;
assign AXI_00_ARESET_N_in = AXI_00_ARESET_N;
assign AXI_00_ARID_in = AXI_00_ARID;
assign AXI_00_ARLEN_in = AXI_00_ARLEN;
assign AXI_00_ARSIZE_in = AXI_00_ARSIZE;
assign AXI_00_ARVALID_in = AXI_00_ARVALID;
assign AXI_00_AWADDR_in = AXI_00_AWADDR;
assign AXI_00_AWBURST_in = AXI_00_AWBURST;
assign AXI_00_AWID_in = AXI_00_AWID;
assign AXI_00_AWLEN_in = AXI_00_AWLEN;
assign AXI_00_AWSIZE_in = AXI_00_AWSIZE;
assign AXI_00_AWVALID_in = AXI_00_AWVALID;
assign AXI_00_BREADY_in = AXI_00_BREADY;
assign AXI_00_DFI_LP_PWR_X_REQ_in = AXI_00_DFI_LP_PWR_X_REQ;
assign AXI_00_RREADY_in = AXI_00_RREADY;
assign AXI_00_WDATA_PARITY_in = AXI_00_WDATA_PARITY;
assign AXI_00_WDATA_in = AXI_00_WDATA;
assign AXI_00_WLAST_in = AXI_00_WLAST;
assign AXI_00_WSTRB_in = AXI_00_WSTRB;
assign AXI_00_WVALID_in = AXI_00_WVALID;
assign AXI_01_ACLK_in = AXI_01_ACLK;
assign AXI_01_ARADDR_in = AXI_01_ARADDR;
assign AXI_01_ARBURST_in = AXI_01_ARBURST;
assign AXI_01_ARESET_N_in = AXI_01_ARESET_N;
assign AXI_01_ARID_in = AXI_01_ARID;
assign AXI_01_ARLEN_in = AXI_01_ARLEN;
assign AXI_01_ARSIZE_in = AXI_01_ARSIZE;
assign AXI_01_ARVALID_in = AXI_01_ARVALID;
assign AXI_01_AWADDR_in = AXI_01_AWADDR;
assign AXI_01_AWBURST_in = AXI_01_AWBURST;
assign AXI_01_AWID_in = AXI_01_AWID;
assign AXI_01_AWLEN_in = AXI_01_AWLEN;
assign AXI_01_AWSIZE_in = AXI_01_AWSIZE;
assign AXI_01_AWVALID_in = AXI_01_AWVALID;
assign AXI_01_BREADY_in = AXI_01_BREADY;
assign AXI_01_DFI_LP_PWR_X_REQ_in = AXI_01_DFI_LP_PWR_X_REQ;
assign AXI_01_RREADY_in = AXI_01_RREADY;
assign AXI_01_WDATA_PARITY_in = AXI_01_WDATA_PARITY;
assign AXI_01_WDATA_in = AXI_01_WDATA;
assign AXI_01_WLAST_in = AXI_01_WLAST;
assign AXI_01_WSTRB_in = AXI_01_WSTRB;
assign AXI_01_WVALID_in = AXI_01_WVALID;
assign AXI_02_ACLK_in = AXI_02_ACLK;
assign AXI_02_ARADDR_in = AXI_02_ARADDR;
assign AXI_02_ARBURST_in = AXI_02_ARBURST;
assign AXI_02_ARESET_N_in = AXI_02_ARESET_N;
assign AXI_02_ARID_in = AXI_02_ARID;
assign AXI_02_ARLEN_in = AXI_02_ARLEN;
assign AXI_02_ARSIZE_in = AXI_02_ARSIZE;
assign AXI_02_ARVALID_in = AXI_02_ARVALID;
assign AXI_02_AWADDR_in = AXI_02_AWADDR;
assign AXI_02_AWBURST_in = AXI_02_AWBURST;
assign AXI_02_AWID_in = AXI_02_AWID;
assign AXI_02_AWLEN_in = AXI_02_AWLEN;
assign AXI_02_AWSIZE_in = AXI_02_AWSIZE;
assign AXI_02_AWVALID_in = AXI_02_AWVALID;
assign AXI_02_BREADY_in = AXI_02_BREADY;
assign AXI_02_DFI_LP_PWR_X_REQ_in = AXI_02_DFI_LP_PWR_X_REQ;
assign AXI_02_RREADY_in = AXI_02_RREADY;
assign AXI_02_WDATA_PARITY_in = AXI_02_WDATA_PARITY;
assign AXI_02_WDATA_in = AXI_02_WDATA;
assign AXI_02_WLAST_in = AXI_02_WLAST;
assign AXI_02_WSTRB_in = AXI_02_WSTRB;
assign AXI_02_WVALID_in = AXI_02_WVALID;
assign AXI_03_ACLK_in = AXI_03_ACLK;
assign AXI_03_ARADDR_in = AXI_03_ARADDR;
assign AXI_03_ARBURST_in = AXI_03_ARBURST;
assign AXI_03_ARESET_N_in = AXI_03_ARESET_N;
assign AXI_03_ARID_in = AXI_03_ARID;
assign AXI_03_ARLEN_in = AXI_03_ARLEN;
assign AXI_03_ARSIZE_in = AXI_03_ARSIZE;
assign AXI_03_ARVALID_in = AXI_03_ARVALID;
assign AXI_03_AWADDR_in = AXI_03_AWADDR;
assign AXI_03_AWBURST_in = AXI_03_AWBURST;
assign AXI_03_AWID_in = AXI_03_AWID;
assign AXI_03_AWLEN_in = AXI_03_AWLEN;
assign AXI_03_AWSIZE_in = AXI_03_AWSIZE;
assign AXI_03_AWVALID_in = AXI_03_AWVALID;
assign AXI_03_BREADY_in = AXI_03_BREADY;
assign AXI_03_DFI_LP_PWR_X_REQ_in = AXI_03_DFI_LP_PWR_X_REQ;
assign AXI_03_RREADY_in = AXI_03_RREADY;
assign AXI_03_WDATA_PARITY_in = AXI_03_WDATA_PARITY;
assign AXI_03_WDATA_in = AXI_03_WDATA;
assign AXI_03_WLAST_in = AXI_03_WLAST;
assign AXI_03_WSTRB_in = AXI_03_WSTRB;
assign AXI_03_WVALID_in = AXI_03_WVALID;
assign AXI_04_ACLK_in = AXI_04_ACLK;
assign AXI_04_ARADDR_in = AXI_04_ARADDR;
assign AXI_04_ARBURST_in = AXI_04_ARBURST;
assign AXI_04_ARESET_N_in = AXI_04_ARESET_N;
assign AXI_04_ARID_in = AXI_04_ARID;
assign AXI_04_ARLEN_in = AXI_04_ARLEN;
assign AXI_04_ARSIZE_in = AXI_04_ARSIZE;
assign AXI_04_ARVALID_in = AXI_04_ARVALID;
assign AXI_04_AWADDR_in = AXI_04_AWADDR;
assign AXI_04_AWBURST_in = AXI_04_AWBURST;
assign AXI_04_AWID_in = AXI_04_AWID;
assign AXI_04_AWLEN_in = AXI_04_AWLEN;
assign AXI_04_AWSIZE_in = AXI_04_AWSIZE;
assign AXI_04_AWVALID_in = AXI_04_AWVALID;
assign AXI_04_BREADY_in = AXI_04_BREADY;
assign AXI_04_DFI_LP_PWR_X_REQ_in = AXI_04_DFI_LP_PWR_X_REQ;
assign AXI_04_RREADY_in = AXI_04_RREADY;
assign AXI_04_WDATA_PARITY_in = AXI_04_WDATA_PARITY;
assign AXI_04_WDATA_in = AXI_04_WDATA;
assign AXI_04_WLAST_in = AXI_04_WLAST;
assign AXI_04_WSTRB_in = AXI_04_WSTRB;
assign AXI_04_WVALID_in = AXI_04_WVALID;
assign AXI_05_ACLK_in = AXI_05_ACLK;
assign AXI_05_ARADDR_in = AXI_05_ARADDR;
assign AXI_05_ARBURST_in = AXI_05_ARBURST;
assign AXI_05_ARESET_N_in = AXI_05_ARESET_N;
assign AXI_05_ARID_in = AXI_05_ARID;
assign AXI_05_ARLEN_in = AXI_05_ARLEN;
assign AXI_05_ARSIZE_in = AXI_05_ARSIZE;
assign AXI_05_ARVALID_in = AXI_05_ARVALID;
assign AXI_05_AWADDR_in = AXI_05_AWADDR;
assign AXI_05_AWBURST_in = AXI_05_AWBURST;
assign AXI_05_AWID_in = AXI_05_AWID;
assign AXI_05_AWLEN_in = AXI_05_AWLEN;
assign AXI_05_AWSIZE_in = AXI_05_AWSIZE;
assign AXI_05_AWVALID_in = AXI_05_AWVALID;
assign AXI_05_BREADY_in = AXI_05_BREADY;
assign AXI_05_DFI_LP_PWR_X_REQ_in = AXI_05_DFI_LP_PWR_X_REQ;
assign AXI_05_RREADY_in = AXI_05_RREADY;
assign AXI_05_WDATA_PARITY_in = AXI_05_WDATA_PARITY;
assign AXI_05_WDATA_in = AXI_05_WDATA;
assign AXI_05_WLAST_in = AXI_05_WLAST;
assign AXI_05_WSTRB_in = AXI_05_WSTRB;
assign AXI_05_WVALID_in = AXI_05_WVALID;
assign AXI_06_ACLK_in = AXI_06_ACLK;
assign AXI_06_ARADDR_in = AXI_06_ARADDR;
assign AXI_06_ARBURST_in = AXI_06_ARBURST;
assign AXI_06_ARESET_N_in = AXI_06_ARESET_N;
assign AXI_06_ARID_in = AXI_06_ARID;
assign AXI_06_ARLEN_in = AXI_06_ARLEN;
assign AXI_06_ARSIZE_in = AXI_06_ARSIZE;
assign AXI_06_ARVALID_in = AXI_06_ARVALID;
assign AXI_06_AWADDR_in = AXI_06_AWADDR;
assign AXI_06_AWBURST_in = AXI_06_AWBURST;
assign AXI_06_AWID_in = AXI_06_AWID;
assign AXI_06_AWLEN_in = AXI_06_AWLEN;
assign AXI_06_AWSIZE_in = AXI_06_AWSIZE;
assign AXI_06_AWVALID_in = AXI_06_AWVALID;
assign AXI_06_BREADY_in = AXI_06_BREADY;
assign AXI_06_DFI_LP_PWR_X_REQ_in = AXI_06_DFI_LP_PWR_X_REQ;
assign AXI_06_RREADY_in = AXI_06_RREADY;
assign AXI_06_WDATA_PARITY_in = AXI_06_WDATA_PARITY;
assign AXI_06_WDATA_in = AXI_06_WDATA;
assign AXI_06_WLAST_in = AXI_06_WLAST;
assign AXI_06_WSTRB_in = AXI_06_WSTRB;
assign AXI_06_WVALID_in = AXI_06_WVALID;
assign AXI_07_ACLK_in = AXI_07_ACLK;
assign AXI_07_ARADDR_in = AXI_07_ARADDR;
assign AXI_07_ARBURST_in = AXI_07_ARBURST;
assign AXI_07_ARESET_N_in = AXI_07_ARESET_N;
assign AXI_07_ARID_in = AXI_07_ARID;
assign AXI_07_ARLEN_in = AXI_07_ARLEN;
assign AXI_07_ARSIZE_in = AXI_07_ARSIZE;
assign AXI_07_ARVALID_in = AXI_07_ARVALID;
assign AXI_07_AWADDR_in = AXI_07_AWADDR;
assign AXI_07_AWBURST_in = AXI_07_AWBURST;
assign AXI_07_AWID_in = AXI_07_AWID;
assign AXI_07_AWLEN_in = AXI_07_AWLEN;
assign AXI_07_AWSIZE_in = AXI_07_AWSIZE;
assign AXI_07_AWVALID_in = AXI_07_AWVALID;
assign AXI_07_BREADY_in = AXI_07_BREADY;
assign AXI_07_DFI_LP_PWR_X_REQ_in = AXI_07_DFI_LP_PWR_X_REQ;
assign AXI_07_RREADY_in = AXI_07_RREADY;
assign AXI_07_WDATA_PARITY_in = AXI_07_WDATA_PARITY;
assign AXI_07_WDATA_in = AXI_07_WDATA;
assign AXI_07_WLAST_in = AXI_07_WLAST;
assign AXI_07_WSTRB_in = AXI_07_WSTRB;
assign AXI_07_WVALID_in = AXI_07_WVALID;
assign AXI_08_ACLK_in = AXI_08_ACLK;
assign AXI_08_ARADDR_in = AXI_08_ARADDR;
assign AXI_08_ARBURST_in = AXI_08_ARBURST;
assign AXI_08_ARESET_N_in = AXI_08_ARESET_N;
assign AXI_08_ARID_in = AXI_08_ARID;
assign AXI_08_ARLEN_in = AXI_08_ARLEN;
assign AXI_08_ARSIZE_in = AXI_08_ARSIZE;
assign AXI_08_ARVALID_in = AXI_08_ARVALID;
assign AXI_08_AWADDR_in = AXI_08_AWADDR;
assign AXI_08_AWBURST_in = AXI_08_AWBURST;
assign AXI_08_AWID_in = AXI_08_AWID;
assign AXI_08_AWLEN_in = AXI_08_AWLEN;
assign AXI_08_AWSIZE_in = AXI_08_AWSIZE;
assign AXI_08_AWVALID_in = AXI_08_AWVALID;
assign AXI_08_BREADY_in = AXI_08_BREADY;
assign AXI_08_DFI_LP_PWR_X_REQ_in = AXI_08_DFI_LP_PWR_X_REQ;
assign AXI_08_RREADY_in = AXI_08_RREADY;
assign AXI_08_WDATA_PARITY_in = AXI_08_WDATA_PARITY;
assign AXI_08_WDATA_in = AXI_08_WDATA;
assign AXI_08_WLAST_in = AXI_08_WLAST;
assign AXI_08_WSTRB_in = AXI_08_WSTRB;
assign AXI_08_WVALID_in = AXI_08_WVALID;
assign AXI_09_ACLK_in = AXI_09_ACLK;
assign AXI_09_ARADDR_in = AXI_09_ARADDR;
assign AXI_09_ARBURST_in = AXI_09_ARBURST;
assign AXI_09_ARESET_N_in = AXI_09_ARESET_N;
assign AXI_09_ARID_in = AXI_09_ARID;
assign AXI_09_ARLEN_in = AXI_09_ARLEN;
assign AXI_09_ARSIZE_in = AXI_09_ARSIZE;
assign AXI_09_ARVALID_in = AXI_09_ARVALID;
assign AXI_09_AWADDR_in = AXI_09_AWADDR;
assign AXI_09_AWBURST_in = AXI_09_AWBURST;
assign AXI_09_AWID_in = AXI_09_AWID;
assign AXI_09_AWLEN_in = AXI_09_AWLEN;
assign AXI_09_AWSIZE_in = AXI_09_AWSIZE;
assign AXI_09_AWVALID_in = AXI_09_AWVALID;
assign AXI_09_BREADY_in = AXI_09_BREADY;
assign AXI_09_DFI_LP_PWR_X_REQ_in = AXI_09_DFI_LP_PWR_X_REQ;
assign AXI_09_RREADY_in = AXI_09_RREADY;
assign AXI_09_WDATA_PARITY_in = AXI_09_WDATA_PARITY;
assign AXI_09_WDATA_in = AXI_09_WDATA;
assign AXI_09_WLAST_in = AXI_09_WLAST;
assign AXI_09_WSTRB_in = AXI_09_WSTRB;
assign AXI_09_WVALID_in = AXI_09_WVALID;
assign AXI_10_ACLK_in = AXI_10_ACLK;
assign AXI_10_ARADDR_in = AXI_10_ARADDR;
assign AXI_10_ARBURST_in = AXI_10_ARBURST;
assign AXI_10_ARESET_N_in = AXI_10_ARESET_N;
assign AXI_10_ARID_in = AXI_10_ARID;
assign AXI_10_ARLEN_in = AXI_10_ARLEN;
assign AXI_10_ARSIZE_in = AXI_10_ARSIZE;
assign AXI_10_ARVALID_in = AXI_10_ARVALID;
assign AXI_10_AWADDR_in = AXI_10_AWADDR;
assign AXI_10_AWBURST_in = AXI_10_AWBURST;
assign AXI_10_AWID_in = AXI_10_AWID;
assign AXI_10_AWLEN_in = AXI_10_AWLEN;
assign AXI_10_AWSIZE_in = AXI_10_AWSIZE;
assign AXI_10_AWVALID_in = AXI_10_AWVALID;
assign AXI_10_BREADY_in = AXI_10_BREADY;
assign AXI_10_DFI_LP_PWR_X_REQ_in = AXI_10_DFI_LP_PWR_X_REQ;
assign AXI_10_RREADY_in = AXI_10_RREADY;
assign AXI_10_WDATA_PARITY_in = AXI_10_WDATA_PARITY;
assign AXI_10_WDATA_in = AXI_10_WDATA;
assign AXI_10_WLAST_in = AXI_10_WLAST;
assign AXI_10_WSTRB_in = AXI_10_WSTRB;
assign AXI_10_WVALID_in = AXI_10_WVALID;
assign AXI_11_ACLK_in = AXI_11_ACLK;
assign AXI_11_ARADDR_in = AXI_11_ARADDR;
assign AXI_11_ARBURST_in = AXI_11_ARBURST;
assign AXI_11_ARESET_N_in = AXI_11_ARESET_N;
assign AXI_11_ARID_in = AXI_11_ARID;
assign AXI_11_ARLEN_in = AXI_11_ARLEN;
assign AXI_11_ARSIZE_in = AXI_11_ARSIZE;
assign AXI_11_ARVALID_in = AXI_11_ARVALID;
assign AXI_11_AWADDR_in = AXI_11_AWADDR;
assign AXI_11_AWBURST_in = AXI_11_AWBURST;
assign AXI_11_AWID_in = AXI_11_AWID;
assign AXI_11_AWLEN_in = AXI_11_AWLEN;
assign AXI_11_AWSIZE_in = AXI_11_AWSIZE;
assign AXI_11_AWVALID_in = AXI_11_AWVALID;
assign AXI_11_BREADY_in = AXI_11_BREADY;
assign AXI_11_DFI_LP_PWR_X_REQ_in = AXI_11_DFI_LP_PWR_X_REQ;
assign AXI_11_RREADY_in = AXI_11_RREADY;
assign AXI_11_WDATA_PARITY_in = AXI_11_WDATA_PARITY;
assign AXI_11_WDATA_in = AXI_11_WDATA;
assign AXI_11_WLAST_in = AXI_11_WLAST;
assign AXI_11_WSTRB_in = AXI_11_WSTRB;
assign AXI_11_WVALID_in = AXI_11_WVALID;
assign AXI_12_ACLK_in = AXI_12_ACLK;
assign AXI_12_ARADDR_in = AXI_12_ARADDR;
assign AXI_12_ARBURST_in = AXI_12_ARBURST;
assign AXI_12_ARESET_N_in = AXI_12_ARESET_N;
assign AXI_12_ARID_in = AXI_12_ARID;
assign AXI_12_ARLEN_in = AXI_12_ARLEN;
assign AXI_12_ARSIZE_in = AXI_12_ARSIZE;
assign AXI_12_ARVALID_in = AXI_12_ARVALID;
assign AXI_12_AWADDR_in = AXI_12_AWADDR;
assign AXI_12_AWBURST_in = AXI_12_AWBURST;
assign AXI_12_AWID_in = AXI_12_AWID;
assign AXI_12_AWLEN_in = AXI_12_AWLEN;
assign AXI_12_AWSIZE_in = AXI_12_AWSIZE;
assign AXI_12_AWVALID_in = AXI_12_AWVALID;
assign AXI_12_BREADY_in = AXI_12_BREADY;
assign AXI_12_DFI_LP_PWR_X_REQ_in = AXI_12_DFI_LP_PWR_X_REQ;
assign AXI_12_RREADY_in = AXI_12_RREADY;
assign AXI_12_WDATA_PARITY_in = AXI_12_WDATA_PARITY;
assign AXI_12_WDATA_in = AXI_12_WDATA;
assign AXI_12_WLAST_in = AXI_12_WLAST;
assign AXI_12_WSTRB_in = AXI_12_WSTRB;
assign AXI_12_WVALID_in = AXI_12_WVALID;
assign AXI_13_ACLK_in = AXI_13_ACLK;
assign AXI_13_ARADDR_in = AXI_13_ARADDR;
assign AXI_13_ARBURST_in = AXI_13_ARBURST;
assign AXI_13_ARESET_N_in = AXI_13_ARESET_N;
assign AXI_13_ARID_in = AXI_13_ARID;
assign AXI_13_ARLEN_in = AXI_13_ARLEN;
assign AXI_13_ARSIZE_in = AXI_13_ARSIZE;
assign AXI_13_ARVALID_in = AXI_13_ARVALID;
assign AXI_13_AWADDR_in = AXI_13_AWADDR;
assign AXI_13_AWBURST_in = AXI_13_AWBURST;
assign AXI_13_AWID_in = AXI_13_AWID;
assign AXI_13_AWLEN_in = AXI_13_AWLEN;
assign AXI_13_AWSIZE_in = AXI_13_AWSIZE;
assign AXI_13_AWVALID_in = AXI_13_AWVALID;
assign AXI_13_BREADY_in = AXI_13_BREADY;
assign AXI_13_DFI_LP_PWR_X_REQ_in = AXI_13_DFI_LP_PWR_X_REQ;
assign AXI_13_RREADY_in = AXI_13_RREADY;
assign AXI_13_WDATA_PARITY_in = AXI_13_WDATA_PARITY;
assign AXI_13_WDATA_in = AXI_13_WDATA;
assign AXI_13_WLAST_in = AXI_13_WLAST;
assign AXI_13_WSTRB_in = AXI_13_WSTRB;
assign AXI_13_WVALID_in = AXI_13_WVALID;
assign AXI_14_ACLK_in = AXI_14_ACLK;
assign AXI_14_ARADDR_in = AXI_14_ARADDR;
assign AXI_14_ARBURST_in = AXI_14_ARBURST;
assign AXI_14_ARESET_N_in = AXI_14_ARESET_N;
assign AXI_14_ARID_in = AXI_14_ARID;
assign AXI_14_ARLEN_in = AXI_14_ARLEN;
assign AXI_14_ARSIZE_in = AXI_14_ARSIZE;
assign AXI_14_ARVALID_in = AXI_14_ARVALID;
assign AXI_14_AWADDR_in = AXI_14_AWADDR;
assign AXI_14_AWBURST_in = AXI_14_AWBURST;
assign AXI_14_AWID_in = AXI_14_AWID;
assign AXI_14_AWLEN_in = AXI_14_AWLEN;
assign AXI_14_AWSIZE_in = AXI_14_AWSIZE;
assign AXI_14_AWVALID_in = AXI_14_AWVALID;
assign AXI_14_BREADY_in = AXI_14_BREADY;
assign AXI_14_DFI_LP_PWR_X_REQ_in = AXI_14_DFI_LP_PWR_X_REQ;
assign AXI_14_RREADY_in = AXI_14_RREADY;
assign AXI_14_WDATA_PARITY_in = AXI_14_WDATA_PARITY;
assign AXI_14_WDATA_in = AXI_14_WDATA;
assign AXI_14_WLAST_in = AXI_14_WLAST;
assign AXI_14_WSTRB_in = AXI_14_WSTRB;
assign AXI_14_WVALID_in = AXI_14_WVALID;
assign AXI_15_ACLK_in = AXI_15_ACLK;
assign AXI_15_ARADDR_in = AXI_15_ARADDR;
assign AXI_15_ARBURST_in = AXI_15_ARBURST;
assign AXI_15_ARESET_N_in = AXI_15_ARESET_N;
assign AXI_15_ARID_in = AXI_15_ARID;
assign AXI_15_ARLEN_in = AXI_15_ARLEN;
assign AXI_15_ARSIZE_in = AXI_15_ARSIZE;
assign AXI_15_ARVALID_in = AXI_15_ARVALID;
assign AXI_15_AWADDR_in = AXI_15_AWADDR;
assign AXI_15_AWBURST_in = AXI_15_AWBURST;
assign AXI_15_AWID_in = AXI_15_AWID;
assign AXI_15_AWLEN_in = AXI_15_AWLEN;
assign AXI_15_AWSIZE_in = AXI_15_AWSIZE;
assign AXI_15_AWVALID_in = AXI_15_AWVALID;
assign AXI_15_BREADY_in = AXI_15_BREADY;
assign AXI_15_DFI_LP_PWR_X_REQ_in = AXI_15_DFI_LP_PWR_X_REQ;
assign AXI_15_RREADY_in = AXI_15_RREADY;
assign AXI_15_WDATA_PARITY_in = AXI_15_WDATA_PARITY;
assign AXI_15_WDATA_in = AXI_15_WDATA;
assign AXI_15_WLAST_in = AXI_15_WLAST;
assign AXI_15_WSTRB_in = AXI_15_WSTRB;
assign AXI_15_WVALID_in = AXI_15_WVALID;
assign BSCAN_DRCK_in = BSCAN_DRCK;
assign BSCAN_TCK_in = BSCAN_TCK;
assign HBM_REF_CLK_in = HBM_REF_CLK;
assign MBIST_EN_00_in = MBIST_EN_00;
assign MBIST_EN_01_in = MBIST_EN_01;
assign MBIST_EN_02_in = MBIST_EN_02;
assign MBIST_EN_03_in = MBIST_EN_03;
assign MBIST_EN_04_in = MBIST_EN_04;
assign MBIST_EN_05_in = MBIST_EN_05;
assign MBIST_EN_06_in = MBIST_EN_06;
assign MBIST_EN_07_in = MBIST_EN_07;
`ifndef XIL_XECLIB
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CLK_SEL_00_REG != "FALSE") &&
(CLK_SEL_00_REG != "TRUE"))) begin
$display("Error: [Unisim %s-105] CLK_SEL_00 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_00_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_01_REG != "FALSE") &&
(CLK_SEL_01_REG != "TRUE"))) begin
$display("Error: [Unisim %s-106] CLK_SEL_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_01_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_02_REG != "FALSE") &&
(CLK_SEL_02_REG != "TRUE"))) begin
$display("Error: [Unisim %s-107] CLK_SEL_02 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_02_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_03_REG != "FALSE") &&
(CLK_SEL_03_REG != "TRUE"))) begin
$display("Error: [Unisim %s-108] CLK_SEL_03 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_03_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_04_REG != "FALSE") &&
(CLK_SEL_04_REG != "TRUE"))) begin
$display("Error: [Unisim %s-109] CLK_SEL_04 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_04_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_05_REG != "FALSE") &&
(CLK_SEL_05_REG != "TRUE"))) begin
$display("Error: [Unisim %s-110] CLK_SEL_05 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_05_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_06_REG != "FALSE") &&
(CLK_SEL_06_REG != "TRUE"))) begin
$display("Error: [Unisim %s-111] CLK_SEL_06 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_06_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_07_REG != "FALSE") &&
(CLK_SEL_07_REG != "TRUE"))) begin
$display("Error: [Unisim %s-112] CLK_SEL_07 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_07_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_08_REG != "FALSE") &&
(CLK_SEL_08_REG != "TRUE"))) begin
$display("Error: [Unisim %s-113] CLK_SEL_08 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_08_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_09_REG != "FALSE") &&
(CLK_SEL_09_REG != "TRUE"))) begin
$display("Error: [Unisim %s-114] CLK_SEL_09 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_09_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_10_REG != "FALSE") &&
(CLK_SEL_10_REG != "TRUE"))) begin
$display("Error: [Unisim %s-115] CLK_SEL_10 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_10_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_11_REG != "FALSE") &&
(CLK_SEL_11_REG != "TRUE"))) begin
$display("Error: [Unisim %s-116] CLK_SEL_11 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_11_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_12_REG != "FALSE") &&
(CLK_SEL_12_REG != "TRUE"))) begin
$display("Error: [Unisim %s-117] CLK_SEL_12 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_12_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_13_REG != "FALSE") &&
(CLK_SEL_13_REG != "TRUE"))) begin
$display("Error: [Unisim %s-118] CLK_SEL_13 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_13_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_14_REG != "FALSE") &&
(CLK_SEL_14_REG != "TRUE"))) begin
$display("Error: [Unisim %s-119] CLK_SEL_14 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_14_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_15_REG != "FALSE") &&
(CLK_SEL_15_REG != "TRUE"))) begin
$display("Error: [Unisim %s-120] CLK_SEL_15 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_15_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_00_REG < 50) || (DATARATE_00_REG > 1800))) begin
$display("Error: [Unisim %s-121] DATARATE_00 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_00_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_01_REG < 50) || (DATARATE_01_REG > 1800))) begin
$display("Error: [Unisim %s-122] DATARATE_01 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_01_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_02_REG < 50) || (DATARATE_02_REG > 1800))) begin
$display("Error: [Unisim %s-123] DATARATE_02 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_02_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_03_REG < 50) || (DATARATE_03_REG > 1800))) begin
$display("Error: [Unisim %s-124] DATARATE_03 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_03_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_04_REG < 50) || (DATARATE_04_REG > 1800))) begin
$display("Error: [Unisim %s-125] DATARATE_04 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_04_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_05_REG < 50) || (DATARATE_05_REG > 1800))) begin
$display("Error: [Unisim %s-126] DATARATE_05 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_05_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_06_REG < 50) || (DATARATE_06_REG > 1800))) begin
$display("Error: [Unisim %s-127] DATARATE_06 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_06_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_07_REG < 50) || (DATARATE_07_REG > 1800))) begin
$display("Error: [Unisim %s-128] DATARATE_07 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_07_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DA_LOCKOUT_REG != "FALSE") &&
(DA_LOCKOUT_REG != "TRUE"))) begin
$display("Error: [Unisim %s-129] DA_LOCKOUT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DA_LOCKOUT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_0_REG != "FALSE") &&
(MC_ENABLE_0_REG != "TRUE"))) begin
$display("Error: [Unisim %s-177] MC_ENABLE_0 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_1_REG != "FALSE") &&
(MC_ENABLE_1_REG != "TRUE"))) begin
$display("Error: [Unisim %s-178] MC_ENABLE_1 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_2_REG != "FALSE") &&
(MC_ENABLE_2_REG != "TRUE"))) begin
$display("Error: [Unisim %s-179] MC_ENABLE_2 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_3_REG != "FALSE") &&
(MC_ENABLE_3_REG != "TRUE"))) begin
$display("Error: [Unisim %s-180] MC_ENABLE_3 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_4_REG != "FALSE") &&
(MC_ENABLE_4_REG != "TRUE"))) begin
$display("Error: [Unisim %s-181] MC_ENABLE_4 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_5_REG != "FALSE") &&
(MC_ENABLE_5_REG != "TRUE"))) begin
$display("Error: [Unisim %s-182] MC_ENABLE_5 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_6_REG != "FALSE") &&
(MC_ENABLE_6_REG != "TRUE"))) begin
$display("Error: [Unisim %s-183] MC_ENABLE_6 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_6_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_7_REG != "FALSE") &&
(MC_ENABLE_7_REG != "TRUE"))) begin
$display("Error: [Unisim %s-184] MC_ENABLE_7 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_7_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_APB_REG != "FALSE") &&
(MC_ENABLE_APB_REG != "TRUE"))) begin
$display("Error: [Unisim %s-185] MC_ENABLE_APB attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_APB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PAGEHIT_PERCENT_00_REG < 0) || (PAGEHIT_PERCENT_00_REG > 100))) begin
$display("Error: [Unisim %s-194] PAGEHIT_PERCENT_00 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, PAGEHIT_PERCENT_00_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_00_REG != "FALSE") &&
(PHY_ENABLE_00_REG != "TRUE"))) begin
$display("Error: [Unisim %s-196] PHY_ENABLE_00 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_00_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_01_REG != "FALSE") &&
(PHY_ENABLE_01_REG != "TRUE"))) begin
$display("Error: [Unisim %s-197] PHY_ENABLE_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_01_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_02_REG != "FALSE") &&
(PHY_ENABLE_02_REG != "TRUE"))) begin
$display("Error: [Unisim %s-198] PHY_ENABLE_02 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_02_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_03_REG != "FALSE") &&
(PHY_ENABLE_03_REG != "TRUE"))) begin
$display("Error: [Unisim %s-199] PHY_ENABLE_03 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_03_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_04_REG != "FALSE") &&
(PHY_ENABLE_04_REG != "TRUE"))) begin
$display("Error: [Unisim %s-200] PHY_ENABLE_04 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_04_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_05_REG != "FALSE") &&
(PHY_ENABLE_05_REG != "TRUE"))) begin
$display("Error: [Unisim %s-201] PHY_ENABLE_05 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_05_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_06_REG != "FALSE") &&
(PHY_ENABLE_06_REG != "TRUE"))) begin
$display("Error: [Unisim %s-202] PHY_ENABLE_06 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_06_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_07_REG != "FALSE") &&
(PHY_ENABLE_07_REG != "TRUE"))) begin
$display("Error: [Unisim %s-203] PHY_ENABLE_07 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_07_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_08_REG != "FALSE") &&
(PHY_ENABLE_08_REG != "TRUE"))) begin
$display("Error: [Unisim %s-204] PHY_ENABLE_08 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_08_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_09_REG != "FALSE") &&
(PHY_ENABLE_09_REG != "TRUE"))) begin
$display("Error: [Unisim %s-205] PHY_ENABLE_09 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_09_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_10_REG != "FALSE") &&
(PHY_ENABLE_10_REG != "TRUE"))) begin
$display("Error: [Unisim %s-206] PHY_ENABLE_10 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_10_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_11_REG != "FALSE") &&
(PHY_ENABLE_11_REG != "TRUE"))) begin
$display("Error: [Unisim %s-207] PHY_ENABLE_11 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_11_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_12_REG != "FALSE") &&
(PHY_ENABLE_12_REG != "TRUE"))) begin
$display("Error: [Unisim %s-208] PHY_ENABLE_12 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_12_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_13_REG != "FALSE") &&
(PHY_ENABLE_13_REG != "TRUE"))) begin
$display("Error: [Unisim %s-209] PHY_ENABLE_13 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_13_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_14_REG != "FALSE") &&
(PHY_ENABLE_14_REG != "TRUE"))) begin
$display("Error: [Unisim %s-210] PHY_ENABLE_14 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_14_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_15_REG != "FALSE") &&
(PHY_ENABLE_15_REG != "TRUE"))) begin
$display("Error: [Unisim %s-211] PHY_ENABLE_15 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_15_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_APB_REG != "FALSE") &&
(PHY_ENABLE_APB_REG != "TRUE"))) begin
$display("Error: [Unisim %s-212] PHY_ENABLE_APB attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_APB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_PCLK_INVERT_01_REG != "FALSE") &&
(PHY_PCLK_INVERT_01_REG != "TRUE"))) begin
$display("Error: [Unisim %s-213] PHY_PCLK_INVERT_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_PCLK_INVERT_01_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_00_REG < 0) || (READ_PERCENT_00_REG > 100))) begin
$display("Error: [Unisim %s-215] READ_PERCENT_00 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_00_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_01_REG < 0) || (READ_PERCENT_01_REG > 100))) begin
$display("Error: [Unisim %s-216] READ_PERCENT_01 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_01_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_02_REG < 0) || (READ_PERCENT_02_REG > 100))) begin
$display("Error: [Unisim %s-217] READ_PERCENT_02 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_02_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_03_REG < 0) || (READ_PERCENT_03_REG > 100))) begin
$display("Error: [Unisim %s-218] READ_PERCENT_03 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_03_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_04_REG < 0) || (READ_PERCENT_04_REG > 100))) begin
$display("Error: [Unisim %s-219] READ_PERCENT_04 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_04_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_05_REG < 0) || (READ_PERCENT_05_REG > 100))) begin
$display("Error: [Unisim %s-220] READ_PERCENT_05 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_05_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_06_REG < 0) || (READ_PERCENT_06_REG > 100))) begin
$display("Error: [Unisim %s-221] READ_PERCENT_06 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_06_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_07_REG < 0) || (READ_PERCENT_07_REG > 100))) begin
$display("Error: [Unisim %s-222] READ_PERCENT_07 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_07_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_08_REG < 0) || (READ_PERCENT_08_REG > 100))) begin
$display("Error: [Unisim %s-223] READ_PERCENT_08 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_08_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_09_REG < 0) || (READ_PERCENT_09_REG > 100))) begin
$display("Error: [Unisim %s-224] READ_PERCENT_09 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_09_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_10_REG < 0) || (READ_PERCENT_10_REG > 100))) begin
$display("Error: [Unisim %s-225] READ_PERCENT_10 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_10_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_11_REG < 0) || (READ_PERCENT_11_REG > 100))) begin
$display("Error: [Unisim %s-226] READ_PERCENT_11 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_11_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_12_REG < 0) || (READ_PERCENT_12_REG > 100))) begin
$display("Error: [Unisim %s-227] READ_PERCENT_12 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_12_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_13_REG < 0) || (READ_PERCENT_13_REG > 100))) begin
$display("Error: [Unisim %s-228] READ_PERCENT_13 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_13_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_14_REG < 0) || (READ_PERCENT_14_REG > 100))) begin
$display("Error: [Unisim %s-229] READ_PERCENT_14 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_14_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_15_REG < 0) || (READ_PERCENT_15_REG > 100))) begin
$display("Error: [Unisim %s-230] READ_PERCENT_15 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_15_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_DEVICE_REG != "ULTRASCALE_PLUS") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin
$display("Error: [Unisim %s-231] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((STACK_LOCATION_REG != 0) &&
(STACK_LOCATION_REG != 1))) begin
$display("Error: [Unisim %s-232] STACK_LOCATION attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, STACK_LOCATION_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SWITCH_ENABLE_REG != "FALSE") &&
(SWITCH_ENABLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-233] SWITCH_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SWITCH_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_00_REG < 0) || (WRITE_PERCENT_00_REG > 100))) begin
$display("Error: [Unisim %s-235] WRITE_PERCENT_00 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_00_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_01_REG < 0) || (WRITE_PERCENT_01_REG > 100))) begin
$display("Error: [Unisim %s-236] WRITE_PERCENT_01 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_01_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_02_REG < 0) || (WRITE_PERCENT_02_REG > 100))) begin
$display("Error: [Unisim %s-237] WRITE_PERCENT_02 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_02_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_03_REG < 0) || (WRITE_PERCENT_03_REG > 100))) begin
$display("Error: [Unisim %s-238] WRITE_PERCENT_03 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_03_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_04_REG < 0) || (WRITE_PERCENT_04_REG > 100))) begin
$display("Error: [Unisim %s-239] WRITE_PERCENT_04 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_04_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_05_REG < 0) || (WRITE_PERCENT_05_REG > 100))) begin
$display("Error: [Unisim %s-240] WRITE_PERCENT_05 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_05_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_06_REG < 0) || (WRITE_PERCENT_06_REG > 100))) begin
$display("Error: [Unisim %s-241] WRITE_PERCENT_06 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_06_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_07_REG < 0) || (WRITE_PERCENT_07_REG > 100))) begin
$display("Error: [Unisim %s-242] WRITE_PERCENT_07 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_07_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_08_REG < 0) || (WRITE_PERCENT_08_REG > 100))) begin
$display("Error: [Unisim %s-243] WRITE_PERCENT_08 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_08_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_09_REG < 0) || (WRITE_PERCENT_09_REG > 100))) begin
$display("Error: [Unisim %s-244] WRITE_PERCENT_09 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_09_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_10_REG < 0) || (WRITE_PERCENT_10_REG > 100))) begin
$display("Error: [Unisim %s-245] WRITE_PERCENT_10 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_10_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_11_REG < 0) || (WRITE_PERCENT_11_REG > 100))) begin
$display("Error: [Unisim %s-246] WRITE_PERCENT_11 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_11_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_12_REG < 0) || (WRITE_PERCENT_12_REG > 100))) begin
$display("Error: [Unisim %s-247] WRITE_PERCENT_12 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_12_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_13_REG < 0) || (WRITE_PERCENT_13_REG > 100))) begin
$display("Error: [Unisim %s-248] WRITE_PERCENT_13 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_13_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_14_REG < 0) || (WRITE_PERCENT_14_REG > 100))) begin
$display("Error: [Unisim %s-249] WRITE_PERCENT_14 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_14_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_15_REG < 0) || (WRITE_PERCENT_15_REG > 100))) begin
$display("Error: [Unisim %s-250] WRITE_PERCENT_15 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_15_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
assign ANALOG_HBM_SEL_00_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_00_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_01_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_02_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_03_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_04_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_05_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_06_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_07_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_08_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_09_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_10_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_11_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_12_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_13_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_14_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_15_in = 1'b1; // tie off
assign BLI_SCAN_IN_00_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_01_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_02_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_03_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_04_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_05_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_06_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_07_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_08_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_09_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_10_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_11_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_12_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_13_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_14_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_15_in = 8'b11111111; // tie off
assign DBG_IN_00_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_01_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_02_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_03_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_04_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_05_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_06_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_07_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_08_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_09_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_10_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_11_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_12_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_13_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_14_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_15_in = 24'b111111111111111111111111; // tie off
assign DLL_SCAN_CK_00_in = 1'b1; // tie off
assign DLL_SCAN_ENABLE_00_in = 1'b1; // tie off
assign DLL_SCAN_IN_00_in = 2'b11; // tie off
assign DLL_SCAN_MODE_00_in = 1'b1; // tie off
assign DLL_SCAN_RST_N_00_in = 1'b1; // tie off
assign IO_SCAN_CK_00_in = 1'b1; // tie off
assign IO_SCAN_ENABLE_00_in = 1'b1; // tie off
assign IO_SCAN_IN_00_in = 2'b11; // tie off
assign IO_SCAN_MODE_00_in = 1'b1; // tie off
assign IO_SCAN_RST_N_00_in = 1'b1; // tie off
assign MC_SCAN_CK_00_in = 1'b1; // tie off
assign MC_SCAN_CK_01_in = 1'b1; // tie off
assign MC_SCAN_CK_02_in = 1'b1; // tie off
assign MC_SCAN_CK_03_in = 1'b1; // tie off
assign MC_SCAN_CK_04_in = 1'b1; // tie off
assign MC_SCAN_CK_05_in = 1'b1; // tie off
assign MC_SCAN_CK_06_in = 1'b1; // tie off
assign MC_SCAN_CK_07_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_00_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_01_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_02_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_03_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_04_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_05_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_06_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_07_in = 1'b1; // tie off
assign MC_SCAN_IN_00_in = 2'b11; // tie off
assign MC_SCAN_IN_01_in = 2'b11; // tie off
assign MC_SCAN_IN_02_in = 2'b11; // tie off
assign MC_SCAN_IN_03_in = 2'b11; // tie off
assign MC_SCAN_IN_04_in = 2'b11; // tie off
assign MC_SCAN_IN_05_in = 2'b11; // tie off
assign MC_SCAN_IN_06_in = 2'b11; // tie off
assign MC_SCAN_IN_07_in = 2'b11; // tie off
assign MC_SCAN_MODE_00_in = 1'b1; // tie off
assign MC_SCAN_MODE_01_in = 1'b1; // tie off
assign MC_SCAN_MODE_02_in = 1'b1; // tie off
assign MC_SCAN_MODE_03_in = 1'b1; // tie off
assign MC_SCAN_MODE_04_in = 1'b1; // tie off
assign MC_SCAN_MODE_05_in = 1'b1; // tie off
assign MC_SCAN_MODE_06_in = 1'b1; // tie off
assign MC_SCAN_MODE_07_in = 1'b1; // tie off
assign MC_SCAN_RST_N_00_in = 1'b1; // tie off
assign MC_SCAN_RST_N_01_in = 1'b1; // tie off
assign MC_SCAN_RST_N_02_in = 1'b1; // tie off
assign MC_SCAN_RST_N_03_in = 1'b1; // tie off
assign MC_SCAN_RST_N_04_in = 1'b1; // tie off
assign MC_SCAN_RST_N_05_in = 1'b1; // tie off
assign MC_SCAN_RST_N_06_in = 1'b1; // tie off
assign MC_SCAN_RST_N_07_in = 1'b1; // tie off
assign PHY_SCAN_CK_00_in = 1'b1; // tie off
assign PHY_SCAN_ENABLE_00_in = 1'b1; // tie off
assign PHY_SCAN_IN_00_in = 2'b11; // tie off
assign PHY_SCAN_MODE_00_in = 1'b1; // tie off
assign PHY_SCAN_RST_N_00_in = 1'b1; // tie off
assign SW_SCAN_CK_00_in = 1'b1; // tie off
assign SW_SCAN_ENABLE_00_in = 1'b1; // tie off
assign SW_SCAN_IN_00_in = 2'b11; // tie off
assign SW_SCAN_IN_01_in = 2'b11; // tie off
assign SW_SCAN_IN_02_in = 2'b11; // tie off
assign SW_SCAN_IN_03_in = 2'b11; // tie off
assign SW_SCAN_MODE_00_in = 1'b1; // tie off
assign SW_SCAN_RST_N_00_in = 1'b1; // tie off
SIP_HBM_ONE_STACK_INTF SIP_HBM_ONE_STACK_INTF_INST (
.ANALOG_MUX_SEL_0 (ANALOG_MUX_SEL_0_REG),
.APB_BYPASS_EN (APB_BYPASS_EN_REG),
.AXI_BYPASS_EN (AXI_BYPASS_EN_REG),
.BLI_TESTMODE_SEL (BLI_TESTMODE_SEL_REG),
.CLK_SEL_00 (CLK_SEL_00_REG),
.CLK_SEL_01 (CLK_SEL_01_REG),
.CLK_SEL_02 (CLK_SEL_02_REG),
.CLK_SEL_03 (CLK_SEL_03_REG),
.CLK_SEL_04 (CLK_SEL_04_REG),
.CLK_SEL_05 (CLK_SEL_05_REG),
.CLK_SEL_06 (CLK_SEL_06_REG),
.CLK_SEL_07 (CLK_SEL_07_REG),
.CLK_SEL_08 (CLK_SEL_08_REG),
.CLK_SEL_09 (CLK_SEL_09_REG),
.CLK_SEL_10 (CLK_SEL_10_REG),
.CLK_SEL_11 (CLK_SEL_11_REG),
.CLK_SEL_12 (CLK_SEL_12_REG),
.CLK_SEL_13 (CLK_SEL_13_REG),
.CLK_SEL_14 (CLK_SEL_14_REG),
.CLK_SEL_15 (CLK_SEL_15_REG),
.DATARATE_00 (DATARATE_00_REG),
.DATARATE_01 (DATARATE_01_REG),
.DATARATE_02 (DATARATE_02_REG),
.DATARATE_03 (DATARATE_03_REG),
.DATARATE_04 (DATARATE_04_REG),
.DATARATE_05 (DATARATE_05_REG),
.DATARATE_06 (DATARATE_06_REG),
.DATARATE_07 (DATARATE_07_REG),
.DA_LOCKOUT (DA_LOCKOUT_REG),
.DBG_BYPASS_VAL (DBG_BYPASS_VAL_REG),
.DEBUG_MODE (DEBUG_MODE_REG),
.DFI_BYPASS_VAL (DFI_BYPASS_VAL_REG),
.DLL_TESTMODE_SEL_0 (DLL_TESTMODE_SEL_0_REG),
.IO_TESTMODE_SEL_0 (IO_TESTMODE_SEL_0_REG),
.IS_APB_0_PCLK_INVERTED (IS_APB_0_PCLK_INVERTED_REG),
.IS_APB_0_PRESET_N_INVERTED (IS_APB_0_PRESET_N_INVERTED_REG),
.IS_AXI_00_ACLK_INVERTED (IS_AXI_00_ACLK_INVERTED_REG),
.IS_AXI_00_ARESET_N_INVERTED (IS_AXI_00_ARESET_N_INVERTED_REG),
.IS_AXI_01_ACLK_INVERTED (IS_AXI_01_ACLK_INVERTED_REG),
.IS_AXI_01_ARESET_N_INVERTED (IS_AXI_01_ARESET_N_INVERTED_REG),
.IS_AXI_02_ACLK_INVERTED (IS_AXI_02_ACLK_INVERTED_REG),
.IS_AXI_02_ARESET_N_INVERTED (IS_AXI_02_ARESET_N_INVERTED_REG),
.IS_AXI_03_ACLK_INVERTED (IS_AXI_03_ACLK_INVERTED_REG),
.IS_AXI_03_ARESET_N_INVERTED (IS_AXI_03_ARESET_N_INVERTED_REG),
.IS_AXI_04_ACLK_INVERTED (IS_AXI_04_ACLK_INVERTED_REG),
.IS_AXI_04_ARESET_N_INVERTED (IS_AXI_04_ARESET_N_INVERTED_REG),
.IS_AXI_05_ACLK_INVERTED (IS_AXI_05_ACLK_INVERTED_REG),
.IS_AXI_05_ARESET_N_INVERTED (IS_AXI_05_ARESET_N_INVERTED_REG),
.IS_AXI_06_ACLK_INVERTED (IS_AXI_06_ACLK_INVERTED_REG),
.IS_AXI_06_ARESET_N_INVERTED (IS_AXI_06_ARESET_N_INVERTED_REG),
.IS_AXI_07_ACLK_INVERTED (IS_AXI_07_ACLK_INVERTED_REG),
.IS_AXI_07_ARESET_N_INVERTED (IS_AXI_07_ARESET_N_INVERTED_REG),
.IS_AXI_08_ACLK_INVERTED (IS_AXI_08_ACLK_INVERTED_REG),
.IS_AXI_08_ARESET_N_INVERTED (IS_AXI_08_ARESET_N_INVERTED_REG),
.IS_AXI_09_ACLK_INVERTED (IS_AXI_09_ACLK_INVERTED_REG),
.IS_AXI_09_ARESET_N_INVERTED (IS_AXI_09_ARESET_N_INVERTED_REG),
.IS_AXI_10_ACLK_INVERTED (IS_AXI_10_ACLK_INVERTED_REG),
.IS_AXI_10_ARESET_N_INVERTED (IS_AXI_10_ARESET_N_INVERTED_REG),
.IS_AXI_11_ACLK_INVERTED (IS_AXI_11_ACLK_INVERTED_REG),
.IS_AXI_11_ARESET_N_INVERTED (IS_AXI_11_ARESET_N_INVERTED_REG),
.IS_AXI_12_ACLK_INVERTED (IS_AXI_12_ACLK_INVERTED_REG),
.IS_AXI_12_ARESET_N_INVERTED (IS_AXI_12_ARESET_N_INVERTED_REG),
.IS_AXI_13_ACLK_INVERTED (IS_AXI_13_ACLK_INVERTED_REG),
.IS_AXI_13_ARESET_N_INVERTED (IS_AXI_13_ARESET_N_INVERTED_REG),
.IS_AXI_14_ACLK_INVERTED (IS_AXI_14_ACLK_INVERTED_REG),
.IS_AXI_14_ARESET_N_INVERTED (IS_AXI_14_ARESET_N_INVERTED_REG),
.IS_AXI_15_ACLK_INVERTED (IS_AXI_15_ACLK_INVERTED_REG),
.IS_AXI_15_ARESET_N_INVERTED (IS_AXI_15_ARESET_N_INVERTED_REG),
.MC_CSSD_SEL_0 (MC_CSSD_SEL_0_REG),
.MC_CSSD_SEL_1 (MC_CSSD_SEL_1_REG),
.MC_CSSD_SEL_2 (MC_CSSD_SEL_2_REG),
.MC_CSSD_SEL_3 (MC_CSSD_SEL_3_REG),
.MC_CSSD_SEL_4 (MC_CSSD_SEL_4_REG),
.MC_CSSD_SEL_5 (MC_CSSD_SEL_5_REG),
.MC_CSSD_SEL_6 (MC_CSSD_SEL_6_REG),
.MC_CSSD_SEL_7 (MC_CSSD_SEL_7_REG),
.MC_ENABLE_0 (MC_ENABLE_0_REG),
.MC_ENABLE_1 (MC_ENABLE_1_REG),
.MC_ENABLE_2 (MC_ENABLE_2_REG),
.MC_ENABLE_3 (MC_ENABLE_3_REG),
.MC_ENABLE_4 (MC_ENABLE_4_REG),
.MC_ENABLE_5 (MC_ENABLE_5_REG),
.MC_ENABLE_6 (MC_ENABLE_6_REG),
.MC_ENABLE_7 (MC_ENABLE_7_REG),
.MC_ENABLE_APB (MC_ENABLE_APB_REG),
.MC_TESTMODE_SEL_0 (MC_TESTMODE_SEL_0_REG),
.MC_TESTMODE_SEL_1 (MC_TESTMODE_SEL_1_REG),
.MC_TESTMODE_SEL_2 (MC_TESTMODE_SEL_2_REG),
.MC_TESTMODE_SEL_3 (MC_TESTMODE_SEL_3_REG),
.MC_TESTMODE_SEL_4 (MC_TESTMODE_SEL_4_REG),
.MC_TESTMODE_SEL_5 (MC_TESTMODE_SEL_5_REG),
.MC_TESTMODE_SEL_6 (MC_TESTMODE_SEL_6_REG),
.MC_TESTMODE_SEL_7 (MC_TESTMODE_SEL_7_REG),
.PAGEHIT_PERCENT_00 (PAGEHIT_PERCENT_00_REG),
.PHY_CSSD_SEL_0 (PHY_CSSD_SEL_0_REG),
.PHY_ENABLE_00 (PHY_ENABLE_00_REG),
.PHY_ENABLE_01 (PHY_ENABLE_01_REG),
.PHY_ENABLE_02 (PHY_ENABLE_02_REG),
.PHY_ENABLE_03 (PHY_ENABLE_03_REG),
.PHY_ENABLE_04 (PHY_ENABLE_04_REG),
.PHY_ENABLE_05 (PHY_ENABLE_05_REG),
.PHY_ENABLE_06 (PHY_ENABLE_06_REG),
.PHY_ENABLE_07 (PHY_ENABLE_07_REG),
.PHY_ENABLE_08 (PHY_ENABLE_08_REG),
.PHY_ENABLE_09 (PHY_ENABLE_09_REG),
.PHY_ENABLE_10 (PHY_ENABLE_10_REG),
.PHY_ENABLE_11 (PHY_ENABLE_11_REG),
.PHY_ENABLE_12 (PHY_ENABLE_12_REG),
.PHY_ENABLE_13 (PHY_ENABLE_13_REG),
.PHY_ENABLE_14 (PHY_ENABLE_14_REG),
.PHY_ENABLE_15 (PHY_ENABLE_15_REG),
.PHY_ENABLE_APB (PHY_ENABLE_APB_REG),
.PHY_PCLK_INVERT_01 (PHY_PCLK_INVERT_01_REG),
.PHY_TESTMODE_SEL_0 (PHY_TESTMODE_SEL_0_REG),
.READ_PERCENT_00 (READ_PERCENT_00_REG),
.READ_PERCENT_01 (READ_PERCENT_01_REG),
.READ_PERCENT_02 (READ_PERCENT_02_REG),
.READ_PERCENT_03 (READ_PERCENT_03_REG),
.READ_PERCENT_04 (READ_PERCENT_04_REG),
.READ_PERCENT_05 (READ_PERCENT_05_REG),
.READ_PERCENT_06 (READ_PERCENT_06_REG),
.READ_PERCENT_07 (READ_PERCENT_07_REG),
.READ_PERCENT_08 (READ_PERCENT_08_REG),
.READ_PERCENT_09 (READ_PERCENT_09_REG),
.READ_PERCENT_10 (READ_PERCENT_10_REG),
.READ_PERCENT_11 (READ_PERCENT_11_REG),
.READ_PERCENT_12 (READ_PERCENT_12_REG),
.READ_PERCENT_13 (READ_PERCENT_13_REG),
.READ_PERCENT_14 (READ_PERCENT_14_REG),
.READ_PERCENT_15 (READ_PERCENT_15_REG),
.STACK_LOCATION (STACK_LOCATION_REG),
.SWITCH_ENABLE (SWITCH_ENABLE_REG),
.SW_TESTMODE_SEL_0 (SW_TESTMODE_SEL_0_REG),
.WRITE_PERCENT_00 (WRITE_PERCENT_00_REG),
.WRITE_PERCENT_01 (WRITE_PERCENT_01_REG),
.WRITE_PERCENT_02 (WRITE_PERCENT_02_REG),
.WRITE_PERCENT_03 (WRITE_PERCENT_03_REG),
.WRITE_PERCENT_04 (WRITE_PERCENT_04_REG),
.WRITE_PERCENT_05 (WRITE_PERCENT_05_REG),
.WRITE_PERCENT_06 (WRITE_PERCENT_06_REG),
.WRITE_PERCENT_07 (WRITE_PERCENT_07_REG),
.WRITE_PERCENT_08 (WRITE_PERCENT_08_REG),
.WRITE_PERCENT_09 (WRITE_PERCENT_09_REG),
.WRITE_PERCENT_10 (WRITE_PERCENT_10_REG),
.WRITE_PERCENT_11 (WRITE_PERCENT_11_REG),
.WRITE_PERCENT_12 (WRITE_PERCENT_12_REG),
.WRITE_PERCENT_13 (WRITE_PERCENT_13_REG),
.WRITE_PERCENT_14 (WRITE_PERCENT_14_REG),
.WRITE_PERCENT_15 (WRITE_PERCENT_15_REG),
.APB_0_PRDATA (APB_0_PRDATA_out),
.APB_0_PREADY (APB_0_PREADY_out),
.APB_0_PSLVERR (APB_0_PSLVERR_out),
.AXI_00_ARREADY (AXI_00_ARREADY_out),
.AXI_00_AWREADY (AXI_00_AWREADY_out),
.AXI_00_BID (AXI_00_BID_out),
.AXI_00_BRESP (AXI_00_BRESP_out),
.AXI_00_BVALID (AXI_00_BVALID_out),
.AXI_00_DFI_AW_AERR_N (AXI_00_DFI_AW_AERR_N_out),
.AXI_00_DFI_CLK_BUF (AXI_00_DFI_CLK_BUF_out),
.AXI_00_DFI_DBI_BYTE_DISABLE (AXI_00_DFI_DBI_BYTE_DISABLE_out),
.AXI_00_DFI_DW_RDDATA_DBI (AXI_00_DFI_DW_RDDATA_DBI_out),
.AXI_00_DFI_DW_RDDATA_DERR (AXI_00_DFI_DW_RDDATA_DERR_out),
.AXI_00_DFI_DW_RDDATA_VALID (AXI_00_DFI_DW_RDDATA_VALID_out),
.AXI_00_DFI_INIT_COMPLETE (AXI_00_DFI_INIT_COMPLETE_out),
.AXI_00_DFI_PHYUPD_REQ (AXI_00_DFI_PHYUPD_REQ_out),
.AXI_00_DFI_PHY_LP_STATE (AXI_00_DFI_PHY_LP_STATE_out),
.AXI_00_DFI_RST_N_BUF (AXI_00_DFI_RST_N_BUF_out),
.AXI_00_MC_STATUS (AXI_00_MC_STATUS_out),
.AXI_00_PHY_STATUS (AXI_00_PHY_STATUS_out),
.AXI_00_RDATA (AXI_00_RDATA_out),
.AXI_00_RDATA_PARITY (AXI_00_RDATA_PARITY_out),
.AXI_00_RID (AXI_00_RID_out),
.AXI_00_RLAST (AXI_00_RLAST_out),
.AXI_00_RRESP (AXI_00_RRESP_out),
.AXI_00_RVALID (AXI_00_RVALID_out),
.AXI_00_WREADY (AXI_00_WREADY_out),
.AXI_01_ARREADY (AXI_01_ARREADY_out),
.AXI_01_AWREADY (AXI_01_AWREADY_out),
.AXI_01_BID (AXI_01_BID_out),
.AXI_01_BRESP (AXI_01_BRESP_out),
.AXI_01_BVALID (AXI_01_BVALID_out),
.AXI_01_DFI_AW_AERR_N (AXI_01_DFI_AW_AERR_N_out),
.AXI_01_DFI_CLK_BUF (AXI_01_DFI_CLK_BUF_out),
.AXI_01_DFI_DBI_BYTE_DISABLE (AXI_01_DFI_DBI_BYTE_DISABLE_out),
.AXI_01_DFI_DW_RDDATA_DBI (AXI_01_DFI_DW_RDDATA_DBI_out),
.AXI_01_DFI_DW_RDDATA_DERR (AXI_01_DFI_DW_RDDATA_DERR_out),
.AXI_01_DFI_DW_RDDATA_VALID (AXI_01_DFI_DW_RDDATA_VALID_out),
.AXI_01_DFI_INIT_COMPLETE (AXI_01_DFI_INIT_COMPLETE_out),
.AXI_01_DFI_PHYUPD_REQ (AXI_01_DFI_PHYUPD_REQ_out),
.AXI_01_DFI_PHY_LP_STATE (AXI_01_DFI_PHY_LP_STATE_out),
.AXI_01_DFI_RST_N_BUF (AXI_01_DFI_RST_N_BUF_out),
.AXI_01_RDATA (AXI_01_RDATA_out),
.AXI_01_RDATA_PARITY (AXI_01_RDATA_PARITY_out),
.AXI_01_RID (AXI_01_RID_out),
.AXI_01_RLAST (AXI_01_RLAST_out),
.AXI_01_RRESP (AXI_01_RRESP_out),
.AXI_01_RVALID (AXI_01_RVALID_out),
.AXI_01_WREADY (AXI_01_WREADY_out),
.AXI_02_ARREADY (AXI_02_ARREADY_out),
.AXI_02_AWREADY (AXI_02_AWREADY_out),
.AXI_02_BID (AXI_02_BID_out),
.AXI_02_BRESP (AXI_02_BRESP_out),
.AXI_02_BVALID (AXI_02_BVALID_out),
.AXI_02_DFI_AW_AERR_N (AXI_02_DFI_AW_AERR_N_out),
.AXI_02_DFI_CLK_BUF (AXI_02_DFI_CLK_BUF_out),
.AXI_02_DFI_DBI_BYTE_DISABLE (AXI_02_DFI_DBI_BYTE_DISABLE_out),
.AXI_02_DFI_DW_RDDATA_DBI (AXI_02_DFI_DW_RDDATA_DBI_out),
.AXI_02_DFI_DW_RDDATA_DERR (AXI_02_DFI_DW_RDDATA_DERR_out),
.AXI_02_DFI_DW_RDDATA_VALID (AXI_02_DFI_DW_RDDATA_VALID_out),
.AXI_02_DFI_INIT_COMPLETE (AXI_02_DFI_INIT_COMPLETE_out),
.AXI_02_DFI_PHYUPD_REQ (AXI_02_DFI_PHYUPD_REQ_out),
.AXI_02_DFI_PHY_LP_STATE (AXI_02_DFI_PHY_LP_STATE_out),
.AXI_02_DFI_RST_N_BUF (AXI_02_DFI_RST_N_BUF_out),
.AXI_02_MC_STATUS (AXI_02_MC_STATUS_out),
.AXI_02_PHY_STATUS (AXI_02_PHY_STATUS_out),
.AXI_02_RDATA (AXI_02_RDATA_out),
.AXI_02_RDATA_PARITY (AXI_02_RDATA_PARITY_out),
.AXI_02_RID (AXI_02_RID_out),
.AXI_02_RLAST (AXI_02_RLAST_out),
.AXI_02_RRESP (AXI_02_RRESP_out),
.AXI_02_RVALID (AXI_02_RVALID_out),
.AXI_02_WREADY (AXI_02_WREADY_out),
.AXI_03_ARREADY (AXI_03_ARREADY_out),
.AXI_03_AWREADY (AXI_03_AWREADY_out),
.AXI_03_BID (AXI_03_BID_out),
.AXI_03_BRESP (AXI_03_BRESP_out),
.AXI_03_BVALID (AXI_03_BVALID_out),
.AXI_03_DFI_AW_AERR_N (AXI_03_DFI_AW_AERR_N_out),
.AXI_03_DFI_CLK_BUF (AXI_03_DFI_CLK_BUF_out),
.AXI_03_DFI_DBI_BYTE_DISABLE (AXI_03_DFI_DBI_BYTE_DISABLE_out),
.AXI_03_DFI_DW_RDDATA_DBI (AXI_03_DFI_DW_RDDATA_DBI_out),
.AXI_03_DFI_DW_RDDATA_DERR (AXI_03_DFI_DW_RDDATA_DERR_out),
.AXI_03_DFI_DW_RDDATA_VALID (AXI_03_DFI_DW_RDDATA_VALID_out),
.AXI_03_DFI_INIT_COMPLETE (AXI_03_DFI_INIT_COMPLETE_out),
.AXI_03_DFI_PHYUPD_REQ (AXI_03_DFI_PHYUPD_REQ_out),
.AXI_03_DFI_PHY_LP_STATE (AXI_03_DFI_PHY_LP_STATE_out),
.AXI_03_DFI_RST_N_BUF (AXI_03_DFI_RST_N_BUF_out),
.AXI_03_RDATA (AXI_03_RDATA_out),
.AXI_03_RDATA_PARITY (AXI_03_RDATA_PARITY_out),
.AXI_03_RID (AXI_03_RID_out),
.AXI_03_RLAST (AXI_03_RLAST_out),
.AXI_03_RRESP (AXI_03_RRESP_out),
.AXI_03_RVALID (AXI_03_RVALID_out),
.AXI_03_WREADY (AXI_03_WREADY_out),
.AXI_04_ARREADY (AXI_04_ARREADY_out),
.AXI_04_AWREADY (AXI_04_AWREADY_out),
.AXI_04_BID (AXI_04_BID_out),
.AXI_04_BRESP (AXI_04_BRESP_out),
.AXI_04_BVALID (AXI_04_BVALID_out),
.AXI_04_DFI_AW_AERR_N (AXI_04_DFI_AW_AERR_N_out),
.AXI_04_DFI_CLK_BUF (AXI_04_DFI_CLK_BUF_out),
.AXI_04_DFI_DBI_BYTE_DISABLE (AXI_04_DFI_DBI_BYTE_DISABLE_out),
.AXI_04_DFI_DW_RDDATA_DBI (AXI_04_DFI_DW_RDDATA_DBI_out),
.AXI_04_DFI_DW_RDDATA_DERR (AXI_04_DFI_DW_RDDATA_DERR_out),
.AXI_04_DFI_DW_RDDATA_VALID (AXI_04_DFI_DW_RDDATA_VALID_out),
.AXI_04_DFI_INIT_COMPLETE (AXI_04_DFI_INIT_COMPLETE_out),
.AXI_04_DFI_PHYUPD_REQ (AXI_04_DFI_PHYUPD_REQ_out),
.AXI_04_DFI_PHY_LP_STATE (AXI_04_DFI_PHY_LP_STATE_out),
.AXI_04_DFI_RST_N_BUF (AXI_04_DFI_RST_N_BUF_out),
.AXI_04_MC_STATUS (AXI_04_MC_STATUS_out),
.AXI_04_PHY_STATUS (AXI_04_PHY_STATUS_out),
.AXI_04_RDATA (AXI_04_RDATA_out),
.AXI_04_RDATA_PARITY (AXI_04_RDATA_PARITY_out),
.AXI_04_RID (AXI_04_RID_out),
.AXI_04_RLAST (AXI_04_RLAST_out),
.AXI_04_RRESP (AXI_04_RRESP_out),
.AXI_04_RVALID (AXI_04_RVALID_out),
.AXI_04_WREADY (AXI_04_WREADY_out),
.AXI_05_ARREADY (AXI_05_ARREADY_out),
.AXI_05_AWREADY (AXI_05_AWREADY_out),
.AXI_05_BID (AXI_05_BID_out),
.AXI_05_BRESP (AXI_05_BRESP_out),
.AXI_05_BVALID (AXI_05_BVALID_out),
.AXI_05_DFI_AW_AERR_N (AXI_05_DFI_AW_AERR_N_out),
.AXI_05_DFI_CLK_BUF (AXI_05_DFI_CLK_BUF_out),
.AXI_05_DFI_DBI_BYTE_DISABLE (AXI_05_DFI_DBI_BYTE_DISABLE_out),
.AXI_05_DFI_DW_RDDATA_DBI (AXI_05_DFI_DW_RDDATA_DBI_out),
.AXI_05_DFI_DW_RDDATA_DERR (AXI_05_DFI_DW_RDDATA_DERR_out),
.AXI_05_DFI_DW_RDDATA_VALID (AXI_05_DFI_DW_RDDATA_VALID_out),
.AXI_05_DFI_INIT_COMPLETE (AXI_05_DFI_INIT_COMPLETE_out),
.AXI_05_DFI_PHYUPD_REQ (AXI_05_DFI_PHYUPD_REQ_out),
.AXI_05_DFI_PHY_LP_STATE (AXI_05_DFI_PHY_LP_STATE_out),
.AXI_05_DFI_RST_N_BUF (AXI_05_DFI_RST_N_BUF_out),
.AXI_05_RDATA (AXI_05_RDATA_out),
.AXI_05_RDATA_PARITY (AXI_05_RDATA_PARITY_out),
.AXI_05_RID (AXI_05_RID_out),
.AXI_05_RLAST (AXI_05_RLAST_out),
.AXI_05_RRESP (AXI_05_RRESP_out),
.AXI_05_RVALID (AXI_05_RVALID_out),
.AXI_05_WREADY (AXI_05_WREADY_out),
.AXI_06_ARREADY (AXI_06_ARREADY_out),
.AXI_06_AWREADY (AXI_06_AWREADY_out),
.AXI_06_BID (AXI_06_BID_out),
.AXI_06_BRESP (AXI_06_BRESP_out),
.AXI_06_BVALID (AXI_06_BVALID_out),
.AXI_06_DFI_AW_AERR_N (AXI_06_DFI_AW_AERR_N_out),
.AXI_06_DFI_CLK_BUF (AXI_06_DFI_CLK_BUF_out),
.AXI_06_DFI_DBI_BYTE_DISABLE (AXI_06_DFI_DBI_BYTE_DISABLE_out),
.AXI_06_DFI_DW_RDDATA_DBI (AXI_06_DFI_DW_RDDATA_DBI_out),
.AXI_06_DFI_DW_RDDATA_DERR (AXI_06_DFI_DW_RDDATA_DERR_out),
.AXI_06_DFI_DW_RDDATA_VALID (AXI_06_DFI_DW_RDDATA_VALID_out),
.AXI_06_DFI_INIT_COMPLETE (AXI_06_DFI_INIT_COMPLETE_out),
.AXI_06_DFI_PHYUPD_REQ (AXI_06_DFI_PHYUPD_REQ_out),
.AXI_06_DFI_PHY_LP_STATE (AXI_06_DFI_PHY_LP_STATE_out),
.AXI_06_DFI_RST_N_BUF (AXI_06_DFI_RST_N_BUF_out),
.AXI_06_MC_STATUS (AXI_06_MC_STATUS_out),
.AXI_06_PHY_STATUS (AXI_06_PHY_STATUS_out),
.AXI_06_RDATA (AXI_06_RDATA_out),
.AXI_06_RDATA_PARITY (AXI_06_RDATA_PARITY_out),
.AXI_06_RID (AXI_06_RID_out),
.AXI_06_RLAST (AXI_06_RLAST_out),
.AXI_06_RRESP (AXI_06_RRESP_out),
.AXI_06_RVALID (AXI_06_RVALID_out),
.AXI_06_WREADY (AXI_06_WREADY_out),
.AXI_07_ARREADY (AXI_07_ARREADY_out),
.AXI_07_AWREADY (AXI_07_AWREADY_out),
.AXI_07_BID (AXI_07_BID_out),
.AXI_07_BRESP (AXI_07_BRESP_out),
.AXI_07_BVALID (AXI_07_BVALID_out),
.AXI_07_DFI_AW_AERR_N (AXI_07_DFI_AW_AERR_N_out),
.AXI_07_DFI_CLK_BUF (AXI_07_DFI_CLK_BUF_out),
.AXI_07_DFI_DBI_BYTE_DISABLE (AXI_07_DFI_DBI_BYTE_DISABLE_out),
.AXI_07_DFI_DW_RDDATA_DBI (AXI_07_DFI_DW_RDDATA_DBI_out),
.AXI_07_DFI_DW_RDDATA_DERR (AXI_07_DFI_DW_RDDATA_DERR_out),
.AXI_07_DFI_DW_RDDATA_VALID (AXI_07_DFI_DW_RDDATA_VALID_out),
.AXI_07_DFI_INIT_COMPLETE (AXI_07_DFI_INIT_COMPLETE_out),
.AXI_07_DFI_PHYUPD_REQ (AXI_07_DFI_PHYUPD_REQ_out),
.AXI_07_DFI_PHY_LP_STATE (AXI_07_DFI_PHY_LP_STATE_out),
.AXI_07_DFI_RST_N_BUF (AXI_07_DFI_RST_N_BUF_out),
.AXI_07_RDATA (AXI_07_RDATA_out),
.AXI_07_RDATA_PARITY (AXI_07_RDATA_PARITY_out),
.AXI_07_RID (AXI_07_RID_out),
.AXI_07_RLAST (AXI_07_RLAST_out),
.AXI_07_RRESP (AXI_07_RRESP_out),
.AXI_07_RVALID (AXI_07_RVALID_out),
.AXI_07_WREADY (AXI_07_WREADY_out),
.AXI_08_ARREADY (AXI_08_ARREADY_out),
.AXI_08_AWREADY (AXI_08_AWREADY_out),
.AXI_08_BID (AXI_08_BID_out),
.AXI_08_BRESP (AXI_08_BRESP_out),
.AXI_08_BVALID (AXI_08_BVALID_out),
.AXI_08_DFI_AW_AERR_N (AXI_08_DFI_AW_AERR_N_out),
.AXI_08_DFI_CLK_BUF (AXI_08_DFI_CLK_BUF_out),
.AXI_08_DFI_DBI_BYTE_DISABLE (AXI_08_DFI_DBI_BYTE_DISABLE_out),
.AXI_08_DFI_DW_RDDATA_DBI (AXI_08_DFI_DW_RDDATA_DBI_out),
.AXI_08_DFI_DW_RDDATA_DERR (AXI_08_DFI_DW_RDDATA_DERR_out),
.AXI_08_DFI_DW_RDDATA_VALID (AXI_08_DFI_DW_RDDATA_VALID_out),
.AXI_08_DFI_INIT_COMPLETE (AXI_08_DFI_INIT_COMPLETE_out),
.AXI_08_DFI_PHYUPD_REQ (AXI_08_DFI_PHYUPD_REQ_out),
.AXI_08_DFI_PHY_LP_STATE (AXI_08_DFI_PHY_LP_STATE_out),
.AXI_08_DFI_RST_N_BUF (AXI_08_DFI_RST_N_BUF_out),
.AXI_08_MC_STATUS (AXI_08_MC_STATUS_out),
.AXI_08_PHY_STATUS (AXI_08_PHY_STATUS_out),
.AXI_08_RDATA (AXI_08_RDATA_out),
.AXI_08_RDATA_PARITY (AXI_08_RDATA_PARITY_out),
.AXI_08_RID (AXI_08_RID_out),
.AXI_08_RLAST (AXI_08_RLAST_out),
.AXI_08_RRESP (AXI_08_RRESP_out),
.AXI_08_RVALID (AXI_08_RVALID_out),
.AXI_08_WREADY (AXI_08_WREADY_out),
.AXI_09_ARREADY (AXI_09_ARREADY_out),
.AXI_09_AWREADY (AXI_09_AWREADY_out),
.AXI_09_BID (AXI_09_BID_out),
.AXI_09_BRESP (AXI_09_BRESP_out),
.AXI_09_BVALID (AXI_09_BVALID_out),
.AXI_09_DFI_AW_AERR_N (AXI_09_DFI_AW_AERR_N_out),
.AXI_09_DFI_CLK_BUF (AXI_09_DFI_CLK_BUF_out),
.AXI_09_DFI_DBI_BYTE_DISABLE (AXI_09_DFI_DBI_BYTE_DISABLE_out),
.AXI_09_DFI_DW_RDDATA_DBI (AXI_09_DFI_DW_RDDATA_DBI_out),
.AXI_09_DFI_DW_RDDATA_DERR (AXI_09_DFI_DW_RDDATA_DERR_out),
.AXI_09_DFI_DW_RDDATA_VALID (AXI_09_DFI_DW_RDDATA_VALID_out),
.AXI_09_DFI_INIT_COMPLETE (AXI_09_DFI_INIT_COMPLETE_out),
.AXI_09_DFI_PHYUPD_REQ (AXI_09_DFI_PHYUPD_REQ_out),
.AXI_09_DFI_PHY_LP_STATE (AXI_09_DFI_PHY_LP_STATE_out),
.AXI_09_DFI_RST_N_BUF (AXI_09_DFI_RST_N_BUF_out),
.AXI_09_RDATA (AXI_09_RDATA_out),
.AXI_09_RDATA_PARITY (AXI_09_RDATA_PARITY_out),
.AXI_09_RID (AXI_09_RID_out),
.AXI_09_RLAST (AXI_09_RLAST_out),
.AXI_09_RRESP (AXI_09_RRESP_out),
.AXI_09_RVALID (AXI_09_RVALID_out),
.AXI_09_WREADY (AXI_09_WREADY_out),
.AXI_10_ARREADY (AXI_10_ARREADY_out),
.AXI_10_AWREADY (AXI_10_AWREADY_out),
.AXI_10_BID (AXI_10_BID_out),
.AXI_10_BRESP (AXI_10_BRESP_out),
.AXI_10_BVALID (AXI_10_BVALID_out),
.AXI_10_DFI_AW_AERR_N (AXI_10_DFI_AW_AERR_N_out),
.AXI_10_DFI_CLK_BUF (AXI_10_DFI_CLK_BUF_out),
.AXI_10_DFI_DBI_BYTE_DISABLE (AXI_10_DFI_DBI_BYTE_DISABLE_out),
.AXI_10_DFI_DW_RDDATA_DBI (AXI_10_DFI_DW_RDDATA_DBI_out),
.AXI_10_DFI_DW_RDDATA_DERR (AXI_10_DFI_DW_RDDATA_DERR_out),
.AXI_10_DFI_DW_RDDATA_VALID (AXI_10_DFI_DW_RDDATA_VALID_out),
.AXI_10_DFI_INIT_COMPLETE (AXI_10_DFI_INIT_COMPLETE_out),
.AXI_10_DFI_PHYUPD_REQ (AXI_10_DFI_PHYUPD_REQ_out),
.AXI_10_DFI_PHY_LP_STATE (AXI_10_DFI_PHY_LP_STATE_out),
.AXI_10_DFI_RST_N_BUF (AXI_10_DFI_RST_N_BUF_out),
.AXI_10_MC_STATUS (AXI_10_MC_STATUS_out),
.AXI_10_PHY_STATUS (AXI_10_PHY_STATUS_out),
.AXI_10_RDATA (AXI_10_RDATA_out),
.AXI_10_RDATA_PARITY (AXI_10_RDATA_PARITY_out),
.AXI_10_RID (AXI_10_RID_out),
.AXI_10_RLAST (AXI_10_RLAST_out),
.AXI_10_RRESP (AXI_10_RRESP_out),
.AXI_10_RVALID (AXI_10_RVALID_out),
.AXI_10_WREADY (AXI_10_WREADY_out),
.AXI_11_ARREADY (AXI_11_ARREADY_out),
.AXI_11_AWREADY (AXI_11_AWREADY_out),
.AXI_11_BID (AXI_11_BID_out),
.AXI_11_BRESP (AXI_11_BRESP_out),
.AXI_11_BVALID (AXI_11_BVALID_out),
.AXI_11_DFI_AW_AERR_N (AXI_11_DFI_AW_AERR_N_out),
.AXI_11_DFI_CLK_BUF (AXI_11_DFI_CLK_BUF_out),
.AXI_11_DFI_DBI_BYTE_DISABLE (AXI_11_DFI_DBI_BYTE_DISABLE_out),
.AXI_11_DFI_DW_RDDATA_DBI (AXI_11_DFI_DW_RDDATA_DBI_out),
.AXI_11_DFI_DW_RDDATA_DERR (AXI_11_DFI_DW_RDDATA_DERR_out),
.AXI_11_DFI_DW_RDDATA_VALID (AXI_11_DFI_DW_RDDATA_VALID_out),
.AXI_11_DFI_INIT_COMPLETE (AXI_11_DFI_INIT_COMPLETE_out),
.AXI_11_DFI_PHYUPD_REQ (AXI_11_DFI_PHYUPD_REQ_out),
.AXI_11_DFI_PHY_LP_STATE (AXI_11_DFI_PHY_LP_STATE_out),
.AXI_11_DFI_RST_N_BUF (AXI_11_DFI_RST_N_BUF_out),
.AXI_11_RDATA (AXI_11_RDATA_out),
.AXI_11_RDATA_PARITY (AXI_11_RDATA_PARITY_out),
.AXI_11_RID (AXI_11_RID_out),
.AXI_11_RLAST (AXI_11_RLAST_out),
.AXI_11_RRESP (AXI_11_RRESP_out),
.AXI_11_RVALID (AXI_11_RVALID_out),
.AXI_11_WREADY (AXI_11_WREADY_out),
.AXI_12_ARREADY (AXI_12_ARREADY_out),
.AXI_12_AWREADY (AXI_12_AWREADY_out),
.AXI_12_BID (AXI_12_BID_out),
.AXI_12_BRESP (AXI_12_BRESP_out),
.AXI_12_BVALID (AXI_12_BVALID_out),
.AXI_12_DFI_AW_AERR_N (AXI_12_DFI_AW_AERR_N_out),
.AXI_12_DFI_CLK_BUF (AXI_12_DFI_CLK_BUF_out),
.AXI_12_DFI_DBI_BYTE_DISABLE (AXI_12_DFI_DBI_BYTE_DISABLE_out),
.AXI_12_DFI_DW_RDDATA_DBI (AXI_12_DFI_DW_RDDATA_DBI_out),
.AXI_12_DFI_DW_RDDATA_DERR (AXI_12_DFI_DW_RDDATA_DERR_out),
.AXI_12_DFI_DW_RDDATA_VALID (AXI_12_DFI_DW_RDDATA_VALID_out),
.AXI_12_DFI_INIT_COMPLETE (AXI_12_DFI_INIT_COMPLETE_out),
.AXI_12_DFI_PHYUPD_REQ (AXI_12_DFI_PHYUPD_REQ_out),
.AXI_12_DFI_PHY_LP_STATE (AXI_12_DFI_PHY_LP_STATE_out),
.AXI_12_DFI_RST_N_BUF (AXI_12_DFI_RST_N_BUF_out),
.AXI_12_MC_STATUS (AXI_12_MC_STATUS_out),
.AXI_12_PHY_STATUS (AXI_12_PHY_STATUS_out),
.AXI_12_RDATA (AXI_12_RDATA_out),
.AXI_12_RDATA_PARITY (AXI_12_RDATA_PARITY_out),
.AXI_12_RID (AXI_12_RID_out),
.AXI_12_RLAST (AXI_12_RLAST_out),
.AXI_12_RRESP (AXI_12_RRESP_out),
.AXI_12_RVALID (AXI_12_RVALID_out),
.AXI_12_WREADY (AXI_12_WREADY_out),
.AXI_13_ARREADY (AXI_13_ARREADY_out),
.AXI_13_AWREADY (AXI_13_AWREADY_out),
.AXI_13_BID (AXI_13_BID_out),
.AXI_13_BRESP (AXI_13_BRESP_out),
.AXI_13_BVALID (AXI_13_BVALID_out),
.AXI_13_DFI_AW_AERR_N (AXI_13_DFI_AW_AERR_N_out),
.AXI_13_DFI_CLK_BUF (AXI_13_DFI_CLK_BUF_out),
.AXI_13_DFI_DBI_BYTE_DISABLE (AXI_13_DFI_DBI_BYTE_DISABLE_out),
.AXI_13_DFI_DW_RDDATA_DBI (AXI_13_DFI_DW_RDDATA_DBI_out),
.AXI_13_DFI_DW_RDDATA_DERR (AXI_13_DFI_DW_RDDATA_DERR_out),
.AXI_13_DFI_DW_RDDATA_VALID (AXI_13_DFI_DW_RDDATA_VALID_out),
.AXI_13_DFI_INIT_COMPLETE (AXI_13_DFI_INIT_COMPLETE_out),
.AXI_13_DFI_PHYUPD_REQ (AXI_13_DFI_PHYUPD_REQ_out),
.AXI_13_DFI_PHY_LP_STATE (AXI_13_DFI_PHY_LP_STATE_out),
.AXI_13_DFI_RST_N_BUF (AXI_13_DFI_RST_N_BUF_out),
.AXI_13_RDATA (AXI_13_RDATA_out),
.AXI_13_RDATA_PARITY (AXI_13_RDATA_PARITY_out),
.AXI_13_RID (AXI_13_RID_out),
.AXI_13_RLAST (AXI_13_RLAST_out),
.AXI_13_RRESP (AXI_13_RRESP_out),
.AXI_13_RVALID (AXI_13_RVALID_out),
.AXI_13_WREADY (AXI_13_WREADY_out),
.AXI_14_ARREADY (AXI_14_ARREADY_out),
.AXI_14_AWREADY (AXI_14_AWREADY_out),
.AXI_14_BID (AXI_14_BID_out),
.AXI_14_BRESP (AXI_14_BRESP_out),
.AXI_14_BVALID (AXI_14_BVALID_out),
.AXI_14_DFI_AW_AERR_N (AXI_14_DFI_AW_AERR_N_out),
.AXI_14_DFI_CLK_BUF (AXI_14_DFI_CLK_BUF_out),
.AXI_14_DFI_DBI_BYTE_DISABLE (AXI_14_DFI_DBI_BYTE_DISABLE_out),
.AXI_14_DFI_DW_RDDATA_DBI (AXI_14_DFI_DW_RDDATA_DBI_out),
.AXI_14_DFI_DW_RDDATA_DERR (AXI_14_DFI_DW_RDDATA_DERR_out),
.AXI_14_DFI_DW_RDDATA_VALID (AXI_14_DFI_DW_RDDATA_VALID_out),
.AXI_14_DFI_INIT_COMPLETE (AXI_14_DFI_INIT_COMPLETE_out),
.AXI_14_DFI_PHYUPD_REQ (AXI_14_DFI_PHYUPD_REQ_out),
.AXI_14_DFI_PHY_LP_STATE (AXI_14_DFI_PHY_LP_STATE_out),
.AXI_14_DFI_RST_N_BUF (AXI_14_DFI_RST_N_BUF_out),
.AXI_14_MC_STATUS (AXI_14_MC_STATUS_out),
.AXI_14_PHY_STATUS (AXI_14_PHY_STATUS_out),
.AXI_14_RDATA (AXI_14_RDATA_out),
.AXI_14_RDATA_PARITY (AXI_14_RDATA_PARITY_out),
.AXI_14_RID (AXI_14_RID_out),
.AXI_14_RLAST (AXI_14_RLAST_out),
.AXI_14_RRESP (AXI_14_RRESP_out),
.AXI_14_RVALID (AXI_14_RVALID_out),
.AXI_14_WREADY (AXI_14_WREADY_out),
.AXI_15_ARREADY (AXI_15_ARREADY_out),
.AXI_15_AWREADY (AXI_15_AWREADY_out),
.AXI_15_BID (AXI_15_BID_out),
.AXI_15_BRESP (AXI_15_BRESP_out),
.AXI_15_BVALID (AXI_15_BVALID_out),
.AXI_15_DFI_AW_AERR_N (AXI_15_DFI_AW_AERR_N_out),
.AXI_15_DFI_CLK_BUF (AXI_15_DFI_CLK_BUF_out),
.AXI_15_DFI_DBI_BYTE_DISABLE (AXI_15_DFI_DBI_BYTE_DISABLE_out),
.AXI_15_DFI_DW_RDDATA_DBI (AXI_15_DFI_DW_RDDATA_DBI_out),
.AXI_15_DFI_DW_RDDATA_DERR (AXI_15_DFI_DW_RDDATA_DERR_out),
.AXI_15_DFI_DW_RDDATA_VALID (AXI_15_DFI_DW_RDDATA_VALID_out),
.AXI_15_DFI_INIT_COMPLETE (AXI_15_DFI_INIT_COMPLETE_out),
.AXI_15_DFI_PHYUPD_REQ (AXI_15_DFI_PHYUPD_REQ_out),
.AXI_15_DFI_PHY_LP_STATE (AXI_15_DFI_PHY_LP_STATE_out),
.AXI_15_DFI_RST_N_BUF (AXI_15_DFI_RST_N_BUF_out),
.AXI_15_RDATA (AXI_15_RDATA_out),
.AXI_15_RDATA_PARITY (AXI_15_RDATA_PARITY_out),
.AXI_15_RID (AXI_15_RID_out),
.AXI_15_RLAST (AXI_15_RLAST_out),
.AXI_15_RRESP (AXI_15_RRESP_out),
.AXI_15_RVALID (AXI_15_RVALID_out),
.AXI_15_WREADY (AXI_15_WREADY_out),
.BLI_SCAN_OUT_00 (BLI_SCAN_OUT_00_out),
.BLI_SCAN_OUT_01 (BLI_SCAN_OUT_01_out),
.BLI_SCAN_OUT_02 (BLI_SCAN_OUT_02_out),
.BLI_SCAN_OUT_03 (BLI_SCAN_OUT_03_out),
.BLI_SCAN_OUT_04 (BLI_SCAN_OUT_04_out),
.BLI_SCAN_OUT_05 (BLI_SCAN_OUT_05_out),
.BLI_SCAN_OUT_06 (BLI_SCAN_OUT_06_out),
.BLI_SCAN_OUT_07 (BLI_SCAN_OUT_07_out),
.BLI_SCAN_OUT_08 (BLI_SCAN_OUT_08_out),
.BLI_SCAN_OUT_09 (BLI_SCAN_OUT_09_out),
.BLI_SCAN_OUT_10 (BLI_SCAN_OUT_10_out),
.BLI_SCAN_OUT_11 (BLI_SCAN_OUT_11_out),
.BLI_SCAN_OUT_12 (BLI_SCAN_OUT_12_out),
.BLI_SCAN_OUT_13 (BLI_SCAN_OUT_13_out),
.BLI_SCAN_OUT_14 (BLI_SCAN_OUT_14_out),
.BLI_SCAN_OUT_15 (BLI_SCAN_OUT_15_out),
.DBG_OUT_00 (DBG_OUT_00_out),
.DBG_OUT_01 (DBG_OUT_01_out),
.DBG_OUT_02 (DBG_OUT_02_out),
.DBG_OUT_03 (DBG_OUT_03_out),
.DBG_OUT_04 (DBG_OUT_04_out),
.DBG_OUT_05 (DBG_OUT_05_out),
.DBG_OUT_06 (DBG_OUT_06_out),
.DBG_OUT_07 (DBG_OUT_07_out),
.DBG_OUT_08 (DBG_OUT_08_out),
.DBG_OUT_09 (DBG_OUT_09_out),
.DBG_OUT_10 (DBG_OUT_10_out),
.DBG_OUT_11 (DBG_OUT_11_out),
.DBG_OUT_12 (DBG_OUT_12_out),
.DBG_OUT_13 (DBG_OUT_13_out),
.DBG_OUT_14 (DBG_OUT_14_out),
.DBG_OUT_15 (DBG_OUT_15_out),
.DLL_SCAN_OUT_00 (DLL_SCAN_OUT_00_out),
.DRAM_0_STAT_CATTRIP (DRAM_0_STAT_CATTRIP_out),
.DRAM_0_STAT_TEMP (DRAM_0_STAT_TEMP_out),
.IO_SCAN_OUT_00 (IO_SCAN_OUT_00_out),
.MC_SCAN_OUT_00 (MC_SCAN_OUT_00_out),
.MC_SCAN_OUT_01 (MC_SCAN_OUT_01_out),
.MC_SCAN_OUT_02 (MC_SCAN_OUT_02_out),
.MC_SCAN_OUT_03 (MC_SCAN_OUT_03_out),
.MC_SCAN_OUT_04 (MC_SCAN_OUT_04_out),
.MC_SCAN_OUT_05 (MC_SCAN_OUT_05_out),
.MC_SCAN_OUT_06 (MC_SCAN_OUT_06_out),
.MC_SCAN_OUT_07 (MC_SCAN_OUT_07_out),
.PHY_SCAN_OUT_00 (PHY_SCAN_OUT_00_out),
.STATUS_00 (STATUS_00_out),
.STATUS_01 (STATUS_01_out),
.STATUS_02 (STATUS_02_out),
.STATUS_03 (STATUS_03_out),
.STATUS_04 (STATUS_04_out),
.STATUS_05 (STATUS_05_out),
.STATUS_06 (STATUS_06_out),
.STATUS_07 (STATUS_07_out),
.SW_SCAN_OUT_00 (SW_SCAN_OUT_00_out),
.SW_SCAN_OUT_01 (SW_SCAN_OUT_01_out),
.SW_SCAN_OUT_02 (SW_SCAN_OUT_02_out),
.SW_SCAN_OUT_03 (SW_SCAN_OUT_03_out),
.ANALOG_HBM_SEL_00 (ANALOG_HBM_SEL_00_in),
.APB_0_PADDR (APB_0_PADDR_in),
.APB_0_PCLK (APB_0_PCLK_in),
.APB_0_PENABLE (APB_0_PENABLE_in),
.APB_0_PRESET_N (APB_0_PRESET_N_in),
.APB_0_PSEL (APB_0_PSEL_in),
.APB_0_PWDATA (APB_0_PWDATA_in),
.APB_0_PWRITE (APB_0_PWRITE_in),
.AXI_00_ACLK (AXI_00_ACLK_in),
.AXI_00_ARADDR (AXI_00_ARADDR_in),
.AXI_00_ARBURST (AXI_00_ARBURST_in),
.AXI_00_ARESET_N (AXI_00_ARESET_N_in),
.AXI_00_ARID (AXI_00_ARID_in),
.AXI_00_ARLEN (AXI_00_ARLEN_in),
.AXI_00_ARSIZE (AXI_00_ARSIZE_in),
.AXI_00_ARVALID (AXI_00_ARVALID_in),
.AXI_00_AWADDR (AXI_00_AWADDR_in),
.AXI_00_AWBURST (AXI_00_AWBURST_in),
.AXI_00_AWID (AXI_00_AWID_in),
.AXI_00_AWLEN (AXI_00_AWLEN_in),
.AXI_00_AWSIZE (AXI_00_AWSIZE_in),
.AXI_00_AWVALID (AXI_00_AWVALID_in),
.AXI_00_BREADY (AXI_00_BREADY_in),
.AXI_00_DFI_LP_PWR_X_REQ (AXI_00_DFI_LP_PWR_X_REQ_in),
.AXI_00_RREADY (AXI_00_RREADY_in),
.AXI_00_WDATA (AXI_00_WDATA_in),
.AXI_00_WDATA_PARITY (AXI_00_WDATA_PARITY_in),
.AXI_00_WLAST (AXI_00_WLAST_in),
.AXI_00_WSTRB (AXI_00_WSTRB_in),
.AXI_00_WVALID (AXI_00_WVALID_in),
.AXI_01_ACLK (AXI_01_ACLK_in),
.AXI_01_ARADDR (AXI_01_ARADDR_in),
.AXI_01_ARBURST (AXI_01_ARBURST_in),
.AXI_01_ARESET_N (AXI_01_ARESET_N_in),
.AXI_01_ARID (AXI_01_ARID_in),
.AXI_01_ARLEN (AXI_01_ARLEN_in),
.AXI_01_ARSIZE (AXI_01_ARSIZE_in),
.AXI_01_ARVALID (AXI_01_ARVALID_in),
.AXI_01_AWADDR (AXI_01_AWADDR_in),
.AXI_01_AWBURST (AXI_01_AWBURST_in),
.AXI_01_AWID (AXI_01_AWID_in),
.AXI_01_AWLEN (AXI_01_AWLEN_in),
.AXI_01_AWSIZE (AXI_01_AWSIZE_in),
.AXI_01_AWVALID (AXI_01_AWVALID_in),
.AXI_01_BREADY (AXI_01_BREADY_in),
.AXI_01_DFI_LP_PWR_X_REQ (AXI_01_DFI_LP_PWR_X_REQ_in),
.AXI_01_RREADY (AXI_01_RREADY_in),
.AXI_01_WDATA (AXI_01_WDATA_in),
.AXI_01_WDATA_PARITY (AXI_01_WDATA_PARITY_in),
.AXI_01_WLAST (AXI_01_WLAST_in),
.AXI_01_WSTRB (AXI_01_WSTRB_in),
.AXI_01_WVALID (AXI_01_WVALID_in),
.AXI_02_ACLK (AXI_02_ACLK_in),
.AXI_02_ARADDR (AXI_02_ARADDR_in),
.AXI_02_ARBURST (AXI_02_ARBURST_in),
.AXI_02_ARESET_N (AXI_02_ARESET_N_in),
.AXI_02_ARID (AXI_02_ARID_in),
.AXI_02_ARLEN (AXI_02_ARLEN_in),
.AXI_02_ARSIZE (AXI_02_ARSIZE_in),
.AXI_02_ARVALID (AXI_02_ARVALID_in),
.AXI_02_AWADDR (AXI_02_AWADDR_in),
.AXI_02_AWBURST (AXI_02_AWBURST_in),
.AXI_02_AWID (AXI_02_AWID_in),
.AXI_02_AWLEN (AXI_02_AWLEN_in),
.AXI_02_AWSIZE (AXI_02_AWSIZE_in),
.AXI_02_AWVALID (AXI_02_AWVALID_in),
.AXI_02_BREADY (AXI_02_BREADY_in),
.AXI_02_DFI_LP_PWR_X_REQ (AXI_02_DFI_LP_PWR_X_REQ_in),
.AXI_02_RREADY (AXI_02_RREADY_in),
.AXI_02_WDATA (AXI_02_WDATA_in),
.AXI_02_WDATA_PARITY (AXI_02_WDATA_PARITY_in),
.AXI_02_WLAST (AXI_02_WLAST_in),
.AXI_02_WSTRB (AXI_02_WSTRB_in),
.AXI_02_WVALID (AXI_02_WVALID_in),
.AXI_03_ACLK (AXI_03_ACLK_in),
.AXI_03_ARADDR (AXI_03_ARADDR_in),
.AXI_03_ARBURST (AXI_03_ARBURST_in),
.AXI_03_ARESET_N (AXI_03_ARESET_N_in),
.AXI_03_ARID (AXI_03_ARID_in),
.AXI_03_ARLEN (AXI_03_ARLEN_in),
.AXI_03_ARSIZE (AXI_03_ARSIZE_in),
.AXI_03_ARVALID (AXI_03_ARVALID_in),
.AXI_03_AWADDR (AXI_03_AWADDR_in),
.AXI_03_AWBURST (AXI_03_AWBURST_in),
.AXI_03_AWID (AXI_03_AWID_in),
.AXI_03_AWLEN (AXI_03_AWLEN_in),
.AXI_03_AWSIZE (AXI_03_AWSIZE_in),
.AXI_03_AWVALID (AXI_03_AWVALID_in),
.AXI_03_BREADY (AXI_03_BREADY_in),
.AXI_03_DFI_LP_PWR_X_REQ (AXI_03_DFI_LP_PWR_X_REQ_in),
.AXI_03_RREADY (AXI_03_RREADY_in),
.AXI_03_WDATA (AXI_03_WDATA_in),
.AXI_03_WDATA_PARITY (AXI_03_WDATA_PARITY_in),
.AXI_03_WLAST (AXI_03_WLAST_in),
.AXI_03_WSTRB (AXI_03_WSTRB_in),
.AXI_03_WVALID (AXI_03_WVALID_in),
.AXI_04_ACLK (AXI_04_ACLK_in),
.AXI_04_ARADDR (AXI_04_ARADDR_in),
.AXI_04_ARBURST (AXI_04_ARBURST_in),
.AXI_04_ARESET_N (AXI_04_ARESET_N_in),
.AXI_04_ARID (AXI_04_ARID_in),
.AXI_04_ARLEN (AXI_04_ARLEN_in),
.AXI_04_ARSIZE (AXI_04_ARSIZE_in),
.AXI_04_ARVALID (AXI_04_ARVALID_in),
.AXI_04_AWADDR (AXI_04_AWADDR_in),
.AXI_04_AWBURST (AXI_04_AWBURST_in),
.AXI_04_AWID (AXI_04_AWID_in),
.AXI_04_AWLEN (AXI_04_AWLEN_in),
.AXI_04_AWSIZE (AXI_04_AWSIZE_in),
.AXI_04_AWVALID (AXI_04_AWVALID_in),
.AXI_04_BREADY (AXI_04_BREADY_in),
.AXI_04_DFI_LP_PWR_X_REQ (AXI_04_DFI_LP_PWR_X_REQ_in),
.AXI_04_RREADY (AXI_04_RREADY_in),
.AXI_04_WDATA (AXI_04_WDATA_in),
.AXI_04_WDATA_PARITY (AXI_04_WDATA_PARITY_in),
.AXI_04_WLAST (AXI_04_WLAST_in),
.AXI_04_WSTRB (AXI_04_WSTRB_in),
.AXI_04_WVALID (AXI_04_WVALID_in),
.AXI_05_ACLK (AXI_05_ACLK_in),
.AXI_05_ARADDR (AXI_05_ARADDR_in),
.AXI_05_ARBURST (AXI_05_ARBURST_in),
.AXI_05_ARESET_N (AXI_05_ARESET_N_in),
.AXI_05_ARID (AXI_05_ARID_in),
.AXI_05_ARLEN (AXI_05_ARLEN_in),
.AXI_05_ARSIZE (AXI_05_ARSIZE_in),
.AXI_05_ARVALID (AXI_05_ARVALID_in),
.AXI_05_AWADDR (AXI_05_AWADDR_in),
.AXI_05_AWBURST (AXI_05_AWBURST_in),
.AXI_05_AWID (AXI_05_AWID_in),
.AXI_05_AWLEN (AXI_05_AWLEN_in),
.AXI_05_AWSIZE (AXI_05_AWSIZE_in),
.AXI_05_AWVALID (AXI_05_AWVALID_in),
.AXI_05_BREADY (AXI_05_BREADY_in),
.AXI_05_DFI_LP_PWR_X_REQ (AXI_05_DFI_LP_PWR_X_REQ_in),
.AXI_05_RREADY (AXI_05_RREADY_in),
.AXI_05_WDATA (AXI_05_WDATA_in),
.AXI_05_WDATA_PARITY (AXI_05_WDATA_PARITY_in),
.AXI_05_WLAST (AXI_05_WLAST_in),
.AXI_05_WSTRB (AXI_05_WSTRB_in),
.AXI_05_WVALID (AXI_05_WVALID_in),
.AXI_06_ACLK (AXI_06_ACLK_in),
.AXI_06_ARADDR (AXI_06_ARADDR_in),
.AXI_06_ARBURST (AXI_06_ARBURST_in),
.AXI_06_ARESET_N (AXI_06_ARESET_N_in),
.AXI_06_ARID (AXI_06_ARID_in),
.AXI_06_ARLEN (AXI_06_ARLEN_in),
.AXI_06_ARSIZE (AXI_06_ARSIZE_in),
.AXI_06_ARVALID (AXI_06_ARVALID_in),
.AXI_06_AWADDR (AXI_06_AWADDR_in),
.AXI_06_AWBURST (AXI_06_AWBURST_in),
.AXI_06_AWID (AXI_06_AWID_in),
.AXI_06_AWLEN (AXI_06_AWLEN_in),
.AXI_06_AWSIZE (AXI_06_AWSIZE_in),
.AXI_06_AWVALID (AXI_06_AWVALID_in),
.AXI_06_BREADY (AXI_06_BREADY_in),
.AXI_06_DFI_LP_PWR_X_REQ (AXI_06_DFI_LP_PWR_X_REQ_in),
.AXI_06_RREADY (AXI_06_RREADY_in),
.AXI_06_WDATA (AXI_06_WDATA_in),
.AXI_06_WDATA_PARITY (AXI_06_WDATA_PARITY_in),
.AXI_06_WLAST (AXI_06_WLAST_in),
.AXI_06_WSTRB (AXI_06_WSTRB_in),
.AXI_06_WVALID (AXI_06_WVALID_in),
.AXI_07_ACLK (AXI_07_ACLK_in),
.AXI_07_ARADDR (AXI_07_ARADDR_in),
.AXI_07_ARBURST (AXI_07_ARBURST_in),
.AXI_07_ARESET_N (AXI_07_ARESET_N_in),
.AXI_07_ARID (AXI_07_ARID_in),
.AXI_07_ARLEN (AXI_07_ARLEN_in),
.AXI_07_ARSIZE (AXI_07_ARSIZE_in),
.AXI_07_ARVALID (AXI_07_ARVALID_in),
.AXI_07_AWADDR (AXI_07_AWADDR_in),
.AXI_07_AWBURST (AXI_07_AWBURST_in),
.AXI_07_AWID (AXI_07_AWID_in),
.AXI_07_AWLEN (AXI_07_AWLEN_in),
.AXI_07_AWSIZE (AXI_07_AWSIZE_in),
.AXI_07_AWVALID (AXI_07_AWVALID_in),
.AXI_07_BREADY (AXI_07_BREADY_in),
.AXI_07_DFI_LP_PWR_X_REQ (AXI_07_DFI_LP_PWR_X_REQ_in),
.AXI_07_RREADY (AXI_07_RREADY_in),
.AXI_07_WDATA (AXI_07_WDATA_in),
.AXI_07_WDATA_PARITY (AXI_07_WDATA_PARITY_in),
.AXI_07_WLAST (AXI_07_WLAST_in),
.AXI_07_WSTRB (AXI_07_WSTRB_in),
.AXI_07_WVALID (AXI_07_WVALID_in),
.AXI_08_ACLK (AXI_08_ACLK_in),
.AXI_08_ARADDR (AXI_08_ARADDR_in),
.AXI_08_ARBURST (AXI_08_ARBURST_in),
.AXI_08_ARESET_N (AXI_08_ARESET_N_in),
.AXI_08_ARID (AXI_08_ARID_in),
.AXI_08_ARLEN (AXI_08_ARLEN_in),
.AXI_08_ARSIZE (AXI_08_ARSIZE_in),
.AXI_08_ARVALID (AXI_08_ARVALID_in),
.AXI_08_AWADDR (AXI_08_AWADDR_in),
.AXI_08_AWBURST (AXI_08_AWBURST_in),
.AXI_08_AWID (AXI_08_AWID_in),
.AXI_08_AWLEN (AXI_08_AWLEN_in),
.AXI_08_AWSIZE (AXI_08_AWSIZE_in),
.AXI_08_AWVALID (AXI_08_AWVALID_in),
.AXI_08_BREADY (AXI_08_BREADY_in),
.AXI_08_DFI_LP_PWR_X_REQ (AXI_08_DFI_LP_PWR_X_REQ_in),
.AXI_08_RREADY (AXI_08_RREADY_in),
.AXI_08_WDATA (AXI_08_WDATA_in),
.AXI_08_WDATA_PARITY (AXI_08_WDATA_PARITY_in),
.AXI_08_WLAST (AXI_08_WLAST_in),
.AXI_08_WSTRB (AXI_08_WSTRB_in),
.AXI_08_WVALID (AXI_08_WVALID_in),
.AXI_09_ACLK (AXI_09_ACLK_in),
.AXI_09_ARADDR (AXI_09_ARADDR_in),
.AXI_09_ARBURST (AXI_09_ARBURST_in),
.AXI_09_ARESET_N (AXI_09_ARESET_N_in),
.AXI_09_ARID (AXI_09_ARID_in),
.AXI_09_ARLEN (AXI_09_ARLEN_in),
.AXI_09_ARSIZE (AXI_09_ARSIZE_in),
.AXI_09_ARVALID (AXI_09_ARVALID_in),
.AXI_09_AWADDR (AXI_09_AWADDR_in),
.AXI_09_AWBURST (AXI_09_AWBURST_in),
.AXI_09_AWID (AXI_09_AWID_in),
.AXI_09_AWLEN (AXI_09_AWLEN_in),
.AXI_09_AWSIZE (AXI_09_AWSIZE_in),
.AXI_09_AWVALID (AXI_09_AWVALID_in),
.AXI_09_BREADY (AXI_09_BREADY_in),
.AXI_09_DFI_LP_PWR_X_REQ (AXI_09_DFI_LP_PWR_X_REQ_in),
.AXI_09_RREADY (AXI_09_RREADY_in),
.AXI_09_WDATA (AXI_09_WDATA_in),
.AXI_09_WDATA_PARITY (AXI_09_WDATA_PARITY_in),
.AXI_09_WLAST (AXI_09_WLAST_in),
.AXI_09_WSTRB (AXI_09_WSTRB_in),
.AXI_09_WVALID (AXI_09_WVALID_in),
.AXI_10_ACLK (AXI_10_ACLK_in),
.AXI_10_ARADDR (AXI_10_ARADDR_in),
.AXI_10_ARBURST (AXI_10_ARBURST_in),
.AXI_10_ARESET_N (AXI_10_ARESET_N_in),
.AXI_10_ARID (AXI_10_ARID_in),
.AXI_10_ARLEN (AXI_10_ARLEN_in),
.AXI_10_ARSIZE (AXI_10_ARSIZE_in),
.AXI_10_ARVALID (AXI_10_ARVALID_in),
.AXI_10_AWADDR (AXI_10_AWADDR_in),
.AXI_10_AWBURST (AXI_10_AWBURST_in),
.AXI_10_AWID (AXI_10_AWID_in),
.AXI_10_AWLEN (AXI_10_AWLEN_in),
.AXI_10_AWSIZE (AXI_10_AWSIZE_in),
.AXI_10_AWVALID (AXI_10_AWVALID_in),
.AXI_10_BREADY (AXI_10_BREADY_in),
.AXI_10_DFI_LP_PWR_X_REQ (AXI_10_DFI_LP_PWR_X_REQ_in),
.AXI_10_RREADY (AXI_10_RREADY_in),
.AXI_10_WDATA (AXI_10_WDATA_in),
.AXI_10_WDATA_PARITY (AXI_10_WDATA_PARITY_in),
.AXI_10_WLAST (AXI_10_WLAST_in),
.AXI_10_WSTRB (AXI_10_WSTRB_in),
.AXI_10_WVALID (AXI_10_WVALID_in),
.AXI_11_ACLK (AXI_11_ACLK_in),
.AXI_11_ARADDR (AXI_11_ARADDR_in),
.AXI_11_ARBURST (AXI_11_ARBURST_in),
.AXI_11_ARESET_N (AXI_11_ARESET_N_in),
.AXI_11_ARID (AXI_11_ARID_in),
.AXI_11_ARLEN (AXI_11_ARLEN_in),
.AXI_11_ARSIZE (AXI_11_ARSIZE_in),
.AXI_11_ARVALID (AXI_11_ARVALID_in),
.AXI_11_AWADDR (AXI_11_AWADDR_in),
.AXI_11_AWBURST (AXI_11_AWBURST_in),
.AXI_11_AWID (AXI_11_AWID_in),
.AXI_11_AWLEN (AXI_11_AWLEN_in),
.AXI_11_AWSIZE (AXI_11_AWSIZE_in),
.AXI_11_AWVALID (AXI_11_AWVALID_in),
.AXI_11_BREADY (AXI_11_BREADY_in),
.AXI_11_DFI_LP_PWR_X_REQ (AXI_11_DFI_LP_PWR_X_REQ_in),
.AXI_11_RREADY (AXI_11_RREADY_in),
.AXI_11_WDATA (AXI_11_WDATA_in),
.AXI_11_WDATA_PARITY (AXI_11_WDATA_PARITY_in),
.AXI_11_WLAST (AXI_11_WLAST_in),
.AXI_11_WSTRB (AXI_11_WSTRB_in),
.AXI_11_WVALID (AXI_11_WVALID_in),
.AXI_12_ACLK (AXI_12_ACLK_in),
.AXI_12_ARADDR (AXI_12_ARADDR_in),
.AXI_12_ARBURST (AXI_12_ARBURST_in),
.AXI_12_ARESET_N (AXI_12_ARESET_N_in),
.AXI_12_ARID (AXI_12_ARID_in),
.AXI_12_ARLEN (AXI_12_ARLEN_in),
.AXI_12_ARSIZE (AXI_12_ARSIZE_in),
.AXI_12_ARVALID (AXI_12_ARVALID_in),
.AXI_12_AWADDR (AXI_12_AWADDR_in),
.AXI_12_AWBURST (AXI_12_AWBURST_in),
.AXI_12_AWID (AXI_12_AWID_in),
.AXI_12_AWLEN (AXI_12_AWLEN_in),
.AXI_12_AWSIZE (AXI_12_AWSIZE_in),
.AXI_12_AWVALID (AXI_12_AWVALID_in),
.AXI_12_BREADY (AXI_12_BREADY_in),
.AXI_12_DFI_LP_PWR_X_REQ (AXI_12_DFI_LP_PWR_X_REQ_in),
.AXI_12_RREADY (AXI_12_RREADY_in),
.AXI_12_WDATA (AXI_12_WDATA_in),
.AXI_12_WDATA_PARITY (AXI_12_WDATA_PARITY_in),
.AXI_12_WLAST (AXI_12_WLAST_in),
.AXI_12_WSTRB (AXI_12_WSTRB_in),
.AXI_12_WVALID (AXI_12_WVALID_in),
.AXI_13_ACLK (AXI_13_ACLK_in),
.AXI_13_ARADDR (AXI_13_ARADDR_in),
.AXI_13_ARBURST (AXI_13_ARBURST_in),
.AXI_13_ARESET_N (AXI_13_ARESET_N_in),
.AXI_13_ARID (AXI_13_ARID_in),
.AXI_13_ARLEN (AXI_13_ARLEN_in),
.AXI_13_ARSIZE (AXI_13_ARSIZE_in),
.AXI_13_ARVALID (AXI_13_ARVALID_in),
.AXI_13_AWADDR (AXI_13_AWADDR_in),
.AXI_13_AWBURST (AXI_13_AWBURST_in),
.AXI_13_AWID (AXI_13_AWID_in),
.AXI_13_AWLEN (AXI_13_AWLEN_in),
.AXI_13_AWSIZE (AXI_13_AWSIZE_in),
.AXI_13_AWVALID (AXI_13_AWVALID_in),
.AXI_13_BREADY (AXI_13_BREADY_in),
.AXI_13_DFI_LP_PWR_X_REQ (AXI_13_DFI_LP_PWR_X_REQ_in),
.AXI_13_RREADY (AXI_13_RREADY_in),
.AXI_13_WDATA (AXI_13_WDATA_in),
.AXI_13_WDATA_PARITY (AXI_13_WDATA_PARITY_in),
.AXI_13_WLAST (AXI_13_WLAST_in),
.AXI_13_WSTRB (AXI_13_WSTRB_in),
.AXI_13_WVALID (AXI_13_WVALID_in),
.AXI_14_ACLK (AXI_14_ACLK_in),
.AXI_14_ARADDR (AXI_14_ARADDR_in),
.AXI_14_ARBURST (AXI_14_ARBURST_in),
.AXI_14_ARESET_N (AXI_14_ARESET_N_in),
.AXI_14_ARID (AXI_14_ARID_in),
.AXI_14_ARLEN (AXI_14_ARLEN_in),
.AXI_14_ARSIZE (AXI_14_ARSIZE_in),
.AXI_14_ARVALID (AXI_14_ARVALID_in),
.AXI_14_AWADDR (AXI_14_AWADDR_in),
.AXI_14_AWBURST (AXI_14_AWBURST_in),
.AXI_14_AWID (AXI_14_AWID_in),
.AXI_14_AWLEN (AXI_14_AWLEN_in),
.AXI_14_AWSIZE (AXI_14_AWSIZE_in),
.AXI_14_AWVALID (AXI_14_AWVALID_in),
.AXI_14_BREADY (AXI_14_BREADY_in),
.AXI_14_DFI_LP_PWR_X_REQ (AXI_14_DFI_LP_PWR_X_REQ_in),
.AXI_14_RREADY (AXI_14_RREADY_in),
.AXI_14_WDATA (AXI_14_WDATA_in),
.AXI_14_WDATA_PARITY (AXI_14_WDATA_PARITY_in),
.AXI_14_WLAST (AXI_14_WLAST_in),
.AXI_14_WSTRB (AXI_14_WSTRB_in),
.AXI_14_WVALID (AXI_14_WVALID_in),
.AXI_15_ACLK (AXI_15_ACLK_in),
.AXI_15_ARADDR (AXI_15_ARADDR_in),
.AXI_15_ARBURST (AXI_15_ARBURST_in),
.AXI_15_ARESET_N (AXI_15_ARESET_N_in),
.AXI_15_ARID (AXI_15_ARID_in),
.AXI_15_ARLEN (AXI_15_ARLEN_in),
.AXI_15_ARSIZE (AXI_15_ARSIZE_in),
.AXI_15_ARVALID (AXI_15_ARVALID_in),
.AXI_15_AWADDR (AXI_15_AWADDR_in),
.AXI_15_AWBURST (AXI_15_AWBURST_in),
.AXI_15_AWID (AXI_15_AWID_in),
.AXI_15_AWLEN (AXI_15_AWLEN_in),
.AXI_15_AWSIZE (AXI_15_AWSIZE_in),
.AXI_15_AWVALID (AXI_15_AWVALID_in),
.AXI_15_BREADY (AXI_15_BREADY_in),
.AXI_15_DFI_LP_PWR_X_REQ (AXI_15_DFI_LP_PWR_X_REQ_in),
.AXI_15_RREADY (AXI_15_RREADY_in),
.AXI_15_WDATA (AXI_15_WDATA_in),
.AXI_15_WDATA_PARITY (AXI_15_WDATA_PARITY_in),
.AXI_15_WLAST (AXI_15_WLAST_in),
.AXI_15_WSTRB (AXI_15_WSTRB_in),
.AXI_15_WVALID (AXI_15_WVALID_in),
.BLI_SCAN_ENABLE_00 (BLI_SCAN_ENABLE_00_in),
.BLI_SCAN_ENABLE_01 (BLI_SCAN_ENABLE_01_in),
.BLI_SCAN_ENABLE_02 (BLI_SCAN_ENABLE_02_in),
.BLI_SCAN_ENABLE_03 (BLI_SCAN_ENABLE_03_in),
.BLI_SCAN_ENABLE_04 (BLI_SCAN_ENABLE_04_in),
.BLI_SCAN_ENABLE_05 (BLI_SCAN_ENABLE_05_in),
.BLI_SCAN_ENABLE_06 (BLI_SCAN_ENABLE_06_in),
.BLI_SCAN_ENABLE_07 (BLI_SCAN_ENABLE_07_in),
.BLI_SCAN_ENABLE_08 (BLI_SCAN_ENABLE_08_in),
.BLI_SCAN_ENABLE_09 (BLI_SCAN_ENABLE_09_in),
.BLI_SCAN_ENABLE_10 (BLI_SCAN_ENABLE_10_in),
.BLI_SCAN_ENABLE_11 (BLI_SCAN_ENABLE_11_in),
.BLI_SCAN_ENABLE_12 (BLI_SCAN_ENABLE_12_in),
.BLI_SCAN_ENABLE_13 (BLI_SCAN_ENABLE_13_in),
.BLI_SCAN_ENABLE_14 (BLI_SCAN_ENABLE_14_in),
.BLI_SCAN_ENABLE_15 (BLI_SCAN_ENABLE_15_in),
.BLI_SCAN_IN_00 (BLI_SCAN_IN_00_in),
.BLI_SCAN_IN_01 (BLI_SCAN_IN_01_in),
.BLI_SCAN_IN_02 (BLI_SCAN_IN_02_in),
.BLI_SCAN_IN_03 (BLI_SCAN_IN_03_in),
.BLI_SCAN_IN_04 (BLI_SCAN_IN_04_in),
.BLI_SCAN_IN_05 (BLI_SCAN_IN_05_in),
.BLI_SCAN_IN_06 (BLI_SCAN_IN_06_in),
.BLI_SCAN_IN_07 (BLI_SCAN_IN_07_in),
.BLI_SCAN_IN_08 (BLI_SCAN_IN_08_in),
.BLI_SCAN_IN_09 (BLI_SCAN_IN_09_in),
.BLI_SCAN_IN_10 (BLI_SCAN_IN_10_in),
.BLI_SCAN_IN_11 (BLI_SCAN_IN_11_in),
.BLI_SCAN_IN_12 (BLI_SCAN_IN_12_in),
.BLI_SCAN_IN_13 (BLI_SCAN_IN_13_in),
.BLI_SCAN_IN_14 (BLI_SCAN_IN_14_in),
.BLI_SCAN_IN_15 (BLI_SCAN_IN_15_in),
.BSCAN_DRCK (BSCAN_DRCK_in),
.BSCAN_TCK (BSCAN_TCK_in),
.DBG_IN_00 (DBG_IN_00_in),
.DBG_IN_01 (DBG_IN_01_in),
.DBG_IN_02 (DBG_IN_02_in),
.DBG_IN_03 (DBG_IN_03_in),
.DBG_IN_04 (DBG_IN_04_in),
.DBG_IN_05 (DBG_IN_05_in),
.DBG_IN_06 (DBG_IN_06_in),
.DBG_IN_07 (DBG_IN_07_in),
.DBG_IN_08 (DBG_IN_08_in),
.DBG_IN_09 (DBG_IN_09_in),
.DBG_IN_10 (DBG_IN_10_in),
.DBG_IN_11 (DBG_IN_11_in),
.DBG_IN_12 (DBG_IN_12_in),
.DBG_IN_13 (DBG_IN_13_in),
.DBG_IN_14 (DBG_IN_14_in),
.DBG_IN_15 (DBG_IN_15_in),
.DLL_SCAN_CK_00 (DLL_SCAN_CK_00_in),
.DLL_SCAN_ENABLE_00 (DLL_SCAN_ENABLE_00_in),
.DLL_SCAN_IN_00 (DLL_SCAN_IN_00_in),
.DLL_SCAN_MODE_00 (DLL_SCAN_MODE_00_in),
.DLL_SCAN_RST_N_00 (DLL_SCAN_RST_N_00_in),
.HBM_REF_CLK (HBM_REF_CLK_in),
.IO_SCAN_CK_00 (IO_SCAN_CK_00_in),
.IO_SCAN_ENABLE_00 (IO_SCAN_ENABLE_00_in),
.IO_SCAN_IN_00 (IO_SCAN_IN_00_in),
.IO_SCAN_MODE_00 (IO_SCAN_MODE_00_in),
.IO_SCAN_RST_N_00 (IO_SCAN_RST_N_00_in),
.MBIST_EN_00 (MBIST_EN_00_in),
.MBIST_EN_01 (MBIST_EN_01_in),
.MBIST_EN_02 (MBIST_EN_02_in),
.MBIST_EN_03 (MBIST_EN_03_in),
.MBIST_EN_04 (MBIST_EN_04_in),
.MBIST_EN_05 (MBIST_EN_05_in),
.MBIST_EN_06 (MBIST_EN_06_in),
.MBIST_EN_07 (MBIST_EN_07_in),
.MC_SCAN_CK_00 (MC_SCAN_CK_00_in),
.MC_SCAN_CK_01 (MC_SCAN_CK_01_in),
.MC_SCAN_CK_02 (MC_SCAN_CK_02_in),
.MC_SCAN_CK_03 (MC_SCAN_CK_03_in),
.MC_SCAN_CK_04 (MC_SCAN_CK_04_in),
.MC_SCAN_CK_05 (MC_SCAN_CK_05_in),
.MC_SCAN_CK_06 (MC_SCAN_CK_06_in),
.MC_SCAN_CK_07 (MC_SCAN_CK_07_in),
.MC_SCAN_ENABLE_00 (MC_SCAN_ENABLE_00_in),
.MC_SCAN_ENABLE_01 (MC_SCAN_ENABLE_01_in),
.MC_SCAN_ENABLE_02 (MC_SCAN_ENABLE_02_in),
.MC_SCAN_ENABLE_03 (MC_SCAN_ENABLE_03_in),
.MC_SCAN_ENABLE_04 (MC_SCAN_ENABLE_04_in),
.MC_SCAN_ENABLE_05 (MC_SCAN_ENABLE_05_in),
.MC_SCAN_ENABLE_06 (MC_SCAN_ENABLE_06_in),
.MC_SCAN_ENABLE_07 (MC_SCAN_ENABLE_07_in),
.MC_SCAN_IN_00 (MC_SCAN_IN_00_in),
.MC_SCAN_IN_01 (MC_SCAN_IN_01_in),
.MC_SCAN_IN_02 (MC_SCAN_IN_02_in),
.MC_SCAN_IN_03 (MC_SCAN_IN_03_in),
.MC_SCAN_IN_04 (MC_SCAN_IN_04_in),
.MC_SCAN_IN_05 (MC_SCAN_IN_05_in),
.MC_SCAN_IN_06 (MC_SCAN_IN_06_in),
.MC_SCAN_IN_07 (MC_SCAN_IN_07_in),
.MC_SCAN_MODE_00 (MC_SCAN_MODE_00_in),
.MC_SCAN_MODE_01 (MC_SCAN_MODE_01_in),
.MC_SCAN_MODE_02 (MC_SCAN_MODE_02_in),
.MC_SCAN_MODE_03 (MC_SCAN_MODE_03_in),
.MC_SCAN_MODE_04 (MC_SCAN_MODE_04_in),
.MC_SCAN_MODE_05 (MC_SCAN_MODE_05_in),
.MC_SCAN_MODE_06 (MC_SCAN_MODE_06_in),
.MC_SCAN_MODE_07 (MC_SCAN_MODE_07_in),
.MC_SCAN_RST_N_00 (MC_SCAN_RST_N_00_in),
.MC_SCAN_RST_N_01 (MC_SCAN_RST_N_01_in),
.MC_SCAN_RST_N_02 (MC_SCAN_RST_N_02_in),
.MC_SCAN_RST_N_03 (MC_SCAN_RST_N_03_in),
.MC_SCAN_RST_N_04 (MC_SCAN_RST_N_04_in),
.MC_SCAN_RST_N_05 (MC_SCAN_RST_N_05_in),
.MC_SCAN_RST_N_06 (MC_SCAN_RST_N_06_in),
.MC_SCAN_RST_N_07 (MC_SCAN_RST_N_07_in),
.PHY_SCAN_CK_00 (PHY_SCAN_CK_00_in),
.PHY_SCAN_ENABLE_00 (PHY_SCAN_ENABLE_00_in),
.PHY_SCAN_IN_00 (PHY_SCAN_IN_00_in),
.PHY_SCAN_MODE_00 (PHY_SCAN_MODE_00_in),
.PHY_SCAN_RST_N_00 (PHY_SCAN_RST_N_00_in),
.SW_SCAN_CK_00 (SW_SCAN_CK_00_in),
.SW_SCAN_ENABLE_00 (SW_SCAN_ENABLE_00_in),
.SW_SCAN_IN_00 (SW_SCAN_IN_00_in),
.SW_SCAN_IN_01 (SW_SCAN_IN_01_in),
.SW_SCAN_IN_02 (SW_SCAN_IN_02_in),
.SW_SCAN_IN_03 (SW_SCAN_IN_03_in),
.SW_SCAN_MODE_00 (SW_SCAN_MODE_00_in),
.SW_SCAN_RST_N_00 (SW_SCAN_RST_N_00_in),
.GSR (glblGSR)
);
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22.08.2013 08:35:02
// Design Name:
// Module Name: network_module
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module network_module(
input clk156,
input reset,
input aresetn,
input dclk,
input txusrclk,
input txusrclk2,
output txclk322,
//input ref_clk_n,
input areset_refclk_bufh,
input areset_clk156,
input mmcm_locked_clk156,
input gttxreset_txusrclk2,
input gttxreset,
input gtrxreset,
input txuserrdy,
input qplllock,
input qplloutclk,
input qplloutrefclk,
input reset_counter_done,
output tx_resetdone,
output txp,
output txn,
input rxp,
input rxn,
//Axi Stream Interface
input[63:0] tx_axis_tdata,
input tx_axis_tvalid,
input tx_axis_tlast,
input tx_axis_tuser,
input[7:0] tx_axis_tkeep,
output tx_axis_tready,
output[63:0] rx_axis_tdata,
output rx_axis_tvalid,
output rx_axis_tlast,
output rx_axis_tuser,
output[7:0] rx_axis_tkeep,
input rx_axis_tready,
input core_reset, //TODO
input tx_fault,
input signal_detect,
// input[4:0] prtad,
input[7:0] tx_ifg_delay,
output tx_disable,
//status signals
output rx_fifo_overflow,
output [29:0] rx_statistics_vector,
output rx_statistics_valid,
output[7:0] core_status
);
wire[535:0] configuration_vector;
assign configuration_vector = 0;
wire[63:0] xgmii_txd;
wire[7:0] xgmii_txc;
wire[63:0] xgmii_rxd;
wire[7:0] xgmii_rxc;
reg[63:0] xgmii_txd_reg;
reg[7:0] xgmii_txc_reg;
reg[63:0] xgmii_rxd_reg;
reg[7:0] xgmii_rxc_reg;
reg[63:0] xgmii_txd_reg2;
reg[7:0] xgmii_txc_reg2;
reg[63:0] xgmii_rxd_reg2;
reg[7:0] xgmii_rxc_reg2;
reg[63:0] xgmii_txd_reg3;
reg[7:0] xgmii_txc_reg3;
reg[63:0] xgmii_rxd_reg3;
reg[7:0] xgmii_rxc_reg3;
wire[63:0] axi_str_tdata_to_xgmac;
wire[7:0] axi_str_tkeep_to_xgmac;
wire axi_str_tvalid_to_xgmac;
wire axi_str_tlast_to_xgmac;
wire axi_str_tready_to_xgmac;
wire[63:0] axi_str_rd_tdata_to_fifo;
wire[7:0] axi_str_rd_tkeep_to_fifo;
wire[0:0] axi_str_rd_tuser_to_fifo;
wire axi_str_rd_tvalid_to_fifo;
wire axi_str_rd_tlast_to_fifo;
// Wires for axi register slices
wire tx_axis_slice2interface_tvalid;
wire tx_axis_slice2interface_tready;
wire[63:0] tx_axis_slice2interface_tdata;
wire[7:0] tx_axis_slice2interface_tkeep;
wire tx_axis_slice2interface_tlast;
wire rx_axis_interface2slice_tvalid;
wire rx_axis_interface2slice_tready;
wire[63:0] rx_axis_interface2slice_tdata;
wire[7:0] rx_axis_interface2slice_tkeep;
wire rx_axis_interface2slice_tlast;
//wire resetdone;
//assign resetdone = tx_resetdone & rx_resetdone;
// Delay serial paths
always @(posedge clk156) begin
xgmii_rxd_reg <= xgmii_rxd;
xgmii_rxc_reg <= xgmii_rxc;
xgmii_txd_reg <= xgmii_txd;
xgmii_txc_reg <= xgmii_txc;
xgmii_rxd_reg2 <= xgmii_rxd_reg;
xgmii_rxc_reg2 <= xgmii_rxc_reg;
xgmii_txd_reg2 <= xgmii_txd_reg;
xgmii_txc_reg2 <= xgmii_txc_reg;
xgmii_rxd_reg3 <= xgmii_rxd_reg2;
xgmii_rxc_reg3 <= xgmii_rxc_reg2;
xgmii_txd_reg3 <= xgmii_txd_reg2;
xgmii_txc_reg3 <= xgmii_txc_reg2;
/*if (reset == 1'b1) begin
xgmii_rxd_reg <= 0;
xgmii_rxc_reg <= 0;
xgmii_txd_reg <= 0;
xgmii_txc_reg <= 0;
end
else begin
xgmii_rxd_reg <= xgmii_rxd;
xgmii_rxc_reg <= xgmii_rxc;
xgmii_txd_reg <= xgmii_txd;
xgmii_txc_reg <= xgmii_txc;
end*/
end
wire drp_req; // output wire drp_req
wire drp_den_o; // output wire drp_den_o
wire drp_dwe_o; // output wire drp_dwe_o
wire[15:0] drp_daddr_o; // output wire [15 : 0] drp_daddr_o
wire[15:0] drp_di_o; // output wire [15 : 0] drp_di_o
wire drp_drdy_o; // output wire drp_drdy_o
wire[15:0] drp_drpdo_o; // output wire [15 : 0] drp_drpdo_o
ten_gig_eth_pcs_pma_ip //# (
//.EXAMPLE_SIM_GTRESET_SPEEDUP("TRUE") ) //Does not affect hardware
ten_gig_eth_pcs_pma_inst
(
.coreclk(clk156),
.dclk(dclk),
.txusrclk(txusrclk),
.txusrclk2(txusrclk2),
.areset(reset),
.txoutclk(txclk322),
//.areset_refclk_bufh(areset_refclk_bufh),
.areset_coreclk(areset_clk156),
//.mmcm_locked_clk156(mmcm_locked_clk156),
//.gttxreset_txusrclk2(gttxreset_txusrclk2),
.gttxreset(gttxreset),
.gtrxreset(gtrxreset),
.txuserrdy(txuserrdy),
.qplllock(qplllock),
.qplloutclk(qplloutclk),
.qplloutrefclk(qplloutrefclk),
.reset_counter_done(reset_counter_done),
.xgmii_txd(xgmii_txd_reg3),
.xgmii_txc(xgmii_txc_reg3),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.txp(txp),
.txn(txn),
.rxp(rxp),
.rxn(rxn),
.configuration_vector(configuration_vector),
.status_vector(),
.core_status(core_status),
.tx_resetdone(tx_resetdone),
.rx_resetdone(),
.signal_detect(signal_detect),
.tx_fault(tx_fault),
//extra drp signals introduced in vivado 2013.4 core gen
.drp_req(drp_req), // output wire drp_req
.drp_gnt(drp_req), // input wire drp_gnt
.drp_den_o(drp_den_o), // output wire drp_den_o
.drp_dwe_o(drp_dwe_o), // output wire drp_dwe_o
.drp_daddr_o(drp_daddr_o), // output wire [15 : 0] drp_daddr_o
.drp_di_o(drp_di_o), // output wire [15 : 0] drp_di_o
.drp_drdy_o(drp_drdy_o), // output wire drp_drdy_o
.drp_drpdo_o(drp_drpdo_o), // output wire [15 : 0] drp_drpdo_o
.drp_den_i(drp_den_o), // input wire drp_den_i
.drp_dwe_i(drp_dwe_o), // input wire drp_dwe_i
.drp_daddr_i(drp_daddr_o), // input wire [15 : 0] drp_daddr_i
.drp_di_i(drp_di_o), // input wire [15 : 0] drp_di_i
.drp_drdy_i(drp_drdy_o), // input wire drp_drdy_i
.drp_drpdo_i(drp_drpdo_o),
.pma_pmd_type(3'b101),
//.pma_pmd_type(pma_pmd_type),
.tx_disable(tx_disable),
.sim_speedup_control(1'b0)
);
ten_gig_eth_mac_ip ten_gig_eth_mac_inst
(
.reset(reset),
.tx_axis_aresetn(~reset),
.tx_axis_tdata(axi_str_tdata_to_xgmac),
.tx_axis_tvalid(axi_str_tvalid_to_xgmac),
.tx_axis_tlast(axi_str_tlast_to_xgmac),
.tx_axis_tuser(1'b0),
.tx_ifg_delay(tx_ifg_delay),
.tx_axis_tkeep(axi_str_tkeep_to_xgmac),
.tx_axis_tready(axi_str_tready_from_xgmac),
.tx_statistics_vector(),
.tx_statistics_valid(),
.rx_axis_aresetn(~reset),
.rx_axis_tdata(axi_str_rd_tdata_to_fifo),
.rx_axis_tvalid(axi_str_rd_tvalid_to_fifo),
.rx_axis_tuser(axi_str_rd_tuser_to_fifo),
.rx_axis_tlast(axi_str_rd_tlast_to_fifo),
.rx_axis_tkeep(axi_str_rd_tkeep_to_fifo),
.rx_statistics_vector(rx_statistics_vector),
.rx_statistics_valid(rx_statistics_valid),
.pause_val(16'b0),
.pause_req(1'b0),
.tx_configuration_vector(80'h00000000000000000016),
.rx_configuration_vector(80'h00000000000000000016),
.status_vector(),
.tx_clk0(clk156),
.tx_dcm_locked(mmcm_locked_clk156),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.rx_clk0(clk156),
.rx_dcm_locked(mmcm_locked_clk156),
.xgmii_rxd(xgmii_rxd_reg3),
.xgmii_rxc(xgmii_rxc_reg3)
);
/*rx_interface
rx_interface_i (
.axi_str_tdata_from_xgmac (axi_str_rd_tdata_to_fifo ),
.axi_str_tkeep_from_xgmac (axi_str_rd_tkeep_to_fifo ),
.axi_str_tvalid_from_xgmac (axi_str_rd_tvalid_to_fifo ),
.axi_str_tlast_from_xgmac (axi_str_rd_tlast_to_fifo ),
.axi_str_tuser_from_xgmac (axi_str_rd_tuser_to_fifo ),
//.mac_id (48'h000000000000 ),
//.mac_id_valid (1'b0 ),
.rx_statistics_vector (rx_statistics_vector ),
.rx_statistics_valid (rx_statistics_valid ),
//.promiscuous_mode_en (1'b0 ),
.axi_str_tready_from_fifo (rx_axis_interface2slice_tready),
.axi_str_tdata_to_fifo (rx_axis_interface2slice_tdata),
.axi_str_tkeep_to_fifo (rx_axis_interface2slice_tkeep),
.axi_str_tvalid_to_fifo (rx_axis_interface2slice_tvalid),
.axi_str_tlast_to_fifo (rx_axis_interface2slice_tlast),
.rd_data_count ( ), //TODO
.rd_pkt_len ( ),
.rx_fifo_overflow (rx_fifo_overflow), //TODO
.user_clk (clk156 ),
.soft_reset (reset ),
.reset (reset )
);*/
rx_isolation rx_interface_i (
.axi_str_tdata_from_xgmac (axi_str_rd_tdata_to_fifo ),
.axi_str_tkeep_from_xgmac (axi_str_rd_tkeep_to_fifo ),
.axi_str_tvalid_from_xgmac (axi_str_rd_tvalid_to_fifo ),
.axi_str_tlast_from_xgmac (axi_str_rd_tlast_to_fifo ),
.axi_str_tready_from_fifo (rx_axis_interface2slice_tready),
.axi_str_tdata_to_fifo (rx_axis_interface2slice_tdata),
.axi_str_tkeep_to_fifo (rx_axis_interface2slice_tkeep),
.axi_str_tvalid_to_fifo (rx_axis_interface2slice_tvalid),
.axi_str_tlast_to_fifo (rx_axis_interface2slice_tlast),
.user_clk (clk156),
.reset (reset)
);
tx_interface tx_interface_i (
//tx_isolation tx_interface_i (
.axi_str_tdata_to_xgmac (axi_str_tdata_to_xgmac ),
.axi_str_tkeep_to_xgmac (axi_str_tkeep_to_xgmac ),
.axi_str_tvalid_to_xgmac (axi_str_tvalid_to_xgmac ),
.axi_str_tlast_to_xgmac (axi_str_tlast_to_xgmac ),
.axi_str_tuser_to_xgmac (axi_str_tuser_to_xgmac ),
.axi_str_tready_from_xgmac(axi_str_tready_from_xgmac ),
.axi_str_tready_to_fifo (tx_axis_slice2interface_tready),
.axi_str_tdata_from_fifo (tx_axis_slice2interface_tdata),
.axi_str_tkeep_from_fifo (tx_axis_slice2interface_tkeep),
.axi_str_tvalid_from_fifo (tx_axis_slice2interface_tvalid),
.axi_str_tlast_from_fifo (tx_axis_slice2interface_tlast),
.user_clk (clk156),
.reset (reset)
);
// TX Input Slice
axis_register_slice_64 axis_register_input_slice(
.aclk(clk156),
.aresetn(aresetn),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tlast(tx_axis_tlast),
.m_axis_tvalid(tx_axis_slice2interface_tvalid),
.m_axis_tready(tx_axis_slice2interface_tready),
.m_axis_tdata(tx_axis_slice2interface_tdata),
.m_axis_tkeep(tx_axis_slice2interface_tkeep),
.m_axis_tlast(tx_axis_slice2interface_tlast)
);
// RX Output slice
axis_register_slice_64 axis_register_output_slice(
.aclk(clk156),
.aresetn(aresetn),
.s_axis_tvalid(rx_axis_interface2slice_tvalid),
.s_axis_tready(rx_axis_interface2slice_tready),
.s_axis_tdata(rx_axis_interface2slice_tdata),
.s_axis_tkeep(rx_axis_interface2slice_tkeep),
.s_axis_tlast(rx_axis_interface2slice_tlast),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tlast(rx_axis_tlast)
);
endmodule
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: openhmc_sync_fifo
*
*/
`default_nettype none
module openhmc_sync_fifo #(
`ifdef CAG_ASSERTIONS
parameter DISABLE_EMPTY_ASSERT = 0,
parameter DISABLE_SHIFT_OUT_ASSERT = 0,
parameter DISABLE_XCHECK_ASSERT = 0,
`endif
parameter DATASIZE = 8,
parameter ADDRSIZE = 8
) (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
input wire res_n,
//----------------------------------
//----Signals
//----------------------------------
input wire [DATASIZE-1:0] d_in,
input wire shift_in,
input wire shift_out,
input wire next_stage_full, // Set to 1 if not chained
output wire [DATASIZE-1:0] d_out,
output wire empty
);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
wire si, so; // internal gated shift signals
reg full_r1, full_r2;
wire full_1, full_2, full_3;
reg full_m2, full_m1;
reg [DATASIZE-1:0] d_out_r1, d_out_r2;
wire [DATASIZE-1:0] d_out_m2, d_out_2, d_out_3;
wire mux_rm_2;
reg [ADDRSIZE -1:0] ra_m, wa_m; //addr after register similar to signal internal to sram
reg [ADDRSIZE -1:0] ra, wa; // address calculated for the next read
wire wen, ren;
wire m_empty;
assign full_1 = full_r1 || full_m1 || (full_m2 && full_r2);
assign full_2 = full_r2 || full_m2;
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------LOGIC STARTS HERE---------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
d_out_r1 <= {DATASIZE {1'b0}};
d_out_r2 <= {DATASIZE {1'b0}};
full_r1 <= 1'b0;
full_r2 <= 1'b0;
end else begin
// Register stage 1 (conditions shouldn't overlap)
if ((full_2 && !full_1 && si && !so) || // fill stage
(full_1 && m_empty && si && so)) begin // shift through
d_out_r1 <= d_in;
full_r1 <= 1'b1;
end
if (full_r1 && so && (!si || !m_empty)) begin // shift out
full_r1 <= 1'b0;
end
// Register stage 2 (conditions shouldn't overlap)
if (full_3 && ((!full_2 && si && !so) || // fill stage
(full_2 && !full_1 && si && so))) begin // shift through
d_out_r2 <= d_in;
full_r2 <= 1'b1;
end
if (full_r1 && so) begin // shift through
d_out_r2 <= d_out_r1;
full_r2 <= 1'b1;
end
if (full_m2 && ((!full_r2 && !so) || // Rescue
(full_r2 && so))) begin
d_out_r2 <= d_out_m2;
full_r2 <= 1'b1;
end
if (full_r2 &&
((!full_r1 && !full_m2 && so && !si) || // shift out
(full_m1 && si && so))) begin // shift through with RAM
full_r2 <= 1'b0;
end
end
end
// assign outputs and inputs to module interface
assign d_out = d_out_3;
assign empty = !full_3; // if the last stage is empty, the fifo is empty
assign si = shift_in;
assign so = shift_out;
wire [ADDRSIZE:0] fifo_ram_count = wa_m - ra_m;
assign mux_rm_2 = full_r2; // mux control of SRAM data bypass if only one value in stage r2
assign d_out_2 = mux_rm_2 ? d_out_r2 : d_out_m2; // additional data mux for SRAM bypass
// write port control of SRAM
assign wen = si && !so && full_1 // enter new value into SRAM, because regs are filled
|| si && !m_empty; // if a value is in the SRAM, then we have to shift through or shift in
// read port control of SRAM
assign ren = so && !m_empty;
assign m_empty = (wa_m == ra_m);
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
full_m1 <= 1'b0;
full_m2 <= 1'b0;
end else begin
full_m1 <= ren; // no control of m1
full_m2 <= full_m1
|| full_m2 && !so && full_r2; // no rescue possible
end
end
// pointer management
always @(*) begin
wa = wa_m + 1'b1; // wa_m is the address stored in mem addr register
ra = ra_m + 1'b1;
end
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
wa_m <= {ADDRSIZE {1'b0}};
ra_m <= {ADDRSIZE {1'b0}};
end else begin
if (wen) begin
wa_m <= wa; // next mem write addr to mem addr register
end
if (ren) begin
ra_m <= ra;
end
end
end
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
openhmc_sync_fifo_reg_stage #(.DWIDTH(DATASIZE))
sync_fifo_reg_stage_3_I (
.clk(clk),
.res_n(res_n),
.d_in(d_in),
.d_in_p(d_out_2),
.p_full(full_2),
.n_full(1'b1),
.si(si),
.so(so),
.full(full_3),
.d_out(d_out_3)
);
openhmc_ram #(
.DATASIZE(DATASIZE), // Memory data word width
.ADDRSIZE(ADDRSIZE), // Number of memory address bits
.PIPELINED(1)
)
ram(
.clk(clk),
.wen(wen),
.wdata(d_in),
.waddr(wa),
.ren(ren),
.raddr(ra),
.rdata(d_out_m2)
);
`ifdef CAG_ASSERTIONS
if (DISABLE_SHIFT_OUT_ASSERT == 0)
shift_out_and_empty: assert property (@(posedge clk) disable iff(!res_n) (shift_out |-> !empty));
if (DISABLE_XCHECK_ASSERT == 0)
dout_known: assert property (@(posedge clk) disable iff(!res_n) (!empty |-> !$isunknown(d_out)));
final
begin
if (DISABLE_EMPTY_ASSERT == 0)
begin
empty_not_set_assert: assert (empty);
end
end
`endif // CAG_ASSERTIONS
endmodule
`default_nettype wire
|
//deps: core.v, sdram_controller3.v, IS42S16160.v
`timescale 1ns/1ps
module top_tb;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [12:0] DRAM_ADDR; // From controller of sdram_controller3.v
wire [1:0] DRAM_BA; // From controller of sdram_controller3.v
wire DRAM_CAS_N; // From controller of sdram_controller3.v
wire DRAM_CKE; // From controller of sdram_controller3.v
wire DRAM_CLK; // From controller of sdram_controller3.v
wire DRAM_CS_N; // From controller of sdram_controller3.v
wire [15:0] DRAM_DQ; // To/From controller of sdram_controller3.v
wire [1:0] DRAM_DQM; // From controller of sdram_controller3.v
wire DRAM_RAS_N; // From controller of sdram_controller3.v
wire DRAM_WE_N; // From controller of sdram_controller3.v
wire [16-1:0] Dq; // To/From memory of IS42S16160.v
wire [7:0] LED; // From core of core.v
wire [31:0] data_out; // From controller of sdram_controller3.v
wire data_valid; // From controller of sdram_controller3.v
wire [23:0] dram_addr; // From core of core.v
wire [31:0] dram_data_out; // From core of core.v
wire dram_req_read; // From core of core.v
wire dram_req_write; // From core of core.v
wire snd_out; // From core of core.v
wire [3:0] snd_signals; // From core of core.v
wire tx; // From core of core.v
wire write_complete; // From controller of sdram_controller3.v
wire [31:0] dram_data_in; // To core of core.v
wire dram_data_valid; // To core of core.v
wire dram_write_complete; // To core of core.v
wire req_read; // To controller of sdram_controller3.v
wire req_write; // To controller of sdram_controller3.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg [13-1:0] Addr; // To memory of IS42S16160.v
reg [1:0] Ba; // To memory of IS42S16160.v
reg CLOCK_100; // To controller of sdram_controller3.v
reg CLOCK_100_del_3ns; // To controller of sdram_controller3.v
reg CLOCK_50; // To controller of sdram_controller3.v
reg Cas_n; // To memory of IS42S16160.v
reg Cke; // To memory of IS42S16160.v
reg Clk; // To memory of IS42S16160.v
reg Cs_n; // To memory of IS42S16160.v
reg [1:0] Dqm; // To memory of IS42S16160.v
reg Ras_n; // To memory of IS42S16160.v
reg We_n; // To memory of IS42S16160.v
reg [23:0] address; // To controller of sdram_controller3.v
reg clk; // To core of core.v
reg [31:0] data_in; // To controller of sdram_controller3.v
reg rst; // To controller of sdram_controller3.v
reg rx; // To core of core.v
reg [3:0] switches; // To core of core.v
wire rst_n;
assign rst_n = ~rst;
always @* begin
clk <= CLOCK_50;
end
// End of automatics
core core(
// Outputs
.LED (LED[7:0]),
.tx (tx),
.snd_out (snd_out),
.snd_signals (snd_signals[3:0]),
.dram_data_out (dram_data_in[31:0]),
.dram_addr (dram_addr[23:0]),
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
// Inputs
.clk (clk),
.rst_n (rst_n),
.rx (rx),
.switches (switches[3:0]),
.dram_data_in (dram_data_out[31:0]),
.dram_data_valid (dram_data_valid),
.dram_write_complete (dram_write_complete));
sdram_controller3 controller(
// Outputs
.data_out (dram_data_out[31:0]),
.data_valid (dram_data_valid),
.write_complete (dram_write_complete),
.DRAM_ADDR (DRAM_ADDR[12:0]),
.DRAM_BA (DRAM_BA[1:0]),
.DRAM_CAS_N (DRAM_CAS_N),
.DRAM_CKE (DRAM_CKE),
.DRAM_CLK (DRAM_CLK),
.DRAM_CS_N (DRAM_CS_N),
.DRAM_DQM (DRAM_DQM[1:0]),
.DRAM_RAS_N (DRAM_RAS_N),
.DRAM_WE_N (DRAM_WE_N),
// Inouts
.DRAM_DQ (DRAM_DQ[15:0]),
// Inputs
.CLOCK_50 (CLOCK_50),
.CLOCK_100 (CLOCK_100),
.CLOCK_100_del_3ns(CLOCK_100_del_3ns),
.rst (rst),
.address (dram_addr[23:0]),
.req_read (dram_req_read),
.req_write (dram_req_write),
.data_in (dram_data_in[31:0]));
IS42S16160 memory(
// Inouts
.Dq (DRAM_DQ[16-1:0]),
// Inputs
.Addr (DRAM_ADDR[13-1:0]),
.Ba (DRAM_BA[1:0]),
.Clk (DRAM_CLK),
.Cke (DRAM_CKE),
.Cs_n (DRAM_CS_N),
.Ras_n (DRAM_RAS_N),
.Cas_n (DRAM_CAS_N),
.We_n (DRAM_WE_N),
.Dqm (DRAM_DQM[1:0]));
initial begin
CLOCK_50 = 0;
CLOCK_100 = 0;
rst = 1;
$dumpfile("dump.vcd");
$dumpvars;
#9000 $finish;
end // initial begin
initial begin
#60 rst = 0;
end
always #10 CLOCK_50 <= ~CLOCK_50;
always #5 begin
CLOCK_100 <= ~CLOCK_100;
end
always @(CLOCK_100) begin
#3
CLOCK_100_del_3ns <= CLOCK_100;
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_Sys_PIO0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
irq,
readdata
)
;
inout [ 4: 0] bidir_port;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire [ 4: 0] bidir_port;
wire clk_en;
reg [ 4: 0] d1_data_in;
reg [ 4: 0] d2_data_in;
reg [ 4: 0] data_dir;
wire [ 4: 0] data_in;
reg [ 4: 0] data_out;
reg [ 4: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 4: 0] edge_detect;
wire irq;
reg [ 4: 0] irq_mask;
wire [ 4: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({5 {(address == 0)}} & data_in) |
({5 {(address == 1)}} & data_dir) |
({5 {(address == 2)}} & irq_mask) |
({5 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[4 : 0];
end
assign bidir_port[0] = data_dir[0] ? data_out[0] : 1'bZ;
assign bidir_port[1] = data_dir[1] ? data_out[1] : 1'bZ;
assign bidir_port[2] = data_dir[2] ? data_out[2] : 1'bZ;
assign bidir_port[3] = data_dir[3] ? data_out[3] : 1'bZ;
assign bidir_port[4] = data_dir[4] ? data_out[4] : 1'bZ;
assign data_in = bidir_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_dir <= 0;
else if (chipselect && ~write_n && (address == 1))
data_dir <= writedata[4 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[4 : 0];
end
assign irq = |(data_in & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[4] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[4] <= 0;
else if (edge_detect[4])
edge_capture[4] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
(* *********************************************************************)
(* *)
(* The Compcert verified compiler *)
(* *)
(* Xavier Leroy, INRIA Paris-Rocquencourt *)
(* *)
(* Copyright Institut National de Recherche en Informatique et en *)
(* Automatique. All rights reserved. This file is distributed *)
(* under the terms of the GNU General Public License as published by *)
(* the Free Software Foundation, either version 2 of the License, or *)
(* (at your option) any later version. This file is also distributed *)
(* under the terms of the INRIA Non-Commercial License Agreement. *)
(* *)
(* *********************************************************************)
(** Applicative finite maps are the main data structure used in this
project. A finite map associates data to keys. The two main operations
are [set k d m], which returns a map identical to [m] except that [d]
is associated to [k], and [get k m] which returns the data associated
to key [k] in map [m]. In this library, we distinguish two kinds of maps:
- Trees: the [get] operation returns an option type, either [None]
if no data is associated to the key, or [Some d] otherwise.
- Maps: the [get] operation always returns a data. If no data was explicitly
associated with the key, a default data provided at map initialization time
is returned.
In this library, we provide efficient implementations of trees and
maps whose keys range over the type [positive] of binary positive
integers or any type that can be injected into [positive]. The
implementation is based on radix-2 search trees (uncompressed
Patricia trees) and guarantees logarithmic-time operations. An
inefficient implementation of maps as functions is also provided.
*)
Require Import Equivalence EquivDec.
Require Import Coqlib.
(* To avoid useless definitions of inductors in extracted code. *)
Local Unset Elimination Schemes.
Local Unset Case Analysis Schemes.
Set Implicit Arguments.
(** * The abstract signatures of trees *)
Module Type TREE.
Variable elt: Type.
Variable elt_eq: forall (a b: elt), {a = b} + {a <> b}.
Variable t: Type -> Type.
Variable empty: forall (A: Type), t A.
Variable get: forall (A: Type), elt -> t A -> option A.
Variable set: forall (A: Type), elt -> A -> t A -> t A.
Variable remove: forall (A: Type), elt -> t A -> t A.
(** The ``good variables'' properties for trees, expressing
commutations between [get], [set] and [remove]. *)
Hypothesis gempty:
forall (A: Type) (i: elt), get i (empty A) = None.
Hypothesis gss:
forall (A: Type) (i: elt) (x: A) (m: t A), get i (set i x m) = Some x.
Hypothesis gso:
forall (A: Type) (i j: elt) (x: A) (m: t A),
i <> j -> get i (set j x m) = get i m.
Hypothesis gsspec:
forall (A: Type) (i j: elt) (x: A) (m: t A),
get i (set j x m) = if elt_eq i j then Some x else get i m.
Hypothesis gsident:
forall (A: Type) (i: elt) (m: t A) (v: A),
get i m = Some v -> set i v m = m.
(* We could implement the following, but it's not needed for the moment.
Hypothesis grident:
forall (A: Type) (i: elt) (m: t A) (v: A),
get i m = None -> remove i m = m.
*)
Hypothesis grs:
forall (A: Type) (i: elt) (m: t A), get i (remove i m) = None.
Hypothesis gro:
forall (A: Type) (i j: elt) (m: t A),
i <> j -> get i (remove j m) = get i m.
Hypothesis grspec:
forall (A: Type) (i j: elt) (m: t A),
get i (remove j m) = if elt_eq i j then None else get i m.
(** Extensional equality between trees. *)
Variable beq: forall (A: Type), (A -> A -> bool) -> t A -> t A -> bool.
Hypothesis beq_correct:
forall (A: Type) (eqA: A -> A -> bool) (t1 t2: t A),
beq eqA t1 t2 = true <->
(forall (x: elt),
match get x t1, get x t2 with
| None, None => True
| Some y1, Some y2 => eqA y1 y2 = true
| _, _ => False
end).
(** Applying a function to all data of a tree. *)
Variable map:
forall (A B: Type), (elt -> A -> B) -> t A -> t B.
Hypothesis gmap:
forall (A B: Type) (f: elt -> A -> B) (i: elt) (m: t A),
get i (map f m) = option_map (f i) (get i m).
(** Same as [map], but the function does not receive the [elt] argument. *)
Variable map1:
forall (A B: Type), (A -> B) -> t A -> t B.
Hypothesis gmap1:
forall (A B: Type) (f: A -> B) (i: elt) (m: t A),
get i (map1 f m) = option_map f (get i m).
(** Applying a function pairwise to all data of two trees. *)
Variable combine:
forall (A B C: Type), (option A -> option B -> option C) -> t A -> t B -> t C.
Hypothesis gcombine:
forall (A B C: Type) (f: option A -> option B -> option C),
f None None = None ->
forall (m1: t A) (m2: t B) (i: elt),
get i (combine f m1 m2) = f (get i m1) (get i m2).
Hypothesis combine_commut:
forall (A B: Type) (f g: option A -> option A -> option B),
(forall (i j: option A), f i j = g j i) ->
forall (m1 m2: t A),
combine f m1 m2 = combine g m2 m1.
(** Enumerating the bindings of a tree. *)
Variable elements:
forall (A: Type), t A -> list (elt * A).
Hypothesis elements_correct:
forall (A: Type) (m: t A) (i: elt) (v: A),
get i m = Some v -> In (i, v) (elements m).
Hypothesis elements_complete:
forall (A: Type) (m: t A) (i: elt) (v: A),
In (i, v) (elements m) -> get i m = Some v.
Hypothesis elements_keys_norepet:
forall (A: Type) (m: t A),
list_norepet (List.map (@fst elt A) (elements m)).
(** Folding a function over all bindings of a tree. *)
Variable fold:
forall (A B: Type), (B -> elt -> A -> B) -> t A -> B -> B.
Hypothesis fold_spec:
forall (A B: Type) (f: B -> elt -> A -> B) (v: B) (m: t A),
fold f m v =
List.fold_left (fun a p => f a (fst p) (snd p)) (elements m) v.
End TREE.
(** * The abstract signatures of maps *)
Module Type MAP.
Variable elt: Type.
Variable elt_eq: forall (a b: elt), {a = b} + {a <> b}.
Variable t: Type -> Type.
Variable init: forall (A: Type), A -> t A.
Variable get: forall (A: Type), elt -> t A -> A.
Variable set: forall (A: Type), elt -> A -> t A -> t A.
Hypothesis gi:
forall (A: Type) (i: elt) (x: A), get i (init x) = x.
Hypothesis gss:
forall (A: Type) (i: elt) (x: A) (m: t A), get i (set i x m) = x.
Hypothesis gso:
forall (A: Type) (i j: elt) (x: A) (m: t A),
i <> j -> get i (set j x m) = get i m.
Hypothesis gsspec:
forall (A: Type) (i j: elt) (x: A) (m: t A),
get i (set j x m) = if elt_eq i j then x else get i m.
Hypothesis gsident:
forall (A: Type) (i j: elt) (m: t A), get j (set i (get i m) m) = get j m.
Variable map: forall (A B: Type), (A -> B) -> t A -> t B.
Hypothesis gmap:
forall (A B: Type) (f: A -> B) (i: elt) (m: t A),
get i (map f m) = f(get i m).
End MAP.
(** * An implementation of trees over type [positive] *)
Module PTree <: TREE.
Definition elt := positive.
Definition elt_eq := peq.
Inductive tree (A : Type) : Type :=
| Leaf : tree A
| Node : tree A -> option A -> tree A -> tree A.
Implicit Arguments Leaf [A].
Implicit Arguments Node [A].
Scheme tree_ind := Induction for tree Sort Prop.
Definition t := tree.
Definition empty (A : Type) := (Leaf : t A).
Fixpoint get (A : Type) (i : positive) (m : t A) {struct i} : option A :=
match m with
| Leaf => None
| Node l o r =>
match i with
| xH => o
| xO ii => get ii l
| xI ii => get ii r
end
end.
Fixpoint set (A : Type) (i : positive) (v : A) (m : t A) {struct i} : t A :=
match m with
| Leaf =>
match i with
| xH => Node Leaf (Some v) Leaf
| xO ii => Node (set ii v Leaf) None Leaf
| xI ii => Node Leaf None (set ii v Leaf)
end
| Node l o r =>
match i with
| xH => Node l (Some v) r
| xO ii => Node (set ii v l) o r
| xI ii => Node l o (set ii v r)
end
end.
Fixpoint remove (A : Type) (i : positive) (m : t A) {struct i} : t A :=
match i with
| xH =>
match m with
| Leaf => Leaf
| Node Leaf o Leaf => Leaf
| Node l o r => Node l None r
end
| xO ii =>
match m with
| Leaf => Leaf
| Node l None Leaf =>
match remove ii l with
| Leaf => Leaf
| mm => Node mm None Leaf
end
| Node l o r => Node (remove ii l) o r
end
| xI ii =>
match m with
| Leaf => Leaf
| Node Leaf None r =>
match remove ii r with
| Leaf => Leaf
| mm => Node Leaf None mm
end
| Node l o r => Node l o (remove ii r)
end
end.
Theorem gempty:
forall (A: Type) (i: positive), get i (empty A) = None.
Proof.
induction i; simpl; auto.
Qed.
Theorem gss:
forall (A: Type) (i: positive) (x: A) (m: t A), get i (set i x m) = Some x.
Proof.
induction i; destruct m; simpl; auto.
Qed.
Lemma gleaf : forall (A : Type) (i : positive), get i (Leaf : t A) = None.
Proof. exact gempty. Qed.
Theorem gso:
forall (A: Type) (i j: positive) (x: A) (m: t A),
i <> j -> get i (set j x m) = get i m.
Proof.
induction i; intros; destruct j; destruct m; simpl;
try rewrite <- (gleaf A i); auto; try apply IHi; congruence.
Qed.
Theorem gsspec:
forall (A: Type) (i j: positive) (x: A) (m: t A),
get i (set j x m) = if peq i j then Some x else get i m.
Proof.
intros.
destruct (peq i j); [ rewrite e; apply gss | apply gso; auto ].
Qed.
Theorem gsident:
forall (A: Type) (i: positive) (m: t A) (v: A),
get i m = Some v -> set i v m = m.
Proof.
induction i; intros; destruct m; simpl; simpl in H; try congruence.
rewrite (IHi m2 v H); congruence.
rewrite (IHi m1 v H); congruence.
Qed.
Theorem set2:
forall (A: Type) (i: elt) (m: t A) (v1 v2: A),
set i v2 (set i v1 m) = set i v2 m.
Proof.
induction i; intros; destruct m; simpl; try (rewrite IHi); auto.
Qed.
Lemma rleaf : forall (A : Type) (i : positive), remove i (Leaf : t A) = Leaf.
Proof. destruct i; simpl; auto. Qed.
Theorem grs:
forall (A: Type) (i: positive) (m: t A), get i (remove i m) = None.
Proof.
induction i; destruct m.
simpl; auto.
destruct m1; destruct o; destruct m2 as [ | ll oo rr]; simpl; auto.
rewrite (rleaf A i); auto.
cut (get i (remove i (Node ll oo rr)) = None).
destruct (remove i (Node ll oo rr)); auto; apply IHi.
apply IHi.
simpl; auto.
destruct m1 as [ | ll oo rr]; destruct o; destruct m2; simpl; auto.
rewrite (rleaf A i); auto.
cut (get i (remove i (Node ll oo rr)) = None).
destruct (remove i (Node ll oo rr)); auto; apply IHi.
apply IHi.
simpl; auto.
destruct m1; destruct m2; simpl; auto.
Qed.
Theorem gro:
forall (A: Type) (i j: positive) (m: t A),
i <> j -> get i (remove j m) = get i m.
Proof.
induction i; intros; destruct j; destruct m;
try rewrite (rleaf A (xI j));
try rewrite (rleaf A (xO j));
try rewrite (rleaf A 1); auto;
destruct m1; destruct o; destruct m2;
simpl;
try apply IHi; try congruence;
try rewrite (rleaf A j); auto;
try rewrite (gleaf A i); auto.
cut (get i (remove j (Node m2_1 o m2_2)) = get i (Node m2_1 o m2_2));
[ destruct (remove j (Node m2_1 o m2_2)); try rewrite (gleaf A i); auto
| apply IHi; congruence ].
destruct (remove j (Node m1_1 o0 m1_2)); simpl; try rewrite (gleaf A i);
auto.
destruct (remove j (Node m2_1 o m2_2)); simpl; try rewrite (gleaf A i);
auto.
cut (get i (remove j (Node m1_1 o0 m1_2)) = get i (Node m1_1 o0 m1_2));
[ destruct (remove j (Node m1_1 o0 m1_2)); try rewrite (gleaf A i); auto
| apply IHi; congruence ].
destruct (remove j (Node m2_1 o m2_2)); simpl; try rewrite (gleaf A i);
auto.
destruct (remove j (Node m1_1 o0 m1_2)); simpl; try rewrite (gleaf A i);
auto.
Qed.
Theorem grspec:
forall (A: Type) (i j: elt) (m: t A),
get i (remove j m) = if elt_eq i j then None else get i m.
Proof.
intros. destruct (elt_eq i j). subst j. apply grs. apply gro; auto.
Qed.
Section BOOLEAN_EQUALITY.
Variable A: Type.
Variable beqA: A -> A -> bool.
Fixpoint bempty (m: t A) : bool :=
match m with
| Leaf => true
| Node l None r => bempty l && bempty r
| Node l (Some _) r => false
end.
Fixpoint beq (m1 m2: t A) {struct m1} : bool :=
match m1, m2 with
| Leaf, _ => bempty m2
| _, Leaf => bempty m1
| Node l1 o1 r1, Node l2 o2 r2 =>
match o1, o2 with
| None, None => true
| Some y1, Some y2 => beqA y1 y2
| _, _ => false
end
&& beq l1 l2 && beq r1 r2
end.
Lemma bempty_correct:
forall m, bempty m = true -> forall x, get x m = None.
Proof.
induction m; simpl; intros.
change (@Leaf A) with (empty A). apply gempty.
destruct o. congruence. destruct (andb_prop _ _ H).
destruct x; simpl; auto.
Qed.
Lemma bempty_complete:
forall m, (forall x, get x m = None) -> bempty m = true.
Proof.
induction m; simpl; intros.
auto.
destruct o. generalize (H xH); simpl; congruence.
rewrite IHm1. rewrite IHm2. auto.
intros; apply (H (xI x)).
intros; apply (H (xO x)).
Qed.
Lemma beq_correct:
forall m1 m2,
beq m1 m2 = true <->
(forall (x: elt),
match get x m1, get x m2 with
| None, None => True
| Some y1, Some y2 => beqA y1 y2 = true
| _, _ => False
end).
Proof.
intros; split.
- (* beq = true -> exteq *)
revert m1 m2. induction m1; destruct m2; simpl.
intros; red; intros. change (@Leaf A) with (empty A).
repeat rewrite gempty. auto.
destruct o; intro. congruence.
red; intros. change (@Leaf A) with (empty A). rewrite gempty.
rewrite bempty_correct. auto. assumption.
destruct o; intro. congruence.
red; intros. change (@Leaf A) with (empty A). rewrite gempty.
rewrite bempty_correct. auto. assumption.
destruct o; destruct o0; simpl; intro; try congruence.
destruct (andb_prop _ _ H). destruct (andb_prop _ _ H0).
destruct x; simpl.
apply IHm1_2; auto. apply IHm1_1; auto. auto.
destruct (andb_prop _ _ H).
red; intros. destruct x; simpl.
apply IHm1_2; auto. apply IHm1_1; auto.
auto.
- (* exteq -> beq = true *)
revert m1 m2. induction m1; destruct m2; simpl; intros.
auto.
change (bempty (Node m2_1 o m2_2) = true).
apply bempty_complete. intros. generalize (H x). rewrite gleaf.
destruct (get x (Node m2_1 o m2_2)); tauto.
change (bempty (Node m1_1 o m1_2) = true).
apply bempty_complete. intros. generalize (H x). rewrite gleaf.
destruct (get x (Node m1_1 o m1_2)); tauto.
apply andb_true_intro. split. apply andb_true_intro. split.
generalize (H xH); simpl. destruct o; destruct o0; auto.
apply IHm1_1. intros. apply (H (xO x)).
apply IHm1_2. intros. apply (H (xI x)).
Qed.
End BOOLEAN_EQUALITY.
Fixpoint append (i j : positive) {struct i} : positive :=
match i with
| xH => j
| xI ii => xI (append ii j)
| xO ii => xO (append ii j)
end.
Lemma append_assoc_0 : forall (i j : positive),
append i (xO j) = append (append i (xO xH)) j.
Proof.
induction i; intros; destruct j; simpl;
try rewrite (IHi (xI j));
try rewrite (IHi (xO j));
try rewrite <- (IHi xH);
auto.
Qed.
Lemma append_assoc_1 : forall (i j : positive),
append i (xI j) = append (append i (xI xH)) j.
Proof.
induction i; intros; destruct j; simpl;
try rewrite (IHi (xI j));
try rewrite (IHi (xO j));
try rewrite <- (IHi xH);
auto.
Qed.
Lemma append_neutral_r : forall (i : positive), append i xH = i.
Proof.
induction i; simpl; congruence.
Qed.
Lemma append_neutral_l : forall (i : positive), append xH i = i.
Proof.
simpl; auto.
Qed.
Fixpoint xmap (A B : Type) (f : positive -> A -> B) (m : t A) (i : positive)
{struct m} : t B :=
match m with
| Leaf => Leaf
| Node l o r => Node (xmap f l (append i (xO xH)))
(option_map (f i) o)
(xmap f r (append i (xI xH)))
end.
Definition map (A B : Type) (f : positive -> A -> B) m := xmap f m xH.
Lemma xgmap:
forall (A B: Type) (f: positive -> A -> B) (i j : positive) (m: t A),
get i (xmap f m j) = option_map (f (append j i)) (get i m).
Proof.
induction i; intros; destruct m; simpl; auto.
rewrite (append_assoc_1 j i); apply IHi.
rewrite (append_assoc_0 j i); apply IHi.
rewrite (append_neutral_r j); auto.
Qed.
Theorem gmap:
forall (A B: Type) (f: positive -> A -> B) (i: positive) (m: t A),
get i (map f m) = option_map (f i) (get i m).
Proof.
intros.
unfold map.
replace (f i) with (f (append xH i)).
apply xgmap.
rewrite append_neutral_l; auto.
Qed.
Fixpoint map1 (A B: Type) (f: A -> B) (m: t A) {struct m} : t B :=
match m with
| Leaf => Leaf
| Node l o r => Node (map1 f l) (option_map f o) (map1 f r)
end.
Theorem gmap1:
forall (A B: Type) (f: A -> B) (i: elt) (m: t A),
get i (map1 f m) = option_map f (get i m).
Proof.
induction i; intros; destruct m; simpl; auto.
Qed.
Definition Node' (A: Type) (l: t A) (x: option A) (r: t A): t A :=
match l, x, r with
| Leaf, None, Leaf => Leaf
| _, _, _ => Node l x r
end.
Lemma gnode':
forall (A: Type) (l r: t A) (x: option A) (i: positive),
get i (Node' l x r) = get i (Node l x r).
Proof.
intros. unfold Node'.
destruct l; destruct x; destruct r; auto.
destruct i; simpl; auto; rewrite gleaf; auto.
Qed.
Fixpoint filter1 (A: Type) (pred: A -> bool) (m: t A) {struct m} : t A :=
match m with
| Leaf => Leaf
| Node l o r =>
let o' := match o with None => None | Some x => if pred x then o else None end in
Node' (filter1 pred l) o' (filter1 pred r)
end.
Theorem gfilter1:
forall (A: Type) (pred: A -> bool) (i: elt) (m: t A),
get i (filter1 pred m) =
match get i m with None => None | Some x => if pred x then Some x else None end.
Proof.
intros until m. revert m i. induction m; simpl; intros.
rewrite gleaf; auto.
rewrite gnode'. destruct i; simpl; auto. destruct o; auto.
Qed.
Section COMBINE.
Variable A B C: Type.
Variable f: option A -> option B -> option C.
Hypothesis f_none_none: f None None = None.
Fixpoint xcombine_l (m : t A) {struct m} : t C :=
match m with
| Leaf => Leaf
| Node l o r => Node' (xcombine_l l) (f o None) (xcombine_l r)
end.
Lemma xgcombine_l :
forall (m: t A) (i : positive),
get i (xcombine_l m) = f (get i m) None.
Proof.
induction m; intros; simpl.
repeat rewrite gleaf. auto.
rewrite gnode'. destruct i; simpl; auto.
Qed.
Fixpoint xcombine_r (m : t B) {struct m} : t C :=
match m with
| Leaf => Leaf
| Node l o r => Node' (xcombine_r l) (f None o) (xcombine_r r)
end.
Lemma xgcombine_r :
forall (m: t B) (i : positive),
get i (xcombine_r m) = f None (get i m).
Proof.
induction m; intros; simpl.
repeat rewrite gleaf. auto.
rewrite gnode'. destruct i; simpl; auto.
Qed.
Fixpoint combine (m1: t A) (m2: t B) {struct m1} : t C :=
match m1 with
| Leaf => xcombine_r m2
| Node l1 o1 r1 =>
match m2 with
| Leaf => xcombine_l m1
| Node l2 o2 r2 => Node' (combine l1 l2) (f o1 o2) (combine r1 r2)
end
end.
Theorem gcombine:
forall (m1: t A) (m2: t B) (i: positive),
get i (combine m1 m2) = f (get i m1) (get i m2).
Proof.
induction m1; intros; simpl.
rewrite gleaf. apply xgcombine_r.
destruct m2; simpl.
rewrite gleaf. rewrite <- xgcombine_l. auto.
repeat rewrite gnode'. destruct i; simpl; auto.
Qed.
End COMBINE.
Lemma xcombine_lr :
forall (A B: Type) (f g : option A -> option A -> option B) (m : t A),
(forall (i j : option A), f i j = g j i) ->
xcombine_l f m = xcombine_r g m.
Proof.
induction m; intros; simpl; auto.
rewrite IHm1; auto.
rewrite IHm2; auto.
rewrite H; auto.
Qed.
Theorem combine_commut:
forall (A B: Type) (f g: option A -> option A -> option B),
(forall (i j: option A), f i j = g j i) ->
forall (m1 m2: t A),
combine f m1 m2 = combine g m2 m1.
Proof.
intros A B f g EQ1.
assert (EQ2: forall (i j: option A), g i j = f j i).
intros; auto.
induction m1; intros; destruct m2; simpl;
try rewrite EQ1;
repeat rewrite (xcombine_lr f g);
repeat rewrite (xcombine_lr g f);
auto.
rewrite IHm1_1.
rewrite IHm1_2.
auto.
Qed.
Fixpoint xelements (A : Type) (m : t A) (i : positive) {struct m}
: list (positive * A) :=
match m with
| Leaf => nil
| Node l None r =>
(xelements l (append i (xO xH))) ++ (xelements r (append i (xI xH)))
| Node l (Some x) r =>
(xelements l (append i (xO xH)))
++ ((i, x) :: xelements r (append i (xI xH)))
end.
(* Note: function [xelements] above is inefficient. We should apply
deforestation to it, but that makes the proofs even harder. *)
Definition elements A (m : t A) := xelements m xH.
Lemma xelements_correct:
forall (A: Type) (m: t A) (i j : positive) (v: A),
get i m = Some v -> In (append j i, v) (xelements m j).
Proof.
induction m; intros.
rewrite (gleaf A i) in H; congruence.
destruct o; destruct i; simpl; simpl in H.
rewrite append_assoc_1; apply in_or_app; right; apply in_cons;
apply IHm2; auto.
rewrite append_assoc_0; apply in_or_app; left; apply IHm1; auto.
rewrite append_neutral_r; apply in_or_app; injection H;
intro EQ; rewrite EQ; right; apply in_eq.
rewrite append_assoc_1; apply in_or_app; right; apply IHm2; auto.
rewrite append_assoc_0; apply in_or_app; left; apply IHm1; auto.
congruence.
Qed.
Theorem elements_correct:
forall (A: Type) (m: t A) (i: positive) (v: A),
get i m = Some v -> In (i, v) (elements m).
Proof.
intros A m i v H.
exact (xelements_correct m i xH H).
Qed.
Fixpoint xget (A : Type) (i j : positive) (m : t A) {struct j} : option A :=
match i, j with
| _, xH => get i m
| xO ii, xO jj => xget ii jj m
| xI ii, xI jj => xget ii jj m
| _, _ => None
end.
Lemma xget_left :
forall (A : Type) (j i : positive) (m1 m2 : t A) (o : option A) (v : A),
xget i (append j (xO xH)) m1 = Some v -> xget i j (Node m1 o m2) = Some v.
Proof.
induction j; intros; destruct i; simpl; simpl in H; auto; try congruence.
destruct i; congruence.
Qed.
Lemma xelements_ii :
forall (A: Type) (m: t A) (i j : positive) (v: A),
In (xI i, v) (xelements m (xI j)) -> In (i, v) (xelements m j).
Proof.
induction m.
simpl; auto.
intros; destruct o; simpl; simpl in H; destruct (in_app_or _ _ _ H);
apply in_or_app.
left; apply IHm1; auto.
right; destruct (in_inv H0).
injection H1; intros EQ1 EQ2; rewrite EQ1; rewrite EQ2; apply in_eq.
apply in_cons; apply IHm2; auto.
left; apply IHm1; auto.
right; apply IHm2; auto.
Qed.
Lemma xelements_io :
forall (A: Type) (m: t A) (i j : positive) (v: A),
~In (xI i, v) (xelements m (xO j)).
Proof.
induction m.
simpl; auto.
intros; destruct o; simpl; intro H; destruct (in_app_or _ _ _ H).
apply (IHm1 _ _ _ H0).
destruct (in_inv H0).
congruence.
apply (IHm2 _ _ _ H1).
apply (IHm1 _ _ _ H0).
apply (IHm2 _ _ _ H0).
Qed.
Lemma xelements_oo :
forall (A: Type) (m: t A) (i j : positive) (v: A),
In (xO i, v) (xelements m (xO j)) -> In (i, v) (xelements m j).
Proof.
induction m.
simpl; auto.
intros; destruct o; simpl; simpl in H; destruct (in_app_or _ _ _ H);
apply in_or_app.
left; apply IHm1; auto.
right; destruct (in_inv H0).
injection H1; intros EQ1 EQ2; rewrite EQ1; rewrite EQ2; apply in_eq.
apply in_cons; apply IHm2; auto.
left; apply IHm1; auto.
right; apply IHm2; auto.
Qed.
Lemma xelements_oi :
forall (A: Type) (m: t A) (i j : positive) (v: A),
~In (xO i, v) (xelements m (xI j)).
Proof.
induction m.
simpl; auto.
intros; destruct o; simpl; intro H; destruct (in_app_or _ _ _ H).
apply (IHm1 _ _ _ H0).
destruct (in_inv H0).
congruence.
apply (IHm2 _ _ _ H1).
apply (IHm1 _ _ _ H0).
apply (IHm2 _ _ _ H0).
Qed.
Lemma xelements_ih :
forall (A: Type) (m1 m2: t A) (o: option A) (i : positive) (v: A),
In (xI i, v) (xelements (Node m1 o m2) xH) -> In (i, v) (xelements m2 xH).
Proof.
destruct o; simpl; intros; destruct (in_app_or _ _ _ H).
absurd (In (xI i, v) (xelements m1 2)); auto; apply xelements_io; auto.
destruct (in_inv H0).
congruence.
apply xelements_ii; auto.
absurd (In (xI i, v) (xelements m1 2)); auto; apply xelements_io; auto.
apply xelements_ii; auto.
Qed.
Lemma xelements_oh :
forall (A: Type) (m1 m2: t A) (o: option A) (i : positive) (v: A),
In (xO i, v) (xelements (Node m1 o m2) xH) -> In (i, v) (xelements m1 xH).
Proof.
destruct o; simpl; intros; destruct (in_app_or _ _ _ H).
apply xelements_oo; auto.
destruct (in_inv H0).
congruence.
absurd (In (xO i, v) (xelements m2 3)); auto; apply xelements_oi; auto.
apply xelements_oo; auto.
absurd (In (xO i, v) (xelements m2 3)); auto; apply xelements_oi; auto.
Qed.
Lemma xelements_hi :
forall (A: Type) (m: t A) (i : positive) (v: A),
~In (xH, v) (xelements m (xI i)).
Proof.
induction m; intros.
simpl; auto.
destruct o; simpl; intro H; destruct (in_app_or _ _ _ H).
generalize H0; apply IHm1; auto.
destruct (in_inv H0).
congruence.
generalize H1; apply IHm2; auto.
generalize H0; apply IHm1; auto.
generalize H0; apply IHm2; auto.
Qed.
Lemma xelements_ho :
forall (A: Type) (m: t A) (i : positive) (v: A),
~In (xH, v) (xelements m (xO i)).
Proof.
induction m; intros.
simpl; auto.
destruct o; simpl; intro H; destruct (in_app_or _ _ _ H).
generalize H0; apply IHm1; auto.
destruct (in_inv H0).
congruence.
generalize H1; apply IHm2; auto.
generalize H0; apply IHm1; auto.
generalize H0; apply IHm2; auto.
Qed.
Lemma get_xget_h :
forall (A: Type) (m: t A) (i: positive), get i m = xget i xH m.
Proof.
destruct i; simpl; auto.
Qed.
Lemma xelements_complete:
forall (A: Type) (i j : positive) (m: t A) (v: A),
In (i, v) (xelements m j) -> xget i j m = Some v.
Proof.
induction i; simpl; intros; destruct j; simpl.
apply IHi; apply xelements_ii; auto.
absurd (In (xI i, v) (xelements m (xO j))); auto; apply xelements_io.
destruct m.
simpl in H; tauto.
rewrite get_xget_h. apply IHi. apply (xelements_ih _ _ _ _ _ H).
absurd (In (xO i, v) (xelements m (xI j))); auto; apply xelements_oi.
apply IHi; apply xelements_oo; auto.
destruct m.
simpl in H; tauto.
rewrite get_xget_h. apply IHi. apply (xelements_oh _ _ _ _ _ H).
absurd (In (xH, v) (xelements m (xI j))); auto; apply xelements_hi.
absurd (In (xH, v) (xelements m (xO j))); auto; apply xelements_ho.
destruct m.
simpl in H; tauto.
destruct o; simpl in H; destruct (in_app_or _ _ _ H).
absurd (In (xH, v) (xelements m1 (xO xH))); auto; apply xelements_ho.
destruct (in_inv H0).
congruence.
absurd (In (xH, v) (xelements m2 (xI xH))); auto; apply xelements_hi.
absurd (In (xH, v) (xelements m1 (xO xH))); auto; apply xelements_ho.
absurd (In (xH, v) (xelements m2 (xI xH))); auto; apply xelements_hi.
Qed.
Theorem elements_complete:
forall (A: Type) (m: t A) (i: positive) (v: A),
In (i, v) (elements m) -> get i m = Some v.
Proof.
intros A m i v H.
unfold elements in H.
rewrite get_xget_h.
exact (xelements_complete i xH m v H).
Qed.
Lemma in_xelements:
forall (A: Type) (m: t A) (i k: positive) (v: A),
In (k, v) (xelements m i) ->
exists j, k = append i j.
Proof.
induction m; simpl; intros.
tauto.
assert (k = i \/ In (k, v) (xelements m1 (append i 2))
\/ In (k, v) (xelements m2 (append i 3))).
destruct o.
elim (in_app_or _ _ _ H); simpl; intuition.
replace k with i. tauto. congruence.
elim (in_app_or _ _ _ H); simpl; intuition.
elim H0; intro.
exists xH. rewrite append_neutral_r. auto.
elim H1; intro.
elim (IHm1 _ _ _ H2). intros k1 EQ. rewrite EQ.
rewrite <- append_assoc_0. exists (xO k1); auto.
elim (IHm2 _ _ _ H2). intros k1 EQ. rewrite EQ.
rewrite <- append_assoc_1. exists (xI k1); auto.
Qed.
Definition xkeys (A: Type) (m: t A) (i: positive) :=
List.map (@fst positive A) (xelements m i).
Lemma in_xkeys:
forall (A: Type) (m: t A) (i k: positive),
In k (xkeys m i) ->
exists j, k = append i j.
Proof.
unfold xkeys; intros.
elim (list_in_map_inv _ _ _ H). intros [k1 v1] [EQ IN].
simpl in EQ; subst k1. apply in_xelements with A m v1. auto.
Qed.
Remark list_append_cons_norepet:
forall (A: Type) (l1 l2: list A) (x: A),
list_norepet l1 -> list_norepet l2 -> list_disjoint l1 l2 ->
~In x l1 -> ~In x l2 ->
list_norepet (l1 ++ x :: l2).
Proof.
intros. apply list_norepet_append_commut. simpl; constructor.
red; intros. elim (in_app_or _ _ _ H4); intro; tauto.
apply list_norepet_append; auto.
apply list_disjoint_sym; auto.
Qed.
Lemma append_injective:
forall i j1 j2, append i j1 = append i j2 -> j1 = j2.
Proof.
induction i; simpl; intros.
apply IHi. congruence.
apply IHi. congruence.
auto.
Qed.
Lemma xelements_keys_norepet:
forall (A: Type) (m: t A) (i: positive),
list_norepet (xkeys m i).
Proof.
induction m; unfold xkeys; simpl; fold xkeys; intros.
constructor.
assert (list_disjoint (xkeys m1 (append i 2)) (xkeys m2 (append i 3))).
red; intros; red; intro. subst y.
elim (in_xkeys _ _ _ H); intros j1 EQ1.
elim (in_xkeys _ _ _ H0); intros j2 EQ2.
rewrite EQ1 in EQ2.
rewrite <- append_assoc_0 in EQ2.
rewrite <- append_assoc_1 in EQ2.
generalize (append_injective _ _ _ EQ2). congruence.
assert (forall (m: t A) j,
j = 2%positive \/ j = 3%positive ->
~In i (xkeys m (append i j))).
intros; red; intros.
elim (in_xkeys _ _ _ H1); intros k EQ.
assert (EQ1: append i xH = append (append i j) k).
rewrite append_neutral_r. auto.
elim H0; intro; subst j;
try (rewrite <- append_assoc_0 in EQ1);
try (rewrite <- append_assoc_1 in EQ1);
generalize (append_injective _ _ _ EQ1); congruence.
destruct o; rewrite list_append_map; simpl;
change (List.map (@fst positive A) (xelements m1 (append i 2)))
with (xkeys m1 (append i 2));
change (List.map (@fst positive A) (xelements m2 (append i 3)))
with (xkeys m2 (append i 3)).
apply list_append_cons_norepet; auto.
apply list_norepet_append; auto.
Qed.
Theorem elements_keys_norepet:
forall (A: Type) (m: t A),
list_norepet (List.map (@fst elt A) (elements m)).
Proof.
intros. change (list_norepet (xkeys m 1)). apply xelements_keys_norepet.
Qed.
Theorem elements_canonical_order:
forall (A B: Type) (R: A -> B -> Prop) (m: t A) (n: t B),
(forall i x, get i m = Some x -> exists y, get i n = Some y /\ R x y) ->
(forall i y, get i n = Some y -> exists x, get i m = Some x /\ R x y) ->
list_forall2
(fun i_x i_y => fst i_x = fst i_y /\ R (snd i_x) (snd i_y))
(elements m) (elements n).
Proof.
intros until R.
assert (forall m n j,
(forall i x, get i m = Some x -> exists y, get i n = Some y /\ R x y) ->
(forall i y, get i n = Some y -> exists x, get i m = Some x /\ R x y) ->
list_forall2
(fun i_x i_y => fst i_x = fst i_y /\ R (snd i_x) (snd i_y))
(xelements m j) (xelements n j)).
induction m; induction n; intros; simpl.
constructor.
destruct o. exploit (H0 xH). simpl. reflexivity. simpl. intros [x [P Q]]. congruence.
change (@nil (positive*A)) with ((@nil (positive * A))++nil).
apply list_forall2_app.
apply IHn1.
intros. rewrite gleaf in H1. congruence.
intros. exploit (H0 (xO i)). simpl; eauto. rewrite gleaf. intros [x [P Q]]. congruence.
apply IHn2.
intros. rewrite gleaf in H1. congruence.
intros. exploit (H0 (xI i)). simpl; eauto. rewrite gleaf. intros [x [P Q]]. congruence.
destruct o. exploit (H xH). simpl. reflexivity. simpl. intros [x [P Q]]. congruence.
change (@nil (positive*B)) with (xelements (@Leaf B) (append j 2) ++ (xelements (@Leaf B) (append j 3))).
apply list_forall2_app.
apply IHm1.
intros. exploit (H (xO i)). simpl; eauto. rewrite gleaf. intros [y [P Q]]. congruence.
intros. rewrite gleaf in H1. congruence.
apply IHm2.
intros. exploit (H (xI i)). simpl; eauto. rewrite gleaf. intros [y [P Q]]. congruence.
intros. rewrite gleaf in H1. congruence.
exploit (IHm1 n1 (append j 2)).
intros. exploit (H (xO i)). simpl; eauto. simpl. auto.
intros. exploit (H0 (xO i)). simpl; eauto. simpl; auto.
intro REC1.
exploit (IHm2 n2 (append j 3)).
intros. exploit (H (xI i)). simpl; eauto. simpl. auto.
intros. exploit (H0 (xI i)). simpl; eauto. simpl; auto.
intro REC2.
destruct o; destruct o0.
apply list_forall2_app; auto. constructor; auto.
simpl; split; auto. exploit (H xH). simpl; eauto. simpl. intros [y [P Q]]. congruence.
exploit (H xH). simpl; eauto. simpl. intros [y [P Q]]; congruence.
exploit (H0 xH). simpl; eauto. simpl. intros [x [P Q]]; congruence.
apply list_forall2_app; auto.
unfold elements; auto.
Qed.
Theorem elements_extensional:
forall (A: Type) (m n: t A),
(forall i, get i m = get i n) ->
elements m = elements n.
Proof.
intros.
exploit (elements_canonical_order (fun (x y: A) => x = y) m n).
intros. rewrite H in H0. exists x; auto.
intros. rewrite <- H in H0. exists y; auto.
induction 1. auto. destruct a1 as [a2 a3]; destruct b1 as [b2 b3]; simpl in *.
destruct H0. congruence.
Qed.
Fixpoint xfold (A B: Type) (f: B -> positive -> A -> B)
(i: positive) (m: t A) (v: B) {struct m} : B :=
match m with
| Leaf => v
| Node l None r =>
let v1 := xfold f (append i (xO xH)) l v in
xfold f (append i (xI xH)) r v1
| Node l (Some x) r =>
let v1 := xfold f (append i (xO xH)) l v in
let v2 := f v1 i x in
xfold f (append i (xI xH)) r v2
end.
Definition fold (A B : Type) (f: B -> positive -> A -> B) (m: t A) (v: B) :=
xfold f xH m v.
Lemma xfold_xelements:
forall (A B: Type) (f: B -> positive -> A -> B) m i v,
xfold f i m v =
List.fold_left (fun a p => f a (fst p) (snd p))
(xelements m i)
v.
Proof.
induction m; intros.
simpl. auto.
simpl. destruct o.
rewrite fold_left_app. simpl.
rewrite IHm1. apply IHm2.
rewrite fold_left_app. simpl.
rewrite IHm1. apply IHm2.
Qed.
Theorem fold_spec:
forall (A B: Type) (f: B -> positive -> A -> B) (v: B) (m: t A),
fold f m v =
List.fold_left (fun a p => f a (fst p) (snd p)) (elements m) v.
Proof.
intros. unfold fold, elements. apply xfold_xelements.
Qed.
End PTree.
(** * An implementation of maps over type [positive] *)
Module PMap <: MAP.
Definition elt := positive.
Definition elt_eq := peq.
Definition t (A : Type) : Type := (A * PTree.t A)%type.
Definition init (A : Type) (x : A) :=
(x, PTree.empty A).
Definition get (A : Type) (i : positive) (m : t A) :=
match PTree.get i (snd m) with
| Some x => x
| None => fst m
end.
Definition set (A : Type) (i : positive) (x : A) (m : t A) :=
(fst m, PTree.set i x (snd m)).
Theorem gi:
forall (A: Type) (i: positive) (x: A), get i (init x) = x.
Proof.
intros. unfold init. unfold get. simpl. rewrite PTree.gempty. auto.
Qed.
Theorem gss:
forall (A: Type) (i: positive) (x: A) (m: t A), get i (set i x m) = x.
Proof.
intros. unfold get. unfold set. simpl. rewrite PTree.gss. auto.
Qed.
Theorem gso:
forall (A: Type) (i j: positive) (x: A) (m: t A),
i <> j -> get i (set j x m) = get i m.
Proof.
intros. unfold get. unfold set. simpl. rewrite PTree.gso; auto.
Qed.
Theorem gsspec:
forall (A: Type) (i j: positive) (x: A) (m: t A),
get i (set j x m) = if peq i j then x else get i m.
Proof.
intros. destruct (peq i j).
rewrite e. apply gss. auto.
apply gso. auto.
Qed.
Theorem gsident:
forall (A: Type) (i j: positive) (m: t A),
get j (set i (get i m) m) = get j m.
Proof.
intros. destruct (peq i j).
rewrite e. rewrite gss. auto.
rewrite gso; auto.
Qed.
Definition map (A B : Type) (f : A -> B) (m : t A) : t B :=
(f (fst m), PTree.map1 f (snd m)).
Theorem gmap:
forall (A B: Type) (f: A -> B) (i: positive) (m: t A),
get i (map f m) = f(get i m).
Proof.
intros. unfold map. unfold get. simpl. rewrite PTree.gmap1.
unfold option_map. destruct (PTree.get i (snd m)); auto.
Qed.
Theorem set2:
forall (A: Type) (i: elt) (x y: A) (m: t A),
set i y (set i x m) = set i y m.
Proof.
intros. unfold set. simpl. decEq. apply PTree.set2.
Qed.
End PMap.
(** * An implementation of maps over any type that injects into type [positive] *)
Module Type INDEXED_TYPE.
Variable t: Type.
Variable index: t -> positive.
Hypothesis index_inj: forall (x y: t), index x = index y -> x = y.
Variable eq: forall (x y: t), {x = y} + {x <> y}.
End INDEXED_TYPE.
Module IMap(X: INDEXED_TYPE).
Definition elt := X.t.
Definition elt_eq := X.eq.
Definition t : Type -> Type := PMap.t.
Definition init (A: Type) (x: A) := PMap.init x.
Definition get (A: Type) (i: X.t) (m: t A) := PMap.get (X.index i) m.
Definition set (A: Type) (i: X.t) (v: A) (m: t A) := PMap.set (X.index i) v m.
Definition map (A B: Type) (f: A -> B) (m: t A) : t B := PMap.map f m.
Lemma gi:
forall (A: Type) (x: A) (i: X.t), get i (init x) = x.
Proof.
intros. unfold get, init. apply PMap.gi.
Qed.
Lemma gss:
forall (A: Type) (i: X.t) (x: A) (m: t A), get i (set i x m) = x.
Proof.
intros. unfold get, set. apply PMap.gss.
Qed.
Lemma gso:
forall (A: Type) (i j: X.t) (x: A) (m: t A),
i <> j -> get i (set j x m) = get i m.
Proof.
intros. unfold get, set. apply PMap.gso.
red. intro. apply H. apply X.index_inj; auto.
Qed.
Lemma gsspec:
forall (A: Type) (i j: X.t) (x: A) (m: t A),
get i (set j x m) = if X.eq i j then x else get i m.
Proof.
intros. unfold get, set.
rewrite PMap.gsspec.
case (X.eq i j); intro.
subst j. rewrite peq_true. reflexivity.
rewrite peq_false. reflexivity.
red; intro. elim n. apply X.index_inj; auto.
Qed.
Lemma gmap:
forall (A B: Type) (f: A -> B) (i: X.t) (m: t A),
get i (map f m) = f(get i m).
Proof.
intros. unfold map, get. apply PMap.gmap.
Qed.
Lemma set2:
forall (A: Type) (i: elt) (x y: A) (m: t A),
set i y (set i x m) = set i y m.
Proof.
intros. unfold set. apply PMap.set2.
Qed.
End IMap.
Module ZIndexed.
Definition t := Z.
Definition index (z: Z): positive :=
match z with
| Z0 => xH
| Zpos p => xO p
| Zneg p => xI p
end.
Lemma index_inj: forall (x y: Z), index x = index y -> x = y.
Proof.
unfold index; destruct x; destruct y; intros;
try discriminate; try reflexivity.
congruence.
congruence.
Qed.
Definition eq := zeq.
End ZIndexed.
Module ZMap := IMap(ZIndexed).
Module NIndexed.
Definition t := N.
Definition index (n: N): positive :=
match n with
| N0 => xH
| Npos p => xO p
end.
Lemma index_inj: forall (x y: N), index x = index y -> x = y.
Proof.
unfold index; destruct x; destruct y; intros;
try discriminate; try reflexivity.
congruence.
Qed.
Lemma eq: forall (x y: N), {x = y} + {x <> y}.
Proof.
decide equality. apply peq.
Qed.
End NIndexed.
Module NMap := IMap(NIndexed).
(** * An implementation of maps over any type with decidable equality *)
Module Type EQUALITY_TYPE.
Variable t: Type.
Variable eq: forall (x y: t), {x = y} + {x <> y}.
End EQUALITY_TYPE.
Module EMap(X: EQUALITY_TYPE) <: MAP.
Definition elt := X.t.
Definition elt_eq := X.eq.
Definition t (A: Type) := X.t -> A.
Definition init (A: Type) (v: A) := fun (_: X.t) => v.
Definition get (A: Type) (x: X.t) (m: t A) := m x.
Definition set (A: Type) (x: X.t) (v: A) (m: t A) :=
fun (y: X.t) => if X.eq y x then v else m y.
Lemma gi:
forall (A: Type) (i: elt) (x: A), init x i = x.
Proof.
intros. reflexivity.
Qed.
Lemma gss:
forall (A: Type) (i: elt) (x: A) (m: t A), (set i x m) i = x.
Proof.
intros. unfold set. case (X.eq i i); intro.
reflexivity. tauto.
Qed.
Lemma gso:
forall (A: Type) (i j: elt) (x: A) (m: t A),
i <> j -> (set j x m) i = m i.
Proof.
intros. unfold set. case (X.eq i j); intro.
congruence. reflexivity.
Qed.
Lemma gsspec:
forall (A: Type) (i j: elt) (x: A) (m: t A),
get i (set j x m) = if elt_eq i j then x else get i m.
Proof.
intros. unfold get, set, elt_eq. reflexivity.
Qed.
Lemma gsident:
forall (A: Type) (i j: elt) (m: t A), get j (set i (get i m) m) = get j m.
Proof.
intros. unfold get, set. case (X.eq j i); intro.
congruence. reflexivity.
Qed.
Definition map (A B: Type) (f: A -> B) (m: t A) :=
fun (x: X.t) => f(m x).
Lemma gmap:
forall (A B: Type) (f: A -> B) (i: elt) (m: t A),
get i (map f m) = f(get i m).
Proof.
intros. unfold get, map. reflexivity.
Qed.
End EMap.
(** * Additional properties over trees *)
Module Tree_Properties(T: TREE).
(** An induction principle over [fold]. *)
Section TREE_FOLD_IND.
Variables V A: Type.
Variable f: A -> T.elt -> V -> A.
Variable P: T.t V -> A -> Prop.
Variable init: A.
Variable m_final: T.t V.
Hypothesis P_compat:
forall m m' a,
(forall x, T.get x m = T.get x m') ->
P m a -> P m' a.
Hypothesis H_base:
P (T.empty _) init.
Hypothesis H_rec:
forall m a k v,
T.get k m = None -> T.get k m_final = Some v -> P m a -> P (T.set k v m) (f a k v).
Let f' (a: A) (p : T.elt * V) := f a (fst p) (snd p).
Let P' (l: list (T.elt * V)) (a: A) : Prop :=
forall m, list_equiv l (T.elements m) -> P m a.
Remark H_base':
P' nil init.
Proof.
red; intros. apply P_compat with (T.empty _); auto.
intros. rewrite T.gempty. symmetry. case_eq (T.get x m); intros; auto.
assert (In (x, v) nil). rewrite (H (x, v)). apply T.elements_correct. auto.
contradiction.
Qed.
Remark H_rec':
forall k v l a,
~In k (List.map (@fst T.elt V) l) ->
In (k, v) (T.elements m_final) ->
P' l a ->
P' (l ++ (k, v) :: nil) (f a k v).
Proof.
unfold P'; intros.
set (m0 := T.remove k m).
apply P_compat with (T.set k v m0).
intros. unfold m0. rewrite T.gsspec. destruct (T.elt_eq x k).
symmetry. apply T.elements_complete. rewrite <- (H2 (x, v)).
apply in_or_app. simpl. intuition congruence.
apply T.gro. auto.
apply H_rec. unfold m0. apply T.grs. apply T.elements_complete. auto.
apply H1. red. intros [k' v'].
split; intros.
apply T.elements_correct. unfold m0. rewrite T.gro. apply T.elements_complete.
rewrite <- (H2 (k', v')). apply in_or_app. auto.
red; intro; subst k'. elim H. change k with (fst (k, v')). apply in_map. auto.
assert (T.get k' m0 = Some v'). apply T.elements_complete. auto.
unfold m0 in H4. rewrite T.grspec in H4. destruct (T.elt_eq k' k). congruence.
assert (In (k', v') (T.elements m)). apply T.elements_correct; auto.
rewrite <- (H2 (k', v')) in H5. destruct (in_app_or _ _ _ H5). auto.
simpl in H6. intuition congruence.
Qed.
Lemma fold_rec_aux:
forall l1 l2 a,
list_equiv (l2 ++ l1) (T.elements m_final) ->
list_disjoint (List.map (@fst T.elt V) l1) (List.map (@fst T.elt V) l2) ->
list_norepet (List.map (@fst T.elt V) l1) ->
P' l2 a -> P' (l2 ++ l1) (List.fold_left f' l1 a).
Proof.
induction l1; intros; simpl.
rewrite <- List.app_nil_end. auto.
destruct a as [k v]; simpl in *. inv H1.
change ((k, v) :: l1) with (((k, v) :: nil) ++ l1). rewrite <- List.app_ass. apply IHl1.
rewrite app_ass. auto.
red; intros. rewrite map_app in H3. destruct (in_app_or _ _ _ H3). apply H0; auto with coqlib.
simpl in H4. intuition congruence.
auto.
unfold f'. simpl. apply H_rec'; auto. eapply list_disjoint_notin; eauto with coqlib.
rewrite <- (H (k, v)). apply in_or_app. simpl. auto.
Qed.
Theorem fold_rec:
P m_final (T.fold f m_final init).
Proof.
intros. rewrite T.fold_spec. fold f'.
assert (P' (nil ++ T.elements m_final) (List.fold_left f' (T.elements m_final) init)).
apply fold_rec_aux.
simpl. red; intros; tauto.
simpl. red; intros. elim H0.
apply T.elements_keys_norepet.
apply H_base'.
simpl in H. red in H. apply H. red; intros. tauto.
Qed.
End TREE_FOLD_IND.
(** A nonnegative measure over trees *)
Section MEASURE.
Variable V: Type.
Definition cardinal (x: T.t V) : nat := List.length (T.elements x).
Remark list_incl_length:
forall (A: Type) (l1: list A), list_norepet l1 ->
forall (l2: list A), List.incl l1 l2 -> (List.length l1 <= List.length l2)%nat.
Proof.
induction 1; simpl; intros.
omega.
exploit (List.in_split hd l2). auto with coqlib. intros [l3 [l4 EQ]]. subst l2.
assert (length tl <= length (l3 ++ l4))%nat.
apply IHlist_norepet. red; intros.
exploit (H1 a); auto with coqlib.
repeat rewrite in_app_iff. simpl. intuition. subst. contradiction.
repeat rewrite app_length in *. simpl. omega.
Qed.
Remark list_length_incl:
forall (A: Type) (l1: list A), list_norepet l1 ->
forall l2, List.incl l1 l2 -> List.length l1 = List.length l2 -> List.incl l2 l1.
Proof.
induction 1; simpl; intros.
destruct l2; simpl in *. auto with coqlib. discriminate.
exploit (List.in_split hd l2). auto with coqlib. intros [l3 [l4 EQ]]. subst l2.
assert (incl (l3 ++ l4) tl).
apply IHlist_norepet. red; intros.
exploit (H1 a); auto with coqlib.
repeat rewrite in_app_iff. simpl. intuition. subst. contradiction.
repeat rewrite app_length in *. simpl in H2. omega.
red; simpl; intros. rewrite in_app_iff in H4; simpl in H4. intuition.
Qed.
Remark list_strict_incl_length:
forall (A: Type) (l1 l2: list A) (x: A),
list_norepet l1 -> List.incl l1 l2 -> ~In x l1 -> In x l2 ->
(List.length l1 < List.length l2)%nat.
Proof.
intros. exploit list_incl_length; eauto. intros.
assert (length l1 = length l2 \/ length l1 < length l2)%nat by omega.
destruct H4; auto. elim H1. eapply list_length_incl; eauto.
Qed.
Remark list_norepet_map:
forall (A B: Type) (f: A -> B) (l: list A),
list_norepet (List.map f l) -> list_norepet l.
Proof.
induction l; simpl; intros.
constructor.
inv H. constructor; auto. red; intros; elim H2. apply List.in_map; auto.
Qed.
Theorem cardinal_remove:
forall x m y, T.get x m = Some y -> (cardinal (T.remove x m) < cardinal m)%nat.
Proof.
unfold cardinal; intros. apply list_strict_incl_length with (x := (x, y)).
apply list_norepet_map with (f := @fst T.elt V). apply T.elements_keys_norepet.
red; intros. destruct a as [x' y']. exploit T.elements_complete; eauto.
rewrite T.grspec. destruct (T.elt_eq x' x); intros; try discriminate.
apply T.elements_correct; auto.
red; intros. exploit T.elements_complete; eauto. rewrite T.grspec. rewrite dec_eq_true. congruence.
apply T.elements_correct; auto.
Qed.
End MEASURE.
(** Forall and exists *)
Section FORALL_EXISTS.
Variable A: Type.
Definition for_all (m: T.t A) (f: T.elt -> A -> bool) : bool :=
T.fold (fun b x a => b && f x a) m true.
Lemma for_all_correct:
forall m f,
for_all m f = true <-> (forall x a, T.get x m = Some a -> f x a = true).
Proof.
intros m0 f.
unfold for_all. apply fold_rec; intros.
- (* Extensionality *)
rewrite H0. split; intros. rewrite <- H in H2; auto. rewrite H in H2; auto.
- (* Base case *)
split; intros. rewrite T.gempty in H0; congruence. auto.
- (* Inductive case *)
split; intros.
destruct (andb_prop _ _ H2). rewrite T.gsspec in H3. destruct (T.elt_eq x k).
inv H3. auto.
apply H1; auto.
apply andb_true_intro. split.
rewrite H1. intros. apply H2. rewrite T.gso; auto. congruence.
apply H2. apply T.gss.
Qed.
Definition exists_ (m: T.t A) (f: T.elt -> A -> bool) : bool :=
T.fold (fun b x a => b || f x a) m false.
Lemma exists_correct:
forall m f,
exists_ m f = true <-> (exists x a, T.get x m = Some a /\ f x a = true).
Proof.
intros m0 f.
unfold exists_. apply fold_rec; intros.
- (* Extensionality *)
rewrite H0. split; intros (x0 & a0 & P & Q); exists x0; exists a0; split; auto; congruence.
- (* Base case *)
split; intros. congruence. destruct H as (x & a & P & Q). rewrite T.gempty in P; congruence.
- (* Inductive case *)
split; intros.
destruct (orb_true_elim _ _ H2).
rewrite H1 in e. destruct e as (x1 & a1 & P & Q).
exists x1; exists a1; split; auto. rewrite T.gso; auto. congruence.
exists k; exists v; split; auto. apply T.gss.
destruct H2 as (x1 & a1 & P & Q). apply orb_true_intro.
rewrite T.gsspec in P. destruct (T.elt_eq x1 k).
inv P. right; auto.
left. apply H1. exists x1; exists a1; auto.
Qed.
Remark exists_for_all:
forall m f,
exists_ m f = negb (for_all m (fun x a => negb (f x a))).
Proof.
intros. unfold exists_, for_all. rewrite ! T.fold_spec.
change false with (negb true). generalize (T.elements m) true.
induction l; simpl; intros.
auto.
rewrite <- IHl. f_equal.
destruct b; destruct (f (fst a) (snd a)); reflexivity.
Qed.
Remark for_all_exists:
forall m f,
for_all m f = negb (exists_ m (fun x a => negb (f x a))).
Proof.
intros. unfold exists_, for_all. rewrite ! T.fold_spec.
change true with (negb false). generalize (T.elements m) false.
induction l; simpl; intros.
auto.
rewrite <- IHl. f_equal.
destruct b; destruct (f (fst a) (snd a)); reflexivity.
Qed.
Lemma for_all_false:
forall m f,
for_all m f = false <-> (exists x a, T.get x m = Some a /\ f x a = false).
Proof.
intros. rewrite for_all_exists.
rewrite negb_false_iff. rewrite exists_correct.
split; intros (x & a & P & Q); exists x; exists a; split; auto.
rewrite negb_true_iff in Q. auto.
rewrite Q; auto.
Qed.
Lemma exists_false:
forall m f,
exists_ m f = false <-> (forall x a, T.get x m = Some a -> f x a = false).
Proof.
intros. rewrite exists_for_all.
rewrite negb_false_iff. rewrite for_all_correct.
split; intros. apply H in H0. rewrite negb_true_iff in H0. auto. rewrite H; auto.
Qed.
End FORALL_EXISTS.
(** More about [beq] *)
Section BOOLEAN_EQUALITY.
Variable A: Type.
Variable beqA: A -> A -> bool.
Theorem beq_false:
forall m1 m2,
T.beq beqA m1 m2 = false <->
exists x, match T.get x m1, T.get x m2 with
| None, None => False
| Some a1, Some a2 => beqA a1 a2 = false
| _, _ => True
end.
Proof.
intros; split; intros.
- (* beq = false -> existence *)
set (p1 := fun x a1 => match T.get x m2 with None => false | Some a2 => beqA a1 a2 end).
set (p2 := fun x a2 => match T.get x m1 with None => false | Some a1 => beqA a1 a2 end).
destruct (for_all m1 p1) eqn:F1; [destruct (for_all m2 p2) eqn:F2 | idtac].
+ cut (T.beq beqA m1 m2 = true). congruence.
rewrite for_all_correct in *. rewrite T.beq_correct; intros.
destruct (T.get x m1) as [a1|] eqn:X1.
generalize (F1 _ _ X1). unfold p1. destruct (T.get x m2); congruence.
destruct (T.get x m2) as [a2|] eqn:X2; auto.
generalize (F2 _ _ X2). unfold p2. rewrite X1. congruence.
+ rewrite for_all_false in F2. destruct F2 as (x & a & P & Q).
exists x. rewrite P. unfold p2 in Q. destruct (T.get x m1); auto.
+ rewrite for_all_false in F1. destruct F1 as (x & a & P & Q).
exists x. rewrite P. unfold p1 in Q. destruct (T.get x m2); auto.
- (* existence -> beq = false *)
destruct H as [x P].
destruct (T.beq beqA m1 m2) eqn:E; auto.
rewrite T.beq_correct in E.
generalize (E x). destruct (T.get x m1); destruct (T.get x m2); tauto || congruence.
Qed.
End BOOLEAN_EQUALITY.
(** Extensional equality between trees *)
Section EXTENSIONAL_EQUALITY.
Variable A: Type.
Variable eqA: A -> A -> Prop.
Hypothesis eqAeq: Equivalence eqA.
Definition Equal (m1 m2: T.t A) : Prop :=
forall x, match T.get x m1, T.get x m2 with
| None, None => True
| Some a1, Some a2 => a1 === a2
| _, _ => False
end.
Lemma Equal_refl: forall m, Equal m m.
Proof.
intros; red; intros. destruct (T.get x m); auto. reflexivity.
Qed.
Lemma Equal_sym: forall m1 m2, Equal m1 m2 -> Equal m2 m1.
Proof.
intros; red; intros. generalize (H x). destruct (T.get x m1); destruct (T.get x m2); auto. intros; symmetry; auto.
Qed.
Lemma Equal_trans: forall m1 m2 m3, Equal m1 m2 -> Equal m2 m3 -> Equal m1 m3.
Proof.
intros; red; intros. generalize (H x) (H0 x).
destruct (T.get x m1); destruct (T.get x m2); try tauto;
destruct (T.get x m3); try tauto.
intros. transitivity a0; auto.
Qed.
Instance Equal_Equivalence : Equivalence Equal := {
Equivalence_Reflexive := Equal_refl;
Equivalence_Symmetric := Equal_sym;
Equivalence_Transitive := Equal_trans
}.
Hypothesis eqAdec: EqDec A eqA.
Program Definition Equal_dec (m1 m2: T.t A) : { m1 === m2 } + { m1 =/= m2 } :=
match T.beq (fun a1 a2 => proj_sumbool (a1 == a2)) m1 m2 with
| true => left _
| false => right _
end.
Next Obligation.
rename Heq_anonymous into B.
symmetry in B. rewrite T.beq_correct in B.
red; intros. generalize (B x).
destruct (T.get x m1); destruct (T.get x m2); auto.
intros. eapply proj_sumbool_true; eauto.
Qed.
Next Obligation.
assert (T.beq (fun a1 a2 => proj_sumbool (a1 == a2)) m1 m2 = true).
apply T.beq_correct; intros.
generalize (H x).
destruct (T.get x m1); destruct (T.get x m2); try tauto.
intros. apply proj_sumbool_is_true; auto.
unfold equiv, complement in H0. congruence.
Qed.
Instance Equal_EqDec : EqDec (T.t A) Equal := Equal_dec.
End EXTENSIONAL_EQUALITY.
End Tree_Properties.
Module PTree_Properties := Tree_Properties(PTree).
(** * Useful notations *)
Notation "a ! b" := (PTree.get b a) (at level 1).
Notation "a !! b" := (PMap.get b a) (at level 1).
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_PP_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_SYMBOL_V
`define SKY130_FD_SC_HVL__O22AI_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o22ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_TB_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_TB_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_pwrgood_l_pp_pg_s.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
reg VGND;
reg SLEEP;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
SLEEP = 1'bX;
UDP_IN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 SLEEP = 1'b0;
#40 UDP_IN = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 SLEEP = 1'b1;
#120 UDP_IN = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 SLEEP = 1'b0;
#200 UDP_IN = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 UDP_IN = 1'b1;
#320 SLEEP = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 UDP_IN = 1'bx;
#400 SLEEP = 1'bx;
end
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .SLEEP(SLEEP), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSTP_4_V
`define SKY130_FD_SC_HD__SDFSTP_4_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSTP_4_V
|
module fifo # (parameter abits = 400, dbits = 1)(
input reset, clock,
input rd, wr,
input [dbits-1:0] din,
output [dbits-1:0] dout,
output empty,
output full,
output reg ledres
);
wire db_wr;
wire db_rd;
reg dffw1, dffr1;
reg [dbits-1:0] out;
initial ledres = 0;
reg [1:0] count;
reg [1:0] count1;
//always @ (posedge clock) dffw1 <= ~wr;
//always @ (posedge clock) dffw2 <= rd;
assign db_wr = dffw1; //monostable multivibrator to detect only one pulse of the button
//always @ (posedge clock) dffr1 <= rd;
//always @ (posedge clock) dffr2 <= dffr1;
assign db_rd = dffr1; //monostable multivibrator to detect only one pulse of the button
reg [dbits-1:0] regarray[2**abits-1:0]; //number of words in fifo = 2^(number of address bits)
reg [abits-1:0] wr_reg, wr_next, wr_succ; //points to the register that needs to be written to
reg [abits-1:0] rd_reg, rd_next, rd_succ; //points to the register that needs to be read from
reg full_reg, empty_reg, full_next, empty_next;
assign wr_en = db_wr & ~full; //only write if write signal is high and fifo is not full
always @ (posedge clock)//only write
begin
if(wr && ~rd)
begin
if(count)
begin
//dffr1<=0;
dffw1<=0;
count<=count+1;
end
else
begin
//dffr1<=0;
dffw1<=1;
count<=0;
end
end
else dffw1<=0;
end
always @ (posedge clock)//only read
begin
if(rd && ~wr)
begin
if(count1)
begin
//dffw1<=0;
dffr1<=0;
count1<=count1+1;
end
else
begin
//dffw1<=0;
dffr1<=1;
count1<=0;
end
end
else dffr1<=0;
end
//always block for write operation
always @ (posedge clock)
begin
if(wr_en)
regarray[wr_reg] <= din; //at wr_reg location of regarray store what is given at din
end
//always block for read operation
always @ (posedge clock)
begin
if(db_rd)
out <= regarray[rd_reg];
end
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
wr_reg <= 0;
rd_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
ledres=0;
end
else
begin
wr_reg <= wr_next; //created the next registers to avoid the error of mixing blocking and non blocking assignment to the same signal
rd_reg <= rd_next;
full_reg <= full_next;
empty_reg <= empty_next;
ledres=1;
end
end
always @(clock)
begin
wr_succ = wr_reg + 1; //assigned to new value as wr_next cannot be tested for in same always block
rd_succ = rd_reg + 1; //assigned to new value as rd_next cannot be tested for in same always block
wr_next = wr_reg; //defaults state stays the same
rd_next = rd_reg; //defaults state stays the same
full_next = full_reg; //defaults state stays the same
empty_next = empty_reg; //defaults state stays the same
case({db_wr,db_rd})
//2'b00: do nothing LOL..
2'b01: //read
begin
if(~empty) //if fifo is not empty continue
begin
rd_next = rd_succ;
full_next = 1'b0;
if(rd_succ == wr_reg) //all data has been read
empty_next = 1'b1; //its empty again
end
end
2'b10: //write
begin
if(~full) //if fifo is not full continue
begin
wr_next = wr_succ;
empty_next = 1'b0;
if(wr_succ == (2**abits-1)) //all registers have been written to
full_next = 1'b1; //its full now
end
end
2'b11: //read and write
begin
wr_next = wr_succ;
rd_next = rd_succ;
end
//no empty or full flag will be checked for or asserted in this state since data is being written to and read from together it can not get full in this state.
endcase
end
assign full = full_reg;
assign empty = empty_reg;
assign dout = out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHE_TB_V
`define SKY130_FD_SC_LS__DECAPHE_TB_V
/**
* decaphe: Shielded Decoupling capacitance filler.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decaphe.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__decaphe dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHE_TB_V
|
// ledtest_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.0 595
`timescale 1 ps / 1 ps
module ledtest_mm_interconnect_1 (
input wire CLOCK_clk_clk, // CLOCK_clk.clk
input wire MM_BRIDGE_reset_reset_bridge_in_reset_reset, // MM_BRIDGE_reset_reset_bridge_in_reset.reset
input wire [4:0] MM_BRIDGE_m0_address, // MM_BRIDGE_m0.address
output wire MM_BRIDGE_m0_waitrequest, // .waitrequest
input wire [0:0] MM_BRIDGE_m0_burstcount, // .burstcount
input wire [3:0] MM_BRIDGE_m0_byteenable, // .byteenable
input wire MM_BRIDGE_m0_read, // .read
output wire [31:0] MM_BRIDGE_m0_readdata, // .readdata
output wire MM_BRIDGE_m0_readdatavalid, // .readdatavalid
input wire MM_BRIDGE_m0_write, // .write
input wire [31:0] MM_BRIDGE_m0_writedata, // .writedata
input wire MM_BRIDGE_m0_debugaccess, // .debugaccess
output wire [1:0] LED_ARRAY_s1_address, // LED_ARRAY_s1.address
output wire LED_ARRAY_s1_write, // .write
input wire [31:0] LED_ARRAY_s1_readdata, // .readdata
output wire [31:0] LED_ARRAY_s1_writedata, // .writedata
output wire LED_ARRAY_s1_chipselect, // .chipselect
output wire [1:0] SWITCH_ARRAY_s1_address, // SWITCH_ARRAY_s1.address
input wire [31:0] SWITCH_ARRAY_s1_readdata // .readdata
);
wire mm_bridge_m0_translator_avalon_universal_master_0_waitrequest; // MM_BRIDGE_m0_agent:av_waitrequest -> MM_BRIDGE_m0_translator:uav_waitrequest
wire [31:0] mm_bridge_m0_translator_avalon_universal_master_0_readdata; // MM_BRIDGE_m0_agent:av_readdata -> MM_BRIDGE_m0_translator:uav_readdata
wire mm_bridge_m0_translator_avalon_universal_master_0_debugaccess; // MM_BRIDGE_m0_translator:uav_debugaccess -> MM_BRIDGE_m0_agent:av_debugaccess
wire [4:0] mm_bridge_m0_translator_avalon_universal_master_0_address; // MM_BRIDGE_m0_translator:uav_address -> MM_BRIDGE_m0_agent:av_address
wire mm_bridge_m0_translator_avalon_universal_master_0_read; // MM_BRIDGE_m0_translator:uav_read -> MM_BRIDGE_m0_agent:av_read
wire [3:0] mm_bridge_m0_translator_avalon_universal_master_0_byteenable; // MM_BRIDGE_m0_translator:uav_byteenable -> MM_BRIDGE_m0_agent:av_byteenable
wire mm_bridge_m0_translator_avalon_universal_master_0_readdatavalid; // MM_BRIDGE_m0_agent:av_readdatavalid -> MM_BRIDGE_m0_translator:uav_readdatavalid
wire mm_bridge_m0_translator_avalon_universal_master_0_lock; // MM_BRIDGE_m0_translator:uav_lock -> MM_BRIDGE_m0_agent:av_lock
wire mm_bridge_m0_translator_avalon_universal_master_0_write; // MM_BRIDGE_m0_translator:uav_write -> MM_BRIDGE_m0_agent:av_write
wire [31:0] mm_bridge_m0_translator_avalon_universal_master_0_writedata; // MM_BRIDGE_m0_translator:uav_writedata -> MM_BRIDGE_m0_agent:av_writedata
wire [2:0] mm_bridge_m0_translator_avalon_universal_master_0_burstcount; // MM_BRIDGE_m0_translator:uav_burstcount -> MM_BRIDGE_m0_agent:av_burstcount
wire [31:0] led_array_s1_agent_m0_readdata; // LED_ARRAY_s1_translator:uav_readdata -> LED_ARRAY_s1_agent:m0_readdata
wire led_array_s1_agent_m0_waitrequest; // LED_ARRAY_s1_translator:uav_waitrequest -> LED_ARRAY_s1_agent:m0_waitrequest
wire led_array_s1_agent_m0_debugaccess; // LED_ARRAY_s1_agent:m0_debugaccess -> LED_ARRAY_s1_translator:uav_debugaccess
wire [4:0] led_array_s1_agent_m0_address; // LED_ARRAY_s1_agent:m0_address -> LED_ARRAY_s1_translator:uav_address
wire [3:0] led_array_s1_agent_m0_byteenable; // LED_ARRAY_s1_agent:m0_byteenable -> LED_ARRAY_s1_translator:uav_byteenable
wire led_array_s1_agent_m0_read; // LED_ARRAY_s1_agent:m0_read -> LED_ARRAY_s1_translator:uav_read
wire led_array_s1_agent_m0_readdatavalid; // LED_ARRAY_s1_translator:uav_readdatavalid -> LED_ARRAY_s1_agent:m0_readdatavalid
wire led_array_s1_agent_m0_lock; // LED_ARRAY_s1_agent:m0_lock -> LED_ARRAY_s1_translator:uav_lock
wire [31:0] led_array_s1_agent_m0_writedata; // LED_ARRAY_s1_agent:m0_writedata -> LED_ARRAY_s1_translator:uav_writedata
wire led_array_s1_agent_m0_write; // LED_ARRAY_s1_agent:m0_write -> LED_ARRAY_s1_translator:uav_write
wire [2:0] led_array_s1_agent_m0_burstcount; // LED_ARRAY_s1_agent:m0_burstcount -> LED_ARRAY_s1_translator:uav_burstcount
wire led_array_s1_agent_rf_source_valid; // LED_ARRAY_s1_agent:rf_source_valid -> LED_ARRAY_s1_agent_rsp_fifo:in_valid
wire [75:0] led_array_s1_agent_rf_source_data; // LED_ARRAY_s1_agent:rf_source_data -> LED_ARRAY_s1_agent_rsp_fifo:in_data
wire led_array_s1_agent_rf_source_ready; // LED_ARRAY_s1_agent_rsp_fifo:in_ready -> LED_ARRAY_s1_agent:rf_source_ready
wire led_array_s1_agent_rf_source_startofpacket; // LED_ARRAY_s1_agent:rf_source_startofpacket -> LED_ARRAY_s1_agent_rsp_fifo:in_startofpacket
wire led_array_s1_agent_rf_source_endofpacket; // LED_ARRAY_s1_agent:rf_source_endofpacket -> LED_ARRAY_s1_agent_rsp_fifo:in_endofpacket
wire led_array_s1_agent_rsp_fifo_out_valid; // LED_ARRAY_s1_agent_rsp_fifo:out_valid -> LED_ARRAY_s1_agent:rf_sink_valid
wire [75:0] led_array_s1_agent_rsp_fifo_out_data; // LED_ARRAY_s1_agent_rsp_fifo:out_data -> LED_ARRAY_s1_agent:rf_sink_data
wire led_array_s1_agent_rsp_fifo_out_ready; // LED_ARRAY_s1_agent:rf_sink_ready -> LED_ARRAY_s1_agent_rsp_fifo:out_ready
wire led_array_s1_agent_rsp_fifo_out_startofpacket; // LED_ARRAY_s1_agent_rsp_fifo:out_startofpacket -> LED_ARRAY_s1_agent:rf_sink_startofpacket
wire led_array_s1_agent_rsp_fifo_out_endofpacket; // LED_ARRAY_s1_agent_rsp_fifo:out_endofpacket -> LED_ARRAY_s1_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> LED_ARRAY_s1_agent:cp_valid
wire [74:0] cmd_mux_src_data; // cmd_mux:src_data -> LED_ARRAY_s1_agent:cp_data
wire cmd_mux_src_ready; // LED_ARRAY_s1_agent:cp_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> LED_ARRAY_s1_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> LED_ARRAY_s1_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> LED_ARRAY_s1_agent:cp_endofpacket
wire [31:0] switch_array_s1_agent_m0_readdata; // SWITCH_ARRAY_s1_translator:uav_readdata -> SWITCH_ARRAY_s1_agent:m0_readdata
wire switch_array_s1_agent_m0_waitrequest; // SWITCH_ARRAY_s1_translator:uav_waitrequest -> SWITCH_ARRAY_s1_agent:m0_waitrequest
wire switch_array_s1_agent_m0_debugaccess; // SWITCH_ARRAY_s1_agent:m0_debugaccess -> SWITCH_ARRAY_s1_translator:uav_debugaccess
wire [4:0] switch_array_s1_agent_m0_address; // SWITCH_ARRAY_s1_agent:m0_address -> SWITCH_ARRAY_s1_translator:uav_address
wire [3:0] switch_array_s1_agent_m0_byteenable; // SWITCH_ARRAY_s1_agent:m0_byteenable -> SWITCH_ARRAY_s1_translator:uav_byteenable
wire switch_array_s1_agent_m0_read; // SWITCH_ARRAY_s1_agent:m0_read -> SWITCH_ARRAY_s1_translator:uav_read
wire switch_array_s1_agent_m0_readdatavalid; // SWITCH_ARRAY_s1_translator:uav_readdatavalid -> SWITCH_ARRAY_s1_agent:m0_readdatavalid
wire switch_array_s1_agent_m0_lock; // SWITCH_ARRAY_s1_agent:m0_lock -> SWITCH_ARRAY_s1_translator:uav_lock
wire [31:0] switch_array_s1_agent_m0_writedata; // SWITCH_ARRAY_s1_agent:m0_writedata -> SWITCH_ARRAY_s1_translator:uav_writedata
wire switch_array_s1_agent_m0_write; // SWITCH_ARRAY_s1_agent:m0_write -> SWITCH_ARRAY_s1_translator:uav_write
wire [2:0] switch_array_s1_agent_m0_burstcount; // SWITCH_ARRAY_s1_agent:m0_burstcount -> SWITCH_ARRAY_s1_translator:uav_burstcount
wire switch_array_s1_agent_rf_source_valid; // SWITCH_ARRAY_s1_agent:rf_source_valid -> SWITCH_ARRAY_s1_agent_rsp_fifo:in_valid
wire [75:0] switch_array_s1_agent_rf_source_data; // SWITCH_ARRAY_s1_agent:rf_source_data -> SWITCH_ARRAY_s1_agent_rsp_fifo:in_data
wire switch_array_s1_agent_rf_source_ready; // SWITCH_ARRAY_s1_agent_rsp_fifo:in_ready -> SWITCH_ARRAY_s1_agent:rf_source_ready
wire switch_array_s1_agent_rf_source_startofpacket; // SWITCH_ARRAY_s1_agent:rf_source_startofpacket -> SWITCH_ARRAY_s1_agent_rsp_fifo:in_startofpacket
wire switch_array_s1_agent_rf_source_endofpacket; // SWITCH_ARRAY_s1_agent:rf_source_endofpacket -> SWITCH_ARRAY_s1_agent_rsp_fifo:in_endofpacket
wire switch_array_s1_agent_rsp_fifo_out_valid; // SWITCH_ARRAY_s1_agent_rsp_fifo:out_valid -> SWITCH_ARRAY_s1_agent:rf_sink_valid
wire [75:0] switch_array_s1_agent_rsp_fifo_out_data; // SWITCH_ARRAY_s1_agent_rsp_fifo:out_data -> SWITCH_ARRAY_s1_agent:rf_sink_data
wire switch_array_s1_agent_rsp_fifo_out_ready; // SWITCH_ARRAY_s1_agent:rf_sink_ready -> SWITCH_ARRAY_s1_agent_rsp_fifo:out_ready
wire switch_array_s1_agent_rsp_fifo_out_startofpacket; // SWITCH_ARRAY_s1_agent_rsp_fifo:out_startofpacket -> SWITCH_ARRAY_s1_agent:rf_sink_startofpacket
wire switch_array_s1_agent_rsp_fifo_out_endofpacket; // SWITCH_ARRAY_s1_agent_rsp_fifo:out_endofpacket -> SWITCH_ARRAY_s1_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> SWITCH_ARRAY_s1_agent:cp_valid
wire [74:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> SWITCH_ARRAY_s1_agent:cp_data
wire cmd_mux_001_src_ready; // SWITCH_ARRAY_s1_agent:cp_ready -> cmd_mux_001:src_ready
wire [1:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> SWITCH_ARRAY_s1_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> SWITCH_ARRAY_s1_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> SWITCH_ARRAY_s1_agent:cp_endofpacket
wire mm_bridge_m0_agent_cp_valid; // MM_BRIDGE_m0_agent:cp_valid -> router:sink_valid
wire [74:0] mm_bridge_m0_agent_cp_data; // MM_BRIDGE_m0_agent:cp_data -> router:sink_data
wire mm_bridge_m0_agent_cp_ready; // router:sink_ready -> MM_BRIDGE_m0_agent:cp_ready
wire mm_bridge_m0_agent_cp_startofpacket; // MM_BRIDGE_m0_agent:cp_startofpacket -> router:sink_startofpacket
wire mm_bridge_m0_agent_cp_endofpacket; // MM_BRIDGE_m0_agent:cp_endofpacket -> router:sink_endofpacket
wire led_array_s1_agent_rp_valid; // LED_ARRAY_s1_agent:rp_valid -> router_001:sink_valid
wire [74:0] led_array_s1_agent_rp_data; // LED_ARRAY_s1_agent:rp_data -> router_001:sink_data
wire led_array_s1_agent_rp_ready; // router_001:sink_ready -> LED_ARRAY_s1_agent:rp_ready
wire led_array_s1_agent_rp_startofpacket; // LED_ARRAY_s1_agent:rp_startofpacket -> router_001:sink_startofpacket
wire led_array_s1_agent_rp_endofpacket; // LED_ARRAY_s1_agent:rp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire [74:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire switch_array_s1_agent_rp_valid; // SWITCH_ARRAY_s1_agent:rp_valid -> router_002:sink_valid
wire [74:0] switch_array_s1_agent_rp_data; // SWITCH_ARRAY_s1_agent:rp_data -> router_002:sink_data
wire switch_array_s1_agent_rp_ready; // router_002:sink_ready -> SWITCH_ARRAY_s1_agent:rp_ready
wire switch_array_s1_agent_rp_startofpacket; // SWITCH_ARRAY_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
wire switch_array_s1_agent_rp_endofpacket; // SWITCH_ARRAY_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux_001:sink_valid
wire [74:0] router_002_src_data; // router_002:src_data -> rsp_demux_001:sink_data
wire router_002_src_ready; // rsp_demux_001:sink_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> rsp_demux_001:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_src_valid; // router:src_valid -> MM_BRIDGE_m0_limiter:cmd_sink_valid
wire [74:0] router_src_data; // router:src_data -> MM_BRIDGE_m0_limiter:cmd_sink_data
wire router_src_ready; // MM_BRIDGE_m0_limiter:cmd_sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> MM_BRIDGE_m0_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> MM_BRIDGE_m0_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> MM_BRIDGE_m0_limiter:cmd_sink_endofpacket
wire [74:0] mm_bridge_m0_limiter_cmd_src_data; // MM_BRIDGE_m0_limiter:cmd_src_data -> cmd_demux:sink_data
wire mm_bridge_m0_limiter_cmd_src_ready; // cmd_demux:sink_ready -> MM_BRIDGE_m0_limiter:cmd_src_ready
wire [1:0] mm_bridge_m0_limiter_cmd_src_channel; // MM_BRIDGE_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire mm_bridge_m0_limiter_cmd_src_startofpacket; // MM_BRIDGE_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire mm_bridge_m0_limiter_cmd_src_endofpacket; // MM_BRIDGE_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> MM_BRIDGE_m0_limiter:rsp_sink_valid
wire [74:0] rsp_mux_src_data; // rsp_mux:src_data -> MM_BRIDGE_m0_limiter:rsp_sink_data
wire rsp_mux_src_ready; // MM_BRIDGE_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> MM_BRIDGE_m0_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> MM_BRIDGE_m0_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> MM_BRIDGE_m0_limiter:rsp_sink_endofpacket
wire mm_bridge_m0_limiter_rsp_src_valid; // MM_BRIDGE_m0_limiter:rsp_src_valid -> MM_BRIDGE_m0_agent:rp_valid
wire [74:0] mm_bridge_m0_limiter_rsp_src_data; // MM_BRIDGE_m0_limiter:rsp_src_data -> MM_BRIDGE_m0_agent:rp_data
wire mm_bridge_m0_limiter_rsp_src_ready; // MM_BRIDGE_m0_agent:rp_ready -> MM_BRIDGE_m0_limiter:rsp_src_ready
wire [1:0] mm_bridge_m0_limiter_rsp_src_channel; // MM_BRIDGE_m0_limiter:rsp_src_channel -> MM_BRIDGE_m0_agent:rp_channel
wire mm_bridge_m0_limiter_rsp_src_startofpacket; // MM_BRIDGE_m0_limiter:rsp_src_startofpacket -> MM_BRIDGE_m0_agent:rp_startofpacket
wire mm_bridge_m0_limiter_rsp_src_endofpacket; // MM_BRIDGE_m0_limiter:rsp_src_endofpacket -> MM_BRIDGE_m0_agent:rp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [74:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [74:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [1:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [74:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [74:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [1:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire [1:0] mm_bridge_m0_limiter_cmd_valid_data; // MM_BRIDGE_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire led_array_s1_agent_rdata_fifo_src_valid; // LED_ARRAY_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] led_array_s1_agent_rdata_fifo_src_data; // LED_ARRAY_s1_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire led_array_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> LED_ARRAY_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> LED_ARRAY_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> LED_ARRAY_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // LED_ARRAY_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> LED_ARRAY_s1_agent:rdata_fifo_sink_error
wire switch_array_s1_agent_rdata_fifo_src_valid; // SWITCH_ARRAY_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] switch_array_s1_agent_rdata_fifo_src_data; // SWITCH_ARRAY_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire switch_array_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> SWITCH_ARRAY_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> SWITCH_ARRAY_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> SWITCH_ARRAY_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // SWITCH_ARRAY_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> SWITCH_ARRAY_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (5),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (5),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) mm_bridge_m0_translator (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (mm_bridge_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (mm_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (mm_bridge_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (mm_bridge_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (mm_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (mm_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (mm_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (mm_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (mm_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (mm_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (mm_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (MM_BRIDGE_m0_address), // avalon_anti_master_0.address
.av_waitrequest (MM_BRIDGE_m0_waitrequest), // .waitrequest
.av_burstcount (MM_BRIDGE_m0_burstcount), // .burstcount
.av_byteenable (MM_BRIDGE_m0_byteenable), // .byteenable
.av_read (MM_BRIDGE_m0_read), // .read
.av_readdata (MM_BRIDGE_m0_readdata), // .readdata
.av_readdatavalid (MM_BRIDGE_m0_readdatavalid), // .readdatavalid
.av_write (MM_BRIDGE_m0_write), // .write
.av_writedata (MM_BRIDGE_m0_writedata), // .writedata
.av_debugaccess (MM_BRIDGE_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (5),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) led_array_s1_translator (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (led_array_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (led_array_s1_agent_m0_burstcount), // .burstcount
.uav_read (led_array_s1_agent_m0_read), // .read
.uav_write (led_array_s1_agent_m0_write), // .write
.uav_waitrequest (led_array_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (led_array_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (led_array_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (led_array_s1_agent_m0_readdata), // .readdata
.uav_writedata (led_array_s1_agent_m0_writedata), // .writedata
.uav_lock (led_array_s1_agent_m0_lock), // .lock
.uav_debugaccess (led_array_s1_agent_m0_debugaccess), // .debugaccess
.av_address (LED_ARRAY_s1_address), // avalon_anti_slave_0.address
.av_write (LED_ARRAY_s1_write), // .write
.av_readdata (LED_ARRAY_s1_readdata), // .readdata
.av_writedata (LED_ARRAY_s1_writedata), // .writedata
.av_chipselect (LED_ARRAY_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (5),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) switch_array_s1_translator (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (switch_array_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (switch_array_s1_agent_m0_burstcount), // .burstcount
.uav_read (switch_array_s1_agent_m0_read), // .read
.uav_write (switch_array_s1_agent_m0_write), // .write
.uav_waitrequest (switch_array_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (switch_array_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (switch_array_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (switch_array_s1_agent_m0_readdata), // .readdata
.uav_writedata (switch_array_s1_agent_m0_writedata), // .writedata
.uav_lock (switch_array_s1_agent_m0_lock), // .lock
.uav_debugaccess (switch_array_s1_agent_m0_debugaccess), // .debugaccess
.av_address (SWITCH_ARRAY_s1_address), // avalon_anti_slave_0.address
.av_readdata (SWITCH_ARRAY_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (74),
.PKT_ORI_BURST_SIZE_L (72),
.PKT_RESPONSE_STATUS_H (71),
.PKT_RESPONSE_STATUS_L (70),
.PKT_QOS_H (59),
.PKT_QOS_L (59),
.PKT_DATA_SIDEBAND_H (57),
.PKT_DATA_SIDEBAND_L (57),
.PKT_ADDR_SIDEBAND_H (56),
.PKT_ADDR_SIDEBAND_L (56),
.PKT_BURST_TYPE_H (55),
.PKT_BURST_TYPE_L (54),
.PKT_CACHE_H (69),
.PKT_CACHE_L (66),
.PKT_THREAD_ID_H (62),
.PKT_THREAD_ID_L (62),
.PKT_BURST_SIZE_H (53),
.PKT_BURST_SIZE_L (51),
.PKT_TRANS_EXCLUSIVE (46),
.PKT_TRANS_LOCK (45),
.PKT_BEGIN_BURST (58),
.PKT_PROTECTION_H (65),
.PKT_PROTECTION_L (63),
.PKT_BURSTWRAP_H (50),
.PKT_BURSTWRAP_L (50),
.PKT_BYTE_CNT_H (49),
.PKT_BYTE_CNT_L (47),
.PKT_ADDR_H (40),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (41),
.PKT_TRANS_POSTED (42),
.PKT_TRANS_WRITE (43),
.PKT_TRANS_READ (44),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (60),
.PKT_SRC_ID_L (60),
.PKT_DEST_ID_H (61),
.PKT_DEST_ID_L (61),
.ST_DATA_W (75),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) mm_bridge_m0_agent (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (mm_bridge_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (mm_bridge_m0_translator_avalon_universal_master_0_write), // .write
.av_read (mm_bridge_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (mm_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (mm_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (mm_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (mm_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (mm_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (mm_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (mm_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (mm_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (mm_bridge_m0_agent_cp_valid), // cp.valid
.cp_data (mm_bridge_m0_agent_cp_data), // .data
.cp_startofpacket (mm_bridge_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (mm_bridge_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (mm_bridge_m0_agent_cp_ready), // .ready
.rp_valid (mm_bridge_m0_limiter_rsp_src_valid), // rp.valid
.rp_data (mm_bridge_m0_limiter_rsp_src_data), // .data
.rp_channel (mm_bridge_m0_limiter_rsp_src_channel), // .channel
.rp_startofpacket (mm_bridge_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (mm_bridge_m0_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (mm_bridge_m0_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (74),
.PKT_ORI_BURST_SIZE_L (72),
.PKT_RESPONSE_STATUS_H (71),
.PKT_RESPONSE_STATUS_L (70),
.PKT_BURST_SIZE_H (53),
.PKT_BURST_SIZE_L (51),
.PKT_TRANS_LOCK (45),
.PKT_BEGIN_BURST (58),
.PKT_PROTECTION_H (65),
.PKT_PROTECTION_L (63),
.PKT_BURSTWRAP_H (50),
.PKT_BURSTWRAP_L (50),
.PKT_BYTE_CNT_H (49),
.PKT_BYTE_CNT_L (47),
.PKT_ADDR_H (40),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (41),
.PKT_TRANS_POSTED (42),
.PKT_TRANS_WRITE (43),
.PKT_TRANS_READ (44),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (60),
.PKT_SRC_ID_L (60),
.PKT_DEST_ID_H (61),
.PKT_DEST_ID_L (61),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (2),
.ST_DATA_W (75),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) led_array_s1_agent (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (led_array_s1_agent_m0_address), // m0.address
.m0_burstcount (led_array_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (led_array_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (led_array_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (led_array_s1_agent_m0_lock), // .lock
.m0_readdata (led_array_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (led_array_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (led_array_s1_agent_m0_read), // .read
.m0_waitrequest (led_array_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (led_array_s1_agent_m0_writedata), // .writedata
.m0_write (led_array_s1_agent_m0_write), // .write
.rp_endofpacket (led_array_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (led_array_s1_agent_rp_ready), // .ready
.rp_valid (led_array_s1_agent_rp_valid), // .valid
.rp_data (led_array_s1_agent_rp_data), // .data
.rp_startofpacket (led_array_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (led_array_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (led_array_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (led_array_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (led_array_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (led_array_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (led_array_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (led_array_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (led_array_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (led_array_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (led_array_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (led_array_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (led_array_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (led_array_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (76),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) led_array_s1_agent_rsp_fifo (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (led_array_s1_agent_rf_source_data), // in.data
.in_valid (led_array_s1_agent_rf_source_valid), // .valid
.in_ready (led_array_s1_agent_rf_source_ready), // .ready
.in_startofpacket (led_array_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (led_array_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (led_array_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (led_array_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (led_array_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (led_array_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (led_array_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (74),
.PKT_ORI_BURST_SIZE_L (72),
.PKT_RESPONSE_STATUS_H (71),
.PKT_RESPONSE_STATUS_L (70),
.PKT_BURST_SIZE_H (53),
.PKT_BURST_SIZE_L (51),
.PKT_TRANS_LOCK (45),
.PKT_BEGIN_BURST (58),
.PKT_PROTECTION_H (65),
.PKT_PROTECTION_L (63),
.PKT_BURSTWRAP_H (50),
.PKT_BURSTWRAP_L (50),
.PKT_BYTE_CNT_H (49),
.PKT_BYTE_CNT_L (47),
.PKT_ADDR_H (40),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (41),
.PKT_TRANS_POSTED (42),
.PKT_TRANS_WRITE (43),
.PKT_TRANS_READ (44),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (60),
.PKT_SRC_ID_L (60),
.PKT_DEST_ID_H (61),
.PKT_DEST_ID_L (61),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (2),
.ST_DATA_W (75),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) switch_array_s1_agent (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (switch_array_s1_agent_m0_address), // m0.address
.m0_burstcount (switch_array_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (switch_array_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (switch_array_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (switch_array_s1_agent_m0_lock), // .lock
.m0_readdata (switch_array_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (switch_array_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (switch_array_s1_agent_m0_read), // .read
.m0_waitrequest (switch_array_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (switch_array_s1_agent_m0_writedata), // .writedata
.m0_write (switch_array_s1_agent_m0_write), // .write
.rp_endofpacket (switch_array_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (switch_array_s1_agent_rp_ready), // .ready
.rp_valid (switch_array_s1_agent_rp_valid), // .valid
.rp_data (switch_array_s1_agent_rp_data), // .data
.rp_startofpacket (switch_array_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (switch_array_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (switch_array_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (switch_array_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (switch_array_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (switch_array_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (switch_array_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (switch_array_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (switch_array_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (switch_array_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (switch_array_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (switch_array_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (switch_array_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (switch_array_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (76),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) switch_array_s1_agent_rsp_fifo (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (switch_array_s1_agent_rf_source_data), // in.data
.in_valid (switch_array_s1_agent_rf_source_valid), // .valid
.in_ready (switch_array_s1_agent_rf_source_ready), // .ready
.in_startofpacket (switch_array_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (switch_array_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (switch_array_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (switch_array_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (switch_array_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (switch_array_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (switch_array_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
ledtest_mm_interconnect_1_router router (
.sink_ready (mm_bridge_m0_agent_cp_ready), // sink.ready
.sink_valid (mm_bridge_m0_agent_cp_valid), // .valid
.sink_data (mm_bridge_m0_agent_cp_data), // .data
.sink_startofpacket (mm_bridge_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (mm_bridge_m0_agent_cp_endofpacket), // .endofpacket
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_1_router_001 router_001 (
.sink_ready (led_array_s1_agent_rp_ready), // sink.ready
.sink_valid (led_array_s1_agent_rp_valid), // .valid
.sink_data (led_array_s1_agent_rp_data), // .data
.sink_startofpacket (led_array_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (led_array_s1_agent_rp_endofpacket), // .endofpacket
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_1_router_001 router_002 (
.sink_ready (switch_array_s1_agent_rp_ready), // sink.ready
.sink_valid (switch_array_s1_agent_rp_valid), // .valid
.sink_data (switch_array_s1_agent_rp_data), // .data
.sink_startofpacket (switch_array_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (switch_array_s1_agent_rp_endofpacket), // .endofpacket
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (61),
.PKT_DEST_ID_L (61),
.PKT_SRC_ID_H (60),
.PKT_SRC_ID_L (60),
.PKT_BYTE_CNT_H (49),
.PKT_BYTE_CNT_L (47),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (42),
.PKT_TRANS_WRITE (43),
.MAX_OUTSTANDING_RESPONSES (1),
.PIPELINED (0),
.ST_DATA_W (75),
.ST_CHANNEL_W (2),
.VALID_WIDTH (2),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) mm_bridge_m0_limiter (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (mm_bridge_m0_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (mm_bridge_m0_limiter_cmd_src_data), // .data
.cmd_src_channel (mm_bridge_m0_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (mm_bridge_m0_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (mm_bridge_m0_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (mm_bridge_m0_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (mm_bridge_m0_limiter_rsp_src_valid), // .valid
.rsp_src_data (mm_bridge_m0_limiter_rsp_src_data), // .data
.rsp_src_channel (mm_bridge_m0_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (mm_bridge_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (mm_bridge_m0_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (mm_bridge_m0_limiter_cmd_valid_data) // cmd_valid.data
);
ledtest_mm_interconnect_1_cmd_demux cmd_demux (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (mm_bridge_m0_limiter_cmd_src_ready), // sink.ready
.sink_channel (mm_bridge_m0_limiter_cmd_src_channel), // .channel
.sink_data (mm_bridge_m0_limiter_cmd_src_data), // .data
.sink_startofpacket (mm_bridge_m0_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (mm_bridge_m0_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (mm_bridge_m0_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_1_cmd_mux cmd_mux (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_1_cmd_mux cmd_mux_001 (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_1_rsp_demux rsp_demux (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_1_rsp_demux rsp_demux_001 (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_1_rsp_mux rsp_mux (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (CLOCK_clk_clk), // in_clk_0.clk
.in_rst_0_reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (led_array_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (led_array_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (led_array_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
ledtest_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (CLOCK_clk_clk), // in_clk_0.clk
.in_rst_0_reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (switch_array_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (switch_array_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (switch_array_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BOI_0_V
`define SKY130_FD_SC_LP__A21BOI_0_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21boi_0 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21boi_0 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BOI_0_V
|
// DSP48E1
// [1] 7 Series DSP48E1 User Guide UG479 (v1.9) September 27, 2016
`include "amux/areg_mux.sim.v"
`include "dmux/dreg_mux.sim.v"
`include "ain_mux/ain_mux.sim.v"
`include "acout_mux/acout_mux.sim.v"
`include "amult_mux/amult_mux.sim.v"
`include "a_adder_mux/a_adder_mux.sim.v"
`include "../nreg/nreg.sim.v"
// Figure 2-7 shows details
module DUAL_AD_PREADDER
(
A, ACIN, D, INMODE,
ACOUT, XMUX, AMULT,
CEA1, CEA2, RSTA, CED, CEAD, RSTD, CLK
);
parameter A_INPUT = "DIRECT";
parameter ACASCREG = 1;
parameter ADREG = 1;
parameter ALUMODEREG = 1;
parameter AREG = 1;
parameter DREG = 1;
parameter USE_DPORT = "FALSE";
input wire [29:0] A;
input wire [29:0] ACIN;
input wire [24:0] D;
input wire [4:0] INMODE;
output wire [29:0] ACOUT;
output wire [29:0] XMUX;
output wire [24:0] AMULT;
input wire CEA1;
input wire CEA2;
input wire RSTA;
input wire CED;
input wire CEAD;
input wire RSTD;
input wire CLK;
wire [29:0] A1IN;
wire [29:0] A1REG_OUT;
wire [29:0] A2IN;
wire [29:0] A2REG_OUT;
wire [29:0] XMUX;
wire [24:0] DREG_OUT;
wire [24:0] DOUT;
wire [24:0] ADDER_OUT;
wire [24:0] ADDER_AIN;
wire [24:0] ADDER_DIN;
wire [24:0] ADREG_OUT;
wire [24:0] AD_OUT;
wire [24:0] A_ADDER_CANDIDATE;
`ifndef PB_TYPE
AIN_MUX #(.S(A_INPUT == "DIRECT")) ain_mux (.A(A), .ACIN(ACIN), .O(A1IN));
AREG_MUX #(.S(AREG==2)) a1mux (.BYPASS(A1IN), .REG(A1REG_OUT), .O(A2IN));
AREG_MUX #(.S(AREG>0)) a2mux (.BYPASS(A2IN), .REG(A2REG_OUT), .O(XMUX));
ACOUT_MUX #(.S(ACASCREG == 1)) acout_mux (.I0(A1REG_OUT), .I1(XMUX), .O(ACOUT));
NREG #(.NBITS(30)) a1 (.D(A1IN), .Q(A1REG_OUT), .CLK(CLK), .CE(CEA1), .RESET(RSTA));
NREG #(.NBITS(30)) a2 (.D(A2IN), .Q(A2REG_OUT), .CLK(CLK), .CE(CEA2), .RESET(RSTA));
DREG_MUX #(.S(DREG == 0)) d_mux (.BYPASS(D), .REG(DREG_OUT), .O(DOUT));
DREG_MUX #(.S(ADREG == 0)) ad_mux (.BYPASS(ADDER_OUT), .REG(ADREG_OUT), .O(AD_OUT));
NREG #(.NBITS(25)) d (.D(D), .Q(DREG_OUT), .CLK(CLK), .CE(CED), .RESET(RSTD));
NREG #(.NBITS(25)) ad (.D(ADDER_OUT), .Q(ADREG_OUT), .CLK(CLK), .CE(CEAD), .RESET(RSTD));
A_ADDER_MUX a_adder_muxx (.A2(XMUX[24:0]), .A1(A1REG_OUT[24:0]), .S(INMODE[0]), .O(A_ADDER_CANDIDATE));
A_ADDER_MUX a_or_zero (.A2(A_ADDER_CANDIDATE), .A1(25'b0), .S(INMODE[1]), .O(ADDER_AIN));
A_ADDER_MUX d_or_zero (.A2(25'b0), .A1(DOUT), .S(INMODE[2]), .O(ADDER_DIN));
assign ADDER_OUT = INMODE[3] ? (ADDER_DIN - ADDER_AIN) : (ADDER_DIN + ADDER_AIN);
AMULT_MUX #(.S(USE_DPORT == "FALSE")) amult_mux (.A(ADDER_AIN), .ADDER_OUT(ADDER_OUT), .O(AMULT));
`endif // `ifndef PB_TYPE
endmodule // DUAL_AD_PREADDER
// Table 2-5 defines behavior
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22A_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O22A_PP_SYMBOL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o22a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22A_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_2_V
`define SKY130_FD_SC_MS__EINVN_2_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_2_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Top level multiplier and MAC ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Multiplier is 32x32 however multiply instructions only ////
//// use lower 32 bits of the result. MAC is 32x32=64+64. ////
//// ////
//// To Do: ////
//// - make signed division better, w/o negating the operands ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_mult_mac.v,v $
// Revision 1.5 2006/04/09 01:32:29 lampret
// See OR1200_MAC_SHIFTBY in rtl/verilog/or1200/or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts.
//
// Revision 1.4 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.3 2003/04/24 00:16:07 lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.2 2002/09/08 05:52:16 lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.3 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.2 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:38 igorm
// no message
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_mult_mac(
// Clock and reset
clk, rst,
// Multiplier/MAC interface
ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,
// SPR interface
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Multiplier/MAC interface
//
input ex_freeze;
input id_macrc_op;
input macrc_op;
input [width-1:0] a;
input [width-1:0] b;
input [`OR1200_MACOP_WIDTH-1:0] mac_op;
input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
output [width-1:0] result;
output mac_stall_r;
//
// SPR interface
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
`ifdef OR1200_MULT_IMPLEMENTED
reg [width-1:0] result;
reg [2*width-1:0] mul_prod_r;
`else
wire [width-1:0] result;
wire [2*width-1:0] mul_prod_r;
`endif
wire [2*width-1:0] mul_prod;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
`ifdef OR1200_MAC_IMPLEMENTED
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
reg mac_stall_r;
reg [2*width-1:0] mac_r;
`else
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
wire mac_stall_r;
wire [2*width-1:0] mac_r;
`endif
wire [width-1:0] x;
wire [width-1:0] y;
wire spr_maclo_we;
wire spr_machi_we;
wire alu_op_div_divu;
wire alu_op_div;
reg div_free;
`ifdef OR1200_IMPL_DIV
wire [width-1:0] div_tmp;
reg [5:0] div_cntr;
`endif
//
// Combinatorial logic
//
`ifdef OR1200_MAC_IMPLEMENTED
assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
`else
assign spr_maclo_we = 1'b0;
assign spr_machi_we = 1'b0;
assign spr_dat_o = 32'h0000_0000;
`endif
`ifdef OR1200_LOWPWR_MULT
assign x = (alu_op_div & a[31]) ? ~a + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? a : 32'h0000_0000;
assign y = (alu_op_div & b[31]) ? ~b + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? b : 32'h0000_0000;
`else
assign x = alu_op_div & a[31] ? ~a + 32'b1 : a;
assign y = alu_op_div & b[31] ? ~b + 32'b1 : b;
`endif
`ifdef OR1200_IMPL_DIV
assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV);
assign alu_op_div_divu = alu_op_div | (alu_op == `OR1200_ALUOP_DIVU);
assign div_tmp = mul_prod_r[63:32] - y;
`else
assign alu_op_div = 1'b0;
assign alu_op_div_divu = 1'b0;
`endif
`ifdef OR1200_MULT_IMPLEMENTED
//
// Select result of current ALU operation to be forwarded
// to next instruction and to WB stage
//
always @(alu_op or mul_prod_r or mac_r or a or b)
casex(alu_op) // synopsys parallel_case
`ifdef OR1200_IMPL_DIV
`OR1200_ALUOP_DIV:
result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
`OR1200_ALUOP_DIVU,
`endif
`OR1200_ALUOP_MUL: begin
result = mul_prod_r[31:0];
end
default:
`ifdef OR1200_MAC_SHIFTBY
result = mac_r[`OR1200_MAC_SHIFTBY+31:`OR1200_MAC_SHIFTBY];
`else
result = mac_r[31:0];
`endif
endcase
//
// Instantiation of the multiplier
//
`ifdef OR1200_ASIC_MULTP2_32X32
or1200_amultp2_32x32 or1200_amultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`else // OR1200_ASIC_MULTP2_32X32
or1200_gmultp2_32x32 or1200_gmultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`endif // OR1200_ASIC_MULTP2_32X32
//
// Registered output from the multiplier and
// an optional divider
//
always @(posedge rst or posedge clk)
if (rst) begin
mul_prod_r <= #1 64'h0000_0000_0000_0000;
div_free <= #1 1'b1;
`ifdef OR1200_IMPL_DIV
div_cntr <= #1 6'b00_0000;
`endif
end
`ifdef OR1200_IMPL_DIV
else if (|div_cntr) begin
if (div_tmp[31])
mul_prod_r <= #1 {mul_prod_r[62:0], 1'b0};
else
mul_prod_r <= #1 {div_tmp[30:0], mul_prod_r[31:0], 1'b1};
div_cntr <= #1 div_cntr - 1'b1;
end
else if (alu_op_div_divu && div_free) begin
mul_prod_r <= #1 {31'b0, x[31:0], 1'b0};
div_cntr <= #1 6'b10_0000;
div_free <= #1 1'b0;
end
`endif // OR1200_IMPL_DIV
else if (div_free | !ex_freeze) begin
mul_prod_r <= #1 mul_prod[63:0];
div_free <= #1 1'b1;
end
`else // OR1200_MULT_IMPLEMENTED
assign result = {width{1'b0}};
assign mul_prod = {2*width{1'b0}};
assign mul_prod_r = {2*width{1'b0}};
`endif // OR1200_MULT_IMPLEMENTED
`ifdef OR1200_MAC_IMPLEMENTED
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r1 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r1 <= #1 mac_op;
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r2 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r2 <= #1 mac_op_r1;
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r3 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r3 <= #1 mac_op_r2;
//
// Implementation of MAC
//
always @(posedge rst or posedge clk)
if (rst)
mac_r <= #1 64'h0000_0000_0000_0000;
`ifdef OR1200_MAC_SPR_WE
else if (spr_maclo_we)
mac_r[31:0] <= #1 spr_dat_i;
else if (spr_machi_we)
mac_r[63:32] <= #1 spr_dat_i;
`endif
else if (mac_op_r3 == `OR1200_MACOP_MAC)
mac_r <= #1 mac_r + mul_prod_r;
else if (mac_op_r3 == `OR1200_MACOP_MSB)
mac_r <= #1 mac_r - mul_prod_r;
else if (macrc_op & !ex_freeze)
mac_r <= #1 64'h0000_0000_0000_0000;
//
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
// in EX stage (e.g. inside multiplier)
// This stall signal is also used by the divider.
//
always @(posedge rst or posedge clk)
if (rst)
mac_stall_r <= #1 1'b0;
else
mac_stall_r <= #1 (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & id_macrc_op
`ifdef OR1200_IMPL_DIV
| (|div_cntr)
`endif
;
`else // OR1200_MAC_IMPLEMENTED
assign mac_stall_r = 1'b0;
assign mac_r = {2*width{1'b0}};
assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r3 = `OR1200_MACOP_WIDTH'b0;
`endif // OR1200_MAC_IMPLEMENTED
//
// Abstruct the signal we are interested in
//
//always @(posedge clk or posedge rst)
//$show_signal_value(or1200_mult_mac, mac_stall_r);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31O_2_V
`define SKY130_FD_SC_LS__A31O_2_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31o_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31O_2_V
|
module juniversalShiftRegisterTb;
wire [3:0] DATAOUT;
reg clock, reset;
reg [1:0] MODE;
reg [3:0] DATAIN;
juniversalShiftRegister jusr(DATAOUT, clock, reset, MODE, DATAIN);
initial
begin
clock =0; MODE = 2'b00; DATAIN = 4'b0000;
reset = 1; #10; reset = 0; #10;
$display("RSLT\tD == DOUT");
// Start testing Right Shift mode
MODE = 2'b00; reset = 1; #10; reset = 0; #10;
MODE = 2'b01; DATAIN = 4'b0011; #10;
if ( DATAOUT === 4'b1000 ) // look at previous value of DATAOUT as well
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
MODE = 2'b01; DATAIN = 4'b0011; #10;
if ( DATAOUT === 4'b1100 ) // look at previous value of DATAOUT as well
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
// Start testing Left Shift mode
MODE = 2'b00; reset = 1; #10; reset = 0; #10;
MODE = 2'b10; DATAIN = 4'b0111; #10;
if ( DATAOUT === 4'b0001 ) //
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
MODE = 2'b10; DATAIN = 4'b0111; #10;
if ( DATAOUT === 4'b0011 ) //
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
// Start testing parallel load mode
MODE = 2'b00; reset = 1; #10; reset = 0; #10;
MODE = 2'b11; DATAIN = 4'b1010; #10;
if ( DATAOUT === 4'b1010 )
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
#20;
$finish;
end
always #5 clock = ~clock;
endmodule |
`include "defines.v"
module ex_mem(
input wire clk,
input wire rst,
//À´×Ô¿ØÖÆÄ£¿éµÄÐÅÏ¢
input wire[5:0] stall,
input wire flush,
//À´×ÔÖ´Ðн׶εÄÐÅÏ¢
input wire[`RegAddrBus] ex_wd,
input wire ex_wreg,
input wire[`RegBus] ex_wdata,
input wire[`RegBus] ex_hi,
input wire[`RegBus] ex_lo,
input wire ex_whilo,
//ΪʵÏÖ¼ÓÔØ¡¢·Ã´æÖ¸Áî¶øÌí¼Ó
input wire[`AluOpBus] ex_aluop,
input wire[`RegBus] ex_mem_addr,
input wire[`RegBus] ex_reg2,
input wire[`DoubleRegBus] hilo_i,
input wire[1:0] cnt_i,
input wire ex_cp0_reg_we,
input wire[4:0] ex_cp0_reg_write_addr,
input wire[`RegBus] ex_cp0_reg_data,
input wire[31:0] ex_excepttype,
input wire ex_is_in_delayslot,
input wire[`RegBus] ex_current_inst_address,
//Ë͵½·Ã´æ½×¶ÎµÄÐÅÏ¢
output reg[`RegAddrBus] mem_wd,
output reg mem_wreg,
output reg[`RegBus] mem_wdata,
output reg[`RegBus] mem_hi,
output reg[`RegBus] mem_lo,
output reg mem_whilo,
//ΪʵÏÖ¼ÓÔØ¡¢·Ã´æÖ¸Áî¶øÌí¼Ó
output reg[`AluOpBus] mem_aluop,
output reg[`RegBus] mem_mem_addr,
output reg[`RegBus] mem_reg2,
output reg mem_cp0_reg_we,
output reg[4:0] mem_cp0_reg_write_addr,
output reg[`RegBus] mem_cp0_reg_data,
output reg[31:0] mem_excepttype,
output reg mem_is_in_delayslot,
output reg[`RegBus] mem_current_inst_address,
output reg[`DoubleRegBus] hilo_o,
output reg[1:0] cnt_o
);
always @ (posedge clk) begin
if(rst == `RstEnable) begin
mem_wd <= `NOPRegAddr;
mem_wreg <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_hi <= `ZeroWord;
mem_lo <= `ZeroWord;
mem_whilo <= `WriteDisable;
hilo_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b00;
mem_aluop <= `EXE_NOP_OP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
mem_cp0_reg_we <= `WriteDisable;
mem_cp0_reg_write_addr <= 5'b00000;
mem_cp0_reg_data <= `ZeroWord;
mem_excepttype <= `ZeroWord;
mem_is_in_delayslot <= `NotInDelaySlot;
mem_current_inst_address <= `ZeroWord;
end else if(flush == 1'b1 ) begin
mem_wd <= `NOPRegAddr;
mem_wreg <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_hi <= `ZeroWord;
mem_lo <= `ZeroWord;
mem_whilo <= `WriteDisable;
mem_aluop <= `EXE_NOP_OP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
mem_cp0_reg_we <= `WriteDisable;
mem_cp0_reg_write_addr <= 5'b00000;
mem_cp0_reg_data <= `ZeroWord;
mem_excepttype <= `ZeroWord;
mem_is_in_delayslot <= `NotInDelaySlot;
mem_current_inst_address <= `ZeroWord;
hilo_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b00;
end else if(stall[3] == `Stop && stall[4] == `NoStop) begin
mem_wd <= `NOPRegAddr;
mem_wreg <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_hi <= `ZeroWord;
mem_lo <= `ZeroWord;
mem_whilo <= `WriteDisable;
hilo_o <= hilo_i;
cnt_o <= cnt_i;
mem_aluop <= `EXE_NOP_OP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
mem_cp0_reg_we <= `WriteDisable;
mem_cp0_reg_write_addr <= 5'b00000;
mem_cp0_reg_data <= `ZeroWord;
mem_excepttype <= `ZeroWord;
mem_is_in_delayslot <= `NotInDelaySlot;
mem_current_inst_address <= `ZeroWord;
end else if(stall[3] == `NoStop) begin
mem_wd <= ex_wd;
mem_wreg <= ex_wreg;
mem_wdata <= ex_wdata;
mem_hi <= ex_hi;
mem_lo <= ex_lo;
mem_whilo <= ex_whilo;
hilo_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b00;
mem_aluop <= ex_aluop;
mem_mem_addr <= ex_mem_addr;
mem_reg2 <= ex_reg2;
mem_cp0_reg_we <= ex_cp0_reg_we;
mem_cp0_reg_write_addr <= ex_cp0_reg_write_addr;
mem_cp0_reg_data <= ex_cp0_reg_data;
mem_excepttype <= ex_excepttype;
mem_is_in_delayslot <= ex_is_in_delayslot;
mem_current_inst_address <= ex_current_inst_address;
end else begin
hilo_o <= hilo_i;
cnt_o <= cnt_i;
end //if
end //always
endmodule |
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
//
// Owner: Jayant Mittal
// Revision: $Id: qdr_rld_phy_4lanes.v,v 1.2 2012/05/08 01:03:44 rodrigoa Exp $
// $Author: rodrigoa $
// $DateTime: 2010/09/27 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is the parameterizable 4-byte lane phy primitive top
// This module may be ganged to create an N-lane phy.
//
// History:
// Date Engineer Description
// 04/01/2010 J. Mittal Initial Checkin.
// 07/30/2013 Added PO_COARSE_BYPASS for QDR2+ design.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module mig_7series_v2_0_qdr_rld_phy_4lanes #(
parameter MEMORY_TYPE = "SRAM",
parameter SIMULATION = "FALSE",
parameter PO_COARSE_BYPASS = "FALSE",
parameter CPT_CLK_CQ_ONLY = "TRUE",
parameter INTERFACE_TYPE = "UNIDIR",
parameter PRE_FIFO = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG", //May be assigned unique name
// when mult IP cores in design
parameter IODELAY_HP_MODE = "ON", //IODELAY High Performance Mode
parameter BYTE_GROUP_TYPE = 4'b1111,
parameter GENERATE_CQ = 4'b0000,
// next three parameter fields correspond to byte lanes for lane order DCBA
parameter BYTE_LANES = 4'b1111, // lane existence, one per lane
parameter BITLANES_IN = 48'h000_000_000_000,
parameter BITLANES_OUT = 48'h000_000_000_000,
parameter CK_P_OUT = 48'h000_000_000_000,
parameter DATA_CTL_N = 4'b1111, // data or control, per lane
parameter CPT_CLK_SEL = 32'h12_12_11_11,
parameter PO_FINE_DELAY = 0,
parameter PI_FINE_DELAY = 0,
parameter A_PO_COARSE_DELAY = 0,
parameter B_PO_COARSE_DELAY = 0,
parameter C_PO_COARSE_DELAY = 0,
parameter D_PO_COARSE_DELAY = 0,
parameter A_PO_FINE_DELAY = 0,
parameter B_PO_FINE_DELAY = 0,
parameter C_PO_FINE_DELAY = 0,
parameter D_PO_FINE_DELAY = 0,
parameter BUFMR_DELAY = 500,
parameter GENERATE_DDR_CK = 4'b1111,
parameter GENERATE_DDR_DK = 4'b0000,
parameter DIFF_CK = 1'b1,
parameter DIFF_DK = 1'b1,
parameter DIFF_CQ = 1'b0,
parameter CK_VALUE_D1 = 1'b0,
parameter DK_VALUE_D1 = 1'b0,
parameter LANE_REMAP = 16'h3210,// 4-bit index
// used to rewire to one of four
// input/output buss lanes
// example: 0321 remaps lanes as:
// D->A
// C->D
// B->C
// A->B
parameter LAST_BANK = "FALSE",
//phaser_in parameters
parameter A_PI_FREQ_REF_DIV = "NONE",
parameter A_PI_FINE_DELAY = PI_FINE_DELAY,
parameter real A_PI_REFCLK_PERIOD = 2.5,
parameter real MEMREFCLK_PERIOD = 2.5,
parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY,
parameter real B_PI_REFCLK_PERIOD = 2.5,
parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter C_PI_FINE_DELAY = A_PI_FINE_DELAY,
parameter real C_PI_REFCLK_PERIOD = 2.5,
parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter D_PI_FINE_DELAY = A_PI_FINE_DELAY,
parameter real D_PI_REFCLK_PERIOD = 2.5,
//phaser_out parameters
//parameter A_PO_FINE_DELAY = PO_FINE_DELAY,
parameter A_PO_OCLK_DELAY = 5,
parameter A_PO_OCLKDELAY_INV = "TRUE",
parameter real A_PO_REFCLK_PERIOD = 2.5,
//parameter B_PO_FINE_DELAY = PO_FINE_DELAY,
parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter real B_PO_REFCLK_PERIOD = A_PO_REFCLK_PERIOD,
//parameter C_PO_FINE_DELAY = PO_FINE_DELAY,
parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter real C_PO_REFCLK_PERIOD = A_PO_REFCLK_PERIOD,
//parameter D_PO_FINE_DELAY = PO_FINE_DELAY,
parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter real D_PO_REFCLK_PERIOD = A_PO_REFCLK_PERIOD,
// phy_control parameters
parameter PC_BURST_MODE = "TRUE",
parameter PC_CLK_RATIO = 2,
//parameter PC_DATA_CTL_N = DATA_CTL_N,
parameter PC_CMD_OFFSET = 0,
parameter PC_RD_CMD_OFFSET_0 = 0,
parameter PC_RD_CMD_OFFSET_1 = 0,
parameter PC_RD_CMD_OFFSET_2 = 0,
parameter PC_RD_CMD_OFFSET_3 = 0,
parameter PC_CO_DURATION = 1,
parameter PC_DI_DURATION = 1,
parameter PC_DO_DURATION = 1,
parameter PC_RD_DURATION_0 = 0,
parameter PC_RD_DURATION_1 = 0,
parameter PC_RD_DURATION_2 = 0,
parameter PC_RD_DURATION_3 = 0,
parameter PC_WR_CMD_OFFSET_0 = 5,
parameter PC_WR_CMD_OFFSET_1 = 5,
parameter PC_WR_CMD_OFFSET_2 = 5,
parameter PC_WR_CMD_OFFSET_3 = 5,
parameter PC_WR_DURATION_0 = 6,
parameter PC_WR_DURATION_1 = 6,
parameter PC_WR_DURATION_2 = 6,
parameter PC_WR_DURATION_3 = 6,
parameter PC_AO_WRLVL_EN = 0,
parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PC_FOUR_WINDOW_CLOCKS = 63,
parameter PC_EVENTS_DELAY = 18,
parameter PC_PHY_COUNT_EN = "TRUE",
parameter PC_SYNC_MODE = "FALSE",
parameter PC_DISABLE_SEQ_MATCH = "TRUE",
parameter PC_MULTI_REGION = "FALSE",
parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1),
parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])),
parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]),
parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES,
parameter REFCLK_FREQ = 300.0, //Reference Clk Feq for IODELAYs
parameter BUFG_FOR_OUTPUTS = "OFF",
parameter CLK_PERIOD = 0,
parameter TCQ = 100
)
(
input rst,
input phy_clk,
input phy_clk_fast,
input freq_refclk,
input mem_refclk,
//input mem_refclk_div4,
input sync_pulse,
input phy_ctl_mstr_empty,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input out_fifos_full ,
// phy control word
input phy_ctl_clk,
input pll_lock,
input [31:0] phy_ctl_wd,
input phy_ctl_wr,
//input input_sink,
output phy_ctl_a_full,
output phy_ctl_full,
//output reg mcGo,
output phy_ctl_empty,
output phy_ctl_ready,
input phy_read_calib,
input phy_write_calib,
output [7:0] ddr_clk, // to memory
output if_a_empty,
output if_empty,
output if_full,
output of_empty,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output [HIGHEST_LANE*80-1:0]phy_din, // array_mode 4x4
output [HIGHEST_LANE*12-1:0]O,
input [HIGHEST_LANE*12-1:0]I,
output wire [HIGHEST_LANE*12-1:0] mem_dq_ts,
input sys_rst,
input rst_rd_clk,
input [3:0] Q_clk,
input [3:0] Qn_clk,
input [1:0] cpt_clk_above, //read clock from bank above
input [1:0] cpt_clk_n_above, //read clock from bank above
input [1:0] cpt_clk_below, //read clock from bank below
input [1:0] cpt_clk_n_below, //read clock from bank below
output [1:0] cpt_clk,
output [1:0] cpt_clk_n,
input idelay_ld,
input [47:0] idelay_ce,
input [47:0] idelay_inc,
input [HIGHEST_LANE*5*12-1:0] idelay_cnt_in,
output wire [HIGHEST_LANE*5*12-1:0] idelay_cnt_out,
input [2:0] calib_sel,
input calib_in_common,
input [3:0] drive_on_calib_in_common,
input po_edge_adv,
input po_fine_enable,
input po_coarse_enable,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [8:0] po_counter_load_val,
input po_sel_fine_oclk_delay,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
output wire po_delay_done,
input po_dec_done,
input po_inc_done,
input pi_edge_adv,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output wire ref_dll_lock,
input rst_phaser_ref,
output [1023:0] dbg_byte_lane, // RC
output [255:0] dbg_phy_4lanes // RC
);
localparam DATA_CTL_A = (~DATA_CTL_N[0]);
localparam DATA_CTL_B = (~DATA_CTL_N[1]);
localparam DATA_CTL_C = (~DATA_CTL_N[2]);
localparam DATA_CTL_D = (~DATA_CTL_N[3]);
localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0];
localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1];
localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2];
localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3];
// OUTPUT_BANK is true when the byte lane has atleast one output byte lane.
localparam OUTPUT_BANK = ((BYTE_LANES[0] && ~BYTE_GROUP_TYPE[0]) ||
(BYTE_LANES[1] && ~BYTE_GROUP_TYPE[1]) ||
(BYTE_LANES[2] && ~BYTE_GROUP_TYPE[2]) ||
(BYTE_LANES[3] && ~BYTE_GROUP_TYPE[3]) ) ? "TRUE" : "FALSE";
localparam INPUT_BANK = ((BYTE_LANES[0] && DATA_CTL_N[0]) ||
(BYTE_LANES[1] && DATA_CTL_N[1]) ||
(BYTE_LANES[2] && DATA_CTL_N[2]) ||
(BYTE_LANES[3] && DATA_CTL_N[3]) ) ? "TRUE" : "FALSE";
localparam PC_DATA_CTL_A = (MEMORY_TYPE == "RLD3" && DATA_CTL_A) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_B = (MEMORY_TYPE == "RLD3" && DATA_CTL_B) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_C = (MEMORY_TYPE == "RLD3" && DATA_CTL_C) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_D = (MEMORY_TYPE == "RLD3" && DATA_CTL_D) ? "FALSE" : "TRUE";
localparam MSB_BURST_PEND_PO = 3;
localparam MSB_BURST_PEND_PI = 7;
localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI+ 8;
localparam MSB_RANK_SEL_O = MSB_RANK_SEL_I + 8;
localparam MSB_DIV_RST = MSB_RANK_SEL_O + 1;
localparam MSB_PHASE_SELECT = MSB_DIV_RST + 1;
localparam MSB_BURST_PI = MSB_PHASE_SELECT + 4;
localparam PHASER_CTL_BUS_WIDTH = MSB_BURST_PI + 1;
localparam A_BYTE_GROUP_TYPE = ((BYTE_LANES[0] != 1) ? "DC" :
(INTERFACE_TYPE == "BIDIR") ?
((DATA_CTL_N[0] == 1) ? "BIDIR" : "OUT") :
(BYTE_GROUP_TYPE[0] == 1'b1)? "IN" : "OUT");
localparam B_BYTE_GROUP_TYPE = ((BYTE_LANES[1] != 1) ? "DC" :
(INTERFACE_TYPE == "BIDIR") ?
((DATA_CTL_N[1] == 1) ? "BIDIR" : "OUT"):
(BYTE_GROUP_TYPE[1] == 1'b1)? "IN" : "OUT");
localparam C_BYTE_GROUP_TYPE = ((BYTE_LANES[2] != 1) ? "DC" :
(INTERFACE_TYPE == "BIDIR") ?
((DATA_CTL_N[2] == 1) ? "BIDIR" : "OUT") :
(BYTE_GROUP_TYPE[2] == 1'b1)? "IN" : "OUT");
localparam D_BYTE_GROUP_TYPE = ((BYTE_LANES[3] != 1) ? "DC" :
(INTERFACE_TYPE == "BIDIR") ?
((DATA_CTL_N[3] == 1) ? "BIDIR" : "OUT") :
(BYTE_GROUP_TYPE[3] == 1'b1)? "IN" : "OUT");
wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus;
wire [7:0] in_rank;
wire [7:0] out_rank;
wire [11:0] IO_A;
wire [11:0] IO_B;
wire [11:0] IO_C;
wire [11:0] IO_D;
wire [319:0] phy_din_remap;
reg A_po_counter_read_en;
wire [8:0] A_po_counter_read_val;
reg A_pi_counter_read_en;
wire [5:0] A_pi_counter_read_val;
wire A_pi_fine_overflow;
wire A_po_coarse_overflow;
wire A_po_fine_overflow;
reg A_pi_edge_adv;
reg A_pi_fine_enable;
reg A_pi_fine_inc;
reg A_pi_counter_load_en;
reg [5:0] A_pi_counter_load_val;
reg A_po_fine_enable;
reg A_po_edge_adv;
reg A_po_coarse_enable;
reg A_po_fine_inc;
reg A_po_sel_fine_oclk_delay;
reg A_po_coarse_inc;
reg A_po_counter_load_en;
reg [8:0] A_po_counter_load_val;
wire A_po_delay_done;
reg B_po_counter_read_en;
wire [8:0] B_po_counter_read_val;
reg B_pi_counter_read_en;
wire [5:0] B_pi_counter_read_val;
wire B_pi_fine_overflow;
wire B_po_coarse_overflow;
wire B_po_fine_overflow;
reg B_pi_edge_adv;
reg B_pi_fine_enable;
reg B_pi_fine_inc;
reg B_pi_counter_load_en;
reg [5:0] B_pi_counter_load_val;
wire B_po_delay_done;
reg B_po_fine_enable;
reg B_po_edge_adv;
reg B_po_coarse_enable;
reg B_po_fine_inc;
reg B_po_coarse_inc;
reg B_po_sel_fine_oclk_delay;
reg B_po_counter_load_en;
reg [8:0] B_po_counter_load_val;
reg C_pi_fine_inc;
reg D_pi_fine_inc;
reg C_pi_fine_enable;
reg D_pi_fine_enable;
reg C_pi_edge_adv;
reg D_pi_edge_adv;
reg C_po_counter_load_en;
reg D_po_counter_load_en;
reg C_po_coarse_inc;
reg D_po_coarse_inc;
reg C_po_fine_inc;
reg D_po_fine_inc;
reg C_po_sel_fine_oclk_delay;
reg D_po_sel_fine_oclk_delay;
reg [5:0] C_pi_counter_load_val;
reg [5:0] D_pi_counter_load_val;
reg [8:0] C_po_counter_load_val;
reg [8:0] D_po_counter_load_val;
reg C_po_edge_adv;
reg C_po_coarse_enable;
reg D_po_edge_adv;
reg D_po_coarse_enable;
reg C_po_fine_enable;
reg D_po_fine_enable;
wire C_po_coarse_overflow;
wire D_po_coarse_overflow;
wire C_po_fine_overflow;
wire D_po_fine_overflow;
wire [8:0] C_po_counter_read_val;
wire [8:0] D_po_counter_read_val;
reg C_po_counter_read_en;
reg D_po_counter_read_en;
wire C_pi_fine_overflow;
wire D_pi_fine_overflow;
reg C_pi_counter_read_en;
reg D_pi_counter_read_en;
reg C_pi_counter_load_en;
reg D_pi_counter_load_en;
wire [5:0] C_pi_counter_read_val;
wire [5:0] D_pi_counter_read_val;
wire C_po_delay_done;
wire D_po_delay_done;
wire A_if_empty;
wire B_if_empty;
wire C_if_empty;
wire D_if_empty;
wire A_if_a_empty;
wire B_if_a_empty;
wire C_if_a_empty;
wire D_if_a_empty;
wire A_if_full;
wire B_if_full;
wire C_if_full;
wire D_if_full;
//wire A_if_a_full;
//wire B_if_a_full;
//wire C_if_a_full;
//wire D_if_a_full;
wire A_of_empty;
wire B_of_empty;
wire C_of_empty;
wire D_of_empty;
wire A_of_full;
wire B_of_full;
wire C_of_full;
wire D_of_full;
wire A_of_ctl_full;
wire B_of_ctl_full;
wire C_of_ctl_full;
wire D_of_ctl_full;
wire A_of_data_full;
wire B_of_data_full;
wire C_of_data_full;
wire D_of_data_full;
wire A_of_a_full;
wire B_of_a_full;
wire C_of_a_full;
wire D_of_a_full;
wire A_of_ctl_a_full;
wire B_of_ctl_a_full;
wire C_of_ctl_a_full;
wire D_of_ctl_a_full;
wire A_of_data_a_full;
wire B_of_data_a_full;
wire C_of_data_a_full;
wire D_of_data_a_full;
reg A_cq_clk;
reg B_cq_clk;
reg C_cq_clk;
reg D_cq_clk;
reg A_cqn_clk;
reg B_cqn_clk;
reg C_cqn_clk;
reg D_cqn_clk;
wire [1:0] A_ddr_clk; // for generation
wire [1:0] B_ddr_clk; //
wire [1:0] C_ddr_clk; //
wire [1:0] D_ddr_clk; //
wire [1:0] cq_buf_clk;
wire [1:0] cqn_buf_clk;
wire [3:0] cq_clk;
wire [3:0] cqn_clk;
wire cq_capt_clk;
wire cqn_capt_clk;
wire [3:0] aux_out;
wire [1:0] phy_encalib;
wire dangling_outputs; // this reduces all constant 0 values to 1 signal
// which can be tied to an unused input. The purpose
// is to fake the tools into ignoring dangling outputs.
// Because it is anded with 1'b0, the contributing signals
// are folded as constants or trimmed.
assign dbg_phy_4lanes[3:0] = {D_if_empty, C_if_empty, B_if_empty, A_if_empty};
wire [255:0] A_dbg_byte_lane;
wire [255:0] B_dbg_byte_lane;
wire [255:0] C_dbg_byte_lane;
wire [255:0] D_dbg_byte_lane;
assign dbg_byte_lane = {D_dbg_byte_lane,
C_dbg_byte_lane,
B_dbg_byte_lane,
A_dbg_byte_lane};
assign dangling_outputs = (& idelay_cnt_in) & ( &phy_dout) ;
assign if_empty = A_if_empty | B_if_empty | C_if_empty | D_if_empty;
assign if_a_empty = A_if_a_empty & B_if_a_empty & C_if_a_empty & D_if_a_empty;
assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ;
//assign if_a_full = A_if_a_full | B_if_a_full | C_if_a_full | D_if_a_full ;
assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty;
assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ;
assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ;
assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ;
assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full ;
assign po_delay_done = A_po_delay_done & B_po_delay_done & C_po_delay_done & D_po_delay_done;
function [47:0] part_select_48;
input [191:0] vector;
input [1:0] select;
begin
case (select)
2'b00 : part_select_48[47:0] = vector[1*48-1:0*48];
2'b01 : part_select_48[47:0] = vector[2*48-1:1*48];
2'b10 : part_select_48[47:0] = vector[3*48-1:2*48];
2'b11 : part_select_48[47:0] = vector[4*48-1:3*48];
endcase
end
endfunction
function [79:0] part_select_80;
input [319:0] vector;
input [1:0] select;
begin
case (select)
2'b00 : part_select_80[79:0] = vector[1*80-1:0*80];
2'b01 : part_select_80[79:0] = vector[2*80-1:1*80];
2'b10 : part_select_80[79:0] = vector[3*80-1:2*80];
2'b11 : part_select_80[79:0] = vector[4*80-1:3*80];
endcase
end
endfunction
wire [319:0] phy_dout_remap;
assign ddr_clk = {D_ddr_clk, C_ddr_clk, B_ddr_clk, A_ddr_clk};
generate
if (~BYTE_LANES[0]) begin
assign A_of_ctl_full = 0;
assign A_of_data_full = 0;
assign A_of_ctl_a_full = 0;
assign A_of_data_a_full = 0;
end else if (PRESENT_DATA_A) begin
assign A_of_data_full = A_of_full;
assign A_of_ctl_full = 0;
assign A_of_data_a_full = A_of_a_full;
assign A_of_ctl_a_full = 0;
end else begin
assign A_of_ctl_full = A_of_full;
assign A_of_data_full = 0;
assign A_of_ctl_a_full = A_of_a_full;
assign A_of_data_a_full = 0;
end
if (~BYTE_LANES[1]) begin
assign B_of_ctl_full = 0;
assign B_of_data_full = 0;
assign B_of_ctl_a_full = 0;
assign B_of_data_a_full = 0;
end else if (PRESENT_DATA_B) begin
assign B_of_data_full = B_of_full;
assign B_of_ctl_full = 0;
assign B_of_data_a_full = B_of_a_full;
assign B_of_ctl_a_full = 0;
end else begin
assign B_of_ctl_full = B_of_full;
assign B_of_data_full = 0;
assign B_of_ctl_a_full = B_of_a_full;
assign B_of_data_a_full = 0;
end
if (~BYTE_LANES[2]) begin
assign C_of_ctl_full = 0;
assign C_of_data_full = 0;
assign C_of_ctl_a_full = 0;
assign C_of_data_a_full = 0;
end else if (PRESENT_DATA_C) begin
assign C_of_data_full = C_of_full;
assign C_of_ctl_full = 0;
assign C_of_data_a_full = C_of_a_full;
assign C_of_ctl_a_full = 0;
end else begin
assign C_of_ctl_full = C_of_full;
assign C_of_data_full = 0;
assign C_of_ctl_a_full = C_of_a_full;
assign C_of_data_a_full = 0;
end
if (~BYTE_LANES[3]) begin
assign D_of_ctl_full = 0;
assign D_of_data_full = 0;
assign D_of_ctl_a_full = 0;
assign D_of_data_a_full = 0;
end else if (PRESENT_DATA_D) begin
assign D_of_data_full = D_of_full;
assign D_of_ctl_full = 0;
assign D_of_data_a_full = D_of_a_full;
assign D_of_ctl_a_full = 0;
end else begin
assign D_of_ctl_full = D_of_full;
assign D_of_data_full = 0;
assign D_of_ctl_a_full = D_of_a_full;
assign D_of_data_a_full = 0;
end
// byte lane must exist and be data lane.
if (PRESENT_DATA_A )
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0];
endcase
else
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_B )
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80];
endcase
else
if (HIGHEST_LANE > 1)
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
// byte lane must exist and be data lane.
if (PRESENT_DATA_C)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160];
endcase
else
if (HIGHEST_LANE > 2)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_D )
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240];
endcase
else
if (HIGHEST_LANE > 3)
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
endgenerate
assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank;
generate
if (OUTPUT_BANK == "TRUE" && BUFG_FOR_OUTPUTS == "OFF") begin : PHY_CONTROL_INST
`ifdef FUJI_BLH
B_PHY_CONTROL #(
`else
PHY_CONTROL #(
`endif
//B_PHY_CONTROL #(
.AO_WRLVL_EN ( PC_AO_WRLVL_EN),
.AO_TOGGLE ( PC_AO_TOGGLE),
.BURST_MODE ( PC_BURST_MODE),
.CO_DURATION ( PC_CO_DURATION ),
.CLK_RATIO ( PC_CLK_RATIO),
.DATA_CTL_A_N ( PC_DATA_CTL_A),
.DATA_CTL_B_N ( PC_DATA_CTL_B),
.DATA_CTL_C_N ( PC_DATA_CTL_C),
.DATA_CTL_D_N ( PC_DATA_CTL_D),
.DI_DURATION ( PC_DI_DURATION ),
.DO_DURATION ( PC_DO_DURATION ),
.EVENTS_DELAY ( PC_EVENTS_DELAY),
.FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS),
.MULTI_REGION ( PC_MULTI_REGION ),
.PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN),
.DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH),
.SYNC_MODE ( PC_SYNC_MODE),
.CMD_OFFSET ( PC_CMD_OFFSET),
.RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0),
.RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1),
.RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2),
.RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3),
.RD_DURATION_0 ( PC_RD_DURATION_0),
.RD_DURATION_1 ( PC_RD_DURATION_1),
.RD_DURATION_2 ( PC_RD_DURATION_2),
.RD_DURATION_3 ( PC_RD_DURATION_3),
.WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0),
.WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1),
.WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2),
.WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3),
.WR_DURATION_0 ( PC_WR_DURATION_0),
.WR_DURATION_1 ( PC_WR_DURATION_1),
.WR_DURATION_2 ( PC_WR_DURATION_2),
.WR_DURATION_3 ( PC_WR_DURATION_3)
) phy_control_i (
.AUXOUTPUT (aux_out),
//`ifdef DEDICATED_ROUTES
.INBURSTPENDING (),
.INRANKA (),
.INRANKB (),
.INRANKC (),
.INRANKD (),
// .OUTBURSTPENDING (),
// .PCENABLECALIB (),
//`else
// .INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]),
// .INRANKA (in_rank[1:0]),
// .INRANKB (in_rank[3:2]),
// .INRANKC (in_rank[5:4]),
// .INRANKD (in_rank[7:6]),
.OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]),
.PCENABLECALIB (phy_encalib),
//`endif
.PHYCTLALMOSTFULL (phy_ctl_a_full),
.PHYCTLFULL (phy_ctl_full),
.PHYCTLEMPTY (phy_ctl_empty),
.PHYCTLREADY (phy_ctl_ready),
.MEMREFCLK (mem_refclk),
.PHYCLK (phy_ctl_clk),
.PHYCTLMSTREMPTY (phy_ctl_mstr_empty),
.PHYCTLWD (phy_ctl_wd),
.PHYCTLWRENABLE (phy_ctl_wr),
.PLLLOCK (pll_lock),
.REFDLLLOCK (ref_dll_lock),
.RESET (rst),
.SYNCIN (sync_pulse),
.READCALIBENABLE (phy_read_calib),
.WRITECALIBENABLE (phy_write_calib)
);
end else begin : NO_PHY_CONTROL_INST
assign phaser_ctl_bus = 'b0;
assign phy_ctl_full = 1'b0;
assign phy_ctl_a_full = 1'b0;
assign phy_ctl_ready = ~rst;//1'b1;
assign phy_ctl_empty = 1'b0;
end
endgenerate
//obligatory phaser-ref
//GENERATE statement commented out to avoid a change in the UCF for placing the
//PHASER_REF for non-BUFG interfaces (which is most of them).
//To use the BUFG scheme for outputs this will need to be uncommented
//generate
// if (BUFG_FOR_OUTPUTS == "OFF" ||
// (BUFG_FOR_OUTPUTS == "ON" && INPUT_BANK == "TRUE")) begin : PHASER_REF_INST
PHASER_REF phaser_ref_i(
.LOCKED (ref_dll_lock),
.CLKIN (freq_refclk),
.PWRDWN (1'b0),
.RST (rst_phaser_ref)
);
// end else begin : GEN_NO_PHASER_REF
// assign ref_dll_lock = 1'b1;
// end
//endgenerate
generate
if ( BYTE_LANES[0] ) begin : qdr_rld_byte_lane_A
assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0]));
mig_7series_v2_0_qdr_rld_byte_lane#(
.ABCD ("A"),
.SIMULATION (SIMULATION),
.PO_COARSE_BYPASS (PO_COARSE_BYPASS),
.CPT_CLK_CQ_ONLY (CPT_CLK_CQ_ONLY),
.PRE_FIFO (PRE_FIFO),
.BITLANES_IN (BITLANES_IN[11:0]),
.BITLANES_OUT (BITLANES_OUT[11:0]),
.CK_P_OUT (CK_P_OUT[11:0]),
.MEMORY_TYPE (MEMORY_TYPE),
.DATA_CTL_N (DATA_CTL_N[0]),
.GENERATE_DDR_CK (GENERATE_DDR_CK[0]),
.GENERATE_DDR_DK (GENERATE_DDR_DK[0]),
.DIFF_CK (DIFF_CK),
.DIFF_DK (DIFF_DK),
.CK_VALUE_D1 (CK_VALUE_D1),
.DK_VALUE_D1 (DK_VALUE_D1),
.IODELAY_GRP (IODELAY_GRP),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.BYTE_GROUP_TYPE (A_BYTE_GROUP_TYPE),
.REFCLK_FREQ (REFCLK_FREQ),
.BUFG_FOR_OUTPUTS (BUFG_FOR_OUTPUTS),
.CLK_PERIOD (CLK_PERIOD),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (A_PI_FINE_DELAY),
.PI_REFCLK_PERIOD (A_PI_REFCLK_PERIOD),
.MEMREFCLK_PERIOD (MEMREFCLK_PERIOD),
.PO_FINE_DELAY (PO_FINE_DELAY),
.PO_FINE_SKEW_DELAY (A_PO_FINE_DELAY),
.PO_COARSE_SKEW_DELAY (A_PO_COARSE_DELAY),
.PO_OCLK_DELAY (A_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV),
.PO_REFCLK_PERIOD (A_PO_REFCLK_PERIOD),
.PHASER_CTL_BUS_WIDTH (PHASER_CTL_BUS_WIDTH),
.TCQ (TCQ)
)
qdr_rld_byte_lane_A(
.O ( O[11:0]),
.I ( I[11:0]),
.mem_dq_ts ( mem_dq_ts[11:0]),
.rst (rst),
.phy_clk (phy_clk),
.phy_clk_fast (phy_clk_fast),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.sync_pulse (sync_pulse),
.sys_rst (sys_rst),
.rst_rd_clk (rst_rd_clk),
.cq_buf_clk (A_cq_clk),
.cqn_buf_clk (A_cqn_clk),
.ddr_ck_out (A_ddr_clk),
.if_a_empty (A_if_a_empty),
.if_empty (A_if_empty),
.if_a_full (),
.if_full (A_if_full),
.of_a_empty (),
.of_empty (A_of_empty),
.of_a_full (A_of_a_full),
.of_full (A_of_full),
.out_fifos_full (out_fifos_full ),
.phy_din (phy_din_remap[79:0]),
.phy_dout (phy_dout_remap[79:0]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce[(1*12)-1:(12)*0]),
.idelay_inc (idelay_inc[(1*12)-1:(12)*0]),
.idelay_cnt_in (idelay_cnt_in[12*5-1:0]),
.idelay_cnt_out (idelay_cnt_out[12*5-1:0]),
.po_edge_adv (A_po_edge_adv),
.po_fine_enable (A_po_fine_enable),
.po_coarse_enable (A_po_coarse_enable),
.po_fine_inc (A_po_fine_inc),
.po_coarse_inc (A_po_coarse_inc),
.po_counter_load_en (A_po_counter_load_en),
.po_counter_read_en (A_po_counter_read_en),
.po_counter_load_val (A_po_counter_load_val),
.po_coarse_overflow (A_po_coarse_overflow),
.po_fine_overflow (A_po_fine_overflow),
.po_counter_read_val (A_po_counter_read_val),
.po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay),
.pi_edge_adv (A_pi_edge_adv),
.pi_fine_enable (A_pi_fine_enable),
.pi_fine_inc (A_pi_fine_inc),
.pi_counter_load_en (A_pi_counter_load_en),
.pi_counter_read_en (A_pi_counter_read_en),
.pi_counter_load_val (A_pi_counter_load_val),
.pi_fine_overflow (A_pi_fine_overflow),
.pi_counter_read_val (A_pi_counter_read_val),
.po_delay_done (A_po_delay_done),
.po_dec_done (po_dec_done),
.po_inc_done (po_inc_done),
.dbg_byte_lane (A_dbg_byte_lane)
);
end
else begin : no_byte_lane_A
assign A_of_a_full = 1'b0;
assign A_of_full = 1'b0;
assign A_if_full = 1'b0;
assign A_if_empty = 0;
assign A_po_delay_done = 1;
assign O[11:0] = 0;
end
if ( BYTE_LANES[1] ) begin : qdr_rld_byte_lane_B
assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4]));
mig_7series_v2_0_qdr_rld_byte_lane#(
.ABCD ("B"),
.SIMULATION (SIMULATION),
.PO_COARSE_BYPASS (PO_COARSE_BYPASS),
.CPT_CLK_CQ_ONLY (CPT_CLK_CQ_ONLY),
.PRE_FIFO (PRE_FIFO),
.BITLANES_IN (BITLANES_IN[23:12]),
.BITLANES_OUT (BITLANES_OUT[23:12]),
.CK_P_OUT (CK_P_OUT[23:12]),
.MEMORY_TYPE (MEMORY_TYPE),
.BYTE_GROUP_TYPE (B_BYTE_GROUP_TYPE),
.REFCLK_FREQ (REFCLK_FREQ),
.BUFG_FOR_OUTPUTS (BUFG_FOR_OUTPUTS),
.CLK_PERIOD (CLK_PERIOD),
.PC_CLK_RATIO (PC_CLK_RATIO),
.IODELAY_GRP (IODELAY_GRP),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.DATA_CTL_N (DATA_CTL_N[1]),
.GENERATE_DDR_CK (GENERATE_DDR_CK[1]),
.GENERATE_DDR_DK (GENERATE_DDR_DK[1]),
.DIFF_CK (DIFF_CK),
.DIFF_DK (DIFF_DK),
.CK_VALUE_D1 (CK_VALUE_D1),
.DK_VALUE_D1 (DK_VALUE_D1),
.PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (B_PI_FINE_DELAY),
.PI_REFCLK_PERIOD (B_PI_REFCLK_PERIOD),
.MEMREFCLK_PERIOD (MEMREFCLK_PERIOD),
.PO_FINE_DELAY (PO_FINE_DELAY),
.PO_FINE_SKEW_DELAY (B_PO_FINE_DELAY),
.PO_COARSE_SKEW_DELAY (B_PO_COARSE_DELAY),
.PO_OCLK_DELAY (B_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV),
.PO_REFCLK_PERIOD (B_PO_REFCLK_PERIOD),
.PHASER_CTL_BUS_WIDTH (PHASER_CTL_BUS_WIDTH),
.TCQ (TCQ)
)
qdr_rld_byte_lane_B(
.O ( O[23:12]),
.I ( I[23:12]),
.mem_dq_ts ( mem_dq_ts[23:12]),
.rst (rst),
.phy_clk (phy_clk),
.phy_clk_fast (phy_clk_fast),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.sync_pulse (sync_pulse),
.sys_rst (sys_rst),
.rst_rd_clk (rst_rd_clk),
.cq_buf_clk (B_cq_clk),
.cqn_buf_clk (B_cqn_clk),
.ddr_ck_out (B_ddr_clk),
.if_a_empty (B_if_a_empty),
.if_empty (B_if_empty),
.if_a_full (),
.if_full (B_if_full),
.of_a_empty (),
.of_empty (B_of_empty),
.of_a_full (B_of_a_full),
.of_full (B_of_full),
.out_fifos_full (out_fifos_full ),
.phy_din (phy_din_remap[159:80]),
.phy_dout (phy_dout_remap[159:80]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce[(2*12)-1:(12)*1]),
.idelay_inc (idelay_inc[(2*12)-1:(12)*1]),
.idelay_cnt_in (idelay_cnt_in[24*5-1:12*5]),
.idelay_cnt_out (idelay_cnt_out[24*5-1:12*5]),
.po_edge_adv (B_po_edge_adv),
.po_fine_enable (B_po_fine_enable),
.po_coarse_enable (B_po_coarse_enable),
.po_fine_inc (B_po_fine_inc),
.po_coarse_inc (B_po_coarse_inc),
.po_counter_load_en (B_po_counter_load_en),
.po_counter_read_en (B_po_counter_read_en),
.po_counter_load_val (B_po_counter_load_val),
.po_coarse_overflow (B_po_coarse_overflow),
.po_fine_overflow (B_po_fine_overflow),
.po_counter_read_val (B_po_counter_read_val),
.po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay),
.pi_edge_adv (B_pi_edge_adv),
.pi_fine_enable (B_pi_fine_enable),
.pi_fine_inc (B_pi_fine_inc),
.pi_counter_load_en (B_pi_counter_load_en),
.pi_counter_read_en (B_pi_counter_read_en),
.pi_counter_load_val (B_pi_counter_load_val),
.pi_fine_overflow (B_pi_fine_overflow),
.pi_counter_read_val (B_pi_counter_read_val),
.po_delay_done (B_po_delay_done),
.po_dec_done (po_dec_done),
.po_inc_done (po_inc_done),
.dbg_byte_lane (B_dbg_byte_lane)
);
end
else begin : no_byte_lane_B
assign B_of_a_full = 1'b0;
assign B_of_full = 1'b0;
assign B_if_full = 1'b0;
assign B_if_empty = 0;
assign B_po_delay_done = 1;
if ( HIGHEST_LANE > 1) begin
assign O[23:12] = 0;
end
end
if ( BYTE_LANES[2] ) begin : qdr_rld_byte_lane_C
assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8]));
mig_7series_v2_0_qdr_rld_byte_lane#(
.ABCD ("C"),
.SIMULATION (SIMULATION),
.PO_COARSE_BYPASS (PO_COARSE_BYPASS),
.CPT_CLK_CQ_ONLY (CPT_CLK_CQ_ONLY),
.PRE_FIFO (PRE_FIFO),
.BITLANES_IN (BITLANES_IN[35:24]),
.BITLANES_OUT (BITLANES_OUT[35:24]),
.CK_P_OUT (CK_P_OUT[35:24]),
.MEMORY_TYPE (MEMORY_TYPE),
.BYTE_GROUP_TYPE (C_BYTE_GROUP_TYPE),
.REFCLK_FREQ (REFCLK_FREQ),
.BUFG_FOR_OUTPUTS (BUFG_FOR_OUTPUTS),
.CLK_PERIOD (CLK_PERIOD),
.PC_CLK_RATIO (PC_CLK_RATIO),
.IODELAY_GRP (IODELAY_GRP),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.DATA_CTL_N (DATA_CTL_N[2]),
.GENERATE_DDR_CK (GENERATE_DDR_CK[2]),
.GENERATE_DDR_DK (GENERATE_DDR_DK[2]),
.DIFF_CK (DIFF_CK),
.DIFF_DK (DIFF_DK),
.CK_VALUE_D1 (CK_VALUE_D1),
.DK_VALUE_D1 (DK_VALUE_D1),
.PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (C_PI_FINE_DELAY),
.PI_REFCLK_PERIOD (C_PI_REFCLK_PERIOD),
.MEMREFCLK_PERIOD (MEMREFCLK_PERIOD),
.PO_FINE_DELAY (PO_FINE_DELAY),
.PO_FINE_SKEW_DELAY (C_PO_FINE_DELAY),
.PO_COARSE_SKEW_DELAY (C_PO_COARSE_DELAY),
.PO_OCLK_DELAY (C_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV),
.PO_REFCLK_PERIOD (C_PO_REFCLK_PERIOD),
.PHASER_CTL_BUS_WIDTH (PHASER_CTL_BUS_WIDTH),
.TCQ (TCQ)
)
qdr_rld_byte_lane_C(
.O ( O[35:24]),
.I ( I[35:24]),
.mem_dq_ts ( mem_dq_ts[35:24]),
.rst (rst),
.phy_clk (phy_clk),
.phy_clk_fast (phy_clk_fast),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.sync_pulse (sync_pulse),
.sys_rst (sys_rst),
.rst_rd_clk (rst_rd_clk),
.cq_buf_clk (C_cq_clk),
.cqn_buf_clk (C_cqn_clk),
.ddr_ck_out (C_ddr_clk),
.if_a_empty (C_if_a_empty),
.if_empty (C_if_empty),
.if_a_full (),
.if_full (C_if_full),
.of_a_empty (),
.of_empty (C_of_empty),
.of_a_full (C_of_a_full),
.of_full (C_of_full),
.out_fifos_full (out_fifos_full ),
.phy_din (phy_din_remap[239:160]),
.phy_dout (phy_dout_remap[239:160]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce[(3*12)-1:(12)*2]),
.idelay_inc (idelay_inc[(3*12)-1:(12)*2]),
.idelay_cnt_in (idelay_cnt_in[36*5-1:24*5]),
.idelay_cnt_out (idelay_cnt_out[36*5-1:24*5]),
.po_edge_adv (C_po_edge_adv),
.po_fine_enable (C_po_fine_enable),
.po_coarse_enable (C_po_coarse_enable),
.po_fine_inc (C_po_fine_inc),
.po_coarse_inc (C_po_coarse_inc),
.po_counter_load_en (C_po_counter_load_en),
.po_counter_read_en (C_po_counter_read_en),
.po_counter_load_val (C_po_counter_load_val),
.po_coarse_overflow (C_po_coarse_overflow),
.po_fine_overflow (C_po_fine_overflow),
.po_counter_read_val (C_po_counter_read_val),
.po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay),
.pi_edge_adv (C_pi_edge_adv),
.pi_fine_enable (C_pi_fine_enable),
.pi_fine_inc (C_pi_fine_inc),
.pi_counter_load_en (C_pi_counter_load_en),
.pi_counter_read_en (C_pi_counter_read_en),
.pi_counter_load_val (C_pi_counter_load_val),
.pi_fine_overflow (C_pi_fine_overflow),
.pi_counter_read_val (C_pi_counter_read_val),
.po_delay_done (C_po_delay_done),
.po_dec_done (po_dec_done),
.po_inc_done (po_inc_done),
.dbg_byte_lane (C_dbg_byte_lane)
);
end
else begin : no_byte_lane_C
assign C_of_a_full = 1'b0;
assign C_of_full = 1'b0;
assign C_if_full = 1'b0;
assign C_if_empty = 0;
assign C_po_delay_done = 1;
if ( HIGHEST_LANE > 2) begin
assign O[35:24] = 0;
end
end
if ( BYTE_LANES[3] ) begin : qdr_rld_byte_lane_D
assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12]));
mig_7series_v2_0_qdr_rld_byte_lane#(
.ABCD ("D"),
.SIMULATION (SIMULATION),
.PO_COARSE_BYPASS (PO_COARSE_BYPASS),
.CPT_CLK_CQ_ONLY (CPT_CLK_CQ_ONLY),
.PRE_FIFO (PRE_FIFO),
.BITLANES_IN (BITLANES_IN[47:36]),
.BITLANES_OUT (BITLANES_OUT[47:36]),
.CK_P_OUT (CK_P_OUT[47:36]),
.MEMORY_TYPE (MEMORY_TYPE),
.BYTE_GROUP_TYPE (D_BYTE_GROUP_TYPE),
.REFCLK_FREQ (REFCLK_FREQ),
.BUFG_FOR_OUTPUTS (BUFG_FOR_OUTPUTS),
.CLK_PERIOD (CLK_PERIOD),
.PC_CLK_RATIO (PC_CLK_RATIO),
.IODELAY_GRP (IODELAY_GRP),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.DATA_CTL_N (DATA_CTL_N[3]),
.GENERATE_DDR_CK (GENERATE_DDR_CK[3]),
.GENERATE_DDR_DK (GENERATE_DDR_DK[3]),
.DIFF_CK (DIFF_CK),
.DIFF_DK (DIFF_DK),
.CK_VALUE_D1 (CK_VALUE_D1),
.DK_VALUE_D1 (DK_VALUE_D1),
.PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (D_PI_FINE_DELAY),
.PI_REFCLK_PERIOD (D_PI_REFCLK_PERIOD),
.MEMREFCLK_PERIOD (MEMREFCLK_PERIOD),
.PO_FINE_DELAY (PO_FINE_DELAY),
.PO_FINE_SKEW_DELAY (D_PO_FINE_DELAY),
.PO_COARSE_SKEW_DELAY (D_PO_COARSE_DELAY),
.PO_OCLK_DELAY (D_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV),
.PO_REFCLK_PERIOD (D_PO_REFCLK_PERIOD),
.PHASER_CTL_BUS_WIDTH (PHASER_CTL_BUS_WIDTH),
.TCQ (TCQ)
)
qdr_rld_byte_lane_D(
.O ( O[47:36]),
.I ( I[47:36]),
.mem_dq_ts ( mem_dq_ts[47:36]),
.rst (rst),
.phy_clk (phy_clk),
.phy_clk_fast (phy_clk_fast),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.sync_pulse (sync_pulse),
.sys_rst (sys_rst),
.rst_rd_clk (rst_rd_clk),
.cq_buf_clk (D_cq_clk),
.cqn_buf_clk (D_cqn_clk),
.ddr_ck_out (D_ddr_clk),
.if_a_empty (D_if_a_empty),
.if_empty (D_if_empty),
.if_a_full (),
.if_full (D_if_full),
.of_a_empty (),
.of_empty (D_of_empty),
.of_a_full (D_of_a_full),
.of_full (D_of_full),
.out_fifos_full (out_fifos_full),
.phy_din (phy_din_remap[319:240]),
.phy_dout (phy_dout_remap[319:240]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce[(4*12)-1:(12)*3]),
.idelay_inc (idelay_inc[(4*12)-1:(12)*3]),
.idelay_cnt_in (idelay_cnt_in[48*5-1:36*5]),
.idelay_cnt_out (idelay_cnt_out[48*5-1:36*5]),
.po_edge_adv (D_po_edge_adv),
.po_fine_enable (D_po_fine_enable),
.po_coarse_enable (D_po_coarse_enable),
.po_fine_inc (D_po_fine_inc),
.po_coarse_inc (D_po_coarse_inc),
.po_counter_load_en (D_po_counter_load_en),
.po_counter_read_en (D_po_counter_read_en),
.po_counter_load_val (D_po_counter_load_val),
.po_coarse_overflow (D_po_coarse_overflow),
.po_fine_overflow (D_po_fine_overflow),
.po_counter_read_val (D_po_counter_read_val),
.po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay),
.pi_edge_adv (D_pi_edge_adv),
.pi_fine_enable (D_pi_fine_enable),
.pi_fine_inc (D_pi_fine_inc),
.pi_counter_load_en (D_pi_counter_load_en),
.pi_counter_read_en (D_pi_counter_read_en),
.pi_counter_load_val (D_pi_counter_load_val),
.pi_fine_overflow (D_pi_fine_overflow),
.pi_counter_read_val (D_pi_counter_read_val),
.po_delay_done (D_po_delay_done),
.po_dec_done (po_dec_done),
.po_inc_done (po_inc_done),
.dbg_byte_lane (D_dbg_byte_lane)
);
end
else begin : no_byte_lane_D
assign D_of_a_full = 1'b0;
assign D_of_full = 1'b0;
assign D_if_full = 1'b0;
assign D_if_empty = 0;
assign D_po_delay_done = 1;
if ( HIGHEST_LANE > 3) begin
assign O[47:36] = 0;
end
end
endgenerate
// register outputs to give extra slack in timing
always @(posedge phy_clk) begin
case (calib_sel[1:0])
2'h0: begin
po_coarse_overflow <= #1 A_po_coarse_overflow;
po_fine_overflow <= #1 A_po_fine_overflow;
po_counter_read_val <= #1 A_po_counter_read_val;
pi_fine_overflow <= #1 A_pi_fine_overflow;
pi_counter_read_val <= #1 A_pi_counter_read_val;
end
2'h1: begin
po_coarse_overflow <= #1 B_po_coarse_overflow;
po_fine_overflow <= #1 B_po_fine_overflow;
po_counter_read_val <= #1 B_po_counter_read_val;
pi_fine_overflow <= #1 B_pi_fine_overflow;
pi_counter_read_val <= #1 B_pi_counter_read_val;
end
2'h2: begin
po_coarse_overflow <= #1 C_po_coarse_overflow;
po_fine_overflow <= #1 C_po_fine_overflow;
po_counter_read_val <= #1 C_po_counter_read_val;
pi_fine_overflow <= #1 C_pi_fine_overflow;
pi_counter_read_val <= #1 C_pi_counter_read_val;
end
2'h3: begin
po_coarse_overflow <= #1 D_po_coarse_overflow;
po_fine_overflow <= #1 D_po_fine_overflow;
po_counter_read_val <= #1 D_po_counter_read_val;
pi_fine_overflow <= #1 D_pi_fine_overflow;
pi_counter_read_val <= #1 D_pi_counter_read_val;
end
default: begin
po_coarse_overflow <= #1 A_po_coarse_overflow;
po_fine_overflow <= #1 A_po_fine_overflow;
po_counter_read_val <= #1 A_po_counter_read_val;
pi_fine_overflow <= #1 A_pi_fine_overflow;
pi_counter_read_val <= #1 A_pi_counter_read_val;
end
endcase
end
always @(posedge phy_clk) begin
if ( calib_sel[2]) begin
A_pi_fine_enable <= #TCQ 0;
A_pi_edge_adv <= #TCQ 0;
A_pi_fine_inc <= #TCQ 0;
A_pi_counter_load_en <= #TCQ 0;
A_pi_counter_read_en <= #TCQ 0;
A_pi_counter_load_val <= #TCQ 0;
A_po_fine_enable <= #TCQ 0;
A_po_edge_adv <= #TCQ 0;
A_po_coarse_enable <= #TCQ 0;
A_po_fine_inc <= #TCQ 0;
A_po_coarse_inc <= #TCQ 0;
A_po_counter_load_en <= #TCQ 0;
A_po_counter_read_en <= #TCQ 0;
A_po_counter_load_val <= #TCQ 0;
A_po_sel_fine_oclk_delay <= #TCQ 0;
B_pi_fine_enable <= #TCQ 0;
B_pi_edge_adv <= #TCQ 0;
B_pi_fine_inc <= #TCQ 0;
B_pi_counter_load_en <= #TCQ 0;
B_pi_counter_read_en <= #TCQ 0;
B_pi_counter_load_val <= #TCQ 0;
B_po_fine_enable <= #TCQ 0;
B_po_edge_adv <= #TCQ 0;
B_po_coarse_enable <= #TCQ 0;
B_po_fine_inc <= #TCQ 0;
B_po_coarse_inc <= #TCQ 0;
B_po_counter_load_en <= #TCQ 0;
B_po_counter_read_en <= #TCQ 0;
B_po_counter_load_val <= #TCQ 0;
B_po_sel_fine_oclk_delay <= #TCQ 0;
C_pi_fine_enable <= #TCQ 0;
C_pi_edge_adv <= #TCQ 0;
C_pi_fine_inc <= #TCQ 0;
C_pi_counter_load_en <= #TCQ 0;
C_pi_counter_read_en <= #TCQ 0;
C_pi_counter_load_val <= #TCQ 0;
C_po_fine_enable <= #TCQ 0;
C_po_edge_adv <= #TCQ 0;
C_po_coarse_enable <= #TCQ 0;
C_po_fine_inc <= #TCQ 0;
C_po_coarse_inc <= #TCQ 0;
C_po_counter_load_en <= #TCQ 0;
C_po_counter_read_en <= #TCQ 0;
C_po_counter_load_val <= #TCQ 0;
C_po_sel_fine_oclk_delay <= #TCQ 0;
D_pi_fine_enable <= #TCQ 0;
D_pi_edge_adv <= #TCQ 0;
D_pi_fine_inc <= #TCQ 0;
D_pi_counter_load_en <= #TCQ 0;
D_pi_counter_read_en <= #TCQ 0;
D_pi_counter_load_val <= #TCQ 0;
D_po_fine_enable <= #TCQ 0;
D_po_edge_adv <= #TCQ 0;
D_po_coarse_enable <= #TCQ 0;
D_po_fine_inc <= #TCQ 0;
D_po_coarse_inc <= #TCQ 0;
D_po_counter_load_en <= #TCQ 0;
D_po_counter_read_en <= #TCQ 0;
D_po_counter_load_val <= #TCQ 0;
D_po_sel_fine_oclk_delay <= #TCQ 0;
end else
if (calib_in_common) begin
if (drive_on_calib_in_common[0] == 1) begin
A_pi_fine_enable <= #TCQ pi_fine_enable;
A_pi_edge_adv <= #TCQ pi_edge_adv;
A_pi_fine_inc <= #TCQ pi_fine_inc;
A_pi_counter_load_en <= #TCQ pi_counter_load_en;
A_pi_counter_read_en <= #TCQ pi_counter_read_en;
A_pi_counter_load_val <= #TCQ pi_counter_load_val;
A_po_fine_enable <= #TCQ po_fine_enable;
A_po_edge_adv <= #TCQ po_edge_adv;
A_po_coarse_enable <= #TCQ po_coarse_enable;
A_po_fine_inc <= #TCQ po_fine_inc;
A_po_coarse_inc <= #TCQ po_coarse_inc;
A_po_counter_load_en <= #TCQ po_counter_load_en;
A_po_counter_read_en <= #TCQ po_counter_read_en;
A_po_counter_load_val <= #TCQ po_counter_load_val;
A_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
if (drive_on_calib_in_common[1] == 1) begin
B_pi_fine_enable <= #TCQ pi_fine_enable;
B_pi_edge_adv <= #TCQ pi_edge_adv;
B_pi_fine_inc <= #TCQ pi_fine_inc;
B_pi_counter_load_en <= #TCQ pi_counter_load_en;
B_pi_counter_read_en <= #TCQ pi_counter_read_en;
B_pi_counter_load_val <= #TCQ pi_counter_load_val;
B_po_fine_enable <= #TCQ po_fine_enable;
B_po_edge_adv <= #TCQ po_edge_adv;
B_po_coarse_enable <= #TCQ po_coarse_enable;
B_po_fine_inc <= #TCQ po_fine_inc;
B_po_coarse_inc <= #TCQ po_coarse_inc;
B_po_counter_load_en <= #TCQ po_counter_load_en;
B_po_counter_read_en <= #TCQ po_counter_read_en;
B_po_counter_load_val <= #TCQ po_counter_load_val;
B_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
if (drive_on_calib_in_common[2] == 1) begin
C_pi_fine_enable <= #TCQ pi_fine_enable;
C_pi_edge_adv <= #TCQ pi_edge_adv;
C_pi_fine_inc <= #TCQ pi_fine_inc;
C_pi_counter_load_en <= #TCQ pi_counter_load_en;
C_pi_counter_read_en <= #TCQ pi_counter_read_en;
C_pi_counter_load_val <= #TCQ pi_counter_load_val;
C_po_fine_enable <= #TCQ po_fine_enable;
C_po_edge_adv <= #TCQ po_edge_adv;
C_po_coarse_enable <= #TCQ po_coarse_enable;
C_po_fine_inc <= #TCQ po_fine_inc;
C_po_coarse_inc <= #TCQ po_coarse_inc;
C_po_counter_load_en <= #TCQ po_counter_load_en;
C_po_counter_read_en <= #TCQ po_counter_read_en;
C_po_counter_load_val <= #TCQ po_counter_load_val;
C_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
if (drive_on_calib_in_common[3] == 1) begin
D_pi_fine_enable <= #TCQ pi_fine_enable;
D_pi_edge_adv <= #TCQ pi_edge_adv;
D_pi_fine_inc <= #TCQ pi_fine_inc;
D_pi_counter_load_en <= #TCQ pi_counter_load_en;
D_pi_counter_read_en <= #TCQ pi_counter_read_en;
D_pi_counter_load_val <= #TCQ pi_counter_load_val;
D_po_fine_enable <= #TCQ po_fine_enable;
D_po_edge_adv <= #TCQ po_edge_adv;
D_po_coarse_enable <= #TCQ po_coarse_enable;
D_po_fine_inc <= #TCQ po_fine_inc;
D_po_coarse_inc <= #TCQ po_coarse_inc;
D_po_counter_load_en <= #TCQ po_counter_load_en;
D_po_counter_read_en <= #TCQ po_counter_read_en;
D_po_counter_load_val <= #TCQ po_counter_load_val;
D_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
end
else begin
// otherwise, only a single phaser is selected
A_pi_fine_enable <= #TCQ 0;
A_pi_edge_adv <= #TCQ 0;
A_pi_fine_inc <= #TCQ 0;
A_pi_counter_load_en <= #TCQ 0;
A_pi_counter_read_en <= #TCQ 0;
A_pi_counter_load_val <= #TCQ 0;
A_po_fine_enable <= #TCQ 0;
A_po_edge_adv <= #TCQ 0;
A_po_coarse_enable <= #TCQ 0;
A_po_fine_inc <= #TCQ 0;
A_po_coarse_inc <= #TCQ 0;
A_po_counter_load_en <= #TCQ 0;
A_po_counter_read_en <= #TCQ 0;
A_po_counter_load_val <= #TCQ 0;
A_po_sel_fine_oclk_delay <= #TCQ 0;
B_pi_fine_enable <= #TCQ 0;
B_pi_edge_adv <= #TCQ 0;
B_pi_fine_inc <= #TCQ 0;
B_pi_counter_load_en <= #TCQ 0;
B_pi_counter_read_en <= #TCQ 0;
B_pi_counter_load_val <= #TCQ 0;
B_po_fine_enable <= #TCQ 0;
B_po_edge_adv <= #TCQ 0;
B_po_coarse_enable <= #TCQ 0;
B_po_fine_inc <= #TCQ 0;
B_po_coarse_inc <= #TCQ 0;
B_po_counter_load_en <= #TCQ 0;
B_po_counter_read_en <= #TCQ 0;
B_po_counter_load_val <= #TCQ 0;
B_po_sel_fine_oclk_delay <= #TCQ 0;
C_pi_fine_enable <= #TCQ 0;
C_pi_edge_adv <= #TCQ 0;
C_pi_fine_inc <= #TCQ 0;
C_pi_counter_load_en <= #TCQ 0;
C_pi_counter_read_en <= #TCQ 0;
C_pi_counter_load_val <= #TCQ 0;
C_po_fine_enable <= #TCQ 0;
C_po_edge_adv <= #TCQ 0;
C_po_coarse_enable <= #TCQ 0;
C_po_fine_inc <= #TCQ 0;
C_po_coarse_inc <= #TCQ 0;
C_po_counter_load_en <= #TCQ 0;
C_po_counter_read_en <= #TCQ 0;
C_po_counter_load_val <= #TCQ 0;
C_po_sel_fine_oclk_delay <= #TCQ 0;
D_pi_fine_enable <= #TCQ 0;
D_pi_edge_adv <= #TCQ 0;
D_pi_fine_inc <= #TCQ 0;
D_pi_counter_load_en <= #TCQ 0;
D_pi_counter_read_en <= #TCQ 0;
D_pi_counter_load_val <= #TCQ 0;
D_po_fine_enable <= #TCQ 0;
D_po_edge_adv <= #TCQ 0;
D_po_coarse_enable <= #TCQ 0;
D_po_fine_inc <= #TCQ 0;
D_po_coarse_inc <= #TCQ 0;
D_po_counter_load_en <= #TCQ 0;
D_po_counter_read_en <= #TCQ 0;
D_po_counter_load_val <= #TCQ 0;
D_po_sel_fine_oclk_delay <= #TCQ 0;
case (calib_sel[1:0])
0: begin
A_pi_fine_enable <= #TCQ pi_fine_enable;
A_pi_edge_adv <= #TCQ pi_edge_adv;
A_pi_fine_inc <= #TCQ pi_fine_inc;
A_pi_counter_load_en <= #TCQ pi_counter_load_en;
A_pi_counter_read_en <= #TCQ pi_counter_read_en;
A_pi_counter_load_val <= #TCQ pi_counter_load_val;
A_po_fine_enable <= #TCQ po_fine_enable;
A_po_edge_adv <= #TCQ po_edge_adv;
A_po_coarse_enable <= #TCQ po_coarse_enable;
A_po_fine_inc <= #TCQ po_fine_inc;
A_po_coarse_inc <= #TCQ po_coarse_inc;
A_po_counter_load_en <= #TCQ po_counter_load_en;
A_po_counter_read_en <= #TCQ po_counter_read_en;
A_po_counter_load_val <= #TCQ po_counter_load_val;
A_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
1: begin
B_pi_fine_enable <= #TCQ pi_fine_enable;
B_pi_edge_adv <= #TCQ pi_edge_adv;
B_pi_fine_inc <= #TCQ pi_fine_inc;
B_pi_counter_load_en <= #TCQ pi_counter_load_en;
B_pi_counter_read_en <= #TCQ pi_counter_read_en;
B_pi_counter_load_val <= #TCQ pi_counter_load_val;
B_po_fine_enable <= #TCQ po_fine_enable;
B_po_edge_adv <= #TCQ po_edge_adv;
B_po_coarse_enable <= #TCQ po_coarse_enable;
B_po_fine_inc <= #TCQ po_fine_inc;
B_po_coarse_inc <= #TCQ po_coarse_inc;
B_po_counter_load_en <= #TCQ po_counter_load_en;
B_po_counter_read_en <= #TCQ po_counter_read_en;
B_po_counter_load_val <= #TCQ po_counter_load_val;
B_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
2: begin
C_pi_fine_enable <= #TCQ pi_fine_enable;
C_pi_edge_adv <= #TCQ pi_edge_adv;
C_pi_fine_inc <= #TCQ pi_fine_inc;
C_pi_counter_load_en <= #TCQ pi_counter_load_en;
C_pi_counter_read_en <= #TCQ pi_counter_read_en;
C_pi_counter_load_val <= #TCQ pi_counter_load_val;
C_po_fine_enable <= #TCQ po_fine_enable;
C_po_edge_adv <= #TCQ po_edge_adv;
C_po_coarse_enable <= #TCQ po_coarse_enable;
C_po_fine_inc <= #TCQ po_fine_inc;
C_po_coarse_inc <= #TCQ po_coarse_inc;
C_po_counter_load_en <= #TCQ po_counter_load_en;
C_po_counter_read_en <= #TCQ po_counter_read_en;
C_po_counter_load_val <= #TCQ po_counter_load_val;
C_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
3: begin
D_pi_fine_enable <= #TCQ pi_fine_enable;
D_pi_edge_adv <= #TCQ pi_edge_adv;
D_pi_fine_inc <= #TCQ pi_fine_inc;
D_pi_counter_load_en <= #TCQ pi_counter_load_en;
D_pi_counter_read_en <= #TCQ pi_counter_read_en;
D_pi_counter_load_val <= #TCQ pi_counter_load_val;
D_po_fine_enable <= #TCQ po_fine_enable;
D_po_edge_adv <= #TCQ po_edge_adv;
D_po_coarse_enable <= #TCQ po_coarse_enable;
D_po_fine_inc <= #TCQ po_fine_inc;
D_po_coarse_inc <= #TCQ po_coarse_inc;
D_po_counter_load_en <= #TCQ po_counter_load_en;
D_po_counter_read_en <= #TCQ po_counter_read_en;
D_po_counter_load_val <= #TCQ po_counter_load_val;
D_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
endcase
end
end
//For QDR2+ since there is only one clock we use both BUFMR locations
//Hence, even if we only specify one location we generate both in that case
generate
genvar i;
if (DIFF_CQ == 1) begin: gen_ibufds_cq //Differential Read Clock
assign cqn_buf_clk = 'b0; //tie-off unused signal
if (MEMORY_TYPE == "RLD3") begin : gen_ibufds_cq_rld3
for (i = 0; i < 4; i = i + 1) begin
if (GENERATE_CQ[i]==1) begin
IBUFDS u_bufds_cq ( .I (Q_clk[i]),
.IB (Qn_clk[i]),
.O (cq_clk[i]) //cq_buf_clk[i]
);
assign cqn_clk[i] = ~cq_clk[i];
end //end of if
end //end of for
end else begin
//BUFMR instances
if (GENERATE_CQ[1]==1) begin
IBUFDS bufds_cq_1 ( .I (Q_clk[1]),
.IB (Qn_clk[1]),
.O (cq_buf_clk[0])
);
BUFMR bufmr_cq_1 ( .O(cq_clk[0]), .I(cq_buf_clk[0]) );
assign cqn_clk[0] = ~cq_clk[0];
end //end of if
if (GENERATE_CQ[2]==1) begin
IBUFDS bufds_cq_2 ( .I (Q_clk[2]),
.IB (Qn_clk[2]),
.O (cq_buf_clk[1])
);
BUFMR bufmr_cq_2 ( .O(cq_clk[1]), .I(cq_buf_clk[1]) );
assign cqn_clk[1] = ~cq_clk[1];
end //end of if
end
end else begin: gen_ibuf_cq //QDR2+ case, use both locations all the time
//work around for current QDR2+ parameters
//ideally since we have 4 byte lanes we want the parameters to specify
//where the clocks should go, but QDR2+ parameters handle it differently
// When changed, fix this to [1] & {2] as expected
if (GENERATE_CQ[0]==1 || GENERATE_CQ[1]==1 ||
GENERATE_CQ[2]==1 || GENERATE_CQ[3]==1 ) begin
//tie-off unused signals
assign cq_clk[1] = 1'b0;
assign cqn_clk[1] = 1'b0;
// it is legal to have the cq in either bytelane 1 or 2 for QDR.
if (GENERATE_CQ[1] == 1) begin
assign cq_capt_clk = Q_clk[1];
assign cqn_capt_clk = Qn_clk[1];
end else if (GENERATE_CQ[2] == 1) begin
assign cq_capt_clk = Q_clk[2];
assign cqn_capt_clk = Qn_clk[2];
end
IBUF buf_cq (.O (cq_buf_clk[0]), .I (cq_capt_clk) );
IBUF buf_cqn (.O (cqn_buf_clk[0]), .I (cqn_capt_clk) );
BUFMR bufmr_cq (.O (cq_clk[0]), .I (cq_buf_clk[0]) );
BUFMR bufmr_cqn (.O (cqn_clk[0]), .I (cqn_buf_clk[0]));
end else begin
assign cq_buf_clk = 'b0;
assign cqn_buf_clk= 'b0;
assign cq_clk = 'b0;
assign cqn_clk = 'b0;
end
end //end gen_ibuf_cq
endgenerate
assign #(BUFMR_DELAY) cpt_clk[0] = cq_clk[0];
assign #(BUFMR_DELAY) cpt_clk[1] = cq_clk[1];
assign #(BUFMR_DELAY) cpt_clk_n[0] = cqn_clk[0];
assign #(BUFMR_DELAY) cpt_clk_n[1] = cqn_clk[1];
//assign all of the read clocks to the different phy lanes (RLDRAM only)
generate
if (DIFF_CQ == 1) begin: gen_cpt_assignments
if (MEMORY_TYPE == "RLD3") begin
//One clock per byte lane, no BUFMR so no extra delay needs to be inserted
//for simulation
always @(*) begin
A_cq_clk <= cq_clk[0];
B_cq_clk <= cq_clk[1];
C_cq_clk <= cq_clk[2];
D_cq_clk <= cq_clk[3];
//N-side not used
A_cqn_clk <= 1'b0;
B_cqn_clk <= 1'b0;
C_cqn_clk <= 1'b0;
D_cqn_clk <= 1'b0;
end
end else begin
always @(*) begin
//A byte lane
if (CPT_CLK_SEL[7:0]==8'h11)
A_cq_clk <= cpt_clk[0];
else if (CPT_CLK_SEL[7:0]==8'h12)
A_cq_clk <= cpt_clk[1];
else if (CPT_CLK_SEL[7:0]==8'h01) //from Bank below
A_cq_clk <= cpt_clk_below[0];
else if (CPT_CLK_SEL[7:0]==8'h02) //from Bank below
A_cq_clk <= cpt_clk_below[1];
else if (CPT_CLK_SEL[7:0]==8'h21) //from Bank above
A_cq_clk <= cpt_clk_above[0];
else if (CPT_CLK_SEL[7:0]==8'h22) //from Bank above
A_cq_clk <= cpt_clk_above[1];
else
A_cq_clk <= cpt_clk[0]; //default
//B byte lane
if (CPT_CLK_SEL[15:8]==8'h11)
B_cq_clk <= cpt_clk[0];
else if (CPT_CLK_SEL[15:8]==8'h12)
B_cq_clk <= cpt_clk[1];
else if (CPT_CLK_SEL[15:8]==8'h01) //from Bank below
B_cq_clk <= cpt_clk_below[0];
else if (CPT_CLK_SEL[15:8]==8'h02) //from Bank below
B_cq_clk <= cpt_clk_below[1];
else if (CPT_CLK_SEL[15:8]==8'h21) //from Bank above
B_cq_clk <= cpt_clk_above[0];
else if (CPT_CLK_SEL[15:8]==8'h22) //from Bank above
B_cq_clk <= cpt_clk_above[1];
else
B_cq_clk <= cpt_clk[0]; //default
//C byte lane
if (CPT_CLK_SEL[23:16]==8'h11)
C_cq_clk <= cpt_clk[0];
else if (CPT_CLK_SEL[23:16]==8'h12)
C_cq_clk <= cpt_clk[1];
else if (CPT_CLK_SEL[23:16]==8'h01) //from Bank below
C_cq_clk <= cpt_clk_below[0];
else if (CPT_CLK_SEL[23:16]==8'h02) //from Bank below
C_cq_clk <= cpt_clk_below[1];
else if (CPT_CLK_SEL[23:16]==8'h21) //from Bank above
C_cq_clk <= cpt_clk_above[0];
else if (CPT_CLK_SEL[23:16]==8'h22) //from Bank above
C_cq_clk <= cpt_clk_above[1];
else
C_cq_clk <= cpt_clk[0]; //default
//D byte lane
if (CPT_CLK_SEL[31:24]==8'h11)
D_cq_clk <= cpt_clk[0];
else if (CPT_CLK_SEL[31:24]==8'h12)
D_cq_clk <= cpt_clk[1];
else if (CPT_CLK_SEL[31:24]==8'h01) //from Bank below
D_cq_clk <= cpt_clk_below[0];
else if (CPT_CLK_SEL[31:24]==8'h02) //from Bank below
D_cq_clk <= cpt_clk_below[1];
else if (CPT_CLK_SEL[31:24]==8'h21) //from Bank above
D_cq_clk <= cpt_clk_above[0];
else if (CPT_CLK_SEL[31:24]==8'h22) //from Bank above
D_cq_clk <= cpt_clk_above[1];
else
D_cq_clk <= cpt_clk[0]; //default
//n-side of signal not used, tie to 0
A_cqn_clk <= #(BUFMR_DELAY) 1'b0;
B_cqn_clk <= #(BUFMR_DELAY) 1'b0;
C_cqn_clk <= #(BUFMR_DELAY) 1'b0;
D_cqn_clk <= #(BUFMR_DELAY) 1'b0;
end //always @ (*)
end
end else begin : gen_qdr_assignments
always @(*) begin
//A byte lane
if (CPT_CLK_SEL[7:4]== 4'h1) begin
A_cq_clk = cpt_clk[0];
A_cqn_clk = cpt_clk_n[0];
end else if (CPT_CLK_SEL[7:4]==4'h0) begin//from Bank below
A_cq_clk = cpt_clk_below[0];
A_cqn_clk = cpt_clk_n_below[0];
end else if (CPT_CLK_SEL[7:4]==4'h2) begin //from Bank above
A_cq_clk = cpt_clk_above[0];
A_cqn_clk = cpt_clk_n_above[0];
end else begin //default case
A_cq_clk = cpt_clk[0];
A_cqn_clk = cpt_clk_n[0];
end
//B byte lane
if (CPT_CLK_SEL[15:12]== 4'h1) begin
B_cq_clk = cpt_clk[0];
B_cqn_clk = cpt_clk_n[0];
end else if (CPT_CLK_SEL[15:12]==4'h0) begin//from Bank below
B_cq_clk = cpt_clk_below[0];
B_cqn_clk = cpt_clk_n_below[0];
end else if (CPT_CLK_SEL[15:12]==4'h2) begin //from Bank above
B_cq_clk = cpt_clk_above[0];
B_cqn_clk = cpt_clk_n_above[0];
end else begin //default case
B_cq_clk = cpt_clk[0];
B_cqn_clk = cpt_clk_n[0];
end
//C byte lane
if (CPT_CLK_SEL[23:20]== 4'h1) begin
C_cq_clk = cpt_clk[0];
C_cqn_clk = cpt_clk_n[0];
end else if (CPT_CLK_SEL[23:20]==4'h0) begin//from Bank below
C_cq_clk = cpt_clk_below[0];
C_cqn_clk = cpt_clk_n_below[0];
end else if (CPT_CLK_SEL[23:20]==4'h2) begin //from Bank above
C_cq_clk = cpt_clk_above[0];
C_cqn_clk = cpt_clk_n_above[0];
end else begin //default case
C_cq_clk = cpt_clk[0];
C_cqn_clk = cpt_clk_n[0];
end
//D byte lane
if (CPT_CLK_SEL[31:28]== 4'h1) begin
D_cq_clk = cpt_clk[0];
D_cqn_clk = cpt_clk_n[0];
end else if (CPT_CLK_SEL[31:28]==4'h0) begin//from Bank below
D_cq_clk = cpt_clk_below[0];
D_cqn_clk = cpt_clk_n_below[0];
end else if (CPT_CLK_SEL[31:28]==4'h2) begin //from Bank above
D_cq_clk = cpt_clk_above[0];
D_cqn_clk = cpt_clk_n_above[0];
end else begin //default case
D_cq_clk = cpt_clk[0];
D_cqn_clk = cpt_clk_n[0];
end
end
end
endgenerate
endmodule
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 1
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (DRT) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
assign wbs0_int_i = 0;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//Spi Stuff
wire [31:0] ss_pad_o;
//wire ss_pad_o;
wire sclk_pad_o;
wire mosi_pad_o;
reg miso_pad_i;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_spi s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int ),
.ss_pad_o (ss_pad_o ),
.sclk_pad_o (sclk_pad_o ),
.mosi_pad_o (mosi_pad_o ),
.miso_pad_i (miso_pad_i )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
$display ("");
end
else begin
$display ("Error unrecognized line: %h" % ch);
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
$display ("Sleep for %h Clock cycles", r_in_data_count);
`SLEEP_CLK(r_in_data_count);
$display ("Sleep Finished");
end
else begin
$display ("Error: read_count = %h != 4", read_count);
$display ("Character: %h", ch);
end
end
else begin
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
$display ("Execute Command");
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
$display ("TB: reading a new double word: %h", r_in_data);
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
$display ("Command Finished");
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
$display ("TB: finished command");
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
$display ("TB: sdram is ready");
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
$display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data);
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
$display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count);
state <= WRITE_RESPONSE;
end
end
else begin
$display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data);
$display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count);
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
$display ("TB: Ping Response Good");
end
else begin
$display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status);
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
$display ("In Write Response");
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
$display ("TB: Write Response Good");
end
else begin
$display ("TB: Write Response Bad (Malformed response: %h)", w_out_status);
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
$display ("TB: Read Response Good");
if (w_out_data_count > 0) begin
$display("TB: w_out_data_count: %d", w_out_data_count);
if (data_read_count <= w_out_data_count) begin
$display ("TB: Read more data...");
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
$display ("TB: Read Response Bad (Malformed response: %h)", w_out_status);
state <= FINISHED;
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
$display ("TB: Read a 32bit data packet");
$display ("TB: \tRead Data: %h", w_out_data);
data_read_count <= data_read_count + 1;
end
if (data_read_count > r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
$display ("Execute Command is low");
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
$display("TB: Output Handler Recieved interrupt");
$display("TB:\tcommand: %h", w_out_status);
$display("TB:\taddress: %h", w_out_address);
$display("TB:\tdata: %h", w_out_data);
end
end//not reset
end
reg prev_sclk;
reg [127:0]mosi_data;
wire pos_edge_sclk;
reg [7:0] index;
assign pos_edge_sclk = ~prev_sclk && sclk_pad_o;
always @ (posedge clk) begin
if (rst) begin
miso_pad_i <= 0;
prev_sclk <= 0;
mosi_data <= 0;
index <= 0;
end
else begin
if (~ss_pad_o[0]) begin
//if (~ss_pad_o) begin
index <= 0;
end
if (pos_edge_sclk) begin
miso_pad_i <= ~miso_pad_i;
mosi_data[index] <= mosi_pad_o;
index <= index + 1;
end
prev_sclk <= sclk_pad_o;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_V |
`include "constants.vh"
`default_nettype none
module rs_ldst_ent
(
//Memory
input wire clk,
input wire reset,
input wire busy,
input wire [`ADDR_LEN-1:0] wpc,
input wire [`DATA_LEN-1:0] wsrc1,
input wire [`DATA_LEN-1:0] wsrc2,
input wire wvalid1,
input wire wvalid2,
input wire [`DATA_LEN-1:0] wimm,
input wire [`RRF_SEL-1:0] wrrftag,
input wire wdstval,
input wire [`SPECTAG_LEN-1:0] wspectag,
input wire we,
output wire [`DATA_LEN-1:0] ex_src1,
output wire [`DATA_LEN-1:0] ex_src2,
output wire ready,
output reg [`ADDR_LEN-1:0] pc,
output reg [`DATA_LEN-1:0] imm,
output reg [`RRF_SEL-1:0] rrftag,
output reg dstval,
output reg [`SPECTAG_LEN-1:0] spectag,
//EXRSLT
input wire [`DATA_LEN-1:0] exrslt1,
input wire [`RRF_SEL-1:0] exdst1,
input wire kill_spec1,
input wire [`DATA_LEN-1:0] exrslt2,
input wire [`RRF_SEL-1:0] exdst2,
input wire kill_spec2,
input wire [`DATA_LEN-1:0] exrslt3,
input wire [`RRF_SEL-1:0] exdst3,
input wire kill_spec3,
input wire [`DATA_LEN-1:0] exrslt4,
input wire [`RRF_SEL-1:0] exdst4,
input wire kill_spec4,
input wire [`DATA_LEN-1:0] exrslt5,
input wire [`RRF_SEL-1:0] exdst5,
input wire kill_spec5
);
reg [`DATA_LEN-1:0] src1;
reg [`DATA_LEN-1:0] src2;
reg valid1;
reg valid2;
wire [`DATA_LEN-1:0] nextsrc1;
wire [`DATA_LEN-1:0] nextsrc2;
wire nextvalid1;
wire nextvalid2;
assign ready = busy & valid1 & valid2;
assign ex_src1 = ~valid1 & nextvalid1 ?
nextsrc1 : src1;
assign ex_src2 = ~valid2 & nextvalid2 ?
nextsrc2 : src2;
always @ (posedge clk) begin
if (reset) begin
pc <= 0;
imm <= 0;
rrftag <= 0;
dstval <= 0;
spectag <= 0;
src1 <= 0;
src2 <= 0;
valid1 <= 0;
valid2 <= 0;
end else if (we) begin
pc <= wpc;
imm <= wimm;
rrftag <= wrrftag;
dstval <= wdstval;
spectag <= wspectag;
src1 <= wsrc1;
src2 <= wsrc2;
valid1 <= wvalid1;
valid2 <= wvalid2;
end else begin // if (we)
src1 <= nextsrc1;
src2 <= nextsrc2;
valid1 <= nextvalid1;
valid2 <= nextvalid2;
end
end
src_manager srcmng1(
.opr(src1),
.opr_rdy(valid1),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5),
.src(nextsrc1),
.resolved(nextvalid1)
);
src_manager srcmng2(
.opr(src2),
.opr_rdy(valid2),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5),
.src(nextsrc2),
.resolved(nextvalid2)
);
endmodule // rs_ldst
module rs_ldst
(
//System
input wire clk,
input wire reset,
output reg [`LDST_ENT_NUM-1:0] busyvec,
input wire prmiss,
input wire prsuccess,
input wire [`SPECTAG_LEN-1:0] prtag,
input wire [`SPECTAG_LEN-1:0] specfixtag,
output wire [`LDST_ENT_NUM-1:0] prbusyvec_next,
//WriteSignal
input wire clearbusy, //Issue
input wire [`LDST_ENT_SEL-1:0] issueaddr, //= raddr, clsbsyadr
input wire we1, //alloc1
input wire we2, //alloc2
input wire [`LDST_ENT_SEL-1:0] waddr1, //allocent1
input wire [`LDST_ENT_SEL-1:0] waddr2, //allocent2
//WriteSignal1
input wire [`ADDR_LEN-1:0] wpc_1,
input wire [`DATA_LEN-1:0] wsrc1_1,
input wire [`DATA_LEN-1:0] wsrc2_1,
input wire wvalid1_1,
input wire wvalid2_1,
input wire [`DATA_LEN-1:0] wimm_1,
input wire [`RRF_SEL-1:0] wrrftag_1,
input wire wdstval_1,
input wire [`SPECTAG_LEN-1:0] wspectag_1,
input wire wspecbit_1,
//WriteSignal2
input wire [`ADDR_LEN-1:0] wpc_2,
input wire [`DATA_LEN-1:0] wsrc1_2,
input wire [`DATA_LEN-1:0] wsrc2_2,
input wire wvalid1_2,
input wire wvalid2_2,
input wire [`DATA_LEN-1:0] wimm_2,
input wire [`RRF_SEL-1:0] wrrftag_2,
input wire wdstval_2,
input wire [`SPECTAG_LEN-1:0] wspectag_2,
input wire wspecbit_2,
//ReadSignal
output wire [`DATA_LEN-1:0] ex_src1,
output wire [`DATA_LEN-1:0] ex_src2,
output wire [`LDST_ENT_NUM-1:0] ready,
output wire [`ADDR_LEN-1:0] pc,
output wire [`DATA_LEN-1:0] imm,
output wire [`RRF_SEL-1:0] rrftag,
output wire dstval,
output wire [`SPECTAG_LEN-1:0] spectag,
output wire specbit,
//EXRSLT
input wire [`DATA_LEN-1:0] exrslt1,
input wire [`RRF_SEL-1:0] exdst1,
input wire kill_spec1,
input wire [`DATA_LEN-1:0] exrslt2,
input wire [`RRF_SEL-1:0] exdst2,
input wire kill_spec2,
input wire [`DATA_LEN-1:0] exrslt3,
input wire [`RRF_SEL-1:0] exdst3,
input wire kill_spec3,
input wire [`DATA_LEN-1:0] exrslt4,
input wire [`RRF_SEL-1:0] exdst4,
input wire kill_spec4,
input wire [`DATA_LEN-1:0] exrslt5,
input wire [`RRF_SEL-1:0] exdst5,
input wire kill_spec5
);
//_0
wire [`DATA_LEN-1:0] ex_src1_0;
wire [`DATA_LEN-1:0] ex_src2_0;
wire ready_0;
wire [`ADDR_LEN-1:0] pc_0;
wire [`DATA_LEN-1:0] imm_0;
wire [`RRF_SEL-1:0] rrftag_0;
wire dstval_0;
wire [`SPECTAG_LEN-1:0] spectag_0;
//_1
wire [`DATA_LEN-1:0] ex_src1_1;
wire [`DATA_LEN-1:0] ex_src2_1;
wire ready_1;
wire [`ADDR_LEN-1:0] pc_1;
wire [`DATA_LEN-1:0] imm_1;
wire [`RRF_SEL-1:0] rrftag_1;
wire dstval_1;
wire [`SPECTAG_LEN-1:0] spectag_1;
//_2
wire [`DATA_LEN-1:0] ex_src1_2;
wire [`DATA_LEN-1:0] ex_src2_2;
wire ready_2;
wire [`ADDR_LEN-1:0] pc_2;
wire [`DATA_LEN-1:0] imm_2;
wire [`RRF_SEL-1:0] rrftag_2;
wire dstval_2;
wire [`SPECTAG_LEN-1:0] spectag_2;
//_3
wire [`DATA_LEN-1:0] ex_src1_3;
wire [`DATA_LEN-1:0] ex_src2_3;
wire ready_3;
wire [`ADDR_LEN-1:0] pc_3;
wire [`DATA_LEN-1:0] imm_3;
wire [`RRF_SEL-1:0] rrftag_3;
wire dstval_3;
wire [`SPECTAG_LEN-1:0] spectag_3;
reg [`LDST_ENT_NUM-1:0] specbitvec;
//busy invalidation
wire [`LDST_ENT_NUM-1:0] inv_vector =
{(spectag_3 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_2 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_1 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_0 & specfixtag) == 0 ? 1'b1 : 1'b0};
wire [`LDST_ENT_NUM-1:0] inv_vector_spec =
{(spectag_3 == prtag) ? 1'b0 : 1'b1,
(spectag_2 == prtag) ? 1'b0 : 1'b1,
(spectag_1 == prtag) ? 1'b0 : 1'b1,
(spectag_0 == prtag) ? 1'b0 : 1'b1};
wire [`LDST_ENT_NUM-1:0] specbitvec_next =
(inv_vector_spec & specbitvec);
/*|
(we1 & wspecbit_1 ? (`LDST_ENT_SEL'b1 << waddr1) : 0) |
(we2 & wspecbit_2 ? (`LDST_ENT_SEL'b1 << waddr2) : 0);
*/
assign specbit = prsuccess ?
specbitvec_next[issueaddr] : specbitvec[issueaddr];
assign ready = {ready_3, ready_2, ready_1, ready_0};
assign prbusyvec_next = inv_vector & busyvec;
always @ (posedge clk) begin
if (reset) begin
busyvec <= 0;
specbitvec <= 0;
end else begin
if (prmiss) begin
busyvec <= prbusyvec_next;
specbitvec <= 0;
end else if (prsuccess) begin
specbitvec <= specbitvec_next;
/*
if (we1) begin
busyvec[waddr1] <= 1'b1;
end
if (we2) begin
busyvec[waddr2] <= 1'b1;
end
*/
if (clearbusy) begin
busyvec[issueaddr] <= 1'b0;
end
end else begin
if (we1) begin
busyvec[waddr1] <= 1'b1;
specbitvec[waddr1] <= wspecbit_1;
end
if (we2) begin
busyvec[waddr2] <= 1'b1;
specbitvec[waddr2] <= wspecbit_2;
end
if (clearbusy) begin
busyvec[issueaddr] <= 1'b0;
end
end
end
end
rs_ldst_ent ent0(
.clk(clk),
.reset(reset),
.busy(busyvec[0]),
.wpc((we1 && (waddr1 == 0)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 0)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 0)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 0)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 0)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 0)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 0)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 0)) ? wdstval_1 : wdstval_2),
.wspectag((we1 && (waddr1 == 0)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 0)) || (we2 && (waddr2 == 0))),
.ex_src1(ex_src1_0),
.ex_src2(ex_src2_0),
.ready(ready_0),
.pc(pc_0),
.imm(imm_0),
.rrftag(rrftag_0),
.dstval(dstval_0),
.spectag(spectag_0),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_ldst_ent ent1(
.clk(clk),
.reset(reset),
.busy(busyvec[1]),
.wpc((we1 && (waddr1 == 1)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 1)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 1)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 1)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 1)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 1)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 1)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 1)) ? wdstval_1 : wdstval_2),
.wspectag((we1 && (waddr1 == 1)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 1)) || (we2 && (waddr2 == 1))),
.ex_src1(ex_src1_1),
.ex_src2(ex_src2_1),
.ready(ready_1),
.pc(pc_1),
.imm(imm_1),
.rrftag(rrftag_1),
.dstval(dstval_1),
.spectag(spectag_1),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_ldst_ent ent2(
.clk(clk),
.reset(reset),
.busy(busyvec[2]),
.wpc((we1 && (waddr1 == 2)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 2)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 2)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 2)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 2)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 2)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 2)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 2)) ? wdstval_1 : wdstval_2),
.wspectag((we1 && (waddr1 == 2)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 2)) || (we2 && (waddr2 == 2))),
.ex_src1(ex_src1_2),
.ex_src2(ex_src2_2),
.ready(ready_2),
.pc(pc_2),
.imm(imm_2),
.rrftag(rrftag_2),
.dstval(dstval_2),
.spectag(spectag_2),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_ldst_ent ent3(
.clk(clk),
.reset(reset),
.busy(busyvec[3]),
.wpc((we1 && (waddr1 == 3)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 3)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 3)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 3)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 3)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 3)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 3)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 3)) ? wdstval_1 : wdstval_2),
.wspectag((we1 && (waddr1 == 3)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 3)) || (we2 && (waddr2 == 3))),
.ex_src1(ex_src1_3),
.ex_src2(ex_src2_3),
.ready(ready_3),
.pc(pc_3),
.imm(imm_3),
.rrftag(rrftag_3),
.dstval(dstval_3),
.spectag(spectag_3),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
assign ex_src1 = (issueaddr == 0) ? ex_src1_0 :
(issueaddr == 1) ? ex_src1_1 :
(issueaddr == 2) ? ex_src1_2 : ex_src1_3;
assign ex_src2 = (issueaddr == 0) ? ex_src2_0 :
(issueaddr == 1) ? ex_src2_1 :
(issueaddr == 2) ? ex_src2_2 : ex_src2_3;
assign pc = (issueaddr == 0) ? pc_0 :
(issueaddr == 1) ? pc_1 :
(issueaddr == 2) ? pc_2 : pc_3;
assign imm = (issueaddr == 0) ? imm_0 :
(issueaddr == 1) ? imm_1 :
(issueaddr == 2) ? imm_2 : imm_3;
assign rrftag = (issueaddr == 0) ? rrftag_0 :
(issueaddr == 1) ? rrftag_1 :
(issueaddr == 2) ? rrftag_2 : rrftag_3;
assign dstval = (issueaddr == 0) ? dstval_0 :
(issueaddr == 1) ? dstval_1 :
(issueaddr == 2) ? dstval_2 : dstval_3;
assign spectag = (issueaddr == 0) ? spectag_0 :
(issueaddr == 1) ? spectag_1 :
(issueaddr == 2) ? spectag_2 : spectag_3;
endmodule // rs_ldst
`default_nettype wire
|
// soc_system_fpga_only_master.v
// This file was auto-generated from altera_jtag_avalon_master_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 190 at 2017.03.21.23:05:03
`timescale 1 ps / 1 ps
module soc_system_fpga_only_master #(
parameter USE_PLI = 0,
parameter PLI_PORT = 50000,
parameter FIFO_DEPTHS = 2
) (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (USE_PLI != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_pli_check ( .error(1'b1) );
end
if (PLI_PORT != 50000)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
pli_port_check ( .error(1'b1) );
end
if (FIFO_DEPTHS != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.EXPORT_JTAG (0),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // clock.clk
.reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.sink_data (p2b_out_bytes_stream_data), // sink.data
.sink_valid (p2b_out_bytes_stream_valid), // .valid
.sink_ready (p2b_out_bytes_stream_ready), // .ready
.resetrequest (master_reset_reset), // resetrequest.reset
.source_ready (1'b1), // (terminated)
.mgmt_valid (), // (terminated)
.mgmt_channel (), // (terminated)
.mgmt_data (), // (terminated)
.jtag_tck (1'b0), // (terminated)
.jtag_tms (1'b0), // (terminated)
.jtag_tdi (1'b0), // (terminated)
.jtag_tdo (), // (terminated)
.jtag_ena (1'b0), // (terminated)
.jtag_usr1 (1'b0), // (terminated)
.jtag_clr (1'b0), // (terminated)
.jtag_clrn (1'b0), // (terminated)
.jtag_state_tlr (1'b0), // (terminated)
.jtag_state_rti (1'b0), // (terminated)
.jtag_state_sdrs (1'b0), // (terminated)
.jtag_state_cdr (1'b0), // (terminated)
.jtag_state_sdr (1'b0), // (terminated)
.jtag_state_e1dr (1'b0), // (terminated)
.jtag_state_pdr (1'b0), // (terminated)
.jtag_state_e2dr (1'b0), // (terminated)
.jtag_state_udr (1'b0), // (terminated)
.jtag_state_sirs (1'b0), // (terminated)
.jtag_state_cir (1'b0), // (terminated)
.jtag_state_sir (1'b0), // (terminated)
.jtag_state_e1ir (1'b0), // (terminated)
.jtag_state_pir (1'b0), // (terminated)
.jtag_state_e2ir (1'b0), // (terminated)
.jtag_state_uir (1'b0), // (terminated)
.jtag_ir_in (3'b000), // (terminated)
.jtag_irq (), // (terminated)
.jtag_ir_out () // (terminated)
);
soc_system_fpga_only_master_timing_adt timing_adt (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // in.data
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.out_data (timing_adt_out_data), // out.data
.out_valid (timing_adt_out_valid), // .valid
.out_ready (timing_adt_out_ready) // .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timing_adt_out_data), // in.data
.in_valid (timing_adt_out_valid), // .valid
.in_ready (timing_adt_out_ready), // .ready
.out_data (fifo_out_data), // out.data
.out_valid (fifo_out_valid), // .valid
.out_ready (fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // .ready
.out_valid (b2p_out_packets_stream_valid), // .valid
.out_data (b2p_out_packets_stream_data), // .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_ready (fifo_out_ready), // in_bytes_stream.ready
.in_valid (fifo_out_valid), // .valid
.in_data (fifo_out_data) // .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // .valid
.in_data (p2b_adapter_out_data), // .data
.in_channel (p2b_adapter_out_channel), // .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // .valid
.out_data (p2b_out_bytes_stream_data) // .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // out_stream.ready
.out_valid (transacto_out_stream_valid), // .valid
.out_data (transacto_out_stream_data), // .data
.out_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.in_ready (b2p_adapter_out_ready), // in_stream.ready
.in_valid (b2p_adapter_out_valid), // .valid
.in_data (b2p_adapter_out_data), // .data
.in_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // .endofpacket
.address (master_address), // avalon_master.address
.readdata (master_readdata), // .readdata
.read (master_read), // .read
.write (master_write), // .write
.writedata (master_writedata), // .writedata
.waitrequest (master_waitrequest), // .waitrequest
.readdatavalid (master_readdatavalid), // .readdatavalid
.byteenable (master_byteenable) // .byteenable
);
soc_system_fpga_only_master_b2p_adapter b2p_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (b2p_out_packets_stream_data), // in.data
.in_valid (b2p_out_packets_stream_valid), // .valid
.in_ready (b2p_out_packets_stream_ready), // .ready
.in_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_channel (b2p_out_packets_stream_channel), // .channel
.out_data (b2p_adapter_out_data), // out.data
.out_valid (b2p_adapter_out_valid), // .valid
.out_ready (b2p_adapter_out_ready), // .ready
.out_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // .endofpacket
);
soc_system_fpga_only_master_p2b_adapter p2b_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (transacto_out_stream_data), // in.data
.in_valid (transacto_out_stream_valid), // .valid
.in_ready (transacto_out_stream_ready), // .ready
.in_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.out_data (p2b_adapter_out_data), // out.data
.out_valid (p2b_adapter_out_valid), // .valid
.out_ready (p2b_adapter_out_ready), // .ready
.out_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_channel (p2b_adapter_out_channel) // .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
module charComp(char, enter, cEnter, cEne, cVirgul, cDelete, cNum);
input [6:0] char;
input enter;
output reg cEnter, cEne, cVirgul, cDelete,cNum;
always @(char or enter) begin
if(enter==0) begin
case (char)
7'b0000100:begin
cEnter=1;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=0;
end
7'b1101110:begin
cEnter=0;
cEne=1;
cVirgul=0;
cDelete=0;
cNum=0;
end
7'b1001110:begin
cEnter=0;
cEne=1;
cVirgul=0;
cDelete=0;
cNum=0;
end
7'b1111110:begin
cEnter=0;
cEne=0;
cVirgul=1;
cDelete=0;
cNum=0;
end
7'b0001000:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=1;
cNum=0;
end
default: begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=0;
end
endcase
end
if(enter==1) begin
case (char)
7'b0110000:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0110001:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0110010:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0110011:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0110100:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0110101:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0110110:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0110111:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0111000:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0111001:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
default: begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=0;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111AI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O2111AI_FUNCTIONAL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o2111ai (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111AI_FUNCTIONAL_V |
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-2-2017
YM3438_APL.pdf
Timer A = 144*(1024-NA)/Phi M
Timer B = 2304*(256-NB)/Phi M
*/
module jt12_timers(
input clk,
input rst,
input clk_en /* synthesis direct_enable */,
input zero,
input [9:0] value_A,
input [7:0] value_B,
input load_A,
input load_B,
input clr_flag_A,
input clr_flag_B,
input enable_irq_A,
input enable_irq_B,
output flag_A,
output flag_B,
output overflow_A,
output irq_n
);
parameter num_ch = 6;
assign irq_n = ~( (flag_A&enable_irq_A) | (flag_B&enable_irq_B) );
/*
reg zero2;
always @(posedge clk, posedge rst) begin
if( rst )
zero2 <= 0;
else if(clk_en) begin
if( zero ) zero2 <= ~zero;
end
end
wire zero = num_ch == 6 ? zero : (zero2&zero);
*/
jt12_timer #(.CW(10)) timer_A(
.clk ( clk ),
.rst ( rst ),
.cen ( clk_en ),
.zero ( zero ),
.start_value( value_A ),
.load ( load_A ),
.clr_flag ( clr_flag_A ),
.flag ( flag_A ),
.overflow ( overflow_A )
);
jt12_timer #(.CW(8),.FREE_EN(1)) timer_B(
.clk ( clk ),
.rst ( rst ),
.cen ( clk_en ),
.zero ( zero ),
.start_value( value_B ),
.load ( load_B ),
.clr_flag ( clr_flag_B ),
.flag ( flag_B ),
.overflow ( )
);
endmodule
module jt12_timer #(parameter
CW = 8, // counter bit width. This is the counter that can be loaded
FW = 4, // number of bits for the free-running counter
FREE_EN = 0 // enables a 4-bit free enable count
) (
input rst,
input clk,
input cen,
input zero,
input [CW-1:0] start_value,
input load,
input clr_flag,
output reg flag,
output reg overflow
);
/* verilator lint_off WIDTH */
reg load_l;
reg [CW-1:0] cnt, next;
reg [FW-1:0] free_cnt, free_next;
reg free_ov;
always@(posedge clk, posedge rst)
if( rst )
flag <= 1'b0;
else /*if(cen)*/ begin
if( clr_flag )
flag <= 1'b0;
else if( cen && zero && load && overflow ) flag<=1'b1;
end
always @(*) begin
{free_ov, free_next} = { 1'b0, free_cnt} + 1'b1;
{overflow, next } = { 1'b0, cnt } + (FREE_EN ? free_ov : 1'b1);
end
always @(posedge clk) begin
load_l <= load;
if( !load_l && load ) begin
cnt <= start_value;
end else if( cen && zero && load )
cnt <= overflow ? start_value : next;
end
// Free running counter
always @(posedge clk) begin
if( rst ) begin
free_cnt <= 0;
end else if( cen && zero ) begin
free_cnt <= free_cnt+1'd1;
end
end
/* verilator lint_on WIDTH */
endmodule
|
(** * MoreCoq: More About Coq's Tactics *)
Require Export Poly.
(** This chapter introduces several more proof strategies and
tactics that, together, allow us to prove theorems about the
functional programs we have been writing. In particular, we'll
reason about functions that work with natural numbers and lists.
In particular, we will see:
- how to use auxiliary lemmas, in both forwards and backwards reasoning;
- how to reason about data constructors, which are injective and disjoint;
- how to create a strong induction hypotheses (and when
strengthening is required); and
- how to reason by case analysis.
*)
(* ###################################################### *)
(** * The [apply] Tactic *)
(** We often encounter situations where the goal to be proved is
exactly the same as some hypothesis in the context or some
previously proved lemma. *)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n;o] = [n;p] ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
rewrite <- eq1.
(* At this point, we could finish with
"[rewrite -> eq2. reflexivity.]" as we have
done several times above. But we can achieve the
same effect in a single step by using the
[apply] tactic instead: *)
apply eq2. Qed.
(** The [apply] tactic also works with _conditional_ hypotheses
and lemmas: if the statement being applied is an implication, then
the premises of this implication will be added to the list of
subgoals needing to be proved. *)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q;o] = [r;p]) ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
apply eq2. apply eq1. Qed.
(** You may find it instructive to experiment with this proof
and see if there is a way to complete it using just [rewrite]
instead of [apply]. *)
(** Typically, when we use [apply H], the statement [H] will
begin with a [forall] binding some _universal variables_. When
Coq matches the current goal against the conclusion of [H], it
will try to find appropriate values for these variables. For
example, when we do [apply eq2] in the following proof, the
universal variable [q] in [eq2] gets instantiated with [n] and [r]
gets instantiated with [m]. *)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros n m eq1 eq2.
apply eq2. apply eq1. Qed.
(** **** Exercise: 2 stars, optional (silly_ex) *)
(** Complete the following proof without using [simpl]. *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof.
intros H1 H2.
apply H1.
apply H2.
Qed.
(** [] *)
(** To use the [apply] tactic, the (conclusion of the) fact
being applied must match the goal _exactly_ -- for example, [apply]
will not work if the left and right sides of the equality are
swapped. *)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
simpl.
(* Here we cannot use [apply] directly *)
Abort.
(** In this case we can use the [symmetry] tactic, which switches the
left and right sides of an equality in the goal. *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
symmetry.
simpl. (* Actually, this [simpl] is unnecessary, since
[apply] will perform simplification first. *)
apply H. Qed.
(** **** Exercise: 3 stars (apply_exercise1) *)
(** Hint: you can use [apply] with previously defined lemmas, not
just hypotheses in the context. Remember that [SearchAbout] is
your friend. *)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' ->
l' = rev l.
Proof.
intros l l' H.
rewrite H.
symmetry.
apply rev_involutive.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (apply_rewrite) *)
(** Briefly explain the difference between the tactics [apply] and
[rewrite]. Are there situations where both can usefully be
applied?
(* FILL IN HERE *)
*)
(** [] *)
(* ###################################################### *)
(** * The [apply ... with ...] Tactic *)
(** The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
Example trans_eq_example : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
Theorem trans_eq : forall (X:Type) (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(** Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
apply trans_eq with (m:=[c;d]). apply eq1. apply eq2. Qed.
(** Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: [apply trans_eq with [c,d]]. *)
(** **** Exercise: 3 stars, optional (apply_with_exercise) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof.
intros n m o p H1 H2.
apply trans_eq with m.
apply H2.
apply H1.
Qed.
(** [] *)
(* ###################################################### *)
(** * The [inversion] tactic *)
(** Recall the definition of natural numbers:
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
It is clear from this definition that every number has one of two
forms: either it is the constructor [O] or it is built by applying
the constructor [S] to another number. But there is more here than
meets the eye: implicit in the definition (and in our informal
understanding of how datatype declarations work in other
programming languages) are two other facts:
- The constructor [S] is _injective_. That is, the only way we can
have [S n = S m] is if [n = m].
- The constructors [O] and [S] are _disjoint_. That is, [O] is not
equal to [S n] for any [n]. *)
(** Similar principles apply to all inductively defined types: all
constructors are injective, and the values built from distinct
constructors are never equal. For lists, the [cons] constructor is
injective and [nil] is different from every non-empty list. For
booleans, [true] and [false] are unequal. (Since neither [true]
nor [false] take any arguments, their injectivity is not an issue.) *)
(** Coq provides a tactic called [inversion] that allows us to exploit
these principles in proofs.
The [inversion] tactic is used like this. Suppose [H] is a
hypothesis in the context (or a previously proven lemma) of the
form
c a1 a2 ... an = d b1 b2 ... bm
for some constructors [c] and [d] and arguments [a1 ... an] and
[b1 ... bm]. Then [inversion H] instructs Coq to "invert" this
equality to extract the information it contains about these terms:
- If [c] and [d] are the same constructor, then we know, by the
injectivity of this constructor, that [a1 = b1], [a2 = b2],
etc.; [inversion H] adds these facts to the context, and tries
to use them to rewrite the goal.
- If [c] and [d] are different constructors, then the hypothesis
[H] is contradictory. That is, a false assumption has crept
into the context, and this means that any goal whatsoever is
provable! In this case, [inversion H] marks the current goal as
completed and pops it off the goal stack. *)
(** The [inversion] tactic is probably easier to understand by
seeing it in action than from general descriptions like the above.
Below you will find example theorems that demonstrate the use of
[inversion] and exercises to test your understanding. *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros n m eq. inversion eq. reflexivity. Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. inversion eq. reflexivity. Qed.
(** As a convenience, the [inversion] tactic can also
destruct equalities between complex values, binding
multiple variables as it goes. *)
Theorem silly5 : forall (n m o : nat),
[n;m] = [o;o] ->
[n] = [m].
Proof.
intros n m o eq. inversion eq. reflexivity. Qed.
(** **** Exercise: 1 star (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof.
intros X x y z l j H1 H2.
inversion H1.
inversion H2.
symmetry.
apply H0.
Qed.
(** [] *)
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
(** **** Exercise: 1 star (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof.
intros X x y z l j contra.
inversion contra.
Qed.
(** [] *)
(** While the injectivity of constructors allows us to reason
[forall (n m : nat), S n = S m -> n = m], the reverse direction of
the implication is an instance of a more general fact about
constructors and functions, which we will often find useful: *)
Theorem f_equal : forall (A B : Type) (f: A -> B) (x y: A),
x = y -> f x = f y.
Proof. intros A B f x y eq. rewrite eq. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (practice) *)
(** A couple more nontrivial but not-too-complicated proofs to work
together in class, or for you to work as exercises. *)
Theorem beq_nat_0_l : forall n,
beq_nat 0 n = true -> n = 0.
Proof.
intros n.
destruct n.
Case "n = 0".
reflexivity.
Case "n > 0".
intros contra.
inversion contra.
Qed.
Theorem beq_nat_0_r : forall n,
beq_nat n 0 = true -> n = 0.
Proof.
intros n.
destruct n.
Case "n = 0".
reflexivity.
Case "n > 0".
simpl.
intros contra.
inversion contra.
Qed.
(** [] *)
(* ###################################################### *)
(** * Using Tactics on Hypotheses *)
(** By default, most tactics work on the goal formula and leave
the context unchanged. However, most tactics also have a variant
that performs a similar operation on a statement in the context.
For example, the tactic [simpl in H] performs simplification in
the hypothesis named [H] in the context. *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros n m b H. simpl in H. apply H. Qed.
(** Similarly, the tactic [apply L in H] matches some
conditional statement [L] (of the form [L1 -> L2], say) against a
hypothesis [H] in the context. However, unlike ordinary
[apply] (which rewrites a goal matching [L2] into a subgoal [L1]),
[apply L in H] matches [H] against [L1] and, if successful,
replaces it with [L2].
In other words, [apply L in H] gives us a form of "forward
reasoning" -- from [L1 -> L2] and a hypothesis matching [L1], it
gives us a hypothesis matching [L2]. By contrast, [apply L] is
"backward reasoning" -- it says that if we know [L1->L2] and we
are trying to prove [L2], it suffices to prove [L1].
Here is a variant of a proof from above, using forward reasoning
throughout instead of backward reasoning. *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros n eq H.
symmetry in H. apply eq in H. symmetry in H.
apply H. Qed.
(** Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached. Backward reasoning starts from
the _goal_, and iteratively reasons about what would imply the
goal, until premises or previously proven theorems are reached.
If you've seen informal proofs before (for example, in a math or
computer science class), they probably used forward reasoning. In
general, Coq tends to favor backward reasoning, but in some
situations the forward style can be easier to use or to think
about. *)
(** **** Exercise: 3 stars (plus_n_n_injective) *)
(** Practice using "in" variants in this exercise. *)
Theorem plus_n_n_injective : forall n m,
n + n = m + m ->
n = m.
Proof.
intros n.
induction n as [| n'].
Case "n = 0".
simpl.
intros m H.
destruct m as [| m'].
SCase "m = 0".
reflexivity.
SCase "m = S m'".
inversion H.
Case "n = S n'".
simpl.
intros m H.
destruct m as [| m'].
SCase "m = 0".
inversion H.
SCase "m = S m'".
simpl in H.
rewrite <- plus_n_Sm in H.
rewrite <- plus_n_Sm in H.
inversion H.
apply IHn' in H1.
apply f_equal.
apply H1.
Qed.
(** [] *)
(* ###################################################### *)
(** * Varying the Induction Hypothesis *)
(** Sometimes it is important to control the exact form of the
induction hypothesis when carrying out inductive proofs in Coq.
In particular, we need to be careful about which of the
assumptions we move (using [intros]) from the goal to the context
before invoking the [induction] tactic. For example, suppose
we want to show that the [double] function is injective -- i.e.,
that it always maps different arguments to different results:
Theorem double_injective: forall n m, double n = double m -> n = m.
The way we _start_ this proof is a little bit delicate: if we
begin it with
intros n. induction n.
]]
all is well. But if we begin it with
intros n m. induction n.
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'". apply f_equal.
(* Here we are stuck. The induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the goal is not provable. *)
Abort.
(** What went wrong? *)
(** The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context --
intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we know
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.) *)
(** To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for _every_ [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
SCase "m = O".
(* The 0 case is trivial *)
inversion eq.
SCase "m = S m'".
apply f_equal.
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
apply IHn'. inversion eq. reflexivity. Qed.
(** What this teaches us is that we need to be careful about using
induction to try to prove something too specific: If we're proving
a property of [n] and [m] by induction on [n], we may need to
leave [m] generic. *)
(** The proof of this theorem (left as an exercise) has to be treated similarly: *)
(** **** Exercise: 2 stars (beq_nat_true) *)
Theorem beq_nat_true : forall n m,
beq_nat n m = true -> n = m.
Proof.
intros n.
induction n as [| n'].
Case "n = 0".
intros m H.
destruct m.
SCase "m = 0".
reflexivity.
SCase "m > 0".
inversion H.
Case "n = S n'".
intros m H.
destruct m.
SCase "m = 0".
inversion H.
SCase "m > 0".
simpl in H.
apply f_equal.
apply IHn'.
apply H.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (beq_nat_true_informal) *)
(** Give a careful informal proof of [beq_nat_true], being as explicit
as possible about quantifiers. *)
(* FILL IN HERE *)
(** [] *)
(** The strategy of doing fewer [intros] before an [induction] doesn't
always work directly; sometimes a little _rearrangement_ of
quantified variables is needed. Suppose, for example, that we
wanted to prove [double_injective] by induction on [m] instead of
[n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
(* Stuck again here, just like before. *)
Abort.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) *)
(** What can we do about this? One possibility is to rewrite the
statement of the lemma so that [m] is quantified before [n]. This
will work, but it's not nice: We don't want to have to mangle the
statements of lemmas to fit the needs of a particular strategy for
proving them -- we want to state them in the most clear and
natural way. *)
(** What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
apply IHm'. inversion eq. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that
the proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [double n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** Here's another illustration of [inversion] and using an
appropriately general induction hypothesis. This is a slightly
roundabout way of stating a fact that we have already proved
above. The extra equalities force us to do a little more
equational reasoning and exercise some of the tactics we've seen
recently. *)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l'].
Case "l = []".
intros n eq. rewrite <- eq. reflexivity.
Case "l = v' :: l'".
intros n eq. simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. apply IHl'. inversion eq. reflexivity. Qed.
(** It might be tempting to start proving the above theorem
by introducing [n] and [eq] at the outset. However, this leads
to an induction hypothesis that is not strong enough. Compare
the above to the following (aborted) attempt: *)
Theorem length_snoc_bad : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l n eq. induction l as [| v' l'].
Case "l = []".
rewrite <- eq. reflexivity.
Case "l = v' :: l'".
simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. Abort. (* apply IHl'. *) (* The IH doesn't apply! *)
(** As in the double examples, the problem is that by
introducing [n] before doing induction on [l], the induction
hypothesis is specialized to one particular natural number, namely
[n]. In the induction case, however, we need to be able to use
the induction hypothesis on some other natural number [n'].
Retaining the more general form of the induction hypothesis thus
gives us more flexibility.
In general, a good rule of thumb is to make the induction hypothesis
as general as possible. *)
(** **** Exercise: 3 stars (gen_dep_practice) *)
(** Prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index n l = None.
Proof.
intros n X l.
generalize dependent n.
induction l as [| x l'].
Case "l = []".
intros n H.
destruct n.
SCase "n = 0".
reflexivity.
SCase "n > 0".
inversion H.
Case "l = x::l'".
intros n H.
destruct n as [| n'].
SCase "n = 0".
inversion H.
SCase "n > 0".
simpl.
apply IHl'.
inversion H.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index n l = None].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (gen_dep_practice_more) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
intros n X v l.
generalize dependent n.
induction l as [| x l'].
Case "l = []".
intros n H.
destruct n.
SCase "n = 0". reflexivity.
SCase "n > 0". inversion H.
Case "l = x::l'".
intros n H.
destruct n as [| n'].
SCase "n = 0".
inversion H.
SCase "n = S n'".
simpl.
apply f_equal.
apply IHl'.
simpl in H.
inversion H.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]
from [Lists]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof.
intros X l1.
induction l1 as [| x1 l1'].
Case "l1 = []".
intros l2 x n H.
destruct n as [| n'].
SCase "n = 0".
inversion H.
SCase "n = S n'".
simpl.
apply f_equal.
simpl in H.
inversion H.
reflexivity.
Case "l1 = x1::l1'".
intros l2 x n H.
destruct n as [| n'].
SCase "n = 0".
inversion H.
SCase "n = S n'".
simpl.
apply f_equal.
apply IHl1' with x.
simpl in H.
inversion H.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
Theorem app_length_cons_eq : forall (X: Type) (l1 l2: list X) (x: X),
length (l1 ++ (x::l2)) = S (length (l1 ++ l2)).
Proof.
intros X l1.
induction l1 as [| x1 l1'].
Case "l1 = []".
intros l2 x.
reflexivity.
Case "l1 = x1::l1'".
intros l2 x.
simpl.
apply f_equal.
apply IHl1'.
Qed.
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
intros X n l.
generalize dependent n.
induction l as [| x l'].
Case "l = []".
simpl.
intros n H.
rewrite <- H.
reflexivity.
Case "l = x::l'".
simpl.
intros n H.
rewrite app_length_cons_eq.
destruct n as [| n'].
SCase "n = 0".
inversion H.
SCase "n = S n'".
simpl.
rewrite <- plus_n_Sm.
apply f_equal.
apply f_equal.
apply IHl'.
inversion H.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (double_induction) *)
(** Prove the following principle of induction over two naturals. *)
Theorem double_induction: forall (P : nat -> nat -> Prop),
P 0 0 ->
(forall m, P m 0 -> P (S m) 0) ->
(forall n, P 0 n -> P 0 (S n)) ->
(forall m n, P m n -> P (S m) (S n)) ->
forall m n, P m n.
Proof.
intros P H1 H2 H3 H4.
induction m as [| m'].
Case "m = 0".
induction n as [| n'].
SCase "n = 0".
apply H1.
SCase "n = S n'".
apply H3.
apply IHn'.
Case "m = S m'".
induction n as [| n'].
SCase "n = 0".
apply H2.
apply IHm'.
SCase "n = S n'".
apply H4.
apply IHm'.
Qed.
(** [] *)
(* ###################################################### *)
(** * Using [destruct] on Compound Expressions *)
(** We have seen many examples where the [destruct] tactic is
used to perform case analysis of the value of some variable. But
sometimes we need to reason by cases on the result of some
_expression_. We can also do this with [destruct].
Here are some examples: *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
Case "beq_nat n 3 = true". reflexivity.
Case "beq_nat n 3 = false". destruct (beq_nat n 5).
SCase "beq_nat n 5 = true". reflexivity.
SCase "beq_nat n 5 = false". reflexivity. Qed.
(** After unfolding [sillyfun] in the above proof, we find that
we are stuck on [if (beq_nat n 3) then ... else ...]. Well,
either [n] is equal to [3] or it isn't, so we use [destruct
(beq_nat n 3)] to let us reason about the two cases.
In general, the [destruct] tactic can be used to perform case
analysis of the results of arbitrary computations. If [e] is an
expression whose type is some inductively defined type [T], then,
for each constructor [c] of [T], [destruct e] generates a subgoal
in which all occurrences of [e] (in the goal and in the context)
are replaced by [c].
*)
(** **** Exercise: 1 star (override_shadow) *)
Theorem override_shadow : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof.
intros X x1 x2 k1 k2 f.
unfold override.
destruct (beq_nat k1 k2).
Case "k1 = k2". reflexivity.
Case "k1 <> k2". reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (combine_split) *)
(** Complete the proof below *)
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) ->
combine l1 l2 = l.
Proof.
intros X Y l.
induction l as [| p l'].
Case "l = []".
intros l1 l2 H.
inversion H.
reflexivity.
Case "l = p::l'".
destruct p as [x y].
intros l1 l2 H.
simpl in H.
destruct (split l') as [xs ys].
inversion H.
simpl.
apply f_equal.
apply IHl'.
reflexivity.
Qed.
(** [] *)
(** Sometimes, doing a [destruct] on a compound expression (a
non-variable) will erase information we need to complete a proof. *)
(** For example, suppose
we define a function [sillyfun1] like this: *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(** And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* stuck... *)
Abort.
(** We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep some
memory of this expression and how it was destructed, because we
need to be able to reason that since, in this branch of the case
analysis, [beq_nat n 3 = true], it must be that [n = 3], from
which it follows that [n] is odd.
What we would really like is to substitute away all existing
occurences of [beq_nat n 3], but at the same time add an equation
to the context that records which case we are in. The [eqn:]
qualifier allows us to introduce such an equation (with whatever
name we choose). *)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3) eqn:Heqe3.
(* Now we have the same state as at the point where we got stuck
above, except that the context contains an extra equality
assumption, which is exactly what we need to make progress. *)
Case "e3 = true". apply beq_nat_true in Heqe3.
rewrite -> Heqe3. reflexivity.
Case "e3 = false".
(* When we come to the second equality test in the body of the
function we are reasoning about, we can use [eqn:] again in the
same way, allow us to finish the proof. *)
destruct (beq_nat n 5) eqn:Heqe5.
SCase "e5 = true".
apply beq_nat_true in Heqe5.
rewrite -> Heqe5. reflexivity.
SCase "e5 = false". inversion eq. Qed.
(** **** Exercise: 2 stars (destruct_eqn_practice) *)
Theorem bool_fn_applied_thrice :
forall (f : bool -> bool) (b : bool),
f (f (f b)) = f b.
Proof.
intros f b.
destruct (f b) eqn: fb.
Case "f b = true".
destruct b.
SCase "b = true".
rewrite fb.
rewrite fb.
reflexivity.
SCase "b = false".
destruct (f true) eqn:ftrue.
apply ftrue.
apply fb.
Case "f b = false".
destruct b.
SCase "b = true".
destruct (f false) eqn:ffalse.
apply fb.
apply ffalse.
SCase "b = false".
rewrite fb.
apply fb.
Qed.
(** [] *)
(** **** Exercise: 2 stars (override_same) *)
Theorem override_same : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override f k1 x1) k2 = f k2.
Proof.
intros X x1 k1 k2 f H.
unfold override.
destruct (beq_nat k1 k2) eqn:k1k2.
Case "k1 = k2".
apply beq_nat_true in k1k2.
rewrite k1k2 in H.
symmetry.
apply H.
Case "k1 <> k2".
reflexivity.
Qed.
(** [] *)
(* ################################################################## *)
(** * Review *)
(** We've now seen a bunch of Coq's fundamental tactics. We'll
introduce a few more as we go along through the coming lectures,
and later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [symmetry]:
changes a goal of the form [t=u] into [u=t]
- [symmetry in H]:
changes a hypothesis of the form [t=u] into [u=t]
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [destruct... eqn:...]:
specify the name of an equation to be added to the context,
recording the result of the case analysis
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
- [generalize dependent x]:
move the variable [x] (and anything else that depends on it)
from the context back to an explicit hypothesis in the goal
formula
*)
(* ###################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (beq_nat_sym) *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof.
intros n.
induction n as [| n'].
Case "n = 0".
intros m.
induction m as [| m'].
SCase "m = 0".
reflexivity.
SCase "m = S m'".
reflexivity.
Case "n = S n'".
intros m.
induction m as [| m'].
SCase "m = 0".
reflexivity.
SCase "m = S m'".
simpl.
apply IHn'.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (beq_nat_sym_informal) *)
(** Give an informal proof of this lemma that corresponds to your
formal proof above:
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (beq_nat_trans) *)
Theorem beq_nat_trans : forall n m p,
beq_nat n m = true ->
beq_nat m p = true ->
beq_nat n p = true.
Proof.
intros n m p H1 H2.
apply beq_nat_true in H1.
apply beq_nat_true in H2.
rewrite <- H1 in H2.
rewrite H2.
rewrite <- beq_nat_refl.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (split_combine) *)
(** We have just proven that for all lists of pairs, [combine] is the
inverse of [split]. How would you formalize the statement that
[split] is the inverse of [combine]? When is this property true?
Complete the definition of [split_combine_statement] below with a
property that states that [split] is the inverse of
[combine]. Then, prove that the property holds. (Be sure to leave
your induction hypothesis general by not doing [intros] on more
things than necessary. Hint: what property do you need of [l1]
and [l2] for [split] [combine l1 l2 = (l1,l2)] to be true?) *)
Definition split_combine_statement : Prop :=
forall (X: Type) (l1 l2: list X), length l1 = length l2 -> split (combine l1 l2) = (l1, l2).
Lemma length_0 : forall (X: Type) (l: list X), length l = 0 -> l = [].
Proof.
intros X l H.
induction l as [| x l'].
reflexivity.
inversion H.
Qed.
Theorem split_combine : split_combine_statement.
Proof.
unfold split_combine_statement.
intros X l1.
induction l1 as [| x1 l1'].
Case "l1 = []".
simpl.
intros l2 H.
symmetry in H.
apply length_0 in H.
rewrite H.
reflexivity.
Case "l1 = x1::l1'".
intros l2 H.
induction l2 as [| x2 l2'].
SCase "l2 = []".
inversion H.
SCase "l2 = x2::l2'".
simpl in H.
inversion H.
apply IHl1' in H1.
simpl.
destruct (split (combine l1' l2')) as [xs ys].
inversion H1.
apply f_equal.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (override_permute) *)
Theorem override_permute : forall (X:Type) x1 x2 k1 k2 k3 (f : nat->X),
beq_nat k2 k1 = false ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof.
intros X x1 x2 k1 k2 k3 f H.
unfold override.
destruct (beq_nat k1 k3) eqn:k1k3.
Case "k1 = k3".
apply beq_nat_true in k1k3.
rewrite k1k3 in H.
rewrite H.
reflexivity.
Case "k1 <> k3".
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (filter_exercise) *)
(** This one is a bit challenging. Pay attention to the form of your IH. *)
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
intros X test x l.
induction l as [| x' l'].
Case "l = []".
simpl.
intros lf H.
inversion H.
Case "l = x'::l'".
intros lf H.
simpl in H.
destruct (test x') eqn:testx'.
SCase "test x' = true".
inversion H.
rewrite <- H1.
apply testx'.
SCase "test x' = false".
apply IHl' with lf.
apply H.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (forall_exists_challenge) *)
(** Define two recursive [Fixpoints], [forallb] and [existsb]. The
first checks whether every element in a list satisfies a given
predicate:
forallb oddb [1;3;5;7;9] = true
forallb negb [false;false] = true
forallb evenb [0;2;4;5] = false
forallb (beq_nat 5) [] = true
The second checks whether there exists an element in the list that
satisfies a given predicate:
existsb (beq_nat 5) [0;2;3;6] = false
existsb (andb true) [true;true;false] = true
existsb oddb [1;0;0;0;0;3] = true
existsb evenb [] = false
Next, define a _nonrecursive_ version of [existsb] -- call it
[existsb'] -- using [forallb] and [negb].
Prove theorem [existsb_existsb'] that [existsb'] and [existsb] have
the same behavior.
*)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 16:01:37 -0500 (Wed, 31 Dec 2014) $ *)
|
`timescale 1ns / 1ps
// Copyright (c) 2018 Cees Wolfs
//
// Module: int_controller
// Project: Ceespu
// Description: The interrupt controller, that can interrupt the processor if something happens
module intr_controller(
input I_clk,
input I_rst,
input [2:0] I_intr_rq,
input I_intr_ack,
output reg O_intr = 0,
output reg [1:0] O_intr_vector = 0
);
reg wait_state = 0;
reg [2:0] intr_rq = 0;
always @(posedge I_clk) begin
if (I_intr_rq[1]) begin
intr_rq[1] <= 1;
end
if (I_intr_rq[2]) begin
intr_rq[2] <= 1;
end
if (wait_state) begin
if (I_intr_ack) begin
wait_state <= 0;
intr_rq[O_intr_vector] <= 0;
O_intr <= 0;
end
end
else begin
if(intr_rq[1]) begin
O_intr <= 1;
O_intr_vector <= 1;
wait_state <= 1;
$display("intr_contr 1 is called vector = %d", O_intr_vector);
end
else if (intr_rq[2]) begin
O_intr <= 1;
O_intr_vector <= 2;
wait_state <= 1;
$display("intr_contr 2 is called vector = %d", O_intr_vector);
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:29:01 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_sim_netlist.v
// Design : system_inverter_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_0_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_0_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_0_V
`define SKY130_FD_SC_LP__A311O_0_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311o_0 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311o_0 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_0_V
|
/*
* Titor - Barrel Processor - Task-dedicated register bank
* Copyright (C) 2012,2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Register_Bank
`else
`define INC_Register_Bank
`timescale 1 ns / 100 ps
// Register module
module Register_Bank (
// memory interface
din,
dout,
address,
size,
enable,
read_write,
// register inputs
PC0_next,
PC1_next,
PC2_next,
MSR0_next,
MSR1_next,
MSR2_next,
HMULT_next,
result,
result_reg,
result_valid,
// register outputs
reg0,
reg1,
reg2,
reg3,
PC0,
PC1,
PC2,
MSR0,
MSR1,
MSR2,
HMULT,
// control
sel0,
sel1,
sel2,
sel3,
state,
clk,
reset
);
`include "definition/Definition.v"
parameter REGWSTATE_HMULT = 0; // state to write HMULT
parameter REGWSTATE_GEN = 0; // state to write any general registers
parameter REGWSTATE_SFR = 0; // state to write all SFRs
// memory interface
input [WORD-1:0] din;
input [WORD-1:0] address;
output reg [WORD-1:0] dout;
input enable;
input read_write;
input [LOGWORDBYTE-1:0] size;
// register inputs
input [WORD-1:0] PC0_next;
input [WORD-1:0] PC1_next;
input [WORD-1:0] PC2_next;
input [WORD-1:0] MSR0_next;
input [WORD-1:0] MSR1_next;
input [WORD-1:0] MSR2_next;
input [WORD-1:0] HMULT_next;
input [WORD-1:0] result;
input [WORD-1:0] result_reg;
input result_valid;
// register outputs
output reg [WORD-1:0] reg0;
output reg [WORD-1:0] reg1;
output reg [WORD-1:0] reg2;
output reg [WORD-1:0] reg3;
output reg [WORD-1:0] PC0;
output reg [WORD-1:0] PC1;
output reg [WORD-1:0] PC2;
output reg [WORD-1:0] MSR0;
output reg [WORD-1:0] MSR1;
output reg [WORD-1:0] MSR2;
output reg [WORD-1:0] HMULT;
// control
input [WIDTH_FIELD0-1:0] sel0;
input [WIDTH_FIELD1-1:0] sel1;
input [WIDTH_FIELD2-1:0] sel2;
input [WIDTH_SHAMT_R-1:0] sel3;
input [WORD-1:0] state;
input clk;
input reset;
wire [WORD-1:0] value [TOTAL_SPACE-1:0]; // register value outputs
reg active;
reg unpacked_sel_memory [REG_SPACE-1:0];
always @(*) begin
dout <= value[address];
reg0 <= value[sel0];
reg1 <= value[sel1];
reg2 <= value[sel2];
reg3 <= value[sel3];
PC0 <= value[SFR_PC0];
PC1 <= value[SFR_PC1];
PC2 <= value[SFR_PC2];
MSR0 <= value[SFR_MSR0];
MSR1 <= value[SFR_MSR1];
MSR2 <= value[SFR_MSR2];
HMULT <= value[REG_HMULT];
end
genvar i;
generate
for(i=0; i<REG_SPACE; i=i+1) begin : REGSEL
always @(*) begin
unpacked_sel_memory[i] <= ((address/WORDBYTE) == i) && (read_write == WRITE) && enable;
end
end
endgenerate
// register set ****************************************************************
// Zero register
Register X0(
.value (value[REG_Z] ),
.memory (0 ),
.datapath (0 ),
.sel_memory (0 ),
.sel_datapath (0 ),
.clk (clk ),
.reset (reset )
);
// Higher Multiplication register
Register X1(
.value (value[REG_HMULT] ),
.memory (din ),
.datapath (HMULT_next ),
.sel_memory (unpacked_sel_memory[REG_HMULT] ),
.sel_datapath ((state == REGWSTATE_HMULT) ),
.clk (clk ),
.reset (reset )
);
// "Real" general purpose registers
generate
for(i=GENERAL_OFFSET; i<GENERAL_SPACE; i=i+1) begin : REGGENERAL
Register X(
.value (value[i] ),
.memory (din ),
.datapath (result ),
.sel_memory (unpacked_sel_memory[i] ),
.sel_datapath ((state == REGWSTATE_GEN) && (result_reg == i) && result_valid ), // REGWRITE_BROADSIDE
.clk (clk ),
.reset (reset )
);
end
endgenerate
// PC*
Register X16(
.value (value[SFR_PC0] ),
.memory (din ),
.datapath (PC0_next ),
.sel_memory (unpacked_sel_memory[SFR_PC0] ),
.sel_datapath ((state == REGWSTATE_SFR) ), // REGWRITE_BROADSIDE
.clk (clk ),
.reset (reset )
);
Register X17(
.value (value[SFR_PC1] ),
.memory (din ),
.datapath (PC1_next ),
.sel_memory (unpacked_sel_memory[SFR_PC1] ),
.sel_datapath ((state == REGWSTATE_SFR) ),
.clk (clk ),
.reset (reset )
);
Register X18(
.value (value[SFR_PC2] ),
.memory (din ),
.datapath (PC2_next ),
.sel_memory (unpacked_sel_memory[SFR_PC2] ),
.sel_datapath ((state == REGWSTATE_SFR) ),
.clk (clk ),
.reset (reset )
);
// MSR*
Register X19(
.value (value[SFR_MSR0] ),
.memory (din ),
.datapath (MSR0_next ),
.sel_memory (unpacked_sel_memory[SFR_MSR0] ),
.sel_datapath ((state == REGWSTATE_SFR) ), // REGWRITE_BROADSIDE
.clk (clk ),
.reset (reset )
);
Register X20(
.value (value[SFR_MSR1] ),
.memory (din ),
.datapath (MSR1_next ),
.sel_memory (unpacked_sel_memory[SFR_MSR1] ),
.sel_datapath ((state == REGWSTATE_SFR) ),
.clk (clk ),
.reset (reset )
);
Register X21(
.value (value[SFR_MSR2] ),
.memory (din ),
.datapath (MSR2_next ),
.sel_memory (unpacked_sel_memory[SFR_MSR2] ),
.sel_datapath ((state == REGWSTATE_SFR) ),
.clk (clk ),
.reset (reset )
);
endmodule
`endif
|
/**
*@file tai_ecc.v
*@brief Automatically detect error of TAI counter
*@author LUAN Yuezhen
*@date Origin 2016.11.17
*@tab Tab size = 4 spaces
*/
module tai_ecc(
input clk,
input rst_n,
input pps,
input [63 : 0] tai_sec_1,
input [63 : 0] tai_sec_2,
input [63 : 0] tai_sec_3,
output [63 : 0] tai_sec_correct,
output [ 7 : 0] tai_cnt_err_1,
output [ 7 : 0] tai_cnt_err_2,
output [ 7 : 0] tai_cnt_err_3,
output reg fault_interrupt
);
localparam IDLE = 5'b0;
localparam WAIT_PPS_RISE = 5'b1;
localparam GET_DATA = 5'b10;
localparam CMP_DATA = 5'b100;
localparam ERROR_CNT = 5'b1000;
localparam WAIT_PPS_FALL = 5'b10000;
reg [ 4 : 0] corr_state;
reg [ 4 : 0] corr_next_state;
reg [63 : 0] tai_sec_1_hold;
reg [63 : 0] tai_sec_2_hold;
reg [63 : 0] tai_sec_3_hold;
reg [63 : 0] tai_most_probably_fine;
reg [63 : 0] last_sec;
reg [ 7 : 0] t1_err;
reg [ 7 : 0] t2_err;
reg [ 7 : 0] t3_err;
reg t1_equal_t2;
reg t1_equal_t3;
reg t2_equal_t3;
assign tai_sec_correct = tai_most_probably_fine;
assign tai_cnt_err_1 = t1_err;
assign tai_cnt_err_2 = t2_err;
assign tai_cnt_err_3 = t3_err;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
tai_most_probably_fine <= 64'b0;
end
else begin
tai_most_probably_fine <= ((tai_sec_1 & tai_sec_2 & tai_sec_3) |
(( ~tai_sec_1) & tai_sec_2 & tai_sec_3) |
( tai_sec_1 & (~tai_sec_2) & tai_sec_3) |
( tai_sec_1 & tai_sec_2 & (~tai_sec_3)));
end
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
corr_state <= 0;
end
else begin
corr_state <= corr_next_state;
end
end
always @ (*)
begin
case (corr_state)
IDLE : begin
corr_next_state = WAIT_PPS_RISE;
end
WAIT_PPS_RISE : begin
if (pps) begin
corr_next_state = GET_DATA;
end
else begin
corr_next_state = WAIT_PPS_RISE;
end
end
GET_DATA : begin
corr_next_state = CMP_DATA;
end
CMP_DATA : begin
corr_next_state = ERROR_CNT;
end
ERROR_CNT : begin
corr_next_state = WAIT_PPS_FALL;
end
WAIT_PPS_FALL : begin
if (!pps) begin
corr_next_state = WAIT_PPS_RISE;
end
else begin
corr_next_state = WAIT_PPS_FALL;
end
end
default : begin
corr_next_state = IDLE;
end
endcase
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
tai_sec_1_hold <= 64'b0;
tai_sec_2_hold <= 64'b0;
tai_sec_3_hold <= 64'b0;
t1_equal_t2 <= 1'b0;
t1_equal_t3 <= 1'b0;
t2_equal_t3 <= 1'b0;
fault_interrupt <= 1'b0;
t1_err <= 8'b0;
t2_err <= 8'b0;
t3_err <= 8'b0;
end
else begin
case (corr_state)
IDLE : begin
end
WAIT_PPS_RISE : begin
end
GET_DATA : begin
tai_sec_1_hold <= tai_sec_1;
tai_sec_2_hold <= tai_sec_2;
tai_sec_3_hold <= tai_sec_3;
end
CMP_DATA : begin
t1_equal_t2 <= (tai_sec_1_hold == tai_sec_2_hold) ? 1'b1 : 1'b0;
t1_equal_t3 <= (tai_sec_1_hold == tai_sec_3_hold) ? 1'b1 : 1'b0;
t2_equal_t3 <= (tai_sec_2_hold == tai_sec_3_hold) ? 1'b1 : 1'b0;
end
ERROR_CNT : begin
casez ({t1_equal_t2, t1_equal_t3, t2_equal_t3})
3'b11? : begin
fault_interrupt <= 1'b0;
end
3'b10? : begin
t3_err <= t3_err + 1'b1;
fault_interrupt <= 1'b1;
end
3'b01? : begin
t2_err <= t2_err + 1'b1;
fault_interrupt <= 1'b1;
end
3'b001 : begin
t1_err <= t1_err + 1'b1;
fault_interrupt <= 1'b1;
end
3'b000 : begin
fault_interrupt <= 1'b1;
end
endcase
end
WAIT_PPS_FALL : begin
end
endcase
end
end
endmodule
|
// the clock is manually controlled to set the inputs correctly
module jfsmMealyWithOverlapTb;
wire dataout;
reg clock, reset, datain;
jfsmMealyWithOverlap jfsmM(dataout, clock, reset, datain);
initial
begin
reset = 1; datain = 0;
clock = 1; #5; clock = 0; #5;
reset = 0;
clock = 1; #5; clock = 0; #5;
$display("Starting input sequence");
// we now make the 5 transistions and check the dataout to see if it is detected
datain = 1; clock = 1; #5; clock = 0; #5;
datain = 1; clock = 1; #5; clock = 0; #5;
datain = 1; clock = 1; #5; clock = 0; #5;
datain = 0; clock = 1; #5; clock = 0; #5;
datain = 1; clock = 1; #5; clock = 0; #5;
if ( dataout === 1 )
$display("PASS %b", dataout);
else
$display("FAIL %b", dataout);
// we now make the ONLY 4 transistions and check the dataout to see if it is detected
//datain = 1; clock = 1; #5; clock = 0; #5;
datain = 1; clock = 1; #5; clock = 0; #5;
datain = 1; clock = 1; #5; clock = 0; #5;
datain = 0; clock = 1; #5; clock = 0; #5;
datain = 1; clock = 1; #5; clock = 0; #5;
if ( dataout === 1 )
$display("PASS %b", dataout);
else
$display("FAIL %b", dataout);
// we now make a wrongsequence the 5 transistions and check the dataout to see if it is detected
datain = 0; clock = 1; #5; clock = 0; #5;
datain = 0; clock = 1; #5; clock = 0; #5;
if ( dataout === 0 )
$display("PASS %b", dataout);
else
$display("FAIL %b", dataout);
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clocker.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.0 Build 156 04/24/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clocker (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [4:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 25000,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1000,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clocker",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "25000"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1000"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.002000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.050000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.40000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clocker.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25000"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1000"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: GEN_FILE: TYPE_NORMAL clocker.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clocker.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clocker.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clocker.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clocker.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clocker_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clocker_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1P_TB_V
`define SKY130_FD_SC_HDLL__INPUTISO1P_TB_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inputiso1p.v"
module top();
// Inputs are registered
reg A;
reg SLEEP;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__inputiso1p dut (.A(A), .SLEEP(SLEEP), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1P_TB_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: asyn_256_134.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module asyn_256_134 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw);
input aclr;
input [133:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [133:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [133:0] sub_wire0;
wire [7:0] sub_wire1;
wire [133:0] q = sub_wire0[133:0];
wire [7:0] wrusedw = sub_wire1[7:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.wrusedw (sub_wire1),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 134,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "134"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "134"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "134"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 134 0 INPUT NODEFVAL "data[133..0]"
// Retrieval info: USED_PORT: q 0 0 134 0 OUTPUT NODEFVAL "q[133..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL "wrusedw[7..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 134 0 data 0 0 134 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 134 0 @q 0 0 134 0
// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_134.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_134.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_134.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_134.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_134_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_134_bb.v FALSE
|
module wr_port_mux_9to1
(/*AUTOARG*/
// Outputs
muxed_port_wr_en, muxed_port_wr_mask, muxed_port_wr_addr,
muxed_port_wr_data,
// Inputs
wr_port_select, port0_wr_en, port0_wr_mask, port0_wr_addr,
port0_wr_data, port1_wr_en, port1_wr_mask, port1_wr_addr,
port1_wr_data, port2_wr_en, port2_wr_mask, port2_wr_addr,
port2_wr_data, port3_wr_en, port3_wr_mask, port3_wr_addr,
port3_wr_data, port4_wr_en, port4_wr_mask, port4_wr_addr,
port4_wr_data, port5_wr_en, port5_wr_mask, port5_wr_addr,
port5_wr_data, port6_wr_en, port6_wr_mask, port6_wr_addr,
port6_wr_data, port7_wr_en, port7_wr_mask, port7_wr_addr,
port7_wr_data, port8_wr_en, port8_wr_mask, port8_wr_addr,
port8_wr_data
);
output[3:0] muxed_port_wr_en;
output [63:0] muxed_port_wr_mask;
output [9:0] muxed_port_wr_addr;
// change output port width
output [2047:0] muxed_port_wr_data;
input [15:0] wr_port_select;
input[3:0] port0_wr_en;
input [63:0] port0_wr_mask;
input [9:0] port0_wr_addr;
input [2047:0] port0_wr_data;
input[3:0] port1_wr_en;
input [63:0] port1_wr_mask;
input [9:0] port1_wr_addr;
input [2047:0] port1_wr_data;
input[3:0] port2_wr_en;
input [63:0] port2_wr_mask;
input [9:0] port2_wr_addr;
input [2047:0] port2_wr_data;
input[3:0] port3_wr_en;
input [63:0] port3_wr_mask;
input [9:0] port3_wr_addr;
input [2047:0] port3_wr_data;
input[3:0] port4_wr_en;
input [63:0] port4_wr_mask;
input [9:0] port4_wr_addr;
input [2047:0] port4_wr_data;
input[3:0] port5_wr_en;
input [63:0] port5_wr_mask;
input [9:0] port5_wr_addr;
input [2047:0] port5_wr_data;
input[3:0] port6_wr_en;
input [63:0] port6_wr_mask;
input [9:0] port6_wr_addr;
input [2047:0] port6_wr_data;
input[3:0] port7_wr_en;
input [63:0] port7_wr_mask;
input [9:0] port7_wr_addr;
input [2047:0] port7_wr_data;
input[3:0] port8_wr_en;
input [63:0] port8_wr_mask;
input [9:0] port8_wr_addr;
// S: change output width
input [2047:0] port8_wr_data;
/*
wire [2047:0] port0_wr_data_i, port1_wr_data_i, port2_wr_data_i,
port3_wr_data_i, port4_wr_data_i, port5_wr_data_i,
port6_wr_data_i, port7_wr_data_i;
assign port0_wr_data_i =
*/
/*
genvar i;
generate
for (i = 0; i<64; i=i+1) begin
assign port0_wr_data_i[i*32+:32] = {port0_wr_data[i*32+:32]};
assign port1_wr_data_i[i*32+:32] = {port1_wr_data[i*32+:32]};
assign port2_wr_data_i[i*32+:32] = {port2_wr_data[i*32+:32]};
assign port3_wr_data_i[i*32+:32] = {port3_wr_data[i*32+:32]};
assign port4_wr_data_i[i*128+:128] = {port4_wr_data[i*32+:32]};
assign port5_wr_data_i[i*128+:128] = {port5_wr_data[i*32+:32]};
assign port6_wr_data_i[i*128+:128] = {port6_wr_data[i*32+:32]};
assign port7_wr_data_i[i*128+:128] = {port7_wr_data[i*32+:32]};
end
endgenerate
*/
reg [3:0] muxed_port_wr_en;
reg [63:0] muxed_port_wr_mask;
reg [9:0] muxed_port_wr_addr;
reg [2047:0] muxed_port_wr_data;
always @ (*) begin
casex(wr_port_select)
16'h0001:
begin
muxed_port_wr_en <= port0_wr_en;
muxed_port_wr_mask <= port0_wr_mask;
muxed_port_wr_addr <= port0_wr_addr;
muxed_port_wr_data <= port0_wr_data;
end
16'h0002:
begin
muxed_port_wr_en <= port1_wr_en;
muxed_port_wr_mask <= port1_wr_mask;
muxed_port_wr_addr <= port1_wr_addr;
muxed_port_wr_data <= port1_wr_data;
end
16'h0004:
begin
muxed_port_wr_en <= port2_wr_en;
muxed_port_wr_mask <= port2_wr_mask;
muxed_port_wr_addr <= port2_wr_addr;
muxed_port_wr_data <= port2_wr_data;
end
16'h0008:
begin
muxed_port_wr_en <= port3_wr_en;
muxed_port_wr_mask <= port3_wr_mask;
muxed_port_wr_addr <= port3_wr_addr;
muxed_port_wr_data <= port3_wr_data;
end
16'h0010:
begin
muxed_port_wr_en <= port4_wr_en;
muxed_port_wr_mask <= port4_wr_mask;
muxed_port_wr_addr <= port4_wr_addr;
muxed_port_wr_data <= port4_wr_data;
end
16'h0020:
begin
muxed_port_wr_en <= port5_wr_en;
muxed_port_wr_mask <= port5_wr_mask;
muxed_port_wr_addr <= port5_wr_addr;
muxed_port_wr_data <= port5_wr_data;
end
16'h0040:
begin
muxed_port_wr_en <= port6_wr_en;
muxed_port_wr_mask <= port6_wr_mask;
muxed_port_wr_addr <= port6_wr_addr;
muxed_port_wr_data <= port6_wr_data;
end
16'h0080:
begin
muxed_port_wr_en <= port7_wr_en;
muxed_port_wr_mask <= port7_wr_mask;
muxed_port_wr_addr <= port7_wr_addr;
muxed_port_wr_data <= port7_wr_data;
end
16'h0100:
begin
muxed_port_wr_en <= port8_wr_en;
muxed_port_wr_mask <= port8_wr_mask;
muxed_port_wr_addr <= port8_wr_addr;
muxed_port_wr_data <= port8_wr_data;
end
16'b0000:
begin
muxed_port_wr_en <= 4'd0;
muxed_port_wr_mask <= 64'b0;
muxed_port_wr_addr <= {10{1'bx}};
// S: change from 8k to 2k
muxed_port_wr_data <= {2048{1'bx}};
end
default:
begin
muxed_port_wr_en <= 4'd0;
muxed_port_wr_mask <= {64{1'b0}};
muxed_port_wr_addr <= {10{1'bx}};
// S: change from 8k to 2k
muxed_port_wr_data <= {2048{1'bx}};
end
endcase
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:19:47 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemWinner/MemWinner_stub.v
// Design : MemWinner
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dist_mem_gen_v8_0,Vivado 2014.4" *)
module MemWinner(a, clk, spo)
/* synthesis syn_black_box black_box_pad_pin="a[4:0],clk,spo[107:0]" */;
input [4:0]a;
input clk;
output [107:0]spo;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_dmac #(
parameter ID = 0,
parameter DMA_DATA_WIDTH_SRC = 64,
parameter DMA_DATA_WIDTH_DEST = 64,
parameter DMA_LENGTH_WIDTH = 24,
parameter DMA_2D_TRANSFER = 0,
parameter ASYNC_CLK_REQ_SRC = 1,
parameter ASYNC_CLK_SRC_DEST = 1,
parameter ASYNC_CLK_DEST_REQ = 1,
parameter AXI_SLICE_DEST = 0,
parameter AXI_SLICE_SRC = 0,
parameter SYNC_TRANSFER_START = 0,
parameter CYCLIC = 1,
parameter DMA_AXI_PROTOCOL_DEST = 0,
parameter DMA_AXI_PROTOCOL_SRC = 0,
parameter DMA_TYPE_DEST = 0,
parameter DMA_TYPE_SRC = 2,
parameter DMA_AXI_ADDR_WIDTH = 32,
parameter MAX_BYTES_PER_BURST = 128,
parameter FIFO_SIZE = 8, // In bursts
parameter AXI_ID_WIDTH_SRC = 1,
parameter AXI_ID_WIDTH_DEST = 1,
parameter DISABLE_DEBUG_REGISTERS = 0,
parameter ENABLE_DIAGNOSTICS_IF = 0)(
// Slave AXI interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [11:0] s_axi_awaddr,
output s_axi_awready,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [11:0] s_axi_araddr,
output s_axi_arready,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
// Interrupt
output irq,
// Master AXI interface
input m_dest_axi_aclk,
input m_dest_axi_aresetn,
// Write address
output [DMA_AXI_ADDR_WIDTH-1:0] m_dest_axi_awaddr,
output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen,
output [ 2:0] m_dest_axi_awsize,
output [ 1:0] m_dest_axi_awburst,
output [ 2:0] m_dest_axi_awprot,
output [ 3:0] m_dest_axi_awcache,
output m_dest_axi_awvalid,
input m_dest_axi_awready,
output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_awid,
output [DMA_AXI_PROTOCOL_DEST:0] m_dest_axi_awlock,
// Write data
output [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata,
output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb,
input m_dest_axi_wready,
output m_dest_axi_wvalid,
output m_dest_axi_wlast,
output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_wid,
// Write response
input m_dest_axi_bvalid,
input [ 1:0] m_dest_axi_bresp,
output m_dest_axi_bready,
input [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_bid,
// Unused read interface
output m_dest_axi_arvalid,
output [DMA_AXI_ADDR_WIDTH-1:0] m_dest_axi_araddr,
output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen,
output [ 2:0] m_dest_axi_arsize,
output [ 1:0] m_dest_axi_arburst,
output [ 3:0] m_dest_axi_arcache,
output [ 2:0] m_dest_axi_arprot,
input m_dest_axi_arready,
input m_dest_axi_rvalid,
input [ 1:0] m_dest_axi_rresp,
input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata,
output m_dest_axi_rready,
output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_arid,
output [DMA_AXI_PROTOCOL_DEST:0] m_dest_axi_arlock,
input [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_rid,
input m_dest_axi_rlast,
// Master AXI interface
input m_src_axi_aclk,
input m_src_axi_aresetn,
// Read address
input m_src_axi_arready,
output m_src_axi_arvalid,
output [DMA_AXI_ADDR_WIDTH-1:0] m_src_axi_araddr,
output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen,
output [ 2:0] m_src_axi_arsize,
output [ 1:0] m_src_axi_arburst,
output [ 2:0] m_src_axi_arprot,
output [ 3:0] m_src_axi_arcache,
output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_arid,
output [DMA_AXI_PROTOCOL_SRC:0] m_src_axi_arlock,
// Read data and response
input [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata,
output m_src_axi_rready,
input m_src_axi_rvalid,
input [ 1:0] m_src_axi_rresp,
input [AXI_ID_WIDTH_SRC-1:0] m_src_axi_rid,
input m_src_axi_rlast,
// Unused write interface
output m_src_axi_awvalid,
output [DMA_AXI_ADDR_WIDTH-1:0] m_src_axi_awaddr,
output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen,
output [ 2:0] m_src_axi_awsize,
output [ 1:0] m_src_axi_awburst,
output [ 3:0] m_src_axi_awcache,
output [ 2:0] m_src_axi_awprot,
input m_src_axi_awready,
output m_src_axi_wvalid,
output [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata,
output [(DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb,
output m_src_axi_wlast,
input m_src_axi_wready,
input m_src_axi_bvalid,
input [ 1:0] m_src_axi_bresp,
output m_src_axi_bready,
output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_awid,
output [DMA_AXI_PROTOCOL_SRC:0] m_src_axi_awlock,
output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_wid,
input [AXI_ID_WIDTH_SRC-1:0] m_src_axi_bid,
// Slave streaming AXI interface
input s_axis_aclk,
output s_axis_ready,
input s_axis_valid,
input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
input [0:0] s_axis_user,
input s_axis_last,
output s_axis_xfer_req,
// Master streaming AXI interface
input m_axis_aclk,
input m_axis_ready,
output m_axis_valid,
output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
output m_axis_last,
output m_axis_xfer_req,
// Input FIFO interface
input fifo_wr_clk,
input fifo_wr_en,
input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
output fifo_wr_overflow,
input fifo_wr_sync,
output fifo_wr_xfer_req,
// Input FIFO interface
input fifo_rd_clk,
input fifo_rd_en,
output fifo_rd_valid,
output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
output fifo_rd_underflow,
output fifo_rd_xfer_req,
// Diagnostics interface
output [7:0] dest_diag_level_bursts
);
localparam DMA_TYPE_AXI_MM = 0;
localparam DMA_TYPE_AXI_STREAM = 1;
localparam DMA_TYPE_FIFO = 2;
localparam HAS_DEST_ADDR = DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
localparam HAS_SRC_ADDR = DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
// Argh... "[Synth 8-2722] system function call clog2 is not allowed here"
localparam BYTES_PER_BEAT_WIDTH_DEST = DMA_DATA_WIDTH_DEST > 1024 ? 8 :
DMA_DATA_WIDTH_DEST > 512 ? 7 :
DMA_DATA_WIDTH_DEST > 256 ? 6 :
DMA_DATA_WIDTH_DEST > 128 ? 5 :
DMA_DATA_WIDTH_DEST > 64 ? 4 :
DMA_DATA_WIDTH_DEST > 32 ? 3 :
DMA_DATA_WIDTH_DEST > 16 ? 2 :
DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 :
DMA_DATA_WIDTH_SRC > 512 ? 7 :
DMA_DATA_WIDTH_SRC > 256 ? 6 :
DMA_DATA_WIDTH_SRC > 128 ? 5 :
DMA_DATA_WIDTH_SRC > 64 ? 4 :
DMA_DATA_WIDTH_SRC > 32 ? 3 :
DMA_DATA_WIDTH_SRC > 16 ? 2 :
DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
localparam ID_WIDTH = (FIFO_SIZE) > 64 ? 8 :
(FIFO_SIZE) > 32 ? 7 :
(FIFO_SIZE) > 16 ? 6 :
(FIFO_SIZE) > 8 ? 5 :
(FIFO_SIZE) > 4 ? 4 :
(FIFO_SIZE) > 2 ? 3 :
(FIFO_SIZE) > 1 ? 2 : 1;
localparam DBG_ID_PADDING = ID_WIDTH > 8 ? 0 : 8 - ID_WIDTH;
/* AXI3 supports a maximum of 16 beats per burst. AXI4 supports a maximum of
256 beats per burst. If either bus is AXI3 set the maximum number of beats
per burst to 16. For non AXI interfaces the maximum beats per burst is in
theory unlimted. Set it to 1024 to provide a reasonable upper threshold */
localparam BEATS_PER_BURST_LIMIT_DEST =
(DMA_TYPE_DEST == DMA_TYPE_AXI_MM) ?
(DMA_AXI_PROTOCOL_DEST == 1 ? 16 : 256) :
1024;
localparam BYTES_PER_BURST_LIMIT_DEST =
BEATS_PER_BURST_LIMIT_DEST * DMA_DATA_WIDTH_DEST / 8;
localparam BEATS_PER_BURST_LIMIT_SRC =
(DMA_TYPE_SRC == DMA_TYPE_AXI_MM) ?
(DMA_AXI_PROTOCOL_SRC == 1 ? 16 : 256) :
1024;
localparam BYTES_PER_BURST_LIMIT_SRC =
BEATS_PER_BURST_LIMIT_SRC * DMA_DATA_WIDTH_SRC / 8;
/* The smaller bus limits the maximum bytes per burst. */
localparam BYTES_PER_BURST_LIMIT =
(BYTES_PER_BURST_LIMIT_DEST < BYTES_PER_BURST_LIMIT_SRC) ?
BYTES_PER_BURST_LIMIT_DEST : BYTES_PER_BURST_LIMIT_SRC;
/* Make sure the requested MAX_BYTES_PER_BURST does not exceed what the
interfaces can support. Limit the value if necessary. */
localparam REAL_MAX_BYTES_PER_BURST =
BYTES_PER_BURST_LIMIT < MAX_BYTES_PER_BURST ?
BYTES_PER_BURST_LIMIT : MAX_BYTES_PER_BURST;
/* Align to the length to the wider interface */
localparam DMA_LENGTH_ALIGN =
BYTES_PER_BEAT_WIDTH_DEST < BYTES_PER_BEAT_WIDTH_SRC ?
BYTES_PER_BEAT_WIDTH_SRC : BYTES_PER_BEAT_WIDTH_DEST;
localparam BYTES_PER_BURST_WIDTH =
REAL_MAX_BYTES_PER_BURST > 2048 ? 12 :
REAL_MAX_BYTES_PER_BURST > 1024 ? 11 :
REAL_MAX_BYTES_PER_BURST > 512 ? 10 :
REAL_MAX_BYTES_PER_BURST > 256 ? 9 :
REAL_MAX_BYTES_PER_BURST > 128 ? 8 :
REAL_MAX_BYTES_PER_BURST > 64 ? 7 :
REAL_MAX_BYTES_PER_BURST > 32 ? 6 :
REAL_MAX_BYTES_PER_BURST > 16 ? 5 :
REAL_MAX_BYTES_PER_BURST > 8 ? 4 :
REAL_MAX_BYTES_PER_BURST > 4 ? 3 :
REAL_MAX_BYTES_PER_BURST > 2 ? 2 : 1;
// ID signals from the DMAC, just for debugging
wire [ID_WIDTH-1:0] dest_request_id;
wire [ID_WIDTH-1:0] dest_data_id;
wire [ID_WIDTH-1:0] dest_address_id;
wire [ID_WIDTH-1:0] dest_response_id;
wire [ID_WIDTH-1:0] src_request_id;
wire [ID_WIDTH-1:0] src_data_id;
wire [ID_WIDTH-1:0] src_address_id;
wire [ID_WIDTH-1:0] src_response_id;
wire [11:0] dbg_status;
wire [31:0] dbg_ids0;
wire [31:0] dbg_ids1;
assign m_dest_axi_araddr = 'd0;
assign m_dest_axi_arlen = 'd0;
assign m_dest_axi_arsize = 'd0;
assign m_dest_axi_arburst = 'd0;
assign m_dest_axi_arcache = 'd0;
assign m_dest_axi_arprot = 'd0;
assign m_dest_axi_awid = 'h0;
assign m_dest_axi_awlock = 'h0;
assign m_dest_axi_wid = 'h0;
assign m_dest_axi_arid = 'h0;
assign m_dest_axi_arlock = 'h0;
assign m_src_axi_awaddr = 'd0;
assign m_src_axi_awlen = 'd0;
assign m_src_axi_awsize = 'd0;
assign m_src_axi_awburst = 'd0;
assign m_src_axi_awcache = 'd0;
assign m_src_axi_awprot = 'd0;
assign m_src_axi_wdata = 'd0;
assign m_src_axi_wstrb = 'd0;
assign m_src_axi_wlast = 'd0;
assign m_src_axi_awid = 'h0;
assign m_src_axi_awlock = 'h0;
assign m_src_axi_wid = 'h0;
assign m_src_axi_arid = 'h0;
assign m_src_axi_arlock = 'h0;
wire up_req_eot;
wire [BYTES_PER_BURST_WIDTH-1:0] up_req_measured_burst_length;
wire up_response_partial;
wire up_response_valid;
wire up_response_ready;
wire ctrl_enable;
wire ctrl_pause;
wire up_dma_req_valid;
wire up_dma_req_ready;
wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] up_dma_req_dest_address;
wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] up_dma_req_src_address;
wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_x_length;
wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_y_length;
wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_dest_stride;
wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_src_stride;
wire up_dma_req_sync_transfer_start;
wire up_dma_req_last;
assign dbg_ids0 = {
{DBG_ID_PADDING{1'b0}}, dest_response_id,
{DBG_ID_PADDING{1'b0}}, dest_data_id,
{DBG_ID_PADDING{1'b0}}, dest_address_id,
{DBG_ID_PADDING{1'b0}}, dest_request_id
};
assign dbg_ids1 = {
{DBG_ID_PADDING{1'b0}}, src_response_id,
{DBG_ID_PADDING{1'b0}}, src_data_id,
{DBG_ID_PADDING{1'b0}}, src_address_id,
{DBG_ID_PADDING{1'b0}}, src_request_id
};
axi_dmac_regmap #(
.DISABLE_DEBUG_REGISTERS(DISABLE_DEBUG_REGISTERS),
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
.BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
.DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
.DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN),
.DMA_CYCLIC(CYCLIC),
.HAS_DEST_ADDR(HAS_DEST_ADDR),
.HAS_SRC_ADDR(HAS_SRC_ADDR),
.DMA_2D_TRANSFER(DMA_2D_TRANSFER),
.SYNC_TRANSFER_START(SYNC_TRANSFER_START)
) i_regmap (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awprot(s_axi_awprot),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wready(s_axi_wready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bready(s_axi_bready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arready(s_axi_arready),
.s_axi_arprot(s_axi_arprot),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rdata(s_axi_rdata),
// Interrupt
.irq(irq),
// Control interface
.ctrl_enable(ctrl_enable),
.ctrl_pause(ctrl_pause),
// Request interface
.request_valid(up_dma_req_valid),
.request_ready(up_dma_req_ready),
.request_dest_address(up_dma_req_dest_address),
.request_src_address(up_dma_req_src_address),
.request_x_length(up_dma_req_x_length),
.request_y_length(up_dma_req_y_length),
.request_dest_stride(up_dma_req_dest_stride),
.request_src_stride(up_dma_req_src_stride),
.request_sync_transfer_start(up_dma_req_sync_transfer_start),
.request_last(up_dma_req_last),
// DMA response interface
.response_eot(up_req_eot),
.response_measured_burst_length(up_req_measured_burst_length),
.response_partial(up_response_partial),
.response_valid(up_response_valid),
.response_ready(up_response_ready),
// Debug interface
.dbg_dest_addr(m_dest_axi_awaddr),
.dbg_src_addr(m_src_axi_araddr),
.dbg_status(dbg_status),
.dbg_ids0(dbg_ids0),
.dbg_ids1(dbg_ids1)
);
axi_dmac_transfer #(
.DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
.DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
.BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
.DMA_TYPE_DEST(DMA_TYPE_DEST),
.DMA_TYPE_SRC(DMA_TYPE_SRC),
.DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
.DMA_2D_TRANSFER(DMA_2D_TRANSFER),
.ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC),
.ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST),
.ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ),
.AXI_SLICE_DEST(AXI_SLICE_DEST),
.AXI_SLICE_SRC(AXI_SLICE_SRC),
.MAX_BYTES_PER_BURST(REAL_MAX_BYTES_PER_BURST),
.FIFO_SIZE(FIFO_SIZE),
.ID_WIDTH(ID_WIDTH),
.AXI_LENGTH_WIDTH_SRC(8-(4*DMA_AXI_PROTOCOL_SRC)),
.AXI_LENGTH_WIDTH_DEST(8-(4*DMA_AXI_PROTOCOL_DEST)),
.ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF)
) i_transfer (
.ctrl_clk(s_axi_aclk),
.ctrl_resetn(s_axi_aresetn),
.ctrl_enable(ctrl_enable),
.ctrl_pause(ctrl_pause),
.req_valid(up_dma_req_valid),
.req_ready(up_dma_req_ready),
.req_dest_address(up_dma_req_dest_address),
.req_src_address(up_dma_req_src_address),
.req_x_length(up_dma_req_x_length),
.req_y_length(up_dma_req_y_length),
.req_dest_stride(up_dma_req_dest_stride),
.req_src_stride(up_dma_req_src_stride),
.req_sync_transfer_start(up_dma_req_sync_transfer_start),
.req_last(up_dma_req_last),
.req_eot(up_req_eot),
.req_measured_burst_length(up_req_measured_burst_length),
.req_response_partial(up_response_partial),
.req_response_valid(up_response_valid),
.req_response_ready(up_response_ready),
.m_dest_axi_aclk(m_dest_axi_aclk),
.m_dest_axi_aresetn(m_dest_axi_aresetn),
.m_src_axi_aclk(m_src_axi_aclk),
.m_src_axi_aresetn(m_src_axi_aresetn),
.m_axi_awaddr(m_dest_axi_awaddr),
.m_axi_awlen(m_dest_axi_awlen),
.m_axi_awsize(m_dest_axi_awsize),
.m_axi_awburst(m_dest_axi_awburst),
.m_axi_awprot(m_dest_axi_awprot),
.m_axi_awcache(m_dest_axi_awcache),
.m_axi_awvalid(m_dest_axi_awvalid),
.m_axi_awready(m_dest_axi_awready),
.m_axi_wdata(m_dest_axi_wdata),
.m_axi_wstrb(m_dest_axi_wstrb),
.m_axi_wready(m_dest_axi_wready),
.m_axi_wvalid(m_dest_axi_wvalid),
.m_axi_wlast(m_dest_axi_wlast),
.m_axi_bvalid(m_dest_axi_bvalid),
.m_axi_bresp(m_dest_axi_bresp),
.m_axi_bready(m_dest_axi_bready),
.m_axi_arready(m_src_axi_arready),
.m_axi_arvalid(m_src_axi_arvalid),
.m_axi_araddr(m_src_axi_araddr),
.m_axi_arlen(m_src_axi_arlen),
.m_axi_arsize(m_src_axi_arsize),
.m_axi_arburst(m_src_axi_arburst),
.m_axi_arprot(m_src_axi_arprot),
.m_axi_arcache(m_src_axi_arcache),
.m_axi_rdata(m_src_axi_rdata),
.m_axi_rready(m_src_axi_rready),
.m_axi_rvalid(m_src_axi_rvalid),
.m_axi_rlast(m_src_axi_rlast),
.m_axi_rresp(m_src_axi_rresp),
.s_axis_aclk(s_axis_aclk),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_data(s_axis_data),
.s_axis_user(s_axis_user),
.s_axis_last(s_axis_last),
.s_axis_xfer_req(s_axis_xfer_req),
.m_axis_aclk(m_axis_aclk),
.m_axis_ready(m_axis_ready),
.m_axis_valid(m_axis_valid),
.m_axis_data(m_axis_data),
.m_axis_last(m_axis_last),
.m_axis_xfer_req(m_axis_xfer_req),
.fifo_wr_clk(fifo_wr_clk),
.fifo_wr_en(fifo_wr_en),
.fifo_wr_din(fifo_wr_din),
.fifo_wr_overflow(fifo_wr_overflow),
.fifo_wr_sync(fifo_wr_sync),
.fifo_wr_xfer_req(fifo_wr_xfer_req),
.fifo_rd_clk(fifo_rd_clk),
.fifo_rd_en(fifo_rd_en),
.fifo_rd_valid(fifo_rd_valid),
.fifo_rd_dout(fifo_rd_dout),
.fifo_rd_underflow(fifo_rd_underflow),
.fifo_rd_xfer_req(fifo_rd_xfer_req),
// DBG
.dbg_dest_request_id(dest_request_id),
.dbg_dest_address_id(dest_address_id),
.dbg_dest_data_id(dest_data_id),
.dbg_dest_response_id(dest_response_id),
.dbg_src_request_id(src_request_id),
.dbg_src_address_id(src_address_id),
.dbg_src_data_id(src_data_id),
.dbg_src_response_id(src_response_id),
.dbg_status(dbg_status),
.dest_diag_level_bursts(dest_diag_level_bursts)
);
assign m_dest_axi_arvalid = 1'b0;
assign m_dest_axi_rready = 1'b0;
assign m_dest_axi_araddr = 'h0;
assign m_dest_axi_arlen = 'h0;
assign m_dest_axi_arsize = 'h0;
assign m_dest_axi_arburst = 'h0;
assign m_dest_axi_arcache = 'h0;
assign m_dest_axi_arprot = 'h0;
assign m_src_axi_awvalid = 1'b0;
assign m_src_axi_wvalid = 1'b0;
assign m_src_axi_bready = 1'b0;
assign m_src_axi_awvalid = 'h0;
assign m_src_axi_awaddr = 'h0;
assign m_src_axi_awlen = 'h0;
assign m_src_axi_awsize = 'h0;
assign m_src_axi_awburst = 'h0;
assign m_src_axi_awcache = 'h0;
assign m_src_axi_awprot = 'h0;
assign m_src_axi_wvalid = 'h0;
assign m_src_axi_wdata = 'h0;
assign m_src_axi_wstrb = 'h0;
assign m_src_axi_wlast = 'h0;
endmodule
|
////////////////////////////////////////////////////////
// RS-232 RX and TX module
// (c) fpga4fun.com & KNJN LLC - 2003 to 2013
// The RS-232 settings are fixed
// TX: 8-bit data, 2 stop, no-parity
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
//`define SIMULATION // in this mode, TX outputs one bit per clock cycle
// and RX receives one bit per clock cycle (for fast simulations)
////////////////////////////////////////////////////////
//source of these modules:
//http://www.fpga4fun.com/SerialInterface.html
//http://www.fpga4fun.com/SiteInformation.html -- some legal info
module async_transmitter(
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
// TxD_data is latched so that it doesn't have to stay valid while it is being sent
parameter ClkFrequency = 50000000; // 25MHz
parameter Baud = 115200;
generate
if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate");
endgenerate
////////////////////////////////
`ifdef SIMULATION
wire BitTick = 1'b1; // output one bit per clock cycle
`else
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
`endif
reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_shift = 0;
always @(posedge clk)
begin
if(TxD_ready & TxD_start)
TxD_shift <= TxD_data;
else if(TxD_state[3] & BitTick)
TxD_shift <= (TxD_shift >> 1);
case(TxD_state)
4'b0000: if(TxD_start) TxD_state <= 4'b0100;
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
default: if(BitTick) TxD_state <= 4'b0000;
endcase
end
assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits
endmodule
////////////////////////////////////////////////////////
module async_receiver(
input clk,
input RxD,
output reg RxD_data_ready = 0,
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_idle, // asserted when no data has been received for a while
output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
);
parameter ClkFrequency = 50000000; // 25MHz
parameter Baud = 115200;
parameter Oversampling = 16; // needs to be a power of 2
// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
// 8 times oversampling by default, use 16 for higher quality reception
generate
if(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling");
if(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
endgenerate
////////////////////////////////
reg [3:0] RxD_state = 0;
`ifdef SIMULATION
wire RxD_bit = RxD;
wire sampleNow = 1'b1; // receive one bit per clock cycle
`else
wire OversamplingTick;
BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick));
// synchronize RxD to our clk domain
reg [1:0] RxD_sync = 2'b11;
always @(posedge clk)
if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};
// and filter it
reg [1:0] Filter_cnt = 2'b11;
reg RxD_bit = 1'b1;
always @(posedge clk)
if(OversamplingTick)
begin
if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1;
else
if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1;
if(Filter_cnt==2'b11) RxD_bit <= 1'b1;
else
if(Filter_cnt==2'b00) RxD_bit <= 1'b0;
end
// and decide when is the good time to sample the RxD line
function integer log2(input integer v);
begin log2=0;
while(v>>log2)
log2=log2+1;
end endfunction
localparam l2o = log2(Oversampling);
reg [l2o-2:0] OversamplingCnt = 0;
always @(posedge clk)
if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;
wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
`endif
// now we can accumulate the RxD bits in a shift-register
always @(posedge clk)
case(RxD_state)
4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found?
4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow
4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0
4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1
4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2
4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3
4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4
4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5
4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6
4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7
4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit
default: RxD_state <= 4'b0000;
endcase
always @(posedge clk)
if(sampleNow && RxD_state[3])
RxD_data <= {RxD_bit, RxD_data[7:1]};
//reg RxD_data_error = 0;
always @(posedge clk)
begin
RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received
//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received
end
reg [l2o+1:0] GapCnt = 0;
always @(posedge clk)
if (RxD_state!=0)
GapCnt<=0;
else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1])
GapCnt <= GapCnt + 1'h1;
assign RxD_idle = GapCnt[l2o+1];
always @(posedge clk)
RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
endmodule
////////////////////////////////////////////////////////
// dummy module used to be able to raise an assertion in Verilog
module ASSERTION_ERROR();
endmodule
////////////////////////////////////////////////////////
module BaudTickGen(
input clk, enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 50000000;
parameter Baud = 115200;
parameter Oversampling = 1;
function integer log2(input integer v);
begin log2=0;
while(v>>log2)
log2=log2+1;
end endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte
//acc width == 16
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow
//shiftlimiter == 5
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk)
if(enable)
Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0];
else
Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
////////////////////////////////////////////////////////
|
`timescale 1 ns / 1 ps
module seven_segment_display
(
input clk,
input [15:0]num_in,
output reg [6:0]dig,
output reg dp,
output reg neg,
output reg clr,
output reg [3:0]dig_sel
);
//dig format
//dig[0] : A, top
//dig[1] : B, top/right
//dig[2] : C, bottom/right
//dig[3] : D, bottom
//dig[4] : E, bottom/left
//dig[5] : F, top/left
//dig[6] : G, middle
reg [6:0]dig1;
reg [6:0]dig2;
reg [6:0]dig3;
reg [6:0]dig4;
reg [19:0] clk_div;
always @(posedge clk) begin
clk_div = clk_div + 1;
end
always @(posedge clk) begin
/* dig_sel <= 4'b0001; */
/* dig <= dig1; */
if (clk_div == 0)
begin
if(dig_sel == 0)
dig_sel <= 1;
else
dig_sel <= {dig_sel[0],dig_sel[3:1]};
case(dig_sel)
4'b0010: dig <= dig4;
4'b0100: dig <= dig3;
4'b1000: dig <= dig2;
4'b0001: dig <= dig1;
endcase
end
end
always @(posedge clk) begin
case(num_in[3:0])
4'b0000: dig1 = 7'b1000000; //0
4'b0001: dig1 = 7'b1111001; //1
4'b0010: dig1 = 7'b0100100; //2
4'b0011: dig1 = 7'b0110000; //3
4'b0100: dig1 = 7'b0011001; //4
4'b0101: dig1 = 7'b0010010; //5
4'b0110: dig1 = 7'b0000010; //6
4'b0111: dig1 = 7'b1111000; //7
4'b1000: dig1 = 7'b0000000; //8
4'b1001: dig1 = 7'b0010000; //9
4'b1010: dig1 = 7'b0001000; //A
4'b1011: dig1 = 7'b0000011; //b
4'b1100: dig1 = 7'b1000110; //C
4'b1101: dig1 = 7'b0100001; //d
4'b1110: dig1 = 7'b0000110; //E
4'b1111: dig1 = 7'b0001110; //F
endcase
case(num_in[7:4])
4'b0000: dig2 = 7'b1000000; //0
4'b0001: dig2 = 7'b1111001; //1
4'b0010: dig2 = 7'b0100100; //2
4'b0011: dig2 = 7'b0110000; //3
4'b0100: dig2 = 7'b0011001; //4
4'b0101: dig2 = 7'b0010010; //5
4'b0110: dig2 = 7'b0000010; //6
4'b0111: dig2 = 7'b1111000; //7
4'b1000: dig2 = 7'b0000000; //8
4'b1001: dig2 = 7'b0010000; //9
4'b1010: dig2 = 7'b0001000; //A
4'b1011: dig2 = 7'b0000011; //b
4'b1100: dig2 = 7'b1000110; //C
4'b1101: dig2 = 7'b0100001; //d
4'b1110: dig2 = 7'b0000110; //E
4'b1111: dig2 = 7'b0001110; //F
endcase
case(num_in[11:8])
4'b0000: dig3 = 7'b1000000; //0
4'b0001: dig3 = 7'b1111001; //1
4'b0010: dig3 = 7'b0100100; //2
4'b0011: dig3 = 7'b0110000; //3
4'b0100: dig3 = 7'b0011001; //4
4'b0101: dig3 = 7'b0010010; //5
4'b0110: dig3 = 7'b0000010; //6
4'b0111: dig3 = 7'b1111000; //7
4'b1000: dig3 = 7'b0000000; //8
4'b1001: dig3 = 7'b0010000; //9
4'b1010: dig3 = 7'b0001000; //A
4'b1011: dig3 = 7'b0000011; //b
4'b1100: dig3 = 7'b1000110; //C
4'b1101: dig3 = 7'b0100001; //d
4'b1110: dig3 = 7'b0000110; //E
4'b1111: dig3 = 7'b0001110; //F
endcase
case(num_in[15:12])
4'b0000: dig4 = 7'b1000000; //0
4'b0001: dig4 = 7'b1111001; //1
4'b0010: dig4 = 7'b0100100; //2
4'b0011: dig4 = 7'b0110000; //3
4'b0100: dig4 = 7'b0011001; //4
4'b0101: dig4 = 7'b0010010; //5
4'b0110: dig4 = 7'b0000010; //6
4'b0111: dig4 = 7'b1111000; //7
4'b1000: dig4 = 7'b0000000; //8
4'b1001: dig4 = 7'b0010000; //9
4'b1010: dig4 = 7'b0001000; //A
4'b1011: dig4 = 7'b0000011; //b
4'b1100: dig4 = 7'b1000110; //C
4'b1101: dig4 = 7'b0100001; //d
4'b1110: dig4 = 7'b0000110; //E
4'b1111: dig4 = 7'b0001110; //F
endcase
end
always @(posedge clk) begin
dp <= 1;
neg <= 1;
clr <= 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3B_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND3B_BLACKBOX_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and3b (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3B_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_SYMBOL_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dff$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_SYMBOL_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Nov 2 09:18:11 2016
/////////////////////////////////////////////////////////////
module FPU_Add_Subtract_Function_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
input [1:0] r_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire FSM_selector_C, add_overflow_flag, FSM_selector_D, intAS,
sign_final_result, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21,
n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35,
n36, n37, n38, n39, n40, n41, n43, n44, n45, n47, n48, n49, n51, n52,
n53, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67,
n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81,
n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95,
n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107,
n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118,
n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129,
n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140,
n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151,
n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162,
n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173,
n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184,
n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206,
n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217,
n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228,
n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239,
n240, n241, n242, n243, n244, n245, n246, n247, n248, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731,
n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742,
n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753,
n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764,
n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786,
n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797,
n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808,
n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819,
n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830,
n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841,
n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852,
n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863,
n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874,
n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885,
n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896,
n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n972, n973, n974,
n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985,
n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996,
n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006,
n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016,
n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226,
n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256,
n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266,
n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276,
n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286,
n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296,
n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306,
n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326,
n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336,
n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346,
n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356,
n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366,
n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376,
n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386,
n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396,
n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406,
n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416,
n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426,
n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436,
n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446,
n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456,
n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466,
n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476,
n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486,
n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496,
n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506,
n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516,
n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526,
n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536,
n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546,
n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556,
n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566,
n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576,
n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596,
n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606,
n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616,
n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726,
n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736,
n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746,
n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756,
n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766,
n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776,
n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786,
n1787, n1788, n1789, n1790;
wire [1:0] FSM_selector_B;
wire [31:0] intDX;
wire [31:0] intDY;
wire [30:0] DMP;
wire [30:0] DmP;
wire [7:0] exp_oper_result;
wire [4:0] LZA_output;
wire [25:0] Add_Subt_result;
wire [25:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [51:0] Barrel_Shifter_module_Mux_Array_Data_array;
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n173), .CK(clk), .RN(
n1790), .Q(DmP[28]) );
DFFRXLTS YRegister_Q_reg_27_ ( .D(n171), .CK(clk), .RN(n1762), .Q(intDY[27]),
.QN(n688) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n170), .CK(clk), .RN(
n1790), .Q(DmP[27]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n167), .CK(clk), .RN(
n1781), .Q(DmP[26]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n164), .CK(clk), .RN(
n1782), .Q(DmP[25]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n161), .CK(clk), .RN(
n1781), .Q(DmP[24]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n158), .CK(clk), .RN(
n1773), .Q(DmP[23]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n155), .CK(clk), .RN(
n1763), .Q(DmP[22]), .QN(n1743) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n152), .CK(clk), .RN(
n1763), .Q(DmP[21]), .QN(n1734) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n149), .CK(clk), .RN(
n1763), .QN(n660) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n146), .CK(clk), .RN(
n1763), .Q(DmP[19]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n143), .CK(clk), .RN(
n1763), .Q(DmP[18]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n137), .CK(clk), .RN(
n1779), .Q(DmP[16]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n134), .CK(clk), .RN(
n1783), .Q(DmP[15]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n131), .CK(clk), .RN(
n1787), .Q(DmP[14]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n128), .CK(clk), .RN(
n1779), .Q(DmP[13]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n125), .CK(clk), .RN(
n1787), .Q(DmP[12]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n122), .CK(clk), .RN(
n1789), .Q(DmP[11]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n119), .CK(clk), .RN(
n1783), .Q(DmP[10]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n107), .CK(clk), .RN(
n1764), .Q(DmP[6]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n101), .CK(clk), .RN(
n1764), .Q(DmP[4]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n98), .CK(clk), .RN(
n1764), .Q(DmP[3]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n95), .CK(clk), .RN(
n1765), .Q(DmP[2]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(n75), .CK(clk), .RN(n1786), .QN(n654) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(n73), .CK(clk), .RN(n1765), .Q(LZA_output[0]), .QN(n1757) );
DFFRX1TS Sel_B_Q_reg_1_ ( .D(n70), .CK(clk), .RN(n244), .Q(FSM_selector_B[1]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk), .RN(n1767),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[27]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk), .RN(n1767),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[26]) );
DFFRX1TS Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n77), .CK(clk), .RN(
n1771), .Q(overflow_flag), .QN(n1760) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(n74), .CK(clk), .RN(n1782), .Q(LZA_output[1]), .QN(n1758) );
DFFRX1TS Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n69), .CK(clk), .RN(
n1771), .Q(underflow_flag), .QN(n1756) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[35]), .QN(n1755) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[34]), .QN(n1754) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk), .RN(n1768),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[47]), .QN(n1753) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk), .RN(n1768),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[49]), .QN(n1752) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk), .RN(n1768),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[48]), .QN(n1751) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk), .RN(n1778),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[51]), .QN(n1749) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n21), .CK(clk),
.RN(n1778), .Q(Sgf_normalized_result[22]), .QN(n1742) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n17), .CK(clk),
.RN(n1778), .Q(Sgf_normalized_result[23]), .QN(n1741) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n14), .CK(clk),
.RN(n1778), .Q(Sgf_normalized_result[24]), .QN(n1740) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(n225), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[9]), .QN(n1738) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(n223), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[7]), .QN(n1736) );
DFFRX2TS XRegister_Q_reg_16_ ( .D(n199), .CK(clk), .RN(n1788), .Q(intDX[16]),
.QN(n1733) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n29), .CK(clk),
.RN(n1780), .Q(Sgf_normalized_result[20]), .QN(n1732) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n25), .CK(clk),
.RN(n1785), .Q(Sgf_normalized_result[21]), .QN(n1731) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(n227), .CK(clk),
.RN(n1771), .Q(Add_Subt_result[11]), .QN(n1730) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(n226), .CK(clk),
.RN(n1771), .Q(Add_Subt_result[10]), .QN(n1729) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n33), .CK(clk),
.RN(n1780), .Q(Sgf_normalized_result[19]), .QN(n1726) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n37), .CK(clk),
.RN(n1785), .Q(Sgf_normalized_result[18]), .QN(n1725) );
DFFRX2TS XRegister_Q_reg_10_ ( .D(n193), .CK(clk), .RN(n1762), .Q(intDX[10]),
.QN(n1724) );
DFFRX2TS XRegister_Q_reg_28_ ( .D(n211), .CK(clk), .RN(n1784), .QN(n1723) );
DFFRX2TS XRegister_Q_reg_5_ ( .D(n188), .CK(clk), .RN(n1780), .Q(intDX[5]),
.QN(n1721) );
DFFRX2TS YRegister_Q_reg_12_ ( .D(n126), .CK(clk), .RN(n1783), .Q(intDY[12]),
.QN(n1719) );
DFFRX2TS XRegister_Q_reg_6_ ( .D(n189), .CK(clk), .RN(n1776), .Q(intDX[6]),
.QN(n1718) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n57), .CK(clk),
.RN(n1777), .Q(Sgf_normalized_result[13]), .QN(n1716) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n49), .CK(clk),
.RN(n1777), .Q(Sgf_normalized_result[15]), .QN(n1715) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n45), .CK(clk),
.RN(n1777), .Q(Sgf_normalized_result[16]), .QN(n1714) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n41), .CK(clk),
.RN(n1780), .Q(Sgf_normalized_result[17]), .QN(n1713) );
DFFRX2TS YRegister_Q_reg_18_ ( .D(n144), .CK(clk), .RN(n1763), .Q(intDY[18]),
.QN(n1711) );
DFFRX2TS YRegister_Q_reg_30_ ( .D(n180), .CK(clk), .RN(n1762), .Q(intDY[30]),
.QN(n1710) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(n228), .CK(clk),
.RN(n1771), .Q(Add_Subt_result[12]), .QN(n1709) );
DFFRX2TS YRegister_Q_reg_21_ ( .D(n153), .CK(clk), .RN(n1763), .Q(intDY[21]),
.QN(n1708) );
DFFRX2TS YRegister_Q_reg_26_ ( .D(n168), .CK(clk), .RN(n1762), .Q(intDY[26]),
.QN(n1707) );
DFFRX1TS XRegister_Q_reg_8_ ( .D(n191), .CK(clk), .RN(n1776), .Q(intDX[8]),
.QN(n1704) );
DFFRX2TS XRegister_Q_reg_30_ ( .D(n213), .CK(clk), .RN(n1789), .Q(intDX[30]),
.QN(n1702) );
DFFRX2TS XRegister_Q_reg_29_ ( .D(n212), .CK(clk), .RN(n1788), .Q(intDX[29]),
.QN(n1701) );
DFFRX2TS XRegister_Q_reg_19_ ( .D(n202), .CK(clk), .RN(n1784), .Q(intDX[19]),
.QN(n1700) );
DFFRX2TS XRegister_Q_reg_14_ ( .D(n197), .CK(clk), .RN(n1788), .Q(intDX[14]),
.QN(n1699) );
DFFRX2TS XRegister_Q_reg_13_ ( .D(n196), .CK(clk), .RN(n1789), .Q(intDX[13]),
.QN(n1698) );
DFFRX2TS XRegister_Q_reg_18_ ( .D(n201), .CK(clk), .RN(n1784), .Q(intDX[18]),
.QN(n1697) );
DFFRX2TS XRegister_Q_reg_17_ ( .D(n200), .CK(clk), .RN(n1789), .Q(intDX[17]),
.QN(n1696) );
DFFRX2TS XRegister_Q_reg_15_ ( .D(n198), .CK(clk), .RN(n1788), .Q(intDX[15]),
.QN(n1695) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n53), .CK(clk),
.RN(n1777), .Q(Sgf_normalized_result[14]), .QN(n1693) );
DFFRX2TS YRegister_Q_reg_8_ ( .D(n114), .CK(clk), .RN(n1784), .Q(intDY[8]),
.QN(n1690) );
DFFRX2TS YRegister_Q_reg_17_ ( .D(n141), .CK(clk), .RN(n1763), .Q(intDY[17]),
.QN(n1689) );
DFFRX2TS YRegister_Q_reg_25_ ( .D(n165), .CK(clk), .RN(n1762), .Q(intDY[25]),
.QN(n1688) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(n231), .CK(clk),
.RN(n1771), .Q(Add_Subt_result[15]), .QN(n1687) );
DFFRX2TS YRegister_Q_reg_20_ ( .D(n150), .CK(clk), .RN(n1763), .Q(intDY[20]),
.QN(n1685) );
DFFRX2TS YRegister_Q_reg_22_ ( .D(n156), .CK(clk), .RN(n1762), .Q(intDY[22]),
.QN(n1684) );
DFFRX2TS YRegister_Q_reg_11_ ( .D(n123), .CK(clk), .RN(n1787), .Q(intDY[11]),
.QN(n1683) );
DFFRX2TS YRegister_Q_reg_14_ ( .D(n132), .CK(clk), .RN(n1783), .Q(intDY[14]),
.QN(n1681) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(n217), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[1]), .QN(n1678) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(n218), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[2]), .QN(n1677) );
DFFRX2TS XRegister_Q_reg_4_ ( .D(n187), .CK(clk), .RN(n1780), .Q(intDX[4]),
.QN(n1676) );
DFFRX2TS Sel_C_Q_reg_0_ ( .D(n243), .CK(clk), .RN(n244), .Q(FSM_selector_C),
.QN(n1727) );
DFFRX2TS XRegister_Q_reg_7_ ( .D(n190), .CK(clk), .RN(n1776), .Q(intDX[7]),
.QN(n1675) );
DFFRX2TS YRegister_Q_reg_29_ ( .D(n177), .CK(clk), .RN(n1762), .Q(intDY[29]),
.QN(n1674) );
DFFRX1TS XRegister_Q_reg_9_ ( .D(n192), .CK(clk), .RN(n1774), .Q(intDX[9]),
.QN(n1673) );
DFFRX2TS YRegister_Q_reg_19_ ( .D(n147), .CK(clk), .RN(n1763), .Q(intDY[19]),
.QN(n1672) );
DFFRX2TS YRegister_Q_reg_7_ ( .D(n111), .CK(clk), .RN(n1787), .Q(intDY[7]),
.QN(n1671) );
DFFRX2TS XRegister_Q_reg_26_ ( .D(n209), .CK(clk), .RN(n1784), .Q(intDX[26]),
.QN(n1670) );
DFFRX2TS XRegister_Q_reg_24_ ( .D(n207), .CK(clk), .RN(n1788), .Q(intDX[24]),
.QN(n1669) );
DFFRX2TS XRegister_Q_reg_22_ ( .D(n205), .CK(clk), .RN(n1789), .Q(intDX[22]),
.QN(n1668) );
DFFRX2TS XRegister_Q_reg_21_ ( .D(n204), .CK(clk), .RN(n1788), .Q(intDX[21]),
.QN(n1667) );
DFFRX2TS XRegister_Q_reg_27_ ( .D(n210), .CK(clk), .RN(n1788), .Q(intDX[27]),
.QN(n1666) );
DFFRX2TS XRegister_Q_reg_25_ ( .D(n208), .CK(clk), .RN(n1789), .Q(intDX[25]),
.QN(n1665) );
DFFRX2TS XRegister_Q_reg_23_ ( .D(n206), .CK(clk), .RN(n1784), .Q(intDX[23]),
.QN(n1664) );
DFFRX2TS XRegister_Q_reg_11_ ( .D(n194), .CK(clk), .RN(n1789), .Q(intDX[11]),
.QN(n1663) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(n230), .CK(clk),
.RN(n1771), .Q(Add_Subt_result[14]), .QN(n1662) );
DFFRX2TS YRegister_Q_reg_23_ ( .D(n159), .CK(clk), .RN(n1762), .Q(intDY[23]),
.QN(n1661) );
DFFRX2TS YRegister_Q_reg_15_ ( .D(n135), .CK(clk), .RN(n1785), .Q(intDY[15]),
.QN(n1660) );
DFFRX2TS XRegister_Q_reg_20_ ( .D(n203), .CK(clk), .RN(n1789), .Q(intDX[20]),
.QN(n1659) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n68),
.CK(clk), .RN(n1767), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n58),
.CK(clk), .RN(n1768), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n56),
.CK(clk), .RN(n1769), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n52),
.CK(clk), .RN(n1769), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n48),
.CK(clk), .RN(n1769), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n44),
.CK(clk), .RN(n1769), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n40),
.CK(clk), .RN(n1769), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n36),
.CK(clk), .RN(n1769), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n32),
.CK(clk), .RN(n1769), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n28),
.CK(clk), .RN(n1769), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n24),
.CK(clk), .RN(n1769), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n20),
.CK(clk), .RN(n1769), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n16),
.CK(clk), .RN(n1770), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n13),
.CK(clk), .RN(n1770), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n38), .CK(
clk), .RN(n1770), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n34), .CK(
clk), .RN(n1770), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n30), .CK(
clk), .RN(n1770), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n26), .CK(
clk), .RN(n1770), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n22), .CK(
clk), .RN(n1771), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n18), .CK(
clk), .RN(n1771), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n62),
.CK(clk), .RN(n1768), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n61),
.CK(clk), .RN(n1768), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n60),
.CK(clk), .RN(n1768), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n1747),
.CK(clk), .RN(n1770), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n1746),
.CK(clk), .RN(n1770), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n1745),
.CK(clk), .RN(n1770), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n1744),
.CK(clk), .RN(n1770), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n67),
.CK(clk), .RN(n1767), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n66),
.CK(clk), .RN(n1767), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n65),
.CK(clk), .RN(n1767), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n64),
.CK(clk), .RN(n1767), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n63),
.CK(clk), .RN(n1768), .Q(final_result_ieee[27]) );
DFFRX1TS XRegister_Q_reg_3_ ( .D(n186), .CK(clk), .RN(n1786), .Q(intDX[3]),
.QN(n1703) );
DFFRX2TS YRegister_Q_reg_13_ ( .D(n129), .CK(clk), .RN(n1787), .Q(intDY[13]),
.QN(n1686) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n59), .CK(clk),
.RN(n1777), .Q(Sgf_normalized_result[12]), .QN(n1717) );
DFFRX1TS XRegister_Q_reg_31_ ( .D(n182), .CK(clk), .RN(n1779), .Q(intDX[31]),
.QN(n1761) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n23), .CK(clk), .RN(
n1775), .Q(Sgf_normalized_result[3]) );
DFFRX2TS Sel_D_Q_reg_0_ ( .D(n245), .CK(clk), .RN(n244), .Q(FSM_selector_D)
);
DFFRX2TS YRegister_Q_reg_5_ ( .D(n105), .CK(clk), .RN(n1764), .Q(intDY[5])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(n219), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[3]) );
DFFRX2TS YRegister_Q_reg_6_ ( .D(n108), .CK(clk), .RN(n1764), .Q(intDY[6])
);
DFFRX2TS YRegister_Q_reg_16_ ( .D(n138), .CK(clk), .RN(n1787), .Q(intDY[16])
);
DFFRX2TS XRegister_Q_reg_12_ ( .D(n195), .CK(clk), .RN(n1784), .Q(intDX[12])
);
DFFRX2TS YRegister_Q_reg_2_ ( .D(n96), .CK(clk), .RN(n1764), .Q(intDY[2]) );
DFFRX2TS YRegister_Q_reg_10_ ( .D(n120), .CK(clk), .RN(n1783), .Q(intDY[10])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(n222), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[6]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(n224), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[8]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(n236), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[20]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(n220), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[4]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(n234), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[18]) );
DFFRX2TS Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(n241), .CK(
clk), .RN(n1775), .Q(add_overflow_flag), .QN(n1759) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk), .RN(n1768),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[46]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(n232), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[16]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk), .RN(n1765),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[44]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk), .RN(n1768),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[45]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(n216), .CK(clk),
.RN(n1778), .Q(Add_Subt_result[0]) );
DFFRX2TS YRegister_Q_reg_1_ ( .D(n93), .CK(clk), .RN(n1765), .Q(intDY[1]),
.QN(n1682) );
DFFRX2TS YRegister_Q_reg_3_ ( .D(n99), .CK(clk), .RN(n1764), .Q(intDY[3]),
.QN(n1680) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n83), .CK(clk), .RN(
n1781), .Q(exp_oper_result[4]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk), .RN(n1765),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[42]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[36]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[37]) );
DFFRX1TS XRegister_Q_reg_1_ ( .D(n184), .CK(clk), .RN(n1775), .Q(intDX[1]),
.QN(n1705) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk), .RN(n1765),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[43]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[38]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[39]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[40]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n15), .CK(clk), .RN(
n1774), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n82), .CK(clk), .RN(
n1790), .Q(exp_oper_result[3]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n79), .CK(clk), .RN(
n1773), .Q(exp_oper_result[0]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n80), .CK(clk), .RN(
n1790), .Q(exp_oper_result[1]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n81), .CK(clk), .RN(
n1781), .Q(exp_oper_result[2]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk), .RN(n1765),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[41]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n19), .CK(clk), .RN(
n1775), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n27), .CK(clk), .RN(
n1775), .Q(Sgf_normalized_result[4]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n31), .CK(clk), .RN(
n1786), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n35), .CK(clk), .RN(
n1786), .Q(Sgf_normalized_result[6]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n39), .CK(clk), .RN(
n1781), .Q(Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n47), .CK(clk), .RN(
n1776), .Q(Sgf_normalized_result[9]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n78), .CK(clk), .RN(
n1774), .Q(exp_oper_result[7]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n84), .CK(clk), .RN(
n1774), .Q(exp_oper_result[5]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n85), .CK(clk), .RN(
n1774), .Q(exp_oper_result[6]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(n76), .CK(clk), .RN(n1790), .Q(LZA_output[3]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n12), .CK(clk),
.RN(n1779), .Q(Sgf_normalized_result[25]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n157), .CK(clk), .RN(
n1782), .Q(DMP[23]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n163), .CK(clk), .RN(
n1782), .Q(DMP[25]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n169), .CK(clk), .RN(
n1782), .Q(DMP[27]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(n72), .CK(clk), .RN(n1782), .Q(LZA_output[4]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n112), .CK(clk), .RN(
n1776), .Q(DMP[8]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n115), .CK(clk), .RN(
n1777), .Q(DMP[9]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n89), .CK(clk), .RN(
n1765), .Q(DmP[0]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n113), .CK(clk), .RN(
n1783), .Q(DmP[8]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n116), .CK(clk), .RN(
n1783), .Q(DmP[9]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n127), .CK(clk), .RN(
n1777), .Q(DMP[13]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n133), .CK(clk), .RN(
n1780), .Q(DMP[15]) );
DFFRX2TS YRegister_Q_reg_4_ ( .D(n102), .CK(clk), .RN(n1764), .Q(intDY[4])
);
DFFRX2TS YRegister_Q_reg_9_ ( .D(n117), .CK(clk), .RN(n1787), .Q(intDY[9])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(n221), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[5]) );
DFFRX2TS YRegister_Q_reg_0_ ( .D(n90), .CK(clk), .RN(n1765), .Q(intDY[0]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(n238), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[22]) );
DFFRX1TS XRegister_Q_reg_0_ ( .D(n183), .CK(clk), .RN(n1775), .Q(intDX[0]),
.QN(n1722) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n248), .CK(clk),
.RN(n1775), .Q(Sgf_normalized_result[0]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n55), .CK(clk),
.RN(n1776), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n51), .CK(clk),
.RN(n1776), .Q(Sgf_normalized_result[10]) );
DFFRX1TS Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n86), .CK(clk),
.RN(n1779), .Q(sign_final_result), .QN(n1679) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk), .RN(n1779),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[50]), .QN(n1748) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n139), .CK(clk), .RN(
n1780), .Q(DMP[17]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n160), .CK(clk), .RN(
n1786), .Q(DMP[24]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n166), .CK(clk), .RN(
n1786), .Q(DMP[26]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n176), .CK(clk), .RN(
n1786), .Q(DmP[29]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n179), .CK(clk), .RN(
n1781), .Q(DmP[30]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n118), .CK(clk), .RN(
n1777), .Q(DMP[10]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n109), .CK(clk), .RN(
n1776), .Q(DMP[7]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n106), .CK(clk), .RN(
n1776), .Q(DMP[6]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n103), .CK(clk), .RN(
n1782), .Q(DMP[5]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n100), .CK(clk), .RN(
n1782), .Q(DMP[4]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n97), .CK(clk), .RN(
n1782), .Q(DMP[3]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n94), .CK(clk), .RN(
n1775), .Q(DMP[2]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n91), .CK(clk), .RN(
n1775), .Q(DMP[1]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n88), .CK(clk), .RN(
n1775), .Q(DMP[0]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[29]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[32]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk), .RN(n1767),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[28]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk), .RN(n1767),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[31]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk), .RN(n1767),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[30]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n140), .CK(clk), .RN(
n1783), .Q(DmP[17]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n110), .CK(clk), .RN(
n1764), .Q(DmP[7]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n104), .CK(clk), .RN(
n1764), .Q(DmP[5]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n92), .CK(clk), .RN(
n1765), .Q(DmP[1]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n178), .CK(clk), .RN(
n1774), .Q(DMP[30]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n175), .CK(clk), .RN(
n1774), .Q(DMP[29]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n172), .CK(clk), .RN(
n1774), .Q(DMP[28]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n154), .CK(clk), .RN(
n1778), .Q(DMP[22]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n151), .CK(clk), .RN(
n1778), .Q(DMP[21]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n148), .CK(clk), .RN(
n1778), .Q(DMP[20]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n142), .CK(clk), .RN(
n1785), .Q(DMP[18]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n136), .CK(clk), .RN(
n1785), .Q(DMP[16]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n130), .CK(clk), .RN(
n1785), .Q(DMP[14]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n124), .CK(clk), .RN(
n1777), .Q(DMP[12]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n121), .CK(clk), .RN(
n1777), .Q(DMP[11]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[33]) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n247), .CK(clk), .RN(n1779), .Q(
FS_Module_state_reg[1]), .QN(n655) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n246), .CK(clk), .RN(n1779), .Q(
FS_Module_state_reg[2]), .QN(n1694) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n214), .CK(clk), .RN(n1774), .Q(
FS_Module_state_reg[0]), .QN(n1712) );
DFFRX1TS YRegister_Q_reg_31_ ( .D(n87), .CK(clk), .RN(n1779), .Q(intDY[31])
);
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(n233), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[17]), .QN(n1750) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(n235), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[19]), .QN(n1739) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(n240), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[24]), .QN(n1737) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(n237), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[21]), .QN(n1735) );
DFFRX1TS XRegister_Q_reg_2_ ( .D(n185), .CK(clk), .RN(n1780), .Q(intDX[2]),
.QN(n1706) );
DFFRX2TS Sel_B_Q_reg_0_ ( .D(n71), .CK(clk), .RN(n244), .Q(FSM_selector_B[0]), .QN(n1692) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(n229), .CK(clk),
.RN(n1771), .Q(Add_Subt_result[13]), .QN(n1691) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(n215), .CK(clk),
.RN(n1778), .Q(Add_Subt_result[25]) );
DFFRX1TS ASRegister_Q_reg_0_ ( .D(n181), .CK(clk), .RN(n1779), .Q(intAS) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n43), .CK(clk), .RN(
n1776), .Q(Sgf_normalized_result[8]) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n242), .CK(clk), .RN(n1774), .Q(
FS_Module_state_reg[3]), .QN(n1720) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n145), .CK(clk), .RN(
n1778), .Q(DMP[19]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(n239), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[23]), .QN(n1728) );
DFFRX2TS YRegister_Q_reg_24_ ( .D(n162), .CK(clk), .RN(n1762), .Q(intDY[24])
);
DFFRX2TS YRegister_Q_reg_28_ ( .D(n174), .CK(clk), .RN(n1762), .Q(intDY[28])
);
AND2X2TS U892 ( .A(n1109), .B(n653), .Y(n1165) );
CLKXOR2X2TS U893 ( .A(n740), .B(n739), .Y(n1285) );
OAI21X2TS U894 ( .A0(n740), .A1(n736), .B0(n737), .Y(n767) );
INVX4TS U895 ( .A(n744), .Y(n751) );
NAND2X2TS U896 ( .A(n1712), .B(n954), .Y(n1144) );
NOR2X1TS U897 ( .A(n731), .B(n730), .Y(n736) );
NAND2X1TS U898 ( .A(n727), .B(n726), .Y(n741) );
AOI21X1TS U899 ( .A0(n696), .A1(n745), .B0(n722), .Y(n723) );
NOR2X4TS U900 ( .A(FSM_selector_B[1]), .B(n1692), .Y(n702) );
NOR2X1TS U901 ( .A(FS_Module_state_reg[3]), .B(n909), .Y(n954) );
NOR2X1TS U902 ( .A(n1444), .B(n1456), .Y(n838) );
NOR2X1TS U903 ( .A(n1402), .B(n1404), .Y(n816) );
NOR2X1TS U904 ( .A(n1366), .B(n1378), .Y(n1391) );
NAND2BX2TS U905 ( .AN(n1316), .B(n1317), .Y(n776) );
NAND2X1TS U906 ( .A(n844), .B(n843), .Y(n1481) );
INVX6TS U907 ( .A(n1281), .Y(n877) );
INVX4TS U908 ( .A(n1281), .Y(n821) );
XOR2X2TS U909 ( .A(n1201), .B(intDX[31]), .Y(n1174) );
OAI21XLTS U910 ( .A0(intDX[15]), .A1(n1660), .B0(intDX[14]), .Y(n1076) );
OAI21XLTS U911 ( .A0(n1471), .A1(n1481), .B0(n1472), .Y(n847) );
NOR2XLTS U912 ( .A(n1716), .B(n885), .Y(n827) );
NOR2XLTS U913 ( .A(n885), .B(n1742), .Y(n882) );
NOR2XLTS U914 ( .A(n1725), .B(n894), .Y(n866) );
NOR2XLTS U915 ( .A(n885), .B(n1717), .Y(n826) );
OAI21XLTS U916 ( .A0(intDX[23]), .A1(n1661), .B0(intDX[22]), .Y(n1096) );
XOR2X1TS U917 ( .A(n768), .B(n725), .Y(n727) );
XOR2X1TS U918 ( .A(n821), .B(n819), .Y(n830) );
NOR2XLTS U919 ( .A(n1555), .B(n1728), .Y(n969) );
NAND2X1TS U920 ( .A(n695), .B(n696), .Y(n724) );
OR2X1TS U921 ( .A(n907), .B(n1012), .Y(n657) );
OAI211XLTS U922 ( .A0(Add_Subt_result[25]), .A1(n789), .B0(n788), .C0(n787),
.Y(n790) );
CLKINVX3TS U923 ( .A(n690), .Y(n1139) );
NOR2XLTS U924 ( .A(n1352), .B(n1351), .Y(n1357) );
OAI211XLTS U925 ( .A0(n1317), .A1(n1316), .B0(n1315), .C0(n1314), .Y(n1319)
);
OAI211XLTS U926 ( .A0(n917), .A1(n1754), .B0(n916), .C0(n1640), .Y(n918) );
OR2X1TS U927 ( .A(n907), .B(n1017), .Y(n1274) );
OAI211XLTS U928 ( .A0(n917), .A1(n1755), .B0(n911), .C0(n1640), .Y(n912) );
OAI21XLTS U929 ( .A0(n1663), .A1(n1160), .B0(n1121), .Y(n121) );
OAI21XLTS U930 ( .A0(n1702), .A1(n1160), .B0(n1125), .Y(n178) );
OAI21XLTS U931 ( .A0(n1164), .A1(n1722), .B0(n1148), .Y(n88) );
OAI211XLTS U932 ( .A0(n1749), .A1(n658), .B0(n1024), .C0(n1023), .Y(n248) );
OAI21XLTS U933 ( .A0(n1666), .A1(n1160), .B0(n1136), .Y(n169) );
OAI211XLTS U934 ( .A0(n658), .A1(n1753), .B0(n1011), .C0(n1010), .Y(n27) );
OAI211XLTS U935 ( .A0(n1504), .A1(n1043), .B0(n1042), .C0(n1041), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[16]) );
OAI21XLTS U936 ( .A0(n1724), .A1(n1188), .B0(n1184), .Y(n119) );
CLKINVX3TS U937 ( .A(n1373), .Y(n1495) );
NAND4X1TS U938 ( .A(n1328), .B(n1299), .C(n1298), .D(n1297), .Y(n1300) );
AOI21X2TS U939 ( .A0(n751), .A1(n695), .B0(n745), .Y(n748) );
NAND2X1TS U940 ( .A(n738), .B(n737), .Y(n739) );
INVX2TS U941 ( .A(n746), .Y(n722) );
INVX2TS U942 ( .A(n765), .Y(n766) );
INVX2TS U943 ( .A(n736), .Y(n738) );
INVX4TS U944 ( .A(n1198), .Y(n1161) );
INVX4TS U945 ( .A(n690), .Y(n1147) );
INVX2TS U946 ( .A(n1375), .Y(n1376) );
INVX3TS U947 ( .A(n653), .Y(n1196) );
OAI21X1TS U948 ( .A0(n1334), .A1(n1759), .B0(n986), .Y(n70) );
INVX3TS U949 ( .A(n653), .Y(n1162) );
INVX3TS U950 ( .A(n653), .Y(n1128) );
INVX3TS U951 ( .A(n653), .Y(n1155) );
INVX3TS U952 ( .A(n653), .Y(n1190) );
INVX3TS U953 ( .A(n653), .Y(n1186) );
NAND2X4TS U954 ( .A(n1638), .B(n664), .Y(n907) );
XOR2X1TS U955 ( .A(n821), .B(n805), .Y(n812) );
NOR2X4TS U956 ( .A(n776), .B(Add_Subt_result[18]), .Y(n1306) );
INVX1TS U957 ( .A(n1174), .Y(n955) );
OAI211X1TS U958 ( .A0(intDX[8]), .A1(n1690), .B0(n1070), .C0(n1073), .Y(
n1084) );
NOR2X1TS U959 ( .A(n1103), .B(intDY[24]), .Y(n1044) );
NAND3X1TS U960 ( .A(n1690), .B(n1070), .C(intDX[8]), .Y(n1071) );
NOR2X1TS U961 ( .A(n1693), .B(n885), .Y(n828) );
MX2X2TS U962 ( .A(add_overflow_flag), .B(n1283), .S0(n661), .Y(n241) );
MX2X2TS U963 ( .A(Add_Subt_result[25]), .B(n900), .S0(n1450), .Y(n215) );
OAI2BB1X1TS U964 ( .A0N(n682), .A1N(n1334), .B0(n1321), .Y(n75) );
XOR2X2TS U965 ( .A(n770), .B(n769), .Y(n1209) );
OAI21X1TS U966 ( .A0(n1320), .A1(n1319), .B0(n1318), .Y(n1321) );
NAND3BX1TS U967 ( .AN(n1284), .B(n1206), .C(n1205), .Y(n1208) );
AOI21X2TS U968 ( .A0(n767), .A1(n691), .B0(n766), .Y(n770) );
OAI211X2TS U969 ( .A0(Add_Subt_result[3]), .A1(n780), .B0(n779), .C0(n1299),
.Y(n1320) );
XOR2X2TS U970 ( .A(n748), .B(n747), .Y(n1287) );
OAI21X1TS U971 ( .A0(n1164), .A1(n1703), .B0(n1151), .Y(n97) );
OAI21X1TS U972 ( .A0(n1164), .A1(n1706), .B0(n1153), .Y(n94) );
OAI21X1TS U973 ( .A0(n1164), .A1(n1705), .B0(n1152), .Y(n91) );
OAI21X1TS U974 ( .A0(n1703), .A1(n690), .B0(n1180), .Y(n98) );
OAI21X1TS U975 ( .A0(n1676), .A1(n690), .B0(n1193), .Y(n101) );
OAI21X1TS U976 ( .A0(n1667), .A1(n1192), .B0(n1131), .Y(n152) );
OAI21X1TS U977 ( .A0(n1663), .A1(n1188), .B0(n1167), .Y(n122) );
OAI21X1TS U978 ( .A0(n1670), .A1(n1188), .B0(n1126), .Y(n167) );
OAI21X1TS U979 ( .A0(n1669), .A1(n1188), .B0(n1143), .Y(n161) );
OAI21X1TS U980 ( .A0(n1722), .A1(n1188), .B0(n1182), .Y(n89) );
OAI21X1TS U981 ( .A0(n1719), .A1(n1202), .B0(n1133), .Y(n125) );
OAI211X1TS U982 ( .A0(n658), .A1(n1752), .B0(n1007), .C0(n1006), .Y(n19) );
OAI211X1TS U983 ( .A0(n1000), .A1(n1504), .B0(n1502), .C0(n995), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[23]) );
OAI21X1TS U984 ( .A0(n1704), .A1(n1188), .B0(n1173), .Y(n113) );
OAI21X1TS U985 ( .A0(n1028), .A1(n1605), .B0(n1027), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[21]) );
OAI21X1TS U986 ( .A0(n1665), .A1(n1188), .B0(n1127), .Y(n164) );
OAI21X1TS U987 ( .A0(n1705), .A1(n1198), .B0(n1181), .Y(n92) );
OAI21X1TS U988 ( .A0(n1673), .A1(n1188), .B0(n1187), .Y(n116) );
OAI21X1TS U989 ( .A0(n1718), .A1(n690), .B0(n1194), .Y(n107) );
OAI21X1TS U990 ( .A0(n1668), .A1(n1188), .B0(n1166), .Y(n155) );
OAI21X1TS U991 ( .A0(n1706), .A1(n690), .B0(n1185), .Y(n95) );
OAI21X1TS U992 ( .A0(n1695), .A1(n1141), .B0(n1113), .Y(n133) );
OAI21X1TS U993 ( .A0(n1698), .A1(n1192), .B0(n1170), .Y(n128) );
OAI21X1TS U994 ( .A0(n1733), .A1(n1141), .B0(n1140), .Y(n136) );
OAI21X1TS U995 ( .A0(n1666), .A1(n1192), .B0(n1142), .Y(n170) );
OAI21X1TS U996 ( .A0(n1699), .A1(n1141), .B0(n1112), .Y(n130) );
OAI21X1TS U997 ( .A0(n1669), .A1(n1160), .B0(n1137), .Y(n160) );
OAI21X1TS U998 ( .A0(n1700), .A1(n1198), .B0(n1132), .Y(n146) );
OAI21X1TS U999 ( .A0(n1699), .A1(n1192), .B0(n1171), .Y(n131) );
OAI21X1TS U1000 ( .A0(n1700), .A1(n1141), .B0(n1117), .Y(n145) );
OAI211X1TS U1001 ( .A0(n1043), .A1(n1508), .B0(n1031), .C0(n1030), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[19]) );
OAI21X1TS U1002 ( .A0(n1670), .A1(n1160), .B0(n1123), .Y(n166) );
OAI21X1TS U1003 ( .A0(n1702), .A1(n1192), .B0(n1129), .Y(n179) );
OAI21X1TS U1004 ( .A0(n1696), .A1(n1141), .B0(n1119), .Y(n139) );
OAI21X1TS U1005 ( .A0(n1697), .A1(n1198), .B0(n1168), .Y(n143) );
OAI21X1TS U1006 ( .A0(n1721), .A1(n1198), .B0(n1197), .Y(n104) );
OAI211X1TS U1007 ( .A0(n658), .A1(n1751), .B0(n1004), .C0(n1003), .Y(n23) );
OAI211X1TS U1008 ( .A0(n1043), .A1(n991), .B0(n1036), .C0(n1035), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[18]) );
OAI21X1TS U1009 ( .A0(n1719), .A1(n1192), .B0(n1183), .Y(n124) );
OAI21X1TS U1010 ( .A0(n1695), .A1(n1192), .B0(n1169), .Y(n134) );
OAI21X1TS U1011 ( .A0(n1723), .A1(n1192), .B0(n1145), .Y(n173) );
OAI21X1TS U1012 ( .A0(n1701), .A1(n1192), .B0(n1130), .Y(n176) );
OAI21X1TS U1013 ( .A0(n1671), .A1(n1202), .B0(n1135), .Y(n110) );
OAI21X1TS U1014 ( .A0(n1696), .A1(n1198), .B0(n1172), .Y(n140) );
OAI21X1TS U1015 ( .A0(n1664), .A1(n1188), .B0(n1156), .Y(n158) );
OAI21X1TS U1016 ( .A0(n1733), .A1(n1192), .B0(n1191), .Y(n137) );
OAI21X1TS U1017 ( .A0(n1464), .A1(n1426), .B0(n1425), .Y(n1431) );
NAND3X1TS U1018 ( .A(n1623), .B(n1622), .C(n1640), .Y(n21) );
OAI21X1TS U1019 ( .A0(n1659), .A1(n1198), .B0(n1110), .Y(n149) );
INVX2TS U1020 ( .A(n1146), .Y(n1164) );
OAI21X1TS U1021 ( .A0(n1403), .A1(n1402), .B0(n1401), .Y(n1408) );
OAI211X1TS U1022 ( .A0(n1636), .A1(n1229), .B0(n1228), .C0(n1227), .Y(n1230)
);
OAI211X1TS U1023 ( .A0(n1016), .A1(n907), .B0(n1015), .C0(n1014), .Y(n43) );
NAND3X1TS U1024 ( .A(n1642), .B(n1641), .C(n1640), .Y(n33) );
NAND3X1TS U1025 ( .A(n1618), .B(n1617), .C(n1640), .Y(n17) );
NAND3X1TS U1026 ( .A(n1628), .B(n1627), .C(n1640), .Y(n25) );
OAI21X1TS U1027 ( .A0(n1510), .A1(n1605), .B0(n1502), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[24]) );
OAI211X1TS U1028 ( .A0(n1021), .A1(n907), .B0(n1020), .C0(n1019), .Y(n47) );
OAI211X1TS U1029 ( .A0(n1638), .A1(n1717), .B0(n1252), .C0(n1251), .Y(n1253)
);
NAND3X1TS U1030 ( .A(n1633), .B(n1632), .C(n1640), .Y(n29) );
OAI211X1TS U1031 ( .A0(n658), .A1(n1748), .B0(n999), .C0(n998), .Y(n15) );
OAI211X1TS U1032 ( .A0(n1043), .A1(n1025), .B0(n984), .C0(n983), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[17]) );
NOR2X4TS U1033 ( .A(n710), .B(n709), .Y(n759) );
AOI32X2TS U1034 ( .A0(n1586), .A1(n1585), .A2(n1584), .B0(n1583), .B1(n1591),
.Y(n1601) );
AOI32X2TS U1035 ( .A0(n1578), .A1(n1585), .A2(n1577), .B0(n1576), .B1(n1591),
.Y(n1599) );
OAI211X1TS U1036 ( .A0(n1179), .A1(n1178), .B0(n1177), .C0(n1176), .Y(n242)
);
INVX2TS U1037 ( .A(n768), .Y(n769) );
NOR2X4TS U1038 ( .A(Add_Subt_result[10]), .B(n777), .Y(n1296) );
NOR2X1TS U1039 ( .A(n907), .B(n1619), .Y(n1002) );
NOR2X1TS U1040 ( .A(n907), .B(n1614), .Y(n1005) );
INVX1TS U1041 ( .A(n1344), .Y(n1352) );
NOR2X1TS U1042 ( .A(n907), .B(n1624), .Y(n1008) );
NOR2X4TS U1043 ( .A(n907), .B(n996), .Y(n1241) );
NAND2X1TS U1044 ( .A(n1391), .B(n816), .Y(n818) );
OR2X2TS U1045 ( .A(n1636), .B(n996), .Y(n658) );
OAI21X1TS U1046 ( .A0(n1508), .A1(n1605), .B0(n1038), .Y(n990) );
INVX3TS U1047 ( .A(n674), .Y(n676) );
NOR2X1TS U1048 ( .A(n1311), .B(n1310), .Y(n1304) );
NOR2X1TS U1049 ( .A(n1555), .B(Add_Subt_result[25]), .Y(n989) );
OAI21X1TS U1050 ( .A0(n1404), .A1(n1401), .B0(n1405), .Y(n815) );
NOR2X4TS U1051 ( .A(n1636), .B(n1012), .Y(n906) );
NOR2X1TS U1052 ( .A(n1555), .B(n1737), .Y(n980) );
NOR2X1TS U1053 ( .A(n664), .B(Add_Subt_result[0]), .Y(n988) );
OAI31XLTS U1054 ( .A0(FS_Module_state_reg[0]), .A1(FS_Module_state_reg[1]),
.A2(FS_Module_state_reg[3]), .B0(n956), .Y(n957) );
INVX3TS U1055 ( .A(n1500), .Y(n1594) );
AND2X2TS U1056 ( .A(n1638), .B(n905), .Y(n1237) );
INVX2TS U1057 ( .A(n1289), .Y(n1336) );
INVX3TS U1058 ( .A(n1500), .Y(n1608) );
INVX1TS U1059 ( .A(n954), .Y(n697) );
INVX4TS U1060 ( .A(n1144), .Y(n653) );
AO22X1TS U1061 ( .A0(LZA_output[4]), .A1(n702), .B0(n665), .B1(
exp_oper_result[4]), .Y(n656) );
INVX2TS U1062 ( .A(n960), .Y(n1651) );
AND2X2TS U1063 ( .A(n904), .B(n903), .Y(n905) );
NOR2X1TS U1064 ( .A(n1715), .B(n894), .Y(n853) );
NAND2BX1TS U1065 ( .AN(Sgf_normalized_result[25]), .B(n894), .Y(n1279) );
NAND2BX1TS U1066 ( .AN(n689), .B(intDX[27]), .Y(n1046) );
NOR2X1TS U1067 ( .A(n1740), .B(n894), .Y(n890) );
NAND3X1TS U1068 ( .A(n1707), .B(n1045), .C(intDX[26]), .Y(n1047) );
NOR2X1TS U1069 ( .A(n1068), .B(intDY[10]), .Y(n1069) );
NOR2X1TS U1070 ( .A(n885), .B(n1741), .Y(n886) );
AOI211X1TS U1071 ( .A0(intDY[28]), .A1(n1723), .B0(n1051), .C0(n1049), .Y(
n1102) );
NOR2X1TS U1072 ( .A(n885), .B(n1731), .Y(n876) );
NOR2X1TS U1073 ( .A(n1582), .B(FS_Module_state_reg[3]), .Y(n904) );
OAI211X2TS U1074 ( .A0(intDX[12]), .A1(n1719), .B0(n1080), .C0(n1066), .Y(
n1082) );
NOR2X1TS U1075 ( .A(n885), .B(n1732), .Y(n873) );
OAI211X2TS U1076 ( .A0(intDX[20]), .A1(n1685), .B0(n1100), .C0(n1085), .Y(
n1094) );
NOR2X1TS U1077 ( .A(n1714), .B(n894), .Y(n854) );
NOR2X1TS U1078 ( .A(n885), .B(n1726), .Y(n869) );
NOR2X1TS U1079 ( .A(n1713), .B(n894), .Y(n862) );
NAND2BX1TS U1080 ( .AN(n962), .B(n961), .Y(n963) );
NOR3X2TS U1081 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[1]), .C(
n962), .Y(n1217) );
OR2X2TS U1082 ( .A(n899), .B(FS_Module_state_reg[3]), .Y(n1373) );
NOR2X1TS U1083 ( .A(Add_Subt_result[9]), .B(Add_Subt_result[8]), .Y(n775) );
NAND2BX1TS U1084 ( .AN(intDX[21]), .B(intDY[21]), .Y(n1085) );
NAND2BX1TS U1085 ( .AN(intDX[19]), .B(intDY[19]), .Y(n1091) );
NAND2BX1TS U1086 ( .AN(intDX[27]), .B(intDY[27]), .Y(n1045) );
OR2X2TS U1087 ( .A(FSM_selector_B[1]), .B(FSM_selector_B[0]), .Y(n703) );
NAND2BX1TS U1088 ( .AN(intDX[24]), .B(intDY[24]), .Y(n1101) );
NOR2X1TS U1089 ( .A(r_mode[1]), .B(sign_final_result), .Y(n965) );
NAND2BX1TS U1090 ( .AN(intDX[9]), .B(intDY[9]), .Y(n1070) );
NAND2BX1TS U1091 ( .AN(intDX[13]), .B(intDY[13]), .Y(n1066) );
NOR3X1TS U1092 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[1]), .C(
FS_Module_state_reg[3]), .Y(n959) );
OR2X4TS U1093 ( .A(n1174), .B(n885), .Y(n1281) );
AOI21X2TS U1094 ( .A0(n1441), .A1(n838), .B0(n837), .Y(n1462) );
OAI21X1TS U1095 ( .A0(n1456), .A1(n1452), .B0(n1457), .Y(n837) );
XOR2X2TS U1096 ( .A(n1282), .B(n1281), .Y(n1283) );
NAND2X2TS U1097 ( .A(n1296), .B(n775), .Y(n783) );
NAND2X4TS U1098 ( .A(n1709), .B(n1302), .Y(n777) );
AOI31X1TS U1099 ( .A0(n1301), .A1(Add_Subt_result[0]), .A2(n1678), .B0(n1332), .Y(n779) );
NAND2X1TS U1100 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]),
.Y(n962) );
OAI2BB2XLTS U1101 ( .B0(intDY[12]), .B1(n1067), .A0N(intDX[13]), .A1N(n1686),
.Y(n1079) );
OAI2BB2XLTS U1102 ( .B0(n1075), .B1(n1082), .A0N(n1074), .A1N(n1073), .Y(
n1078) );
XOR2X1TS U1103 ( .A(n768), .B(n717), .Y(n721) );
AO22XLTS U1104 ( .A0(LZA_output[4]), .A1(n702), .B0(n666), .B1(DmP[27]), .Y(
n717) );
XOR2X1TS U1105 ( .A(n768), .B(n716), .Y(n719) );
AO22XLTS U1106 ( .A0(LZA_output[3]), .A1(n702), .B0(n666), .B1(DmP[26]), .Y(
n716) );
MX2X1TS U1107 ( .A(DMP[3]), .B(Sgf_normalized_result[5]), .S0(n825), .Y(n811) );
OAI21X2TS U1108 ( .A0(n1378), .A1(n1375), .B0(n1379), .Y(n1390) );
MX2X1TS U1109 ( .A(DMP[13]), .B(Sgf_normalized_result[15]), .S0(n878), .Y(
n855) );
INVX2TS U1110 ( .A(n741), .Y(n728) );
NAND2X1TS U1111 ( .A(n761), .B(n760), .Y(n763) );
INVX2TS U1112 ( .A(n759), .Y(n761) );
XNOR2X2TS U1113 ( .A(n756), .B(n755), .Y(n1290) );
NAND2X1TS U1114 ( .A(n754), .B(n753), .Y(n755) );
OAI21X1TS U1115 ( .A0(n762), .A1(n759), .B0(n760), .Y(n756) );
INVX2TS U1116 ( .A(n752), .Y(n754) );
NAND4XLTS U1117 ( .A(n933), .B(n932), .C(n931), .D(n930), .Y(n952) );
NAND4XLTS U1118 ( .A(n925), .B(n924), .C(n923), .D(n922), .Y(n953) );
NAND4XLTS U1119 ( .A(n941), .B(n940), .C(n939), .D(n938), .Y(n951) );
AOI2BB2XLTS U1120 ( .B0(intDX[3]), .B1(n1680), .A0N(intDY[2]), .A1N(n1059),
.Y(n1060) );
OAI21XLTS U1121 ( .A0(intDX[3]), .A1(n1680), .B0(intDX[2]), .Y(n1059) );
CLKXOR2X2TS U1122 ( .A(n768), .B(n704), .Y(n710) );
AO22XLTS U1123 ( .A0(LZA_output[1]), .A1(n702), .B0(n665), .B1(DmP[24]), .Y(
n704) );
MX2X1TS U1124 ( .A(DMP[24]), .B(exp_oper_result[1]), .S0(n891), .Y(n709) );
XOR2X1TS U1125 ( .A(n768), .B(n705), .Y(n712) );
AO22XLTS U1126 ( .A0(n682), .A1(n702), .B0(n666), .B1(DmP[25]), .Y(n705) );
MX2X1TS U1127 ( .A(DMP[25]), .B(exp_oper_result[2]), .S0(n891), .Y(n711) );
MX2X1TS U1128 ( .A(DMP[14]), .B(Sgf_normalized_result[16]), .S0(n878), .Y(
n857) );
MX2X1TS U1129 ( .A(DMP[16]), .B(Sgf_normalized_result[18]), .S0(n878), .Y(
n867) );
MX2X1TS U1130 ( .A(DMP[2]), .B(Sgf_normalized_result[4]), .S0(n825), .Y(n809) );
MX2X1TS U1131 ( .A(DMP[6]), .B(Sgf_normalized_result[8]), .S0(n825), .Y(n831) );
MX2X1TS U1132 ( .A(DMP[4]), .B(Sgf_normalized_result[6]), .S0(n825), .Y(n813) );
MX2X1TS U1133 ( .A(DMP[1]), .B(Sgf_normalized_result[3]), .S0(n825), .Y(n807) );
MX2X1TS U1134 ( .A(DMP[0]), .B(Sgf_normalized_result[2]), .S0(n825), .Y(n799) );
MX2X1TS U1135 ( .A(DMP[11]), .B(Sgf_normalized_result[13]), .S0(n878), .Y(
n843) );
MX2X1TS U1136 ( .A(DMP[8]), .B(Sgf_normalized_result[10]), .S0(n825), .Y(
n835) );
MX2X1TS U1137 ( .A(DMP[9]), .B(Sgf_normalized_result[11]), .S0(n825), .Y(
n839) );
MX2X1TS U1138 ( .A(DMP[5]), .B(Sgf_normalized_result[7]), .S0(n825), .Y(n829) );
MX2X1TS U1139 ( .A(DMP[7]), .B(Sgf_normalized_result[9]), .S0(n825), .Y(n833) );
MX2X1TS U1140 ( .A(DMP[17]), .B(Sgf_normalized_result[19]), .S0(n878), .Y(
n870) );
MX2X1TS U1141 ( .A(DMP[15]), .B(Sgf_normalized_result[17]), .S0(n878), .Y(
n863) );
NAND3X1TS U1142 ( .A(n1327), .B(n1662), .C(n1691), .Y(n1329) );
AOI32X1TS U1143 ( .A0(n1108), .A1(n1107), .A2(n1106), .B0(n1105), .B1(n1108),
.Y(n1109) );
AOI2BB2X1TS U1144 ( .B0(n1053), .B1(n1102), .A0N(n1052), .A1N(n1051), .Y(
n1108) );
INVX2TS U1145 ( .A(n1165), .Y(n1141) );
NAND2BXLTS U1146 ( .AN(Add_Subt_result[6]), .B(n1736), .Y(n1293) );
INVX2TS U1147 ( .A(n1165), .Y(n1160) );
CLKAND2X2TS U1148 ( .A(n891), .B(Sgf_normalized_result[0]), .Y(n797) );
OR2X1TS U1149 ( .A(n858), .B(n857), .Y(n1436) );
AO22XLTS U1150 ( .A0(n1603), .A1(Add_Subt_result[4]), .B0(DmP[19]), .B1(
n1727), .Y(n977) );
CLKAND2X2TS U1151 ( .A(n1179), .B(n1217), .Y(n1211) );
CLKAND2X2TS U1152 ( .A(n967), .B(Sgf_normalized_result[1]), .Y(n793) );
OR2X1TS U1153 ( .A(n888), .B(n887), .Y(n1347) );
OR2X1TS U1154 ( .A(n880), .B(n879), .Y(n1370) );
INVX2TS U1155 ( .A(n1237), .Y(n1636) );
OR2X1TS U1156 ( .A(n864), .B(n863), .Y(n1421) );
NOR2BX2TS U1157 ( .AN(n1306), .B(n1305), .Y(n1327) );
INVX2TS U1158 ( .A(n776), .Y(n1323) );
MX2X1TS U1159 ( .A(DMP[23]), .B(exp_oper_result[0]), .S0(n891), .Y(n758) );
AO21XLTS U1160 ( .A0(DmP[23]), .A1(n1692), .B0(n972), .Y(n708) );
NAND2X1TS U1161 ( .A(n695), .B(n749), .Y(n750) );
NAND2X1TS U1162 ( .A(n696), .B(n746), .Y(n747) );
XNOR2X2TS U1163 ( .A(n743), .B(n742), .Y(n1286) );
NAND2X1TS U1164 ( .A(n692), .B(n741), .Y(n742) );
XNOR2X2TS U1165 ( .A(n767), .B(n735), .Y(n1284) );
INVX2TS U1166 ( .A(n783), .Y(n1294) );
NOR2X2TS U1167 ( .A(Add_Subt_result[11]), .B(n1329), .Y(n1302) );
NAND2X1TS U1168 ( .A(n1324), .B(n1326), .Y(n1316) );
BUFX3TS U1169 ( .A(n1165), .Y(n1189) );
BUFX3TS U1170 ( .A(n1165), .Y(n1146) );
AOI2BB2XLTS U1171 ( .B0(intDX[31]), .B1(n653), .A0N(n1199), .A1N(n1198), .Y(
n1200) );
MX2X1TS U1172 ( .A(Add_Subt_result[5]), .B(n1395), .S0(n661), .Y(n221) );
MX2X1TS U1173 ( .A(Add_Subt_result[15]), .B(n1451), .S0(n1495), .Y(n231) );
MX2X1TS U1174 ( .A(Add_Subt_result[12]), .B(n1496), .S0(n1495), .Y(n228) );
NAND2BXLTS U1175 ( .AN(intDX[2]), .B(intDY[2]), .Y(n1057) );
NAND2BXLTS U1176 ( .AN(intDY[9]), .B(intDX[9]), .Y(n1072) );
NOR2X1TS U1177 ( .A(n1469), .B(n1471), .Y(n848) );
XOR2X1TS U1178 ( .A(n768), .B(n729), .Y(n731) );
CLKAND2X2TS U1179 ( .A(n666), .B(DmP[29]), .Y(n729) );
MX2X1TS U1180 ( .A(DMP[29]), .B(exp_oper_result[6]), .S0(n891), .Y(n730) );
MX2X1TS U1181 ( .A(DMP[27]), .B(exp_oper_result[4]), .S0(n891), .Y(n720) );
MX2X1TS U1182 ( .A(DMP[26]), .B(exp_oper_result[3]), .S0(n891), .Y(n718) );
NOR2X1TS U1183 ( .A(n759), .B(n752), .Y(n715) );
OAI21X1TS U1184 ( .A0(n752), .A1(n760), .B0(n753), .Y(n713) );
CLKAND2X2TS U1185 ( .A(n666), .B(DmP[28]), .Y(n725) );
MX2X1TS U1186 ( .A(DMP[28]), .B(exp_oper_result[5]), .S0(n891), .Y(n726) );
XOR2X1TS U1187 ( .A(n768), .B(n732), .Y(n734) );
CLKAND2X2TS U1188 ( .A(n666), .B(DmP[30]), .Y(n732) );
MX2X1TS U1189 ( .A(DMP[30]), .B(exp_oper_result[7]), .S0(n891), .Y(n733) );
OAI21XLTS U1190 ( .A0(intDX[21]), .A1(n1708), .B0(intDX[20]), .Y(n1088) );
NAND3BX1TS U1191 ( .AN(n1089), .B(n1087), .C(n1086), .Y(n1107) );
MX2X1TS U1192 ( .A(DMP[20]), .B(Sgf_normalized_result[22]), .S0(n894), .Y(
n883) );
AO22XLTS U1193 ( .A0(n1603), .A1(Add_Subt_result[8]), .B0(DmP[15]), .B1(
n1560), .Y(n976) );
MX2X1TS U1194 ( .A(DMP[18]), .B(Sgf_normalized_result[20]), .S0(n878), .Y(
n874) );
MX2X1TS U1195 ( .A(DMP[12]), .B(Sgf_normalized_result[14]), .S0(n878), .Y(
n845) );
NOR2X1TS U1196 ( .A(n1477), .B(n1490), .Y(n1465) );
NAND2X1TS U1197 ( .A(n1440), .B(n838), .Y(n1463) );
MX2X1TS U1198 ( .A(DMP[10]), .B(Sgf_normalized_result[12]), .S0(n878), .Y(
n841) );
MX2X1TS U1199 ( .A(DMP[21]), .B(Sgf_normalized_result[23]), .S0(
FSM_selector_D), .Y(n887) );
MX2X1TS U1200 ( .A(DMP[19]), .B(Sgf_normalized_result[21]), .S0(n878), .Y(
n879) );
MX2X1TS U1201 ( .A(DMP[22]), .B(Sgf_normalized_result[24]), .S0(n891), .Y(
n892) );
AO22XLTS U1202 ( .A0(n1603), .A1(Add_Subt_result[13]), .B0(DmP[10]), .B1(
n1560), .Y(n1528) );
AO22XLTS U1203 ( .A0(n1603), .A1(Add_Subt_result[12]), .B0(DmP[11]), .B1(
n1560), .Y(n1523) );
NOR2X2TS U1204 ( .A(n712), .B(n711), .Y(n752) );
NAND2X2TS U1205 ( .A(n710), .B(n709), .Y(n760) );
NAND2X1TS U1206 ( .A(n712), .B(n711), .Y(n753) );
NAND2X1TS U1207 ( .A(n719), .B(n718), .Y(n749) );
NAND2X1TS U1208 ( .A(n731), .B(n730), .Y(n737) );
NAND2X1TS U1209 ( .A(n721), .B(n720), .Y(n746) );
INVX2TS U1210 ( .A(n749), .Y(n745) );
NAND2X1TS U1211 ( .A(n734), .B(n733), .Y(n765) );
AO22XLTS U1212 ( .A0(n670), .A1(Add_Subt_result[17]), .B0(DmP[6]), .B1(n1727), .Y(n1549) );
AO22XLTS U1213 ( .A0(n670), .A1(Add_Subt_result[20]), .B0(DmP[3]), .B1(n1727), .Y(n1566) );
NAND4XLTS U1214 ( .A(n949), .B(n948), .C(n947), .D(n946), .Y(n950) );
AO22XLTS U1215 ( .A0(n1603), .A1(Add_Subt_result[5]), .B0(DmP[18]), .B1(
n1727), .Y(n978) );
AOI222X1TS U1216 ( .A0(n1039), .A1(n1038), .B0(n1590), .B1(n1499), .C0(n1498), .C1(n687), .Y(n1510) );
INVX2TS U1217 ( .A(n1651), .Y(n1269) );
AO22XLTS U1218 ( .A0(n670), .A1(Add_Subt_result[21]), .B0(DmP[2]), .B1(n1727), .Y(n1571) );
AOI2BB1XLTS U1219 ( .A0N(n784), .A1N(Add_Subt_result[23]), .B0(
Add_Subt_result[24]), .Y(n789) );
NAND3XLTS U1220 ( .A(n1323), .B(Add_Subt_result[16]), .C(n1750), .Y(n787) );
CLKAND2X2TS U1221 ( .A(Add_Subt_result[8]), .B(n1738), .Y(n782) );
NAND3XLTS U1222 ( .A(n1652), .B(n1214), .C(n1213), .Y(n247) );
AOI211XLTS U1223 ( .A0(FS_Module_state_reg[1]), .A1(n1215), .B0(n1211), .C0(
n1216), .Y(n1214) );
NAND4XLTS U1224 ( .A(n1261), .B(n1260), .C(n1259), .D(n1258), .Y(n51) );
NAND4XLTS U1225 ( .A(n1261), .B(n1257), .C(n1256), .D(n1255), .Y(n55) );
MX2X1TS U1226 ( .A(Data_X[0]), .B(intDX[0]), .S0(n1652), .Y(n183) );
MX2X1TS U1227 ( .A(Add_Subt_result[22]), .B(n1364), .S0(n661), .Y(n238) );
AO22XLTS U1228 ( .A0(n1653), .A1(Data_Y[0]), .B0(n1650), .B1(intDY[0]), .Y(
n90) );
AO22XLTS U1229 ( .A0(n1647), .A1(Data_Y[9]), .B0(n1269), .B1(intDY[9]), .Y(
n117) );
AO22XLTS U1230 ( .A0(n1647), .A1(Data_Y[4]), .B0(n1646), .B1(intDY[4]), .Y(
n102) );
OAI21XLTS U1231 ( .A0(n1164), .A1(n1673), .B0(n1154), .Y(n115) );
OAI21XLTS U1232 ( .A0(n1164), .A1(n1704), .B0(n1150), .Y(n112) );
MX2X1TS U1233 ( .A(n1300), .B(LZA_output[4]), .S0(n1334), .Y(n72) );
OAI21XLTS U1234 ( .A0(n1665), .A1(n1160), .B0(n1122), .Y(n163) );
OAI21XLTS U1235 ( .A0(n1664), .A1(n1160), .B0(n1120), .Y(n157) );
AO21XLTS U1236 ( .A0(n1022), .A1(n1237), .B0(n918), .Y(n12) );
AO21XLTS U1237 ( .A0(LZA_output[3]), .A1(n1334), .B0(n1309), .Y(n76) );
MX2X1TS U1238 ( .A(exp_oper_result[6]), .B(n1285), .S0(n1289), .Y(n85) );
MX2X1TS U1239 ( .A(exp_oper_result[5]), .B(n1286), .S0(n1289), .Y(n84) );
MX2X1TS U1240 ( .A(exp_oper_result[7]), .B(n1284), .S0(n1289), .Y(n78) );
NAND4XLTS U1241 ( .A(n1265), .B(n1264), .C(n1263), .D(n1274), .Y(n39) );
NAND4XLTS U1242 ( .A(n1268), .B(n1267), .C(n1266), .D(n1274), .Y(n35) );
NAND4XLTS U1243 ( .A(n1277), .B(n1276), .C(n1275), .D(n1274), .Y(n31) );
MX2X1TS U1244 ( .A(exp_oper_result[2]), .B(n1290), .S0(n1289), .Y(n81) );
MX2X1TS U1245 ( .A(n1291), .B(exp_oper_result[1]), .S0(n1336), .Y(n80) );
MX2X1TS U1246 ( .A(n1337), .B(exp_oper_result[0]), .S0(n1336), .Y(n79) );
MX2X1TS U1247 ( .A(exp_oper_result[3]), .B(n1288), .S0(n1289), .Y(n82) );
MX2X1TS U1248 ( .A(Data_X[1]), .B(intDX[1]), .S0(n1648), .Y(n184) );
MX2X1TS U1249 ( .A(exp_oper_result[4]), .B(n1287), .S0(n1289), .Y(n83) );
AO22XLTS U1250 ( .A0(n1647), .A1(Data_Y[3]), .B0(n1269), .B1(intDY[3]), .Y(
n99) );
AO22XLTS U1251 ( .A0(n1647), .A1(Data_Y[1]), .B0(n1648), .B1(intDY[1]), .Y(
n93) );
MX2X1TS U1252 ( .A(Add_Subt_result[0]), .B(n1224), .S0(n1495), .Y(n216) );
MX2X1TS U1253 ( .A(Add_Subt_result[16]), .B(n1439), .S0(n661), .Y(n232) );
MX2X1TS U1254 ( .A(Add_Subt_result[18]), .B(n1415), .S0(n661), .Y(n234) );
MX2X1TS U1255 ( .A(Add_Subt_result[4]), .B(n1383), .S0(n1450), .Y(n220) );
MX2X1TS U1256 ( .A(Add_Subt_result[20]), .B(n1389), .S0(n1450), .Y(n236) );
MX2X1TS U1257 ( .A(Add_Subt_result[8]), .B(n1432), .S0(n1495), .Y(n224) );
MX2X1TS U1258 ( .A(Add_Subt_result[6]), .B(n1409), .S0(n1495), .Y(n222) );
AO22XLTS U1259 ( .A0(n1647), .A1(Data_Y[10]), .B0(n1646), .B1(intDY[10]),
.Y(n120) );
AO22XLTS U1260 ( .A0(n1651), .A1(Data_Y[2]), .B0(n1652), .B1(intDY[2]), .Y(
n96) );
AO22XLTS U1261 ( .A0(n1653), .A1(Data_X[12]), .B0(n1652), .B1(intDX[12]),
.Y(n195) );
AO22XLTS U1262 ( .A0(n1649), .A1(Data_Y[16]), .B0(n1646), .B1(intDY[16]),
.Y(n138) );
AO22XLTS U1263 ( .A0(n1653), .A1(Data_Y[24]), .B0(n1646), .B1(intDY[24]),
.Y(n162) );
AO22XLTS U1264 ( .A0(n1647), .A1(Data_Y[6]), .B0(n1648), .B1(intDY[6]), .Y(
n108) );
AO22XLTS U1265 ( .A0(n1653), .A1(Data_Y[28]), .B0(n1646), .B1(intDY[28]),
.Y(n174) );
MX2X1TS U1266 ( .A(Add_Subt_result[3]), .B(n1368), .S0(n1495), .Y(n219) );
AO22XLTS U1267 ( .A0(n1647), .A1(Data_Y[5]), .B0(n1650), .B1(intDY[5]), .Y(
n105) );
OR2X1TS U1268 ( .A(n1211), .B(n967), .Y(n245) );
MX2X1TS U1269 ( .A(Data_X[31]), .B(intDX[31]), .S0(n1646), .Y(n182) );
MX2X1TS U1270 ( .A(add_subt), .B(intAS), .S0(n1269), .Y(n181) );
AO22XLTS U1271 ( .A0(n1649), .A1(Data_Y[13]), .B0(n1648), .B1(intDY[13]),
.Y(n129) );
MX2X1TS U1272 ( .A(Data_X[3]), .B(intDX[3]), .S0(n1648), .Y(n186) );
AO22XLTS U1273 ( .A0(final_result_ieee[6]), .A1(n1203), .B0(
Sgf_normalized_result[8]), .B1(n1497), .Y(n1744) );
AO22XLTS U1274 ( .A0(final_result_ieee[7]), .A1(n1643), .B0(
Sgf_normalized_result[9]), .B1(n1497), .Y(n1745) );
AO22XLTS U1275 ( .A0(final_result_ieee[8]), .A1(n1203), .B0(
Sgf_normalized_result[10]), .B1(n1497), .Y(n1746) );
AO22XLTS U1276 ( .A0(final_result_ieee[9]), .A1(n1643), .B0(
Sgf_normalized_result[11]), .B1(n1497), .Y(n1747) );
AO22XLTS U1277 ( .A0(Sgf_normalized_result[2]), .A1(n1497), .B0(
final_result_ieee[0]), .B1(n1203), .Y(n18) );
AO22XLTS U1278 ( .A0(n1203), .A1(final_result_ieee[1]), .B0(
Sgf_normalized_result[3]), .B1(n1497), .Y(n22) );
AO22XLTS U1279 ( .A0(n1643), .A1(final_result_ieee[2]), .B0(
Sgf_normalized_result[4]), .B1(n1497), .Y(n26) );
AO22XLTS U1280 ( .A0(n1203), .A1(final_result_ieee[3]), .B0(
Sgf_normalized_result[5]), .B1(n1497), .Y(n30) );
AO22XLTS U1281 ( .A0(n1643), .A1(final_result_ieee[4]), .B0(
Sgf_normalized_result[6]), .B1(n1497), .Y(n34) );
AO22XLTS U1282 ( .A0(n1643), .A1(final_result_ieee[5]), .B0(
Sgf_normalized_result[7]), .B1(n1497), .Y(n38) );
OAI2BB2XLTS U1283 ( .B0(n1725), .B1(n672), .A0N(final_result_ieee[16]),
.A1N(n1203), .Y(n36) );
OAI2BB2XLTS U1284 ( .B0(n1713), .B1(n673), .A0N(final_result_ieee[15]),
.A1N(n1643), .Y(n40) );
OAI2BB2XLTS U1285 ( .B0(n1714), .B1(n672), .A0N(final_result_ieee[14]),
.A1N(n1203), .Y(n44) );
OAI2BB2XLTS U1286 ( .B0(n1715), .B1(n673), .A0N(final_result_ieee[13]),
.A1N(n1643), .Y(n48) );
AO22XLTS U1287 ( .A0(n1644), .A1(n964), .B0(n1629), .B1(
final_result_ieee[31]), .Y(n68) );
AO22XLTS U1288 ( .A0(n1649), .A1(Data_Y[15]), .B0(n1269), .B1(intDY[15]),
.Y(n135) );
AO22XLTS U1289 ( .A0(n1653), .A1(Data_Y[23]), .B0(n1652), .B1(intDY[23]),
.Y(n159) );
AO22XLTS U1290 ( .A0(n1649), .A1(Data_Y[19]), .B0(n1650), .B1(intDY[19]),
.Y(n147) );
MX2X1TS U1291 ( .A(Data_X[9]), .B(intDX[9]), .S0(n1269), .Y(n192) );
AO22XLTS U1292 ( .A0(n1653), .A1(Data_Y[29]), .B0(n1650), .B1(intDY[29]),
.Y(n177) );
MX2X1TS U1293 ( .A(Data_X[7]), .B(intDX[7]), .S0(n1650), .Y(n190) );
OAI21XLTS U1294 ( .A0(n1373), .A1(FS_Module_state_reg[0]), .B0(n1560), .Y(
n243) );
MX2X1TS U1295 ( .A(Data_X[4]), .B(intDX[4]), .S0(n1269), .Y(n187) );
MX2X1TS U1296 ( .A(Add_Subt_result[2]), .B(n1358), .S0(n1495), .Y(n218) );
MX2X1TS U1297 ( .A(Add_Subt_result[1]), .B(n1345), .S0(n662), .Y(n217) );
AO22XLTS U1298 ( .A0(n1649), .A1(Data_Y[14]), .B0(n1652), .B1(intDY[14]),
.Y(n132) );
AO22XLTS U1299 ( .A0(n1647), .A1(Data_Y[11]), .B0(n1650), .B1(intDY[11]),
.Y(n123) );
AO22XLTS U1300 ( .A0(n1649), .A1(Data_Y[22]), .B0(n1269), .B1(intDY[22]),
.Y(n156) );
AO22XLTS U1301 ( .A0(n1649), .A1(Data_Y[20]), .B0(n1648), .B1(intDY[20]),
.Y(n150) );
AO22XLTS U1302 ( .A0(n1653), .A1(Data_Y[25]), .B0(n1269), .B1(intDY[25]),
.Y(n165) );
AO22XLTS U1303 ( .A0(n1649), .A1(Data_Y[17]), .B0(n1650), .B1(intDY[17]),
.Y(n141) );
AO22XLTS U1304 ( .A0(n1647), .A1(Data_Y[8]), .B0(n1652), .B1(intDY[8]), .Y(
n114) );
MX2X1TS U1305 ( .A(Add_Subt_result[13]), .B(n1485), .S0(n661), .Y(n229) );
NAND4XLTS U1306 ( .A(n1261), .B(n1247), .C(n1246), .D(n1245), .Y(n53) );
MX2X1TS U1307 ( .A(Data_X[8]), .B(intDX[8]), .S0(n1650), .Y(n191) );
MX2X1TS U1308 ( .A(Data_X[2]), .B(intDX[2]), .S0(n1650), .Y(n185) );
AO22XLTS U1309 ( .A0(n1653), .A1(Data_Y[26]), .B0(n1648), .B1(intDY[26]),
.Y(n168) );
AO22XLTS U1310 ( .A0(n1649), .A1(Data_Y[21]), .B0(n1652), .B1(intDY[21]),
.Y(n153) );
AO22XLTS U1311 ( .A0(n1653), .A1(Data_Y[30]), .B0(n1648), .B1(intDY[30]),
.Y(n180) );
AO22XLTS U1312 ( .A0(n1649), .A1(Data_Y[18]), .B0(n1646), .B1(intDY[18]),
.Y(n144) );
NAND4XLTS U1313 ( .A(n1261), .B(n1235), .C(n1234), .D(n1233), .Y(n41) );
NAND4XLTS U1314 ( .A(n1261), .B(n1240), .C(n1239), .D(n1238), .Y(n45) );
NAND4XLTS U1315 ( .A(n1261), .B(n1244), .C(n1243), .D(n1242), .Y(n49) );
NAND4XLTS U1316 ( .A(n1261), .B(n1250), .C(n1249), .D(n1248), .Y(n57) );
MX2X1TS U1317 ( .A(Data_X[6]), .B(intDX[6]), .S0(n1648), .Y(n189) );
MX2X1TS U1318 ( .A(Data_X[5]), .B(intDX[5]), .S0(n1652), .Y(n188) );
AO21XLTS U1319 ( .A0(n906), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(n1230), .Y(n37)
);
MX2X1TS U1320 ( .A(Add_Subt_result[23]), .B(n1350), .S0(n662), .Y(n239) );
MX2X1TS U1321 ( .A(Add_Subt_result[10]), .B(n1461), .S0(n1495), .Y(n226) );
MX2X1TS U1322 ( .A(Add_Subt_result[11]), .B(n1480), .S0(n662), .Y(n227) );
MX2X1TS U1323 ( .A(Add_Subt_result[21]), .B(n1374), .S0(n1450), .Y(n237) );
MX2X1TS U1324 ( .A(Add_Subt_result[7]), .B(n1419), .S0(n662), .Y(n223) );
MX2X1TS U1325 ( .A(Add_Subt_result[24]), .B(n1343), .S0(n662), .Y(n240) );
MX2X1TS U1326 ( .A(Add_Subt_result[9]), .B(n1446), .S0(n662), .Y(n225) );
MX2X1TS U1327 ( .A(Add_Subt_result[19]), .B(n1400), .S0(n1450), .Y(n235) );
AO21XLTS U1328 ( .A0(n997), .A1(n1237), .B0(n912), .Y(n14) );
MX2X1TS U1329 ( .A(Add_Subt_result[17]), .B(n1424), .S0(n1450), .Y(n233) );
AND3X1TS U1330 ( .A(n1323), .B(n1322), .C(Add_Subt_result[15]), .Y(n1333) );
AO22XLTS U1331 ( .A0(n1327), .A1(Add_Subt_result[14]), .B0(n1326), .B1(n1325), .Y(n1331) );
AOI21X1TS U1332 ( .A0(n1284), .A1(n771), .B0(n1209), .Y(n773) );
AOI2BB2X1TS U1333 ( .B0(n1757), .B1(n1334), .A0N(n1320), .A1N(n792), .Y(n73)
);
NAND2BX1TS U1334 ( .AN(n693), .B(n791), .Y(n792) );
AO21XLTS U1335 ( .A0(n1302), .A1(n782), .B0(n781), .Y(n693) );
AOI31XLTS U1336 ( .A0(Add_Subt_result[6]), .A1(n1294), .A2(n1736), .B0(n790),
.Y(n791) );
AO21XLTS U1337 ( .A0(n1311), .A1(n1709), .B0(n1310), .Y(n1315) );
MX2X1TS U1338 ( .A(Data_Y[31]), .B(intDY[31]), .S0(n1646), .Y(n87) );
AO22XLTS U1339 ( .A0(n1653), .A1(Data_Y[27]), .B0(n1646), .B1(n689), .Y(n171) );
AOI2BB1XLTS U1340 ( .A0N(n958), .A1N(n957), .B0(n1215), .Y(n214) );
NAND4BXLTS U1341 ( .AN(n1221), .B(n1220), .C(n1336), .D(n1219), .Y(n246) );
AOI211XLTS U1342 ( .A0(n1218), .A1(n655), .B0(n1217), .C0(n1216), .Y(n1219)
);
XOR2X1TS U1343 ( .A(n768), .B(n708), .Y(n757) );
NAND2X4TS U1344 ( .A(n1210), .B(n908), .Y(n1638) );
INVX2TS U1345 ( .A(n1555), .Y(n1604) );
INVX2TS U1346 ( .A(n663), .Y(n1603) );
BUFX3TS U1347 ( .A(n690), .Y(n1198) );
INVX2TS U1348 ( .A(n1025), .Y(n1602) );
NOR3X2TS U1349 ( .A(overflow_flag), .B(underflow_flag), .C(n1629), .Y(n659)
);
INVX2TS U1350 ( .A(n1373), .Y(n661) );
INVX2TS U1351 ( .A(n1373), .Y(n662) );
INVX2TS U1352 ( .A(n905), .Y(n663) );
INVX2TS U1353 ( .A(n905), .Y(n664) );
INVX2TS U1354 ( .A(n703), .Y(n665) );
INVX2TS U1355 ( .A(n703), .Y(n666) );
INVX2TS U1356 ( .A(n657), .Y(n667) );
INVX2TS U1357 ( .A(n657), .Y(n668) );
INVX2TS U1358 ( .A(n1555), .Y(n669) );
INVX2TS U1359 ( .A(n663), .Y(n670) );
INVX2TS U1360 ( .A(n659), .Y(n671) );
INVX2TS U1361 ( .A(n659), .Y(n672) );
INVX2TS U1362 ( .A(n659), .Y(n673) );
INVX2TS U1363 ( .A(n1272), .Y(n674) );
INVX2TS U1364 ( .A(n674), .Y(n675) );
AOI211X1TS U1365 ( .A0(n1218), .A1(n1212), .B0(n1217), .C0(n1175), .Y(n956)
);
AOI211X1TS U1366 ( .A0(n1306), .A1(n1305), .B0(n1304), .C0(n1303), .Y(n1307)
);
OAI21XLTS U1367 ( .A0(n1697), .A1(n1141), .B0(n1111), .Y(n142) );
OAI21XLTS U1368 ( .A0(n1659), .A1(n1141), .B0(n1118), .Y(n148) );
OAI21XLTS U1369 ( .A0(n1667), .A1(n1141), .B0(n1116), .Y(n151) );
OAI21XLTS U1370 ( .A0(n1668), .A1(n1141), .B0(n1115), .Y(n154) );
OAI21XLTS U1371 ( .A0(n1723), .A1(n1160), .B0(n1138), .Y(n172) );
OAI21XLTS U1372 ( .A0(n1701), .A1(n1160), .B0(n1124), .Y(n175) );
INVX2TS U1373 ( .A(n660), .Y(n677) );
OAI21XLTS U1374 ( .A0(n1164), .A1(n1676), .B0(n1158), .Y(n100) );
OAI21XLTS U1375 ( .A0(n1164), .A1(n1721), .B0(n1163), .Y(n103) );
OAI21XLTS U1376 ( .A0(n1160), .A1(n1718), .B0(n1159), .Y(n106) );
OAI21XLTS U1377 ( .A0(n1164), .A1(n1675), .B0(n1149), .Y(n109) );
OAI21XLTS U1378 ( .A0(n1164), .A1(n1724), .B0(n1157), .Y(n118) );
INVX2TS U1379 ( .A(n1602), .Y(n678) );
INVX2TS U1380 ( .A(n678), .Y(n679) );
INVX2TS U1381 ( .A(n678), .Y(n680) );
BUFX3TS U1382 ( .A(n1782), .Y(n1781) );
AOI221X1TS U1383 ( .A0(n1670), .A1(intDY[26]), .B0(intDY[1]), .B1(n1705),
.C0(n936), .Y(n939) );
AOI221X1TS U1384 ( .A0(n1701), .A1(intDY[29]), .B0(n689), .B1(n1666), .C0(
n927), .Y(n932) );
MXI2X1TS U1385 ( .A(n1760), .B(n773), .S0(n1289), .Y(n77) );
INVX2TS U1386 ( .A(n656), .Y(n681) );
OA21X2TS U1387 ( .A0(n1175), .A1(n1207), .B0(add_overflow_flag), .Y(n1038)
);
OAI21X2TS U1388 ( .A0(n1210), .A1(n1560), .B0(n908), .Y(n1175) );
NOR2X2TS U1389 ( .A(n989), .B(n988), .Y(n1499) );
OAI22X2TS U1390 ( .A0(n910), .A1(n1582), .B0(n962), .B1(n909), .Y(n1207) );
NAND2X1TS U1391 ( .A(n700), .B(n1712), .Y(n910) );
INVX2TS U1392 ( .A(n1504), .Y(n1600) );
BUFX3TS U1393 ( .A(n1781), .Y(n1786) );
BUFX3TS U1394 ( .A(n1790), .Y(n1780) );
INVX2TS U1395 ( .A(n654), .Y(n682) );
INVX2TS U1396 ( .A(n658), .Y(n683) );
INVX2TS U1397 ( .A(n658), .Y(n684) );
INVX2TS U1398 ( .A(n658), .Y(n685) );
AOI22X2TS U1399 ( .A0(n1608), .A1(n1507), .B0(n1026), .B1(n1605), .Y(n1034)
);
AOI22X2TS U1400 ( .A0(n1608), .A1(n1509), .B0(n992), .B1(n1500), .Y(n1032)
);
AOI22X2TS U1401 ( .A0(n1608), .A1(n1524), .B0(n1507), .B1(n1605), .Y(n1520)
);
AOI21X2TS U1402 ( .A0(n669), .A1(Add_Subt_result[21]), .B0(n977), .Y(n1507)
);
AOI221X1TS U1403 ( .A0(n1722), .A1(intDY[0]), .B0(intDY[28]), .B1(n1723),
.C0(n937), .Y(n938) );
OAI31X1TS U1404 ( .A0(Add_Subt_result[5]), .A1(Add_Subt_result[9]), .A2(
Add_Subt_result[8]), .B0(n1296), .Y(n1297) );
NAND2BX2TS U1405 ( .AN(Add_Subt_result[5]), .B(n1313), .Y(n778) );
AOI221X1TS U1406 ( .A0(n1706), .A1(intDY[2]), .B0(intDY[9]), .B1(n1673),
.C0(n944), .Y(n947) );
AOI222X1TS U1407 ( .A0(intDY[4]), .A1(n1676), .B0(n1061), .B1(n1060), .C0(
intDY[5]), .C1(n1721), .Y(n1063) );
AOI221X1TS U1408 ( .A0(n1676), .A1(intDY[4]), .B0(intDY[3]), .B1(n1703),
.C0(n935), .Y(n940) );
OAI21XLTS U1409 ( .A0(n1698), .A1(n1141), .B0(n1114), .Y(n127) );
NOR2X2TS U1410 ( .A(n832), .B(n831), .Y(n1427) );
AOI211X1TS U1411 ( .A0(intDY[16]), .A1(n1733), .B0(n1094), .C0(n1095), .Y(
n1086) );
NOR2X4TS U1412 ( .A(n655), .B(FS_Module_state_reg[2]), .Y(n1212) );
BUFX3TS U1413 ( .A(n1790), .Y(n1782) );
OAI21XLTS U1414 ( .A0(n1215), .A1(n1212), .B0(FS_Module_state_reg[3]), .Y(
n1177) );
OAI22X2TS U1415 ( .A0(beg_FSM), .A1(n244), .B0(ack_FSM), .B1(n987), .Y(n1215) );
BUFX3TS U1416 ( .A(n975), .Y(n686) );
BUFX3TS U1417 ( .A(n975), .Y(n687) );
AOI22X2TS U1418 ( .A0(LZA_output[1]), .A1(n702), .B0(n666), .B1(
exp_oper_result[1]), .Y(n981) );
AOI21X2TS U1419 ( .A0(exp_oper_result[0]), .A1(n1692), .B0(n972), .Y(n982)
);
AOI22X2TS U1420 ( .A0(LZA_output[3]), .A1(n702), .B0(n665), .B1(
exp_oper_result[3]), .Y(n901) );
AOI32X4TS U1421 ( .A0(n1512), .A1(n1585), .A2(n1511), .B0(n1510), .B1(n1591),
.Y(Barrel_Shifter_module_Mux_Array_Data_array[20]) );
NOR2BX1TS U1422 ( .AN(n961), .B(add_overflow_flag), .Y(n903) );
NOR3X2TS U1423 ( .A(Add_Subt_result[21]), .B(Add_Subt_result[20]), .C(
Add_Subt_result[19]), .Y(n1317) );
AOI21X2TS U1424 ( .A0(n669), .A1(Add_Subt_result[20]), .B0(n978), .Y(n1509)
);
OAI31X1TS U1425 ( .A0(n1739), .A1(Add_Subt_result[21]), .A2(
Add_Subt_result[20]), .B0(n1324), .Y(n1325) );
AOI221X1TS U1426 ( .A0(n1698), .A1(intDY[13]), .B0(intDY[10]), .B1(n1724),
.C0(n943), .Y(n948) );
OAI21XLTS U1427 ( .A0(intDX[13]), .A1(n1686), .B0(intDX[12]), .Y(n1067) );
INVX2TS U1428 ( .A(n688), .Y(n689) );
OR2X4TS U1429 ( .A(n1109), .B(n1144), .Y(n690) );
OR2X1TS U1430 ( .A(n734), .B(n733), .Y(n691) );
OR2X1TS U1431 ( .A(n727), .B(n726), .Y(n692) );
OR2X1TS U1432 ( .A(n856), .B(n855), .Y(n694) );
OR2X2TS U1433 ( .A(n719), .B(n718), .Y(n695) );
OR2X2TS U1434 ( .A(n721), .B(n720), .Y(n696) );
OAI21XLTS U1435 ( .A0(intDX[1]), .A1(n1682), .B0(intDX[0]), .Y(n1056) );
NOR2XLTS U1436 ( .A(n1089), .B(intDY[16]), .Y(n1090) );
NAND2X1TS U1437 ( .A(n1465), .B(n848), .Y(n850) );
INVX2TS U1438 ( .A(n762), .Y(n714) );
OAI21X2TS U1439 ( .A0(n1365), .A1(n818), .B0(n817), .Y(n1416) );
OR2X1TS U1440 ( .A(n871), .B(n870), .Y(n1397) );
INVX2TS U1441 ( .A(n1416), .Y(n1464) );
AND4X1TS U1442 ( .A(n1285), .B(n1286), .C(n1287), .D(n764), .Y(n771) );
OAI21XLTS U1443 ( .A0(Add_Subt_result[1]), .A1(Add_Subt_result[0]), .B0(
n1301), .Y(n1298) );
NAND2X1TS U1444 ( .A(n691), .B(n765), .Y(n735) );
XNOR2X2TS U1445 ( .A(intDY[31]), .B(intAS), .Y(n1201) );
CLKXOR2X2TS U1446 ( .A(n763), .B(n762), .Y(n1291) );
NAND2X2TS U1447 ( .A(n959), .B(n1712), .Y(n244) );
NOR2X2TS U1448 ( .A(FS_Module_state_reg[1]), .B(n1694), .Y(n961) );
NOR2BX2TS U1449 ( .AN(n961), .B(FS_Module_state_reg[3]), .Y(n700) );
NOR2X1TS U1450 ( .A(n910), .B(FSM_selector_C), .Y(n699) );
INVX2TS U1451 ( .A(n1212), .Y(n909) );
NAND2X1TS U1452 ( .A(add_overflow_flag), .B(n697), .Y(n698) );
NOR2X1TS U1453 ( .A(n699), .B(n698), .Y(n701) );
NAND2X2TS U1454 ( .A(n700), .B(FS_Module_state_reg[0]), .Y(n1210) );
NOR2X4TS U1455 ( .A(FS_Module_state_reg[0]), .B(n1720), .Y(n1218) );
NAND2X1TS U1456 ( .A(n1218), .B(n961), .Y(n908) );
INVX6TS U1457 ( .A(n1638), .Y(n1272) );
NAND3X6TS U1458 ( .A(n701), .B(n675), .C(n244), .Y(n768) );
BUFX3TS U1459 ( .A(FSM_selector_D), .Y(n891) );
NAND2X1TS U1460 ( .A(n702), .B(LZA_output[0]), .Y(n707) );
NAND2X1TS U1461 ( .A(n1692), .B(FSM_selector_B[1]), .Y(n706) );
NAND2X1TS U1462 ( .A(n707), .B(n706), .Y(n972) );
AOI21X4TS U1463 ( .A0(n715), .A1(n714), .B0(n713), .Y(n744) );
OAI21X4TS U1464 ( .A0(n744), .A1(n724), .B0(n723), .Y(n743) );
AOI21X4TS U1465 ( .A0(n743), .A1(n692), .B0(n728), .Y(n740) );
XNOR2X4TS U1466 ( .A(n751), .B(n750), .Y(n1288) );
AFHCONX2TS U1467 ( .A(n758), .B(n768), .CI(n757), .CON(n762), .S(n1337) );
AND4X1TS U1468 ( .A(n1288), .B(n1290), .C(n1337), .D(n1291), .Y(n764) );
NAND2X1TS U1469 ( .A(FS_Module_state_reg[0]), .B(n1212), .Y(n772) );
NAND2X2TS U1470 ( .A(n910), .B(n772), .Y(n1289) );
INVX2TS U1471 ( .A(n1218), .Y(n774) );
NOR2X2TS U1472 ( .A(FS_Module_state_reg[2]), .B(n774), .Y(n1292) );
NAND2X2TS U1473 ( .A(n1292), .B(n655), .Y(n1334) );
NOR2X1TS U1474 ( .A(Add_Subt_result[23]), .B(Add_Subt_result[22]), .Y(n1324)
);
NOR2X1TS U1475 ( .A(Add_Subt_result[25]), .B(Add_Subt_result[24]), .Y(n1326)
);
NOR2X1TS U1476 ( .A(Add_Subt_result[17]), .B(Add_Subt_result[16]), .Y(n1322)
);
NAND2X1TS U1477 ( .A(n1322), .B(n1687), .Y(n1305) );
NOR3X2TS U1478 ( .A(Add_Subt_result[7]), .B(Add_Subt_result[6]), .C(n783),
.Y(n1313) );
NOR2X4TS U1479 ( .A(Add_Subt_result[4]), .B(n778), .Y(n1312) );
NAND2X1TS U1480 ( .A(Add_Subt_result[2]), .B(n1312), .Y(n780) );
NOR3BX4TS U1481 ( .AN(n1312), .B(Add_Subt_result[3]), .C(Add_Subt_result[2]),
.Y(n1301) );
OAI2BB2X1TS U1482 ( .B0(n1729), .B1(n777), .A0N(Add_Subt_result[18]), .A1N(
n1323), .Y(n1332) );
NAND2BX1TS U1483 ( .AN(n778), .B(Add_Subt_result[4]), .Y(n1299) );
INVX2TS U1484 ( .A(n1334), .Y(n1318) );
INVX2TS U1485 ( .A(n1318), .Y(n781) );
AOI21X1TS U1486 ( .A0(n1735), .A1(Add_Subt_result[20]), .B0(
Add_Subt_result[22]), .Y(n784) );
INVX2TS U1487 ( .A(n1327), .Y(n786) );
AOI21X1TS U1488 ( .A0(n1691), .A1(Add_Subt_result[12]), .B0(
Add_Subt_result[14]), .Y(n785) );
NOR2X1TS U1489 ( .A(n786), .B(n785), .Y(n1303) );
INVX2TS U1490 ( .A(n1303), .Y(n788) );
BUFX3TS U1491 ( .A(FSM_selector_D), .Y(n885) );
XOR2X1TS U1492 ( .A(n821), .B(Sgf_normalized_result[1]), .Y(n794) );
BUFX3TS U1493 ( .A(FSM_selector_D), .Y(n967) );
NOR2X2TS U1494 ( .A(n794), .B(n793), .Y(n1351) );
OR2X1TS U1495 ( .A(n885), .B(Sgf_normalized_result[2]), .Y(n795) );
XOR2X1TS U1496 ( .A(n821), .B(n795), .Y(n800) );
BUFX3TS U1497 ( .A(FSM_selector_D), .Y(n825) );
NOR2X1TS U1498 ( .A(n800), .B(n799), .Y(n1353) );
NOR2X1TS U1499 ( .A(n1351), .B(n1353), .Y(n802) );
INVX4TS U1500 ( .A(n1281), .Y(n896) );
BUFX3TS U1501 ( .A(FSM_selector_D), .Y(n894) );
NOR2BX1TS U1502 ( .AN(Sgf_normalized_result[0]), .B(n894), .Y(n796) );
XOR2X1TS U1503 ( .A(n896), .B(n796), .Y(n1222) );
INVX2TS U1504 ( .A(n1222), .Y(n798) );
NOR2X1TS U1505 ( .A(n896), .B(n797), .Y(n1223) );
NOR2X1TS U1506 ( .A(n798), .B(n1223), .Y(n1344) );
NAND2X1TS U1507 ( .A(n800), .B(n799), .Y(n1354) );
INVX2TS U1508 ( .A(n1354), .Y(n801) );
AOI21X2TS U1509 ( .A0(n802), .A1(n1344), .B0(n801), .Y(n1365) );
NOR2BX1TS U1510 ( .AN(Sgf_normalized_result[3]), .B(n967), .Y(n803) );
XOR2X1TS U1511 ( .A(n821), .B(n803), .Y(n808) );
NOR2X1TS U1512 ( .A(n808), .B(n807), .Y(n1366) );
NOR2BX1TS U1513 ( .AN(Sgf_normalized_result[4]), .B(n894), .Y(n804) );
XOR2X1TS U1514 ( .A(n821), .B(n804), .Y(n810) );
NOR2X2TS U1515 ( .A(n810), .B(n809), .Y(n1378) );
NOR2BX1TS U1516 ( .AN(Sgf_normalized_result[5]), .B(n894), .Y(n805) );
NOR2X2TS U1517 ( .A(n812), .B(n811), .Y(n1402) );
NOR2BX1TS U1518 ( .AN(Sgf_normalized_result[6]), .B(n967), .Y(n806) );
XOR2X1TS U1519 ( .A(n821), .B(n806), .Y(n814) );
NOR2X2TS U1520 ( .A(n814), .B(n813), .Y(n1404) );
NAND2X1TS U1521 ( .A(n808), .B(n807), .Y(n1375) );
NAND2X1TS U1522 ( .A(n810), .B(n809), .Y(n1379) );
NAND2X1TS U1523 ( .A(n812), .B(n811), .Y(n1401) );
NAND2X1TS U1524 ( .A(n814), .B(n813), .Y(n1405) );
AOI21X1TS U1525 ( .A0(n1390), .A1(n816), .B0(n815), .Y(n817) );
NOR2BX1TS U1526 ( .AN(Sgf_normalized_result[7]), .B(n967), .Y(n819) );
NOR2X2TS U1527 ( .A(n830), .B(n829), .Y(n1426) );
NOR2BX1TS U1528 ( .AN(Sgf_normalized_result[8]), .B(n967), .Y(n820) );
XOR2X1TS U1529 ( .A(n821), .B(n820), .Y(n832) );
NOR2X1TS U1530 ( .A(n1426), .B(n1427), .Y(n1440) );
NOR2BX1TS U1531 ( .AN(Sgf_normalized_result[9]), .B(n967), .Y(n822) );
XOR2X1TS U1532 ( .A(n877), .B(n822), .Y(n834) );
NOR2X1TS U1533 ( .A(n834), .B(n833), .Y(n1444) );
NOR2BX1TS U1534 ( .AN(Sgf_normalized_result[10]), .B(n967), .Y(n823) );
XOR2X1TS U1535 ( .A(n877), .B(n823), .Y(n836) );
NOR2X2TS U1536 ( .A(n836), .B(n835), .Y(n1456) );
NOR2BX1TS U1537 ( .AN(Sgf_normalized_result[11]), .B(n967), .Y(n824) );
XOR2X1TS U1538 ( .A(n877), .B(n824), .Y(n840) );
NOR2X1TS U1539 ( .A(n840), .B(n839), .Y(n1477) );
XOR2X1TS U1540 ( .A(n877), .B(n826), .Y(n842) );
BUFX3TS U1541 ( .A(FSM_selector_D), .Y(n878) );
NOR2X2TS U1542 ( .A(n842), .B(n841), .Y(n1490) );
XOR2X1TS U1543 ( .A(n877), .B(n827), .Y(n844) );
NOR2X1TS U1544 ( .A(n844), .B(n843), .Y(n1469) );
XOR2X1TS U1545 ( .A(n877), .B(n828), .Y(n846) );
NOR2X2TS U1546 ( .A(n846), .B(n845), .Y(n1471) );
NOR2X2TS U1547 ( .A(n1463), .B(n850), .Y(n852) );
NAND2X2TS U1548 ( .A(n830), .B(n829), .Y(n1425) );
NAND2X1TS U1549 ( .A(n832), .B(n831), .Y(n1428) );
OAI21X1TS U1550 ( .A0(n1427), .A1(n1425), .B0(n1428), .Y(n1441) );
NAND2X1TS U1551 ( .A(n834), .B(n833), .Y(n1452) );
NAND2X1TS U1552 ( .A(n836), .B(n835), .Y(n1457) );
NAND2X1TS U1553 ( .A(n840), .B(n839), .Y(n1486) );
NAND2X1TS U1554 ( .A(n842), .B(n841), .Y(n1491) );
OAI21X1TS U1555 ( .A0(n1490), .A1(n1486), .B0(n1491), .Y(n1466) );
NAND2X1TS U1556 ( .A(n846), .B(n845), .Y(n1472) );
AOI21X1TS U1557 ( .A0(n1466), .A1(n848), .B0(n847), .Y(n849) );
OAI21X2TS U1558 ( .A0(n1462), .A1(n850), .B0(n849), .Y(n851) );
AOI21X4TS U1559 ( .A0(n1416), .A1(n852), .B0(n851), .Y(n1433) );
XOR2X1TS U1560 ( .A(n877), .B(n853), .Y(n856) );
XOR2X1TS U1561 ( .A(n877), .B(n854), .Y(n858) );
NAND2X1TS U1562 ( .A(n694), .B(n1436), .Y(n861) );
NAND2X1TS U1563 ( .A(n856), .B(n855), .Y(n1447) );
INVX2TS U1564 ( .A(n1447), .Y(n1434) );
NAND2X1TS U1565 ( .A(n858), .B(n857), .Y(n1435) );
INVX2TS U1566 ( .A(n1435), .Y(n859) );
AOI21X1TS U1567 ( .A0(n1436), .A1(n1434), .B0(n859), .Y(n860) );
OAI21X4TS U1568 ( .A0(n1433), .A1(n861), .B0(n860), .Y(n1423) );
XOR2X1TS U1569 ( .A(n877), .B(n862), .Y(n864) );
NAND2X1TS U1570 ( .A(n864), .B(n863), .Y(n1420) );
INVX2TS U1571 ( .A(n1420), .Y(n865) );
AOI21X4TS U1572 ( .A0(n1423), .A1(n1421), .B0(n865), .Y(n1414) );
XOR2X1TS U1573 ( .A(n896), .B(n866), .Y(n868) );
NOR2X1TS U1574 ( .A(n868), .B(n867), .Y(n1410) );
NAND2X1TS U1575 ( .A(n868), .B(n867), .Y(n1411) );
OAI21X4TS U1576 ( .A0(n1414), .A1(n1410), .B0(n1411), .Y(n1399) );
XOR2X1TS U1577 ( .A(n896), .B(n869), .Y(n871) );
NAND2X1TS U1578 ( .A(n871), .B(n870), .Y(n1396) );
INVX2TS U1579 ( .A(n1396), .Y(n872) );
AOI21X4TS U1580 ( .A0(n1399), .A1(n1397), .B0(n872), .Y(n1388) );
XOR2X1TS U1581 ( .A(n896), .B(n873), .Y(n875) );
NOR2X1TS U1582 ( .A(n875), .B(n874), .Y(n1384) );
NAND2X1TS U1583 ( .A(n875), .B(n874), .Y(n1385) );
OAI21X4TS U1584 ( .A0(n1388), .A1(n1384), .B0(n1385), .Y(n1372) );
XOR2X1TS U1585 ( .A(n877), .B(n876), .Y(n880) );
NAND2X1TS U1586 ( .A(n880), .B(n879), .Y(n1369) );
INVX2TS U1587 ( .A(n1369), .Y(n881) );
AOI21X4TS U1588 ( .A0(n1372), .A1(n1370), .B0(n881), .Y(n1363) );
XOR2X1TS U1589 ( .A(n896), .B(n882), .Y(n884) );
NOR2X1TS U1590 ( .A(n884), .B(n883), .Y(n1359) );
NAND2X1TS U1591 ( .A(n884), .B(n883), .Y(n1360) );
OAI21X4TS U1592 ( .A0(n1363), .A1(n1359), .B0(n1360), .Y(n1349) );
XOR2X1TS U1593 ( .A(n896), .B(n886), .Y(n888) );
NAND2X1TS U1594 ( .A(n888), .B(n887), .Y(n1346) );
INVX2TS U1595 ( .A(n1346), .Y(n889) );
AOI21X4TS U1596 ( .A0(n1349), .A1(n1347), .B0(n889), .Y(n1342) );
XOR2X1TS U1597 ( .A(n896), .B(n890), .Y(n893) );
NOR2X1TS U1598 ( .A(n893), .B(n892), .Y(n1338) );
NAND2X1TS U1599 ( .A(n893), .B(n892), .Y(n1339) );
OAI21X4TS U1600 ( .A0(n1342), .A1(n1338), .B0(n1339), .Y(n1280) );
NOR2BX1TS U1601 ( .AN(Sgf_normalized_result[25]), .B(n967), .Y(n895) );
XOR2X1TS U1602 ( .A(n896), .B(n895), .Y(n1278) );
INVX2TS U1603 ( .A(n1278), .Y(n897) );
NAND2X1TS U1604 ( .A(n1279), .B(n897), .Y(n898) );
XNOR2X1TS U1605 ( .A(n1280), .B(n898), .Y(n900) );
NAND2X1TS U1606 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[1]),
.Y(n899) );
NOR2X1TS U1607 ( .A(n681), .B(n901), .Y(n915) );
NAND2X1TS U1608 ( .A(n901), .B(n681), .Y(n996) );
INVX2TS U1609 ( .A(n996), .Y(n913) );
INVX2TS U1610 ( .A(n901), .Y(n1001) );
NOR2X4TS U1611 ( .A(n681), .B(n1001), .Y(n1225) );
AOI22X1TS U1612 ( .A0(n913), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[27]), .B0(n1225), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n902) );
OAI2BB1X1TS U1613 ( .A0N(Barrel_Shifter_module_Mux_Array_Data_array[51]),
.A1N(n915), .B0(n902), .Y(n997) );
BUFX3TS U1614 ( .A(n1727), .Y(n1582) );
NAND2X1TS U1615 ( .A(n1001), .B(n681), .Y(n1012) );
INVX2TS U1616 ( .A(n906), .Y(n917) );
BUFX3TS U1617 ( .A(n1241), .Y(n1639) );
AOI22X1TS U1618 ( .A0(n675), .A1(Sgf_normalized_result[24]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B1(n1639), .Y(n911)
);
BUFX3TS U1619 ( .A(n1727), .Y(n1560) );
INVX2TS U1620 ( .A(n1038), .Y(n1000) );
NOR3X1TS U1621 ( .A(n1000), .B(n675), .C(n913), .Y(n1226) );
INVX2TS U1622 ( .A(n1226), .Y(n1640) );
AOI22X1TS U1623 ( .A0(n913), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[26]), .B0(n1225), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n914) );
OAI2BB1X1TS U1624 ( .A0N(Barrel_Shifter_module_Mux_Array_Data_array[50]),
.A1N(n915), .B0(n914), .Y(n1022) );
AOI22X1TS U1625 ( .A0(n676), .A1(Sgf_normalized_result[25]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .B1(n1639), .Y(n916)
);
INVX2TS U1626 ( .A(rst), .Y(n1790) );
OAI22X1TS U1627 ( .A0(n1719), .A1(intDX[12]), .B0(n1704), .B1(intDY[8]), .Y(
n919) );
AOI221X1TS U1628 ( .A0(n1719), .A1(intDX[12]), .B0(intDY[8]), .B1(n1704),
.C0(n919), .Y(n925) );
OAI22X1TS U1629 ( .A0(n1667), .A1(intDY[21]), .B0(n1696), .B1(intDY[17]),
.Y(n920) );
AOI221X1TS U1630 ( .A0(n1667), .A1(intDY[21]), .B0(intDY[17]), .B1(n1696),
.C0(n920), .Y(n924) );
OAI22X1TS U1631 ( .A0(n1733), .A1(intDY[16]), .B0(n1664), .B1(intDY[23]),
.Y(n921) );
AOI221X1TS U1632 ( .A0(n1733), .A1(intDY[16]), .B0(intDY[23]), .B1(n1664),
.C0(n921), .Y(n923) );
AOI22X1TS U1633 ( .A0(intDX[7]), .A1(n1671), .B0(intDY[7]), .B1(n1675), .Y(
n922) );
OAI22X1TS U1634 ( .A0(n1668), .A1(intDY[22]), .B0(n1697), .B1(intDY[18]),
.Y(n926) );
AOI221X1TS U1635 ( .A0(n1668), .A1(intDY[22]), .B0(intDY[18]), .B1(n1697),
.C0(n926), .Y(n933) );
OAI22X1TS U1636 ( .A0(n1701), .A1(intDY[29]), .B0(n1666), .B1(intDY[27]),
.Y(n927) );
OAI22X1TS U1637 ( .A0(n1700), .A1(intDY[19]), .B0(n1665), .B1(intDY[25]),
.Y(n928) );
AOI221X1TS U1638 ( .A0(n1700), .A1(intDY[19]), .B0(intDY[25]), .B1(n1665),
.C0(n928), .Y(n931) );
OAI22X1TS U1639 ( .A0(n1669), .A1(intDY[24]), .B0(n1659), .B1(intDY[20]),
.Y(n929) );
AOI221X1TS U1640 ( .A0(n1669), .A1(intDY[24]), .B0(intDY[20]), .B1(n1659),
.C0(n929), .Y(n930) );
OAI22X1TS U1641 ( .A0(n1702), .A1(intDY[30]), .B0(n1721), .B1(intDY[5]), .Y(
n934) );
AOI221X1TS U1642 ( .A0(n1702), .A1(intDY[30]), .B0(intDY[5]), .B1(n1721),
.C0(n934), .Y(n941) );
OAI22X1TS U1643 ( .A0(n1676), .A1(intDY[4]), .B0(n1703), .B1(intDY[3]), .Y(
n935) );
OAI22X1TS U1644 ( .A0(n1670), .A1(intDY[26]), .B0(n1705), .B1(intDY[1]), .Y(
n936) );
OAI22X1TS U1645 ( .A0(n1722), .A1(intDY[0]), .B0(n1723), .B1(intDY[28]), .Y(
n937) );
OAI22X1TS U1646 ( .A0(n1718), .A1(intDY[6]), .B0(n1695), .B1(intDY[15]), .Y(
n942) );
AOI221X1TS U1647 ( .A0(n1718), .A1(intDY[6]), .B0(intDY[15]), .B1(n1695),
.C0(n942), .Y(n949) );
OAI22X1TS U1648 ( .A0(n1698), .A1(intDY[13]), .B0(n1724), .B1(intDY[10]),
.Y(n943) );
OAI22X1TS U1649 ( .A0(n1706), .A1(intDY[2]), .B0(n1673), .B1(intDY[9]), .Y(
n944) );
OAI22X1TS U1650 ( .A0(n1699), .A1(intDY[14]), .B0(n1663), .B1(intDY[11]),
.Y(n945) );
AOI221X1TS U1651 ( .A0(n1699), .A1(intDY[14]), .B0(intDY[11]), .B1(n1663),
.C0(n945), .Y(n946) );
NOR4X2TS U1652 ( .A(n953), .B(n952), .C(n951), .D(n950), .Y(n1199) );
AOI21X1TS U1653 ( .A0(n1199), .A1(n955), .B0(n1190), .Y(n958) );
NAND3X1TS U1654 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[2]),
.C(n1218), .Y(n987) );
BUFX3TS U1655 ( .A(n1786), .Y(n1766) );
BUFX3TS U1656 ( .A(n1780), .Y(n1785) );
BUFX3TS U1657 ( .A(n1785), .Y(n1783) );
BUFX3TS U1658 ( .A(n1783), .Y(n1772) );
BUFX3TS U1659 ( .A(n1785), .Y(n1769) );
BUFX3TS U1660 ( .A(n1785), .Y(n1768) );
BUFX3TS U1661 ( .A(n1786), .Y(n1767) );
BUFX3TS U1662 ( .A(n1781), .Y(n1775) );
BUFX3TS U1663 ( .A(n1790), .Y(n1778) );
BUFX3TS U1664 ( .A(n1781), .Y(n1776) );
BUFX3TS U1665 ( .A(n1781), .Y(n1774) );
BUFX3TS U1666 ( .A(n1785), .Y(n1787) );
BUFX3TS U1667 ( .A(n1780), .Y(n1777) );
BUFX3TS U1668 ( .A(n1786), .Y(n1784) );
CLKBUFX3TS U1669 ( .A(n1784), .Y(n1789) );
CLKBUFX3TS U1670 ( .A(n1789), .Y(n1788) );
BUFX3TS U1671 ( .A(n1788), .Y(n1762) );
BUFX3TS U1672 ( .A(n1783), .Y(n1773) );
BUFX3TS U1673 ( .A(n1788), .Y(n1763) );
NAND2X1TS U1674 ( .A(n959), .B(FS_Module_state_reg[0]), .Y(n960) );
INVX2TS U1675 ( .A(n960), .Y(n1654) );
BUFX3TS U1676 ( .A(n1654), .Y(n1653) );
INVX2TS U1677 ( .A(n1651), .Y(n1650) );
BUFX3TS U1678 ( .A(n1651), .Y(n1647) );
BUFX3TS U1679 ( .A(n1654), .Y(n1655) );
OAI2BB2XLTS U1680 ( .B0(n1647), .B1(n1663), .A0N(n1655), .A1N(Data_X[11]),
.Y(n194) );
BUFX3TS U1681 ( .A(n1654), .Y(n1658) );
OAI2BB2XLTS U1682 ( .B0(n1658), .B1(n1702), .A0N(n1654), .A1N(Data_X[30]),
.Y(n213) );
OAI2BB2XLTS U1683 ( .B0(n1658), .B1(n1701), .A0N(n1654), .A1N(Data_X[29]),
.Y(n212) );
INVX2TS U1684 ( .A(n963), .Y(n1645) );
BUFX3TS U1685 ( .A(n1645), .Y(n1644) );
AOI21X1TS U1686 ( .A0(n1679), .A1(n1756), .B0(overflow_flag), .Y(n964) );
INVX2TS U1687 ( .A(n1644), .Y(n1629) );
OAI22X1TS U1688 ( .A0(r_mode[0]), .A1(n1679), .B0(Sgf_normalized_result[0]),
.B1(Sgf_normalized_result[1]), .Y(n966) );
AOI211X1TS U1689 ( .A0(r_mode[0]), .A1(r_mode[1]), .B0(n966), .C0(n965), .Y(
n1179) );
AO22X2TS U1690 ( .A0(n682), .A1(n702), .B0(n666), .B1(exp_oper_result[2]),
.Y(n1500) );
INVX2TS U1691 ( .A(n1500), .Y(n1585) );
NAND2X4TS U1692 ( .A(n663), .B(FSM_selector_C), .Y(n1555) );
OAI22X1TS U1693 ( .A0(n664), .A1(n1677), .B0(FSM_selector_C), .B1(n1734),
.Y(n968) );
NOR2X1TS U1694 ( .A(n969), .B(n968), .Y(n993) );
INVX2TS U1695 ( .A(n993), .Y(n1505) );
AOI22X1TS U1696 ( .A0(n670), .A1(Add_Subt_result[6]), .B0(DmP[17]), .B1(
n1582), .Y(n970) );
OA21XLTS U1697 ( .A0(n1555), .A1(n1739), .B0(n970), .Y(n1514) );
OAI2BB2X2TS U1698 ( .B0(n1585), .B1(n1505), .A0N(n1585), .A1N(n1514), .Y(
n1043) );
INVX2TS U1699 ( .A(n981), .Y(n1039) );
NAND2X1TS U1700 ( .A(n1039), .B(n982), .Y(n1025) );
OR2X2TS U1701 ( .A(n982), .B(n1039), .Y(n991) );
INVX2TS U1702 ( .A(n991), .Y(n1611) );
OAI2BB2XLTS U1703 ( .B0(n664), .B1(n1736), .A0N(DmP[16]), .A1N(n1560), .Y(
n973) );
AOI21X1TS U1704 ( .A0(n669), .A1(Add_Subt_result[18]), .B0(n973), .Y(n1519)
);
AOI22X1TS U1705 ( .A0(n670), .A1(Add_Subt_result[3]), .B0(n677), .B1(n1582),
.Y(n974) );
OAI2BB1X2TS U1706 ( .A0N(Add_Subt_result[22]), .A1N(n669), .B0(n974), .Y(
n1506) );
AOI2BB2X2TS U1707 ( .B0(n1585), .B1(n1519), .A0N(n1506), .A1N(n1585), .Y(
n1515) );
NAND2X2TS U1708 ( .A(n982), .B(n981), .Y(n1508) );
INVX2TS U1709 ( .A(n1508), .Y(n975) );
AOI21X1TS U1710 ( .A0(n669), .A1(Add_Subt_result[17]), .B0(n976), .Y(n1524)
);
BUFX3TS U1711 ( .A(n1500), .Y(n1544) );
BUFX3TS U1712 ( .A(n1544), .Y(n1605) );
AOI22X1TS U1713 ( .A0(n1590), .A1(n1515), .B0(n687), .B1(n1520), .Y(n984) );
OAI22X1TS U1714 ( .A0(n664), .A1(n1678), .B0(FSM_selector_C), .B1(n1743),
.Y(n979) );
NOR2X1TS U1715 ( .A(n980), .B(n979), .Y(n992) );
OR2X2TS U1716 ( .A(n982), .B(n981), .Y(n1504) );
INVX2TS U1717 ( .A(n1504), .Y(n1033) );
NAND2X1TS U1718 ( .A(n1032), .B(n1600), .Y(n983) );
BUFX3TS U1719 ( .A(n1787), .Y(n1765) );
BUFX3TS U1720 ( .A(n1787), .Y(n1764) );
BUFX3TS U1721 ( .A(n1787), .Y(n1779) );
BUFX3TS U1722 ( .A(n1784), .Y(n1770) );
BUFX3TS U1723 ( .A(n1784), .Y(n1771) );
INVX2TS U1724 ( .A(n1292), .Y(n985) );
AOI22X1TS U1725 ( .A0(n1218), .A1(n1212), .B0(FSM_selector_B[1]), .B1(n985),
.Y(n986) );
INVX2TS U1726 ( .A(n987), .Y(ready) );
INVX2TS U1727 ( .A(n1499), .Y(n1026) );
OAI31X1TS U1728 ( .A0(n1508), .A1(n1605), .A2(n1026), .B0(n990), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[25]) );
NAND2X2TS U1729 ( .A(n1605), .B(n1038), .Y(n1502) );
INVX2TS U1730 ( .A(n991), .Y(n1037) );
INVX2TS U1731 ( .A(n992), .Y(n1498) );
OAI22X1TS U1732 ( .A0(n993), .A1(n1508), .B0(n1025), .B1(n1026), .Y(n994) );
AOI32X1TS U1733 ( .A0(n1037), .A1(n1585), .A2(n1498), .B0(n994), .B1(n1594),
.Y(n995) );
INVX2TS U1734 ( .A(n907), .Y(n1273) );
NAND2X1TS U1735 ( .A(n997), .B(n1273), .Y(n999) );
AOI22X1TS U1736 ( .A0(n667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(n1272), .B1(
Sgf_normalized_result[1]), .Y(n998) );
NOR2X1TS U1737 ( .A(n1000), .B(n681), .Y(n1231) );
NAND2X1TS U1738 ( .A(n1231), .B(n1001), .Y(n1017) );
INVX2TS U1739 ( .A(n1274), .Y(n1009) );
NAND2X1TS U1740 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[45]), .B(
n1225), .Y(n1619) );
AOI211X1TS U1741 ( .A0(n676), .A1(Sgf_normalized_result[3]), .B0(n1009),
.C0(n1002), .Y(n1004) );
BUFX3TS U1742 ( .A(n1241), .Y(n1270) );
AOI22X1TS U1743 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .B0(n668), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(n1003) );
NAND2X1TS U1744 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[44]), .B(
n1225), .Y(n1614) );
AOI211X1TS U1745 ( .A0(n676), .A1(Sgf_normalized_result[2]), .B0(n1009),
.C0(n1005), .Y(n1007) );
AOI22X1TS U1746 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .B0(n668), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n1006) );
NAND2X1TS U1747 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[46]), .B(
n1225), .Y(n1624) );
AOI211X1TS U1748 ( .A0(n1272), .A1(Sgf_normalized_result[4]), .B0(n1009),
.C0(n1008), .Y(n1011) );
AOI22X1TS U1749 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .B0(n668), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n1010) );
INVX2TS U1750 ( .A(n1012), .Y(n1635) );
AOI22X1TS U1751 ( .A0(n1635), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B1(n1225), .Y(n1013)
);
NAND2X1TS U1752 ( .A(n1013), .B(n1017), .Y(n1232) );
INVX2TS U1753 ( .A(n1232), .Y(n1016) );
AOI22X1TS U1754 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .B0(n1272), .B1(
Sgf_normalized_result[8]), .Y(n1015) );
AOI22X1TS U1755 ( .A0(n906), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .B0(n685), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n1014) );
AOI22X1TS U1756 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[51]), .A1(
n1225), .B0(n1635), .B1(Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n1018) );
NAND2X1TS U1757 ( .A(n1018), .B(n1017), .Y(n1236) );
INVX2TS U1758 ( .A(n1236), .Y(n1021) );
AOI22X1TS U1759 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(n676), .B1(
Sgf_normalized_result[9]), .Y(n1020) );
AOI22X1TS U1760 ( .A0(n906), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B0(n683), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n1019) );
NAND2X1TS U1761 ( .A(n1022), .B(n1273), .Y(n1024) );
AOI22X1TS U1762 ( .A0(n667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .B0(n676), .B1(
Sgf_normalized_result[0]), .Y(n1023) );
AOI222X1TS U1763 ( .A0(n1506), .A1(n1590), .B0(n1498), .B1(n1600), .C0(n1505), .C1(n679), .Y(n1028) );
INVX2TS U1764 ( .A(n1502), .Y(n1029) );
AOI22X1TS U1765 ( .A0(n975), .A1(n1034), .B0(n1029), .B1(n1508), .Y(n1027)
);
AOI22X1TS U1766 ( .A0(n1037), .A1(n1032), .B0(n679), .B1(n1034), .Y(n1031)
);
INVX2TS U1767 ( .A(n1504), .Y(n1596) );
AOI32X1TS U1768 ( .A0(n1608), .A1(n1596), .A2(n1506), .B0(n1029), .B1(n1596),
.Y(n1030) );
AOI22X1TS U1769 ( .A0(n1032), .A1(n679), .B0(n686), .B1(n1515), .Y(n1036) );
NAND2X1TS U1770 ( .A(n1034), .B(n1033), .Y(n1035) );
OAI2BB2XLTS U1771 ( .B0(n664), .B1(n1738), .A0N(DmP[14]), .A1N(n1560), .Y(
n1040) );
AOI21X1TS U1772 ( .A0(n669), .A1(Add_Subt_result[16]), .B0(n1040), .Y(n1529)
);
AOI22X2TS U1773 ( .A0(n1608), .A1(n1529), .B0(n1509), .B1(n1544), .Y(n1525)
);
AOI22X1TS U1774 ( .A0(n1611), .A1(n1520), .B0(n686), .B1(n1525), .Y(n1042)
);
NAND2X1TS U1775 ( .A(n679), .B(n1515), .Y(n1041) );
NOR2X1TS U1776 ( .A(n1688), .B(intDX[25]), .Y(n1103) );
AOI22X1TS U1777 ( .A0(intDX[25]), .A1(n1688), .B0(intDX[24]), .B1(n1044),
.Y(n1048) );
OAI21X1TS U1778 ( .A0(intDX[26]), .A1(n1707), .B0(n1045), .Y(n1104) );
OAI211X1TS U1779 ( .A0(n1048), .A1(n1104), .B0(n1047), .C0(n1046), .Y(n1053)
);
NOR2X1TS U1780 ( .A(n1710), .B(intDX[30]), .Y(n1051) );
NOR2X1TS U1781 ( .A(n1674), .B(intDX[29]), .Y(n1049) );
NOR3X1TS U1782 ( .A(n1723), .B(n1049), .C(intDY[28]), .Y(n1050) );
AOI221X1TS U1783 ( .A0(intDX[30]), .A1(n1710), .B0(intDX[29]), .B1(n1674),
.C0(n1050), .Y(n1052) );
NOR2X1TS U1784 ( .A(n1689), .B(intDX[17]), .Y(n1089) );
NOR2X1TS U1785 ( .A(n1683), .B(intDX[11]), .Y(n1068) );
AOI21X1TS U1786 ( .A0(intDY[10]), .A1(n1724), .B0(n1068), .Y(n1073) );
OAI2BB1X1TS U1787 ( .A0N(n1721), .A1N(intDY[5]), .B0(intDX[4]), .Y(n1054) );
OAI22X1TS U1788 ( .A0(intDY[4]), .A1(n1054), .B0(n1721), .B1(intDY[5]), .Y(
n1065) );
OAI2BB1X1TS U1789 ( .A0N(n1675), .A1N(intDY[7]), .B0(intDX[6]), .Y(n1055) );
OAI22X1TS U1790 ( .A0(intDY[6]), .A1(n1055), .B0(n1675), .B1(intDY[7]), .Y(
n1064) );
OAI2BB2XLTS U1791 ( .B0(intDY[0]), .B1(n1056), .A0N(intDX[1]), .A1N(n1682),
.Y(n1058) );
OAI211X1TS U1792 ( .A0(n1680), .A1(intDX[3]), .B0(n1058), .C0(n1057), .Y(
n1061) );
AOI22X1TS U1793 ( .A0(intDY[7]), .A1(n1675), .B0(intDY[6]), .B1(n1718), .Y(
n1062) );
OAI32X1TS U1794 ( .A0(n1065), .A1(n1064), .A2(n1063), .B0(n1062), .B1(n1064),
.Y(n1083) );
OA22X1TS U1795 ( .A0(n1681), .A1(intDX[14]), .B0(n1660), .B1(intDX[15]), .Y(
n1080) );
AOI22X1TS U1796 ( .A0(intDX[11]), .A1(n1683), .B0(intDX[10]), .B1(n1069),
.Y(n1075) );
AOI21X1TS U1797 ( .A0(n1072), .A1(n1071), .B0(n1082), .Y(n1074) );
OAI2BB2XLTS U1798 ( .B0(intDY[14]), .B1(n1076), .A0N(intDX[15]), .A1N(n1660),
.Y(n1077) );
AOI211X1TS U1799 ( .A0(n1080), .A1(n1079), .B0(n1078), .C0(n1077), .Y(n1081)
);
OAI31X1TS U1800 ( .A0(n1084), .A1(n1083), .A2(n1082), .B0(n1081), .Y(n1087)
);
OA22X1TS U1801 ( .A0(n1684), .A1(intDX[22]), .B0(n1661), .B1(intDX[23]), .Y(
n1100) );
OAI21X1TS U1802 ( .A0(intDX[18]), .A1(n1711), .B0(n1091), .Y(n1095) );
OAI2BB2XLTS U1803 ( .B0(intDY[20]), .B1(n1088), .A0N(intDX[21]), .A1N(n1708),
.Y(n1099) );
AOI22X1TS U1804 ( .A0(intDX[17]), .A1(n1689), .B0(intDX[16]), .B1(n1090),
.Y(n1093) );
AOI32X1TS U1805 ( .A0(n1711), .A1(n1091), .A2(intDX[18]), .B0(intDX[19]),
.B1(n1672), .Y(n1092) );
OAI32X1TS U1806 ( .A0(n1095), .A1(n1094), .A2(n1093), .B0(n1092), .B1(n1094),
.Y(n1098) );
OAI2BB2XLTS U1807 ( .B0(intDY[22]), .B1(n1096), .A0N(intDX[23]), .A1N(n1661),
.Y(n1097) );
AOI211X1TS U1808 ( .A0(n1100), .A1(n1099), .B0(n1098), .C0(n1097), .Y(n1106)
);
NAND4BBX1TS U1809 ( .AN(n1104), .BN(n1103), .C(n1102), .D(n1101), .Y(n1105)
);
AOI22X1TS U1810 ( .A0(n677), .A1(n1186), .B0(intDY[20]), .B1(n1165), .Y(
n1110) );
AOI22X1TS U1811 ( .A0(intDY[18]), .A1(n1139), .B0(DMP[18]), .B1(n1128), .Y(
n1111) );
AOI22X1TS U1812 ( .A0(intDY[14]), .A1(n1139), .B0(DMP[14]), .B1(n1128), .Y(
n1112) );
AOI22X1TS U1813 ( .A0(intDY[15]), .A1(n1139), .B0(DMP[15]), .B1(n1190), .Y(
n1113) );
AOI22X1TS U1814 ( .A0(intDY[13]), .A1(n1139), .B0(DMP[13]), .B1(n1190), .Y(
n1114) );
AOI22X1TS U1815 ( .A0(intDY[22]), .A1(n1147), .B0(DMP[22]), .B1(n1128), .Y(
n1115) );
AOI22X1TS U1816 ( .A0(intDY[21]), .A1(n1147), .B0(DMP[21]), .B1(n1128), .Y(
n1116) );
AOI22X1TS U1817 ( .A0(intDY[19]), .A1(n1139), .B0(DMP[19]), .B1(n1128), .Y(
n1117) );
AOI22X1TS U1818 ( .A0(intDY[20]), .A1(n1139), .B0(DMP[20]), .B1(n1128), .Y(
n1118) );
AOI22X1TS U1819 ( .A0(intDY[17]), .A1(n1139), .B0(DMP[17]), .B1(n1128), .Y(
n1119) );
AOI22X1TS U1820 ( .A0(intDY[23]), .A1(n1147), .B0(DMP[23]), .B1(n1128), .Y(
n1120) );
AOI22X1TS U1821 ( .A0(intDY[11]), .A1(n1139), .B0(DMP[11]), .B1(n1128), .Y(
n1121) );
AOI22X1TS U1822 ( .A0(intDY[25]), .A1(n1147), .B0(DMP[25]), .B1(n1155), .Y(
n1122) );
AOI22X1TS U1823 ( .A0(intDY[26]), .A1(n1147), .B0(DMP[26]), .B1(n1155), .Y(
n1123) );
AOI22X1TS U1824 ( .A0(intDY[29]), .A1(n1147), .B0(DMP[29]), .B1(n1144), .Y(
n1124) );
AOI22X1TS U1825 ( .A0(intDY[30]), .A1(n1139), .B0(DMP[30]), .B1(n1144), .Y(
n1125) );
BUFX3TS U1826 ( .A(n1198), .Y(n1188) );
AOI22X1TS U1827 ( .A0(intDY[26]), .A1(n1146), .B0(DmP[26]), .B1(n1155), .Y(
n1126) );
AOI22X1TS U1828 ( .A0(intDY[25]), .A1(n1146), .B0(DmP[25]), .B1(n1155), .Y(
n1127) );
BUFX3TS U1829 ( .A(n690), .Y(n1192) );
AOI22X1TS U1830 ( .A0(intDY[30]), .A1(n1146), .B0(DmP[30]), .B1(n1128), .Y(
n1129) );
AOI22X1TS U1831 ( .A0(intDY[29]), .A1(n1146), .B0(DmP[29]), .B1(n1144), .Y(
n1130) );
AOI22X1TS U1832 ( .A0(DmP[21]), .A1(n1196), .B0(intDY[21]), .B1(n1146), .Y(
n1131) );
AOI22X1TS U1833 ( .A0(DmP[19]), .A1(n1196), .B0(intDY[19]), .B1(n1146), .Y(
n1132) );
INVX2TS U1834 ( .A(n1165), .Y(n1202) );
INVX2TS U1835 ( .A(n690), .Y(n1134) );
AOI22X1TS U1836 ( .A0(DmP[12]), .A1(n1196), .B0(intDX[12]), .B1(n1134), .Y(
n1133) );
AOI22X1TS U1837 ( .A0(DmP[7]), .A1(n1196), .B0(intDX[7]), .B1(n1134), .Y(
n1135) );
AOI22X1TS U1838 ( .A0(n689), .A1(n1147), .B0(DMP[27]), .B1(n1155), .Y(n1136)
);
AOI22X1TS U1839 ( .A0(intDY[24]), .A1(n1147), .B0(DMP[24]), .B1(n1155), .Y(
n1137) );
AOI22X1TS U1840 ( .A0(intDY[28]), .A1(n1147), .B0(DMP[28]), .B1(n1155), .Y(
n1138) );
AOI22X1TS U1841 ( .A0(intDY[16]), .A1(n1139), .B0(DMP[16]), .B1(n1190), .Y(
n1140) );
AOI22X1TS U1842 ( .A0(n689), .A1(n1146), .B0(DmP[27]), .B1(n1155), .Y(n1142)
);
AOI22X1TS U1843 ( .A0(intDY[24]), .A1(n1146), .B0(DmP[24]), .B1(n1155), .Y(
n1143) );
AOI22X1TS U1844 ( .A0(intDY[28]), .A1(n1146), .B0(DmP[28]), .B1(n1144), .Y(
n1145) );
AOI22X1TS U1845 ( .A0(n1190), .A1(DMP[0]), .B0(intDY[0]), .B1(n1147), .Y(
n1148) );
AOI22X1TS U1846 ( .A0(n1196), .A1(DMP[7]), .B0(intDY[7]), .B1(n1161), .Y(
n1149) );
AOI22X1TS U1847 ( .A0(n1162), .A1(DMP[8]), .B0(intDY[8]), .B1(n1161), .Y(
n1150) );
AOI22X1TS U1848 ( .A0(n1196), .A1(DMP[3]), .B0(intDY[3]), .B1(n1161), .Y(
n1151) );
AOI22X1TS U1849 ( .A0(n1162), .A1(DMP[1]), .B0(intDY[1]), .B1(n1161), .Y(
n1152) );
AOI22X1TS U1850 ( .A0(n1186), .A1(DMP[2]), .B0(intDY[2]), .B1(n1161), .Y(
n1153) );
AOI22X1TS U1851 ( .A0(n1186), .A1(DMP[9]), .B0(intDY[9]), .B1(n1161), .Y(
n1154) );
BUFX3TS U1852 ( .A(n1165), .Y(n1195) );
AOI22X1TS U1853 ( .A0(intDY[23]), .A1(n1195), .B0(DmP[23]), .B1(n1155), .Y(
n1156) );
AOI22X1TS U1854 ( .A0(n1186), .A1(DMP[10]), .B0(intDY[10]), .B1(n1161), .Y(
n1157) );
AOI22X1TS U1855 ( .A0(n1196), .A1(DMP[4]), .B0(intDY[4]), .B1(n1161), .Y(
n1158) );
AOI22X1TS U1856 ( .A0(n1162), .A1(DMP[6]), .B0(intDY[6]), .B1(n1161), .Y(
n1159) );
AOI22X1TS U1857 ( .A0(n1186), .A1(DMP[5]), .B0(intDY[5]), .B1(n1161), .Y(
n1163) );
AOI22X1TS U1858 ( .A0(DmP[22]), .A1(n1162), .B0(intDY[22]), .B1(n1189), .Y(
n1166) );
AOI22X1TS U1859 ( .A0(DmP[11]), .A1(n1162), .B0(intDY[11]), .B1(n1189), .Y(
n1167) );
AOI22X1TS U1860 ( .A0(DmP[18]), .A1(n1162), .B0(intDY[18]), .B1(n1189), .Y(
n1168) );
AOI22X1TS U1861 ( .A0(DmP[15]), .A1(n1196), .B0(intDY[15]), .B1(n1189), .Y(
n1169) );
AOI22X1TS U1862 ( .A0(DmP[13]), .A1(n1186), .B0(intDY[13]), .B1(n1189), .Y(
n1170) );
AOI22X1TS U1863 ( .A0(DmP[14]), .A1(n1190), .B0(intDY[14]), .B1(n1189), .Y(
n1171) );
AOI22X1TS U1864 ( .A0(DmP[17]), .A1(n1186), .B0(intDY[17]), .B1(n1189), .Y(
n1172) );
AOI22X1TS U1865 ( .A0(DmP[8]), .A1(n1190), .B0(intDY[8]), .B1(n1195), .Y(
n1173) );
INVX2TS U1866 ( .A(n1217), .Y(n1178) );
NOR3BX1TS U1867 ( .AN(n1199), .B(n1190), .C(n1174), .Y(n1221) );
NOR4X1TS U1868 ( .A(n1221), .B(n1644), .C(n1450), .D(n1175), .Y(n1176) );
AOI22X1TS U1869 ( .A0(DmP[3]), .A1(n1162), .B0(intDY[3]), .B1(n1195), .Y(
n1180) );
AOI22X1TS U1870 ( .A0(DmP[1]), .A1(n1196), .B0(intDY[1]), .B1(n1195), .Y(
n1181) );
AOI22X1TS U1871 ( .A0(DmP[0]), .A1(n1190), .B0(intDY[0]), .B1(n1189), .Y(
n1182) );
AOI22X1TS U1872 ( .A0(intDX[12]), .A1(n1195), .B0(DMP[12]), .B1(n1162), .Y(
n1183) );
AOI22X1TS U1873 ( .A0(DmP[10]), .A1(n1186), .B0(intDY[10]), .B1(n1189), .Y(
n1184) );
AOI22X1TS U1874 ( .A0(DmP[2]), .A1(n1162), .B0(intDY[2]), .B1(n1195), .Y(
n1185) );
AOI22X1TS U1875 ( .A0(DmP[9]), .A1(n1190), .B0(intDY[9]), .B1(n1195), .Y(
n1187) );
AOI22X1TS U1876 ( .A0(DmP[16]), .A1(n1162), .B0(intDY[16]), .B1(n1189), .Y(
n1191) );
AOI22X1TS U1877 ( .A0(DmP[4]), .A1(n1186), .B0(intDY[4]), .B1(n1195), .Y(
n1193) );
AOI22X1TS U1878 ( .A0(DmP[6]), .A1(n1196), .B0(intDY[6]), .B1(n1195), .Y(
n1194) );
AOI22X1TS U1879 ( .A0(DmP[5]), .A1(n1186), .B0(intDY[5]), .B1(n1195), .Y(
n1197) );
INVX2TS U1880 ( .A(n1645), .Y(n1643) );
INVX2TS U1881 ( .A(n671), .Y(n1497) );
INVX2TS U1882 ( .A(n1645), .Y(n1203) );
OAI222X1TS U1883 ( .A0(n1202), .A1(n1761), .B0(n1679), .B1(n653), .C0(n1201),
.C1(n1200), .Y(n86) );
NOR4BX1TS U1884 ( .AN(n1207), .B(n1290), .C(n1337), .D(n1291), .Y(n1204) );
NOR4BX1TS U1885 ( .AN(n1204), .B(n1286), .C(n1287), .D(n1288), .Y(n1206) );
INVX2TS U1886 ( .A(n1285), .Y(n1205) );
OAI22X1TS U1887 ( .A0(n1209), .A1(n1208), .B0(n1756), .B1(n1207), .Y(n69) );
OAI21X1TS U1888 ( .A0(FSM_selector_C), .A1(n1210), .B0(n1643), .Y(n1216) );
AOI22X1TS U1889 ( .A0(FS_Module_state_reg[0]), .A1(n1450), .B0(n1212), .B1(
n1712), .Y(n1213) );
NAND2X1TS U1890 ( .A(FS_Module_state_reg[2]), .B(n1215), .Y(n1220) );
XNOR2X1TS U1891 ( .A(n1223), .B(n1222), .Y(n1224) );
INVX2TS U1892 ( .A(n1225), .Y(n1271) );
NOR2X1TS U1893 ( .A(n1752), .B(n1271), .Y(n1262) );
INVX2TS U1894 ( .A(n1262), .Y(n1229) );
AOI21X1TS U1895 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n1639), .B0(n1226), .Y(n1228) );
AOI22X1TS U1896 ( .A0(n676), .A1(Sgf_normalized_result[18]), .B0(n683), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .Y(n1227) );
NAND2X2TS U1897 ( .A(n1231), .B(n1273), .Y(n1261) );
AOI22X1TS U1898 ( .A0(n1237), .A1(n1232), .B0(n684), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .Y(n1235) );
AOI22X1TS U1899 ( .A0(n1272), .A1(Sgf_normalized_result[17]), .B0(n1639),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n1234) );
NAND2X1TS U1900 ( .A(n667), .B(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .Y(n1233) );
AOI22X1TS U1901 ( .A0(n1237), .A1(n1236), .B0(n685), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .Y(n1240) );
AOI22X1TS U1902 ( .A0(n676), .A1(Sgf_normalized_result[16]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .B1(n1639), .Y(n1239)
);
NAND2X1TS U1903 ( .A(n668), .B(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .Y(n1238) );
AOI22X1TS U1904 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n906), .B0(Barrel_Shifter_module_Mux_Array_Data_array[49]), .B1(n668),
.Y(n1244) );
AOI22X1TS U1905 ( .A0(n1272), .A1(Sgf_normalized_result[15]), .B0(n685),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n1243) );
NAND2X1TS U1906 ( .A(n1241), .B(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n1242) );
AOI22X1TS U1907 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(
n906), .B0(Barrel_Shifter_module_Mux_Array_Data_array[48]), .B1(n668),
.Y(n1247) );
AOI22X1TS U1908 ( .A0(n676), .A1(Sgf_normalized_result[14]), .B0(n684), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(n1246) );
NAND2X1TS U1909 ( .A(n1241), .B(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n1245) );
AOI22X1TS U1910 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n906), .B0(Barrel_Shifter_module_Mux_Array_Data_array[47]), .B1(n668),
.Y(n1250) );
AOI22X1TS U1911 ( .A0(n1272), .A1(Sgf_normalized_result[13]), .B0(n685),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n1249) );
NAND2X1TS U1912 ( .A(n1241), .B(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(n1248) );
NAND2X1TS U1913 ( .A(n1241), .B(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n1252) );
AOI22X1TS U1914 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n667), .B0(Barrel_Shifter_module_Mux_Array_Data_array[47]), .B1(n906),
.Y(n1251) );
AOI21X1TS U1915 ( .A0(n684), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .B0(n1253), .Y(n1254)
);
NAND2X1TS U1916 ( .A(n1261), .B(n1254), .Y(n59) );
AOI22X1TS U1917 ( .A0(n906), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(n668), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .Y(n1257) );
AOI22X1TS U1918 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .B0(n1272), .B1(
Sgf_normalized_result[11]), .Y(n1256) );
NAND2X1TS U1919 ( .A(n683), .B(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n1255) );
AOI22X1TS U1920 ( .A0(n906), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .B0(n667), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .Y(n1260) );
AOI22X1TS U1921 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .B0(n676), .B1(
Sgf_normalized_result[10]), .Y(n1259) );
NAND2X1TS U1922 ( .A(n684), .B(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n1258) );
AOI22X1TS U1923 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .B0(n667), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n1265) );
NAND2X1TS U1924 ( .A(n684), .B(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .Y(n1264) );
AOI22X1TS U1925 ( .A0(n1273), .A1(n1262), .B0(n1272), .B1(
Sgf_normalized_result[7]), .Y(n1263) );
AOI22X1TS U1926 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .B0(n668), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n1268) );
NAND2X1TS U1927 ( .A(n685), .B(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .Y(n1267) );
NOR2X1TS U1928 ( .A(n1751), .B(n1271), .Y(n1634) );
AOI22X1TS U1929 ( .A0(n1273), .A1(n1634), .B0(n676), .B1(
Sgf_normalized_result[6]), .Y(n1266) );
AOI22X1TS U1930 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .B0(n667), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(n1277) );
NAND2X1TS U1931 ( .A(n685), .B(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .Y(n1276) );
NOR2X1TS U1932 ( .A(n1753), .B(n1271), .Y(n1630) );
AOI22X1TS U1933 ( .A0(n1273), .A1(n1630), .B0(n1272), .B1(
Sgf_normalized_result[5]), .Y(n1275) );
INVX2TS U1934 ( .A(n1651), .Y(n1646) );
AOI21X2TS U1935 ( .A0(n1280), .A1(n1279), .B0(n1278), .Y(n1282) );
MXI2X1TS U1936 ( .A(n1692), .B(add_overflow_flag), .S0(n1292), .Y(n71) );
OR2X1TS U1937 ( .A(Add_Subt_result[3]), .B(Add_Subt_result[2]), .Y(n1295) );
AOI22X1TS U1938 ( .A0(n1312), .A1(n1295), .B0(n1294), .B1(n1293), .Y(n1328)
);
AOI22X1TS U1939 ( .A0(Add_Subt_result[10]), .A1(n1302), .B0(n1301), .B1(
Add_Subt_result[1]), .Y(n1308) );
NOR2X1TS U1940 ( .A(Add_Subt_result[11]), .B(Add_Subt_result[13]), .Y(n1311)
);
NAND2X1TS U1941 ( .A(n1327), .B(n1662), .Y(n1310) );
AOI21X1TS U1942 ( .A0(n1308), .A1(n1307), .B0(n1334), .Y(n1309) );
AOI22X1TS U1943 ( .A0(Add_Subt_result[5]), .A1(n1313), .B0(
Add_Subt_result[3]), .B1(n1312), .Y(n1314) );
OAI31X1TS U1944 ( .A0(Add_Subt_result[12]), .A1(n1730), .A2(n1329), .B0(
n1328), .Y(n1330) );
NOR4X1TS U1945 ( .A(n1333), .B(n1332), .C(n1331), .D(n1330), .Y(n1335) );
MXI2X1TS U1946 ( .A(n1335), .B(n1758), .S0(n1334), .Y(n74) );
INVX2TS U1947 ( .A(n1338), .Y(n1340) );
NAND2X1TS U1948 ( .A(n1340), .B(n1339), .Y(n1341) );
XOR2X1TS U1949 ( .A(n1342), .B(n1341), .Y(n1343) );
XOR2X1TS U1950 ( .A(n1351), .B(n1352), .Y(n1345) );
NAND2X1TS U1951 ( .A(n1347), .B(n1346), .Y(n1348) );
XNOR2X1TS U1952 ( .A(n1349), .B(n1348), .Y(n1350) );
INVX2TS U1953 ( .A(n1353), .Y(n1355) );
NAND2X1TS U1954 ( .A(n1355), .B(n1354), .Y(n1356) );
XNOR2X1TS U1955 ( .A(n1357), .B(n1356), .Y(n1358) );
INVX2TS U1956 ( .A(n1359), .Y(n1361) );
NAND2X1TS U1957 ( .A(n1361), .B(n1360), .Y(n1362) );
XOR2X1TS U1958 ( .A(n1363), .B(n1362), .Y(n1364) );
INVX2TS U1959 ( .A(n1365), .Y(n1392) );
INVX2TS U1960 ( .A(n1366), .Y(n1377) );
NAND2X1TS U1961 ( .A(n1377), .B(n1375), .Y(n1367) );
XNOR2X1TS U1962 ( .A(n1392), .B(n1367), .Y(n1368) );
NAND2X1TS U1963 ( .A(n1370), .B(n1369), .Y(n1371) );
XNOR2X1TS U1964 ( .A(n1372), .B(n1371), .Y(n1374) );
INVX2TS U1965 ( .A(n1373), .Y(n1450) );
AOI21X1TS U1966 ( .A0(n1392), .A1(n1377), .B0(n1376), .Y(n1382) );
INVX2TS U1967 ( .A(n1378), .Y(n1380) );
NAND2X1TS U1968 ( .A(n1380), .B(n1379), .Y(n1381) );
XOR2X1TS U1969 ( .A(n1382), .B(n1381), .Y(n1383) );
INVX2TS U1970 ( .A(n1384), .Y(n1386) );
NAND2X1TS U1971 ( .A(n1386), .B(n1385), .Y(n1387) );
XOR2X1TS U1972 ( .A(n1388), .B(n1387), .Y(n1389) );
AOI21X1TS U1973 ( .A0(n1392), .A1(n1391), .B0(n1390), .Y(n1403) );
INVX2TS U1974 ( .A(n1402), .Y(n1393) );
NAND2X1TS U1975 ( .A(n1393), .B(n1401), .Y(n1394) );
XOR2X1TS U1976 ( .A(n1403), .B(n1394), .Y(n1395) );
NAND2X1TS U1977 ( .A(n1397), .B(n1396), .Y(n1398) );
XNOR2X1TS U1978 ( .A(n1399), .B(n1398), .Y(n1400) );
INVX2TS U1979 ( .A(n1404), .Y(n1406) );
NAND2X1TS U1980 ( .A(n1406), .B(n1405), .Y(n1407) );
XNOR2X1TS U1981 ( .A(n1408), .B(n1407), .Y(n1409) );
INVX2TS U1982 ( .A(n1410), .Y(n1412) );
NAND2X1TS U1983 ( .A(n1412), .B(n1411), .Y(n1413) );
XOR2X1TS U1984 ( .A(n1414), .B(n1413), .Y(n1415) );
INVX2TS U1985 ( .A(n1426), .Y(n1417) );
NAND2X1TS U1986 ( .A(n1417), .B(n1425), .Y(n1418) );
XOR2X1TS U1987 ( .A(n1464), .B(n1418), .Y(n1419) );
NAND2X1TS U1988 ( .A(n1421), .B(n1420), .Y(n1422) );
XNOR2X1TS U1989 ( .A(n1423), .B(n1422), .Y(n1424) );
INVX2TS U1990 ( .A(n1427), .Y(n1429) );
NAND2X1TS U1991 ( .A(n1429), .B(n1428), .Y(n1430) );
XNOR2X1TS U1992 ( .A(n1431), .B(n1430), .Y(n1432) );
INVX2TS U1993 ( .A(n1433), .Y(n1449) );
AOI21X1TS U1994 ( .A0(n1449), .A1(n694), .B0(n1434), .Y(n1438) );
NAND2X1TS U1995 ( .A(n1436), .B(n1435), .Y(n1437) );
XOR2X1TS U1996 ( .A(n1438), .B(n1437), .Y(n1439) );
INVX2TS U1997 ( .A(n1440), .Y(n1443) );
INVX2TS U1998 ( .A(n1441), .Y(n1442) );
OAI21X1TS U1999 ( .A0(n1464), .A1(n1443), .B0(n1442), .Y(n1455) );
INVX2TS U2000 ( .A(n1444), .Y(n1454) );
NAND2X1TS U2001 ( .A(n1454), .B(n1452), .Y(n1445) );
XNOR2X1TS U2002 ( .A(n1455), .B(n1445), .Y(n1446) );
NAND2X1TS U2003 ( .A(n694), .B(n1447), .Y(n1448) );
XNOR2X1TS U2004 ( .A(n1449), .B(n1448), .Y(n1451) );
INVX2TS U2005 ( .A(n1452), .Y(n1453) );
AOI21X1TS U2006 ( .A0(n1455), .A1(n1454), .B0(n1453), .Y(n1460) );
INVX2TS U2007 ( .A(n1456), .Y(n1458) );
NAND2X1TS U2008 ( .A(n1458), .B(n1457), .Y(n1459) );
XOR2X1TS U2009 ( .A(n1460), .B(n1459), .Y(n1461) );
OAI21X1TS U2010 ( .A0(n1464), .A1(n1463), .B0(n1462), .Y(n1489) );
INVX2TS U2011 ( .A(n1489), .Y(n1479) );
INVX2TS U2012 ( .A(n1465), .Y(n1468) );
INVX2TS U2013 ( .A(n1466), .Y(n1467) );
OAI21X1TS U2014 ( .A0(n1479), .A1(n1468), .B0(n1467), .Y(n1484) );
INVX2TS U2015 ( .A(n1469), .Y(n1482) );
INVX2TS U2016 ( .A(n1481), .Y(n1470) );
AOI21X1TS U2017 ( .A0(n1484), .A1(n1482), .B0(n1470), .Y(n1475) );
INVX2TS U2018 ( .A(n1471), .Y(n1473) );
NAND2X1TS U2019 ( .A(n1473), .B(n1472), .Y(n1474) );
XOR2X1TS U2020 ( .A(n1475), .B(n1474), .Y(n1476) );
CLKMX2X2TS U2021 ( .A(Add_Subt_result[14]), .B(n1476), .S0(n1495), .Y(n230)
);
INVX2TS U2022 ( .A(n1477), .Y(n1488) );
NAND2X1TS U2023 ( .A(n1488), .B(n1486), .Y(n1478) );
XOR2X1TS U2024 ( .A(n1479), .B(n1478), .Y(n1480) );
NAND2X1TS U2025 ( .A(n1482), .B(n1481), .Y(n1483) );
XNOR2X1TS U2026 ( .A(n1484), .B(n1483), .Y(n1485) );
INVX2TS U2027 ( .A(n1486), .Y(n1487) );
AOI21X1TS U2028 ( .A0(n1489), .A1(n1488), .B0(n1487), .Y(n1494) );
INVX2TS U2029 ( .A(n1490), .Y(n1492) );
NAND2X1TS U2030 ( .A(n1492), .B(n1491), .Y(n1493) );
XOR2X1TS U2031 ( .A(n1494), .B(n1493), .Y(n1496) );
AOI22X1TS U2032 ( .A0(n1037), .A1(n1505), .B0(n679), .B1(n1498), .Y(n1503)
);
AOI22X1TS U2033 ( .A0(n1499), .A1(n1596), .B0(n686), .B1(n1506), .Y(n1501)
);
BUFX3TS U2034 ( .A(n1500), .Y(n1591) );
AOI32X1TS U2035 ( .A0(n1503), .A1(n1502), .A2(n1501), .B0(n1591), .B1(n1502),
.Y(Barrel_Shifter_module_Mux_Array_Data_array[22]) );
AOI22X1TS U2036 ( .A0(n679), .A1(n1506), .B0(n1596), .B1(n1505), .Y(n1512)
);
OA22X1TS U2037 ( .A0(n1509), .A1(n1508), .B0(n1507), .B1(n991), .Y(n1511) );
OAI2BB2XLTS U2038 ( .B0(n664), .B1(n1729), .A0N(DmP[13]), .A1N(n1560), .Y(
n1513) );
AOI21X1TS U2039 ( .A0(n669), .A1(Add_Subt_result[15]), .B0(n1513), .Y(n1534)
);
AOI22X2TS U2040 ( .A0(n1608), .A1(n1534), .B0(n1514), .B1(n1544), .Y(n1530)
);
AOI22X1TS U2041 ( .A0(n1590), .A1(n1525), .B0(n975), .B1(n1530), .Y(n1517)
);
AOI22X1TS U2042 ( .A0(n680), .A1(n1520), .B0(n1033), .B1(n1515), .Y(n1516)
);
NAND2X1TS U2043 ( .A(n1517), .B(n1516), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[15]) );
OAI2BB2XLTS U2044 ( .B0(n664), .B1(n1730), .A0N(DmP[12]), .A1N(n1560), .Y(
n1518) );
AOI21X1TS U2045 ( .A0(n1604), .A1(Add_Subt_result[14]), .B0(n1518), .Y(n1539) );
AOI22X2TS U2046 ( .A0(n1608), .A1(n1539), .B0(n1519), .B1(n1544), .Y(n1535)
);
AOI22X1TS U2047 ( .A0(n1037), .A1(n1530), .B0(n686), .B1(n1535), .Y(n1522)
);
AOI22X1TS U2048 ( .A0(n1602), .A1(n1525), .B0(n1596), .B1(n1520), .Y(n1521)
);
NAND2X1TS U2049 ( .A(n1522), .B(n1521), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[14]) );
AOI21X1TS U2050 ( .A0(n1604), .A1(Add_Subt_result[13]), .B0(n1523), .Y(n1545) );
AOI22X2TS U2051 ( .A0(n1608), .A1(n1545), .B0(n1524), .B1(n1544), .Y(n1540)
);
AOI22X1TS U2052 ( .A0(n1611), .A1(n1535), .B0(n687), .B1(n1540), .Y(n1527)
);
AOI22X1TS U2053 ( .A0(n1602), .A1(n1530), .B0(n1600), .B1(n1525), .Y(n1526)
);
NAND2X1TS U2054 ( .A(n1527), .B(n1526), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[13]) );
AOI21X1TS U2055 ( .A0(n1604), .A1(Add_Subt_result[12]), .B0(n1528), .Y(n1550) );
AOI22X2TS U2056 ( .A0(n1608), .A1(n1550), .B0(n1529), .B1(n1605), .Y(n1546)
);
AOI22X1TS U2057 ( .A0(n1590), .A1(n1540), .B0(n686), .B1(n1546), .Y(n1532)
);
AOI22X1TS U2058 ( .A0(n1602), .A1(n1535), .B0(n1600), .B1(n1530), .Y(n1531)
);
NAND2X1TS U2059 ( .A(n1532), .B(n1531), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[12]) );
AOI22X1TS U2060 ( .A0(n670), .A1(Add_Subt_result[14]), .B0(DmP[9]), .B1(
n1582), .Y(n1533) );
OA21XLTS U2061 ( .A0(n1555), .A1(n1730), .B0(n1533), .Y(n1556) );
AOI22X2TS U2062 ( .A0(n1594), .A1(n1556), .B0(n1534), .B1(n1544), .Y(n1551)
);
AOI22X1TS U2063 ( .A0(n1037), .A1(n1546), .B0(n687), .B1(n1551), .Y(n1537)
);
AOI22X1TS U2064 ( .A0(n680), .A1(n1540), .B0(n1600), .B1(n1535), .Y(n1536)
);
NAND2X1TS U2065 ( .A(n1537), .B(n1536), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[11]) );
INVX2TS U2066 ( .A(n991), .Y(n1590) );
AOI22X1TS U2067 ( .A0(n905), .A1(Add_Subt_result[15]), .B0(DmP[8]), .B1(
n1582), .Y(n1538) );
OA21XLTS U2068 ( .A0(n1555), .A1(n1729), .B0(n1538), .Y(n1562) );
AOI22X2TS U2069 ( .A0(n1594), .A1(n1562), .B0(n1539), .B1(n1605), .Y(n1557)
);
AOI22X1TS U2070 ( .A0(n1611), .A1(n1551), .B0(n686), .B1(n1557), .Y(n1542)
);
AOI22X1TS U2071 ( .A0(n680), .A1(n1546), .B0(n1033), .B1(n1540), .Y(n1541)
);
NAND2X1TS U2072 ( .A(n1542), .B(n1541), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[10]) );
AOI22X1TS U2073 ( .A0(n670), .A1(Add_Subt_result[16]), .B0(DmP[7]), .B1(
n1582), .Y(n1543) );
OA21XLTS U2074 ( .A0(n1555), .A1(n1738), .B0(n1543), .Y(n1567) );
AOI22X2TS U2075 ( .A0(n1594), .A1(n1567), .B0(n1545), .B1(n1544), .Y(n1563)
);
AOI22X1TS U2076 ( .A0(n1590), .A1(n1557), .B0(n975), .B1(n1563), .Y(n1548)
);
AOI22X1TS U2077 ( .A0(n680), .A1(n1551), .B0(n1033), .B1(n1546), .Y(n1547)
);
NAND2X1TS U2078 ( .A(n1548), .B(n1547), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[9]) );
AOI21X1TS U2079 ( .A0(n669), .A1(Add_Subt_result[8]), .B0(n1549), .Y(n1572)
);
AOI22X2TS U2080 ( .A0(n1594), .A1(n1572), .B0(n1550), .B1(n1591), .Y(n1568)
);
AOI22X1TS U2081 ( .A0(n1037), .A1(n1563), .B0(n687), .B1(n1568), .Y(n1553)
);
AOI22X1TS U2082 ( .A0(n1602), .A1(n1557), .B0(n1600), .B1(n1551), .Y(n1552)
);
NAND2X1TS U2083 ( .A(n1553), .B(n1552), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[8]) );
AOI22X1TS U2084 ( .A0(n1603), .A1(Add_Subt_result[18]), .B0(DmP[5]), .B1(
n1582), .Y(n1554) );
OA21XLTS U2085 ( .A0(n1555), .A1(n1736), .B0(n1554), .Y(n1576) );
AOI22X2TS U2086 ( .A0(n1594), .A1(n1576), .B0(n1556), .B1(n1591), .Y(n1573)
);
AOI22X1TS U2087 ( .A0(n1590), .A1(n1568), .B0(n687), .B1(n1573), .Y(n1559)
);
AOI22X1TS U2088 ( .A0(n680), .A1(n1563), .B0(n1033), .B1(n1557), .Y(n1558)
);
NAND2X1TS U2089 ( .A(n1559), .B(n1558), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[7]) );
OAI2BB2XLTS U2090 ( .B0(n664), .B1(n1739), .A0N(DmP[4]), .A1N(n1560), .Y(
n1561) );
AOI21X1TS U2091 ( .A0(n1604), .A1(Add_Subt_result[6]), .B0(n1561), .Y(n1583)
);
AOI22X2TS U2092 ( .A0(n1594), .A1(n1583), .B0(n1562), .B1(n1591), .Y(n1579)
);
AOI22X1TS U2093 ( .A0(n1037), .A1(n1573), .B0(n686), .B1(n1579), .Y(n1565)
);
AOI22X1TS U2094 ( .A0(n1602), .A1(n1568), .B0(n1600), .B1(n1563), .Y(n1564)
);
NAND2X1TS U2095 ( .A(n1565), .B(n1564), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[6]) );
AOI21X1TS U2096 ( .A0(n1604), .A1(Add_Subt_result[5]), .B0(n1566), .Y(n1592)
);
AOI22X2TS U2097 ( .A0(n1594), .A1(n1592), .B0(n1567), .B1(n1591), .Y(n1587)
);
AOI22X1TS U2098 ( .A0(n1611), .A1(n1579), .B0(n687), .B1(n1587), .Y(n1570)
);
AOI22X1TS U2099 ( .A0(n680), .A1(n1573), .B0(n1033), .B1(n1568), .Y(n1569)
);
NAND2X1TS U2100 ( .A(n1570), .B(n1569), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[5]) );
AOI21X1TS U2101 ( .A0(n1604), .A1(Add_Subt_result[4]), .B0(n1571), .Y(n1606)
);
AOI22X2TS U2102 ( .A0(n1594), .A1(n1606), .B0(n1572), .B1(n1591), .Y(n1595)
);
AOI22X1TS U2103 ( .A0(n1590), .A1(n1587), .B0(n686), .B1(n1595), .Y(n1575)
);
AOI22X1TS U2104 ( .A0(n1602), .A1(n1579), .B0(n1600), .B1(n1573), .Y(n1574)
);
NAND2X1TS U2105 ( .A(n1575), .B(n1574), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[4]) );
AOI22X1TS U2106 ( .A0(n1603), .A1(Add_Subt_result[22]), .B0(DmP[1]), .B1(
n1582), .Y(n1578) );
NAND2X1TS U2107 ( .A(Add_Subt_result[3]), .B(n1604), .Y(n1577) );
AOI22X1TS U2108 ( .A0(n1037), .A1(n1595), .B0(n687), .B1(n1599), .Y(n1581)
);
AOI22X1TS U2109 ( .A0(n680), .A1(n1587), .B0(n1033), .B1(n1579), .Y(n1580)
);
NAND2X1TS U2110 ( .A(n1581), .B(n1580), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[3]) );
AOI22X1TS U2111 ( .A0(n670), .A1(Add_Subt_result[23]), .B0(DmP[0]), .B1(
n1582), .Y(n1586) );
NAND2X1TS U2112 ( .A(Add_Subt_result[2]), .B(n1604), .Y(n1584) );
AOI22X1TS U2113 ( .A0(n1611), .A1(n1599), .B0(n687), .B1(n1601), .Y(n1589)
);
AOI22X1TS U2114 ( .A0(n680), .A1(n1595), .B0(n1600), .B1(n1587), .Y(n1588)
);
NAND2X1TS U2115 ( .A(n1589), .B(n1588), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[2]) );
AOI22X1TS U2116 ( .A0(n1611), .A1(n1601), .B0(n680), .B1(n1599), .Y(n1598)
);
AOI22X1TS U2117 ( .A0(n1604), .A1(Add_Subt_result[1]), .B0(n1603), .B1(
Add_Subt_result[24]), .Y(n1593) );
AOI22X1TS U2118 ( .A0(n1594), .A1(n1593), .B0(n1592), .B1(n1591), .Y(n1610)
);
AOI22X1TS U2119 ( .A0(n686), .A1(n1610), .B0(n1033), .B1(n1595), .Y(n1597)
);
NAND2X1TS U2120 ( .A(n1598), .B(n1597), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[1]) );
AOI22X1TS U2121 ( .A0(n1602), .A1(n1601), .B0(n1033), .B1(n1599), .Y(n1613)
);
AOI22X1TS U2122 ( .A0(n669), .A1(Add_Subt_result[0]), .B0(
Add_Subt_result[25]), .B1(n670), .Y(n1607) );
AOI22X1TS U2123 ( .A0(n1608), .A1(n1607), .B0(n1606), .B1(n1605), .Y(n1609)
);
AOI22X1TS U2124 ( .A0(n1611), .A1(n1610), .B0(n686), .B1(n1609), .Y(n1612)
);
NAND2X1TS U2125 ( .A(n1613), .B(n1612), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[0]) );
OAI2BB2XLTS U2126 ( .B0(n1740), .B1(n671), .A0N(final_result_ieee[22]),
.A1N(n1629), .Y(n13) );
OAI2BB2XLTS U2127 ( .B0(n1741), .B1(n672), .A0N(final_result_ieee[21]),
.A1N(n1629), .Y(n16) );
INVX2TS U2128 ( .A(n1614), .Y(n1615) );
AOI21X1TS U2129 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[36]), .A1(
n1635), .B0(n1615), .Y(n1616) );
OA22X1TS U2130 ( .A0(n1638), .A1(n1741), .B0(n1616), .B1(n1636), .Y(n1618)
);
AOI22X1TS U2131 ( .A0(n684), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .B0(n1639), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .Y(n1617) );
OAI2BB2XLTS U2132 ( .B0(n1742), .B1(n673), .A0N(final_result_ieee[20]),
.A1N(n1629), .Y(n20) );
INVX2TS U2133 ( .A(n1619), .Y(n1620) );
AOI21X1TS U2134 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[37]), .A1(
n1635), .B0(n1620), .Y(n1621) );
OA22X1TS U2135 ( .A0(n1638), .A1(n1742), .B0(n1621), .B1(n1636), .Y(n1623)
);
AOI22X1TS U2136 ( .A0(n685), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .B0(n1639), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .Y(n1622) );
OAI2BB2XLTS U2137 ( .B0(n1731), .B1(n672), .A0N(final_result_ieee[19]),
.A1N(n1629), .Y(n24) );
INVX2TS U2138 ( .A(n1624), .Y(n1625) );
AOI21X1TS U2139 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[38]), .A1(
n1635), .B0(n1625), .Y(n1626) );
OA22X1TS U2140 ( .A0(n1638), .A1(n1731), .B0(n1626), .B1(n1636), .Y(n1628)
);
AOI22X1TS U2141 ( .A0(n684), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .B0(n1639), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(n1627) );
OAI2BB2XLTS U2142 ( .B0(n1732), .B1(n673), .A0N(final_result_ieee[18]),
.A1N(n1629), .Y(n28) );
AOI21X1TS U2143 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[39]), .A1(
n1635), .B0(n1630), .Y(n1631) );
OA22X1TS U2144 ( .A0(n1638), .A1(n1732), .B0(n1631), .B1(n1636), .Y(n1633)
);
AOI22X1TS U2145 ( .A0(n685), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .B0(n1639), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .Y(n1632) );
OAI2BB2XLTS U2146 ( .B0(n1726), .B1(n672), .A0N(final_result_ieee[17]),
.A1N(n1203), .Y(n32) );
AOI21X1TS U2147 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[40]), .A1(
n1635), .B0(n1634), .Y(n1637) );
OA22X1TS U2148 ( .A0(n1638), .A1(n1726), .B0(n1637), .B1(n1636), .Y(n1642)
);
AOI22X1TS U2149 ( .A0(n684), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .B0(n1639), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .Y(n1641) );
OAI2BB2XLTS U2150 ( .B0(n1693), .B1(n671), .A0N(final_result_ieee[12]),
.A1N(n1643), .Y(n52) );
OAI2BB2XLTS U2151 ( .B0(n1716), .B1(n673), .A0N(final_result_ieee[11]),
.A1N(n1203), .Y(n56) );
OAI2BB2XLTS U2152 ( .B0(n1717), .B1(n673), .A0N(final_result_ieee[10]),
.A1N(n1643), .Y(n58) );
OA22X1TS U2153 ( .A0(exp_oper_result[7]), .A1(n672), .B0(n1644), .B1(
final_result_ieee[30]), .Y(n60) );
OA22X1TS U2154 ( .A0(exp_oper_result[6]), .A1(n673), .B0(n1644), .B1(
final_result_ieee[29]), .Y(n61) );
OA22X1TS U2155 ( .A0(exp_oper_result[5]), .A1(n672), .B0(n1644), .B1(
final_result_ieee[28]), .Y(n62) );
OA22X1TS U2156 ( .A0(n1644), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n672), .Y(n63) );
OA22X1TS U2157 ( .A0(n1644), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n673), .Y(n64) );
OA22X1TS U2158 ( .A0(n1644), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n672), .Y(n65) );
OA22X1TS U2159 ( .A0(n1644), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n673), .Y(n66) );
OA22X1TS U2160 ( .A0(n1645), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n673), .Y(n67) );
INVX2TS U2161 ( .A(n1651), .Y(n1648) );
BUFX3TS U2162 ( .A(n1654), .Y(n1657) );
OAI2BB2XLTS U2163 ( .B0(n1658), .B1(n1671), .A0N(n1657), .A1N(Data_Y[7]),
.Y(n111) );
OAI2BB2XLTS U2164 ( .B0(n1651), .B1(n1719), .A0N(n1655), .A1N(Data_Y[12]),
.Y(n126) );
BUFX3TS U2165 ( .A(n1651), .Y(n1649) );
INVX2TS U2166 ( .A(n1651), .Y(n1652) );
OAI2BB2XLTS U2167 ( .B0(n1658), .B1(n1724), .A0N(n1655), .A1N(Data_X[10]),
.Y(n193) );
BUFX3TS U2168 ( .A(n1654), .Y(n1656) );
OAI2BB2XLTS U2169 ( .B0(n1656), .B1(n1698), .A0N(n1655), .A1N(Data_X[13]),
.Y(n196) );
OAI2BB2XLTS U2170 ( .B0(n1656), .B1(n1699), .A0N(n1655), .A1N(Data_X[14]),
.Y(n197) );
OAI2BB2XLTS U2171 ( .B0(n1656), .B1(n1695), .A0N(n1655), .A1N(Data_X[15]),
.Y(n198) );
OAI2BB2XLTS U2172 ( .B0(n1656), .B1(n1733), .A0N(n1655), .A1N(Data_X[16]),
.Y(n199) );
OAI2BB2XLTS U2173 ( .B0(n1656), .B1(n1696), .A0N(n1655), .A1N(Data_X[17]),
.Y(n200) );
OAI2BB2XLTS U2174 ( .B0(n1656), .B1(n1697), .A0N(n1655), .A1N(Data_X[18]),
.Y(n201) );
OAI2BB2XLTS U2175 ( .B0(n1656), .B1(n1700), .A0N(n1655), .A1N(Data_X[19]),
.Y(n202) );
OAI2BB2XLTS U2176 ( .B0(n1656), .B1(n1659), .A0N(n1657), .A1N(Data_X[20]),
.Y(n203) );
OAI2BB2XLTS U2177 ( .B0(n1656), .B1(n1667), .A0N(n1657), .A1N(Data_X[21]),
.Y(n204) );
OAI2BB2XLTS U2178 ( .B0(n1656), .B1(n1668), .A0N(n1657), .A1N(Data_X[22]),
.Y(n205) );
OAI2BB2XLTS U2179 ( .B0(n1658), .B1(n1664), .A0N(n1657), .A1N(Data_X[23]),
.Y(n206) );
OAI2BB2XLTS U2180 ( .B0(n1658), .B1(n1669), .A0N(n1657), .A1N(Data_X[24]),
.Y(n207) );
OAI2BB2XLTS U2181 ( .B0(n1658), .B1(n1665), .A0N(n1657), .A1N(Data_X[25]),
.Y(n208) );
OAI2BB2XLTS U2182 ( .B0(n1658), .B1(n1670), .A0N(n1657), .A1N(Data_X[26]),
.Y(n209) );
OAI2BB2XLTS U2183 ( .B0(n1658), .B1(n1666), .A0N(n1657), .A1N(Data_X[27]),
.Y(n210) );
OAI2BB2XLTS U2184 ( .B0(n1658), .B1(n1723), .A0N(n1657), .A1N(Data_X[28]),
.Y(n211) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module cmd_seq #(
parameter BASEADDR = 32'h0000,
parameter HIGHADDR = 32'h0000,
parameter ABUSWIDTH = 16,
parameter OUTPUTS = 1,
parameter CMD_MEM_SIZE = 2048
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire [OUTPUTS-1:0] CMD_CLK_OUT,
input wire CMD_CLK_IN,
input wire CMD_EXT_START_FLAG,
output wire CMD_EXT_START_ENABLE,
output wire [OUTPUTS-1:0] CMD_DATA,
output wire CMD_READY,
output wire CMD_START_FLAG
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
cmd_seq_core #(
.CMD_MEM_SIZE(CMD_MEM_SIZE),
.ABUSWIDTH(ABUSWIDTH),
.OUTPUTS(OUTPUTS)
) i_cmd_seq_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CMD_CLK_OUT(CMD_CLK_OUT),
.CMD_CLK_IN(CMD_CLK_IN),
.CMD_EXT_START_FLAG(CMD_EXT_START_FLAG),
.CMD_EXT_START_ENABLE(CMD_EXT_START_ENABLE),
.CMD_DATA(CMD_DATA),
.CMD_READY(CMD_READY),
.CMD_START_FLAG(CMD_START_FLAG)
);
endmodule
|
`timescale 1ns / 1ps
module testbench;
localparam CLOCK_FREQ_HZ = 12e6;
localparam BAUD_RATE = 115200;
reg clk = 0;
initial begin
#(1.5e9 / CLOCK_FREQ_HZ);
forever #(0.5e9 / CLOCK_FREQ_HZ) clk = ~clk;
end
reg resetq = 0;
initial begin
repeat (100) @(posedge clk);
resetq <= 1;
end
reg RXD = 1;
wire TXD;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
// wait 10 bit times
repeat (10) #(1e9 / BAUD_RATE);
// send 'a' (b01100001)
#(1e9 / BAUD_RATE); RXD <= 0; // start bit
#(1e9 / BAUD_RATE); RXD <= 1; // data bit #0 (LSB)
#(1e9 / BAUD_RATE); RXD <= 0; // data bit #1
#(1e9 / BAUD_RATE); RXD <= 0; // data bit #2
#(1e9 / BAUD_RATE); RXD <= 0; // data bit #3
#(1e9 / BAUD_RATE); RXD <= 0; // data bit #4
#(1e9 / BAUD_RATE); RXD <= 1; // data bit #5
#(1e9 / BAUD_RATE); RXD <= 1; // data bit #6
#(1e9 / BAUD_RATE); RXD <= 0; // data bit #7 (MSB)
#(1e9 / BAUD_RATE); RXD <= 1; // stop bit
// wait 100 bit times
repeat (100) #(1e9 / BAUD_RATE);
$finish;
end
reg [7:0] tx_buffer;
integer i;
always begin
// tx start bit
@(negedge TXD);
#(0.5e9 / BAUD_RATE);
// tx data bits
tx_buffer = 0;
for (i = 0; i < 8; i = i+1) begin
#(1e9 / BAUD_RATE);
tx_buffer = tx_buffer | (TXD << i);
end
if (tx_buffer < 32)
$display("TX char: hex %02x", tx_buffer);
else
$display("TX char: '%c'", tx_buffer);
end
top uut (
.clk(clk),
.resetq(resetq),
.TXD(TXD),
.RXD(RXD)
);
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.