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import "DPI-C" context function int init_socket();
import "DPI-C" context function void close_socket();
import "DPI-C" context function void senduart(input bit[7:0] in);
import "DPI-C" context function bit[8:0] recuart();
module simuart(input wire clk,
input wire cs,
input wire [31:0] bus_addr,
input wire [31:0] bus_wr_val,
input wire [3:0] bus_bytesel,
output reg bus_ack,
output reg [31:0] bus_data,
output reg inter,
input wire intack
);
reg [8:0] uart_buf;
reg ff;
reg ffold;
initial begin
bus_ack = 1'b0;
bus_data = 32'b0;
inter = 1'b0;
init_socket();
end
final begin
close_socket();
end
always @(posedge clk) begin
bus_data <= 32'b0;
ff <= 1'b0;
ffold <= 1'b0;
if (~uart_buf[8] && ~cs)
uart_buf <= recuart();
ff<=ffold;
if (uart_buf[8] && (uart_buf[7:0]==8'h3)) begin
if(intack==1'b0) begin
inter <=1'b1;
end else begin
uart_buf[8]<=1'b0;
end
end else begin
if (cs && bus_bytesel[3:0] == 4'b0001) begin
if (bus_addr[3:0] == 4'b0000) begin
senduart(bus_wr_val[7:0]);
end
if (bus_addr[3:0] == 4'b1000) begin
inter<=1'b0;
end
if (bus_addr[3:0] == 4'b1100) begin
inter<=1'b1;
end
end else if (cs) begin
if (bus_addr[3:0] == 4'b0000) begin
bus_data <= {24'b0, uart_buf[7:0]};
ff <= 1'b1;
if (ff && ~ffold) uart_buf[8] <= 1'b0;
end else if (bus_addr[3:0] == 4'b0100) begin
/* Status register read. */
bus_data <= (uart_buf[8] ? 32'b10 : 32'b0);
end
end
end
bus_ack <= cs;
end
endmodule
|
// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
// web: http://www.terasic.com/
// email: [email protected]
//
// ============================================================================
//Date: Thu Jul 11 11:26:45 2013
// ============================================================================
`timescale 1 ps / 1 ps
module de1_soc_proc(
///////// CLOCK2 /////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
///////// GPIO /////////
inout [35:0] GPIO_0,
///////// HEX0 /////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
///////// KEY /////////
input [3:0] KEY,
///////// LEDR /////////
output [9:0] LEDR,
///////// SW /////////
input [9:0] SW
);
reg rCPU_CLK = 1;
integer dCPU_CLK_CNTR = 0;
assign LEDR[8] = rCPU_CLK;
always@(posedge CLOCK2_50)
begin
if(dCPU_CLK_CNTR == 250000) begin
dCPU_CLK_CNTR <= 0;
rCPU_CLK <= ~rCPU_CLK;
end
else begin
dCPU_CLK_CNTR <= dCPU_CLK_CNTR + 1;
end
end
core core(
.iCLK(rCPU_CLK),
.iGPI(SW[7:0]),
.oGPO(LEDR[7:0])
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ea_e
//
// Generated
// by: wig
// on: Thu Jul 6 05:51:58 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../autoopen.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ea_e.v,v 1.4 2006/07/10 07:30:09 wig Exp $
// $Date: 2006/07/10 07:30:09 $
// $Log: inst_ea_e.v,v $
// Revision 1.4 2006/07/10 07:30:09 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_ea_e
//
// No user `defines in this module
module inst_ea_e
//
// Generated Module inst_ea
//
(
s_eo1,
s_eo2,
s_eo3,
s_eo4,
s_eo5
);
// Generated Module Inputs:
input s_eo4;
// Generated Module Outputs:
output s_eo1;
output s_eo2;
output s_eo3;
output s_eo5;
// Generated Wires:
wire s_eo1;
wire s_eo2;
wire s_eo3;
wire s_eo4;
wire s_eo5;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_eaa
inst_eaa_e inst_eaa (
);
// End of Generated Instance Port Map for inst_eaa
// Generated Instance Port Map for inst_eab
inst_eab_e inst_eab (
);
// End of Generated Instance Port Map for inst_eab
// Generated Instance Port Map for inst_eac
inst_eac_e inst_eac (
);
// End of Generated Instance Port Map for inst_eac
endmodule
//
// End of Generated Module rtl of inst_ea_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
module Decoder(clk, sig, numOut);
/***
This module decodes an input signal, sig, reading a number, num. The encoding is as follows: an initial HIGH pulse of length, tau_w clock cycles, appears, followed by an LOW pulse of equal length. After the LOW pulse, the bits are encoded from most significant bit to least in time bins of length, tau_w, with bins adjacent to one another. Finally, the input goes LOW. For example, a bit sequence along the lines of
1110001111110001110000000
would give a binary number, 1101.
This module decodes the signal by timing the initial HIGH pulse to determine tau_w, and then averaging a portion of the input sequence in each time bin of the recorded length, tau_w.
Ted Golfinopoulos, 9 Aug 2012
*/
parameter NUM_SIZE=7;
parameter TIMER_SIZE=13; //Number of bits in timer for measuring duration of ON/OFF pulses in clock cycles. For 10E6 Hz clock and 2E3 Hz maximum input signal, ON/OFF pulses are 1/2E3 Hz = 500 us, so register has to be able to count to at least 10E6/2E3 = 5E3 < 2^13 = 8192.
parameter THRESHOLD_TIME=127; //Number of consecutive clock cycles that the signal must hold its value before the state is accepted as genuine.
input clk, sig;
output wire [NUM_SIZE-1:0] numOut;
reg [NUM_SIZE-1:0] newNum, lastNum;
reg [3:0] numIndex; //Number to indicate where to index into encoded binary number.
reg sigLast; //Bit holding last value of input state.
//Timers and pulse width registers.
reg [TIMER_SIZE-1:0] sigTimer, sequenceTimer, tau_w;
reg [1:0] stageInSequence; //Number representing the stage in searching for and parsing numbers from serial bit sequences - see below.
reg numLock; //When this bit is high, don't allow changes to bits in decoded number.
assign numOut=lastNum; //Assign wire output to lastNum register.
initial begin
lastNum=1'b0; //Initialize output.
newNum=1'b0;
sigTimer=1'b0;
sequenceTimer=1'b0;
tau_w=1'b1;
sigLast=1'b0;
stageInSequence=1'b0;
numIndex=1'b0;
numLock=1'b0;
end
always @(posedge clk) begin
//STAGES IN SEQUENCE:
//0 => waiting for a new sequence.
//1 => timing initial on pulse.
//2 => waiting for off time that separates initial arm pulse from number pulse.
//3 => parsing number pulse
//TIME HOW LONG SIG HAS BEEN IN CURRENT STATE
if(sig==sigLast) begin
//Note - this timer will overflow.
sigTimer=sigTimer+1'b1;
end else begin
//$display("State change");
if(stageInSequence==1'b1) begin
tau_w=sigTimer; //If we are timing the pulse length, record time.
stageInSequence=2'b10; //Advance to next stage - wait for off pulse to finish.
sequenceTimer=1'b0; //Reset sequence timer.
sigTimer=1'b0; //Reset signal timer.
//$display("stageInSequence=%b, sig=%b, tau_w=%d",stageInSequence,sig,tau_w);
end
sigTimer=1'b0; //Reset signal timer.
sigLast=sig; //Update register holding last value of sig.
end
//Look for arm pulses - if found, time the arm pulse to calibrate the length of pulses in the sequence.
if(sigLast && sigTimer>THRESHOLD_TIME && stageInSequence==1'b0) begin
stageInSequence=1'b1; //Time initial on pulse to calibrate tau_w.
//$display("stageInSequence=%b, sig=%b",stageInSequence,sig);
end
//SEQUENCE TIMER
if(sequenceTimer<tau_w && stageInSequence>2'b01) begin
sequenceTimer=sequenceTimer+1'b1; //Increment timer
end else begin //Reset timer and increment index into parsed number.
if(stageInSequence==2'b10) begin
//Initial off period between arm pulse and number pulse is complete - advance stage in sequence.
stageInSequence=2'b11;
numIndex=1'b0;
numLock=1'b0; //Turn off lock for changing bit values.
//$display("stageInSequence=%b, sig=%b",stageInSequence,sig);
end else if(stageInSequence==2'b11) begin
numIndex=numIndex+1'b1; //Increment index in parsed number.
numLock=1'b0; //Turn off lock on bit value for current number in sequence.
end
sequenceTimer=1'b0;
//Reset signal timer - otherwise, can have repeated bits which are immediately
//accepted as valid because they have been on for over the threshold time.
if(stageInSequence>2'b01) begin sigTimer=1'b0; end
end
//STAGE 3 - PARSE NUMBERS FROM INPUT SEQUENCE.
if(stageInSequence==2'b11) begin
if(numIndex>=NUM_SIZE) begin
lastNum=newNum; //Update stored number.
stageInSequence=1'b0; //Number has been parsed - sequence is done.
//$display("stageInSequence=%b, sig=%b",stageInSequence,sig);
end else if(sigTimer>THRESHOLD_TIME && !numLock) begin
newNum[NUM_SIZE-1-numIndex]=sigLast; //Update bit in new number.
numLock=1'b1; //Don't allow any more changes for this bit in the number.
//$display("Recorded bit, %b, which has held for %d cycles", sigLast,sigTimer);
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:18:06 04/02/2016
// Design Name: Alejandro Morales; AMP
// Module Name: VGA_text
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module VGA_text
(
input [7:0] estado,
input [3:0]RG1_Dec,
input [3:0]RG2_Dec,
input [3:0]RG3_Dec,
input [3:0]RG1_Unit,
input [3:0]RG2_Unit,
input [3:0]RG3_Unit,
input escribiendo,
input en_out,
input wire CLK, off_alarma, on_alarma, //preguntar al profe cual es clk ???
input wire [3:0] dig0_Dec, dig1_Unit, direccion,
input wire [9:0] pix_x, pix_y,
output wire [8:0] text_on,
output reg [2:0] text_rgb,
output [7:0] seg_Ti,
output [7:0] min_Ti,
output [7:0] hor_Ti
);
wire [10:0] rom_addr;
reg [6:0] char_addr, char_addr_H, char_addr_F,
char_addr_C, char_addr_EN1, char_addr_EN2, char_addr_EN3, char_addr_EN4, char_addr_TF, char_addr_sep;
reg [3:0] row_addr;
wire [3:0] row_addr_H, row_addr_F, row_addr_C, row_addr_EN1, row_addr_EN2, row_addr_EN3, row_addr_EN4, row_addr_TF, row_addr_sep;
reg [2:0] bit_addr;
wire [2:0] bit_addr_H, bit_addr_F,bit_addr_C, bit_addr_EN1, bit_addr_EN2, bit_addr_EN3, bit_addr_EN4, bit_addr_TF, bit_addr_sep;
wire [7:0] font_word;
wire font_bit, HORA_on, FECHA_on, CRONOMETRO_on, TCRONOFIN_on, ENCABEZADO1_on, ENCABEZADO2_on, ENCABEZADO3_on, ENCABEZADO4_on,separa_on;
wire [3:0] dig_Dec_Ho, dig_Dec_min, dig_Dec_seg, dig_Dec_mes, dig_Dec_dia, dig_Dec_an, dig_Dec_Ho_Ti, dig_Dec_min_Ti, dig_Dec_seg_Ti;
wire [3:0] dig_Unit_Ho, dig_Unit_min, dig_Unit_seg, dig_Unit_mes, dig_Unit_dia, dig_Unit_an, dig_Unit_Ho_Ti, dig_Unit_min_Ti, dig_Unit_seg_Ti;
assign pix_x [0]=0;
assign seg_Ti= {dig_Dec_seg_Ti,dig_Unit_seg_Ti};
assign min_Ti= {dig_Dec_min_Ti,dig_Unit_min_Ti};
assign hor_Ti= {dig_Dec_Ho_Ti,dig_Unit_Ho_Ti};
// Instanciación de la ROM
font_rom font_unit
(.Clk(CLK), .addr(rom_addr), .data(font_word));
// instantiate control de digitos
control_digitos_1 digitos_1_unit
(
.estado(estado),
.RG1_Dec(RG1_Dec),
.RG2_Dec(RG2_Dec),
.RG3_Dec(RG3_Dec),
.escribiendo(escribiendo),
.en_out(en_out),
.clk(CLK),
.dig0_Dec(dig0_Dec),
.direccion(direccion),
.dig_Dec_Ho (dig_Dec_Ho), .dig_Dec_min (dig_Dec_min), .dig_Dec_seg (dig_Dec_seg),
.dig_Dec_mes (dig_Dec_mes), .dig_Dec_dia(dig_Dec_dia), .dig_Dec_an (dig_Dec_an),
.dig_Dec_Ho_Ti (dig_Dec_Ho_Ti), .dig_Dec_min_Ti (dig_Dec_min_Ti), .dig_Dec_seg_Ti (dig_Dec_seg_Ti)
);
// instantiate control de digitos 2
control_digitos_2 digitos_2_unit
(
.estado(estado),
.RG1_Unit(RG1_Unit),
.RG2_Unit(RG2_Unit),
.RG3_Unit(RG3_Unit),
.escribiendo(escribiendo),
.en_out(en_out),
.clk(CLK),
.dig1_Unit(dig1_Unit),
.direccion (direccion),
.dig_Unit_Ho (dig_Unit_Ho), .dig_Unit_min (dig_Unit_min), .dig_Unit_seg (dig_Unit_seg),
.dig_Unit_mes (dig_Unit_mes), .dig_Unit_dia (dig_Unit_dia), .dig_Unit_an (dig_Unit_an),
.dig_Unit_Ho_Ti (dig_Unit_Ho_Ti), .dig_Unit_min_Ti (dig_Unit_min_Ti), .dig_Unit_seg_Ti (dig_Unit_seg_Ti)
);
//-------------------------------------------
// Region de Encabezado1
// - escala 16(x)-a-16(y) de fuente, 640x480=40x15
// - line 1, 35 caracteres: "Instituto Tecnologico de Costa Rica"
//-------------------------------------------
assign ENCABEZADO1_on = (pix_y[9:4]==0) && (2<=pix_x[9:4]<=36);//los bits sobrantes son lo que tienen que dar 2^5=32
assign row_addr_EN1 = pix_y[3:0];
assign bit_addr_EN1 = pix_x[3:1];
always @*
case (pix_x[9:4])// 6 bits 2^6=64, tengo que poner un default para los extra
6'h2: char_addr_EN1 = 7'h49; // I
6'h3: char_addr_EN1 = 7'h6e; // n
6'h4: char_addr_EN1 = 7'h73; // s
6'h5: char_addr_EN1 = 7'h74; // t
6'h6: char_addr_EN1 = 7'h69; // i
6'h7: char_addr_EN1 = 7'h74; // t
6'h8: char_addr_EN1 = 7'h75; // u
6'h9: char_addr_EN1 = 7'h74; // t
6'ha: char_addr_EN1 = 7'h6f; // o
6'hb: char_addr_EN1 = 7'h00; //
6'hc: char_addr_EN1 = 7'h54; // T
6'hd: char_addr_EN1 = 7'h65; // e
6'he: char_addr_EN1 = 7'h63; // c
6'hf: char_addr_EN1 = 7'h6e; // n
6'h10: char_addr_EN1 = 7'h6f; // o
6'h11: char_addr_EN1 = 7'h6c; // l
6'h12: char_addr_EN1 = 7'h6f; // o
6'h13: char_addr_EN1 = 7'h67; // g
6'h14: char_addr_EN1 = 7'h69; // i
6'h15: char_addr_EN1 = 7'h63; // c
6'h16: char_addr_EN1 = 7'h6f; // o
6'h17: char_addr_EN1 = 7'h00; //
6'h18: char_addr_EN1 = 7'h64; // d
6'h19: char_addr_EN1 = 7'h65; // e
6'h1a: char_addr_EN1 = 7'h00; //
6'h1b: char_addr_EN1 = 7'h43; // C
6'h1c: char_addr_EN1 = 7'h6f; // o
6'h1d: char_addr_EN1 = 7'h73; // s
6'h1e: char_addr_EN1 = 7'h74; // t
6'h1f: char_addr_EN1 = 7'h61; // a
6'h20: char_addr_EN1 = 7'h00; //
6'h21: char_addr_EN1 = 7'h52; // R
6'h22: char_addr_EN1 = 7'h69; // i
6'h23: char_addr_EN1 = 7'h63; // c
6'h24: char_addr_EN1 = 7'h61; // a
default: char_addr_EN1 = 7'h00; //
endcase
//-------------------------------------------
// Region de Encabezado2
// - escala 16(x)-a-16(y) de fuente, 640x480=40x15
// - line 2, 36 caracteres: "Escuela de Ingenieria en Electronica"
//-------------------------------------------
assign ENCABEZADO2_on = (pix_y[9:4]==1) && (2<=pix_x[9:4]<=37);//los bits sobrantes son lo que tienen que dar 2^5=32
assign row_addr_EN2 = pix_y[3:0];
assign bit_addr_EN2 = pix_x[3:1];
always @*
case (pix_x[9:4])// 6 bits 2^6=64, tengo que poner un default para los extra
6'h2: char_addr_EN2 = 7'h45; // E
6'h3: char_addr_EN2 = 7'h73; // s
6'h4: char_addr_EN2 = 7'h63; // c
6'h5: char_addr_EN2 = 7'h75; // u
6'h6: char_addr_EN2 = 7'h65; // e
6'h7: char_addr_EN2 = 7'h6c; // l
6'h8: char_addr_EN2 = 7'h61; // a
6'h9: char_addr_EN2 = 7'h00; //
6'ha: char_addr_EN2 = 7'h64; // d
6'hb: char_addr_EN2 = 7'h65; // e
6'hc: char_addr_EN2 = 7'h00; //
6'hd: char_addr_EN2 = 7'h49; // I
6'he: char_addr_EN2 = 7'h6e; // n
6'hf: char_addr_EN2 = 7'h67; // g
6'h10: char_addr_EN2 = 7'h65; // e
6'h11: char_addr_EN2 = 7'h6e; // n
6'h12: char_addr_EN2 = 7'h69; // i
6'h13: char_addr_EN2 = 7'h65; // e
6'h14: char_addr_EN2 = 7'h72; // r
6'h15: char_addr_EN2 = 7'h69; // i
6'h16: char_addr_EN2 = 7'h61; // a
6'h17: char_addr_EN2 = 7'h00; //
6'h18: char_addr_EN2 = 7'h65; // e
6'h19: char_addr_EN2 = 7'h6e; // n
6'h1a: char_addr_EN2 = 7'h00; //
6'h1b: char_addr_EN2 = 7'h45; // E
6'h1c: char_addr_EN2 = 7'h6c; // l
6'h1d: char_addr_EN2 = 7'h65; // e
6'h1e: char_addr_EN2 = 7'h63; // c
6'h1f: char_addr_EN2 = 7'h74; // t
6'h20: char_addr_EN2 = 7'h72; // r
6'h21: char_addr_EN2 = 7'h6f; // o
6'h22: char_addr_EN2 = 7'h6e; // n
6'h23: char_addr_EN2 = 7'h69; // i
6'h24: char_addr_EN2 = 7'h63; // c
6'h25: char_addr_EN2 = 7'h61; // a
default: char_addr_EN2 = 7'h00; //
endcase
//-------------------------------------------
// Region de Encabezado3
// - escala 16(x)-a-16(y) de fuente, 640x480=40x15
// - line 3, 36 caracteres: "Lab. de Diseno de Sistemas Digitales"
//-------------------------------------------
assign ENCABEZADO3_on = (pix_y[9:4]==2) && (2<=pix_x[9:4]<=37);//los bits sobrantes son lo que tienen que dar 2^5=32
assign row_addr_EN3 = pix_y[3:0];
assign bit_addr_EN3 = pix_x[3:1];
always @*
case (pix_x[9:4])// 6 bits 2^6=64, tengo que poner un default para los extra
6'h2: char_addr_EN3 = 7'h4c; // L
6'h3: char_addr_EN3 = 7'h61; // a
6'h4: char_addr_EN3 = 7'h62; // b
6'h5: char_addr_EN3 = 7'h2e; // .
6'h6: char_addr_EN3 = 7'h00; //
6'h7: char_addr_EN3 = 7'h64; // d
6'h8: char_addr_EN3 = 7'h65; // e
6'h9: char_addr_EN3 = 7'h00; //
6'ha: char_addr_EN3 = 7'h44; // D
6'hb: char_addr_EN3 = 7'h69; // i
6'hc: char_addr_EN3 = 7'h73; // s
6'hd: char_addr_EN3 = 7'h65; // e
6'he: char_addr_EN3 = 7'h6e; // n
6'hf: char_addr_EN3 = 7'h6f; // o
6'h10: char_addr_EN3 = 7'h00; //
6'h11: char_addr_EN3 = 7'h64; // d
6'h12: char_addr_EN3 = 7'h65; // e
6'h13: char_addr_EN3 = 7'h00; //
6'h14: char_addr_EN3 = 7'h53; // S
6'h15: char_addr_EN3 = 7'h69; // i
6'h16: char_addr_EN3 = 7'h73; // s
6'h17: char_addr_EN3 = 7'h74; // t
6'h18: char_addr_EN3 = 7'h65; // e
6'h19: char_addr_EN3 = 7'h6d; // m
6'h1a: char_addr_EN3 = 7'h61; // a
6'h1b: char_addr_EN3 = 7'h73; // s
6'h1c: char_addr_EN3 = 7'h00; //
6'h1d: char_addr_EN3 = 7'h44; // D
6'h1e: char_addr_EN3 = 7'h69; // i
6'h1f: char_addr_EN3 = 7'h67; // g
6'h20: char_addr_EN3 = 7'h69; // i
6'h21: char_addr_EN3 = 7'h74; // t
6'h22: char_addr_EN3 = 7'h61; // a
6'h23: char_addr_EN3 = 7'h6c; // l
6'h24: char_addr_EN3 = 7'h65; // e
6'h25: char_addr_EN3 = 7'h73; // s
default: char_addr_EN3 = 7'h00; //
endcase
//-------------------------------------------
// Region de Encabezado4
// - escala 16(x)-a-16(y) de fuente, 640x480=40x15
// - line 15, 8 caracteres: ">Alarma<"
//-------------------------------------------
assign ENCABEZADO4_on = (pix_y[9:4]==14) && (17<=pix_x[9:4]<=24);//los bits sobrantes son lo que tienen que dar 2^5=32
assign row_addr_EN4 = pix_y[3:0];
assign bit_addr_EN4 = pix_x[3:1];
always @*
case (pix_x[8:4])// 5 bits 2^5=32, tengo que poner un default para los extra
5'h11: char_addr_EN4 = 7'h10; // >
5'h12: char_addr_EN4 = 7'h41; // A
5'h13: char_addr_EN4 = 7'h6c; // l
5'h14: char_addr_EN4 = 7'h61; // a
5'h15: char_addr_EN4 = 7'h72; // r
5'h16: char_addr_EN4 = 7'h6d; // m
5'h17: char_addr_EN4 = 7'h61; // a
5'h18: char_addr_EN4 = 7'h11; // <
default: char_addr_EN4 = 7'h00; //
endcase
//-------------------------------------------
// Region de separacion
// - escala 16(x)-a-16(y) de fuente, 640x480=10x3.75~4
// - line 6, 40 caracteres: "----------"
//-------------------------------------------
assign separa_on = (pix_y[9:4]==5) && (0<=pix_x[9:4]<=39);//los bits sobrantes son lo que tienen que dar 2^7=128
assign row_addr_sep = pix_y[3:0];//4b
assign bit_addr_sep = pix_x[3:1];//3b
always @*
case (pix_x[7:4])// 4 bits 2^4=16, y ocupo 10, tengo que poner un default para los extra
4'h0: char_addr_sep = 7'h2d; // -
4'h1: char_addr_sep = 7'h0f; //*
4'h2: char_addr_sep = 7'h2d; // -
4'h3: char_addr_sep = 7'h0f; //*
4'h4: char_addr_sep = 7'h2d; // -
4'h5: char_addr_sep = 7'h0f; //*
4'h6: char_addr_sep = 7'h2d; // -
4'h7: char_addr_sep = 7'h0f; //*
4'h8: char_addr_sep = 7'h2d; // -
4'h9: char_addr_sep = 7'h0f; //*
4'ha: char_addr_sep = 7'h2d; // -
4'hb: char_addr_sep = 7'h0f; //*
4'hc: char_addr_sep = 7'h2d; // -
4'hd: char_addr_sep = 7'h0f; //*
4'he: char_addr_sep = 7'h2d; // -
4'hf: char_addr_sep = 7'h0f; //*
4'h10: char_addr_sep = 7'h2d; // -
4'h11: char_addr_sep = 7'h0f; //*
4'h12: char_addr_sep = 7'h2d; // -
4'h13: char_addr_sep = 7'h0f; //*
4'h14: char_addr_sep = 7'h2d; // -
4'h15: char_addr_sep = 7'h0f; //*
4'h16: char_addr_sep = 7'h2d; // -
4'h17: char_addr_sep = 7'h0f; //*
4'h18: char_addr_sep = 7'h2d; // -
4'h19: char_addr_sep = 7'h0f; //*
4'h1a: char_addr_sep = 7'h2d; // -
4'h1b: char_addr_sep = 7'h0f; //*
4'h1c: char_addr_sep = 7'h2d; // -
4'h1d: char_addr_sep = 7'h0f; //*
4'h1e: char_addr_sep = 7'h2d; // -
4'h1f: char_addr_sep = 7'h0f; //*
4'h20: char_addr_sep = 7'h2d; // -
4'h21: char_addr_sep = 7'h0f; //*
4'h22: char_addr_sep = 7'h2d; // -
4'h23: char_addr_sep = 7'h0f; //*
4'h24: char_addr_sep = 7'h2d; // -
4'h25: char_addr_sep = 7'h0f; //*
4'h26: char_addr_sep = 7'h2d; // -
4'h27: char_addr_sep = 7'h0f; //*
default: char_addr_sep = 7'h0f; //*
endcase
//-------------------------------------------
// Region de Fecha
// - escala 16(x)-a-16(y) de fuente, 640x480=40x7.5~8
// - line 8, 17 chars: ">Fecha:DD/DD/20DD"
//-------------------------------------------
assign FECHA_on = (pix_y[9:4]==7) && (1<=pix_x[9:4]) && (pix_x[9:4]<=17);//los bits sobrantes son lo que tienen que dar 2^4=16
assign row_addr_F = pix_y[3:0];
assign bit_addr_F = pix_x[3:1];
always @*
case (pix_x[8:4])//UTILIZO 5 BITS PARA GENERAR LAS 17 COMBINACIONES
5'h1: char_addr_F = 7'h00; // >
5'h2: char_addr_F = 7'h00; // F
5'h3: char_addr_F = 7'h00; // e
5'h4: char_addr_F = 7'h00; // c
5'h5: char_addr_F = 7'h00; // h
5'h6: char_addr_F = 7'h00; // a
5'h7: char_addr_F = 7'h00; // :
5'h8: char_addr_F = {3'b011, dig_Dec_dia}; // dia
5'h9: char_addr_F = {3'b011,dig_Unit_dia}; // dia
5'ha: char_addr_F = 7'h2f; // /
5'hb: char_addr_F = {3'b011, dig_Dec_mes}; // mes
5'hc: char_addr_F = {3'b011, dig_Unit_mes}; // mes
5'hd: char_addr_F = 7'h2f; // /
5'he: char_addr_F = 7'h32; // 2
5'hf: char_addr_F = 7'h30; // 0
5'h10: char_addr_F = {3'b011, dig_Dec_an}; // año
default char_addr_F = {3'b011, dig_Unit_an}; // año
endcase
//-------------------------------------------
// Region de Cronometro
// - escala 16(x)-a-64(y) de fuente, 640x480=40x7.5~8
// - line 10, 20 chars: ">Cronometro:DD/DD/DD"
//-------------------------------------------
assign CRONOMETRO_on = (pix_y[9:4]==24) && (1<=pix_x[9:4]) && (pix_x[9:4]<=17);//los bits sobrantes son lo que tienen que dar 2^4=16
assign row_addr_C = pix_y[3:0];
assign bit_addr_C = pix_x[3:1];
always @*
case (pix_x[8:4])//UTILIZO 5 BITS PARA GENERAR LAS 20 COMBINACIONES
5'h1: char_addr_C = 7'h00;// >
5'h2: char_addr_C = 7'h00; // C
5'h3: char_addr_C = 7'h00; // r
5'h4: char_addr_C = 7'h00; // o
5'h5: char_addr_C = 7'h00; // n
5'h6: char_addr_C = 7'h00; // o
5'h7: char_addr_C = 7'h00; // m
5'h8: char_addr_C = 7'h00; // e
5'h9: char_addr_C = {3'b011, dig_Dec_Ho_Ti}; //Horas
5'ha: char_addr_C = {3'b011, dig_Unit_Ho_Ti}; // Horas
5'hb: char_addr_C = 7'h3a; // :
5'hc: char_addr_C = {3'b011, dig_Dec_min_Ti}; // minutos
5'hd: char_addr_C = {3'b011, dig_Unit_min_Ti}; // minutos
5'he: char_addr_C = 7'h3a; // :
5'hf: char_addr_C = {3'b011, dig_Dec_seg_Ti}; //segundos
5'h10: char_addr_C = {3'b011, dig_Unit_seg_Ti}; // segundos
default: char_addr_C = 7'h00; // e
endcase
//-------------------------------------------
// Region de Hora
// - escala 16(x)-a-16(y) de fuente, 640x480=40x7.5~8
// - line 12, 14 chars: ">Hora:DD/DD/DD"
//-------------------------------------------
assign HORA_on = (pix_y[9:4]==15) && (1<=pix_x[9:4]) && (pix_x[9:4]<=17);//los bits sobrantes son lo que tienen que dar 2^4=16
assign row_addr_H = pix_y[3:0];
assign bit_addr_H = pix_x[3:1];
always @*
case (pix_x[7:4])//UTILIZO 4 BITS PARA GENERAR LAS 14 COMBINACIONES
4'h1: char_addr_H = 7'h00; // >
4'h2: char_addr_H = 7'h00; // H
4'h3: char_addr_H = 7'h00; // o
4'h4: char_addr_H = 7'h00; // r
4'h5: char_addr_H = 7'h00; // a
4'h6: char_addr_H = 7'h00; // :
4'h7: char_addr_H = 7'h00; // a
4'h8: char_addr_H = 7'h00; // :
4'h9: char_addr_H = {3'b011, dig_Dec_Ho}; // Horas
4'ha: char_addr_H = {3'b011, dig_Unit_Ho}; // Horas
4'hb: char_addr_H = 7'h3a; // :
4'hc: char_addr_H = {3'b011, dig_Dec_min}; // minutos
4'hd: char_addr_H = {3'b011, dig_Unit_min}; // minutos
4'he: char_addr_H = 7'h3a; // :
4'hf: char_addr_H = {3'b011, dig_Dec_seg}; // segundos
4'h10: char_addr_H = {3'b011, dig_Unit_seg}; // segundos
default: char_addr_H = 7'h00; // :
endcase
//-------------------------------------------
// Region de separacion
// - escala 64(x)-a-128(y) de fuente, 640x480=10x3.75~4
// - line 3, 10 caracter:
//
//
// ******
// ********
// ** ** **
// ********
// ********
// ** **
// *** ***
// ********
// ********
// ******
//
//
//
//
//-------------------------------------------
assign TCRONOFIN_on= (pix_y[9:7]==2) && ((2<=pix_x[9:6])&& (pix_x[9:6]<=8));//los bits sobrantes son lo que tienen que dar 2^7=128
assign row_addr_TF = pix_y[6:3];//4b
assign bit_addr_TF = pix_x[5:3];//3b
always @*
case (pix_x[8:6])// 4 bits 2^4=16, y ocupo 10, tengo que poner un default para los extra
3'h2: char_addr_TF = 7'h00; //
3'h3: char_addr_TF = 7'h02; //
3'h4: char_addr_TF = 7'h00; //
3'h5: char_addr_TF = 7'h02; //
3'h6: char_addr_TF = 7'h00; //
3'h7: char_addr_TF = 7'h02; //
3'h8: char_addr_TF = 7'h00; //
default: char_addr_TF = 7'h0f; //*
endcase
//-------------------------------------------
// Direccion de fuente en ROM y rgb
//-------------------------------------------
always @*
begin
text_rgb = 3'b000; // fondo, negro
if (ENCABEZADO1_on)
begin
char_addr = char_addr_EN1;
row_addr = row_addr_EN1;
bit_addr = bit_addr_EN1;
if (font_bit)
text_rgb = 3'b001;
else
text_rgb = 3'b111;
end
else if (ENCABEZADO2_on)
begin
char_addr = char_addr_EN2;
row_addr = row_addr_EN2;
bit_addr = bit_addr_EN2;
if (font_bit)
text_rgb = 3'b001;
else
text_rgb = 3'b111;
end
else if (ENCABEZADO3_on)
begin
char_addr = char_addr_EN3;
row_addr = row_addr_EN3;
bit_addr = bit_addr_EN3;
if (font_bit)
text_rgb = 3'b001;
else
text_rgb = 3'b111;
end
else if (separa_on)
begin
char_addr = char_addr_sep;
row_addr = row_addr_sep;
bit_addr = bit_addr_sep;
if (font_bit)
text_rgb = 3'b010;
else
text_rgb = 3'b111;
end
else if (HORA_on )
begin
char_addr = char_addr_H;
row_addr = row_addr_H;
bit_addr = bit_addr_H;
if (font_bit)
text_rgb = 3'b111;
else
text_rgb = 3'b000;
end
else if (CRONOMETRO_on)
begin
char_addr = char_addr_C;
row_addr = row_addr_C;
bit_addr = bit_addr_C;
if (font_bit)
text_rgb = 3'b111;
else
text_rgb = 3'b000;
end
else if (FECHA_on)
begin
char_addr = char_addr_F;
row_addr = row_addr_F;
bit_addr = bit_addr_F;
if (font_bit)
text_rgb = 3'b111;
else
text_rgb = 3'b000;
end
else if (ENCABEZADO4_on)
begin
char_addr = char_addr_EN4;
row_addr = row_addr_EN4;
bit_addr = bit_addr_EN4;
if (font_bit)
text_rgb = 3'b010;
else
text_rgb = 3'b111;
end
else //TCRONOFIN_on))
begin
char_addr = char_addr_TF;
row_addr = row_addr_TF;
bit_addr = bit_addr_TF;
if ((font_bit)&&(off_alarma))
text_rgb = 3'b010;
else if ((font_bit)&&(on_alarma))
text_rgb = 3'b100;
else
text_rgb = 3'b000;
end
end
assign text_on = {ENCABEZADO1_on, ENCABEZADO2_on, ENCABEZADO3_on, separa_on, HORA_on, CRONOMETRO_on, FECHA_on, ENCABEZADO4_on,TCRONOFIN_on};
//-------------------------------------------
// font rom interface
//-------------------------------------------
assign rom_addr = {char_addr, row_addr};
assign font_bit = font_word[~bit_addr];
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Virtual-Channel (Channel-level) Flow-Control
* ============================================
*
* Supports
* - credit flow-control
* - stop/go style flow-control
*
* Credit Counter Optimization (for credit-based flow-control)
* ===========================
*
* optimized_credit_counter = 0 | 1
*
* Set to '1' to move credit counter logic to start of next clock cycle.
* Remove add/sub from critical path.
*
* To move add/sub logic we buffer the last credit rec. and the any
* flit sent on the output.
*
*/
module NW_vc_fc_out (flit, flit_valid,
channel_cntrl_in,
vc_status, // vc_status[vc]=1 if blocked (fifo is full)
// only when using credit-based flow control
vc_empty, // vc_empty[vc]=1 if VC fifo is empty (credits=init_credits)
vc_credits,
clk, rst_n);
`include "NW_functions.v"
parameter num_vcs = 4;
parameter init_credits = 4;
parameter optimized_credit_counter = 1;
// +1 as has to hold 'init_credits' value
parameter counter_bits = clogb2(init_credits+1);
input flit_t flit;
input flit_valid;
input chan_cntrl_t channel_cntrl_in;
output vc_t vc_status;
output [num_vcs-1:0] vc_empty;
output [num_vcs-1:0][counter_bits-1:0] vc_credits;
input clk, rst_n;
logic [num_vcs-1:0][counter_bits-1:0] counter;
logic [num_vcs-1:0] inc, dec;
// buffer credit and flit vc id.'s so we can move counter in credit counter optimization
logic last_credit_valid, last_flit_valid;
logic [num_vcs-1:0] last_flit_vc_id;
// logic [counter_bits-1:0] last_credit;
vc_index_t last_credit;
logic [num_vcs-1:0][counter_bits-1:0] counter_current;
logic [num_vcs-1:0] vc_empty;
genvar i;
// fsm states
parameter stop=1'b0, go=1'b1;
logic [num_vcs-1:0] current_state, next_state;
// *************************************
// Stop/Go Flow Control
// *************************************
`ifdef NEARLY_FULL_FLOW_CONTROL
generate
for (i=0; i<num_vcs; i++) begin:pervc
always@(posedge clk) begin
if (!rst_n)
current_state[i]<=go;
else
current_state[i]<=next_state[i];
end
always_comb begin
case (current_state[i])
stop:
if (channel_cntrl_in.nearly_full[i])
begin
next_state[i]<=go;
end
else
begin
next_state[i]<=stop;
end
go:
// nearly full and flit sent
if (channel_cntrl_in.nearly_full[i] && flit_valid && (oh2bin(flit.control.vc_id)==i))
begin
next_state[i]<=stop;
end
else
begin
next_state[i]<=go;
end
endcase
end // always_comb begin
assign vc_status[i]=(current_state[i]==stop);
end // block: pervc
endgenerate
`endif
// *************************************
// Credit-based Flow Control
// *************************************
`ifdef CREDIT_FLOW_CONTROL
generate
if (optimized_credit_counter) begin
// ***********************************
// optimized credit-counter (moves counter logic off critical path)
// ***********************************
always@(posedge clk) begin
last_credit_valid <= channel_cntrl_in.credit_valid;
last_credit <= channel_cntrl_in.credit;
last_flit_valid <= flit_valid;
last_flit_vc_id <= flit.control.vc_id;
// $display ("empty=%b", vc_empty);
end
assign vc_credits = counter_current;
for (i=0; i<num_vcs; i++) begin:pervc1
always_comb begin:addsub
if (inc[i] && !dec[i])
counter_current[i]=counter[i]+1;
else if (dec[i] && !inc[i])
counter_current[i]=counter[i]-1;
else
counter_current[i]=counter[i];
end
always@(posedge clk) begin
if (!rst_n) begin
counter[i]<=init_credits;
vc_empty[i]<='1;
end else begin
counter[i]<=counter_current[i];
if ((counter_current[i]==0) ||
((counter_current[i]==1) && flit_valid && (oh2bin(flit.control.vc_id)==i)) &&
!(channel_cntrl_in.credit_valid && (channel_cntrl_in.credit==i))) begin
vc_status[i] <= 1'b1;
vc_empty[i] <= 1'b0;
end else begin
vc_status[i] <= 1'b0;
vc_empty[i] <= (counter_current[i]==init_credits);
end
end // else: !if(!rst_n)
end // always@ (posedge clk)
assign inc[i]=(last_credit_valid) && (last_credit==i);
assign dec[i]=(last_flit_valid) && (oh2bin(last_flit_vc_id)==i);
end
end else begin
assign vc_credits = counter;
// ***********************************
// unoptimized credit-counter
// ***********************************
for (i=0; i<num_vcs; i++) begin:pervc
always@(posedge clk) begin
if (!rst_n) begin
counter[i]<=init_credits;
end else begin
if (inc[i] && !dec[i]) begin
assert (counter[i]!=init_credits) else $fatal;
counter[i]<=counter[i]+1;
end
if (dec[i] && !inc[i]) begin
assert (counter[i]!=0) else $fatal;
counter[i]<=counter[i]-1;
end
end // else: !if(!rst_n)
end
// received credit for VC i?
assign inc[i]=(channel_cntrl_in.credit_valid) && (channel_cntrl_in.credit==i);
// flit sent, one less credit
assign dec[i]=(flit_valid) && (oh2bin(flit.control.vc_id)==i);
// if counter==0, VC is blocked
assign vc_status[i]=(counter[i]==0);
// if counter==init_credits, VC buffer is empty
assign vc_empty[i]=(counter[i]==init_credits);
end // block: pervc
end
endgenerate
`endif
endmodule
|
// system_acl_iface_hps.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.18.10:44:18
`timescale 1 ps / 1 ps
module system_acl_iface_hps #(
parameter F2S_Width = 0,
parameter S2F_Width = 0
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire h2f_lw_axi_clk, // h2f_lw_axi_clock.clk
output wire [11:0] h2f_lw_AWID, // h2f_lw_axi_master.awid
output wire [20:0] h2f_lw_AWADDR, // .awaddr
output wire [3:0] h2f_lw_AWLEN, // .awlen
output wire [2:0] h2f_lw_AWSIZE, // .awsize
output wire [1:0] h2f_lw_AWBURST, // .awburst
output wire [1:0] h2f_lw_AWLOCK, // .awlock
output wire [3:0] h2f_lw_AWCACHE, // .awcache
output wire [2:0] h2f_lw_AWPROT, // .awprot
output wire h2f_lw_AWVALID, // .awvalid
input wire h2f_lw_AWREADY, // .awready
output wire [11:0] h2f_lw_WID, // .wid
output wire [31:0] h2f_lw_WDATA, // .wdata
output wire [3:0] h2f_lw_WSTRB, // .wstrb
output wire h2f_lw_WLAST, // .wlast
output wire h2f_lw_WVALID, // .wvalid
input wire h2f_lw_WREADY, // .wready
input wire [11:0] h2f_lw_BID, // .bid
input wire [1:0] h2f_lw_BRESP, // .bresp
input wire h2f_lw_BVALID, // .bvalid
output wire h2f_lw_BREADY, // .bready
output wire [11:0] h2f_lw_ARID, // .arid
output wire [20:0] h2f_lw_ARADDR, // .araddr
output wire [3:0] h2f_lw_ARLEN, // .arlen
output wire [2:0] h2f_lw_ARSIZE, // .arsize
output wire [1:0] h2f_lw_ARBURST, // .arburst
output wire [1:0] h2f_lw_ARLOCK, // .arlock
output wire [3:0] h2f_lw_ARCACHE, // .arcache
output wire [2:0] h2f_lw_ARPROT, // .arprot
output wire h2f_lw_ARVALID, // .arvalid
input wire h2f_lw_ARREADY, // .arready
input wire [11:0] h2f_lw_RID, // .rid
input wire [31:0] h2f_lw_RDATA, // .rdata
input wire [1:0] h2f_lw_RRESP, // .rresp
input wire h2f_lw_RLAST, // .rlast
input wire h2f_lw_RVALID, // .rvalid
output wire h2f_lw_RREADY, // .rready
input wire [26:0] f2h_sdram0_ADDRESS, // f2h_sdram0_data.address
input wire [7:0] f2h_sdram0_BURSTCOUNT, // .burstcount
output wire f2h_sdram0_WAITREQUEST, // .waitrequest
output wire [255:0] f2h_sdram0_READDATA, // .readdata
output wire f2h_sdram0_READDATAVALID, // .readdatavalid
input wire f2h_sdram0_READ, // .read
input wire [255:0] f2h_sdram0_WRITEDATA, // .writedata
input wire [31:0] f2h_sdram0_BYTEENABLE, // .byteenable
input wire f2h_sdram0_WRITE, // .write
input wire f2h_sdram0_clk, // f2h_sdram0_clock.clk
input wire [31:0] f2h_irq_p0, // f2h_irq0.irq
input wire [31:0] f2h_irq_p1, // f2h_irq1.irq
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO53 // .hps_io_gpio_inst_GPIO53
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
system_acl_iface_hps_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY), // .rready
.f2h_sdram0_ADDRESS (f2h_sdram0_ADDRESS), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (f2h_sdram0_BURSTCOUNT), // .burstcount
.f2h_sdram0_WAITREQUEST (f2h_sdram0_WAITREQUEST), // .waitrequest
.f2h_sdram0_READDATA (f2h_sdram0_READDATA), // .readdata
.f2h_sdram0_READDATAVALID (f2h_sdram0_READDATAVALID), // .readdatavalid
.f2h_sdram0_READ (f2h_sdram0_READ), // .read
.f2h_sdram0_WRITEDATA (f2h_sdram0_WRITEDATA), // .writedata
.f2h_sdram0_BYTEENABLE (f2h_sdram0_BYTEENABLE), // .byteenable
.f2h_sdram0_WRITE (f2h_sdram0_WRITE), // .write
.f2h_sdram0_clk (f2h_sdram0_clk), // f2h_sdram0_clock.clk
.f2h_irq_p0 (f2h_irq_p0), // f2h_irq0.irq
.f2h_irq_p1 (f2h_irq_p1) // f2h_irq1.irq
);
system_acl_iface_hps_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53) // .hps_io_gpio_inst_GPIO53
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of cgu
//
// Generated
// by: wig
// on: Mon Jun 26 16:38:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../nreset2.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: cgu.v,v 1.3 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: cgu.v,v $
// Revision 1.3 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of cgu
//
// No user `defines in this module
module cgu
//
// Generated Module cgu_i1
//
(
nreset, // Auxiliary Signals (PAD)
nreset_out // Auxiliary Signals (PAD)
);
// Generated Module Inputs:
input nreset;
// Generated Module Outputs:
output nreset_out;
// Generated Wires:
wire nreset;
wire nreset_out;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of cgu
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : EP_MEM.v
// Version : 1.11
//--
//-- Description: Endpoint Memory: 8KB organized as 4 x (512 DW) BlockRAM banks.
//-- Block RAM Port A: Read Port
//-- Block RAM Port B: Write Port
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module EP_MEM (
clk,
a_rd_a_i_0, // [8:0] Port A Read Address Bank 0
a_rd_d_o_0, // [31:0] Port A Read Data Bank 0
a_rd_en_i_0, // Port A Read Enable Bank 0
b_wr_a_i_0, // [8:0] Port B Write Address Bank 0
b_wr_d_i_0, // [31:0] Port B Write Data Bank 0
b_wr_en_i_0, // Port B Write Enable Bank 0
b_rd_d_o_0, // [31:0] Port B Read Data Bank 0
b_rd_en_i_0, // Port B Read Enable Bank 0
a_rd_a_i_1, // [8:0] Port A Read Address Bank 1
a_rd_d_o_1, // [31:0] Port A Read Data Bank 1
a_rd_en_i_1,
b_wr_a_i_1, // [8:0] Port B Write Address Bank 1
b_wr_d_i_1, // [31:0] Port B Write Data Bank 1
b_wr_en_i_1, // Port B Write Enable Bank 1
b_rd_d_o_1, // [31:0] Port B Read Data Bank 1
b_rd_en_i_1, // Port B Read Enable Bank 1
a_rd_a_i_2, // [8:0] Port A Read Address Bank 2
a_rd_d_o_2, // [31:0] Port A Read Data Bank 2
a_rd_en_i_2,
b_wr_a_i_2, // [8:0] Port B Write Address Bank 2
b_wr_d_i_2, // [31:0] Port B Write Data Bank 2
b_wr_en_i_2, // Port B Write Enable Bank 2
b_rd_d_o_2, // [31:0] Port B Read Data Bank 2
b_rd_en_i_2, // Port B Read Enable Bank 2
a_rd_a_i_3, // [8:0] Port A Read Address Bank 3
a_rd_d_o_3, // [31:0] Port A Read Data Bank 3
a_rd_en_i_3,
b_wr_a_i_3, // [8:0] Port B Write Address Bank 3
b_wr_d_i_3, // [31:0] Port B Write Data Bank 3
b_wr_en_i_3, // Port B Write Enable Bank 3
b_rd_d_o_3, // [31:0] Port B Read Data Bank 3
b_rd_en_i_3 // Port B Read Enable Bank 3
);
input clk;
input [08:00] a_rd_a_i_0;
output [31:00] a_rd_d_o_0;
input a_rd_en_i_0;
input [08:00] b_wr_a_i_0;
input [31:00] b_wr_d_i_0;
input b_wr_en_i_0;
output [31:00] b_rd_d_o_0;
input b_rd_en_i_0;
input [08:00] a_rd_a_i_1;
output [31:00] a_rd_d_o_1;
input a_rd_en_i_1;
input [08:00] b_wr_a_i_1;
input [31:00] b_wr_d_i_1;
input b_wr_en_i_1;
output [31:00] b_rd_d_o_1;
input b_rd_en_i_1;
input [08:00] a_rd_a_i_2;
output [31:00] a_rd_d_o_2;
input a_rd_en_i_2;
input [08:00] b_wr_a_i_2;
input [31:00] b_wr_d_i_2;
input b_wr_en_i_2;
output [31:00] b_rd_d_o_2;
input b_rd_en_i_2;
input [08:00] a_rd_a_i_3;
output [31:00] a_rd_d_o_3;
input a_rd_en_i_3;
input [08:00] b_wr_a_i_3;
input [31:00] b_wr_d_i_3;
input b_wr_en_i_3;
output [31:00] b_rd_d_o_3;
input b_rd_en_i_3;
//----------------------------------------------------------------
//
// 4 x 512 DWs Buffer Banks (512 x 32 bits + 512 x 4 bits)
// 1 each for IO, Mem32, Mem64 and EROM
//----------------------------------------------------------------
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_io_mem_inst (
.DOA(a_rd_d_o_0[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_0[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_0[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_0[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_0[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_0), // 1-bit A port enable input
.ENB(b_rd_en_i_0), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_0, b_wr_en_i_0, b_wr_en_i_0, b_wr_en_i_0}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem32_inst (
.DOA(a_rd_d_o_1[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_1[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_1[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_1[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_1[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_1), // 1-bit A port enable input
.ENB(b_rd_en_i_1), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_1, b_wr_en_i_1, b_wr_en_i_1, b_wr_en_i_1}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem64_inst (
.DOA(a_rd_d_o_2[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_2[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_2[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_2[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_2[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_2), // 1-bit A port enable input
.ENB(b_rd_en_i_2), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_2, b_wr_en_i_2, b_wr_en_i_2, b_wr_en_i_2}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem_erom_inst (
.DOA(a_rd_d_o_3[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_3[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_3[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_3[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_3[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_3), // 1-bit A port enable input
.ENB(b_rd_en_i_3), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_3, b_wr_en_i_3, b_wr_en_i_3, b_wr_en_i_3}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/07/2015 06:38:17 PM
// Design Name:
// Module Name: m_port_ultra
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module m_port_ultra_processor_array (
input clk,
input reset_n,
input processorEnable,
input [8191:0] convexCloud,
output [4095:0] convexHull1,
output [4095:0] convexHull2,
output [7:0] convexHullSize1,
output [7:0] convexHullSize2
);
// Wires -- processor inputs
wire [4095:0] processorConvexCloud1;
wire [4095:0] processorConvexCloud2;
wire [8:0] processorConvexCloudSize1;
wire [8:0] processorConvexCloudSize2;
// Declare processor unit 1
m_port_ultra_quickhull quickhullProcessor1 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.points (processorConvexCloud1),
.size (processorConvexCloudSize1),
.convexPointsOutput (convexHull1),
.convexSetSizeOutput (convexHullSize1)
);
// Declare processor unit 2
m_port_ultra_quickhull quickhullProcessor2 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.points (processorConvexCloud2),
.size (processorConvexCloudSize2),
.convexPointsOutput (convexHull2),
.convexSetSizeOutput (convexHullSize2)
);
endmodule
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs.
As of Coq 8.4 [admit] is in the standard library, but we include
it here for backwards compatibility.
*)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
mathematics: If a procedure or method has no side effects, then
pretty much all you need to understand about it is how it maps
inputs to outputs -- that is, you can think of its behavior as
just computing a mathematical function. This is one reason for
the word "functional" in "functional programming." This direct
connection between programs and simple mathematical objects
supports both sound informal reasoning and formal proofs of
correctness.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful idioms, as we will see.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code.
To see how this works, let's start with a very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second through eighth lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters.
More information can also be found in the Coq'Art book by Bertot
and Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] will automatically perform
simplification.) *)
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
negb (andb b1 b2).
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
andb (andb b1 b2) b3.
Example test_andb31: (andb3 true true true) = true.
reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| 0 => 1
| S n => mult (S n) (factorial n)
end.
Example test_factorial1: (factorial 3) = 6.
compute. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
compute. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Optional Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition blt_nat (n m : nat) : bool :=
andb (ble_nat n m) (negb (beq_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
compute. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
compute. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
compute. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** Step through these proofs in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros. rewrite -> H. rewrite <- H0. reflexivity. Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros. rewrite -> H. reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros. destruct n.
reflexivity.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros. rewrite -> H. rewrite -> H. reflexivity. Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros. rewrite -> H, -> H, negb_involutive. reflexivity. Qed.
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c.
destruct b, c.
reflexivity.
intros H. inversion H.
intros H. inversion H.
reflexivity.
Qed.
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Write some unit tests for your increment and binary-to-unary
functions. Notice that incrementing a binary number and
then converting it to unary should yield the same result as first
converting it to unary and then incrementing.
*)
Inductive bin : Type :=
| BO : bin
| BS : bin -> bin
| BSS : bin -> bin.
Fixpoint inc_bin (n : bin) : bin :=
match n with
| BO => BS BO
| BS n => BSS n
| BSS n => BS (BSS n)
end.
Fixpoint bin_to_nat (n : bin) : nat :=
match n with
| BO => O
| BS n => S (bin_to_nat n)
| BSS n => S (S (bin_to_nat n))
end.
Theorem bS_nat_s_nat :
forall (n : bin),
bin_to_nat (inc_bin n) = S (bin_to_nat n).
intros. destruct n.
reflexivity.
reflexivity.
reflexivity.
Qed.
(* ###################################################################### *)
(** * Optional Material *)
(** ** More on Notation *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** ** [Fixpoint]s and Structural Recursion *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(* $Date: 2013-12-03 07:45:41 -0500 (Tue, 03 Dec 2013) $ *)
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream asynchronous frame FIFO (64 bit datapath)
*/
module axis_async_frame_fifo_64 #
(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter DROP_WHEN_FULL = 0
)
(
/*
* AXI input
*/
input wire input_clk,
input wire input_rst,
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
input wire output_clk,
input wire output_rst,
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast
);
reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_cur = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync1 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg input_rst_sync1 = 1;
reg input_rst_sync2 = 1;
reg output_rst_sync1 = 1;
reg output_rst_sync2 = 1;
reg drop_frame = 1'b0;
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_out_reg = {1'b0, {KEEP_WIDTH{1'b0}}, {DATA_WIDTH{1'b0}}};
//(* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg output_read = 1'b0;
reg output_axis_tvalid_reg = 1'b0;
wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tkeep, input_axis_tdata};
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
wire full = ((wr_ptr_gray[ADDR_WIDTH] != rd_ptr_gray_sync2[ADDR_WIDTH]) &&
(wr_ptr_gray[ADDR_WIDTH-1] != rd_ptr_gray_sync2[ADDR_WIDTH-1]) &&
(wr_ptr_gray[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2[ADDR_WIDTH-2:0]));
// empty when pointers match exactly
wire empty = rd_ptr_gray == wr_ptr_gray_sync2;
// overflow in single packet
wire full_cur = ((wr_ptr[ADDR_WIDTH] != wr_ptr_cur[ADDR_WIDTH]) &&
(wr_ptr[ADDR_WIDTH-1:0] == wr_ptr_cur[ADDR_WIDTH-1:0]));
wire write = input_axis_tvalid & (~full | DROP_WHEN_FULL);
wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
assign {output_axis_tlast, output_axis_tkeep, output_axis_tdata} = data_out_reg;
assign input_axis_tready = (~full | DROP_WHEN_FULL);
assign output_axis_tvalid = output_axis_tvalid_reg;
// reset synchronization
always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
if (input_rst | output_rst) begin
input_rst_sync1 <= 1;
input_rst_sync2 <= 1;
end else begin
input_rst_sync1 <= 0;
input_rst_sync2 <= input_rst_sync1;
end
end
always @(posedge output_clk or posedge input_rst or posedge output_rst) begin
if (input_rst | output_rst) begin
output_rst_sync1 <= 1;
output_rst_sync2 <= 1;
end else begin
output_rst_sync1 <= 0;
output_rst_sync2 <= output_rst_sync1;
end
end
// write
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
wr_ptr <= 0;
wr_ptr_cur <= 0;
wr_ptr_gray <= 0;
drop_frame <= 0;
end else if (write) begin
if (full | full_cur | drop_frame) begin
// buffer full, hold current pointer, drop packet at end
drop_frame <= 1;
if (input_axis_tlast) begin
wr_ptr_cur <= wr_ptr;
drop_frame <= 0;
end
end else begin
mem[wr_ptr_cur[ADDR_WIDTH-1:0]] <= data_in;
wr_ptr_cur <= wr_ptr_cur + 1;
if (input_axis_tlast) begin
if (input_axis_tuser) begin
// bad packet, reset write pointer
wr_ptr_cur <= wr_ptr;
end else begin
// good packet, push new write pointer
wr_ptr_next = wr_ptr_cur + 1;
wr_ptr <= wr_ptr_next;
wr_ptr_gray <= wr_ptr_next ^ (wr_ptr_next >> 1);
end
end
end
end
end
// pointer synchronization
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
rd_ptr_gray_sync1 <= 0;
rd_ptr_gray_sync2 <= 0;
end else begin
rd_ptr_gray_sync1 <= rd_ptr_gray;
rd_ptr_gray_sync2 <= rd_ptr_gray_sync1;
end
end
// read
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
rd_ptr <= 0;
rd_ptr_gray <= 0;
end else if (read) begin
data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
rd_ptr_next = rd_ptr + 1;
rd_ptr <= rd_ptr_next;
rd_ptr_gray <= rd_ptr_next ^ (rd_ptr_next >> 1);
end
end
// pointer synchronization
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
wr_ptr_gray_sync1 <= 0;
wr_ptr_gray_sync2 <= 0;
end else begin
wr_ptr_gray_sync1 <= wr_ptr_gray;
wr_ptr_gray_sync2 <= wr_ptr_gray_sync1;
end
end
// source ready output
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
output_axis_tvalid_reg <= 1'b0;
end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
output_axis_tvalid_reg <= ~empty;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_reg;
end
end
endmodule
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* PTP tag insert module
*/
module ptp_tag_insert #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = DATA_WIDTH/8,
parameter TAG_WIDTH = 16,
parameter TAG_OFFSET = 1,
parameter USER_WIDTH = TAG_WIDTH+TAG_OFFSET
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Tag input
*/
input wire [TAG_WIDTH-1:0] s_axis_tag,
input wire s_axis_tag_valid,
output wire s_axis_tag_ready
);
reg [TAG_WIDTH-1:0] tag_reg = {TAG_WIDTH{1'b0}};
reg tag_valid_reg = 1'b0;
reg [USER_WIDTH-1:0] user;
assign s_axis_tready = m_axis_tready && tag_valid_reg;
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = s_axis_tkeep;
assign m_axis_tvalid = s_axis_tvalid && tag_valid_reg;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tuser = user;
assign s_axis_tag_ready = !tag_valid_reg;
always @* begin
user = s_axis_tuser;
user[TAG_OFFSET +: TAG_WIDTH] = tag_reg;
end
always @(posedge clk) begin
if (tag_valid_reg) begin
if (s_axis_tvalid && s_axis_tready && s_axis_tlast) begin
tag_valid_reg <= 1'b0;
end
end else begin
tag_reg <= s_axis_tag;
tag_valid_reg <= s_axis_tag_valid;
end
if (rst) begin
tag_valid_reg <= 1'b0;
end
end
endmodule
`resetall
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : jtag_lm32.v
// Title : JTAG data register for LM32 CPU debug interface
// Version : 6.0.13
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module jtag_lm32 (
input JTCK,
input JTDI,
output JTDO2,
input JSHIFT,
input JUPDATE,
input JRSTN,
input JCE2,
input JTAGREG_ENABLE,
input CONTROL_DATAN,
output REG_UPDATE,
input [7:0] REG_D,
input [2:0] REG_ADDR_D,
output [7:0] REG_Q,
output [2:0] REG_ADDR_Q
);
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire [9:0] tdibus;
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
TYPEA DATA_BIT0 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(JTDI),
.TDO(tdibus[0]),
.DATA_OUT(REG_Q[0]),
.DATA_IN(REG_D[0]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT1 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[0]),
.TDO(tdibus[1]),
.DATA_OUT(REG_Q[1]),
.DATA_IN(REG_D[1]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT2 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[1]),
.TDO(tdibus[2]),
.DATA_OUT(REG_Q[2]),
.DATA_IN(REG_D[2]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT3 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[2]),
.TDO(tdibus[3]),
.DATA_OUT(REG_Q[3]),
.DATA_IN(REG_D[3]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT4 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[3]),
.TDO(tdibus[4]),
.DATA_OUT(REG_Q[4]),
.DATA_IN(REG_D[4]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT5 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[4]),
.TDO(tdibus[5]),
.DATA_OUT(REG_Q[5]),
.DATA_IN(REG_D[5]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT6 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[5]),
.TDO(tdibus[6]),
.DATA_OUT(REG_Q[6]),
.DATA_IN(REG_D[6]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT7 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[6]),
.TDO(tdibus[7]),
.DATA_OUT(REG_Q[7]),
.DATA_IN(REG_D[7]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA ADDR_BIT0 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[7]),
.TDO(tdibus[8]),
.DATA_OUT(REG_ADDR_Q[0]),
.DATA_IN(REG_ADDR_D[0]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA ADDR_BIT1 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[8]),
.TDO(tdibus[9]),
.DATA_OUT(REG_ADDR_Q[1]),
.DATA_IN(REG_ADDR_D[1]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA ADDR_BIT2 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[9]),
.TDO(JTDO2),
.DATA_OUT(REG_ADDR_Q[2]),
.DATA_IN(REG_ADDR_D[2]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
assign clk_enable = JTAGREG_ENABLE & JCE2;
assign captureDr = !JSHIFT & JCE2;
// JCE2 is only active during shift
assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/18/2016 01:33:37 PM
// Design Name:
// Module Name: scaler
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module axis_bayer_extractor #
(
parameter integer C_PIXEL_WIDTH = 8,
parameter integer C_BYPASS = 0,
parameter integer C_COL_ODD = 0,
parameter integer C_ROW_ODD = 0
) (
input wire clk,
input wire resetn,
input wire s_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tuser,
input wire s_axis_tlast,
output wire s_axis_tready,
output wire m_axis_tvalid,
output wire [C_PIXEL_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tuser,
output wire m_axis_tlast,
input wire m_axis_tready
);
generate
if (C_BYPASS == 1) begin: direct_connect
assign m_axis_tvalid = s_axis_tvalid;
assign m_axis_tdata[C_PIXEL_WIDTH-1:0] = s_axis_tdata[C_PIXEL_WIDTH-1:0];
assign m_axis_tuser = s_axis_tuser;
assign m_axis_tlast = s_axis_tlast;
assign s_axis_tready = m_axis_tready;
end
else begin: extract_quater
reg r_m_axis_tvalid;
assign m_axis_tvalid = r_m_axis_tvalid;
reg [C_PIXEL_WIDTH-1:0] r_m_axis_tdata;
assign m_axis_tdata[C_PIXEL_WIDTH-1:0] = r_m_axis_tdata;
reg r_m_axis_tuser;
assign m_axis_tuser = r_m_axis_tuser;
reg r_m_axis_tlast;
assign m_axis_tlast = r_m_axis_tlast;
wire snext;
assign snext = s_axis_tvalid && s_axis_tready;
wire mnext;
assign mnext = m_axis_tvalid && m_axis_tready;
reg sline_lsb;
reg spixel_lsb;
always @ (posedge clk) begin
if (resetn == 1'b0)
sline_lsb <= 0;
else if (snext && s_axis_tlast)
sline_lsb <= ~sline_lsb;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
spixel_lsb <= 0;
else if (snext)
spixel_lsb <= ~spixel_lsb;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
r_m_axis_tdata <= 0;
else if (snext
&& (spixel_lsb == C_COL_ODD)
&& (sline_lsb == C_ROW_ODD))
r_m_axis_tdata <= s_axis_tdata;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
r_m_axis_tvalid <= 0;
else if (snext
&& (spixel_lsb == 1)
&& (sline_lsb == C_ROW_ODD))
r_m_axis_tvalid <= 1;
else if (m_axis_tready)
r_m_axis_tvalid <= 0;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
r_m_axis_tlast <= 0;
else if (snext
&& (spixel_lsb == 1)
&& (sline_lsb == C_ROW_ODD))
r_m_axis_tlast <= s_axis_tlast;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
r_m_axis_tuser <= 0;
else if (snext
&& s_axis_tuser)
r_m_axis_tuser <= 1;
else if (mnext)
r_m_axis_tuser <= 0;
end
assign s_axis_tready = (~m_axis_tvalid || m_axis_tready);
end
endgenerate
endmodule
|
// File for.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// no timescale needed
module forp(
reset,
sysclk
);
input reset, sysclk;
wire reset;
wire sysclk;
reg selection;
reg [6:0] egg_timer;
always @(posedge reset or posedge sysclk) begin : P1
reg [31:0] timer_var = 0;
reg [31:0] a, i, j, k;
reg [31:0] zz5;
reg [511:0] zz;
if(reset == 1'b 1) begin
selection <= 1'b 1;
timer_var = 2;
egg_timer <= {7{1'b0}};
end else begin
// pulse only lasts for once cycle
selection <= 1'b 0;
egg_timer <= {7{1'b1}};
for (i=0; i <= j * k; i = i + 1) begin
a = a + i;
for (k=a - 9; k >= -14; k = k - 1) begin
zz5 = zz[31 + k:k];
end
// k
end
// i
end
end
endmodule
|
// 32-bit ALU
// Function codes are defined on page 243
module alu( input [31:0] A, B,
input [2:0] F,
output reg [31:0] Y, output Zero);
always @ ( * )
case (F[2:0])
3'b000: Y <= A & B;
3'b001: Y <= A | B;
3'b010: Y <= A + B;
//3'b011: Y <= 0; // not used
3'b011: Y <= A & ~B;
3'b101: Y <= A + ~B;
3'b110: Y <= A - B;
3'b111: Y <= A < B ? 1:0;
default: Y <= 0; //default to 0, should not happen
endcase
assign Zero = (Y == 32'b0);
endmodule
// Example 7.6 Register file
module regfile(input clk,
input we3,
input [4:0] ra1, ra2, wa3,
input [31:0] wd3,
output [31:0] rd1, rd2);
reg [31:0] rf[31:0];
// three ported register file
// read two ports combinationally
// write third port on rising edge of clock
// register 0 hardwired to 0
always @(posedge clk)
if (we3) rf[wa3] <= wd3;
assign rd1 = (ra1 != 0) ? rf[ra1] : 0;
assign rd2 = (ra2 != 0) ? rf[ra2] : 0;
endmodule
// Example 7.8 Left Shift (Multiply by 4)
module sl2(input [31:0] a,
output [31:0] y);
// shift left by 2
assign y = {a[29:0], 2'b00};
endmodule
// Example 7.9 Sign Extension
module signext(input [15:0] a,
output [31:0] y);
assign y = {{16{a[15]}}, a};
endmodule
// Example 7.10 Resettable Flip-flop with width parameter
module flopr #(parameter WIDTH = 8)
(input clk, reset,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
always @(posedge clk, posedge reset)
if (reset) q <= 0;
else q <= d;
endmodule
// Example 4.20 RESETTABLE ENABLED REGISTER with width parameter
module flopenr #(parameter WIDTH = 8)
(input clk, reset,
input en,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
always @(posedge clk, posedge reset)
if (reset) q <= 0;
else if (en) q <= d;
endmodule
// Example 4.5 2:1 MULTIPLEXER with width parameter
module mux2 #(parameter WIDTH = 8)
(input [WIDTH-1:0] d0, d1,
input s,
output [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule
// 3:1 MULTIPLEXER with width parameter
module mux3 #(parameter WIDTH = 8)
(input [WIDTH-1:0] d0, d1, d2,
input [1:0] s,
output [WIDTH-1:0] y);
assign #1 y = s[1] ? d2 : (s[0] ? d1 : d0);
endmodule
// Example 4.6 4:1 MULTIPLEXER with width parameter
module mux4 #(parameter WIDTH = 8)
(input [WIDTH-1:0] d0, d1, d2, d3,
input [1:0] s,
output reg [WIDTH-1:0] y);
always @( * )
case(s)
2'b00: y <= d0;
2'b01: y <= d1;
2'b10: y <= d2;
2'b11: y <= d3;
endcase
endmodule
|
/*
File: parallella.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module parallella (/*AUTOARG*/
// Outputs
csysack, cactive, reset_chip, reset_fpga, txo_data_p, txo_data_n,
txo_frame_p, txo_frame_n, txo_lclk_p, txo_lclk_n, rxo_wr_wait_p,
rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n, rxi_cclk_p,
rxi_cclk_n, emaxi_awid, emaxi_awaddr, emaxi_awlen, emaxi_awsize,
emaxi_awburst, emaxi_awlock, emaxi_awcache, emaxi_awprot,
emaxi_awvalid, esaxi_awready, emaxi_wid, emaxi_wdata, emaxi_wstrb,
emaxi_wlast, emaxi_wvalid, esaxi_wready, emaxi_bready, esaxi_bid,
esaxi_bresp, esaxi_bvalid, emaxi_arid, emaxi_araddr, emaxi_arlen,
emaxi_arsize, emaxi_arburst, emaxi_arlock, emaxi_arcache,
emaxi_arprot, emaxi_arvalid, esaxi_arready, emaxi_rready,
esaxi_rid, esaxi_rdata, esaxi_rresp, esaxi_rlast, esaxi_rvalid,
emaxi_awqos, emaxi_arqos,
// Inputs
clkin_100, esaxi_aclk, emaxi_aclk, reset, esaxi_aresetn,
emaxi_aresetn, csysreq, rxi_data_p, rxi_data_n, rxi_frame_p,
rxi_frame_n, rxi_lclk_p, rxi_lclk_n, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, emaxi_awready, esaxi_awid,
esaxi_awaddr, esaxi_awlen, esaxi_awsize, esaxi_awburst,
esaxi_awlock, esaxi_awcache, esaxi_awprot, esaxi_awvalid,
emaxi_wready, esaxi_wid, esaxi_wdata, esaxi_wstrb, esaxi_wlast,
esaxi_wvalid, emaxi_bid, emaxi_bresp, emaxi_bvalid, esaxi_bready,
emaxi_arready, esaxi_arid, esaxi_araddr, esaxi_arlen, esaxi_arsize,
esaxi_arburst, esaxi_arlock, esaxi_arcache, esaxi_arprot,
esaxi_arvalid, emaxi_rid, emaxi_rdata, emaxi_rresp, emaxi_rlast,
emaxi_rvalid, esaxi_rready, esaxi_awqos, esaxi_arqos
);
parameter SIDW = 12; //ID Width
parameter SAW = 32; //Address Bus Width
parameter SDW = 32; //Data Bus Width
parameter MIDW = 6; //ID Width
parameter MAW = 32; //Address Bus Width
parameter MDW = 64; //Data Bus Width
parameter STW = 8; //Number of strobes
parameter LW = 8;
parameter AW = 32; //Address Bus Width
parameter DW = 32; //Data Bus Width
//#########
//# Inputs
//#########
// global signals
input clkin_100; // 100MHz input clock
input esaxi_aclk; // clock source of the axi bus for slave port
input emaxi_aclk; // clock source of the axi bus for master port
input reset; // system reset
input esaxi_aresetn; // reset of axi bus for slave port
input emaxi_aresetn; // reset of axi bus for master port
input csysreq; // system exit low-power state request
// LVDS FMC Port
input [7:0] rxi_data_p;
input [7:0] rxi_data_n;
input rxi_frame_p;
input rxi_frame_n;
input rxi_lclk_p;
input rxi_lclk_n;
input txi_wr_wait_p;
input txi_wr_wait_n;
input txi_rd_wait_p;
input txi_rd_wait_n;
//########################
//# Write address channel
//########################
// Master Port
input emaxi_awready; //write address ready
input emaxi_wready;//write ready
// Master Port
input [MIDW-1:0] emaxi_rid; //read ID tag
input [MDW-1:0] emaxi_rdata; //read data
input [1:0] emaxi_rresp; //read response
input emaxi_rlast; //read last, indicates last transfer in burst
input emaxi_rvalid;//read valid
// Slave Port
input [SIDW-1:0] e // Master Port
input [MIDW-1:0] emaxi_rid; //read ID tag
input [MDW-1:0] emaxi_rdata; //read data
input [1:0] emaxi_rresp; //read response
input emaxi_rlast; //read last, indicates last transfer in burst
input emaxi_rvalid;//read valid // Master Port
input [MIDW-1:0] emaxi_rid; //read ID tag
input [MDW-1:0] emaxi_rdata; //read data
input [1:0] emaxi_rresp; //read response
input emaxi_rlast; //read last, indicates last transfer in burst
input emaxi_rvalid;//read valid // Master Port
input [MIDW-1:0] emaxi_rid; //read ID tag
input [MDW-1:0] emaxi_rdata; //read data
input [1:0] emaxi_rresp; //read response
input emaxi_rlast; //read last, indicates last transfer in burst
input emaxi_rvalid;//read validsaxi_awid; //write address ID
input [MAW-1:0] esaxi_awaddr; //write address
input [3:0] esaxi_awlen; //burst lenght (the number of data transfers)
input [2:0] esaxi_awsize; //burst size (the size of each transfer)
input [1:0] esaxi_awburst; //burst type
input [1:0] esaxi_awlock; //lock type (atomic characteristics)
input [3:0] esaxi_awcache; //memory type
input [2:0] esaxi_awprot; //protection type
input esaxi_awvalid; //write address valid
//########################,
//# Write data channel
//########################
// Master Port
// Slave Port
input [SIDW-1:0] esaxi_wid; //write ID tag (supported only in AXI3)
input [SDW-1:0] esaxi_wdata; //write data
input [3:0] esaxi_wstrb; //write strobes
input esaxi_wlast; //write last. Indicates last transfer in burst
input esaxi_wvalid;//write valid
//########################
// Write response channel
//########################
// Master Port
input [MIDW-1:0] emaxi_bid; //response ID tag
input [1:0] emaxi_bresp; //write response
input emaxi_bvalid;//write response valid
// Slave Port
input esaxi_bready;//response ready
//########################
//# Read address channel
//########################
// Master Port
input emaxi_arready;//read address ready
// Slave Port
input [SIDW-1:0] esaxi_arid; //read address ID
input [MAW-1:0] esaxi_araddr; //read address
input [3:0] esaxi_arlen; //burst lenght (the number of data transfers)
input [2:0] esaxi_arsize; //burst size (the size of each transfer)
input [1:0] esaxi_arburst; //burst type
input [1:0] esaxi_arlock; //lock type (atomic characteristics)
input [3:0] esaxi_arcache; //memory type
input [2:0] esaxi_arprot; //protection type
input esaxi_arvalid; //write address valid
// Master Port // Master Port
input [MIDW-1:0] emaxi_rid; //read ID tag
input [MDW-1:0] emaxi_rdata; //read data
input [1:0] emaxi_rresp; //read response
input emaxi_rlast; //read last, indicates last transfer in burst
input emaxi_rvalid;//read valid
input [MIDW-1:0] emaxi_rid; //read ID tag
input [MDW-1:0] emaxi_rdata; //read data
input [1:0] emaxi_rresp; //read response
input emaxi_rlast; //read last, indicates last transfer in burst
input emaxi_rvalid;//read valid
//########################
//# Read data channel
//########################
// Slave Port
input esaxi_rready; //read ready
//##########
//# Outputs
//##########
// global signals
output csysack;//exit low-power state acknowledgement
output cactive;//clock active
output reset_chip;
output reset_fpga;
// LVDS FMC Port
output [7:0] txo_data_p;
output [7:0] txo_data_n;
output txo_frame_p;
output txo_frame_n;
output txo_lclk_p;
output txo_lclk_n;
output rxo_wr_wait_p;
output rxo_wr_wait_n;
output rxo_rd_wait_p;
output rxo_rd_wait_n;
output rxi_cclk_p;
output rxi_cclk_n;
//########################
//# Write address channel
//########################
// Master Port
output [MIDW-1:0] emaxi_awid; //write address ID
output [MAW-1:0] emaxi_awaddr; //write address
output [3:0] emaxi_awlen; //burst length (number of data transfers)
output [2:0] emaxi_awsize; //burst size (the size of each transfer)
output [1:0] emaxi_awburst; //burst type
output [1:0] emaxi_awlock; //lock type (atomic characteristics)
output [3:0] emaxi_awcache; //memory type
output [2:0] emaxi_awprot; //protection type
output emaxi_awvalid; //write address valid
// Slave Port
output esaxi_awready; //write address ready
//########################
//# Write data channel
//########################
// Master Port
output [MIDW-1:0] emaxi_wid; //write ID tag (supported only in AXI3)
output [MDW-1:0] emaxi_wdata; //write data
output [STW-1:0] emaxi_wstrb; //write strobes
output emaxi_wlast; //write last, indicates last transfer in burst
output emaxi_wvalid;//write valid
// Slave Port
output esaxi_wready;//write ready
//########################
// Write response channel
//########################
// Master Port
output emaxi_bready;//response ready
// Slave Port
output [SIDW-1:0] esaxi_bid; //response ID tag
output [1:0] esaxi_bresp; //write response
output esaxi_bvalid;//write response valid
//########################
//# Read address channel
//########################
// Master Port
output [MIDW-1:0] emaxi_arid; //read address ID
output [MAW-1:0] emaxi_araddr; //read address
output [3:0] emaxi_arlen; //burst lenght (number of data transfers)
output [2:0] emaxi_arsize; //burst size (the size of each transfer)
output [1:0] emaxi_arburst; //burst type
output [1:0] emaxi_arlock; //lock type (atomic characteristics)
output [3:0] emaxi_arcache; //memory type
output [2:0] emaxi_arprot; //protection type
output emaxi_arvalid; //write address valid
// Slave Port
output esaxi_arready; //read address ready
//########################
//# Read data channel
//########################
// Master Port
output emaxi_rready; //read ready
// Slave Port
output [SIDW-1:0] esaxi_rid; //read ID tag (must match arid of transaction)
output [SDW-1:0] esaxi_rdata; //read data
output [1:0] esaxi_rresp; //read response
output esaxi_rlast; //read last, indicates last transfer in burst
output esaxi_rvalid;//read valid
//#######################################################################
//# The following features are not supported (AXI4 only)
//# If un-commented, those signals have to be driven with default values
//#######################################################################
// input emaxi_buser; //user signal
// input emaxi_ruser; //user signal
output [3:0] emaxi_awqos; //quality of service default 4'b0000
// output [3:0] emaxi_awregion;//region identifier
// output emaxi_awuser; //user signal
// output emaxi_wuser; //user signal
output [3:0] emaxi_arqos; //quality of service default 4'b0000
// output [3:0] emaxi_arregion;//region identifier
// output emaxi_aruser; //user signal
input [3:0] esaxi_awqos; //Quality of Service default 4'b0000
// input [3:0] awregion; //region identifier
// input awuser; //user signal
// input wuser; //user signal
input [3:0] esaxi_arqos; //quality of service default 4'b0000
// input [3:0] arregion; //region identifier (AXI4 only)
// input aruser; //user signal (AXI4 only)
// output buser; //user signal (AXI4 only)
// output ruser; //user signal (AXI4 only)
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire elink_access_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire elink_access_outb; // From axi_elink_if of axi_elink_if.v
wire elink_cclk_enb; // From axi_elink_if of axi_elink_if.v
wire [1:0] elink_clk_div; // From axi_elink_if of axi_elink_if.v
wire [3:0] elink_ctrlmode_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire [3:0] elink_ctrlmode_outb; // From axi_elink_if of axi_elink_if.v
wire [31:0] elink_data_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire [31:0] elink_data_outb; // From axi_elink_if of axi_elink_if.v
wire [1:0] elink_datamode_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire [1:0] elink_datamode_outb; // From axi_elink_if of axi_elink_if.v
wire elink_disable; // From axi_elink_if of axi_elink_if.v
wire [31:0] elink_dstaddr_outb; // From axi_elink_if of axi_elink_if.v
wire elink_rd_wait_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire elink_rd_wait_outb; // From axi_elink_if of axi_elink_if.v
wire [31:0] elink_srcaddr_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire [31:0] elink_srcaddr_outb; // From axi_elink_if of axi_elink_if.v
wire elink_wr_wait_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire elink_wr_wait_outb; // From axi_elink_if of axi_elink_if.v
wire elink_write_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire elink_write_outb; // From axi_elink_if of axi_elink_if.v
wire emaxi_access_inb; // From axi_master of axi_master.v
wire emaxi_access_outb; // From axi_elink_if of axi_elink_if.v
wire [3:0] emaxi_ctrlmode_inb; // From axi_master of axi_master.v
wire [3:0] emaxi_ctrlmode_outb; // From axi_elink_if of axi_elink_if.v
wire [31:0] emaxi_data_inb; // From axi_master of axi_master.v
wire [31:0] emaxi_data_outb; // From axi_elink_if of axi_elink_if.v
wire [1:0] emaxi_datamode_inb; // From axi_master of axi_master.v
wire [1:0] emaxi_datamode_outb; // From axi_elink_if of axi_elink_if.v
wire [31:0] emaxi_dstaddr_inb; // From axi_master of axi_master.v
wire [31:0] emaxi_dstaddr_outb; // From axi_elink_if of axi_elink_if.v
wire emaxi_rd_wait_inb; // From axi_master of axi_master.v
wire [31:0] emaxi_srcaddr_inb; // From axi_master of axi_master.v
wire [31:0] emaxi_srcaddr_outb; // From axi_elink_if of axi_elink_if.v
wire emaxi_wr_wait_inb; // From axi_master of axi_master.v
wire emaxi_wr_wait_outb; // From axi_elink_if of axi_elink_if.v
wire emaxi_write_inb; // From axi_master of axi_master.v
wire emaxi_write_outb; // From axi_elink_if of axi_elink_if.v
wire esaxi_access_inb; // From axi_slave of axi_slave.v
wire esaxi_access_outb; // From axi_elink_if of axi_elink_if.v
wire [3:0] esaxi_ctrlmode_inb; // From axi_slave of axi_slave.v
wire [3:0] esaxi_ctrlmode_outb; // From axi_elink_if of axi_elink_if.v
wire [31:0] esaxi_data_inb; // From axi_slave of axi_slave.v
wire [31:0] esaxi_data_outb; // From axi_elink_if of axi_elink_if.v
wire [1:0] esaxi_datamode_inb; // From axi_slave of axi_slave.v
wire [1:0] esaxi_datamode_outb; // From axi_elink_if of axi_elink_if.v
wire [31:0] esaxi_dstaddr_inb; // From axi_slave of axi_slave.v
wire [31:0] esaxi_dstaddr_outb; // From axi_elink_if of axi_elink_if.v
wire esaxi_rd_wait_inb; // From axi_slave of axi_slave.v
wire esaxi_rd_wait_outb; // From axi_elink_if of axi_elink_if.v
wire [31:0] esaxi_srcaddr_inb; // From axi_slave of axi_slave.v
wire [31:0] esaxi_srcaddr_outb; // From axi_elink_if of axi_elink_if.v
wire esaxi_wr_wait_inb; // From axi_slave of axi_slave.v
wire esaxi_wr_wait_outb; // From axi_elink_if of axi_elink_if.v
wire esaxi_write_inb; // From axi_slave of axi_slave.v
wire esaxi_write_outb; // From axi_elink_if of axi_elink_if.v
// End of automatics
//#########
//# Regs
//#########
//#########
//# Wires
//#########
wire emaxi_reset;
wire esaxi_reset;
wire rxi_eclk;
wire [31:0] elink_dstaddr_inb;
wire [31:0] elink_dstaddr_tmp;
wire ext_mem_access;
//#################
//# global signals
//#################
assign emaxi_reset = ~emaxi_aresetn;
assign esaxi_reset = ~esaxi_aresetn;
//##################################
//# AXI Slave Port Instantiation
//##################################
/*axi_slave AUTO_TEMPLATE(.eclk (rxi_eclk),
.reset (esaxi_reset),
.aclk (esaxi_aclk),
.aw\(.*\) (esaxi_aw\1[]),
.w\(.*\) (esaxi_w\1[]),
.b\(.*\) (esaxi_b\1[]),
.ar\(.*\) (esaxi_ar\1[]),
.r\(.*\) (esaxi_r\1[]),
.emesh_\(.*\) (esaxi_\1[]),
);
*/
axi_slave axi_slave(/*AUTOINST*/
// Outputs
.csysack (csysack),
.cactive (cactive),
.awready (esaxi_awready), // Templated
.wready (esaxi_wready), // Templated
.bid (esaxi_bid[SIDW-1:0]), // Templated
.bresp (esaxi_bresp[1:0]), // Templated
.bvalid (esaxi_bvalid), // Templated
.arready (esaxi_arready), // Templated
.rid (esaxi_rid[SIDW-1:0]), // Templated
.rdata (esaxi_rdata[SDW-1:0]), // Templated
.rresp (esaxi_rresp[1:0]), // Templated
.rlast (esaxi_rlast), // Templated
.rvalid (esaxi_rvalid), // Templated
.emesh_access_inb(esaxi_access_inb), // Templated
.emesh_write_inb (esaxi_write_inb), // Templated
.emesh_datamode_inb(esaxi_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb(esaxi_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb(esaxi_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb(esaxi_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (esaxi_data_inb[31:0]), // Templated
.emesh_wr_wait_inb(esaxi_wr_wait_inb), // Templated
.emesh_rd_wait_inb(esaxi_rd_wait_inb), // Templated
// Inputs
.aclk (esaxi_aclk), // Templated
.eclk (rxi_eclk), // Templated
.reset (esaxi_reset), // Templated
.csysreq (csysreq),
.awid (esaxi_awid[SIDW-1:0]), // Templated
.awaddr (esaxi_awaddr[SAW-1:0]), // Templated
.awlen (esaxi_awlen[3:0]), // Templated
.awsize (esaxi_awsize[2:0]), // Templated
.awburst (esaxi_awburst[1:0]), // Templated
.awlock (esaxi_awlock[1:0]), // Templated
.awcache (esaxi_awcache[3:0]), // Templated
.awprot (esaxi_awprot[2:0]), // Templated
.awvalid (esaxi_awvalid), // Templated
.wid (esaxi_wid[SIDW-1:0]), // Templated
.wdata (esaxi_wdata[SDW-1:0]), // Templated
.wstrb (esaxi_wstrb[3:0]), // Templated
.wlast (esaxi_wlast), // Templated
.wvalid (esaxi_wvalid), // Templated
.bready (esaxi_bready), // Templated
.arid (esaxi_arid[SIDW-1:0]), // Templated
.araddr (esaxi_araddr[SAW-1:0]), // Templated
.arlen (esaxi_arlen[3:0]), // Templated
.arsize (esaxi_arsize[2:0]), // Templated
.arburst (esaxi_arburst[1:0]), // Templated
.arlock (esaxi_arlock[1:0]), // Templated
.arcache (esaxi_arcache[3:0]), // Templated
.arprot (esaxi_arprot[2:0]), // Templated
.arvalid (esaxi_arvalid), // Templated
.rready (esaxi_rready), // Templated
.emesh_access_outb(esaxi_access_outb), // Templated
.emesh_write_outb(esaxi_write_outb), // Templated
.emesh_datamode_outb(esaxi_datamode_outb[1:0]), // Templated
.emesh_ctrlmode_outb(esaxi_ctrlmode_outb[3:0]), // Templated
.emesh_dstaddr_outb(esaxi_dstaddr_outb[31:0]), // Templated
.emesh_srcaddr_outb(esaxi_srcaddr_outb[31:0]), // Templated
.emesh_data_outb (esaxi_data_outb[31:0]), // Templated
.emesh_wr_wait_outb(esaxi_wr_wait_outb), // Templated
.emesh_rd_wait_outb(esaxi_rd_wait_outb), // Templated
.awqos (esaxi_awqos[3:0]), // Templated
.arqos (esaxi_arqos[3:0])); // Templated
//##################################
//# AXI Master Port Instantiation
//##################################
/*axi_master AUTO_TEMPLATE(.eclk (rxi_eclk),
.reset (emaxi_reset),
.aclk (emaxi_aclk),
.aw\(.*\) (emaxi_aw\1[]),
.w\(.*\) (emaxi_w\1[]),
.b\(.*\) (emaxi_b\1[]),
.ar\(.*\) (emaxi_ar\1[]),
.r\(.*\) (emaxi_r\1[]),
.emesh_\(.*\) (emaxi_\1[]),
);
*/
axi_master axi_master(/*AUTOINST*/
// Outputs
.awid (emaxi_awid[MIDW-1:0]), // Templated
.awaddr (emaxi_awaddr[MAW-1:0]), // Templated
.awlen (emaxi_awlen[3:0]), // Templated
.awsize (emaxi_awsize[2:0]), // Templated
.awburst (emaxi_awburst[1:0]), // Templated
.awlock (emaxi_awlock[1:0]), // Templated
.awcache (emaxi_awcache[3:0]), // Templated
.awprot (emaxi_awprot[2:0]), // Templated
.awvalid (emaxi_awvalid), // Templated
.wid (emaxi_wid[MIDW-1:0]), // Templated
.wdata (emaxi_wdata[MDW-1:0]), // Templated
.wstrb (emaxi_wstrb[STW-1:0]), // Templated
.wlast (emaxi_wlast), // Templated
.wvalid (emaxi_wvalid), // Templated
.bready (emaxi_bready), // Templated
.arid (emaxi_arid[MIDW-1:0]), // Templated
.araddr (emaxi_araddr[MAW-1:0]), // Templated
.arlen (emaxi_arlen[3:0]), // Templated
.arsize (emaxi_arsize[2:0]), // Templated
.arburst (emaxi_arburst[1:0]), // Templated
.arlock (emaxi_arlock[1:0]), // Templated
.arcache (emaxi_arcache[3:0]), // Templated
.arprot (emaxi_arprot[2:0]), // Templated
.arvalid (emaxi_arvalid), // Templated
.rready (emaxi_rready), // Templated
.emesh_access_inb (emaxi_access_inb), // Templated
.emesh_write_inb (emaxi_write_inb), // Templated
.emesh_datamode_inb (emaxi_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb (emaxi_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (emaxi_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb (emaxi_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (emaxi_data_inb[31:0]), // Templated
.emesh_wr_wait_inb (emaxi_wr_wait_inb), // Templated
.emesh_rd_wait_inb (emaxi_rd_wait_inb), // Templated
.awqos (emaxi_awqos[3:0]), // Templated
.arqos (emaxi_arqos[3:0]), // Templated
// Inputs
.aclk (emaxi_aclk), // Templated
.eclk (rxi_eclk), // Templated
.reset (emaxi_reset), // Templated
.awready (emaxi_awready), // Templated
.wready (emaxi_wready), // Templated
.bid (emaxi_bid[MIDW-1:0]), // Templated
.bresp (emaxi_bresp[1:0]), // Templated
.bvalid (emaxi_bvalid), // Templated
.arready (emaxi_arready), // Templated
.rid (emaxi_rid[MIDW-1:0]), // Templated
.rdata (emaxi_rdata[MDW-1:0]), // Templated
.rresp (emaxi_rresp[1:0]), // Templated
.rlast (emaxi_rlast), // Templated
.rvalid (emaxi_rvalid), // Templated
.emesh_access_outb (emaxi_access_outb), // Templated
.emesh_write_outb (emaxi_write_outb), // Templated
.emesh_datamode_outb (emaxi_datamode_outb[1:0]), // Templated
.emesh_ctrlmode_outb (emaxi_ctrlmode_outb[3:0]), // Templated
.emesh_dstaddr_outb (emaxi_dstaddr_outb[31:0]), // Templated
.emesh_srcaddr_outb (emaxi_srcaddr_outb[31:0]), // Templated
.emesh_data_outb (emaxi_data_outb[31:0]), // Templated
.emesh_wr_wait_outb (emaxi_wr_wait_outb)); // Templated
//#####################################
//# ELINK (CHIP Port) Instantiation
//#####################################
//# "manual remapping" of external memory address seen by the chips
assign ext_mem_access = (elink_dstaddr_tmp[31:28] == `VIRT_EXT_MEM) &
~(elink_dstaddr_tmp[31:20] == `AXI_COORD);
assign elink_dstaddr_inb[31:28] = ext_mem_access ? `PHYS_EXT_MEM :
elink_dstaddr_tmp[31:28];
assign elink_dstaddr_inb[27:0] = elink_dstaddr_tmp[27:0];
/*ewrapper_link_top AUTO_TEMPLATE(.emesh_clk_inb (rxi_eclk),
.burst_en (1'b1),
.emesh_dstaddr_inb(elink_dstaddr_tmp[31:0]),
.emesh_\(.*\) (elink_\1[]),
);
*/
ewrapper_link_top ewrapper_link_top
(/*AUTOINST*/
// Outputs
.emesh_clk_inb (rxi_eclk), // Templated
.emesh_access_inb (elink_access_inb), // Templated
.emesh_write_inb (elink_write_inb), // Templated
.emesh_datamode_inb (elink_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb (elink_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (elink_dstaddr_tmp[31:0]), // Templated
.emesh_srcaddr_inb (elink_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (elink_data_inb[31:0]), // Templated
.emesh_wr_wait_inb (elink_wr_wait_inb), // Templated
.emesh_rd_wait_inb (elink_rd_wait_inb), // Templated
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
.rxi_cclk_p (rxi_cclk_p),
.rxi_cclk_n (rxi_cclk_n),
// Inputs
.reset (reset),
.clkin_100 (clkin_100),
.elink_disable (elink_disable),
.elink_cclk_enb (elink_cclk_enb),
.elink_clk_div (elink_clk_div[1:0]),
.emesh_access_outb (elink_access_outb), // Templated
.emesh_write_outb (elink_write_outb), // Templated
.emesh_datamode_outb (elink_datamode_outb[1:0]), // Templated
.emesh_ctrlmode_outb (elink_ctrlmode_outb[3:0]), // Templated
.emesh_dstaddr_outb (elink_dstaddr_outb[31:0]), // Templated
.emesh_srcaddr_outb (elink_srcaddr_outb[31:0]), // Templated
.emesh_data_outb (elink_data_outb[31:0]), // Templated
.emesh_wr_wait_outb (elink_wr_wait_outb), // Templated
.emesh_rd_wait_outb (elink_rd_wait_outb), // Templated
.rxi_data_p (rxi_data_p[7:0]),
.rxi_data_n (rxi_data_n[7:0]),
.rxi_frame_p (rxi_frame_p),
.rxi_frame_n (rxi_frame_n),
.rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n),
.txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n),
.burst_en (1'b1)); // Templated
//####################################
//# AXI-ELINK Interface Instantiation
//####################################
/*axi_elink_if AUTO_TEMPLATE(.eclk (rxi_eclk),
.aclk (esaxi_aclk),
);
*/
axi_elink_if axi_elink_if
(/*AUTOINST*/
// Outputs
.reset_chip (reset_chip),
.reset_fpga (reset_fpga),
.emaxi_access_outb (emaxi_access_outb),
.emaxi_write_outb (emaxi_write_outb),
.emaxi_datamode_outb (emaxi_datamode_outb[1:0]),
.emaxi_ctrlmode_outb (emaxi_ctrlmode_outb[3:0]),
.emaxi_dstaddr_outb (emaxi_dstaddr_outb[31:0]),
.emaxi_srcaddr_outb (emaxi_srcaddr_outb[31:0]),
.emaxi_data_outb (emaxi_data_outb[31:0]),
.emaxi_wr_wait_outb (emaxi_wr_wait_outb),
.esaxi_access_outb (esaxi_access_outb),
.esaxi_write_outb (esaxi_write_outb),
.esaxi_datamode_outb (esaxi_datamode_outb[1:0]),
.esaxi_ctrlmode_outb (esaxi_ctrlmode_outb[3:0]),
.esaxi_dstaddr_outb (esaxi_dstaddr_outb[31:0]),
.esaxi_srcaddr_outb (esaxi_srcaddr_outb[31:0]),
.esaxi_data_outb (esaxi_data_outb[31:0]),
.esaxi_wr_wait_outb (esaxi_wr_wait_outb),
.esaxi_rd_wait_outb (esaxi_rd_wait_outb),
.elink_access_outb (elink_access_outb),
.elink_write_outb (elink_write_outb),
.elink_datamode_outb (elink_datamode_outb[1:0]),
.elink_ctrlmode_outb (elink_ctrlmode_outb[3:0]),
.elink_dstaddr_outb (elink_dstaddr_outb[31:0]),
.elink_srcaddr_outb (elink_srcaddr_outb[31:0]),
.elink_data_outb (elink_data_outb[31:0]),
.elink_wr_wait_outb (elink_wr_wait_outb),
.elink_rd_wait_outb (elink_rd_wait_outb),
.elink_disable (elink_disable),
.elink_cclk_enb (elink_cclk_enb),
.elink_clk_div (elink_clk_div[1:0]),
// Inputs
.eclk (rxi_eclk), // Templated
.aclk (esaxi_aclk), // Templated
.reset (reset),
.emaxi_access_inb (emaxi_access_inb),
.emaxi_write_inb (emaxi_write_inb),
.emaxi_datamode_inb (emaxi_datamode_inb[1:0]),
.emaxi_ctrlmode_inb (emaxi_ctrlmode_inb[3:0]),
.emaxi_dstaddr_inb (emaxi_dstaddr_inb[31:0]),
.emaxi_srcaddr_inb (emaxi_srcaddr_inb[31:0]),
.emaxi_data_inb (emaxi_data_inb[31:0]),
.emaxi_wr_wait_inb (emaxi_wr_wait_inb),
.emaxi_rd_wait_inb (emaxi_rd_wait_inb),
.esaxi_access_inb (esaxi_access_inb),
.esaxi_write_inb (esaxi_write_inb),
.esaxi_datamode_inb (esaxi_datamode_inb[1:0]),
.esaxi_ctrlmode_inb (esaxi_ctrlmode_inb[3:0]),
.esaxi_dstaddr_inb (esaxi_dstaddr_inb[31:0]),
.esaxi_srcaddr_inb (esaxi_srcaddr_inb[31:0]),
.esaxi_data_inb (esaxi_data_inb[31:0]),
.esaxi_wr_wait_inb (esaxi_wr_wait_inb),
.esaxi_rd_wait_inb (esaxi_rd_wait_inb),
.elink_access_inb (elink_access_inb),
.elink_write_inb (elink_write_inb),
.elink_datamode_inb (elink_datamode_inb[1:0]),
.elink_ctrlmode_inb (elink_ctrlmode_inb[3:0]),
.elink_dstaddr_inb (elink_dstaddr_inb[31:0]),
.elink_srcaddr_inb (elink_srcaddr_inb[31:0]),
.elink_data_inb (elink_data_inb[31:0]),
.elink_wr_wait_inb (elink_wr_wait_inb),
.elink_rd_wait_inb (elink_rd_wait_inb));
endmodule // parallella
// Local Variables:
// verilog-library-directories:("." "../elink" "../axi")
// End:
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue May 09 14:50:53 2017
// Host : DESKTOP-7MUQLTN running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/Kiwi/Desktop/Projet_VHDL_-_Paint/04_IP_Xillinx/Clk_Wizard/Clk_Wizard_sim_netlist.v
// Design : Clk_Wizard
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module Clk_Wizard
(VGA_clock,
Main_clock,
resetn,
locked,
Clock_Board);
output VGA_clock;
output Main_clock;
input resetn;
output locked;
input Clock_Board;
(* IBUF_LOW_PWR *) wire Clock_Board;
wire Main_clock;
wire VGA_clock;
wire locked;
wire resetn;
Clk_Wizard_Clk_Wizard_clk_wiz inst
(.Clock_Board(Clock_Board),
.Main_clock(Main_clock),
.VGA_clock(VGA_clock),
.locked(locked),
.resetn(resetn));
endmodule
(* ORIG_REF_NAME = "Clk_Wizard_clk_wiz" *)
module Clk_Wizard_Clk_Wizard_clk_wiz
(VGA_clock,
Main_clock,
resetn,
locked,
Clock_Board);
output VGA_clock;
output Main_clock;
input resetn;
output locked;
input Clock_Board;
wire Clock_Board;
wire Clock_Board_Clk_Wizard;
wire Main_clock;
wire Main_clock_Clk_Wizard;
wire VGA_clock;
wire VGA_clock_Clk_Wizard;
wire clkfbout_Clk_Wizard;
wire locked;
wire reset_high;
wire resetn;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(Clock_Board),
.O(Clock_Board_Clk_Wizard));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(VGA_clock_Clk_Wizard),
.O(VGA_clock));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(Main_clock_Clk_Wizard),
.O(Main_clock));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(21.875000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(10.125000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(11),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(2),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_Clk_Wizard),
.CLKFBOUT(clkfbout_Clk_Wizard),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(Clock_Board_Clk_Wizard),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(VGA_clock_Clk_Wizard),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(Main_clock_Clk_Wizard),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset_high));
LUT1 #(
.INIT(2'h1))
mmcm_adv_inst_i_1
(.I0(resetn),
.O(reset_high));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i32.sub.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i32.sub_tb.vcd");
$dumpvars(0, cpu_tb);
#24
`assert(result, 1);
`assert(result_type, `i32);
`assert(result_empty, 0);
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:27:55 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_ov7670_controller_1_0 -prefix
// system_ov7670_controller_1_0_ system_ov7670_controller_1_0_sim_netlist.v
// Design : system_ov7670_controller_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_ov7670_controller_1_0_i2c_sender
(E,
sioc,
p_0_in,
\busy_sr_reg[1]_0 ,
siod,
\busy_sr_reg[31]_0 ,
clk,
p_1_in,
DOADO,
\busy_sr_reg[31]_1 );
output [0:0]E;
output sioc;
output p_0_in;
output \busy_sr_reg[1]_0 ;
output siod;
input \busy_sr_reg[31]_0 ;
input clk;
input [0:0]p_1_in;
input [15:0]DOADO;
input [0:0]\busy_sr_reg[31]_1 ;
wire [15:0]DOADO;
wire [0:0]E;
wire busy_sr0;
wire \busy_sr[0]_i_3_n_0 ;
wire \busy_sr[0]_i_5_n_0 ;
wire \busy_sr[10]_i_1_n_0 ;
wire \busy_sr[11]_i_1_n_0 ;
wire \busy_sr[12]_i_1_n_0 ;
wire \busy_sr[13]_i_1_n_0 ;
wire \busy_sr[14]_i_1_n_0 ;
wire \busy_sr[15]_i_1_n_0 ;
wire \busy_sr[16]_i_1_n_0 ;
wire \busy_sr[17]_i_1_n_0 ;
wire \busy_sr[18]_i_1_n_0 ;
wire \busy_sr[19]_i_1_n_0 ;
wire \busy_sr[1]_i_1_n_0 ;
wire \busy_sr[20]_i_1_n_0 ;
wire \busy_sr[21]_i_1_n_0 ;
wire \busy_sr[22]_i_1_n_0 ;
wire \busy_sr[23]_i_1_n_0 ;
wire \busy_sr[24]_i_1_n_0 ;
wire \busy_sr[25]_i_1_n_0 ;
wire \busy_sr[26]_i_1_n_0 ;
wire \busy_sr[27]_i_1_n_0 ;
wire \busy_sr[28]_i_1_n_0 ;
wire \busy_sr[29]_i_1_n_0 ;
wire \busy_sr[2]_i_1_n_0 ;
wire \busy_sr[30]_i_1_n_0 ;
wire \busy_sr[31]_i_1_n_0 ;
wire \busy_sr[31]_i_2_n_0 ;
wire \busy_sr[3]_i_1_n_0 ;
wire \busy_sr[4]_i_1_n_0 ;
wire \busy_sr[5]_i_1_n_0 ;
wire \busy_sr[6]_i_1_n_0 ;
wire \busy_sr[7]_i_1_n_0 ;
wire \busy_sr[8]_i_1_n_0 ;
wire \busy_sr[9]_i_1_n_0 ;
wire \busy_sr_reg[1]_0 ;
wire \busy_sr_reg[31]_0 ;
wire [0:0]\busy_sr_reg[31]_1 ;
wire \busy_sr_reg_n_0_[0] ;
wire \busy_sr_reg_n_0_[10] ;
wire \busy_sr_reg_n_0_[11] ;
wire \busy_sr_reg_n_0_[12] ;
wire \busy_sr_reg_n_0_[13] ;
wire \busy_sr_reg_n_0_[14] ;
wire \busy_sr_reg_n_0_[15] ;
wire \busy_sr_reg_n_0_[16] ;
wire \busy_sr_reg_n_0_[17] ;
wire \busy_sr_reg_n_0_[18] ;
wire \busy_sr_reg_n_0_[1] ;
wire \busy_sr_reg_n_0_[21] ;
wire \busy_sr_reg_n_0_[22] ;
wire \busy_sr_reg_n_0_[23] ;
wire \busy_sr_reg_n_0_[24] ;
wire \busy_sr_reg_n_0_[25] ;
wire \busy_sr_reg_n_0_[26] ;
wire \busy_sr_reg_n_0_[27] ;
wire \busy_sr_reg_n_0_[28] ;
wire \busy_sr_reg_n_0_[29] ;
wire \busy_sr_reg_n_0_[2] ;
wire \busy_sr_reg_n_0_[30] ;
wire \busy_sr_reg_n_0_[3] ;
wire \busy_sr_reg_n_0_[4] ;
wire \busy_sr_reg_n_0_[5] ;
wire \busy_sr_reg_n_0_[6] ;
wire \busy_sr_reg_n_0_[7] ;
wire \busy_sr_reg_n_0_[8] ;
wire \busy_sr_reg_n_0_[9] ;
wire clk;
wire \data_sr[10]_i_1_n_0 ;
wire \data_sr[12]_i_1_n_0 ;
wire \data_sr[13]_i_1_n_0 ;
wire \data_sr[14]_i_1_n_0 ;
wire \data_sr[15]_i_1_n_0 ;
wire \data_sr[16]_i_1_n_0 ;
wire \data_sr[17]_i_1_n_0 ;
wire \data_sr[18]_i_1_n_0 ;
wire \data_sr[19]_i_1_n_0 ;
wire \data_sr[22]_i_1_n_0 ;
wire \data_sr[27]_i_1_n_0 ;
wire \data_sr[30]_i_1_n_0 ;
wire \data_sr[31]_i_1_n_0 ;
wire \data_sr[31]_i_2_n_0 ;
wire \data_sr[3]_i_1_n_0 ;
wire \data_sr[4]_i_1_n_0 ;
wire \data_sr[5]_i_1_n_0 ;
wire \data_sr[6]_i_1_n_0 ;
wire \data_sr[7]_i_1_n_0 ;
wire \data_sr[8]_i_1_n_0 ;
wire \data_sr[9]_i_1_n_0 ;
wire \data_sr_reg_n_0_[10] ;
wire \data_sr_reg_n_0_[11] ;
wire \data_sr_reg_n_0_[12] ;
wire \data_sr_reg_n_0_[13] ;
wire \data_sr_reg_n_0_[14] ;
wire \data_sr_reg_n_0_[15] ;
wire \data_sr_reg_n_0_[16] ;
wire \data_sr_reg_n_0_[17] ;
wire \data_sr_reg_n_0_[18] ;
wire \data_sr_reg_n_0_[19] ;
wire \data_sr_reg_n_0_[1] ;
wire \data_sr_reg_n_0_[20] ;
wire \data_sr_reg_n_0_[21] ;
wire \data_sr_reg_n_0_[22] ;
wire \data_sr_reg_n_0_[23] ;
wire \data_sr_reg_n_0_[24] ;
wire \data_sr_reg_n_0_[25] ;
wire \data_sr_reg_n_0_[26] ;
wire \data_sr_reg_n_0_[27] ;
wire \data_sr_reg_n_0_[28] ;
wire \data_sr_reg_n_0_[29] ;
wire \data_sr_reg_n_0_[2] ;
wire \data_sr_reg_n_0_[30] ;
wire \data_sr_reg_n_0_[31] ;
wire \data_sr_reg_n_0_[3] ;
wire \data_sr_reg_n_0_[4] ;
wire \data_sr_reg_n_0_[5] ;
wire \data_sr_reg_n_0_[6] ;
wire \data_sr_reg_n_0_[7] ;
wire \data_sr_reg_n_0_[8] ;
wire \data_sr_reg_n_0_[9] ;
wire [7:6]divider_reg__0;
wire [5:0]divider_reg__1;
wire p_0_in;
wire [7:0]p_0_in__0;
wire [0:0]p_1_in;
wire [1:0]p_1_in_0;
wire sioc;
wire sioc_i_1_n_0;
wire sioc_i_2_n_0;
wire sioc_i_3_n_0;
wire sioc_i_4_n_0;
wire sioc_i_5_n_0;
wire siod;
wire siod_INST_0_i_1_n_0;
LUT6 #(
.INIT(64'h4000FFFF40004000))
\busy_sr[0]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.I2(divider_reg__0[7]),
.I3(p_0_in),
.I4(\busy_sr_reg[1]_0 ),
.I5(p_1_in),
.O(busy_sr0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\busy_sr[0]_i_3
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(\busy_sr[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\busy_sr[0]_i_4
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[3]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(\busy_sr[0]_i_5_n_0 ),
.O(\busy_sr_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFFFE))
\busy_sr[0]_i_5
(.I0(divider_reg__1[5]),
.I1(divider_reg__1[4]),
.I2(divider_reg__0[7]),
.I3(divider_reg__0[6]),
.O(\busy_sr[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[10]_i_1
(.I0(\busy_sr_reg_n_0_[9] ),
.I1(p_0_in),
.O(\busy_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[11]_i_1
(.I0(\busy_sr_reg_n_0_[10] ),
.I1(p_0_in),
.O(\busy_sr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[12]_i_1
(.I0(\busy_sr_reg_n_0_[11] ),
.I1(p_0_in),
.O(\busy_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[13]_i_1
(.I0(\busy_sr_reg_n_0_[12] ),
.I1(p_0_in),
.O(\busy_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[14]_i_1
(.I0(\busy_sr_reg_n_0_[13] ),
.I1(p_0_in),
.O(\busy_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[15]_i_1
(.I0(\busy_sr_reg_n_0_[14] ),
.I1(p_0_in),
.O(\busy_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[16]_i_1
(.I0(\busy_sr_reg_n_0_[15] ),
.I1(p_0_in),
.O(\busy_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[17]_i_1
(.I0(\busy_sr_reg_n_0_[16] ),
.I1(p_0_in),
.O(\busy_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[18]_i_1
(.I0(\busy_sr_reg_n_0_[17] ),
.I1(p_0_in),
.O(\busy_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[19]_i_1
(.I0(\busy_sr_reg_n_0_[18] ),
.I1(p_0_in),
.O(\busy_sr[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[1]_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(p_0_in),
.O(\busy_sr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[20]_i_1
(.I0(p_1_in_0[0]),
.I1(p_0_in),
.O(\busy_sr[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[21]_i_1
(.I0(p_1_in_0[1]),
.I1(p_0_in),
.O(\busy_sr[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[22]_i_1
(.I0(\busy_sr_reg_n_0_[21] ),
.I1(p_0_in),
.O(\busy_sr[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[23]_i_1
(.I0(\busy_sr_reg_n_0_[22] ),
.I1(p_0_in),
.O(\busy_sr[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[24]_i_1
(.I0(\busy_sr_reg_n_0_[23] ),
.I1(p_0_in),
.O(\busy_sr[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[25]_i_1
(.I0(\busy_sr_reg_n_0_[24] ),
.I1(p_0_in),
.O(\busy_sr[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[26]_i_1
(.I0(\busy_sr_reg_n_0_[25] ),
.I1(p_0_in),
.O(\busy_sr[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[27]_i_1
(.I0(\busy_sr_reg_n_0_[26] ),
.I1(p_0_in),
.O(\busy_sr[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[28]_i_1
(.I0(\busy_sr_reg_n_0_[27] ),
.I1(p_0_in),
.O(\busy_sr[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[29]_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(p_0_in),
.O(\busy_sr[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[2]_i_1
(.I0(\busy_sr_reg_n_0_[1] ),
.I1(p_0_in),
.O(\busy_sr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[30]_i_1
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(p_0_in),
.O(\busy_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h22222222A2222222))
\busy_sr[31]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.I3(divider_reg__0[7]),
.I4(divider_reg__0[6]),
.I5(\busy_sr[0]_i_3_n_0 ),
.O(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[31]_i_2
(.I0(p_0_in),
.I1(\busy_sr_reg_n_0_[30] ),
.O(\busy_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[3]_i_1
(.I0(\busy_sr_reg_n_0_[2] ),
.I1(p_0_in),
.O(\busy_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[4]_i_1
(.I0(\busy_sr_reg_n_0_[3] ),
.I1(p_0_in),
.O(\busy_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[5]_i_1
(.I0(\busy_sr_reg_n_0_[4] ),
.I1(p_0_in),
.O(\busy_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[6]_i_1
(.I0(\busy_sr_reg_n_0_[5] ),
.I1(p_0_in),
.O(\busy_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[7]_i_1
(.I0(\busy_sr_reg_n_0_[6] ),
.I1(p_0_in),
.O(\busy_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[8]_i_1
(.I0(\busy_sr_reg_n_0_[7] ),
.I1(p_0_in),
.O(\busy_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[9]_i_1
(.I0(\busy_sr_reg_n_0_[8] ),
.I1(p_0_in),
.O(\busy_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\busy_sr_reg[0]
(.C(clk),
.CE(busy_sr0),
.D(p_1_in),
.Q(\busy_sr_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[10]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[10] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[11]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[11] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[12]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[12] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[13]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[13] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[14]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[14] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[15]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[15] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[16]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[16] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[17]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[17] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[18]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[18] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[19]_i_1_n_0 ),
.Q(p_1_in_0[0]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[1]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[1] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[20]_i_1_n_0 ),
.Q(p_1_in_0[1]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[21]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[21] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[22]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[22]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[22] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[23]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[23] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[24]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[24] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[25]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[25] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[26]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[26] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[27]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[27]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[27] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[28]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[28] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[29]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[29] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[2]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[2] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[30]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[30] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[31]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[31]_i_2_n_0 ),
.Q(p_0_in),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[3]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[3] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[4]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[4] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[5]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[5] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[6]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[6] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[7]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[7] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[8]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[8] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[9]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[9] ),
.S(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[10]_i_1
(.I0(\data_sr_reg_n_0_[9] ),
.I1(p_0_in),
.I2(DOADO[7]),
.O(\data_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[12]_i_1
(.I0(\data_sr_reg_n_0_[11] ),
.I1(p_0_in),
.I2(DOADO[8]),
.O(\data_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[13]_i_1
(.I0(\data_sr_reg_n_0_[12] ),
.I1(p_0_in),
.I2(DOADO[9]),
.O(\data_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[14]_i_1
(.I0(\data_sr_reg_n_0_[13] ),
.I1(p_0_in),
.I2(DOADO[10]),
.O(\data_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[15]_i_1
(.I0(\data_sr_reg_n_0_[14] ),
.I1(p_0_in),
.I2(DOADO[11]),
.O(\data_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[16]_i_1
(.I0(\data_sr_reg_n_0_[15] ),
.I1(p_0_in),
.I2(DOADO[12]),
.O(\data_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[17]_i_1
(.I0(\data_sr_reg_n_0_[16] ),
.I1(p_0_in),
.I2(DOADO[13]),
.O(\data_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[18]_i_1
(.I0(\data_sr_reg_n_0_[17] ),
.I1(p_0_in),
.I2(DOADO[14]),
.O(\data_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[19]_i_1
(.I0(\data_sr_reg_n_0_[18] ),
.I1(p_0_in),
.I2(DOADO[15]),
.O(\data_sr[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[22]_i_1
(.I0(\data_sr_reg_n_0_[22] ),
.I1(\data_sr_reg_n_0_[21] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[27]_i_1
(.I0(\data_sr_reg_n_0_[27] ),
.I1(\data_sr_reg_n_0_[26] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[27]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\data_sr[30]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.O(\data_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[31]_i_1
(.I0(\data_sr_reg_n_0_[31] ),
.I1(\data_sr_reg_n_0_[30] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\data_sr[31]_i_2
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(\data_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[3]_i_1
(.I0(\data_sr_reg_n_0_[2] ),
.I1(p_0_in),
.I2(DOADO[0]),
.O(\data_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[4]_i_1
(.I0(\data_sr_reg_n_0_[3] ),
.I1(p_0_in),
.I2(DOADO[1]),
.O(\data_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[5]_i_1
(.I0(\data_sr_reg_n_0_[4] ),
.I1(p_0_in),
.I2(DOADO[2]),
.O(\data_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[6]_i_1
(.I0(\data_sr_reg_n_0_[5] ),
.I1(p_0_in),
.I2(DOADO[3]),
.O(\data_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[7]_i_1
(.I0(\data_sr_reg_n_0_[6] ),
.I1(p_0_in),
.I2(DOADO[4]),
.O(\data_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[8]_i_1
(.I0(\data_sr_reg_n_0_[7] ),
.I1(p_0_in),
.I2(DOADO[5]),
.O(\data_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[9]_i_1
(.I0(\data_sr_reg_n_0_[8] ),
.I1(p_0_in),
.I2(DOADO[6]),
.O(\data_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[10]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[10] ),
.Q(\data_sr_reg_n_0_[11] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[12]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[13]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[14]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[15]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[16]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[16] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[17]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[17] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[18]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[18] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[19]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[19] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(p_0_in),
.Q(\data_sr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[19] ),
.Q(\data_sr_reg_n_0_[20] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[20] ),
.Q(\data_sr_reg_n_0_[21] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[22]
(.C(clk),
.CE(1'b1),
.D(\data_sr[22]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[22] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[22] ),
.Q(\data_sr_reg_n_0_[23] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[23] ),
.Q(\data_sr_reg_n_0_[24] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[24] ),
.Q(\data_sr_reg_n_0_[25] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[25] ),
.Q(\data_sr_reg_n_0_[26] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[27]
(.C(clk),
.CE(1'b1),
.D(\data_sr[27]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[27] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[27] ),
.Q(\data_sr_reg_n_0_[28] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[28] ),
.Q(\data_sr_reg_n_0_[29] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[1] ),
.Q(\data_sr_reg_n_0_[2] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[29] ),
.Q(\data_sr_reg_n_0_[30] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[31]
(.C(clk),
.CE(1'b1),
.D(\data_sr[31]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[31] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[3]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[4]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[5]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[6]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[7]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[8]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[9]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT1 #(
.INIT(2'h1))
\divider[0]_i_1
(.I0(divider_reg__1[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\divider[1]_i_1
(.I0(divider_reg__1[0]),
.I1(divider_reg__1[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\divider[2]_i_1
(.I0(divider_reg__1[1]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[2]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\divider[3]_i_1
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[1]),
.I3(divider_reg__1[3]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\divider[4]_i_1
(.I0(divider_reg__1[3]),
.I1(divider_reg__1[1]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[2]),
.I4(divider_reg__1[4]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\divider[5]_i_1
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(p_0_in__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\divider[6]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hD2))
\divider[7]_i_2
(.I0(divider_reg__0[6]),
.I1(\busy_sr[0]_i_3_n_0 ),
.I2(divider_reg__0[7]),
.O(p_0_in__0[7]));
FDRE #(
.INIT(1'b1))
\divider_reg[0]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[0]),
.Q(divider_reg__1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[1]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[1]),
.Q(divider_reg__1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[2]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[2]),
.Q(divider_reg__1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[3]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[3]),
.Q(divider_reg__1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[4]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[4]),
.Q(divider_reg__1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[5]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[5]),
.Q(divider_reg__1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[6]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[6]),
.Q(divider_reg__0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[7]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[7]),
.Q(divider_reg__0[7]),
.R(1'b0));
LUT6 #(
.INIT(64'hFCFCFFF8FFFFFFFF))
sioc_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(sioc_i_2_n_0),
.I2(sioc_i_3_n_0),
.I3(\busy_sr_reg_n_0_[1] ),
.I4(sioc_i_4_n_0),
.I5(p_0_in),
.O(sioc_i_1_n_0));
LUT2 #(
.INIT(4'h6))
sioc_i_2
(.I0(divider_reg__0[6]),
.I1(divider_reg__0[7]),
.O(sioc_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hA222))
sioc_i_3
(.I0(sioc_i_5_n_0),
.I1(\busy_sr_reg_n_0_[30] ),
.I2(divider_reg__0[6]),
.I3(p_0_in),
.O(sioc_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7FFF))
sioc_i_4
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(\busy_sr_reg_n_0_[2] ),
.I2(p_0_in),
.I3(\busy_sr_reg_n_0_[30] ),
.O(sioc_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
sioc_i_5
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(\busy_sr_reg_n_0_[1] ),
.I2(\busy_sr_reg_n_0_[29] ),
.I3(\busy_sr_reg_n_0_[2] ),
.O(sioc_i_5_n_0));
FDRE sioc_reg
(.C(clk),
.CE(1'b1),
.D(sioc_i_1_n_0),
.Q(sioc),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
siod_INST_0
(.I0(\data_sr_reg_n_0_[31] ),
.I1(siod_INST_0_i_1_n_0),
.O(siod));
LUT6 #(
.INIT(64'hB0BBB0BB0000B0BB))
siod_INST_0_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(\busy_sr_reg_n_0_[29] ),
.I2(p_1_in_0[0]),
.I3(p_1_in_0[1]),
.I4(\busy_sr_reg_n_0_[11] ),
.I5(\busy_sr_reg_n_0_[10] ),
.O(siod_INST_0_i_1_n_0));
FDRE taken_reg
(.C(clk),
.CE(1'b1),
.D(\busy_sr_reg[31]_0 ),
.Q(E),
.R(1'b0));
endmodule
module system_ov7670_controller_1_0_ov7670_controller
(config_finished,
siod,
sioc,
resend,
clk);
output config_finished;
output siod;
output sioc;
input resend;
input clk;
wire Inst_i2c_sender_n_3;
wire Inst_ov7670_registers_n_16;
wire Inst_ov7670_registers_n_18;
wire clk;
wire config_finished;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire sioc;
wire siod;
wire [15:0]sreg_reg;
wire taken;
system_ov7670_controller_1_0_i2c_sender Inst_i2c_sender
(.DOADO(sreg_reg),
.E(taken),
.\busy_sr_reg[1]_0 (Inst_i2c_sender_n_3),
.\busy_sr_reg[31]_0 (Inst_ov7670_registers_n_18),
.\busy_sr_reg[31]_1 (Inst_ov7670_registers_n_16),
.clk(clk),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.sioc(sioc),
.siod(siod));
system_ov7670_controller_1_0_ov7670_registers Inst_ov7670_registers
(.DOADO(sreg_reg),
.E(taken),
.clk(clk),
.config_finished(config_finished),
.\divider_reg[2] (Inst_i2c_sender_n_3),
.\divider_reg[7] (Inst_ov7670_registers_n_16),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.resend(resend),
.taken_reg(Inst_ov7670_registers_n_18));
endmodule
module system_ov7670_controller_1_0_ov7670_registers
(DOADO,
\divider_reg[7] ,
config_finished,
taken_reg,
p_1_in,
clk,
\divider_reg[2] ,
p_0_in,
resend,
E);
output [15:0]DOADO;
output [0:0]\divider_reg[7] ;
output config_finished;
output taken_reg;
output [0:0]p_1_in;
input clk;
input \divider_reg[2] ;
input p_0_in;
input resend;
input [0:0]E;
wire [15:0]DOADO;
wire [0:0]E;
wire [7:0]address;
wire [7:0]address_reg__0;
wire \address_rep[0]_i_1_n_0 ;
wire \address_rep[1]_i_1_n_0 ;
wire \address_rep[2]_i_1_n_0 ;
wire \address_rep[3]_i_1_n_0 ;
wire \address_rep[4]_i_1_n_0 ;
wire \address_rep[5]_i_1_n_0 ;
wire \address_rep[6]_i_1_n_0 ;
wire \address_rep[7]_i_1_n_0 ;
wire \address_rep[7]_i_2_n_0 ;
wire clk;
wire config_finished;
wire config_finished_INST_0_i_1_n_0;
wire config_finished_INST_0_i_2_n_0;
wire config_finished_INST_0_i_3_n_0;
wire config_finished_INST_0_i_4_n_0;
wire \divider_reg[2] ;
wire [0:0]\divider_reg[7] ;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire taken_reg;
wire [15:0]NLW_sreg_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPBDOP_UNCONNECTED;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address_reg__0[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address_reg__0[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address_reg__0[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address_reg__0[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address_reg__0[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address_reg__0[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address_reg__0[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address_reg__0[7]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address[7]),
.R(resend));
LUT1 #(
.INIT(2'h1))
\address_rep[0]_i_1
(.I0(address_reg__0[0]),
.O(\address_rep[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h6))
\address_rep[1]_i_1
(.I0(address_reg__0[0]),
.I1(address_reg__0[1]),
.O(\address_rep[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h78))
\address_rep[2]_i_1
(.I0(address_reg__0[1]),
.I1(address_reg__0[0]),
.I2(address_reg__0[2]),
.O(\address_rep[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h7F80))
\address_rep[3]_i_1
(.I0(address_reg__0[2]),
.I1(address_reg__0[0]),
.I2(address_reg__0[1]),
.I3(address_reg__0[3]),
.O(\address_rep[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h7FFF8000))
\address_rep[4]_i_1
(.I0(address_reg__0[3]),
.I1(address_reg__0[1]),
.I2(address_reg__0[0]),
.I3(address_reg__0[2]),
.I4(address_reg__0[4]),
.O(\address_rep[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\address_rep[5]_i_1
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h9))
\address_rep[6]_i_1
(.I0(\address_rep[7]_i_2_n_0 ),
.I1(address_reg__0[6]),
.O(\address_rep[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hD2))
\address_rep[7]_i_1
(.I0(address_reg__0[6]),
.I1(\address_rep[7]_i_2_n_0 ),
.I2(address_reg__0[7]),
.O(\address_rep[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\address_rep[7]_i_2
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h0000FFFE))
\busy_sr[0]_i_2
(.I0(config_finished_INST_0_i_4_n_0),
.I1(config_finished_INST_0_i_3_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_1_n_0),
.I4(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0001))
config_finished_INST_0
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.O(config_finished));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_1
(.I0(DOADO[5]),
.I1(DOADO[4]),
.I2(DOADO[7]),
.I3(DOADO[6]),
.O(config_finished_INST_0_i_1_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_2
(.I0(DOADO[1]),
.I1(DOADO[0]),
.I2(DOADO[3]),
.I3(DOADO[2]),
.O(config_finished_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_3
(.I0(DOADO[13]),
.I1(DOADO[12]),
.I2(DOADO[15]),
.I3(DOADO[14]),
.O(config_finished_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_4
(.I0(DOADO[9]),
.I1(DOADO[8]),
.I2(DOADO[11]),
.I3(DOADO[10]),
.O(config_finished_INST_0_i_4_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\divider[7]_i_1
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.I4(\divider_reg[2] ),
.I5(p_0_in),
.O(\divider_reg[7] ));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "4096" *)
(* RTL_RAM_NAME = "U0/Inst_ov7670_registers/sreg" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "1023" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "15" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h53295217510C50344F4014383A04401004008C003E000C001100120412801280),
.INIT_01(256'h229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440),
.INIT_02(256'h90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
sreg_reg
(.ADDRARDADDR({1'b0,1'b0,address,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(clk),
.CLKBWRCLK(1'b0),
.DIADI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO(DOADO),
.DOBDO(NLW_sreg_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_sreg_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_sreg_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000055555554))
taken_i_1
(.I0(p_0_in),
.I1(config_finished_INST_0_i_1_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_3_n_0),
.I4(config_finished_INST_0_i_4_n_0),
.I5(\divider_reg[2] ),
.O(taken_reg));
endmodule
(* CHECK_LICENSE_TYPE = "system_ov7670_controller_1_0,ov7670_controller,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_controller,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_ov7670_controller_1_0
(clk,
resend,
config_finished,
sioc,
siod,
reset,
pwdn,
xclk);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input resend;
output config_finished;
output sioc;
inout siod;
(* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) output reset;
output pwdn;
output xclk;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire config_finished;
wire resend;
wire sioc;
wire siod;
assign pwdn = \<const0> ;
assign reset = \<const1> ;
GND GND
(.G(\<const0> ));
system_ov7670_controller_1_0_ov7670_controller U0
(.clk(clk),
.config_finished(config_finished),
.resend(resend),
.sioc(sioc),
.siod(siod));
VCC VCC
(.P(\<const1> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Generates the current game screen contents.
*/
module game_engine (
RESET,
SYSTEM_CLOCK,
VGA_CLOCK,
PADDLE_A_POSITION,
PADDLE_B_POSITION,
PIXEL_H,
PIXEL_V,
BALL_H,
BALL_V,
PIXEL
);
input RESET;
input SYSTEM_CLOCK;
input VGA_CLOCK;
input [7:0] PADDLE_A_POSITION;
input [7:0] PADDLE_B_POSITION;
input [10:0] PIXEL_H;
input [10:0] PIXEL_V;
output [10:0] BALL_H;
output [10:0] BALL_V;
output [2:0] PIXEL; // 1 red, 1 green, 1 blue
reg [2:0] pixel;
reg [10:0] paddle_a_pos;
reg [10:0] paddle_b_pos;
reg [10:0] ball_h;
reg [10:0] ball_v;
wire [10:0] ball_h_wire;
wire [10:0] ball_v_wire;
wire border = (PIXEL_V <= 4 || PIXEL_V >= 474 || PIXEL_H <= 4 || PIXEL_H >= 774);
wire net = (PIXEL_V[4] == 1 && (PIXEL_H == 389 || PIXEL_H == 390));
wire paddle_a = (PIXEL_H >= 10 && PIXEL_H <= 20 && PIXEL_V >= paddle_a_pos && PIXEL_V <= (paddle_a_pos + 75));
wire paddle_b = (PIXEL_H >= 760 && PIXEL_H <= 770 && PIXEL_V >= paddle_b_pos && PIXEL_V <= (paddle_b_pos + 75));
wire ball = PIXEL_H >= ball_h && PIXEL_H <= (ball_h + 16) && PIXEL_V >= ball_v && PIXEL_V <= (ball_v + 16);
wire [2:0] score_rgb;
reg [7:0] score_player_one;
reg [7:0] score_player_two;
score score_1(
.clk(SYSTEM_CLOCK),
.PIXEL_H(PIXEL_H),
.PIXEL_V(PIXEL_V),
.PLAYER_ONE(score_player_one),
.PLAYER_TWO(score_player_two),
.PIXEL(score_rgb)
);
always @ (posedge VGA_CLOCK) begin
// Max incomming postion is 255
// so double to get to 510 which is a bit bigger than wanted.
paddle_a_pos <= PADDLE_A_POSITION << 1;
paddle_b_pos <= PADDLE_B_POSITION << 1;
end
// Ball
reg [16:0] ball_timer;
reg [27:0] ball_timer_delay;
reg ball_h_direction;
reg ball_v_direction;
always @ (posedge VGA_CLOCK or posedge RESET) begin
if (RESET) begin
ball_h <= 382;
ball_v <= 200;
ball_h_direction <= 0;
ball_v_direction <= 0;
ball_timer <= 0;
ball_timer_delay <= 28'd67108863;
score_player_one <= 0;
score_player_two <= 0;
end else begin
if (ball_timer_delay > 0) begin
ball_timer_delay <= ball_timer_delay -1;
end
else begin
ball_timer <= ball_timer + 1;
end
// Only move the ball when timer says so.
if (ball_timer == 17'd91071) begin
ball_timer <= 0;
// Move the ball
if (ball_h_direction) begin
ball_h <= ball_h + 1;
// Paddle B detection (right side)
if (ball_h > 755) begin
if (ball_v >= paddle_b_pos && ball_v < (paddle_b_pos + 75)) begin
// Hit the paddle
ball_h_direction <= 0;
end
else begin
// Missed the paddle - new serve
ball_h <= 382;
ball_h_direction <= 1;
ball_timer_delay <= 28'd67108863;
score_player_one <= score_player_one + 1'd1;
end
end
end
else begin
ball_h <= ball_h - 1;
// Paddle A detection (left side)
if (ball_h < 20) begin
if (ball_v >= paddle_a_pos && ball_v < (paddle_a_pos + 75)) begin
// Hit the paddle
ball_h_direction <= 1;
end
else begin
// Missed the paddle - new serve
ball_h <= 382;
ball_h_direction <= 0;
ball_timer_delay <= 28'd67108863;
score_player_two <= score_player_two + 1'd1;
end
end
end
if (ball_v_direction) begin
ball_v <= ball_v + 1;
// Bottom border collision
if (ball_v > 470) ball_v_direction <= 0;
end
else begin
ball_v <= ball_v - 1;
// Top border collision
if (ball_v < 4) ball_v_direction <= 1;
end
end
end
end
// Draw the pixel for the requested vga location.
always @ (posedge VGA_CLOCK) begin
if (paddle_a) begin
pixel <= 3'b111; // white paddle
end
else if (paddle_b) begin
pixel <= 3'b111; // white paddle
end
else if (border) begin
pixel <= 3'b100; // red border
end
else if (ball && ball_timer_delay == 0) begin
pixel <= 3'b001; // blue ball
end
else if (score_rgb) begin
pixel <= score_rgb;
end
else if (net) begin
pixel <= 3'b110; // yellow net
end
else begin
pixel <= 3'b000; // black
end
end
assign PIXEL = pixel;
assign BALL_H = ball_h;
assign BALL_V = ball_v;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4BB_TB_V
`define SKY130_FD_SC_HDLL__NAND4BB_TB_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand4bb.v"
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_hdll__nand4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4BB_TB_V
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`timescale 1ns/100ps
`include "master_updateable_megarom.v"
`define assert(condition, message) if(!(condition)) begin $display(message); $finish(1); end
module master_updateable_megarom_tb;
// test clock
reg clk;
// inputs to the module under test
wire [7:0] D; // inout, but we only care about it when it's an output
reg [16:0] bbc_A = 16'b0; // driven by BBC
reg [1:0] cpld_JP = 2'b00; // driven externally
// outputs from the module under test
wire [18:0] flash_A;
wire flash_nOE;
wire flash_nWE;
// test spi feeder
reg spi_ss = 1'b1;
reg spi_sck = 1'b0;
reg spi_mosi = 1'b0;
wire spi_miso;
reg [31:0] spi_shift;
reg [31:0] spi_d;
reg spi_start = 0; // drive this high for one clk pulse to start an spi transaction
reg [5:0] spi_count;
// module under test
master_updateable_megarom dut(
.D(D),
.bbc_A(bbc_A),
.flash_A(flash_A),
.flash_nOE(flash_nOE),
.flash_nWE(flash_nWE),
.cpld_SCK_in(spi_sck),
.cpld_MOSI(spi_mosi),
.cpld_SS(spi_ss),
.cpld_MISO(spi_miso),
.cpld_JP(cpld_JP)
);
// clock driver
initial begin
clk = 1'b0;
forever #9 clk = ~clk;
end
// spi process
always @(posedge clk) begin
if (spi_start == 1'b1) begin
$display("- start SPI transaction");
spi_ss <= 1'b0;
spi_count <= 6'd32;
spi_mosi <= spi_d[31]; // first bit
spi_shift <= {spi_d[30:0], 1'b0};
spi_sck <= 1'b0;
end else if (spi_ss == 1'b0) begin
if (spi_count == 0) begin
$display("- end SPI transaction with spi_shift=%x (A %x, rnw %x, wdata %x, rdata %x)",
spi_shift, spi_shift[31:13], spi_shift[12], spi_shift[11:4], spi_shift[7:0]);
spi_ss <= 1'b1; // end of transaction
end else if (spi_sck == 1'b0) begin
spi_sck <= 1'b1;
end else begin
// mid-transaction
spi_mosi <= spi_shift[31];
spi_shift <= {spi_shift[30:0], spi_miso};
spi_count <= spi_count - 1;
spi_sck <= 1'b0;
end;
end
end
always @(negedge dut.allowing_bbc_access) begin
$display("disallowing bbc access");
end
always @(posedge dut.allowing_bbc_access) begin
$display("allowing bbc access");
end
always @(negedge flash_nOE) begin
$display("flash_nOE low with flash_A=%x", flash_A);
end
// flash fixture always reads 0x42
assign D = (flash_nOE == 1'b0) ? 8'h42 : 8'hZZ;
always @(posedge flash_nOE) begin
$display("flash_nOE high with flash_A=%x", flash_A);
end
always @(negedge flash_nWE) begin
$display("flash_nWE low with flash_A=%x and D=%x", flash_A, D);
end
always @(posedge flash_nWE) begin
$display("flash_nWE high with flash_A=%x and D=%x", flash_A, D);
end
initial begin
$display("running master_updateable_megarom_tb");
$dumpfile("master_updateable_megarom_tb.vcd");
$dumpvars(0, master_updateable_megarom_tb);
$display("start");
repeat(10) @(posedge clk);
// check that we start out letting the BBC control the flash
`assert(dut.allowing_bbc_access == 1'b1, "FAIL: not allowing bbc access initially");
$display("\nSetting bbc_A to 12345");
bbc_A <= 17'h12345;
$display("\nTEST that ffffff00 disables BBC access");
spi_d <= 32'hffffff00;
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
@(posedge clk);
`assert(dut.allowing_bbc_access == 1'b0, "FAIL: ffffff00 didn't disable bbc access");
$display("\nTEST that ffffffff reenables BBC access");
spi_d <= 32'hffffffff;
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
@(posedge clk);
`assert(dut.allowing_bbc_access == 1'b1, "FAIL: 32 1's didn't reenable bbc access");
$display("\nTEST that we can write to the flash (51234)");
// message format for a WRITE: 17 address bits, rnw, 8 data bits, 6 zeros (32 bits total)
// with the write happening during the six zeros
spi_d <= {19'b1010001001000110100, 1'b0, 8'b10001001, 4'b0000};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
`assert(dut.allowing_bbc_access == 1'b0, "FAIL: write operation unlocked bbc access");
$display("\nTEST that we can read from the flash (70f0f)");
// message format for a READ: 17 address bits, rnw, 14 zeros (32 bits total)
// with the data byte returned in the final 8 bits
spi_d <= {19'b1110000111100001111, 1'b1, 12'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
`assert(dut.allowing_bbc_access == 1'b0, "FAIL: write operation unlocked bbc access");
$display("\nTEST that the unlock process appears correct");
spi_d <= {19'h5555, 1'b0, 8'hAA, 4'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19'h2AAA, 1'b0, 8'h55, 4'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19'h5555, 1'b0, 8'h90, 4'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19'h0, 1'b1, 12'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19'h1, 1'b1, 12'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19'h5555, 1'b0, 8'hF0, 4'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
$display("^^^ expect write 5555, write 2AAA, write 5555, read 0, read 1, write 5555");
// finish off
$display("running out the clock");
repeat(1000) @(posedge clk);
$display("PASS");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DECAP_4_V
`define SKY130_FD_SC_MS__DECAP_4_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__decap_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DECAP_4_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:54:06 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_1_0_stub.v
// Design : design_1_axi_gpio_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [3:0]gpio_io_i;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31O_SYMBOL_V
`define SKY130_FD_SC_LP__A31O_SYMBOL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a31o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31O_SYMBOL_V
|
`ifndef SDIO_DEFINES
`define SDIO_DEFINES
`define SDIO_STATE_RESET 0
`define SDIO_STATE_ACTIVE 1
`define SDIO_C_BIT_TXRX_DIR 1
`define SDIO_C_BIT_CMD_START 2
`define SDIO_C_BIT_CMD_END 7
`define SDIO_C_BIT_ARG_START 8
`define SDIO_C_BIT_ARG_END 39
`define SDIO_C_BIT_CRC_START 40
`define SDIO_C_BIT_CRC_END 46
`define SDIO_C_BIT_FINISH 47
`define SDIO_R_BIT_START_BIT 0
`define SDIO_R_BIT_TXRX_DIR 1
`define SD_CMD_GO_IDLE_STATE (6'd0 )
//`define SD_CMD_SEND_CID (6'd2 )
`define SD_CMD_SEND_RELATIVE_ADDR (6'd3 )
//`define SD_CMD_SET_DSR (6'd4 )
`define SD_CMD_IO_SEND_OP_CMD (6'd5 )
//`define SD_CMD_SWITCH_FUNC (6'd6 )
`define SD_CMD_SEL_DESEL_CARD (6'd7 )
`define SD_CMD_SEND_IF_COND (6'd8 )
//`define SD_CMD_SEND_CSD (6'd9 )
//`define SD_CMD_SEND_CID (6'd10)
`define SD_CMD_VOLTAGE_SWITCH (6'd11)
//`define SD_CMD_STOP_TRANSMISSION (6'd12)
//`define SD_CMD_SEND_STATUS (6'd13)
`define SD_CMD_GO_INACTIVE_STATE (6'd15)
//`define SD_CMD_SET_BLOCKLEN (6'd16)
//`define SD_CMD_READ_SINGLE_BLOCK (6'd17)
//`define SD_CMD_READ_MULTIPLE_BLOCK (6'd18)
`define SD_CMD_SEND_TUNNING_BLOCK (6'd19)
//`define SD_CMD_SET_BLOCK_COUNT (6'd23)
//`define SD_CMD_WRITE_BLOCK (6'd24)
//`define SD_CMD_WRITE_MULTIPLE_BLOCK (6'd25)
//`define SD_CMD_PROGRAM_CSD (6'd27)
//`define SD_CMD_SET_WRITE_PROT (6'd28)
//`define SD_CMD_CLR_WRITE_PRO (6'd29)
//`define SD_CMD_SEND_WRITE_PROT (6'd30)
//`define SD_CMD_ERASE_WR_BLK_START (6'd32)
//`define SD_CMD_ERASE_WR_BLK_END (6'd33)
//`define SD_CMD_ERASE (6'd38)
//`define SD_CMD_LOCK_UNLOCK (6'd42)
`define SD_CMD_IO_RW_DIRECT (6'd52)
`define SD_CMD_IO_RW_EXTENDED (6'd53)
//`define SD_CMD_APP_CMD (6'd55)
//`define SD_CMD_GEN_CMD (6'd56)
//`define SD_ACMD_SET_BUS_WIDTH (6'd6)
//`define SD_ACMD_SD_STATUS (6'd13)
//`define SD_ACMD_SEND_NUM_WR_BLOCK (6'd22)
//`define SD_ACMD_SET_WR_BLK_ERASE_CNT (6'd23)
//`define SD_ACMD_SD_APP_OP_COND (6'd41)
//`define SD_ACMD_SET_CLR_CARD_DETECT (6'd42)
//`define SD_ACMD_SEND_SCR (6'd51)
//Functions
//Relative Card Address
`define RELATIVE_CARD_ADDRESS (16'h0001)
//Not SD_CURRENT_STATE shall always return 0x0F
//Card Status
`define CMD_RSP_CMD 45:40
`define CMD_RSP_CRD_STS_START (39)
`define CMD_RSP_CRD_STS_END (8)
//IO_SEND_OP_COND Response (R4 32 bits)
`define CMD5_ARG_S18R (24)
`define CMD5_ARG_OCR 23:0
`define VHS_DEFAULT_VALUE (4'b0001)
`define CMD7_RCA 31:16
`define CMD8_ARG_VHS_START 15
`define CMD8_ARG_VHS_END 8
`define CMD8_ARG_VHS 15:8
`define CMD8_ARG_PATTERN 7:0
`define CMD52_ARG_RW_FLAG 31 /* 0 = Read 1 = Write */
`define CMD52_ARG_FNUM 30:27
`define CMD52_ARG_RAW_FLAG 26 /* Read the value of the register after a write RW_FLAG = 1*/
`define CMD52_ARG_REG_ADDR 25:9
`define CMD52_ARG_WR_DATA 7:0
`define CMD52_RST_ADDR 6
`define CMD52_RST_BIT 3
//Extended
`define CMD53_ARG_RW_FLAG 31
`define CMD53_ARG_FNUM 30:28
`define CMD53_ARG_BLOCK_MODE 27
`define CMD53_ARG_INC_ADDR 26
`define CMD53_ARG_REG_ADDR 25:9
`define CMD53_ARG_DATA_COUNT 8:0
//COMMAND SEL DESEL CARD
//Response R1
`define R1_OUT_OF_RANGE (39)
`define R1_COM_CRC_ERROR (38)
`define R1_ILLEGAL_COMMAND (37)
`define R1_ERROR (19)
`define R1_CURRENT_STATE 12:9
//Respone R4
`define R4_RSRVD 45:40
`define R4_READY (39) /* Card is ready to operate */
`define R4_NUM_FUNCS 38:36 /* Number of functions */
`define R4_MEM_PRESENT (35) /* Memory is Also Availalbe */
`define R4_UHSII_AVAILABLE (34) /* Ultra HS Mode II Available */
`define R4_S18A (32) /* Accept switch to 1.8V */
`define R4_IO_OCR 31:8 /* Operating Condition Range */
//Response R5
`define R5_FLAGS_RANGE 31:16
`define R5_DATA 15:8
`define R5_FLAG_CRC_ERROR (15)
`define R5_INVALID_CMD (14)
`define R5_FLAG_CURR_STATE 13:12
`define R5_FLAG_ERROR (11)
`define R5_INVALID_FNUM (9)
`define R5_OUT_OF_RANGE (8)
//Response R6
`define R6_REL_ADDR 39:24
`define R6_STS_CRC_COMM_ERR (23)
`define R6_STS_ILLEGAL_CMD (22)
`define R6_STS_ERROR (21)
//Response 7
`define R7_VHS 19:16
`define R7_PATTERN 15:8
//FBR
`define FBR_FUNC_ID_ADDR 0
`define FBR_FUNC_EXT_ID_ADDR 1
`define FBR_POWER_SUPPLY_ADDR 2
`define FBR_ISDIO_FUNC_ID_ADDR 3
`define FBR_MANF_ID_LOW_ADDR 4
`define FBR_MANF_ID_HIGH_ADDR 5
`define FBR_PROD_ID_LOW_ADDR 6
`define FBR_PROD_ID_HIGH_ADDR 7
`define FBR_ISDIO_PROD_TYPE 8
`define FBR_CIS_LOW_ADDR 9
`define FBR_CIS_MID_ADDR 10
`define FBR_CIS_HIGH_ADDR 11
`define FBR_CSA_LOW_ADDR 12
`define FBR_CSA_MID_ADDR 13
`define FBR_CSA_HIGH_ADDR 14
`define FBR_DATA_ACC_ADDR 15
`define FBR_BLOCK_SIZE_LOW_ADDR 16
`define FBR_BLOCK_SIZE_HIGH_ADDR 17
`endif
|
`timescale 1 ns/100 ps
// Name: WcaReadDwordReg.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaReadDwordReg
(
input wire reset, //Active Hi
input wire clock, //System clock, should be synchronous with WcaRegbus
input wire enableIn, //Allows input if specified.
input wire [31:0] in,
//Internal Interface.
input wire [11:0] rbusCtrl, // Address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter my_addr = 0;
wire [7:0] Q0;
wire [7:0] Q1;
wire [7:0] Q2;
wire [7:0] Q3;
wire addrValid = (my_addr == rbusCtrl[11:4]);
wire read = addrValid & rbusCtrl[3];
wire enable = enableIn & ~addrValid; //Latch if address is us.
//Count register for 4 pulse read.
reg [1:0] select;
always @(posedge rbusCtrl[0])
begin
if( reset | ~addrValid)
select <= 2'h0;
else if(rbusCtrl[1] & addrValid)
select <= select + 2'h1;
end
// Only allow latching when addres is not valid. If preparing for a read, everything must be stable.
WcaRegCore8 sr3( .Data(in[31:24]), .Enable( enable ), .Aclr(reset), .Clock(clock), .Q(Q3));
WcaRegCore8 sr2( .Data(in[23:16]), .Enable( enable ), .Aclr(reset), .Clock(clock), .Q(Q2));
WcaRegCore8 sr1( .Data(in[15:8]), .Enable( enable ), .Aclr(reset), .Clock(clock), .Q(Q1));
WcaRegCore8 sr0( .Data(in[7:0]), .Enable( enable ), .Aclr(reset), .Clock(clock), .Q(Q0));
//Place data on the buss if reading.
assign rbusData = (read & select == 2'h3) ? Q3 : 8'bz;
assign rbusData = (read & select == 2'h2) ? Q2 : 8'bz;
assign rbusData = (read & select == 2'h1) ? Q1 : 8'bz;
assign rbusData = (read & select == 2'h0) ? Q0 : 8'bz;
endmodule // WcaReadDwordReg
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__BUF_BEHAVIORAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__buf (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUF_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__INV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__INV_FUNCTIONAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__inv (
VPWR,
VGND,
Y ,
A
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__INV_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:06:59 11/16/2014
// Design Name:
// Module Name: serial
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module serial # (
parameter TRUE = 1'b1,
parameter FALSE = 1'b0,
parameter CLOCK_PER_BAUD_RATE = 5208,
parameter SERIAL_STATE_LAST = 8,
parameter SERIAL_STATE_SENT = 9,
parameter SERIAL_STATE_WAIT = 10
)(
input CLOCK_50M,
// input RX,
output TX,
input [63:0] send_buffer_in,
input [2:0] send_buffer_count_in,
// output [63:0] send_buffer_out,
output [2:0] send_buffer_count_out,
output LED1,
output LED2
);
reg [63:0] send_buffer;
reg [2:0] send_buffer_count;
assign send_buffer_out = send_buffer;
assign send_buffer_count_out = send_buffer_count;
/*
* CLOCK GENERATOR
*/
reg CLOCK = FALSE;
reg [15:0] clock_counter;
always @(posedge CLOCK_50M) begin
if (clock_counter < CLOCK_PER_BAUD_RATE) begin
CLOCK <= FALSE;
clock_counter <= clock_counter + 1;
end
else begin
CLOCK <= TRUE;
clock_counter <= 0;
end
end
/*
* TRANSMIT DATA
*/
// reg serial_state = SERIAL_STATE_WAIT;
reg [7:0] tx_buffer = "A";
reg [3:0] tx_counter = SERIAL_STATE_WAIT; // 0->start bit sent,1=>first bit sent,...8=>wight bit sent,9=>sent, 10=>not send yet
reg tx_state = TRUE;
assign TX = tx_state;
assign LED1 = tx_state;
assign LED2 = TRUE;
// wire send_buffer_input;
// wire send_buffer_count_input;
// assign send_buffer_input = send_buffer;
// assign send_buffer_count_input = send_buffer_count;
always @(posedge CLOCK) begin
if (tx_counter == SERIAL_STATE_WAIT) begin
tx_state <= FALSE;
tx_counter <= 0;
end
else if (tx_counter == SERIAL_STATE_LAST) begin
tx_state <= TRUE;
tx_counter <= SERIAL_STATE_SENT;
end
else if (tx_counter == SERIAL_STATE_SENT && send_buffer_count_in > 0) begin
tx_buffer <= send_buffer_in[7:0];
send_buffer <= send_buffer_in >> 8;
send_buffer_count <= send_buffer_count_in - 1;
end
else begin
tx_state <= tx_buffer[tx_counter];
tx_counter <= tx_counter + 1;
end
end
// function send (
// input dummy
// );
// begin
// tx_buffer = "A";
// tx_counter = SERIAL_STATE_WAIT;
// end
// endfunction
/*
* RECEIVE DATA
*/
// always @(posedge CLOCK) begin
// end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_r_l2d_rep_bot.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_r_l2d_rep_bot (/*AUTOARG*/
// Outputs
fuse_l2d_rden_buf, fuse_l2d_wren_buf, si_buf, arst_l_buf, se_buf,
sehold_buf, fuse_l2d_rid_buf, fuse_read_data_in_buf,
fuse_l2d_data_in_buf, word_en_l, col_offset_l, set_l, wr_en_l,
way_sel_l, decc_in_l, scbuf_scdata_fbdecc_top_buf,
scbuf_scdata_fbdecc_bot_buf, sbdt_l, sbdb_l, fuse_clk1_buf,
fuse_clk2_buf, mem_write_disable_buf,
// Inputs
fuse_l2d_rden, fuse_l2d_wren, si, arst_l, se, sehold,
fuse_l2d_rid, fuse_read_data_in, fuse_l2d_data_in, word_en,
col_offset, set, wr_en, way_sel, decc_in, fbdt_l, fbdb_l,
scdata_scbuf_decc_top, scdata_scbuf_decc_bot,
efc_scdata_fuse_clk1, efc_scdata_fuse_clk2, mem_write_disable
);
input fuse_l2d_rden;
input [5:0] fuse_l2d_wren;
input si;
input arst_l;
input se;
input sehold;
input [2:0] fuse_l2d_rid;
input fuse_read_data_in;
input fuse_l2d_data_in;
input [3:0] word_en;
input col_offset;
input [9:0] set;
input wr_en;
input [11:0] way_sel;
input [155:0] decc_in;
input [155:0] fbdt_l;
input [155:0] fbdb_l;
input [155:0] scdata_scbuf_decc_top;
input [155:0] scdata_scbuf_decc_bot;
input efc_scdata_fuse_clk1;
input efc_scdata_fuse_clk2;
input mem_write_disable;
output fuse_l2d_rden_buf;
output [5:0] fuse_l2d_wren_buf;
output si_buf;
output arst_l_buf;
output se_buf;
output sehold_buf;
output [2:0] fuse_l2d_rid_buf;
output fuse_read_data_in_buf;
output fuse_l2d_data_in_buf;
output [3:0] word_en_l;
output col_offset_l;
output [9:0] set_l;
output wr_en_l;
output [11:0] way_sel_l;
output [155:0] decc_in_l;
output [155:0] scbuf_scdata_fbdecc_top_buf;
output [155:0] scbuf_scdata_fbdecc_bot_buf;
output [155:0] sbdt_l;
output [155:0] sbdb_l;
output fuse_clk1_buf;
output fuse_clk2_buf;
output mem_write_disable_buf;
///////////////////////////////////////////////////////////////////////
// Non-inverting Buffers
///////////////////////////////////////////////////////////////////////
assign fuse_l2d_rden_buf = fuse_l2d_rden;
assign fuse_l2d_wren_buf[5:0] = fuse_l2d_wren[5:0];
assign si_buf = si;
assign arst_l_buf = arst_l;
assign se_buf = se;
assign sehold_buf = sehold;
assign fuse_l2d_rid_buf[2:0] = fuse_l2d_rid[2:0];
assign fuse_read_data_in_buf = fuse_read_data_in;
assign fuse_l2d_data_in_buf = fuse_l2d_data_in;
assign fuse_clk1_buf = efc_scdata_fuse_clk1;
assign fuse_clk2_buf = efc_scdata_fuse_clk2;
assign mem_write_disable_buf = mem_write_disable;
///////////////////////////////////////////////////////////////////////
// Inverting Buffers
///////////////////////////////////////////////////////////////////////
assign word_en_l[3:0] = ~word_en[3:0];
assign col_offset_l = ~col_offset;
assign set_l[9:0] = ~set[9:0];
assign wr_en_l = ~wr_en;
assign way_sel_l = ~way_sel;
assign decc_in_l[155:0] = ~decc_in[155:0];
assign scbuf_scdata_fbdecc_top_buf[155:0] = ~fbdt_l[155:0];
assign scbuf_scdata_fbdecc_bot_buf[155:0] = ~fbdb_l[155:0];
assign sbdt_l[155:0] = ~scdata_scbuf_decc_top[155:0];
assign sbdb_l[155:0] = ~scdata_scbuf_decc_bot[155:0];
endmodule // bw_r_l2d_rep_bot
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet MAC/PHY combination with TX and RX FIFOs
*/
module eth_mac_phy_10g_fifo #
(
parameter DATA_WIDTH = 64,
parameter HDR_WIDTH = (DATA_WIDTH/32),
parameter AXIS_DATA_WIDTH = DATA_WIDTH,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_PIPELINE_OUTPUT = 2,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FIFO_PIPELINE_OUTPUT = 2,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
parameter RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter TX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_FIFO_DEPTH = 64,
parameter PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = 0,
parameter PTP_TAG_WIDTH = 16,
parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE && TX_PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
input wire logic_clk,
input wire logic_rst,
input wire ptp_sample_clk,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* Transmit timestamp output
*/
output wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96,
output wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag,
output wire m_axis_tx_ptp_ts_valid,
input wire m_axis_tx_ptp_ts_ready,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* PTP clock
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
input wire ptp_ts_step,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
);
parameter KEEP_WIDTH = DATA_WIDTH/8;
wire [DATA_WIDTH-1:0] tx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] tx_fifo_axis_tkeep;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire [TX_USER_WIDTH-1:0] tx_fifo_axis_tuser;
wire [DATA_WIDTH-1:0] rx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] rx_fifo_axis_tkeep;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire [RX_USER_WIDTH-1:0] rx_fifo_axis_tuser;
wire [PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] tx_axis_ptp_ts_96;
wire [PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag;
wire tx_axis_ptp_ts_valid;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
wire rx_bad_block_int;
wire rx_block_lock_int;
wire rx_high_ber_int;
reg [4:0] rx_sync_reg_1 = 5'd0;
reg [4:0] rx_sync_reg_2 = 5'd0;
reg [4:0] rx_sync_reg_3 = 5'd0;
reg [4:0] rx_sync_reg_4 = 5'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
assign rx_bad_block = rx_sync_reg_3[2] ^ rx_sync_reg_4[2];
assign rx_block_lock = rx_sync_reg_3[3] ^ rx_sync_reg_4[3];
assign rx_high_ber = rx_sync_reg_3[4] ^ rx_sync_reg_4[4];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 5'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_high_ber_int, rx_block_lock_int, rx_bad_block_int, rx_error_bad_fcs_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 5'd0;
rx_sync_reg_3 <= 5'd0;
rx_sync_reg_4 <= 5'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
// PTP timestamping
generate
if (TX_PTP_TS_ENABLE) begin
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
)
tx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(tx_clk),
.output_rst(tx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(tx_ptp_ts_96),
.output_ts_step(),
.output_pps(),
.locked()
);
axis_async_fifo #(
.DEPTH(TX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(TX_PTP_TAG_ENABLE),
.ID_WIDTH(PTP_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo (
.async_rst(logic_rst | tx_rst),
// AXI input
.s_clk(tx_clk),
.s_axis_tdata(tx_axis_ptp_ts_96),
.s_axis_tkeep(0),
.s_axis_tvalid(tx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(tx_axis_ptp_ts_tag),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(logic_clk),
.m_axis_tdata(m_axis_tx_ptp_ts_96),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_tx_ptp_ts_valid),
.m_axis_tready(m_axis_tx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(m_axis_tx_ptp_ts_tag),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
end else begin
assign m_axis_tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_tag = {PTP_TAG_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_valid = 1'b0;
assign tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
end
if (RX_PTP_TS_ENABLE) begin
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
)
rx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(rx_clk),
.output_rst(rx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(rx_ptp_ts_96),
.output_ts_step(),
.output_pps(),
.locked()
);
end else begin
assign rx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
end
endgenerate
eth_mac_phy_10g #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(TX_USER_WIDTH),
.RX_USER_WIDTH(RX_USER_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_mac_phy_10g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tkeep(tx_fifo_axis_tkeep),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tkeep(rx_fifo_axis_tkeep),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.tx_ptp_ts(tx_ptp_ts_96),
.rx_ptp_ts(rx_ptp_ts_96),
.tx_axis_ptp_ts(tx_axis_ptp_ts_96),
.tx_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.tx_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.rx_bad_block(rx_bad_block_int),
.rx_block_lock(rx_block_lock_int),
.rx_high_ber(rx_high_ber_int),
.ifg_delay(ifg_delay),
.tx_prbs31_enable(tx_prbs31_enable),
.rx_prbs31_enable(rx_prbs31_enable)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(DATA_WIDTH),
.M_KEEP_ENABLE(1),
.M_KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(TX_USER_WIDTH),
.PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(tx_fifo_axis_tkeep),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(DATA_WIDTH),
.S_KEEP_ENABLE(1),
.S_KEEP_WIDTH(KEEP_WIDTH),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(RX_USER_WIDTH),
.PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(rx_fifo_axis_tkeep),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule
`resetall
|
// ghrd_10as066n2_hps_m_altera_jtag_avalon_master_171_wqhllki.v
// This file was auto-generated from altera_jtag_avalon_master_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_hps_m_altera_jtag_avalon_master_171_wqhllki #(
parameter USE_PLI = 0,
parameter PLI_PORT = 50000,
parameter FIFO_DEPTHS = 2
) (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (USE_PLI != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_pli_check ( .error(1'b1) );
end
if (PLI_PORT != 50000)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
pli_port_check ( .error(1'b1) );
end
if (FIFO_DEPTHS != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.EXPORT_JTAG (0),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // input, width = 1, clock.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // output, width = 8, src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // output, width = 1, .valid
.sink_data (p2b_out_bytes_stream_data), // input, width = 8, sink.data
.sink_valid (p2b_out_bytes_stream_valid), // input, width = 1, .valid
.sink_ready (p2b_out_bytes_stream_ready), // output, width = 1, .ready
.resetrequest (master_reset_reset), // output, width = 1, resetrequest.reset
.source_ready (1'b1), // (terminated),
.mgmt_valid (), // (terminated),
.mgmt_channel (), // (terminated),
.mgmt_data (), // (terminated),
.jtag_tck (1'b0), // (terminated),
.jtag_tms (1'b0), // (terminated),
.jtag_tdi (1'b0), // (terminated),
.jtag_tdo (), // (terminated),
.jtag_ena (1'b0), // (terminated),
.jtag_usr1 (1'b0), // (terminated),
.jtag_clr (1'b0), // (terminated),
.jtag_clrn (1'b0), // (terminated),
.jtag_state_tlr (1'b0), // (terminated),
.jtag_state_rti (1'b0), // (terminated),
.jtag_state_sdrs (1'b0), // (terminated),
.jtag_state_cdr (1'b0), // (terminated),
.jtag_state_sdr (1'b0), // (terminated),
.jtag_state_e1dr (1'b0), // (terminated),
.jtag_state_pdr (1'b0), // (terminated),
.jtag_state_e2dr (1'b0), // (terminated),
.jtag_state_udr (1'b0), // (terminated),
.jtag_state_sirs (1'b0), // (terminated),
.jtag_state_cir (1'b0), // (terminated),
.jtag_state_sir (1'b0), // (terminated),
.jtag_state_e1ir (1'b0), // (terminated),
.jtag_state_pir (1'b0), // (terminated),
.jtag_state_e2ir (1'b0), // (terminated),
.jtag_state_uir (1'b0), // (terminated),
.jtag_ir_in (3'b000), // (terminated),
.jtag_irq (), // (terminated),
.jtag_ir_out () // (terminated),
);
ghrd_10as066n2_hps_m_timing_adapter_171_xf5weri timing_adt (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // input, width = 8, in.data
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // input, width = 1, .valid
.out_data (timing_adt_out_data), // output, width = 8, out.data
.out_valid (timing_adt_out_valid), // output, width = 1, .valid
.out_ready (timing_adt_out_ready) // input, width = 1, .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // input, width = 1, clk.clk
.reset (rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset
.in_data (timing_adt_out_data), // input, width = 8, in.data
.in_valid (timing_adt_out_valid), // input, width = 1, .valid
.in_ready (timing_adt_out_ready), // output, width = 1, .ready
.out_data (fifo_out_data), // output, width = 8, out.data
.out_valid (fifo_out_valid), // output, width = 1, .valid
.out_ready (fifo_out_ready), // input, width = 1, .ready
.csr_address (2'b00), // (terminated),
.csr_read (1'b0), // (terminated),
.csr_write (1'b0), // (terminated),
.csr_readdata (), // (terminated),
.csr_writedata (32'b00000000000000000000000000000000), // (terminated),
.almost_full_data (), // (terminated),
.almost_empty_data (), // (terminated),
.in_startofpacket (1'b0), // (terminated),
.in_endofpacket (1'b0), // (terminated),
.out_startofpacket (), // (terminated),
.out_endofpacket (), // (terminated),
.in_empty (1'b0), // (terminated),
.out_empty (), // (terminated),
.in_error (1'b0), // (terminated),
.out_error (), // (terminated),
.in_channel (1'b0), // (terminated),
.out_channel () // (terminated),
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // output, width = 8, out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // input, width = 1, .ready
.out_valid (b2p_out_packets_stream_valid), // output, width = 1, .valid
.out_data (b2p_out_packets_stream_data), // output, width = 8, .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // output, width = 1, .endofpacket
.in_ready (fifo_out_ready), // output, width = 1, in_bytes_stream.ready
.in_valid (fifo_out_valid), // input, width = 1, .valid
.in_data (fifo_out_data) // input, width = 8, .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // output, width = 1, in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // input, width = 1, .valid
.in_data (p2b_adapter_out_data), // input, width = 8, .data
.in_channel (p2b_adapter_out_channel), // input, width = 8, .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // input, width = 1, .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // input, width = 1, out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // output, width = 1, .valid
.out_data (p2b_out_bytes_stream_data) // output, width = 8, .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // input, width = 1, out_stream.ready
.out_valid (transacto_out_stream_valid), // output, width = 1, .valid
.out_data (transacto_out_stream_data), // output, width = 8, .data
.out_startofpacket (transacto_out_stream_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // output, width = 1, .endofpacket
.in_ready (b2p_adapter_out_ready), // output, width = 1, in_stream.ready
.in_valid (b2p_adapter_out_valid), // input, width = 1, .valid
.in_data (b2p_adapter_out_data), // input, width = 8, .data
.in_startofpacket (b2p_adapter_out_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // input, width = 1, .endofpacket
.address (master_address), // output, width = 32, avalon_master.address
.readdata (master_readdata), // input, width = 32, .readdata
.read (master_read), // output, width = 1, .read
.write (master_write), // output, width = 1, .write
.writedata (master_writedata), // output, width = 32, .writedata
.waitrequest (master_waitrequest), // input, width = 1, .waitrequest
.readdatavalid (master_readdatavalid), // input, width = 1, .readdatavalid
.byteenable (master_byteenable) // output, width = 4, .byteenable
);
ghrd_10as066n2_hps_m_channel_adapter_171_2swajja b2p_adapter (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
.in_data (b2p_out_packets_stream_data), // input, width = 8, in.data
.in_valid (b2p_out_packets_stream_valid), // input, width = 1, .valid
.in_ready (b2p_out_packets_stream_ready), // output, width = 1, .ready
.in_startofpacket (b2p_out_packets_stream_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // input, width = 1, .endofpacket
.in_channel (b2p_out_packets_stream_channel), // input, width = 8, .channel
.out_data (b2p_adapter_out_data), // output, width = 8, out.data
.out_valid (b2p_adapter_out_valid), // output, width = 1, .valid
.out_ready (b2p_adapter_out_ready), // input, width = 1, .ready
.out_startofpacket (b2p_adapter_out_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // output, width = 1, .endofpacket
);
ghrd_10as066n2_hps_m_channel_adapter_171_vh2yu6y p2b_adapter (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
.in_data (transacto_out_stream_data), // input, width = 8, in.data
.in_valid (transacto_out_stream_valid), // input, width = 1, .valid
.in_ready (transacto_out_stream_ready), // output, width = 1, .ready
.in_startofpacket (transacto_out_stream_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // input, width = 1, .endofpacket
.out_data (p2b_adapter_out_data), // output, width = 8, out.data
.out_valid (p2b_adapter_out_valid), // output, width = 1, .valid
.out_ready (p2b_adapter_out_ready), // input, width = 1, .ready
.out_startofpacket (p2b_adapter_out_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // output, width = 1, .endofpacket
.out_channel (p2b_adapter_out_channel) // output, width = 8, .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // input, width = 1, reset_in0.reset
.clk (clk_clk), // input, width = 1, clk.clk
.reset_out (rst_controller_reset_out_reset), // output, width = 1, reset_out.reset
.reset_req (), // (terminated),
.reset_req_in0 (1'b0), // (terminated),
.reset_in1 (1'b0), // (terminated),
.reset_req_in1 (1'b0), // (terminated),
.reset_in2 (1'b0), // (terminated),
.reset_req_in2 (1'b0), // (terminated),
.reset_in3 (1'b0), // (terminated),
.reset_req_in3 (1'b0), // (terminated),
.reset_in4 (1'b0), // (terminated),
.reset_req_in4 (1'b0), // (terminated),
.reset_in5 (1'b0), // (terminated),
.reset_req_in5 (1'b0), // (terminated),
.reset_in6 (1'b0), // (terminated),
.reset_req_in6 (1'b0), // (terminated),
.reset_in7 (1'b0), // (terminated),
.reset_req_in7 (1'b0), // (terminated),
.reset_in8 (1'b0), // (terminated),
.reset_req_in8 (1'b0), // (terminated),
.reset_in9 (1'b0), // (terminated),
.reset_req_in9 (1'b0), // (terminated),
.reset_in10 (1'b0), // (terminated),
.reset_req_in10 (1'b0), // (terminated),
.reset_in11 (1'b0), // (terminated),
.reset_req_in11 (1'b0), // (terminated),
.reset_in12 (1'b0), // (terminated),
.reset_req_in12 (1'b0), // (terminated),
.reset_in13 (1'b0), // (terminated),
.reset_req_in13 (1'b0), // (terminated),
.reset_in14 (1'b0), // (terminated),
.reset_req_in14 (1'b0), // (terminated),
.reset_in15 (1'b0), // (terminated),
.reset_req_in15 (1'b0) // (terminated),
);
endmodule
|
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_AVMM_DATA_CONTROLLER (PARALLEL-to-PARALLEL MODE)
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_avmm_data_controller (
// To/From System
clock,
reset_n,
// To/From Flash IP interface
flash_busy,
flash_se_pass,
flash_sp_pass,
flash_osc,
flash_drdout,
flash_xe_ye,
flash_se,
flash_arclk,
flash_arshft,
flash_drclk,
flash_drshft,
flash_drdin,
flash_nprogram,
flash_nerase,
flash_ardin,
// To/From Avalon_MM data slave interface
avmm_read,
avmm_write,
avmm_addr,
avmm_writedata,
avmm_burstcount,
avmm_waitrequest,
avmm_readdatavalid,
avmm_readdata,
// To/From Avalon_MM csr slave interface
csr_control,
csr_status
);
parameter READ_AND_WRITE_MODE = 0;
parameter WRAPPING_BURST_MODE = 0;
parameter DATA_WIDTH = 32;
parameter AVMM_DATA_ADDR_WIDTH = 20;
parameter AVMM_DATA_BURSTCOUNT_WIDTH = 4;
parameter FLASH_ADDR_WIDTH = 23;
parameter FLASH_SEQ_READ_DATA_COUNT = 2; //number of 32-bit data per sequential read
parameter FLASH_READ_CYCLE_MAX_INDEX = 3; //period to for each sequential read
parameter FLASH_ADDR_ALIGNMENT_BITS = 1; //number of last addr bits for alignment
parameter FLASH_RESET_CYCLE_MAX_INDEX = 28; //period that required by flash before back to idle for erase and program operation
parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (1200ns)
parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE2_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
parameter ADDR_RANGE3_OFFSET = 1;
localparam [1:0] ERASE_ST_IDLE = 0,
ERASE_ST_PENDING = 1,
ERASE_ST_BUSY = 2;
localparam [1:0] STATUS_IDLE = 0,
STATUS_BUSY_ERASE = 1,
STATUS_BUSY_WRITE = 2,
STATUS_BUSY_READ = 3;
localparam [2:0] WRITE_STATE_IDLE = 0,
WRITE_STATE_ADDR = 1,
WRITE_STATE_WRITE = 2,
WRITE_STATE_WAIT_BUSY = 3,
WRITE_STATE_WAIT_DONE = 4,
WRITE_STATE_RESET = 5,
WRITE_STATE_ERROR = 6;
localparam [2:0] ERASE_STATE_IDLE = 0,
ERASE_STATE_ADDR = 1,
ERASE_STATE_WAIT_BUSY = 2,
ERASE_STATE_WAIT_DONE = 3,
ERASE_STATE_RESET = 4,
ERASE_STATE_ERROR = 5;
localparam [2:0] READ_STATE_IDLE = 0,
READ_STATE_ADDR = 1,
READ_STATE_READ = 2,
READ_STATE_SETUP = 2,
READ_STATE_DUMMY = 3,
READ_STATE_READY = 4,
READ_STATE_FINAL = 5,
READ_STATE_CLEAR = 6,
READ_STATE_PULSE_SE = 7;
localparam [0:0] READ_SETUP = 0,
READ_RECV_DATA = 1;
localparam [1:0] READ_VALID_IDLE = 0,
READ_VALID_READING = 1,
READ_VALID_PRE_READING = 2;
// To/From System
input clock;
input reset_n;
// To/From Flash IP interface
input flash_busy;
input flash_se_pass;
input flash_sp_pass;
input flash_osc;
input [DATA_WIDTH-1:0] flash_drdout;
output flash_xe_ye;
output flash_se;
output flash_arclk;
output flash_arshft;
output flash_drclk;
output flash_drshft;
output flash_drdin;
output flash_nprogram;
output flash_nerase;
output [FLASH_ADDR_WIDTH-1:0] flash_ardin;
// To/From Avalon_MM data slave interface
input avmm_read;
input avmm_write;
input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_addr;
input [DATA_WIDTH-1:0] avmm_writedata;
input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount;
output avmm_waitrequest;
output avmm_readdatavalid;
output reg [DATA_WIDTH-1:0] avmm_readdata;
// To/From Avalon_MM csr slave interface
input [31:0] csr_control;
output [9:0] csr_status;
reg reset_n_reg1;
reg reset_n_reg2;
reg [1:0] csr_status_busy;
reg csr_status_e_pass;
reg csr_status_w_pass;
reg csr_status_r_pass;
reg [2:0] erase_state;
reg [2:0] write_state;
reg [2:0] read_state;
reg avmm_read_state;
reg [1:0] avmm_read_valid_state;
reg avmm_readdatavalid_reg;
reg avmm_readdata_ready;
reg [2:0] flash_sector_addr;
reg [FLASH_ADDR_WIDTH-1:0] flash_page_addr;
reg [FLASH_ADDR_WIDTH-1:0] flash_seq_read_ardin;
reg [FLASH_ADDR_WIDTH-1:0] flash_addr_wire_neg_reg;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_reg;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_backup_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_input_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_reg;
reg write_drclk_en;
reg read_drclk_en;
reg enable_arclk_sync_reg;
reg enable_arclk_neg_reg;
reg enable_arclk_neg_pos_reg;
reg enable_drclk_neg_reg;
reg enable_drclk_neg_pos_reg;
reg enable_drclk_neg_pos_write_reg;
reg flash_drdin_neg_reg;
reg [15:0] write_count;
reg [25:0] erase_count;
reg [2:0] read_count;
reg [2:0] read_ctrl_count;
reg [2:0] data_count;
reg write_timeout;
reg write_wait;
reg write_wait_neg;
reg erase_timeout;
reg read_wait;
reg read_wait_neg;
reg flash_drshft_reg;
reg flash_drshft_neg_reg;
reg flash_se_neg_reg;
reg flash_se_pass_reg;
reg flash_sp_pass_reg;
reg flash_busy_reg;
reg flash_busy_clear_reg;
reg erase_busy_scan;
reg write_busy_scan;
reg is_sector1_writable_reg;
reg is_sector2_writable_reg;
reg is_sector3_writable_reg;
reg is_sector4_writable_reg;
reg is_sector5_writable_reg;
wire reset_n_w;
wire is_addr_within_valid_range;
wire is_addr_writable;
wire is_sector_writable;
wire is_erase_addr_writable;
wire [2:0] cur_e_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_a_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] flash_addr_wire;
wire [FLASH_ADDR_WIDTH-1:0] flash_page_addr_wire;
wire [2:0] flash_sector_wire;
wire is_valid_write_burst_count;
wire is_erase_busy;
wire is_write_busy;
wire is_read_busy;
wire [FLASH_ADDR_WIDTH-1:0] flash_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] next_flash_read_ardin;
wire [19:0] csr_page_erase_addr;
wire [2:0] csr_sector_erase_addr;
wire valid_csr_sector_erase_addr;
wire [1:0] csr_erase_state;
wire [4:0] csr_write_protection_mode;
wire valid_csr_erase;
wire valid_command;
wire flash_drdin_w;
wire flash_arclk_arshft_en_w;
wire flash_se_w;
wire is_busy;
wire write_wait_w;
wire read_wait_w;
wire flash_busy_sync;
wire flash_busy_clear_sync;
generate // generate combi based on read and write mode
if (READ_AND_WRITE_MODE == 1) begin
assign is_erase_busy = (erase_state != ERASE_STATE_IDLE);
assign is_write_busy = (write_state != WRITE_STATE_IDLE);
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_erase_busy || is_write_busy || is_read_busy;
assign flash_drdin = flash_drdin_neg_reg;
assign write_wait_w = (write_wait || write_wait_neg);
assign is_erase_addr_writable =
(valid_csr_erase && valid_csr_sector_erase_addr) ? is_sector_writable : is_addr_writable;
assign csr_write_protection_mode = csr_control[27:23];
assign is_valid_write_burst_count = (avmm_burstcount == 1);
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_addr_wire_neg_reg <= 0;
end
else if (valid_csr_erase && valid_csr_sector_erase_addr) begin
flash_addr_wire_neg_reg <= { flash_sector_addr, 1'b0, {(19){1'b1}}};
end
else begin
flash_addr_wire_neg_reg <= flash_page_addr;
end
end
end
else begin
assign is_erase_busy = 1'b0;
assign is_write_busy = 1'b0;
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_read_busy;
assign flash_drdin = 1'b1;
assign write_wait_w = 1'b0;
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_addr_wire_neg_reg <= 0;
end
else begin
flash_addr_wire_neg_reg <= flash_page_addr;
end
end
end
endgenerate
assign csr_status = { SECTOR_READ_PROTECTION_MODE[4:0], csr_status_e_pass, csr_status_w_pass, csr_status_r_pass, csr_status_busy};
assign csr_page_erase_addr = csr_control[19:0];
assign csr_sector_erase_addr = csr_control[22:20];
assign csr_erase_state = csr_control[31:30];
assign valid_csr_sector_erase_addr = (csr_sector_erase_addr != {(3){1'b1}});
assign valid_csr_erase = (csr_erase_state == ERASE_ST_PENDING);
assign valid_command = (valid_csr_erase == 1) || (avmm_write == 1);
assign cur_read_addr = avmm_addr;
assign read_wait_w = (read_wait || read_wait_neg);
generate // generate combi based on read burst mode
if (WRAPPING_BURST_MODE == 0) begin
// incrementing read
assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
assign cur_e_addr = csr_sector_erase_addr;
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : flash_read_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (is_read_busy && (read_state == READ_STATE_FINAL || read_state == READ_STATE_ADDR));
assign flash_se_w = (read_state == READ_STATE_SETUP);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
assign next_flash_read_ardin = {flash_seq_read_ardin[FLASH_ADDR_WIDTH-1:FLASH_ADDR_ALIGNMENT_BITS], {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}}} + FLASH_SEQ_READ_DATA_COUNT[22:0];
end
else begin
// wrapping read
assign cur_e_addr = csr_sector_erase_addr;
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : avmm_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (read_wait && read_ctrl_count <= 1 && avmm_read);
assign flash_se_w = (read_state == READ_STATE_READ && read_ctrl_count==FLASH_READ_CYCLE_MAX_INDEX+1);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
end
endgenerate
assign flash_arshft = 1'b1;
assign flash_drshft = flash_drshft_neg_reg;
assign flash_arclk = (~enable_arclk_neg_reg || clock || enable_arclk_neg_pos_reg);
assign flash_drclk = (~enable_drclk_neg_reg || clock || enable_drclk_neg_pos_reg || enable_drclk_neg_pos_write_reg);
assign flash_nerase = ~(erase_state == ERASE_STATE_WAIT_BUSY || erase_state == ERASE_STATE_WAIT_DONE);
assign flash_nprogram = ~(write_state == WRITE_STATE_WAIT_BUSY || write_state == WRITE_STATE_WAIT_DONE);
assign flash_xe_ye = ((~is_busy && avmm_read) || is_read_busy);
assign flash_se = flash_se_neg_reg;
assign flash_ardin = flash_addr_wire_neg_reg;
assign avmm_readdatavalid = avmm_readdatavalid_reg;
always @(posedge clock) begin
if (~reset_n_w | ~csr_status_r_pass) begin
avmm_readdata <= 32'hffffffff;
end
else begin
avmm_readdata <= flash_drdout;
end
end
// avoid async reset removal issue
assign reset_n_w = reset_n_reg2;
// initial register
initial begin
csr_status_busy = STATUS_IDLE;
csr_status_e_pass = 0;
csr_status_w_pass = 0;
csr_status_r_pass = 0;
avmm_burstcount_input_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
avmm_burstcount_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
erase_state = ERASE_STATE_IDLE;
write_state = WRITE_STATE_IDLE;
read_state = READ_STATE_IDLE;
avmm_read_state = READ_SETUP;
avmm_read_valid_state = READ_VALID_IDLE;
avmm_readdatavalid_reg = 0;
avmm_readdata_ready = 0;
flash_sector_addr = 0;
flash_page_addr = 0;
flash_ardin_align_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
flash_ardin_align_backup_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
write_drclk_en = 0;
read_drclk_en = 0;
flash_drshft_reg = 1;
flash_drshft_neg_reg = 1;
flash_busy_reg = 0;
flash_busy_clear_reg = 0;
flash_se_neg_reg = 0;
flash_se_pass_reg = 0;
flash_sp_pass_reg = 0;
erase_busy_scan = 0;
write_busy_scan = 0;
flash_seq_read_ardin = 0;
enable_arclk_neg_reg = 0;
enable_arclk_neg_pos_reg = 0;
enable_drclk_neg_reg = 0;
enable_drclk_neg_pos_reg = 0;
enable_drclk_neg_pos_write_reg = 0;
flash_drdin_neg_reg = 0;
write_count = 0;
erase_count = 0;
read_ctrl_count = 0;
data_count = 0;
write_timeout = 0;
erase_timeout = 0;
write_wait = 0;
write_wait_neg = 0;
reset_n_reg1 = 0;
reset_n_reg2 = 0;
read_wait = 0;
read_wait_neg = 0;
read_count = 0;
is_sector1_writable_reg = 0;
is_sector2_writable_reg = 0;
is_sector3_writable_reg = 0;
is_sector4_writable_reg = 0;
is_sector5_writable_reg = 0;
end
// -------------------------------------------------------------------
// Avoid async reset removal issue
// -------------------------------------------------------------------
always @ (negedge reset_n or posedge clock) begin
if (~reset_n) begin
{reset_n_reg2, reset_n_reg1} <= 2'b0;
end
else begin
{reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
end
end
// -------------------------------------------------------------------
// Sync combinational output before feeding into flash
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_sync_reg <= 0;
end
else begin
enable_arclk_sync_reg <= flash_arclk_arshft_en_w;
end
end
// -------------------------------------------------------------------
// Get rid of the race condition between different dynamic clock. Trigger clock enable in early half cycle.
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_reg <= 0;
enable_drclk_neg_reg <= 0;
flash_drshft_neg_reg <= 1;
flash_se_neg_reg <= 0;
write_wait_neg <= 0;
read_wait_neg <= 0;
end
else begin
enable_arclk_neg_reg <= enable_arclk_sync_reg;
enable_drclk_neg_reg <= (write_drclk_en || read_drclk_en);
flash_drshft_neg_reg <= flash_drshft_reg;
flash_se_neg_reg <= flash_se_w;
write_wait_neg <= write_wait;
read_wait_neg <= read_wait;
end
end
// -------------------------------------------------------------------
// Get rid of glitch for pos clock
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_pos_reg <= 0;
end
else begin
enable_arclk_neg_pos_reg <= enable_arclk_neg_reg;
end
end
// -------------------------------------------------------------------
// Pine line page address path
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_page_addr <= 0;
end
else begin
flash_page_addr <= flash_page_addr_wire;
end
end
generate // generate always block based on read and write mode. Write and erase operation is unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Pine line sector address path
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_sector_addr <= 0;
end
else begin
flash_sector_addr <= flash_sector_wire;
end
end
// -------------------------------------------------------------------
// Minitor flash pass signal and update CSR busy status
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_se_pass_reg <= 0;
flash_sp_pass_reg <= 0;
csr_status_busy <= STATUS_IDLE;
end
else begin
flash_se_pass_reg <= flash_se_pass;
flash_sp_pass_reg <= flash_sp_pass;
if (is_erase_busy) begin
csr_status_busy <= STATUS_BUSY_ERASE;
end
else if (is_write_busy) begin
csr_status_busy <= STATUS_BUSY_WRITE;
end
else if (is_read_busy) begin
csr_status_busy <= STATUS_BUSY_READ;
end
else begin
csr_status_busy <= STATUS_IDLE;
end
end
end
// -------------------------------------------------------------------
// Monitor and store flash busy signal, it may faster then the clock
// -------------------------------------------------------------------
wire busy_scan;
assign busy_scan = (erase_busy_scan || write_busy_scan);
always @ (negedge reset_n or negedge busy_scan or posedge flash_osc) begin
if (~reset_n || ~busy_scan) begin
flash_busy_reg <= 0;
flash_busy_clear_reg <= 0;
end
else if (flash_busy_reg) begin
flash_busy_reg <= flash_busy_reg;
flash_busy_clear_reg <= ~flash_busy;
end
else begin
flash_busy_reg <= flash_busy;
flash_busy_clear_reg <= 0;
end
end
altera_std_synchronizer #(
.depth (2)
) stdsync_busy (
.clk(clock), // clock
.din(flash_busy_reg), // busy signal
.dout(flash_busy_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
altera_std_synchronizer #(
.depth (2)
) stdsync_busy_clear (
.clk(clock), // clock
.din(flash_busy_clear_reg), // busy signal
.dout(flash_busy_clear_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
// -------------------------------------------------------------------
// Get rid of the race condition of shftreg signal (drdin), add half cycle delay to the data
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_drdin_neg_reg <= 1;
end
else begin
flash_drdin_neg_reg <= flash_drdin_w;
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Write Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
write_state <= WRITE_STATE_IDLE;
write_wait <= 0;
end
else begin
case (write_state)
WRITE_STATE_IDLE: begin
// reset all register
write_count <= 0;
write_timeout <= 1'b0;
write_busy_scan <= 1'b0;
enable_drclk_neg_pos_write_reg <= 0;
// check command
if (avmm_write) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_read_busy) begin
write_state <= WRITE_STATE_ADDR;
write_wait <= 1;
end
end
end
WRITE_STATE_ADDR: begin
if (is_addr_writable && is_valid_write_burst_count) begin
write_count <= DATA_WIDTH[5:0];
write_state <= WRITE_STATE_WRITE;
end
else begin
write_wait <= 0;
write_count <= 2;
write_state <= WRITE_STATE_ERROR;
end
end
WRITE_STATE_WRITE: begin
if (write_count != 0) begin
write_drclk_en <= 1;
write_count <= write_count - 16'd1;
end
else begin
enable_drclk_neg_pos_write_reg <= 1;
write_drclk_en <= 0;
write_busy_scan <= 1'b1;
write_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_BUSY;
end
end
WRITE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
write_count <= FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_DONE;
end
else begin
if (write_count != 0)
write_count <= write_count - 16'd1;
else begin
write_timeout <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
else begin
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_timeout <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_RESET: begin
write_busy_scan <= 1'b0;
if (write_timeout) begin
csr_status_w_pass <= 1'b0;
end
else begin
csr_status_w_pass <= flash_sp_pass_reg;
end
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
WRITE_STATE_ERROR: begin
csr_status_w_pass <= 1'b0;
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
default: begin
write_state <= WRITE_STATE_IDLE;
end
endcase
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Erase Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
erase_state <= ERASE_STATE_IDLE;
end
else begin
case (erase_state)
ERASE_STATE_IDLE: begin
// reset all register
erase_count <= 0;
erase_timeout <= 1'b0;
erase_busy_scan <= 1'b0;
// check command
if (valid_csr_erase && ~is_write_busy && ~is_read_busy) begin
erase_state <= ERASE_STATE_ADDR;
end
end
ERASE_STATE_ADDR: begin
if (is_erase_addr_writable) begin
erase_busy_scan <= 1'b1;
erase_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_BUSY;
end
else begin
erase_count <= 2;
erase_state <= ERASE_STATE_ERROR;
end
end
ERASE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
erase_count <= FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_DONE;
end
else begin
if (erase_count != 0)
erase_count <= erase_count - 26'd1;
else begin
erase_timeout <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
else begin
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_timeout <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_RESET: begin
erase_busy_scan <= 1'b0;
if (erase_timeout) begin
csr_status_e_pass <= 1'b0;
end
else begin
csr_status_e_pass <= flash_se_pass_reg;
end
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
ERASE_STATE_ERROR: begin
csr_status_e_pass <= 1'b0;
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
default: begin
erase_state <= ERASE_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate always block for read operation based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Increamenting Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_read_state <= READ_SETUP;
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
avmm_burstcount_input_reg <= 0;
enable_drclk_neg_pos_reg <= 0;
read_drclk_en <= 0;
flash_drshft_reg <= 1;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
read_state <= READ_STATE_ADDR;
flash_seq_read_ardin <= avmm_addr;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
READ_STATE_ADDR: begin
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_wait <= 0;
read_state <= READ_STATE_PULSE_SE;
end
READ_STATE_PULSE_SE: begin
read_wait <= 1;
read_state <= READ_STATE_SETUP;
end
// incrementing read
READ_STATE_SETUP: begin
if (next_flash_read_ardin > MAX_VALID_ADDR) begin
flash_seq_read_ardin <= MIN_VALID_ADDR[FLASH_ADDR_WIDTH-1:0];
end
else begin
flash_seq_read_ardin <= next_flash_read_ardin;
end
flash_ardin_align_reg <= flash_seq_read_ardin[FLASH_ADDR_ALIGNMENT_BITS-1:0];
if (FLASH_READ_CYCLE_MAX_INDEX[2:0] > 2) begin
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] - 3'd2;
read_state <= READ_STATE_DUMMY;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_DUMMY: begin
if (read_ctrl_count > 1) begin
read_ctrl_count <= read_ctrl_count - 3'd1;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_READY: begin
if (avmm_read_state == READ_SETUP) begin
avmm_readdata_ready <= 1;
end
read_drclk_en <= 1;
flash_drshft_reg <= 0;
read_state <= READ_STATE_FINAL;
end
READ_STATE_FINAL: begin
flash_drshft_reg <= 1;
avmm_readdata_ready <= 0;
avmm_read_state <= READ_RECV_DATA;
if ((avmm_read_state == READ_RECV_DATA) && (avmm_burstcount_reg == 0)) begin
read_state <= READ_STATE_CLEAR;
read_drclk_en <= 0;
enable_drclk_neg_pos_reg <= 1;
end
else begin
read_state <= READ_STATE_PULSE_SE;
end
end
// Dummy state to clear arclk glitch
READ_STATE_CLEAR: begin
read_wait <= 0;
read_state <= READ_STATE_IDLE;
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Wrapping Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
enable_drclk_neg_pos_reg <= 0;
flash_drshft_reg <= 1;
read_drclk_en <= 0;
avmm_burstcount_input_reg <= 0;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
read_state <= READ_STATE_ADDR;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
READ_STATE_ADDR: begin
read_wait <= 0;
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_state <= READ_STATE_PULSE_SE;
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] + 3'd1;
end
READ_STATE_PULSE_SE: begin
read_wait <= 1;
read_state <= READ_STATE_READ;
end
// wrapping read
READ_STATE_READ: begin
// read control signal
if (read_ctrl_count > 0) begin
read_ctrl_count <= read_ctrl_count - 3'd1;
end
if (read_ctrl_count == 2) begin
avmm_readdata_ready <= 1;
read_drclk_en <= 1;
flash_drshft_reg <= 0;
end
else begin
flash_drshft_reg <= 1;
end
if (avmm_read && ~read_wait) begin
read_wait <= 1;
end
if (avmm_readdata_ready || read_ctrl_count == 0) begin
avmm_readdata_ready <= 0;
if (avmm_read) begin
avmm_burstcount_input_reg <= avmm_burstcount;
read_state <= READ_STATE_ADDR;
end
end
// read data signal
if (read_count > 0) begin
read_count <= read_count - 3'd1;
end
else begin
if (avmm_readdata_ready) begin
read_count <= FLASH_SEQ_READ_DATA_COUNT[2:0] - 3'd1;
end
end
// back to idle if both control and read cycle are finished
if (read_ctrl_count == 0 && read_count == 0 && ~avmm_read) begin
read_state <= READ_STATE_IDLE;
read_drclk_en <= 0;
read_wait <= 0;
enable_drclk_neg_pos_reg <= 1;
end
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate readdatavalid control signal always block based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Control readdatavalid signal - incrementing read
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
if (avmm_readdata_ready) begin
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_read_valid_state <= READ_VALID_PRE_READING;
avmm_burstcount_reg <= avmm_burstcount_input_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
flash_ardin_align_backup_reg <= flash_ardin_align_reg;
end
end
READ_VALID_PRE_READING: begin
avmm_readdatavalid_reg <= 1;
avmm_read_valid_state <= READ_VALID_READING;
end
READ_VALID_READING: begin
if (avmm_burstcount_reg == 0) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
if (data_count > 0) begin
if ((FLASH_READ_CYCLE_MAX_INDEX - data_count + 1 + flash_ardin_align_backup_reg) < FLASH_SEQ_READ_DATA_COUNT) begin
avmm_readdatavalid_reg <= 1;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
end
else begin
avmm_readdatavalid_reg <= 0;
end
data_count <= data_count - 3'd1;
end
else begin
flash_ardin_align_backup_reg <= 0;
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_read_valid_state <= READ_VALID_PRE_READING;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Control readdatavalid signal - wrapping read with fixed burst count
// Burst count
// 1~2 - ZB8
// 1~4 - all other devices
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
data_count <= 0;
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3'd1;
avmm_read_valid_state <= READ_VALID_PRE_READING;
end
end
READ_VALID_PRE_READING: begin
avmm_readdatavalid_reg <= 1;
avmm_read_valid_state <= READ_VALID_READING;
end
READ_VALID_READING: begin
if (data_count > 0) begin
data_count <= data_count - 3'd1;
end
else begin
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3'd1;
end
else begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate shiftreg based on read and write mode. Unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Instantiate a shift register to send the data to UFM serially (load parallel)
// -------------------------------------------------------------------
lpm_shiftreg # (
.lpm_type ("LPM_SHIFTREG"),
.lpm_width (DATA_WIDTH),
.lpm_direction ("LEFT")
) ufm_data_shiftreg (
.data(avmm_writedata),
.clock(clock),
.enable(write_state == WRITE_STATE_WRITE),
.load(write_count == DATA_WIDTH),
.shiftout(flash_drdin_w),
.aclr(write_state == WRITE_STATE_IDLE)
);
end
endgenerate
altera_onchip_flash_address_range_check # (
.MIN_VALID_ADDR(MIN_VALID_ADDR),
.MAX_VALID_ADDR(MAX_VALID_ADDR)
) address_range_checker (
.address(cur_read_addr),
.is_addr_within_valid_range(is_addr_within_valid_range)
);
altera_onchip_flash_convert_address # (
.ADDR_RANGE1_END_ADDR(ADDR_RANGE1_END_ADDR),
.ADDR_RANGE2_END_ADDR(ADDR_RANGE2_END_ADDR),
.ADDR_RANGE1_OFFSET(ADDR_RANGE1_OFFSET),
.ADDR_RANGE2_OFFSET(ADDR_RANGE2_OFFSET),
.ADDR_RANGE3_OFFSET(ADDR_RANGE3_OFFSET)
) address_convertor (
.address(cur_a_addr),
.flash_addr(flash_page_addr_wire)
);
generate // sector address convertsion is unnecessary in read only mode
if (READ_AND_WRITE_MODE == 1) begin
// pipe line addr legality check logic
always @ (posedge clock) begin
if (~reset_n_w) begin
is_sector1_writable_reg <= 1'b0;
is_sector2_writable_reg <= 1'b0;
is_sector3_writable_reg <= 1'b0;
is_sector4_writable_reg <= 1'b0;
is_sector5_writable_reg <= 1'b0;
end
else begin
is_sector1_writable_reg <= ~(csr_write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
is_sector2_writable_reg <= ~(csr_write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
is_sector3_writable_reg <= ~(csr_write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
is_sector4_writable_reg <= ~(csr_write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
is_sector5_writable_reg <= ~(csr_write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
end
end
altera_onchip_flash_a_address_write_protection_check # (
.SECTOR1_START_ADDR(SECTOR1_START_ADDR),
.SECTOR1_END_ADDR(SECTOR1_END_ADDR),
.SECTOR2_START_ADDR(SECTOR2_START_ADDR),
.SECTOR2_END_ADDR(SECTOR2_END_ADDR),
.SECTOR3_START_ADDR(SECTOR3_START_ADDR),
.SECTOR3_END_ADDR(SECTOR3_END_ADDR),
.SECTOR4_START_ADDR(SECTOR4_START_ADDR),
.SECTOR4_END_ADDR(SECTOR4_END_ADDR),
.SECTOR5_START_ADDR(SECTOR5_START_ADDR),
.SECTOR5_END_ADDR(SECTOR5_END_ADDR)
) access_address_write_protection_checker (
.address(cur_a_addr),
.is_sector1_writable(is_sector1_writable_reg),
.is_sector2_writable(is_sector2_writable_reg),
.is_sector3_writable(is_sector3_writable_reg),
.is_sector4_writable(is_sector4_writable_reg),
.is_sector5_writable(is_sector5_writable_reg),
.is_addr_writable(is_addr_writable)
);
altera_onchip_flash_s_address_write_protection_check sector_address_write_protection_checker (
.address(cur_e_addr[2:0]),
.is_sector1_writable(is_sector1_writable_reg),
.is_sector2_writable(is_sector2_writable_reg),
.is_sector3_writable(is_sector3_writable_reg),
.is_sector4_writable(is_sector4_writable_reg),
.is_sector5_writable(is_sector5_writable_reg),
.is_addr_writable(is_sector_writable)
);
altera_onchip_flash_convert_sector # (
.SECTOR1_MAP(SECTOR1_MAP),
.SECTOR2_MAP(SECTOR2_MAP),
.SECTOR3_MAP(SECTOR3_MAP),
.SECTOR4_MAP(SECTOR4_MAP),
.SECTOR5_MAP(SECTOR5_MAP)
) sector_convertor (
.sector(cur_e_addr[2:0]),
.flash_sector(flash_sector_wire)
);
end
endgenerate
endmodule
|
// MBT 8-27-14
//
// This is the "whole enchilada" for full-duplex DDR calibrated
// communication over multiple source-synchronous channels :
//
// - bsg_assembler_in
// - bsg_assembler_out
// - source_synchronous_in
// - source_synchronous_out
// - bsg_source_sync_channel_control_slave
// - bsg_source_sync_channel_control_master
// - bsg_source_sync_channel_control_master_master
//
// ** CLOCKS
//
// There are many clocks in this module, and synchronizer
// conventions must be obeyed when mixing signals in
// different domains. Moreover, they need to be generated
// as clocks in physical design.
//
// We use the following conventions for signals:
//
// core_ : synchronous to core clock domain
// im_ : synchronous to the io_master_clk (for output channels)
// io_ [link_channels_p] : synchronous to one of N input channel clocks,
// each potentially with a different freq/phase
// token_ [link_channels_p] : synchronous to one of N incoming token clocks
//
// signals in the core clock domain begin with core_
// signals in the channel's clock domains begin with channel_
//
//
// ** RESETS
//
// All resets in this module are synchronous.
// Care has been made to synchronize all of the resets.
// See notes below for token reset.
/*
Reset is the hardest part about this module.
Here is the reset timeline:
FPGA:
async_reset 0'd for 16 [C0,C1,M0,M1] cycles. <test_bsg_comm_link>
async_reset 1'd for 256 [C0,C1,M0,M1] cycles. <test_bsg_comm_link>
async_reset 0'd
bsg_comm_link:
async_reset --> CO CO -> core_reset (C0)
async_reset --> M0 M0 -> im_reset (MO)
MO:
im_start_calibration_n goes high
master_lg_wait_after_reset_p M0 cycles after im_reset goes lo <bsg_comm_link>,
causing start_i is asserted on master_master.
1 M0 cycle later, prepare_o goes high in master_master
-> im_channel_reset -> token_reset
(prepare_o goes low after master_calib_prepare_cycles_p)
1 M0 cycle later
a. im_slave_reset_tline_r_o goes high ----> ASIC async_reset_i (slave)
b. out_ctr_r in master starts at zero
2^master_lg_token_width_p cycles later, token act goes high (QQ)
2^master_lg_token_width_p cycles later, token act goes lo (ZZ)
im_channel_reset -> {M0,I0n,IOn} -> io_reset (I0n) --> token_bypass (BB)
IOn:
ASIC:
ASIC async_reset_i {C1,C1}'d --> core_reset (C1)
ASIC async_reset_i {M1,M1}'d --> im_reset (M1)
= token_reset = im_channel_reset
async_reset_i {In,In}'d --> io_reset (I1n)= token_bypass
M1:
1 M1 cycle later
slave enters sBegin state
out_ctr_r is zeroed
(2^slave_lg_token_width_p) M1 cycles later, token bit goes high. (XX)
(2^slave_lg_token_width_p) M1 cycles later, token bit goes low. (YY)
I1n:
1 In cycle later, token_bypass is enabled (QQ)
C1:
A few cycles later, the fifos in the core are reset.
Race condition tests:
(BB) master token bypass must go high after ASIC token_reset
when prepare signal goes high:
master: prepare->M0->ASIC reset_hi->M1->M1->token_reset
prepare->M0->I0n->I0n->token_bypass
since IOn = M1/2 (DDR); we know we are always safe.
(QQ) token_bypass must enabled before token bit goes hi from FPGA
if we do not do this, we could fail to properly reset
the token signal.
--> Since I1n = 2 M0, this case is easy; basically around 6 M0
i.e. 2^master_lg_token_width_p > 6. A bigger constraint
is we want to slow things down by the token decimation factor.
:: simple solution; make sure master_lg_token_width_p >= 5
(ZZ) token act must have time to go hi and then lo before token_bypass goes low
before async_reset_i goes low. This means lg_token_width_p is too
long relative to prepare_cycles.
:: Make sure prepare_cycles >> 2**(master_lg_token_width_p+1)
(XX) ASIC token_activation must go high after FPGA token_reset hi
--> currently token_reset goes high before ASIC_reset is even asserted
so this is always satisfied.
:: keep slave_lg_token_width_p = 5 (or at least the decimation factor)
(YY) ASIC token_activation must complete before FPGA token_reset goes lo
--> master_calib_prepare_cycles_p x M0 > (3+2^slave_lg_token_width_p) x M1
--> master_calib_prepare_cycles_p > (3+2^slave_lg_token_width_p) x (M1 / M0)
(SS) prepare_hold_cycles. we need to make sure that somehow the changed data
does not get to wherever before the reset gets to where it needs to go.
going out of the FPGA, these should be pretty evenly matched in M0 cycles.
the reset has to go through two M1 latches that the data does not have to.
so, to be safe 10 + 5*(M1/M0) should be more than adequate.
(CC) prepare_hold_cycles. we need to make sure that enough cycles have passed
for the core to reset so that the inputs to the source synchronous
channels are valid.
--> master_calib_prepare_cycles > ~5 * C1/M0
*/
`include "bsg_defines.v"
module bsg_comm_link
#(parameter `BSG_INV_PARAM(channel_width_p )
, parameter `BSG_INV_PARAM(core_channels_p )
, parameter `BSG_INV_PARAM(link_channels_p )
, parameter `BSG_INV_PARAM(nodes_p ) // how many nodes on the FSB
, parameter `BSG_INV_PARAM(master_p ) // 1=FPGA,0=ASIC
// e.g if you have four channels, and you wanted any
// subset of them to be supported, you would
// provide 1111. if you only want all four channels
// to be supported, then you provide 1000.
//
// any combination of channels
, parameter channel_mask_p=(1 << (link_channels_p))-1
// NB: master_ parameters only apply to the master
// this is the maximum ratio between master io frequency
// and the min of: slave io frequency
// slave core frequency
// master core frequency
//
// that we want to support.
// Used only by master.
, parameter master_to_slave_speedup_p = 100
// have this node enabled at startup (typ. 0 for ASIC; 1 for FPGA)
, parameter enabled_at_start_vec_p = (nodes_p) ' (0)
// * PARAMETERS
// * below here mostly can be left alone
// *
// *
// *
// enable this if comm_link appears on the critical path
// adds one core cycle of latency in or out
// and two channel_width_p*link_channels fifos.
, parameter sbox_pipeline_in_p = 1'b1
, parameter sbox_pipeline_out_p = 1'b1
// made this node see all packets (typ. 0 for ASIC and FPGA)
, parameter snoop_vec_p = (nodes_p) ' (0)
// in testing, use this to disable tests
, parameter master_bypass_test_p = 5'b00000
// for DDR at 500 mbps, we make token go at / 8 = 66 mbps
// this will keep the token clock nice and slow
// careful: values other than 3 have not been tested.
, parameter lg_credit_to_token_decimation_p = 3
// lg of how many cycles to wait to assert token reset
// also how many cycles to assert it for
// keep these at 5; bigger is not necessarilybetter.
// bigger is not necessarily better for token_width
// keep these at 5, unless token_decimation
// increases.
, parameter master_lg_token_width_p = lg_credit_to_token_decimation_p+2
, parameter slave_lg_token_width_p = lg_credit_to_token_decimation_p+2
// time after reset to start calibration process
, parameter master_lg_wait_after_reset_p = $clog2(1+master_to_slave_speedup_p*128)
// time to assert reset before calibration code
, parameter master_calib_prepare_cycles_p
= master_to_slave_speedup_p
* 2 * (2**(master_lg_token_width_p+1)+2**(slave_lg_token_width_p+1))
// time to hold calibration code after reset
// see derivation in master_master
, parameter master_lg_out_prepare_hold_cycles_p
= $clog2(5*master_to_slave_speedup_p+10)
// fixme: derive value better (we reduced this to 25 from 5000 for simulation)
// 25 might actually be okay
, parameter master_calib_timeout_cycles_p = master_to_slave_speedup_p * 25
)
(input core_clk_i
, input async_reset_i
, input io_master_clk_i
// into nodes (control)
, output [nodes_p-1:0] core_node_reset_r_o
, output [nodes_p-1:0] core_node_en_r_o
// into nodes (fsb interface)
, output [nodes_p-1:0] core_node_v_o
, output [core_channels_p*channel_width_p-1:0] core_node_data_o [nodes_p-1:0]
, input [nodes_p-1:0] core_node_ready_i
// out of nodes (fsb interface)
, input [nodes_p-1:0] core_node_v_i
, input [core_channels_p*channel_width_p-1:0] core_node_data_i [nodes_p-1:0]
, output [nodes_p-1:0] core_node_yumi_o
// use this as a reset signal if you want to wakeup
// after the comm link has woken up.
, output core_calib_reset_r_o
// in from i/o
, input [link_channels_p-1:0] io_valid_tline_i
, input [channel_width_p-1:0] io_data_tline_i [link_channels_p-1:0]
, input [link_channels_p-1:0] io_clk_tline_i // clk
, output [link_channels_p-1:0] io_token_clk_tline_o // clk
// out to i/o
, output [link_channels_p-1:0] im_valid_tline_o
, output [channel_width_p-1:0] im_data_tline_o [link_channels_p-1:0]
, output [link_channels_p-1:0] im_clk_tline_o // clk
// note: generate by the master (FPGA) and sent to the slave (ASIC)
// not used by slave (ASIC).
, output reg im_slave_reset_tline_r_o
, input [link_channels_p-1:0] token_clk_tline_i // clk
// note: this is almost never the right reset to use
// as it occurs before the channels come up
// safest thing is to not connect it
, output core_async_reset_danger_o
);
// if we have more than 2X the number of core channels than link channels
// we should use a channel narrow gadget to simplify the circuit
// higher multiples are possible but TBD.
localparam bao_narrow_lp = (
((core_channels_p / 2) >= link_channels_p)
& (core_channels_p % 2) == 0
) ? 2 : 1;
// across all frequency combinations, we need a little over 20 fifo slots
// so we round up to 32, to allow for delay in the FPGA
localparam lg_input_fifo_depth_lp = 5;
// synchronized resets for incoming i/o channels
wire [link_channels_p-1:0] io_reset;
wire [link_channels_p-1:0] io_calib_done;
wire im_reset;
wire [link_channels_p-1:0] im_clk_init;
wire im_slave_reset_tline_n;
wire core_reset_i;
assign core_async_reset_danger_o = core_reset_i;
// synchronize core and im resets
bsg_sync_sync #(.width_p(1)) core_reset_ss
(.oclk_i(core_clk_i)
, .iclk_data_i(async_reset_i)
, .oclk_data_o(core_reset_i)
);
bsg_sync_sync #(.width_p(1)) im_reset_ss
(.oclk_i(io_master_clk_i)
, .iclk_data_i(async_reset_i)
, .oclk_data_o(im_reset)
);
// register true output signals
always @(posedge io_master_clk_i)
im_slave_reset_tline_r_o <= im_slave_reset_tline_n;
wire [link_channels_p-1:0] core_asm_to_sso_valid;
wire [channel_width_p-1:0] core_asm_to_sso_data [link_channels_p-1:0];
wire [link_channels_p-1:0] core_asm_to_sso_ready;
wire [link_channels_p-1:0] core_ssi_to_asm_valid;
wire [channel_width_p-1:0] core_ssi_to_asm_data [link_channels_p-1:0];
wire [link_channels_p-1:0] core_ssi_to_asm_yumi;
wire [link_channels_p-1:0] core_asm_to_sso_valid_sbox
, core_ssi_to_asm_valid_sbox;
wire [channel_width_p-1:0] core_asm_to_sso_data_sbox [link_channels_p-1:0];
wire [channel_width_p-1:0] core_ssi_to_asm_data_sbox [link_channels_p-1:0];
wire [link_channels_p-1:0] core_asm_to_sso_ready_sbox
, core_ssi_to_asm_yumi_sbox;
// synchronous to im clock
wire [link_channels_p-1:0] im_override_en;
wire [channel_width_p+1-1:0] im_override_valid_data [link_channels_p-1:0];
wire [link_channels_p-1:0] im_override_is_posedge, im_infinite_credits_en;
// synchronous to io clocks
wire [channel_width_p+1-1:0] io_snoop_valid_data_pos [link_channels_p-1:0];
wire [channel_width_p+1-1:0] io_snoop_valid_data_neg [link_channels_p-1:0];
wire [link_channels_p-1:0] io_trigger_mode_en, io_trigger_mode_alt_en;
wire [link_channels_p-1:0] core_loopback_en;
wire [link_channels_p-1:0] core_channel_active, im_channel_active;
// computed from channel_active signals
logic [`BSG_MAX(0,$clog2(link_channels_p)-1):0] core_top_active_channel_bao_r, core_top_active_channel_bai_r, core_top_active_channel_n;
logic [`BSG_MAX(0,$clog2(link_channels_p+1)-1):0] active_channel_count;
bsg_popcount #(.width_p(link_channels_p)) pop (.i(core_channel_active)
,.o(active_channel_count) );
// how many channels are alive?
assign core_top_active_channel_n = (| core_channel_active) ? (active_channel_count - 1) : '0;
// clone this register to keep it off critical paths
bsg_dff #(.harden_p(1)
,.strength_p(4)
,.width_p(`BSG_MAX(1,$clog2(link_channels_p)))
) core_top_active_channel_bai_r_reg
(.clock_i(core_clk_i)
,.data_i(core_top_active_channel_n)
,.data_o(core_top_active_channel_bai_r)
);
bsg_dff #(.harden_p(1)
,.strength_p(4)
,.width_p(`BSG_MAX(1,$clog2(link_channels_p)))
) core_top_active_channel_bao_r_reg
(.clock_i(core_clk_i)
,.data_i(core_top_active_channel_n)
,.data_o(core_top_active_channel_bao_r)
);
localparam tests_p = 5;
wire im_calib_done, im_calib_done_r;
wire core_calib_done_prefanout_r;
bsg_launch_sync_sync #(.width_p(1)) out_to_core_sync_calib_done
(.iclk_i(io_master_clk_i)
,.iclk_reset_i(1'b0)
,.oclk_i(core_clk_i)
,.iclk_data_i(im_calib_done)
,.iclk_data_o(im_calib_done_r)
// ,.oclk_data_o(core_calib_done_r)
,.oclk_data_o(core_calib_done_prefanout_r)
);
// generate pipelined reset tree
wire [5:0] core_calib_done_vec_r;
assign core_calib_reset_r_o = ~core_calib_done_vec_r[0];
genvar k;
for (k = 0; k < 6; k=k+1)
begin: cr
bsg_dff #(.harden_p(1)
,.strength_p(4)
,.width_p(1)
) core_calib_reset_fanout_reg
(.clock_i(core_clk_i)
,.data_i(core_calib_done_prefanout_r)
,.data_o(core_calib_done_vec_r[k])
);
end
if (master_p)
begin : mstr
// counter intuitive; organized by tests then by channel
wire [tests_p+1-1:0][link_channels_p-1:0] im_test_scoreboard;
wire [$clog2(tests_p+1)-1:0] im_test_index; // + 1; for the "final test"
wire im_prepare;
// assert the tline
assign im_slave_reset_tline_n = im_prepare;
logic im_start_calibration_n, im_start_calibration_r;
// wait a certain number of cycles after global reset to start
// global calibration
bsg_wait_after_reset #(.lg_wait_cycles_p(master_lg_wait_after_reset_p)) bwar
(.clk_i(io_master_clk_i)
,.reset_i (im_reset)
,.ready_r_o(im_start_calibration_n)
);
always_ff @(posedge io_master_clk_i)
im_start_calibration_r <= im_start_calibration_n;
bsg_source_sync_channel_control_master_master
#(.link_channels_p(link_channels_p)
,.tests_p(tests_p)
,.prepare_cycles_p(master_calib_prepare_cycles_p)
,.timeout_cycles_p(master_calib_timeout_cycles_p)
) master_master
(.clk_i(io_master_clk_i)
,.reset_i (im_reset)
,.start_i (~im_start_calibration_r & im_start_calibration_n )
,.test_scoreboard_i(im_test_scoreboard)
,.test_index_r_o (im_test_index )
,.prepare_o (im_prepare )
,.done_o (im_calib_done )
);
always_ff @(negedge io_master_clk_i)
if (im_calib_done & ~im_calib_done_r)
$display("###### Master calibration COMPLETED with active channels: (%b)."
, im_channel_active);
end // block: mstr
else // slave
begin
// the slave is done calibrating if any of the channels are
// active. since activation goes high only when im_reset goes
// low, all channels will all activate at the same time.
//
// no waiting for differences in channel clocks is necessary.
//
assign im_calib_done = (|im_channel_active);
assign im_slave_reset_tline_n = 1'b0;
end
wire im_channel_reset, core_channel_reset;
genvar i,j;
logic im_reset_r;
if (master_p)
begin : rreg
always @(posedge io_master_clk_i)
im_reset_r <= im_reset;
end
// create all of the input and output channels
for (i = 0; i < link_channels_p; i=i+1)
begin: ch
bsg_launch_sync_sync #(.width_p(1)) blss_channel_active
(.iclk_i (io_master_clk_i)
,.iclk_reset_i(im_reset)
,.oclk_i (core_clk_i)
,.iclk_data_i (im_channel_active[i])
,.iclk_data_o()
,.oclk_data_o (core_channel_active[i])
);
if (master_p)
begin :m
wire [tests_p+1-1:0] im_tests_gather;
for (j = 0; j < tests_p+1; j=j+1)
begin : mpa
assign mstr.im_test_scoreboard[j][i] = im_tests_gather[j];
end
bsg_source_sync_channel_control_master
#(.width_p(channel_width_p)
,.lg_token_width_p(master_lg_token_width_p)
,.lg_out_prepare_hold_cycles_p(master_lg_out_prepare_hold_cycles_p)
,.bypass_test_p(master_bypass_test_p)
,.tests_lp(tests_p)
) control_master
(
.out_clk_i (io_master_clk_i)
,.out_reset_i (im_reset)
,.out_calibration_state_i (mstr.im_test_index)
,.out_calib_prepare_i (mstr.im_prepare)
,.out_channel_blessed_i (im_channel_active[i])
,.out_override_en_o (im_override_en [i])
,.out_override_valid_data_o (im_override_valid_data [i])
,.out_override_is_posedge_i (im_override_is_posedge [i])
,.in_clk_i (io_clk_tline_i [i])
// reset synchronized to io_clk_tline_i
,.in_reset_i (io_reset [i])
,.in_snoop_valid_data_neg_i(io_snoop_valid_data_neg [i])
,.in_snoop_valid_data_pos_i(io_snoop_valid_data_pos [i])
// AWC fixme: incorrect name should be output clocked, not in clocked
// i.e. should be:
,.out_infinite_credits_o (im_infinite_credits_en[i])
//,.in_infinite_credits_o (io_infinite_credits_en [i])
,.out_test_pass_r_o ( im_tests_gather )
);
assign im_channel_reset = mstr.im_prepare;
bsg_launch_sync_sync #(.width_p(1)) io_reset_lss
(.iclk_i (io_master_clk_i)
,.iclk_reset_i(1'b0)
,.oclk_i (io_clk_tline_i[i])
,.iclk_data_i (im_channel_reset)
,.iclk_data_o()
,.oclk_data_o (io_reset[i])
);
// generate core_channel reset from im_channel reset
bsg_launch_sync_sync #(.width_p(1)) bssi_reset
(.iclk_i(io_master_clk_i)
,.iclk_reset_i(1'b0)
,.oclk_i(core_clk_i)
,.iclk_data_i(im_channel_reset)
,.iclk_data_o()
,.oclk_data_o(core_channel_reset)
);
assign io_trigger_mode_en [i] = 1'b0;
assign io_trigger_mode_alt_en [i] = 1'b0;
assign core_loopback_en [i] = 1'b0;
`ifndef SYNTHESIS
// activate the channel if all of the "real" tests passed
// MBT: we use triple equals because this handles the X case in simulation
// DC of course does not like ===
assign im_channel_active[i] = (im_tests_gather[tests_p-1:0] === { tests_p {1'b1} });
`else
assign im_channel_active[i] = (im_tests_gather[tests_p-1:0] == { tests_p {1'b1} });
`endif
assign im_clk_init [i] = im_reset & ~im_reset_r;
end
else
begin : s
// no launch flop necessary here
// and we synchronize directly from
// the async reset for speed
bsg_sync_sync #(.width_p(1)) io_reset_ss
(.oclk_i(io_clk_tline_i[i])
, .iclk_data_i(async_reset_i)
, .oclk_data_o(io_reset[i])
);
assign core_channel_reset = core_reset_i;
assign im_channel_reset = im_reset;
bsg_source_sync_channel_control_slave
#(.width_p(channel_width_p)
,.lg_token_width_p(slave_lg_token_width_p)
)
control_slave
(// output channel
.out_clk_i (io_master_clk_i)
,.out_reset_i (im_reset)
,.out_clk_init_r_o (im_clk_init [i])
,.out_override_en_o (im_override_en [i])
,.out_override_valid_data_o (im_override_valid_data [i])
// whether the channel is available for I/O assembler, post reset
,.out_channel_active_o (im_channel_active [i])
// for input channel
,.in_clk_i (io_clk_tline_i [i])
,.in_snoop_valid_data_i (io_snoop_valid_data_pos [i])
,.in_trigger_mode_en_o (io_trigger_mode_en [i])
,.in_trigger_mode_alt_en_o (io_trigger_mode_alt_en [i])
// AWC fixme: incorrect name should be output clocked, not in clocked
// i.e. should be:
,.out_infinite_credits_o (im_infinite_credits_en[i])
//,.in_infinite_credits_o (io_infinite_credits_en [i])
// for core control
,.core_clk_i (core_clk_i )
,.core_loopback_en_o (core_loopback_en [i])
);
end
// The token reset strategy for metastability is different,
// because clocking the token clock increments a counter. Introducing
// a synchronizer for the reset requires for us to control the token reset
// precisely relative to the token clock, which cannot easily be done
// from another clock domain.
//
// Instead, we tie the token reset to the im reset, and avoid
// metastability by requiring the master reset be asserted for many cycles
// before going low.
//
// During that reset period, we toggle the token clock to clear out state.
// The token clock should only be toggled again (in normal use) a safe
// number of cycles after reset goes low.
wire token_reset = im_channel_reset;
bsg_source_sync_output
#(.lg_start_credits_p(lg_input_fifo_depth_lp)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.channel_width_p(channel_width_p)
) sso
(.core_clk_i(core_clk_i)
,.core_reset_i(core_channel_reset)
,.core_data_i (core_loopback_en[i]
? core_ssi_to_asm_data [i]
: core_asm_to_sso_data_sbox [i])
,.core_valid_i(core_loopback_en[i]
? core_ssi_to_asm_valid[i]
: core_asm_to_sso_valid_sbox[i])
// fixme: any special treatment required for loopback?
,.core_ready_o(core_asm_to_sso_ready [i])
,.io_master_clk_i(io_master_clk_i)
,.io_reset_i (im_channel_reset)
,.io_clk_init_i (im_clk_init[i])
,.io_override_en_i (im_override_en[i] )
,.io_override_valid_data_i(im_override_valid_data[i])
,.io_override_is_posedge_o(im_override_is_posedge[i])
,.io_clk_r_o( im_clk_tline_o [i])
,.io_data_r_o( im_data_tline_o [i])
,.io_valid_r_o(im_valid_tline_o [i])
// AWC fixme: incorrect name should be output clocked, not in clocked
// i.e. should be:
,.io_infinite_credits_i (im_infinite_credits_en[i])
//,.io_infinite_credits_i (io_infinite_credits_en[i])
,.token_clk_i (token_clk_tline_i [i])
,.token_reset_i(token_reset )
);
bsg_launch_sync_sync #(.width_p(1)) im_to_io_calib_done
(.iclk_i (io_master_clk_i)
,.iclk_reset_i(1'b0)
,.oclk_i (io_clk_tline_i[i])
,.iclk_data_i (im_calib_done)
,.iclk_data_o()
,.oclk_data_o (io_calib_done[i])
);
bsg_source_sync_input
#(.lg_fifo_depth_p(lg_input_fifo_depth_lp)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.channel_width_p(channel_width_p)
) ssi
// starts on reset lo->hi xition
(.io_clk_i (io_clk_tline_i [i])
,.io_data_i (io_data_tline_i [i])
,.io_valid_i (io_valid_tline_i [i])
,.io_token_r_o(io_token_clk_tline_o [i])
// note a small quirk: for the master, we tie reset of the
// input channel to the calibration being done rather
// than the channel reset. this is because for the most
// part the input channel is not used during calibration.
// for the master, we keep this unit quiet until calibration is done
// for the slave, we need to use this unit, but we reset it for each
// phase of calibration
,.io_reset_i(master_p ? ~io_calib_done[i] : io_reset[i])
// for both master and slave, prepare/reset mode enables token bypass
// i.e.; we reset the token on every Phase.
//
,.io_token_bypass_i(io_reset[i])
,.io_edge_i(2'b11) // latch on both edges; could change on the fly
,.io_snoop_pos_r_o(io_snoop_valid_data_pos[i]) // snoop input channel
// for establishing calib.
// state on reset
,.io_snoop_neg_r_o(io_snoop_valid_data_neg[i])
// enable loop-back trigger mode
,.io_trigger_mode_en_i (io_trigger_mode_en [i])
// enable loop-back trigger mode: alternate trigger
,.io_trigger_mode_alt_en_i(io_trigger_mode_alt_en[i])
,.core_clk_i (core_clk_i)
,.core_reset_i(core_channel_reset)
// core 1 side logical signals
,.core_data_o (core_ssi_to_asm_data [i] )
,.core_valid_o(core_ssi_to_asm_valid [i] )
,.core_yumi_i (core_loopback_en[i]
? (core_asm_to_sso_ready[i] & core_ssi_to_asm_valid[i])
: core_ssi_to_asm_yumi_sbox[i])
);
// only used by master; ignore for slave
// wire ignore = | io_snoop_valid_data_neg[i];
end // block: channel
//***************************************************
//
// SBOX, ASSEMBLER AND FRONT SIDE BUS
//
//
// fixme: the code after this point
// could be factored into another file
//
//***************************************************
bsg_sbox #(.num_channels_p(link_channels_p)
,.channel_width_p(channel_width_p)
,.pipeline_indir_p(sbox_pipeline_in_p)
,.pipeline_outdir_p(sbox_pipeline_out_p)
) sbox
(.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.calibration_done_i(core_calib_done_vec_r[1])
,.channel_active_i(core_channel_active)
,.in_v_i (core_ssi_to_asm_valid)
,.in_data_i(core_ssi_to_asm_data )
,.in_yumi_o(core_ssi_to_asm_yumi_sbox )
,.in_v_o (core_ssi_to_asm_valid_sbox )
,.in_data_o(core_ssi_to_asm_data_sbox )
,.in_yumi_i(core_ssi_to_asm_yumi )
,.out_me_v_i (core_asm_to_sso_valid )
,.out_me_data_i (core_asm_to_sso_data )
,.out_me_ready_o(core_asm_to_sso_ready_sbox )
,.out_me_v_o (core_asm_to_sso_valid_sbox )
,.out_me_data_o (core_asm_to_sso_data_sbox )
,.out_me_ready_i(core_asm_to_sso_ready )
);
// outgoing from fsb to nrw
wire core_nrw_valid_li;
wire [core_channels_p*channel_width_p-1:0] core_nrw_data_li;
wire core_nrw_ready_lo;
// outgoing from nrw to asm
wire core_asm_valid_li;
wire [core_channels_p*channel_width_p/bao_narrow_lp-1:0] core_asm_data_li;
wire core_asm_ready_lo;
// out to core
wire core_asm_valid_lo;
wire [core_channels_p*channel_width_p-1:0] core_asm_data_lo;
wire core_asm_yumi_li;
typedef logic [`BSG_MAX($clog2(core_channels_p/bao_narrow_lp),1)-1:0] bsg_comm_link_active_out_vec_t;
typedef logic [`BSG_MAX($clog2(core_channels_p),1)-1:0] bsg_comm_link_active_in_vec_t;
// de-bond channel into multiple individual channels
bsg_assembler_out #(.width_p(channel_width_p)
,.num_in_p(core_channels_p/bao_narrow_lp)
,.num_out_p(link_channels_p)
,.out_channel_count_mask_p(channel_mask_p)
) bao
(.clk (core_clk_i )
,.reset (core_channel_reset)
,.calibration_done_i(core_calib_done_vec_r[2])
,.valid_i(core_asm_valid_li)
,.data_i (core_asm_data_li )
,.ready_o(core_asm_ready_lo)
// typesafe equivalent to core_channels_p-1
,.in_top_channel_i( (bsg_comm_link_active_out_vec_t ' (core_channels_p/bao_narrow_lp))
- 1'b1
)
,.out_top_channel_i(core_top_active_channel_bao_r)
,.valid_o(core_asm_to_sso_valid)
,.data_o( core_asm_to_sso_data )
,.ready_i(core_asm_to_sso_ready_sbox)
);
// we will not say that data is available unless
// calibration is done; keeps interface clean.
wire core_valid_tmp;
assign core_asm_valid_lo = core_valid_tmp & core_calib_done_vec_r[2];
// merge them into one bonded channel
bsg_assembler_in #(.width_p(channel_width_p)
,.num_in_p(link_channels_p)
,.num_out_p(core_channels_p)
,.in_channel_count_mask_p(channel_mask_p)
) bai
(.clk (core_clk_i )
,.reset (core_channel_reset)
,.calibration_done_i (core_calib_done_vec_r[3] )
,.valid_i(core_ssi_to_asm_valid_sbox)
,.data_i (core_ssi_to_asm_data_sbox )
,.yumi_o (core_ssi_to_asm_yumi )
,.in_top_channel_i(core_top_active_channel_bai_r)
// typesafe equivalent to core_channels_p-1
,.out_top_channel_i((bsg_comm_link_active_in_vec_t ' (core_channels_p)) - 1'b1)
,.valid_o(core_valid_tmp)
,.data_o (core_asm_data_lo )
,.yumi_i (core_asm_yumi_li )
);
if (bao_narrow_lp == 2)
begin: nrw
bsg_fifo_1r1w_narrowed #(.width_p(channel_width_p*core_channels_p)
,.els_p(2)
,.width_out_p(channel_width_p*core_channels_p/bao_narrow_lp)
) nrw
(.clk_i(core_clk_i)
,.reset_i(~core_calib_done_vec_r[4])
// from FSB
,.v_i (core_nrw_valid_li)
,.data_i (core_nrw_data_li )
,.ready_o(core_nrw_ready_lo)
// to assembler
,.v_o (core_asm_valid_li)
,.data_o(core_asm_data_li)
,.yumi_i(core_asm_ready_lo & core_asm_valid_li)
);
end // block: nrw
else
begin : not_nrw
assign core_asm_valid_li = core_nrw_valid_li;
assign core_asm_data_li = core_nrw_data_li;
assign core_nrw_ready_lo = core_asm_ready_lo;
end
bsg_fsb #(.width_p(channel_width_p*core_channels_p)
,.nodes_p(nodes_p)
,.enabled_at_start_vec_p(enabled_at_start_vec_p)
,.snoop_vec_p(snoop_vec_p)
) fsb
(.clk_i (core_clk_i)
,.reset_i(~core_calib_done_vec_r[5])
// from assembler
,.asm_v_i (core_asm_valid_lo)
,.asm_data_i(core_asm_data_lo )
,.asm_yumi_o(core_asm_yumi_li )
// to assembler
,.asm_v_o (core_nrw_valid_li)
,.asm_data_o (core_nrw_data_li )
,.asm_ready_i(core_nrw_ready_lo)
// into nodes
,.node_v_o (core_node_v_o )
,.node_data_o (core_node_data_o )
,.node_ready_i (core_node_ready_i )
,.node_en_r_o (core_node_en_r_o )
,.node_reset_r_o(core_node_reset_r_o)
// out of nodes
,.node_v_i (core_node_v_i )
,.node_data_i(core_node_data_i)
,.node_yumi_o(core_node_yumi_o)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_comm_link)
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MEMC
// / / Filename: memc_traffic_gen.v
// /___/ /\ Date Last Modified: $Date:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6/Virtex6
//Design Name: memc_traffic_gen
//Purpose: This is top level module of memory traffic generator which can
// generate different CMD_PATTERN and DATA_PATTERN to Spartan 6
// hard memory controller core.
//Reference:
//Revision History: 1.1 Brought out internal signals cmp_data and cmp_error as outputs.
// 1.2 7/1/2009 Added EYE_TEST parameter for signal SI probing.
// 1.3 10/1/2009 Added dq_error_bytelane_cmp,cumlative_dq_lane_error signals for V6.
// Any comparison error on user read data bus are mapped back to
// dq bus. The cumulative_dq_lane_error accumulate any errors on
// DQ bus. And the dq_error_bytelane_cmp shows error during current
// command cycle. The error can be cleared by input signal "manual_clear_error".
// 1.4 7/29/10 Support virtex Back-to-back commands over user interface.
//
//*****************************************************************************
`timescale 1ps/1ps
module memc_traffic_gen #
(
parameter TCQ = 100, // SIMULATION tCQ delay.
parameter FAMILY = "SPARTAN6", // "VIRTEX6", "SPARTAN6"
parameter MEM_TYPE = "DDR3",
parameter SIMULATION = "FALSE",
parameter tCK = 2500,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter BL_WIDTH = 6,
parameter MEM_BURST_LEN = 8, // For VIRTEX6 Only in this traffic gen.
// This traffic gen doesn't support DDR3 OTF Burst mode.
parameter PORT_MODE = "BI_MODE", // SPARTAN6: "BI_MODE", "WR_MODE", "RD_MODE"
// VIRTEX6: "BI_MODE"
parameter DATA_PATTERN = "DGEN_ALL", // "DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_RPBS","CGEN_FIXED", "CGEN_BRAM", "CGEN_SEQUENTIAL", "CGEN_ALL",
parameter ADDR_WIDTH = 30, // Spartan 6 Addr width is 30
parameter BANK_WIDTH = 3,
parameter CMP_DATA_PIPE_STAGES = 0, // parameter for MPMC, it should always set to 0
// memory type specific
parameter MEM_COL_WIDTH = 10, // memory column width
parameter NUM_DQ_PINS = 16, // Spartan 6 Options: 4,8,16;
// Virtex 6 DDR2/DDR3 Options: 8,16,24,32,.....144
parameter SEL_VICTIM_LINE = 3, // SEL_VICTIM_LINE LINE is one of the DQ pins is selected to be different than hammer pattern
// SEL_VICTIM_LINE is only for V6.
// Virtex 6 option: 8,9,16,17,32,36,64,72
parameter DWIDTH = NUM_DQ_PINS*2*nCK_PER_CLK, //NUM_DQ_PINS*4, // Spartan 6 Options: 32,64,128;
// Virtex 6 Always: 4* NUM_DQ_PINS
// the following parameter is to limit the range of generated PRBS Address
//
// e.g PRBS_SADDR_MASK_POS = 32'h0000_7000 the bit 14:12 of PRBS_SADDR will be ORed with
// PRBS_SADDR = 32'h0000_5000 the LFSR[14:12] to add the starting address offset.
// PRBS_EADDR = 32'h0000_7fff
// PRBS_EADDR_MASK_POS = 32'hffff_7000 => mark all the leading 0's in PRBS_EADDR to 1 to
// zero out the LFSR[31:15]
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter PRBS_EADDR = 32'h00002000,
parameter PRBS_SADDR = 32'h00005000,
parameter EYE_TEST = "FALSE" // set EYE_TEST = "TRUE" to probe memory signals.
// Traffic Generator will only write to one single location and no
// read transactions will be generated.
)
(
input clk_i,
input rst_i,
input run_traffic_i,
input manual_clear_error,
input [5:0] cmds_gap_delay_value, // control delay gap between each sucessive
// burst commands.
// *** runtime parameter ***
input mem_pattern_init_done_i,
input [31:0] start_addr_i, // define the start of address
input [31:0] end_addr_i, // define upper limit addressboundary
input [31:0] cmd_seed_i, // seed for cmd PRBS generators
input [31:0] data_seed_i, // data seed will be added to generated address
// for PRBS data generation
// seed for cmd PRBS generators
input load_seed_i, // when asserted the cmd_seed and data_seed inputs will be registered.
// upper layer inputs to determine the command bus and data pattern
// internal traffic generator initialize the memory with
input [2:0] addr_mode_i, // "00" = bram; takes the address from bram interface
// "01" = fixed address from the fixed_addr input
// "10" = psuedo ramdom pattern; generated from internal 64 bit LFSR
// "11" = sequential
// for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined
// in the instr_mode input. The runtime mode will be automatically loaded inside when it is in
input [3:0] instr_mode_i, // "0000" = BRAM
// "0001" = Fixed; takes instruction from bram output
// "0010" = R/W
// "0011" = RP/WP
// "0100" = R/RP/W/WP
// "0101" = R/RP/W/WP/REF
// "0110" = PRBS
// "1111" = Read Only from Address 0 . Expecting phy calibration data pattern.
input [1:0] bl_mode_i, // "00" = bram; takes the burst length from bram output
// "01" = fixed , takes the burst length from the fixed_bl input
// "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR
input [3:0] data_mode_i, // "000" = address as data
// "001" = hammer
// "010" = neighbour
// "011" = prbs
// "100" = walking 0's
// "101" = walking 1's
// "110" =
// "111" =
input wr_data_mask_gen_i, // "1": turn on wr_data_mask generation
// random follow by walking 1's
input mode_load_i,
// fixed pattern inputs interface
input [BL_WIDTH - 1:0] fixed_bl_i, // range from 1 to 64
input [2:0] fixed_instr_i, //RD 3'b001
//RDP 3'b011
//WR 3'b000
//WRP 3'b010
//REFRESH 3'b100
input [31:0] fixed_addr_i, // only upper 30 bits will be used
input [31:0] fixed_data_i, //
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
// BRAM interface.
// bram bus formats:
// Only SP6 has been tested.
input [38:0] bram_cmd_i, // {{bl}, {cmd}, {address[28:2]}}
input bram_valid_i,
output bram_rdy_o, //
/////////////////////////////////////////////////////////////////////////////
// MCB INTERFACE
// interface to mcb command port
output memc_cmd_en_o,
output [2:0] memc_cmd_instr_o,
output [31:0] memc_cmd_addr_o,
output [5:0] memc_cmd_bl_o, // this output is for Spartan 6
input memc_cmd_full_i,
// interface to qdr interface
output qdr_wr_cmd_o,
output qdr_rd_cmd_o,
// interface to mcb wr data port
output memc_wr_en_o,
output [DWIDTH-1:0] memc_wr_data_o,
output memc_wr_data_end_o,
output [(DWIDTH/8) - 1:0] memc_wr_mask_o,
input memc_wr_full_i,
// interface to mcb rd data port
output memc_rd_en_o,
input [DWIDTH-1:0] memc_rd_data_i,
input memc_rd_empty_i,
/////////////////////////////////////////////////////////////////////////////
// status feedback
input counts_rst,
output reg [47:0] wr_data_counts,
output reg [47:0] rd_data_counts,
output cmp_error,
output cmp_data_valid,
output error, // asserted whenever the read back data is not correct.
output [64 + (2*DWIDTH - 1):0] error_status ,// TBD how signals mapped
output [DWIDTH-1:0] cmp_data,
output [DWIDTH-1:0] mem_rd_data,
// **** V6 Signals
output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp, // V6: real time compare error byte lane
output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error, // V6: latched error byte lane that occure on
// first error
//************************************************
// DQ bit error debug signals.
output [NUM_DQ_PINS - 1:0] cumlative_dq_r0_bit_error ,
output [NUM_DQ_PINS - 1:0] cumlative_dq_f0_bit_error ,
output [NUM_DQ_PINS - 1:0] cumlative_dq_r1_bit_error ,
output [NUM_DQ_PINS - 1:0] cumlative_dq_f1_bit_error ,
output [NUM_DQ_PINS-1:0] dq_r0_bit_error_r,
output [NUM_DQ_PINS-1:0] dq_f0_bit_error_r,
output [NUM_DQ_PINS-1:0] dq_r1_bit_error_r,
output [NUM_DQ_PINS-1:0] dq_f1_bit_error_r,
//
output [NUM_DQ_PINS - 1:0] dq_r0_read_bit, // rising 0 read bits from mc
output [NUM_DQ_PINS - 1:0] dq_f0_read_bit, // falling 0 read bits from mc
output [NUM_DQ_PINS - 1:0] dq_r1_read_bit, // rising 1 read bits from mc
output [NUM_DQ_PINS - 1:0] dq_f1_read_bit, // falling 1 read bits from mc
output [NUM_DQ_PINS - 1:0] dq_r0_expect_bit, // rising 0 read bits from internal expect data generator
output [NUM_DQ_PINS - 1:0] dq_f0_expect_bit, // falling 0 read bits from internal expect data generator
output [NUM_DQ_PINS - 1:0] dq_r1_expect_bit, // rising 1 read bits from internal expect data generator
output [NUM_DQ_PINS - 1:0] dq_f1_expect_bit, // falling 1 read bits from internal expect data generator
output [31:0] error_addr // the command address of the returned data.
// Can use dq_rx_bit_error as write enable to latch the address.
);
wire [DWIDTH-1:0] rdpath_rd_data_i;
wire rdpath_data_valid_i;
wire memc_wr_en;
wire cmd2flow_valid;
wire [2:0] cmd2flow_cmd;
wire [31:0] cmd2flow_addr;
wire [BL_WIDTH-1:0] cmd2flow_bl;
wire last_word_wr;
wire flow2cmd_rdy;
wire [31:0] wr_addr;
wire [31:0] rd_addr;
wire [BL_WIDTH-1:0] wr_bl;
wire [BL_WIDTH-1:0] rd_bl;
reg run_traffic_reg;
wire wr_validB, wr_valid,wr_validC;
wire [31:0] bram_addr_i;
wire [2:0] bram_instr_i;
wire [5:0] bram_bl_i;
reg AC2_G_E2,AC1_G_E1,AC3_G_E3;
reg upper_end_matched;
reg [7:0] end_boundary_addr;
reg lower_end_matched;
wire [31:0] addr_o;
wire [31:0] m_addr;
wire dcount_rst;
wire [31:0] rd_addr_error;
wire rd_rdy;
//wire cmp_error;
wire cmd_full;
wire rd_mdata_fifo_rd_en;
wire rd_mdata_fifo_afull;
reg memc_wr_en_r;
wire memc_wr_data_end;
reg [DWIDTH-1:0] memc_rd_data_r;
wire [DWIDTH-1:0] memc_wr_data;
reg [DWIDTH-1:0] memc_wr_data_r;
wire wr_path_data_rdy_i;
//
wire [31:0] cmp_addr;
wire [5:0] cmp_bl;
// synthesis attribute keep of rst_ra is "true";
// synthesis attribute keep of rst_rb is "true";
reg [9:0] rst_ra,rst_rb;
wire mem_init_done;
reg [3:0] data_mode_r_a;
reg [3:0] data_mode_r_b;
reg [3:0] data_mode_r_c;
reg error_access_range = 1'b0;
wire [BL_WIDTH-1:0] memc_bl_o;
// generic parameters and need to be tested in both MCB mode and V7 Virtext Mode.
initial begin
if((MEM_BURST_LEN !== 4) && (MEM_BURST_LEN !== 8))
begin: NO_OTF_Warning_Error
$display("Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!");
$stop;
end
else
begin: Dummy1
end
end
always @ (memc_cmd_en_o,memc_cmd_addr_o,memc_cmd_bl_o,end_addr_i)
if (memc_cmd_en_o &&
((FAMILY == "SPARTAN6" && memc_cmd_addr_o + 20) > end_addr_i[ADDR_WIDTH-1:0]) ||
((FAMILY == "VIRTEX6" && memc_cmd_addr_o ) > end_addr_i[ADDR_WIDTH-1:0])
)
begin
$display("Error ! Command access beyond address range");
$display("Assigned Address Space: Start_Address = 0x%h ; End_Addr = 0x%h",start_addr_i,end_addr_i);
$display("Attempted area = 0x%h",memc_cmd_addr_o + (memc_cmd_bl_o - 1) * (DWIDTH/8));
$stop;
end
else
begin: No_Error_Display
end
//synthesis translate_on
assign memc_cmd_bl_o = memc_bl_o[5:0];
always @ (posedge clk_i)
begin
data_mode_r_a <= #TCQ data_mode_i;
data_mode_r_b <= #TCQ data_mode_i;
data_mode_r_c <= #TCQ data_mode_i;
end
// synthesis attribute MAX_FANOUT of rst_ra is 20;
// synthesis attribute MAX_FANOUT of rst_rb is 20;
//reg GSR = 1'b0;
always @(posedge clk_i)
begin
rst_ra <= #TCQ {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i};
rst_rb <= #TCQ {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i};
end
// register it . Just in case the calling modules didn't syn with clk_i
always @(posedge clk_i)
begin
run_traffic_reg <= #TCQ run_traffic_i;
end
assign bram_addr_i = {bram_cmd_i[29:0],2'b00};
assign bram_instr_i = bram_cmd_i[32:30];
assign bram_bl_i[5:0] = bram_cmd_i[38:33]; //41
//
//
reg COutc,COutd;
assign dcount_rst = counts_rst | rst_ra[0];
always @ (posedge clk_i)
begin
if (dcount_rst)
wr_data_counts <= #TCQ 'b0;
else if (memc_wr_en)
{COutc,wr_data_counts} <= #TCQ wr_data_counts + DWIDTH/8;
end
always @ (posedge clk_i)
begin
if (dcount_rst)
rd_data_counts <= #TCQ 'b0;
else if (memc_rd_en_o)
{COutd,rd_data_counts} <= #TCQ rd_data_counts + DWIDTH/8;
end
// **** for debug
// this part of logic is to check there are no commands been duplicated or dropped
// in the cmd_flow_control logic
generate
if (SIMULATION == "TRUE")
begin: cmd_check
wire fifo_error;
wire [31:0] xfer_addr;
wire cmd_fifo_rd;
assign cmd_fifo_wr = flow2cmd_rdy & cmd2flow_valid;
assign fifo_error = ( xfer_addr != memc_cmd_addr_o) ? 1'b1: 1'b0;
wire cmd_fifo_empty;
//assign cmd_fifo_rd = memc_cmd_en_o & ~memc_cmd_full_i & ~cmd_fifo_empty;
assign cmd_fifo_rd = memc_cmd_en_o & ~cmd_fifo_empty;
afifo #
(.TCQ (TCQ),
.DSIZE (38),
.FIFO_DEPTH (16),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
cmd_fifo
(
.wr_clk (clk_i),
.rst (rst_ra[0]),
.wr_en (cmd_fifo_wr),
.wr_data ({cmd2flow_bl,cmd2flow_addr}),
.rd_en (cmd_fifo_rd),
.rd_clk (clk_i),
.rd_data ({xfer_cmd_bl,xfer_addr}),
.full (cmd_fifo_full),
.almost_full (),
.empty (cmd_fifo_empty)
);
end
else
begin
assign fifo_error = 1'b0;
end
endgenerate
reg [31:0] end_addr_r;
always @ (posedge clk_i)
end_addr_r <= end_addr_i;
cmd_gen
#(
.TCQ (TCQ),
.FAMILY (FAMILY) ,
.MEM_TYPE (MEM_TYPE),
.BL_WIDTH (BL_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.PORT_MODE (PORT_MODE),
.BANK_WIDTH (BANK_WIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN),
.ADDR_WIDTH (ADDR_WIDTH),
.DWIDTH (DWIDTH),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS ),
.PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS ),
.PRBS_EADDR (PRBS_EADDR),
.PRBS_SADDR (PRBS_SADDR )
)
u_c_gen
(
.clk_i (clk_i),
.rst_i (rst_ra),
.reading_rd_data_i (memc_rd_en_o),
.run_traffic_i (run_traffic_reg),
.mem_pattern_init_done_i (mem_pattern_init_done_i),
.start_addr_i (start_addr_i),
.end_addr_i (end_addr_r),
.cmd_seed_i (cmd_seed_i),
.load_seed_i (load_seed_i),
.addr_mode_i (addr_mode_i),
.data_mode_i (data_mode_r_a),
.instr_mode_i (instr_mode_i),
.bl_mode_i (bl_mode_i),
.mode_load_i (mode_load_i),
// fixed pattern inputs interface
.fixed_bl_i (fixed_bl_i),
.fixed_addr_i (fixed_addr_i),
.fixed_instr_i (fixed_instr_i),
// BRAM FIFO input : Holist vector inputs
.bram_addr_i (bram_addr_i),
.bram_instr_i (bram_instr_i ),
.bram_bl_i (bram_bl_i ),
.bram_valid_i (bram_valid_i ),
.bram_rdy_o (bram_rdy_o ),
.rdy_i (flow2cmd_rdy),
.instr_o (cmd2flow_cmd),
.addr_o (cmd2flow_addr),
.bl_o (cmd2flow_bl),
// .m_addr_o (m_addr),
.cmd_o_vld (cmd2flow_valid),
.mem_init_done_o (mem_init_done)
);
assign memc_cmd_addr_o = addr_o;
assign qdr_wr_cmd_o = memc_wr_en_r;
assign cmd_full = memc_cmd_full_i;
memc_flow_vcontrol #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.BL_WIDTH (BL_WIDTH),
.MEM_BURST_LEN (MEM_BURST_LEN),
.NUM_DQ_PINS (NUM_DQ_PINS),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE)
)
memc_control
(
.clk_i (clk_i),
.rst_i (rst_ra),
.data_mode_i (data_mode_r_b),
.cmds_gap_delay_value (cmds_gap_delay_value),
.mcb_wr_full_i (memc_wr_full_i),
.cmd_rdy_o (flow2cmd_rdy),
.cmd_valid_i (cmd2flow_valid),
.cmd_i (cmd2flow_cmd),
.addr_i (cmd2flow_addr),
.bl_i (cmd2flow_bl),
// interface to memc_cmd port
.mcb_cmd_full (cmd_full),
.cmd_o (memc_cmd_instr_o),
.addr_o (addr_o),
.bl_o (memc_bl_o),
.cmd_en_o (memc_cmd_en_o),
.qdr_rd_cmd_o (qdr_rd_cmd_o),
// interface to write data path module
.mcb_wr_en_i (memc_wr_en),
.last_word_wr_i (last_word_wr),
.wdp_rdy_i (wr_rdy),//(wr_rdy),
.wdp_valid_o (wr_valid),
.wdp_validB_o (wr_validB),
.wdp_validC_o (wr_validC),
.wr_addr_o (wr_addr),
.wr_bl_o (wr_bl),
// interface to read data path module
.rdp_rdy_i (rd_rdy),// (rd_rdy),
.rdp_valid_o (rd_valid),
.rd_addr_o (rd_addr),
.rd_bl_o (rd_bl)
);
/* afifo #
(
.TCQ (TCQ),
.DSIZE (DWIDTH),
.FIFO_DEPTH (32),
.ASIZE (5),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_mdata_fifo
(
.wr_clk (clk_i),
.rst (rst_rb[0]),
.wr_en (!memc_rd_empty_i),
.wr_data (memc_rd_data_i),
.rd_en (memc_rd_en_o),
.rd_clk (clk_i),
.rd_data (rd_v6_mdata),
.full (),
.almost_full (rd_mdata_fifo_afull),
.empty (rd_mdata_fifo_empty)
);
*/
wire cmd_rd_en;
assign cmd_rd_en = memc_cmd_en_o;
assign rdpath_data_valid_i =!memc_rd_empty_i ;
assign rdpath_rd_data_i = memc_rd_data_i ;
generate
if (PORT_MODE == "RD_MODE" || PORT_MODE == "BI_MODE")
begin : RD_PATH
read_data_path
#(
.TCQ (TCQ),
.FAMILY (FAMILY) ,
.MEM_TYPE (MEM_TYPE),
.BL_WIDTH (BL_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.START_ADDR (PRBS_SADDR),
.CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES),
.ADDR_WIDTH (ADDR_WIDTH),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_COL_WIDTH (MEM_COL_WIDTH)
)
read_data_path
(
.clk_i (clk_i),
.rst_i (rst_rb),
.manual_clear_error (manual_clear_error),
.cmd_rdy_o (rd_rdy),
.cmd_valid_i (rd_valid),
.memc_cmd_full_i (memc_cmd_full_i),
.prbs_fseed_i (data_seed_i),
.cmd_sent (memc_cmd_instr_o),
.bl_sent (memc_bl_o[5:0]),
.cmd_en_i (cmd_rd_en),
.data_mode_i (data_mode_r_b),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.mode_load_i (mode_load_i),
.addr_i (rd_addr),
.bl_i (rd_bl),
.data_rdy_o (memc_rd_en_o),
.data_valid_i (rdpath_data_valid_i),
.data_i (rdpath_rd_data_i),
.data_error_o (cmp_error),
.cmp_data_valid (cmp_data_valid),
.cmp_data_o (cmp_data),
.rd_mdata_o (mem_rd_data ),
.cmp_addr_o (cmp_addr),
.cmp_bl_o (cmp_bl),
.dq_error_bytelane_cmp (dq_error_bytelane_cmp),
//****************************************************
.cumlative_dq_lane_error_r (cumlative_dq_lane_error),
.cumlative_dq_r0_bit_error_r (cumlative_dq_r0_bit_error),
.cumlative_dq_f0_bit_error_r (cumlative_dq_f0_bit_error),
.cumlative_dq_r1_bit_error_r (cumlative_dq_r1_bit_error),
.cumlative_dq_f1_bit_error_r (cumlative_dq_f1_bit_error),
.dq_r0_bit_error_r (dq_r0_bit_error_r),
.dq_f0_bit_error_r (dq_f0_bit_error_r),
.dq_r1_bit_error_r (dq_r1_bit_error_r),
.dq_f1_bit_error_r (dq_f1_bit_error_r),
.dq_r0_read_bit_r (dq_r0_read_bit),
.dq_f0_read_bit_r (dq_f0_read_bit),
.dq_r1_read_bit_r (dq_r1_read_bit),
.dq_f1_read_bit_r (dq_f1_read_bit),
.dq_r0_expect_bit_r (dq_r0_expect_bit),
.dq_f0_expect_bit_r (dq_f0_expect_bit ),
.dq_r1_expect_bit_r (dq_r1_expect_bit),
.dq_f1_expect_bit_r (dq_f1_expect_bit ),
.error_addr_o (error_addr)
);
end
else
begin
assign cmp_error = 1'b0;
assign cmp_data_valid = 1'b0;
assign cmp_data ='b0;
end
endgenerate
assign wr_path_data_rdy_i = !(memc_wr_full_i );
generate
if (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE")
begin : WR_PATH
write_data_path
#(
.TCQ (TCQ),
.FAMILY (FAMILY),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_TYPE (MEM_TYPE),
.START_ADDR (PRBS_SADDR),
.BL_WIDTH (BL_WIDTH),
.MEM_BURST_LEN (MEM_BURST_LEN),
.ADDR_WIDTH (ADDR_WIDTH),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.EYE_TEST (EYE_TEST)
)
write_data_path
(
.clk_i(clk_i),
.rst_i (rst_rb),
.cmd_rdy_o (wr_rdy),
.cmd_valid_i (wr_valid),
.cmd_validB_i (wr_validB),
.cmd_validC_i (wr_validC),
.prbs_fseed_i (data_seed_i),
.mode_load_i (mode_load_i),
.wr_data_mask_gen_i (wr_data_mask_gen_i),
.mem_init_done_i (mem_init_done),
.data_mode_i (data_mode_r_c),
.last_word_wr_o (last_word_wr),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.addr_i (wr_addr),
.bl_i (wr_bl),
.data_rdy_i (wr_path_data_rdy_i),
.data_valid_o (memc_wr_en),
.data_o (memc_wr_data),
.data_mask_o (memc_wr_mask_o),
.data_wr_end_o (memc_wr_data_end)
);
end
else
begin
assign memc_wr_en = 1'b0;
assign memc_wr_data = 'b0;
assign memc_wr_mask_o = 'b0;
end
endgenerate
generate
if (MEM_TYPE != "QDR2PLUS" && (FAMILY == "VIRTEX6" || FAMILY == "SPARTAN6" ))
begin: nonQDR_WR
assign memc_wr_en_o = memc_wr_en;
assign memc_wr_data_o = memc_wr_data ;
assign memc_wr_data_end_o = (nCK_PER_CLK == 4) ? memc_wr_data_end: memc_wr_data_end;
end
// QDR
else
begin: QDR_WR
always @ (posedge clk_i)
memc_wr_data_r <= memc_wr_data;
assign memc_wr_en_o = memc_wr_en;
assign memc_wr_data_o = memc_wr_data_r ;
assign memc_wr_data_end_o = memc_wr_data_end;
end
endgenerate
//QDR
always @ (posedge clk_i)
begin
if (memc_wr_full_i)
begin
memc_wr_en_r <= 1'b0;
end
else
begin
memc_wr_en_r <= memc_wr_en;
end
end
tg_status
#(
.TCQ (TCQ),
.DWIDTH (DWIDTH)
)
tg_status
(
.clk_i (clk_i),
.rst_i (rst_ra[2]),
.manual_clear_error (manual_clear_error),
.data_error_i (cmp_error),
.cmp_data_i (cmp_data),
.rd_data_i (mem_rd_data ),
.cmp_addr_i (cmp_addr),
.cmp_bl_i (cmp_bl),
.mcb_cmd_full_i (memc_cmd_full_i),
.mcb_wr_full_i (memc_wr_full_i),
.mcb_rd_empty_i (memc_rd_empty_i),
.error_status (error_status),
.error (error)
);
endmodule // memc_traffic_gen
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2_FUNCTIONAL_V
`define SKY130_FD_SC_HD__AND2_FUNCTIONAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22A_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O22A_PP_SYMBOL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o22a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22A_PP_SYMBOL_V
|
module control_o (reset, rxd, StringReady, CharReady, parity, ready, error, WriteChar, WriteString, PossibleStart, clk_2, check);
input rxd;
input StringReady;
input CharReady;
input parity;
input clk_2;
input check;
input reset;
output reg ready;
output reg error;
output reg WriteChar;
output reg WriteString;
output reg PossibleStart;
reg [2:0] current_state;
reg [2:0] next_state;
// se les ponen nombres a los estados para que en el case se pueda entender y manejar mejor
parameter IDLE = 3'b000;
parameter POSSIBLESTART = 3'b001;
parameter READ = 3'b010;
parameter ERROR = 3'b011;
parameter WRITE = 3'b100;
parameter STOP = 3'b101;
always @(current_state or rxd or check or CharReady or StringReady or reset or parity) begin
if (reset==1'b1) begin
next_state <= 3'b000;
ready =1'b0;
error = 1'b0;
WriteString = 1'b0;
WriteChar = 1'b0;
PossibleStart = 1'b0;
end
else begin
case (current_state)
IDLE: begin
if (rxd==1)
next_state<=IDLE;
else
next_state<=POSSIBLESTART;
ready=1'b0;
error=1'b0;
WriteChar=1'b0;
WriteString=1'b0;
PossibleStart=1'b0;
end // case: IDLE
POSSIBLESTART: begin
if (check == 1) begin
if (rxd == 0) begin
next_state<=READ;
end
else
next_state<=IDLE;
end
else
next_state<=POSSIBLESTART;
ready=1'b0;
error=1'b0;
WriteChar=1'b0;
WriteString=1'b0;
PossibleStart=1'b1;
end // case: POSSIBLESTART
READ: begin
if (CharReady==0)
next_state<=READ;
else
next_state<=ERROR;
ready=1'b0;
error=1'b0;
WriteChar=1'b1;
WriteString=1'b0;
PossibleStart=1'b0;
end // case: READ
ERROR: begin
next_state<=WRITE;
if (parity==1)
error=1'b1;
else
error=1'b0;
ready=1'b0;
WriteChar=1'b0;
WriteString=1'b0;
PossibleStart=1'b0;
end // case: ERROR
WRITE: begin
if (StringReady==0)
next_state<=IDLE;
else
next_state<=STOP;
ready=1'b0;
error=1'b0;
WriteChar=1'b0;
WriteString=1'b1;
PossibleStart=1'b0;
end // case: WRITE
STOP: begin
next_state<=IDLE;
ready=1'b1;
error=1'b0;
WriteChar=1'b0;
WriteString=1'b0;
PossibleStart=1'b0;
end // case: STOP
default: begin
next_state<=IDLE;
ready=1'b0;
error=1'b0;
WriteChar=1'b0;
WriteString=1'b0;
PossibleStart=1'b0;
end
endcase // case (current_state)
end // else: !if(reset==1'b1)
end // always @ (posedge clk_2)
always @(negedge clk_2 or posedge reset) begin
if (reset == 1'b1) begin
current_state<=IDLE;
end
else begin
current_state<=next_state;
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/23/2015 05:17:53 PM
// Design Name:
// Module Name: testcase_basic
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////
`include "packet_type.vh"
`include "system.vh"
module testcase_TENC();
localparam X_WIDTH = 5;
localparam Y_WIDTH = 5;
localparam PROC_CYCLES = 16;
localparam TOTAL_PAQUETES = 100000;
localparam TRAFFIC = 10;
//
localparam NODOS_INYECCION = X_WIDTH + X_WIDTH;
localparam STEP = TOTAL_PAQUETES / NODOS_INYECCION;
// -- Instancia de harnes de pruebas ----------------------------- >>>>>
/*
-- Descripcion: Instancia de Nucleo de la red + los modulos source y
sink para la captura y emicion de paquetes de
prueba.
Este arnes incluye deflectores en los puertos del
cuadrante 'x+' y 'y-'.
-- Parametros:
-- X_WIDTH: Numero de nodos en la dimension X de la red.
En otras palabra el numero de nodos por fila
de la red.
-- Y_WIDTH: Numero de nodos en la dimension Y de la red.
En otras palabra el numero de nodos por
columna de la red.
-- PROC_CYCLES: Numero de ciclos de procesamiento que
ejecutara el modulo 'test_engine' de
cada nodo de la red.
*/
harness_TENC
#(
.X_WIDTH (X_WIDTH),
.Y_WIDTH (Y_WIDTH),
.PROC_CYCLES (PROC_CYCLES)
)
arnes
();
// -- variables de simulacion ------------------------------------ >>>>>
integer sum = 0;
/*
-- Descripcion: La variable 'x_deflector' almacena las direcciones
'x' de todos los deflectores de la red. La variable
'y_deflector' lleva a cabo la misma tarea pero con
las direcciones en 'y'.
Las variables 'x_gate' y 'y_gate' cumplen la misma
tarea que las variables anteriormente mencionadas
pero para las 'gate' de salida de la red.
*/
integer x_deflectors [0:NODOS_INYECCION - 1] = {
1,
5,
2,
4,
3,
3,
4,
2,
5,
1
};
integer y_deflectors [0:NODOS_INYECCION - 1] = {
0,
6,
0,
6,
0,
6,
0,
6,
0,
6
};
integer x_gates [0:NODOS_INYECCION - 1] = {
1,
5,
1,
5,
1,
5,
1,
5,
1,
5
};
integer y_gates [0:NODOS_INYECCION - 1] = {
1,
5,
2,
4,
3,
3,
4,
2,
5,
1
};
// -- Generadores de trafico ------------------------------------- >>>>>
genvar index_y;
// -- Generadores de puertos en X- --------------------------- >>>>>
generate
for(index_y = 0; index_y < Y_WIDTH; index_y = index_y + 1)
begin: XNEG_generator
// -- Bloque de inyector para puertos XNEG ----------- >>>>>
initial
begin: xneg_injectors
integer packet_count;
integer dest;
integer gate;
integer traffic_arbiter;
integer seed;
integer packet_serial;
// -- Inicializar Variables ------------------ >>>>>
seed = $stime + (((-1)^(index_y + 2)) * ((Y_WIDTH * STEP) + (index_y * STEP)));
//traffic_arbiter = ({$random(seed)}) % 10;
traffic_arbiter = $urandom(seed) % 10;
//dest = ({$random(seed)}) % NODOS_INYECCION;
//gate = (dest * STEP) % NODOS_INYECCION;
dest = index_y;
gate = index_y;
//packet_serial = 0;
packet_serial = index_y * STEP;
// -- Habilitacion de observador ------------- >>>>>
arnes.xneg_ports[index_y].source.open_observer();
// -- Espera de Reset de la red -------------- >>>>>
@(negedge arnes.reset);
// -- Inicio de ciclo de envio de paquetes --- >>>>>
for (packet_count = (index_y * STEP); packet_count < ((index_y * STEP) + STEP); packet_count = packet_count + 1)
begin
@(posedge arnes.clk)
#(arnes.Thold)
if (traffic_arbiter < TRAFFIC)
begin
arnes.xneg_ports[index_y].packet_generator.network_directed_packet(x_deflectors[dest], y_deflectors[dest], x_gates[gate], y_gates[gate], packet_serial);
arnes.xneg_ports[index_y].source.send_packet(arnes.xneg_ports[index_y].packet_generator.packet);
packet_serial = packet_serial + 1;
end
else
begin
packet_count = packet_count - 1;
end
//traffic_arbiter = (traffic_arbiter + 1) % 10;
traffic_arbiter = $urandom(seed) % 10;
dest = (dest + 1) % NODOS_INYECCION;
gate = (gate + 1) % NODOS_INYECCION;
end
sum = sum + 1;
#(10);
arnes.xneg_ports[index_y].source.close_observer();
end
// -- Observador de salida --------------------------- >>>>>
initial
begin
arnes.xneg_ports[index_y].sink.open_observer();
@(negedge arnes.reset);
@(posedge arnes.clk & sum == (NODOS_INYECCION));
repeat(400)
@(negedge arnes.clk);
arnes.xneg_ports[index_y].sink.close_observer();
end
end
endgenerate
// -- Generadores de puertos en Y+ --------------------------- >>>>>
generate
for(index_y = 0; index_y < Y_WIDTH; index_y = index_y + 1)
begin: XPOS_generator
// -- Bloque de inyector para puertos YPOS ----------- >>>>>
initial
begin: xpos_injectors
integer packet_count;
integer dest;
integer gate;
integer traffic_arbiter;
integer seed;
integer packet_serial;
// -- Inicializar Variables ------------------ >>>>>
seed = $stime + (((-1)^(index_y + 2)) * ((X_WIDTH * STEP) + (index_y * STEP)));
//traffic_arbiter = ({$random(seed)}) % 10;
traffic_arbiter = $urandom(seed) % 10;
//dest = ({$random(seed)}) % NODOS_INYECCION;
//gate = (dest * STEP) % NODOS_INYECCION;
dest = index_y + 5;
gate = index_y + 5;
//packet_serial = 0;
packet_serial = ((Y_WIDTH * STEP) + (index_y * STEP));
// -- Habilitacion de observador ------------- >>>>>
arnes.xpos_ports[index_y].source.open_observer();
// -- Espera de Reset de la red -------------- >>>>>
@(negedge arnes.reset);
// -- Inicio de ciclo de envio de paquetes --- >>>>>
for (packet_count = ((Y_WIDTH * STEP) + (index_y * STEP)); packet_count < ((Y_WIDTH * STEP) + ((index_y + 1) * STEP)); packet_count = packet_count + 1)
begin
@(posedge arnes.clk)
#(arnes.Thold)
if (traffic_arbiter < TRAFFIC)
begin
arnes.xpos_ports[index_y].packet_generator.network_directed_packet(x_deflectors[dest], y_deflectors[dest], x_gates[gate], y_gates[gate], packet_serial);
arnes.xpos_ports[index_y].source.send_packet(arnes.xpos_ports[index_y].packet_generator.packet);
packet_serial = packet_serial + 1;
end
else
begin
packet_count = packet_count - 1;
end
//traffic_arbiter = (traffic_arbiter + 1) % 10;
traffic_arbiter = $urandom(seed) % 10;
dest = (dest + 1) % NODOS_INYECCION;
gate = (gate + 1) % NODOS_INYECCION;
end
sum = sum + 1;
#(10);
arnes.xpos_ports[index_y].source.close_observer();
end
// -- Observador de salida --------------------------- >>>>>
initial
begin
arnes.xpos_ports[index_y].sink.open_observer();
@(negedge arnes.reset);
@(posedge arnes.clk & sum == (NODOS_INYECCION));
repeat(400)
@(negedge arnes.clk);
arnes.xpos_ports[index_y].sink.close_observer();
end
end
endgenerate
initial
begin : ciclo_principal
integer total_recepcion;
integer fp;
arnes.sync_reset();
@(posedge arnes.clk & sum == (NODOS_INYECCION))
// DBG: $display("suma: ", sum);
repeat(800)
@(negedge arnes.clk);
fp = $fopen("reception_resume.dat", "w");
if(!fp)
$display("Could not open reception_resume.dat");
else
$display("Success opening reception_resume.dat");
total_recepcion = arnes.xpos_ports[0].sink.packet_count +
arnes.xpos_ports[1].sink.packet_count +
arnes.xpos_ports[2].sink.packet_count +
arnes.xpos_ports[3].sink.packet_count +
arnes.xpos_ports[4].sink.packet_count +
arnes.xneg_ports[0].sink.packet_count +
arnes.xneg_ports[1].sink.packet_count +
arnes.xneg_ports[2].sink.packet_count +
arnes.xneg_ports[3].sink.packet_count +
arnes.xneg_ports[4].sink.packet_count;
$fdisplay(fp, "%d", arnes.xneg_ports[0].sink.packet_count);
$fdisplay(fp, "%d", arnes.xneg_ports[1].sink.packet_count);
$fdisplay(fp, "%d", arnes.xneg_ports[2].sink.packet_count);
$fdisplay(fp, "%d", arnes.xneg_ports[3].sink.packet_count);
$fdisplay(fp, "%d", arnes.xneg_ports[4].sink.packet_count);
$fdisplay(fp, "%d", arnes.xpos_ports[0].sink.packet_count);
$fdisplay(fp, "%d", arnes.xpos_ports[1].sink.packet_count);
$fdisplay(fp, "%d", arnes.xpos_ports[2].sink.packet_count);
$fdisplay(fp, "%d", arnes.xpos_ports[3].sink.packet_count);
$fdisplay(fp, "%d", arnes.xpos_ports[4].sink.packet_count);
$fclose(fp);
$display("reception_resume.dat se cerro de manera exitosa");
$display("",);
$display("Total de paquetes enviados 'xpos(1,6)': ", arnes.xpos_ports[0].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xpos(2,6)': ", arnes.xpos_ports[1].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xpos(3,6)': ", arnes.xpos_ports[2].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xpos(4,6)': ", arnes.xpos_ports[3].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xpos(5,6)': ", arnes.xpos_ports[4].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xneg(1,0)': ", arnes.xneg_ports[0].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xneg(2,0)': ", arnes.xneg_ports[1].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xneg(3,0)': ", arnes.xneg_ports[2].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xneg(4,0)': ", arnes.xneg_ports[3].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xneg(5,0)': ", arnes.xneg_ports[4].source.packet_count);
$display("",);
$display("",);
$display("",);
$display("",);
$display("",);
$display("Total de paquetes recibidos 'xpos(1,6)': ", arnes.xpos_ports[0].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xpos(2,6)': ", arnes.xpos_ports[1].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xpos(3,6)': ", arnes.xpos_ports[2].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xpos(4,6)': ", arnes.xpos_ports[3].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xpos(5,6)': ", arnes.xpos_ports[4].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xneg(1,0)': ", arnes.xneg_ports[0].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xneg(2,0)': ", arnes.xneg_ports[1].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xneg(3,0)': ", arnes.xneg_ports[2].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xneg(4,0)': ", arnes.xneg_ports[3].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xneg(5,0)': ", arnes.xneg_ports[4].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'testcase': ", total_recepcion);
#(10);
$stop;
$finish;
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__MUX4_BEHAVIORAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_4to2/sky130_fd_sc_lp__udp_mux_4to2.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX4_BEHAVIORAL_PP_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Color Space Conversion, adder. This is a simple adder, but had to be
// pipe-lined for faster clock rates. The delay input is delay-matched to
// the sum pipe-line stages
`timescale 1ps/1ps
module cf_add (
// data_p = data_1 + data_2 + data_3 + data_4 (all the inputs are signed)
clk,
data_1,
data_2,
data_3,
data_4,
data_p,
// ddata_out is internal pipe-line matched for ddata_in
ddata_in,
ddata_out);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
parameter DW = DELAY_DATA_WIDTH - 1;
input clk;
input [24:0] data_1;
input [24:0] data_2;
input [24:0] data_3;
input [24:0] data_4;
output [ 7:0] data_p;
input [DW:0] ddata_in;
output [DW:0] ddata_out;
reg [DW:0] p1_ddata = 'd0;
reg [24:0] p1_data_1 = 'd0;
reg [24:0] p1_data_2 = 'd0;
reg [24:0] p1_data_3 = 'd0;
reg [24:0] p1_data_4 = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [24:0] p2_data_0 = 'd0;
reg [24:0] p2_data_1 = 'd0;
reg [DW:0] p3_ddata = 'd0;
reg [24:0] p3_data = 'd0;
reg [DW:0] ddata_out = 'd0;
reg [ 7:0] data_p = 'd0;
wire [24:0] p1_data_1_p_s;
wire [24:0] p1_data_1_n_s;
wire [24:0] p1_data_1_s;
wire [24:0] p1_data_2_p_s;
wire [24:0] p1_data_2_n_s;
wire [24:0] p1_data_2_s;
wire [24:0] p1_data_3_p_s;
wire [24:0] p1_data_3_n_s;
wire [24:0] p1_data_3_s;
wire [24:0] p1_data_4_p_s;
wire [24:0] p1_data_4_n_s;
wire [24:0] p1_data_4_s;
// pipe line stage 1, get the two's complement versions
assign p1_data_1_p_s = {1'b0, data_1[23:0]};
assign p1_data_1_n_s = ~p1_data_1_p_s + 1'b1;
assign p1_data_1_s = (data_1[24] == 1'b1) ? p1_data_1_n_s : p1_data_1_p_s;
assign p1_data_2_p_s = {1'b0, data_2[23:0]};
assign p1_data_2_n_s = ~p1_data_2_p_s + 1'b1;
assign p1_data_2_s = (data_2[24] == 1'b1) ? p1_data_2_n_s : p1_data_2_p_s;
assign p1_data_3_p_s = {1'b0, data_3[23:0]};
assign p1_data_3_n_s = ~p1_data_3_p_s + 1'b1;
assign p1_data_3_s = (data_3[24] == 1'b1) ? p1_data_3_n_s : p1_data_3_p_s;
assign p1_data_4_p_s = {1'b0, data_4[23:0]};
assign p1_data_4_n_s = ~p1_data_4_p_s + 1'b1;
assign p1_data_4_s = (data_4[24] == 1'b1) ? p1_data_4_n_s : p1_data_4_p_s;
always @(posedge clk) begin
p1_ddata <= ddata_in;
p1_data_1 <= p1_data_1_s;
p1_data_2 <= p1_data_2_s;
p1_data_3 <= p1_data_3_s;
p1_data_4 <= p1_data_4_s;
end
// pipe line stage 2, get the sum (intermediate, 4->2)
always @(posedge clk) begin
p2_ddata <= p1_ddata;
p2_data_0 <= p1_data_1 + p1_data_2;
p2_data_1 <= p1_data_3 + p1_data_4;
end
// pipe line stage 3, get the sum (final, 2->1)
always @(posedge clk) begin
p3_ddata <= p2_ddata;
p3_data <= p2_data_0 + p2_data_1;
end
// output registers, output is unsigned (0 if sum is < 0) and saturated.
// the inputs are expected to be 1.4.20 format (output is 8bits).
always @(posedge clk) begin
ddata_out <= p3_ddata;
if (p3_data[24] == 1'b1) begin
data_p <= 8'h00;
end else if (p3_data[23:20] == 'd0) begin
data_p <= p3_data[19:12];
end else begin
data_p <= 8'hff;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
module lsu
(/*AUTOARG*/
// Outputs
issue_ready,
vgpr_source1_rd_en, vgpr_source2_rd_en,
sgpr_source1_rd_en, sgpr_source2_rd_en,
mem_gm_or_lds, tracemon_gm_or_lds,
vgpr_dest_wr_en,
mem_rd_en, mem_wr_en,
sgpr_dest_wr_en,
exec_rd_wfid,
mem_tag_req,
sgpr_source1_addr, sgpr_source2_addr, sgpr_dest_addr,
vgpr_source1_addr, vgpr_source2_addr, vgpr_dest_addr,
vgpr_dest_wr_mask, mem_wr_mask,
sgpr_dest_data,
mem_addr,
vgpr_dest_data, mem_wr_data, rfa_dest_wr_req,
lsu_done, lsu_done_wfid,
sgpr_instr_done, sgpr_instr_done_wfid,
vgpr_instr_done, vgpr_instr_done_wfid,
tracemon_retire_pc, tracemon_mem_addr, tracemon_idle,
// Inputs
clk, rst, issue_lsu_select, mem_ack, issue_wfid, mem_tag_resp,
issue_source_reg1, issue_source_reg2, issue_source_reg3,
issue_dest_reg, issue_mem_sgpr, issue_imm_value0, issue_lds_base,
issue_imm_value1, issue_opcode, sgpr_source2_data,
exec_rd_m0_value, issue_instr_pc, exec_exec_value,
sgpr_source1_data, vgpr_source2_data, vgpr_source1_data,
mem_rd_data, lsu_stall
);
parameter MEMORY_BUS_WIDTH = 32;
parameter MEM_SLOTS = 1;
input clk;
input rst;
input issue_lsu_select, mem_ack;
input [5:0] issue_wfid;
input [6:0] mem_tag_resp;
input [11:0] issue_source_reg1, issue_source_reg2, issue_source_reg3,
issue_dest_reg, issue_mem_sgpr;
input [15:0] issue_imm_value0, issue_lds_base;
input [31:0] issue_imm_value1, issue_opcode, sgpr_source2_data, exec_rd_m0_value,
issue_instr_pc;
input [63:0] exec_exec_value;
input [127:0] sgpr_source1_data;
input [2047:0] vgpr_source1_data;
input [2047:0] vgpr_source2_data;
input [MEMORY_BUS_WIDTH-1:0] mem_rd_data;
input lsu_stall;
output issue_ready, vgpr_source1_rd_en, vgpr_source2_rd_en,
sgpr_source1_rd_en, sgpr_source2_rd_en, mem_gm_or_lds,
tracemon_gm_or_lds;
output vgpr_dest_wr_en, mem_rd_en, mem_wr_en;
output [3:0] sgpr_dest_wr_en;
output [5:0] exec_rd_wfid;
output [6:0] mem_tag_req;
output [8:0] sgpr_source1_addr, sgpr_source2_addr, sgpr_dest_addr;
output [9:0] vgpr_source1_addr, vgpr_source2_addr, vgpr_dest_addr;
output [63:0] vgpr_dest_wr_mask, mem_wr_mask;
output [127:0] sgpr_dest_data;
output [31:0] mem_addr;
output [2047:0] vgpr_dest_data;
output [MEMORY_BUS_WIDTH-1:0] mem_wr_data;
output rfa_dest_wr_req;
output lsu_done;
output sgpr_instr_done;
output vgpr_instr_done;
output [5:0] lsu_done_wfid;
output [5:0] sgpr_instr_done_wfid;
output [5:0] vgpr_instr_done_wfid;
output [31:0] tracemon_retire_pc;
output [2047:0] tracemon_mem_addr;
output tracemon_idle;
assign exec_rd_wfid = issue_wfid;
reg [31:0] issue_opcode_flopped;
reg [15:0] issue_lds_base_flopped;
reg [15:0] issue_imm_value0_flopped;
wire [2047:0] calc_mem_addr;
wire gm_or_lds;
wire decoded_sgpr_source1_rd_en;
wire decoded_sgpr_source2_rd_en;
wire [8:0] decoded_sgpr_source1_addr;
wire [8:0] decoded_sgpr_source2_addr;
//wire decoded_vgpr_source1_rd_en;
wire decoded_vgpr_source2_rd_en;
wire [9:0] decoded_vgpr_source1_addr;
wire [9:0] decoded_vgpr_source2_addr;
wire [5:0] mem_op_cnt;
wire mem_op_rd;
wire mem_op_wr;
wire mem_gpr;
wire [3:0] sgpr_wr_mask;
wire [1:0] gpr_op_depth;
always@(posedge clk) begin
if(rst) begin
issue_opcode_flopped <= 32'd0;
issue_lds_base_flopped <= 16'd0;
issue_imm_value0_flopped <= 16'd0;
end
else begin
issue_opcode_flopped <= issue_opcode;
issue_lds_base_flopped <= issue_lds_base;
issue_imm_value0_flopped <= issue_imm_value0;
end
end
// The decoder requires two cycles to receive the entire opcode. On the second
// cycle it generates register read operations for getting addres values from
// the GPRs.
lsu_opcode_decoder lsu_opcode_decoder0(
.lsu_selected(issue_lsu_select),
.lsu_opcode(issue_opcode),
.issue_source_reg1(issue_source_reg1),
.issue_source_reg2(issue_source_reg2),
.issue_source_reg3(issue_source_reg3),
.issue_mem_sgpr(issue_mem_sgpr),
//.issue_dest_reg(issue_dest_reg_flopped),
.sgpr_source1_rd_en(decoded_sgpr_source1_rd_en),
.sgpr_source2_rd_en(decoded_sgpr_source2_rd_en),
.sgpr_source1_addr(decoded_sgpr_source1_addr),
.sgpr_source2_addr(decoded_sgpr_source2_addr),
.vgpr_source2_rd_en(decoded_vgpr_source2_rd_en),
.vgpr_source1_addr(decoded_vgpr_source1_addr),
.vgpr_source2_addr(decoded_vgpr_source2_addr),
// Signals to indicate a new memory request
.mem_op_cnt(mem_op_cnt),
.mem_op_rd(mem_op_rd),
.mem_op_wr(mem_op_wr),
.mem_gpr(mem_gpr),
.sgpr_wr_mask(sgpr_wr_mask),
.gpr_op_depth(gpr_op_depth)
);
lsu_op_manager lsu_op_manager0(
.lsu_wfid(issue_wfid),
.instr_pc(issue_instr_pc),
// Signals to indicate a new memory request
.mem_op_cnt(mem_op_cnt),
.mem_op_rd(mem_op_rd),
.mem_op_wr(mem_op_wr),
.mem_gpr(mem_gpr),
.gm_or_lds(gm_or_lds),
.sgpr_wr_mask(sgpr_wr_mask),
.gpr_op_depth(gpr_op_depth),
.exec_mask(exec_exec_value),
.mem_in_addr(calc_mem_addr),
.mem_ack(mem_ack),
.mem_rd_data(mem_rd_data),
.vgpr_source1_data(vgpr_source1_data),
.free_mem_slots(1'b0),
.decoded_sgpr_source1_rd_en(decoded_sgpr_source1_rd_en),
.decoded_sgpr_source2_rd_en(decoded_sgpr_source2_rd_en),
.decoded_sgpr_source1_addr(decoded_sgpr_source1_addr),
.decoded_sgpr_source2_addr(decoded_sgpr_source2_addr),
//decoded_vgpr_source1_rd_en,
.decoded_vgpr_source2_rd_en(decoded_vgpr_source2_rd_en),
.decoded_vgpr_source1_addr(decoded_vgpr_source1_addr),
.decoded_vgpr_source2_addr(decoded_vgpr_source2_addr),
.decoded_dest_addr(issue_dest_reg),
.sgpr_dest_data(sgpr_dest_data),
.sgpr_dest_wr_en(sgpr_dest_wr_en),
.sgpr_dest_addr(sgpr_dest_addr),
.vgpr_dest_data(vgpr_dest_data),
.vgpr_dest_wr_en(vgpr_dest_wr_en),
.vgpr_wr_mask(vgpr_dest_wr_mask),
.vgpr_dest_addr(vgpr_dest_addr),
.lsu_rdy(issue_ready),
.lsu_done(lsu_done),
.sgpr_instr_done(sgpr_instr_done),
.vgpr_instr_done(vgpr_instr_done),
.lsu_done_wfid(lsu_done_wfid),
.sgpr_instr_done_wfid(sgpr_instr_done_wfid),
.vgpr_instr_done_wfid(vgpr_instr_done_wfid),
.retire_pc(tracemon_retire_pc),
.retire_gm_or_lds(tracemon_gm_or_lds),
.tracemon_mem_addr(tracemon_mem_addr),
.mem_rd_en(mem_rd_en),
.mem_wr_en(mem_wr_en),
.mem_out_addr(mem_addr),
.mem_wr_data(mem_wr_data),
.mem_tag_req(mem_tag_req),
.mem_gm_or_lds(mem_gm_or_lds),
.sgpr_source1_rd_en(sgpr_source1_rd_en),
.sgpr_source2_rd_en(sgpr_source2_rd_en),
.sgpr_source1_addr(sgpr_source1_addr),
.sgpr_source2_addr(sgpr_source2_addr),
.vgpr_source1_rd_en(vgpr_source1_rd_en),
.vgpr_source2_rd_en(vgpr_source2_rd_en),
.vgpr_source1_addr(vgpr_source1_addr),
.vgpr_source2_addr(vgpr_source2_addr),
.clk(clk),
.rst(rst)
);
// Because the register read operations for the address values will take one
// cycle to complete the opcode needs to be flopped so that the opcode being
// used by the address calculator is properly aligned.
lsu_addr_calculator addr_calc(
.in_vector_source_b(vgpr_source2_data),
.in_scalar_source_a(sgpr_source1_data),
.in_scalar_source_b(sgpr_source2_data),
.in_opcode(issue_opcode_flopped),
.in_lds_base(issue_lds_base_flopped),
.in_imm_value0(issue_imm_value0_flopped),
.out_ld_st_addr(calc_mem_addr),
.out_gm_or_lds(gm_or_lds)
);
assign rfa_dest_wr_req = (|sgpr_dest_wr_en) | vgpr_dest_wr_en;
// Something of a hack, at this point it's not actually needed
assign mem_wr_mask = vgpr_dest_wr_mask;
assign tracemon_idle = issue_ready;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_data_in #(
// parameters
parameter SINGLE_ENDED = 0,
parameter DEVICE_TYPE = 0,
parameter IODELAY_ENABLE = 1,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// data interface
input rx_clk,
input rx_data_in_p,
input rx_data_in_n,
output rx_data_p,
output rx_data_n,
// delay-data interface
input up_clk,
input up_dld,
input [ 4:0] up_dwdata,
output [ 4:0] up_drdata,
// delay-cntrl interface
input delay_clk,
input delay_rst,
output delay_locked);
// internal parameters
localparam NONE = -1;
localparam VIRTEX7 = 0;
localparam ULTRASCALE_PLUS = 2;
localparam ULTRASCALE = 3;
localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE == 1) ? IODELAY_CTRL : 0;
localparam IODELAY_CTRL_SIM_DEVICE = (DEVICE_TYPE == ULTRASCALE_PLUS) ? "ULTRASCALE" :
(DEVICE_TYPE == ULTRASCALE) ? "ULTRASCALE" : "7SERIES";
localparam IODELAY_DEVICE_TYPE = (IODELAY_ENABLE == 1) ? DEVICE_TYPE : NONE;
localparam IODELAY_SIM_DEVICE = (DEVICE_TYPE == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS" :
(DEVICE_TYPE == ULTRASCALE) ? "ULTRASCALE" : "7SERIES";
// internal signals
wire rx_data_ibuf_s;
wire rx_data_idelay_s;
wire [ 8:0] up_drdata_s;
// delay controller
generate
if (IODELAY_CTRL_ENABLED == 0) begin
assign delay_locked = 1'b1;
end else begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL #(.SIM_DEVICE (IODELAY_CTRL_SIM_DEVICE)) i_delay_ctrl (
.RST (delay_rst),
.REFCLK (delay_clk),
.RDY (delay_locked));
end
endgenerate
// receive data interface, ibuf -> idelay -> iddr
generate
if (SINGLE_ENDED == 1) begin
IBUF i_rx_data_ibuf (
.I (rx_data_in_p),
.O (rx_data_ibuf_s));
end else begin
IBUFDS i_rx_data_ibuf (
.I (rx_data_in_p),
.IB (rx_data_in_n),
.O (rx_data_ibuf_s));
end
endgenerate
// idelay
generate
if (IODELAY_DEVICE_TYPE == VIRTEX7) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_rx_data_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (up_clk),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.LD (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
end
endgenerate
generate
if ((IODELAY_DEVICE_TYPE == ULTRASCALE) || (IODELAY_DEVICE_TYPE == ULTRASCALE_PLUS)) begin
assign up_drdata = up_drdata_s[8:4];
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE3 #(
.SIM_DEVICE (IODELAY_SIM_DEVICE),
.DELAY_SRC ("IDATAIN"),
.DELAY_TYPE ("VAR_LOAD"),
.REFCLK_FREQUENCY (200.0),
.DELAY_FORMAT ("COUNT"))
i_rx_data_idelay (
.CASC_RETURN (1'b0),
.CASC_IN (1'b0),
.CASC_OUT (),
.CE (1'b0),
.CLK (up_clk),
.INC (1'b0),
.LOAD (up_dld),
.CNTVALUEIN ({up_dwdata, 4'd0}),
.CNTVALUEOUT (up_drdata_s),
.DATAIN (1'b0),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.RST (1'b0),
.EN_VTC (~up_dld));
end
endgenerate
generate
if (IODELAY_DEVICE_TYPE == NONE) begin
assign rx_data_idelay_s = rx_data_ibuf_s;
assign up_drdata = 5'd0;
end
endgenerate
// iddr
generate
if ((DEVICE_TYPE == ULTRASCALE) || (DEVICE_TYPE == ULTRASCALE_PLUS)) begin
IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE")) i_rx_data_iddr (
.R (1'b0),
.C (rx_clk),
.CB (~rx_clk),
.D (rx_data_idelay_s),
.Q1 (rx_data_p),
.Q2 (rx_data_n));
end
endgenerate
generate
if (DEVICE_TYPE == VIRTEX7) begin
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE")) i_rx_data_iddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (rx_clk),
.D (rx_data_idelay_s),
.Q1 (rx_data_p),
.Q2 (rx_data_n));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__HA_TB_V
`define SKY130_FD_SC_HS__HA_TB_V
/**
* ha: Half adder.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__ha.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 A = 1'b1;
#120 B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 A = 1'b0;
#200 B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 B = 1'b1;
#320 A = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 B = 1'bx;
#400 A = 1'bx;
end
sky130_fd_sc_hs__ha dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__HA_TB_V
|
///////////////////////////////////////////////////////////////////////////////
// (c) Copyright 2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
///////////////////////////////////////////////////////////////////////////////
//
// SYM_GEN
//
//
// Description: The SYM_GEN module is a symbol generator for 2-byte Aurora Lanes.
// Its inputs request the transmission of specific symbols, and its
// outputs drive the GTP interface to fulfil those requests.
//
// All generation request inputs must be asserted exclusively
// except for the GEN_K, GEN_R and GEN_A signals from the Global
// Logic, and the GEN_PAD and TX_PE_DATA_V signals from TX_LL.
//
// GEN_K, GEN_R and GEN_A can be asserted anytime, but they are
// ignored when other signals are being asserted. This allows the
// idle generator in the Global Logic to run continuosly without
// feedback, but requires the TX_LL and Lane Init SM modules to
// be quiescent during Channel Bonding and Verification.
//
// The GEN_PAD signal is only valid while the TX_PE_DATA_V signal
// is asserted. This allows padding to be specified for the LSB of
// the data transmission. GEN_PAD must not be asserted when
// TX_PE_DATA_V is not asserted - this will generate errors.
//
//
`timescale 1 ns / 1 ps
module aur1_SYM_GEN
(
// TX_LL Interface
GEN_SCP,
GEN_ECP,
GEN_PAD,
TX_PE_DATA,
TX_PE_DATA_V,
GEN_CC,
// Global Logic Interface
GEN_A,
GEN_K,
GEN_R,
GEN_V,
// Lane Init SM Interface
GEN_K_FSM,
GEN_SP_DATA,
GEN_SPA_DATA,
// GTP Interface
TX_CHAR_IS_K,
TX_DATA,
// System Interface
USER_CLK,
RESET
);
`define DLY #1
//***********************************Port Declarations*******************************
// TX_LL Interface // See description for info about GEN_PAD and TX_PE_DATA_V.
input GEN_SCP; // Generate SCP.
input GEN_ECP; // Generate ECP.
input GEN_PAD; // Replace LSB with Pad character.
input [0:15] TX_PE_DATA; // Data. Transmitted when TX_PE_DATA_V is asserted.
input TX_PE_DATA_V; // Transmit data.
input GEN_CC; // Generate Clock Correction symbols.
// Global Logic Interface // See description for info about GEN_K,GEN_R and GEN_A.
input GEN_A; // Generate A character for MSBYTE
input [0:1] GEN_K; // Generate K character for selected bytes.
input [0:1] GEN_R; // Generate R character for selected bytes.
input [0:1] GEN_V; // Generate Ver data character on selected bytes.
// Lane Init SM Interface
input GEN_K_FSM; // Generate K character on byte 0.
input [0:1] GEN_SP_DATA; // Generate SP data character on selected bytes.
input [0:1] GEN_SPA_DATA; // Generate SPA data character on selected bytes.
// GTP Interface
output [1:0] TX_CHAR_IS_K; // Transmit TX_DATA as a control character.
output [15:0] TX_DATA; // Data to GTP for transmission to channel partner.
// System Interface
input USER_CLK; // Clock for all non-GTP Aurora Logic.
input RESET; // RESET signal to drive TX_CHAR_IS_K to known value
//**************************External Register Declarations****************************
reg [15:0] TX_DATA;
reg [1:0] TX_CHAR_IS_K;
//**************************Internal Register Declarations****************************
// Slack registers. Allow slack for routing delay and automatic retiming.
reg gen_scp_r;
reg gen_ecp_r;
reg gen_pad_r;
reg [0:15] tx_pe_data_r;
reg tx_pe_data_v_r;
reg gen_cc_r;
reg gen_a_r;
reg [0:1] gen_k_r;
reg [0:1] gen_r_r;
reg [0:1] gen_v_r;
reg gen_k_fsm_r;
reg [0:1] gen_sp_data_r;
reg [0:1] gen_spa_data_r;
//*********************************Wire Declarations**********************************
wire [0:1] idle_c;
//*********************************Main Body of Code**********************************
// Register all inputs with the slack registers.
always @(posedge USER_CLK)
begin
gen_scp_r <= `DLY GEN_SCP;
gen_ecp_r <= `DLY GEN_ECP;
gen_pad_r <= `DLY GEN_PAD;
tx_pe_data_r <= `DLY TX_PE_DATA;
tx_pe_data_v_r <= `DLY TX_PE_DATA_V;
gen_cc_r <= `DLY GEN_CC;
gen_a_r <= `DLY GEN_A;
gen_k_r <= `DLY GEN_K;
gen_r_r <= `DLY GEN_R;
gen_v_r <= `DLY GEN_V;
gen_k_fsm_r <= `DLY GEN_K_FSM;
gen_sp_data_r <= `DLY GEN_SP_DATA;
gen_spa_data_r <= `DLY GEN_SPA_DATA;
end
// When none of the msb non_idle inputs are asserted, allow idle characters.
assign idle_c[0] = !( gen_scp_r |
gen_ecp_r |
tx_pe_data_v_r |
gen_cc_r |
gen_k_fsm_r |
gen_sp_data_r[0] |
gen_spa_data_r[0] |
gen_v_r[0]
);
// Generate data for MSB. Note that all inputs must be asserted exclusively, except
// for the GEN_A, GEN_K and GEN_R inputs which are ignored when other characters
// are asserted.
always @ (posedge USER_CLK)
begin
if(gen_scp_r) TX_DATA[15:8] <= `DLY 8'h5c; // K28.2(SCP)
if(gen_ecp_r) TX_DATA[15:8] <= `DLY 8'hfd; // K29.7(ECP)
if(tx_pe_data_v_r) TX_DATA[15:8] <= `DLY tx_pe_data_r[0:7]; // DATA
if(gen_cc_r) TX_DATA[15:8] <= `DLY 8'hf7; // K23.7(CC)
if(idle_c[0] & gen_a_r) TX_DATA[15:8] <= `DLY 8'h7c; // K28.3(A)
if(idle_c[0] & gen_k_r[0]) TX_DATA[15:8] <= `DLY 8'hbc; // K28.5(K)
if(idle_c[0] & gen_r_r[0]) TX_DATA[15:8] <= `DLY 8'h1c; // K28.0(R)
if(gen_k_fsm_r) TX_DATA[15:8] <= `DLY 8'hbc; // K28.5(K)
if(gen_sp_data_r[0]) TX_DATA[15:8] <= `DLY 8'h4a; // D10.2(SP data)
if(gen_spa_data_r[0]) TX_DATA[15:8] <= `DLY 8'h2c; // D12.1(SPA data)
if(gen_v_r[0]) TX_DATA[15:8] <= `DLY 8'he8; // D8.7(Ver data)
end
// Generate control signal for MSB.
always @(posedge USER_CLK)
begin
if(RESET)
TX_CHAR_IS_K[1] <= `DLY 1'b0;
else
TX_CHAR_IS_K[1] <= `DLY !( tx_pe_data_v_r |
gen_sp_data_r[0] |
gen_spa_data_r[0] |
gen_v_r[0]
);
end
// When none of the msb non_idle inputs are asserted, allow idle characters. Note that
// because gen_pad is only valid with the data valid signal, we only look at the data
// valid signal.
assign idle_c[1] = !( gen_scp_r |
gen_ecp_r |
tx_pe_data_v_r |
gen_cc_r |
gen_sp_data_r[1] |
gen_spa_data_r[1] |
gen_v_r[1]
);
// Generate data for LSB. Note that all inputs must be asserted exclusively except for
// the GEN_PAD signal and the GEN_K and GEN_R set. GEN_PAD can be asserted
// at the same time as TX_DATA_VALID. This will override TX_DATA and replace the
// lsb user data with a PAD character. The GEN_K and GEN_R inputs are ignored
// if any other input is asserted.
always @ (posedge USER_CLK)
begin
if(gen_scp_r) TX_DATA[7:0] <= `DLY 8'hfb; // K27.7(SCP)
if(gen_ecp_r) TX_DATA[7:0] <= `DLY 8'hfe; // K30.7(ECP)
if(tx_pe_data_v_r & gen_pad_r) TX_DATA[7:0] <= `DLY 8'h9c; // K28.4(PAD)
if(tx_pe_data_v_r & !gen_pad_r) TX_DATA[7:0] <= `DLY tx_pe_data_r[8:15]; // DATA
if(gen_cc_r) TX_DATA[7:0] <= `DLY 8'hf7; // K23.7(CC)
if(idle_c[1] & gen_k_r[1]) TX_DATA[7:0] <= `DLY 8'hbc; // K28.5(K)
if(idle_c[1] & gen_r_r[1]) TX_DATA[7:0] <= `DLY 8'h1c; // K28.0(R)
if(gen_sp_data_r[1]) TX_DATA[7:0] <= `DLY 8'h4a; // D10.2(SP data)
if(gen_spa_data_r[1]) TX_DATA[7:0] <= `DLY 8'h2c; // D12.1(SPA data)
if(gen_v_r[1]) TX_DATA[7:0] <= `DLY 8'he8; // D8.7(Ver data)
end
// Generate control signal for LSB.
always @(posedge USER_CLK)
begin
if(RESET)
TX_CHAR_IS_K[0] <= `DLY 1'b0;
else
TX_CHAR_IS_K[0] <= `DLY !( tx_pe_data_v_r & !gen_pad_r |
gen_sp_data_r[1] |
gen_spa_data_r[1] |
gen_v_r[1]
);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S15_BEHAVIORAL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S15_BEHAVIORAL_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s15 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S15_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSBP_2_V
`define SKY130_FD_SC_HS__SDFSBP_2_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfsbp_2 (
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfsbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfsbp_2 (
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE ,
SET_B
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfsbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSBP_2_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// iq correction = a*(i+x) + b*(q+y); offsets are added in dcfilter.
// if SCALE_ONLY is set to 1, b*(q+y) is set to 0, and the module is used for
// scale correction of channel I
`timescale 1ns/100ps
module ad_iqcor #(
// select i/q if disabled
parameter Q_OR_I_N = 0,
parameter SCALE_ONLY = 0,
parameter DISABLE = 0) (
// data interface
input clk,
input valid,
input [15:0] data_in,
input [15:0] data_iq,
output valid_out,
output [15:0] data_out,
// control interface
input iqcor_enable,
input [15:0] iqcor_coeff_1,
input [15:0] iqcor_coeff_2);
// internal registers
reg p1_valid = 'd0;
reg [33:0] p1_data_p = 'd0;
reg valid_int = 'd0;
reg [15:0] data_int = 'd0;
reg [15:0] iqcor_coeff_1_r = 'd0;
reg [15:0] iqcor_coeff_2_r = 'd0;
// internal signals
wire [15:0] data_i_s;
wire [15:0] data_q_s;
wire [33:0] p1_data_p_i_s;
wire p1_valid_s;
wire [15:0] p1_data_i_s;
wire [33:0] p1_data_p_q_s;
wire [15:0] p1_data_q_s;
wire [15:0] p1_data_i_int;
wire [15:0] p1_data_q_int;
// data-path disable
generate
if (DISABLE == 1) begin
assign valid_out = valid;
assign data_out = data_in;
end else begin
assign valid_out = valid_int;
assign data_out = data_int;
end
endgenerate
// swap i & q
assign data_i_s = (Q_OR_I_N == 1 && SCALE_ONLY == 1'b0) ? data_iq : data_in;
assign data_q_s = (Q_OR_I_N == 1) ? data_in : data_iq;
// coefficients are flopped to remove warnings from vivado
always @(posedge clk) begin
iqcor_coeff_1_r <= iqcor_coeff_1;
iqcor_coeff_2_r <= iqcor_coeff_2;
end
// scaling functions - i
ad_mul #(.DELAY_DATA_WIDTH(17)) i_mul_i (
.clk (clk),
.data_a ({data_i_s[15], data_i_s}),
.data_b ({iqcor_coeff_1_r[15], iqcor_coeff_1_r}),
.data_p (p1_data_p_i_s),
.ddata_in ({valid, data_i_s}),
.ddata_out ({p1_valid_s, p1_data_i_s}));
generate
if (SCALE_ONLY == 0) begin
// scaling functions - q
ad_mul #(.DELAY_DATA_WIDTH(16)) i_mul_q (
.clk (clk),
.data_a ({data_q_s[15], data_q_s}),
.data_b ({iqcor_coeff_2_r[15], iqcor_coeff_2_r}),
.data_p (p1_data_p_q_s),
.ddata_in (data_q_s),
.ddata_out (p1_data_q_s));
// sum
end else begin
assign p1_data_p_q_s = 34'h0;
assign p1_data_q_s = 16'h0;
end
endgenerate
generate
if (Q_OR_I_N == 1 && SCALE_ONLY == 0) begin
reg [15:0] p1_data_q = 'd0;
always @(posedge clk) begin
p1_data_q <= p1_data_q_s;
end
assign p1_data_i_int = 16'h0;
assign p1_data_q_int = p1_data_q;
// sum
end else begin
reg [15:0] p1_data_i = 'd0;
always @(posedge clk) begin
p1_data_i <= p1_data_i_s;
end
assign p1_data_i_int = p1_data_i;
assign p1_data_q_int = 16'h0;
end
endgenerate
always @(posedge clk) begin
p1_valid <= p1_valid_s;
p1_data_p <= p1_data_p_i_s + p1_data_p_q_s;
end
// output registers
always @(posedge clk) begin
valid_int <= p1_valid;
if (iqcor_enable == 1'b1) begin
data_int <= p1_data_p[29:14];
end else if (Q_OR_I_N == 1 && SCALE_ONLY == 0) begin
data_int <= p1_data_q_int;
end else begin
data_int <= p1_data_i_int;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
//this code demodulates and modulates signal as described in ISO/IEC 18092. That includes packets used for Felica, NFC Tag 3, etc. (which do overlap)
//simple envelope following algorithm is used (modification of fail0verflow LF one) is used to combat some nasty aliasing effect with testing phone (envelope looked like sine wave)
// only 212 kbps (fc/64) for now 414 is relatively straightforward... though for reader, the selection has to come from ARM
// modulation waits for
//market sprocket -doesn't really mean anything ;)
//redefining mod_type: bits 210: bit 2 - reader drive/power on/off, bit 1 - speed bit, 0:212, 1 -424 bit 0: listen or modulate
module hi_flite(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
mod_type // used
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [2:0] mod_type; // used.
assign dbg=0;
wire power= mod_type[2];
wire speed= mod_type[1];
wire disabl= mod_type[0];
// Most off, oe4 for modulation;
// Trying reader emulation (would presumably just require switching power on, but I am not sure)
//;// 1'b0;
assign pwr_lo = 1'b0;
//512x64/fc -wait before ts0, 32768 ticks
//tslot: 256*64/fc
assign adc_clk = ck_1356meg;
///heuristic values for initial thresholds. seem to work OK
`define imin 70//(13'd256)
`define imax 180//(-13'd256)
`define ithrmin 91//-13'd8
`define ithrmax 160// 13'd8
`define min_bitdelay_212 8
//minimum values and corresponding thresholds
reg [8:0] curmin=`imin;
reg [8:0] curminthres=`ithrmin;
reg [8:0] curmaxthres=`ithrmax;
reg [8:0] curmax=`imax;
//signal state, 1-not modulated, 0 -modulated
reg after_hysteresis = 1'b1;
//state machine for envelope tracking
reg [1:0] state=1'd0;
//lower edge detected, trying to detect first bit of SYNC (b24d, 1011001001001101)
reg try_sync=1'b0;
//detected first sync bit, phase frozen
reg did_sync=0;
`define bithalf_212 32 //half-bit length for 212 kbit
`define bitmlen_212 63 //bit transition edge
`define bithalf_424 16 //half-bit length for 212 kbit
`define bitmlen_424 31 //bit transition edge
wire [7:0]bithalf= speed ? `bithalf_424 : `bithalf_212;
wire [7:0]bitmlen= speed ? `bitmlen_424 : `bitmlen_212;
//ssp clock and current values
reg ssp_clk;
reg ssp_frame;
reg curbit=1'b0;
reg [7:0] fccount=8'd0; // in-bit tick counter. Counts carrier cycles from the first lower edge detected, reset on every manchester bit detected
reg [7:0] tsinceedge=8'd0;// ticks from last edge, desync if the valye is too large
reg zero=1'b0; // Manchester first halfbit low second high corresponds to this value. It has been known to change. SYNC is used to set it
//ssp counter for transfer and framing
reg [8:0] ssp_cnt=9'd0;
always @(posedge adc_clk)
ssp_cnt <= (ssp_cnt + 1);
//maybe change it so that ARM sends preamble as well.
//then: ready bits sent to ARM, 8 bits sent from ARM (all ones), then preamble (all zeros, presumably) - which starts modulation
always @(negedge adc_clk)
begin
//count fc/64 - transfer bits to ARM at the rate they are received
if( ((~speed) && (ssp_cnt[5:0] == 6'b000000)) || (speed &&(ssp_cnt[4:0] == 5'b00000)))
begin
ssp_clk <= 1'b1;
// if(mod_type[2])
// begin
// ssp_din<=outp[0];//after_hysteresis;
//outp<={1'b0,outp[7:1]};
// end
// else
ssp_din <= curbit;
//sample ssp_dout
end
if( ( (~speed) && (ssp_cnt[5:0] == 6'b100000)) ||(speed && ssp_cnt[4:0] == 5'b10000))
ssp_clk <= 1'b0;
//create frame pulses. TBH, I still don't know what they do exactly, but they are crucial for ARM->FPGA transfer. If the frame is in the beginning of the byte, transfer slows to a crawl for some reason
// took me a day to figure THAT out.
if(( (~speed) && (ssp_cnt[8:0] == 9'd31))||(speed && ssp_cnt[7:0] == 8'd15))
begin
ssp_frame <= 1'b1;
end
if(( (~speed) && (ssp_cnt[8:0] == 9'b1011111))||(speed &&ssp_cnt[7:0] == 8'b101111) )
begin
ssp_frame <= 1'b0;
end
end
//send current bit (detected in SNIFF mode or the one being modulated in MOD mode, 0 otherwise)
reg ssp_din;//= outp[0];
//previous signal value, mostly to detect SYNC
reg prv =1'b1;
reg[7:0] mid=8'd128; //for simple error correction in mod/demod detection, use maximum of modded/demodded in given interval. Maybe 1 bit is extra? but better safe than sorry.
// set TAGSIM__MODULATE on ARM if we want to write... (frame would get lost if done mid-frame...)
// start sending over 1s on ssp->arm when we start sending preamble
reg counting_desync=1'b0; // are we counting bits since last frame?
reg sending=1'b0; // are we actively modulating?
reg [11:0] bit_counts=12'd0;///for timeslots... only support ts=0 for now, at 212 speed -512 fullbits from end of frame. One hopes. might remove those?
//reg [2:0]old_mod;
//always @(mod_type) //when moving from modulate_mode
//begin
//if (mod_type[2]==1&&old_mod[2]==0)
// bit_counts=0;
//old_mod=mod_type;
//end
//we need some way to flush bit_counts triggers on mod_type changes don't compile
reg dlay;
always @(negedge adc_clk) //every data ping?
begin
//envelope follow code...
////////////
//move the counter to the outside...
// if (adc_d>=curminthres||try_sync)
if(fccount==bitmlen)
begin
if((~try_sync)&&(adc_d<curminthres)&&disabl )
begin
fccount<=1;
end
else
begin
fccount<=0;
end
// if (counting_desync)
// begin
dlay<=ssp_dout;
if(bit_counts>768) // should be over ts0 now, without ARM interference... stop counting...
begin
bit_counts<=0;
// counting_desync<=0;
end
else
if((power))
bit_counts<=0;
else
bit_counts<=bit_counts+1;
// end
end
else
begin
if((~try_sync)&&(adc_d<curminthres) &&disabl)
begin
fccount<=1;
end
else
begin
fccount<=fccount+1;
end
end
if (adc_d>curmaxthres) //rising edge
begin
case (state)
0: begin
curmax <= adc_d>`imax? adc_d :`imax;
state <= 2;
end
1: begin
curminthres <= ( (curmin>>1)+(curmin>>2)+(curmin>>4)+(curmax>>3)+(curmax>>4)); //threshold: 0.1875 max + 0.8125 min
curmaxthres <= ( (curmax>>1)+(curmax>>2)+(curmax>>4)+(curmin>>3)+(curmin>>4));
curmax <= adc_d>155? adc_d :155; // to hopefully prevent overflow from spikes going up to 255
state <= 2;
end
2: begin
if (adc_d>curmax)
curmax <= adc_d;
end
default:
begin
end
endcase
after_hysteresis <=1'b1;
if(try_sync)
tsinceedge<=0;
end
else if (adc_d<curminthres) //falling edge
begin
case (state)
0: begin
curmin <=adc_d<`imin? adc_d :`imin;
state <=1;
end
1: begin
if (adc_d<curmin)
curmin <= adc_d;
end
2: begin
curminthres <= ( (curmin>>1)+(curmin>>2)+(curmin>>4)+(curmax>>3)+(curmax>>4));
curmaxthres <= ( (curmax>>1)+(curmax>>2)+(curmax>>4)+(curmin>>3)+(curmin>>4));
curmin <=adc_d<`imin? adc_d :`imin;
state <=1;
end
default:
begin
end
endcase
after_hysteresis <=0;
if (~try_sync ) //begin modulation, lower edge...
begin
try_sync <=1;
//counting_desync<=1'b0;
fccount <= 1;
did_sync<=0;
curbit<=0;
mid <=8'd127;
tsinceedge<=0;
prv <=1;
end
else
begin
tsinceedge<=0;
end
end
else //stable state, low or high
begin
curminthres <= ( (curmin>>1)+(curmin>>2)+(curmin>>4)+(curmax>>3)+(curmax>>4));
curmaxthres <= ( (curmax>>1)+(curmax>>2)+(curmax>>4)+(curmin>>3)+(curmin>>4));
state <=0;
if (try_sync )
begin
if (tsinceedge>=(128))
begin
//we might need to start counting... assuming ARM wants to reply to the frame.
// counting_desync<=1'b1;
bit_counts<=1;// i think? 128 is about 2 bits passed... but 1 also works
try_sync<=0;
did_sync<=0;//desync
curmin <=`imin; //reset envelope
curmax <=`imax;
curminthres <=`ithrmin;
curmaxthres <=`ithrmax;
prv <=1;
tsinceedge <=0;
after_hysteresis <=1'b1;
curbit <=0;
mid <=8'd128;
end
else
tsinceedge<=(tsinceedge+1);
end
end
if (try_sync && tsinceedge<128)
begin
//detect bits in their middle ssp sampling is in sync, so it would sample all bits in order
if (fccount==bithalf)
begin
if ((~did_sync) && ((prv==1&&(mid>128))||(prv==0&&(mid<=128))))
begin
//sync the Zero, and set curbit roperly
did_sync <=1'b1;
zero <= ~prv;// 1-prv
curbit <=1;
end
else
curbit <= (mid>128) ? (~zero):zero;
prv <=(mid>128) ?1:0;
if(adc_d>curmaxthres)
mid <=8'd129;
else if (adc_d<curminthres)
mid <=8'd127;
else
begin
if (after_hysteresis)
begin
mid <=8'd129;
end
else
begin
mid<=8'd127;
end
end
end
else
begin
if (fccount==bitmlen)
begin
// fccount <=0;
prv <=(mid>128)?1:0;
mid <=128;
end
else
begin
// minimum-maximum calc
if(adc_d>curmaxthres)
mid <=mid+1;
else if (adc_d<curminthres)
mid <=mid-1;
else
begin
if (after_hysteresis)
begin
mid <=mid+1;
end
else
begin
mid<=mid-1;
end
end
end
end
end
else
begin
end
sending <=0;
end
//put modulation here to maintain the correct clock. Seems that some readers are sensitive to that
reg pwr_hi;
reg pwr_oe1;
reg pwr_oe2;
reg pwr_oe3;
reg pwr_oe4;
wire mod=((fccount>=bithalf)^dlay)&(~disabl);
always @(ck_1356megb or ssp_dout or power or disabl or mod)
begin
if (power)
begin
pwr_hi <= ck_1356megb;
pwr_oe1 <= 1'b0;//mod;
pwr_oe2 <= 1'b0;//mod;
pwr_oe3 <= 1'b0;//mod;
pwr_oe4 <= mod;//1'b0;
end
else
begin
pwr_hi <= 1'b0;
pwr_oe1 <= 1'b0;
pwr_oe2 <= 1'b0;
pwr_oe3 <= 1'b0;
pwr_oe4 <= mod;
end
end
//assign pwr_oe4 = 1'b0;// mod_sig_coil & (modulate_mode)&sending & (~mod_type[2]);
//try shallow mod for reader?
//assign pwr_hi= (mod_type[2]) & ck_1356megb;
//assign pwr_oe1= 1'b0; //mod_sig_coil & (modulate_mode)&sending & (mod_type[2]);
//assign pwr_oe2 = 1'b0;// mod_sig_coil & (modulate_mode)&sending & (mod_type[2]);
//assign pwr_oe3 = 1'b0; //mod_sig_coil & (modulate_mode)&sending & (mod_type[2]);
endmodule
|
// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 190 at 2017.03.21.23:05:17
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_7"),
.ENUM_MEM_IF_TCWL ("TCWL_7"),
.ENUM_MEM_IF_TFAW ("TFAW_15"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (120),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__SDLCLKP_FUNCTIONAL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_ms__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_ms__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_ms__udp_dlatch$P dlatch0 (m0 , SCE_GATE, clkn );
and and0 (GCLK , m0n, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDLCLKP_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND2_1_V
`define SKY130_FD_SC_HS__TAPVGND2_1_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog wrapper for tapvgnd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__tapvgnd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__tapvgnd2_1 (
VPWR,
VGND
);
input VPWR;
input VGND;
sky130_fd_sc_hs__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__tapvgnd2_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__tapvgnd2 base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND2_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2B_4_V
`define SKY130_FD_SC_MS__NOR2B_4_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor2b_4 (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor2b_4 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2B_4_V
|
`timescale 1 ps / 1 ps
module ram_r(
input clk,
input rst,
output wire[ADD_WIDTH-1:0] ram_r_address,
input ram_r_waitrequest,
input ram_r_readdatavalid,
output wire[BYTE_ENABLE_WIDTH-1:0] ram_r_byteenable,
output wire ram_r_read,
input wire[DATA_WIDTH-1:0] ram_r_readdata,
output wire[BURST_WIDTH_R-1:0] ram_r_burstcount,
output wire [DATA_WIDTH-1:0] data_fifo_in,
input read_fifo_in,
input start_fifo_in,
input [ADD_WIDTH-1:0] address_fifo_in,
input [DATA_WIDTH-1:0] n_burst_fifo_in,
output wire bussy_fifo_in,
output wire empty_fifo_in,
output wire [FIFO_DEPTH_LOG2:0] usedw_fifo_in
);
parameter DATA_WIDTH = 32;
parameter ADD_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4; // derived parameter
parameter MAX_BURST_COUNT_R = 32; // must be a multiple of 2 between 2 and 1024, when bursting is disabled this value must be set to 1
parameter BURST_WIDTH_R = 6;
parameter FIFO_DEPTH_LOG2 = 8;
parameter FIFO_DEPTH = 256;
wire read_complete;
reg [DATA_WIDTH-1:0] reads_pending;
wire read_burst_end;
reg next_r;
wire too_many_reads_pending;
reg [ADD_WIDTH-1:0] read_address;
reg [DATA_WIDTH-1:0] in_n;
reg [DATA_WIDTH-1:0] in_n_2;
wire fifo_full;
wire fifo_empty;
wire [FIFO_DEPTH_LOG2:0] fifo_used;
scfifo master_to_st_fifo(
.aclr(start_fifo_in),
.clock(clk),
.data(ram_r_readdata),
.wrreq(read_complete),
.q(data_fifo_in),
.rdreq(read_fifo_in),
.full(fifo_full),
.empty(fifo_empty),
.usedw(fifo_used[FIFO_DEPTH_LOG2-1:0])
);
defparam master_to_st_fifo.lpm_width = DATA_WIDTH;
defparam master_to_st_fifo.lpm_numwords = FIFO_DEPTH;
defparam master_to_st_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam master_to_st_fifo.lpm_showahead = "ON";
defparam master_to_st_fifo.use_eab = "ON";
defparam master_to_st_fifo.add_ram_output_register = "OFF"; // FIFO latency of 2
defparam master_to_st_fifo.underflow_checking = "OFF";
defparam master_to_st_fifo.overflow_checking = "OFF";
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
in_n <= 0;
end else begin
if (start_fifo_in == 1) begin
in_n <= n_burst_fifo_in * MAX_BURST_COUNT_R;
end else begin
if (read_complete == 1) begin
in_n <= in_n - 1;
end
end
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
in_n_2 <= 0;
end else begin
if (start_fifo_in == 1) begin
in_n_2 <= n_burst_fifo_in * MAX_BURST_COUNT_R;
end else begin
if (read_burst_end == 1) begin
in_n_2 <= in_n_2 - MAX_BURST_COUNT_R;
end
end
end
end
always @(posedge clk) begin
if (start_fifo_in == 1) begin
read_address <= address_fifo_in;
end else begin
if (read_burst_end == 1) begin
read_address <= read_address + MAX_BURST_COUNT_R * BYTE_ENABLE_WIDTH;
end
end
end
// tracking FIFO
always @ (posedge clk) begin
if (start_fifo_in == 1) begin
reads_pending <= 0;
end else begin
if(read_burst_end == 1) begin
if(ram_r_readdatavalid == 0) begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R;
end else begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R - 1; // a burst read was posted, but a word returned
end
end else begin
if(ram_r_readdatavalid == 0) begin
reads_pending <= reads_pending; // burst read was not posted and no read returned
end else begin
reads_pending <= reads_pending - 1; // burst read was not posted but a word returned
end
end
end
end
always @ (posedge clk) begin
if (start_fifo_in == 1) begin
next_r <= 0;
end else begin
if(read_burst_end == 1) begin
next_r <= 0;
end else begin
if (ram_r_read == 1) begin
next_r <= 1;
end
end
end
end
assign read_complete = (ram_r_readdatavalid == 1);
assign read_burst_end = (ram_r_waitrequest == 0) & (next_r == 1);// & (header_c > 4);
assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFO_DEPTH - MAX_BURST_COUNT_R - 4); // make sure there are fewer reads posted than room in the FIFO
assign ram_r_address = read_address;
assign ram_r_read = (too_many_reads_pending == 0) & (in_n_2 != 0);// & (header_c > 4);
assign ram_r_byteenable = {BYTE_ENABLE_WIDTH{1'b1}};
assign ram_r_burstcount = MAX_BURST_COUNT_R;
assign bussy_fifo_in = in_n != 0;
assign empty_fifo_in = fifo_empty;
assign usedw_fifo_in = fifo_used;
endmodule
|
// ------------------------------------------------------------------------- //
// pdatapath_top.v
//
// This is our top module. This module connects all individual elements to form
// a complete MIPS datapath.
//
// Alex Interrante-Grant
// James Massucco
// 11/13/2015
// ------------------------------------------------------------------------- //
`timescale 1ns / 1ps
module pdatapath_top(
input wire clk,
input wire top_pb_clk,
input wire right_pb_rst_general
);
wire [7:0] alu_1st_input, alu_2nd_input;
wire [7:0] alu_output;
wire [2:0] ALUOp;
wire alu_ovf_flag;
wire alu_zero_output;
wire [15:0] instruction;
//insturction fields
wire [3:0] opcode;
wire [1:0] rs_addr;
wire [1:0] rt_addr;
wire [1:0] rd_addr;
wire [7:0] immediate;
//control signals
wire RegDst;
wire RegWrite;
wire ALUSrc1;
wire ALUSrc2;
wire MemWrite;
wire MemToReg;
wire [1:0] regfile_write_address;//destination register address
wire [8:0] regfile_write_data;//result data
wire [8:0] read_data1;//source register1 data
wire [8:0] read_data2;//source register2 data
wire [8:0] alu_result;
wire [8:0] zero_register;
wire [8:0] data_mem_out;
wire pb_clk_debounced;
wire [7:0] pc;
debounce debounce_clk(
.clk_in(clk),
.rst_in(right_pb_rst_general),
.sig_in(top_pb_clk),
.sig_debounced_out(pb_clk_debounced)
);
inst_decoder instruction_decoder (
.instruction(instruction),
.opcode(opcode),
.rs_addr(rs_addr),
.rt_addr(rt_addr),
.rd_addr(rd_addr),
.immediate(immediate),
.RegDst(RegDst),
.RegWrite(RegWrite),
.ALUSrc1(ALUSrc1),
.ALUSrc2(ALUSrc2),
.ALUOp(ALUOp),
.MemWrite(MemWrite),
.MemToReg(MemToReg)
);
//Select the right signal for the ALU's first input
assign alu_1st_input = ALUSrc1 ? zero_register[7:0] : read_data1[7:0];
//Select the right signal for the ALU's second input
assign alu_2nd_input = ALUSrc2 ? immediate[7:0] : read_data2[7:0];
assign zero_register = 8'b0;//ZERO constant
//ALU
eightbit_alu alu (
.a(alu_1st_input),
.b(alu_2nd_input),
.sel(ALUOp),
.f(alu_output),
.ovf(alu_ovf_flag),
.zero(alu_zero_output)
);
//VIO Module
vio_0 vio_core (
.clk(clk), // input wire clk
.probe_in0(alu_output), // input wire [7 : 0] probe_in0
.probe_in1(alu_ovf_flag), // input wire [0 : 0] probe_in1
.probe_in2(alu_zero_output), // input wire [0 : 0] probe_in2
.probe_in3(read_data1), // input wire [7 : 0] probe_in3
.probe_in4(read_data2), // input wire [7 : 0] probe_in4
.probe_in5(alu_1st_input), // input wire [7 : 0] probe_in5
.probe_in6(alu_2nd_input), // input wire [7 : 0] probe_in6
.probe_in7(read_data2), // input wire [8 : 0] probe_in7
.probe_in8(data_mem_out), // input wire [8 : 0] probe_in8
.probe_in9(opcode), // input wire [2 : 0] probe_in9
.probe_in10(rs_addr), // input wire [1 : 0] probe_in10
.probe_in11(rt_addr), // input wire [1 : 0] probe_in11
.probe_in12(rd_addr), // input wire [1 : 0] probe_in12
.probe_in13(immediate), // input wire [7 : 0] probe_in13
.probe_in14(RegDst), // input wire [0 : 0] probe_in14
.probe_in15(RegWrite), // input wire [0 : 0] probe_in15
.probe_in16(ALUSrc1), // input wire [0 : 0] probe_in16
.probe_in17(ALUSrc2), // input wire [0 : 0] probe_in17
.probe_in18(ALUOp), // input wire [0 : 0] probe_in18
.probe_in19(MemWrite), // input wire [0 : 0] probe_in19
.probe_in20(MemToReg), // input wire [0 : 0] probe_in20
.probe_in21(pc), // input wire [7 : 0] probe_in21
.probe_in22(instruction) // input wire [15 : 0] probe_in22
);
assign alu_result = {alu_ovf_flag, alu_output};
//Select the right signal for the register file write data
assign regfile_write_data = MemToReg ? data_mem_out : alu_result;
//Select the right signal for the register file write address
assign regfile_write_address = RegDst ? rd_addr : rt_addr;
reg_file register_file (
.rst(right_pb_rst_general),//reset
.clk(pb_clk_debounced),//clock
.wr_en(RegWrite),//Write enable
.rd0_addr(rs_addr),//source register1 address
.rd1_addr(rt_addr),//source register2 address
.wr_addr(regfile_write_address),//destination register address
.wr_data(regfile_write_data),//result data
.rd0_data(read_data1),//source register1 data
.rd1_data(read_data2)//source register2 data
);
data_memory_take2 data_memory (
.a(alu_output), // input wire [7 : 0] a
.d(read_data2), // input wire [8 : 0] d
.clk(pb_clk_debounced), // input wire clk
.we(MemWrite), // input wire we
.spo(data_mem_out) // output wire [8 : 0] spo
);
program_counter program_counter(
.clk(pb_clk_debounced),
.rst(right_pb_rst_general),
.branch_offs(immediate),
.ALU_zero(alu_zero_output),
.value(pc)
);
instr_memory inst_memory (
.clka(pb_clk_debounced), // input wire clka
.rsta(right_pb_rst_general), // input wire rsta
.addra(pc), // input wire [7 : 0] addra
.douta(instruction) ); //ire [15 : 0] douta
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: CacheBlockRAM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 232 07/05/2012 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module CacheBlockRAM (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [8:0] address_a;
input [8:0] address_b;
input clock;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [17:0] sub_wire0;
wire [17:0] sub_wire1;
wire [17:0] q_a = sub_wire0[17:0];
wire [17:0] q_b = sub_wire1[17:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (wren_a),
.address_b (address_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 18,
altsyncram_component.width_b = 18,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "9216"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]"
// Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]"
// Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]"
// Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0
// Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0
// Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_4_V
`define SKY130_FD_SC_LP__NAND2B_4_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2b_4 (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2b_4 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR2_BLACKBOX_V
`define SKY130_FD_SC_MS__XOR2_BLACKBOX_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__xor2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR2_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHE_18_V
`define SKY130_FD_SC_LS__DECAPHE_18_V
/**
* decaphe: Shielded Decoupling capacitance filler.
*
* Verilog wrapper for decaphe with size of 18 units (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decaphe.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphe_18 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__decaphe base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphe_18 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__decaphe base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHE_18_V
|
`include "i2c_master.v"
`include "i2c_probe.v"
`include "i2c_scan.v"
`include "simpleuart.v"
`default_nettype none
// ============================================================================
module top
(
input wire clk,
input wire [15:0] sw,
output wire [15:0] led,
input wire rx,
output wire tx,
inout wire jc1, // sda
inout wire jc2, // scl
output wire jc3, // unused
input wire jc4 // unused
);
// ============================================================================
// IOBUFs
wire sda_i;
wire sda_o;
wire sda_t;
wire scl_i;
wire scl_o;
wire scl_t;
IOBUF # (
.IOSTANDARD("LVCMOS33"),
.DRIVE(12),
.SLEW("SLOW")
)
iobuf_sda
(
.I (sda_i),
.O (sda_o),
.T (sda_t),
.IO (jc1)
);
IOBUF # (
.IOSTANDARD("LVCMOS33"),
.DRIVE(12),
.SLEW("SLOW")
)
iobuf_scl
(
.I (scl_i),
.O (scl_o),
.T (scl_t),
.IO (jc2)
);
// ============================================================================
// Clock buffer, reset generator
reg [3:0] rst_sr;
wire rst;
wire clk_g;
initial rst_sr <= 4'hF;
always @(posedge clk_g)
if (sw[0]) rst_sr <= 4'hF;
else rst_sr = {1'b0, rst_sr[3:1]};
assign rst = rst_sr[0];
wire clk_ibuf;
IBUF ibuf (.I(clk), .O(clk_ibuf));
BUFG bufg (.I(clk_ibuf), .O(clk_g));
// ============================================================================
// I2C scanner
wire i2c_scan_trg;
wire i2c_scan_trg_en;
wire i2c_scan_bsy;
// Button synchronizer
reg [3:0] i2c_scan_trg_en_sr;
initial i2c_scan_trg_en_sr <= 4'h0;
always @(posedge clk_g)
i2c_scan_trg_en_sr <= {sw[1], i2c_scan_trg_en_sr[3:1]};
// The scanner
i2c_scan #
(
.UART_PRESCALER (868), // 115200 @100MHz
.I2C_PRESCALER (250) // 100kHz @100MHz
)
i2c_scan
(
.clk (clk_g),
.rst (rst),
.scl_i (scl_o),
.scl_o (scl_i),
.scl_t (scl_t),
.sda_i (sda_o),
.sda_o (sda_i),
.sda_t (sda_t),
.rx (rx),
.tx (tx),
.i_trg (i2c_scan_trg & i2c_scan_trg_en_sr[0]),
.i_bsy (i2c_scan_bsy)
);
// Trigger generator
reg [32:0] trg_cnt;
always @(posedge clk_g)
if (rst) trg_cnt <= 0;
else if (trg_cnt[32]) trg_cnt <= 1 * 100000000; // 1s @100MHz
else trg_cnt <= trg_cnt - 1;
assign i2c_scan_trg = trg_cnt[32];
// ============================================================================
// I/O
assign led[0] = rst;
assign led[1] = i2c_scan_bsy;
assign led[15:2] = sw[15:2];
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:46:45 2016
/////////////////////////////////////////////////////////////
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire n7077, NaN_reg, ready_add_subt, underflow_flag_mult,
overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_d_ff3_sign_out, FPSENCOS_d_ff1_operation_out,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A,
FPMULT_FSM_exp_operation_A_S, FPMULT_FSM_add_overflow_flag,
FPMULT_zero_flag, FPADDSUB_OP_FLAG_SFG, FPADDSUB_SIGN_FLAG_SFG,
FPADDSUB_SIGN_FLAG_NRM, FPADDSUB_SIGN_FLAG_SHT1SHT2,
FPADDSUB_ADD_OVRFLW_NRM2, FPADDSUB_OP_FLAG_SHT2,
FPADDSUB_SIGN_FLAG_SHT2, FPADDSUB_bit_shift_SHT2,
FPADDSUB_left_right_SHT2, FPADDSUB_ADD_OVRFLW_NRM,
FPADDSUB_OP_FLAG_SHT1, FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP,
FPADDSUB_SIGN_FLAG_EXP, FPADDSUB_intAS, FPADDSUB_Shift_reg_FLAGS_7_5,
FPADDSUB_Shift_reg_FLAGS_7_6, FPMULT_Exp_module_Overflow_flag_A,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229,
n1230, n1231, n1232, n1233, n1234, n1236, n1237, n1238, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1288, n1289, n1290, n1291, n1292, n1293,
n1295, n1296, n1297, n1298, n1299, n1300, n1302, n1303, n1304, n1305,
n1306, n1307, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1481, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726,
n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736,
n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746,
n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756,
n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766,
n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776,
n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786,
n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796,
n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806,
n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816,
n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826,
n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836,
n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846,
n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856,
n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866,
n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876,
n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886,
n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896,
n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906,
n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916,
n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926,
n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936,
n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946,
n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956,
n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966,
n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976,
n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986,
n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996,
n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006,
n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016,
n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026,
n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036,
n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046,
n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056,
n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066,
n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076,
n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086,
n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096,
n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106,
n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116,
n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126,
n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136,
n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146,
n2147, n2148, n2149, n2191, mult_x_311_n37, mult_x_311_n36,
mult_x_311_n30, mult_x_311_n29, mult_x_311_n23, mult_x_311_n22,
mult_x_311_n18, mult_x_311_n17, mult_x_311_n15, mult_x_311_n14,
mult_x_309_n37, mult_x_309_n36, mult_x_309_n30, mult_x_309_n29,
mult_x_309_n23, mult_x_309_n22, mult_x_309_n18, mult_x_309_n17,
mult_x_309_n15, mult_x_309_n14, DP_OP_26J223_129_1325_n18,
DP_OP_26J223_129_1325_n17, DP_OP_26J223_129_1325_n16,
DP_OP_26J223_129_1325_n15, DP_OP_26J223_129_1325_n14,
DP_OP_26J223_129_1325_n8, DP_OP_26J223_129_1325_n7,
DP_OP_26J223_129_1325_n6, DP_OP_26J223_129_1325_n5,
DP_OP_26J223_129_1325_n4, DP_OP_26J223_129_1325_n3,
DP_OP_26J223_129_1325_n2, DP_OP_26J223_129_1325_n1,
DP_OP_234J223_132_4955_n22, DP_OP_234J223_132_4955_n21,
DP_OP_234J223_132_4955_n20, DP_OP_234J223_132_4955_n19,
DP_OP_234J223_132_4955_n18, DP_OP_234J223_132_4955_n17,
DP_OP_234J223_132_4955_n16, DP_OP_234J223_132_4955_n15,
DP_OP_234J223_132_4955_n9, DP_OP_234J223_132_4955_n8,
DP_OP_234J223_132_4955_n7, DP_OP_234J223_132_4955_n6,
DP_OP_234J223_132_4955_n5, DP_OP_234J223_132_4955_n4,
DP_OP_234J223_132_4955_n3, DP_OP_234J223_132_4955_n2,
DP_OP_234J223_132_4955_n1, intadd_512_A_7_, intadd_512_A_6_,
intadd_512_A_5_, intadd_512_A_4_, intadd_512_A_3_, intadd_512_A_2_,
intadd_512_A_1_, intadd_512_A_0_, intadd_512_B_7_, intadd_512_B_6_,
intadd_512_B_5_, intadd_512_B_4_, intadd_512_B_3_, intadd_512_B_2_,
intadd_512_B_1_, intadd_512_B_0_, intadd_512_CI, intadd_512_SUM_7_,
intadd_512_SUM_6_, intadd_512_SUM_5_, intadd_512_SUM_4_,
intadd_512_SUM_3_, intadd_512_SUM_2_, intadd_512_SUM_1_,
intadd_512_SUM_0_, intadd_512_n8, intadd_512_n7, intadd_512_n6,
intadd_512_n5, intadd_512_n4, intadd_512_n3, intadd_512_n2,
intadd_512_n1, intadd_513_A_7_, intadd_513_A_0_, intadd_513_B_7_,
intadd_513_B_6_, intadd_513_B_1_, intadd_513_B_0_, intadd_513_CI,
intadd_513_n8, intadd_513_n7, intadd_513_n6, intadd_513_n5,
intadd_513_n4, intadd_513_n3, intadd_513_n2, intadd_513_n1,
intadd_514_A_7_, intadd_514_A_6_, intadd_514_A_5_, intadd_514_A_4_,
intadd_514_A_3_, intadd_514_A_2_, intadd_514_A_1_, intadd_514_A_0_,
intadd_514_B_7_, intadd_514_B_6_, intadd_514_B_5_, intadd_514_B_4_,
intadd_514_B_3_, intadd_514_B_2_, intadd_514_B_1_, intadd_514_B_0_,
intadd_514_CI, intadd_514_SUM_7_, intadd_514_SUM_6_,
intadd_514_SUM_5_, intadd_514_SUM_4_, intadd_514_SUM_3_,
intadd_514_SUM_2_, intadd_514_SUM_1_, intadd_514_SUM_0_,
intadd_514_n8, intadd_514_n7, intadd_514_n6, intadd_514_n5,
intadd_514_n4, intadd_514_n3, intadd_514_n2, intadd_514_n1,
intadd_515_A_0_, intadd_515_B_6_, intadd_515_B_1_, intadd_515_B_0_,
intadd_515_CI, intadd_515_n7, intadd_515_n6, intadd_515_n5,
intadd_515_n4, intadd_515_n3, intadd_515_n2, intadd_515_n1,
intadd_516_CI, intadd_516_SUM_2_, intadd_516_SUM_1_,
intadd_516_SUM_0_, intadd_516_n3, intadd_516_n2, intadd_516_n1,
intadd_517_B_1_, intadd_517_CI, intadd_517_SUM_2_, intadd_517_SUM_1_,
intadd_517_SUM_0_, intadd_517_n3, intadd_517_n2, intadd_517_n1,
intadd_518_CI, intadd_518_SUM_2_, intadd_518_SUM_1_,
intadd_518_SUM_0_, intadd_518_n3, intadd_518_n2, intadd_518_n1,
DP_OP_500J223_126_4510_n188, DP_OP_500J223_126_4510_n187,
DP_OP_500J223_126_4510_n186, DP_OP_500J223_126_4510_n185,
DP_OP_500J223_126_4510_n181, DP_OP_500J223_126_4510_n180,
DP_OP_500J223_126_4510_n179, DP_OP_500J223_126_4510_n178,
DP_OP_500J223_126_4510_n174, DP_OP_500J223_126_4510_n172,
DP_OP_500J223_126_4510_n171, DP_OP_500J223_126_4510_n170,
DP_OP_500J223_126_4510_n165, DP_OP_500J223_126_4510_n164,
DP_OP_500J223_126_4510_n162, DP_OP_500J223_126_4510_n161,
DP_OP_500J223_126_4510_n158, DP_OP_500J223_126_4510_n157,
DP_OP_500J223_126_4510_n155, DP_OP_500J223_126_4510_n154,
DP_OP_500J223_126_4510_n151, DP_OP_500J223_126_4510_n150,
DP_OP_500J223_126_4510_n147, DP_OP_500J223_126_4510_n141,
DP_OP_500J223_126_4510_n138, DP_OP_500J223_126_4510_n137,
DP_OP_500J223_126_4510_n136, DP_OP_500J223_126_4510_n135,
DP_OP_500J223_126_4510_n134, DP_OP_500J223_126_4510_n132,
DP_OP_500J223_126_4510_n131, DP_OP_500J223_126_4510_n130,
DP_OP_500J223_126_4510_n129, DP_OP_500J223_126_4510_n128,
DP_OP_500J223_126_4510_n127, DP_OP_500J223_126_4510_n126,
DP_OP_500J223_126_4510_n125, DP_OP_500J223_126_4510_n124,
DP_OP_500J223_126_4510_n123, DP_OP_500J223_126_4510_n122,
DP_OP_500J223_126_4510_n121, DP_OP_500J223_126_4510_n120,
DP_OP_500J223_126_4510_n119, DP_OP_500J223_126_4510_n118,
DP_OP_500J223_126_4510_n117, DP_OP_500J223_126_4510_n116,
DP_OP_500J223_126_4510_n115, DP_OP_500J223_126_4510_n112,
DP_OP_500J223_126_4510_n111, DP_OP_500J223_126_4510_n110,
DP_OP_500J223_126_4510_n109, DP_OP_500J223_126_4510_n108,
DP_OP_500J223_126_4510_n107, DP_OP_500J223_126_4510_n106,
DP_OP_500J223_126_4510_n105, DP_OP_500J223_126_4510_n104,
DP_OP_500J223_126_4510_n103, DP_OP_500J223_126_4510_n102,
DP_OP_500J223_126_4510_n101, DP_OP_500J223_126_4510_n100,
DP_OP_502J223_128_4510_n188, DP_OP_502J223_128_4510_n187,
DP_OP_502J223_128_4510_n186, DP_OP_502J223_128_4510_n185,
DP_OP_502J223_128_4510_n181, DP_OP_502J223_128_4510_n180,
DP_OP_502J223_128_4510_n179, DP_OP_502J223_128_4510_n178,
DP_OP_502J223_128_4510_n174, DP_OP_502J223_128_4510_n172,
DP_OP_502J223_128_4510_n171, DP_OP_502J223_128_4510_n170,
DP_OP_502J223_128_4510_n165, DP_OP_502J223_128_4510_n164,
DP_OP_502J223_128_4510_n162, DP_OP_502J223_128_4510_n161,
DP_OP_502J223_128_4510_n158, DP_OP_502J223_128_4510_n157,
DP_OP_502J223_128_4510_n155, DP_OP_502J223_128_4510_n154,
DP_OP_502J223_128_4510_n151, DP_OP_502J223_128_4510_n150,
DP_OP_502J223_128_4510_n147, DP_OP_502J223_128_4510_n141,
DP_OP_502J223_128_4510_n138, DP_OP_502J223_128_4510_n137,
DP_OP_502J223_128_4510_n136, DP_OP_502J223_128_4510_n135,
DP_OP_502J223_128_4510_n134, DP_OP_502J223_128_4510_n132,
DP_OP_502J223_128_4510_n131, DP_OP_502J223_128_4510_n130,
DP_OP_502J223_128_4510_n129, DP_OP_502J223_128_4510_n128,
DP_OP_502J223_128_4510_n127, DP_OP_502J223_128_4510_n126,
DP_OP_502J223_128_4510_n125, DP_OP_502J223_128_4510_n124,
DP_OP_502J223_128_4510_n123, DP_OP_502J223_128_4510_n122,
DP_OP_502J223_128_4510_n121, DP_OP_502J223_128_4510_n120,
DP_OP_502J223_128_4510_n119, DP_OP_502J223_128_4510_n118,
DP_OP_502J223_128_4510_n117, DP_OP_502J223_128_4510_n116,
DP_OP_502J223_128_4510_n115, DP_OP_502J223_128_4510_n112,
DP_OP_502J223_128_4510_n111, DP_OP_502J223_128_4510_n110,
DP_OP_502J223_128_4510_n109, DP_OP_502J223_128_4510_n108,
DP_OP_502J223_128_4510_n107, DP_OP_502J223_128_4510_n106,
DP_OP_502J223_128_4510_n105, DP_OP_502J223_128_4510_n104,
DP_OP_502J223_128_4510_n103, DP_OP_502J223_128_4510_n102,
DP_OP_502J223_128_4510_n101, DP_OP_502J223_128_4510_n100,
DP_OP_499J223_125_1651_n304, DP_OP_499J223_125_1651_n303,
DP_OP_499J223_125_1651_n302, DP_OP_499J223_125_1651_n301,
DP_OP_499J223_125_1651_n300, DP_OP_499J223_125_1651_n299,
DP_OP_499J223_125_1651_n297, DP_OP_499J223_125_1651_n296,
DP_OP_499J223_125_1651_n295, DP_OP_499J223_125_1651_n294,
DP_OP_499J223_125_1651_n293, DP_OP_499J223_125_1651_n292,
DP_OP_499J223_125_1651_n281, DP_OP_499J223_125_1651_n280,
DP_OP_499J223_125_1651_n279, DP_OP_499J223_125_1651_n278,
DP_OP_499J223_125_1651_n277, DP_OP_499J223_125_1651_n276,
DP_OP_499J223_125_1651_n274, DP_OP_499J223_125_1651_n273,
DP_OP_499J223_125_1651_n272, DP_OP_499J223_125_1651_n271,
DP_OP_499J223_125_1651_n270, DP_OP_499J223_125_1651_n269,
DP_OP_499J223_125_1651_n268, DP_OP_499J223_125_1651_n266,
DP_OP_499J223_125_1651_n252, DP_OP_499J223_125_1651_n250,
DP_OP_499J223_125_1651_n249, DP_OP_499J223_125_1651_n248,
DP_OP_499J223_125_1651_n247, DP_OP_499J223_125_1651_n246,
DP_OP_499J223_125_1651_n245, DP_OP_499J223_125_1651_n244,
DP_OP_499J223_125_1651_n243, DP_OP_499J223_125_1651_n242,
DP_OP_499J223_125_1651_n241, DP_OP_499J223_125_1651_n240,
DP_OP_499J223_125_1651_n239, DP_OP_499J223_125_1651_n238,
DP_OP_499J223_125_1651_n237, DP_OP_499J223_125_1651_n236,
DP_OP_499J223_125_1651_n235, DP_OP_499J223_125_1651_n234,
DP_OP_499J223_125_1651_n233, DP_OP_499J223_125_1651_n232,
DP_OP_499J223_125_1651_n231, DP_OP_499J223_125_1651_n230,
DP_OP_499J223_125_1651_n229, DP_OP_499J223_125_1651_n228,
DP_OP_499J223_125_1651_n227, DP_OP_499J223_125_1651_n226,
DP_OP_499J223_125_1651_n225, DP_OP_499J223_125_1651_n224,
DP_OP_499J223_125_1651_n223, DP_OP_499J223_125_1651_n222,
DP_OP_499J223_125_1651_n221, DP_OP_499J223_125_1651_n220,
DP_OP_499J223_125_1651_n219, DP_OP_499J223_125_1651_n218,
DP_OP_499J223_125_1651_n217, DP_OP_499J223_125_1651_n216,
DP_OP_499J223_125_1651_n215, DP_OP_499J223_125_1651_n214,
DP_OP_499J223_125_1651_n213, DP_OP_499J223_125_1651_n212,
DP_OP_499J223_125_1651_n211, DP_OP_499J223_125_1651_n210,
DP_OP_499J223_125_1651_n209, DP_OP_499J223_125_1651_n208,
DP_OP_499J223_125_1651_n207, DP_OP_499J223_125_1651_n206,
DP_OP_499J223_125_1651_n205, DP_OP_499J223_125_1651_n204,
DP_OP_499J223_125_1651_n203, DP_OP_499J223_125_1651_n202,
DP_OP_496J223_122_3236_n147, DP_OP_501J223_127_5235_n944,
DP_OP_501J223_127_5235_n903, DP_OP_501J223_127_5235_n897,
DP_OP_501J223_127_5235_n723, DP_OP_501J223_127_5235_n630,
DP_OP_501J223_127_5235_n523, DP_OP_501J223_127_5235_n521,
DP_OP_501J223_127_5235_n517, DP_OP_501J223_127_5235_n515,
DP_OP_501J223_127_5235_n511, DP_OP_501J223_127_5235_n510,
DP_OP_501J223_127_5235_n509, DP_OP_501J223_127_5235_n508,
DP_OP_501J223_127_5235_n503, DP_OP_501J223_127_5235_n500,
DP_OP_501J223_127_5235_n497, DP_OP_501J223_127_5235_n495,
DP_OP_501J223_127_5235_n494, DP_OP_501J223_127_5235_n491,
DP_OP_501J223_127_5235_n488, DP_OP_501J223_127_5235_n482,
DP_OP_501J223_127_5235_n479, DP_OP_501J223_127_5235_n478,
DP_OP_501J223_127_5235_n477, DP_OP_501J223_127_5235_n476,
DP_OP_501J223_127_5235_n475, DP_OP_501J223_127_5235_n474,
DP_OP_501J223_127_5235_n473, DP_OP_501J223_127_5235_n472,
DP_OP_501J223_127_5235_n471, DP_OP_501J223_127_5235_n470,
DP_OP_501J223_127_5235_n469, DP_OP_501J223_127_5235_n468,
DP_OP_501J223_127_5235_n467, DP_OP_501J223_127_5235_n466,
DP_OP_501J223_127_5235_n465, DP_OP_501J223_127_5235_n464,
DP_OP_501J223_127_5235_n463, DP_OP_501J223_127_5235_n462,
DP_OP_501J223_127_5235_n460, DP_OP_501J223_127_5235_n459,
DP_OP_501J223_127_5235_n458, DP_OP_501J223_127_5235_n457,
DP_OP_501J223_127_5235_n456, DP_OP_501J223_127_5235_n455,
DP_OP_501J223_127_5235_n454, DP_OP_501J223_127_5235_n453,
DP_OP_501J223_127_5235_n452, DP_OP_501J223_127_5235_n451,
DP_OP_501J223_127_5235_n450, DP_OP_501J223_127_5235_n449,
DP_OP_501J223_127_5235_n448, DP_OP_501J223_127_5235_n447,
DP_OP_501J223_127_5235_n263, DP_OP_501J223_127_5235_n262,
DP_OP_501J223_127_5235_n261, DP_OP_501J223_127_5235_n260,
DP_OP_501J223_127_5235_n259, DP_OP_501J223_127_5235_n254,
DP_OP_501J223_127_5235_n253, DP_OP_501J223_127_5235_n252,
DP_OP_501J223_127_5235_n251, DP_OP_501J223_127_5235_n250,
DP_OP_501J223_127_5235_n247, DP_OP_501J223_127_5235_n246,
DP_OP_501J223_127_5235_n245, DP_OP_501J223_127_5235_n244,
DP_OP_501J223_127_5235_n243, DP_OP_501J223_127_5235_n242,
DP_OP_501J223_127_5235_n241, DP_OP_501J223_127_5235_n237,
DP_OP_501J223_127_5235_n236, DP_OP_501J223_127_5235_n235,
DP_OP_501J223_127_5235_n234, DP_OP_501J223_127_5235_n233,
DP_OP_501J223_127_5235_n232, DP_OP_501J223_127_5235_n229,
DP_OP_501J223_127_5235_n228, DP_OP_501J223_127_5235_n227,
DP_OP_501J223_127_5235_n225, DP_OP_501J223_127_5235_n224,
DP_OP_501J223_127_5235_n219, DP_OP_501J223_127_5235_n216,
DP_OP_501J223_127_5235_n214, DP_OP_501J223_127_5235_n211,
DP_OP_501J223_127_5235_n208, DP_OP_501J223_127_5235_n207,
DP_OP_501J223_127_5235_n206, DP_OP_501J223_127_5235_n203,
DP_OP_501J223_127_5235_n200, DP_OP_501J223_127_5235_n198,
DP_OP_501J223_127_5235_n193, DP_OP_501J223_127_5235_n191,
DP_OP_501J223_127_5235_n190, DP_OP_501J223_127_5235_n188,
DP_OP_501J223_127_5235_n187, DP_OP_501J223_127_5235_n186,
DP_OP_501J223_127_5235_n184, DP_OP_501J223_127_5235_n183,
DP_OP_501J223_127_5235_n182, DP_OP_501J223_127_5235_n181,
DP_OP_501J223_127_5235_n180, DP_OP_501J223_127_5235_n179,
DP_OP_501J223_127_5235_n178, DP_OP_501J223_127_5235_n176,
DP_OP_501J223_127_5235_n175, DP_OP_501J223_127_5235_n174,
DP_OP_501J223_127_5235_n173, DP_OP_501J223_127_5235_n172,
DP_OP_501J223_127_5235_n171, DP_OP_501J223_127_5235_n169,
DP_OP_501J223_127_5235_n168, DP_OP_501J223_127_5235_n167,
DP_OP_501J223_127_5235_n166, DP_OP_501J223_127_5235_n165,
DP_OP_501J223_127_5235_n164, DP_OP_501J223_127_5235_n163,
DP_OP_501J223_127_5235_n162, DP_OP_501J223_127_5235_n161,
DP_OP_501J223_127_5235_n160, DP_OP_501J223_127_5235_n159,
DP_OP_501J223_127_5235_n158, DP_OP_501J223_127_5235_n157,
DP_OP_501J223_127_5235_n156, DP_OP_501J223_127_5235_n155,
DP_OP_501J223_127_5235_n154, DP_OP_501J223_127_5235_n153,
DP_OP_501J223_127_5235_n152, DP_OP_501J223_127_5235_n151,
DP_OP_501J223_127_5235_n150, DP_OP_501J223_127_5235_n149,
DP_OP_501J223_127_5235_n148, DP_OP_501J223_127_5235_n147,
DP_OP_501J223_127_5235_n146, DP_OP_501J223_127_5235_n145,
DP_OP_501J223_127_5235_n144, DP_OP_501J223_127_5235_n143,
DP_OP_501J223_127_5235_n142, DP_OP_501J223_127_5235_n141,
DP_OP_501J223_127_5235_n140, DP_OP_501J223_127_5235_n139,
DP_OP_501J223_127_5235_n138, DP_OP_501J223_127_5235_n137,
DP_OP_501J223_127_5235_n136, DP_OP_501J223_127_5235_n135,
DP_OP_501J223_127_5235_n134, DP_OP_501J223_127_5235_n133,
DP_OP_501J223_127_5235_n132, DP_OP_501J223_127_5235_n131,
DP_OP_501J223_127_5235_n130, DP_OP_501J223_127_5235_n129,
DP_OP_501J223_127_5235_n128, DP_OP_501J223_127_5235_n127,
DP_OP_501J223_127_5235_n126, DP_OP_501J223_127_5235_n125,
DP_OP_501J223_127_5235_n124, DP_OP_501J223_127_5235_n123,
DP_OP_501J223_127_5235_n122, DP_OP_501J223_127_5235_n121,
DP_OP_501J223_127_5235_n120, n2194, n2196, n2197, n2198, n2199, n2200,
n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210,
n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220,
n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230,
n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240,
n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250,
n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260,
n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270,
n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280,
n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2289, n2290, n2291,
n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301,
n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311,
n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321,
n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331,
n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341,
n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351,
n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361,
n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371,
n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381,
n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391,
n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401,
n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411,
n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421,
n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431,
n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441,
n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451,
n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461,
n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471,
n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481,
n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491,
n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501,
n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511,
n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521,
n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531,
n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541,
n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551,
n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561,
n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571,
n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581,
n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591,
n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601,
n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611,
n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621,
n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631,
n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641,
n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651,
n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661,
n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671,
n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681,
n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691,
n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701,
n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711,
n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721,
n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731,
n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741,
n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751,
n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761,
n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771,
n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781,
n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791,
n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801,
n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811,
n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821,
n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831,
n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841,
n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851,
n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861,
n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871,
n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881,
n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891,
n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901,
n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911,
n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921,
n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931,
n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941,
n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951,
n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961,
n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971,
n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981,
n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991,
n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001,
n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011,
n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021,
n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031,
n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041,
n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051,
n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061,
n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071,
n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081,
n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091,
n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101,
n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111,
n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121,
n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131,
n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141,
n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151,
n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161,
n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171,
n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181,
n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191,
n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201,
n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211,
n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221,
n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231,
n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241,
n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251,
n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261,
n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271,
n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281,
n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291,
n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301,
n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311,
n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321,
n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331,
n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341,
n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351,
n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361,
n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371,
n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381,
n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391,
n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401,
n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411,
n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421,
n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431,
n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441,
n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451,
n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461,
n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471,
n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481,
n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491,
n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501,
n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511,
n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521,
n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531,
n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541,
n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551,
n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561,
n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571,
n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581,
n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591,
n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601,
n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611,
n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621,
n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631,
n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641,
n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651,
n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661,
n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671,
n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681,
n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691,
n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701,
n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711,
n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721,
n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731,
n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741,
n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751,
n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761,
n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771,
n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781,
n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791,
n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801,
n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811,
n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821,
n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831,
n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841,
n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851,
n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861,
n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871,
n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881,
n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891,
n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901,
n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911,
n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921,
n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931,
n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941,
n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951,
n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961,
n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971,
n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981,
n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991,
n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001,
n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011,
n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021,
n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031,
n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041,
n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051,
n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061,
n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071,
n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081,
n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091,
n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101,
n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111,
n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121,
n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131,
n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141,
n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151,
n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161,
n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171,
n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181,
n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191,
n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201,
n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211,
n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221,
n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231,
n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241,
n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251,
n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261,
n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271,
n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281,
n4282, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292,
n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302,
n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312,
n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322,
n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332,
n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342,
n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352,
n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362,
n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372,
n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382,
n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392,
n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402,
n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412,
n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422,
n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432,
n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442,
n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452,
n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462,
n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472,
n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482,
n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492,
n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502,
n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512,
n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522,
n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532,
n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542,
n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552,
n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562,
n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572,
n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582,
n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592,
n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602,
n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612,
n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622,
n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632,
n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642,
n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652,
n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662,
n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672,
n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682,
n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692,
n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702,
n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712,
n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722,
n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732,
n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742,
n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752,
n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762,
n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772,
n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782,
n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792,
n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802,
n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812,
n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822,
n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832,
n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842,
n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852,
n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862,
n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872,
n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882,
n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892,
n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902,
n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912,
n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922,
n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932,
n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942,
n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952,
n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962,
n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972,
n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982,
n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992,
n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002,
n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012,
n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022,
n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032,
n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042,
n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052,
n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062,
n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072,
n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082,
n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092,
n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102,
n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112,
n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122,
n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132,
n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142,
n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152,
n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162,
n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172,
n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182,
n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192,
n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202,
n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212,
n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222,
n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232,
n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242,
n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252,
n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262,
n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272,
n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282,
n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292,
n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302,
n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312,
n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322,
n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332,
n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342,
n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352,
n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362,
n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372,
n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382,
n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392,
n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402,
n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412,
n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422,
n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432,
n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442,
n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452,
n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462,
n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472,
n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482,
n5483, n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492,
n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502,
n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512,
n5513, n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522,
n5523, n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532,
n5533, n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542,
n5543, n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552,
n5553, n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562,
n5563, n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572,
n5573, n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582,
n5583, n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592,
n5593, n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602,
n5603, n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612,
n5613, n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622,
n5623, n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632,
n5633, n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642,
n5643, n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652,
n5653, n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662,
n5663, n5664, n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672,
n5673, n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682,
n5683, n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692,
n5693, n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702,
n5703, n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712,
n5713, n5714, n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722,
n5723, n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732,
n5733, n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742,
n5743, n5744, n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752,
n5753, n5754, n5755, n5756, n5757, n5758, n5759, n5760, n5761, n5762,
n5763, n5764, n5765, n5766, n5767, n5768, n5769, n5770, n5771, n5772,
n5773, n5774, n5775, n5776, n5777, n5778, n5779, n5780, n5781, n5782,
n5783, n5784, n5785, n5786, n5787, n5788, n5789, n5790, n5791, n5792,
n5793, n5794, n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802,
n5803, n5804, n5805, n5806, n5807, n5808, n5809, n5810, n5811, n5812,
n5813, n5814, n5815, n5816, n5817, n5818, n5819, n5820, n5821, n5822,
n5823, n5824, n5825, n5826, n5827, n5828, n5829, n5830, n5831, n5832,
n5833, n5834, n5835, n5836, n5837, n5838, n5839, n5840, n5841, n5842,
n5843, n5844, n5845, n5846, n5847, n5848, n5849, n5850, n5851, n5852,
n5853, n5854, n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5862,
n5863, n5864, n5865, n5866, n5867, n5868, n5869, n5870, n5871, n5872,
n5873, n5874, n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882,
n5883, n5884, n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892,
n5893, n5894, n5895, n5896, n5897, n5898, n5899, n5900, n5901, n5902,
n5903, n5904, n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912,
n5913, n5914, n5915, n5916, n5917, n5918, n5919, n5920, n5921, n5922,
n5923, n5924, n5925, n5926, n5927, n5928, n5929, n5930, n5931, n5932,
n5933, n5934, n5935, n5936, n5937, n5938, n5939, n5940, n5941, n5942,
n5943, n5944, n5945, n5946, n5947, n5948, n5949, n5950, n5951, n5952,
n5953, n5954, n5955, n5956, n5957, n5958, n5959, n5960, n5961, n5962,
n5963, n5964, n5965, n5966, n5967, n5968, n5969, n5970, n5971, n5972,
n5973, n5974, n5975, n5976, n5977, n5978, n5979, n5980, n5981, n5982,
n5983, n5984, n5985, n5986, n5987, n5988, n5989, n5990, n5991, n5992,
n5993, n5994, n5995, n5996, n5997, n5998, n5999, n6000, n6001, n6002,
n6003, n6004, n6005, n6006, n6007, n6008, n6009, n6010, n6011, n6012,
n6013, n6014, n6015, n6016, n6017, n6018, n6019, n6020, n6021, n6022,
n6023, n6024, n6025, n6026, n6027, n6028, n6029, n6030, n6031, n6032,
n6033, n6034, n6035, n6036, n6037, n6038, n6039, n6040, n6041, n6042,
n6043, n6044, n6045, n6046, n6047, n6048, n6049, n6050, n6051, n6052,
n6053, n6054, n6055, n6056, n6057, n6058, n6059, n6060, n6061, n6062,
n6063, n6064, n6065, n6066, n6067, n6068, n6069, n6070, n6071, n6072,
n6073, n6074, n6075, n6076, n6077, n6078, n6079, n6080, n6081, n6082,
n6083, n6084, n6085, n6086, n6087, n6088, n6089, n6090, n6091, n6092,
n6093, n6094, n6095, n6096, n6097, n6098, n6099, n6100, n6101, n6102,
n6103, n6104, n6105, n6106, n6107, n6108, n6109, n6110, n6111, n6112,
n6113, n6114, n6115, n6116, n6117, n6118, n6119, n6120, n6121, n6122,
n6123, n6124, n6125, n6126, n6127, n6128, n6129, n6130, n6131, n6132,
n6133, n6134, n6135, n6136, n6137, n6138, n6139, n6140, n6141, n6142,
n6143, n6144, n6145, n6146, n6147, n6148, n6149, n6150, n6151, n6152,
n6153, n6154, n6155, n6156, n6157, n6158, n6159, n6160, n6161, n6162,
n6163, n6164, n6165, n6166, n6167, n6168, n6169, n6170, n6171, n6172,
n6173, n6174, n6175, n6176, n6177, n6178, n6179, n6180, n6181, n6182,
n6183, n6184, n6185, n6186, n6187, n6188, n6189, n6190, n6191, n6192,
n6193, n6194, n6195, n6196, n6197, n6198, n6199, n6200, n6201, n6202,
n6203, n6204, n6205, n6206, n6207, n6208, n6209, n6210, n6211, n6212,
n6213, n6214, n6215, n6216, n6217, n6218, n6219, n6220, n6221, n6222,
n6223, n6224, n6225, n6226, n6227, n6228, n6229, n6230, n6231, n6232,
n6233, n6234, n6235, n6236, n6237, n6238, n6239, n6240, n6241, n6242,
n6243, n6244, n6245, n6246, n6247, n6248, n6249, n6250, n6251, n6252,
n6253, n6254, n6255, n6256, n6257, n6258, n6259, n6260, n6261, n6262,
n6263, n6264, n6265, n6266, n6267, n6268, n6269, n6270, n6271, n6272,
n6273, n6274, n6275, n6276, n6277, n6278, n6279, n6280, n6281, n6282,
n6283, n6284, n6285, n6286, n6287, n6288, n6289, n6290, n6291, n6292,
n6293, n6294, n6295, n6296, n6297, n6298, n6299, n6300, n6301, n6302,
n6303, n6304, n6305, n6306, n6307, n6308, n6309, n6310, n6311, n6312,
n6313, n6314, n6315, n6316, n6317, n6318, n6319, n6320, n6321, n6322,
n6323, n6324, n6325, n6326, n6327, n6328, n6329, n6330, n6331, n6332,
n6333, n6334, n6335, n6336, n6337, n6338, n6339, n6340, n6341, n6342,
n6343, n6344, n6345, n6346, n6347, n6348, n6349, n6350, n6351, n6352,
n6353, n6354, n6355, n6356, n6357, n6358, n6359, n6360, n6361, n6362,
n6363, n6364, n6365, n6366, n6367, n6368, n6369, n6370, n6371, n6372,
n6373, n6374, n6375, n6376, n6377, n6378, n6379, n6380, n6381, n6382,
n6383, n6384, n6385, n6386, n6387, n6388, n6389, n6390, n6391, n6392,
n6393, n6394, n6395, n6396, n6397, n6398, n6399, n6400, n6401, n6402,
n6403, n6404, n6405, n6406, n6407, n6408, n6409, n6410, n6411, n6412,
n6413, n6414, n6415, n6416, n6417, n6418, n6419, n6420, n6421, n6422,
n6423, n6424, n6425, n6426, n6427, n6428, n6429, n6430, n6431, n6432,
n6433, n6434, n6435, n6436, n6437, n6438, n6439, n6440, n6441, n6442,
n6443, n6444, n6445, n6446, n6447, n6448, n6449, n6450, n6451, n6452,
n6453, n6454, n6455, n6456, n6457, n6458, n6459, n6460, n6461, n6462,
n6463, n6464, n6465, n6466, n6467, n6468, n6469, n6470, n6471, n6472,
n6473, n6474, n6475, n6476, n6477, n6478, n6479, n6480, n6481, n6482,
n6483, n6484, n6485, n6486, n6487, n6488, n6489, n6490, n6491, n6492,
n6493, n6494, n6495, n6496, n6497, n6498, n6499, n6500, n6501, n6502,
n6503, n6504, n6505, n6506, n6507, n6508, n6509, n6510, n6511, n6512,
n6513, n6514, n6515, n6516, n6517, n6518, n6519, n6520, n6521, n6522,
n6523, n6524, n6525, n6526, n6527, n6528, n6529, n6530, n6531, n6532,
n6533, n6534, n6535, n6536, n6537, n6538, n6539, n6540, n6541, n6542,
n6543, n6544, n6545, n6546, n6547, n6548, n6549, n6550, n6551, n6552,
n6553, n6554, n6555, n6556, n6557, n6558, n6559, n6560, n6561, n6562,
n6563, n6564, n6565, n6566, n6567, n6568, n6569, n6570, n6572, n6573,
n6574, n6575, n6576, n6579, n6580, n6581, n6582, n6583, n6584, n6585,
n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594, n6595,
n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604, n6605,
n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614, n6615,
n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624, n6625,
n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634, n6635,
n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644, n6645,
n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654, n6655,
n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664, n6665,
n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674, n6675,
n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684, n6685,
n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694, n6695,
n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704, n6705,
n6706, n6707, n6708, n6709, n6710, n6711, n6713, n6714, n6715, n6716,
n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724, n6725, n6726,
n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734, n6735, n6736,
n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744, n6746, n6747,
n6748, n6749, n6750, n6751, n6752, n6753, n6754, n6755, n6756, n6757,
n6758, n6759, n6760, n6761, n6762, n6763, n6764, n6765, n6766, n6767,
n6768, n6769, n6770, n6771, n6772, n6773, n6774, n6775, n6776, n6777,
n6778, n6779, n6780, n6781, n6782, n6783, n6784, n6785, n6786, n6787,
n6788, n6789, n6790, n6791, n6792, n6793, n6794, n6795, n6796, n6797,
n6798, n6799, n6800, n6801, n6802, n6803, n6804, n6805, n6806, n6807,
n6808, n6809, n6810, n6811, n6812, n6813, n6814, n6815, n6816, n6817,
n6818, n6819, n6820, n6821, n6822, n6823, n6824, n6825, n6826, n6827,
n6828, n6829, n6830, n6831, n6832, n6833, n6834, n6835, n6836, n6837,
n6838, n6839, n6840, n6841, n6842, n6843, n6844, n6845, n6846, n6847,
n6848, n6849, n6850, n6851, n6852, n6853, n6854, n6855, n6856, n6857,
n6858, n6859, n6860, n6861, n6862, n6863, n6864, n6865, n6866, n6867,
n6868, n6869, n6870, n6871, n6872, n6873, n6874, n6875, n6876, n6877,
n6878, n6879, n6880, n6881, n6882, n6883, n6884, n6885, n6886, n6887,
n6888, n6889, n6890, n6891, n6892, n6893, n6894, n6895, n6896, n6897,
n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905, n6906, n6907,
n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915, n6916, n6917,
n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925, n6926, n6927,
n6928, n6929, n6930, n6931, n6932, n6933, n6934, n6935, n6936, n6937,
n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945, n6946, n6947,
n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955, n6956, n6957,
n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965, n6966, n6967,
n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975, n6976, n6977,
n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985, n6986, n6987,
n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995, n6996, n6997,
n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005, n7006, n7007,
n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015, n7016, n7017,
n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025, n7026, n7027,
n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035, n7036, n7037,
n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045, n7046, n7047,
n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055, n7056, n7057,
n7058, n7059, n7060, n7062, n7063, n7064, n7065, n7066, n7067, n7068,
n7069, n7070, n7071, n7072, n7073, n7074, n7075, n7076;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [31:4] result_add_subt;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:3] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [31:2] FPMULT_Op_MY;
wire [31:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [35:0] FPMULT_P_Sgf;
wire [25:0] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [25:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [31:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [47:0] FPMULT_Sgf_operation_Result;
wire [5:0] FPMULT_Sgf_operation_EVEN1_Q_left;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
wire [13:0] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle;
wire [11:6] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right;
wire [11:0] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left;
wire [16:1] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B;
wire [15:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle;
wire [13:1] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right;
wire [10:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left;
wire [13:0] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle;
wire [11:5] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right;
wire [11:0] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left;
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n7027), .Q(
dataA[24]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n7027), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n7041), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n7026), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n7026), .Q(
dataB[31]) );
DFFRXLTS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2141), .CK(clk), .RN(n7025),
.Q(FPSENCOS_cont_iter_out[0]), .QN(n2468) );
DFFRXLTS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2139), .CK(clk), .RN(n7025),
.Q(FPSENCOS_cont_iter_out[2]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2147), .CK(clk), .RN(
n6959), .Q(FPADDSUB_Shift_reg_FLAGS_7_5), .QN(n6852) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2145), .CK(clk), .RN(
n6997), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n2142), .CK(clk), .RN(
n4492), .Q(FPADDSUB_Shift_reg_FLAGS_7[0]), .QN(n6849) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2135), .CK(clk), .RN(n7024),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2132), .CK(clk), .RN(n7024), .Q(
FPSENCOS_d_ff3_LUT_out[1]), .QN(n6900) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2130), .CK(clk), .RN(n7024), .Q(
FPSENCOS_d_ff3_LUT_out[3]), .QN(n6901) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2126), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[7]), .QN(n6902) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2125), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2123), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2121), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2120), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[15]), .QN(n6903) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2119), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2117), .CK(clk), .RN(n7022), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2115), .CK(clk), .RN(n7022), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2114), .CK(clk), .RN(n7022), .Q(
FPSENCOS_d_ff3_LUT_out[26]), .QN(n6899) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2113), .CK(clk), .RN(n7022), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1853), .CK(clk), .RN(n7022),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1852), .CK(clk), .RN(n7022),
.QN(n2415) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1851), .CK(clk), .RN(n7022),
.QN(n2441) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1850), .CK(clk), .RN(n7022),
.QN(n2445) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1849), .CK(clk), .RN(n7022),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1848), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1847), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1846), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1951), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1950), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1949), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1948), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1947), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1946), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1945), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1944), .CK(clk), .RN(n7020),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2112), .CK(clk), .RN(n7026), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2111), .CK(clk), .RN(n7040), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2110), .CK(clk), .RN(n7040), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2109), .CK(clk), .RN(n7040), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2108), .CK(clk), .RN(n7040), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2107), .CK(clk), .RN(n7040), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2106), .CK(clk), .RN(n7040), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2105), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2104), .CK(clk), .RN(n7040), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2103), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2102), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2101), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2100), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2099), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2098), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2097), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2096), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2095), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2094), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2093), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2092), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2091), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2090), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2089), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2088), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2087), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2086), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2085), .CK(clk), .RN(n7037), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2084), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2083), .CK(clk), .RN(n7037), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2082), .CK(clk), .RN(n7037), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2081), .CK(clk), .RN(n7037), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1786), .CK(clk), .RN(n7037), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1741), .CK(clk), .RN(
n7037), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1783), .CK(clk), .RN(n7036), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1740), .CK(clk), .RN(
n7036), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1781), .CK(clk), .RN(n7036), .Q(
FPSENCOS_d_ff_Xn[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1780), .CK(clk), .RN(n7035), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1739), .CK(clk), .RN(
n7036), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1777), .CK(clk), .RN(n7035), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1738), .CK(clk), .RN(
n7035), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1775), .CK(clk), .RN(n7034), .Q(
FPSENCOS_d_ff_Xn[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1774), .CK(clk), .RN(n7034), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1737), .CK(clk), .RN(
n7034), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1772), .CK(clk), .RN(n7034), .Q(
FPSENCOS_d_ff_Xn[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1771), .CK(clk), .RN(n7033), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1736), .CK(clk), .RN(
n7033), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1769), .CK(clk), .RN(n7033), .Q(
FPSENCOS_d_ff_Xn[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n7033), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1735), .CK(clk), .RN(
n7033), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1765), .CK(clk), .RN(n7032), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1734), .CK(clk), .RN(
n7032), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1788), .CK(clk), .RN(n6961),
.Q(FPADDSUB_Data_array_SWR[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2008), .CK(clk), .RN(n7031), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1742), .CK(clk), .RN(
n7031), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1862), .CK(clk), .RN(n7031),
.Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1960), .CK(clk), .RN(n7031),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2029), .CK(clk), .RN(n7030), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1749), .CK(clk), .RN(
n7030), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1876), .CK(clk), .RN(n7030),
.Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1975), .CK(clk), .RN(
n7030), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1974), .CK(clk), .RN(n7030),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2020), .CK(clk), .RN(n7030), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1746), .CK(clk), .RN(
n7030), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1870), .CK(clk), .RN(n7029),
.Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1969), .CK(clk), .RN(
n7029), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1968), .CK(clk), .RN(n7029),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1789), .CK(clk), .RN(n6962),
.Q(FPADDSUB_Data_array_SWR[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2011), .CK(clk), .RN(n7029), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1743), .CK(clk), .RN(
n7029), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1963), .CK(clk), .RN(
n7034), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1962), .CK(clk), .RN(n7040),
.Q(FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2017), .CK(clk), .RN(n2391), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1745), .CK(clk), .RN(
n2392), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1868), .CK(clk), .RN(n2393),
.Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2015), .CK(clk), .RN(n2391), .Q(
FPSENCOS_d_ff_Xn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1967), .CK(clk), .RN(
n7041), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1966), .CK(clk), .RN(n7041),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1790), .CK(clk), .RN(n6962),
.Q(FPADDSUB_Data_array_SWR[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2014), .CK(clk), .RN(n7041), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1744), .CK(clk), .RN(
n7009), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1866), .CK(clk), .RN(n7009),
.Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2012), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff_Xn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1965), .CK(clk), .RN(
n7009), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1964), .CK(clk), .RN(n7009),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2023), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1747), .CK(clk), .RN(
n7009), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1872), .CK(clk), .RN(n7008),
.Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2021), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff_Xn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1971), .CK(clk), .RN(
n7008), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1970), .CK(clk), .RN(n7008),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2062), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1760), .CK(clk), .RN(
n7008), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1898), .CK(clk), .RN(n7008),
.QN(n2435) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1997), .CK(clk), .RN(
n7007), .Q(FPSENCOS_d_ff2_X[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1996), .CK(clk), .RN(n7007),
.Q(FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2056), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1758), .CK(clk), .RN(
n7007), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1894), .CK(clk), .RN(n7007),
.QN(n2439) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1992), .CK(clk), .RN(n7006),
.Q(FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2035), .CK(clk), .RN(n7006), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1751), .CK(clk), .RN(
n7006), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1880), .CK(clk), .RN(n7006),
.Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1978), .CK(clk), .RN(n7006),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2026), .CK(clk), .RN(n7006), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1748), .CK(clk), .RN(
n7005), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1874), .CK(clk), .RN(n7005),
.Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1972), .CK(clk), .RN(n7005),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2050), .CK(clk), .RN(n7005), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1756), .CK(clk), .RN(
n7005), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1890), .CK(clk), .RN(n7004),
.QN(n2419) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1989), .CK(clk), .RN(
n7004), .Q(FPSENCOS_d_ff2_X[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1988), .CK(clk), .RN(n7004),
.Q(FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2041), .CK(clk), .RN(n7004), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1753), .CK(clk), .RN(
n7004), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1884), .CK(clk), .RN(n7003),
.Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1983), .CK(clk), .RN(
n7003), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1982), .CK(clk), .RN(n7003),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2032), .CK(clk), .RN(n7003), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1750), .CK(clk), .RN(
n7003), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1878), .CK(clk), .RN(n7003),
.Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2030), .CK(clk), .RN(n7003), .Q(
FPSENCOS_d_ff_Xn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1977), .CK(clk), .RN(
n7002), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1976), .CK(clk), .RN(n7002),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2044), .CK(clk), .RN(n7002), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1754), .CK(clk), .RN(
n7002), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1886), .CK(clk), .RN(n7002),
.QN(n2446) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1984), .CK(clk), .RN(n7002),
.Q(FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2038), .CK(clk), .RN(n7001), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1752), .CK(clk), .RN(
n7001), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1882), .CK(clk), .RN(n7001),
.QN(n2453) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2036), .CK(clk), .RN(n7001), .Q(
FPSENCOS_d_ff_Xn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1981), .CK(clk), .RN(
n7001), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1980), .CK(clk), .RN(n7001),
.Q(FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1909), .CK(clk), .RN(n7001), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1844), .CK(clk), .RN(n7000),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1943), .CK(clk), .RN(
n7000), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1942), .CK(clk), .RN(n7000),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2079), .CK(clk), .RN(
n6966), .Q(FPADDSUB_bit_shift_SHT2) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2065), .CK(clk), .RN(n7000), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1761), .CK(clk), .RN(
n7000), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1900), .CK(clk), .RN(n6999),
.Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2063), .CK(clk), .RN(n6999), .Q(
FPSENCOS_d_ff_Xn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n1999), .CK(clk), .RN(
n6999), .Q(FPSENCOS_d_ff2_X[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n1998), .CK(clk), .RN(n6999),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1723), .CK(clk), .RN(n6999),
.Q(cordic_result[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2068), .CK(clk), .RN(n6999), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1762), .CK(clk), .RN(
n6999), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1902), .CK(clk), .RN(n7020),
.QN(n2282) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2001), .CK(clk), .RN(
n7020), .Q(FPSENCOS_d_ff2_X[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2000), .CK(clk), .RN(n7020),
.Q(FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1724), .CK(clk), .RN(n7020),
.Q(cordic_result[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2053), .CK(clk), .RN(n7020), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1757), .CK(clk), .RN(
n7020), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1892), .CK(clk), .RN(n7013),
.Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2051), .CK(clk), .RN(n7042), .Q(
FPSENCOS_d_ff_Xn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1991), .CK(clk), .RN(
n7013), .Q(FPSENCOS_d_ff2_X[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1990), .CK(clk), .RN(n7019),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1719), .CK(clk), .RN(n7013),
.Q(cordic_result[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2074), .CK(clk), .RN(n4493), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1764), .CK(clk), .RN(
n7014), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1906), .CK(clk), .RN(n7018),
.QN(n2281) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2005), .CK(clk), .RN(
n7018), .Q(FPSENCOS_d_ff2_X[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2004), .CK(clk), .RN(n7018),
.Q(FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1726), .CK(clk), .RN(n7018),
.Q(cordic_result[0]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2071), .CK(clk), .RN(n7018), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1763), .CK(clk), .RN(
n7018), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1904), .CK(clk), .RN(n7018),
.QN(n2428) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2069), .CK(clk), .RN(n7017), .Q(
FPSENCOS_d_ff_Xn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2003), .CK(clk), .RN(
n7017), .Q(FPSENCOS_d_ff2_X[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2002), .CK(clk), .RN(n7017),
.Q(FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2047), .CK(clk), .RN(n7017), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1755), .CK(clk), .RN(
n7017), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1888), .CK(clk), .RN(n7017),
.QN(n2436) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1987), .CK(clk), .RN(
n7016), .Q(FPSENCOS_d_ff2_X[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1986), .CK(clk), .RN(n7016),
.Q(FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1717), .CK(clk), .RN(n7016),
.Q(cordic_result[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2059), .CK(clk), .RN(n7016), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1759), .CK(clk), .RN(
n7016), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1896), .CK(clk), .RN(n7016),
.Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2057), .CK(clk), .RN(n7016), .Q(
FPSENCOS_d_ff_Xn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1995), .CK(clk), .RN(
n7016), .Q(FPSENCOS_d_ff2_X[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1994), .CK(clk), .RN(n7015),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1721), .CK(clk), .RN(n7015),
.Q(cordic_result[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1695), .CK(clk), .RN(n7015),
.Q(cordic_result[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1716), .CK(clk), .RN(n7015),
.Q(cordic_result[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1715), .CK(clk), .RN(n7015),
.Q(cordic_result[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1718), .CK(clk), .RN(n7015),
.Q(cordic_result[8]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1787), .CK(clk), .RN(n6984),
.Q(FPADDSUB_Data_array_SWR[0]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1624), .CK(clk),
.RN(n7048), .Q(FPMULT_Op_MY[31]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n1677), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[19]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n1671), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[13]), .QN(n2469) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n1667), .CK(clk),
.RN(n7056), .Q(DP_OP_501J223_127_5235_n944), .QN(n6754) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n1659), .CK(clk),
.RN(n7056), .Q(n2481), .QN(n2482) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1657), .CK(clk),
.RN(n7055), .Q(FPMULT_Op_MX[31]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n1598), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[22]), .QN(n2400) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n1645), .CK(clk),
.RN(n7051), .Q(n6753), .QN(n6771) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n1639), .CK(clk),
.RN(n7046), .Q(FPMULT_Op_MY[13]), .QN(n2483) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1632), .CK(clk),
.RN(n7058), .Q(DP_OP_501J223_127_5235_n903), .QN(n6765) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n1630), .CK(clk),
.RN(n7051), .Q(FPMULT_Op_MY[4]), .QN(n2488) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n1627), .CK(clk),
.RN(n7052), .Q(n2220), .QN(n2477) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1625), .CK(
clk), .RN(n4494), .Q(FPMULT_zero_flag), .QN(n6904) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n1551), .CK(clk),
.RN(n4493), .Q(FPMULT_P_Sgf[22]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n1540), .CK(clk),
.RN(n7019), .Q(FPMULT_P_Sgf[11]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n1537), .CK(clk),
.RN(n4495), .Q(FPMULT_P_Sgf[8]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n1536), .CK(clk),
.RN(n4495), .Q(FPMULT_P_Sgf[7]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n1535), .CK(clk),
.RN(n7013), .Q(FPMULT_P_Sgf[6]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n1531), .CK(clk),
.RN(n7042), .Q(FPMULT_P_Sgf[2]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n1529), .CK(clk),
.RN(n4493), .Q(FPMULT_P_Sgf[0]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1621), .CK(
clk), .RN(n7051), .Q(FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1576), .CK(clk), .RN(n7048), .Q(mult_result[31]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1584), .CK(clk), .RN(n7052), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1583), .CK(clk), .RN(n7058), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1582), .CK(clk), .RN(n7045), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1581), .CK(clk), .RN(n7045), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1580), .CK(clk), .RN(n7045), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1579), .CK(clk), .RN(n7045), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1578), .CK(clk), .RN(n7045), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1577), .CK(clk), .RN(n7045), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1504), .CK(clk), .RN(n7045), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1503), .CK(clk), .RN(n7045), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1502), .CK(clk), .RN(n7045), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1501), .CK(clk), .RN(n7045), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1500), .CK(clk), .RN(n7044), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1499), .CK(clk), .RN(n7044), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1498), .CK(clk), .RN(n7044), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1497), .CK(clk), .RN(n7044), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1496), .CK(clk), .RN(n7044), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1495), .CK(clk), .RN(n7044), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1494), .CK(clk), .RN(n7044), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1493), .CK(clk), .RN(n7044), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1492), .CK(clk), .RN(n7044), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1491), .CK(clk), .RN(n7044), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1490), .CK(clk), .RN(n7043), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1489), .CK(clk), .RN(n7043), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1488), .CK(clk), .RN(n7043), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1487), .CK(clk), .RN(n7043), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1486), .CK(clk), .RN(n7043), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1485), .CK(clk), .RN(n7043), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1484), .CK(clk), .RN(n7043), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1483), .CK(clk), .RN(n7043), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1481), .CK(clk), .RN(n7043), .Q(mult_result[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1478), .CK(clk), .RN(
n6969), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1477), .CK(clk), .RN(
n6969), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1475), .CK(clk), .RN(
n6969), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1474), .CK(clk), .RN(
n6969), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1473), .CK(clk), .RN(
n6988), .Q(result_add_subt[23]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1472), .CK(clk), .RN(
n6988), .Q(result_add_subt[24]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1471), .CK(clk), .RN(
n6988), .Q(result_add_subt[25]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1470), .CK(clk), .RN(
n6988), .Q(result_add_subt[26]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1469), .CK(clk), .RN(
n6989), .Q(result_add_subt[27]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1468), .CK(clk), .RN(
n6989), .Q(result_add_subt[28]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1467), .CK(clk), .RN(
n6989), .Q(result_add_subt[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1460), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1459), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1458), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1456), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1455), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1454), .CK(clk), .RN(
n6997), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1451), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1450), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1449), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1446), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1445), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1444), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1441), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1440), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1439), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1436), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1435), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1434), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1431), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1430), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1429), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1426), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1425), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1424), .CK(clk), .RN(
n4492), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1421), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1420), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1419), .CK(clk), .RN(
n4490), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1412), .CK(clk), .RN(n6973), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1411), .CK(clk), .RN(n6989), .Q(overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1409), .CK(clk), .RN(
n6989), .Q(FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1408), .CK(clk), .RN(
n6973), .Q(result_add_subt[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1407), .CK(clk), .RN(n6973),
.Q(FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1406), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1405), .CK(clk), .RN(
n6973), .Q(result_add_subt[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n1404), .CK(clk), .RN(n6973),
.Q(FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1403), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1402), .CK(clk), .RN(
n6973), .Q(result_add_subt[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n1401), .CK(clk), .RN(n6973),
.Q(FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1400), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1399), .CK(clk), .RN(
n6974), .Q(result_add_subt[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1398), .CK(clk), .RN(n6974),
.Q(FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1397), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1396), .CK(clk), .RN(
n6974), .Q(result_add_subt[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n1395), .CK(clk), .RN(n6974),
.Q(FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1394), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1393), .CK(clk), .RN(
n6974), .Q(result_add_subt[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1392), .CK(clk), .RN(n6974),
.Q(FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1391), .CK(clk), .RN(
n6985), .QN(n6854) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1390), .CK(clk), .RN(
n6974), .Q(result_add_subt[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n1389), .CK(clk), .RN(n6974),
.Q(FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1388), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1386), .CK(clk), .RN(n6974),
.Q(FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1385), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1383), .CK(clk), .RN(n6975),
.Q(FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1382), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(
n6975), .Q(result_add_subt[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1380), .CK(clk), .RN(n6975),
.Q(FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1379), .CK(clk), .RN(
n6975), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(
n6975), .Q(result_add_subt[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n1377), .CK(clk), .RN(n6975),
.Q(FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1376), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1375), .CK(clk), .RN(
n6975), .Q(result_add_subt[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1374), .CK(clk), .RN(n6975),
.Q(FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1373), .CK(clk), .RN(
n6975), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1372), .CK(clk), .RN(
n6976), .Q(result_add_subt[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1371), .CK(clk), .RN(n6976),
.Q(FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1370), .CK(clk), .RN(
n6976), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n1368), .CK(clk), .RN(n6976),
.Q(FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1367), .CK(clk), .RN(
n6976), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1365), .CK(clk), .RN(n6976),
.Q(FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1364), .CK(clk), .RN(
n6976), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(clk), .RN(n6977),
.Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(clk), .RN(n6977), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1360), .CK(clk), .RN(n6977), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1359), .CK(clk), .RN(n6977),
.Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1358), .CK(clk), .RN(n6977),
.Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(
n6984), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1356), .CK(clk), .RN(
n6977), .Q(result_add_subt[31]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(clk), .RN(n6977),
.Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(clk), .RN(n6977), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1353), .CK(clk), .RN(n6977), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1330), .CK(clk), .RN(
n6997), .Q(FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n1328), .CK(clk), .RN(n6978),
.Q(FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1327), .CK(clk), .RN(
n6984), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1326), .CK(clk), .RN(n6978),
.Q(FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n6978),
.Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n6914), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1322), .CK(clk), .RN(
n6989), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1318), .CK(clk), .RN(
n6989), .Q(FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1312), .CK(clk), .RN(n6978),
.Q(FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1311), .CK(clk), .RN(
n6984), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1310), .CK(clk), .RN(n6978),
.Q(FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1309), .CK(clk), .RN(n6978),
.Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n6913), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n1305), .CK(clk), .RN(n6978),
.Q(FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(
n6978), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n1303), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1302), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n6912), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n1298), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(
n6984), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n1296), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n6911), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n1291), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1290), .CK(clk), .RN(
n6984), .QN(n6855) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n1289), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n6910), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n1284), .CK(clk), .RN(n6980),
.Q(FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1283), .CK(clk), .RN(
n6980), .QN(n6814) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n6980),
.Q(FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n6980),
.Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1280), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n1277), .CK(clk), .RN(n6980),
.Q(FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1276), .CK(clk), .RN(
n6980), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n1275), .CK(clk), .RN(n6980),
.Q(FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1274), .CK(clk), .RN(n6980),
.Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n6909), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n1271), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1270), .CK(clk), .RN(
n6981), .QN(n6815) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1267), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1263), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1259), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1255), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1251), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1247), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1243), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n1241), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1240), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n6908), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n1237), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n6907), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1231), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1227), .CK(clk), .RN(n6997),
.Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1223), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1219), .CK(clk), .RN(n6997),
.Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1215), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(clk), .RN(n6984),
.Q(FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(clk), .RN(n6984),
.Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1211), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(clk), .RN(n6984),
.Q(FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(clk), .RN(n6984),
.Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1207), .CK(clk), .RN(n6997),
.Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1180), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n6867) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n7067), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_14_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_15_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15])
);
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n2493), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n6905), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13])
);
CMPR32X2TS DP_OP_234J223_132_4955_U6 ( .A(DP_OP_234J223_132_4955_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J223_132_4955_n6), .CO(
DP_OP_234J223_132_4955_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J223_132_4955_U4 ( .A(DP_OP_234J223_132_4955_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J223_132_4955_n4), .CO(
DP_OP_234J223_132_4955_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_234J223_132_4955_U3 ( .A(DP_OP_234J223_132_4955_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J223_132_4955_n3), .CO(
DP_OP_234J223_132_4955_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS intadd_512_U9 ( .A(intadd_512_A_0_), .B(intadd_512_B_0_), .C(
intadd_512_CI), .CO(intadd_512_n8), .S(intadd_512_SUM_0_) );
CMPR32X2TS intadd_512_U8 ( .A(intadd_512_A_1_), .B(intadd_512_B_1_), .C(
intadd_512_n8), .CO(intadd_512_n7), .S(intadd_512_SUM_1_) );
CMPR32X2TS intadd_512_U7 ( .A(intadd_512_A_2_), .B(intadd_512_B_2_), .C(
intadd_512_n7), .CO(intadd_512_n6), .S(intadd_512_SUM_2_) );
CMPR32X2TS intadd_512_U6 ( .A(intadd_512_A_3_), .B(intadd_512_B_3_), .C(
intadd_512_n6), .CO(intadd_512_n5), .S(intadd_512_SUM_3_) );
CMPR32X2TS intadd_512_U4 ( .A(intadd_512_A_5_), .B(intadd_512_B_5_), .C(
intadd_512_n4), .CO(intadd_512_n3), .S(intadd_512_SUM_5_) );
CMPR32X2TS intadd_512_U2 ( .A(intadd_512_A_7_), .B(intadd_512_B_7_), .C(
intadd_512_n2), .CO(intadd_512_n1), .S(intadd_512_SUM_7_) );
CMPR32X2TS intadd_513_U9 ( .A(intadd_513_A_0_), .B(intadd_513_B_0_), .C(
intadd_513_CI), .CO(intadd_513_n8), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_513_U8 ( .A(mult_x_311_n37), .B(intadd_513_B_1_), .C(
intadd_513_n8), .CO(intadd_513_n7), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_513_U6 ( .A(mult_x_311_n29), .B(mult_x_311_n23), .C(
intadd_513_n6), .CO(intadd_513_n5), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_513_U5 ( .A(mult_x_311_n22), .B(mult_x_311_n18), .C(
intadd_513_n5), .CO(intadd_513_n4), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_513_U4 ( .A(mult_x_311_n17), .B(mult_x_311_n15), .C(
intadd_513_n4), .CO(intadd_513_n3), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_513_U3 ( .A(mult_x_311_n14), .B(intadd_513_B_6_), .C(
intadd_513_n3), .CO(intadd_513_n2), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_513_U2 ( .A(intadd_513_A_7_), .B(intadd_513_B_7_), .C(
intadd_513_n2), .CO(intadd_513_n1), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10) );
CMPR32X2TS intadd_514_U9 ( .A(intadd_514_A_0_), .B(intadd_514_B_0_), .C(
intadd_514_CI), .CO(intadd_514_n8), .S(intadd_514_SUM_0_) );
CMPR32X2TS intadd_514_U8 ( .A(intadd_514_A_1_), .B(intadd_514_B_1_), .C(
intadd_514_n8), .CO(intadd_514_n7), .S(intadd_514_SUM_1_) );
CMPR32X2TS intadd_514_U7 ( .A(intadd_514_A_2_), .B(intadd_514_B_2_), .C(
intadd_514_n7), .CO(intadd_514_n6), .S(intadd_514_SUM_2_) );
CMPR32X2TS intadd_514_U6 ( .A(intadd_514_A_3_), .B(intadd_514_B_3_), .C(
intadd_514_n6), .CO(intadd_514_n5), .S(intadd_514_SUM_3_) );
CMPR32X2TS intadd_514_U4 ( .A(intadd_514_A_5_), .B(intadd_514_B_5_), .C(
intadd_514_n4), .CO(intadd_514_n3), .S(intadd_514_SUM_5_) );
CMPR32X2TS intadd_514_U2 ( .A(intadd_514_A_7_), .B(intadd_514_B_7_), .C(
intadd_514_n2), .CO(intadd_514_n1), .S(intadd_514_SUM_7_) );
CMPR32X2TS intadd_515_U8 ( .A(intadd_515_A_0_), .B(intadd_515_B_0_), .C(
intadd_515_CI), .CO(intadd_515_n7), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_515_U7 ( .A(mult_x_309_n37), .B(intadd_515_B_1_), .C(
intadd_515_n7), .CO(intadd_515_n6), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_515_U5 ( .A(mult_x_309_n29), .B(mult_x_309_n23), .C(
intadd_515_n5), .CO(intadd_515_n4), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_518_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(intadd_517_B_1_),
.C(intadd_518_n3), .CO(intadd_518_n2), .S(intadd_518_SUM_1_) );
CMPR32X2TS intadd_518_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n6782), .C(
intadd_518_n2), .CO(intadd_518_n1), .S(intadd_518_SUM_2_) );
CMPR42X1TS DP_OP_500J223_126_4510_U122 ( .A(DP_OP_500J223_126_4510_n137),
.B(DP_OP_500J223_126_4510_n180), .C(DP_OP_500J223_126_4510_n134), .D(
DP_OP_500J223_126_4510_n187), .ICI(DP_OP_500J223_126_4510_n131), .S(
DP_OP_500J223_126_4510_n129), .ICO(DP_OP_500J223_126_4510_n127), .CO(
DP_OP_500J223_126_4510_n128) );
CMPR42X1TS DP_OP_500J223_126_4510_U118 ( .A(DP_OP_500J223_126_4510_n124),
.B(DP_OP_500J223_126_4510_n178), .C(DP_OP_500J223_126_4510_n121), .D(
DP_OP_500J223_126_4510_n125), .ICI(DP_OP_500J223_126_4510_n120), .S(
DP_OP_500J223_126_4510_n117), .ICO(DP_OP_500J223_126_4510_n115), .CO(
DP_OP_500J223_126_4510_n116) );
CMPR42X2TS DP_OP_500J223_126_4510_U115 ( .A(DP_OP_500J223_126_4510_n170),
.B(DP_OP_500J223_126_4510_n118), .C(DP_OP_500J223_126_4510_n112), .D(
DP_OP_500J223_126_4510_n119), .ICI(DP_OP_500J223_126_4510_n115), .S(
DP_OP_500J223_126_4510_n110), .ICO(DP_OP_500J223_126_4510_n108), .CO(
DP_OP_500J223_126_4510_n109) );
CMPR42X2TS DP_OP_500J223_126_4510_U113 ( .A(DP_OP_500J223_126_4510_n162),
.B(DP_OP_500J223_126_4510_n155), .C(DP_OP_500J223_126_4510_n107), .D(
DP_OP_500J223_126_4510_n111), .ICI(DP_OP_500J223_126_4510_n108), .S(
DP_OP_500J223_126_4510_n105), .ICO(DP_OP_500J223_126_4510_n103), .CO(
DP_OP_500J223_126_4510_n104) );
CMPR42X2TS DP_OP_500J223_126_4510_U112 ( .A(DP_OP_500J223_126_4510_n161),
.B(DP_OP_500J223_126_4510_n154), .C(DP_OP_500J223_126_4510_n147), .D(
DP_OP_500J223_126_4510_n106), .ICI(DP_OP_500J223_126_4510_n103), .S(
DP_OP_500J223_126_4510_n102), .ICO(DP_OP_500J223_126_4510_n100), .CO(
DP_OP_500J223_126_4510_n101) );
CMPR42X1TS DP_OP_502J223_128_4510_U125 ( .A(DP_OP_502J223_128_4510_n174),
.B(DP_OP_502J223_128_4510_n138), .C(DP_OP_502J223_128_4510_n141), .D(
DP_OP_502J223_128_4510_n181), .ICI(DP_OP_502J223_128_4510_n188), .S(
DP_OP_502J223_128_4510_n136), .ICO(DP_OP_502J223_128_4510_n134), .CO(
DP_OP_502J223_128_4510_n135) );
CMPR42X1TS DP_OP_502J223_128_4510_U121 ( .A(DP_OP_502J223_128_4510_n151),
.B(DP_OP_502J223_128_4510_n158), .C(DP_OP_502J223_128_4510_n132), .D(
DP_OP_502J223_128_4510_n165), .ICI(DP_OP_502J223_128_4510_n130), .S(
DP_OP_502J223_128_4510_n126), .ICO(DP_OP_502J223_128_4510_n124), .CO(
DP_OP_502J223_128_4510_n125) );
CMPR42X1TS DP_OP_502J223_128_4510_U118 ( .A(DP_OP_502J223_128_4510_n178),
.B(DP_OP_502J223_128_4510_n171), .C(DP_OP_502J223_128_4510_n121), .D(
DP_OP_502J223_128_4510_n125), .ICI(DP_OP_502J223_128_4510_n120), .S(
DP_OP_502J223_128_4510_n117), .ICO(DP_OP_502J223_128_4510_n115), .CO(
DP_OP_502J223_128_4510_n116) );
CMPR42X2TS DP_OP_502J223_128_4510_U112 ( .A(DP_OP_502J223_128_4510_n161),
.B(DP_OP_502J223_128_4510_n154), .C(DP_OP_502J223_128_4510_n147), .D(
DP_OP_502J223_128_4510_n106), .ICI(DP_OP_502J223_128_4510_n103), .S(
DP_OP_502J223_128_4510_n102), .ICO(DP_OP_502J223_128_4510_n100), .CO(
DP_OP_502J223_128_4510_n101) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_Result[3]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[5]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_Result[2]) );
DFFRX2TS R_60 ( .D(n2284), .CK(clk), .RN(n2393), .Q(n6917) );
DFFRX2TS R_61 ( .D(n6957), .CK(clk), .RN(n2392), .Q(n6916) );
DFFRX1TS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1864), .CK(clk), .RN(n7028),
.QN(n6876) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1954), .CK(clk), .RN(
n7033), .QN(n6838) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1689), .CK(clk), .RN(n7043), .Q(
FPMULT_FSM_selector_A), .QN(n6845) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1691), .CK(clk), .RN(n7012),
.Q(FPMULT_FS_Module_state_reg[1]), .QN(n6787) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1622), .CK(clk), .RN(n7049), .Q(
FPMULT_FSM_selector_B[1]), .QN(n6784) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1959), .CK(clk), .RN(
n7037), .QN(n6783) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2138), .CK(clk), .RN(n7025),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n6782) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1350), .CK(clk), .RN(
n6989), .Q(FPADDSUB_ADD_OVRFLW_NRM2), .QN(n6766) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2137), .CK(clk), .RN(n7024),
.Q(FPSENCOS_cont_var_out[0]), .QN(n6756) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n7026), .Q(NaN_flag)
);
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n1693), .CK(clk), .RN(n7012),
.Q(FPMULT_FS_Module_state_reg[3]), .QN(n6790) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1692), .CK(clk), .RN(n7012),
.Q(FPMULT_FS_Module_state_reg[0]), .QN(n6757) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[3]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[2]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n6870), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]) );
CMPR32X2TS intadd_515_U2 ( .A(mult_x_309_n14), .B(intadd_515_B_6_), .C(
intadd_515_n2), .CO(intadd_515_n1), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_512_U5 ( .A(intadd_512_A_4_), .B(intadd_512_B_4_), .C(
intadd_512_n5), .CO(intadd_512_n4), .S(intadd_512_SUM_4_) );
CMPR32X2TS intadd_512_U3 ( .A(intadd_512_A_6_), .B(intadd_512_B_6_), .C(
intadd_512_n3), .CO(intadd_512_n2), .S(intadd_512_SUM_6_) );
CMPR32X2TS intadd_514_U5 ( .A(intadd_514_A_4_), .B(intadd_514_B_4_), .C(
intadd_514_n5), .CO(intadd_514_n4), .S(intadd_514_SUM_4_) );
CMPR32X2TS intadd_514_U3 ( .A(intadd_514_A_6_), .B(intadd_514_B_6_), .C(
intadd_514_n3), .CO(intadd_514_n2), .S(intadd_514_SUM_6_) );
CMPR32X2TS intadd_513_U7 ( .A(mult_x_311_n36), .B(mult_x_311_n30), .C(
intadd_513_n7), .CO(intadd_513_n6), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_515_U6 ( .A(mult_x_309_n36), .B(mult_x_309_n30), .C(
intadd_515_n6), .CO(intadd_515_n5), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_515_U4 ( .A(mult_x_309_n22), .B(mult_x_309_n18), .C(
intadd_515_n4), .CO(intadd_515_n3), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7) );
CMPR42X2TS DP_OP_499J223_125_1651_U242 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .B(
DP_OP_499J223_125_1651_n252), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]), .D(
DP_OP_499J223_125_1651_n250), .ICI(DP_OP_499J223_125_1651_n281), .S(
DP_OP_499J223_125_1651_n249), .ICO(DP_OP_499J223_125_1651_n247), .CO(
DP_OP_499J223_125_1651_n248) );
CMPR42X2TS DP_OP_499J223_125_1651_U239 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]), .C(
DP_OP_499J223_125_1651_n241), .D(DP_OP_499J223_125_1651_n278), .ICI(
DP_OP_499J223_125_1651_n302), .S(DP_OP_499J223_125_1651_n240), .ICO(
DP_OP_499J223_125_1651_n238), .CO(DP_OP_499J223_125_1651_n239) );
CMPR42X2TS DP_OP_499J223_125_1651_U238 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]), .C(
DP_OP_499J223_125_1651_n238), .D(DP_OP_499J223_125_1651_n277), .ICI(
DP_OP_499J223_125_1651_n301), .S(DP_OP_499J223_125_1651_n237), .ICO(
DP_OP_499J223_125_1651_n235), .CO(DP_OP_499J223_125_1651_n236) );
CMPR42X2TS DP_OP_499J223_125_1651_U237 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]), .C(
DP_OP_499J223_125_1651_n235), .D(DP_OP_499J223_125_1651_n276), .ICI(
DP_OP_499J223_125_1651_n300), .S(DP_OP_499J223_125_1651_n234), .ICO(
DP_OP_499J223_125_1651_n232), .CO(DP_OP_499J223_125_1651_n233) );
CMPR42X2TS DP_OP_499J223_125_1651_U234 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .C(
DP_OP_499J223_125_1651_n273), .D(DP_OP_499J223_125_1651_n297), .ICI(
DP_OP_499J223_125_1651_n226), .S(DP_OP_499J223_125_1651_n225), .ICO(
DP_OP_499J223_125_1651_n223), .CO(DP_OP_499J223_125_1651_n224) );
CMPR42X2TS DP_OP_499J223_125_1651_U233 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .C(
DP_OP_499J223_125_1651_n272), .D(DP_OP_499J223_125_1651_n296), .ICI(
DP_OP_499J223_125_1651_n223), .S(DP_OP_499J223_125_1651_n222), .ICO(
DP_OP_499J223_125_1651_n220), .CO(DP_OP_499J223_125_1651_n221) );
CMPR42X2TS DP_OP_499J223_125_1651_U232 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .C(
DP_OP_499J223_125_1651_n271), .D(DP_OP_499J223_125_1651_n295), .ICI(
DP_OP_499J223_125_1651_n220), .S(DP_OP_499J223_125_1651_n219), .ICO(
DP_OP_499J223_125_1651_n217), .CO(DP_OP_499J223_125_1651_n218) );
CMPR42X2TS DP_OP_499J223_125_1651_U231 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .C(
DP_OP_499J223_125_1651_n270), .D(DP_OP_499J223_125_1651_n294), .ICI(
DP_OP_499J223_125_1651_n217), .S(DP_OP_499J223_125_1651_n216), .ICO(
DP_OP_499J223_125_1651_n214), .CO(DP_OP_499J223_125_1651_n215) );
CMPR42X2TS DP_OP_499J223_125_1651_U230 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .C(
DP_OP_499J223_125_1651_n269), .D(DP_OP_499J223_125_1651_n293), .ICI(
DP_OP_499J223_125_1651_n214), .S(DP_OP_499J223_125_1651_n213), .ICO(
DP_OP_499J223_125_1651_n211), .CO(DP_OP_499J223_125_1651_n212) );
CMPR42X2TS DP_OP_499J223_125_1651_U229 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]), .C(
DP_OP_499J223_125_1651_n268), .D(DP_OP_499J223_125_1651_n292), .ICI(
DP_OP_499J223_125_1651_n211), .S(DP_OP_499J223_125_1651_n210), .ICO(
DP_OP_499J223_125_1651_n208), .CO(DP_OP_499J223_125_1651_n209) );
CMPR42X2TS DP_OP_499J223_125_1651_U228 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .C(n2213),
.D(n2264), .ICI(DP_OP_499J223_125_1651_n208), .S(
DP_OP_499J223_125_1651_n207), .ICO(DP_OP_499J223_125_1651_n205), .CO(
DP_OP_499J223_125_1651_n206) );
CMPR42X2TS DP_OP_499J223_125_1651_U227 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .C(
DP_OP_499J223_125_1651_n266), .D(n2265), .ICI(
DP_OP_499J223_125_1651_n205), .S(DP_OP_499J223_125_1651_n204), .ICO(
DP_OP_499J223_125_1651_n202), .CO(DP_OP_499J223_125_1651_n203) );
CMPR42X2TS DP_OP_501J223_127_5235_U432 ( .A(DP_OP_501J223_127_5235_n503),
.B(DP_OP_501J223_127_5235_n509), .C(DP_OP_501J223_127_5235_n473), .D(
DP_OP_501J223_127_5235_n468), .ICI(DP_OP_501J223_127_5235_n467), .S(
DP_OP_501J223_127_5235_n464), .ICO(DP_OP_501J223_127_5235_n462), .CO(
DP_OP_501J223_127_5235_n463) );
CMPR42X2TS DP_OP_501J223_127_5235_U427 ( .A(DP_OP_501J223_127_5235_n495),
.B(DP_OP_501J223_127_5235_n460), .C(DP_OP_501J223_127_5235_n454), .D(
DP_OP_501J223_127_5235_n458), .ICI(DP_OP_501J223_127_5235_n455), .S(
DP_OP_501J223_127_5235_n452), .ICO(DP_OP_501J223_127_5235_n450), .CO(
DP_OP_501J223_127_5235_n451) );
CMPR42X2TS DP_OP_501J223_127_5235_U426 ( .A(DP_OP_501J223_127_5235_n500),
.B(DP_OP_501J223_127_5235_n494), .C(DP_OP_501J223_127_5235_n488), .D(
DP_OP_501J223_127_5235_n453), .ICI(DP_OP_501J223_127_5235_n450), .S(
DP_OP_501J223_127_5235_n449), .ICO(DP_OP_501J223_127_5235_n447), .CO(
DP_OP_501J223_127_5235_n448) );
CMPR42X2TS DP_OP_501J223_127_5235_U159 ( .A(DP_OP_501J223_127_5235_n190),
.B(DP_OP_501J223_127_5235_n247), .C(DP_OP_501J223_127_5235_n193), .D(
DP_OP_501J223_127_5235_n263), .ICI(DP_OP_501J223_127_5235_n191), .S(
DP_OP_501J223_127_5235_n188), .ICO(DP_OP_501J223_127_5235_n186), .CO(
DP_OP_501J223_127_5235_n187) );
CMPR42X2TS DP_OP_501J223_127_5235_U156 ( .A(DP_OP_501J223_127_5235_n262),
.B(DP_OP_501J223_127_5235_n186), .C(DP_OP_501J223_127_5235_n246), .D(
DP_OP_501J223_127_5235_n254), .ICI(DP_OP_501J223_127_5235_n183), .S(
DP_OP_501J223_127_5235_n181), .ICO(DP_OP_501J223_127_5235_n179), .CO(
DP_OP_501J223_127_5235_n180) );
CMPR42X2TS DP_OP_501J223_127_5235_U153 ( .A(DP_OP_501J223_127_5235_n245),
.B(DP_OP_501J223_127_5235_n182), .C(DP_OP_501J223_127_5235_n261), .D(
DP_OP_501J223_127_5235_n179), .ICI(DP_OP_501J223_127_5235_n176), .S(
DP_OP_501J223_127_5235_n173), .ICO(DP_OP_501J223_127_5235_n171), .CO(
DP_OP_501J223_127_5235_n172) );
CMPR42X2TS DP_OP_501J223_127_5235_U150 ( .A(DP_OP_501J223_127_5235_n174),
.B(DP_OP_501J223_127_5235_n236), .C(DP_OP_501J223_127_5235_n244), .D(
DP_OP_501J223_127_5235_n168), .ICI(DP_OP_501J223_127_5235_n252), .S(
DP_OP_501J223_127_5235_n166), .ICO(DP_OP_501J223_127_5235_n164), .CO(
DP_OP_501J223_127_5235_n165) );
CMPR42X2TS DP_OP_501J223_127_5235_U149 ( .A(DP_OP_501J223_127_5235_n228),
.B(DP_OP_501J223_127_5235_n171), .C(DP_OP_501J223_127_5235_n260), .D(
DP_OP_501J223_127_5235_n175), .ICI(DP_OP_501J223_127_5235_n166), .S(
DP_OP_501J223_127_5235_n163), .ICO(DP_OP_501J223_127_5235_n161), .CO(
DP_OP_501J223_127_5235_n162) );
CMPR42X2TS DP_OP_501J223_127_5235_U147 ( .A(DP_OP_501J223_127_5235_n167),
.B(DP_OP_501J223_127_5235_n235), .C(DP_OP_501J223_127_5235_n259), .D(
DP_OP_501J223_127_5235_n164), .ICI(DP_OP_501J223_127_5235_n243), .S(
DP_OP_501J223_127_5235_n157), .ICO(DP_OP_501J223_127_5235_n155), .CO(
DP_OP_501J223_127_5235_n156) );
CMPR42X2TS DP_OP_501J223_127_5235_U143 ( .A(DP_OP_501J223_127_5235_n151),
.B(DP_OP_501J223_127_5235_n250), .C(DP_OP_501J223_127_5235_n234), .D(
DP_OP_501J223_127_5235_n242), .ICI(DP_OP_501J223_127_5235_n159), .S(
DP_OP_501J223_127_5235_n147), .ICO(DP_OP_501J223_127_5235_n145), .CO(
DP_OP_501J223_127_5235_n146) );
CMPR42X2TS DP_OP_501J223_127_5235_U142 ( .A(DP_OP_501J223_127_5235_n149),
.B(DP_OP_501J223_127_5235_n155), .C(DP_OP_501J223_127_5235_n156), .D(
DP_OP_501J223_127_5235_n152), .ICI(DP_OP_501J223_127_5235_n147), .S(
DP_OP_501J223_127_5235_n144), .ICO(DP_OP_501J223_127_5235_n142), .CO(
DP_OP_501J223_127_5235_n143) );
CMPR42X2TS DP_OP_501J223_127_5235_U140 ( .A(DP_OP_501J223_127_5235_n150),
.B(DP_OP_501J223_127_5235_n241), .C(DP_OP_501J223_127_5235_n141), .D(
DP_OP_501J223_127_5235_n225), .ICI(DP_OP_501J223_127_5235_n145), .S(
DP_OP_501J223_127_5235_n139), .ICO(DP_OP_501J223_127_5235_n137), .CO(
DP_OP_501J223_127_5235_n138) );
CMPR42X2TS DP_OP_501J223_127_5235_U139 ( .A(DP_OP_501J223_127_5235_n233),
.B(DP_OP_501J223_127_5235_n148), .C(DP_OP_501J223_127_5235_n146), .D(
DP_OP_501J223_127_5235_n139), .ICI(DP_OP_501J223_127_5235_n142), .S(
DP_OP_501J223_127_5235_n136), .ICO(DP_OP_501J223_127_5235_n134), .CO(
DP_OP_501J223_127_5235_n135) );
CMPR42X2TS DP_OP_501J223_127_5235_U138 ( .A(DP_OP_501J223_127_5235_n200),
.B(DP_OP_501J223_127_5235_n208), .C(DP_OP_501J223_127_5235_n232), .D(
DP_OP_501J223_127_5235_n140), .ICI(DP_OP_501J223_127_5235_n216), .S(
DP_OP_501J223_127_5235_n133), .ICO(DP_OP_501J223_127_5235_n131), .CO(
DP_OP_501J223_127_5235_n132) );
CMPR42X2TS DP_OP_501J223_127_5235_U137 ( .A(DP_OP_501J223_127_5235_n224),
.B(DP_OP_501J223_127_5235_n137), .C(DP_OP_501J223_127_5235_n138), .D(
DP_OP_501J223_127_5235_n133), .ICI(DP_OP_501J223_127_5235_n134), .S(
DP_OP_501J223_127_5235_n130), .ICO(DP_OP_501J223_127_5235_n128), .CO(
DP_OP_501J223_127_5235_n129) );
CMPR42X2TS DP_OP_501J223_127_5235_U135 ( .A(DP_OP_501J223_127_5235_n207),
.B(DP_OP_501J223_127_5235_n131), .C(DP_OP_501J223_127_5235_n127), .D(
DP_OP_501J223_127_5235_n132), .ICI(DP_OP_501J223_127_5235_n128), .S(
DP_OP_501J223_127_5235_n125), .ICO(DP_OP_501J223_127_5235_n123), .CO(
DP_OP_501J223_127_5235_n124) );
CMPR42X2TS DP_OP_501J223_127_5235_U134 ( .A(DP_OP_501J223_127_5235_n214),
.B(DP_OP_501J223_127_5235_n198), .C(DP_OP_501J223_127_5235_n206), .D(
DP_OP_501J223_127_5235_n126), .ICI(DP_OP_501J223_127_5235_n123), .S(
DP_OP_501J223_127_5235_n122), .ICO(DP_OP_501J223_127_5235_n120), .CO(
DP_OP_501J223_127_5235_n121) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1832), .CK(clk), .RN(
n6965), .Q(FPADDSUB_intDY_EWSW[11]), .QN(n6748) );
DFFRXLTS R_41 ( .D(n1694), .CK(clk), .RN(n2365), .Q(n6926) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1333), .CK(clk), .RN(
n6988), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]), .QN(n6800) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1279), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SFG[9]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1250), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SFG[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1300), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SFG[7]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1238), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SFG[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1272), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SFG[5]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1234), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SFG[4]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1323), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SFG[3]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1307), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SFG[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1286), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SFG[1]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1293), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SFG[0]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1336), .CK(clk), .RN(
n6988), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1334), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1337), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1315), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1410), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n1658), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[0]), .QN(n2221) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n7040), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8])
);
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_513_n1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9])
);
DFFRXLTS R_23 ( .D(n1567), .CK(clk), .RN(n2392), .Q(n6938) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1608), .CK(clk),
.RN(n7054), .Q(FPMULT_Add_result[12]), .QN(n6886) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1958), .CK(clk), .RN(
n7036), .Q(FPSENCOS_d_ff2_X[24]), .QN(n6873) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1513), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[8]), .QN(n6759) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n1676), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[18]), .QN(n2491) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n1678), .CK(clk),
.RN(n7050), .Q(FPMULT_Op_MX[20]), .QN(n2478) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1838), .CK(clk), .RN(
n6968), .Q(FPADDSUB_intDY_EWSW[5]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1836), .CK(clk), .RN(
n6967), .Q(FPADDSUB_intDY_EWSW[7]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2075), .CK(clk), .RN(
n6966), .Q(FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n2263) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1827), .CK(clk), .RN(
n6964), .Q(FPADDSUB_intDY_EWSW[16]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1816), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDY_EWSW[27]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1834), .CK(clk), .RN(
n6968), .Q(FPADDSUB_intDY_EWSW[9]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1340), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1823), .CK(clk), .RN(
n6962), .Q(FPADDSUB_intDY_EWSW[20]), .QN(n2459) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1824), .CK(clk), .RN(
n6962), .Q(FPADDSUB_intDY_EWSW[19]), .QN(n2410) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1830), .CK(clk), .RN(
n6964), .Q(FPADDSUB_intDY_EWSW[13]), .QN(n2467) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1815), .CK(clk), .RN(
n6961), .Q(FPADDSUB_intDY_EWSW[28]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1831), .CK(clk), .RN(
n6965), .Q(FPADDSUB_intDY_EWSW[12]), .QN(n2455) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1821), .CK(clk), .RN(
n6961), .Q(FPADDSUB_intDY_EWSW[22]), .QN(n2409) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2076), .CK(clk), .RN(
n6966), .Q(FPADDSUB_shift_value_SHT2_EWR[3]), .QN(n6785) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1807), .CK(clk), .RN(n6962), .Q(FPADDSUB_Data_array_SWR[20]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1808), .CK(clk), .RN(n6961), .Q(FPADDSUB_Data_array_SWR[21]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1809), .CK(clk), .RN(n6967), .Q(FPADDSUB_Data_array_SWR[22]) );
DFFRX2TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(n7060), .CK(clk), .RN(n6959), .Q(
ready_add_subt) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1262), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SFG[10]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1254), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SFG[11]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1505), .CK(
clk), .RN(n7052), .Q(FPMULT_Sgf_normalized_result[0]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1507), .CK(
clk), .RN(n7048), .Q(FPMULT_Sgf_normalized_result[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1266), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SFG[12]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1810), .CK(clk), .RN(n6967), .Q(FPADDSUB_Data_array_SWR[23]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1820), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDY_EWSW[23]), .QN(n2438) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1349), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1835), .CK(clk), .RN(
n6964), .Q(FPADDSUB_intDY_EWSW[8]), .QN(n2442) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1210), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SFG[15]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1218), .CK(clk), .RN(n6997),
.Q(FPADDSUB_DMP_SFG[21]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1222), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SFG[19]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1230), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SFG[17]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1242), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SFG[13]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1840), .CK(clk), .RN(
n6966), .Q(FPADDSUB_intDY_EWSW[3]), .QN(n2397) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1214), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SFG[18]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1226), .CK(clk), .RN(n6997),
.Q(FPADDSUB_DMP_SFG[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1258), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SFG[14]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1800), .CK(clk), .RN(n6965), .Q(FPADDSUB_Data_array_SWR[13]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1246), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SFG[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1206), .CK(clk), .RN(n6997),
.Q(FPADDSUB_DMP_SFG[22]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1466), .CK(clk), .RN(
n6989), .QN(n2451) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2077), .CK(clk), .RN(
n6966), .Q(FPADDSUB_shift_value_SHT2_EWR[2]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n7025), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1511), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[6]), .QN(n2399) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n7025), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n6959),
.Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n6850) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1345), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n6791) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1343), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n6821) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1933), .CK(clk), .RN(
n6964), .Q(FPADDSUB_intDX_EWSW[8]), .QN(n2270) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1930), .CK(clk), .RN(
n6965), .Q(FPADDSUB_intDX_EWSW[11]), .QN(n2230) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1919), .CK(clk), .RN(
n6961), .Q(FPADDSUB_intDX_EWSW[22]), .QN(n2232) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1509), .CK(
clk), .RN(n7050), .Q(FPMULT_Sgf_normalized_result[4]), .QN(n2450) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1929), .CK(clk), .RN(
n6966), .Q(FPADDSUB_intDX_EWSW[12]), .QN(n2231) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1921), .CK(clk), .RN(
n6963), .Q(FPADDSUB_intDX_EWSW[20]), .QN(n2274) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1916), .CK(clk), .RN(
n6959), .Q(FPADDSUB_intDX_EWSW[25]), .QN(n6811) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1915), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDX_EWSW[26]), .QN(n6804) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1939), .CK(clk), .RN(
n6967), .Q(FPADDSUB_intDX_EWSW[2]), .QN(n2273) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1924), .CK(clk), .RN(
n6963), .Q(FPADDSUB_intDX_EWSW[17]), .QN(n2432) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1923), .CK(clk), .RN(
n6962), .Q(FPADDSUB_intDX_EWSW[18]), .QN(n2272) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1332), .CK(clk), .RN(
n6988), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]), .QN(n6758) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n7025), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2148), .CK(clk), .RN(
n6959), .Q(FPADDSUB_Shift_reg_FLAGS_7_6), .QN(n6829) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1855), .CK(clk), .RN(
n7032), .Q(FPSENCOS_d_ff2_Y[29]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1857), .CK(clk), .RN(
n7034), .Q(FPSENCOS_d_ff2_Y[27]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1940), .CK(clk), .RN(
n6968), .Q(FPADDSUB_intDX_EWSW[1]), .QN(n2434) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1797), .CK(clk), .RN(n6968), .Q(FPADDSUB_Data_array_SWR[10]) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1585), .CK(clk), .RN(
n7050), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1854), .CK(clk), .RN(
n7032), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1861), .CK(clk), .RN(
n7037), .Q(FPSENCOS_d_ff2_Y[23]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1341), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n6795) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1516), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1518), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1520), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[15]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1522), .CK(
clk), .RN(n7051), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1524), .CK(
clk), .RN(n7046), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1526), .CK(
clk), .RN(n7058), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1428), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1448), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1517), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1519), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1521), .CK(
clk), .RN(n7052), .Q(FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1523), .CK(
clk), .RN(n7048), .Q(FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1525), .CK(
clk), .RN(n7050), .Q(FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1527), .CK(
clk), .RN(n7051), .Q(FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n1556), .CK(clk),
.RN(n7013), .Q(FPMULT_P_Sgf[27]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n1559), .CK(clk),
.RN(n7014), .Q(FPMULT_P_Sgf[30]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n1562), .CK(clk),
.RN(n7019), .Q(FPMULT_P_Sgf[33]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n1564), .CK(clk),
.RN(n4493), .Q(FPMULT_P_Sgf[35]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1941), .CK(clk), .RN(
n6967), .Q(FPADDSUB_intDX_EWSW[0]), .QN(n2275) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n1686), .CK(clk),
.RN(n7058), .Q(FPMULT_Op_MX[28]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1858), .CK(clk), .RN(
n7035), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1859), .CK(clk), .RN(
n7035), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1860), .CK(clk), .RN(
n7036), .Q(FPSENCOS_d_ff2_Y[24]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1198), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n6776) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1200), .CK(clk), .RN(
n6990), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n6777) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n1688), .CK(clk),
.RN(n7046), .Q(FPMULT_Op_MX[30]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1934), .CK(clk), .RN(
n6967), .Q(FPADDSUB_intDX_EWSW[7]), .QN(n2269) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1793), .CK(clk), .RN(n6963),
.Q(FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1462), .CK(clk), .RN(n6969),
.Q(FPADDSUB_DMP_EXP_EWSW[26]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1463), .CK(clk), .RN(n6969),
.Q(FPADDSUB_DMP_EXP_EWSW[25]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1346), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n6796) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1348), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n6793) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n1553), .CK(clk),
.RN(n7012), .Q(FPMULT_P_Sgf[24]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1911), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDX_EWSW[30]), .QN(n6810) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1811), .CK(clk), .RN(n6967), .Q(FPADDSUB_Data_array_SWR[24]), .QN(n6816) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1912), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDX_EWSW[29]), .QN(n6812) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n6999),
.Q(operation_reg[0]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1344), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n6780) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1794), .CK(clk), .RN(n6964),
.Q(FPADDSUB_Data_array_SWR[7]) );
DFFRX1TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1352), .CK(clk), .RN(n6990),
.Q(FPADDSUB_OP_FLAG_SFG) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1791), .CK(clk), .RN(n6969),
.Q(FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1792), .CK(clk), .RN(n6961),
.Q(FPADDSUB_Data_array_SWR[5]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1656), .CK(clk),
.RN(n7053), .Q(FPMULT_Op_MY[30]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n1681), .CK(clk),
.RN(n7048), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1654), .CK(clk),
.RN(n7053), .Q(FPMULT_Op_MY[28]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1733), .CK(clk), .RN(
n7001), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1588), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1590), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1591), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1592), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1593), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[1]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1973), .CK(clk), .RN(
n7005), .QN(n2417) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1979), .CK(clk), .RN(
n7006), .QN(n2425) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1993), .CK(clk), .RN(
n7007), .QN(n2422) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1649), .CK(clk),
.RN(n7046), .Q(FPMULT_Op_MY[23]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1339), .CK(clk), .RN(
n6988), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]), .QN(n6799) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1201), .CK(clk), .RN(
n6990), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n6773) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1202), .CK(clk), .RN(
n6990), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n6778) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1196), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n6779) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1197), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n6774) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1199), .CK(clk), .RN(
n6990), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n6775) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2058), .CK(clk), .RN(n7016), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2046), .CK(clk), .RN(n7017), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2070), .CK(clk), .RN(n7018), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2073), .CK(clk), .RN(n4495), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2052), .CK(clk), .RN(n7020), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2067), .CK(clk), .RN(n6999), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2064), .CK(clk), .RN(n7000), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2037), .CK(clk), .RN(n7001), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2043), .CK(clk), .RN(n7002), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2031), .CK(clk), .RN(n7003), .Q(
FPSENCOS_d_ff_Yn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2040), .CK(clk), .RN(n7004), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2049), .CK(clk), .RN(n7005), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2025), .CK(clk), .RN(n7005), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2034), .CK(clk), .RN(n7006), .Q(
FPSENCOS_d_ff_Yn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2055), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2061), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2022), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff_Yn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2013), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff_Yn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2016), .CK(clk), .RN(n2393), .Q(
FPSENCOS_d_ff_Yn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2010), .CK(clk), .RN(n7029), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2019), .CK(clk), .RN(n7029), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2028), .CK(clk), .RN(n7030), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2007), .CK(clk), .RN(n7031), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1727), .CK(clk), .RN(n7000), .Q(
FPSENCOS_d_ff_Xn[31]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1770), .CK(clk), .RN(n7033), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1910), .CK(clk), .RN(
n6966), .Q(FPADDSUB_intDX_EWSW[31]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1985), .CK(clk), .RN(
n7002), .QN(n2449) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2045), .CK(clk), .RN(n7017), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2072), .CK(clk), .RN(n7018), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2039), .CK(clk), .RN(n7003), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2048), .CK(clk), .RN(n7004), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2060), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2009), .CK(clk), .RN(n7028), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2018), .CK(clk), .RN(n7029), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2027), .CK(clk), .RN(n7030), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2006), .CK(clk), .RN(n7031), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1784), .CK(clk), .RN(n7036), .Q(
FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2078), .CK(clk), .RN(
n6991), .Q(FPADDSUB_left_right_SHT2), .QN(n2235) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1418), .CK(clk), .RN(
n4497), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n1548), .CK(clk),
.RN(n7011), .Q(FPMULT_P_Sgf[19]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1438), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1423), .CK(clk), .RN(
n4487), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1433), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1443), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1331), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n2256) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1936), .CK(clk), .RN(
n6968), .Q(FPADDSUB_intDX_EWSW[5]), .QN(n2465) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1913), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDX_EWSW[28]), .QN(n2464) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1728), .CK(clk), .RN(
n6966), .Q(FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1453), .CK(clk), .RN(
n6997), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n1530), .CK(clk),
.RN(n4493), .Q(FPMULT_P_Sgf[1]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n1538), .CK(clk),
.RN(n7014), .Q(FPMULT_P_Sgf[9]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n1542), .CK(clk),
.RN(n7012), .Q(FPMULT_P_Sgf[13]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1713), .CK(clk), .RN(n7015),
.Q(cordic_result[13]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1710), .CK(clk), .RN(n7015),
.Q(cordic_result[16]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1712), .CK(clk), .RN(n7015),
.Q(cordic_result[14]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1714), .CK(clk), .RN(n7015),
.Q(cordic_result[12]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1725), .CK(clk), .RN(n7017),
.Q(cordic_result[1]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1696), .CK(clk), .RN(n7031),
.Q(cordic_result[30]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1697), .CK(clk), .RN(n7032),
.Q(cordic_result[29]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1698), .CK(clk), .RN(n7033),
.Q(cordic_result[28]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1699), .CK(clk), .RN(n7033),
.Q(cordic_result[27]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1700), .CK(clk), .RN(n7034),
.Q(cordic_result[26]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1701), .CK(clk), .RN(n7035),
.Q(cordic_result[25]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1702), .CK(clk), .RN(n7036),
.Q(cordic_result[24]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1703), .CK(clk), .RN(n7036),
.Q(cordic_result[23]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1387), .CK(clk), .RN(
n6974), .Q(result_add_subt[4]), .QN(n2280) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n7026), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n7041), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n4495), .Q(
dataA[29]) );
DFFRX1TS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n7026), .Q(
dataB[29]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2116), .CK(clk), .RN(n7022), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2129), .CK(clk), .RN(n7024), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2131), .CK(clk), .RN(n7024), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2133), .CK(clk), .RN(n7024), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n1597), .CK(clk),
.RN(n7053), .Q(FPMULT_Add_result[23]), .QN(n6898) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2118), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2122), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2124), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n1596), .CK(clk),
.RN(n7053), .Q(FPMULT_FSM_add_overflow_flag) );
DFFRX1TS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n7026), .Q(
dataB[27]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2128), .CK(clk), .RN(n7024), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1833), .CK(clk), .RN(
n6965), .Q(FPADDSUB_intDY_EWSW[10]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1841), .CK(clk), .RN(
n6967), .Q(FPADDSUB_intDY_EWSW[2]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1822), .CK(clk), .RN(
n6962), .Q(FPADDSUB_intDY_EWSW[21]), .QN(n2448) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1829), .CK(clk), .RN(
n6965), .Q(FPADDSUB_intDY_EWSW[14]), .QN(n2398) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1843), .CK(clk), .RN(
n6967), .Q(FPADDSUB_intDY_EWSW[0]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2143), .CK(clk), .RN(
n4486), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n7059) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1918), .CK(clk), .RN(
n6959), .Q(FPADDSUB_intDX_EWSW[23]), .QN(n6805) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1826), .CK(clk), .RN(
n6963), .Q(FPADDSUB_intDY_EWSW[17]), .QN(n2460) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1828), .CK(clk), .RN(
n6961), .Q(FPADDSUB_intDY_EWSW[15]), .QN(n2461) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1825), .CK(clk), .RN(
n6962), .Q(FPADDSUB_intDY_EWSW[18]), .QN(n2466) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1842), .CK(clk), .RN(
n6968), .Q(FPADDSUB_intDY_EWSW[1]), .QN(n2433) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1803), .CK(clk), .RN(n6963), .Q(FPADDSUB_Data_array_SWR[16]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1801), .CK(clk), .RN(n6964), .Q(FPADDSUB_Data_array_SWR[14]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1804), .CK(clk), .RN(n6968), .Q(FPADDSUB_Data_array_SWR[17]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1839), .CK(clk), .RN(
n6963), .Q(FPADDSUB_intDY_EWSW[4]), .QN(n6761) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1806), .CK(clk), .RN(n6963), .Q(FPADDSUB_Data_array_SWR[19]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1818), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDY_EWSW[25]), .QN(n2421) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1817), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDY_EWSW[26]), .QN(n2423) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n6439), .CK(clk),
.RN(n7025), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1914), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDX_EWSW[27]), .QN(n2215) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1932), .CK(clk), .RN(
n6968), .Q(FPADDSUB_intDX_EWSW[9]), .QN(n2234) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1814), .CK(clk), .RN(
n6961), .Q(FPADDSUB_intDY_EWSW[29]), .QN(n2430) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1347), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]), .QN(n6760) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1927), .CK(clk), .RN(
n6965), .Q(FPADDSUB_intDX_EWSW[14]), .QN(n2233) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1928), .CK(clk), .RN(
n6964), .Q(FPADDSUB_intDX_EWSW[13]), .QN(n2413) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1796), .CK(clk), .RN(n6965),
.Q(FPADDSUB_Data_array_SWR[9]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1795), .CK(clk), .RN(n6968),
.Q(FPADDSUB_Data_array_SWR[8]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1922), .CK(clk), .RN(
n6962), .Q(FPADDSUB_intDX_EWSW[19]), .QN(n2271) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1813), .CK(clk), .RN(
n6961), .Q(FPADDSUB_intDY_EWSW[30]), .QN(n2412) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1917), .CK(clk), .RN(
n6959), .Q(FPADDSUB_intDX_EWSW[24]), .QN(n6803) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1937), .CK(clk), .RN(
n6963), .Q(FPADDSUB_intDX_EWSW[4]), .QN(n6813) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1798), .CK(clk), .RN(n6965), .Q(FPADDSUB_Data_array_SWR[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1506), .CK(
clk), .RN(n7051), .Q(FPMULT_Sgf_normalized_result[1]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n1563), .CK(clk),
.RN(n7019), .Q(FPMULT_P_Sgf[34]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n1560), .CK(clk),
.RN(n7042), .Q(FPMULT_P_Sgf[31]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n1558), .CK(clk),
.RN(n7010), .Q(FPMULT_P_Sgf[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1931), .CK(clk), .RN(
n6965), .Q(FPADDSUB_intDX_EWSW[10]), .QN(n2407) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1464), .CK(clk), .RN(n6969),
.Q(FPADDSUB_DMP_EXP_EWSW[24]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n1685), .CK(clk),
.RN(n7052), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n1683), .CK(clk),
.RN(n7050), .Q(FPMULT_Op_MX[25]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1812), .CK(clk), .RN(n6967), .Q(FPADDSUB_Data_array_SWR[25]), .QN(n2504) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n1557), .CK(clk),
.RN(n7013), .Q(FPMULT_P_Sgf[28]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1805), .CK(clk), .RN(n6968), .Q(FPADDSUB_Data_array_SWR[18]), .QN(n6842) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2149), .CK(
clk), .RN(n6959), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.QN(n6826) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1190), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n6858) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1925), .CK(clk), .RN(
n6964), .Q(FPADDSUB_intDX_EWSW[16]), .QN(n2408) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1193), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n6860) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1192), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n6859) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n1682), .CK(clk),
.RN(n7051), .Q(FPMULT_Op_MX[24]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1195), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n6856) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2191), .CK(
clk), .RN(n6959), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.QN(n6772) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1655), .CK(clk),
.RN(n7053), .Q(FPMULT_Op_MY[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1935), .CK(clk), .RN(
n6963), .Q(FPADDSUB_intDX_EWSW[6]), .QN(n2411) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n7028),
.Q(operation_reg[1]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1184), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n6823) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1182), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n6843) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1188), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n6807) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1186), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n6817) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1203), .CK(clk), .RN(
n6990), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n6861) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1194), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n6863) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1773), .CK(clk), .RN(n7034), .Q(
FPSENCOS_d_ff_Yn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1767), .CK(clk), .RN(n7032), .Q(
FPSENCOS_d_ff_Yn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1779), .CK(clk), .RN(n7035), .Q(
FPSENCOS_d_ff_Yn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1776), .CK(clk), .RN(n7035), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1785), .CK(clk), .RN(n7037), .Q(
FPSENCOS_d_ff_Yn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1782), .CK(clk), .RN(n7036), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1730), .CK(clk), .RN(n7032), .Q(
FPSENCOS_d_ff_Yn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1729), .CK(clk), .RN(n7032), .Q(
FPSENCOS_d_ff_Xn[30]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1313), .CK(clk), .RN(
n6978), .QN(n6834) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1278), .CK(clk), .RN(
n6980), .QN(n6836) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1366), .CK(clk), .RN(
n6976), .QN(n6831) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(
n6976), .QN(n6830) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1285), .CK(clk), .RN(
n6980), .QN(n6837) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n1544), .CK(clk),
.RN(n2365), .Q(FPMULT_P_Sgf[15]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n1546), .CK(clk),
.RN(n2365), .Q(FPMULT_P_Sgf[17]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n1552), .CK(clk),
.RN(n2365), .Q(FPMULT_P_Sgf[23]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n1554), .CK(clk),
.RN(n2365), .Q(FPMULT_P_Sgf[25]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1476), .CK(clk), .RN(
n6969), .QN(n6820) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2134), .CK(clk), .RN(n7024),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n2266) );
DFFRXLTS R_17 ( .D(n1575), .CK(clk), .RN(n2365), .Q(n6943) );
DFFRXLTS R_19 ( .D(n6956), .CK(clk), .RN(n7010), .Q(n6941) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1720), .CK(clk), .RN(n7011),
.Q(cordic_result[6]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1722), .CK(clk), .RN(n7010),
.Q(cordic_result[4]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1709), .CK(clk), .RN(n4498),
.Q(cordic_result[17]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1706), .CK(clk), .RN(n4496),
.Q(cordic_result[20]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1707), .CK(clk), .RN(n7011),
.Q(cordic_result[19]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1705), .CK(clk), .RN(n7010),
.Q(cordic_result[21]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1708), .CK(clk), .RN(n2393),
.Q(cordic_result[18]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1711), .CK(clk), .RN(n7041),
.Q(cordic_result[15]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1704), .CK(clk), .RN(n2365),
.Q(cordic_result[22]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1342), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]), .QN(n6819) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n1549), .CK(clk),
.RN(n7019), .Q(FPMULT_P_Sgf[20]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n1547), .CK(clk),
.RN(n4496), .Q(FPMULT_P_Sgf[18]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n1543), .CK(clk),
.RN(n7014), .Q(FPMULT_P_Sgf[14]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n1532), .CK(clk),
.RN(n7019), .Q(FPMULT_P_Sgf[3]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n1550), .CK(clk),
.RN(n7013), .Q(FPMULT_P_Sgf[21]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n1539), .CK(clk),
.RN(n4498), .Q(FPMULT_P_Sgf[10]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n1534), .CK(clk),
.RN(n7014), .Q(FPMULT_P_Sgf[5]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n7026), .Q(
dataB[28]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n1545), .CK(clk),
.RN(n7014), .Q(FPMULT_P_Sgf[16]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n1541), .CK(clk),
.RN(n7042), .Q(FPMULT_P_Sgf[12]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n1533), .CK(clk),
.RN(n4495), .Q(FPMULT_P_Sgf[4]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1731), .CK(clk), .RN(
n6966), .Q(FPADDSUB_intAS) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2140), .CK(clk), .RN(n7025),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n6768) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2127), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1620), .CK(clk), .RN(
n7053), .Q(FPMULT_Add_result[0]) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n7042), .Q(
dataB[23]) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n7027), .Q(
dataA[25]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n7027), .Q(
dataA[28]) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n7026), .Q(
dataB[26]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1778), .CK(clk), .RN(n7035), .Q(
FPSENCOS_d_ff_Xn[25]), .QN(n2452) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1766), .CK(clk), .RN(n7032), .Q(
FPSENCOS_d_ff_Xn[29]), .QN(n2431) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2054), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff_Xn[6]), .QN(n2440) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2033), .CK(clk), .RN(n7006), .Q(
FPSENCOS_d_ff_Xn[13]), .QN(n2424) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2024), .CK(clk), .RN(n7005), .Q(
FPSENCOS_d_ff_Xn[16]), .QN(n2414) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2042), .CK(clk), .RN(n7002), .Q(
FPSENCOS_d_ff_Xn[10]), .QN(n2447) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2066), .CK(clk), .RN(n7020), .Q(
FPSENCOS_d_ff_Xn[2]), .QN(n2401) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n7027), .Q(
dataA[23]) );
DFFRX1TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n7027), .Q(
dataA[27]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n4495), .Q(
dataB[24]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1413), .CK(clk), .RN(n6973),
.Q(FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n7025), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n1684), .CK(clk),
.RN(n7046), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n1687), .CK(clk),
.RN(n7058), .Q(FPMULT_Op_MX[29]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n1555), .CK(clk),
.RN(n7014), .Q(FPMULT_P_Sgf[26]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1204), .CK(clk), .RN(
n6990), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]), .QN(n6755) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1652), .CK(clk),
.RN(n7058), .Q(FPMULT_Op_MY[26]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1594), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1589), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1587), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1653), .CK(clk),
.RN(n7053), .Q(FPMULT_Op_MY[27]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1461), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1651), .CK(clk),
.RN(n7052), .Q(FPMULT_Op_MY[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1961), .CK(clk), .RN(
n7031), .QN(n2416) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1865), .CK(clk), .RN(
n7029), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1899), .CK(clk), .RN(
n7008), .Q(FPSENCOS_d_ff2_Y[4]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1895), .CK(clk), .RN(
n7007), .Q(FPSENCOS_d_ff2_Y[6]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1891), .CK(clk), .RN(
n7004), .Q(FPSENCOS_d_ff2_Y[8]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1887), .CK(clk), .RN(
n7002), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1883), .CK(clk), .RN(
n7001), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1903), .CK(clk), .RN(
n7004), .Q(FPSENCOS_d_ff2_Y[2]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1907), .CK(clk), .RN(
n4493), .Q(FPSENCOS_d_ff2_Y[0]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1905), .CK(clk), .RN(
n7018), .Q(FPSENCOS_d_ff2_Y[1]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1889), .CK(clk), .RN(
n7017), .Q(FPSENCOS_d_ff2_Y[9]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1863), .CK(clk), .RN(
n7031), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1877), .CK(clk), .RN(
n7030), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1871), .CK(clk), .RN(
n7029), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1869), .CK(clk), .RN(
n2392), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1867), .CK(clk), .RN(
n7009), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1873), .CK(clk), .RN(
n7008), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1881), .CK(clk), .RN(
n7006), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1875), .CK(clk), .RN(
n7005), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1885), .CK(clk), .RN(
n7004), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1879), .CK(clk), .RN(
n7003), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1845), .CK(clk), .RN(
n7000), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1901), .CK(clk), .RN(
n6999), .Q(FPSENCOS_d_ff2_Y[3]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1893), .CK(clk), .RN(
n7019), .Q(FPSENCOS_d_ff2_Y[7]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1897), .CK(clk), .RN(
n7016), .Q(FPSENCOS_d_ff2_Y[5]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1191), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n6862) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1908), .CK(clk), .RN(n7000), .Q(
FPSENCOS_d_ff_Yn[31]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1189), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n6809) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1187), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n6808) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1185), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n6818) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1183), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n6824) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1181), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n6844) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1650), .CK(clk),
.RN(n7048), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1732), .CK(clk), .RN(n7000), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11), .CK(clk), .QN(DP_OP_496J223_122_3236_n147) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1926), .CK(clk), .RN(
n6961), .Q(FPADDSUB_intDX_EWSW[15]), .QN(n2279) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1938), .CK(clk), .RN(
n6966), .Q(FPADDSUB_intDX_EWSW[3]), .QN(n2278) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1920), .CK(clk), .RN(
n6962), .Q(FPADDSUB_intDX_EWSW[21]), .QN(n2277) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(
n6979), .Q(n2276) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n1637), .CK(clk),
.RN(n7052), .Q(FPMULT_Op_MY[11]), .QN(n2219) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1635), .CK(clk),
.RN(n7046), .Q(FPMULT_Op_MY[9]), .QN(n2225) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n1666), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[8]), .QN(n2259) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n1679), .CK(clk),
.RN(n7046), .Q(FPMULT_Op_MX[21]), .QN(n2255) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n1628), .CK(clk),
.RN(n7048), .Q(FPMULT_Op_MY[2]), .QN(n2248) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n1680), .CK(clk),
.RN(n7058), .Q(FPMULT_Op_MX[22]), .QN(n2239) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n1669), .CK(clk),
.RN(n7057), .Q(n2403), .QN(n6767) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2146), .CK(clk), .RN(
n6959), .Q(n7077), .QN(n6915) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n1647), .CK(clk),
.RN(n7051), .Q(n2228), .QN(n2237) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n1648), .CK(clk),
.RN(n7046), .Q(n2223), .QN(n2238) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n1638), .CK(clk),
.RN(n7051), .Q(FPMULT_Op_MY[12]), .QN(n2484) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n1668), .CK(clk),
.RN(n7057), .Q(n6750), .QN(n6769) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n1665), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[7]), .QN(n6794) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n1641), .CK(clk),
.RN(n7052), .Q(FPMULT_Op_MY[15]), .QN(n2214) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n1633), .CK(clk),
.RN(n7052), .Q(n6764), .QN(n6770) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n1629), .CK(clk),
.RN(n7050), .Q(FPMULT_Op_MY[3]), .QN(n2260) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n6828), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[3]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10])
);
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[9])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[11])
);
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n7064), .CK(clk), .Q(FPMULT_Sgf_operation_Result[0]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n6906), .CK(clk), .Q(FPMULT_Sgf_operation_Result[1]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10])
);
DFFQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11])
);
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]) );
DFFQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n2490), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13])
);
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0])
);
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n6827), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[2])
);
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[4])
);
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11])
);
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n7065), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]) );
DFFRXLTS R_0 ( .D(n1569), .CK(clk), .RN(n2393), .Q(n6954) );
DFFSX1TS R_1 ( .D(FPMULT_Sgf_operation_Result[40]), .CK(clk), .SN(n2392),
.Q(n6953) );
DFFRXLTS R_3 ( .D(n1573), .CK(clk), .RN(n2392), .Q(n6952) );
DFFSX1TS R_4 ( .D(FPMULT_Sgf_operation_Result[44]), .CK(clk), .SN(n2392),
.Q(n6951) );
DFFRXLTS R_6 ( .D(n1570), .CK(clk), .RN(n2391), .Q(n6950) );
DFFSX1TS R_7 ( .D(FPMULT_Sgf_operation_Result[41]), .CK(clk), .SN(n2392),
.Q(n6949) );
DFFRXLTS R_9 ( .D(n1565), .CK(clk), .RN(n2391), .Q(n6948) );
DFFSX1TS R_10 ( .D(FPMULT_Sgf_operation_Result[36]), .CK(clk), .SN(n2393),
.Q(n6947) );
DFFSX1TS R_12 ( .D(n7076), .CK(clk), .SN(n6973), .Q(n6946), .QN(n6857) );
DFFSX1TS R_13 ( .D(n7073), .CK(clk), .SN(n6972), .QN(n6848) );
DFFSX1TS R_14 ( .D(n7075), .CK(clk), .SN(n6973), .Q(n6945), .QN(n6847) );
DFFSX1TS R_15 ( .D(n7074), .CK(clk), .SN(n6972), .Q(n6944), .QN(n6846) );
DFFSX1TS R_16 ( .D(n7072), .CK(clk), .SN(n6969), .Q(n6763), .QN(n6822) );
DFFSX1TS R_18 ( .D(FPMULT_Sgf_operation_Result[46]), .CK(clk), .SN(n2391),
.Q(n6942) );
DFFRXLTS R_20 ( .D(n1571), .CK(clk), .RN(n2391), .Q(n6940) );
DFFSX1TS R_21 ( .D(FPMULT_Sgf_operation_Result[42]), .CK(clk), .SN(n2393),
.Q(n6939) );
DFFSX1TS R_24 ( .D(FPMULT_Sgf_operation_Result[38]), .CK(clk), .SN(n2393),
.Q(n6937) );
DFFRXLTS R_26 ( .D(n1574), .CK(clk), .RN(n2391), .Q(n6936) );
DFFSX1TS R_27 ( .D(FPMULT_Sgf_operation_Result[45]), .CK(clk), .SN(n2392),
.Q(n6935) );
DFFRXLTS R_29 ( .D(n1568), .CK(clk), .RN(n2391), .Q(n6934) );
DFFSX1TS R_30 ( .D(FPMULT_Sgf_operation_Result[39]), .CK(clk), .SN(n2393),
.Q(n6933) );
DFFRXLTS R_32 ( .D(n1561), .CK(clk), .RN(n7042), .Q(n6932) );
DFFSX1TS R_33 ( .D(FPMULT_Sgf_operation_Result[32]), .CK(clk), .SN(n7010),
.Q(n6931) );
DFFRXLTS R_35 ( .D(n1566), .CK(clk), .RN(n2391), .Q(n6930) );
DFFSX1TS R_36 ( .D(FPMULT_Sgf_operation_Result[37]), .CK(clk), .SN(n2392),
.Q(n6929) );
DFFRXLTS R_38 ( .D(n1572), .CK(clk), .RN(n2391), .Q(n6928) );
DFFSX1TS R_39 ( .D(FPMULT_Sgf_operation_Result[43]), .CK(clk), .SN(n2393),
.Q(n6927) );
DFFSX1TS R_42 ( .D(FPMULT_Sgf_operation_Result[47]), .CK(clk), .SN(n2365),
.Q(n6925) );
DFFRXLTS R_43 ( .D(n6958), .CK(clk), .RN(n7012), .Q(n6924) );
DFFRX1TS R_46 ( .D(n6922), .CK(clk), .RN(n4494), .Q(
DP_OP_501J223_127_5235_n897) );
DFFSX1TS R_50 ( .D(n6921), .CK(clk), .SN(n7041), .Q(n7070) );
DFFSX1TS R_58 ( .D(n6919), .CK(clk), .SN(n4496), .Q(n7069) );
DFFRX1TS R_59 ( .D(n6918), .CK(clk), .RN(n7028), .Q(n7068) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12])
);
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n1690), .CK(clk), .RN(n7020),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n6751) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]) );
DFFSX2TS R_45 ( .D(n6923), .CK(clk), .SN(n7048), .Q(n7062), .QN(n6955) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1618), .CK(clk), .RN(
n7053), .Q(FPMULT_Add_result[2]), .QN(n6896) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1619), .CK(clk), .RN(
n7053), .Q(FPMULT_Add_result[1]), .QN(n6897) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n1623), .CK(clk), .RN(n4494), .Q(
FPMULT_FSM_selector_B[0]), .QN(n6781) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1617), .CK(clk), .RN(
n7053), .Q(FPMULT_Add_result[3]), .QN(n6895) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1616), .CK(clk), .RN(
n7054), .Q(FPMULT_Add_result[4]), .QN(n6894) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1609), .CK(clk),
.RN(n7054), .Q(FPMULT_Add_result[11]), .QN(n6887) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n7026), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .QN(n6797) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1612), .CK(clk), .RN(
n7054), .Q(FPMULT_Add_result[8]), .QN(n6890) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1615), .CK(clk), .RN(
n7054), .Q(FPMULT_Add_result[5]), .QN(n6893) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n7025), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .QN(n6786) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1611), .CK(clk), .RN(
n7054), .Q(FPMULT_Add_result[9]), .QN(n6889) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1610), .CK(clk),
.RN(n7054), .Q(FPMULT_Add_result[10]), .QN(n6888) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1607), .CK(clk),
.RN(n7054), .Q(FPMULT_Add_result[13]), .QN(n6885) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1614), .CK(clk), .RN(
n7054), .Q(FPMULT_Add_result[6]), .QN(n6892) );
DFFRX1TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2136), .CK(clk), .RN(n7024),
.Q(FPSENCOS_cont_var_out[1]), .QN(n6802) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1613), .CK(clk), .RN(
n7054), .Q(FPMULT_Add_result[7]), .QN(n6891) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1338), .CK(clk), .RN(
n6988), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n6752) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1605), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[15]), .QN(n6883) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1953), .CK(clk), .RN(
n7032), .Q(FPSENCOS_d_ff2_X[29]), .QN(n6871) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1955), .CK(clk), .RN(
n7034), .Q(FPSENCOS_d_ff2_X[27]), .QN(n6872) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1956), .CK(clk), .RN(
n7034), .Q(FPSENCOS_d_ff2_X[26]), .QN(n6875) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1957), .CK(clk), .RN(
n7035), .Q(FPSENCOS_d_ff2_X[25]), .QN(n6874) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1604), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[16]), .QN(n6882) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2080), .CK(clk), .RN(n7037),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n6825) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1603), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[17]), .QN(n6881) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1856), .CK(clk), .RN(
n7033), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n6841) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1952), .CK(clk), .RN(
n7031), .Q(FPSENCOS_d_ff2_X[30]), .QN(n6851) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1602), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[18]), .QN(n6880) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1508), .CK(
clk), .RN(n7051), .Q(FPMULT_Sgf_normalized_result[3]), .QN(n6788) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1515), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[10]), .QN(n6865) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1601), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[19]), .QN(n6879) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1320), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n6869) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1319), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]), .QN(n6801) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1512), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[7]), .QN(n6866) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1510), .CK(
clk), .RN(n7046), .Q(FPMULT_Sgf_normalized_result[5]), .QN(n6792) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1600), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[20]), .QN(n6878) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1595), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[8]), .QN(n6762) );
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1586), .CK(clk), .RN(
n7058), .Q(underflow_flag_mult), .QN(n6864) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1599), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[21]), .QN(n6877) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(
n6975), .Q(result_add_subt[6]), .QN(n6839) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1306), .CK(clk), .RN(
n6978), .Q(result_add_subt[7]), .QN(n6840) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1335), .CK(clk), .RN(
n6988), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n7063) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n1662), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[4]), .QN(n2480) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n1661), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[3]), .QN(n2216) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n1643), .CK(clk),
.RN(n7050), .Q(FPMULT_Op_MY[17]), .QN(n2463) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n1674), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[16]), .QN(n2406) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1528), .CK(clk), .RN(n7048), .Q(
FPMULT_FSM_selector_C) );
DFFSX1TS R_51 ( .D(n6920), .CK(clk), .SN(n7011), .Q(n7071) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1837), .CK(clk), .RN(
n6963), .Q(FPADDSUB_intDY_EWSW[6]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1802), .CK(clk), .RN(n6964), .Q(FPADDSUB_Data_array_SWR[15]), .QN(n2418) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1292), .CK(clk), .RN(
n6979), .QN(n6835) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1329), .CK(clk), .RN(
n6977), .QN(n6833) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1363), .CK(clk), .RN(
n6976), .QN(n6832) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1351), .CK(clk), .RN(n6990),
.Q(FPADDSUB_ADD_OVRFLW_NRM), .QN(n6806) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n1636), .CK(clk),
.RN(n7058), .Q(n2201), .QN(n2240) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n1675), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[17]), .QN(n2405) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1317), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n6853) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[7]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]) );
ADDFHX2TS DP_OP_26J223_129_1325_U2 ( .A(n6766), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .CI(DP_OP_26J223_129_1325_n2), .CO(
DP_OP_26J223_129_1325_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1205), .CK(clk), .RN(
n6990), .Q(FPADDSUB_DmP_mant_SFG_SWR[0]), .QN(n6798) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[5]) );
DFFX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(n2210) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[5]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_Result[4]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n1642), .CK(clk),
.RN(n7052), .Q(FPMULT_Op_MY[16]), .QN(n2199) );
MDFFHQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D0(DP_OP_501J223_127_5235_n630), .D1(1'b1), .S0(
DP_OP_501J223_127_5235_n723), .CK(clk), .Q(n6746) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1321), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]), .QN(n6868) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1606), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[14]), .QN(n6884) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1514), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[9]), .QN(n6789) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1314), .CK(clk), .RN(
n6989), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[4]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[6])
);
DFFQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[7])
);
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n7066), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[0]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[6]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[8])
);
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10])
);
DFFQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1])
);
DFFQX4TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n2497), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]) );
DFFQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[2])
);
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]) );
DFFQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3])
);
DFFQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n1640), .CK(clk),
.RN(n7058), .Q(FPMULT_Op_MY[14]), .QN(n2226) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5])
);
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n1631), .CK(clk),
.RN(n7046), .Q(FPMULT_Op_MY[5]), .QN(n2198) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n1646), .CK(clk),
.RN(n7050), .QN(n2194) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1634), .CK(clk),
.RN(n7048), .Q(FPMULT_Op_MY[8]), .QN(n2236) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n1644), .CK(clk),
.RN(n7050), .Q(n6749), .QN(n2217) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n1670), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[12]), .QN(n2261) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n1672), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[14]), .QN(n2257) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n1660), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[2]), .QN(n2258) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n1673), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[15]), .QN(n2479) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n1663), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[5]), .QN(n2458) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1316), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n1664), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[6]), .QN(n2420) );
CMPR32X2TS DP_OP_26J223_129_1325_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n6766), .C(DP_OP_26J223_129_1325_n18), .CO(DP_OP_26J223_129_1325_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J223_129_1325_U8 ( .A(DP_OP_26J223_129_1325_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J223_129_1325_n8), .CO(
DP_OP_26J223_129_1325_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J223_129_1325_U7 ( .A(DP_OP_26J223_129_1325_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J223_129_1325_n7), .CO(
DP_OP_26J223_129_1325_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J223_129_1325_U6 ( .A(DP_OP_26J223_129_1325_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J223_129_1325_n6), .CO(
DP_OP_26J223_129_1325_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1819), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDY_EWSW[24]) );
CMPR32X2TS DP_OP_234J223_132_4955_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(
FPMULT_FSM_exp_operation_A_S), .C(DP_OP_234J223_132_4955_n22), .CO(
DP_OP_234J223_132_4955_n9), .S(FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_26J223_129_1325_U5 ( .A(DP_OP_26J223_129_1325_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J223_129_1325_n5), .CO(
DP_OP_26J223_129_1325_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_234J223_132_4955_U9 ( .A(DP_OP_234J223_132_4955_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J223_132_4955_n9), .CO(
DP_OP_234J223_132_4955_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_26J223_129_1325_U4 ( .A(n6766), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J223_129_1325_n4), .CO(
DP_OP_26J223_129_1325_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR42X1TS DP_OP_502J223_128_4510_U115 ( .A(DP_OP_502J223_128_4510_n170),
.B(DP_OP_502J223_128_4510_n118), .C(DP_OP_502J223_128_4510_n112), .D(
DP_OP_502J223_128_4510_n119), .ICI(DP_OP_502J223_128_4510_n115), .S(
DP_OP_502J223_128_4510_n110), .ICO(DP_OP_502J223_128_4510_n108), .CO(
DP_OP_502J223_128_4510_n109) );
CMPR32X2TS DP_OP_234J223_132_4955_U8 ( .A(DP_OP_234J223_132_4955_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J223_132_4955_n8), .CO(
DP_OP_234J223_132_4955_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_26J223_129_1325_U3 ( .A(n6766), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J223_129_1325_n3), .CO(
DP_OP_26J223_129_1325_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_234J223_132_4955_U7 ( .A(DP_OP_234J223_132_4955_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J223_132_4955_n7), .CO(
DP_OP_234J223_132_4955_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS intadd_518_U4 ( .A(FPSENCOS_d_ff2_X[24]), .B(n6768), .C(
intadd_518_CI), .CO(intadd_518_n3), .S(intadd_518_SUM_0_) );
CMPR32X2TS intadd_517_U4 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n6768), .C(
intadd_517_CI), .CO(intadd_517_n3), .S(intadd_517_SUM_0_) );
CMPR42X1TS DP_OP_501J223_127_5235_U433 ( .A(DP_OP_501J223_127_5235_n521),
.B(DP_OP_501J223_127_5235_n491), .C(DP_OP_501J223_127_5235_n497), .D(
DP_OP_501J223_127_5235_n515), .ICI(DP_OP_501J223_127_5235_n471), .S(
DP_OP_501J223_127_5235_n467), .ICO(DP_OP_501J223_127_5235_n465), .CO(
DP_OP_501J223_127_5235_n466) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2144), .CK(clk), .RN(
n6990), .Q(FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n2501) );
CMPR42X1TS DP_OP_501J223_127_5235_U434 ( .A(DP_OP_501J223_127_5235_n510),
.B(DP_OP_501J223_127_5235_n474), .C(DP_OP_501J223_127_5235_n478), .D(
DP_OP_501J223_127_5235_n475), .ICI(DP_OP_501J223_127_5235_n472), .S(
DP_OP_501J223_127_5235_n470), .ICO(DP_OP_501J223_127_5235_n468), .CO(
DP_OP_501J223_127_5235_n469) );
CMPR32X2TS intadd_517_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(intadd_517_B_1_),
.C(intadd_517_n3), .CO(intadd_517_n2), .S(intadd_517_SUM_1_) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1799), .CK(clk), .RN(n6964), .Q(FPADDSUB_Data_array_SWR[12]) );
CMPR32X2TS intadd_517_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n6782), .C(
intadd_517_n2), .CO(intadd_517_n1), .S(intadd_517_SUM_2_) );
CMPR32X2TS DP_OP_234J223_132_4955_U5 ( .A(DP_OP_234J223_132_4955_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J223_132_4955_n5), .CO(
DP_OP_234J223_132_4955_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS intadd_516_U4 ( .A(n6944), .B(FPADDSUB_DMP_EXP_EWSW[24]), .C(
intadd_516_CI), .CO(intadd_516_n3), .S(intadd_516_SUM_0_) );
CMPR32X2TS intadd_515_U3 ( .A(mult_x_309_n17), .B(mult_x_309_n15), .C(
intadd_515_n3), .CO(intadd_515_n2), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_516_U3 ( .A(n6945), .B(FPADDSUB_DMP_EXP_EWSW[25]), .C(
intadd_516_n3), .CO(intadd_516_n2), .S(intadd_516_SUM_1_) );
CMPR32X2TS intadd_516_U2 ( .A(n6946), .B(FPADDSUB_DMP_EXP_EWSW[26]), .C(
intadd_516_n2), .CO(intadd_516_n1), .S(intadd_516_SUM_2_) );
CMPR32X2TS DP_OP_234J223_132_4955_U2 ( .A(n2382), .B(FPMULT_S_Oper_A_exp[8]),
.C(DP_OP_234J223_132_4955_n2), .CO(DP_OP_234J223_132_4955_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
CLKMX2X2TS U2217 ( .A(FPMULT_P_Sgf[29]), .B(n3287), .S0(n6260), .Y(n1558) );
XOR2X1TS U2218 ( .A(n4186), .B(n4185), .Y(FPMULT_Sgf_operation_Result[36])
);
XNOR2X1TS U2219 ( .A(n5564), .B(n5563), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11) );
XOR2X2TS U2220 ( .A(n3278), .B(n3344), .Y(FPMULT_Sgf_operation_Result[42])
);
CLKBUFX2TS U2221 ( .A(n6290), .Y(n2284) );
NAND2X1TS U2222 ( .A(n3570), .B(n2429), .Y(n3561) );
AOI21X2TS U2223 ( .A0(n4181), .A1(n3419), .B0(n3357), .Y(n3421) );
OAI21X1TS U2224 ( .A0(n3597), .A1(n3594), .B0(n3595), .Y(n3593) );
OAI32X1TS U2225 ( .A0(n6714), .A1(FPADDSUB_intDX_EWSW[31]), .A2(n6717), .B0(
FPADDSUB_Shift_reg_FLAGS_7_6), .B1(FPADDSUB_OP_FLAG_EXP), .Y(n6715) );
AOI21X1TS U2226 ( .A0(n4181), .A1(n3254), .B0(n3253), .Y(n3278) );
AOI222X1TS U2227 ( .A0(n2302), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[28]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[28]), .Y(n4735) );
AOI222X1TS U2228 ( .A0(n2302), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[22]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[22]), .Y(n4725) );
AOI222X1TS U2229 ( .A0(n2302), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[11]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[11]), .Y(n4715) );
AOI222X1TS U2230 ( .A0(n4748), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[9]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[9]), .Y(n4749)
);
AOI222X1TS U2231 ( .A0(n4748), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[30]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[30]), .Y(n4722) );
AOI222X1TS U2232 ( .A0(n4748), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[18]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[18]), .Y(n4719) );
AOI222X1TS U2233 ( .A0(n4748), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[12]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[12]), .Y(n4712) );
AOI222X1TS U2234 ( .A0(n4748), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[13]), .C0(n4721), .C1(FPSENCOS_d_ff1_Z[13]), .Y(n4716) );
AOI222X1TS U2235 ( .A0(n6562), .A1(cordic_result[0]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[0]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[0]), .Y(n5121)
);
AOI222X1TS U2236 ( .A0(n6469), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[29]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[29]), .Y(n4729) );
AOI222X1TS U2237 ( .A0(n6430), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[27]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[27]), .Y(n4727) );
AOI222X1TS U2238 ( .A0(n6430), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[26]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[26]), .Y(n4738) );
AOI222X1TS U2239 ( .A0(n6453), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[25]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[25]), .Y(n4728) );
AOI222X1TS U2240 ( .A0(n6469), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[24]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[24]), .Y(n4734) );
AOI222X1TS U2241 ( .A0(n6453), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[23]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[23]), .Y(n4733) );
AOI222X1TS U2242 ( .A0(n6430), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[21]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[21]), .Y(n4726) );
AOI222X1TS U2243 ( .A0(n6453), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[20]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[20]), .Y(n4732) );
AOI222X1TS U2244 ( .A0(n6430), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[4]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[4]), .Y(n4746)
);
AOI222X1TS U2245 ( .A0(n6453), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[6]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[6]), .Y(n4744)
);
AOI222X1TS U2246 ( .A0(n6453), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[8]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[8]), .Y(n4741)
);
AOI222X1TS U2247 ( .A0(n6430), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[3]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[3]), .Y(n4739)
);
AOI222X1TS U2248 ( .A0(n6469), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[2]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[2]), .Y(n4742)
);
AOI222X1TS U2249 ( .A0(n4731), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[7]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[7]), .Y(n4745)
);
AOI222X1TS U2250 ( .A0(n6469), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[1]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[1]), .Y(n4740)
);
AOI222X1TS U2251 ( .A0(n4731), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[5]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[5]), .Y(n4743)
);
AOI222X1TS U2252 ( .A0(n6430), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[15]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[15]), .Y(n4713) );
AOI222X1TS U2253 ( .A0(n4731), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[14]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[14]), .Y(n4717) );
AOI222X1TS U2254 ( .A0(n6469), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[10]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[10]), .Y(n4724) );
AOI222X1TS U2255 ( .A0(n6469), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[19]), .C0(n4721), .C1(FPSENCOS_d_ff1_Z[19]), .Y(n4718) );
AOI222X1TS U2256 ( .A0(n6431), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[17]), .C0(n4721), .C1(FPSENCOS_d_ff1_Z[17]), .Y(n4714) );
AOI222X1TS U2257 ( .A0(n6431), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[16]), .C0(n4721), .C1(FPSENCOS_d_ff1_Z[16]), .Y(n4720) );
AOI21X1TS U2258 ( .A0(n2375), .A1(n3415), .B0(n3414), .Y(n3416) );
XNOR2X1TS U2259 ( .A(n4457), .B(n4332), .Y(n4333) );
AOI222X1TS U2260 ( .A0(n6453), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n4933), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n6427), .Y(n4934)
);
AOI222X1TS U2261 ( .A0(n5141), .A1(cordic_result[8]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[8]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[8]), .Y(n5123)
);
AOI222X1TS U2262 ( .A0(n5141), .A1(cordic_result[3]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[3]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[3]), .Y(n5124)
);
AOI222X1TS U2263 ( .A0(n5141), .A1(cordic_result[2]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[2]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[2]), .Y(n5129)
);
AOI222X1TS U2264 ( .A0(n5141), .A1(cordic_result[7]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[7]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[7]), .Y(n5128)
);
AOI222X1TS U2265 ( .A0(n5141), .A1(cordic_result[9]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[9]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[9]), .Y(n5142)
);
AOI222X1TS U2266 ( .A0(n5141), .A1(cordic_result[5]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[5]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[5]), .Y(n5125)
);
AOI222X1TS U2267 ( .A0(n5141), .A1(cordic_result[11]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[11]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[11]), .Y(n5127) );
AOI222X1TS U2268 ( .A0(n5141), .A1(cordic_result[10]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[10]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[10]), .Y(n5119) );
XNOR2X2TS U2269 ( .A(n4328), .B(n4327), .Y(n4329) );
AOI22X1TS U2270 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[10]), .B0(n2338),
.B1(n5358), .Y(n5360) );
BUFX3TS U2271 ( .A(n6518), .Y(n6494) );
INVX3TS U2272 ( .A(n2347), .Y(n2206) );
BUFX3TS U2273 ( .A(n6444), .Y(n6449) );
NAND2X1TS U2274 ( .A(n3770), .B(n3775), .Y(n3755) );
INVX2TS U2275 ( .A(n3423), .Y(n3424) );
CLKBUFX2TS U2276 ( .A(n6608), .Y(n6613) );
BUFX3TS U2277 ( .A(n6444), .Y(n6448) );
AOI21X2TS U2278 ( .A0(n4457), .A1(n4450), .B0(n4452), .Y(n4448) );
CLKBUFX2TS U2279 ( .A(n6414), .Y(n6445) );
AOI21X1TS U2280 ( .A0(n3571), .A1(n3549), .B0(n3548), .Y(n3550) );
BUFX3TS U2281 ( .A(n4997), .Y(n6549) );
CLKBUFX2TS U2282 ( .A(n4996), .Y(n5053) );
INVX2TS U2283 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n6656) );
NOR2X1TS U2284 ( .A(n3556), .B(n3565), .Y(n3549) );
INVX2TS U2285 ( .A(n3556), .Y(n3575) );
BUFX3TS U2286 ( .A(n4721), .Y(n4931) );
INVX2TS U2287 ( .A(n5232), .Y(n2347) );
INVX1TS U2288 ( .A(n3574), .Y(n3562) );
INVX2TS U2289 ( .A(n5232), .Y(n5399) );
OAI21X2TS U2290 ( .A0(n3778), .A1(n3784), .B0(n3779), .Y(n3771) );
NAND2X2TS U2291 ( .A(n4174), .B(n4176), .Y(n3422) );
NAND2X2TS U2292 ( .A(n4174), .B(n3356), .Y(n3417) );
BUFX3TS U2293 ( .A(n4674), .Y(n4697) );
NAND2X1TS U2294 ( .A(DP_OP_501J223_127_5235_n449), .B(
DP_OP_501J223_127_5235_n451), .Y(n3779) );
NAND2X1TS U2295 ( .A(DP_OP_501J223_127_5235_n470), .B(
DP_OP_501J223_127_5235_n476), .Y(n3800) );
NAND2X1TS U2296 ( .A(DP_OP_501J223_127_5235_n448), .B(n3752), .Y(n3774) );
NAND2X1TS U2297 ( .A(DP_OP_501J223_127_5235_n121), .B(n3547), .Y(n3566) );
NAND2X1TS U2298 ( .A(DP_OP_502J223_128_4510_n117), .B(
DP_OP_502J223_128_4510_n122), .Y(n5508) );
NOR2X1TS U2299 ( .A(DP_OP_502J223_128_4510_n123), .B(
DP_OP_502J223_128_4510_n128), .Y(n5512) );
NOR2X1TS U2300 ( .A(DP_OP_500J223_126_4510_n123), .B(
DP_OP_500J223_126_4510_n128), .Y(n5585) );
NOR2X1TS U2301 ( .A(DP_OP_501J223_127_5235_n448), .B(n3752), .Y(n3763) );
INVX6TS U2302 ( .A(n3406), .Y(n4176) );
NOR2X6TS U2303 ( .A(DP_OP_501J223_127_5235_n136), .B(
DP_OP_501J223_127_5235_n143), .Y(n3589) );
CMPR32X2TS U2304 ( .A(n3973), .B(n3972), .C(n3971), .CO(n3975), .S(n3969) );
NOR2X2TS U2305 ( .A(DP_OP_501J223_127_5235_n130), .B(
DP_OP_501J223_127_5235_n135), .Y(n3583) );
NAND2X2TS U2306 ( .A(DP_OP_501J223_127_5235_n452), .B(
DP_OP_501J223_127_5235_n456), .Y(n3784) );
NOR2X6TS U2307 ( .A(DP_OP_501J223_127_5235_n144), .B(
DP_OP_501J223_127_5235_n153), .Y(n3594) );
NAND2X2TS U2308 ( .A(DP_OP_501J223_127_5235_n124), .B(
DP_OP_501J223_127_5235_n122), .Y(n3574) );
NOR2X2TS U2309 ( .A(DP_OP_502J223_128_4510_n110), .B(
DP_OP_502J223_128_4510_n116), .Y(n5502) );
NAND2X2TS U2310 ( .A(DP_OP_501J223_127_5235_n464), .B(
DP_OP_501J223_127_5235_n469), .Y(n3795) );
NOR2X1TS U2311 ( .A(n5236), .B(n6521), .Y(n5315) );
NOR2X1TS U2312 ( .A(n2371), .B(n3840), .Y(n3758) );
NOR2X6TS U2313 ( .A(n4179), .B(n4182), .Y(n4174) );
CLKBUFX2TS U2314 ( .A(n5427), .Y(n6708) );
OR2X2TS U2315 ( .A(n6339), .B(n6343), .Y(n6382) );
NAND2BX2TS U2316 ( .AN(n3302), .B(n3301), .Y(n5143) );
NOR2X4TS U2317 ( .A(operation[1]), .B(n5103), .Y(n4996) );
OR2X2TS U2318 ( .A(n6350), .B(operation[1]), .Y(n4581) );
BUFX3TS U2319 ( .A(n4558), .Y(n4723) );
NOR2X2TS U2320 ( .A(n6557), .B(n6562), .Y(n4985) );
CMPR32X2TS U2321 ( .A(n3757), .B(n3756), .C(DP_OP_501J223_127_5235_n447),
.CO(n3759), .S(n3752) );
CMPR32X2TS U2322 ( .A(n3553), .B(n3552), .C(DP_OP_501J223_127_5235_n120),
.CO(n3554), .S(n3547) );
CMPR32X2TS U2323 ( .A(n3962), .B(n3961), .C(n3960), .CO(n3970), .S(n3957) );
NOR2X1TS U2324 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n4485) );
NAND2X1TS U2325 ( .A(n6787), .B(FPMULT_FS_Module_state_reg[0]), .Y(n5454) );
INVX2TS U2326 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n2316) );
NOR2X1TS U2327 ( .A(n4175), .B(n3354), .Y(n3355) );
NOR2X1TS U2328 ( .A(n4175), .B(n3250), .Y(n3251) );
BUFX3TS U2329 ( .A(n5427), .Y(n6668) );
BUFX3TS U2330 ( .A(n6439), .Y(n6415) );
NOR2X2TS U2331 ( .A(n3406), .B(n3354), .Y(n3356) );
BUFX3TS U2332 ( .A(n5015), .Y(n5103) );
OAI21X2TS U2333 ( .A0(n2576), .A1(n2575), .B0(n2574), .Y(n6706) );
BUFX3TS U2334 ( .A(n4984), .Y(n6562) );
CLKBUFX2TS U2335 ( .A(n6607), .Y(n6615) );
NOR2X2TS U2336 ( .A(DP_OP_501J223_127_5235_n173), .B(
DP_OP_501J223_127_5235_n180), .Y(n3607) );
AND2X2TS U2337 ( .A(n6023), .B(FPMULT_FS_Module_state_reg[3]), .Y(n6607) );
NAND2X2TS U2338 ( .A(n3904), .B(n3903), .Y(n4011) );
BUFX3TS U2339 ( .A(n5422), .Y(n5427) );
BUFX3TS U2340 ( .A(n6438), .Y(n6450) );
NAND2X2TS U2341 ( .A(DP_OP_501J223_127_5235_n163), .B(
DP_OP_501J223_127_5235_n172), .Y(n3604) );
NAND2X2TS U2342 ( .A(n3062), .B(n3061), .Y(n4325) );
NOR2X4TS U2343 ( .A(n6337), .B(n6358), .Y(n4984) );
OA21X2TS U2344 ( .A0(n5452), .A1(n3280), .B0(n3279), .Y(n5478) );
CMPR32X2TS U2345 ( .A(n3824), .B(n3823), .C(n3822), .CO(
DP_OP_501J223_127_5235_n453), .S(DP_OP_501J223_127_5235_n454) );
CMPR32X2TS U2346 ( .A(n3918), .B(n3917), .C(n3916), .CO(n3939), .S(n3906) );
CMPR32X2TS U2347 ( .A(n3950), .B(n3949), .C(n3948), .CO(n3958), .S(n3943) );
AND4X1TS U2348 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n3292), .Y(n3293) );
CMPR32X2TS U2349 ( .A(n3886), .B(n3885), .C(n3884), .CO(n3903), .S(n4016) );
INVX2TS U2350 ( .A(n6372), .Y(intadd_517_B_1_) );
INVX2TS U2351 ( .A(FPADDSUB_Shift_reg_FLAGS_7_6), .Y(n5422) );
INVX2TS U2352 ( .A(FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n6354) );
OR2X2TS U2353 ( .A(DP_OP_501J223_127_5235_n181), .B(
DP_OP_501J223_127_5235_n187), .Y(n2499) );
CMPR32X2TS U2354 ( .A(n3833), .B(n3832), .C(n3831), .CO(
DP_OP_501J223_127_5235_n471), .S(DP_OP_501J223_127_5235_n472) );
INVX2TS U2355 ( .A(n4588), .Y(n4595) );
CLKBUFX2TS U2356 ( .A(n4554), .Y(n6438) );
INVX3TS U2357 ( .A(n3283), .Y(n3059) );
OAI22X1TS U2358 ( .A0(n3968), .A1(n3953), .B0(n3966), .B1(n2394), .Y(n3973)
);
ADDFHX1TS U2359 ( .A(n3667), .B(n3666), .CI(DP_OP_501J223_127_5235_n158),
.CO(DP_OP_501J223_127_5235_n148), .S(DP_OP_501J223_127_5235_n149) );
CMPR32X2TS U2360 ( .A(n3930), .B(n3929), .C(n3928), .CO(n3944), .S(n3942) );
CMPR32X2TS U2361 ( .A(n3876), .B(n3875), .C(n3874), .CO(n3905), .S(n3904) );
ADDHXLTS U2362 ( .A(n3837), .B(n3836), .CO(DP_OP_501J223_127_5235_n478), .S(
DP_OP_501J223_127_5235_n479) );
CMPR32X2TS U2363 ( .A(n4254), .B(n4253), .C(n4252), .CO(
DP_OP_502J223_128_4510_n130), .S(DP_OP_502J223_128_4510_n131) );
CMPR32X2TS U2364 ( .A(n4358), .B(n4359), .C(n4357), .CO(
DP_OP_500J223_126_4510_n130), .S(DP_OP_500J223_126_4510_n131) );
CMPR32X2TS U2365 ( .A(n3873), .B(n3872), .C(n3871), .CO(n3917), .S(n3874) );
NOR2X1TS U2366 ( .A(n2412), .B(FPADDSUB_intDX_EWSW[30]), .Y(n2570) );
CMPR32X2TS U2367 ( .A(n3733), .B(n3732), .C(n3731), .CO(n3741), .S(n3739) );
NOR2X1TS U2368 ( .A(n2334), .B(n3692), .Y(n3652) );
CMPR32X2TS U2369 ( .A(n3892), .B(n3891), .C(n3890), .CO(n3885), .S(n4019) );
NAND2X1TS U2370 ( .A(n2758), .B(n2761), .Y(n2759) );
NAND2X1TS U2371 ( .A(n2772), .B(n2790), .Y(n2773) );
NAND2X1TS U2372 ( .A(n3111), .B(n3131), .Y(n3112) );
NAND2X1TS U2373 ( .A(n4891), .B(n4890), .Y(n4898) );
INVX2TS U2374 ( .A(n6373), .Y(n6371) );
NOR2X2TS U2375 ( .A(DP_OP_501J223_127_5235_n188), .B(n3499), .Y(n3615) );
INVX2TS U2376 ( .A(n2340), .Y(n2341) );
INVX2TS U2377 ( .A(n4425), .Y(n4554) );
INVX2TS U2378 ( .A(n5273), .Y(n5238) );
OAI22X1TS U2379 ( .A0(n2334), .A1(n3698), .B0(n2335), .B1(n3697), .Y(n3666)
);
OAI22X1TS U2380 ( .A0(n3707), .A1(n3700), .B0(n2335), .B1(n3699), .Y(
DP_OP_501J223_127_5235_n235) );
INVX2TS U2381 ( .A(n6733), .Y(n6623) );
CMPR32X2TS U2382 ( .A(n3899), .B(n3924), .C(n3923), .CO(n3928), .S(n3925) );
CMPR32X2TS U2383 ( .A(n4571), .B(n4570), .C(n4569), .CO(
DP_OP_502J223_128_4510_n111), .S(DP_OP_502J223_128_4510_n112) );
CMPR32X2TS U2384 ( .A(n4313), .B(n4312), .C(n4311), .CO(
DP_OP_500J223_126_4510_n111), .S(DP_OP_500J223_126_4510_n112) );
BUFX3TS U2385 ( .A(FPSENCOS_cont_iter_out[2]), .Y(n6372) );
INVX2TS U2386 ( .A(n7059), .Y(n2340) );
NAND2X1TS U2387 ( .A(n3139), .B(n3138), .Y(n3140) );
INVX2TS U2388 ( .A(n7077), .Y(n6733) );
CLKBUFX2TS U2389 ( .A(n4203), .Y(n3353) );
NAND2X1TS U2390 ( .A(n4786), .B(n4785), .Y(n5815) );
NAND2X1TS U2391 ( .A(n6346), .B(n6347), .Y(n6336) );
NAND4BXLTS U2392 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(n4671), .D(n6786), .Y(
n4425) );
NOR2X1TS U2393 ( .A(n6306), .B(n6304), .Y(n2984) );
OAI22X1TS U2394 ( .A0(n3968), .A1(n3877), .B0(n3866), .B1(n3967), .Y(n3871)
);
NAND2X1TS U2395 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B(n6351),
.Y(n6012) );
OAI22X1TS U2396 ( .A0(n3706), .A1(n3700), .B0(n3707), .B1(n3699), .Y(
DP_OP_501J223_127_5235_n234) );
OAI22X1TS U2397 ( .A0(n3968), .A1(n3913), .B0(n3919), .B1(n2394), .Y(n3924)
);
NAND2X1TS U2398 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(n6772),
.Y(n6351) );
NAND2X1TS U2399 ( .A(n3858), .B(n3857), .Y(n3859) );
NAND2X1TS U2400 ( .A(n3026), .B(n3025), .Y(n3027) );
NAND2X1TS U2401 ( .A(n3043), .B(n2498), .Y(n3044) );
INVX4TS U2402 ( .A(n3641), .Y(n2387) );
OAI22X1TS U2403 ( .A0(n3703), .A1(n3698), .B0(n2332), .B1(n3697), .Y(
DP_OP_501J223_127_5235_n229) );
XNOR2X1TS U2404 ( .A(n2395), .B(n3896), .Y(n3877) );
BUFX3TS U2405 ( .A(n3967), .Y(n2394) );
NOR2X2TS U2406 ( .A(n3130), .B(n3132), .Y(n3135) );
NOR2X1TS U2407 ( .A(n2385), .B(n3692), .Y(n3669) );
XNOR2X1TS U2408 ( .A(n2395), .B(n3937), .Y(n3919) );
CLKBUFX2TS U2409 ( .A(n5546), .Y(n2381) );
XNOR2X1TS U2410 ( .A(n2395), .B(n3921), .Y(n3913) );
XNOR2X1TS U2411 ( .A(n3921), .B(n2205), .Y(n3887) );
NOR2X1TS U2412 ( .A(n6790), .B(FPMULT_FS_Module_state_reg[2]), .Y(n4574) );
CLKBUFX2TS U2413 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n5340) );
CLKBUFX2TS U2414 ( .A(n4195), .Y(n3005) );
INVX4TS U2415 ( .A(n3460), .Y(n2386) );
INVX2TS U2416 ( .A(n2250), .Y(n2320) );
INVX12TS U2417 ( .A(n3707), .Y(n2333) );
NAND2X1TS U2418 ( .A(n5225), .B(n7063), .Y(n4810) );
NOR2X1TS U2419 ( .A(n2303), .B(n5544), .Y(n4559) );
NOR2X1TS U2420 ( .A(n3748), .B(FPMULT_Op_MY[11]), .Y(n3745) );
NAND2X2TS U2421 ( .A(n3102), .B(n3107), .Y(n3130) );
OAI22X1TS U2422 ( .A0(n2385), .A1(n3700), .B0(n2332), .B1(n3699), .Y(n3681)
);
XNOR2X1TS U2423 ( .A(n3963), .B(n2308), .Y(n3920) );
NAND2X1TS U2424 ( .A(n4226), .B(n2942), .Y(n6254) );
INVX6TS U2425 ( .A(n3465), .Y(n2385) );
ADDHXLTS U2426 ( .A(n6570), .B(n6572), .CO(n4251), .S(n4244) );
INVX4TS U2427 ( .A(n3363), .Y(n2314) );
INVX4TS U2428 ( .A(n3647), .Y(n3695) );
NAND2X2TS U2429 ( .A(n2205), .B(DP_OP_501J223_127_5235_n723), .Y(n3901) );
INVX4TS U2430 ( .A(n3867), .Y(n3692) );
NOR2X2TS U2431 ( .A(n3679), .B(n3696), .Y(n3684) );
XNOR2X1TS U2432 ( .A(n3896), .B(n2205), .Y(n3898) );
CLKXOR2X2TS U2433 ( .A(n4307), .B(n4287), .Y(n4288) );
XNOR2X1TS U2434 ( .A(n2196), .B(n3716), .Y(n3717) );
CLKXOR2X2TS U2435 ( .A(n3816), .B(n3726), .Y(n3727) );
NAND2X1TS U2436 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MY[5]), .Y(n4793) );
NAND2X1TS U2437 ( .A(n6564), .B(n6757), .Y(n3279) );
INVX2TS U2438 ( .A(n2812), .Y(n2997) );
NAND2X1TS U2439 ( .A(n2222), .B(n3514), .Y(n3458) );
INVX4TS U2440 ( .A(n3465), .Y(n3703) );
INVX2TS U2441 ( .A(n6747), .Y(n2913) );
INVX4TS U2442 ( .A(n3649), .Y(n3696) );
ADDHXLTS U2443 ( .A(n3728), .B(n3865), .CO(n3466), .S(n3461) );
ADDHXLTS U2444 ( .A(n5638), .B(n2345), .CO(n4442), .S(n4250) );
AOI21X2TS U2445 ( .A0(n3464), .A1(n2249), .B0(n3516), .Y(n3459) );
INVX4TS U2446 ( .A(n3678), .Y(n3699) );
AOI21X2TS U2447 ( .A0(n6075), .A1(n6071), .B0(n4265), .Y(n6095) );
OAI21X1TS U2448 ( .A0(n3817), .A1(n3814), .B0(n3818), .Y(n3748) );
XNOR2X1TS U2449 ( .A(n2940), .B(n2939), .Y(n2942) );
XNOR2X2TS U2450 ( .A(n3532), .B(n3531), .Y(n3963) );
INVX6TS U2451 ( .A(n3480), .Y(n3679) );
INVX2TS U2452 ( .A(n2253), .Y(n2331) );
NAND2X1TS U2453 ( .A(FPMULT_Op_MY[9]), .B(n6585), .Y(n3814) );
OAI21X2TS U2454 ( .A0(n3645), .A1(n3541), .B0(n3540), .Y(n3546) );
INVX4TS U2455 ( .A(n3491), .Y(n3700) );
AOI21X2TS U2456 ( .A0(n4285), .A1(n4290), .B0(n4284), .Y(n4307) );
NAND3X1TS U2457 ( .A(n4807), .B(n4689), .C(n4688), .Y(n4811) );
NAND2X1TS U2458 ( .A(n6584), .B(n6753), .Y(n3721) );
NOR2X1TS U2459 ( .A(n6584), .B(n6753), .Y(n3719) );
NAND2X1TS U2460 ( .A(n2456), .B(n3536), .Y(n3537) );
NOR2X4TS U2461 ( .A(n3521), .B(n3520), .Y(n3653) );
CLKINVX6TS U2462 ( .A(n3625), .Y(n3657) );
NOR2X2TS U2463 ( .A(n4172), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]) );
NOR2X1TS U2464 ( .A(n3541), .B(n3542), .Y(n3475) );
NAND2X2TS U2465 ( .A(n3951), .B(n3522), .Y(n3627) );
NOR2X1TS U2466 ( .A(n5221), .B(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n4809) );
OAI21X1TS U2467 ( .A0(n3540), .A1(n3542), .B0(n3543), .Y(n3474) );
ADDHX1TS U2468 ( .A(n3677), .B(n3860), .CO(n3678), .S(n3491) );
INVX2TS U2469 ( .A(n4231), .Y(DP_OP_499J223_125_1651_n268) );
INVX6TS U2470 ( .A(n3534), .Y(n3645) );
NAND2X1TS U2471 ( .A(n4299), .B(n4298), .Y(n4300) );
NOR2X6TS U2472 ( .A(n3951), .B(n3522), .Y(n3626) );
CLKXOR2X2TS U2473 ( .A(n4166), .B(n4163), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]) );
NOR2X4TS U2474 ( .A(n3340), .B(n3223), .Y(n3341) );
ADDFHX2TS U2475 ( .A(n6572), .B(n6567), .CI(n3632), .CO(n3646), .S(n3664) );
OAI21X1TS U2476 ( .A0(n5915), .A1(n6788), .B0(n5850), .Y(n5890) );
INVX6TS U2477 ( .A(n4229), .Y(DP_OP_499J223_125_1651_n297) );
INVX2TS U2478 ( .A(n4235), .Y(DP_OP_499J223_125_1651_n270) );
INVX2TS U2479 ( .A(n4227), .Y(DP_OP_499J223_125_1651_n295) );
INVX1TS U2480 ( .A(n3535), .Y(n3643) );
CMPR32X2TS U2481 ( .A(n3729), .B(FPMULT_Op_MX[20]), .C(n2287), .CO(n3533),
.S(n3492) );
NAND2X1TS U2482 ( .A(n6753), .B(FPMULT_Op_MY[13]), .Y(n4343) );
INVX2TS U2483 ( .A(n4214), .Y(DP_OP_499J223_125_1651_n271) );
NOR2X1TS U2484 ( .A(n2315), .B(FPMULT_Op_MY[13]), .Y(n4342) );
NAND2XLTS U2485 ( .A(n2244), .B(n3507), .Y(n3508) );
OR2X4TS U2486 ( .A(n3921), .B(n3457), .Y(n2222) );
OAI21X2TS U2487 ( .A0(n2968), .A1(n2965), .B0(n2966), .Y(n2882) );
OAI21X2TS U2488 ( .A0(n3527), .A1(n3506), .B0(n3510), .Y(n3509) );
XNOR2X1TS U2489 ( .A(n4144), .B(n4143), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]) );
NOR2X2TS U2490 ( .A(n3328), .B(n3329), .Y(n3332) );
NAND2X2TS U2491 ( .A(n6570), .B(n6579), .Y(n3642) );
INVX2TS U2492 ( .A(n6277), .Y(DP_OP_499J223_125_1651_n278) );
NAND2X1TS U2493 ( .A(n3896), .B(n3444), .Y(n3485) );
NAND2X1TS U2494 ( .A(n2972), .B(n2971), .Y(n2973) );
NAND2X1TS U2495 ( .A(n2914), .B(n2926), .Y(n2915) );
NAND2X1TS U2496 ( .A(n3243), .B(n3242), .Y(n3244) );
NAND2X1TS U2497 ( .A(n3208), .B(n3212), .Y(n3209) );
NAND2X1TS U2498 ( .A(n3511), .B(n3510), .Y(n3512) );
INVX2TS U2499 ( .A(n2194), .Y(n5647) );
NAND2X2TS U2500 ( .A(n3914), .B(n3450), .Y(n3462) );
AOI21X1TS U2501 ( .A0(n3240), .A1(n3232), .B0(n3231), .Y(n3236) );
NAND2X1TS U2502 ( .A(n2934), .B(n2933), .Y(n2935) );
NAND2X1TS U2503 ( .A(n4135), .B(n4134), .Y(n4156) );
CLKAND2X2TS U2504 ( .A(n2677), .B(n2836), .Y(n2678) );
NAND2X6TS U2505 ( .A(n2885), .B(n2878), .Y(n2989) );
NOR2X2TS U2506 ( .A(n3322), .B(n3315), .Y(n3316) );
NAND2X1TS U2507 ( .A(n2949), .B(n2948), .Y(n2950) );
CMPR32X2TS U2508 ( .A(n6585), .B(n5643), .C(n3456), .CO(n3513), .S(n3450) );
NAND2X1TS U2509 ( .A(n3237), .B(n3239), .Y(n3162) );
NAND2X1TS U2510 ( .A(n2251), .B(n3447), .Y(n3448) );
NAND2X1TS U2511 ( .A(n2899), .B(n2898), .Y(n2900) );
NAND2X1TS U2512 ( .A(n3127), .B(n3143), .Y(n3128) );
NAND2XLTS U2513 ( .A(n2218), .B(n3453), .Y(n3454) );
NOR2X6TS U2514 ( .A(n3274), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(n3311)
);
NAND2X1TS U2515 ( .A(n3092), .B(n3144), .Y(n3093) );
INVX4TS U2516 ( .A(n2208), .Y(n2209) );
OAI21X2TS U2517 ( .A0(n3114), .A1(n3142), .B0(n3144), .Y(n3129) );
AOI21X2TS U2518 ( .A0(n4067), .A1(n4079), .B0(n4084), .Y(n4171) );
OAI21X2TS U2519 ( .A0(n3525), .A1(n3528), .B0(n3529), .Y(n3438) );
NAND2X2TS U2520 ( .A(n2889), .B(n2888), .Y(n2890) );
NOR2X2TS U2521 ( .A(n2924), .B(n2928), .Y(n2930) );
NOR2X2TS U2522 ( .A(n3526), .B(n3528), .Y(n3439) );
NAND2X6TS U2523 ( .A(n6568), .B(FPMULT_Op_MX[12]), .Y(n3467) );
INVX4TS U2524 ( .A(n2945), .Y(n2962) );
CMPR32X2TS U2525 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]), .B(n2730), .C(n2729), .CO(n4238), .S(n2724) );
CMPR32X2TS U2526 ( .A(n3449), .B(n5644), .C(n6595), .CO(n3456), .S(n3444) );
INVX2TS U2527 ( .A(n3147), .Y(n3114) );
NOR2X2TS U2528 ( .A(DP_OP_501J223_127_5235_n903), .B(n2291), .Y(n3528) );
XNOR2X2TS U2529 ( .A(n4155), .B(n4154), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]) );
INVX6TS U2530 ( .A(n2931), .Y(n2208) );
NAND2XLTS U2531 ( .A(n3079), .B(n3076), .Y(n2811) );
NAND2X1TS U2532 ( .A(n3075), .B(n2808), .Y(n2788) );
NAND2X1TS U2533 ( .A(n4200), .B(n4199), .Y(n4201) );
NOR2X4TS U2534 ( .A(n3211), .B(n3213), .Y(n3215) );
INVX2TS U2535 ( .A(n3506), .Y(n3511) );
BUFX4TS U2536 ( .A(n6749), .Y(n2291) );
OAI21X2TS U2537 ( .A0(n4150), .A1(n4149), .B0(n4148), .Y(n4155) );
OR2X2TS U2538 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[5]), .Y(n2244) );
INVX4TS U2539 ( .A(n2194), .Y(n6595) );
AND2X2TS U2540 ( .A(n2722), .B(n2739), .Y(n3061) );
NOR2X1TS U2541 ( .A(n3258), .B(n3257), .Y(n3221) );
INVX4TS U2542 ( .A(n6771), .Y(n2315) );
NAND2X2TS U2543 ( .A(n4095), .B(n4094), .Y(n4141) );
NOR2X6TS U2544 ( .A(n3126), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .Y(n3145)
);
OR2X2TS U2545 ( .A(FPMULT_Op_MY[13]), .B(n2283), .Y(n2444) );
NAND2X2TS U2546 ( .A(n3126), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .Y(n3143)
);
NAND2X2TS U2547 ( .A(n2676), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .Y(n2836)
);
NAND2X1TS U2548 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[5]), .Y(n3507) );
NOR2X6TS U2549 ( .A(n2841), .B(n2840), .Y(n2923) );
INVX2TS U2550 ( .A(n3431), .Y(n3442) );
NAND2X2TS U2551 ( .A(n6594), .B(n6587), .Y(n3453) );
NAND2X2TS U2552 ( .A(n6593), .B(n2286), .Y(n3447) );
NOR2X1TS U2553 ( .A(n2856), .B(n2855), .Y(n2847) );
NOR2X6TS U2554 ( .A(n2838), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(n2932)
);
NOR2X6TS U2555 ( .A(n2676), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .Y(n2840)
);
OR2X4TS U2556 ( .A(n2807), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .Y(n3079) );
NAND2X2TS U2557 ( .A(n4044), .B(n4043), .Y(n4148) );
INVX4TS U2558 ( .A(n2226), .Y(n6593) );
OAI21X1TS U2559 ( .A0(n2862), .A1(n2855), .B0(n2858), .Y(n2846) );
NAND2X1TS U2560 ( .A(n3198), .B(n3195), .Y(n3186) );
NAND2X1TS U2561 ( .A(n3088), .B(n3116), .Y(n3089) );
NAND2X1TS U2562 ( .A(n3158), .B(n3165), .Y(n3159) );
AOI21X2TS U2563 ( .A0(n3153), .A1(n3152), .B0(n3151), .Y(n3160) );
NAND2X2TS U2564 ( .A(n4031), .B(n4030), .Y(n4037) );
NOR2X2TS U2565 ( .A(n2867), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]), .Y(
n2871) );
NAND2X1TS U2566 ( .A(n2826), .B(n2823), .Y(n2820) );
OR2X2TS U2567 ( .A(n4040), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]), .Y(
n4043) );
NAND2X2TS U2568 ( .A(n2698), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(n2737)
);
OR2X4TS U2569 ( .A(n2637), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .Y(
n4200) );
NOR2X2TS U2570 ( .A(n2861), .B(n2856), .Y(n2863) );
NAND2X4TS U2571 ( .A(n3203), .B(n3202), .Y(n3260) );
NAND2X1TS U2572 ( .A(n2784), .B(n2800), .Y(n2785) );
NAND2X2TS U2573 ( .A(n2622), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(n2732) );
NAND2X2TS U2574 ( .A(n2637), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .Y(
n4199) );
NAND2X2TS U2575 ( .A(n2719), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .Y(n2734) );
XOR2X2TS U2576 ( .A(n2779), .B(n2688), .Y(n2689) );
INVX6TS U2577 ( .A(n2667), .Y(n2649) );
INVX2TS U2578 ( .A(n2804), .Y(n2779) );
OAI21X2TS U2579 ( .A0(n3166), .A1(n2200), .B0(n3165), .Y(n3167) );
NAND2X2TS U2580 ( .A(n3178), .B(n3177), .Y(n3181) );
INVX2TS U2581 ( .A(n2823), .Y(n2824) );
OR2X4TS U2582 ( .A(n2819), .B(n2818), .Y(n2826) );
ADDFHX2TS U2583 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10]), .B(
n2849), .CI(n2848), .CO(n2850), .S(n2832) );
NAND2X4TS U2584 ( .A(n2593), .B(n2592), .Y(n2625) );
NAND2X2TS U2585 ( .A(n2607), .B(n2606), .Y(n2661) );
NAND2X2TS U2586 ( .A(n2598), .B(n2597), .Y(n2603) );
NAND2X2TS U2587 ( .A(n2653), .B(n2652), .Y(n2660) );
AND2X6TS U2588 ( .A(n2585), .B(n2611), .Y(n2404) );
NOR2X4TS U2589 ( .A(n2602), .B(n2604), .Y(n2666) );
NOR2X4TS U2590 ( .A(n2652), .B(n2653), .Y(n2662) );
INVX4TS U2591 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(n3329) );
OR2X4TS U2592 ( .A(n2680), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]), .Y(n2696) );
INVX2TS U2593 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(n3085) );
INVX2TS U2594 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(n2781) );
INVX2TS U2595 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .Y(n2672)
);
INVX3TS U2596 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(n2605)
);
INVX4TS U2597 ( .A(FPMULT_Sgf_operation_Result[0]), .Y(n2700) );
INVX2TS U2598 ( .A(FPMULT_Sgf_operation_Result[2]), .Y(n2579) );
INVX2TS U2599 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(n2651)
);
OR2X1TS U2600 ( .A(n4135), .B(n4134), .Y(n4158) );
INVX6TS U2601 ( .A(n2211), .Y(n2872) );
XNOR2X1TS U2602 ( .A(n4115), .B(n4114), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]) );
NOR2XLTS U2603 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n3297) );
XNOR2X1TS U2604 ( .A(n2395), .B(n3914), .Y(n3866) );
NOR2X1TS U2605 ( .A(n4855), .B(n5742), .Y(n4846) );
AOI21X1TS U2606 ( .A0(n2196), .A1(n3715), .B0(n3710), .Y(n3713) );
XNOR2X1TS U2607 ( .A(n3821), .B(n3820), .Y(n2202) );
INVX2TS U2608 ( .A(n3635), .Y(n3469) );
NAND2X2TS U2609 ( .A(n2584), .B(n2703), .Y(n2615) );
NAND2X2TS U2610 ( .A(n3091), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .Y(n3144) );
XNOR2X1TS U2611 ( .A(n2395), .B(n3963), .Y(n3953) );
XNOR2X1TS U2612 ( .A(n3963), .B(n2205), .Y(n3868) );
NAND2X1TS U2613 ( .A(FPMULT_Op_MY[13]), .B(n2220), .Y(n3441) );
NOR2X1TS U2614 ( .A(n3848), .B(n2396), .Y(n3832) );
NAND2X2TS U2615 ( .A(n2738), .B(n2737), .Y(n2740) );
INVX2TS U2616 ( .A(n2202), .Y(n2296) );
NOR2X1TS U2617 ( .A(n2486), .B(n3705), .Y(DP_OP_501J223_127_5235_n250) );
OAI21XLTS U2618 ( .A0(n4377), .A1(n6197), .B0(n4376), .Y(n4378) );
NOR2X4TS U2619 ( .A(n2196), .B(n3440), .Y(n3476) );
OAI21XLTS U2620 ( .A0(n4811), .A1(n6799), .B0(n2256), .Y(n4812) );
OAI22X1TS U2621 ( .A0(n2320), .A1(n5545), .B0(n2379), .B1(n5544), .Y(
DP_OP_502J223_128_4510_n180) );
BUFX8TS U2622 ( .A(n3931), .Y(n2395) );
CMPR42X1TS U2623 ( .A(DP_OP_500J223_126_4510_n150), .B(
DP_OP_500J223_126_4510_n157), .C(DP_OP_500J223_126_4510_n185), .D(
DP_OP_500J223_126_4510_n164), .ICI(DP_OP_500J223_126_4510_n171), .S(
DP_OP_500J223_126_4510_n120), .ICO(DP_OP_500J223_126_4510_n118), .CO(
DP_OP_500J223_126_4510_n119) );
OR3X1TS U2624 ( .A(n4941), .B(n4946), .C(n4944), .Y(n4943) );
NOR2X4TS U2625 ( .A(n3020), .B(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(
n5909) );
NAND2X2TS U2626 ( .A(FPMULT_Op_MX[15]), .B(n6569), .Y(n3635) );
CLKINVX6TS U2627 ( .A(n2324), .Y(n2325) );
OR2X1TS U2628 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n2262) );
OAI21XLTS U2629 ( .A0(n5222), .A1(n5221), .B0(n5220), .Y(n5223) );
NOR2X1TS U2630 ( .A(n4175), .B(n3334), .Y(n3335) );
INVX2TS U2631 ( .A(n3369), .Y(n2377) );
AOI21X2TS U2632 ( .A0(n6246), .A1(n2944), .B0(n2943), .Y(n6242) );
CMPR42X1TS U2633 ( .A(DP_OP_502J223_128_4510_n162), .B(
DP_OP_502J223_128_4510_n155), .C(DP_OP_502J223_128_4510_n107), .D(
DP_OP_502J223_128_4510_n111), .ICI(DP_OP_502J223_128_4510_n108), .S(
DP_OP_502J223_128_4510_n105), .ICO(DP_OP_502J223_128_4510_n103), .CO(
DP_OP_502J223_128_4510_n104) );
NOR2XLTS U2634 ( .A(n6843), .B(FPADDSUB_DMP_SFG[21]), .Y(n4411) );
OAI21X1TS U2635 ( .A0(n6095), .A1(n6089), .B0(n6090), .Y(n6066) );
INVX2TS U2636 ( .A(n2478), .Y(n2285) );
NOR2XLTS U2637 ( .A(n3566), .B(n3557), .Y(n3558) );
NOR2X2TS U2638 ( .A(DP_OP_501J223_127_5235_n121), .B(n3547), .Y(n3565) );
NOR2XLTS U2639 ( .A(n5652), .B(n5651), .Y(n4478) );
OR2X1TS U2640 ( .A(DP_OP_501J223_127_5235_n477), .B(n3741), .Y(n2494) );
OAI21X1TS U2641 ( .A0(n6118), .A1(n4403), .B0(n4402), .Y(n6138) );
NOR2X1TS U2642 ( .A(n3343), .B(n3344), .Y(n3347) );
NOR2X2TS U2643 ( .A(n3413), .B(DP_OP_499J223_125_1651_n297), .Y(n3403) );
AOI21X1TS U2644 ( .A0(n3771), .A1(n3775), .B0(n3753), .Y(n3754) );
NOR2X1TS U2645 ( .A(n3737), .B(n3736), .Y(n3809) );
OR2X1TS U2646 ( .A(n3497), .B(n3496), .Y(n2495) );
OR2X1TS U2647 ( .A(n5182), .B(n5181), .Y(n5605) );
BUFX3TS U2648 ( .A(n4985), .Y(n5118) );
OAI21XLTS U2649 ( .A0(n5816), .A1(n5817), .B0(n4764), .Y(intadd_514_A_2_) );
AOI21X1TS U2650 ( .A0(n3571), .A1(n3575), .B0(n3562), .Y(n3563) );
OAI21XLTS U2651 ( .A0(n5664), .A1(n5663), .B0(n5665), .Y(n4965) );
BUFX3TS U2652 ( .A(n4697), .Y(n4708) );
AND2X2TS U2653 ( .A(n6342), .B(n6350), .Y(n4994) );
OAI21X1TS U2654 ( .A0(n5594), .A1(n5597), .B0(n5595), .Y(n5592) );
AOI31X1TS U2655 ( .A0(n6364), .A1(n6768), .A2(intadd_517_B_1_), .B0(n6413),
.Y(n4558) );
AOI21X2TS U2656 ( .A0(n3986), .A1(n2475), .B0(n3959), .Y(n3983) );
CLKINVX3TS U2657 ( .A(n2577), .Y(n5291) );
NAND2X1TS U2658 ( .A(n4028), .B(n4027), .Y(n4029) );
OAI21X1TS U2659 ( .A0(n5573), .A1(n5565), .B0(n5570), .Y(n5569) );
CLKINVX3TS U2660 ( .A(n2238), .Y(n2383) );
CLKBUFX2TS U2661 ( .A(n4483), .Y(n2364) );
CLKINVX3TS U2662 ( .A(n5478), .Y(n6260) );
BUFX3TS U2663 ( .A(n5937), .Y(n6624) );
CLKINVX3TS U2664 ( .A(n6550), .Y(n5052) );
OAI21XLTS U2665 ( .A0(n5762), .A1(n4930), .B0(n4929), .Y(mult_x_311_n14) );
NOR2XLTS U2666 ( .A(n6664), .B(n6648), .Y(n6649) );
INVX2TS U2667 ( .A(n6615), .Y(n6617) );
BUFX3TS U2668 ( .A(n4723), .Y(n6414) );
CLKBUFX2TS U2669 ( .A(n6382), .Y(n6380) );
OAI21XLTS U2670 ( .A0(n6433), .A1(n6838), .B0(n6436), .Y(n6434) );
BUFX3TS U2671 ( .A(n4554), .Y(n6444) );
INVX1TS U2672 ( .A(result_add_subt[23]), .Y(n6524) );
INVX1TS U2673 ( .A(result_add_subt[25]), .Y(n6527) );
OAI211XLTS U2674 ( .A0(n2363), .A1(n6887), .B0(n4634), .C0(n4633), .Y(n1515)
);
XOR2X2TS U2675 ( .A(n3342), .B(n2265), .Y(FPMULT_Sgf_operation_Result[47])
);
XOR2X1TS U2676 ( .A(n3430), .B(n2264), .Y(FPMULT_Sgf_operation_Result[46])
);
OAI211XLTS U2677 ( .A0(n5087), .A1(n6426), .B0(n5071), .C0(n5070), .Y(n1920)
);
OAI211XLTS U2678 ( .A0(n5116), .A1(n6401), .B0(n5081), .C0(n5080), .Y(n1938)
);
OAI21XLTS U2679 ( .A0(n5876), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
n4575), .Y(n1620) );
CLKINVX3TS U2680 ( .A(n5478), .Y(n6956) );
OAI211XLTS U2681 ( .A0(n5110), .A1(n2449), .B0(n5089), .C0(n5088), .Y(n1931)
);
OAI21XLTS U2682 ( .A0(n6371), .A1(n6362), .B0(n4686), .Y(n2131) );
OAI211XLTS U2683 ( .A0(n5087), .A1(n6838), .B0(n5049), .C0(n5048), .Y(n1913)
);
OAI211XLTS U2684 ( .A0(n5067), .A1(n6441), .B0(n5066), .C0(n5065), .Y(n1910)
);
OAI21XLTS U2685 ( .A0(n5393), .A1(n5389), .B0(n5233), .Y(n1811) );
OAI211XLTS U2686 ( .A0(n2361), .A1(n6878), .B0(n4608), .C0(n4607), .Y(n1524)
);
OAI211XLTS U2687 ( .A0(n5110), .A1(n6421), .B0(n5061), .C0(n5060), .Y(n1923)
);
OAI211XLTS U2688 ( .A0(n2362), .A1(n6891), .B0(n4631), .C0(n4630), .Y(n1511)
);
OAI211XLTS U2689 ( .A0(n5067), .A1(n2419), .B0(n5029), .C0(n5028), .Y(n1835)
);
OAI211XLTS U2690 ( .A0(n5393), .A1(n5381), .B0(n5336), .C0(n5335), .Y(n1808)
);
NOR2X2TS U2691 ( .A(n2491), .B(n2217), .Y(n7067) );
OAI21XLTS U2692 ( .A0(n2277), .A1(n5436), .B0(n5421), .Y(n1221) );
OAI21XLTS U2693 ( .A0(n2525), .A1(n5436), .B0(n5431), .Y(n1241) );
OAI21XLTS U2694 ( .A0(n2230), .A1(n5433), .B0(n5413), .Y(n1257) );
OAI21XLTS U2695 ( .A0(n6692), .A1(n5433), .B0(n2578), .Y(n1275) );
OAI21XLTS U2696 ( .A0(n2275), .A1(n5433), .B0(n5408), .Y(n1296) );
OAI21XLTS U2697 ( .A0(n2273), .A1(n5312), .B0(n5307), .Y(n1312) );
OAI21XLTS U2698 ( .A0(n7060), .A1(n6554), .B0(n5145), .Y(n1356) );
OAI21XLTS U2699 ( .A0(n2270), .A1(n5312), .B0(n5296), .Y(n1374) );
OAI21XLTS U2700 ( .A0(n2432), .A1(n5310), .B0(n5297), .Y(n1389) );
OAI21XLTS U2701 ( .A0(n2279), .A1(n5310), .B0(n5287), .Y(n1404) );
OAI21XLTS U2702 ( .A0(n4710), .A1(n6832), .B0(n4698), .Y(op_result[12]) );
OAI21XLTS U2703 ( .A0(n4670), .A1(n6644), .B0(n4702), .Y(op_result[19]) );
AO21X4TS U2704 ( .A0(n3505), .A1(n3439), .B0(n3438), .Y(n2196) );
OR2X4TS U2705 ( .A(n2844), .B(n2843), .Y(n2197) );
INVX2TS U2706 ( .A(n4748), .Y(n2301) );
INVX2TS U2707 ( .A(n6005), .Y(n2356) );
NAND2X2TS U2708 ( .A(n3122), .B(n3121), .Y(n2200) );
CLKINVX3TS U2709 ( .A(n2468), .Y(n6455) );
INVX2TS U2710 ( .A(n2224), .Y(n2322) );
INVX2TS U2711 ( .A(n2243), .Y(n2308) );
OR2X1TS U2712 ( .A(n2977), .B(n4235), .Y(n2203) );
OR2X2TS U2713 ( .A(n3006), .B(n3005), .Y(n2204) );
INVX2TS U2714 ( .A(n3253), .Y(n3345) );
XNOR2X1TS U2715 ( .A(n4337), .B(n4336), .Y(n4338) );
BUFX8TS U2716 ( .A(n4337), .Y(n4181) );
BUFX12TS U2717 ( .A(n4337), .Y(n2375) );
MX2X2TS U2718 ( .A(FPMULT_P_Sgf[34]), .B(n4463), .S0(n6958), .Y(n1563) );
INVX2TS U2719 ( .A(n3337), .Y(n3428) );
CLKMX2X2TS U2720 ( .A(FPMULT_P_Sgf[28]), .B(n4424), .S0(n6290), .Y(n1557) );
BUFX16TS U2721 ( .A(n3163), .Y(n3406) );
CLKMX2X2TS U2722 ( .A(FPMULT_P_Sgf[27]), .B(n4320), .S0(n6956), .Y(n1556) );
CLKMX2X2TS U2723 ( .A(FPMULT_P_Sgf[26]), .B(n5904), .S0(n6290), .Y(n1555) );
CLKMX2X2TS U2724 ( .A(FPMULT_P_Sgf[25]), .B(n5914), .S0(n6958), .Y(n1554) );
CLKMX2X2TS U2725 ( .A(FPMULT_P_Sgf[23]), .B(n5929), .S0(n6956), .Y(n1552) );
CLKMX2X2TS U2726 ( .A(FPMULT_P_Sgf[21]), .B(n6311), .S0(n6956), .Y(n1550) );
CLKMX2X2TS U2727 ( .A(FPMULT_P_Sgf[22]), .B(n6281), .S0(n6956), .Y(n1551) );
CLKMX2X2TS U2728 ( .A(FPMULT_P_Sgf[20]), .B(n6302), .S0(n6956), .Y(n1549) );
CLKMX2X2TS U2729 ( .A(FPMULT_P_Sgf[18]), .B(n6291), .S0(n6957), .Y(n1547) );
INVX2TS U2730 ( .A(n3588), .Y(n3597) );
OAI21X1TS U2731 ( .A0(n6305), .A1(n6304), .B0(n6303), .Y(n6310) );
NOR2X2TS U2732 ( .A(n2754), .B(n3052), .Y(n2757) );
NOR2X4TS U2733 ( .A(n3583), .B(n3578), .Y(n3570) );
NOR2X4TS U2734 ( .A(DP_OP_499J223_125_1651_n203), .B(n3110), .Y(n3132) );
NOR2X4TS U2735 ( .A(DP_OP_501J223_127_5235_n154), .B(
DP_OP_501J223_127_5235_n162), .Y(n3599) );
XNOR2X1TS U2736 ( .A(n3777), .B(n3776), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9) );
XNOR2X2TS U2737 ( .A(n2997), .B(n2814), .Y(n2982) );
OAI21X2TS U2738 ( .A0(n5500), .A1(n5482), .B0(n5481), .Y(n5486) );
OAI21X1TS U2739 ( .A0(n5500), .A1(n5492), .B0(n5491), .Y(n5496) );
NOR2X2TS U2740 ( .A(n2325), .B(n3699), .Y(DP_OP_501J223_127_5235_n232) );
ADDHX2TS U2741 ( .A(n3669), .B(n3668), .CO(DP_OP_501J223_127_5235_n150), .S(
DP_OP_501J223_127_5235_n151) );
INVX2TS U2742 ( .A(n4205), .Y(n3410) );
CLKMX2X2TS U2743 ( .A(FPMULT_Add_result[22]), .B(n5857), .S0(n5931), .Y(
n1598) );
CLKMX2X2TS U2744 ( .A(FPMULT_Add_result[21]), .B(n5859), .S0(n5873), .Y(
n1599) );
INVX2TS U2745 ( .A(n4204), .Y(DP_OP_499J223_125_1651_n301) );
ADDHX2TS U2746 ( .A(n3676), .B(n3675), .CO(n3671), .S(
DP_OP_501J223_127_5235_n178) );
XOR2X1TS U2747 ( .A(n6166), .B(n6165), .Y(n6171) );
OR2X2TS U2748 ( .A(n3739), .B(n3738), .Y(n2500) );
INVX4TS U2749 ( .A(n5315), .Y(n5389) );
INVX2TS U2750 ( .A(n4220), .Y(DP_OP_499J223_125_1651_n302) );
INVX4TS U2751 ( .A(n6629), .Y(n2374) );
CLKMX2X2TS U2752 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_exp_oper_result[8]), .S0(n5933), .Y(n1595) );
NOR2X4TS U2753 ( .A(n6521), .B(n5386), .Y(n5232) );
OR2X4TS U2754 ( .A(n5392), .B(n5236), .Y(n5237) );
OR2X2TS U2755 ( .A(DP_OP_500J223_126_4510_n129), .B(
DP_OP_500J223_126_4510_n135), .Y(n5591) );
INVX1TS U2756 ( .A(n5143), .Y(n5144) );
NOR2X4TS U2757 ( .A(n2874), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(n2945)
);
ADDFHX1TS U2758 ( .A(n3956), .B(n3955), .CI(n3954), .CO(n3960), .S(n3948) );
INVX4TS U2759 ( .A(n2322), .Y(n5424) );
NAND4BX1TS U2760 ( .AN(n6018), .B(FPMULT_Exp_module_Data_S[6]), .C(
FPMULT_Exp_module_Data_S[5]), .D(FPMULT_Exp_module_Data_S[4]), .Y(
n6019) );
AOI2BB1X1TS U2761 ( .A0N(n2340), .A1N(FPADDSUB_LZD_output_NRM2_EW[1]), .B0(
n6015), .Y(n1409) );
INVX4TS U2762 ( .A(n2322), .Y(n5434) );
AOI211X1TS U2763 ( .A0(n5231), .A1(FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n4818),
.C0(n4817), .Y(n4821) );
CLKMX2X2TS U2764 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_exp_oper_result[6]), .S0(n5933), .Y(n1588) );
OR2X2TS U2765 ( .A(DP_OP_502J223_128_4510_n129), .B(
DP_OP_502J223_128_4510_n135), .Y(n2472) );
NAND2X2TS U2766 ( .A(n3655), .B(n3654), .Y(n3656) );
AOI31X2TS U2767 ( .A0(n5214), .A1(n5213), .A2(n5212), .B0(n2341), .Y(n6016)
);
AOI2BB2X1TS U2768 ( .B0(FPSENCOS_d_ff2_X[30]), .B1(n6435), .A0N(n6435),
.A1N(FPSENCOS_d_ff2_X[30]), .Y(n4557) );
INVX4TS U2769 ( .A(n2577), .Y(n5308) );
AOI2BB2X1TS U2770 ( .B0(FPSENCOS_d_ff2_Y[30]), .B1(n6466), .A0N(n6466),
.A1N(FPSENCOS_d_ff2_Y[30]), .Y(n6467) );
INVX4TS U2771 ( .A(n2577), .Y(n5313) );
NOR2X4TS U2772 ( .A(n6706), .B(n6668), .Y(n2224) );
OAI22X1TS U2773 ( .A0(n3901), .A1(n3868), .B0(n2368), .B1(
DP_OP_501J223_127_5235_n723), .Y(n3912) );
BUFX4TS U2774 ( .A(n4995), .Y(n6550) );
AOI2BB2X1TS U2775 ( .B0(n6438), .B1(n6432), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n6464), .Y(n1947) );
INVX3TS U2776 ( .A(n3653), .Y(n3655) );
AOI2BB2X1TS U2777 ( .B0(n6444), .B1(n6460), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n6464), .Y(n1849) );
INVX2TS U2778 ( .A(n3626), .Y(n3628) );
AO21X1TS U2779 ( .A0(FPSENCOS_d_ff3_LUT_out[13]), .A1(n6408), .B0(n6366),
.Y(n2121) );
OAI21X1TS U2780 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n6455), .B0(n5013),
.Y(n4760) );
NAND2BX1TS U2781 ( .AN(n3900), .B(n2308), .Y(n3893) );
NAND2X4TS U2782 ( .A(n3521), .B(n3520), .Y(n3654) );
XOR2X1TS U2783 ( .A(n6756), .B(n6360), .Y(n2137) );
AO21X1TS U2784 ( .A0(n5660), .A1(n5659), .B0(n5661), .Y(n5449) );
OAI2BB2XLTS U2785 ( .B0(n6442), .B1(n6396), .A0N(n6408), .A1N(
FPSENCOS_d_ff3_sh_x_out[0]), .Y(n2004) );
OR2X4TS U2786 ( .A(n3937), .B(FPMULT_Op_MY[11]), .Y(n3522) );
AO21X1TS U2787 ( .A0(n5770), .A1(n5769), .B0(n5771), .Y(n4895) );
OAI2BB2XLTS U2788 ( .B0(n6442), .B1(n6399), .A0N(n6408), .A1N(
FPSENCOS_d_ff3_sh_x_out[2]), .Y(n2000) );
OAI211X1TS U2789 ( .A0(n5460), .A1(n6787), .B0(n5459), .C0(n5458), .Y(n1693)
);
AOI31X1TS U2790 ( .A0(n4692), .A1(n5218), .A2(n4691), .B0(n4690), .Y(n4693)
);
OAI21X1TS U2791 ( .A0(n4470), .A1(n6007), .B0(n6006), .Y(n4471) );
OAI21X1TS U2792 ( .A0(n6008), .A1(n6007), .B0(n6006), .Y(n6010) );
AO22X1TS U2793 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n6709),
.B1(FPADDSUB_DMP_SFG[27]), .Y(n1435) );
INVX4TS U2794 ( .A(n5637), .Y(n2350) );
AO22X1TS U2795 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n6709),
.B1(FPADDSUB_DMP_SFG[26]), .Y(n1440) );
AO22X1TS U2796 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n6709),
.B1(FPADDSUB_DMP_SFG[29]), .Y(n1425) );
AO22X1TS U2797 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n6003),
.B1(FPADDSUB_DMP_SFG[23]), .Y(n1455) );
AO22X1TS U2798 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n6709),
.B1(FPADDSUB_DMP_SFG[28]), .Y(n1430) );
OAI21X1TS U2799 ( .A0(n6185), .A1(n6100), .B0(n6099), .Y(n6105) );
AO22X1TS U2800 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n6709),
.B1(FPADDSUB_DMP_SFG[25]), .Y(n1445) );
AO22X1TS U2801 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n6003),
.B1(FPADDSUB_DMP_SFG[30]), .Y(n1420) );
AO22X1TS U2802 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n6709),
.B1(FPADDSUB_DMP_SFG[24]), .Y(n1450) );
AO21X1TS U2803 ( .A0(n5448), .A1(n5446), .B0(n5445), .Y(n4972) );
AO22X1TS U2804 ( .A0(n6635), .A1(n6622), .B0(n6625), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1474) );
AO22X1TS U2805 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n6382), .B1(
Data_1[15]), .Y(n2097) );
INVX4TS U2806 ( .A(n6444), .Y(n6442) );
AO22X1TS U2807 ( .A0(n6710), .A1(FPADDSUB_SIGN_FLAG_SHT2), .B0(n6709), .B1(
FPADDSUB_SIGN_FLAG_SFG), .Y(n1359) );
OAI21X1TS U2808 ( .A0(n6185), .A1(n6052), .B0(n6051), .Y(n6056) );
OAI21X1TS U2809 ( .A0(n6185), .A1(n6029), .B0(n6028), .Y(n6033) );
AO22X1TS U2810 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n6382), .B1(
Data_1[18]), .Y(n2094) );
AO22X1TS U2811 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2326), .Y(n5943) );
INVX4TS U2812 ( .A(n5935), .Y(n2382) );
AO22X4TS U2813 ( .A0(operation[1]), .A1(n6336), .B0(begin_operation), .B1(
n4994), .Y(n5461) );
AND2X2TS U2814 ( .A(n5207), .B(n4812), .Y(n5215) );
AO22X1TS U2815 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n2326), .B0(
FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n5957), .Y(n5938) );
AOI31X1TS U2816 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[16]), .A1(n5207), .A2(n6758),
.B0(n5206), .Y(n5214) );
AO22X1TS U2817 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n2342), .Y(n5950) );
AO22X1TS U2818 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n2342), .Y(n5953) );
AO22X1TS U2819 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[2]), .B1(n2342), .Y(n5941) );
AND3X2TS U2820 ( .A(n5276), .B(n5275), .C(n5274), .Y(n5396) );
AO21X1TS U2821 ( .A0(n4468), .A1(n4467), .B0(n4466), .Y(intadd_515_B_6_) );
INVX8TS U2822 ( .A(n2368), .Y(n2205) );
INVX4TS U2823 ( .A(n6439), .Y(n6413) );
INVX4TS U2824 ( .A(n5265), .Y(n5372) );
INVX4TS U2825 ( .A(n5265), .Y(n5379) );
INVX4TS U2826 ( .A(n2815), .Y(n2825) );
CLKINVX1TS U2827 ( .A(n6339), .Y(n6341) );
CLKBUFX2TS U2828 ( .A(n3288), .Y(n2326) );
INVX4TS U2829 ( .A(FPADDSUB_left_right_SHT2), .Y(n5984) );
INVX4TS U2830 ( .A(n5876), .Y(n5899) );
INVX4TS U2831 ( .A(n6392), .Y(n6528) );
AND2X4TS U2832 ( .A(n4473), .B(n4485), .Y(n5637) );
INVX2TS U2833 ( .A(n3542), .Y(n3544) );
INVX4TS U2834 ( .A(DP_OP_501J223_127_5235_n630), .Y(n3900) );
INVX4TS U2835 ( .A(n6392), .Y(n6539) );
NOR2X1TS U2836 ( .A(n5205), .B(FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n5206) );
NAND2BX1TS U2837 ( .AN(n5780), .B(n2287), .Y(n5785) );
INVX6TS U2838 ( .A(n3467), .Y(n3482) );
INVX4TS U2839 ( .A(n3453), .Y(n3433) );
NAND2X1TS U2840 ( .A(n5326), .B(FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n5322) );
INVX4TS U2841 ( .A(n6354), .Y(n6022) );
OAI21X1TS U2842 ( .A0(n4371), .A1(n4517), .B0(n4370), .Y(n4372) );
OAI21X1TS U2843 ( .A0(n4529), .A1(n4533), .B0(n4530), .Y(n4255) );
INVX4TS U2844 ( .A(n6354), .Y(n6730) );
AOI2BB1X1TS U2845 ( .A0N(n5204), .A1N(FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n5205) );
INVX4TS U2846 ( .A(n5340), .Y(n5326) );
OR2X2TS U2847 ( .A(n4133), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]), .Y(
n4134) );
NOR2X1TS U2848 ( .A(n2554), .B(FPADDSUB_intDY_EWSW[16]), .Y(n2507) );
ADDHX2TS U2849 ( .A(n2315), .B(n6764), .CO(n3449), .S(n3440) );
NAND3BX1TS U2850 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n4660),
.C(n4992), .Y(n4661) );
CLKMX2X2TS U2851 ( .A(n6936), .B(n6935), .S0(n6917), .Y(n1574) );
NAND2BX1TS U2852 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n2537) );
OAI21X1TS U2853 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n2467), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n2532) );
CLKMX2X2TS U2854 ( .A(n6932), .B(n6931), .S0(n6916), .Y(n1561) );
INVX4TS U2855 ( .A(n2248), .Y(n2286) );
ADDHX2TS U2856 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MX[19]), .CO(n3729), .S(
n3728) );
CLKMX2X2TS U2857 ( .A(n6950), .B(n6949), .S0(n6917), .Y(n1570) );
CLKMX2X2TS U2858 ( .A(n6954), .B(n6953), .S0(n6917), .Y(n1569) );
CLKMX2X2TS U2859 ( .A(n6940), .B(n6939), .S0(n6917), .Y(n1571) );
CLKMX2X2TS U2860 ( .A(n6930), .B(n6929), .S0(n6916), .Y(n1566) );
CLKMX2X2TS U2861 ( .A(n6938), .B(n6937), .S0(n6916), .Y(n1567) );
CLKMX2X2TS U2862 ( .A(n6928), .B(n6927), .S0(n6917), .Y(n1572) );
CLKMX2X2TS U2863 ( .A(n6934), .B(n6933), .S0(n6916), .Y(n1568) );
INVX2TS U2864 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .Y(n2849) );
CLKMX2X2TS U2865 ( .A(n6926), .B(n6925), .S0(n6924), .Y(n1694) );
INVX2TS U2866 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .Y(n2726)
);
CLKMX2X2TS U2867 ( .A(n6948), .B(n6947), .S0(n6916), .Y(n1565) );
CLKMX2X2TS U2868 ( .A(n6952), .B(n6951), .S0(n6917), .Y(n1573) );
INVX2TS U2869 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(n2830)
);
INVX2TS U2870 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(n2829) );
INVX2TS U2871 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]), .Y(n3223)
);
INVX4TS U2872 ( .A(operation[1]), .Y(n6342) );
XOR2X2TS U2873 ( .A(n3421), .B(n3420), .Y(FPMULT_Sgf_operation_Result[44])
);
XOR2X2TS U2874 ( .A(n3416), .B(DP_OP_499J223_125_1651_n297), .Y(
FPMULT_Sgf_operation_Result[40]) );
AOI21X2TS U2875 ( .A0(n4181), .A1(n3404), .B0(n3403), .Y(n3405) );
XOR2X2TS U2876 ( .A(n4448), .B(n4447), .Y(n4449) );
INVX3TS U2877 ( .A(n3357), .Y(n3418) );
NOR2X2TS U2878 ( .A(n3417), .B(n3420), .Y(n3359) );
NOR2X2TS U2879 ( .A(n3422), .B(DP_OP_499J223_125_1651_n299), .Y(n3409) );
XNOR2X2TS U2880 ( .A(n3286), .B(n3285), .Y(n3287) );
INVX3TS U2881 ( .A(n4420), .Y(n3060) );
AOI21X2TS U2882 ( .A0(n3571), .A1(n2429), .B0(n2457), .Y(n3560) );
NAND2X2TS U2883 ( .A(n3570), .B(n3549), .Y(n3551) );
AO21X1TS U2884 ( .A0(n3562), .A1(n3559), .B0(n3558), .Y(n2457) );
NOR2X2TS U2885 ( .A(n3565), .B(n3557), .Y(n3559) );
OR2X2TS U2886 ( .A(n3137), .B(DP_OP_496J223_122_3236_n147), .Y(n3139) );
OAI21X1TS U2887 ( .A0(n6252), .A1(n6251), .B0(n6250), .Y(n6257) );
NAND2X2TS U2888 ( .A(DP_OP_501J223_127_5235_n173), .B(
DP_OP_501J223_127_5235_n180), .Y(n3608) );
OR2X4TS U2889 ( .A(DP_OP_501J223_127_5235_n163), .B(
DP_OP_501J223_127_5235_n172), .Y(n3501) );
OAI21X1TS U2890 ( .A0(n3798), .A1(n3794), .B0(n3795), .Y(n3793) );
OR2X2TS U2891 ( .A(n3004), .B(n4232), .Y(n2471) );
NOR2X1TS U2892 ( .A(n3326), .B(n3350), .Y(n3327) );
OAI21X1TS U2893 ( .A0(n3787), .A1(n3769), .B0(n3768), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11) );
OAI211X1TS U2894 ( .A0(n5400), .A1(n5399), .B0(n5398), .C0(n5397), .Y(n1809)
);
INVX2TS U2895 ( .A(n2213), .Y(n4232) );
OAI21X2TS U2896 ( .A0(n3983), .A1(n3979), .B0(n3980), .Y(n3978) );
ADDFHX2TS U2897 ( .A(n3652), .B(n3651), .CI(n3650), .CO(
DP_OP_501J223_127_5235_n126), .S(DP_OP_501J223_127_5235_n127) );
OAI211X1TS U2898 ( .A0(n5399), .A1(n5349), .B0(n5321), .C0(n5320), .Y(n1804)
);
NOR2X4TS U2899 ( .A(n3003), .B(n3002), .Y(n2994) );
OAI211X1TS U2900 ( .A0(n5385), .A1(n5237), .B0(n5332), .C0(n5331), .Y(n1787)
);
INVX2TS U2901 ( .A(n3612), .Y(n3500) );
OAI211X1TS U2902 ( .A0(n5389), .A1(n5349), .B0(n5245), .C0(n5244), .Y(n1805)
);
OAI211X1TS U2903 ( .A0(n5237), .A1(n5349), .B0(n5334), .C0(n5333), .Y(n1803)
);
OAI211X1TS U2904 ( .A0(n5381), .A1(n5349), .B0(n5348), .C0(n5347), .Y(n1802)
);
OAI21X1TS U2905 ( .A0(n3774), .A1(n3765), .B0(n3764), .Y(n3766) );
OAI211X1TS U2906 ( .A0(n5381), .A1(n5370), .B0(n5369), .C0(n5368), .Y(n1801)
);
OAI211X1TS U2907 ( .A0(n5389), .A1(n5365), .B0(n5281), .C0(n5280), .Y(n1807)
);
INVX2TS U2908 ( .A(n3763), .Y(n3775) );
OAI211X1TS U2909 ( .A0(n5399), .A1(n5377), .B0(n5376), .C0(n5375), .Y(n1798)
);
NOR2X2TS U2910 ( .A(n3789), .B(n3794), .Y(n3744) );
AO22X1TS U2911 ( .A0(n4271), .A1(n4499), .B0(FPADDSUB_ADD_OVRFLW_NRM), .B1(
n6711), .Y(n1351) );
OAI211X1TS U2912 ( .A0(n5389), .A1(n5261), .B0(n5257), .C0(n5256), .Y(n1793)
);
OAI211X1TS U2913 ( .A0(n5389), .A1(n5353), .B0(n5268), .C0(n5267), .Y(n1795)
);
XOR2X1TS U2914 ( .A(n5584), .B(n5583), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7) );
OAI211X1TS U2915 ( .A0(n5399), .A1(n5353), .B0(n5352), .C0(n5351), .Y(n1794)
);
OAI211X1TS U2916 ( .A0(n5380), .A1(n5399), .B0(n5357), .C0(n5356), .Y(n1791)
);
OAI211X1TS U2917 ( .A0(n5380), .A1(n5389), .B0(n5264), .C0(n5263), .Y(n1792)
);
OAI21X2TS U2918 ( .A0(n3789), .A1(n3795), .B0(n3790), .Y(n3743) );
OAI211X1TS U2919 ( .A0(n5381), .A1(n5377), .B0(n5338), .C0(n5337), .Y(n1796)
);
INVX4TS U2920 ( .A(n2917), .Y(DP_OP_499J223_125_1651_n274) );
OAI211X1TS U2921 ( .A0(n5385), .A1(n5399), .B0(n5343), .C0(n5342), .Y(n1788)
);
OAI211X1TS U2922 ( .A0(n5389), .A1(n5377), .B0(n5284), .C0(n5283), .Y(n1799)
);
OAI211X1TS U2923 ( .A0(n5389), .A1(n5282), .B0(n5272), .C0(n5271), .Y(n1800)
);
INVX4TS U2924 ( .A(n4233), .Y(DP_OP_499J223_125_1651_n296) );
INVX3TS U2925 ( .A(n4209), .Y(DP_OP_499J223_125_1651_n294) );
INVX12TS U2926 ( .A(n2333), .Y(n2334) );
NAND2X2TS U2927 ( .A(DP_OP_501J223_127_5235_n188), .B(n3499), .Y(n3616) );
OAI21X1TS U2928 ( .A0(n4004), .A1(n4010), .B0(n4011), .Y(n4009) );
XOR2X1TS U2929 ( .A(n5589), .B(n5588), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6) );
XOR2X1TS U2930 ( .A(n5511), .B(n5510), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7) );
NOR2X1TS U2931 ( .A(n2325), .B(n3692), .Y(n3552) );
AO21X1TS U2932 ( .A0(result_add_subt[4]), .A1(n6354), .B0(n3303), .Y(n1387)
);
OAI21X1TS U2933 ( .A0(n5500), .A1(n5487), .B0(n5497), .Y(n3398) );
OAI21X1TS U2934 ( .A0(n5510), .A1(n5507), .B0(n5508), .Y(n5506) );
OAI21X2TS U2935 ( .A0(n4005), .A1(n4011), .B0(n4006), .Y(n3907) );
NOR2X2TS U2936 ( .A(n4005), .B(n4010), .Y(n3908) );
INVX3TS U2937 ( .A(n6270), .Y(DP_OP_499J223_125_1651_n277) );
ADDHX2TS U2938 ( .A(n3674), .B(n3673), .CO(DP_OP_501J223_127_5235_n169), .S(
n3670) );
MX2X2TS U2939 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(n5936), .S0(n6260),
.Y(n1585) );
INVX6TS U2940 ( .A(n3460), .Y(n3709) );
NOR2X4TS U2941 ( .A(n3906), .B(n3905), .Y(n4005) );
NAND2X2TS U2942 ( .A(n3906), .B(n3905), .Y(n4006) );
NOR2X4TS U2943 ( .A(n3942), .B(n3941), .Y(n3995) );
OR2X2TS U2944 ( .A(DP_OP_500J223_126_4510_n101), .B(n5192), .Y(n2487) );
CLKINVX6TS U2945 ( .A(n2252), .Y(n2354) );
BUFX12TS U2946 ( .A(n3219), .Y(n3333) );
NAND2X2TS U2947 ( .A(n3942), .B(n3941), .Y(n3996) );
XOR2X1TS U2948 ( .A(n5598), .B(n5597), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4) );
OR2X2TS U2949 ( .A(n3958), .B(n3957), .Y(n2475) );
AFHCINX2TS U2950 ( .CIN(n4015), .B(n4016), .A(n4017), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5), .CO(n4013) );
XOR2X1TS U2951 ( .A(n5603), .B(n5602), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3) );
OR2X2TS U2952 ( .A(n3944), .B(n3943), .Y(n2476) );
NOR2X4TS U2953 ( .A(n3904), .B(n3903), .Y(n4010) );
OAI21X1TS U2954 ( .A0(n6810), .A1(n5426), .B0(n5402), .Y(n1458) );
AOI2BB1X1TS U2955 ( .A0N(n6022), .A1N(overflow_flag_addsubt), .B0(n6017),
.Y(n1411) );
OAI21X1TS U2956 ( .A0(n6812), .A1(n5426), .B0(n5401), .Y(n1459) );
OAI21X1TS U2957 ( .A0(n2568), .A1(n5426), .B0(n5406), .Y(n1460) );
OAI21X1TS U2958 ( .A0(n2215), .A1(n5426), .B0(n5416), .Y(n1461) );
OAI21X1TS U2959 ( .A0(n2273), .A1(n5426), .B0(n5425), .Y(n1310) );
OAI21X1TS U2960 ( .A0(n2270), .A1(n5433), .B0(n5412), .Y(n1253) );
OAI21X1TS U2961 ( .A0(n2552), .A1(n5433), .B0(n5432), .Y(n1249) );
OAI21X1TS U2962 ( .A0(n6811), .A1(n5426), .B0(n5404), .Y(n1463) );
OAI21X1TS U2963 ( .A0(n6804), .A1(n5426), .B0(n5403), .Y(n1462) );
OAI21X1TS U2964 ( .A0(n2413), .A1(n5436), .B0(n5423), .Y(n1245) );
OAI21X1TS U2965 ( .A0(n2233), .A1(n5433), .B0(n5429), .Y(n1261) );
OAI21X1TS U2966 ( .A0(n2278), .A1(n5426), .B0(n5407), .Y(n1326) );
OAI21X1TS U2967 ( .A0(n2526), .A1(n5426), .B0(n3399), .Y(n1303) );
OAI21X1TS U2968 ( .A0(n2432), .A1(n5436), .B0(n5414), .Y(n1233) );
OAI21X1TS U2969 ( .A0(n5144), .A1(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n6017),
.Y(n5145) );
OAI21X1TS U2970 ( .A0(n2274), .A1(n5436), .B0(n5428), .Y(n1229) );
OAI21X1TS U2971 ( .A0(n2516), .A1(n5433), .B0(n5430), .Y(n1265) );
OAI21X1TS U2972 ( .A0(n6803), .A1(n5426), .B0(n5415), .Y(n1464) );
OAI21X1TS U2973 ( .A0(n2271), .A1(n5436), .B0(n5435), .Y(n1225) );
OAI21X1TS U2974 ( .A0(n2272), .A1(n5436), .B0(n5411), .Y(n1217) );
OAI21X1TS U2975 ( .A0(n2279), .A1(n5436), .B0(n5409), .Y(n1213) );
OAI21X1TS U2976 ( .A0(n2231), .A1(n5433), .B0(n5420), .Y(n1269) );
OAI21X1TS U2977 ( .A0(n2232), .A1(n5436), .B0(n5419), .Y(n1209) );
OAI21X1TS U2978 ( .A0(n2234), .A1(n5433), .B0(n5417), .Y(n1282) );
OAI21X1TS U2979 ( .A0(n2434), .A1(n5433), .B0(n5410), .Y(n1289) );
XOR2X1TS U2980 ( .A(n5529), .B(n5528), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3) );
OAI211X1TS U2981 ( .A0(n5052), .A1(n2415), .B0(n5005), .C0(n5004), .Y(n1819)
);
OAI211X1TS U2982 ( .A0(n5067), .A1(n2439), .B0(n5033), .C0(n5032), .Y(n1837)
);
OAI211X1TS U2983 ( .A0(n5110), .A1(n6418), .B0(n5051), .C0(n5050), .Y(n1926)
);
OAI21X2TS U2984 ( .A0(n5502), .A1(n5508), .B0(n5503), .Y(n3395) );
XOR2X1TS U2985 ( .A(n5524), .B(n5523), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4) );
CLKMX2X2TS U2986 ( .A(FPMULT_Exp_module_Data_S[7]), .B(
FPMULT_exp_oper_result[7]), .S0(n5933), .Y(n1587) );
AOI222X1TS U2987 ( .A0(n5167), .A1(cordic_result[19]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[19]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[19]), .Y(n5133) );
OAI21X1TS U2988 ( .A0(n2274), .A1(n5310), .B0(n5305), .Y(n1392) );
AOI222X1TS U2989 ( .A0(n5167), .A1(cordic_result[12]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[12]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[12]), .Y(n5126) );
AOI222X1TS U2990 ( .A0(n5167), .A1(cordic_result[17]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[17]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[17]), .Y(n5122) );
OAI21X1TS U2991 ( .A0(n6813), .A1(n5310), .B0(n5286), .Y(n1386) );
AOI222X1TS U2992 ( .A0(n5167), .A1(cordic_result[14]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[14]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[14]), .Y(n5120) );
OAI21X1TS U2993 ( .A0(n2525), .A1(n5310), .B0(n5303), .Y(n1383) );
OAI21X1TS U2994 ( .A0(n2413), .A1(n5312), .B0(n5301), .Y(n1380) );
OAI211X1TS U2995 ( .A0(n5087), .A1(n6872), .B0(n5023), .C0(n5022), .Y(n1914)
);
OAI211X1TS U2996 ( .A0(n5087), .A1(n6871), .B0(n5021), .C0(n5020), .Y(n1912)
);
OAI21X1TS U2997 ( .A0(n2552), .A1(n5312), .B0(n5302), .Y(n1377) );
OAI211X1TS U2998 ( .A0(n5110), .A1(n6423), .B0(n5091), .C0(n5090), .Y(n1922)
);
NAND3BX1TS U2999 ( .AN(FPMULT_Exp_module_Data_S[7]), .B(n6020), .C(n6019),
.Y(n6021) );
OAI21X1TS U3000 ( .A0(n2230), .A1(n5312), .B0(n5298), .Y(n1371) );
OAI211X1TS U3001 ( .A0(n5067), .A1(n2436), .B0(n5041), .C0(n5040), .Y(n1834)
);
AOI222X1TS U3002 ( .A0(n6562), .A1(cordic_result[1]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[1]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[1]), .Y(n5117)
);
OAI21X1TS U3003 ( .A0(n2233), .A1(n5312), .B0(n5306), .Y(n1368) );
OAI21X1TS U3004 ( .A0(n2516), .A1(n5312), .B0(n5304), .Y(n1365) );
OAI21X1TS U3005 ( .A0(n2278), .A1(n5312), .B0(n5293), .Y(n1328) );
NAND3X1TS U3006 ( .A(n6482), .B(n6481), .C(n6480), .Y(n1832) );
NAND3X1TS U3007 ( .A(n6476), .B(n6475), .C(n6486), .Y(n1838) );
NAND3X1TS U3008 ( .A(n6478), .B(n6477), .C(n6480), .Y(n1836) );
NAND3X1TS U3009 ( .A(n6493), .B(n6492), .C(n6491), .Y(n1827) );
NAND3X1TS U3010 ( .A(n6512), .B(n6511), .C(n6515), .Y(n1816) );
OAI21X1TS U3011 ( .A0(n4821), .A1(n7059), .B0(n4820), .Y(n1318) );
OAI211X1TS U3012 ( .A0(n5116), .A1(n6402), .B0(n5057), .C0(n5056), .Y(n1937)
);
NAND3X1TS U3013 ( .A(n6504), .B(n6503), .C(n6502), .Y(n1823) );
NAND3X1TS U3014 ( .A(n6501), .B(n6500), .C(n6506), .Y(n1824) );
NAND3X1TS U3015 ( .A(n6484), .B(n6483), .C(n6497), .Y(n1830) );
OAI211X1TS U3016 ( .A0(n5052), .A1(n2453), .B0(n5003), .C0(n5002), .Y(n1831)
);
NAND3X1TS U3017 ( .A(n6508), .B(n6507), .C(n6506), .Y(n1821) );
AOI222X1TS U3018 ( .A0(n5291), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n6846),
.B1(n6708), .C0(FPADDSUB_intDX_EWSW[24]), .C1(n4321), .Y(n7074) );
OAI211X1TS U3019 ( .A0(n5087), .A1(n6873), .B0(n5017), .C0(n5016), .Y(n1917)
);
OAI211X1TS U3020 ( .A0(n5052), .A1(n6457), .B0(n5011), .C0(n5010), .Y(n1820)
);
AOI222X1TS U3021 ( .A0(n5424), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n6822),
.B1(n6708), .C0(FPADDSUB_intDX_EWSW[23]), .C1(n5291), .Y(n7072) );
OAI21X1TS U3022 ( .A0(n2269), .A1(n5312), .B0(n5311), .Y(n1305) );
OAI211X1TS U3023 ( .A0(n5110), .A1(n6417), .B0(n5079), .C0(n5078), .Y(n1927)
);
NAND3X1TS U3024 ( .A(n6473), .B(n6472), .C(n6491), .Y(n1840) );
OAI21X1TS U3025 ( .A0(n2275), .A1(n2323), .B0(n5295), .Y(n1298) );
OAI211X1TS U3026 ( .A0(n5116), .A1(n6409), .B0(n5059), .C0(n5058), .Y(n1932)
);
OAI21X1TS U3027 ( .A0(n4821), .A1(n2336), .B0(n4819), .Y(n2077) );
AOI222X1TS U3028 ( .A0(n5291), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n6857),
.B1(n6708), .C0(FPADDSUB_intDX_EWSW[26]), .C1(n4321), .Y(n7076) );
OAI211X1TS U3029 ( .A0(n5116), .A1(n6407), .B0(n5055), .C0(n5054), .Y(n1933)
);
OAI211X1TS U3030 ( .A0(n5110), .A1(n6410), .B0(n5073), .C0(n5072), .Y(n1930)
);
OAI211X1TS U3031 ( .A0(n5052), .A1(n2445), .B0(n5007), .C0(n5006), .Y(n1817)
);
OAI211X1TS U3032 ( .A0(n5087), .A1(n2416), .B0(n5075), .C0(n5074), .Y(n1919)
);
OAI21X1TS U3033 ( .A0(n2434), .A1(n2323), .B0(n5294), .Y(n1291) );
OAI211X1TS U3034 ( .A0(n5110), .A1(n6412), .B0(n5099), .C0(n5098), .Y(n1929)
);
OAI211X1TS U3035 ( .A0(n5087), .A1(n6425), .B0(n5086), .C0(n5085), .Y(n1921)
);
OAI211X1TS U3036 ( .A0(n5087), .A1(n6874), .B0(n5025), .C0(n5024), .Y(n1916)
);
OAI211X1TS U3037 ( .A0(n5087), .A1(n6875), .B0(n5027), .C0(n5026), .Y(n1915)
);
OAI211X1TS U3038 ( .A0(n5052), .A1(n2441), .B0(n5009), .C0(n5008), .Y(n1818)
);
OAI211X1TS U3039 ( .A0(n5116), .A1(n6399), .B0(n5083), .C0(n5082), .Y(n1939)
);
OAI211X1TS U3040 ( .A0(n5110), .A1(n6420), .B0(n5096), .C0(n5095), .Y(n1924)
);
OAI21X1TS U3041 ( .A0(n2234), .A1(n2323), .B0(n5299), .Y(n1284) );
OAI211X1TS U3042 ( .A0(n5067), .A1(n2435), .B0(n5043), .C0(n5042), .Y(n1839)
);
OAI211X1TS U3043 ( .A0(n5116), .A1(n6398), .B0(n5105), .C0(n5104), .Y(n1940)
);
OAI21X1TS U3044 ( .A0(n6692), .A1(n2323), .B0(n5314), .Y(n1277) );
OAI211X1TS U3045 ( .A0(n5067), .A1(n2428), .B0(n5037), .C0(n5036), .Y(n1842)
);
NAND3X1TS U3046 ( .A(n6499), .B(n6498), .C(n6497), .Y(n1825) );
NAND3X1TS U3047 ( .A(n6490), .B(n6489), .C(n6502), .Y(n1828) );
OAI21X1TS U3048 ( .A0(n2231), .A1(n2323), .B0(n5300), .Y(n1271) );
NAND3X1TS U3049 ( .A(n6496), .B(n6495), .C(n6502), .Y(n1826) );
OAI211X1TS U3050 ( .A0(n5087), .A1(n6783), .B0(n5047), .C0(n5046), .Y(n1918)
);
OAI211X1TS U3051 ( .A0(n5067), .A1(n2281), .B0(n5045), .C0(n5044), .Y(n1843)
);
NAND3X1TS U3052 ( .A(n6488), .B(n6487), .C(n6486), .Y(n1829) );
OAI211X1TS U3053 ( .A0(n5052), .A1(n6876), .B0(n5001), .C0(n5000), .Y(n1822)
);
OAI211X1TS U3054 ( .A0(n5067), .A1(n2282), .B0(n5035), .C0(n5034), .Y(n1841)
);
OAI211X1TS U3055 ( .A0(n5116), .A1(n6396), .B0(n5069), .C0(n5068), .Y(n1941)
);
OAI211X1TS U3056 ( .A0(n5116), .A1(n6406), .B0(n5115), .C0(n5114), .Y(n1934)
);
OAI211X1TS U3057 ( .A0(n5067), .A1(n6851), .B0(n5019), .C0(n5018), .Y(n1911)
);
OAI21X1TS U3058 ( .A0(n6761), .A1(n5312), .B0(n5285), .Y(n1237) );
OAI211X1TS U3059 ( .A0(n5110), .A1(n2417), .B0(n5102), .C0(n5101), .Y(n1925)
);
OAI211X1TS U3060 ( .A0(n5110), .A1(n2425), .B0(n5109), .C0(n5108), .Y(n1928)
);
OAI211X1TS U3061 ( .A0(n5116), .A1(n2422), .B0(n5093), .C0(n5092), .Y(n1935)
);
OAI211X1TS U3062 ( .A0(n5116), .A1(n6404), .B0(n5077), .C0(n5076), .Y(n1936)
);
OAI21X1TS U3063 ( .A0(n2215), .A1(n2323), .B0(n5289), .Y(n1413) );
OAI21X1TS U3064 ( .A0(n2277), .A1(n5310), .B0(n5292), .Y(n1398) );
ADDFHX1TS U3065 ( .A(n3912), .B(n3911), .CI(n3910), .CO(n3926), .S(n3916) );
OAI21X1TS U3066 ( .A0(n2232), .A1(n5310), .B0(n5290), .Y(n1407) );
OAI21X1TS U3067 ( .A0(n2271), .A1(n5310), .B0(n5309), .Y(n1395) );
OAI21X1TS U3068 ( .A0(n2272), .A1(n5310), .B0(n5288), .Y(n1401) );
AOI222X1TS U3069 ( .A0(n4984), .A1(cordic_result[27]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[27]), .C0(n5118), .C1(FPSENCOS_d_ff_Yn[27]), .Y(n5163) );
NAND2X4TS U3070 ( .A(n2874), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(n2961)
);
AOI222X1TS U3071 ( .A0(n5167), .A1(cordic_result[20]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[20]), .C0(n5118), .C1(FPSENCOS_d_ff_Yn[20]), .Y(n5168) );
AOI222X1TS U3072 ( .A0(n4984), .A1(cordic_result[26]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[26]), .C0(n5118), .C1(FPSENCOS_d_ff_Yn[26]), .Y(n5165) );
AOI222X1TS U3073 ( .A0(n4984), .A1(cordic_result[28]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[28]), .C0(n4985), .C1(FPSENCOS_d_ff_Yn[28]), .Y(n5159) );
AOI222X1TS U3074 ( .A0(n5167), .A1(cordic_result[24]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[24]), .C0(n5118), .C1(FPSENCOS_d_ff_Yn[24]), .Y(n5162) );
OR2X2TS U3075 ( .A(DP_OP_502J223_128_4510_n101), .B(n5149), .Y(n5494) );
OAI21X1TS U3076 ( .A0(n6364), .A1(n4989), .B0(n4988), .Y(n2128) );
AOI2BB2X1TS U3077 ( .B0(n6448), .B1(n6465), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n6464), .Y(n1847) );
AO22X1TS U3078 ( .A0(n6471), .A1(n6467), .B0(n6470), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1846) );
OAI211X1TS U3079 ( .A0(n2363), .A1(n6889), .B0(n4636), .C0(n4635), .Y(n1513)
);
OAI21X1TS U3080 ( .A0(n4696), .A1(n5238), .B0(n4694), .Y(n2075) );
OAI211X1TS U3081 ( .A0(n2362), .A1(n6885), .B0(n4629), .C0(n4628), .Y(n1517)
);
OAI211X1TS U3082 ( .A0(n2361), .A1(n6892), .B0(n4644), .C0(n4643), .Y(n1510)
);
AOI31X1TS U3083 ( .A0(n6704), .A1(n6703), .A2(n6702), .B0(n2323), .Y(n6705)
);
OAI21X1TS U3084 ( .A0(n4696), .A1(n2341), .B0(n4695), .Y(n1330) );
OAI211X1TS U3085 ( .A0(n2361), .A1(n6877), .B0(n4616), .C0(n4615), .Y(n1525)
);
OAI211X1TS U3086 ( .A0(n2361), .A1(n6879), .B0(n4597), .C0(n4596), .Y(n1523)
);
OAI211X1TS U3087 ( .A0(n2361), .A1(n6881), .B0(n4618), .C0(n4617), .Y(n1521)
);
OAI211X1TS U3088 ( .A0(n2361), .A1(n6883), .B0(n4606), .C0(n4605), .Y(n1519)
);
AO22X1TS U3089 ( .A0(n6471), .A1(n4557), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1944) );
NAND3X1TS U3090 ( .A(n6514), .B(n6513), .C(n6515), .Y(n1815) );
OAI211X1TS U3091 ( .A0(n2362), .A1(n6880), .B0(n4620), .C0(n4619), .Y(n1522)
);
OAI211X1TS U3092 ( .A0(n2363), .A1(n6882), .B0(n4614), .C0(n4613), .Y(n1520)
);
OAI211X1TS U3093 ( .A0(n2362), .A1(n6884), .B0(n4612), .C0(n4611), .Y(n1518)
);
OAI211X1TS U3094 ( .A0(n2361), .A1(n6895), .B0(n4625), .C0(n4624), .Y(n1507)
);
AOI2BB2X1TS U3095 ( .B0(n6438), .B1(n6437), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n6459), .Y(n1945) );
OAI211X1TS U3096 ( .A0(n2363), .A1(n6893), .B0(n4627), .C0(n4626), .Y(n1509)
);
OAI211X1TS U3097 ( .A0(n2362), .A1(n6888), .B0(n4592), .C0(n4591), .Y(n1514)
);
OAI211X1TS U3098 ( .A0(n2363), .A1(n6894), .B0(n4594), .C0(n4593), .Y(n1508)
);
OAI211X1TS U3099 ( .A0(n2362), .A1(n6890), .B0(n4604), .C0(n4603), .Y(n1512)
);
NAND3X1TS U3100 ( .A(n6517), .B(n6516), .C(n6515), .Y(n1814) );
NAND2X2TS U3101 ( .A(n3855), .B(n3854), .Y(n3856) );
AO22X1TS U3102 ( .A0(n6464), .A1(n6434), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1946) );
AO22X1TS U3103 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[10]), .B1(n6447), .Y(n1887) );
OAI21X1TS U3104 ( .A0(n4799), .A1(n5826), .B0(n5828), .Y(n4800) );
NAND2X2TS U3105 ( .A(n3478), .B(n3477), .Y(n3479) );
AO22X1TS U3106 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[12]), .B1(n6447), .Y(n1883) );
AO22X1TS U3107 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n2302), .B0(
FPSENCOS_d_ff_Yn[2]), .B1(n6447), .Y(n1903) );
OAI211X1TS U3108 ( .A0(n2362), .A1(n6896), .B0(n4599), .C0(n4598), .Y(n1506)
);
AO22X1TS U3109 ( .A0(n6471), .A1(n6462), .B0(n6470), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1848) );
AO22X1TS U3110 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n2302), .B0(
FPSENCOS_d_ff_Yn[17]), .B1(n6454), .Y(n1873) );
AO22X1TS U3111 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[9]), .B1(n6447), .Y(n1889) );
AO22X1TS U3112 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n4731), .B0(
FPSENCOS_d_ff_Yn[21]), .B1(n6468), .Y(n1865) );
AO22X1TS U3113 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n2302), .B0(
FPSENCOS_d_ff_Yn[22]), .B1(n6468), .Y(n1863) );
AO22X1TS U3114 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n4731), .B0(
FPSENCOS_d_ff_Yn[15]), .B1(n6447), .Y(n1877) );
AO21X1TS U3115 ( .A0(FPSENCOS_d_ff3_LUT_out[10]), .A1(n6408), .B0(n6365),
.Y(n2123) );
AO22X1TS U3116 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n6469), .B0(
FPSENCOS_d_ff_Yn[18]), .B1(n6454), .Y(n1871) );
AO22X1TS U3117 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[5]), .B1(n6447), .Y(n1897) );
AO22X1TS U3118 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[7]), .B1(n6447), .Y(n1893) );
AO22X1TS U3119 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n4748), .B0(
FPSENCOS_d_ff_Yn[3]), .B1(n6447), .Y(n1901) );
AO22X1TS U3120 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n6431), .B0(
FPSENCOS_d_ff_Yn[19]), .B1(n6454), .Y(n1869) );
AO22X1TS U3121 ( .A0(FPSENCOS_d_ff2_Y[31]), .A1(n6469), .B0(n6468), .B1(
FPSENCOS_d_ff_Yn[31]), .Y(n1845) );
AO22X1TS U3122 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n6430), .B0(
FPSENCOS_d_ff_Yn[20]), .B1(n6468), .Y(n1867) );
AO22X1TS U3123 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[14]), .B1(n6454), .Y(n1879) );
OR2X2TS U3124 ( .A(n5197), .B(n5196), .Y(n5555) );
AO22X1TS U3125 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[11]), .B1(n6447), .Y(n1885) );
AO22X1TS U3126 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n6430), .B0(
FPSENCOS_d_ff_Yn[16]), .B1(n6447), .Y(n1875) );
AO22X1TS U3127 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[13]), .B1(n6454), .Y(n1881) );
AO22X1TS U3128 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n6453), .B0(
FPSENCOS_d_ff_Yn[24]), .B1(n6468), .Y(n1860) );
AO22X1TS U3129 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n6431), .B0(
FPSENCOS_d_ff_Yn[25]), .B1(n6454), .Y(n1859) );
AO22X1TS U3130 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n6453), .B0(
FPSENCOS_d_ff_Yn[26]), .B1(n6454), .Y(n1858) );
OAI211X1TS U3131 ( .A0(n4651), .A1(n2400), .B0(n4650), .C0(n4649), .Y(n1527)
);
OAI211X1TS U3132 ( .A0(n2361), .A1(n6886), .B0(n4601), .C0(n4600), .Y(n1516)
);
AO22X1TS U3133 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n2302), .B0(
FPSENCOS_d_ff_Yn[30]), .B1(n6454), .Y(n1854) );
AO22X1TS U3134 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n6431), .B0(
FPSENCOS_d_ff_Yn[27]), .B1(n6454), .Y(n1857) );
AO22X1TS U3135 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n6431), .B0(
FPSENCOS_d_ff_Yn[29]), .B1(n6454), .Y(n1855) );
OAI211X1TS U3136 ( .A0(n2362), .A1(n6897), .B0(n4640), .C0(n4639), .Y(n1505)
);
OAI21X1TS U3137 ( .A0(n4758), .A1(n5238), .B0(n4756), .Y(n2076) );
OAI21X1TS U3138 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[6]), .A1(n4816), .B0(n5213),
.Y(n4817) );
OAI21X1TS U3139 ( .A0(n4758), .A1(n7059), .B0(n4757), .Y(n1322) );
AO22X1TS U3140 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n6453), .B0(
FPSENCOS_d_ff_Yn[1]), .B1(n6452), .Y(n1905) );
OAI211X1TS U3141 ( .A0(n6449), .A1(n6902), .B0(n4987), .C0(n4980), .Y(n2126)
);
INVX6TS U3142 ( .A(n3638), .Y(n3697) );
AO22X1TS U3143 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[8]), .B1(n6452), .Y(n1891) );
AO22X1TS U3144 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n6469), .B0(
FPSENCOS_d_ff_Yn[0]), .B1(n6452), .Y(n1907) );
AO22X1TS U3145 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[6]), .B1(n6452), .Y(n1895) );
INVX6TS U3146 ( .A(n3665), .Y(n3698) );
AO22X1TS U3147 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n4748), .B0(
FPSENCOS_d_ff_Yn[4]), .B1(n6452), .Y(n1899) );
OAI211X1TS U3148 ( .A0(n6362), .A1(n6371), .B0(n4761), .C0(n4760), .Y(n2127)
);
OR2X2TS U3149 ( .A(n5154), .B(n5153), .Y(n5484) );
NAND2BX1TS U3150 ( .AN(n3900), .B(n2395), .Y(n3870) );
AOI222X1TS U3151 ( .A0(n4748), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n6427), .B1(
FPSENCOS_d_ff_Zn[31]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[31]), .Y(n4932) );
XNOR2X1TS U3152 ( .A(n3951), .B(n2395), .Y(n3932) );
OAI21X1TS U3153 ( .A0(n6461), .A1(n6841), .B0(n6463), .Y(n6462) );
AOI211X1TS U3154 ( .A0(n4642), .A1(n6898), .B0(n4587), .C0(n4586), .Y(n1621)
);
OAI21X1TS U3155 ( .A0(n4861), .A1(n5723), .B0(n5725), .Y(n4862) );
OAI211X1TS U3156 ( .A0(n6449), .A1(n6900), .B0(n4823), .C0(n6363), .Y(n2132)
);
AO22X1TS U3157 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n4731), .B0(
FPSENCOS_d_ff_Yn[23]), .B1(n6452), .Y(n1861) );
OAI211X1TS U3158 ( .A0(n6448), .A1(n6901), .B0(n4823), .C0(n4989), .Y(n2130)
);
OAI21X1TS U3159 ( .A0(n6371), .A1(n6367), .B0(n4750), .Y(n2116) );
NOR2X4TS U3160 ( .A(n4998), .B(n6345), .Y(n4999) );
NOR2X1TS U3161 ( .A(n6664), .B(n6663), .Y(n6665) );
NOR2X1TS U3162 ( .A(n6664), .B(n6636), .Y(n6637) );
OAI21X1TS U3163 ( .A0(n4759), .A1(n6362), .B0(n4752), .Y(n2129) );
NOR2X1TS U3164 ( .A(n6664), .B(n6639), .Y(n6640) );
XNOR2X1TS U3165 ( .A(n3951), .B(n2205), .Y(n3883) );
NOR2X1TS U3166 ( .A(n6664), .B(n6642), .Y(n6643) );
NOR2X1TS U3167 ( .A(n6664), .B(n6628), .Y(n6630) );
NOR2X1TS U3168 ( .A(n6727), .B(n6718), .Y(n6719) );
NOR2X1TS U3169 ( .A(n6664), .B(n6645), .Y(n6646) );
NOR2X1TS U3170 ( .A(n6727), .B(n6720), .Y(n6721) );
NOR2X1TS U3171 ( .A(n6727), .B(n6723), .Y(n6724) );
OAI21X1TS U3172 ( .A0(n4967), .A1(n4966), .B0(n4965), .Y(mult_x_309_n22) );
AOI2BB2X1TS U3173 ( .B0(n5987), .B1(n6006), .A0N(n6014), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n1196) );
AOI2BB2X1TS U3174 ( .B0(n5991), .B1(n6006), .A0N(n6009), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n1199) );
NOR2X1TS U3175 ( .A(n5720), .B(n5721), .Y(n5697) );
AO22X1TS U3176 ( .A0(FPSENCOS_d_ff3_LUT_out[25]), .A1(n6428), .B0(n6375),
.B1(n6374), .Y(n2115) );
OAI21X1TS U3177 ( .A0(n4915), .A1(n5766), .B0(n5767), .Y(n4916) );
OAI21X1TS U3178 ( .A0(n5763), .A1(n4928), .B0(n5761), .Y(n4929) );
ADDHX2TS U3179 ( .A(n3664), .B(n2307), .CO(n3638), .S(n3665) );
NOR2X1TS U3180 ( .A(n5823), .B(n5824), .Y(n5802) );
AO22X1TS U3181 ( .A0(n6448), .A1(FPSENCOS_d_ff2_Y[18]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1870) );
NAND3X1TS U3182 ( .A(n6384), .B(n6338), .C(n6348), .Y(n6340) );
AO22X1TS U3183 ( .A0(n4554), .A1(FPSENCOS_d_ff2_Y[3]), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1900) );
NOR2X1TS U3184 ( .A(n6664), .B(n6632), .Y(n6633) );
OAI21X1TS U3185 ( .A0(n6360), .A1(n6756), .B0(FPSENCOS_cont_var_out[1]), .Y(
n4553) );
AO22X1TS U3186 ( .A0(n6464), .A1(FPSENCOS_d_ff2_Y[14]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1878) );
NOR2X1TS U3187 ( .A(n6664), .B(n6653), .Y(n6654) );
AO22X1TS U3188 ( .A0(n6464), .A1(FPSENCOS_d_ff2_Y[20]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1866) );
OAI21X1TS U3189 ( .A0(n5815), .A1(n5812), .B0(n5813), .Y(n4790) );
AO22X1TS U3190 ( .A0(n6448), .A1(FPSENCOS_d_ff2_Y[17]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1872) );
AO22X1TS U3191 ( .A0(n4554), .A1(FPSENCOS_d_ff2_Y[7]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1892) );
AO22X1TS U3192 ( .A0(n2357), .A1(n5956), .B0(n5960), .B1(n5955), .Y(n6648)
);
CLKINVX2TS U3193 ( .A(n4590), .Y(n4646) );
AO22X1TS U3194 ( .A0(n6464), .A1(FPSENCOS_d_ff2_Y[16]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1874) );
AO22X1TS U3195 ( .A0(n6471), .A1(FPSENCOS_d_ff2_Y[19]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1868) );
AO22X1TS U3196 ( .A0(n6471), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n6470), .B1(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1844) );
NAND2BX1TS U3197 ( .AN(n6358), .B(n6348), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
INVX3TS U3198 ( .A(n3514), .Y(n3515) );
AO22X1TS U3199 ( .A0(n6464), .A1(FPSENCOS_d_ff2_Y[13]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1880) );
AO22X1TS U3200 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n6612), .B0(
mult_result[3]), .B1(n6614), .Y(n1501) );
AO22X1TS U3201 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n6612), .B0(
mult_result[4]), .B1(n6614), .Y(n1500) );
AO22X1TS U3202 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n6612), .B0(
mult_result[5]), .B1(n6614), .Y(n1499) );
AO22X1TS U3203 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n6616), .B0(
mult_result[6]), .B1(n6614), .Y(n1498) );
AO22X1TS U3204 ( .A0(n6471), .A1(intadd_518_SUM_0_), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_x_out[24]), .Y(n1950) );
AO22X1TS U3205 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n6616), .B0(
mult_result[7]), .B1(n6614), .Y(n1497) );
AO22X1TS U3206 ( .A0(n6438), .A1(FPSENCOS_d_ff2_Y[11]), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1884) );
AO22X1TS U3207 ( .A0(n6471), .A1(n4556), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_x_out[23]), .Y(n1951) );
AOI2BB2X1TS U3208 ( .B0(n5988), .B1(n6006), .A0N(n6009), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n1197) );
AO22X1TS U3209 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n6616), .B0(
mult_result[8]), .B1(n6618), .Y(n1496) );
AO22X1TS U3210 ( .A0(n6471), .A1(FPSENCOS_d_ff2_Y[22]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1862) );
AO22X1TS U3211 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n6616), .B0(
mult_result[9]), .B1(n6618), .Y(n1495) );
AO22X1TS U3212 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n6616), .B0(
mult_result[10]), .B1(n6618), .Y(n1494) );
AO22X1TS U3213 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n6616), .B0(
mult_result[11]), .B1(n6618), .Y(n1493) );
AO22X1TS U3214 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n6616), .B0(
mult_result[12]), .B1(n6618), .Y(n1492) );
AO22X1TS U3215 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n6616), .B0(
mult_result[13]), .B1(n6618), .Y(n1491) );
AO22X1TS U3216 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n6616), .B0(
mult_result[14]), .B1(n6618), .Y(n1490) );
AO22X1TS U3217 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n6616), .B0(
mult_result[15]), .B1(n6618), .Y(n1489) );
NOR2X1TS U3218 ( .A(n2306), .B(n5609), .Y(n5191) );
AO22X1TS U3219 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n6619), .B0(
mult_result[16]), .B1(n6618), .Y(n1488) );
AO22X1TS U3220 ( .A0(n2357), .A1(n5961), .B0(n5960), .B1(n5959), .Y(n6663)
);
AO22X1TS U3221 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n6619), .B0(
mult_result[17]), .B1(n6617), .Y(n1487) );
AO22X1TS U3222 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n6619), .B0(
mult_result[18]), .B1(n6617), .Y(n1486) );
OAI21X1TS U3223 ( .A0(n5658), .A1(n5655), .B0(n5656), .Y(n4977) );
AO22X1TS U3224 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n6619), .B0(
mult_result[19]), .B1(n6617), .Y(n1485) );
AO22X1TS U3225 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n6619), .B0(
mult_result[22]), .B1(n6618), .Y(n1481) );
NOR2X1TS U3226 ( .A(n6005), .B(n6004), .Y(n6011) );
AO22X1TS U3227 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n6619), .B0(
mult_result[20]), .B1(n6617), .Y(n1484) );
AO22X1TS U3228 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n6619), .B0(
mult_result[21]), .B1(n6617), .Y(n1483) );
OAI21X1TS U3229 ( .A0(n5668), .A1(n4952), .B0(n5669), .Y(n4953) );
AO22X1TS U3230 ( .A0(n6438), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n6544), .B1(
FPSENCOS_d_ff3_sign_out), .Y(n1732) );
AO22X1TS U3231 ( .A0(n6619), .A1(FPMULT_Sgf_normalized_result[2]), .B0(
mult_result[2]), .B1(n6617), .Y(n1502) );
AO22X1TS U3232 ( .A0(n6471), .A1(intadd_518_SUM_2_), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_x_out[26]), .Y(n1948) );
AO22X1TS U3233 ( .A0(n6619), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
mult_result[0]), .B1(n6617), .Y(n1504) );
AO22X1TS U3234 ( .A0(n6471), .A1(intadd_518_SUM_1_), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_x_out[25]), .Y(n1949) );
AO22X1TS U3235 ( .A0(n6464), .A1(FPSENCOS_d_ff2_Y[15]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1876) );
AO22X1TS U3236 ( .A0(n6464), .A1(n6370), .B0(n6428), .B1(
FPSENCOS_d_ff3_LUT_out[23]), .Y(n2117) );
NOR2X1TS U3237 ( .A(n6727), .B(n6726), .Y(n6729) );
NAND4BX1TS U3238 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n3297), .C(n3296),
.D(n3295), .Y(n3298) );
AO22X1TS U3239 ( .A0(n6449), .A1(FPSENCOS_d_ff2_Y[5]), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1896) );
AO22X1TS U3240 ( .A0(n6619), .A1(FPMULT_Sgf_normalized_result[1]), .B0(
mult_result[1]), .B1(n6617), .Y(n1503) );
AO22X1TS U3241 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n6379), .B1(
Data_1[0]), .Y(n2112) );
NOR2X1TS U3242 ( .A(n4583), .B(n4582), .Y(n1692) );
OAI21X1TS U3243 ( .A0(n5732), .A1(n5731), .B0(n5733), .Y(n4838) );
AO22X1TS U3244 ( .A0(n6005), .A1(n5958), .B0(n5960), .B1(n5957), .Y(n6632)
);
INVX2TS U3245 ( .A(n5637), .Y(n2349) );
AND3X2TS U3246 ( .A(n5329), .B(n5328), .C(n5327), .Y(n5382) );
NOR2X1TS U3247 ( .A(n2304), .B(n5537), .Y(n5147) );
NAND2BX1TS U3248 ( .AN(n3900), .B(n2205), .Y(n3902) );
AO22X1TS U3249 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n6377), .B1(
Data_1[10]), .Y(n2102) );
AO22X1TS U3250 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n6383), .B1(
Data_1[25]), .Y(n2087) );
AO22X1TS U3251 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n6377), .B1(
Data_1[9]), .Y(n2103) );
AO22X1TS U3252 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n6383), .B1(
Data_1[24]), .Y(n2088) );
AO22X1TS U3253 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n6377), .B1(
Data_1[8]), .Y(n2104) );
OAI222X1TS U3254 ( .A0(n2336), .A1(FPADDSUB_Raw_mant_NRM_SWR[12]), .B0(n5450), .B1(FPADDSUB_Raw_mant_NRM_SWR[13]), .C0(FPADDSUB_DmP_mant_SHT1_SW[11]), .C1(
n6713), .Y(n5282) );
NAND3X1TS U3255 ( .A(n5248), .B(n5247), .C(n5246), .Y(n5261) );
AO22X1TS U3256 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n6377), .B1(
Data_1[11]), .Y(n2101) );
OAI21X1TS U3257 ( .A0(n4898), .A1(n4897), .B0(n4896), .Y(n4899) );
AND3X2TS U3258 ( .A(n5254), .B(n5253), .C(n5252), .Y(n5355) );
AO22X1TS U3259 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n6377), .B1(
Data_1[12]), .Y(n2100) );
AO22X1TS U3260 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n6377), .B1(
Data_1[7]), .Y(n2105) );
AO22X1TS U3261 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n6377), .B1(
Data_1[6]), .Y(n2106) );
AO22X1TS U3262 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n6383), .B1(
Data_1[31]), .Y(n2081) );
AO22X1TS U3263 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n6383), .B1(
Data_1[16]), .Y(n2096) );
AO22X1TS U3264 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n6377), .B1(
Data_1[5]), .Y(n2107) );
AO22X1TS U3265 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n6377), .B1(
Data_1[13]), .Y(n2099) );
AO22X1TS U3266 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n6377), .B1(
Data_1[14]), .Y(n2098) );
AO22X1TS U3267 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n6383), .B1(
Data_1[29]), .Y(n2083) );
AO22X1TS U3268 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n6383), .B1(
Data_1[28]), .Y(n2084) );
NAND3X1TS U3269 ( .A(n5318), .B(n5317), .C(n5316), .Y(n5370) );
NOR2X1TS U3270 ( .A(n2357), .B(n4469), .Y(n4472) );
AO22X1TS U3271 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n6382), .B1(
Data_1[27]), .Y(n2085) );
OAI21X1TS U3272 ( .A0(n4920), .A1(n4919), .B0(n4918), .Y(n4921) );
AO22X1TS U3273 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n6383), .B1(
Data_1[26]), .Y(n2086) );
AO22X1TS U3274 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n6383), .B1(
Data_1[30]), .Y(n2082) );
AND3X2TS U3275 ( .A(n5203), .B(n5202), .C(n5201), .Y(n5393) );
AND2X2TS U3276 ( .A(n4908), .B(n4906), .Y(n5762) );
AO22X1TS U3277 ( .A0(n6376), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n6379), .B1(
Data_1[4]), .Y(n2108) );
AO22X1TS U3278 ( .A0(n6376), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n6379), .B1(
Data_1[1]), .Y(n2111) );
OAI21X1TS U3279 ( .A0(n6610), .A1(underflow_flag_mult), .B0(n6609), .Y(n6611) );
AO22X1TS U3280 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n6380), .B1(
Data_1[21]), .Y(n2091) );
AO22X1TS U3281 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n6380), .B1(
Data_1[19]), .Y(n2093) );
NOR2X1TS U3282 ( .A(n5608), .B(n2344), .Y(n4354) );
AO22X1TS U3283 ( .A0(n6376), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n6379), .B1(
Data_1[3]), .Y(n2109) );
AO22X1TS U3284 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n6380), .B1(
Data_1[20]), .Y(n2092) );
AO22X1TS U3285 ( .A0(n6376), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n6379), .B1(
Data_1[2]), .Y(n2110) );
INVX2TS U3286 ( .A(n6415), .Y(n6431) );
NOR2X1TS U3287 ( .A(n5180), .B(n5622), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0) );
AO22X1TS U3288 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n6380), .B1(
Data_1[23]), .Y(n2089) );
AO22X1TS U3289 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n6379), .B1(
Data_1[22]), .Y(n2090) );
AO22X1TS U3290 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n6380), .B1(
Data_1[17]), .Y(n2095) );
INVX2TS U3291 ( .A(n6415), .Y(n4731) );
OAI21X1TS U3292 ( .A0(n6108), .A1(n6107), .B0(n6106), .Y(n6110) );
OAI21X1TS U3293 ( .A0(n6108), .A1(n6035), .B0(n6053), .Y(n6037) );
INVX3TS U3294 ( .A(n6444), .Y(n6456) );
NAND3X1TS U3295 ( .A(n4940), .B(n5675), .C(n4939), .Y(n5679) );
OAI21X1TS U3296 ( .A0(n5700), .A1(n5699), .B0(n5698), .Y(n5701) );
XOR2X1TS U3297 ( .A(n4036), .B(n4038), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]) );
OAI21X1TS U3298 ( .A0(n6205), .A1(n6199), .B0(n6200), .Y(n6190) );
AOI31X1TS U3299 ( .A0(n6787), .A1(n4550), .A2(n5451), .B0(
FPMULT_FSM_selector_C), .Y(n4551) );
OR2X2TS U3300 ( .A(n3896), .B(n3444), .Y(n2247) );
NOR2X4TS U3301 ( .A(n6260), .B(n6020), .Y(n5933) );
BUFX3TS U3302 ( .A(n5238), .Y(n2336) );
OAI21X1TS U3303 ( .A0(n5754), .A1(n5781), .B0(n5756), .Y(n5753) );
OAI21X1TS U3304 ( .A0(n5805), .A1(n5804), .B0(n5803), .Y(n5806) );
OR2X2TS U3305 ( .A(n5443), .B(n4961), .Y(n4962) );
NAND3BX1TS U3306 ( .AN(n4430), .B(n4429), .C(n4427), .Y(n4428) );
INVX2TS U3307 ( .A(n5637), .Y(n6606) );
INVX2TS U3308 ( .A(n5637), .Y(n5641) );
XOR2X2TS U3309 ( .A(n4346), .B(n4345), .Y(n4347) );
INVX2TS U3310 ( .A(n5637), .Y(n5639) );
INVX2TS U3311 ( .A(n5637), .Y(n5934) );
XNOR2X2TS U3312 ( .A(n3646), .B(n2346), .Y(n3648) );
OAI21X1TS U3313 ( .A0(n4685), .A1(n6650), .B0(n4705), .Y(op_result[17]) );
OAI21X1TS U3314 ( .A0(n4670), .A1(n6655), .B0(n4704), .Y(op_result[16]) );
OAI21X1TS U3315 ( .A0(n4668), .A1(n6652), .B0(n4706), .Y(op_result[13]) );
OAI21X1TS U3316 ( .A0(n4710), .A1(n6830), .B0(n4709), .Y(op_result[14]) );
OAI21X1TS U3317 ( .A0(n4668), .A1(n6638), .B0(n4701), .Y(op_result[18]) );
OAI21X1TS U3318 ( .A0(n4710), .A1(n6634), .B0(n4703), .Y(op_result[15]) );
OAI21X1TS U3319 ( .A0(n4670), .A1(n6641), .B0(n4699), .Y(op_result[21]) );
OAI21X1TS U3320 ( .A0(n4685), .A1(n6647), .B0(n4700), .Y(op_result[20]) );
NOR2X1TS U3321 ( .A(n4905), .B(n4907), .Y(n4904) );
AO22XLTS U3322 ( .A0(n6744), .A1(FPADDSUB_DmP_EXP_EWSW[11]), .B0(n6743),
.B1(FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1370) );
NOR2X1TS U3323 ( .A(n5651), .B(n4935), .Y(intadd_515_B_0_) );
NOR2X1TS U3324 ( .A(n4973), .B(n4948), .Y(n4949) );
CLKBUFX3TS U3325 ( .A(n4488), .Y(n4494) );
NAND2X2TS U3326 ( .A(n4344), .B(n4343), .Y(n4346) );
AND2X2TS U3327 ( .A(n4341), .B(n4345), .Y(n4348) );
AND2X2TS U3328 ( .A(n4584), .B(FPMULT_FS_Module_state_reg[1]), .Y(n4588) );
INVX2TS U3329 ( .A(n5478), .Y(n6957) );
OAI211X2TS U3330 ( .A0(n2504), .A1(n4280), .B0(n4279), .C0(n5967), .Y(n5957)
);
NAND2X4TS U3331 ( .A(n2822), .B(n2826), .Y(n2856) );
OAI211X2TS U3332 ( .A0(n6816), .A1(n4280), .B0(n4275), .C0(n5967), .Y(n5959)
);
NAND2BX1TS U3333 ( .AN(FPSENCOS_d_ff2_Y[23]), .B(n6455), .Y(intadd_517_CI)
);
NOR2X1TS U3334 ( .A(n4572), .B(n5549), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0) );
AND2X2TS U3335 ( .A(n2317), .B(FPADDSUB_OP_FLAG_SFG), .Y(n6024) );
NOR2X4TS U3336 ( .A(n6232), .B(FPADDSUB_OP_FLAG_SFG), .Y(n4499) );
NAND2BX1TS U3337 ( .AN(n4579), .B(n1694), .Y(n4576) );
NAND2XLTS U3338 ( .A(n5273), .B(n6796), .Y(n5276) );
INVX2TS U3339 ( .A(n3748), .Y(n3749) );
NAND2BX1TS U3340 ( .AN(n5847), .B(n5846), .Y(n5849) );
NAND2BX1TS U3341 ( .AN(n6566), .B(n6565), .Y(n1690) );
OAI21X1TS U3342 ( .A0(n1694), .A1(n4579), .B0(n5455), .Y(n4580) );
NOR2X1TS U3343 ( .A(n4831), .B(n4832), .Y(n4836) );
NAND2BX1TS U3344 ( .AN(n5744), .B(n5743), .Y(n5746) );
OAI21XLTS U3345 ( .A0(n4670), .A1(n6540), .B0(n4678), .Y(op_result[29]) );
OAI21XLTS U3346 ( .A0(n4668), .A1(n6537), .B0(n4680), .Y(op_result[28]) );
OAI21XLTS U3347 ( .A0(n4668), .A1(n6526), .B0(n4657), .Y(op_result[24]) );
OAI21XLTS U3348 ( .A0(n4670), .A1(n6533), .B0(n4682), .Y(op_result[27]) );
OAI21XLTS U3349 ( .A0(n4668), .A1(n6530), .B0(n4676), .Y(op_result[26]) );
OAI21XLTS U3350 ( .A0(n4685), .A1(n6527), .B0(n4679), .Y(op_result[25]) );
OAI21XLTS U3351 ( .A0(n4710), .A1(n6631), .B0(n4677), .Y(op_result[22]) );
OAI21XLTS U3352 ( .A0(n4685), .A1(n6554), .B0(n4675), .Y(op_result[31]) );
OAI21XLTS U3353 ( .A0(n4685), .A1(n2451), .B0(n4684), .Y(op_result[30]) );
OAI21XLTS U3354 ( .A0(n4710), .A1(n6524), .B0(n4681), .Y(op_result[23]) );
OAI21XLTS U3355 ( .A0(n4670), .A1(n2367), .B0(n4669), .Y(op_result[0]) );
OAI21XLTS U3356 ( .A0(n4710), .A1(n6835), .B0(n4665), .Y(op_result[1]) );
OAI21XLTS U3357 ( .A0(n4668), .A1(n6834), .B0(n4664), .Y(op_result[2]) );
OAI21XLTS U3358 ( .A0(n4685), .A1(n6833), .B0(n4667), .Y(op_result[3]) );
OAI21XLTS U3359 ( .A0(n4710), .A1(n2280), .B0(n4663), .Y(op_result[4]) );
OAI21XLTS U3360 ( .A0(n4710), .A1(n6836), .B0(n4655), .Y(op_result[5]) );
OAI21XLTS U3361 ( .A0(n4668), .A1(n6659), .B0(n4659), .Y(op_result[8]) );
OAI21XLTS U3362 ( .A0(n4685), .A1(n6831), .B0(n4658), .Y(op_result[10]) );
OAI21XLTS U3363 ( .A0(n4670), .A1(n6837), .B0(n4652), .Y(op_result[9]) );
OAI21XLTS U3364 ( .A0(n4685), .A1(n6839), .B0(n4653), .Y(op_result[6]) );
OAI21XLTS U3365 ( .A0(n4668), .A1(n6840), .B0(n4654), .Y(op_result[7]) );
OAI21XLTS U3366 ( .A0(n4670), .A1(n6662), .B0(n4656), .Y(op_result[11]) );
INVX2TS U3367 ( .A(n2316), .Y(n2317) );
OAI21X1TS U3368 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n6012), .Y(n6335) );
OR2X4TS U3369 ( .A(n6623), .B(n6713), .Y(n5265) );
OAI211X1TS U3370 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n2442), .B0(n2535), .C0(
n2538), .Y(n2549) );
OR2X2TS U3371 ( .A(n3817), .B(n3815), .Y(n2402) );
NAND3X1TS U3372 ( .A(n6364), .B(n6768), .C(intadd_517_B_1_), .Y(n4711) );
INVX1TS U3373 ( .A(n5452), .Y(n4550) );
NOR2X1TS U3374 ( .A(n5905), .B(FPMULT_Sgf_normalized_result[2]), .Y(n5906)
);
OAI21X1TS U3375 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n4545), .Y(n4546) );
NAND3X1TS U3376 ( .A(n5735), .B(FPMULT_Op_MY[14]), .C(FPMULT_Op_MX[13]), .Y(
n5741) );
OAI21X2TS U3377 ( .A0(n3365), .A1(n3371), .B0(n3366), .Y(n4437) );
NAND2X2TS U3378 ( .A(n2218), .B(n2251), .Y(n3435) );
ADDFHX2TS U3379 ( .A(DP_OP_501J223_127_5235_n944), .B(n2292), .CI(n3533),
.CO(n3632), .S(n3677) );
NAND2BX1TS U3380 ( .AN(n4924), .B(intadd_513_A_7_), .Y(n4427) );
NOR2X4TS U3381 ( .A(n4044), .B(n4043), .Y(n4149) );
NOR2X1TS U3382 ( .A(n4769), .B(n4770), .Y(n4774) );
OAI21X1TS U3383 ( .A0(n6181), .A1(n6200), .B0(n6182), .Y(n4257) );
BUFX3TS U3384 ( .A(n6656), .Y(n6738) );
NOR2X1TS U3385 ( .A(n2533), .B(FPADDSUB_intDY_EWSW[10]), .Y(n2534) );
NAND3X1TS U3386 ( .A(n2442), .B(n2535), .C(FPADDSUB_intDX_EWSW[8]), .Y(n2536) );
OAI211X2TS U3387 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n2455), .B0(n2545),
.C0(n2531), .Y(n2547) );
OAI211X2TS U3388 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n2459), .B0(n2515),
.C0(n2506), .Y(n2551) );
AOI211X1TS U3389 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n2568), .B0(n2570),
.C0(n2567), .Y(n2572) );
NOR2X1TS U3390 ( .A(n2560), .B(FPADDSUB_intDY_EWSW[24]), .Y(n2561) );
NAND3X1TS U3391 ( .A(n2423), .B(n2562), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n2564) );
NAND2X2TS U3392 ( .A(n4574), .B(n6757), .Y(n5452) );
ADDFHX2TS U3393 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[2]), .B(
n4042), .CI(n4041), .CO(n4045), .S(n4044) );
NOR2X1TS U3394 ( .A(n5851), .B(n5891), .Y(n5852) );
NOR2X1TS U3395 ( .A(n5851), .B(n6792), .Y(n5853) );
OR2X2TS U3396 ( .A(n4160), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]), .Y(
n4161) );
NOR2X1TS U3397 ( .A(n2292), .B(n2228), .Y(n4248) );
NAND3X1TS U3398 ( .A(n5453), .B(n6757), .C(n6787), .Y(n5456) );
AND2X2TS U3399 ( .A(n3372), .B(n3371), .Y(n3375) );
ADDFHX2TS U3400 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[9]), .B(
n4099), .CI(n4098), .CO(n4100), .S(n4095) );
NAND3X1TS U3401 ( .A(n6318), .B(n6317), .C(n6316), .Y(n6918) );
NAND2BX1TS U3402 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n2535) );
OR2X2TS U3403 ( .A(n2481), .B(FPMULT_Op_MX[13]), .Y(n2246) );
OAI21X1TS U3404 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n2461), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n2541) );
NAND2BX1TS U3405 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n2531) );
NAND2BX1TS U3406 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n2508) );
OR2X2TS U3407 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[2]), .Y(n2454) );
NAND2BX1TS U3408 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n2506) );
NAND2BX1TS U3409 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n2562) );
INVX2TS U3410 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(n2671) );
NAND2BX1TS U3411 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n2563) );
NAND2BX1TS U3412 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n2559) );
INVX3TS U3413 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .Y(n4040)
);
CLKINVX2TS U3414 ( .A(result_add_subt[24]), .Y(n6526) );
CLKINVX2TS U3415 ( .A(result_add_subt[29]), .Y(n6540) );
OR2X2TS U3416 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n5221) );
CLKINVX2TS U3417 ( .A(result_add_subt[26]), .Y(n6530) );
CLKINVX2TS U3418 ( .A(result_add_subt[28]), .Y(n6537) );
CLKINVX2TS U3419 ( .A(result_add_subt[27]), .Y(n6533) );
NOR2X1TS U3420 ( .A(n6762), .B(n6845), .Y(FPMULT_S_Oper_A_exp[8]) );
INVX1TS U3421 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n6558) );
CLKINVX2TS U3422 ( .A(FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n6013) );
OAI21X1TS U3423 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n2438), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n2511) );
OAI21X1TS U3424 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n2448), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n2505) );
NAND3X1TS U3425 ( .A(n4242), .B(n4241), .C(n4240), .Y(n4243) );
INVX4TS U3426 ( .A(operation[2]), .Y(n6350) );
INVX2TS U3427 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(n3119) );
INVX6TS U3428 ( .A(n2208), .Y(n2207) );
INVX6TS U3429 ( .A(n2843), .Y(n2931) );
AOI21X4TS U3430 ( .A0(n3267), .A1(n3221), .B0(n3220), .Y(n3228) );
INVX4TS U3431 ( .A(n6545), .Y(n4998) );
AOI21X2TS U3432 ( .A0(n2757), .A1(n3051), .B0(n2756), .Y(n2760) );
OR2X2TS U3433 ( .A(n3646), .B(n2403), .Y(n3659) );
INVX2TS U3434 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .Y(n2650) );
ADDFHX4TS U3435 ( .A(n2651), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[6]), .CI(
n2650), .CO(n2652), .S(n2607) );
OAI21X4TS U3436 ( .A0(n2922), .A1(n2918), .B0(n2919), .Y(n2940) );
OAI21X4TS U3437 ( .A0(n2731), .A1(n2734), .B0(n2732), .Y(n4223) );
AOI21X2TS U3438 ( .A0(n2997), .A1(n2996), .B0(n2995), .Y(n3001) );
AOI21X2TS U3439 ( .A0(n3017), .A1(n3016), .B0(n3011), .Y(n3014) );
NOR2X2TS U3440 ( .A(n4889), .B(n4869), .Y(n4871) );
OAI21X1TS U3441 ( .A0(n4139), .A1(n4116), .B0(n4119), .Y(n4115) );
INVX6TS U3442 ( .A(n4122), .Y(n4139) );
XOR2X1TS U3443 ( .A(n5573), .B(n5572), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9) );
OAI21X1TS U3444 ( .A0(n5710), .A1(n5707), .B0(n5708), .Y(n4852) );
NOR2X4TS U3445 ( .A(n6342), .B(n5015), .Y(n6545) );
NAND2X2TS U3446 ( .A(n5550), .B(n5555), .Y(n5200) );
ADDFX2TS U3447 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6]), .B(
n4073), .CI(n4072), .CO(n4074), .S(n4071) );
NOR2X2TS U3448 ( .A(n4167), .B(n4081), .Y(n4083) );
NOR2X4TS U3449 ( .A(n2584), .B(n2703), .Y(n2614) );
OAI21X1TS U3450 ( .A0(n4455), .A1(n4454), .B0(n4453), .Y(n4456) );
NOR2X8TS U3451 ( .A(n4454), .B(n4459), .Y(n3072) );
NAND2X4TS U3452 ( .A(n2819), .B(n2818), .Y(n2823) );
NAND2X4TS U3453 ( .A(n2783), .B(n2782), .Y(n2800) );
NOR2X6TS U3454 ( .A(n3157), .B(n3156), .Y(n3166) );
NOR2X6TS U3455 ( .A(n2762), .B(n3052), .Y(n2764) );
NOR2X8TS U3456 ( .A(n2837), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .Y(n2928)
);
OA21X4TS U3457 ( .A0(n2859), .A1(n2858), .B0(n2857), .Y(n2860) );
OR2X6TS U3458 ( .A(n2855), .B(n2859), .Y(n2861) );
NAND2X4TS U3459 ( .A(n4943), .B(n4942), .Y(n5442) );
OAI21X2TS U3460 ( .A0(n6166), .A1(n4411), .B0(n4410), .Y(n6146) );
INVX4TS U3461 ( .A(n3282), .Y(n4421) );
NAND2X4TS U3462 ( .A(n2470), .B(n3016), .Y(n2751) );
OR2X4TS U3463 ( .A(DP_OP_499J223_125_1651_n237), .B(
DP_OP_499J223_125_1651_n239), .Y(n3016) );
XOR2X1TS U3464 ( .A(n3992), .B(n3991), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10) );
NAND2BX4TS U3465 ( .AN(n4806), .B(n4755), .Y(n4690) );
NOR2X4TS U3466 ( .A(FPADDSUB_Raw_mant_NRM_SWR[11]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .Y(n5208) );
OAI21X1TS U3467 ( .A0(n5583), .A1(n5580), .B0(n5581), .Y(n5579) );
AND2X4TS U3468 ( .A(n6017), .B(n5143), .Y(n6629) );
XNOR2X2TS U3469 ( .A(n4078), .B(n4077), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]) );
ADDFHX2TS U3470 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[8]), .B(
n2817), .CI(n2816), .CO(n2818), .S(n2674) );
CMPR42X4TS U3471 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]), .C(
DP_OP_499J223_125_1651_n247), .D(DP_OP_499J223_125_1651_n280), .ICI(
DP_OP_499J223_125_1651_n304), .S(DP_OP_499J223_125_1651_n246), .ICO(
DP_OP_499J223_125_1651_n244), .CO(DP_OP_499J223_125_1651_n245) );
ADDFHX4TS U3472 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[4]), .B(
n2596), .CI(n2595), .CO(n2597), .S(n2593) );
NOR2X4TS U3473 ( .A(n2598), .B(n2597), .Y(n2604) );
NOR2X8TS U3474 ( .A(n3070), .B(n4208), .Y(n4459) );
ADDFHX4TS U3475 ( .A(n3085), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]), .CI(
n2716), .CO(n3087), .S(n2798) );
XNOR2X4TS U3476 ( .A(n3577), .B(n3576), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12) );
AOI21X2TS U3477 ( .A0(n3452), .A1(n2251), .B0(n3451), .Y(n3455) );
AOI21X4TS U3478 ( .A0(n2444), .A1(n3442), .B0(n3432), .Y(n3446) );
INVX6TS U3479 ( .A(n3658), .Y(n2335) );
ADDFHX4TS U3480 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5]), .B(
n2605), .CI(n2715), .CO(n2606), .S(n2598) );
NAND2X6TS U3481 ( .A(n2657), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .Y(n2889)
);
INVX2TS U3482 ( .A(n4452), .Y(n4455) );
OAI211X1TS U3483 ( .A0(n5380), .A1(n5237), .B0(n5345), .C0(n5344), .Y(n1790)
);
OAI21X1TS U3484 ( .A0(n3265), .A1(n3257), .B0(n3260), .Y(n3220) );
NOR2X4TS U3485 ( .A(n3203), .B(n3202), .Y(n3257) );
ADDFHX2TS U3486 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10]), .B(
n3223), .CI(n3222), .CO(n3224), .S(n3203) );
OAI21X1TS U3487 ( .A0(n5500), .A1(n5157), .B0(n5156), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13) );
INVX4TS U3488 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .Y(n2582)
);
NAND2X4TS U3489 ( .A(n2244), .B(n3511), .Y(n3526) );
OAI22X2TS U3490 ( .A0(n2386), .A1(n3696), .B0(n3703), .B1(n3695), .Y(
DP_OP_501J223_127_5235_n219) );
INVX4TS U3491 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .Y(n2591)
);
ADDFHX4TS U3492 ( .A(n2210), .B(n2591), .CI(n2711), .CO(n2592), .S(n2589) );
NAND2X2TS U3493 ( .A(n2620), .B(n2619), .Y(n2621) );
OAI21X1TS U3494 ( .A0(n5921), .A1(n5917), .B0(n5918), .Y(n5913) );
NAND2X4TS U3495 ( .A(n2881), .B(n2880), .Y(n2883) );
ADDFHX4TS U3496 ( .A(n3155), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[6]), .CI(
n3154), .CO(n3156), .S(n3122) );
ADDFHX2TS U3497 ( .A(n3176), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[7]), .CI(
n3175), .CO(n3177), .S(n3157) );
INVX4TS U3498 ( .A(n5386), .Y(n5236) );
OAI211X1TS U3499 ( .A0(n5399), .A1(n5365), .B0(n5364), .C0(n5363), .Y(n1806)
);
ADDFHX2TS U3500 ( .A(n4050), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3]), .CI(
n4049), .CO(n4051), .S(n4046) );
XNOR2X2TS U3501 ( .A(n4067), .B(n4062), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]) );
XOR2X2TS U3502 ( .A(n3236), .B(n3235), .Y(n4205) );
OR2X4TS U3503 ( .A(n3172), .B(n3171), .Y(n3173) );
INVX4TS U3504 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(n2684) );
NOR2X8TS U3505 ( .A(n3069), .B(n4234), .Y(n4454) );
NOR2X4TS U3506 ( .A(n2832), .B(n2831), .Y(n2855) );
NAND2X4TS U3507 ( .A(n2680), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]), .Y(n2695) );
OR2X4TS U3508 ( .A(n2787), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(n3075)
);
ADDFHX2TS U3509 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]), .B(n3329), .CI(n3201), .CO(n3202), .S(n3185) );
NOR2X8TS U3510 ( .A(DP_OP_499J223_125_1651_n227), .B(
DP_OP_499J223_125_1651_n225), .Y(n3040) );
NOR2X4TS U3511 ( .A(n3229), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(n3308)
);
AOI21X2TS U3512 ( .A0(n3152), .A1(n3170), .B0(n3168), .Y(n3125) );
INVX2TS U3513 ( .A(n3168), .Y(n3150) );
NAND2X6TS U3514 ( .A(n3066), .B(n3065), .Y(n4330) );
NOR2X6TS U3515 ( .A(n3068), .B(n3067), .Y(n4190) );
OAI22X4TS U3516 ( .A0(n3709), .A1(n3693), .B0(n3708), .B1(n3694), .Y(n3662)
);
OAI2BB1X4TS U3517 ( .A0N(n2864), .A1N(n2863), .B0(n2212), .Y(n2211) );
OA21X4TS U3518 ( .A0(n2862), .A1(n2861), .B0(n2860), .Y(n2212) );
NOR2X6TS U3519 ( .A(n2970), .B(n2886), .Y(n2878) );
INVX4TS U3520 ( .A(n4228), .Y(DP_OP_499J223_125_1651_n272) );
XOR2X4TS U3521 ( .A(n3003), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .Y(n2213) );
OAI21X2TS U3522 ( .A0(n6285), .A1(n6282), .B0(n6286), .Y(n6292) );
AOI21X4TS U3523 ( .A0(n2955), .A1(n2953), .B0(n2725), .Y(n2968) );
CLKXOR2X4TS U3524 ( .A(n2740), .B(n2739), .Y(n3065) );
INVX6TS U3525 ( .A(n4206), .Y(DP_OP_499J223_125_1651_n299) );
OR2X4TS U3526 ( .A(n3914), .B(n3450), .Y(n2249) );
OAI22X2TS U3527 ( .A0(n2334), .A1(n3694), .B0(n2335), .B1(n3693), .Y(
DP_OP_501J223_127_5235_n208) );
INVX8TS U3528 ( .A(n6770), .Y(n6584) );
CMPR42X2TS U3529 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]), .C(
DP_OP_499J223_125_1651_n229), .D(DP_OP_499J223_125_1651_n274), .ICI(
n3410), .S(DP_OP_499J223_125_1651_n228), .ICO(
DP_OP_499J223_125_1651_n226), .CO(DP_OP_499J223_125_1651_n227) );
NAND2X2TS U3530 ( .A(n4032), .B(n4037), .Y(n4036) );
INVX4TS U3531 ( .A(n3012), .Y(n2749) );
OAI22X1TS U3532 ( .A0(n3968), .A1(n3866), .B0(n3913), .B1(n2394), .Y(n3911)
);
NAND2X4TS U3533 ( .A(n3864), .B(n3967), .Y(n3968) );
NOR2X2TS U3534 ( .A(n3993), .B(n3995), .Y(n3989) );
NOR2X4TS U3535 ( .A(n3940), .B(n3939), .Y(n3993) );
CMPR42X2TS U3536 ( .A(DP_OP_501J223_127_5235_n229), .B(
DP_OP_501J223_127_5235_n184), .C(DP_OP_501J223_127_5235_n178), .D(
DP_OP_501J223_127_5235_n237), .ICI(DP_OP_501J223_127_5235_n253), .S(
DP_OP_501J223_127_5235_n176), .ICO(DP_OP_501J223_127_5235_n174), .CO(
DP_OP_501J223_127_5235_n175) );
ADDFHX2TS U3537 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]), .B(n3183), .CI(n3182), .CO(n3184), .S(n3178) );
NOR2X6TS U3538 ( .A(n3321), .B(n3315), .Y(n3317) );
NAND2X4TS U3539 ( .A(n3229), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(n3310)
);
XOR2X4TS U3540 ( .A(n3640), .B(n3639), .Y(n3641) );
INVX4TS U3541 ( .A(n2664), .Y(n2646) );
OAI21X2TS U3542 ( .A0(n6267), .A1(n6263), .B0(n6264), .Y(n6246) );
NAND2X4TS U3543 ( .A(DP_OP_499J223_125_1651_n228), .B(
DP_OP_499J223_125_1651_n230), .Y(n3025) );
NOR2X8TS U3544 ( .A(DP_OP_499J223_125_1651_n228), .B(
DP_OP_499J223_125_1651_n230), .Y(n3024) );
OAI21X1TS U3545 ( .A0(n3787), .A1(n3783), .B0(n3784), .Y(n3782) );
CMPR42X2TS U3546 ( .A(DP_OP_501J223_127_5235_n508), .B(
DP_OP_501J223_127_5235_n465), .C(DP_OP_501J223_127_5235_n462), .D(
DP_OP_501J223_127_5235_n459), .ICI(DP_OP_501J223_127_5235_n466), .S(
DP_OP_501J223_127_5235_n457), .ICO(DP_OP_501J223_127_5235_n455), .CO(
DP_OP_501J223_127_5235_n456) );
INVX4TS U3547 ( .A(n2240), .Y(n6588) );
INVX4TS U3548 ( .A(n4208), .Y(DP_OP_499J223_125_1651_n303) );
NAND2X4TS U3549 ( .A(DP_OP_499J223_125_1651_n243), .B(
DP_OP_499J223_125_1651_n245), .Y(n2999) );
CMPR42X4TS U3550 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]), .C(
DP_OP_499J223_125_1651_n244), .D(DP_OP_499J223_125_1651_n279), .ICI(
DP_OP_499J223_125_1651_n303), .S(DP_OP_499J223_125_1651_n243), .ICO(
DP_OP_499J223_125_1651_n241), .CO(DP_OP_499J223_125_1651_n242) );
OR2X8TS U3551 ( .A(DP_OP_499J223_125_1651_n243), .B(
DP_OP_499J223_125_1651_n245), .Y(n2998) );
INVX8TS U3552 ( .A(n2766), .Y(n3051) );
NOR2X8TS U3553 ( .A(n2783), .B(n2782), .Y(n2802) );
ADDFHX4TS U3554 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]), .B(n2781), .CI(n2780), .CO(n2782), .S(n2686) );
OAI21X4TS U3555 ( .A0(n3233), .A1(n3213), .B0(n3212), .Y(n3214) );
NOR2X8TS U3556 ( .A(DP_OP_499J223_125_1651_n218), .B(
DP_OP_499J223_125_1651_n216), .Y(n2762) );
NAND2X4TS U3557 ( .A(DP_OP_499J223_125_1651_n216), .B(
DP_OP_499J223_125_1651_n218), .Y(n2761) );
NOR2X6TS U3558 ( .A(n3101), .B(n3104), .Y(n3107) );
NOR2X4TS U3559 ( .A(n3330), .B(n3329), .Y(n3331) );
OAI21X1TS U3560 ( .A0(n3787), .A1(n3773), .B0(n3772), .Y(n3777) );
XNOR2X4TS U3561 ( .A(n3028), .B(n3027), .Y(n3036) );
XOR2X2TS U3562 ( .A(n4060), .B(n4059), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]) );
NAND2X4TS U3563 ( .A(n3069), .B(n4234), .Y(n4453) );
ADDFHX4TS U3564 ( .A(n2672), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[7]), .CI(
n2671), .CO(n2673), .S(n2653) );
NOR2X2TS U3565 ( .A(n5502), .B(n5507), .Y(n3396) );
ADDHX1TS U3566 ( .A(n4340), .B(n4339), .CO(DP_OP_502J223_128_4510_n132), .S(
n4253) );
OR2X8TS U3567 ( .A(n3058), .B(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(
n3284) );
NAND2X2TS U3568 ( .A(n4146), .B(n4148), .Y(n4147) );
AOI21X4TS U3569 ( .A0(n4416), .A1(n4413), .B0(n4270), .Y(n6148) );
OAI21X4TS U3570 ( .A0(n6168), .A1(n6162), .B0(n6163), .Y(n4416) );
OAI21X4TS U3571 ( .A0(n6047), .A1(n6041), .B0(n6042), .Y(n6075) );
XNOR2X1TS U3572 ( .A(n3914), .B(n2205), .Y(n3897) );
OAI22X2TS U3573 ( .A0(n3703), .A1(n3696), .B0(n2331), .B1(n3695), .Y(n3672)
);
NAND2X4TS U3574 ( .A(FPMULT_Op_MY[12]), .B(DP_OP_501J223_127_5235_n897), .Y(
n3431) );
OAI21X4TS U3575 ( .A0(n4322), .A1(n4324), .B0(n4325), .Y(n3063) );
OR2X4TS U3576 ( .A(n6594), .B(FPMULT_Op_MY[3]), .Y(n2218) );
INVX6TS U3577 ( .A(n2214), .Y(n6594) );
OAI21X4TS U3578 ( .A0(n3380), .A1(n4431), .B0(n4433), .Y(n3383) );
NAND2X4TS U3579 ( .A(DP_OP_501J223_127_5235_n903), .B(n6955), .Y(n3371) );
AOI21X4TS U3580 ( .A0(n2246), .A1(n3482), .B0(n3468), .Y(n3488) );
OAI22X2TS U3581 ( .A0(n2331), .A1(n3698), .B0(n3679), .B1(n3697), .Y(n3683)
);
OAI21X2TS U3582 ( .A0(n4563), .A1(n4439), .B0(n4438), .Y(n2241) );
NAND2X1TS U3583 ( .A(n3361), .B(n4433), .Y(n3362) );
OAI21X2TS U3584 ( .A0(n4434), .A1(n4433), .B0(n4432), .Y(n4435) );
OR2X8TS U3585 ( .A(DP_OP_499J223_125_1651_n234), .B(
DP_OP_499J223_125_1651_n236), .Y(n2470) );
NAND2X4TS U3586 ( .A(DP_OP_499J223_125_1651_n234), .B(
DP_OP_499J223_125_1651_n236), .Y(n3012) );
XOR2X2TS U3587 ( .A(n4178), .B(n4177), .Y(FPMULT_Sgf_operation_Result[37])
);
OA21X1TS U3588 ( .A0(n5599), .A1(n5602), .B0(n5600), .Y(n5597) );
OAI21X1TS U3589 ( .A0(n5573), .A1(n5561), .B0(n5560), .Y(n5564) );
OAI21X2TS U3590 ( .A0(n3787), .A1(n3755), .B0(n3754), .Y(n3762) );
OAI211X1TS U3591 ( .A0(n5237), .A1(n5377), .B0(n5360), .C0(n5359), .Y(n1797)
);
NOR2X4TS U3592 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n4810), .Y(n5219) );
NAND2X4TS U3593 ( .A(DP_OP_499J223_125_1651_n210), .B(
DP_OP_499J223_125_1651_n212), .Y(n2790) );
NOR2X4TS U3594 ( .A(n3406), .B(n3400), .Y(n3402) );
AOI21X4TS U3595 ( .A0(n2649), .A1(n2626), .B0(n2594), .Y(n2601) );
XOR2X2TS U3596 ( .A(n3426), .B(DP_OP_499J223_125_1651_n299), .Y(
FPMULT_Sgf_operation_Result[38]) );
OAI21X4TS U3597 ( .A0(n3995), .A1(n4000), .B0(n3996), .Y(n3988) );
NAND2X4TS U3598 ( .A(n3940), .B(n3939), .Y(n4000) );
XNOR2X4TS U3599 ( .A(n3637), .B(n3636), .Y(n2243) );
AOI21X4TS U3600 ( .A0(n2375), .A1(n3339), .B0(n3338), .Y(n3342) );
XOR2X4TS U3601 ( .A(n3277), .B(n3276), .Y(n4227) );
AO21X4TS U3602 ( .A0(n4173), .A1(n3336), .B0(n3335), .Y(n3337) );
NOR2X6TS U3603 ( .A(n3406), .B(n3334), .Y(n3336) );
OR2X4TS U3604 ( .A(n2636), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(n4211) );
NAND2X4TS U3605 ( .A(DP_OP_499J223_125_1651_n237), .B(
DP_OP_499J223_125_1651_n239), .Y(n3015) );
AO21X4TS U3606 ( .A0(n4173), .A1(n3356), .B0(n3355), .Y(n3357) );
XNOR2X4TS U3607 ( .A(n3582), .B(n3581), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11) );
OAI21X2TS U3608 ( .A0(n3587), .A1(n3583), .B0(n3584), .Y(n3582) );
OAI21X4TS U3609 ( .A0(n3519), .A1(n3518), .B0(n3517), .Y(n3625) );
NAND2X4TS U3610 ( .A(n2222), .B(n2249), .Y(n3518) );
INVX6TS U3611 ( .A(n2236), .Y(n5644) );
NAND2X4TS U3612 ( .A(n3284), .B(n4421), .Y(n4323) );
INVX4TS U3613 ( .A(n4145), .Y(n4150) );
XNOR2X4TS U3614 ( .A(n4040), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]), .Y(
n4031) );
AOI21X4TS U3615 ( .A0(n4173), .A1(n3402), .B0(n3401), .Y(n3413) );
OAI21X4TS U3616 ( .A0(n4166), .A1(n4165), .B0(n4164), .Y(n4172) );
AOI21X4TS U3617 ( .A0(n2204), .A1(n5925), .B0(n3007), .Y(n3008) );
AOI21X4TS U3618 ( .A0(n2881), .A1(n2882), .B0(n2744), .Y(n2812) );
OR2X4TS U3619 ( .A(DP_OP_499J223_125_1651_n249), .B(n2743), .Y(n2881) );
XOR2X4TS U3620 ( .A(n3001), .B(n3000), .Y(n3004) );
NAND2X4TS U3621 ( .A(DP_OP_499J223_125_1651_n249), .B(n2743), .Y(n2880) );
ADDFHX2TS U3622 ( .A(n3689), .B(n3688), .CI(n3687), .CO(
DP_OP_501J223_127_5235_n191), .S(n3497) );
AOI21X2TS U3623 ( .A0(n3050), .A1(n3051), .B0(n3049), .Y(n3056) );
NAND2X4TS U3624 ( .A(n2787), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(n2808)
);
OAI21X4TS U3625 ( .A0(n3105), .A1(n3104), .B0(n3103), .Y(n3106) );
OAI21X2TS U3626 ( .A0(n3261), .A1(n3260), .B0(n3259), .Y(n3262) );
NOR2X6TS U3627 ( .A(n3225), .B(n3224), .Y(n3261) );
XNOR2X2TS U3628 ( .A(n4172), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]) );
NOR2X2TS U3629 ( .A(n3427), .B(n2264), .Y(n3339) );
AOI21X4TS U3630 ( .A0(n2864), .A1(n2847), .B0(n2846), .Y(n2854) );
NOR2X4TS U3631 ( .A(n2945), .B(n2947), .Y(n2885) );
XOR2X1TS U3632 ( .A(n3983), .B(n3982), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12) );
XOR2X4TS U3633 ( .A(n3125), .B(n3124), .Y(n3126) );
XOR2X2TS U3634 ( .A(n2694), .B(n2693), .Y(n2698) );
NOR2X4TS U3635 ( .A(n2698), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(n2736)
);
XOR2X4TS U3636 ( .A(n3014), .B(n3013), .Y(n3020) );
NOR2X8TS U3637 ( .A(n2876), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .Y(n2970)
);
AOI21X4TS U3638 ( .A0(n2244), .A1(n3437), .B0(n3436), .Y(n3525) );
XOR2X1TS U3639 ( .A(n3587), .B(n3586), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10) );
AOI21X2TS U3640 ( .A0(n4181), .A1(n3347), .B0(n3346), .Y(n3349) );
XOR2X4TS U3641 ( .A(n2610), .B(n2609), .Y(n2642) );
AOI21X4TS U3642 ( .A0(n2649), .A1(n2666), .B0(n2664), .Y(n2610) );
NOR2X4TS U3643 ( .A(n3345), .B(n3344), .Y(n3346) );
XOR2X4TS U3644 ( .A(n2601), .B(n2600), .Y(n2641) );
NOR2X4TS U3645 ( .A(n3423), .B(DP_OP_499J223_125_1651_n299), .Y(n3408) );
AOI21X4TS U3646 ( .A0(n4173), .A1(n4176), .B0(n3407), .Y(n3423) );
XOR2X4TS U3647 ( .A(n2872), .B(n2869), .Y(n2875) );
XOR2X4TS U3648 ( .A(n3349), .B(n3348), .Y(FPMULT_Sgf_operation_Result[43])
);
OAI21X4TS U3649 ( .A0(n2736), .A1(n2739), .B0(n2737), .Y(n2777) );
NAND2X2TS U3650 ( .A(n2721), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(n2739)
);
XOR2X4TS U3651 ( .A(n3341), .B(n3270), .Y(n2265) );
XOR2X4TS U3652 ( .A(n3228), .B(n3227), .Y(n3229) );
NOR2X2TS U3653 ( .A(n3412), .B(DP_OP_499J223_125_1651_n297), .Y(n3404) );
XNOR2X4TS U3654 ( .A(n3863), .B(n2307), .Y(n3967) );
XOR2X4TS U3655 ( .A(n2916), .B(n2915), .Y(n2917) );
XOR2X4TS U3656 ( .A(n3056), .B(n3055), .Y(n3062) );
XOR2X4TS U3657 ( .A(n3360), .B(DP_OP_499J223_125_1651_n292), .Y(
FPMULT_Sgf_operation_Result[45]) );
AOI21X2TS U3658 ( .A0(n2375), .A1(n3359), .B0(n3358), .Y(n3360) );
OAI21X4TS U3659 ( .A0(n2947), .A1(n2961), .B0(n2948), .Y(n2884) );
NOR2X6TS U3660 ( .A(n2875), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(n2947)
);
NOR2X4TS U3661 ( .A(n3418), .B(n3420), .Y(n3358) );
XOR2X4TS U3662 ( .A(n2854), .B(n2853), .Y(n2874) );
XOR2X4TS U3663 ( .A(n3459), .B(n3458), .Y(n3460) );
AOI21X4TS U3664 ( .A0(n3486), .A1(n2247), .B0(n3445), .Y(n3519) );
OAI21X4TS U3665 ( .A0(DP_OP_501J223_127_5235_n630), .A1(n3476), .B0(n3477),
.Y(n3486) );
XOR2X4TS U3666 ( .A(n3206), .B(n3205), .Y(n3207) );
AOI21X4TS U3667 ( .A0(n3267), .A1(n3200), .B0(n3199), .Y(n3206) );
INVX4TS U3668 ( .A(n3265), .Y(n3199) );
NOR2X4TS U3669 ( .A(n3428), .B(n2264), .Y(n3338) );
XOR2X4TS U3670 ( .A(n3319), .B(n3230), .Y(n4233) );
INVX8TS U3671 ( .A(n3333), .Y(n3319) );
AOI21X4TS U3672 ( .A0(n6157), .A1(n6153), .B0(n4269), .Y(n6168) );
OAI21X4TS U3673 ( .A0(n6130), .A1(n6124), .B0(n6125), .Y(n6157) );
OAI21X4TS U3674 ( .A0(n6120), .A1(n6114), .B0(n6115), .Y(n6140) );
OAI21X4TS U3675 ( .A0(n6085), .A1(n6079), .B0(n6080), .Y(n6177) );
NOR2X2TS U3676 ( .A(n3709), .B(n3692), .Y(n3663) );
MX2X1TS U3677 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
ADDHXLTS U3678 ( .A(DP_OP_501J223_127_5235_n944), .B(n2292), .CO(n3813), .S(
n3730) );
CMPR22X2TS U3679 ( .A(n3863), .B(n3648), .CO(n3647), .S(n3649) );
ADDHX1TS U3680 ( .A(n3684), .B(n3683), .CO(DP_OP_501J223_127_5235_n184), .S(
n3682) );
NAND2X1TS U3681 ( .A(n2249), .B(n3462), .Y(n3463) );
ADDHX1TS U3682 ( .A(n3839), .B(n3838), .CO(DP_OP_501J223_127_5235_n482), .S(
n3731) );
NAND2X2TS U3683 ( .A(n4317), .B(n2485), .Y(n3039) );
MX2X1TS U3684 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U3685 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
NOR2X4TS U3686 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .B(n2657),
.Y(n2841) );
NOR2X2TS U3687 ( .A(n3142), .B(n3145), .Y(n3148) );
NAND2X1TS U3688 ( .A(n2246), .B(n3481), .Y(n3483) );
OAI21X1TS U3689 ( .A0(n3816), .A1(n2402), .B0(n3749), .Y(n3750) );
NAND2X1TS U3690 ( .A(n3819), .B(n3818), .Y(n3820) );
NAND2X1TS U3691 ( .A(n3725), .B(n3814), .Y(n3726) );
INVX2TS U3692 ( .A(n3815), .Y(n3725) );
NOR2X2TS U3693 ( .A(n3626), .B(n3653), .Y(n3524) );
AOI222X1TS U3694 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n6813), .B0(n2524), .B1(
n2523), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n2465), .Y(n2528) );
AOI2BB2XLTS U3695 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n2397), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n2522), .Y(n2523) );
CLKAND2X2TS U3696 ( .A(n6568), .B(FPMULT_Op_MY[4]), .Y(n4770) );
CLKAND2X2TS U3697 ( .A(FPMULT_Op_MX[12]), .B(n2290), .Y(n4832) );
NAND2X1TS U3698 ( .A(n3530), .B(n3529), .Y(n3531) );
INVX2TS U3699 ( .A(n3528), .Y(n3530) );
INVX2TS U3700 ( .A(n2345), .Y(n3840) );
ADDHX1TS U3701 ( .A(n3835), .B(n3834), .CO(DP_OP_501J223_127_5235_n473), .S(
DP_OP_501J223_127_5235_n474) );
NOR2X2TS U3702 ( .A(n2325), .B(n3697), .Y(n3651) );
INVX4TS U3703 ( .A(n3539), .Y(n3693) );
INVX4TS U3704 ( .A(n3660), .Y(n3694) );
ADDFHX2TS U3705 ( .A(n3682), .B(n3681), .CI(n3680), .CO(
DP_OP_501J223_127_5235_n182), .S(DP_OP_501J223_127_5235_n183) );
NAND2X2TS U3706 ( .A(n2245), .B(n2454), .Y(n3471) );
OAI2BB2XLTS U3707 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n2541), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n2461), .Y(n2542) );
OAI2BB2XLTS U3708 ( .B0(n2540), .B1(n2547), .A0N(n2539), .A1N(n2538), .Y(
n2543) );
AOI21X2TS U3709 ( .A0(n2809), .A1(n3075), .B0(n3078), .Y(n2810) );
NAND2X4TS U3710 ( .A(n5461), .B(n6335), .Y(n5015) );
AOI21X1TS U3711 ( .A0(n5853), .A1(n5890), .B0(n5852), .Y(n5882) );
NOR2X2TS U3712 ( .A(n4323), .B(n4324), .Y(n3064) );
NAND2X2TS U3713 ( .A(n2245), .B(n3635), .Y(n3636) );
CLKAND2X2TS U3714 ( .A(n2311), .B(FPADDSUB_Data_array_SWR[18]), .Y(n4479) );
CLKAND2X2TS U3715 ( .A(n6809), .B(FPADDSUB_DMP_SFG[14]), .Y(n4396) );
NOR3X1TS U3716 ( .A(FPSENCOS_cont_var_out[0]), .B(n6802), .C(n4998), .Y(
n4997) );
BUFX3TS U3717 ( .A(n5053), .Y(n6509) );
MX2X1TS U3718 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U3719 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
INVX2TS U3720 ( .A(n3984), .Y(n3959) );
XNOR2X1TS U3721 ( .A(n3937), .B(n2205), .Y(n3882) );
INVX2TS U3722 ( .A(n3788), .Y(n3798) );
NAND2X1TS U3723 ( .A(n5647), .B(FPMULT_Op_MX[19]), .Y(n5671) );
OAI21X2TS U3724 ( .A0(n4066), .A1(n4065), .B0(n4064), .Y(n4084) );
OAI21X2TS U3725 ( .A0(n2662), .A1(n2661), .B0(n2660), .Y(n2663) );
OAI21X2TS U3726 ( .A0(n2646), .A1(n2659), .B0(n2661), .Y(n2647) );
NOR2X4TS U3727 ( .A(n2593), .B(n2592), .Y(n2602) );
CLKAND2X2TS U3728 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MY[14]), .Y(n4828) );
ADDHXLTS U3729 ( .A(n2285), .B(n2287), .CO(n3718), .S(n3714) );
NAND2X1TS U3730 ( .A(n3711), .B(n3720), .Y(n3712) );
INVX2TS U3731 ( .A(n3721), .Y(n3710) );
NOR2X1TS U3732 ( .A(n4297), .B(n4291), .Y(n4285) );
INVX2TS U3733 ( .A(n4221), .Y(n2624) );
ADDFHX2TS U3734 ( .A(n2368), .B(n3934), .CI(n3933), .CO(n3949), .S(n3929) );
INVX2TS U3735 ( .A(n3956), .Y(n3934) );
ADDFHX2TS U3736 ( .A(n3828), .B(n3827), .CI(n3826), .CO(
DP_OP_501J223_127_5235_n458), .S(DP_OP_501J223_127_5235_n459) );
INVX2TS U3737 ( .A(n3718), .Y(n3846) );
INVX2TS U3738 ( .A(n3714), .Y(n3847) );
INVX2TS U3739 ( .A(n3729), .Y(n3849) );
NAND2X1TS U3740 ( .A(n3715), .B(n3721), .Y(n3716) );
INVX4TS U3741 ( .A(n3493), .Y(n3701) );
OAI32X1TS U3742 ( .A0(n2530), .A1(n2529), .A2(n2528), .B0(n2527), .B1(n2529),
.Y(n2548) );
OAI22X1TS U3743 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n2518), .B0(n2526), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n2529) );
NOR2X1TS U3744 ( .A(FPADDSUB_Raw_mant_NRM_SWR[22]), .B(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n5220) );
NOR2X1TS U3745 ( .A(FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n5224) );
OAI31X1TS U3746 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n6795), .A2(n5209),
.B0(n7063), .Y(n5211) );
INVX2TS U3747 ( .A(n5208), .Y(n5209) );
INVX2TS U3748 ( .A(n6186), .Y(n6231) );
OAI21X1TS U3749 ( .A0(n6186), .A1(n4260), .B0(n4259), .Y(n6034) );
NAND2X1TS U3750 ( .A(FPMULT_Sgf_normalized_result[3]), .B(
FPMULT_Sgf_normalized_result[2]), .Y(n5850) );
NAND3XLTS U3751 ( .A(n5838), .B(FPMULT_Op_MY[2]), .C(n2481), .Y(n5844) );
INVX2TS U3752 ( .A(n3973), .Y(n3961) );
OAI22X1TS U3753 ( .A0(n3883), .A1(n3901), .B0(n3868), .B1(
DP_OP_501J223_127_5235_n723), .Y(n3876) );
OAI22X1TS U3754 ( .A0(n2373), .A1(n3840), .B0(n2371), .B1(n2345), .Y(n3756)
);
NOR2X1TS U3755 ( .A(n2325), .B(n3695), .Y(DP_OP_501J223_127_5235_n214) );
NOR2X2TS U3756 ( .A(DP_OP_501J223_127_5235_n124), .B(
DP_OP_501J223_127_5235_n122), .Y(n3556) );
INVX4TS U3757 ( .A(n3484), .Y(n3702) );
NAND2X2TS U3758 ( .A(n2247), .B(n3485), .Y(n3487) );
AO22XLTS U3759 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2329), .Y(n4482) );
AO22XLTS U3760 ( .A0(FPADDSUB_Data_array_SWR[7]), .A1(n2329), .B0(
FPADDSUB_Data_array_SWR[3]), .B1(n2342), .Y(n5942) );
AOI211X2TS U3761 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n2312), .B0(n5948),
.C0(n5947), .Y(n5992) );
NOR2X4TS U3762 ( .A(n2622), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(n2731) );
INVX4TS U3763 ( .A(n2216), .Y(n6569) );
INVX2TS U3764 ( .A(n5315), .Y(n2337) );
AO22XLTS U3765 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[1]), .B1(n2342), .Y(n5939) );
OR2X1TS U3766 ( .A(n5340), .B(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n5316) );
AOI2BB2XLTS U3767 ( .B0(n2360), .B1(n2256), .A0N(n2340), .A1N(
FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n5234) );
BUFX3TS U3768 ( .A(n5158), .Y(n5169) );
NOR2X2TS U3769 ( .A(n6562), .B(n6556), .Y(n5158) );
INVX2TS U3770 ( .A(n4502), .Y(n4519) );
INVX2TS U3771 ( .A(n2337), .Y(n2338) );
INVX2TS U3772 ( .A(n5237), .Y(n2353) );
AOI21X2TS U3773 ( .A0(n6155), .A1(n4409), .B0(n4408), .Y(n6166) );
CLKAND2X2TS U3774 ( .A(n6824), .B(FPADDSUB_DMP_SFG[20]), .Y(n4408) );
INVX2TS U3775 ( .A(n6089), .Y(n6091) );
CLKAND2X2TS U3776 ( .A(n6862), .B(FPADDSUB_DMP_SFG[12]), .Y(n4392) );
INVX2TS U3777 ( .A(n6041), .Y(n6043) );
CLKAND2X2TS U3778 ( .A(n6818), .B(FPADDSUB_DMP_SFG[18]), .Y(n4404) );
CLKAND2X2TS U3779 ( .A(n6808), .B(FPADDSUB_DMP_SFG[16]), .Y(n4400) );
AO21XLTS U3780 ( .A0(n5742), .A1(n5741), .B0(n5740), .Y(intadd_512_CI) );
AO21XLTS U3781 ( .A0(n5716), .A1(n5715), .B0(n5714), .Y(intadd_512_A_0_) );
OR2X1TS U3782 ( .A(n5454), .B(n5460), .Y(n4579) );
NAND3XLTS U3783 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[29]), .Y(n6329) );
AOI31XLTS U3784 ( .A0(n6327), .A1(n6326), .A2(n6325), .B0(n6332), .Y(n6330)
);
NOR3BX2TS U3785 ( .AN(n2298), .B(n6371), .C(n6369), .Y(n6358) );
NOR3XLTS U3786 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n6314) );
NOR2X1TS U3787 ( .A(n3970), .B(n3969), .Y(n3979) );
NAND2X1TS U3788 ( .A(n3970), .B(n3969), .Y(n3980) );
AOI21X2TS U3789 ( .A0(n3988), .A1(n2476), .B0(n3945), .Y(n3946) );
INVX2TS U3790 ( .A(n3990), .Y(n3945) );
INVX2TS U3791 ( .A(n4013), .Y(n4004) );
OAI22X1TS U3792 ( .A0(n3887), .A1(n3901), .B0(n3882), .B1(
DP_OP_501J223_127_5235_n723), .Y(n3891) );
ADDHX1TS U3793 ( .A(n3895), .B(n3894), .CO(n4020), .S(n4022) );
OAI22X1TS U3794 ( .A0(n3887), .A1(DP_OP_501J223_127_5235_n723), .B0(n3901),
.B1(n3897), .Y(n3895) );
NOR2X2TS U3795 ( .A(n3759), .B(n3758), .Y(n3765) );
INVX2TS U3796 ( .A(n3774), .Y(n3753) );
NAND2X1TS U3797 ( .A(n3759), .B(n3758), .Y(n3764) );
NOR2X2TS U3798 ( .A(n3783), .B(n3778), .Y(n3770) );
INVX2TS U3799 ( .A(n3771), .Y(n3772) );
NOR2X4TS U3800 ( .A(DP_OP_501J223_127_5235_n449), .B(
DP_OP_501J223_127_5235_n451), .Y(n3778) );
NOR2X2TS U3801 ( .A(DP_OP_501J223_127_5235_n452), .B(
DP_OP_501J223_127_5235_n456), .Y(n3783) );
NOR2X4TS U3802 ( .A(DP_OP_501J223_127_5235_n464), .B(
DP_OP_501J223_127_5235_n469), .Y(n3794) );
INVX2TS U3803 ( .A(n3804), .Y(n3742) );
NOR2X2TS U3804 ( .A(DP_OP_501J223_127_5235_n470), .B(
DP_OP_501J223_127_5235_n476), .Y(n3799) );
INVX2TS U3805 ( .A(n3571), .Y(n3572) );
NOR2X4TS U3806 ( .A(DP_OP_501J223_127_5235_n129), .B(
DP_OP_501J223_127_5235_n125), .Y(n3578) );
INVX2TS U3807 ( .A(n3620), .Y(n3498) );
INVX2TS U3808 ( .A(n3461), .Y(n3704) );
AO22XLTS U3809 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n3288), .B0(
FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n5959), .Y(n4360) );
AO22XLTS U3810 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[0]), .B1(n2343), .Y(n4361) );
AOI2BB2X1TS U3811 ( .B0(n2573), .B1(n2572), .A0N(n2571), .A1N(n2570), .Y(
n2574) );
NOR2BX1TS U3812 ( .AN(n2558), .B(n2557), .Y(n2576) );
OAI221XLTS U3813 ( .A0(n2413), .A1(FPADDSUB_intDY_EWSW[13]), .B0(n2411),
.B1(FPADDSUB_intDY_EWSW[6]), .C0(n6670), .Y(n6675) );
OAI221XLTS U3814 ( .A0(n6811), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n2408),
.B1(FPADDSUB_intDY_EWSW[16]), .C0(n6686), .Y(n6700) );
BUFX3TS U3815 ( .A(n2322), .Y(n5312) );
BUFX3TS U3816 ( .A(n2322), .Y(n5310) );
BUFX3TS U3817 ( .A(n5118), .Y(n5136) );
BUFX3TS U3818 ( .A(n5158), .Y(n5137) );
BUFX3TS U3819 ( .A(n5118), .Y(n5139) );
BUFX3TS U3820 ( .A(n5158), .Y(n5140) );
AND3X1TS U3821 ( .A(n5260), .B(n5259), .C(n5258), .Y(n5380) );
INVX2TS U3822 ( .A(n2252), .Y(n2355) );
INVX2TS U3823 ( .A(n2337), .Y(n2339) );
AND3X1TS U3824 ( .A(n5324), .B(n5323), .C(n5322), .Y(n5385) );
MX2X1TS U3825 ( .A(FPMULT_Add_result[23]), .B(n5855), .S0(n5931), .Y(n1597)
);
NAND4XLTS U3826 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[1]), .D(
FPMULT_Exp_module_Data_S[0]), .Y(n6018) );
XNOR2X1TS U3827 ( .A(n4014), .B(n4013), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6) );
NAND2X1TS U3828 ( .A(n4012), .B(n4011), .Y(n4014) );
INVX2TS U3829 ( .A(n4010), .Y(n4012) );
INVX2TS U3830 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(n2817)
);
NAND2X1TS U3831 ( .A(n4057), .B(n4056), .Y(n4064) );
OR2X2TS U3832 ( .A(n2684), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]), .Y(n2685) );
AOI21X2TS U3833 ( .A0(n4108), .A1(n4107), .B0(n4106), .Y(n4119) );
INVX2TS U3834 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(n3183) );
INVX2TS U3835 ( .A(n3485), .Y(n3445) );
OAI21X2TS U3836 ( .A0(n4039), .A1(n4038), .B0(n4037), .Y(n4145) );
INVX2TS U3837 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n4030) );
NAND2X1TS U3838 ( .A(n2822), .B(n2815), .Y(n2675) );
AOI21X1TS U3839 ( .A0(n4067), .A1(n4061), .B0(n4053), .Y(n4060) );
NOR2X2TS U3840 ( .A(n4071), .B(n4070), .Y(n4167) );
NOR2X1TS U3841 ( .A(n3271), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]), .Y(
n3305) );
NAND2X1TS U3842 ( .A(n3271), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]), .Y(
n3304) );
OAI21X2TS U3843 ( .A0(n3150), .A1(n3164), .B0(n2200), .Y(n3151) );
INVX2TS U3844 ( .A(n3181), .Y(n3197) );
OR2X2TS U3845 ( .A(n3178), .B(n3177), .Y(n3194) );
INVX2TS U3846 ( .A(n3115), .Y(n3084) );
INVX2TS U3847 ( .A(n3817), .Y(n3819) );
NOR2X2TS U3848 ( .A(FPMULT_Op_MY[9]), .B(n6585), .Y(n3815) );
NOR2X1TS U3849 ( .A(n3722), .B(n3719), .Y(n3724) );
OAI21X1TS U3850 ( .A0(n3722), .A1(n3721), .B0(n3720), .Y(n3723) );
INVX2TS U3851 ( .A(n3722), .Y(n3711) );
NAND2X2TS U3852 ( .A(n3921), .B(n3457), .Y(n3514) );
INVX2TS U3853 ( .A(n3462), .Y(n3516) );
INVX2TS U3854 ( .A(n3519), .Y(n3464) );
NAND2X1TS U3855 ( .A(n2481), .B(FPMULT_Op_MX[13]), .Y(n3481) );
NAND2BXLTS U3856 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n2520) );
OR2X2TS U3857 ( .A(n2581), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]), .Y(
n2586) );
NAND2X1TS U3858 ( .A(n4153), .B(n4152), .Y(n4154) );
XNOR2X1TS U3859 ( .A(n2728), .B(n6746), .Y(n4236) );
NAND2X1TS U3860 ( .A(n4035), .B(n4033), .Y(n2728) );
OR2X1TS U3861 ( .A(n2703), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n2704) );
NAND2X1TS U3862 ( .A(n2868), .B(n2870), .Y(n2869) );
NAND2X1TS U3863 ( .A(n2692), .B(n2691), .Y(n2694) );
NAND2X1TS U3864 ( .A(n2654), .B(n2660), .Y(n2655) );
NAND2X2TS U3865 ( .A(n2589), .B(n2588), .Y(n2632) );
XOR2X1TS U3866 ( .A(n4171), .B(n4170), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]) );
INVX2TS U3867 ( .A(n4225), .Y(DP_OP_499J223_125_1651_n276) );
INVX2TS U3868 ( .A(n4203), .Y(DP_OP_499J223_125_1651_n293) );
NAND2X1TS U3869 ( .A(n3226), .B(n3259), .Y(n3227) );
NAND2X1TS U3870 ( .A(n3204), .B(n3260), .Y(n3205) );
AOI21X2TS U3871 ( .A0(n4437), .A1(n4436), .B0(n4435), .Y(n4563) );
NOR2X1TS U3872 ( .A(n4434), .B(n4431), .Y(n4436) );
NAND2X1TS U3873 ( .A(n6588), .B(n5646), .Y(n4561) );
NAND2X1TS U3874 ( .A(n5644), .B(FPMULT_Op_MY[2]), .Y(n4433) );
INVX2TS U3875 ( .A(n3507), .Y(n3436) );
INVX2TS U3876 ( .A(n3510), .Y(n3437) );
NAND2X1TS U3877 ( .A(DP_OP_501J223_127_5235_n903), .B(n2291), .Y(n3529) );
INVX2TS U3878 ( .A(n3447), .Y(n3451) );
INVX2TS U3879 ( .A(n3441), .Y(n3432) );
CLKAND2X2TS U3880 ( .A(n6569), .B(FPMULT_Op_MY[2]), .Y(n4766) );
ADDHXLTS U3881 ( .A(n6572), .B(n6567), .CO(n3747), .S(n3825) );
INVX2TS U3882 ( .A(n3719), .Y(n3715) );
ADDFHX2TS U3883 ( .A(n3672), .B(n3671), .CI(n3670), .CO(
DP_OP_501J223_127_5235_n167), .S(DP_OP_501J223_127_5235_n168) );
INVX2TS U3884 ( .A(n3481), .Y(n3468) );
NAND2X1TS U3885 ( .A(n2344), .B(FPMULT_Op_MX[5]), .Y(n3536) );
CLKAND2X2TS U3886 ( .A(n4305), .B(n2463), .Y(n4303) );
NAND2X4TS U3887 ( .A(n2587), .B(n2586), .Y(n2628) );
INVX2TS U3888 ( .A(n6746), .Y(n2727) );
NAND2X1TS U3889 ( .A(n2608), .B(n2661), .Y(n2609) );
OR2X1TS U3890 ( .A(n2713), .B(n2712), .Y(n2938) );
NAND2X1TS U3891 ( .A(n2705), .B(n2704), .Y(n2908) );
NAND2X2TS U3892 ( .A(n2875), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(n2948)
);
INVX4TS U3893 ( .A(n2992), .Y(n2964) );
OAI21X2TS U3894 ( .A0(n2755), .A1(n3052), .B0(n3053), .Y(n2756) );
INVX2TS U3895 ( .A(n2808), .Y(n3078) );
INVX2TS U3896 ( .A(n2841), .Y(n2888) );
NAND2X1TS U3897 ( .A(n2742), .B(n2741), .Y(n2966) );
XNOR2X1TS U3898 ( .A(n2697), .B(n2904), .Y(n2721) );
NAND2X1TS U3899 ( .A(n2696), .B(n2695), .Y(n2697) );
INVX2TS U3900 ( .A(n3023), .Y(n3034) );
NOR2X1TS U3901 ( .A(n4903), .B(n5760), .Y(n4889) );
CLKAND2X2TS U3902 ( .A(DP_OP_501J223_127_5235_n944), .B(n5644), .Y(n4870) );
ADDHX1TS U3903 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .B(
DP_OP_499J223_125_1651_n202), .CO(n3137), .S(n3110) );
INVX2TS U3904 ( .A(n2789), .Y(n2771) );
NAND2X1TS U3905 ( .A(n3275), .B(n3309), .Y(n3276) );
NAND2X1TS U3906 ( .A(DP_OP_499J223_125_1651_n203), .B(n3110), .Y(n3131) );
NOR2X6TS U3907 ( .A(n3207), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(n3213)
);
OAI21X2TS U3908 ( .A0(n3191), .A1(n3211), .B0(n3233), .Y(n3192) );
NAND2X2TS U3909 ( .A(n3207), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(n3212)
);
CMPR42X1TS U3910 ( .A(DP_OP_502J223_128_4510_n150), .B(
DP_OP_502J223_128_4510_n157), .C(DP_OP_502J223_128_4510_n185), .D(
DP_OP_502J223_128_4510_n164), .ICI(DP_OP_502J223_128_4510_n124), .S(
DP_OP_502J223_128_4510_n120), .ICO(DP_OP_502J223_128_4510_n118), .CO(
DP_OP_502J223_128_4510_n119) );
INVX2TS U3911 ( .A(n3363), .Y(n2313) );
INVX2TS U3912 ( .A(n3937), .Y(n3952) );
NOR2X2TS U3913 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[4]), .Y(n3506) );
NAND2X2TS U3914 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[4]), .Y(n3510) );
INVX4TS U3915 ( .A(n3505), .Y(n3527) );
NAND2X1TS U3916 ( .A(n3643), .B(n3642), .Y(n3644) );
INVX2TS U3917 ( .A(n3489), .Y(n3633) );
NAND2X1TS U3918 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[2]), .Y(n3489) );
INVX2TS U3919 ( .A(n3488), .Y(n3634) );
INVX2TS U3920 ( .A(n3446), .Y(n3452) );
NAND2X1TS U3921 ( .A(n4848), .B(n4847), .Y(n5710) );
INVX2TS U3922 ( .A(n3825), .Y(n3843) );
INVX2TS U3923 ( .A(n3747), .Y(n3842) );
ADDHX1TS U3924 ( .A(n3830), .B(n3829), .CO(DP_OP_501J223_127_5235_n460), .S(
n3826) );
OAI22X1TS U3925 ( .A0(n3848), .A1(n3844), .B0(n3852), .B1(n3845), .Y(n3823)
);
INVX2TS U3926 ( .A(n3730), .Y(n3845) );
INVX2TS U3927 ( .A(n3813), .Y(n3844) );
NOR2X1TS U3928 ( .A(n2486), .B(n3701), .Y(DP_OP_501J223_127_5235_n241) );
OAI22X1TS U3929 ( .A0(n3706), .A1(n3698), .B0(n2334), .B1(n3697), .Y(
DP_OP_501J223_127_5235_n225) );
CMPR42X1TS U3930 ( .A(DP_OP_501J223_127_5235_n203), .B(
DP_OP_501J223_127_5235_n211), .C(DP_OP_501J223_127_5235_n169), .D(
DP_OP_501J223_127_5235_n219), .ICI(DP_OP_501J223_127_5235_n227), .S(
DP_OP_501J223_127_5235_n160), .ICO(DP_OP_501J223_127_5235_n158), .CO(
DP_OP_501J223_127_5235_n159) );
NOR2X1TS U3931 ( .A(n2332), .B(n3692), .Y(DP_OP_501J223_127_5235_n203) );
INVX6TS U3932 ( .A(n3631), .Y(n3707) );
INVX4TS U3933 ( .A(n3658), .Y(n3708) );
ADDHX1TS U3934 ( .A(n3686), .B(n3685), .CO(n3680), .S(
DP_OP_501J223_127_5235_n190) );
ADDHX1TS U3935 ( .A(n3691), .B(n3690), .CO(DP_OP_501J223_127_5235_n193), .S(
n3687) );
ADDHX1TS U3936 ( .A(n3492), .B(n2205), .CO(n3493), .S(n3484) );
NAND2X4TS U3937 ( .A(n2196), .B(n3440), .Y(n3477) );
NOR2X2TS U3938 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .Y(n3542) );
AOI21X2TS U3939 ( .A0(n2456), .A1(n3473), .B0(n3472), .Y(n3540) );
INVX2TS U3940 ( .A(n3642), .Y(n3473) );
INVX2TS U3941 ( .A(n3536), .Y(n3472) );
NAND2X1TS U3942 ( .A(n2456), .B(n3643), .Y(n3541) );
NAND2X1TS U3943 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .Y(n3543) );
INVX2TS U3944 ( .A(n4288), .Y(n2318) );
INVX2TS U3945 ( .A(n4288), .Y(n2319) );
NAND2X1TS U3946 ( .A(n4293), .B(n4292), .Y(n4294) );
NOR2X1TS U3947 ( .A(n2239), .B(n4968), .Y(n4969) );
NOR2X1TS U3948 ( .A(n5446), .B(n5671), .Y(n4941) );
OR2X4TS U3949 ( .A(n2582), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]), .Y(
n2620) );
NAND2X1TS U3950 ( .A(n2599), .B(n2603), .Y(n2600) );
INVX2TS U3951 ( .A(n4199), .Y(n2638) );
OR2X1TS U3952 ( .A(n2700), .B(n2727), .Y(n2903) );
NOR2X6TS U3953 ( .A(n2642), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .Y(n2897)
);
NAND2X2TS U3954 ( .A(n2642), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .Y(n2898)
);
INVX4TS U3955 ( .A(n4197), .Y(n4213) );
NOR2XLTS U3956 ( .A(n4518), .B(n4371), .Y(n4373) );
NAND2X1TS U3957 ( .A(n3098), .B(n3103), .Y(n3099) );
OR2X1TS U3958 ( .A(n2721), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(n2722)
);
NAND2X1TS U3959 ( .A(n3054), .B(n3053), .Y(n3055) );
NOR2X4TS U3960 ( .A(n3062), .B(n3061), .Y(n4324) );
CLKAND2X2TS U3961 ( .A(n6863), .B(FPADDSUB_DMP_SFG[9]), .Y(n4384) );
OR2X1TS U3962 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n6031) );
OA21X1TS U3963 ( .A0(n4871), .A1(n4870), .B0(n4891), .Y(n5774) );
NAND2X1TS U3964 ( .A(n3323), .B(n3322), .Y(n3324) );
NAND2X1TS U3965 ( .A(n3234), .B(n3233), .Y(n3235) );
NAND2X1TS U3966 ( .A(n3256), .B(n3310), .Y(n3230) );
NAND2X1TS U3967 ( .A(n3352), .B(n3351), .Y(n3354) );
NAND2X1TS U3968 ( .A(n4205), .B(n4206), .Y(n3400) );
CMPR42X1TS U3969 ( .A(DP_OP_502J223_128_4510_n137), .B(
DP_OP_502J223_128_4510_n180), .C(DP_OP_502J223_128_4510_n187), .D(
DP_OP_502J223_128_4510_n134), .ICI(DP_OP_502J223_128_4510_n131), .S(
DP_OP_502J223_128_4510_n129), .ICO(DP_OP_502J223_128_4510_n127), .CO(
DP_OP_502J223_128_4510_n128) );
OR2X1TS U3970 ( .A(DP_OP_501J223_127_5235_n903), .B(n6955), .Y(n3372) );
INVX2TS U3971 ( .A(n3951), .Y(n3965) );
ADDFX2TS U3972 ( .A(n3927), .B(n3926), .CI(n3925), .CO(n3941), .S(n3940) );
XNOR2X2TS U3973 ( .A(n3634), .B(n3490), .Y(n3860) );
NAND2X1TS U3974 ( .A(n2454), .B(n3489), .Y(n3490) );
NAND2X1TS U3975 ( .A(n2444), .B(n3441), .Y(n3443) );
AO21XLTS U3976 ( .A0(n5693), .A1(n5691), .B0(n5692), .Y(n4865) );
AO21XLTS U3977 ( .A0(n5798), .A1(n5796), .B0(n5797), .Y(n4803) );
OAI21XLTS U3978 ( .A0(n5835), .A1(n5834), .B0(n5836), .Y(n4776) );
CMPR42X1TS U3979 ( .A(DP_OP_501J223_127_5235_n511), .B(
DP_OP_501J223_127_5235_n523), .C(DP_OP_501J223_127_5235_n517), .D(
DP_OP_501J223_127_5235_n482), .ICI(DP_OP_501J223_127_5235_n479), .S(
DP_OP_501J223_127_5235_n477), .ICO(DP_OP_501J223_127_5235_n475), .CO(
DP_OP_501J223_127_5235_n476) );
OAI22X1TS U3980 ( .A0(n3850), .A1(n3851), .B0(n2293), .B1(n3849), .Y(n3732)
);
ADDHX1TS U3981 ( .A(n3735), .B(n3734), .CO(n3738), .S(n3737) );
OAI22X1TS U3982 ( .A0(n2294), .A1(n3851), .B0(n2370), .B1(n3849), .Y(n3736)
);
INVX2TS U3983 ( .A(n3728), .Y(n3851) );
NOR2XLTS U3984 ( .A(n2325), .B(n3693), .Y(n3553) );
OR2X1TS U3985 ( .A(n2291), .B(FPMULT_Op_MY[12]), .Y(n4341) );
INVX4TS U3986 ( .A(n2237), .Y(n6585) );
NOR2X1TS U3987 ( .A(n4975), .B(n4973), .Y(n5443) );
NOR2X1TS U3988 ( .A(n4962), .B(n4963), .Y(n5444) );
OA21X1TS U3989 ( .A0(FPMULT_Op_MX[19]), .A1(n2315), .B0(n5445), .Y(n5440) );
NAND2X1TS U3990 ( .A(n5224), .B(n5220), .Y(n4808) );
NOR2BX1TS U3991 ( .AN(n2556), .B(n2555), .Y(n2557) );
NAND2BX1TS U3992 ( .AN(n2554), .B(n2553), .Y(n2555) );
AOI221X1TS U3993 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n2412), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n2430), .C0(n2569), .Y(n2571) );
NAND4XLTS U3994 ( .A(n6697), .B(n6696), .C(n6695), .D(n6694), .Y(n6698) );
AOI221X1TS U3995 ( .A0(n2432), .A1(FPADDSUB_intDY_EWSW[17]), .B0(
FPADDSUB_intDY_EWSW[24]), .B1(n6803), .C0(n6693), .Y(n6694) );
OAI221X1TS U3996 ( .A0(n2407), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n2269),
.B1(FPADDSUB_intDY_EWSW[7]), .C0(n6677), .Y(n6684) );
NAND2X1TS U3997 ( .A(n5978), .B(n5977), .Y(n5981) );
NAND2X1TS U3998 ( .A(n5976), .B(n5975), .Y(n5980) );
NAND2X1TS U3999 ( .A(n5984), .B(n5979), .Y(n6627) );
AOI31XLTS U4000 ( .A0(n6758), .A1(n6800), .A2(FPADDSUB_Raw_mant_NRM_SWR[15]),
.B0(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n5222) );
NAND2X4TS U4001 ( .A(n2623), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(n4221) );
NAND2X4TS U4002 ( .A(n2641), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(
n4216) );
NOR2X6TS U4003 ( .A(n2641), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(
n4215) );
INVX2TS U4004 ( .A(n2896), .Y(n4219) );
INVX4TS U4005 ( .A(n2406), .Y(n6579) );
OAI21XLTS U4006 ( .A0(n6213), .A1(n6198), .B0(n6197), .Y(n6203) );
OAI21XLTS U4007 ( .A0(n4519), .A1(n4518), .B0(n4517), .Y(n4522) );
MX2X1TS U4008 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
MX2X1TS U4009 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
MX2X1TS U4010 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
NOR2X1TS U4011 ( .A(n5882), .B(n5854), .Y(n5880) );
NAND3XLTS U4012 ( .A(n5757), .B(FPMULT_Op_MY[8]), .C(FPMULT_Op_MX[7]), .Y(
n5759) );
NAND2X4TS U4013 ( .A(n3249), .B(n4207), .Y(n4175) );
INVX2TS U4014 ( .A(n4196), .Y(DP_OP_499J223_125_1651_n292) );
AO21XLTS U4015 ( .A0(n5714), .A1(n5711), .B0(n5712), .Y(n4826) );
AO21XLTS U4016 ( .A0(n5816), .A1(n5817), .B0(n5818), .Y(n4764) );
AO21XLTS U4017 ( .A0(n5477), .A1(n5476), .B0(n5816), .Y(intadd_514_A_0_) );
AO21XLTS U4018 ( .A0(n5845), .A1(n5844), .B0(n5843), .Y(intadd_514_CI) );
OAI22X1TS U4019 ( .A0(n3965), .A1(n3974), .B0(n3964), .B1(n3639), .Y(n3972)
);
AO21XLTS U4020 ( .A0(n3968), .A1(n2394), .B0(n3966), .Y(n3971) );
OR2X1TS U4021 ( .A(n3974), .B(n3639), .Y(n2473) );
NAND2X1TS U4022 ( .A(n3958), .B(n3957), .Y(n3984) );
NAND2X1TS U4023 ( .A(n3944), .B(n3943), .Y(n3990) );
INVX2TS U4024 ( .A(n4000), .Y(n3994) );
INVX2TS U4025 ( .A(n3987), .Y(n4003) );
INVX2TS U4026 ( .A(n3993), .Y(n4001) );
CLKAND2X2TS U4027 ( .A(n2346), .B(n5642), .Y(intadd_513_A_7_) );
AO21XLTS U4028 ( .A0(n4925), .A1(n4926), .B0(n4924), .Y(n4426) );
NOR2X2TS U4029 ( .A(DP_OP_501J223_127_5235_n457), .B(
DP_OP_501J223_127_5235_n463), .Y(n3789) );
NAND2X1TS U4030 ( .A(DP_OP_501J223_127_5235_n457), .B(
DP_OP_501J223_127_5235_n463), .Y(n3790) );
NAND2X1TS U4031 ( .A(DP_OP_501J223_127_5235_n477), .B(n3741), .Y(n3804) );
NAND2X1TS U4032 ( .A(n3739), .B(n3738), .Y(n3806) );
OAI21X1TS U4033 ( .A0(n3809), .A1(n3856), .B0(n3810), .Y(n3807) );
NAND2X1TS U4034 ( .A(n3737), .B(n3736), .Y(n3810) );
INVX2TS U4035 ( .A(n3554), .Y(n3557) );
OAI21X1TS U4036 ( .A0(n3574), .A1(n3565), .B0(n3566), .Y(n3548) );
NAND2X2TS U4037 ( .A(DP_OP_501J223_127_5235_n129), .B(
DP_OP_501J223_127_5235_n125), .Y(n3579) );
NAND2X4TS U4038 ( .A(DP_OP_501J223_127_5235_n144), .B(
DP_OP_501J223_127_5235_n153), .Y(n3595) );
NAND2X2TS U4039 ( .A(DP_OP_501J223_127_5235_n136), .B(
DP_OP_501J223_127_5235_n143), .Y(n3590) );
INVX2TS U4040 ( .A(n3604), .Y(n3502) );
NAND2X2TS U4041 ( .A(DP_OP_501J223_127_5235_n154), .B(
DP_OP_501J223_127_5235_n162), .Y(n3600) );
NAND2X2TS U4042 ( .A(DP_OP_501J223_127_5235_n181), .B(
DP_OP_501J223_127_5235_n187), .Y(n3612) );
OAI21X2TS U4043 ( .A0(n3615), .A1(n3618), .B0(n3616), .Y(n3613) );
NAND2X1TS U4044 ( .A(n3497), .B(n3496), .Y(n3620) );
ADDHX1TS U4045 ( .A(n3495), .B(n3494), .CO(n3688), .S(n3623) );
INVX2TS U4046 ( .A(n2253), .Y(n2332) );
INVX2TS U4047 ( .A(n3466), .Y(n3705) );
NAND2X2TS U4048 ( .A(n5143), .B(n6022), .Y(n6626) );
AND2X2TS U4049 ( .A(n2720), .B(n2734), .Y(n6275) );
OR2X1TS U4050 ( .A(n2719), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .Y(n2720) );
XOR2X2TS U4051 ( .A(n2735), .B(n2734), .Y(n6276) );
NAND2X2TS U4052 ( .A(n2733), .B(n2732), .Y(n2735) );
XNOR2X1TS U4053 ( .A(n4224), .B(n4223), .Y(n6274) );
NAND2X1TS U4054 ( .A(n4222), .B(n4221), .Y(n4224) );
INVX2TS U4055 ( .A(rst), .Y(n4491) );
OAI21XLTS U4056 ( .A0(n4581), .A1(n5456), .B0(n4673), .Y(operation_ready) );
MX2X1TS U4057 ( .A(Data_2[5]), .B(FPMULT_Op_MY[5]), .S0(n2350), .Y(n1631) );
MX2X1TS U4058 ( .A(Data_2[12]), .B(n5650), .S0(n2350), .Y(n1638) );
MX2X1TS U4059 ( .A(Data_2[22]), .B(n2383), .S0(n2350), .Y(n1648) );
MX2X1TS U4060 ( .A(Data_2[21]), .B(n2228), .S0(n2350), .Y(n1647) );
MX2X1TS U4061 ( .A(Data_1[11]), .B(n2403), .S0(n5934), .Y(n1669) );
MX2X1TS U4062 ( .A(Data_1[22]), .B(FPMULT_Op_MX[22]), .S0(n5639), .Y(n1680)
);
MX2X1TS U4063 ( .A(Data_2[10]), .B(n2201), .S0(n2350), .Y(n1636) );
MX2X1TS U4064 ( .A(Data_2[2]), .B(FPMULT_Op_MY[2]), .S0(n2349), .Y(n1628) );
MX2X1TS U4065 ( .A(Data_2[16]), .B(FPMULT_Op_MY[16]), .S0(n2369), .Y(n1642)
);
MX2X1TS U4066 ( .A(Data_2[18]), .B(n6749), .S0(n2349), .Y(n1644) );
MX2X1TS U4067 ( .A(Data_1[21]), .B(FPMULT_Op_MX[21]), .S0(n5639), .Y(n1679)
);
MX2X1TS U4068 ( .A(Data_1[8]), .B(FPMULT_Op_MX[8]), .S0(n5639), .Y(n1666) );
MX2X1TS U4069 ( .A(Data_1[12]), .B(FPMULT_Op_MX[12]), .S0(n2350), .Y(n1670)
);
MX2X1TS U4070 ( .A(Data_1[17]), .B(FPMULT_Op_MX[17]), .S0(n5934), .Y(n1675)
);
MX2X1TS U4071 ( .A(Data_2[9]), .B(n5643), .S0(n2350), .Y(n1635) );
MX2X1TS U4072 ( .A(Data_2[11]), .B(n5642), .S0(n5645), .Y(n1637) );
AOI21X1TS U4073 ( .A0(n3771), .A1(n3767), .B0(n3766), .Y(n3768) );
NAND2X1TS U4074 ( .A(n3770), .B(n3767), .Y(n3769) );
NOR2X1TS U4075 ( .A(n3763), .B(n3765), .Y(n3767) );
AO21XLTS U4076 ( .A0(FPADDSUB_LZD_output_NRM2_EW[0]), .A1(n7059), .B0(n6016),
.Y(n1314) );
MX2X1TS U4077 ( .A(Data_2[24]), .B(FPMULT_Op_MY[24]), .S0(n5641), .Y(n1650)
);
MX2X1TS U4078 ( .A(Data_2[25]), .B(FPMULT_Op_MY[25]), .S0(n5641), .Y(n1651)
);
MX2X1TS U4079 ( .A(Data_2[27]), .B(FPMULT_Op_MY[27]), .S0(n6606), .Y(n1653)
);
MX2X1TS U4080 ( .A(FPMULT_Exp_module_Data_S[5]), .B(
FPMULT_exp_oper_result[5]), .S0(n5933), .Y(n1589) );
MX2X1TS U4081 ( .A(FPMULT_Exp_module_Data_S[0]), .B(
FPMULT_exp_oper_result[0]), .S0(n5933), .Y(n1594) );
MX2X1TS U4082 ( .A(Data_2[26]), .B(FPMULT_Op_MY[26]), .S0(n5934), .Y(n1652)
);
MX2X1TS U4083 ( .A(Data_1[29]), .B(FPMULT_Op_MX[29]), .S0(n2349), .Y(n1687)
);
MX2X1TS U4084 ( .A(Data_1[26]), .B(FPMULT_Op_MX[26]), .S0(n5641), .Y(n1684)
);
NOR3BXLTS U4085 ( .AN(begin_operation), .B(n6342), .C(n6341), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
MX2X1TS U4086 ( .A(FPMULT_P_Sgf[4]), .B(FPMULT_Sgf_operation_Result[4]),
.S0(n2284), .Y(n1533) );
MX2X1TS U4087 ( .A(FPMULT_P_Sgf[12]), .B(n6273), .S0(n6958), .Y(n1541) );
MX2X1TS U4088 ( .A(FPMULT_P_Sgf[16]), .B(n6258), .S0(n6957), .Y(n1545) );
MX2X1TS U4089 ( .A(FPMULT_P_Sgf[5]), .B(n6259), .S0(n6956), .Y(n1534) );
MX2X1TS U4090 ( .A(FPMULT_P_Sgf[10]), .B(n6262), .S0(n6956), .Y(n1539) );
MX2X1TS U4091 ( .A(FPMULT_P_Sgf[3]), .B(FPMULT_Sgf_operation_Result[3]),
.S0(n6958), .Y(n1532) );
MX2X1TS U4092 ( .A(FPMULT_P_Sgf[14]), .B(n6268), .S0(n6957), .Y(n1543) );
XOR2XLTS U4093 ( .A(n6213), .B(n6212), .Y(n6220) );
AOI222X1TS U4094 ( .A0(n4984), .A1(cordic_result[22]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[22]), .C0(n4985), .C1(FPSENCOS_d_ff_Yn[22]), .Y(n5166) );
AOI222X1TS U4095 ( .A0(n5167), .A1(cordic_result[15]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[15]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[15]), .Y(n5130) );
AOI222X1TS U4096 ( .A0(n5167), .A1(cordic_result[18]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[18]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[18]), .Y(n5134) );
AOI222X1TS U4097 ( .A0(n4984), .A1(cordic_result[21]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[21]), .C0(n4985), .C1(FPSENCOS_d_ff_Yn[21]), .Y(n5170) );
AOI222X1TS U4098 ( .A0(n5141), .A1(cordic_result[4]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[4]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[4]), .Y(n5131)
);
AOI222X1TS U4099 ( .A0(n5141), .A1(cordic_result[6]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[6]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[6]), .Y(n5135)
);
MX2X1TS U4100 ( .A(n6943), .B(n6942), .S0(n6941), .Y(n1575) );
MX2X1TS U4101 ( .A(FPMULT_P_Sgf[17]), .B(n6245), .S0(n6958), .Y(n1546) );
MX2X1TS U4102 ( .A(FPMULT_P_Sgf[15]), .B(n6249), .S0(n6957), .Y(n1544) );
MX2X1TS U4103 ( .A(Data_2[29]), .B(FPMULT_Op_MY[29]), .S0(n5641), .Y(n1655)
);
NAND2BXLTS U4104 ( .AN(n6352), .B(n6351), .Y(n2191) );
MX2X1TS U4105 ( .A(Data_1[24]), .B(FPMULT_Op_MX[24]), .S0(n5934), .Y(n1682)
);
MX2X1TS U4106 ( .A(Data_1[25]), .B(FPMULT_Op_MX[25]), .S0(n6606), .Y(n1683)
);
MX2X1TS U4107 ( .A(Data_1[27]), .B(FPMULT_Op_MX[27]), .S0(n2369), .Y(n1685)
);
CLKAND2X2TS U4108 ( .A(n4461), .B(n4460), .Y(n2427) );
XOR2XLTS U4109 ( .A(n4514), .B(n4513), .Y(n4516) );
MX2X1TS U4110 ( .A(Data_2[8]), .B(n5644), .S0(n2350), .Y(n1634) );
MX2X1TS U4111 ( .A(FPMULT_FSM_add_overflow_flag), .B(n5932), .S0(n5931), .Y(
n1596) );
AOI222X1TS U4112 ( .A0(n5167), .A1(cordic_result[16]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[16]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[16]), .Y(n5138) );
AOI222X1TS U4113 ( .A0(n5167), .A1(cordic_result[13]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[13]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[13]), .Y(n5132) );
MX2X1TS U4114 ( .A(FPMULT_P_Sgf[13]), .B(n6241), .S0(n2284), .Y(n1542) );
MX2X1TS U4115 ( .A(FPMULT_P_Sgf[9]), .B(n6261), .S0(n6957), .Y(n1538) );
MX2X1TS U4116 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_Sgf_operation_Result[1]),
.S0(n6958), .Y(n1530) );
MX2X1TS U4117 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(n6713), .Y(n1443) );
MX2X1TS U4118 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1433) );
MX2X1TS U4119 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(n2340), .Y(n1423) );
MX2X1TS U4120 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1438) );
MX2X1TS U4121 ( .A(FPMULT_P_Sgf[19]), .B(n6298), .S0(n6290), .Y(n1548) );
MX2X1TS U4122 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(n6713), .Y(n1418) );
OAI21XLTS U4123 ( .A0(n5265), .A1(n2356), .B0(n2336), .Y(n2078) );
MX2X1TS U4124 ( .A(Data_2[23]), .B(FPMULT_Op_MY[23]), .S0(n5934), .Y(n1649)
);
MX2X1TS U4125 ( .A(FPMULT_Exp_module_Data_S[1]), .B(
FPMULT_exp_oper_result[1]), .S0(n5933), .Y(n1593) );
MX2X1TS U4126 ( .A(FPMULT_Exp_module_Data_S[2]), .B(
FPMULT_exp_oper_result[2]), .S0(n5933), .Y(n1592) );
MX2X1TS U4127 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_exp_oper_result[3]), .S0(n5933), .Y(n1591) );
MX2X1TS U4128 ( .A(FPMULT_Exp_module_Data_S[4]), .B(
FPMULT_exp_oper_result[4]), .S0(n5933), .Y(n1590) );
MX2X1TS U4129 ( .A(Data_2[28]), .B(FPMULT_Op_MY[28]), .S0(n6606), .Y(n1654)
);
MX2X1TS U4130 ( .A(Data_1[23]), .B(FPMULT_Op_MX[23]), .S0(n5934), .Y(n1681)
);
MX2X1TS U4131 ( .A(Data_2[30]), .B(FPMULT_Op_MY[30]), .S0(n5641), .Y(n1656)
);
MX2X1TS U4132 ( .A(FPADDSUB_OP_FLAG_SFG), .B(FPADDSUB_OP_FLAG_SHT2), .S0(
n6014), .Y(n1352) );
MX2X1TS U4133 ( .A(FPMULT_P_Sgf[24]), .B(n5922), .S0(n6957), .Y(n1553) );
XOR2XLTS U4134 ( .A(n4519), .B(n4506), .Y(n4510) );
MX2X1TS U4135 ( .A(Data_1[30]), .B(FPMULT_Op_MX[30]), .S0(n5934), .Y(n1688)
);
MX2X1TS U4136 ( .A(Data_1[28]), .B(FPMULT_Op_MX[28]), .S0(n5641), .Y(n1686)
);
CLKMX2X2TS U4137 ( .A(FPMULT_P_Sgf[33]), .B(n4449), .S0(n6956), .Y(n1562) );
MX2X1TS U4138 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1448) );
MX2X1TS U4139 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1428) );
AO21XLTS U4140 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_6), .A1(n6353), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .Y(n2148) );
AO21XLTS U4141 ( .A0(n2299), .A1(n6344), .B0(n6343), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
XOR2XLTS U4142 ( .A(n6083), .B(n6082), .Y(n6088) );
XOR2XLTS U4143 ( .A(n6229), .B(n6228), .Y(n6236) );
CLKAND2X2TS U4144 ( .A(n6335), .B(n6355), .Y(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
AOI32X1TS U4145 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[2]), .A1(n5265), .A2(
n7059), .B0(FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n5379), .Y(n4819)
);
MX2X1TS U4146 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DMP_SHT2_EWSW[22]),
.S0(n6624), .Y(n1206) );
MX2X1TS U4147 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DMP_SHT2_EWSW[16]),
.S0(n5962), .Y(n1246) );
MX2X1TS U4148 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DMP_SHT2_EWSW[14]),
.S0(n6014), .Y(n1258) );
MX2X1TS U4149 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DMP_SHT2_EWSW[20]),
.S0(n5937), .Y(n1226) );
MX2X1TS U4150 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DMP_SHT2_EWSW[18]),
.S0(n6009), .Y(n1214) );
MX2X1TS U4151 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DMP_SHT2_EWSW[13]),
.S0(n6624), .Y(n1242) );
MX2X1TS U4152 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DMP_SHT2_EWSW[17]),
.S0(n6624), .Y(n1230) );
MX2X1TS U4153 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DMP_SHT2_EWSW[19]),
.S0(n6710), .Y(n1222) );
MX2X1TS U4154 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DMP_SHT2_EWSW[21]),
.S0(n6014), .Y(n1218) );
MX2X1TS U4155 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DMP_SHT2_EWSW[15]),
.S0(n6624), .Y(n1210) );
MX2X1TS U4156 ( .A(FPADDSUB_Raw_mant_NRM_SWR[0]), .B(
FPADDSUB_DmP_mant_SFG_SWR[0]), .S0(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(
n1349) );
MX2X1TS U4157 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DMP_SHT2_EWSW[12]),
.S0(n6624), .Y(n1266) );
MX2X1TS U4158 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DMP_SHT2_EWSW[11]),
.S0(n6624), .Y(n1254) );
MX2X1TS U4159 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DMP_SHT2_EWSW[10]),
.S0(n6624), .Y(n1262) );
XOR2XLTS U4160 ( .A(n6185), .B(n6184), .Y(n6194) );
MX2X1TS U4161 ( .A(Data_1[16]), .B(FPMULT_Op_MX[16]), .S0(n5641), .Y(n1674)
);
MX2X1TS U4162 ( .A(Data_1[6]), .B(FPMULT_Op_MX[6]), .S0(n5934), .Y(n1664) );
MX2X1TS U4163 ( .A(Data_2[17]), .B(n5648), .S0(n2349), .Y(n1643) );
MX2X1TS U4164 ( .A(Data_1[3]), .B(FPMULT_Op_MX[3]), .S0(n6606), .Y(n1661) );
MX2X1TS U4165 ( .A(Data_1[20]), .B(FPMULT_Op_MX[20]), .S0(n5641), .Y(n1678)
);
MX2X1TS U4166 ( .A(Data_1[15]), .B(FPMULT_Op_MX[15]), .S0(n6606), .Y(n1673)
);
MX2X1TS U4167 ( .A(Data_1[4]), .B(FPMULT_Op_MX[4]), .S0(n5641), .Y(n1662) );
MX2X1TS U4168 ( .A(Data_1[18]), .B(n5640), .S0(n6606), .Y(n1676) );
MX2X1TS U4169 ( .A(FPMULT_Add_result[12]), .B(n5879), .S0(n5899), .Y(n1608)
);
XOR2XLTS U4170 ( .A(n5500), .B(n5499), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9) );
XOR2X1TS U4171 ( .A(n3787), .B(n3786), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7) );
NAND2X1TS U4172 ( .A(n3785), .B(n3784), .Y(n3786) );
XOR2X1TS U4173 ( .A(n3598), .B(n3597), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8) );
NAND2X1TS U4174 ( .A(n3596), .B(n3595), .Y(n3598) );
INVX2TS U4175 ( .A(n3594), .Y(n3596) );
MX2X1TS U4176 ( .A(Data_1[0]), .B(FPMULT_Op_MX[0]), .S0(n5934), .Y(n1658) );
XOR2XLTS U4177 ( .A(n6093), .B(n6092), .Y(n6098) );
XOR2XLTS U4178 ( .A(n6045), .B(n6044), .Y(n6050) );
MX2X1TS U4179 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DMP_SHT2_EWSW[0]), .S0(
n6014), .Y(n1293) );
MX2X1TS U4180 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DMP_SHT2_EWSW[1]), .S0(
n6014), .Y(n1286) );
MX2X1TS U4181 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DMP_SHT2_EWSW[2]), .S0(
n6014), .Y(n1307) );
MX2X1TS U4182 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DMP_SHT2_EWSW[3]), .S0(
n6014), .Y(n1323) );
MX2X1TS U4183 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DMP_SHT2_EWSW[4]), .S0(
n6014), .Y(n1234) );
MX2X1TS U4184 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DMP_SHT2_EWSW[5]), .S0(
n6014), .Y(n1272) );
MX2X1TS U4185 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DMP_SHT2_EWSW[6]), .S0(
n5937), .Y(n1238) );
MX2X1TS U4186 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DMP_SHT2_EWSW[7]), .S0(
n5937), .Y(n1300) );
MX2X1TS U4187 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DMP_SHT2_EWSW[8]), .S0(
n5937), .Y(n1250) );
MX2X1TS U4188 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DMP_SHT2_EWSW[9]), .S0(
n5937), .Y(n1279) );
AO21X1TS U4189 ( .A0(result_add_subt[7]), .A1(n6354), .B0(n4276), .Y(n1306)
);
AO21X1TS U4190 ( .A0(result_add_subt[6]), .A1(n6354), .B0(n4282), .Y(n1384)
);
MX2X1TS U4191 ( .A(FPMULT_Add_result[20]), .B(n5861), .S0(n5873), .Y(n1600)
);
XOR2XLTS U4192 ( .A(n6128), .B(n6127), .Y(n6133) );
MX2X1TS U4193 ( .A(FPMULT_Add_result[19]), .B(n5863), .S0(n5873), .Y(n1601)
);
XOR2XLTS U4194 ( .A(n6118), .B(n6117), .Y(n6123) );
MX2X1TS U4195 ( .A(FPMULT_Add_result[18]), .B(n5865), .S0(n5873), .Y(n1602)
);
MX2X1TS U4196 ( .A(FPMULT_Add_result[17]), .B(n5867), .S0(n5873), .Y(n1603)
);
MX2X1TS U4197 ( .A(FPMULT_Add_result[16]), .B(n5869), .S0(n5873), .Y(n1604)
);
MX2X1TS U4198 ( .A(FPMULT_Add_result[15]), .B(n5871), .S0(n5873), .Y(n1605)
);
MX2X1TS U4199 ( .A(FPMULT_Add_result[7]), .B(n5893), .S0(n5899), .Y(n1613)
);
OAI31X1TS U4200 ( .A0(n6360), .A1(FPSENCOS_cont_var_out[1]), .A2(n6756),
.B0(n4553), .Y(n2136) );
MX2X1TS U4201 ( .A(FPMULT_Add_result[14]), .B(n5874), .S0(n5931), .Y(n1606)
);
MX2X1TS U4202 ( .A(FPMULT_Add_result[6]), .B(n5895), .S0(n5931), .Y(n1614)
);
MX2X1TS U4203 ( .A(FPMULT_Add_result[13]), .B(n5877), .S0(n5931), .Y(n1607)
);
MX2X1TS U4204 ( .A(FPMULT_Add_result[10]), .B(n5885), .S0(n5899), .Y(n1610)
);
MX2X1TS U4205 ( .A(FPMULT_Add_result[9]), .B(n5887), .S0(n5931), .Y(n1611)
);
MX2X1TS U4206 ( .A(FPMULT_Add_result[5]), .B(n5897), .S0(n5899), .Y(n1615)
);
MX2X1TS U4207 ( .A(FPMULT_Add_result[8]), .B(n5889), .S0(n5899), .Y(n1612)
);
MX2X1TS U4208 ( .A(FPMULT_Add_result[11]), .B(n5881), .S0(n5899), .Y(n1609)
);
MX2X1TS U4209 ( .A(FPMULT_Add_result[4]), .B(n5900), .S0(n5899), .Y(n1616)
);
MX2X1TS U4210 ( .A(FPMULT_Add_result[3]), .B(n5907), .S0(n5899), .Y(n1617)
);
INVX2TS U4211 ( .A(n5915), .Y(n5905) );
MX2X1TS U4212 ( .A(FPMULT_Add_result[1]), .B(n5923), .S0(n5899), .Y(n1619)
);
MX2X1TS U4213 ( .A(FPMULT_Add_result[2]), .B(n5916), .S0(n5931), .Y(n1618)
);
OR2X1TS U4214 ( .A(n5758), .B(n5777), .Y(intadd_513_B_1_) );
OAI21XLTS U4215 ( .A0(n6765), .A1(n6794), .B0(n5757), .Y(n5473) );
CLKAND2X2TS U4216 ( .A(n5679), .B(n5678), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2) );
OAI21XLTS U4217 ( .A0(n2478), .A1(n5677), .B0(n5676), .Y(n5678) );
NAND2X1TS U4218 ( .A(n3981), .B(n3980), .Y(n3982) );
NAND4XLTS U4219 ( .A(n7071), .B(n7070), .C(n7069), .D(n6331), .Y(n6333) );
NAND3XLTS U4220 ( .A(n2299), .B(n6373), .C(n6372), .Y(n6359) );
INVX2TS U4221 ( .A(n4209), .Y(n3348) );
NAND2X1TS U4222 ( .A(n4176), .B(n4175), .Y(n4177) );
AOI21X1TS U4223 ( .A0(n4181), .A1(n4174), .B0(n4173), .Y(n4178) );
XOR2X1TS U4224 ( .A(n4194), .B(n4193), .Y(FPMULT_Sgf_operation_Result[32])
);
NAND2X1TS U4225 ( .A(n4192), .B(n4191), .Y(n4193) );
AOI21X1TS U4226 ( .A0(n4457), .A1(n4331), .B0(n4189), .Y(n4194) );
XOR2X1TS U4227 ( .A(n3411), .B(n3410), .Y(FPMULT_Sgf_operation_Result[39])
);
AOI21X1TS U4228 ( .A0(n2375), .A1(n3409), .B0(n3408), .Y(n3411) );
AOI21X1TS U4229 ( .A0(n4181), .A1(n3425), .B0(n3424), .Y(n3426) );
AOI21X1TS U4230 ( .A0(n2375), .A1(n3429), .B0(n3337), .Y(n3430) );
NAND2X1TS U4231 ( .A(n4184), .B(n4183), .Y(n4185) );
AOI21X1TS U4232 ( .A0(n2375), .A1(n4335), .B0(n4180), .Y(n4186) );
XOR2X1TS U4233 ( .A(n3405), .B(DP_OP_499J223_125_1651_n296), .Y(
FPMULT_Sgf_operation_Result[41]) );
XOR2XLTS U4234 ( .A(n5516), .B(n5515), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6) );
CLKAND2X2TS U4235 ( .A(n5467), .B(n5466), .Y(n6827) );
XNOR2X1TS U4236 ( .A(n3978), .B(n3977), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13) );
NAND2X1TS U4237 ( .A(n2474), .B(n3976), .Y(n3977) );
NAND2X1TS U4238 ( .A(n3975), .B(n2473), .Y(n3976) );
XNOR2X1TS U4239 ( .A(n3986), .B(n3985), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11) );
NAND2X1TS U4240 ( .A(n2475), .B(n3984), .Y(n3985) );
NAND2X1TS U4241 ( .A(n2476), .B(n3990), .Y(n3991) );
AOI21X1TS U4242 ( .A0(n4003), .A1(n3989), .B0(n3988), .Y(n3992) );
XOR2X1TS U4243 ( .A(n3999), .B(n3998), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9) );
NAND2X1TS U4244 ( .A(n3997), .B(n3996), .Y(n3998) );
AOI21X1TS U4245 ( .A0(n4003), .A1(n4001), .B0(n3994), .Y(n3999) );
INVX2TS U4246 ( .A(n3995), .Y(n3997) );
XNOR2X1TS U4247 ( .A(n4003), .B(n4002), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8) );
NAND2X1TS U4248 ( .A(n4001), .B(n4000), .Y(n4002) );
XNOR2X1TS U4249 ( .A(n4009), .B(n4008), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7) );
INVX2TS U4250 ( .A(n4005), .Y(n4007) );
OAI22X1TS U4251 ( .A0(n3883), .A1(DP_OP_501J223_127_5235_n723), .B0(n3901),
.B1(n3882), .Y(n4017) );
CLKAND2X2TS U4252 ( .A(n2489), .B(n4029), .Y(n2490) );
OAI21XLTS U4253 ( .A0(n2484), .A1(n2469), .B0(n5735), .Y(n5474) );
OAI21XLTS U4254 ( .A0(n7062), .A1(n2482), .B0(n5838), .Y(n5475) );
XNOR2X1TS U4255 ( .A(n3762), .B(n3761), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10) );
NAND2X1TS U4256 ( .A(n3760), .B(n3764), .Y(n3761) );
NAND2X1TS U4257 ( .A(n3775), .B(n3774), .Y(n3776) );
INVX2TS U4258 ( .A(n3770), .Y(n3773) );
XNOR2X1TS U4259 ( .A(n3782), .B(n3781), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8) );
NAND2X1TS U4260 ( .A(n3780), .B(n3779), .Y(n3781) );
INVX2TS U4261 ( .A(n3778), .Y(n3780) );
XNOR2X1TS U4262 ( .A(n3793), .B(n3792), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6) );
NAND2X1TS U4263 ( .A(n3791), .B(n3790), .Y(n3792) );
INVX2TS U4264 ( .A(n3789), .Y(n3791) );
XOR2X1TS U4265 ( .A(n3798), .B(n3797), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5) );
INVX2TS U4266 ( .A(n3794), .Y(n3796) );
XOR2X1TS U4267 ( .A(n3803), .B(n3802), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4) );
NAND2X1TS U4268 ( .A(n3801), .B(n3800), .Y(n3803) );
XNOR2X1TS U4269 ( .A(n3805), .B(n2426), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3) );
NAND2X1TS U4270 ( .A(n2494), .B(n3804), .Y(n3805) );
XNOR2X1TS U4271 ( .A(n3808), .B(n3807), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2) );
NAND2X1TS U4272 ( .A(n2500), .B(n3806), .Y(n3808) );
XOR2X1TS U4273 ( .A(n3812), .B(n3856), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1) );
NAND2X1TS U4274 ( .A(n3811), .B(n3810), .Y(n3812) );
INVX2TS U4275 ( .A(n3809), .Y(n3811) );
CLKAND2X2TS U4276 ( .A(n2492), .B(n3856), .Y(n2493) );
INVX2TS U4277 ( .A(n3565), .Y(n3567) );
NAND2X1TS U4278 ( .A(n3575), .B(n3574), .Y(n3576) );
INVX2TS U4279 ( .A(n3570), .Y(n3573) );
NAND2X1TS U4280 ( .A(n3580), .B(n3579), .Y(n3581) );
INVX2TS U4281 ( .A(n3578), .Y(n3580) );
NAND2X1TS U4282 ( .A(n3585), .B(n3584), .Y(n3586) );
INVX2TS U4283 ( .A(n3583), .Y(n3585) );
XNOR2X1TS U4284 ( .A(n3593), .B(n3592), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9) );
NAND2X1TS U4285 ( .A(n3591), .B(n3590), .Y(n3592) );
INVX2TS U4286 ( .A(n3589), .Y(n3591) );
XOR2X1TS U4287 ( .A(n3603), .B(n3602), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7) );
NAND2X1TS U4288 ( .A(n3601), .B(n3600), .Y(n3603) );
INVX2TS U4289 ( .A(n3599), .Y(n3601) );
XNOR2X1TS U4290 ( .A(n3606), .B(n3605), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6) );
XOR2X1TS U4291 ( .A(n3611), .B(n3610), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5) );
NAND2X1TS U4292 ( .A(n3609), .B(n3608), .Y(n3611) );
INVX2TS U4293 ( .A(n3607), .Y(n3609) );
XNOR2X1TS U4294 ( .A(n3614), .B(n3613), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4) );
NAND2X1TS U4295 ( .A(n2499), .B(n3612), .Y(n3614) );
XOR2X1TS U4296 ( .A(n3619), .B(n3618), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3) );
NAND2X1TS U4297 ( .A(n3617), .B(n3616), .Y(n3619) );
XNOR2X1TS U4298 ( .A(n3622), .B(n3621), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2) );
NAND2X1TS U4299 ( .A(n2495), .B(n3620), .Y(n3622) );
CLKAND2X2TS U4300 ( .A(n2496), .B(n3859), .Y(n2497) );
OAI21XLTS U4301 ( .A0(n5573), .A1(n5200), .B0(n5199), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13) );
CLKAND2X2TS U4302 ( .A(n5471), .B(n5470), .Y(n6828) );
AO21XLTS U4303 ( .A0(n4474), .A1(n5672), .B0(n4937), .Y(intadd_515_B_1_) );
AO22XLTS U4304 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1207) );
AO22XLTS U4305 ( .A0(n6744), .A1(FPADDSUB_DMP_EXP_EWSW[22]), .B0(n6743),
.B1(FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1208) );
AO22XLTS U4306 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1211) );
AO22XLTS U4307 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[15]), .B0(n6738),
.B1(FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1212) );
AO22XLTS U4308 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n6740),
.B1(FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1215) );
AO22XLTS U4309 ( .A0(n6739), .A1(FPADDSUB_DMP_EXP_EWSW[18]), .B0(n6741),
.B1(FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n1216) );
AO22XLTS U4310 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1219) );
AO22XLTS U4311 ( .A0(n6739), .A1(FPADDSUB_DMP_EXP_EWSW[21]), .B0(n6741),
.B1(FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1220) );
AO22XLTS U4312 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1223) );
AO22XLTS U4313 ( .A0(n6739), .A1(FPADDSUB_DMP_EXP_EWSW[19]), .B0(n6741),
.B1(FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n1224) );
AO22XLTS U4314 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n6740),
.B1(FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1227) );
AO22XLTS U4315 ( .A0(n6739), .A1(FPADDSUB_DMP_EXP_EWSW[20]), .B0(n6741),
.B1(FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1228) );
AO22XLTS U4316 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1231) );
AO22XLTS U4317 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[17]), .B0(n6736),
.B1(FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1232) );
AO22XLTS U4318 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[4]), .B0(
FPADDSUB_DMP_SHT2_EWSW[4]), .B1(n6733), .Y(n6907) );
AO22XLTS U4319 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[4]), .B0(n6736), .B1(
FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1236) );
AO22XLTS U4320 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[6]), .B0(
FPADDSUB_DMP_SHT2_EWSW[6]), .B1(n6733), .Y(n6908) );
AO22XLTS U4321 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[6]), .B0(n6736), .B1(
FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1240) );
AO22XLTS U4322 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1243) );
AO22XLTS U4323 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[13]), .B0(n6736),
.B1(FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1244) );
AO22XLTS U4324 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n6735),
.B1(FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1247) );
AO22XLTS U4325 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[16]), .B0(n6736),
.B1(FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n1248) );
AO22XLTS U4326 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1251) );
AO22XLTS U4327 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[8]), .B0(n6736), .B1(
FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1252) );
AO22XLTS U4328 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1255) );
AO22XLTS U4329 ( .A0(n6734), .A1(FPADDSUB_DMP_EXP_EWSW[11]), .B0(n6736),
.B1(FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1256) );
AO22XLTS U4330 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n6735),
.B1(FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1259) );
AO22XLTS U4331 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[14]), .B0(n6736),
.B1(FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1260) );
AO22XLTS U4332 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n6733),
.B1(FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1263) );
AO22XLTS U4333 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[10]), .B0(n6736),
.B1(FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1264) );
AO22XLTS U4334 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n6733),
.B1(FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1267) );
AO22XLTS U4335 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[12]), .B0(n6732),
.B1(FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1268) );
AO22XLTS U4336 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[5]), .B0(
FPADDSUB_DMP_SHT2_EWSW[5]), .B1(n6733), .Y(n6909) );
AO22XLTS U4337 ( .A0(n6734), .A1(FPADDSUB_DMP_EXP_EWSW[5]), .B0(n6732), .B1(
FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1274) );
AO22XLTS U4338 ( .A0(n6734), .A1(FPADDSUB_DmP_EXP_EWSW[5]), .B0(n6732), .B1(
FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1276) );
AO22XLTS U4339 ( .A0(n7077), .A1(FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1280) );
AO22XLTS U4340 ( .A0(n6734), .A1(FPADDSUB_DMP_EXP_EWSW[9]), .B0(n6732), .B1(
FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1281) );
AO22XLTS U4341 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[1]), .B0(
FPADDSUB_DMP_SHT2_EWSW[1]), .B1(n6740), .Y(n6910) );
AO22XLTS U4342 ( .A0(n6734), .A1(FPADDSUB_DMP_EXP_EWSW[1]), .B0(n6732), .B1(
FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1288) );
AO22XLTS U4343 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[0]), .B0(
FPADDSUB_DMP_SHT2_EWSW[0]), .B1(n6740), .Y(n6911) );
AO22XLTS U4344 ( .A0(n6734), .A1(FPADDSUB_DMP_EXP_EWSW[0]), .B0(n6732), .B1(
FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1295) );
AO22XLTS U4345 ( .A0(n6734), .A1(FPADDSUB_DmP_EXP_EWSW[0]), .B0(n6732), .B1(
FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1297) );
AO22XLTS U4346 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[7]), .B0(
FPADDSUB_DMP_SHT2_EWSW[7]), .B1(n6733), .Y(n6912) );
AO22XLTS U4347 ( .A0(n6734), .A1(FPADDSUB_DMP_EXP_EWSW[7]), .B0(n6732), .B1(
FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1302) );
AO22XLTS U4348 ( .A0(n6734), .A1(FPADDSUB_DmP_EXP_EWSW[7]), .B0(n6732), .B1(
FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1304) );
AO22XLTS U4349 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[2]), .B0(
FPADDSUB_DMP_SHT2_EWSW[2]), .B1(n6740), .Y(n6913) );
AO22XLTS U4350 ( .A0(n6734), .A1(FPADDSUB_DMP_EXP_EWSW[2]), .B0(n6732), .B1(
FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1309) );
AO22XLTS U4351 ( .A0(n6744), .A1(FPADDSUB_DmP_EXP_EWSW[2]), .B0(n6743), .B1(
FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1311) );
AO22XLTS U4352 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[3]), .B0(
FPADDSUB_DMP_SHT2_EWSW[3]), .B1(n6740), .Y(n6914) );
AO22XLTS U4353 ( .A0(n6744), .A1(FPADDSUB_DMP_EXP_EWSW[3]), .B0(n6743), .B1(
FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1325) );
AO22XLTS U4354 ( .A0(n6744), .A1(FPADDSUB_DmP_EXP_EWSW[3]), .B0(n6743), .B1(
FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1327) );
AO22XLTS U4355 ( .A0(n7077), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n6735), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1353) );
AO22XLTS U4356 ( .A0(n6744), .A1(FPADDSUB_OP_FLAG_EXP), .B0(n6743), .B1(
FPADDSUB_OP_FLAG_SHT1), .Y(n1354) );
AO22XLTS U4357 ( .A0(n6713), .A1(FPADDSUB_SIGN_FLAG_NRM), .B0(n2341), .B1(
FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(n1357) );
AO22XLTS U4358 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_SIGN_FLAG_SFG), .B0(n6711), .B1(FPADDSUB_SIGN_FLAG_NRM), .Y(
n1358) );
AO22XLTS U4359 ( .A0(n7077), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n6735), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n1360) );
AO22XLTS U4360 ( .A0(n6744), .A1(FPADDSUB_SIGN_FLAG_EXP), .B0(n6743), .B1(
FPADDSUB_SIGN_FLAG_SHT1), .Y(n1361) );
AO22XLTS U4361 ( .A0(n6744), .A1(FPADDSUB_DmP_EXP_EWSW[10]), .B0(n6743),
.B1(FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1364) );
AO22XLTS U4362 ( .A0(n6744), .A1(FPADDSUB_DmP_EXP_EWSW[14]), .B0(n6743),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1367) );
AO22XLTS U4363 ( .A0(n6744), .A1(FPADDSUB_DmP_EXP_EWSW[8]), .B0(n6743), .B1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1373) );
AO22XLTS U4364 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[16]), .B0(n6656),
.B1(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1376) );
AO22XLTS U4365 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[13]), .B0(n6656),
.B1(FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1379) );
AO22XLTS U4366 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[6]), .B0(n6656), .B1(
FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1382) );
AO22XLTS U4367 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[4]), .B0(n6656), .B1(
FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1385) );
AO22XLTS U4368 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[17]), .B0(n6656),
.B1(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n1388) );
AO22XLTS U4369 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[19]), .B0(n6656),
.B1(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n1394) );
AO22XLTS U4370 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[21]), .B0(n6656),
.B1(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1397) );
AO22XLTS U4371 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[18]), .B0(n6741),
.B1(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n1400) );
AO22XLTS U4372 ( .A0(n6741), .A1(FPADDSUB_DmP_mant_SHT1_SW[15]), .B0(n6635),
.B1(FPADDSUB_DmP_EXP_EWSW[15]), .Y(n1403) );
AO22XLTS U4373 ( .A0(n6635), .A1(FPADDSUB_DmP_EXP_EWSW[22]), .B0(n6738),
.B1(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1406) );
AO22XLTS U4374 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[30]), .B0(n2316), .B1(FPADDSUB_DMP_exp_NRM_EW[7]),
.Y(n1419) );
AO22XLTS U4375 ( .A0(n7077), .A1(FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n6735),
.B1(FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1421) );
AO22XLTS U4376 ( .A0(n6657), .A1(FPADDSUB_DMP_EXP_EWSW[30]), .B0(n6741),
.B1(FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1422) );
AO22XLTS U4377 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[29]), .B0(n2316), .B1(FPADDSUB_DMP_exp_NRM_EW[6]),
.Y(n1424) );
AO22XLTS U4378 ( .A0(n7077), .A1(FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n6735),
.B1(FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1426) );
AO22XLTS U4379 ( .A0(n6635), .A1(FPADDSUB_DMP_EXP_EWSW[29]), .B0(n6625),
.B1(FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1427) );
AO22XLTS U4380 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[28]), .B0(n2316), .B1(FPADDSUB_DMP_exp_NRM_EW[5]),
.Y(n1429) );
AO22XLTS U4381 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n6735),
.B1(FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1431) );
AO22XLTS U4382 ( .A0(n6635), .A1(FPADDSUB_DMP_EXP_EWSW[28]), .B0(n6625),
.B1(FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1432) );
AO22XLTS U4383 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[27]), .B0(n2316), .B1(FPADDSUB_DMP_exp_NRM_EW[4]),
.Y(n1434) );
AO22XLTS U4384 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n6735),
.B1(FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1436) );
AO22XLTS U4385 ( .A0(n6635), .A1(FPADDSUB_DMP_EXP_EWSW[27]), .B0(n6625),
.B1(FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1437) );
AO22XLTS U4386 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[26]), .B0(n2316), .B1(FPADDSUB_DMP_exp_NRM_EW[3]),
.Y(n1439) );
AO22XLTS U4387 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n6735),
.B1(FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1441) );
AO22XLTS U4388 ( .A0(n6657), .A1(FPADDSUB_DMP_EXP_EWSW[26]), .B0(n6625),
.B1(FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1442) );
AO22XLTS U4389 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[25]), .B0(n2316), .B1(FPADDSUB_DMP_exp_NRM_EW[2]),
.Y(n1444) );
AO22XLTS U4390 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n6740),
.B1(FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1446) );
AO22XLTS U4391 ( .A0(n6635), .A1(FPADDSUB_DMP_EXP_EWSW[25]), .B0(n6625),
.B1(FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1447) );
AO22XLTS U4392 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n6740),
.B1(FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1451) );
AO22XLTS U4393 ( .A0(n6635), .A1(FPADDSUB_DMP_EXP_EWSW[24]), .B0(n6625),
.B1(FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1452) );
AO22XLTS U4394 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n6733),
.B1(FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1456) );
AO22XLTS U4395 ( .A0(n6635), .A1(n6620), .B0(n6625), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1475) );
OAI21XLTS U4396 ( .A0(n6848), .A1(n6763), .B0(intadd_516_CI), .Y(n6620) );
AO22XLTS U4397 ( .A0(n6635), .A1(intadd_516_SUM_1_), .B0(n6625), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1477) );
AO22XLTS U4398 ( .A0(n6739), .A1(intadd_516_SUM_2_), .B0(n6736), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1478) );
NOR2XLTS U4399 ( .A(n4588), .B(FPMULT_Sgf_normalized_result[23]), .Y(n4586)
);
MX2X1TS U4400 ( .A(FPMULT_P_Sgf[0]), .B(FPMULT_Sgf_operation_Result[0]),
.S0(n2284), .Y(n1529) );
MX2X1TS U4401 ( .A(FPMULT_P_Sgf[2]), .B(FPMULT_Sgf_operation_Result[2]),
.S0(n2284), .Y(n1531) );
MX2X1TS U4402 ( .A(FPMULT_P_Sgf[6]), .B(n6275), .S0(n6956), .Y(n1535) );
MX2X1TS U4403 ( .A(FPMULT_P_Sgf[7]), .B(n6276), .S0(n6957), .Y(n1536) );
MX2X1TS U4404 ( .A(FPMULT_P_Sgf[8]), .B(n6274), .S0(n2284), .Y(n1537) );
MX2X1TS U4405 ( .A(FPMULT_P_Sgf[11]), .B(n6277), .S0(n6958), .Y(n1540) );
MX2X1TS U4406 ( .A(Data_2[1]), .B(n2220), .S0(n2349), .Y(n1627) );
MX2X1TS U4407 ( .A(Data_2[3]), .B(FPMULT_Op_MY[3]), .S0(n2349), .Y(n1629) );
MX2X1TS U4408 ( .A(Data_2[4]), .B(n5646), .S0(n2369), .Y(n1630) );
MX2X1TS U4409 ( .A(Data_2[6]), .B(DP_OP_501J223_127_5235_n903), .S0(n2350),
.Y(n1632) );
MX2X1TS U4410 ( .A(Data_2[7]), .B(n6764), .S0(n2369), .Y(n1633) );
MX2X1TS U4411 ( .A(Data_2[13]), .B(n5649), .S0(n2369), .Y(n1639) );
MX2X1TS U4412 ( .A(Data_2[14]), .B(FPMULT_Op_MY[14]), .S0(n2349), .Y(n1640)
);
MX2X1TS U4413 ( .A(Data_2[15]), .B(FPMULT_Op_MY[15]), .S0(n2349), .Y(n1641)
);
MX2X1TS U4414 ( .A(Data_2[19]), .B(n6753), .S0(n2349), .Y(n1645) );
MX2X1TS U4415 ( .A(Data_2[20]), .B(n5647), .S0(n5645), .Y(n1646) );
AO22XLTS U4416 ( .A0(n5637), .A1(Data_1[31]), .B0(n6606), .B1(
FPMULT_Op_MX[31]), .Y(n1657) );
MX2X1TS U4417 ( .A(Data_1[1]), .B(n2481), .S0(n5639), .Y(n1659) );
MX2X1TS U4418 ( .A(Data_1[2]), .B(FPMULT_Op_MX[2]), .S0(n5639), .Y(n1660) );
MX2X1TS U4419 ( .A(Data_1[5]), .B(n5638), .S0(n5639), .Y(n1663) );
MX2X1TS U4420 ( .A(Data_1[7]), .B(FPMULT_Op_MX[7]), .S0(n5639), .Y(n1665) );
MX2X1TS U4421 ( .A(Data_1[9]), .B(DP_OP_501J223_127_5235_n944), .S0(n5639),
.Y(n1667) );
MX2X1TS U4422 ( .A(Data_1[10]), .B(n6750), .S0(n5639), .Y(n1668) );
MX2X1TS U4423 ( .A(Data_1[13]), .B(FPMULT_Op_MX[13]), .S0(n2369), .Y(n1671)
);
MX2X1TS U4424 ( .A(Data_1[14]), .B(FPMULT_Op_MX[14]), .S0(n2350), .Y(n1672)
);
MX2X1TS U4425 ( .A(Data_1[19]), .B(FPMULT_Op_MX[19]), .S0(n6606), .Y(n1677)
);
AO22XLTS U4426 ( .A0(n5637), .A1(Data_2[31]), .B0(n6606), .B1(
FPMULT_Op_MY[31]), .Y(n1624) );
OAI21XLTS U4427 ( .A0(n5265), .A1(n4578), .B0(n5450), .Y(n2079) );
OAI21XLTS U4428 ( .A0(n6455), .A1(n6783), .B0(intadd_518_CI), .Y(n4556) );
NOR2XLTS U4429 ( .A(n6371), .B(intadd_517_B_1_), .Y(n4555) );
OAI21XLTS U4430 ( .A0(n6455), .A1(n6369), .B0(n6368), .Y(n6370) );
OAI31X1TS U4431 ( .A0(n6364), .A1(n6768), .A2(n6367), .B0(n6363), .Y(n6365)
);
NOR2X4TS U4432 ( .A(DP_OP_499J223_125_1651_n215), .B(
DP_OP_499J223_125_1651_n213), .Y(n2789) );
NAND2X4TS U4433 ( .A(DP_OP_499J223_125_1651_n204), .B(
DP_OP_499J223_125_1651_n206), .Y(n3103) );
NOR2X6TS U4434 ( .A(n2607), .B(n2606), .Y(n2659) );
BUFX4TS U4435 ( .A(n3935), .Y(n2389) );
NOR2X4TS U4436 ( .A(n3589), .B(n3594), .Y(n3504) );
OAI22X2TS U4437 ( .A0(n2386), .A1(n3694), .B0(n2385), .B1(n3693), .Y(n3668)
);
OAI21X2TS U4438 ( .A0(n2928), .A1(n2927), .B0(n2926), .Y(n2929) );
NAND2X4TS U4439 ( .A(n2837), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .Y(n2926)
);
NAND2X4TS U4440 ( .A(n3058), .B(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(
n3283) );
NAND2X4TS U4441 ( .A(DP_OP_501J223_127_5235_n130), .B(
DP_OP_501J223_127_5235_n135), .Y(n3584) );
INVX2TS U4442 ( .A(n4195), .Y(DP_OP_499J223_125_1651_n266) );
ADDFHX2TS U4443 ( .A(n3120), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[5]), .CI(
n3119), .CO(n3121), .S(n3086) );
CMPR42X2TS U4444 ( .A(DP_OP_501J223_127_5235_n251), .B(
DP_OP_501J223_127_5235_n161), .C(DP_OP_501J223_127_5235_n160), .D(
DP_OP_501J223_127_5235_n165), .ICI(DP_OP_501J223_127_5235_n157), .S(
DP_OP_501J223_127_5235_n154), .ICO(DP_OP_501J223_127_5235_n152), .CO(
DP_OP_501J223_127_5235_n153) );
OAI21X1TS U4445 ( .A0(n3527), .A1(n3526), .B0(n3525), .Y(n3532) );
XNOR2X4TS U4446 ( .A(n3487), .B(n3486), .Y(n2253) );
INVX4TS U4447 ( .A(n2221), .Y(n6568) );
AND3X2TS U4448 ( .A(n4588), .B(n6260), .C(FPMULT_FSM_selector_C), .Y(n2227)
);
OR2X1TS U4449 ( .A(FPMULT_P_Sgf[8]), .B(FPMULT_P_Sgf[6]), .Y(n2229) );
INVX2TS U4450 ( .A(n5617), .Y(n2309) );
XOR2X1TS U4451 ( .A(n3713), .B(n3712), .Y(n2242) );
INVX2TS U4452 ( .A(n2486), .Y(n2324) );
OR2X4TS U4453 ( .A(n3640), .B(n3639), .Y(n2486) );
OR2X2TS U4454 ( .A(FPMULT_Op_MX[15]), .B(n6569), .Y(n2245) );
CLKXOR2X2TS U4455 ( .A(n3380), .B(n3362), .Y(n3363) );
CLKXOR2X2TS U4456 ( .A(n4563), .B(n4441), .Y(n2250) );
OR2X2TS U4457 ( .A(n6593), .B(n2286), .Y(n2251) );
OR2X2TS U4458 ( .A(n5386), .B(n5392), .Y(n2252) );
OAI21X1TS U4459 ( .A0(n4307), .A1(n4306), .B0(n4303), .Y(n2254) );
NOR2BX2TS U4460 ( .AN(n4590), .B(n6260), .Y(n4589) );
INVX2TS U4461 ( .A(n5238), .Y(n5330) );
NAND2X1TS U4462 ( .A(n5951), .B(n2311), .Y(n5969) );
INVX2TS U4463 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n5951) );
NOR2X4TS U4464 ( .A(n5326), .B(n6806), .Y(n5387) );
XNOR2X4TS U4465 ( .A(n3340), .B(n3223), .Y(n2264) );
OR3X1TS U4466 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n6785), .C(n4274),
.Y(n2267) );
OR2X1TS U4467 ( .A(FPMULT_P_Sgf[7]), .B(FPMULT_P_Sgf[11]), .Y(n2268) );
XNOR2X2TS U4468 ( .A(n3483), .B(n3482), .Y(n3899) );
INVX2TS U4469 ( .A(n5478), .Y(n6290) );
INVX2TS U4470 ( .A(n5637), .Y(n5645) );
BUFX3TS U4471 ( .A(FPADDSUB_left_right_SHT2), .Y(n6005) );
OAI21X2TS U4472 ( .A0(n6306), .A1(n6303), .B0(n6307), .Y(n2983) );
OA21X1TS U4473 ( .A0(n5525), .A1(n5528), .B0(n5526), .Y(n5523) );
OAI21X2TS U4474 ( .A0(n5520), .A1(n5523), .B0(n5521), .Y(n5518) );
AOI21X4TS U4475 ( .A0(n2218), .A1(n3451), .B0(n3433), .Y(n3434) );
ADDFHX2TS U4476 ( .A(n3663), .B(n3662), .CI(n3661), .CO(
DP_OP_501J223_127_5235_n140), .S(DP_OP_501J223_127_5235_n141) );
OAI21X1TS U4477 ( .A0(n3587), .A1(n3561), .B0(n3560), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15) );
OAI21X2TS U4478 ( .A0(n3587), .A1(n3573), .B0(n3572), .Y(n3577) );
OAI21X2TS U4479 ( .A0(n3587), .A1(n3551), .B0(n3550), .Y(n3555) );
OAI21X2TS U4480 ( .A0(n3587), .A1(n3564), .B0(n3563), .Y(n3569) );
INVX2TS U4481 ( .A(n2477), .Y(n2283) );
NAND2X1TS U4482 ( .A(n6584), .B(n2283), .Y(n3366) );
NOR2X2TS U4483 ( .A(n6584), .B(n2220), .Y(n3365) );
INVX2TS U4484 ( .A(n2259), .Y(n2287) );
INVX2TS U4485 ( .A(n2225), .Y(n5643) );
INVX2TS U4486 ( .A(n2198), .Y(n2289) );
INVX2TS U4487 ( .A(n2199), .Y(n2290) );
INVX4TS U4488 ( .A(n2255), .Y(n2292) );
INVX2TS U4489 ( .A(n2242), .Y(n2293) );
INVX2TS U4490 ( .A(n2242), .Y(n2294) );
INVX2TS U4491 ( .A(n2202), .Y(n2295) );
INVX2TS U4492 ( .A(n4484), .Y(n2297) );
INVX2TS U4493 ( .A(n2297), .Y(n2298) );
INVX2TS U4494 ( .A(n2297), .Y(n2299) );
INVX2TS U4495 ( .A(n6455), .Y(n2300) );
INVX2TS U4496 ( .A(n6415), .Y(n4748) );
INVX2TS U4497 ( .A(n2301), .Y(n2302) );
INVX2TS U4498 ( .A(n2241), .Y(n2303) );
INVX2TS U4499 ( .A(n2241), .Y(n2304) );
INVX2TS U4500 ( .A(n2254), .Y(n2305) );
INVX2TS U4501 ( .A(n2254), .Y(n2306) );
INVX2TS U4502 ( .A(n2243), .Y(n2307) );
INVX4TS U4503 ( .A(n2309), .Y(n2310) );
INVX2TS U4504 ( .A(n2262), .Y(n2311) );
INVX2TS U4505 ( .A(n2262), .Y(n2312) );
INVX2TS U4506 ( .A(n2250), .Y(n2321) );
INVX2TS U4507 ( .A(n2224), .Y(n2323) );
INVX2TS U4508 ( .A(n2219), .Y(n5642) );
INVX2TS U4509 ( .A(n2267), .Y(n2327) );
INVX2TS U4510 ( .A(n2267), .Y(n2328) );
INVX2TS U4511 ( .A(n5974), .Y(n2329) );
INVX2TS U4512 ( .A(n5974), .Y(n2330) );
OAI22X2TS U4513 ( .A0(n3707), .A1(n3696), .B0(n3708), .B1(n3695), .Y(n3661)
);
NOR2X1TS U4514 ( .A(n2335), .B(n3692), .Y(DP_OP_501J223_127_5235_n200) );
OAI22X1TS U4515 ( .A0(n3707), .A1(n3702), .B0(n2335), .B1(n3701), .Y(
DP_OP_501J223_127_5235_n244) );
XOR2X4TS U4516 ( .A(n3657), .B(n3656), .Y(n3658) );
INVX2TS U4517 ( .A(n5969), .Y(n2342) );
INVX2TS U4518 ( .A(n5969), .Y(n2343) );
INVX2TS U4519 ( .A(n2405), .Y(n2344) );
INVX2TS U4520 ( .A(n6767), .Y(n2345) );
INVX2TS U4521 ( .A(n6767), .Y(n2346) );
INVX2TS U4522 ( .A(n2347), .Y(n2348) );
INVX2TS U4523 ( .A(n5237), .Y(n2351) );
INVX2TS U4524 ( .A(n5237), .Y(n2352) );
INVX2TS U4525 ( .A(n2356), .Y(n2357) );
INVX2TS U4526 ( .A(n5387), .Y(n2358) );
INVX2TS U4527 ( .A(n2358), .Y(n2359) );
INVX2TS U4528 ( .A(n2358), .Y(n2360) );
INVX2TS U4529 ( .A(n2227), .Y(n2361) );
INVX2TS U4530 ( .A(n2227), .Y(n2362) );
INVX2TS U4531 ( .A(n2227), .Y(n2363) );
AOI32X1TS U4532 ( .A0(FPSENCOS_d_ff3_sign_out), .A1(n6547), .A2(
FPSENCOS_cont_var_out[0]), .B0(n6546), .B1(n6547), .Y(n1731) );
NOR3XLTS U4533 ( .A(n5648), .B(FPMULT_Op_MY[24]), .C(FPMULT_Op_MY[23]), .Y(
n6596) );
AOI21X2TS U4534 ( .A0(n5330), .A1(n6821), .B0(n5242), .Y(n5361) );
AOI21X2TS U4535 ( .A0(n5387), .A1(n6791), .B0(n5341), .Y(n5378) );
AOI21X2TS U4536 ( .A0(n5325), .A1(n6799), .B0(n5270), .Y(n5367) );
AOI21X2TS U4537 ( .A0(n5330), .A1(n6800), .B0(n5255), .Y(n5350) );
AOI211X1TS U4538 ( .A0(n2545), .A1(n2544), .B0(n2543), .C0(n2542), .Y(n2546)
);
INVX2TS U4539 ( .A(n3373), .Y(n5540) );
ADDHX1TS U4540 ( .A(n3881), .B(n3880), .CO(n3875), .S(n3884) );
MXI2X2TS U4541 ( .A(Data_2[0]), .B(DP_OP_501J223_127_5235_n897), .S0(n2369),
.Y(n6923) );
INVX2TS U4542 ( .A(n5637), .Y(n2369) );
NOR2X2TS U4543 ( .A(n5748), .B(n5747), .Y(n5754) );
INVX2TS U4544 ( .A(rst), .Y(n2365) );
CLKBUFX2TS U4545 ( .A(n7019), .Y(n7012) );
NAND3X2TS U4546 ( .A(n4485), .B(n6757), .C(n6787), .Y(n4489) );
CMPR42X1TS U4547 ( .A(DP_OP_500J223_126_4510_n174), .B(
DP_OP_500J223_126_4510_n138), .C(DP_OP_500J223_126_4510_n141), .D(
DP_OP_500J223_126_4510_n181), .ICI(DP_OP_500J223_126_4510_n188), .S(
DP_OP_500J223_126_4510_n136), .ICO(DP_OP_500J223_126_4510_n134), .CO(
DP_OP_500J223_126_4510_n135) );
ADDHX1TS U4548 ( .A(n4350), .B(n4349), .CO(DP_OP_500J223_126_4510_n137), .S(
DP_OP_500J223_126_4510_n138) );
OAI21X1TS U4549 ( .A0(n5770), .A1(n5769), .B0(n4895), .Y(mult_x_311_n22) );
OAI21X2TS U4550 ( .A0(n4888), .A1(n4887), .B0(n4913), .Y(n5769) );
AOI32X1TS U4551 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[4]), .A1(n5265), .A2(
n7059), .B0(FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n5379), .Y(n4694)
);
AOI32X1TS U4552 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[3]), .A1(n5265), .A2(
n7059), .B0(FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n5379), .Y(n4756)
);
ADDFHX2TS U4553 ( .A(n4239), .B(n4238), .CI(n4237), .CO(
DP_OP_499J223_125_1651_n250), .S(n2742) );
ADDHX1TS U4554 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .B(n4236), .CO(DP_OP_499J223_125_1651_n252), .S(n4239) );
AOI21X2TS U4555 ( .A0(n2312), .A1(FPADDSUB_Data_array_SWR[25]), .B0(n4480),
.Y(n4470) );
INVX2TS U4556 ( .A(n4581), .Y(n4666) );
OAI21X2TS U4557 ( .A0(n4901), .A1(n4900), .B0(n4899), .Y(n5766) );
INVX2TS U4558 ( .A(n6849), .Y(n2366) );
INVX2TS U4559 ( .A(n2276), .Y(n2367) );
CLKBUFX3TS U4560 ( .A(n7041), .Y(n7028) );
BUFX3TS U4561 ( .A(n7013), .Y(n7041) );
XNOR2X1TS U4562 ( .A(n3951), .B(n2308), .Y(n3909) );
XNOR2X1TS U4563 ( .A(n3937), .B(n2308), .Y(n3862) );
XNOR2X1TS U4564 ( .A(n3896), .B(n2308), .Y(n3888) );
XNOR2X1TS U4565 ( .A(n3914), .B(n2308), .Y(n3879) );
XNOR2X1TS U4566 ( .A(n3921), .B(n2308), .Y(n3869) );
XOR2X1TS U4567 ( .A(n3860), .B(n2307), .Y(n3861) );
AOI222X1TS U4568 ( .A0(n6562), .A1(cordic_result[30]), .B0(n5158), .B1(
FPSENCOS_d_ff_Xn[30]), .C0(n5118), .C1(FPSENCOS_d_ff_Yn[30]), .Y(n4986) );
CLKBUFX3TS U4569 ( .A(n4491), .Y(n4498) );
CLKBUFX3TS U4570 ( .A(n4491), .Y(n7010) );
CLKBUFX3TS U4571 ( .A(n4491), .Y(n4496) );
OAI2BB2XLTS U4572 ( .B0(n6393), .B1(n2451), .A0N(n6387), .A1N(
FPSENCOS_d_ff_Yn[30]), .Y(n1730) );
AOI222X1TS U4573 ( .A0(n4984), .A1(cordic_result[23]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[23]), .C0(n5118), .C1(FPSENCOS_d_ff_Yn[23]), .Y(n5160) );
AOI222X1TS U4574 ( .A0(n4984), .A1(cordic_result[25]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[25]), .C0(n4985), .C1(FPSENCOS_d_ff_Yn[25]), .Y(n5161) );
AOI222X1TS U4575 ( .A0(n4984), .A1(cordic_result[29]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[29]), .C0(n5118), .C1(FPSENCOS_d_ff_Yn[29]), .Y(n5164) );
OR2X1TS U4576 ( .A(n6863), .B(FPADDSUB_DMP_SFG[9]), .Y(n4385) );
INVX2TS U4577 ( .A(FPADDSUB_intDX_EWSW[6]), .Y(n2525) );
NOR3XLTS U4578 ( .A(n6579), .B(FPMULT_Op_MX[24]), .C(FPMULT_Op_MX[23]), .Y(
n6580) );
INVX2TS U4579 ( .A(FPADDSUB_intDX_EWSW[16]), .Y(n2552) );
CLKMX2X2TS U4580 ( .A(FPMULT_P_Sgf[31]), .B(n4333), .S0(n6290), .Y(n1560) );
AOI21X2TS U4581 ( .A0(n2360), .A1(n6799), .B0(n5266), .Y(n5358) );
OAI22X1TS U4582 ( .A0(n3965), .A1(n3964), .B0(n3974), .B1(n3952), .Y(n3962)
);
OAI22X1TS U4583 ( .A0(n3974), .A1(n3915), .B0(n3964), .B1(n3922), .Y(n3923)
);
OAI22X1TS U4584 ( .A0(n3974), .A1(n3938), .B0(n3964), .B1(n3952), .Y(n3954)
);
OAI22X1TS U4585 ( .A0(n3974), .A1(DP_OP_501J223_127_5235_n630), .B0(n3964),
.B1(n3915), .Y(n3910) );
OAI22X1TS U4586 ( .A0(n3974), .A1(n3922), .B0(n3964), .B1(n3938), .Y(n3933)
);
NOR2BX1TS U4587 ( .AN(n3900), .B(n3964), .Y(n3872) );
NAND2X2TS U4588 ( .A(n3964), .B(n3867), .Y(n3974) );
AOI21X2TS U4589 ( .A0(n5387), .A1(n6800), .B0(n5269), .Y(n5366) );
INVX2TS U4590 ( .A(n3899), .Y(n2368) );
NOR2X2TS U4591 ( .A(FPMULT_Sgf_normalized_result[0]), .B(
FPMULT_Sgf_normalized_result[1]), .Y(n5915) );
OAI221X1TS U4592 ( .A0(FPADDSUB_intDX_EWSW[4]), .A1(n6761), .B0(n6813), .B1(
FPADDSUB_intDY_EWSW[4]), .C0(n6688), .Y(n6699) );
AOI221X1TS U4593 ( .A0(n2270), .A1(FPADDSUB_intDY_EWSW[8]), .B0(
FPADDSUB_intDY_EWSW[30]), .B1(n6810), .C0(n6687), .Y(n6688) );
AOI32X1TS U4594 ( .A0(n2466), .A1(n2508), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n2410), .Y(n2509) );
NOR4X2TS U4595 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n4993) );
OAI221X1TS U4596 ( .A0(n6812), .A1(FPADDSUB_intDY_EWSW[29]), .B0(n2278),
.B1(FPADDSUB_intDY_EWSW[3]), .C0(n6685), .Y(n6701) );
NOR4BX4TS U4597 ( .AN(n4671), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .D(n6786), .Y(n6337) );
NOR2X1TS U4598 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n4552) );
OAI221X1TS U4599 ( .A0(n2464), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n6804),
.B1(FPADDSUB_intDY_EWSW[26]), .C0(n6671), .Y(n6674) );
AOI222X1TS U4600 ( .A0(n5291), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n6847),
.B1(n6668), .C0(FPADDSUB_intDX_EWSW[25]), .C1(n4321), .Y(n7075) );
OAI221X1TS U4601 ( .A0(n6805), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n2434),
.B1(FPADDSUB_intDY_EWSW[1]), .C0(n6679), .Y(n6682) );
OAI221XLTS U4602 ( .A0(n2232), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n2272),
.B1(FPADDSUB_intDY_EWSW[18]), .C0(n6678), .Y(n6683) );
OAI221X1TS U4603 ( .A0(n2215), .A1(FPADDSUB_intDY_EWSW[27]), .B0(n2279),
.B1(FPADDSUB_intDY_EWSW[15]), .C0(n6669), .Y(n6676) );
AOI222X1TS U4604 ( .A0(n5291), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n6848),
.B1(n6668), .C0(FPADDSUB_intDX_EWSW[23]), .C1(n4321), .Y(n7073) );
AOI211X2TS U4605 ( .A0(n2341), .A1(n6820), .B0(n6015), .C0(n2359), .Y(n5235)
);
OAI221XLTS U4606 ( .A0(n2231), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n2275),
.B1(FPADDSUB_intDY_EWSW[0]), .C0(n6672), .Y(n6673) );
AOI221X1TS U4607 ( .A0(n2233), .A1(FPADDSUB_intDY_EWSW[14]), .B0(
FPADDSUB_intDY_EWSW[20]), .B1(n2274), .C0(n6690), .Y(n6696) );
OAI221XLTS U4608 ( .A0(n2277), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n2234),
.B1(FPADDSUB_intDY_EWSW[9]), .C0(n6680), .Y(n6681) );
AOI221X1TS U4609 ( .A0(n2273), .A1(FPADDSUB_intDY_EWSW[2]), .B0(
FPADDSUB_intDY_EWSW[5]), .B1(n6692), .C0(n6691), .Y(n6695) );
INVX2TS U4610 ( .A(n3717), .Y(n2370) );
NOR2X1TS U4611 ( .A(n3841), .B(n2403), .Y(n3835) );
OAI22X1TS U4612 ( .A0(n2294), .A1(n2346), .B0(n2370), .B1(n3840), .Y(
DP_OP_501J223_127_5235_n491) );
OAI22X1TS U4613 ( .A0(n2294), .A1(n3843), .B0(n3841), .B1(n3842), .Y(n3834)
);
NOR2X1TS U4614 ( .A(n3841), .B(n3843), .Y(n3837) );
OAI22X1TS U4615 ( .A0(n2294), .A1(n3845), .B0(n3841), .B1(n3844), .Y(n3836)
);
NOR2X1TS U4616 ( .A(n3841), .B(n3851), .Y(n3854) );
NOR2X1TS U4617 ( .A(n3841), .B(n3847), .Y(n3735) );
OAI22X1TS U4618 ( .A0(n2293), .A1(n3847), .B0(n3841), .B1(n3846), .Y(n3733)
);
INVX2TS U4619 ( .A(n3717), .Y(n3841) );
NAND2X1TS U4620 ( .A(n6595), .B(n5644), .Y(n3720) );
NOR2X2TS U4621 ( .A(n5647), .B(n5644), .Y(n3722) );
NOR2X2TS U4622 ( .A(n5644), .B(n2286), .Y(n4431) );
NAND2X1TS U4623 ( .A(n5643), .B(n6587), .Y(n4432) );
INVX4TS U4624 ( .A(n2260), .Y(n6587) );
NAND2X1TS U4625 ( .A(n6585), .B(n6594), .Y(n4292) );
NOR2X2TS U4626 ( .A(n6585), .B(n6594), .Y(n4291) );
INVX2TS U4627 ( .A(n3746), .Y(n2371) );
NOR2X1TS U4628 ( .A(n3852), .B(n3842), .Y(n3757) );
NOR2X1TS U4629 ( .A(n3852), .B(n3844), .Y(DP_OP_501J223_127_5235_n500) );
NOR2X1TS U4630 ( .A(n3852), .B(n3846), .Y(n3824) );
NOR2X1TS U4631 ( .A(n3852), .B(n3849), .Y(n3830) );
OAI21X2TS U4632 ( .A0(n3816), .A1(n2402), .B0(n3745), .Y(n3746) );
INVX2TS U4633 ( .A(n3746), .Y(n3852) );
INVX2TS U4634 ( .A(n3727), .Y(n2372) );
OAI22X1TS U4635 ( .A0(n2296), .A1(n2345), .B0(n2372), .B1(n3840), .Y(n3822)
);
OAI22X1TS U4636 ( .A0(n2296), .A1(n3847), .B0(n2372), .B1(n3846), .Y(
DP_OP_501J223_127_5235_n510) );
OAI22X1TS U4637 ( .A0(n3850), .A1(n3845), .B0(n2294), .B1(n3844), .Y(n3833)
);
OAI22X1TS U4638 ( .A0(n2296), .A1(n3845), .B0(n2372), .B1(n3844), .Y(
DP_OP_501J223_127_5235_n503) );
OAI22X1TS U4639 ( .A0(n2295), .A1(n3843), .B0(n3850), .B1(n3842), .Y(n3828)
);
OAI22X1TS U4640 ( .A0(n3850), .A1(n2345), .B0(n2294), .B1(n3840), .Y(n3829)
);
OAI22X1TS U4641 ( .A0(n2295), .A1(n3851), .B0(n3850), .B1(n3849), .Y(
DP_OP_501J223_127_5235_n517) );
OAI22X1TS U4642 ( .A0(n3850), .A1(n3847), .B0(n2293), .B1(n3846), .Y(
DP_OP_501J223_127_5235_n511) );
INVX2TS U4643 ( .A(n3727), .Y(n3850) );
INVX2TS U4644 ( .A(n3751), .Y(n2373) );
OAI22X1TS U4645 ( .A0(n2373), .A1(n2346), .B0(n2296), .B1(n3840), .Y(
DP_OP_501J223_127_5235_n488) );
OAI22X1TS U4646 ( .A0(n2373), .A1(n3842), .B0(n3852), .B1(n3843), .Y(
DP_OP_501J223_127_5235_n494) );
OAI22X1TS U4647 ( .A0(n3848), .A1(n3843), .B0(n2296), .B1(n3842), .Y(
DP_OP_501J223_127_5235_n495) );
OAI22X1TS U4648 ( .A0(n3848), .A1(n3851), .B0(n2296), .B1(n3849), .Y(n3831)
);
OAI22X1TS U4649 ( .A0(n3848), .A1(n3846), .B0(n3852), .B1(n3847), .Y(
DP_OP_501J223_127_5235_n508) );
OAI22X1TS U4650 ( .A0(n3848), .A1(n3849), .B0(n3852), .B1(n3851), .Y(
DP_OP_501J223_127_5235_n515) );
OAI22X2TS U4651 ( .A0(n3848), .A1(n3845), .B0(n2296), .B1(n3844), .Y(n3827)
);
XNOR2X2TS U4652 ( .A(n3750), .B(FPMULT_Op_MY[11]), .Y(n3751) );
INVX2TS U4653 ( .A(n3751), .Y(n3848) );
INVX2TS U4654 ( .A(n6629), .Y(n6728) );
INVX2TS U4655 ( .A(n4347), .Y(n2376) );
INVX2TS U4656 ( .A(n4347), .Y(n5614) );
INVX2TS U4657 ( .A(n3369), .Y(n5542) );
CLKXOR2X2TS U4658 ( .A(n3368), .B(n3371), .Y(n3369) );
CLKBUFX2TS U4659 ( .A(n5621), .Y(n2378) );
OAI21X1TS U4660 ( .A0(n4301), .A1(n4297), .B0(n4298), .Y(n4295) );
CLKBUFX2TS U4661 ( .A(n5548), .Y(n2379) );
NAND2X1TS U4662 ( .A(n3381), .B(n4432), .Y(n3382) );
CLKBUFX2TS U4663 ( .A(n5619), .Y(n2380) );
OAI21X1TS U4664 ( .A0(n4563), .A1(n4562), .B0(n4561), .Y(n4568) );
NOR2X2TS U4665 ( .A(n3279), .B(FPMULT_FS_Module_state_reg[1]), .Y(
FPMULT_FSM_exp_operation_A_S) );
INVX2TS U4666 ( .A(FPMULT_FSM_exp_operation_A_S), .Y(n5935) );
NAND2X1TS U4667 ( .A(n2383), .B(n6588), .Y(n3818) );
NOR2X2TS U4668 ( .A(n2383), .B(n6588), .Y(n3817) );
ADDFX2TS U4669 ( .A(n6588), .B(n6586), .CI(n3513), .CO(n3520), .S(n3457) );
NAND2X1TS U4670 ( .A(n6586), .B(n2290), .Y(n4305) );
INVX2TS U4671 ( .A(n2238), .Y(n6586) );
BUFX3TS U4672 ( .A(n3679), .Y(n2384) );
NOR2X1TS U4673 ( .A(n2384), .B(n3704), .Y(n3857) );
OAI22X1TS U4674 ( .A0(n2332), .A1(n3704), .B0(n2384), .B1(n3705), .Y(n3624)
);
NOR2X1TS U4675 ( .A(n3679), .B(n3702), .Y(n3495) );
OAI22X2TS U4676 ( .A0(n3693), .A1(n2384), .B0(n3694), .B1(n2332), .Y(n3673)
);
NOR2X1TS U4677 ( .A(n3679), .B(n3692), .Y(n3674) );
NOR2X1TS U4678 ( .A(n3679), .B(n3700), .Y(n3691) );
OAI22X1TS U4679 ( .A0(n2331), .A1(n3702), .B0(n3679), .B1(n3701), .Y(n3690)
);
NOR2X2TS U4680 ( .A(n3694), .B(n2384), .Y(n3675) );
NOR2X1TS U4681 ( .A(n3679), .B(n3698), .Y(n3686) );
OAI22X1TS U4682 ( .A0(n2331), .A1(n3700), .B0(n3679), .B1(n3699), .Y(n3685)
);
OAI22X2TS U4683 ( .A0(n2331), .A1(n3696), .B0(n3679), .B1(n3695), .Y(n3676)
);
OAI22X1TS U4684 ( .A0(n2385), .A1(n3704), .B0(n2332), .B1(n3705), .Y(n3496)
);
OAI22X1TS U4685 ( .A0(n2385), .A1(n3694), .B0(n3693), .B1(n2332), .Y(
DP_OP_501J223_127_5235_n211) );
OAI22X1TS U4686 ( .A0(n3703), .A1(n3702), .B0(n2332), .B1(n3701), .Y(
DP_OP_501J223_127_5235_n247) );
OAI22X2TS U4687 ( .A0(n2386), .A1(n3704), .B0(n2385), .B1(n3705), .Y(n3499)
);
OAI22X1TS U4688 ( .A0(n3709), .A1(n3698), .B0(n3703), .B1(n3697), .Y(
DP_OP_501J223_127_5235_n228) );
OAI22X1TS U4689 ( .A0(n3709), .A1(n3695), .B0(n2335), .B1(n3696), .Y(n3667)
);
OAI22X1TS U4690 ( .A0(n2386), .A1(n3697), .B0(n2335), .B1(n3698), .Y(
DP_OP_501J223_127_5235_n227) );
OAI22X1TS U4691 ( .A0(n2386), .A1(n3705), .B0(n2335), .B1(n3704), .Y(
DP_OP_501J223_127_5235_n254) );
OAI22X1TS U4692 ( .A0(n3709), .A1(n3699), .B0(n3708), .B1(n3700), .Y(
DP_OP_501J223_127_5235_n236) );
OAI22X1TS U4693 ( .A0(n3709), .A1(n3701), .B0(n2335), .B1(n3702), .Y(
DP_OP_501J223_127_5235_n245) );
OAI22X1TS U4694 ( .A0(n2386), .A1(n3702), .B0(n3703), .B1(n3701), .Y(
DP_OP_501J223_127_5235_n246) );
OAI22X1TS U4695 ( .A0(n2386), .A1(n3700), .B0(n2385), .B1(n3699), .Y(
DP_OP_501J223_127_5235_n237) );
OAI22X1TS U4696 ( .A0(n2387), .A1(n3693), .B0(n2325), .B1(n3694), .Y(
DP_OP_501J223_127_5235_n206) );
NOR2X1TS U4697 ( .A(n2387), .B(n3692), .Y(DP_OP_501J223_127_5235_n198) );
OAI22X1TS U4698 ( .A0(n2387), .A1(n3697), .B0(n2325), .B1(n3698), .Y(
DP_OP_501J223_127_5235_n224) );
OAI22X1TS U4699 ( .A0(n2387), .A1(n3694), .B0(n2334), .B1(n3693), .Y(
DP_OP_501J223_127_5235_n207) );
OAI22X1TS U4700 ( .A0(n2387), .A1(n3695), .B0(n2325), .B1(n3696), .Y(n3650)
);
OAI22X1TS U4701 ( .A0(n2387), .A1(n3705), .B0(n2486), .B1(n3704), .Y(
DP_OP_501J223_127_5235_n251) );
OAI22X1TS U4702 ( .A0(n2387), .A1(n3704), .B0(n2334), .B1(n3705), .Y(
DP_OP_501J223_127_5235_n252) );
OAI22X1TS U4703 ( .A0(n3706), .A1(n3701), .B0(n2486), .B1(n3702), .Y(
DP_OP_501J223_127_5235_n242) );
INVX2TS U4704 ( .A(n3641), .Y(n3706) );
BUFX3TS U4705 ( .A(n4995), .Y(n2388) );
AOI31XLTS U4706 ( .A0(n6323), .A1(n6322), .A2(n6321), .B0(dataB[27]), .Y(
n6334) );
CLKBUFX3TS U4707 ( .A(n4490), .Y(n4497) );
CLKBUFX3TS U4708 ( .A(n4490), .Y(n4487) );
CLKBUFX3TS U4709 ( .A(n4490), .Y(n4492) );
CLKBUFX3TS U4710 ( .A(n4490), .Y(n4486) );
NOR2X4TS U4711 ( .A(n2299), .B(rst), .Y(n4490) );
CLKXOR2X2TS U4712 ( .A(n5815), .B(n5814), .Y(n5832) );
CLKXOR2X2TS U4713 ( .A(n5710), .B(n5709), .Y(n5729) );
NOR4X1TS U4714 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n6920) );
NOR4X1TS U4715 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n6921) );
NOR2XLTS U4716 ( .A(n2229), .B(n2268), .Y(n4541) );
NOR2X2TS U4717 ( .A(n5699), .B(n4824), .Y(n5711) );
NOR2X2TS U4718 ( .A(n5804), .B(n4762), .Y(n5817) );
NOR2X2TS U4719 ( .A(FPSENCOS_d_ff2_X[29]), .B(n6436), .Y(n6435) );
OAI33X4TS U4720 ( .A0(FPSENCOS_d_ff1_shift_region_flag_out[1]), .A1(
FPSENCOS_d_ff1_operation_out), .A2(n6558), .B0(n2266), .B1(n6825),
.B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n6559) );
NOR4X1TS U4721 ( .A(FPMULT_P_Sgf[20]), .B(FPMULT_P_Sgf[21]), .C(
FPMULT_P_Sgf[18]), .D(FPMULT_P_Sgf[19]), .Y(n4548) );
NOR2X2TS U4722 ( .A(n6794), .B(n2225), .Y(n5750) );
NOR2X2TS U4723 ( .A(n2482), .B(n2477), .Y(n5841) );
NOR2X2TS U4724 ( .A(n2469), .B(n2483), .Y(n5738) );
AOI21X2TS U4725 ( .A0(n4476), .A1(n4475), .B0(n4956), .Y(n5652) );
AOI22X2TS U4726 ( .A0(n4884), .A1(n4883), .B0(n4882), .B1(n5748), .Y(n5770)
);
AOI22X2TS U4727 ( .A0(n5442), .A1(n5441), .B0(n5440), .B1(n7067), .Y(n5660)
);
OAI211XLTS U4728 ( .A0(n4554), .A1(n6903), .B0(n4823), .C0(n4980), .Y(n2120)
);
AOI21X2TS U4729 ( .A0(n6375), .A1(n6372), .B0(n5013), .Y(n4823) );
OAI21XLTS U4730 ( .A0(n5774), .A1(n5773), .B0(n5775), .Y(n4878) );
AOI21X2TS U4731 ( .A0(n4892), .A1(n4868), .B0(n4897), .Y(n5773) );
AOI21X2TS U4732 ( .A0(n6364), .A1(intadd_517_B_1_), .B0(n6367), .Y(n6366) );
NOR2X4TS U4733 ( .A(n6455), .B(FPSENCOS_cont_iter_out[3]), .Y(n6364) );
AOI22X2TS U4734 ( .A0(n5690), .A1(n5689), .B0(n5688), .B1(n5687), .Y(n5721)
);
OAI21X2TS U4735 ( .A0(FPMULT_Op_MX[18]), .A1(n2291), .B0(n5439), .Y(n5667)
);
OAI21X2TS U4736 ( .A0(n4923), .A1(n4922), .B0(n4921), .Y(n5763) );
OAI21X2TS U4737 ( .A0(n4792), .A1(n4791), .B0(n4790), .Y(n5827) );
OAI21X2TS U4738 ( .A0(n4854), .A1(n4853), .B0(n4852), .Y(n5724) );
OAI21X2TS U4739 ( .A0(n4767), .A1(n4766), .B0(n4786), .Y(n5835) );
NOR2X1TS U4740 ( .A(n4784), .B(n4765), .Y(n4767) );
NAND2X1TS U4741 ( .A(n4767), .B(n4766), .Y(n4786) );
OAI21X2TS U4742 ( .A0(n4829), .A1(n4828), .B0(n4848), .Y(n5732) );
NOR2X1TS U4743 ( .A(n4846), .B(n4827), .Y(n4829) );
NAND2X1TS U4744 ( .A(n4829), .B(n4828), .Y(n4848) );
AOI22X2TS U4745 ( .A0(n5795), .A1(n5794), .B0(n5793), .B1(n5792), .Y(n5824)
);
AOI22X2TS U4746 ( .A0(n5762), .A1(n4910), .B0(n4909), .B1(n4908), .Y(n5765)
);
OAI22X2TS U4747 ( .A0(n4960), .A1(n4959), .B0(n4958), .B1(n4957), .Y(n5663)
);
NOR2X1TS U4748 ( .A(n4950), .B(n4949), .Y(n4960) );
NOR2X4TS U4749 ( .A(n6768), .B(n2300), .Y(n6373) );
NAND2BX4TS U4750 ( .AN(n6003), .B(n6627), .Y(n5963) );
INVX4TS U4751 ( .A(n6624), .Y(n6003) );
NOR2X2TS U4752 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n6199) );
NOR2X2TS U4753 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n6181) );
NOR2X2TS U4754 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n4534) );
NOR2X1TS U4755 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n4811), .Y(n4755) );
NOR2XLTS U4756 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n5631) );
AOI21X2TS U4757 ( .A0(n2312), .A1(FPADDSUB_Data_array_SWR[24]), .B0(n4480),
.Y(n6008) );
CLKMX2X2TS U4758 ( .A(FPMULT_P_Sgf[35]), .B(n4338), .S0(n6957), .Y(n1564) );
CLKMX2X2TS U4759 ( .A(FPMULT_P_Sgf[30]), .B(n4329), .S0(n6290), .Y(n1559) );
AOI22X2TS U4760 ( .A0(n5325), .A1(n6791), .B0(n5243), .B1(n5238), .Y(n5362)
);
OAI211XLTS U4761 ( .A0(n2400), .A1(n2363), .B0(n4623), .C0(n4622), .Y(n1526)
);
NOR3X1TS U4762 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n6617), .Y(n6609) );
OAI21XLTS U4763 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n2433), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n2519) );
NOR2X2TS U4764 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_517_n1), .Y(n6461) );
NOR2X2TS U4765 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n6463), .Y(n6466) );
NAND2X1TS U4766 ( .A(FPMULT_Sgf_normalized_result[5]), .B(
FPMULT_Sgf_normalized_result[4]), .Y(n5891) );
OA22X1TS U4767 ( .A0(n2409), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n2438), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n2515) );
NOR2X2TS U4768 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(
FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n5218) );
NOR4X1TS U4769 ( .A(FPADDSUB_Raw_mant_NRM_SWR[4]), .B(
FPADDSUB_Raw_mant_NRM_SWR[1]), .C(FPADDSUB_Raw_mant_NRM_SWR[0]), .D(
n5230), .Y(n4691) );
NOR2X1TS U4770 ( .A(FPADDSUB_Raw_mant_NRM_SWR[4]), .B(n4814), .Y(n5231) );
NOR2X1TS U4771 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n5217), .Y(n5210) );
OAI21X2TS U4772 ( .A0(n2336), .A1(FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(n5234),
.Y(n5349) );
NOR2BX2TS U4773 ( .AN(n4993), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n4671) );
NAND2X1TS U4774 ( .A(FPMULT_Sgf_normalized_result[6]), .B(
FPMULT_Sgf_normalized_result[7]), .Y(n5851) );
INVX2TS U4775 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n4274) );
CLKBUFX2TS U4776 ( .A(n3935), .Y(n2390) );
OAI22X1TS U4777 ( .A0(n3909), .A1(n3936), .B0(n3920), .B1(n2390), .Y(n3927)
);
OAI22X1TS U4778 ( .A0(n3909), .A1(n2390), .B0(n3936), .B1(n3862), .Y(n3918)
);
AO21X1TS U4779 ( .A0(n3936), .A1(n2390), .B0(n2243), .Y(n3955) );
OAI22X2TS U4780 ( .A0(n3936), .A1(n3920), .B0(n2390), .B1(n2243), .Y(n3956)
);
OAI22X1TS U4781 ( .A0(n3936), .A1(n3869), .B0(n2390), .B1(n3862), .Y(n3873)
);
OAI22X1TS U4782 ( .A0(n3936), .A1(n3879), .B0(n3869), .B1(n2389), .Y(n3881)
);
OAI22X1TS U4783 ( .A0(n3936), .A1(n3888), .B0(n3879), .B1(n2389), .Y(n3890)
);
OAI22X1TS U4784 ( .A0(n3936), .A1(n3889), .B0(n2389), .B1(n3888), .Y(n3894)
);
NOR2BX1TS U4785 ( .AN(n3900), .B(n2389), .Y(n4026) );
NAND2X4TS U4786 ( .A(n3861), .B(n2389), .Y(n3936) );
XNOR2X1TS U4787 ( .A(n3860), .B(n2205), .Y(n3935) );
BUFX3TS U4788 ( .A(n7013), .Y(n2391) );
BUFX3TS U4789 ( .A(n7014), .Y(n2392) );
BUFX3TS U4790 ( .A(n7011), .Y(n2393) );
NOR2X2TS U4791 ( .A(FPMULT_FSM_selector_C), .B(n4648), .Y(n4590) );
OAI22X1TS U4792 ( .A0(n3932), .A1(n2394), .B0(n3968), .B1(n3919), .Y(n3930)
);
OAI22X1TS U4793 ( .A0(n3932), .A1(n3968), .B0(n3953), .B1(n2394), .Y(n3950)
);
OAI22X1TS U4794 ( .A0(n3968), .A1(n3878), .B0(n3877), .B1(n3967), .Y(n3886)
);
OAI22X1TS U4795 ( .A0(n3968), .A1(n3966), .B0(n3870), .B1(n3967), .Y(n3880)
);
NOR2BX1TS U4796 ( .AN(n3900), .B(n3967), .Y(n3892) );
INVX2TS U4797 ( .A(n2395), .Y(n3966) );
XNOR2X1TS U4798 ( .A(n2395), .B(n3900), .Y(n3878) );
XOR2X1TS U4799 ( .A(n2395), .B(n3863), .Y(n3864) );
ADDHX1TS U4800 ( .A(n3659), .B(n3931), .CO(n3539), .S(n3660) );
OA22X1TS U4801 ( .A0(n2398), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n2461), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n2545) );
OR2X1TS U4802 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]),
.Y(n4413) );
OR2X1TS U4803 ( .A(n6808), .B(FPADDSUB_DMP_SFG[16]), .Y(n4401) );
OR2X1TS U4804 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]),
.Y(n6062) );
OR2X1TS U4805 ( .A(n6809), .B(FPADDSUB_DMP_SFG[14]), .Y(n4397) );
OR2X1TS U4806 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]),
.Y(n6153) );
OR2X1TS U4807 ( .A(n6824), .B(FPADDSUB_DMP_SFG[20]), .Y(n4409) );
OR2X1TS U4808 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]),
.Y(n6136) );
OR2X1TS U4809 ( .A(n6818), .B(FPADDSUB_DMP_SFG[18]), .Y(n4405) );
OAI211XLTS U4810 ( .A0(n2397), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n2521), .C0(
n2520), .Y(n2524) );
OAI21XLTS U4811 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n2397), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n2522) );
OAI32X4TS U4812 ( .A0(n5387), .A1(FPADDSUB_Raw_mant_NRM_SWR[0]), .A2(n2336),
.B0(n5386), .B1(n2360), .Y(n6522) );
AOI21X2TS U4813 ( .A0(n2312), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n4480),
.Y(n6001) );
OR2X1TS U4814 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]),
.Y(n6071) );
NAND2X1TS U4815 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n6070) );
OR2X1TS U4816 ( .A(n6862), .B(FPADDSUB_DMP_SFG[12]), .Y(n4393) );
NAND2X1TS U4817 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n6042) );
AOI21X2TS U4818 ( .A0(n2312), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n4480),
.Y(n5996) );
AOI211X4TS U4819 ( .A0(n5944), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n5948),
.C0(n4479), .Y(n5989) );
NAND3X1TS U4820 ( .A(n4274), .B(n5951), .C(FPADDSUB_shift_value_SHT2_EWR[3]),
.Y(n5966) );
CLKBUFX2TS U4821 ( .A(n3853), .Y(n2396) );
NOR2X1TS U4822 ( .A(n3852), .B(n2396), .Y(DP_OP_501J223_127_5235_n521) );
NOR2X1TS U4823 ( .A(n3841), .B(n2396), .Y(n3855) );
NOR2X1TS U4824 ( .A(n3706), .B(n2396), .Y(DP_OP_501J223_127_5235_n260) );
NOR2X1TS U4825 ( .A(n2486), .B(n2396), .Y(DP_OP_501J223_127_5235_n259) );
NOR2X1TS U4826 ( .A(n2295), .B(n3853), .Y(DP_OP_501J223_127_5235_n523) );
NOR2X1TS U4827 ( .A(n2384), .B(n3853), .Y(n3858) );
NOR2X1TS U4828 ( .A(n3707), .B(n3853), .Y(DP_OP_501J223_127_5235_n261) );
NOR2X1TS U4829 ( .A(n3709), .B(n3853), .Y(DP_OP_501J223_127_5235_n263) );
NOR2X1TS U4830 ( .A(n3850), .B(n3853), .Y(n3838) );
NOR2X1TS U4831 ( .A(n3703), .B(n3853), .Y(n3689) );
NOR2X1TS U4832 ( .A(n2331), .B(n3853), .Y(n3494) );
NOR2X1TS U4833 ( .A(n2293), .B(n3853), .Y(n3734) );
NOR3X1TS U4834 ( .A(n2568), .B(n2567), .C(FPADDSUB_intDY_EWSW[28]), .Y(n2569) );
OAI2BB2XLTS U4835 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n2505), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n2448), .Y(n2514) );
NOR3X2TS U4836 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .C(n4690), .Y(n4753) );
NOR2XLTS U4837 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n4692) );
INVX2TS U4838 ( .A(n7077), .Y(n6735) );
INVX2TS U4839 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(n2866) );
NAND2X2TS U4840 ( .A(n2443), .B(n3431), .Y(DP_OP_501J223_127_5235_n630) );
INVX2TS U4841 ( .A(n3963), .Y(n3639) );
INVX2TS U4842 ( .A(DP_OP_501J223_127_5235_n723), .Y(n3865) );
NAND2X4TS U4843 ( .A(n2437), .B(n3467), .Y(DP_OP_501J223_127_5235_n723) );
AO21X1TS U4844 ( .A0(n2500), .A1(n3807), .B0(n3740), .Y(n2426) );
AND2X2TS U4845 ( .A(n3575), .B(n3559), .Y(n2429) );
OR2X1TS U4846 ( .A(n6568), .B(FPMULT_Op_MX[12]), .Y(n2437) );
OR2X1TS U4847 ( .A(FPMULT_Op_MY[12]), .B(DP_OP_501J223_127_5235_n897), .Y(
n2443) );
OR2X2TS U4848 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MX[5]), .Y(n2456) );
INVX2TS U4849 ( .A(n2458), .Y(n5638) );
OR2X1TS U4850 ( .A(n4225), .B(n2906), .Y(n2462) );
OR2X1TS U4851 ( .A(n3975), .B(n2473), .Y(n2474) );
INVX2TS U4852 ( .A(n2483), .Y(n5649) );
INVX2TS U4853 ( .A(n2484), .Y(n5650) );
OR2X2TS U4854 ( .A(n3035), .B(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .Y(
n2485) );
INVX2TS U4855 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .Y(n2780) );
OR2X1TS U4856 ( .A(n4028), .B(n4027), .Y(n2489) );
OR2X1TS U4857 ( .A(n3855), .B(n3854), .Y(n2492) );
OR2X1TS U4858 ( .A(n3858), .B(n3857), .Y(n2496) );
NAND2X2TS U4859 ( .A(DP_OP_499J223_125_1651_n222), .B(
DP_OP_499J223_125_1651_n224), .Y(n2498) );
OR2X1TS U4860 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n2502) );
AND2X2TS U4861 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n3293), .Y(n2503) );
INVX2TS U4862 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(n2816) );
NOR2X4TS U4863 ( .A(n2659), .B(n2662), .Y(n2665) );
NOR2X2TS U4864 ( .A(n4057), .B(n4056), .Y(n4066) );
INVX2TS U4865 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(n3155) );
OR2X4TS U4866 ( .A(n2668), .B(n2667), .Y(n2669) );
INVX2TS U4867 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(n2682) );
INVX2TS U4868 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(n3176) );
NAND2X1TS U4869 ( .A(n2833), .B(n2858), .Y(n2834) );
AOI21X1TS U4870 ( .A0(n4035), .A1(n6746), .B0(n4034), .Y(n4038) );
INVX2TS U4871 ( .A(n2695), .Y(n2681) );
NOR2X1TS U4872 ( .A(n6748), .B(FPADDSUB_intDX_EWSW[11]), .Y(n2533) );
NAND2X1TS U4873 ( .A(n2852), .B(n2857), .Y(n2853) );
INVX2TS U4874 ( .A(n6274), .Y(DP_OP_499J223_125_1651_n281) );
INVX2TS U4875 ( .A(n4207), .Y(DP_OP_499J223_125_1651_n300) );
NAND2X1TS U4876 ( .A(n3123), .B(n2200), .Y(n3124) );
NOR2X2TS U4877 ( .A(n5643), .B(n6587), .Y(n4434) );
OAI21X1TS U4878 ( .A0(n3816), .A1(n3815), .B0(n3814), .Y(n3821) );
NAND2X1TS U4879 ( .A(n3628), .B(n3627), .Y(n3629) );
INVX2TS U4880 ( .A(n2775), .Y(n2776) );
NAND2X1TS U4881 ( .A(n3194), .B(n3181), .Y(n3179) );
OA21XLTS U4882 ( .A0(n4564), .A1(n4561), .B0(n4565), .Y(n4438) );
NOR2X1TS U4883 ( .A(n4793), .B(n5845), .Y(n4784) );
NAND2X1TS U4884 ( .A(n3544), .B(n3543), .Y(n3545) );
OR2X1TS U4885 ( .A(n2705), .B(n2704), .Y(n2909) );
NAND2X1TS U4886 ( .A(n3137), .B(DP_OP_496J223_122_3236_n147), .Y(n3138) );
INVX2TS U4887 ( .A(n4250), .Y(n5536) );
NAND2X1TS U4888 ( .A(n3367), .B(n3366), .Y(n3368) );
OAI22X1TS U4889 ( .A0(n3850), .A1(n3843), .B0(n2294), .B1(n3842), .Y(
DP_OP_501J223_127_5235_n497) );
NOR2X1TS U4890 ( .A(n3841), .B(n3845), .Y(n3839) );
OAI22X1TS U4891 ( .A0(n2387), .A1(n3696), .B0(n2334), .B1(n3695), .Y(
DP_OP_501J223_127_5235_n216) );
OAI22X1TS U4892 ( .A0(n2387), .A1(n3702), .B0(n2334), .B1(n3701), .Y(
DP_OP_501J223_127_5235_n243) );
OAI22X1TS U4893 ( .A0(n2334), .A1(n3704), .B0(n2335), .B1(n3705), .Y(
DP_OP_501J223_127_5235_n253) );
INVX2TS U4894 ( .A(n3476), .Y(n3478) );
NOR2XLTS U4895 ( .A(n4534), .B(n4529), .Y(n4256) );
NAND2X1TS U4896 ( .A(n2962), .B(n2961), .Y(n2963) );
INVX2TS U4897 ( .A(n6101), .Y(n6103) );
INVX2TS U4898 ( .A(n3180), .Y(n3239) );
INVX2TS U4899 ( .A(n3308), .Y(n3256) );
OAI22X1TS U4900 ( .A0(n3848), .A1(n3847), .B0(n2295), .B1(n3846), .Y(
DP_OP_501J223_127_5235_n509) );
OAI22X1TS U4901 ( .A0(n2387), .A1(n3699), .B0(n2486), .B1(n3700), .Y(
DP_OP_501J223_127_5235_n233) );
NOR2X1TS U4902 ( .A(n3708), .B(n3853), .Y(DP_OP_501J223_127_5235_n262) );
CMPR42X1TS U4903 ( .A(DP_OP_500J223_126_4510_n151), .B(
DP_OP_500J223_126_4510_n158), .C(DP_OP_500J223_126_4510_n132), .D(
DP_OP_500J223_126_4510_n165), .ICI(DP_OP_500J223_126_4510_n130), .S(
DP_OP_500J223_126_4510_n126), .ICO(DP_OP_500J223_126_4510_n124), .CO(
DP_OP_500J223_126_4510_n125) );
INVX4TS U4904 ( .A(n4302), .Y(n5617) );
OR2X1TS U4905 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]),
.Y(n6173) );
NOR2XLTS U4906 ( .A(n6861), .B(FPADDSUB_DMP_SFG[0]), .Y(n4369) );
CLKXOR2X4TS U4907 ( .A(n3114), .B(n3093), .Y(n4220) );
INVX4TS U4908 ( .A(n2480), .Y(n6570) );
NAND2X1TS U4909 ( .A(n5489), .B(n5494), .Y(n5152) );
INVX2TS U4910 ( .A(n3806), .Y(n3740) );
NAND2X1TS U4911 ( .A(n5567), .B(n2487), .Y(n5195) );
OAI21XLTS U4912 ( .A0(n4535), .A1(n4534), .B0(n4533), .Y(n4537) );
INVX2TS U4913 ( .A(n4210), .Y(n4198) );
OAI21XLTS U4914 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n5631), .B0(n5630), .Y(
n5632) );
AND2X2TS U4915 ( .A(n4687), .B(n4809), .Y(n5207) );
OR2X1TS U4916 ( .A(n5340), .B(FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n5252) );
INVX2TS U4917 ( .A(n3979), .Y(n3981) );
OR2X1TS U4918 ( .A(n3389), .B(n3388), .Y(n5531) );
INVX2TS U4919 ( .A(n3783), .Y(n3785) );
INVX2TS U4920 ( .A(n3281), .Y(n4423) );
OR2X1TS U4921 ( .A(n5340), .B(FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n5246) );
BUFX3TS U4922 ( .A(n6549), .Y(n6510) );
OR2X1TS U4923 ( .A(n5465), .B(n5464), .Y(n5467) );
NAND2X1TS U4924 ( .A(n4007), .B(n4006), .Y(n4008) );
NAND2X1TS U4925 ( .A(n3796), .B(n3795), .Y(n3797) );
NAND2X1TS U4926 ( .A(n3567), .B(n3566), .Y(n3568) );
NAND2X1TS U4927 ( .A(n3501), .B(n3604), .Y(n3606) );
OAI21X1TS U4928 ( .A0(n5573), .A1(n5553), .B0(n5552), .Y(n5557) );
OR2X1TS U4929 ( .A(n5469), .B(n5468), .Y(n5471) );
NAND2X1TS U4930 ( .A(n6148), .B(n6867), .Y(n4271) );
INVX2TS U4931 ( .A(n2463), .Y(n5648) );
INVX2TS U4932 ( .A(FPSENCOS_d_ff2_X[14]), .Y(n6417) );
INVX2TS U4933 ( .A(FPSENCOS_d_ff2_X[20]), .Y(n6425) );
XNOR2X1TS U4934 ( .A(n3398), .B(n3397), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10) );
OAI32X1TS U4935 ( .A0(n6456), .A1(FPSENCOS_cont_iter_out[3]), .A2(n4555),
.B0(n4554), .B1(n6899), .Y(n2114) );
INVX2TS U4937 ( .A(FPADDSUB_intDX_EWSW[5]), .Y(n6692) );
OAI21X1TS U4938 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n2466), .B0(n2508), .Y(
n2550) );
NOR2X1TS U4939 ( .A(n2460), .B(FPADDSUB_intDX_EWSW[17]), .Y(n2554) );
AOI22X1TS U4940 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n2460), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n2507), .Y(n2510) );
OAI32X1TS U4941 ( .A0(n2550), .A1(n2551), .A2(n2510), .B0(n2509), .B1(n2551),
.Y(n2513) );
OAI2BB2XLTS U4942 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n2511), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n2438), .Y(n2512) );
AOI211X1TS U4943 ( .A0(n2515), .A1(n2514), .B0(n2513), .C0(n2512), .Y(n2558)
);
INVX2TS U4944 ( .A(FPADDSUB_intDX_EWSW[10]), .Y(n2516) );
AOI21X1TS U4945 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n2516), .B0(n2533), .Y(
n2538) );
OAI2BB1X1TS U4946 ( .A0N(n2465), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n2517) );
OAI22X1TS U4947 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n2517), .B0(n6692), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n2530) );
INVX2TS U4948 ( .A(FPADDSUB_intDX_EWSW[7]), .Y(n2526) );
OAI2BB1X1TS U4949 ( .A0N(n2526), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n2518) );
OAI2BB2XLTS U4950 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n2519), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n2433), .Y(n2521) );
AOI22X1TS U4951 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n2526), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n2525), .Y(n2527) );
OAI2BB2XLTS U4952 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n2532), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n2467), .Y(n2544) );
AOI22X1TS U4953 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n6748), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n2534), .Y(n2540) );
AOI21X1TS U4954 ( .A0(n2537), .A1(n2536), .B0(n2547), .Y(n2539) );
OAI31X1TS U4955 ( .A0(n2549), .A1(n2548), .A2(n2547), .B0(n2546), .Y(n2556)
);
AOI211X1TS U4956 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n2552), .B0(n2551),
.C0(n2550), .Y(n2553) );
OAI21X1TS U4957 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n2423), .B0(n2562), .Y(
n2565) );
NOR2X1TS U4958 ( .A(n2421), .B(FPADDSUB_intDX_EWSW[25]), .Y(n2560) );
INVX2TS U4959 ( .A(FPADDSUB_intDX_EWSW[28]), .Y(n2568) );
NOR2X1TS U4960 ( .A(n2430), .B(FPADDSUB_intDX_EWSW[29]), .Y(n2567) );
NAND4BBX1TS U4961 ( .AN(n2565), .BN(n2560), .C(n2572), .D(n2559), .Y(n2575)
);
AOI22X1TS U4962 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n2421), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n2561), .Y(n2566) );
OAI211X1TS U4963 ( .A0(n2566), .A1(n2565), .B0(n2564), .C0(n2563), .Y(n2573)
);
NAND2X2TS U4964 ( .A(FPADDSUB_Shift_reg_FLAGS_7_6), .B(n6706), .Y(n2577) );
BUFX3TS U4965 ( .A(n2577), .Y(n5433) );
BUFX3TS U4966 ( .A(n6708), .Y(n6714) );
BUFX3TS U4967 ( .A(n6714), .Y(n5418) );
AOI22X1TS U4968 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[5]), .B1(n5418), .Y(n2578) );
NOR2X2TS U4969 ( .A(n6751), .B(FPMULT_FS_Module_state_reg[3]), .Y(n6564) );
INVX4TS U4970 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .Y(n2580)
);
INVX4TS U4971 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .Y(n2581)
);
NOR2X8TS U4972 ( .A(n2587), .B(n2586), .Y(n2629) );
ADDFHX4TS U4973 ( .A(n2579), .B(n2580), .CI(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[2]), .CO(
n2588), .S(n2587) );
NOR2X8TS U4974 ( .A(n2589), .B(n2588), .Y(n2631) );
NOR2X4TS U4975 ( .A(n2629), .B(n2631), .Y(n2585) );
XNOR2X4TS U4976 ( .A(n2581), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]), .Y(
n2584) );
NAND2X4TS U4977 ( .A(n2582), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]), .Y(
n2619) );
INVX2TS U4978 ( .A(n2619), .Y(n2583) );
AOI21X4TS U4979 ( .A0(n2700), .A1(n2620), .B0(n2583), .Y(n2617) );
OAI21X4TS U4980 ( .A0(n2614), .A1(n2617), .B0(n2615), .Y(n2611) );
OAI21X4TS U4981 ( .A0(n2631), .A1(n2628), .B0(n2632), .Y(n2590) );
NOR2X8TS U4982 ( .A(n2404), .B(n2590), .Y(n2667) );
INVX4TS U4983 ( .A(FPMULT_Sgf_operation_Result[4]), .Y(n2596) );
INVX2TS U4984 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(n2595)
);
INVX4TS U4985 ( .A(n2602), .Y(n2626) );
INVX2TS U4986 ( .A(n2625), .Y(n2594) );
INVX2TS U4987 ( .A(n2604), .Y(n2599) );
OAI21X4TS U4988 ( .A0(n2604), .A1(n2625), .B0(n2603), .Y(n2664) );
INVX2TS U4989 ( .A(n2659), .Y(n2608) );
NOR2X4TS U4990 ( .A(n4215), .B(n2897), .Y(n2644) );
INVX4TS U4991 ( .A(n2611), .Y(n2630) );
INVX2TS U4992 ( .A(n2629), .Y(n2612) );
NAND2X2TS U4993 ( .A(n2612), .B(n2628), .Y(n2613) );
XOR2X4TS U4994 ( .A(n2630), .B(n2613), .Y(n2623) );
OR2X4TS U4995 ( .A(n2623), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(n4222) );
INVX2TS U4996 ( .A(n2614), .Y(n2616) );
NAND2X2TS U4997 ( .A(n2616), .B(n2615), .Y(n2618) );
XOR2X4TS U4998 ( .A(n2618), .B(n2617), .Y(n2622) );
XNOR2X4TS U4999 ( .A(n2621), .B(n2700), .Y(n2719) );
AOI21X4TS U5000 ( .A0(n4222), .A1(n4223), .B0(n2624), .Y(n4197) );
NAND2X2TS U5001 ( .A(n2626), .B(n2625), .Y(n2627) );
XOR2X4TS U5002 ( .A(n2667), .B(n2627), .Y(n2637) );
OAI21X4TS U5003 ( .A0(n2630), .A1(n2629), .B0(n2628), .Y(n2635) );
INVX2TS U5004 ( .A(n2631), .Y(n2633) );
NAND2X2TS U5005 ( .A(n2633), .B(n2632), .Y(n2634) );
XNOR2X4TS U5006 ( .A(n2635), .B(n2634), .Y(n2636) );
NAND2X2TS U5007 ( .A(n4200), .B(n4211), .Y(n2640) );
NAND2X4TS U5008 ( .A(n2636), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(n4210) );
AOI21X4TS U5009 ( .A0(n4200), .A1(n4198), .B0(n2638), .Y(n2639) );
OAI21X4TS U5010 ( .A0(n4197), .A1(n2640), .B0(n2639), .Y(n2896) );
OAI21X4TS U5011 ( .A0(n2897), .A1(n4216), .B0(n2898), .Y(n2643) );
AOI21X4TS U5012 ( .A0(n2644), .A1(n2896), .B0(n2643), .Y(n2843) );
INVX2TS U5013 ( .A(n2666), .Y(n2645) );
NOR2X2TS U5014 ( .A(n2645), .B(n2659), .Y(n2648) );
AOI21X2TS U5015 ( .A0(n2649), .A1(n2648), .B0(n2647), .Y(n2656) );
INVX2TS U5016 ( .A(n2662), .Y(n2654) );
XOR2X4TS U5017 ( .A(n2656), .B(n2655), .Y(n2657) );
INVX2TS U5018 ( .A(n2889), .Y(n2658) );
AOI21X4TS U5019 ( .A0(n2931), .A1(n2888), .B0(n2658), .Y(n2679) );
AOI21X4TS U5020 ( .A0(n2665), .A1(n2664), .B0(n2663), .Y(n2670) );
NAND2X4TS U5021 ( .A(n2666), .B(n2665), .Y(n2668) );
NAND2X8TS U5022 ( .A(n2670), .B(n2669), .Y(n2864) );
OR2X4TS U5023 ( .A(n2674), .B(n2673), .Y(n2822) );
NAND2X4TS U5024 ( .A(n2674), .B(n2673), .Y(n2815) );
XNOR2X4TS U5025 ( .A(n2864), .B(n2675), .Y(n2676) );
INVX2TS U5026 ( .A(n2840), .Y(n2677) );
XOR2X4TS U5027 ( .A(n2679), .B(n2678), .Y(n6747) );
NOR2X6TS U5028 ( .A(DP_OP_499J223_125_1651_n231), .B(
DP_OP_499J223_125_1651_n233), .Y(n3030) );
NOR2X4TS U5029 ( .A(n3024), .B(n3030), .Y(n2753) );
OR2X2TS U5030 ( .A(DP_OP_499J223_125_1651_n246), .B(
DP_OP_499J223_125_1651_n248), .Y(n2996) );
NAND2X2TS U5031 ( .A(n2998), .B(n2996), .Y(n2747) );
XNOR2X4TS U5032 ( .A(n2684), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]), .Y(n2683) );
NOR2X4TS U5033 ( .A(n2683), .B(n2682), .Y(n2690) );
INVX4TS U5034 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .Y(n2680) );
AOI21X4TS U5035 ( .A0(n2696), .A1(n2904), .B0(n2681), .Y(n2693) );
NAND2X2TS U5036 ( .A(n2683), .B(n2682), .Y(n2691) );
OAI21X4TS U5037 ( .A0(n2690), .A1(n2693), .B0(n2691), .Y(n2804) );
NOR2X8TS U5038 ( .A(n2686), .B(n2685), .Y(n2799) );
INVX2TS U5039 ( .A(n2799), .Y(n2687) );
NAND2X6TS U5040 ( .A(n2686), .B(n2685), .Y(n2801) );
NAND2X2TS U5041 ( .A(n2687), .B(n2801), .Y(n2688) );
OR2X4TS U5042 ( .A(n2689), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(n2778)
);
NAND2X4TS U5043 ( .A(n2689), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(n2775)
);
NAND2X1TS U5044 ( .A(n2778), .B(n2775), .Y(n2699) );
INVX2TS U5045 ( .A(n2690), .Y(n2692) );
XNOR2X2TS U5046 ( .A(n2699), .B(n2777), .Y(n3067) );
INVX2TS U5047 ( .A(n3067), .Y(n2743) );
INVX2TS U5048 ( .A(FPMULT_Sgf_operation_Result[1]), .Y(n2703) );
XNOR2X1TS U5049 ( .A(n2703), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n2702) );
NOR2X1TS U5050 ( .A(n2702), .B(n2682), .Y(n2891) );
INVX2TS U5051 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .Y(n2904) );
NAND2X1TS U5052 ( .A(n2700), .B(n2727), .Y(n2902) );
INVX2TS U5053 ( .A(n2902), .Y(n2701) );
AOI21X1TS U5054 ( .A0(n2903), .A1(n2904), .B0(n2701), .Y(n2894) );
NAND2X1TS U5055 ( .A(n2702), .B(n2682), .Y(n2892) );
OAI21X2TS U5056 ( .A0(n2891), .A1(n2894), .B0(n2892), .Y(n2911) );
INVX2TS U5057 ( .A(FPMULT_Sgf_operation_Result[2]), .Y(n2707) );
INVX2TS U5058 ( .A(n2908), .Y(n2706) );
AOI21X2TS U5059 ( .A0(n2911), .A1(n2909), .B0(n2706), .Y(n2922) );
INVX2TS U5060 ( .A(FPMULT_Sgf_operation_Result[3]), .Y(n2711) );
INVX2TS U5061 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .Y(n2710) );
CMPR32X2TS U5062 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]), .B(n2707), .C(n2780), .CO(n2708), .S(n2705) );
NOR2X1TS U5063 ( .A(n2709), .B(n2708), .Y(n2918) );
NAND2X1TS U5064 ( .A(n2709), .B(n2708), .Y(n2919) );
INVX2TS U5065 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .Y(n2716) );
CMPR32X2TS U5066 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .B(n2711), .C(n2710), .CO(n2712), .S(n2709) );
NAND2X1TS U5067 ( .A(n2713), .B(n2712), .Y(n2937) );
INVX2TS U5068 ( .A(n2937), .Y(n2714) );
AOI21X4TS U5069 ( .A0(n2940), .A1(n2938), .B0(n2714), .Y(n2960) );
INVX2TS U5070 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[5]), .Y(n2715) );
INVX2TS U5071 ( .A(n2715), .Y(n6259) );
CMPR32X2TS U5072 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .B(n2596), .C(n2716), .CO(n2717), .S(n2713) );
NOR2X1TS U5073 ( .A(n2718), .B(n2717), .Y(n2956) );
NAND2X1TS U5074 ( .A(n2718), .B(n2717), .Y(n2957) );
OAI21X4TS U5075 ( .A0(n2960), .A1(n2956), .B0(n2957), .Y(n2955) );
CMPR32X2TS U5076 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .B(n2715), .C(n3120), .CO(n2730), .S(n2718) );
INVX2TS U5077 ( .A(n6275), .Y(n2729) );
INVX2TS U5078 ( .A(n3061), .Y(n2723) );
OR2X2TS U5079 ( .A(n2724), .B(n2723), .Y(n2953) );
NAND2X1TS U5080 ( .A(n2724), .B(n2723), .Y(n2952) );
INVX2TS U5081 ( .A(n2952), .Y(n2725) );
OR2X4TS U5082 ( .A(n2726), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]), .Y(
n4035) );
NAND2X4TS U5083 ( .A(n2726), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]), .Y(
n4033) );
INVX2TS U5084 ( .A(n2731), .Y(n2733) );
INVX2TS U5085 ( .A(n6276), .Y(n4237) );
INVX2TS U5086 ( .A(n2736), .Y(n2738) );
INVX2TS U5087 ( .A(n3065), .Y(n2741) );
NOR2X2TS U5088 ( .A(n2742), .B(n2741), .Y(n2965) );
INVX2TS U5089 ( .A(n2880), .Y(n2744) );
NAND2X2TS U5090 ( .A(DP_OP_499J223_125_1651_n246), .B(
DP_OP_499J223_125_1651_n248), .Y(n2813) );
INVX2TS U5091 ( .A(n2813), .Y(n2995) );
INVX2TS U5092 ( .A(n2999), .Y(n2745) );
AOI21X4TS U5093 ( .A0(n2998), .A1(n2995), .B0(n2745), .Y(n2746) );
OAI21X4TS U5094 ( .A0(n2747), .A1(n2812), .B0(n2746), .Y(n2987) );
OR2X4TS U5095 ( .A(DP_OP_499J223_125_1651_n240), .B(
DP_OP_499J223_125_1651_n242), .Y(n2986) );
NAND2X2TS U5096 ( .A(DP_OP_499J223_125_1651_n240), .B(
DP_OP_499J223_125_1651_n242), .Y(n2985) );
INVX2TS U5097 ( .A(n2985), .Y(n2748) );
AOI21X4TS U5098 ( .A0(n2987), .A1(n2986), .B0(n2748), .Y(n3010) );
INVX2TS U5099 ( .A(n3015), .Y(n3011) );
AOI21X4TS U5100 ( .A0(n2470), .A1(n3011), .B0(n2749), .Y(n2750) );
OAI21X4TS U5101 ( .A0(n2751), .A1(n3010), .B0(n2750), .Y(n3023) );
NAND2X4TS U5102 ( .A(DP_OP_499J223_125_1651_n231), .B(
DP_OP_499J223_125_1651_n233), .Y(n3031) );
OAI21X4TS U5103 ( .A0(n3024), .A1(n3031), .B0(n3025), .Y(n2752) );
AOI21X4TS U5104 ( .A0(n2753), .A1(n3023), .B0(n2752), .Y(n2766) );
NOR2X6TS U5105 ( .A(DP_OP_499J223_125_1651_n222), .B(
DP_OP_499J223_125_1651_n224), .Y(n3042) );
NOR2X4TS U5106 ( .A(n3040), .B(n3042), .Y(n3050) );
INVX2TS U5107 ( .A(n3050), .Y(n2754) );
NOR2X6TS U5108 ( .A(DP_OP_499J223_125_1651_n219), .B(
DP_OP_499J223_125_1651_n221), .Y(n3052) );
NAND2X4TS U5109 ( .A(DP_OP_499J223_125_1651_n225), .B(
DP_OP_499J223_125_1651_n227), .Y(n3047) );
OAI21X4TS U5110 ( .A0(n3042), .A1(n3047), .B0(n2498), .Y(n3049) );
INVX2TS U5111 ( .A(n3049), .Y(n2755) );
NAND2X4TS U5112 ( .A(DP_OP_499J223_125_1651_n219), .B(
DP_OP_499J223_125_1651_n221), .Y(n3053) );
INVX2TS U5113 ( .A(n2762), .Y(n2758) );
XOR2X4TS U5114 ( .A(n2760), .B(n2759), .Y(n3066) );
NOR2X4TS U5115 ( .A(n3066), .B(n3065), .Y(n4188) );
NAND2X2TS U5116 ( .A(n2764), .B(n3050), .Y(n2767) );
OAI21X4TS U5117 ( .A0(n2762), .A1(n3053), .B0(n2761), .Y(n2763) );
AOI21X4TS U5118 ( .A0(n2764), .A1(n3049), .B0(n2763), .Y(n2765) );
OAI21X4TS U5119 ( .A0(n2767), .A1(n2766), .B0(n2765), .Y(n2768) );
CLKINVX12TS U5120 ( .A(n2768), .Y(n3109) );
INVX16TS U5121 ( .A(n3109), .Y(n3136) );
NAND2X4TS U5122 ( .A(DP_OP_499J223_125_1651_n213), .B(
DP_OP_499J223_125_1651_n215), .Y(n2791) );
NAND2X2TS U5123 ( .A(n2791), .B(n2771), .Y(n2769) );
XNOR2X4TS U5124 ( .A(n3136), .B(n2769), .Y(n3068) );
NOR2X4TS U5125 ( .A(n4188), .B(n4190), .Y(n4450) );
INVX2TS U5126 ( .A(n2791), .Y(n2770) );
AOI21X4TS U5127 ( .A0(n3136), .A1(n2771), .B0(n2770), .Y(n2774) );
NOR2X8TS U5128 ( .A(DP_OP_499J223_125_1651_n210), .B(
DP_OP_499J223_125_1651_n212), .Y(n2792) );
INVX2TS U5129 ( .A(n2792), .Y(n2772) );
XOR2X4TS U5130 ( .A(n2774), .B(n2773), .Y(n3069) );
AOI21X4TS U5131 ( .A0(n2778), .A1(n2777), .B0(n2776), .Y(n3082) );
INVX6TS U5132 ( .A(n3082), .Y(n2809) );
OAI21X4TS U5133 ( .A0(n2779), .A1(n2799), .B0(n2801), .Y(n2786) );
INVX4TS U5134 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(n2796) );
INVX2TS U5135 ( .A(n2802), .Y(n2784) );
XNOR2X4TS U5136 ( .A(n2786), .B(n2785), .Y(n2787) );
XNOR2X4TS U5137 ( .A(n2809), .B(n2788), .Y(n4234) );
NOR2X4TS U5138 ( .A(n2789), .B(n2792), .Y(n3102) );
OAI21X4TS U5139 ( .A0(n2792), .A1(n2791), .B0(n2790), .Y(n3108) );
AOI21X4TS U5140 ( .A0(n3136), .A1(n3102), .B0(n3108), .Y(n2795) );
NOR2X8TS U5141 ( .A(DP_OP_499J223_125_1651_n207), .B(
DP_OP_499J223_125_1651_n209), .Y(n3101) );
INVX2TS U5142 ( .A(n3101), .Y(n2793) );
NAND2X4TS U5143 ( .A(DP_OP_499J223_125_1651_n207), .B(
DP_OP_499J223_125_1651_n209), .Y(n3105) );
NAND2X2TS U5144 ( .A(n2793), .B(n3105), .Y(n2794) );
XOR2X4TS U5145 ( .A(n2795), .B(n2794), .Y(n3070) );
ADDFHX4TS U5146 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[3]), .B(n2796), .CI(n2710), .CO(n2797), .S(n2783) );
NOR2X4TS U5147 ( .A(n2798), .B(n2797), .Y(n3115) );
NAND2X4TS U5148 ( .A(n2798), .B(n2797), .Y(n3117) );
NAND2X2TS U5149 ( .A(n3084), .B(n3117), .Y(n2806) );
NOR2X4TS U5150 ( .A(n2799), .B(n2802), .Y(n2805) );
OAI21X4TS U5151 ( .A0(n2802), .A1(n2801), .B0(n2800), .Y(n2803) );
AOI21X4TS U5152 ( .A0(n2805), .A1(n2804), .B0(n2803), .Y(n3171) );
INVX8TS U5153 ( .A(n3171), .Y(n3152) );
XNOR2X4TS U5154 ( .A(n2806), .B(n3152), .Y(n2807) );
NAND2X4TS U5155 ( .A(n2807), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .Y(n3076) );
XOR2X4TS U5156 ( .A(n2811), .B(n2810), .Y(n4208) );
NAND2X4TS U5157 ( .A(n4450), .B(n3072), .Y(n3074) );
NAND2X1TS U5158 ( .A(n2996), .B(n2813), .Y(n2814) );
AOI21X4TS U5159 ( .A0(n2864), .A1(n2822), .B0(n2825), .Y(n2821) );
XOR2X4TS U5160 ( .A(n2821), .B(n2820), .Y(n2837) );
INVX2TS U5161 ( .A(n2856), .Y(n2828) );
AOI21X4TS U5162 ( .A0(n2826), .A1(n2825), .B0(n2824), .Y(n2862) );
INVX2TS U5163 ( .A(n2862), .Y(n2827) );
AOI21X4TS U5164 ( .A0(n2864), .A1(n2828), .B0(n2827), .Y(n2835) );
INVX2TS U5165 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .Y(
n2848) );
CMPR32X2TS U5166 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9]), .B(
n2830), .C(n2829), .CO(n2831), .S(n2819) );
INVX2TS U5167 ( .A(n2855), .Y(n2833) );
NAND2X2TS U5168 ( .A(n2832), .B(n2831), .Y(n2858) );
XOR2X4TS U5169 ( .A(n2835), .B(n2834), .Y(n2838) );
NOR2X8TS U5170 ( .A(n2928), .B(n2932), .Y(n2842) );
OAI21X4TS U5171 ( .A0(n2889), .A1(n2840), .B0(n2836), .Y(n2925) );
NAND2X2TS U5172 ( .A(n2838), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(n2933)
);
OAI21X4TS U5173 ( .A0(n2932), .A1(n2926), .B0(n2933), .Y(n2839) );
AOI21X4TS U5174 ( .A0(n2842), .A1(n2925), .B0(n2839), .Y(n2845) );
NAND2X4TS U5175 ( .A(n2842), .B(n2923), .Y(n2844) );
NAND2X8TS U5176 ( .A(n2845), .B(n2197), .Y(n2992) );
INVX2TS U5177 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(
n2865) );
NOR2X4TS U5178 ( .A(n2851), .B(n2850), .Y(n2859) );
INVX2TS U5179 ( .A(n2859), .Y(n2852) );
NAND2X2TS U5180 ( .A(n2851), .B(n2850), .Y(n2857) );
CMPR32X2TS U5181 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11]), .B(
n2866), .C(n2865), .CO(n2867), .S(n2851) );
INVX2TS U5182 ( .A(n2871), .Y(n2868) );
NAND2X2TS U5183 ( .A(n2867), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]), .Y(
n2870) );
OAI21X4TS U5184 ( .A0(n2872), .A1(n2871), .B0(n2870), .Y(n2873) );
XNOR2X4TS U5185 ( .A(n2873), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13]), .Y(
n2876) );
INVX2TS U5186 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(n2886)
);
NAND2X4TS U5187 ( .A(n2876), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .Y(n2971)
);
NOR2X4TS U5188 ( .A(n2971), .B(n2886), .Y(n2877) );
AOI21X4TS U5189 ( .A0(n2884), .A1(n2878), .B0(n2877), .Y(n2991) );
OAI21X4TS U5190 ( .A0(n2964), .A1(n2989), .B0(n2991), .Y(n2879) );
INVX2TS U5191 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(n2990)
);
XNOR2X4TS U5192 ( .A(n2879), .B(n2990), .Y(n4231) );
NOR2X2TS U5193 ( .A(n2982), .B(n4231), .Y(n6306) );
XNOR2X1TS U5194 ( .A(n2883), .B(n2882), .Y(n2981) );
AOI21X4TS U5195 ( .A0(n2992), .A1(n2885), .B0(n2884), .Y(n2974) );
OAI21X4TS U5196 ( .A0(n2974), .A1(n2970), .B0(n2971), .Y(n2887) );
XNOR2X4TS U5197 ( .A(n2887), .B(n2886), .Y(n4230) );
NOR2X2TS U5198 ( .A(n2981), .B(n4230), .Y(n6304) );
XNOR2X4TS U5199 ( .A(n2207), .B(n2890), .Y(n4225) );
INVX1TS U5200 ( .A(n2891), .Y(n2893) );
NAND2X1TS U5201 ( .A(n2893), .B(n2892), .Y(n2895) );
XOR2X1TS U5202 ( .A(n2895), .B(n2894), .Y(n2906) );
OAI21X4TS U5203 ( .A0(n4219), .A1(n4215), .B0(n4216), .Y(n2901) );
INVX2TS U5204 ( .A(n2897), .Y(n2899) );
XNOR2X4TS U5205 ( .A(n2901), .B(n2900), .Y(n6270) );
NAND2X1TS U5206 ( .A(n2903), .B(n2902), .Y(n2905) );
XNOR2X1TS U5207 ( .A(n2905), .B(n2904), .Y(n6269) );
NAND2X1TS U5208 ( .A(n6270), .B(n6269), .Y(n6271) );
INVX2TS U5209 ( .A(n6271), .Y(n6239) );
NAND2X1TS U5210 ( .A(n4225), .B(n2906), .Y(n6238) );
INVX2TS U5211 ( .A(n6238), .Y(n2907) );
AOI21X1TS U5212 ( .A0(n2462), .A1(n6239), .B0(n2907), .Y(n6267) );
NAND2X1TS U5213 ( .A(n2909), .B(n2908), .Y(n2910) );
XNOR2X1TS U5214 ( .A(n2911), .B(n2910), .Y(n2912) );
NOR2X1TS U5215 ( .A(n2913), .B(n2912), .Y(n6263) );
NAND2X1TS U5216 ( .A(n2913), .B(n2912), .Y(n6264) );
AOI21X4TS U5217 ( .A0(n2209), .A1(n2923), .B0(n2925), .Y(n2916) );
INVX2TS U5218 ( .A(n2928), .Y(n2914) );
INVX2TS U5219 ( .A(n2918), .Y(n2920) );
NAND2X1TS U5220 ( .A(n2920), .B(n2919), .Y(n2921) );
XOR2X1TS U5221 ( .A(n2922), .B(n2921), .Y(n2941) );
NOR2X2TS U5222 ( .A(n2917), .B(n2941), .Y(n6251) );
INVX2TS U5223 ( .A(n2923), .Y(n2924) );
INVX2TS U5224 ( .A(n2925), .Y(n2927) );
AOI21X2TS U5225 ( .A0(n2209), .A1(n2930), .B0(n2929), .Y(n2936) );
INVX2TS U5226 ( .A(n2932), .Y(n2934) );
XOR2X4TS U5227 ( .A(n2936), .B(n2935), .Y(n4226) );
NAND2X1TS U5228 ( .A(n2938), .B(n2937), .Y(n2939) );
NOR2X2TS U5229 ( .A(n4226), .B(n2942), .Y(n6253) );
NOR2X1TS U5230 ( .A(n6251), .B(n6253), .Y(n2944) );
NAND2X1TS U5231 ( .A(n2917), .B(n2941), .Y(n6250) );
OAI21X1TS U5232 ( .A0(n6253), .A1(n6250), .B0(n6254), .Y(n2943) );
INVX2TS U5233 ( .A(n2961), .Y(n2946) );
AOI21X4TS U5234 ( .A0(n2992), .A1(n2962), .B0(n2946), .Y(n2951) );
INVX2TS U5235 ( .A(n2947), .Y(n2949) );
XOR2X4TS U5236 ( .A(n2951), .B(n2950), .Y(n4214) );
NAND2X1TS U5237 ( .A(n2953), .B(n2952), .Y(n2954) );
XNOR2X1TS U5238 ( .A(n2955), .B(n2954), .Y(n2976) );
NOR2X2TS U5239 ( .A(n4214), .B(n2976), .Y(n6285) );
INVX2TS U5240 ( .A(n2956), .Y(n2958) );
NAND2X1TS U5241 ( .A(n2958), .B(n2957), .Y(n2959) );
XOR2X1TS U5242 ( .A(n2960), .B(n2959), .Y(n2975) );
XOR2X4TS U5243 ( .A(n2964), .B(n2963), .Y(n4228) );
NOR2X1TS U5244 ( .A(n2975), .B(n4228), .Y(n6243) );
NOR2X1TS U5245 ( .A(n6285), .B(n6243), .Y(n6293) );
INVX2TS U5246 ( .A(n2965), .Y(n2967) );
NAND2X1TS U5247 ( .A(n2967), .B(n2966), .Y(n2969) );
XOR2X1TS U5248 ( .A(n2969), .B(n2968), .Y(n2977) );
INVX2TS U5249 ( .A(n2970), .Y(n2972) );
XOR2X4TS U5250 ( .A(n2974), .B(n2973), .Y(n4235) );
NAND2X1TS U5251 ( .A(n6293), .B(n2203), .Y(n2980) );
NAND2X1TS U5252 ( .A(n4228), .B(n2975), .Y(n6282) );
NAND2X1TS U5253 ( .A(n4214), .B(n2976), .Y(n6286) );
NAND2X1TS U5254 ( .A(n4235), .B(n2977), .Y(n6295) );
INVX2TS U5255 ( .A(n6295), .Y(n2978) );
AOI21X1TS U5256 ( .A0(n6292), .A1(n2203), .B0(n2978), .Y(n2979) );
OAI21X4TS U5257 ( .A0(n6242), .A1(n2980), .B0(n2979), .Y(n6299) );
NAND2X1TS U5258 ( .A(n2981), .B(n4230), .Y(n6303) );
NAND2X1TS U5259 ( .A(n2982), .B(n4231), .Y(n6307) );
AOI21X4TS U5260 ( .A0(n2984), .A1(n6299), .B0(n2983), .Y(n5924) );
NAND2X1TS U5261 ( .A(n2986), .B(n2985), .Y(n2988) );
XNOR2X1TS U5262 ( .A(n2988), .B(n2987), .Y(n3006) );
NOR2X4TS U5263 ( .A(n2989), .B(n2990), .Y(n2993) );
AOI2BB2X4TS U5264 ( .B0(n2993), .B1(n2992), .A0N(n2991), .A1N(n2990), .Y(
n3003) );
INVX2TS U5265 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .Y(n3002) );
XNOR2X4TS U5266 ( .A(n2994), .B(n2866), .Y(n4195) );
NAND2X1TS U5267 ( .A(n2999), .B(n2998), .Y(n3000) );
NAND2X2TS U5268 ( .A(n2204), .B(n2471), .Y(n3009) );
NAND2X1TS U5269 ( .A(n3004), .B(n4232), .Y(n6278) );
INVX2TS U5270 ( .A(n6278), .Y(n5925) );
NAND2X1TS U5271 ( .A(n3006), .B(n3005), .Y(n5926) );
INVX2TS U5272 ( .A(n5926), .Y(n3007) );
OAI21X4TS U5273 ( .A0(n5924), .A1(n3009), .B0(n3008), .Y(n5908) );
INVX2TS U5274 ( .A(n3010), .Y(n3017) );
NAND2X1TS U5275 ( .A(n2470), .B(n3012), .Y(n3013) );
NAND2X1TS U5276 ( .A(n3016), .B(n3015), .Y(n3018) );
XNOR2X2TS U5277 ( .A(n3018), .B(n3017), .Y(n3019) );
NOR2X2TS U5278 ( .A(n3019), .B(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .Y(
n5917) );
NOR2X2TS U5279 ( .A(n5909), .B(n5917), .Y(n3022) );
NAND2X2TS U5280 ( .A(n3019), .B(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .Y(
n5918) );
NAND2X2TS U5281 ( .A(n3020), .B(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(
n5910) );
OAI21X2TS U5282 ( .A0(n5909), .A1(n5918), .B0(n5910), .Y(n3021) );
AOI21X4TS U5283 ( .A0(n5908), .A1(n3022), .B0(n3021), .Y(n4314) );
OAI21X2TS U5284 ( .A0(n3034), .A1(n3030), .B0(n3031), .Y(n3028) );
INVX2TS U5285 ( .A(n3024), .Y(n3026) );
NOR2X2TS U5286 ( .A(n3036), .B(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .Y(
n3029) );
INVX4TS U5287 ( .A(n3029), .Y(n4317) );
INVX2TS U5288 ( .A(n3030), .Y(n3032) );
NAND2X2TS U5289 ( .A(n3032), .B(n3031), .Y(n3033) );
XOR2X2TS U5290 ( .A(n3034), .B(n3033), .Y(n3035) );
NAND2X2TS U5291 ( .A(n3035), .B(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .Y(
n5901) );
INVX2TS U5292 ( .A(n5901), .Y(n4315) );
NAND2X2TS U5293 ( .A(n3036), .B(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .Y(
n4316) );
INVX2TS U5294 ( .A(n4316), .Y(n3037) );
AOI21X2TS U5295 ( .A0(n4317), .A1(n4315), .B0(n3037), .Y(n3038) );
OAI21X4TS U5296 ( .A0(n4314), .A1(n3039), .B0(n3038), .Y(n3281) );
INVX2TS U5297 ( .A(n3040), .Y(n3046) );
INVX2TS U5298 ( .A(n3047), .Y(n3041) );
AOI21X4TS U5299 ( .A0(n3051), .A1(n3046), .B0(n3041), .Y(n3045) );
INVX2TS U5300 ( .A(n3042), .Y(n3043) );
XOR2X4TS U5301 ( .A(n3045), .B(n3044), .Y(n3058) );
NAND2X2TS U5302 ( .A(n3047), .B(n3046), .Y(n3048) );
XNOR2X4TS U5303 ( .A(n3051), .B(n3048), .Y(n3057) );
NOR2X2TS U5304 ( .A(n3057), .B(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .Y(
n3282) );
INVX2TS U5305 ( .A(n3052), .Y(n3054) );
NAND2X2TS U5306 ( .A(n3057), .B(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .Y(
n4420) );
AOI21X4TS U5307 ( .A0(n3284), .A1(n3060), .B0(n3059), .Y(n4322) );
AOI21X4TS U5308 ( .A0(n3281), .A1(n3064), .B0(n3063), .Y(n4187) );
NAND2X2TS U5309 ( .A(n3068), .B(n3067), .Y(n4191) );
OAI21X4TS U5310 ( .A0(n4190), .A1(n4330), .B0(n4191), .Y(n4452) );
NAND2X2TS U5311 ( .A(n3070), .B(n4208), .Y(n4460) );
OAI21X4TS U5312 ( .A0(n4459), .A1(n4453), .B0(n4460), .Y(n3071) );
AOI21X4TS U5313 ( .A0(n3072), .A1(n4452), .B0(n3071), .Y(n3073) );
OAI21X4TS U5314 ( .A0(n3074), .A1(n4187), .B0(n3073), .Y(n4337) );
NAND2X2TS U5315 ( .A(n3079), .B(n3075), .Y(n3081) );
INVX2TS U5316 ( .A(n3076), .Y(n3077) );
AOI21X4TS U5317 ( .A0(n3079), .A1(n3078), .B0(n3077), .Y(n3080) );
OAI21X4TS U5318 ( .A0(n3082), .A1(n3081), .B0(n3080), .Y(n3147) );
INVX2TS U5319 ( .A(n3117), .Y(n3083) );
AOI21X4TS U5320 ( .A0(n3152), .A1(n3084), .B0(n3083), .Y(n3090) );
INVX4TS U5321 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(n3120) );
NOR2X6TS U5322 ( .A(n3087), .B(n3086), .Y(n3118) );
INVX2TS U5323 ( .A(n3118), .Y(n3088) );
NAND2X2TS U5324 ( .A(n3087), .B(n3086), .Y(n3116) );
XOR2X4TS U5325 ( .A(n3090), .B(n3089), .Y(n3091) );
NOR2X4TS U5326 ( .A(n3091), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .Y(n3142) );
INVX2TS U5327 ( .A(n3142), .Y(n3092) );
INVX2TS U5328 ( .A(n3102), .Y(n3094) );
NOR2X2TS U5329 ( .A(n3094), .B(n3101), .Y(n3097) );
INVX2TS U5330 ( .A(n3108), .Y(n3095) );
OAI21X4TS U5331 ( .A0(n3095), .A1(n3101), .B0(n3105), .Y(n3096) );
AOI21X4TS U5332 ( .A0(n3136), .A1(n3097), .B0(n3096), .Y(n3100) );
NOR2X8TS U5333 ( .A(DP_OP_499J223_125_1651_n204), .B(
DP_OP_499J223_125_1651_n206), .Y(n3104) );
INVX2TS U5334 ( .A(n3104), .Y(n3098) );
XOR2X4TS U5335 ( .A(n3100), .B(n3099), .Y(n3247) );
NOR2X4TS U5336 ( .A(n4220), .B(n3247), .Y(n4179) );
AOI21X4TS U5337 ( .A0(n3108), .A1(n3107), .B0(n3106), .Y(n3133) );
OAI21X4TS U5338 ( .A0(n3109), .A1(n3130), .B0(n3133), .Y(n3113) );
INVX2TS U5339 ( .A(n3132), .Y(n3111) );
XNOR2X4TS U5340 ( .A(n3113), .B(n3112), .Y(n3248) );
NOR2X4TS U5341 ( .A(n3115), .B(n3118), .Y(n3170) );
OAI21X4TS U5342 ( .A0(n3118), .A1(n3117), .B0(n3116), .Y(n3168) );
INVX2TS U5343 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(n3154)
);
NOR2X6TS U5344 ( .A(n3121), .B(n3122), .Y(n3164) );
INVX2TS U5345 ( .A(n3164), .Y(n3123) );
INVX2TS U5346 ( .A(n3145), .Y(n3127) );
XNOR2X4TS U5347 ( .A(n3129), .B(n3128), .Y(n4204) );
NOR2X6TS U5348 ( .A(n3248), .B(n4204), .Y(n4182) );
OAI21X4TS U5349 ( .A0(n3133), .A1(n3132), .B0(n3131), .Y(n3134) );
AOI21X4TS U5350 ( .A0(n3136), .A1(n3135), .B0(n3134), .Y(n3141) );
XOR2X4TS U5351 ( .A(n3141), .B(n3140), .Y(n3249) );
OAI21X4TS U5352 ( .A0(n3145), .A1(n3144), .B0(n3143), .Y(n3146) );
AOI21X4TS U5353 ( .A0(n3148), .A1(n3147), .B0(n3146), .Y(n3217) );
INVX8TS U5354 ( .A(n3217), .Y(n3240) );
INVX2TS U5355 ( .A(n3170), .Y(n3149) );
NOR2X2TS U5356 ( .A(n3149), .B(n3164), .Y(n3153) );
INVX2TS U5357 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(n3175)
);
INVX2TS U5358 ( .A(n3166), .Y(n3158) );
NAND2X2TS U5359 ( .A(n3157), .B(n3156), .Y(n3165) );
XOR2X4TS U5360 ( .A(n3160), .B(n3159), .Y(n3161) );
NAND2X6TS U5361 ( .A(n3161), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(n3237)
);
NOR2X4TS U5362 ( .A(n3161), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(n3180)
);
XNOR2X4TS U5363 ( .A(n3240), .B(n3162), .Y(n4207) );
NOR2X4TS U5364 ( .A(n3249), .B(n4207), .Y(n3163) );
NOR2X6TS U5365 ( .A(n3164), .B(n3166), .Y(n3169) );
AOI21X4TS U5366 ( .A0(n3168), .A1(n3169), .B0(n3167), .Y(n3174) );
NAND2X4TS U5367 ( .A(n3170), .B(n3169), .Y(n3172) );
NAND2X8TS U5368 ( .A(n3174), .B(n3173), .Y(n3267) );
INVX2TS U5369 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(n3182)
);
XNOR2X4TS U5370 ( .A(n3267), .B(n3179), .Y(n3189) );
NOR2X6TS U5371 ( .A(n3189), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(n3241)
);
NOR2X4TS U5372 ( .A(n3180), .B(n3241), .Y(n3232) );
INVX2TS U5373 ( .A(n3232), .Y(n3188) );
AOI21X4TS U5374 ( .A0(n3267), .A1(n3194), .B0(n3197), .Y(n3187) );
INVX2TS U5375 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(n3201)
);
OR2X4TS U5376 ( .A(n3185), .B(n3184), .Y(n3198) );
NAND2X2TS U5377 ( .A(n3185), .B(n3184), .Y(n3195) );
XOR2X4TS U5378 ( .A(n3187), .B(n3186), .Y(n3190) );
NOR2X8TS U5379 ( .A(n3190), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(n3211)
);
NOR2X2TS U5380 ( .A(n3188), .B(n3211), .Y(n3193) );
NAND2X2TS U5381 ( .A(n3189), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(n3242)
);
OAI21X4TS U5382 ( .A0(n3237), .A1(n3241), .B0(n3242), .Y(n3231) );
INVX2TS U5383 ( .A(n3231), .Y(n3191) );
NAND2X4TS U5384 ( .A(n3190), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(n3233)
);
AOI21X2TS U5385 ( .A0(n3240), .A1(n3193), .B0(n3192), .Y(n3210) );
NAND2X4TS U5386 ( .A(n3194), .B(n3198), .Y(n3258) );
INVX2TS U5387 ( .A(n3258), .Y(n3200) );
INVX2TS U5388 ( .A(n3195), .Y(n3196) );
AOI21X4TS U5389 ( .A0(n3198), .A1(n3197), .B0(n3196), .Y(n3265) );
INVX2TS U5390 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .Y(n3222) );
INVX2TS U5391 ( .A(n3257), .Y(n3204) );
INVX2TS U5392 ( .A(n3213), .Y(n3208) );
XOR2X4TS U5393 ( .A(n3210), .B(n3209), .Y(n4229) );
NAND2X4TS U5394 ( .A(n3215), .B(n3232), .Y(n3218) );
AOI21X4TS U5395 ( .A0(n3215), .A1(n3231), .B0(n3214), .Y(n3216) );
OAI21X4TS U5396 ( .A0(n3218), .A1(n3217), .B0(n3216), .Y(n3219) );
INVX2TS U5397 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(n3270)
);
INVX2TS U5398 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .Y(n3269) );
INVX2TS U5399 ( .A(n3261), .Y(n3226) );
NAND2X2TS U5400 ( .A(n3225), .B(n3224), .Y(n3259) );
NAND2X1TS U5401 ( .A(n4229), .B(n4233), .Y(n3246) );
INVX2TS U5402 ( .A(n3211), .Y(n3234) );
INVX2TS U5403 ( .A(n3237), .Y(n3238) );
AOI21X4TS U5404 ( .A0(n3240), .A1(n3239), .B0(n3238), .Y(n3245) );
INVX2TS U5405 ( .A(n3241), .Y(n3243) );
XOR2X4TS U5406 ( .A(n3245), .B(n3244), .Y(n4206) );
NOR2X2TS U5407 ( .A(n3246), .B(n3400), .Y(n3352) );
INVX2TS U5408 ( .A(n3352), .Y(n3250) );
NOR2X4TS U5409 ( .A(n3406), .B(n3250), .Y(n3252) );
NAND2X2TS U5410 ( .A(n4174), .B(n3252), .Y(n3343) );
INVX2TS U5411 ( .A(n3343), .Y(n3254) );
NAND2X4TS U5412 ( .A(n3247), .B(n4220), .Y(n4334) );
NAND2X2TS U5413 ( .A(n3248), .B(n4204), .Y(n4183) );
OAI21X4TS U5414 ( .A0(n4182), .A1(n4334), .B0(n4183), .Y(n4173) );
AO21X4TS U5415 ( .A0(n4173), .A1(n3252), .B0(n3251), .Y(n3253) );
INVX2TS U5416 ( .A(n3310), .Y(n3255) );
AOI21X4TS U5417 ( .A0(n3333), .A1(n3256), .B0(n3255), .Y(n3277) );
OR2X4TS U5418 ( .A(n3257), .B(n3261), .Y(n3264) );
NOR2X2TS U5419 ( .A(n3264), .B(n3258), .Y(n3268) );
INVX2TS U5420 ( .A(n3262), .Y(n3263) );
OAI21X4TS U5421 ( .A0(n3265), .A1(n3264), .B0(n3263), .Y(n3266) );
AOI21X4TS U5422 ( .A0(n3268), .A1(n3267), .B0(n3266), .Y(n3306) );
CMPR32X2TS U5423 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11]), .B(
n3270), .C(n3269), .CO(n3271), .S(n3225) );
INVX2TS U5424 ( .A(n3305), .Y(n3272) );
NAND2X2TS U5425 ( .A(n3272), .B(n3304), .Y(n3273) );
XOR2X4TS U5426 ( .A(n3306), .B(n3273), .Y(n3274) );
INVX2TS U5427 ( .A(n3311), .Y(n3275) );
NAND2X2TS U5428 ( .A(n3274), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(n3309)
);
INVX2TS U5429 ( .A(n4227), .Y(n3344) );
NAND2X1TS U5430 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FSM_add_overflow_flag), .Y(n3280) );
OAI21X1TS U5431 ( .A0(n4423), .A1(n3282), .B0(n4420), .Y(n3286) );
NAND2X1TS U5432 ( .A(n3284), .B(n3283), .Y(n3285) );
INVX2TS U5433 ( .A(FPADDSUB_bit_shift_SHT2), .Y(n4578) );
NOR2X2TS U5434 ( .A(n2311), .B(n4578), .Y(n4480) );
AOI22X1TS U5435 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[6]), .B1(n2342), .Y(n3290) );
INVX2TS U5436 ( .A(n5966), .Y(n3288) );
NOR2X4TS U5437 ( .A(n4274), .B(FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n5944)
);
NAND2X2TS U5438 ( .A(n5951), .B(n5944), .Y(n5974) );
AOI22X1TS U5439 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n2326), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n2329), .Y(n3289) );
OAI211X1TS U5440 ( .A0(n5996), .A1(n2263), .B0(n3290), .C0(n3289), .Y(n5956)
);
NOR2X2TS U5441 ( .A(n6785), .B(n4578), .Y(n5948) );
AOI22X1TS U5442 ( .A0(FPADDSUB_Data_array_SWR[23]), .A1(n5944), .B0(
FPADDSUB_Data_array_SWR[19]), .B1(n2312), .Y(n3291) );
NAND2BX1TS U5443 ( .AN(n5948), .B(n3291), .Y(n5955) );
NAND2X2TS U5444 ( .A(n2263), .B(n6005), .Y(n6007) );
INVX2TS U5445 ( .A(n6007), .Y(n4281) );
AOI22X1TS U5446 ( .A0(n5956), .A1(n2235), .B0(n5955), .B1(n4281), .Y(n5991)
);
NOR2X4TS U5447 ( .A(n2263), .B(n4578), .Y(n5979) );
NAND2X2TS U5448 ( .A(n6005), .B(n5979), .Y(n5999) );
AND4X1TS U5449 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n3292) );
XNOR2X2TS U5450 ( .A(DP_OP_26J223_129_1325_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n3302) );
OAI2BB1X4TS U5451 ( .A0N(n2503), .A1N(n3302), .B0(n6022), .Y(n3294) );
INVX4TS U5452 ( .A(n3294), .Y(n6017) );
INVX2TS U5453 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(n3296) );
INVX2TS U5454 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n3295) );
NOR2X1TS U5455 ( .A(n3298), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n3299) );
NOR2BX1TS U5456 ( .AN(n3299), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(n3300)
);
NOR2BX2TS U5457 ( .AN(n3300), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n3301)
);
AOI21X1TS U5458 ( .A0(n5991), .A1(n5999), .B0(n6660), .Y(n3303) );
OAI21X4TS U5459 ( .A0(n3306), .A1(n3305), .B0(n3304), .Y(n3307) );
XNOR2X4TS U5460 ( .A(n3307), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13]), .Y(
n3312) );
NOR2X8TS U5461 ( .A(n3312), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(n3321)
);
NOR2X4TS U5462 ( .A(n3308), .B(n3311), .Y(n3314) );
OAI21X4TS U5463 ( .A0(n3311), .A1(n3310), .B0(n3309), .Y(n3318) );
AOI21X4TS U5464 ( .A0(n3333), .A1(n3314), .B0(n3318), .Y(n3325) );
NAND2X4TS U5465 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .B(n3312),
.Y(n3322) );
OAI21X4TS U5466 ( .A0(n3321), .A1(n3325), .B0(n3322), .Y(n3313) );
INVX2TS U5467 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(n3315) );
XNOR2X4TS U5468 ( .A(n3313), .B(n3315), .Y(n4203) );
NAND2X4TS U5469 ( .A(n3314), .B(n3317), .Y(n3328) );
AOI21X4TS U5470 ( .A0(n3318), .A1(n3317), .B0(n3316), .Y(n3330) );
OAI21X4TS U5471 ( .A0(n3319), .A1(n3328), .B0(n3330), .Y(n3320) );
XNOR2X4TS U5472 ( .A(n3320), .B(n3329), .Y(n4196) );
NAND2X1TS U5473 ( .A(n3353), .B(n4196), .Y(n3326) );
INVX2TS U5474 ( .A(n3321), .Y(n3323) );
XOR2X4TS U5475 ( .A(n3325), .B(n3324), .Y(n4209) );
NAND2X1TS U5476 ( .A(n4209), .B(n4227), .Y(n3350) );
NAND2X1TS U5477 ( .A(n3327), .B(n3352), .Y(n3334) );
NAND2X2TS U5478 ( .A(n4174), .B(n3336), .Y(n3427) );
AOI21X4TS U5479 ( .A0(n3333), .A1(n3332), .B0(n3331), .Y(n3340) );
INVX2TS U5480 ( .A(n3350), .Y(n3351) );
INVX2TS U5481 ( .A(n3353), .Y(n3420) );
NOR2X2TS U5482 ( .A(DP_OP_502J223_128_4510_n117), .B(
DP_OP_502J223_128_4510_n122), .Y(n5507) );
INVX2TS U5483 ( .A(n4437), .Y(n3380) );
INVX2TS U5484 ( .A(n4431), .Y(n3361) );
INVX2TS U5485 ( .A(n3364), .Y(n5545) );
INVX2TS U5486 ( .A(n3365), .Y(n3367) );
ADDHXLTS U5487 ( .A(n2481), .B(FPMULT_Op_MX[7]), .CO(n3370), .S(n3364) );
INVX2TS U5488 ( .A(n3370), .Y(n5544) );
OAI22X1TS U5489 ( .A0(n2313), .A1(n5545), .B0(n2377), .B1(n5544), .Y(n3379)
);
INVX2TS U5490 ( .A(n3375), .Y(n5535) );
NOR2X1TS U5491 ( .A(n5535), .B(n5540), .Y(n4352) );
INVX2TS U5492 ( .A(n3374), .Y(n5543) );
INVX2TS U5493 ( .A(n3375), .Y(n4572) );
ADDHXLTS U5494 ( .A(FPMULT_Op_MX[2]), .B(n2287), .CO(n3376), .S(n3374) );
INVX2TS U5495 ( .A(n3376), .Y(n5541) );
OAI22X1TS U5496 ( .A0(n5542), .A1(n5543), .B0(n4572), .B1(n5541), .Y(n4351)
);
NOR2X1TS U5497 ( .A(n4572), .B(n5543), .Y(n3387) );
OAI22X1TS U5498 ( .A0(n5542), .A1(n5545), .B0(n5535), .B1(n5544), .Y(n3386)
);
NOR2X1TS U5499 ( .A(DP_OP_502J223_128_4510_n136), .B(n3393), .Y(n5520) );
CMPR32X2TS U5500 ( .A(n3379), .B(n3378), .C(n3377), .CO(n3393), .S(n3392) );
INVX2TS U5501 ( .A(n4434), .Y(n3381) );
CLKXOR2X4TS U5502 ( .A(n3383), .B(n3382), .Y(n5548) );
INVX2TS U5503 ( .A(n3384), .Y(n5549) );
ADDHXLTS U5504 ( .A(n6568), .B(FPMULT_Op_MX[6]), .CO(n3385), .S(n3384) );
INVX2TS U5505 ( .A(n3385), .Y(n5547) );
OAI22X1TS U5506 ( .A0(n5548), .A1(n5549), .B0(n2314), .B1(n5547), .Y(n3391)
);
NOR2X1TS U5507 ( .A(n3392), .B(n3391), .Y(n5525) );
ADDHX1TS U5508 ( .A(n3387), .B(n3386), .CO(n3377), .S(n3389) );
OAI22X1TS U5509 ( .A0(n2313), .A1(n5549), .B0(n2377), .B1(n5547), .Y(n3388)
);
OAI22X1TS U5510 ( .A0(n2377), .A1(n5549), .B0(n4572), .B1(n5547), .Y(n5465)
);
NOR2X1TS U5511 ( .A(n5535), .B(n5545), .Y(n5464) );
NAND2X1TS U5512 ( .A(n5465), .B(n5464), .Y(n5466) );
INVX2TS U5513 ( .A(n5466), .Y(n5532) );
NAND2X1TS U5514 ( .A(n3389), .B(n3388), .Y(n5530) );
INVX2TS U5515 ( .A(n5530), .Y(n3390) );
AOI21X1TS U5516 ( .A0(n5531), .A1(n5532), .B0(n3390), .Y(n5528) );
NAND2X1TS U5517 ( .A(n3392), .B(n3391), .Y(n5526) );
NAND2X1TS U5518 ( .A(DP_OP_502J223_128_4510_n136), .B(n3393), .Y(n5521) );
NAND2X1TS U5519 ( .A(DP_OP_502J223_128_4510_n129), .B(
DP_OP_502J223_128_4510_n135), .Y(n5517) );
INVX2TS U5520 ( .A(n5517), .Y(n3394) );
AOI21X2TS U5521 ( .A0(n5518), .A1(n2472), .B0(n3394), .Y(n5515) );
NAND2X1TS U5522 ( .A(DP_OP_502J223_128_4510_n123), .B(
DP_OP_502J223_128_4510_n128), .Y(n5513) );
OAI21X2TS U5523 ( .A0(n5515), .A1(n5512), .B0(n5513), .Y(n5501) );
NAND2X1TS U5524 ( .A(DP_OP_502J223_128_4510_n110), .B(
DP_OP_502J223_128_4510_n116), .Y(n5503) );
AOI21X4TS U5525 ( .A0(n3396), .A1(n5501), .B0(n3395), .Y(n5500) );
NOR2X2TS U5526 ( .A(DP_OP_502J223_128_4510_n109), .B(
DP_OP_502J223_128_4510_n105), .Y(n5487) );
NAND2X2TS U5527 ( .A(DP_OP_502J223_128_4510_n109), .B(
DP_OP_502J223_128_4510_n105), .Y(n5497) );
OR2X2TS U5528 ( .A(DP_OP_502J223_128_4510_n102), .B(
DP_OP_502J223_128_4510_n104), .Y(n5489) );
NAND2X1TS U5529 ( .A(DP_OP_502J223_128_4510_n102), .B(
DP_OP_502J223_128_4510_n104), .Y(n5148) );
NAND2X1TS U5530 ( .A(n5489), .B(n5148), .Y(n3397) );
BUFX3TS U5531 ( .A(n2577), .Y(n5426) );
AOI22X1TS U5532 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n4321), .B0(
FPADDSUB_DMP_EXP_EWSW[7]), .B1(n6714), .Y(n3399) );
NAND2X2TS U5533 ( .A(n4174), .B(n3402), .Y(n3412) );
NOR2X2TS U5534 ( .A(n4175), .B(n3400), .Y(n3401) );
INVX2TS U5535 ( .A(n4175), .Y(n3407) );
INVX2TS U5536 ( .A(n3412), .Y(n3415) );
INVX2TS U5537 ( .A(n3413), .Y(n3414) );
INVX2TS U5538 ( .A(n3417), .Y(n3419) );
INVX2TS U5539 ( .A(n3422), .Y(n3425) );
INVX2TS U5540 ( .A(n3427), .Y(n3429) );
OAI21X4TS U5541 ( .A0(n3446), .A1(n3435), .B0(n3434), .Y(n3505) );
XNOR2X4TS U5542 ( .A(n3443), .B(n3442), .Y(n3896) );
XNOR2X4TS U5543 ( .A(n3452), .B(n3448), .Y(n3914) );
CLKXOR2X4TS U5544 ( .A(n3455), .B(n3454), .Y(n3921) );
XNOR2X4TS U5545 ( .A(n3464), .B(n3463), .Y(n3465) );
AOI21X4TS U5546 ( .A0(n2245), .A1(n3633), .B0(n3469), .Y(n3470) );
OAI21X4TS U5547 ( .A0(n3488), .A1(n3471), .B0(n3470), .Y(n3534) );
NOR2X8TS U5548 ( .A(n6570), .B(n6579), .Y(n3535) );
AOI21X4TS U5549 ( .A0(n3534), .A1(n3475), .B0(n3474), .Y(n3853) );
XNOR2X4TS U5550 ( .A(n3900), .B(n3479), .Y(n3480) );
AOI21X4TS U5551 ( .A0(n2495), .A1(n3621), .B0(n3498), .Y(n3618) );
AOI21X4TS U5552 ( .A0(n3613), .A1(n2499), .B0(n3500), .Y(n3610) );
OAI21X4TS U5553 ( .A0(n3610), .A1(n3607), .B0(n3608), .Y(n3605) );
AOI21X4TS U5554 ( .A0(n3605), .A1(n3501), .B0(n3502), .Y(n3602) );
OAI21X4TS U5555 ( .A0(n3602), .A1(n3599), .B0(n3600), .Y(n3588) );
OAI21X4TS U5556 ( .A0(n3589), .A1(n3595), .B0(n3590), .Y(n3503) );
AOI21X4TS U5557 ( .A0(n3504), .A1(n3588), .B0(n3503), .Y(n3587) );
XNOR2X4TS U5558 ( .A(n3509), .B(n3508), .Y(n3951) );
CLKXOR2X4TS U5559 ( .A(n3527), .B(n3512), .Y(n3937) );
XNOR2X4TS U5560 ( .A(n3937), .B(FPMULT_Op_MY[11]), .Y(n3521) );
AOI21X4TS U5561 ( .A0(n2222), .A1(n3516), .B0(n3515), .Y(n3517) );
OAI21X4TS U5562 ( .A0(n3626), .A1(n3654), .B0(n3627), .Y(n3523) );
AOI21X4TS U5563 ( .A0(n3524), .A1(n3625), .B0(n3523), .Y(n3640) );
INVX4TS U5564 ( .A(n6769), .Y(n6572) );
INVX4TS U5565 ( .A(n2239), .Y(n6567) );
OAI21X4TS U5566 ( .A0(n3645), .A1(n3535), .B0(n3642), .Y(n3538) );
XNOR2X4TS U5567 ( .A(n3538), .B(n3537), .Y(n3931) );
XNOR2X4TS U5568 ( .A(n3546), .B(n3545), .Y(n3867) );
OAI21X4TS U5569 ( .A0(n3584), .A1(n3578), .B0(n3579), .Y(n3571) );
XNOR2X4TS U5570 ( .A(n3555), .B(n3557), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14) );
NAND2X2TS U5571 ( .A(n3570), .B(n3575), .Y(n3564) );
XNOR2X4TS U5572 ( .A(n3569), .B(n3568), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13) );
INVX2TS U5573 ( .A(n3615), .Y(n3617) );
AFHCINX2TS U5574 ( .CIN(n3859), .B(n3623), .A(n3624), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1), .CO(n3621) );
OAI21X4TS U5575 ( .A0(n3657), .A1(n3653), .B0(n3654), .Y(n3630) );
XNOR2X4TS U5576 ( .A(n3630), .B(n3629), .Y(n3631) );
AOI21X4TS U5577 ( .A0(n3634), .A1(n2454), .B0(n3633), .Y(n3637) );
CLKXOR2X4TS U5578 ( .A(n3645), .B(n3644), .Y(n3863) );
AOI21X4TS U5579 ( .A0(n2196), .A1(n3724), .B0(n3723), .Y(n3816) );
AOI21X4TS U5580 ( .A0(n2494), .A1(n2426), .B0(n3742), .Y(n3802) );
OAI21X4TS U5581 ( .A0(n3802), .A1(n3799), .B0(n3800), .Y(n3788) );
AOI21X4TS U5582 ( .A0(n3744), .A1(n3788), .B0(n3743), .Y(n3787) );
INVX2TS U5583 ( .A(n3765), .Y(n3760) );
INVX2TS U5584 ( .A(n3799), .Y(n3801) );
XNOR2X4TS U5585 ( .A(n3867), .B(n3931), .Y(n3964) );
INVX2TS U5586 ( .A(n3896), .Y(n3915) );
XNOR2X1TS U5587 ( .A(n3900), .B(n2308), .Y(n3889) );
OAI22X1TS U5588 ( .A0(n3936), .A1(n2243), .B0(n2390), .B1(n3893), .Y(n4023)
);
OAI22X1TS U5589 ( .A0(n3901), .A1(n3898), .B0(n3897), .B1(
DP_OP_501J223_127_5235_n723), .Y(n4025) );
OAI22X1TS U5590 ( .A0(n3901), .A1(n3900), .B0(n3898), .B1(
DP_OP_501J223_127_5235_n723), .Y(n4028) );
NAND2X1TS U5591 ( .A(n3902), .B(n3901), .Y(n4027) );
INVX2TS U5592 ( .A(n4029), .Y(n4024) );
AOI21X4TS U5593 ( .A0(n3908), .A1(n4013), .B0(n3907), .Y(n3987) );
INVX2TS U5594 ( .A(n3914), .Y(n3922) );
INVX2TS U5595 ( .A(n3921), .Y(n3938) );
NAND2X2TS U5596 ( .A(n3989), .B(n2476), .Y(n3947) );
OAI21X4TS U5597 ( .A0(n3987), .A1(n3947), .B0(n3946), .Y(n3986) );
AFHCONX2TS U5598 ( .A(n4020), .B(n4019), .CI(n4018), .CON(n4015), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4) );
AFHCINX2TS U5599 ( .CIN(n4021), .B(n4022), .A(n4023), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3), .CO(n4018) );
AFHCONX2TS U5600 ( .A(n4026), .B(n4025), .CI(n4024), .CON(n4021), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2) );
NOR2X4TS U5601 ( .A(n4031), .B(n4030), .Y(n4039) );
INVX2TS U5602 ( .A(n4039), .Y(n4032) );
INVX2TS U5603 ( .A(n4033), .Y(n4034) );
INVX2TS U5604 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .Y(n4042)
);
INVX2TS U5605 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]), .Y(n4041) );
INVX2TS U5606 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .Y(n4050)
);
INVX2TS U5607 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .Y(n4049) );
NOR2X4TS U5608 ( .A(n4046), .B(n4045), .Y(n4151) );
NOR2X2TS U5609 ( .A(n4149), .B(n4151), .Y(n4048) );
NAND2X2TS U5610 ( .A(n4046), .B(n4045), .Y(n4152) );
OAI21X2TS U5611 ( .A0(n4151), .A1(n4148), .B0(n4152), .Y(n4047) );
AOI21X4TS U5612 ( .A0(n4145), .A1(n4048), .B0(n4047), .Y(n4086) );
INVX4TS U5613 ( .A(n4086), .Y(n4067) );
INVX2TS U5614 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .Y(n4055)
);
INVX2TS U5615 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .Y(n4054) );
NOR2X2TS U5616 ( .A(n4052), .B(n4051), .Y(n4063) );
INVX2TS U5617 ( .A(n4063), .Y(n4061) );
NAND2X2TS U5618 ( .A(n4052), .B(n4051), .Y(n4065) );
INVX2TS U5619 ( .A(n4065), .Y(n4053) );
INVX2TS U5620 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .Y(n4069)
);
INVX2TS U5621 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .Y(n4068) );
CMPR32X2TS U5622 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4]), .B(
n4055), .C(n4054), .CO(n4056), .S(n4052) );
INVX2TS U5623 ( .A(n4066), .Y(n4058) );
NAND2X1TS U5624 ( .A(n4058), .B(n4064), .Y(n4059) );
NAND2X1TS U5625 ( .A(n4061), .B(n4065), .Y(n4062) );
NOR2X2TS U5626 ( .A(n4063), .B(n4066), .Y(n4079) );
INVX2TS U5627 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .Y(n4073)
);
INVX2TS U5628 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]), .Y(n4072) );
CMPR32X2TS U5629 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5]), .B(
n4069), .C(n4068), .CO(n4070), .S(n4057) );
NAND2X2TS U5630 ( .A(n4071), .B(n4070), .Y(n4168) );
OAI21X1TS U5631 ( .A0(n4171), .A1(n4167), .B0(n4168), .Y(n4078) );
INVX2TS U5632 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .Y(n4089)
);
INVX2TS U5633 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .Y(n4088) );
NOR2X4TS U5634 ( .A(n4075), .B(n4074), .Y(n4081) );
INVX2TS U5635 ( .A(n4081), .Y(n4076) );
NAND2X2TS U5636 ( .A(n4075), .B(n4074), .Y(n4080) );
NAND2X1TS U5637 ( .A(n4076), .B(n4080), .Y(n4077) );
NAND2X2TS U5638 ( .A(n4079), .B(n4083), .Y(n4087) );
OAI21X1TS U5639 ( .A0(n4081), .A1(n4168), .B0(n4080), .Y(n4082) );
AOI21X2TS U5640 ( .A0(n4084), .A1(n4083), .B0(n4082), .Y(n4085) );
OAI21X4TS U5641 ( .A0(n4087), .A1(n4086), .B0(n4085), .Y(n4122) );
INVX2TS U5642 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .Y(n4091)
);
INVX2TS U5643 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .Y(n4090) );
CMPR32X2TS U5644 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7]), .B(
n4089), .C(n4088), .CO(n4092), .S(n4075) );
NOR2X2TS U5645 ( .A(n4093), .B(n4092), .Y(n4138) );
INVX2TS U5646 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .Y(n4099)
);
INVX2TS U5647 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .Y(n4098) );
CMPR32X2TS U5648 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8]), .B(
n4091), .C(n4090), .CO(n4094), .S(n4093) );
NOR2X4TS U5649 ( .A(n4095), .B(n4094), .Y(n4140) );
NOR2X2TS U5650 ( .A(n4138), .B(n4140), .Y(n4104) );
INVX2TS U5651 ( .A(n4104), .Y(n4097) );
NAND2X2TS U5652 ( .A(n4093), .B(n4092), .Y(n4137) );
OAI21X4TS U5653 ( .A0(n4140), .A1(n4137), .B0(n4141), .Y(n4108) );
INVX2TS U5654 ( .A(n4108), .Y(n4096) );
OAI21X1TS U5655 ( .A0(n4139), .A1(n4097), .B0(n4096), .Y(n4103) );
INVX2TS U5656 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .Y(n4110) );
INVX2TS U5657 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .Y(
n4109) );
OR2X4TS U5658 ( .A(n4101), .B(n4100), .Y(n4107) );
NAND2X2TS U5659 ( .A(n4101), .B(n4100), .Y(n4105) );
NAND2X1TS U5660 ( .A(n4107), .B(n4105), .Y(n4102) );
XNOR2X1TS U5661 ( .A(n4103), .B(n4102), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]) );
NAND2X2TS U5662 ( .A(n4104), .B(n4107), .Y(n4116) );
INVX2TS U5663 ( .A(n4105), .Y(n4106) );
INVX2TS U5664 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .Y(
n4123) );
CMPR32X2TS U5665 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[10]), .B(
n4110), .C(n4109), .CO(n4111), .S(n4101) );
NOR2X2TS U5666 ( .A(n4112), .B(n4111), .Y(n4118) );
INVX2TS U5667 ( .A(n4118), .Y(n4113) );
NAND2X1TS U5668 ( .A(n4112), .B(n4111), .Y(n4117) );
NAND2X1TS U5669 ( .A(n4113), .B(n4117), .Y(n4114) );
NOR2X2TS U5670 ( .A(n4116), .B(n4118), .Y(n4121) );
OAI21X2TS U5671 ( .A0(n4119), .A1(n4118), .B0(n4117), .Y(n4120) );
AOI21X4TS U5672 ( .A0(n4122), .A1(n4121), .B0(n4120), .Y(n4132) );
INVX2TS U5673 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .Y(
n4133) );
XNOR2X1TS U5674 ( .A(n4133), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]), .Y(
n4125) );
CMPR32X2TS U5675 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[11]), .B(
DP_OP_496J223_122_3236_n147), .C(n4123), .CO(n4124), .S(n4112) );
NOR2X2TS U5676 ( .A(n4125), .B(n4124), .Y(n4131) );
INVX2TS U5677 ( .A(n4131), .Y(n4126) );
NAND2X2TS U5678 ( .A(n4125), .B(n4124), .Y(n4130) );
NAND2X1TS U5679 ( .A(n4126), .B(n4130), .Y(n4127) );
XOR2X1TS U5680 ( .A(n4132), .B(n4127), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]) );
INVX2TS U5681 ( .A(n4138), .Y(n4128) );
NAND2X1TS U5682 ( .A(n4128), .B(n4137), .Y(n4129) );
XOR2X1TS U5683 ( .A(n4139), .B(n4129), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]) );
OAI21X4TS U5684 ( .A0(n4132), .A1(n4131), .B0(n4130), .Y(n4159) );
INVX2TS U5685 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .Y(
n4160) );
XNOR2X1TS U5686 ( .A(n4160), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]), .Y(
n4135) );
NAND2X1TS U5687 ( .A(n4158), .B(n4156), .Y(n4136) );
XNOR2X1TS U5688 ( .A(n4159), .B(n4136), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]) );
OAI21X1TS U5689 ( .A0(n4139), .A1(n4138), .B0(n4137), .Y(n4144) );
INVX2TS U5690 ( .A(n4140), .Y(n4142) );
NAND2X1TS U5691 ( .A(n4142), .B(n4141), .Y(n4143) );
INVX2TS U5692 ( .A(n4149), .Y(n4146) );
XOR2X4TS U5693 ( .A(n4150), .B(n4147), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]) );
INVX2TS U5694 ( .A(n4151), .Y(n4153) );
INVX2TS U5695 ( .A(n4156), .Y(n4157) );
AOI21X4TS U5696 ( .A0(n4159), .A1(n4158), .B0(n4157), .Y(n4166) );
NOR2X1TS U5697 ( .A(n4161), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14]), .Y(
n4165) );
INVX2TS U5698 ( .A(n4165), .Y(n4162) );
NAND2X1TS U5699 ( .A(n4161), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14]), .Y(
n4164) );
NAND2X1TS U5700 ( .A(n4162), .B(n4164), .Y(n4163) );
INVX2TS U5701 ( .A(n4167), .Y(n4169) );
NAND2X1TS U5702 ( .A(n4169), .B(n4168), .Y(n4170) );
INVX2TS U5703 ( .A(n4179), .Y(n4335) );
INVX2TS U5704 ( .A(n4334), .Y(n4180) );
INVX2TS U5705 ( .A(n4182), .Y(n4184) );
INVX4TS U5706 ( .A(n4187), .Y(n4457) );
INVX2TS U5707 ( .A(n4188), .Y(n4331) );
INVX2TS U5708 ( .A(n4330), .Y(n4189) );
INVX2TS U5709 ( .A(n4190), .Y(n4192) );
AOI21X4TS U5710 ( .A0(n4213), .A1(n4211), .B0(n4198), .Y(n4202) );
XOR2X4TS U5711 ( .A(n4202), .B(n4201), .Y(n6262) );
INVX4TS U5712 ( .A(n6262), .Y(DP_OP_499J223_125_1651_n279) );
NAND2X2TS U5713 ( .A(n4211), .B(n4210), .Y(n4212) );
XNOR2X4TS U5714 ( .A(n4213), .B(n4212), .Y(n6261) );
INVX2TS U5715 ( .A(n6261), .Y(DP_OP_499J223_125_1651_n280) );
INVX2TS U5716 ( .A(n4215), .Y(n4217) );
NAND2X2TS U5717 ( .A(n4217), .B(n4216), .Y(n4218) );
XOR2X4TS U5718 ( .A(n4219), .B(n4218), .Y(n6277) );
INVX4TS U5719 ( .A(n4226), .Y(DP_OP_499J223_125_1651_n273) );
INVX4TS U5720 ( .A(n4230), .Y(DP_OP_499J223_125_1651_n269) );
INVX2TS U5721 ( .A(n4234), .Y(DP_OP_499J223_125_1651_n304) );
NOR4X1TS U5722 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n4242) );
NOR4X1TS U5723 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n4241) );
NOR4X1TS U5724 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n4240) );
NOR4X1TS U5725 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n4243),
.Y(n6919) );
INVX2TS U5726 ( .A(n4244), .Y(n5538) );
NOR2X1TS U5727 ( .A(n4572), .B(n5538), .Y(n4247) );
ADDHXLTS U5728 ( .A(n6569), .B(DP_OP_501J223_127_5235_n944), .CO(n4245), .S(
n3373) );
INVX2TS U5729 ( .A(n4245), .Y(n5539) );
OAI22X1TS U5730 ( .A0(n2377), .A1(n5540), .B0(n5535), .B1(n5539), .Y(n4246)
);
ADDHX1TS U5731 ( .A(n4247), .B(n4246), .CO(DP_OP_502J223_128_4510_n137), .S(
DP_OP_502J223_128_4510_n138) );
NAND2X2TS U5732 ( .A(n6567), .B(n2383), .Y(n4975) );
NAND2X1TS U5733 ( .A(n2292), .B(n6585), .Y(n4963) );
OA21X1TS U5734 ( .A0(n4248), .A1(n4975), .B0(n4963), .Y(n4468) );
NOR2X1TS U5735 ( .A(n6567), .B(n2383), .Y(n4464) );
OAI21X1TS U5736 ( .A0(n4468), .A1(n4464), .B0(n4975), .Y(n4249) );
OR2X2TS U5737 ( .A(intadd_515_n1), .B(n4249), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11) );
OAI2BB1X2TS U5738 ( .A0N(intadd_515_n1), .A1N(n4249), .B0(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10) );
INVX2TS U5739 ( .A(n2491), .Y(n5640) );
OAI22X1TS U5740 ( .A0(n2314), .A1(n5540), .B0(n2377), .B1(n5539), .Y(n4254)
);
NOR2X1TS U5741 ( .A(n5535), .B(n5536), .Y(n4340) );
INVX2TS U5742 ( .A(n4251), .Y(n5537) );
OAI22X1TS U5743 ( .A0(n5542), .A1(n5538), .B0(n4572), .B1(n5537), .Y(n4339)
);
OAI22X1TS U5744 ( .A0(n5548), .A1(n5543), .B0(n2314), .B1(n5541), .Y(n4252)
);
NOR2X1TS U5745 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n4503) );
NAND2X1TS U5746 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n4511) );
NAND2X1TS U5747 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n4504) );
OAI21X1TS U5748 ( .A0(n4503), .A1(n4511), .B0(n4504), .Y(n4523) );
NOR2X2TS U5749 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n4529) );
NAND2X1TS U5750 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n4533) );
NAND2X1TS U5751 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n4530) );
AOI21X1TS U5752 ( .A0(n4523), .A1(n4256), .B0(n4255), .Y(n6186) );
NOR2X1TS U5753 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n6214) );
NOR2X2TS U5754 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n6209) );
NOR2X1TS U5755 ( .A(n6214), .B(n6209), .Y(n6188) );
NOR2X1TS U5756 ( .A(n6199), .B(n6181), .Y(n4258) );
NAND2X1TS U5757 ( .A(n6188), .B(n4258), .Y(n4260) );
NAND2X1TS U5758 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n6226) );
NAND2X1TS U5759 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n6210) );
OAI21X1TS U5760 ( .A0(n6209), .A1(n6226), .B0(n6210), .Y(n6187) );
NAND2X1TS U5761 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n6200) );
NAND2X1TS U5762 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n6182) );
AOI21X1TS U5763 ( .A0(n6187), .A1(n4258), .B0(n4257), .Y(n4259) );
NOR2X1TS U5764 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n6035) );
INVX2TS U5765 ( .A(n6035), .Y(n6054) );
NAND2X1TS U5766 ( .A(n6054), .B(n6031), .Y(n6107) );
NOR2X2TS U5767 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]),
.Y(n6101) );
NOR2X1TS U5768 ( .A(n6107), .B(n6101), .Y(n4264) );
NAND2X1TS U5769 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n6053) );
INVX2TS U5770 ( .A(n6053), .Y(n4262) );
NAND2X1TS U5771 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n6030) );
INVX2TS U5772 ( .A(n6030), .Y(n4261) );
AOI21X1TS U5773 ( .A0(n6031), .A1(n4262), .B0(n4261), .Y(n6106) );
NAND2X1TS U5774 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n6102) );
OAI21X1TS U5775 ( .A0(n6106), .A1(n6101), .B0(n6102), .Y(n4263) );
AOI21X2TS U5776 ( .A0(n6034), .A1(n4264), .B0(n4263), .Y(n6047) );
NOR2X1TS U5777 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]),
.Y(n6041) );
INVX2TS U5778 ( .A(n6070), .Y(n4265) );
NOR2X1TS U5779 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]),
.Y(n6089) );
NAND2X1TS U5780 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n6090) );
NAND2X1TS U5781 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n6061) );
INVX2TS U5782 ( .A(n6061), .Y(n4266) );
AOI21X4TS U5783 ( .A0(n6066), .A1(n6062), .B0(n4266), .Y(n6085) );
NOR2X1TS U5784 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]),
.Y(n6079) );
NAND2X1TS U5785 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n6080) );
NAND2X1TS U5786 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n6172) );
INVX2TS U5787 ( .A(n6172), .Y(n4267) );
AOI21X4TS U5788 ( .A0(n6177), .A1(n6173), .B0(n4267), .Y(n6120) );
NOR2X1TS U5789 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]),
.Y(n6114) );
NAND2X1TS U5790 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n6115) );
NAND2X1TS U5791 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n6135) );
INVX2TS U5792 ( .A(n6135), .Y(n4268) );
AOI21X4TS U5793 ( .A0(n6140), .A1(n6136), .B0(n4268), .Y(n6130) );
NOR2X1TS U5794 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]),
.Y(n6124) );
NAND2X1TS U5795 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n6125) );
NAND2X1TS U5796 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n6152) );
INVX2TS U5797 ( .A(n6152), .Y(n4269) );
NOR2X1TS U5798 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]),
.Y(n6162) );
NAND2X1TS U5799 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n6163) );
NAND2X1TS U5800 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n4412) );
INVX2TS U5801 ( .A(n4412), .Y(n4270) );
BUFX3TS U5802 ( .A(n2316), .Y(n6232) );
BUFX3TS U5803 ( .A(n2316), .Y(n6711) );
AOI22X1TS U5804 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[17]), .B1(n2326), .Y(n4273) );
AOI22X1TS U5805 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n2329), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n2342), .Y(n4272) );
OAI211X1TS U5806 ( .A0(n4470), .A1(n2263), .B0(n4273), .C0(n4272), .Y(n5961)
);
NAND2X1TS U5807 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n4274), .Y(n4280)
);
AOI22X1TS U5808 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n5944), .B0(
FPADDSUB_Data_array_SWR[16]), .B1(n2312), .Y(n4275) );
NAND2X1TS U5809 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(n5948), .Y(n5967)
);
AOI22X1TS U5810 ( .A0(n5961), .A1(n5984), .B0(n5959), .B1(n4281), .Y(n5987)
);
AOI21X1TS U5811 ( .A0(n5987), .A1(n5999), .B0(n6728), .Y(n4276) );
AOI22X1TS U5812 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n3288), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n2343), .Y(n4278) );
AOI22X1TS U5813 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[12]), .B1(n2329), .Y(n4277) );
OAI211X1TS U5814 ( .A0(n6008), .A1(n2263), .B0(n4278), .C0(n4277), .Y(n5958)
);
AOI22X1TS U5815 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n5944), .B0(
FPADDSUB_Data_array_SWR[17]), .B1(n2311), .Y(n4279) );
AOI22X1TS U5816 ( .A0(n5958), .A1(n5984), .B0(n5957), .B1(n4281), .Y(n5988)
);
AOI21X1TS U5817 ( .A0(n5988), .A1(n5999), .B0(n6728), .Y(n4282) );
NOR2X4TS U5818 ( .A(n5647), .B(n6593), .Y(n4297) );
NAND2X2TS U5819 ( .A(n6749), .B(n5650), .Y(n4345) );
OAI21X4TS U5820 ( .A0(n4342), .A1(n4345), .B0(n4343), .Y(n4290) );
NAND2X2TS U5821 ( .A(n6595), .B(n6593), .Y(n4298) );
OAI21X1TS U5822 ( .A0(n4291), .A1(n4298), .B0(n4292), .Y(n4284) );
NOR2X2TS U5823 ( .A(n6586), .B(n2290), .Y(n4306) );
INVX2TS U5824 ( .A(n4306), .Y(n4286) );
NAND2X1TS U5825 ( .A(n4286), .B(n4305), .Y(n4287) );
INVX2TS U5826 ( .A(n4289), .Y(n5610) );
INVX2TS U5827 ( .A(n4290), .Y(n4301) );
INVX2TS U5828 ( .A(n4291), .Y(n4293) );
CLKXOR2X4TS U5829 ( .A(n4295), .B(n4294), .Y(n5621) );
ADDHXLTS U5830 ( .A(n6579), .B(n6567), .CO(n4296), .S(n4289) );
INVX2TS U5831 ( .A(n4296), .Y(n5609) );
OAI22X1TS U5832 ( .A0(n2318), .A1(n5610), .B0(n5621), .B1(n5609), .Y(n4313)
);
INVX2TS U5833 ( .A(n4297), .Y(n4299) );
XOR2X1TS U5834 ( .A(n4301), .B(n4300), .Y(n4302) );
OAI22X1TS U5835 ( .A0(n5621), .A1(n2344), .B0(n2310), .B1(n2405), .Y(n4364)
);
INVX2TS U5836 ( .A(n4304), .Y(n5616) );
NOR2X2TS U5837 ( .A(n2305), .B(n5616), .Y(n4363) );
OAI21X1TS U5838 ( .A0(n4307), .A1(n4306), .B0(n4305), .Y(n4308) );
CLKXOR2X4TS U5839 ( .A(n4308), .B(n5648), .Y(n5619) );
INVX2TS U5840 ( .A(n4309), .Y(n5612) );
ADDHXLTS U5841 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[21]), .CO(n4310), .S(
n4309) );
INVX2TS U5842 ( .A(n4310), .Y(n5611) );
OAI22X1TS U5843 ( .A0(n5619), .A1(n5612), .B0(n2319), .B1(n5611), .Y(n4311)
);
INVX2TS U5844 ( .A(n4314), .Y(n5903) );
AOI21X1TS U5845 ( .A0(n5903), .A1(n2485), .B0(n4315), .Y(n4319) );
NAND2X1TS U5846 ( .A(n4317), .B(n4316), .Y(n4318) );
XOR2X1TS U5847 ( .A(n4319), .B(n4318), .Y(n4320) );
INVX2TS U5848 ( .A(n2323), .Y(n4321) );
INVX2TS U5849 ( .A(n5478), .Y(n6958) );
OAI21X1TS U5850 ( .A0(n4423), .A1(n4323), .B0(n4322), .Y(n4328) );
INVX2TS U5851 ( .A(n4324), .Y(n4326) );
NAND2X1TS U5852 ( .A(n4326), .B(n4325), .Y(n4327) );
NAND2X1TS U5853 ( .A(n4331), .B(n4330), .Y(n4332) );
NAND2X1TS U5854 ( .A(n4335), .B(n4334), .Y(n4336) );
INVX2TS U5855 ( .A(n4348), .Y(n5180) );
NOR2X1TS U5856 ( .A(n5180), .B(n5610), .Y(n4350) );
INVX2TS U5857 ( .A(n4342), .Y(n4344) );
INVX2TS U5858 ( .A(n4348), .Y(n5608) );
OAI22X1TS U5859 ( .A0(n5614), .A1(n5612), .B0(n5608), .B1(n5611), .Y(n4349)
);
ADDHX1TS U5860 ( .A(n4352), .B(n4351), .CO(DP_OP_502J223_128_4510_n141), .S(
n3378) );
OAI22X1TS U5861 ( .A0(n5614), .A1(n5610), .B0(n5180), .B1(n5609), .Y(n4353)
);
OAI22X1TS U5862 ( .A0(n5617), .A1(n5612), .B0(n2376), .B1(n5611), .Y(n4359)
);
ADDHXLTS U5863 ( .A(n4354), .B(n4353), .CO(DP_OP_500J223_126_4510_n132), .S(
n4358) );
INVX2TS U5864 ( .A(n4355), .Y(n5615) );
ADDHXLTS U5865 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[20]), .CO(n4356), .S(
n4355) );
INVX2TS U5866 ( .A(n4356), .Y(n5613) );
OAI22X1TS U5867 ( .A0(n5621), .A1(n5615), .B0(n5617), .B1(n5613), .Y(n4357)
);
NOR2X2TS U5868 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(
FPADDSUB_left_right_SHT2), .Y(n5960) );
INVX2TS U5869 ( .A(n5960), .Y(n5954) );
AOI211X1TS U5870 ( .A0(FPADDSUB_Data_array_SWR[4]), .A1(n2330), .B0(n4361),
.C0(n4360), .Y(n4469) );
OAI22X1TS U5871 ( .A0(n4470), .A1(n5954), .B0(n4469), .B1(n2356), .Y(n4362)
);
NOR2X4TS U5872 ( .A(n6013), .B(n6022), .Y(n5937) );
BUFX3TS U5873 ( .A(n5937), .Y(n6009) );
OA22X1TS U5874 ( .A0(n4362), .A1(n5963), .B0(n6009), .B1(
FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n1180) );
NOR3X2TS U5875 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n4992) );
NOR4BX1TS U5876 ( .AN(n4992), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .Y(n4483) );
AND3X2TS U5877 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n2364),
.C(n6797), .Y(n6439) );
NOR2X1TS U5878 ( .A(n2305), .B(n5613), .Y(n4367) );
OAI22X1TS U5879 ( .A0(n2318), .A1(n2344), .B0(n5621), .B1(n2405), .Y(n4366)
);
ADDHX1TS U5880 ( .A(n4364), .B(n4363), .CO(n4365), .S(n4312) );
CMPR32X2TS U5881 ( .A(n4367), .B(n4366), .C(n4365), .CO(
DP_OP_500J223_126_4510_n106), .S(DP_OP_500J223_126_4510_n107) );
BUFX3TS U5882 ( .A(n6024), .Y(n6237) );
NAND2X1TS U5883 ( .A(n6755), .B(n6798), .Y(n4513) );
NAND2X1TS U5884 ( .A(n6861), .B(FPADDSUB_DMP_SFG[0]), .Y(n4368) );
OAI21X1TS U5885 ( .A0(n4513), .A1(n4369), .B0(n4368), .Y(n4502) );
NOR2X1TS U5886 ( .A(n6778), .B(FPADDSUB_DMP_SFG[1]), .Y(n4518) );
NOR2X1TS U5887 ( .A(n6773), .B(FPADDSUB_DMP_SFG[2]), .Y(n4371) );
NAND2X1TS U5888 ( .A(n6778), .B(FPADDSUB_DMP_SFG[1]), .Y(n4517) );
NAND2X1TS U5889 ( .A(n6773), .B(FPADDSUB_DMP_SFG[2]), .Y(n4370) );
AOI21X1TS U5890 ( .A0(n4502), .A1(n4373), .B0(n4372), .Y(n4528) );
NOR2X1TS U5891 ( .A(n6777), .B(FPADDSUB_DMP_SFG[3]), .Y(n6221) );
NOR2X1TS U5892 ( .A(n6775), .B(FPADDSUB_DMP_SFG[4]), .Y(n4375) );
NOR2X1TS U5893 ( .A(n6221), .B(n4375), .Y(n6196) );
NOR2X1TS U5894 ( .A(n6776), .B(FPADDSUB_DMP_SFG[5]), .Y(n6198) );
NOR2X1TS U5895 ( .A(n6774), .B(FPADDSUB_DMP_SFG[6]), .Y(n4377) );
NOR2X1TS U5896 ( .A(n6198), .B(n4377), .Y(n4379) );
NAND2X1TS U5897 ( .A(n6196), .B(n4379), .Y(n4381) );
NAND2X1TS U5898 ( .A(n6777), .B(FPADDSUB_DMP_SFG[3]), .Y(n6222) );
NAND2X1TS U5899 ( .A(n6775), .B(FPADDSUB_DMP_SFG[4]), .Y(n4374) );
OAI21X1TS U5900 ( .A0(n4375), .A1(n6222), .B0(n4374), .Y(n6195) );
NAND2X1TS U5901 ( .A(n6776), .B(FPADDSUB_DMP_SFG[5]), .Y(n6197) );
NAND2X1TS U5902 ( .A(n6774), .B(FPADDSUB_DMP_SFG[6]), .Y(n4376) );
AOI21X1TS U5903 ( .A0(n6195), .A1(n4379), .B0(n4378), .Y(n4380) );
OAI21X1TS U5904 ( .A0(n4528), .A1(n4381), .B0(n4380), .Y(n6025) );
NOR2X1TS U5905 ( .A(n6779), .B(FPADDSUB_DMP_SFG[7]), .Y(n6052) );
NOR2X1TS U5906 ( .A(n6856), .B(FPADDSUB_DMP_SFG[8]), .Y(n4383) );
NOR2X1TS U5907 ( .A(n6052), .B(n4383), .Y(n6026) );
NAND2X1TS U5908 ( .A(n6026), .B(n4385), .Y(n6100) );
NOR2X1TS U5909 ( .A(n6860), .B(FPADDSUB_DMP_SFG[10]), .Y(n4387) );
NOR2X1TS U5910 ( .A(n6100), .B(n4387), .Y(n4389) );
NAND2X1TS U5911 ( .A(n6779), .B(FPADDSUB_DMP_SFG[7]), .Y(n6051) );
NAND2X1TS U5912 ( .A(n6856), .B(FPADDSUB_DMP_SFG[8]), .Y(n4382) );
OAI21X1TS U5913 ( .A0(n4383), .A1(n6051), .B0(n4382), .Y(n6027) );
AOI21X1TS U5914 ( .A0(n6027), .A1(n4385), .B0(n4384), .Y(n6099) );
NAND2X1TS U5915 ( .A(n6860), .B(FPADDSUB_DMP_SFG[10]), .Y(n4386) );
OAI21X1TS U5916 ( .A0(n6099), .A1(n4387), .B0(n4386), .Y(n4388) );
AOI21X2TS U5917 ( .A0(n6025), .A1(n4389), .B0(n4388), .Y(n6045) );
NOR2X1TS U5918 ( .A(n6859), .B(FPADDSUB_DMP_SFG[11]), .Y(n4391) );
NAND2X1TS U5919 ( .A(n6859), .B(FPADDSUB_DMP_SFG[11]), .Y(n4390) );
OAI21X4TS U5920 ( .A0(n6045), .A1(n4391), .B0(n4390), .Y(n6073) );
AOI21X4TS U5921 ( .A0(n6073), .A1(n4393), .B0(n4392), .Y(n6093) );
NOR2X1TS U5922 ( .A(n6858), .B(FPADDSUB_DMP_SFG[13]), .Y(n4395) );
NAND2X1TS U5923 ( .A(n6858), .B(FPADDSUB_DMP_SFG[13]), .Y(n4394) );
OAI21X4TS U5924 ( .A0(n6093), .A1(n4395), .B0(n4394), .Y(n6064) );
AOI21X4TS U5925 ( .A0(n6064), .A1(n4397), .B0(n4396), .Y(n6083) );
NOR2X1TS U5926 ( .A(n6807), .B(FPADDSUB_DMP_SFG[15]), .Y(n4399) );
NAND2X1TS U5927 ( .A(n6807), .B(FPADDSUB_DMP_SFG[15]), .Y(n4398) );
OAI21X4TS U5928 ( .A0(n6083), .A1(n4399), .B0(n4398), .Y(n6175) );
AOI21X4TS U5929 ( .A0(n6175), .A1(n4401), .B0(n4400), .Y(n6118) );
NOR2X1TS U5930 ( .A(n6817), .B(FPADDSUB_DMP_SFG[17]), .Y(n4403) );
NAND2X1TS U5931 ( .A(n6817), .B(FPADDSUB_DMP_SFG[17]), .Y(n4402) );
AOI21X4TS U5932 ( .A0(n6138), .A1(n4405), .B0(n4404), .Y(n6128) );
NOR2X1TS U5933 ( .A(n6823), .B(FPADDSUB_DMP_SFG[19]), .Y(n4407) );
NAND2X1TS U5934 ( .A(n6823), .B(FPADDSUB_DMP_SFG[19]), .Y(n4406) );
OAI21X4TS U5935 ( .A0(n6128), .A1(n4407), .B0(n4406), .Y(n6155) );
NAND2X1TS U5936 ( .A(n6843), .B(FPADDSUB_DMP_SFG[21]), .Y(n4410) );
NAND2X1TS U5937 ( .A(n4413), .B(n4412), .Y(n4415) );
INVX2TS U5938 ( .A(n4415), .Y(n4414) );
XNOR2X1TS U5939 ( .A(n6146), .B(n4414), .Y(n4419) );
XNOR2X1TS U5940 ( .A(n4416), .B(n4415), .Y(n4417) );
BUFX3TS U5941 ( .A(n4499), .Y(n6158) );
BUFX3TS U5942 ( .A(n2316), .Y(n6191) );
AOI22X1TS U5943 ( .A0(n4417), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[24]),
.B1(n6191), .Y(n4418) );
OAI2BB1X1TS U5944 ( .A0N(n6237), .A1N(n4419), .B0(n4418), .Y(n1315) );
NAND2X1TS U5945 ( .A(n4421), .B(n4420), .Y(n4422) );
XOR2X1TS U5946 ( .A(n4423), .B(n4422), .Y(n4424) );
NAND2X2TS U5947 ( .A(FPSENCOS_cont_iter_out[3]), .B(n6372), .Y(n6369) );
NAND2X2TS U5948 ( .A(n6450), .B(n6369), .Y(n6367) );
INVX2TS U5949 ( .A(n6367), .Y(n6375) );
NAND2X2TS U5950 ( .A(n6450), .B(intadd_517_B_1_), .Y(n6362) );
NOR2X2TS U5951 ( .A(n6782), .B(n6362), .Y(n5013) );
NAND2X1TS U5952 ( .A(FPSENCOS_cont_iter_out[1]), .B(n6375), .Y(n4980) );
AOI22X1TS U5953 ( .A0(n2201), .A1(n2346), .B0(n5642), .B1(n6572), .Y(n4430)
);
NAND2X1TS U5954 ( .A(FPMULT_Op_MY[11]), .B(DP_OP_501J223_127_5235_n944), .Y(
n4925) );
NAND2X1TS U5955 ( .A(n2346), .B(n5643), .Y(n4926) );
NAND2X1TS U5956 ( .A(n6588), .B(n6572), .Y(n4924) );
OAI21X1TS U5957 ( .A0(n4925), .A1(n4926), .B0(n4426), .Y(n4429) );
NAND2X1TS U5958 ( .A(n4428), .B(n4427), .Y(intadd_513_B_7_) );
OAI2BB2XLTS U5959 ( .B0(intadd_513_B_7_), .B1(n4430), .A0N(n4429), .A1N(
n4428), .Y(intadd_513_B_6_) );
INVX2TS U5960 ( .A(n2488), .Y(n5646) );
NOR2X2TS U5961 ( .A(n6588), .B(n5646), .Y(n4562) );
NOR2X2TS U5962 ( .A(n5642), .B(n2289), .Y(n4564) );
OR2X2TS U5963 ( .A(n4562), .B(n4564), .Y(n4439) );
NAND2X1TS U5964 ( .A(n5642), .B(n2289), .Y(n4565) );
NOR2X1TS U5965 ( .A(n2303), .B(n5541), .Y(n4445) );
INVX2TS U5966 ( .A(n4562), .Y(n4440) );
NAND2X1TS U5967 ( .A(n4440), .B(n4561), .Y(n4441) );
INVX2TS U5968 ( .A(n4442), .Y(n5534) );
OAI22X1TS U5969 ( .A0(n2320), .A1(n5536), .B0(n5548), .B1(n5534), .Y(n4444)
);
OAI22X1TS U5970 ( .A0(n5548), .A1(n5536), .B0(n2314), .B1(n5534), .Y(n4560)
);
CMPR32X2TS U5971 ( .A(n4445), .B(n4444), .C(n4443), .CO(
DP_OP_502J223_128_4510_n106), .S(DP_OP_502J223_128_4510_n107) );
INVX2TS U5972 ( .A(n4454), .Y(n4446) );
NAND2X1TS U5973 ( .A(n4446), .B(n4453), .Y(n4447) );
INVX2TS U5974 ( .A(n4450), .Y(n4451) );
NOR2X1TS U5975 ( .A(n4451), .B(n4454), .Y(n4458) );
AO21X4TS U5976 ( .A0(n4458), .A1(n4457), .B0(n4456), .Y(n4462) );
INVX2TS U5977 ( .A(n4459), .Y(n4461) );
XOR2X4TS U5978 ( .A(n4462), .B(n2427), .Y(n4463) );
XOR2X1TS U5979 ( .A(n6567), .B(n2383), .Y(n4467) );
INVX2TS U5980 ( .A(n4464), .Y(n4465) );
AOI21X1TS U5981 ( .A0(n4975), .A1(n4465), .B0(n4468), .Y(n4466) );
OAI2BB2XLTS U5982 ( .B0(n6022), .B1(n2451), .A0N(
FPADDSUB_exp_rslt_NRM2_EW1[7]), .A1N(n6017), .Y(n1466) );
NAND2X2TS U5983 ( .A(n5999), .B(n6624), .Y(n5998) );
INVX2TS U5984 ( .A(n5998), .Y(n6006) );
OA22X1TS U5985 ( .A0(n4472), .A1(n4471), .B0(n6009), .B1(
FPADDSUB_DmP_mant_SFG_SWR[0]), .Y(n1205) );
INVX2TS U5986 ( .A(n5454), .Y(n4473) );
BUFX3TS U5987 ( .A(n6444), .Y(n6459) );
OR2X1TS U5988 ( .A(FPSENCOS_d_ff3_LUT_out[27]), .B(n6459), .Y(n2113) );
NOR2X1TS U5989 ( .A(n2221), .B(n7062), .Y(n7064) );
NAND2X1TS U5990 ( .A(FPMULT_Op_MX[5]), .B(n2289), .Y(intadd_514_A_7_) );
NOR2X1TS U5991 ( .A(n2261), .B(n2484), .Y(n7066) );
NAND2X1TS U5992 ( .A(n5648), .B(n2344), .Y(intadd_512_A_7_) );
INVX2TS U5993 ( .A(n5671), .Y(n4474) );
INVX2TS U5994 ( .A(n6585), .Y(n4968) );
NOR2X1TS U5995 ( .A(n2491), .B(n4968), .Y(n5672) );
NAND2X2TS U5996 ( .A(FPMULT_Op_MX[19]), .B(n6753), .Y(n5445) );
NAND2X1TS U5997 ( .A(n5640), .B(n5647), .Y(n4938) );
NOR2X1TS U5998 ( .A(n5445), .B(n4938), .Y(n4937) );
NAND2X1TS U5999 ( .A(n2292), .B(n6753), .Y(n4476) );
NAND2X1TS U6000 ( .A(n6567), .B(n2291), .Y(n4475) );
NOR2X2TS U6001 ( .A(n4476), .B(n4475), .Y(n4956) );
NOR3X2TS U6002 ( .A(n4476), .B(n2217), .C(n2478), .Y(n5651) );
NAND2X1TS U6003 ( .A(FPMULT_Op_MX[18]), .B(n2223), .Y(n4948) );
NAND2X1TS U6004 ( .A(n6585), .B(FPMULT_Op_MX[19]), .Y(n4947) );
XNOR2X1TS U6005 ( .A(n4948), .B(n4947), .Y(n4477) );
NAND2X2TS U6006 ( .A(n6595), .B(FPMULT_Op_MX[20]), .Y(n4973) );
INVX2TS U6007 ( .A(n4973), .Y(n4971) );
XOR2X1TS U6008 ( .A(n4477), .B(n4971), .Y(n5653) );
OAI2BB2XLTS U6009 ( .B0(n4478), .B1(n5653), .A0N(n5651), .A1N(n5652), .Y(
mult_x_309_n36) );
OA22X1TS U6010 ( .A0(n6626), .A1(FPADDSUB_exp_rslt_NRM2_EW1[1]), .B0(n6730),
.B1(result_add_subt[24]), .Y(n1472) );
OA22X1TS U6011 ( .A0(n6626), .A1(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B0(n6730),
.B1(result_add_subt[23]), .Y(n1473) );
OAI22X1TS U6012 ( .A0(n6001), .A1(n2263), .B0(n2418), .B1(n5966), .Y(n4481)
);
AOI211X1TS U6013 ( .A0(FPADDSUB_Data_array_SWR[7]), .A1(n2343), .B0(n4482),
.C0(n4481), .Y(n5990) );
OAI22X1TS U6014 ( .A0(n5989), .A1(n5954), .B0(n5990), .B1(n5984), .Y(n6653)
);
BUFX3TS U6015 ( .A(n5937), .Y(n5962) );
OA22X1TS U6016 ( .A0(n6653), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n1187) );
NOR3BX1TS U6017 ( .AN(n2364), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]),
.C(n6797), .Y(n4484) );
BUFX3TS U6018 ( .A(n4486), .Y(n6986) );
BUFX3TS U6019 ( .A(n7014), .Y(n6999) );
BUFX3TS U6020 ( .A(n4490), .Y(n6974) );
BUFX3TS U6021 ( .A(n4486), .Y(n6985) );
BUFX3TS U6022 ( .A(n4486), .Y(n6983) );
BUFX3TS U6023 ( .A(n4492), .Y(n6996) );
BUFX3TS U6024 ( .A(n4486), .Y(n6982) );
BUFX3TS U6025 ( .A(n7014), .Y(n7001) );
BUFX3TS U6026 ( .A(n4492), .Y(n6995) );
BUFX3TS U6027 ( .A(n4487), .Y(n6981) );
BUFX3TS U6028 ( .A(n4498), .Y(n7000) );
BUFX3TS U6029 ( .A(n4492), .Y(n6994) );
BUFX3TS U6030 ( .A(n4497), .Y(n6993) );
BUFX3TS U6031 ( .A(n4486), .Y(n6966) );
BUFX3TS U6032 ( .A(n4491), .Y(n7013) );
BUFX3TS U6033 ( .A(n4486), .Y(n6984) );
BUFX3TS U6034 ( .A(n4491), .Y(n7014) );
CLKBUFX2TS U6035 ( .A(n4489), .Y(n4488) );
BUFX3TS U6036 ( .A(n4494), .Y(n7048) );
BUFX3TS U6037 ( .A(n4494), .Y(n7051) );
BUFX3TS U6038 ( .A(n4494), .Y(n7052) );
BUFX3TS U6039 ( .A(n4488), .Y(n7056) );
BUFX3TS U6040 ( .A(n4486), .Y(n6987) );
BUFX3TS U6041 ( .A(n4491), .Y(n7019) );
BUFX3TS U6042 ( .A(n4490), .Y(n6972) );
BUFX3TS U6043 ( .A(n4492), .Y(n6971) );
BUFX3TS U6044 ( .A(n4492), .Y(n6998) );
BUFX3TS U6045 ( .A(n4490), .Y(n6970) );
CLKBUFX2TS U6046 ( .A(n4491), .Y(n7042) );
BUFX3TS U6047 ( .A(n7028), .Y(n7018) );
BUFX3TS U6048 ( .A(n4486), .Y(n6973) );
BUFX3TS U6049 ( .A(n4497), .Y(n6969) );
BUFX3TS U6050 ( .A(n4496), .Y(n7017) );
BUFX3TS U6051 ( .A(n4488), .Y(n7044) );
CLKBUFX2TS U6052 ( .A(n4491), .Y(n4495) );
BUFX3TS U6053 ( .A(n4498), .Y(n7016) );
BUFX3TS U6054 ( .A(n4488), .Y(n7045) );
BUFX3TS U6055 ( .A(n4498), .Y(n7015) );
BUFX3TS U6056 ( .A(n4488), .Y(n7057) );
BUFX3TS U6057 ( .A(n4498), .Y(n7002) );
BUFX3TS U6058 ( .A(n4492), .Y(n6968) );
BUFX3TS U6059 ( .A(n4487), .Y(n6967) );
BUFX3TS U6060 ( .A(n4494), .Y(n7046) );
BUFX3TS U6061 ( .A(n4488), .Y(n7047) );
BUFX3TS U6062 ( .A(n4497), .Y(n6989) );
BUFX3TS U6063 ( .A(n4489), .Y(n7049) );
BUFX3TS U6064 ( .A(n7050), .Y(n7043) );
BUFX3TS U6065 ( .A(n4487), .Y(n6976) );
BUFX3TS U6066 ( .A(n4487), .Y(n6977) );
BUFX3TS U6067 ( .A(n4487), .Y(n6979) );
BUFX3TS U6068 ( .A(n4487), .Y(n6980) );
BUFX3TS U6069 ( .A(n4487), .Y(n6975) );
BUFX3TS U6070 ( .A(n4487), .Y(n6978) );
BUFX3TS U6071 ( .A(n4496), .Y(n7033) );
BUFX3TS U6072 ( .A(n4496), .Y(n7032) );
BUFX3TS U6073 ( .A(n4489), .Y(n7055) );
BUFX3TS U6074 ( .A(n7019), .Y(n7031) );
BUFX3TS U6075 ( .A(n4488), .Y(n7054) );
BUFX3TS U6076 ( .A(n4489), .Y(n7053) );
BUFX3TS U6077 ( .A(n4494), .Y(n7050) );
CLKBUFX3TS U6078 ( .A(n4491), .Y(n7011) );
CLKBUFX2TS U6079 ( .A(n4491), .Y(n4493) );
BUFX3TS U6080 ( .A(n4490), .Y(n6961) );
BUFX3TS U6081 ( .A(n7011), .Y(n7025) );
BUFX3TS U6082 ( .A(n4492), .Y(n6997) );
BUFX3TS U6083 ( .A(n4497), .Y(n6990) );
BUFX3TS U6084 ( .A(n4498), .Y(n7024) );
BUFX3TS U6085 ( .A(n4496), .Y(n7023) );
BUFX3TS U6086 ( .A(n4496), .Y(n7022) );
CLKBUFX2TS U6087 ( .A(n7041), .Y(n7027) );
BUFX3TS U6088 ( .A(n7010), .Y(n7021) );
BUFX3TS U6089 ( .A(n7041), .Y(n7020) );
CLKBUFX3TS U6090 ( .A(n4498), .Y(n7040) );
BUFX3TS U6091 ( .A(n7011), .Y(n7039) );
BUFX3TS U6092 ( .A(n7010), .Y(n7038) );
BUFX3TS U6093 ( .A(n7011), .Y(n7037) );
BUFX3TS U6094 ( .A(n4497), .Y(n6959) );
BUFX3TS U6095 ( .A(n4496), .Y(n7036) );
BUFX3TS U6096 ( .A(n7010), .Y(n7035) );
BUFX3TS U6097 ( .A(n4492), .Y(n6960) );
BUFX3TS U6098 ( .A(n4498), .Y(n7026) );
BUFX3TS U6099 ( .A(n4497), .Y(n6988) );
BUFX3TS U6100 ( .A(n7028), .Y(n7009) );
BUFX3TS U6101 ( .A(n7010), .Y(n7008) );
BUFX3TS U6102 ( .A(n4494), .Y(n7058) );
BUFX3TS U6103 ( .A(n4490), .Y(n6963) );
BUFX3TS U6104 ( .A(n7013), .Y(n7006) );
BUFX3TS U6105 ( .A(n4498), .Y(n7005) );
BUFX3TS U6106 ( .A(n4486), .Y(n6964) );
BUFX3TS U6107 ( .A(n4496), .Y(n7004) );
BUFX3TS U6108 ( .A(n4487), .Y(n6965) );
BUFX3TS U6109 ( .A(n4497), .Y(n6992) );
BUFX3TS U6110 ( .A(n7011), .Y(n7003) );
BUFX3TS U6111 ( .A(n4497), .Y(n6991) );
BUFX3TS U6112 ( .A(n7028), .Y(n7007) );
BUFX3TS U6113 ( .A(n7019), .Y(n7030) );
BUFX3TS U6114 ( .A(n7010), .Y(n7034) );
BUFX3TS U6115 ( .A(n4497), .Y(n6962) );
BUFX3TS U6116 ( .A(n7011), .Y(n7029) );
BUFX3TS U6117 ( .A(n6852), .Y(n6625) );
OAI2BB2XLTS U6118 ( .B0(n6852), .B1(n6763), .A0N(n6625), .A1N(
FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1457) );
XNOR2X1TS U6119 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .B(n6798), .Y(n4501) );
BUFX3TS U6120 ( .A(n4499), .Y(n6233) );
AOI22X1TS U6121 ( .A0(n6233), .A1(FPADDSUB_DmP_mant_SFG_SWR[1]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n6232), .Y(n4500) );
OAI2BB1X1TS U6122 ( .A0N(n6024), .A1N(n4501), .B0(n4500), .Y(n1348) );
INVX2TS U6123 ( .A(n4503), .Y(n4505) );
NAND2X1TS U6124 ( .A(n4505), .B(n4504), .Y(n4507) );
INVX2TS U6125 ( .A(n4507), .Y(n4506) );
XOR2X1TS U6126 ( .A(n4507), .B(n4511), .Y(n4508) );
AOI22X1TS U6127 ( .A0(n4508), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.B1(n6232), .Y(n4509) );
OAI2BB1X1TS U6128 ( .A0N(n6024), .A1N(n4510), .B0(n4509), .Y(n1346) );
OR2X1TS U6129 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n4512) );
CLKAND2X2TS U6130 ( .A(n4512), .B(n4511), .Y(n4514) );
AOI22X1TS U6131 ( .A0(n4514), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[2]),
.B1(n6232), .Y(n4515) );
OAI2BB1X1TS U6132 ( .A0N(n6024), .A1N(n4516), .B0(n4515), .Y(n1347) );
INVX2TS U6133 ( .A(n4534), .Y(n4520) );
NAND2X1TS U6134 ( .A(n4520), .B(n4533), .Y(n4524) );
INVX2TS U6135 ( .A(n4524), .Y(n4521) );
XNOR2X1TS U6136 ( .A(n4522), .B(n4521), .Y(n4527) );
INVX2TS U6137 ( .A(n4523), .Y(n4535) );
XOR2X1TS U6138 ( .A(n4535), .B(n4524), .Y(n4525) );
AOI22X1TS U6139 ( .A0(n4525), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[4]),
.B1(n6232), .Y(n4526) );
OAI2BB1X1TS U6140 ( .A0N(n6024), .A1N(n4527), .B0(n4526), .Y(n1345) );
INVX2TS U6141 ( .A(n4528), .Y(n6225) );
INVX2TS U6142 ( .A(n4529), .Y(n4531) );
NAND2X1TS U6143 ( .A(n4531), .B(n4530), .Y(n4536) );
INVX2TS U6144 ( .A(n4536), .Y(n4532) );
XNOR2X1TS U6145 ( .A(n6225), .B(n4532), .Y(n4540) );
XNOR2X1TS U6146 ( .A(n4537), .B(n4536), .Y(n4538) );
AOI22X1TS U6147 ( .A0(n4538), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.B1(n6232), .Y(n4539) );
OAI2BB1X1TS U6148 ( .A0N(n6024), .A1N(n4540), .B0(n4539), .Y(n1344) );
BUFX3TS U6149 ( .A(n5937), .Y(n6710) );
OAI2BB2XLTS U6150 ( .B0(n6449), .B1(n2415), .A0N(n6444), .A1N(
intadd_517_SUM_0_), .Y(n1852) );
NAND3X1TS U6151 ( .A(n6802), .B(FPSENCOS_cont_var_out[0]), .C(ready_add_subt), .Y(n6385) );
BUFX3TS U6152 ( .A(n6385), .Y(n6535) );
BUFX3TS U6153 ( .A(n6385), .Y(n6387) );
OAI2BB2XLTS U6154 ( .B0(n6535), .B1(n6540), .A0N(n6387), .A1N(
FPSENCOS_d_ff_Yn[29]), .Y(n1767) );
NOR4X1TS U6155 ( .A(FPMULT_P_Sgf[13]), .B(FPMULT_P_Sgf[17]), .C(
FPMULT_P_Sgf[15]), .D(FPMULT_P_Sgf[16]), .Y(n4549) );
NOR4X1TS U6156 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_P_Sgf[5]), .C(
FPMULT_P_Sgf[3]), .D(FPMULT_P_Sgf[4]), .Y(n4544) );
NOR3XLTS U6157 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[0]), .C(
FPMULT_P_Sgf[2]), .Y(n4543) );
NOR4X1TS U6158 ( .A(FPMULT_P_Sgf[9]), .B(FPMULT_P_Sgf[10]), .C(
FPMULT_P_Sgf[14]), .D(FPMULT_P_Sgf[12]), .Y(n4542) );
AND4X1TS U6159 ( .A(n4544), .B(n4543), .C(n4542), .D(n4541), .Y(n4547) );
XOR2X1TS U6160 ( .A(FPMULT_Op_MY[31]), .B(FPMULT_Op_MX[31]), .Y(n6610) );
MXI2X1TS U6161 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n6610), .Y(n4545) );
AOI31X1TS U6162 ( .A0(n4549), .A1(n4548), .A2(n4547), .B0(n4546), .Y(n5451)
);
INVX2TS U6163 ( .A(n4551), .Y(n1528) );
BUFX3TS U6164 ( .A(n6387), .Y(n6393) );
OAI2BB2XLTS U6165 ( .B0(n6448), .B1(n2441), .A0N(n6448), .A1N(
intadd_517_SUM_1_), .Y(n1851) );
NAND3X2TS U6166 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n4552),
.C(n4671), .Y(n6346) );
NOR3BX2TS U6167 ( .AN(n6346), .B(n2298), .C(ready_add_subt), .Y(n6360) );
BUFX3TS U6168 ( .A(n6444), .Y(n6471) );
INVX2TS U6169 ( .A(n6449), .Y(n6544) );
NAND2X1TS U6170 ( .A(n6455), .B(n6783), .Y(intadd_518_CI) );
NOR2X2TS U6171 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_518_n1), .Y(n6433) );
NAND2X1TS U6172 ( .A(n6433), .B(n6838), .Y(n6436) );
NOR2X1TS U6173 ( .A(n2420), .B(n6765), .Y(n7065) );
BUFX3TS U6174 ( .A(n6414), .Y(n6427) );
OAI2BB2XLTS U6175 ( .B0(n6783), .B1(n6415), .A0N(FPSENCOS_d_ff_Xn[23]),
.A1N(n6427), .Y(n1959) );
OAI2BB2XLTS U6176 ( .B0(n6841), .B1(n6415), .A0N(FPSENCOS_d_ff_Yn[28]),
.A1N(n6427), .Y(n1856) );
OAI2BB2XLTS U6177 ( .B0(n6851), .B1(n6415), .A0N(FPSENCOS_d_ff_Xn[30]),
.A1N(n6427), .Y(n1952) );
OAI22X1TS U6178 ( .A0(n2320), .A1(n5538), .B0(n5548), .B1(n5537), .Y(n4571)
);
ADDHX1TS U6179 ( .A(n4560), .B(n4559), .CO(n4443), .S(n4570) );
INVX2TS U6180 ( .A(n4564), .Y(n4566) );
NAND2X1TS U6181 ( .A(n4566), .B(n4565), .Y(n4567) );
CLKXOR2X4TS U6182 ( .A(n4568), .B(n4567), .Y(n5546) );
OAI22X1TS U6183 ( .A0(n5546), .A1(n5540), .B0(n2321), .B1(n5539), .Y(n4569)
);
INVX2TS U6184 ( .A(n4573), .Y(n5622) );
INVX2TS U6185 ( .A(n4574), .Y(n5458) );
OR2X2TS U6186 ( .A(n5458), .B(n5454), .Y(n5876) );
NAND2X1TS U6187 ( .A(n5876), .B(FPMULT_Add_result[0]), .Y(n4575) );
NAND2X1TS U6188 ( .A(n6848), .B(n6763), .Y(intadd_516_CI) );
NOR3X1TS U6189 ( .A(n6757), .B(n6787), .C(FPMULT_FS_Module_state_reg[2]),
.Y(n6023) );
NAND2X1TS U6190 ( .A(n6023), .B(n6790), .Y(n6605) );
INVX2TS U6191 ( .A(n6605), .Y(n6020) );
INVX2TS U6192 ( .A(n5876), .Y(n5931) );
INVX2TS U6193 ( .A(n6564), .Y(n5460) );
OAI31X1TS U6194 ( .A0(n6020), .A1(n5899), .A2(n6784), .B0(n4576), .Y(n1622)
);
AOI211X1TS U6195 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n4576), .B0(n6020),
.C0(n5873), .Y(n4577) );
INVX2TS U6196 ( .A(n4577), .Y(n1623) );
INVX2TS U6197 ( .A(intadd_514_SUM_0_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3) );
INVX2TS U6198 ( .A(intadd_512_SUM_0_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3) );
INVX2TS U6199 ( .A(n6923), .Y(n6922) );
INVX2TS U6200 ( .A(intadd_514_SUM_1_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4) );
INVX2TS U6201 ( .A(intadd_512_SUM_1_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4) );
BUFX3TS U6202 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n6713) );
INVX2TS U6203 ( .A(n2359), .Y(n5450) );
INVX2TS U6204 ( .A(intadd_514_SUM_2_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5) );
INVX2TS U6205 ( .A(intadd_512_SUM_2_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5) );
NAND2X1TS U6206 ( .A(n6757), .B(n6751), .Y(n5455) );
AOI21X1TS U6207 ( .A0(n2382), .A1(n6904), .B0(n4580), .Y(n4583) );
INVX2TS U6208 ( .A(n4581), .Y(n5457) );
AOI21X1TS U6209 ( .A0(begin_operation), .A1(n4666), .B0(n4494), .Y(n4582) );
INVX2TS U6210 ( .A(intadd_514_SUM_3_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6) );
INVX2TS U6211 ( .A(intadd_512_SUM_3_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6) );
NOR2X1TS U6212 ( .A(n5326), .B(FPADDSUB_ADD_OVRFLW_NRM), .Y(n5273) );
NAND2X1TS U6213 ( .A(n5452), .B(n5460), .Y(n4584) );
NAND2X1TS U6214 ( .A(n4588), .B(FPMULT_FSM_selector_C), .Y(n4585) );
OR2X2TS U6215 ( .A(n6260), .B(n4585), .Y(n4651) );
INVX2TS U6216 ( .A(n4651), .Y(n4621) );
BUFX3TS U6217 ( .A(n4595), .Y(n4648) );
NOR3X1TS U6218 ( .A(n6260), .B(n1575), .C(n4646), .Y(n4587) );
INVX2TS U6219 ( .A(intadd_514_SUM_4_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7) );
INVX2TS U6220 ( .A(intadd_512_SUM_4_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7) );
INVX2TS U6221 ( .A(n4589), .Y(n4609) );
AND2X2TS U6222 ( .A(n6260), .B(n4590), .Y(n4610) );
CLKBUFX2TS U6223 ( .A(n4610), .Y(n4602) );
AOI22X1TS U6224 ( .A0(n4637), .A1(n1561), .B0(n4602), .B1(FPMULT_P_Sgf[33]),
.Y(n4592) );
INVX2TS U6225 ( .A(n4651), .Y(n4642) );
BUFX3TS U6226 ( .A(n4595), .Y(n4638) );
AOI22X1TS U6227 ( .A0(n4632), .A1(FPMULT_Add_result[9]), .B0(
FPMULT_Sgf_normalized_result[9]), .B1(n4638), .Y(n4591) );
AOI22X1TS U6228 ( .A0(n4641), .A1(FPMULT_P_Sgf[26]), .B0(n4602), .B1(
FPMULT_P_Sgf[27]), .Y(n4594) );
AOI22X1TS U6229 ( .A0(n4642), .A1(FPMULT_Add_result[3]), .B0(
FPMULT_Sgf_normalized_result[3]), .B1(n4638), .Y(n4593) );
INVX2TS U6230 ( .A(n4609), .Y(n4641) );
AOI22X1TS U6231 ( .A0(n4641), .A1(n1570), .B0(n4602), .B1(n1571), .Y(n4597)
);
INVX2TS U6232 ( .A(n4651), .Y(n4632) );
AOI22X1TS U6233 ( .A0(n4632), .A1(FPMULT_Add_result[18]), .B0(
FPMULT_Sgf_normalized_result[18]), .B1(n4595), .Y(n4596) );
AOI22X1TS U6234 ( .A0(n4589), .A1(FPMULT_P_Sgf[24]), .B0(n4602), .B1(
FPMULT_P_Sgf[25]), .Y(n4599) );
AOI22X1TS U6235 ( .A0(n4642), .A1(FPMULT_Add_result[1]), .B0(
FPMULT_Sgf_normalized_result[1]), .B1(n4638), .Y(n4598) );
AOI22X1TS U6236 ( .A0(n4589), .A1(FPMULT_P_Sgf[34]), .B0(n4602), .B1(
FPMULT_P_Sgf[35]), .Y(n4601) );
AOI22X1TS U6237 ( .A0(n4621), .A1(FPMULT_Add_result[11]), .B0(
FPMULT_Sgf_normalized_result[11]), .B1(n4595), .Y(n4600) );
AOI22X1TS U6238 ( .A0(n4637), .A1(FPMULT_P_Sgf[30]), .B0(n4602), .B1(
FPMULT_P_Sgf[31]), .Y(n4604) );
AOI22X1TS U6239 ( .A0(n4621), .A1(FPMULT_Add_result[7]), .B0(
FPMULT_Sgf_normalized_result[7]), .B1(n4638), .Y(n4603) );
AOI22X1TS U6240 ( .A0(n4637), .A1(n1566), .B0(n4610), .B1(n1567), .Y(n4606)
);
AOI22X1TS U6241 ( .A0(n4642), .A1(FPMULT_Add_result[14]), .B0(
FPMULT_Sgf_normalized_result[14]), .B1(n4595), .Y(n4605) );
AOI22X1TS U6242 ( .A0(n4641), .A1(n1571), .B0(n4610), .B1(n1572), .Y(n4608)
);
AOI22X1TS U6243 ( .A0(n4621), .A1(FPMULT_Add_result[19]), .B0(
FPMULT_Sgf_normalized_result[19]), .B1(n4648), .Y(n4607) );
INVX2TS U6244 ( .A(n4609), .Y(n4637) );
BUFX3TS U6245 ( .A(n4610), .Y(n4645) );
AOI22X1TS U6246 ( .A0(n4641), .A1(n1565), .B0(n4645), .B1(n1566), .Y(n4612)
);
AOI22X1TS U6247 ( .A0(n4632), .A1(FPMULT_Add_result[13]), .B0(
FPMULT_Sgf_normalized_result[13]), .B1(n4595), .Y(n4611) );
AOI22X1TS U6248 ( .A0(n4637), .A1(n1567), .B0(n4645), .B1(n1568), .Y(n4614)
);
AOI22X1TS U6249 ( .A0(n4642), .A1(FPMULT_Add_result[15]), .B0(
FPMULT_Sgf_normalized_result[15]), .B1(n4595), .Y(n4613) );
AOI22X1TS U6250 ( .A0(n4637), .A1(n1572), .B0(n4645), .B1(n1573), .Y(n4616)
);
AOI22X1TS U6251 ( .A0(n4632), .A1(FPMULT_Add_result[20]), .B0(
FPMULT_Sgf_normalized_result[20]), .B1(n4648), .Y(n4615) );
AOI22X1TS U6252 ( .A0(n4637), .A1(n1568), .B0(n4645), .B1(n1569), .Y(n4618)
);
AOI22X1TS U6253 ( .A0(n4621), .A1(FPMULT_Add_result[16]), .B0(
FPMULT_Sgf_normalized_result[16]), .B1(n4648), .Y(n4617) );
AOI22X1TS U6254 ( .A0(n4641), .A1(n1569), .B0(n4645), .B1(n1570), .Y(n4620)
);
AOI22X1TS U6255 ( .A0(n4632), .A1(FPMULT_Add_result[17]), .B0(
FPMULT_Sgf_normalized_result[17]), .B1(n4595), .Y(n4619) );
AOI22X1TS U6256 ( .A0(n4641), .A1(n1573), .B0(n1574), .B1(n4610), .Y(n4623)
);
AOI22X1TS U6257 ( .A0(n4621), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_Sgf_normalized_result[21]), .B1(n4648), .Y(n4622) );
AOI22X1TS U6258 ( .A0(n4637), .A1(FPMULT_P_Sgf[25]), .B0(n4610), .B1(
FPMULT_P_Sgf[26]), .Y(n4625) );
AOI22X1TS U6259 ( .A0(n4632), .A1(FPMULT_Add_result[2]), .B0(
FPMULT_Sgf_normalized_result[2]), .B1(n4638), .Y(n4624) );
AOI22X1TS U6260 ( .A0(n4641), .A1(FPMULT_P_Sgf[27]), .B0(n4610), .B1(
FPMULT_P_Sgf[28]), .Y(n4627) );
AOI22X1TS U6261 ( .A0(n4621), .A1(FPMULT_Add_result[4]), .B0(
FPMULT_Sgf_normalized_result[4]), .B1(n4638), .Y(n4626) );
AOI22X1TS U6262 ( .A0(n4637), .A1(FPMULT_P_Sgf[35]), .B0(n4645), .B1(n1565),
.Y(n4629) );
AOI22X1TS U6263 ( .A0(n4642), .A1(FPMULT_Add_result[12]), .B0(
FPMULT_Sgf_normalized_result[12]), .B1(n4648), .Y(n4628) );
AOI22X1TS U6264 ( .A0(n4641), .A1(FPMULT_P_Sgf[29]), .B0(n4645), .B1(
FPMULT_P_Sgf[30]), .Y(n4631) );
AOI22X1TS U6265 ( .A0(n4632), .A1(FPMULT_Add_result[6]), .B0(
FPMULT_Sgf_normalized_result[6]), .B1(n4638), .Y(n4630) );
AOI22X1TS U6266 ( .A0(n4589), .A1(FPMULT_P_Sgf[33]), .B0(n4610), .B1(
FPMULT_P_Sgf[34]), .Y(n4634) );
AOI22X1TS U6267 ( .A0(n4621), .A1(FPMULT_Add_result[10]), .B0(
FPMULT_Sgf_normalized_result[10]), .B1(n4638), .Y(n4633) );
AOI22X1TS U6268 ( .A0(n4637), .A1(FPMULT_P_Sgf[31]), .B0(n4610), .B1(n1561),
.Y(n4636) );
AOI22X1TS U6269 ( .A0(n4642), .A1(FPMULT_Add_result[8]), .B0(
FPMULT_Sgf_normalized_result[8]), .B1(n4638), .Y(n4635) );
AOI22X1TS U6270 ( .A0(FPMULT_P_Sgf[23]), .A1(n4589), .B0(n4645), .B1(
FPMULT_P_Sgf[24]), .Y(n4640) );
AOI22X1TS U6271 ( .A0(n4632), .A1(FPMULT_Add_result[0]), .B0(
FPMULT_Sgf_normalized_result[0]), .B1(n4638), .Y(n4639) );
AOI22X1TS U6272 ( .A0(n4641), .A1(FPMULT_P_Sgf[28]), .B0(n4645), .B1(
FPMULT_P_Sgf[29]), .Y(n4644) );
AOI22X1TS U6273 ( .A0(n4642), .A1(FPMULT_Add_result[5]), .B0(
FPMULT_Sgf_normalized_result[5]), .B1(n4595), .Y(n4643) );
AOI22X1TS U6274 ( .A0(n4645), .A1(n1575), .B0(n2227), .B1(
FPMULT_Add_result[23]), .Y(n4650) );
NOR3BX1TS U6275 ( .AN(n1574), .B(n6260), .C(n4646), .Y(n4647) );
AOI21X1TS U6276 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n4648), .B0(
n4647), .Y(n4649) );
INVX2TS U6277 ( .A(n4994), .Y(n4668) );
NOR2X4TS U6278 ( .A(operation[2]), .B(n6342), .Y(n4674) );
AOI22X1TS U6279 ( .A0(n4674), .A1(cordic_result[9]), .B0(n4707), .B1(
mult_result[9]), .Y(n4652) );
AOI22X1TS U6280 ( .A0(cordic_result[6]), .A1(n4674), .B0(n4707), .B1(
mult_result[6]), .Y(n4653) );
AOI22X1TS U6281 ( .A0(n4674), .A1(cordic_result[7]), .B0(n4707), .B1(
mult_result[7]), .Y(n4654) );
AOI22X1TS U6282 ( .A0(n4674), .A1(cordic_result[5]), .B0(n4707), .B1(
mult_result[5]), .Y(n4655) );
INVX2TS U6283 ( .A(result_add_subt[11]), .Y(n6662) );
AOI22X1TS U6284 ( .A0(n4674), .A1(cordic_result[11]), .B0(n4707), .B1(
mult_result[11]), .Y(n4656) );
INVX2TS U6285 ( .A(n4994), .Y(n4685) );
INVX2TS U6286 ( .A(n4581), .Y(n4683) );
AOI22X1TS U6287 ( .A0(cordic_result[24]), .A1(n4674), .B0(n5457), .B1(
mult_result[24]), .Y(n4657) );
AOI22X1TS U6288 ( .A0(n4674), .A1(cordic_result[10]), .B0(n4683), .B1(
mult_result[10]), .Y(n4658) );
INVX2TS U6289 ( .A(result_add_subt[8]), .Y(n6659) );
AOI22X1TS U6290 ( .A0(n4674), .A1(cordic_result[8]), .B0(n5457), .B1(
mult_result[8]), .Y(n4659) );
NOR2XLTS U6291 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n4660) );
NOR3BX1TS U6292 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(n4661), .Y(n6339) );
NOR3BX1TS U6293 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(n4661), .Y(n6343) );
BUFX3TS U6294 ( .A(n6382), .Y(n6379) );
INVX2TS U6295 ( .A(n6379), .Y(n6384) );
AOI32X1TS U6296 ( .A0(n6379), .A1(operation[0]), .A2(operation[1]), .B0(
FPSENCOS_d_ff1_operation_out), .B1(n6384), .Y(n4662) );
INVX2TS U6297 ( .A(n4662), .Y(n2080) );
INVX2TS U6298 ( .A(n6915), .Y(busy) );
INVX2TS U6299 ( .A(intadd_514_SUM_5_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8) );
CLKBUFX2TS U6300 ( .A(n4674), .Y(n4672) );
AOI22X1TS U6301 ( .A0(cordic_result[4]), .A1(n4672), .B0(n4707), .B1(
mult_result[4]), .Y(n4663) );
AOI22X1TS U6302 ( .A0(n4672), .A1(cordic_result[2]), .B0(n4707), .B1(
mult_result[2]), .Y(n4664) );
INVX2TS U6303 ( .A(n4994), .Y(n4670) );
AOI22X1TS U6304 ( .A0(cordic_result[1]), .A1(n4672), .B0(n5457), .B1(
mult_result[1]), .Y(n4665) );
AOI22X1TS U6305 ( .A0(n4672), .A1(cordic_result[3]), .B0(n4707), .B1(
mult_result[3]), .Y(n4667) );
AOI22X1TS U6306 ( .A0(n4672), .A1(cordic_result[0]), .B0(n4683), .B1(
mult_result[0]), .Y(n4669) );
INVX2TS U6307 ( .A(intadd_512_SUM_5_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8) );
NOR2X1TS U6308 ( .A(n6751), .B(n6790), .Y(n5453) );
AOI22X1TS U6309 ( .A0(n4994), .A1(ready_add_subt), .B0(n6337), .B1(n4672),
.Y(n4673) );
INVX2TS U6310 ( .A(result_add_subt[31]), .Y(n6554) );
AOI22X1TS U6311 ( .A0(cordic_result[31]), .A1(n4697), .B0(n4666), .B1(
mult_result[31]), .Y(n4675) );
AOI22X1TS U6312 ( .A0(cordic_result[26]), .A1(n4697), .B0(n4683), .B1(
mult_result[26]), .Y(n4676) );
INVX2TS U6313 ( .A(result_add_subt[22]), .Y(n6631) );
AOI22X1TS U6314 ( .A0(cordic_result[22]), .A1(n4697), .B0(n5457), .B1(
mult_result[22]), .Y(n4677) );
AOI22X1TS U6315 ( .A0(cordic_result[29]), .A1(n4697), .B0(n4666), .B1(
mult_result[29]), .Y(n4678) );
AOI22X1TS U6316 ( .A0(cordic_result[25]), .A1(n4697), .B0(n4683), .B1(
mult_result[25]), .Y(n4679) );
AOI22X1TS U6317 ( .A0(cordic_result[28]), .A1(n4697), .B0(n5457), .B1(
mult_result[28]), .Y(n4680) );
AOI22X1TS U6318 ( .A0(cordic_result[23]), .A1(n4697), .B0(n4666), .B1(
mult_result[23]), .Y(n4681) );
AOI22X1TS U6319 ( .A0(cordic_result[27]), .A1(n4697), .B0(n4683), .B1(
mult_result[27]), .Y(n4682) );
AOI22X1TS U6320 ( .A0(cordic_result[30]), .A1(n4697), .B0(n4666), .B1(
mult_result[30]), .Y(n4684) );
NOR2X2TS U6321 ( .A(n6367), .B(FPSENCOS_cont_iter_out[1]), .Y(n4990) );
AOI22X1TS U6322 ( .A0(FPSENCOS_d_ff3_LUT_out[2]), .A1(n6456), .B0(n6372),
.B1(n4990), .Y(n4686) );
INVX2TS U6323 ( .A(n4808), .Y(n4687) );
NAND2X2TS U6324 ( .A(n5207), .B(n2256), .Y(n4806) );
NOR2X1TS U6325 ( .A(FPADDSUB_Raw_mant_NRM_SWR[15]), .B(
FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n4807) );
NOR2X1TS U6326 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(n4689) );
NOR2BX1TS U6327 ( .AN(n5208), .B(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n4688)
);
INVX2TS U6328 ( .A(n4753), .Y(n5217) );
NAND2X1TS U6329 ( .A(FPADDSUB_Raw_mant_NRM_SWR[5]), .B(n5210), .Y(n4816) );
NAND2X1TS U6330 ( .A(n6796), .B(n6760), .Y(n5230) );
NOR2BX1TS U6331 ( .AN(n4816), .B(n4693), .Y(n4696) );
NAND2X1TS U6332 ( .A(n5326), .B(FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n4695)
);
INVX2TS U6333 ( .A(intadd_514_SUM_6_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9) );
INVX2TS U6334 ( .A(n4994), .Y(n4710) );
INVX2TS U6335 ( .A(n4581), .Y(n4707) );
AOI22X1TS U6336 ( .A0(cordic_result[12]), .A1(n4708), .B0(n4666), .B1(
mult_result[12]), .Y(n4698) );
INVX2TS U6337 ( .A(result_add_subt[21]), .Y(n6641) );
AOI22X1TS U6338 ( .A0(cordic_result[21]), .A1(n4708), .B0(n4666), .B1(
mult_result[21]), .Y(n4699) );
INVX2TS U6339 ( .A(result_add_subt[20]), .Y(n6647) );
AOI22X1TS U6340 ( .A0(n4708), .A1(cordic_result[20]), .B0(n4683), .B1(
mult_result[20]), .Y(n4700) );
INVX2TS U6341 ( .A(result_add_subt[18]), .Y(n6638) );
AOI22X1TS U6342 ( .A0(cordic_result[18]), .A1(n4708), .B0(n5457), .B1(
mult_result[18]), .Y(n4701) );
INVX2TS U6343 ( .A(result_add_subt[19]), .Y(n6644) );
AOI22X1TS U6344 ( .A0(n4708), .A1(cordic_result[19]), .B0(n4683), .B1(
mult_result[19]), .Y(n4702) );
INVX2TS U6345 ( .A(result_add_subt[15]), .Y(n6634) );
AOI22X1TS U6346 ( .A0(cordic_result[15]), .A1(n4708), .B0(n4666), .B1(
mult_result[15]), .Y(n4703) );
INVX2TS U6347 ( .A(result_add_subt[16]), .Y(n6655) );
AOI22X1TS U6348 ( .A0(cordic_result[16]), .A1(n4708), .B0(n4683), .B1(
mult_result[16]), .Y(n4704) );
INVX2TS U6349 ( .A(result_add_subt[17]), .Y(n6650) );
AOI22X1TS U6350 ( .A0(n4708), .A1(cordic_result[17]), .B0(n5457), .B1(
mult_result[17]), .Y(n4705) );
INVX2TS U6351 ( .A(result_add_subt[13]), .Y(n6652) );
AOI22X1TS U6352 ( .A0(cordic_result[13]), .A1(n4708), .B0(n4683), .B1(
mult_result[13]), .Y(n4706) );
AOI22X1TS U6353 ( .A0(cordic_result[14]), .A1(n4708), .B0(n5457), .B1(
mult_result[14]), .Y(n4709) );
INVX2TS U6354 ( .A(intadd_512_SUM_6_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9) );
BUFX3TS U6355 ( .A(n4723), .Y(n4730) );
NOR2X2TS U6356 ( .A(n6413), .B(n4711), .Y(n4721) );
INVX2TS U6357 ( .A(n4712), .Y(n1752) );
INVX2TS U6358 ( .A(n4713), .Y(n1749) );
INVX2TS U6359 ( .A(n4714), .Y(n1747) );
INVX2TS U6360 ( .A(n4715), .Y(n1753) );
INVX2TS U6361 ( .A(n4716), .Y(n1751) );
INVX2TS U6362 ( .A(n4717), .Y(n1750) );
INVX2TS U6363 ( .A(n4718), .Y(n1745) );
INVX2TS U6364 ( .A(n4719), .Y(n1746) );
INVX2TS U6365 ( .A(n4720), .Y(n1748) );
BUFX3TS U6366 ( .A(n4723), .Y(n4737) );
INVX2TS U6367 ( .A(n4722), .Y(n1734) );
BUFX3TS U6368 ( .A(n4723), .Y(n4747) );
INVX2TS U6369 ( .A(n4724), .Y(n1754) );
INVX2TS U6370 ( .A(n6415), .Y(n6469) );
BUFX3TS U6371 ( .A(n4931), .Y(n4736) );
INVX2TS U6372 ( .A(n4725), .Y(n1742) );
INVX2TS U6373 ( .A(n4726), .Y(n1743) );
INVX2TS U6374 ( .A(n4727), .Y(n1737) );
INVX2TS U6375 ( .A(n4728), .Y(n1739) );
INVX2TS U6376 ( .A(n4729), .Y(n1735) );
INVX2TS U6377 ( .A(n4732), .Y(n1744) );
INVX2TS U6378 ( .A(n4733), .Y(n1741) );
INVX2TS U6379 ( .A(n4734), .Y(n1740) );
INVX2TS U6380 ( .A(n4735), .Y(n1736) );
INVX2TS U6381 ( .A(n4738), .Y(n1738) );
BUFX3TS U6382 ( .A(n4931), .Y(n4933) );
INVX2TS U6383 ( .A(n4739), .Y(n1761) );
INVX2TS U6384 ( .A(n4740), .Y(n1763) );
INVX2TS U6385 ( .A(n4741), .Y(n1756) );
INVX2TS U6386 ( .A(n4742), .Y(n1762) );
INVX2TS U6387 ( .A(n4743), .Y(n1759) );
INVX2TS U6388 ( .A(n4744), .Y(n1758) );
INVX2TS U6389 ( .A(n4745), .Y(n1757) );
INVX2TS U6390 ( .A(n4746), .Y(n1760) );
INVX2TS U6391 ( .A(n4749), .Y(n1755) );
NOR2X2TS U6392 ( .A(FPSENCOS_cont_iter_out[1]), .B(n6442), .Y(n4759) );
NAND2X1TS U6393 ( .A(n6455), .B(n6369), .Y(n6368) );
AOI22X1TS U6394 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n6456), .B0(n4759),
.B1(n6368), .Y(n4750) );
AOI21X1TS U6395 ( .A0(n6455), .A1(n6372), .B0(FPSENCOS_cont_iter_out[3]),
.Y(n4751) );
AOI22X1TS U6396 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n6456), .B0(n4759),
.B1(n4751), .Y(n4752) );
NAND3X2TS U6397 ( .A(n4753), .B(n5218), .C(n6780), .Y(n4814) );
NOR4X1TS U6398 ( .A(FPADDSUB_Raw_mant_NRM_SWR[4]), .B(n4814), .C(n5230), .D(
n6793), .Y(n4754) );
AOI2BB1X1TS U6399 ( .A0N(n4755), .A1N(n4806), .B0(n4754), .Y(n4758) );
NAND2X1TS U6400 ( .A(n5326), .B(FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n4757)
);
AOI22X1TS U6401 ( .A0(FPSENCOS_d_ff3_LUT_out[6]), .A1(n6456), .B0(n6364),
.B1(n4759), .Y(n4761) );
AOI21X1TS U6402 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n6782), .B0(n6362),
.Y(n4822) );
AOI21X1TS U6403 ( .A0(n6372), .A1(n6375), .B0(n4822), .Y(n4987) );
INVX2TS U6404 ( .A(intadd_514_n1), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11) );
INVX2TS U6405 ( .A(intadd_514_SUM_7_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10) );
NAND2X1TS U6406 ( .A(n6569), .B(n6955), .Y(n5477) );
NAND2X1TS U6407 ( .A(FPMULT_Op_MX[2]), .B(n2220), .Y(n5476) );
NOR2X2TS U6408 ( .A(n5477), .B(n5476), .Y(n5816) );
NAND2X2TS U6409 ( .A(n6570), .B(n2220), .Y(n4788) );
NOR2X2TS U6410 ( .A(n4788), .B(n5477), .Y(n5804) );
AOI22X1TS U6411 ( .A0(n6569), .A1(n2220), .B0(n6570), .B1(n6955), .Y(n4762)
);
NOR2X2TS U6412 ( .A(n2258), .B(n2248), .Y(n4769) );
NAND2X1TS U6413 ( .A(n2481), .B(n6587), .Y(n4773) );
XNOR2X1TS U6414 ( .A(n4769), .B(n4773), .Y(n4763) );
XOR2X1TS U6415 ( .A(n4763), .B(n4770), .Y(n5818) );
NAND2X1TS U6416 ( .A(n6587), .B(n6568), .Y(n5845) );
AOI22X1TS U6417 ( .A0(FPMULT_Op_MX[2]), .A1(n6587), .B0(n6568), .B1(n2289),
.Y(n4765) );
INVX2TS U6418 ( .A(n5835), .Y(n4778) );
NAND2X1TS U6419 ( .A(FPMULT_Op_MX[5]), .B(n6955), .Y(n4768) );
NOR2X2TS U6420 ( .A(n4788), .B(n4768), .Y(n5812) );
INVX2TS U6421 ( .A(n5812), .Y(n4791) );
OAI2BB1X1TS U6422 ( .A0N(n4788), .A1N(n4768), .B0(n4791), .Y(n5834) );
INVX2TS U6423 ( .A(n5834), .Y(n4777) );
INVX2TS U6424 ( .A(n4769), .Y(n4772) );
INVX2TS U6425 ( .A(n4770), .Y(n4771) );
OAI22X1TS U6426 ( .A0(n4774), .A1(n4773), .B0(n4772), .B1(n4771), .Y(n5803)
);
NAND2X2TS U6427 ( .A(n2481), .B(FPMULT_Op_MY[4]), .Y(n5807) );
XOR2X1TS U6428 ( .A(n5804), .B(n5807), .Y(n4775) );
XOR2X1TS U6429 ( .A(n5803), .B(n4775), .Y(n5836) );
OAI21X1TS U6430 ( .A0(n4778), .A1(n4777), .B0(n4776), .Y(intadd_514_A_3_) );
NAND2X1TS U6431 ( .A(n6587), .B(n6570), .Y(n4779) );
NOR2X1TS U6432 ( .A(n4793), .B(n4779), .Y(n5788) );
AOI21X1TS U6433 ( .A0(n4793), .A1(n4779), .B0(n5788), .Y(n4781) );
NAND2X1TS U6434 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MX[5]), .Y(n4787) );
INVX2TS U6435 ( .A(n4787), .Y(n4780) );
NAND2X1TS U6436 ( .A(n4781), .B(n4780), .Y(n5789) );
INVX2TS U6437 ( .A(n4781), .Y(n4782) );
NAND2X1TS U6438 ( .A(n4782), .B(n4787), .Y(n4783) );
NAND2X1TS U6439 ( .A(n5789), .B(n4783), .Y(n5826) );
INVX2TS U6440 ( .A(n5826), .Y(n4801) );
INVX2TS U6441 ( .A(n4784), .Y(n4785) );
INVX2TS U6442 ( .A(n5815), .Y(n4792) );
NOR2X2TS U6443 ( .A(n4788), .B(n4787), .Y(n5792) );
AOI22X1TS U6444 ( .A0(n2220), .A1(FPMULT_Op_MX[5]), .B0(n6570), .B1(
FPMULT_Op_MY[2]), .Y(n4789) );
NOR2X1TS U6445 ( .A(n5792), .B(n4789), .Y(n5813) );
INVX2TS U6446 ( .A(n5827), .Y(n4799) );
NOR2X1TS U6447 ( .A(n5807), .B(n4793), .Y(n4796) );
AOI22X1TS U6448 ( .A0(n2481), .A1(n2289), .B0(FPMULT_Op_MY[4]), .B1(
FPMULT_Op_MX[2]), .Y(n4794) );
NOR2X1TS U6449 ( .A(n4796), .B(n4794), .Y(n5811) );
INVX2TS U6450 ( .A(n6569), .Y(n4795) );
NOR2X1TS U6451 ( .A(n4795), .B(n2260), .Y(n5810) );
NAND2X1TS U6452 ( .A(n5811), .B(n5810), .Y(n5809) );
INVX2TS U6453 ( .A(n4796), .Y(n4797) );
NAND2X1TS U6454 ( .A(n5809), .B(n4797), .Y(n5795) );
NAND2X1TS U6455 ( .A(FPMULT_Op_MY[4]), .B(n6569), .Y(n5791) );
XNOR2X1TS U6456 ( .A(n5792), .B(n5791), .Y(n4798) );
XNOR2X1TS U6457 ( .A(n5795), .B(n4798), .Y(n5828) );
OAI21X1TS U6458 ( .A0(n4801), .A1(n5827), .B0(n4800), .Y(intadd_514_A_5_) );
AOI22X1TS U6459 ( .A0(FPMULT_Op_MY[4]), .A1(FPMULT_Op_MX[5]), .B0(n6570),
.B1(n2289), .Y(n4802) );
NAND2X1TS U6460 ( .A(FPMULT_Op_MY[4]), .B(n6570), .Y(n5797) );
NOR2X1TS U6461 ( .A(n5797), .B(intadd_514_A_7_), .Y(n5820) );
NOR2X1TS U6462 ( .A(n4802), .B(n5820), .Y(n4805) );
NAND2X1TS U6463 ( .A(n6569), .B(n2289), .Y(n5796) );
NAND2X1TS U6464 ( .A(n6587), .B(FPMULT_Op_MX[5]), .Y(n5798) );
OAI21X1TS U6465 ( .A0(n5796), .A1(n5798), .B0(n4803), .Y(n4804) );
NAND2X1TS U6466 ( .A(n4804), .B(n4805), .Y(n5821) );
OAI21X1TS U6467 ( .A0(n4805), .A1(n4804), .B0(n5821), .Y(intadd_514_B_6_) );
INVX2TS U6468 ( .A(intadd_512_n1), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11) );
NOR3BX2TS U6469 ( .AN(n4807), .B(n4806), .C(FPADDSUB_Raw_mant_NRM_SWR[16]),
.Y(n5225) );
OAI22X1TS U6470 ( .A0(n4809), .A1(n4808), .B0(n5208), .B1(n4810), .Y(n4818)
);
AOI21X1TS U6471 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n6793), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n4813) );
OAI32X1TS U6472 ( .A0(n4814), .A1(FPADDSUB_Raw_mant_NRM_SWR[3]), .A2(n4813),
.B0(n6791), .B1(n4814), .Y(n4815) );
AOI211X2TS U6473 ( .A0(n5219), .A1(FPADDSUB_Raw_mant_NRM_SWR[12]), .B0(n5215), .C0(n4815), .Y(n5213) );
NAND2X1TS U6474 ( .A(n7059), .B(FPADDSUB_LZD_output_NRM2_EW[2]), .Y(n4820)
);
INVX2TS U6475 ( .A(n4990), .Y(n4989) );
NAND2X1TS U6476 ( .A(n4822), .B(n6768), .Y(n6363) );
INVX2TS U6477 ( .A(intadd_512_SUM_7_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10) );
NAND2X1TS U6478 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MY[12]), .Y(n5716) );
NAND2X1TS U6479 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MY[13]), .Y(n5715) );
NOR2X2TS U6480 ( .A(n5716), .B(n5715), .Y(n5714) );
NAND2X2TS U6481 ( .A(n6579), .B(n5649), .Y(n4850) );
NOR2X2TS U6482 ( .A(n4850), .B(n5716), .Y(n5699) );
AOI22X1TS U6483 ( .A0(FPMULT_Op_MX[15]), .A1(FPMULT_Op_MY[13]), .B0(n6579),
.B1(FPMULT_Op_MY[12]), .Y(n4824) );
NOR2X2TS U6484 ( .A(n2257), .B(n2226), .Y(n4831) );
NAND2X1TS U6485 ( .A(FPMULT_Op_MX[13]), .B(n6594), .Y(n4835) );
XNOR2X1TS U6486 ( .A(n4831), .B(n4835), .Y(n4825) );
XOR2X1TS U6487 ( .A(n4825), .B(n4832), .Y(n5712) );
OAI21X1TS U6488 ( .A0(n5714), .A1(n5711), .B0(n4826), .Y(intadd_512_A_2_) );
NAND2X2TS U6489 ( .A(FPMULT_Op_MX[14]), .B(n5648), .Y(n4855) );
NAND2X1TS U6490 ( .A(n6594), .B(FPMULT_Op_MX[12]), .Y(n5742) );
AOI22X1TS U6491 ( .A0(FPMULT_Op_MX[14]), .A1(FPMULT_Op_MY[15]), .B0(
FPMULT_Op_MX[12]), .B1(n5648), .Y(n4827) );
INVX2TS U6492 ( .A(n5732), .Y(n4840) );
NAND2X1TS U6493 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MX[17]), .Y(n4830) );
NOR2X2TS U6494 ( .A(n4850), .B(n4830), .Y(n5707) );
INVX2TS U6495 ( .A(n5707), .Y(n4853) );
OAI2BB1X1TS U6496 ( .A0N(n4850), .A1N(n4830), .B0(n4853), .Y(n5731) );
INVX2TS U6497 ( .A(n5731), .Y(n4839) );
INVX2TS U6498 ( .A(n4831), .Y(n4834) );
INVX2TS U6499 ( .A(n4832), .Y(n4833) );
OAI22X1TS U6500 ( .A0(n4836), .A1(n4835), .B0(n4834), .B1(n4833), .Y(n5698)
);
NAND2X2TS U6501 ( .A(FPMULT_Op_MX[13]), .B(n2290), .Y(n5702) );
XOR2X1TS U6502 ( .A(n5699), .B(n5702), .Y(n4837) );
XOR2X1TS U6503 ( .A(n5698), .B(n4837), .Y(n5733) );
OAI21X1TS U6504 ( .A0(n4840), .A1(n4839), .B0(n4838), .Y(intadd_512_A_3_) );
NAND2X1TS U6505 ( .A(n6594), .B(n6579), .Y(n4841) );
NOR2X1TS U6506 ( .A(n4855), .B(n4841), .Y(n5683) );
AOI21X1TS U6507 ( .A0(n4855), .A1(n4841), .B0(n5683), .Y(n4843) );
NAND2X1TS U6508 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MX[17]), .Y(n4849) );
INVX2TS U6509 ( .A(n4849), .Y(n4842) );
NAND2X1TS U6510 ( .A(n4843), .B(n4842), .Y(n5684) );
INVX2TS U6511 ( .A(n4843), .Y(n4844) );
NAND2X1TS U6512 ( .A(n4844), .B(n4849), .Y(n4845) );
NAND2X1TS U6513 ( .A(n5684), .B(n4845), .Y(n5723) );
INVX2TS U6514 ( .A(n5723), .Y(n4863) );
INVX2TS U6515 ( .A(n4846), .Y(n4847) );
INVX2TS U6516 ( .A(n5710), .Y(n4854) );
NOR2X2TS U6517 ( .A(n4850), .B(n4849), .Y(n5687) );
AOI22X1TS U6518 ( .A0(n6579), .A1(FPMULT_Op_MY[14]), .B0(FPMULT_Op_MY[13]),
.B1(n2344), .Y(n4851) );
NOR2X1TS U6519 ( .A(n5687), .B(n4851), .Y(n5708) );
INVX2TS U6520 ( .A(n5724), .Y(n4861) );
NOR2X1TS U6521 ( .A(n5702), .B(n4855), .Y(n4858) );
AOI22X1TS U6522 ( .A0(FPMULT_Op_MX[13]), .A1(n5648), .B0(n2290), .B1(
FPMULT_Op_MX[14]), .Y(n4856) );
NOR2X1TS U6523 ( .A(n4858), .B(n4856), .Y(n5706) );
INVX2TS U6524 ( .A(n6594), .Y(n4857) );
NOR2X1TS U6525 ( .A(n2479), .B(n4857), .Y(n5705) );
NAND2X1TS U6526 ( .A(n5706), .B(n5705), .Y(n5704) );
INVX2TS U6527 ( .A(n4858), .Y(n4859) );
NAND2X1TS U6528 ( .A(n5704), .B(n4859), .Y(n5690) );
NAND2X1TS U6529 ( .A(n2290), .B(FPMULT_Op_MX[15]), .Y(n5686) );
XNOR2X1TS U6530 ( .A(n5687), .B(n5686), .Y(n4860) );
XNOR2X1TS U6531 ( .A(n5690), .B(n4860), .Y(n5725) );
OAI21X1TS U6532 ( .A0(n4863), .A1(n5724), .B0(n4862), .Y(intadd_512_A_5_) );
AOI22X1TS U6533 ( .A0(n5648), .A1(n6579), .B0(n2290), .B1(n2344), .Y(n4864)
);
NAND2X1TS U6534 ( .A(n2290), .B(n6579), .Y(n5692) );
NOR2X1TS U6535 ( .A(n5692), .B(intadd_512_A_7_), .Y(n5717) );
NOR2X1TS U6536 ( .A(n4864), .B(n5717), .Y(n4867) );
NAND2X1TS U6537 ( .A(n6594), .B(FPMULT_Op_MX[17]), .Y(n5691) );
NAND2X1TS U6538 ( .A(n5648), .B(FPMULT_Op_MX[15]), .Y(n5693) );
OAI21X1TS U6539 ( .A0(n5691), .A1(n5693), .B0(n4865), .Y(n4866) );
NAND2X1TS U6540 ( .A(n4866), .B(n4867), .Y(n5718) );
OAI21X1TS U6541 ( .A0(n4867), .A1(n4866), .B0(n5718), .Y(intadd_512_B_6_) );
NOR2X1TS U6542 ( .A(n2304), .B(n5539), .Y(DP_OP_502J223_128_4510_n161) );
NAND2X2TS U6543 ( .A(n6584), .B(n6572), .Y(n4892) );
NAND2X1TS U6544 ( .A(DP_OP_501J223_127_5235_n903), .B(n2345), .Y(n4868) );
NOR2X2TS U6545 ( .A(n4892), .B(n4868), .Y(n4897) );
INVX2TS U6546 ( .A(n5773), .Y(n4880) );
NAND2X2TS U6547 ( .A(n2287), .B(n5642), .Y(n4903) );
NAND2X1TS U6548 ( .A(FPMULT_Op_MX[6]), .B(n5643), .Y(n5760) );
AOI22X1TS U6549 ( .A0(n5642), .A1(FPMULT_Op_MX[6]), .B0(FPMULT_Op_MX[8]),
.B1(FPMULT_Op_MY[9]), .Y(n4869) );
NAND2X1TS U6550 ( .A(n4871), .B(n4870), .Y(n4891) );
INVX2TS U6551 ( .A(n5774), .Y(n4879) );
NAND2X1TS U6552 ( .A(DP_OP_501J223_127_5235_n903), .B(
DP_OP_501J223_127_5235_n944), .Y(n5783) );
NOR2X2TS U6553 ( .A(n4892), .B(n5783), .Y(n5748) );
NAND2X2TS U6554 ( .A(FPMULT_Op_MX[7]), .B(n6588), .Y(n4885) );
XOR2X1TS U6555 ( .A(n5748), .B(n4885), .Y(n4877) );
NAND2X1TS U6556 ( .A(n2287), .B(n5644), .Y(n5749) );
NAND2X1TS U6557 ( .A(FPMULT_Op_MX[6]), .B(n6588), .Y(n4873) );
NAND2X1TS U6558 ( .A(n5749), .B(n4873), .Y(n4872) );
NAND2X1TS U6559 ( .A(n4872), .B(n5750), .Y(n4876) );
INVX2TS U6560 ( .A(n5749), .Y(n4874) );
INVX2TS U6561 ( .A(n4873), .Y(n5751) );
NAND2X1TS U6562 ( .A(n4874), .B(n5751), .Y(n4875) );
NAND2X1TS U6563 ( .A(n4876), .B(n4875), .Y(n4883) );
XNOR2X1TS U6564 ( .A(n4877), .B(n4883), .Y(n5775) );
OAI21X1TS U6565 ( .A0(n4880), .A1(n4879), .B0(n4878), .Y(mult_x_311_n29) );
INVX2TS U6566 ( .A(n5748), .Y(n4881) );
NAND2X1TS U6567 ( .A(n4881), .B(n4885), .Y(n4884) );
INVX2TS U6568 ( .A(n4885), .Y(n4882) );
NOR2X1TS U6569 ( .A(n4885), .B(n4903), .Y(n4911) );
AOI22X1TS U6570 ( .A0(FPMULT_Op_MX[7]), .A1(n5642), .B0(FPMULT_Op_MX[8]),
.B1(n6588), .Y(n4886) );
NOR2X1TS U6571 ( .A(n4911), .B(n4886), .Y(n4888) );
NOR2X1TS U6572 ( .A(n2225), .B(n6754), .Y(n4887) );
NAND2X1TS U6573 ( .A(n4888), .B(n4887), .Y(n4913) );
INVX2TS U6574 ( .A(n4889), .Y(n4890) );
NAND2X1TS U6575 ( .A(n2345), .B(n5644), .Y(n4907) );
NOR2X2TS U6576 ( .A(n4892), .B(n4907), .Y(n4920) );
AOI22X1TS U6577 ( .A0(n6584), .A1(n2346), .B0(n6572), .B1(FPMULT_Op_MY[8]),
.Y(n4893) );
NOR2X1TS U6578 ( .A(n4920), .B(n4893), .Y(n4896) );
XOR2X1TS U6579 ( .A(n4896), .B(n4897), .Y(n4894) );
XNOR2X1TS U6580 ( .A(n4898), .B(n4894), .Y(n5771) );
INVX2TS U6581 ( .A(n4898), .Y(n4901) );
INVX2TS U6582 ( .A(n4897), .Y(n4900) );
INVX2TS U6583 ( .A(n5766), .Y(n4917) );
NAND2X1TS U6584 ( .A(FPMULT_Op_MY[9]), .B(n6572), .Y(n4902) );
NOR2X1TS U6585 ( .A(n4903), .B(n4902), .Y(n4905) );
NAND2X1TS U6586 ( .A(n4903), .B(n4902), .Y(n4910) );
NAND2X1TS U6587 ( .A(n4904), .B(n4910), .Y(n4908) );
INVX2TS U6588 ( .A(n4905), .Y(n4906) );
INVX2TS U6589 ( .A(n4907), .Y(n4909) );
INVX2TS U6590 ( .A(n5765), .Y(n4915) );
INVX2TS U6591 ( .A(n4911), .Y(n4912) );
NAND2X1TS U6592 ( .A(n4913), .B(n4912), .Y(n4918) );
NAND2X1TS U6593 ( .A(DP_OP_501J223_127_5235_n944), .B(n6588), .Y(n4923) );
XOR2X1TS U6594 ( .A(n4920), .B(n4923), .Y(n4914) );
XNOR2X1TS U6595 ( .A(n4918), .B(n4914), .Y(n5767) );
OAI21X1TS U6596 ( .A0(n4917), .A1(n5765), .B0(n4916), .Y(mult_x_311_n17) );
INVX2TS U6597 ( .A(n4920), .Y(n4922) );
INVX2TS U6598 ( .A(n4923), .Y(n4919) );
INVX2TS U6599 ( .A(n5763), .Y(n4930) );
INVX2TS U6600 ( .A(n5762), .Y(n4928) );
XNOR2X1TS U6601 ( .A(n4925), .B(n4924), .Y(n4927) );
XOR2X1TS U6602 ( .A(n4927), .B(n4926), .Y(n5761) );
NOR2X1TS U6603 ( .A(n2303), .B(n5547), .Y(DP_OP_502J223_128_4510_n185) );
INVX2TS U6604 ( .A(n4932), .Y(n1733) );
INVX2TS U6605 ( .A(n4934), .Y(n1764) );
AOI22X1TS U6606 ( .A0(n2292), .A1(n2291), .B0(n2285), .B1(n6753), .Y(n4935)
);
INVX2TS U6607 ( .A(n5445), .Y(n4936) );
NAND2X2TS U6608 ( .A(n4936), .B(n7067), .Y(n5674) );
NAND2X1TS U6609 ( .A(n5674), .B(n2291), .Y(n5677) );
NAND2X1TS U6610 ( .A(n5677), .B(n2285), .Y(n4940) );
AOI21X1TS U6611 ( .A0(n5445), .A1(n4938), .B0(n4937), .Y(n5675) );
NAND2X1TS U6612 ( .A(n5674), .B(n2478), .Y(n4939) );
OAI21X1TS U6613 ( .A0(n5674), .A1(n2478), .B0(n5679), .Y(intadd_515_A_0_) );
NAND2X2TS U6614 ( .A(n2383), .B(FPMULT_Op_MX[21]), .Y(n5446) );
AOI22X1TS U6615 ( .A0(n2292), .A1(n6595), .B0(n2383), .B1(FPMULT_Op_MX[19]),
.Y(n4946) );
NAND2X1TS U6616 ( .A(n6567), .B(n6753), .Y(n4944) );
INVX2TS U6617 ( .A(n4941), .Y(n4942) );
INVX2TS U6618 ( .A(n4943), .Y(n4945) );
OAI22X2TS U6619 ( .A0(n5442), .A1(n4946), .B0(n4945), .B1(n4944), .Y(n5668)
);
INVX2TS U6620 ( .A(n5668), .Y(n4954) );
INVX2TS U6621 ( .A(n7067), .Y(n5439) );
INVX2TS U6622 ( .A(n5667), .Y(n4952) );
AOI21X1TS U6623 ( .A0(n4973), .A1(n4948), .B0(n4947), .Y(n4950) );
NAND2X1TS U6624 ( .A(n6585), .B(n2285), .Y(n4958) );
XOR2X1TS U6625 ( .A(n4956), .B(n4958), .Y(n4951) );
XOR2X1TS U6626 ( .A(n4960), .B(n4951), .Y(n5669) );
OAI21X1TS U6627 ( .A0(n4954), .A1(n5667), .B0(n4953), .Y(mult_x_309_n29) );
INVX2TS U6628 ( .A(n4958), .Y(n4955) );
NOR2X1TS U6629 ( .A(n4956), .B(n4955), .Y(n4959) );
INVX2TS U6630 ( .A(n4956), .Y(n4957) );
INVX2TS U6631 ( .A(n5663), .Y(n4967) );
AOI22X1TS U6632 ( .A0(n6567), .A1(n5647), .B0(n2383), .B1(n2285), .Y(n4961)
);
AOI21X2TS U6633 ( .A0(n4963), .A1(n4962), .B0(n5444), .Y(n5664) );
INVX2TS U6634 ( .A(n5664), .Y(n4966) );
XOR2X1TS U6635 ( .A(n5440), .B(n7067), .Y(n4964) );
XOR2X1TS U6636 ( .A(n5442), .B(n4964), .Y(n5665) );
OAI21X1TS U6637 ( .A0(n2285), .A1(n6595), .B0(n4969), .Y(n4974) );
XOR2X1TS U6638 ( .A(n5647), .B(n2285), .Y(n4970) );
OAI22X2TS U6639 ( .A0(n4974), .A1(n4971), .B0(n4970), .B1(n4969), .Y(n5448)
);
OAI21X2TS U6640 ( .A0(n5446), .A1(n5448), .B0(n4972), .Y(n5658) );
INVX2TS U6641 ( .A(n5658), .Y(n4979) );
NAND2X1TS U6642 ( .A(n4974), .B(n4973), .Y(n5655) );
INVX2TS U6643 ( .A(n5655), .Y(n4978) );
XNOR2X1TS U6644 ( .A(n2292), .B(n6585), .Y(n4976) );
XOR2X1TS U6645 ( .A(n4976), .B(n4975), .Y(n5656) );
OAI21X1TS U6646 ( .A0(n4979), .A1(n4978), .B0(n4977), .Y(mult_x_309_n14) );
INVX2TS U6647 ( .A(n4980), .Y(n4981) );
AOI211X1TS U6648 ( .A0(n6456), .A1(FPSENCOS_d_ff3_LUT_out[21]), .B0(n6366),
.C0(n4981), .Y(n4982) );
INVX2TS U6649 ( .A(n4982), .Y(n2118) );
XNOR2X1TS U6650 ( .A(n2266), .B(FPSENCOS_d_ff1_operation_out), .Y(n4983) );
CLKXOR2X2TS U6651 ( .A(n6558), .B(n4983), .Y(n6557) );
INVX2TS U6652 ( .A(n6557), .Y(n6556) );
INVX2TS U6653 ( .A(n4986), .Y(n1696) );
NOR2X2TS U6654 ( .A(n4987), .B(n6768), .Y(n5012) );
AOI21X1TS U6655 ( .A0(FPSENCOS_d_ff3_LUT_out[5]), .A1(n6442), .B0(n5012),
.Y(n4988) );
AOI211X1TS U6656 ( .A0(n6456), .A1(FPSENCOS_d_ff3_LUT_out[9]), .B0(n5012),
.C0(n4990), .Y(n4991) );
INVX2TS U6657 ( .A(n4991), .Y(n2124) );
NAND3X1TS U6658 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n4993),
.C(n4992), .Y(n6347) );
NOR3X2TS U6659 ( .A(n6756), .B(n4998), .C(FPSENCOS_cont_var_out[1]), .Y(
n4995) );
BUFX3TS U6660 ( .A(n5015), .Y(n6505) );
AOI22X1TS U6661 ( .A0(Data_2[21]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[21]),
.B1(n6505), .Y(n5001) );
BUFX3TS U6662 ( .A(n6549), .Y(n5039) );
NOR2X1TS U6663 ( .A(n6756), .B(n6802), .Y(n5463) );
INVX2TS U6664 ( .A(n5463), .Y(n6345) );
BUFX3TS U6665 ( .A(n4999), .Y(n5038) );
AOI22X1TS U6666 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[21]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n5000) );
BUFX3TS U6667 ( .A(n4996), .Y(n6518) );
BUFX3TS U6668 ( .A(n5103), .Y(n6479) );
AOI22X1TS U6669 ( .A0(Data_2[12]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[12]),
.B1(n6479), .Y(n5003) );
AOI22X1TS U6670 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[12]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n5002) );
BUFX3TS U6671 ( .A(n5103), .Y(n6548) );
AOI22X1TS U6672 ( .A0(Data_2[24]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[24]),
.B1(n6548), .Y(n5005) );
AOI22X1TS U6673 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[24]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n5004) );
AOI22X1TS U6674 ( .A0(Data_2[26]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[26]),
.B1(n6548), .Y(n5007) );
AOI22X1TS U6675 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[26]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n5006) );
AOI22X1TS U6676 ( .A0(Data_2[25]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[25]),
.B1(n6548), .Y(n5009) );
AOI22X1TS U6677 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[25]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n5008) );
INVX2TS U6678 ( .A(FPSENCOS_d_ff3_sh_y_out[23]), .Y(n6457) );
AOI22X1TS U6679 ( .A0(Data_2[23]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[23]),
.B1(n6548), .Y(n5011) );
AOI22X1TS U6680 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[23]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n5010) );
AOI211X1TS U6681 ( .A0(n6456), .A1(FPSENCOS_d_ff3_LUT_out[12]), .B0(n5013),
.C0(n5012), .Y(n5014) );
INVX2TS U6682 ( .A(n5014), .Y(n2122) );
BUFX3TS U6683 ( .A(n5052), .Y(n5087) );
BUFX3TS U6684 ( .A(n5053), .Y(n5084) );
BUFX3TS U6685 ( .A(n5015), .Y(n5100) );
AOI22X1TS U6686 ( .A0(Data_1[24]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[24]),
.B1(n5100), .Y(n5017) );
BUFX3TS U6687 ( .A(n6549), .Y(n5094) );
BUFX3TS U6688 ( .A(n4999), .Y(n5097) );
AOI22X1TS U6689 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[24]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n5016) );
BUFX3TS U6690 ( .A(n5052), .Y(n5067) );
BUFX3TS U6691 ( .A(n5103), .Y(n5062) );
AOI22X1TS U6692 ( .A0(Data_1[30]), .A1(n4996), .B0(FPADDSUB_intDX_EWSW[30]),
.B1(n5062), .Y(n5019) );
BUFX3TS U6693 ( .A(n6549), .Y(n5064) );
BUFX3TS U6694 ( .A(n4999), .Y(n5063) );
AOI22X1TS U6695 ( .A0(n5064), .A1(FPSENCOS_d_ff2_Y[30]), .B0(n5063), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n5018) );
AOI22X1TS U6696 ( .A0(Data_1[29]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[29]),
.B1(n5062), .Y(n5021) );
AOI22X1TS U6697 ( .A0(n5064), .A1(FPSENCOS_d_ff2_Y[29]), .B0(n5063), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n5020) );
AOI22X1TS U6698 ( .A0(Data_1[27]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[27]),
.B1(n5062), .Y(n5023) );
AOI22X1TS U6699 ( .A0(n5064), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n5063), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n5022) );
AOI22X1TS U6700 ( .A0(Data_1[25]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[25]),
.B1(n5062), .Y(n5025) );
AOI22X1TS U6701 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[25]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n5024) );
AOI22X1TS U6702 ( .A0(Data_1[26]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[26]),
.B1(n5062), .Y(n5027) );
AOI22X1TS U6703 ( .A0(n5064), .A1(FPSENCOS_d_ff2_Y[26]), .B0(n5063), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n5026) );
AOI22X1TS U6704 ( .A0(Data_2[8]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[8]),
.B1(n6479), .Y(n5029) );
AOI22X1TS U6705 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[8]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n5028) );
AOI22X1TS U6706 ( .A0(Data_2[10]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[10]),
.B1(n6479), .Y(n5031) );
AOI22X1TS U6707 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[10]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n5030) );
OAI211X1TS U6708 ( .A0(n5067), .A1(n2446), .B0(n5031), .C0(n5030), .Y(n1833)
);
AOI22X1TS U6709 ( .A0(Data_2[6]), .A1(n6518), .B0(FPADDSUB_intDY_EWSW[6]),
.B1(n6479), .Y(n5033) );
AOI22X1TS U6710 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[6]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n5032) );
AOI22X1TS U6711 ( .A0(Data_2[2]), .A1(n6518), .B0(FPADDSUB_intDY_EWSW[2]),
.B1(n5062), .Y(n5035) );
AOI22X1TS U6712 ( .A0(n5064), .A1(FPSENCOS_d_ff3_sh_x_out[2]), .B0(n5063),
.B1(FPSENCOS_d_ff3_LUT_out[2]), .Y(n5034) );
AOI22X1TS U6713 ( .A0(Data_2[1]), .A1(n6518), .B0(FPADDSUB_intDY_EWSW[1]),
.B1(n5062), .Y(n5037) );
AOI22X1TS U6714 ( .A0(n5064), .A1(FPSENCOS_d_ff3_sh_x_out[1]), .B0(n5063),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n5036) );
AOI22X1TS U6715 ( .A0(Data_2[9]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[9]),
.B1(n6479), .Y(n5041) );
AOI22X1TS U6716 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[9]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n5040) );
AOI22X1TS U6717 ( .A0(Data_2[4]), .A1(n4996), .B0(FPADDSUB_intDY_EWSW[4]),
.B1(n6479), .Y(n5043) );
AOI22X1TS U6718 ( .A0(n5064), .A1(FPSENCOS_d_ff3_sh_x_out[4]), .B0(n5063),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n5042) );
AOI22X1TS U6719 ( .A0(Data_2[0]), .A1(n6518), .B0(FPADDSUB_intDY_EWSW[0]),
.B1(n5062), .Y(n5045) );
AOI22X1TS U6720 ( .A0(n5064), .A1(FPSENCOS_d_ff3_sh_x_out[0]), .B0(n5063),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n5044) );
AOI22X1TS U6721 ( .A0(Data_1[23]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[23]),
.B1(n5100), .Y(n5047) );
AOI22X1TS U6722 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[23]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n5046) );
AOI22X1TS U6723 ( .A0(Data_1[28]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[28]),
.B1(n5062), .Y(n5049) );
AOI22X1TS U6724 ( .A0(n5064), .A1(FPSENCOS_d_ff2_Y[28]), .B0(n5063), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n5048) );
BUFX3TS U6725 ( .A(n5052), .Y(n5110) );
INVX2TS U6726 ( .A(FPSENCOS_d_ff2_X[15]), .Y(n6418) );
BUFX3TS U6727 ( .A(n5053), .Y(n5106) );
AOI22X1TS U6728 ( .A0(Data_1[15]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[15]),
.B1(n5100), .Y(n5051) );
BUFX3TS U6729 ( .A(n6549), .Y(n5107) );
BUFX3TS U6730 ( .A(n4999), .Y(n5113) );
AOI22X1TS U6731 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[15]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n5050) );
BUFX3TS U6732 ( .A(n5052), .Y(n5116) );
INVX2TS U6733 ( .A(FPSENCOS_d_ff2_X[8]), .Y(n6407) );
BUFX3TS U6734 ( .A(n5053), .Y(n5112) );
BUFX3TS U6735 ( .A(n5103), .Y(n5111) );
AOI22X1TS U6736 ( .A0(Data_1[8]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[8]),
.B1(n5111), .Y(n5055) );
AOI22X1TS U6737 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[8]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n5054) );
INVX2TS U6738 ( .A(FPSENCOS_d_ff2_X[4]), .Y(n6402) );
AOI22X1TS U6739 ( .A0(Data_1[4]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[4]),
.B1(n5103), .Y(n5057) );
BUFX3TS U6740 ( .A(n4999), .Y(n6474) );
AOI22X1TS U6741 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[4]), .B0(n6474), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n5056) );
INVX2TS U6742 ( .A(FPSENCOS_d_ff2_X[9]), .Y(n6409) );
AOI22X1TS U6743 ( .A0(Data_1[9]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[9]),
.B1(n5111), .Y(n5059) );
AOI22X1TS U6744 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[9]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n5058) );
INVX2TS U6745 ( .A(FPSENCOS_d_ff2_X[18]), .Y(n6421) );
AOI22X1TS U6746 ( .A0(Data_1[18]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[18]),
.B1(n5100), .Y(n5061) );
AOI22X1TS U6747 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[18]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n5060) );
INVX2TS U6748 ( .A(FPSENCOS_d_ff2_X[31]), .Y(n6441) );
AOI22X1TS U6749 ( .A0(Data_1[31]), .A1(n4996), .B0(FPADDSUB_intDX_EWSW[31]),
.B1(n5062), .Y(n5066) );
AOI22X1TS U6750 ( .A0(n5064), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n5063), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n5065) );
INVX2TS U6751 ( .A(FPSENCOS_d_ff2_X[0]), .Y(n6396) );
AOI22X1TS U6752 ( .A0(n5112), .A1(Data_1[0]), .B0(FPADDSUB_intDX_EWSW[0]),
.B1(n5103), .Y(n5069) );
AOI22X1TS U6753 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[0]), .B0(
FPSENCOS_d_ff2_Z[0]), .B1(n6474), .Y(n5068) );
INVX2TS U6754 ( .A(FPSENCOS_d_ff2_X[21]), .Y(n6426) );
AOI22X1TS U6755 ( .A0(Data_1[21]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[21]),
.B1(n5100), .Y(n5071) );
AOI22X1TS U6756 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[21]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n5070) );
INVX2TS U6757 ( .A(FPSENCOS_d_ff2_X[11]), .Y(n6410) );
AOI22X1TS U6758 ( .A0(Data_1[11]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[11]),
.B1(n5111), .Y(n5073) );
AOI22X1TS U6759 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[11]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n5072) );
AOI22X1TS U6760 ( .A0(Data_1[22]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[22]),
.B1(n5100), .Y(n5075) );
AOI22X1TS U6761 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[22]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n5074) );
INVX2TS U6762 ( .A(FPSENCOS_d_ff2_X[5]), .Y(n6404) );
AOI22X1TS U6763 ( .A0(Data_1[5]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[5]),
.B1(n5111), .Y(n5077) );
BUFX3TS U6764 ( .A(n6549), .Y(n6485) );
AOI22X1TS U6765 ( .A0(n6485), .A1(FPSENCOS_d_ff2_Y[5]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n5076) );
AOI22X1TS U6766 ( .A0(Data_1[14]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[14]),
.B1(n5111), .Y(n5079) );
AOI22X1TS U6767 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[14]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n5078) );
INVX2TS U6768 ( .A(FPSENCOS_d_ff2_X[3]), .Y(n6401) );
AOI22X1TS U6769 ( .A0(Data_1[3]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[3]),
.B1(n5103), .Y(n5081) );
AOI22X1TS U6770 ( .A0(n6485), .A1(FPSENCOS_d_ff2_Y[3]), .B0(n6474), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n5080) );
INVX2TS U6771 ( .A(FPSENCOS_d_ff2_X[2]), .Y(n6399) );
AOI22X1TS U6772 ( .A0(Data_1[2]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[2]),
.B1(n5103), .Y(n5083) );
AOI22X1TS U6773 ( .A0(n6485), .A1(FPSENCOS_d_ff2_Y[2]), .B0(n6474), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n5082) );
AOI22X1TS U6774 ( .A0(Data_1[20]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[20]),
.B1(n5100), .Y(n5086) );
AOI22X1TS U6775 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[20]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n5085) );
AOI22X1TS U6776 ( .A0(Data_1[10]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[10]),
.B1(n5111), .Y(n5089) );
AOI22X1TS U6777 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[10]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n5088) );
INVX2TS U6778 ( .A(FPSENCOS_d_ff2_X[19]), .Y(n6423) );
AOI22X1TS U6779 ( .A0(Data_1[19]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[19]),
.B1(n5100), .Y(n5091) );
AOI22X1TS U6780 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[19]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n5090) );
AOI22X1TS U6781 ( .A0(Data_1[6]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[6]),
.B1(n5111), .Y(n5093) );
AOI22X1TS U6782 ( .A0(n6485), .A1(FPSENCOS_d_ff2_Y[6]), .B0(n6474), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n5092) );
INVX2TS U6783 ( .A(FPSENCOS_d_ff2_X[17]), .Y(n6420) );
AOI22X1TS U6784 ( .A0(Data_1[17]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[17]),
.B1(n5100), .Y(n5096) );
AOI22X1TS U6785 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[17]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n5095) );
INVX2TS U6786 ( .A(FPSENCOS_d_ff2_X[12]), .Y(n6412) );
AOI22X1TS U6787 ( .A0(Data_1[12]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[12]),
.B1(n5111), .Y(n5099) );
AOI22X1TS U6788 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[12]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n5098) );
AOI22X1TS U6789 ( .A0(Data_1[16]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[16]),
.B1(n5100), .Y(n5102) );
AOI22X1TS U6790 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[16]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n5101) );
INVX2TS U6791 ( .A(FPSENCOS_d_ff2_X[1]), .Y(n6398) );
AOI22X1TS U6792 ( .A0(Data_1[1]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[1]),
.B1(n5103), .Y(n5105) );
AOI22X1TS U6793 ( .A0(n6485), .A1(FPSENCOS_d_ff2_Y[1]), .B0(n6474), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n5104) );
AOI22X1TS U6794 ( .A0(Data_1[13]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[13]),
.B1(n5111), .Y(n5109) );
AOI22X1TS U6795 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[13]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n5108) );
INVX2TS U6796 ( .A(FPSENCOS_d_ff2_X[7]), .Y(n6406) );
AOI22X1TS U6797 ( .A0(Data_1[7]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[7]),
.B1(n5111), .Y(n5115) );
AOI22X1TS U6798 ( .A0(n6485), .A1(FPSENCOS_d_ff2_Y[7]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n5114) );
INVX2TS U6799 ( .A(n5117), .Y(n1725) );
BUFX3TS U6800 ( .A(n6562), .Y(n5141) );
INVX2TS U6801 ( .A(n5119), .Y(n1716) );
BUFX3TS U6802 ( .A(n6562), .Y(n5167) );
INVX2TS U6803 ( .A(n5120), .Y(n1712) );
INVX2TS U6804 ( .A(n5121), .Y(n1726) );
INVX2TS U6805 ( .A(n5122), .Y(n1709) );
INVX2TS U6806 ( .A(n5123), .Y(n1718) );
INVX2TS U6807 ( .A(n5124), .Y(n1723) );
INVX2TS U6808 ( .A(n5125), .Y(n1721) );
INVX2TS U6809 ( .A(n5126), .Y(n1714) );
INVX2TS U6810 ( .A(n5127), .Y(n1715) );
INVX2TS U6811 ( .A(n5128), .Y(n1719) );
INVX2TS U6812 ( .A(n5129), .Y(n1724) );
INVX2TS U6813 ( .A(n5130), .Y(n1711) );
INVX2TS U6814 ( .A(n5131), .Y(n1722) );
INVX2TS U6815 ( .A(n5132), .Y(n1713) );
INVX2TS U6816 ( .A(n5133), .Y(n1707) );
INVX2TS U6817 ( .A(n5134), .Y(n1708) );
INVX2TS U6818 ( .A(n5135), .Y(n1720) );
INVX2TS U6819 ( .A(n5138), .Y(n1710) );
INVX2TS U6820 ( .A(n5142), .Y(n1717) );
INVX2TS U6821 ( .A(n6354), .Y(n7060) );
OAI22X1TS U6822 ( .A0(n2381), .A1(n5534), .B0(n2304), .B1(n5536), .Y(n5146)
);
NOR2X1TS U6823 ( .A(n5152), .B(n5487), .Y(n5479) );
CMPR32X2TS U6824 ( .A(n5147), .B(n5146), .C(DP_OP_502J223_128_4510_n100),
.CO(n5154), .S(n5149) );
NOR2X1TS U6825 ( .A(n2304), .B(n5534), .Y(n5153) );
NAND2X1TS U6826 ( .A(n5479), .B(n5484), .Y(n5157) );
INVX2TS U6827 ( .A(n5148), .Y(n5488) );
NAND2X1TS U6828 ( .A(DP_OP_502J223_128_4510_n101), .B(n5149), .Y(n5493) );
INVX2TS U6829 ( .A(n5493), .Y(n5150) );
AOI21X1TS U6830 ( .A0(n5488), .A1(n5494), .B0(n5150), .Y(n5151) );
OAI21X1TS U6831 ( .A0(n5152), .A1(n5497), .B0(n5151), .Y(n5480) );
NAND2X1TS U6832 ( .A(n5154), .B(n5153), .Y(n5483) );
INVX2TS U6833 ( .A(n5483), .Y(n5155) );
AOI21X1TS U6834 ( .A0(n5480), .A1(n5484), .B0(n5155), .Y(n5156) );
INVX2TS U6835 ( .A(n5159), .Y(n1698) );
INVX2TS U6836 ( .A(n5160), .Y(n1703) );
INVX2TS U6837 ( .A(n5161), .Y(n1701) );
INVX2TS U6838 ( .A(n5162), .Y(n1702) );
INVX2TS U6839 ( .A(n5163), .Y(n1699) );
INVX2TS U6840 ( .A(n5164), .Y(n1697) );
INVX2TS U6841 ( .A(n5165), .Y(n1700) );
INVX2TS U6842 ( .A(n5166), .Y(n1704) );
INVX2TS U6843 ( .A(n5168), .Y(n1706) );
INVX2TS U6844 ( .A(n5170), .Y(n1705) );
NOR2X1TS U6845 ( .A(n5608), .B(n5612), .Y(n5173) );
OAI22X1TS U6846 ( .A0(n2376), .A1(n5615), .B0(n5180), .B1(n5613), .Y(n5172)
);
NOR2X2TS U6847 ( .A(DP_OP_500J223_126_4510_n110), .B(
DP_OP_500J223_126_4510_n116), .Y(n5575) );
NOR2X2TS U6848 ( .A(DP_OP_500J223_126_4510_n117), .B(
DP_OP_500J223_126_4510_n122), .Y(n5580) );
NOR2X1TS U6849 ( .A(n5575), .B(n5580), .Y(n5189) );
ADDHXLTS U6850 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[19]), .CO(n4304), .S(
n5171) );
INVX2TS U6851 ( .A(n5171), .Y(n5618) );
OAI22X1TS U6852 ( .A0(n2310), .A1(n5618), .B0(n2376), .B1(n5616), .Y(n5176)
);
ADDHX1TS U6853 ( .A(n5173), .B(n5172), .CO(DP_OP_500J223_126_4510_n141), .S(
n5175) );
NOR2X1TS U6854 ( .A(n5180), .B(n5615), .Y(n5179) );
OAI22X1TS U6855 ( .A0(n5614), .A1(n5618), .B0(n5608), .B1(n5616), .Y(n5178)
);
NOR2X1TS U6856 ( .A(DP_OP_500J223_126_4510_n136), .B(n5186), .Y(n5594) );
CMPR32X2TS U6857 ( .A(n5176), .B(n5175), .C(n5174), .CO(n5186), .S(n5185) );
ADDHXLTS U6858 ( .A(FPMULT_Op_MX[12]), .B(n5640), .CO(n5177), .S(n4573) );
INVX2TS U6859 ( .A(n5177), .Y(n5620) );
OAI22X1TS U6860 ( .A0(n5621), .A1(n5622), .B0(n5617), .B1(n5620), .Y(n5184)
);
NOR2X2TS U6861 ( .A(n5185), .B(n5184), .Y(n5599) );
ADDHX1TS U6862 ( .A(n5179), .B(n5178), .CO(n5174), .S(n5182) );
OAI22X1TS U6863 ( .A0(n2310), .A1(n5622), .B0(n2376), .B1(n5620), .Y(n5181)
);
OAI22X1TS U6864 ( .A0(n2376), .A1(n5622), .B0(n5180), .B1(n5620), .Y(n5469)
);
NOR2X1TS U6865 ( .A(n5608), .B(n5618), .Y(n5468) );
NAND2X1TS U6866 ( .A(n5469), .B(n5468), .Y(n5470) );
INVX2TS U6867 ( .A(n5470), .Y(n5606) );
NAND2X1TS U6868 ( .A(n5182), .B(n5181), .Y(n5604) );
INVX2TS U6869 ( .A(n5604), .Y(n5183) );
AOI21X1TS U6870 ( .A0(n5605), .A1(n5606), .B0(n5183), .Y(n5602) );
NAND2X1TS U6871 ( .A(n5185), .B(n5184), .Y(n5600) );
NAND2X1TS U6872 ( .A(DP_OP_500J223_126_4510_n136), .B(n5186), .Y(n5595) );
NAND2X1TS U6873 ( .A(DP_OP_500J223_126_4510_n129), .B(
DP_OP_500J223_126_4510_n135), .Y(n5590) );
INVX2TS U6874 ( .A(n5590), .Y(n5187) );
AOI21X2TS U6875 ( .A0(n5592), .A1(n5591), .B0(n5187), .Y(n5588) );
NAND2X1TS U6876 ( .A(DP_OP_500J223_126_4510_n123), .B(
DP_OP_500J223_126_4510_n128), .Y(n5586) );
OAI21X2TS U6877 ( .A0(n5588), .A1(n5585), .B0(n5586), .Y(n5574) );
NAND2X2TS U6878 ( .A(DP_OP_500J223_126_4510_n117), .B(
DP_OP_500J223_126_4510_n122), .Y(n5581) );
NAND2X1TS U6879 ( .A(DP_OP_500J223_126_4510_n110), .B(
DP_OP_500J223_126_4510_n116), .Y(n5576) );
OAI21X1TS U6880 ( .A0(n5575), .A1(n5581), .B0(n5576), .Y(n5188) );
AOI21X4TS U6881 ( .A0(n5189), .A1(n5574), .B0(n5188), .Y(n5573) );
OR2X2TS U6882 ( .A(DP_OP_500J223_126_4510_n102), .B(
DP_OP_500J223_126_4510_n104), .Y(n5567) );
OAI22X1TS U6883 ( .A0(n5619), .A1(n2405), .B0(n2306), .B1(FPMULT_Op_MX[17]),
.Y(n5190) );
NOR2X2TS U6884 ( .A(DP_OP_500J223_126_4510_n109), .B(
DP_OP_500J223_126_4510_n105), .Y(n5565) );
NOR2X1TS U6885 ( .A(n5195), .B(n5565), .Y(n5550) );
CMPR32X2TS U6886 ( .A(n5191), .B(n5190), .C(DP_OP_500J223_126_4510_n100),
.CO(n5197), .S(n5192) );
NOR2X1TS U6887 ( .A(n2306), .B(n2405), .Y(n5196) );
NAND2X2TS U6888 ( .A(DP_OP_500J223_126_4510_n109), .B(
DP_OP_500J223_126_4510_n105), .Y(n5570) );
NAND2X1TS U6889 ( .A(DP_OP_500J223_126_4510_n102), .B(
DP_OP_500J223_126_4510_n104), .Y(n5566) );
INVX2TS U6890 ( .A(n5566), .Y(n5558) );
NAND2X1TS U6891 ( .A(DP_OP_500J223_126_4510_n101), .B(n5192), .Y(n5562) );
INVX2TS U6892 ( .A(n5562), .Y(n5193) );
AOI21X1TS U6893 ( .A0(n5558), .A1(n2487), .B0(n5193), .Y(n5194) );
OAI21X1TS U6894 ( .A0(n5195), .A1(n5570), .B0(n5194), .Y(n5551) );
NAND2X1TS U6895 ( .A(n5197), .B(n5196), .Y(n5554) );
INVX2TS U6896 ( .A(n5554), .Y(n5198) );
AOI21X1TS U6897 ( .A0(n5551), .A1(n5555), .B0(n5198), .Y(n5199) );
NAND2X1TS U6898 ( .A(n5330), .B(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n5203) );
NAND2X1TS U6899 ( .A(n2360), .B(FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n5202) );
NAND2X1TS U6900 ( .A(n5326), .B(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n5201) );
AOI21X1TS U6901 ( .A0(n6801), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n5204) );
AOI22X1TS U6902 ( .A0(n5225), .A1(n5211), .B0(FPADDSUB_Raw_mant_NRM_SWR[6]),
.B1(n5210), .Y(n5212) );
OAI32X4TS U6903 ( .A0(n6016), .A1(n2340), .A2(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .B0(n2336), .B1(n6016), .Y(n5386)
);
INVX2TS U6904 ( .A(n5215), .Y(n5216) );
OAI211X1TS U6905 ( .A0(n5218), .A1(n5217), .B0(n6713), .C0(n5216), .Y(n5229)
);
INVX2TS U6906 ( .A(n5219), .Y(n5227) );
AOI22X1TS U6907 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[14]), .A1(n5225), .B0(n5224),
.B1(n5223), .Y(n5226) );
OAI31X1TS U6908 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n6752), .A2(n5227),
.B0(n5226), .Y(n5228) );
AOI211X2TS U6909 ( .A0(n5231), .A1(n5230), .B0(n5229), .C0(n5228), .Y(n6015)
);
INVX2TS U6910 ( .A(n5265), .Y(n5394) );
OR2X2TS U6911 ( .A(n5235), .B(n5394), .Y(n6521) );
OA22X1TS U6912 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[25]), .A1(n5450), .B0(n5238),
.B1(FPADDSUB_Raw_mant_NRM_SWR[0]), .Y(n5395) );
AOI22X1TS U6913 ( .A0(n5394), .A1(FPADDSUB_Data_array_SWR[24]), .B0(n2348),
.B1(n5395), .Y(n5233) );
NAND2X2TS U6914 ( .A(n5235), .B(n5265), .Y(n5392) );
INVX2TS U6915 ( .A(n5238), .Y(n5325) );
NAND2X1TS U6916 ( .A(n5325), .B(n6780), .Y(n5241) );
NAND2X1TS U6917 ( .A(n2359), .B(n6869), .Y(n5240) );
OR2X1TS U6918 ( .A(n6713), .B(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n5239) );
NAND3X1TS U6919 ( .A(n5241), .B(n5240), .C(n5239), .Y(n5365) );
INVX2TS U6920 ( .A(n5365), .Y(n5319) );
AOI22X1TS U6921 ( .A0(n5394), .A1(FPADDSUB_Data_array_SWR[18]), .B0(n2351),
.B1(n5319), .Y(n5245) );
OAI22X1TS U6922 ( .A0(n5450), .A1(FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(
FPADDSUB_Shift_reg_FLAGS_7[1]), .B1(FPADDSUB_DmP_mant_SHT1_SW[17]),
.Y(n5242) );
MXI2X1TS U6923 ( .A(FPADDSUB_DmP_mant_SHT1_SW[19]), .B(
FPADDSUB_Raw_mant_NRM_SWR[21]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]),
.Y(n5243) );
AOI22X1TS U6924 ( .A0(n2206), .A1(n5361), .B0(n2354), .B1(n5362), .Y(n5244)
);
NAND2X1TS U6925 ( .A(n5325), .B(n6868), .Y(n5248) );
NAND2X1TS U6926 ( .A(n5387), .B(n6821), .Y(n5247) );
NAND2X1TS U6927 ( .A(n5325), .B(n6758), .Y(n5251) );
NAND2X1TS U6928 ( .A(n2360), .B(n6795), .Y(n5250) );
OR2X1TS U6929 ( .A(n5340), .B(FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n5249) );
NAND3X1TS U6930 ( .A(n5251), .B(n5250), .C(n5249), .Y(n5353) );
INVX2TS U6931 ( .A(n5353), .Y(n5262) );
AOI22X1TS U6932 ( .A0(n5379), .A1(FPADDSUB_Data_array_SWR[6]), .B0(n2352),
.B1(n5262), .Y(n5257) );
NAND2X1TS U6933 ( .A(n2360), .B(n6819), .Y(n5254) );
NAND2X1TS U6934 ( .A(n5330), .B(n2256), .Y(n5253) );
OAI22X1TS U6935 ( .A0(n6713), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n5450), .Y(n5255) );
AOI22X1TS U6936 ( .A0(n2348), .A1(n5355), .B0(n2354), .B1(n5350), .Y(n5256)
);
NAND2X1TS U6937 ( .A(n5387), .B(FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n5260) );
NAND2X1TS U6938 ( .A(n5330), .B(FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n5259) );
NAND2X1TS U6939 ( .A(n5326), .B(FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n5258) );
INVX2TS U6940 ( .A(n5261), .Y(n5354) );
AOI22X1TS U6941 ( .A0(n5379), .A1(FPADDSUB_Data_array_SWR[5]), .B0(n2348),
.B1(n5354), .Y(n5264) );
AOI22X1TS U6942 ( .A0(n2354), .A1(n5262), .B0(n2351), .B1(n5355), .Y(n5263)
);
OAI22X1TS U6943 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n2336), .B0(n2340),
.B1(FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n5266) );
AOI22X1TS U6944 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[8]), .B0(n2353),
.B1(n5358), .Y(n5268) );
AOI222X4TS U6945 ( .A0(n6814), .A1(n7059), .B0(n7063), .B1(n5325), .C0(n6752), .C1(n2360), .Y(n5371) );
AOI22X1TS U6946 ( .A0(n5232), .A1(n5350), .B0(n2355), .B1(n5371), .Y(n5267)
);
AOI222X4TS U6947 ( .A0(n6815), .A1(n2341), .B0(n6752), .B1(n5330), .C0(n7063), .C1(n5387), .Y(n5374) );
AOI22X1TS U6948 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n2206),
.B1(n5374), .Y(n5272) );
OAI22X1TS U6949 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n5238), .B0(n2340),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n5269) );
OAI22X1TS U6950 ( .A0(n6713), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[15]), .B1(n5450), .Y(n5270) );
AOI22X1TS U6951 ( .A0(n2354), .A1(n5366), .B0(n2351), .B1(n5367), .Y(n5271)
);
NAND2X1TS U6952 ( .A(n5387), .B(n6853), .Y(n5275) );
NAND2X1TS U6953 ( .A(n5326), .B(n6854), .Y(n5274) );
AOI22X1TS U6954 ( .A0(n5394), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n5396),
.B1(n2353), .Y(n5281) );
NAND2X1TS U6955 ( .A(n5325), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n5279) );
NAND2X1TS U6956 ( .A(n2359), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n5278) );
NAND2X1TS U6957 ( .A(n5326), .B(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n5277) );
NAND3X1TS U6958 ( .A(n5279), .B(n5278), .C(n5277), .Y(n5388) );
AOI22X1TS U6959 ( .A0(n2206), .A1(n5362), .B0(n2355), .B1(n5388), .Y(n5280)
);
OAI222X4TS U6960 ( .A0(n5238), .A1(FPADDSUB_Raw_mant_NRM_SWR[13]), .B0(n5450), .B1(FPADDSUB_Raw_mant_NRM_SWR[12]), .C0(FPADDSUB_DmP_mant_SHT1_SW[10]), .C1(
n6713), .Y(n5377) );
INVX2TS U6961 ( .A(n5282), .Y(n5373) );
AOI22X1TS U6962 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n2206),
.B1(n5373), .Y(n5284) );
AOI22X1TS U6963 ( .A0(n2355), .A1(n5367), .B0(n2352), .B1(n5374), .Y(n5283)
);
AOI22X1TS U6964 ( .A0(FPADDSUB_intDX_EWSW[4]), .A1(n5313), .B0(
FPADDSUB_DMP_EXP_EWSW[4]), .B1(n6714), .Y(n5285) );
BUFX3TS U6965 ( .A(n6714), .Y(n5405) );
AOI22X1TS U6966 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[4]), .B1(n5405), .Y(n5286) );
AOI22X1TS U6967 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n5291), .B0(
FPADDSUB_DmP_EXP_EWSW[15]), .B1(n5405), .Y(n5287) );
AOI22X1TS U6968 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n5291), .B0(
FPADDSUB_DmP_EXP_EWSW[18]), .B1(n5405), .Y(n5288) );
AOI22X1TS U6969 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n5291), .B0(
FPADDSUB_DmP_EXP_EWSW[27]), .B1(n5405), .Y(n5289) );
AOI22X1TS U6970 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n5291), .B0(
FPADDSUB_DmP_EXP_EWSW[22]), .B1(n5405), .Y(n5290) );
AOI22X1TS U6971 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n5291), .B0(
FPADDSUB_DmP_EXP_EWSW[21]), .B1(n5405), .Y(n5292) );
AOI22X1TS U6972 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[3]), .B1(n5418), .Y(n5293) );
AOI22X1TS U6973 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[1]), .B1(n6829), .Y(n5294) );
AOI22X1TS U6974 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[0]), .B1(n6829), .Y(n5295) );
AOI22X1TS U6975 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[8]), .B1(n5418), .Y(n5296) );
AOI22X1TS U6976 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[17]), .B1(n5405), .Y(n5297) );
AOI22X1TS U6977 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[11]), .B1(n5418), .Y(n5298) );
AOI22X1TS U6978 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[9]), .B1(n5422), .Y(n5299) );
AOI22X1TS U6979 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[12]), .B1(n5427), .Y(n5300) );
AOI22X1TS U6980 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[13]), .B1(n5418), .Y(n5301) );
AOI22X1TS U6981 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[16]), .B1(n5418), .Y(n5302) );
AOI22X1TS U6982 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[6]), .B1(n5405), .Y(n5303) );
AOI22X1TS U6983 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[10]), .B1(n5418), .Y(n5304) );
AOI22X1TS U6984 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[20]), .B1(n5405), .Y(n5305) );
AOI22X1TS U6985 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[14]), .B1(n5418), .Y(n5306) );
AOI22X1TS U6986 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[2]), .B1(n5422), .Y(n5307) );
AOI22X1TS U6987 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[19]), .B1(n5418), .Y(n5309) );
AOI22X1TS U6988 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[7]), .B1(n5422), .Y(n5311) );
AOI22X1TS U6989 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[5]), .B1(n6714), .Y(n5314) );
AOI22X1TS U6990 ( .A0(n5394), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n2353),
.B1(n5361), .Y(n5321) );
NAND2X1TS U6991 ( .A(n5330), .B(n6795), .Y(n5318) );
NAND2X1TS U6992 ( .A(n2360), .B(n6758), .Y(n5317) );
INVX2TS U6993 ( .A(n5370), .Y(n5346) );
AOI22X1TS U6994 ( .A0(n2338), .A1(n5346), .B0(n2354), .B1(n5319), .Y(n5320)
);
NAND2X1TS U6995 ( .A(n2360), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n5324) );
NAND2X1TS U6996 ( .A(n5330), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n5323) );
AOI22X1TS U6997 ( .A0(n5325), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n5379),
.B1(FPADDSUB_Data_array_SWR[0]), .Y(n5332) );
NAND2X1TS U6998 ( .A(n5387), .B(n6796), .Y(n5329) );
NAND2X1TS U6999 ( .A(n5325), .B(n6853), .Y(n5328) );
NAND2X1TS U7000 ( .A(n5326), .B(n6855), .Y(n5327) );
OAI2BB2X1TS U7001 ( .B0(n5450), .B1(n6793), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[24]), .A1N(n5330), .Y(n5339) );
AOI21X1TS U7002 ( .A0(n2354), .A1(n5382), .B0(n5339), .Y(n5331) );
AOI22X1TS U7003 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n2206),
.B1(n5346), .Y(n5334) );
AOI22X1TS U7004 ( .A0(n2338), .A1(n5366), .B0(n2354), .B1(n5361), .Y(n5333)
);
INVX2TS U7005 ( .A(n2354), .Y(n5381) );
AOI22X1TS U7006 ( .A0(n5394), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n2351),
.B1(n5388), .Y(n5336) );
AOI22X1TS U7007 ( .A0(n2338), .A1(n5362), .B0(n2348), .B1(n5396), .Y(n5335)
);
AOI22X1TS U7008 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[9]), .B0(n2353),
.B1(n5371), .Y(n5338) );
AOI22X1TS U7009 ( .A0(n2339), .A1(n5350), .B0(n2206), .B1(n5358), .Y(n5337)
);
AOI22X1TS U7010 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[1]), .B0(n2339),
.B1(n5339), .Y(n5343) );
OAI22X1TS U7011 ( .A0(n2336), .A1(FPADDSUB_Raw_mant_NRM_SWR[21]), .B0(n5340),
.B1(FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n5341) );
AOI22X1TS U7012 ( .A0(n2355), .A1(n5378), .B0(n2351), .B1(n5382), .Y(n5342)
);
AOI22X1TS U7013 ( .A0(n5379), .A1(FPADDSUB_Data_array_SWR[3]), .B0(n2339),
.B1(n5382), .Y(n5345) );
AOI22X1TS U7014 ( .A0(n2348), .A1(n5378), .B0(n2355), .B1(n5354), .Y(n5344)
);
AOI22X1TS U7015 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[15]), .B0(n2338),
.B1(n5367), .Y(n5348) );
AOI22X1TS U7016 ( .A0(n2206), .A1(n5366), .B0(n2351), .B1(n5346), .Y(n5347)
);
AOI22X1TS U7017 ( .A0(n5379), .A1(FPADDSUB_Data_array_SWR[7]), .B0(n2339),
.B1(n5355), .Y(n5352) );
AOI22X1TS U7018 ( .A0(n2355), .A1(n5358), .B0(n2352), .B1(n5350), .Y(n5351)
);
AOI22X1TS U7019 ( .A0(n5379), .A1(FPADDSUB_Data_array_SWR[4]), .B0(n2338),
.B1(n5378), .Y(n5357) );
AOI22X1TS U7020 ( .A0(n2355), .A1(n5355), .B0(n2353), .B1(n5354), .Y(n5356)
);
AOI22X1TS U7021 ( .A0(n2206), .A1(n5371), .B0(n2355), .B1(n5373), .Y(n5359)
);
AOI22X1TS U7022 ( .A0(n5394), .A1(FPADDSUB_Data_array_SWR[19]), .B0(n2338),
.B1(n5361), .Y(n5364) );
AOI22X1TS U7023 ( .A0(n2354), .A1(n5396), .B0(n2353), .B1(n5362), .Y(n5363)
);
AOI22X1TS U7024 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n2339),
.B1(n5374), .Y(n5369) );
AOI22X1TS U7025 ( .A0(n2206), .A1(n5367), .B0(n2351), .B1(n5366), .Y(n5368)
);
AOI22X1TS U7026 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n2339),
.B1(n5371), .Y(n5376) );
AOI22X1TS U7027 ( .A0(n2355), .A1(n5374), .B0(n2352), .B1(n5373), .Y(n5375)
);
AOI22X1TS U7028 ( .A0(n5379), .A1(FPADDSUB_Data_array_SWR[2]), .B0(n2352),
.B1(n5378), .Y(n5384) );
AOI2BB2X1TS U7029 ( .B0(n2206), .B1(n5382), .A0N(n5381), .A1N(n5380), .Y(
n5383) );
OAI211X1TS U7030 ( .A0(n5385), .A1(n5389), .B0(n5384), .C0(n5383), .Y(n1789)
);
INVX2TS U7031 ( .A(n5388), .Y(n5400) );
OAI22X1TS U7032 ( .A0(n5400), .A1(n5389), .B0(n5393), .B1(n5399), .Y(n5390)
);
AOI21X1TS U7033 ( .A0(n5394), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n5390),
.Y(n5391) );
OAI21X1TS U7034 ( .A0(n6522), .A1(n5392), .B0(n5391), .Y(n1810) );
AOI2BB2X1TS U7035 ( .B0(n5394), .B1(FPADDSUB_Data_array_SWR[22]), .A0N(n5237), .A1N(n5393), .Y(n5398) );
AOI22X1TS U7036 ( .A0(n2339), .A1(n5396), .B0(n2354), .B1(n5395), .Y(n5397)
);
AOI22X1TS U7037 ( .A0(FPADDSUB_intDY_EWSW[29]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[29]), .B1(n6668), .Y(n5401) );
AOI22X1TS U7038 ( .A0(FPADDSUB_intDY_EWSW[30]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[30]), .B1(n6668), .Y(n5402) );
AOI22X1TS U7039 ( .A0(FPADDSUB_intDY_EWSW[26]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[26]), .B1(n6668), .Y(n5403) );
AOI22X1TS U7040 ( .A0(FPADDSUB_intDY_EWSW[25]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[25]), .B1(n6668), .Y(n5404) );
AOI22X1TS U7041 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[28]), .B1(n5405), .Y(n5406) );
AOI22X1TS U7042 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[3]), .B1(n5422), .Y(n5407) );
AOI22X1TS U7043 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[0]), .B1(n5422), .Y(n5408) );
BUFX3TS U7044 ( .A(n2577), .Y(n5436) );
AOI22X1TS U7045 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[15]), .B1(n5427), .Y(n5409) );
AOI22X1TS U7046 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[1]), .B1(n5427), .Y(n5410) );
AOI22X1TS U7047 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[18]), .B1(n5427), .Y(n5411) );
AOI22X1TS U7048 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[8]), .B1(n6708), .Y(n5412) );
AOI22X1TS U7049 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[11]), .B1(n6714), .Y(n5413) );
AOI22X1TS U7050 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[17]), .B1(n5422), .Y(n5414) );
AOI22X1TS U7051 ( .A0(FPADDSUB_intDY_EWSW[24]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[24]), .B1(n6668), .Y(n5415) );
AOI22X1TS U7052 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[27]), .B1(n6668), .Y(n5416) );
AOI22X1TS U7053 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[9]), .B1(n6708), .Y(n5417) );
AOI22X1TS U7054 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[22]), .B1(n5418), .Y(n5419) );
AOI22X1TS U7055 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[12]), .B1(n5427), .Y(n5420) );
AOI22X1TS U7056 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[21]), .B1(n5427), .Y(n5421) );
AOI22X1TS U7057 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[13]), .B1(n5422), .Y(n5423) );
AOI22X1TS U7058 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[2]), .B1(n5422), .Y(n5425) );
AOI22X1TS U7059 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[20]), .B1(n5427), .Y(n5428) );
AOI22X1TS U7060 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[14]), .B1(n5427), .Y(n5429) );
AOI22X1TS U7061 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n4321), .B0(
FPADDSUB_DMP_EXP_EWSW[10]), .B1(n6714), .Y(n5430) );
AOI22X1TS U7062 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[6]), .B1(n6829), .Y(n5431) );
AOI22X1TS U7063 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[16]), .B1(n6714), .Y(n5432) );
AOI22X1TS U7064 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[19]), .B1(n6829), .Y(n5435) );
NOR2X1TS U7065 ( .A(n2305), .B(n5611), .Y(DP_OP_500J223_126_4510_n161) );
NAND2X1TS U7066 ( .A(n5750), .B(n6770), .Y(n5437) );
NAND2X1TS U7067 ( .A(FPMULT_Op_MX[6]), .B(n5644), .Y(n5778) );
NOR2X1TS U7068 ( .A(n5437), .B(n5778), .Y(n5758) );
NOR2X1TS U7069 ( .A(n6794), .B(n6770), .Y(n5472) );
INVX2TS U7070 ( .A(n5472), .Y(n5779) );
NOR2X1TS U7071 ( .A(n5779), .B(n5778), .Y(n5777) );
NOR2X1TS U7072 ( .A(n2305), .B(n5620), .Y(DP_OP_500J223_126_4510_n185) );
INVX2TS U7073 ( .A(n5440), .Y(n5438) );
NAND2X1TS U7074 ( .A(n5439), .B(n5438), .Y(n5441) );
NOR2X2TS U7075 ( .A(n5444), .B(n5443), .Y(n5659) );
XNOR2X1TS U7076 ( .A(n5446), .B(n5445), .Y(n5447) );
XNOR2X1TS U7077 ( .A(n5448), .B(n5447), .Y(n5661) );
OAI21X1TS U7078 ( .A0(n5660), .A1(n5659), .B0(n5449), .Y(mult_x_309_n17) );
AND3X2TS U7079 ( .A(n6756), .B(FPSENCOS_cont_var_out[1]), .C(ready_add_subt),
.Y(n6386) );
INVX2TS U7080 ( .A(n6386), .Y(n6538) );
NOR2XLTS U7081 ( .A(n6347), .B(n6538), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
OAI21XLTS U7082 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n6766), .B0(n5450),
.Y(n1350) );
OAI222X1TS U7083 ( .A0(n6787), .A1(n5455), .B0(n5454), .B1(n5453), .C0(n5452), .C1(n5451), .Y(n1691) );
AOI21X1TS U7084 ( .A0(ack_operation), .A1(n5457), .B0(n5456), .Y(n6566) );
AOI21X1TS U7085 ( .A0(FPMULT_zero_flag), .A1(n2382), .B0(n6566), .Y(n5459)
);
NOR3X1TS U7086 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .C(n6772), .Y(n6352) );
AOI31XLTS U7087 ( .A0(n5461), .A1(n6351), .A2(n6850), .B0(n6352), .Y(n5462)
);
OAI21XLTS U7088 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
n6012), .B0(n5462), .Y(n2149) );
OAI21XLTS U7089 ( .A0(n5463), .A1(n6346), .B0(n6442), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
NAND2X1TS U7090 ( .A(n5472), .B(n7065), .Y(n5780) );
NAND2X1TS U7091 ( .A(FPMULT_Op_MX[6]), .B(n6584), .Y(n5757) );
CLKAND2X2TS U7092 ( .A(n5780), .B(n5473), .Y(n6870) );
NAND2X1TS U7093 ( .A(n5738), .B(n7066), .Y(n5739) );
NAND2X1TS U7094 ( .A(n5649), .B(FPMULT_Op_MX[12]), .Y(n5735) );
CLKAND2X2TS U7095 ( .A(n5739), .B(n5474), .Y(n6905) );
NAND2X1TS U7096 ( .A(n5841), .B(n7064), .Y(n5842) );
NAND2X1TS U7097 ( .A(n2220), .B(n6568), .Y(n5838) );
CLKAND2X2TS U7098 ( .A(n5842), .B(n5475), .Y(n6906) );
BUFX3TS U7099 ( .A(n6735), .Y(n6740) );
INVX2TS U7100 ( .A(n5479), .Y(n5482) );
INVX2TS U7101 ( .A(n5480), .Y(n5481) );
NAND2X1TS U7102 ( .A(n5484), .B(n5483), .Y(n5485) );
XNOR2X1TS U7103 ( .A(n5486), .B(n5485), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12) );
INVX2TS U7104 ( .A(n5487), .Y(n5498) );
NAND2X1TS U7105 ( .A(n5498), .B(n5489), .Y(n5492) );
INVX2TS U7106 ( .A(n5497), .Y(n5490) );
AOI21X1TS U7107 ( .A0(n5490), .A1(n5489), .B0(n5488), .Y(n5491) );
NAND2X1TS U7108 ( .A(n5494), .B(n5493), .Y(n5495) );
XNOR2X1TS U7109 ( .A(n5496), .B(n5495), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11) );
NAND2X1TS U7110 ( .A(n5498), .B(n5497), .Y(n5499) );
INVX2TS U7111 ( .A(n5501), .Y(n5510) );
INVX2TS U7112 ( .A(n5502), .Y(n5504) );
NAND2X1TS U7113 ( .A(n5504), .B(n5503), .Y(n5505) );
XNOR2X1TS U7114 ( .A(n5506), .B(n5505), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8) );
INVX2TS U7115 ( .A(n5507), .Y(n5509) );
NAND2X1TS U7116 ( .A(n5509), .B(n5508), .Y(n5511) );
INVX2TS U7117 ( .A(n5512), .Y(n5514) );
NAND2X1TS U7118 ( .A(n5514), .B(n5513), .Y(n5516) );
NAND2X1TS U7119 ( .A(n2472), .B(n5517), .Y(n5519) );
XNOR2X1TS U7120 ( .A(n5519), .B(n5518), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5) );
INVX2TS U7121 ( .A(n5520), .Y(n5522) );
NAND2X1TS U7122 ( .A(n5522), .B(n5521), .Y(n5524) );
INVX2TS U7123 ( .A(n5525), .Y(n5527) );
NAND2X1TS U7124 ( .A(n5527), .B(n5526), .Y(n5529) );
NAND2X1TS U7125 ( .A(n5531), .B(n5530), .Y(n5533) );
XNOR2X1TS U7126 ( .A(n5533), .B(n5532), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2) );
OAI22X1TS U7127 ( .A0(n5546), .A1(n5536), .B0(n2321), .B1(n5534), .Y(
DP_OP_502J223_128_4510_n147) );
OAI22X1TS U7128 ( .A0(n2314), .A1(n5536), .B0(n2377), .B1(n5534), .Y(
DP_OP_502J223_128_4510_n150) );
OAI22X1TS U7129 ( .A0(n2377), .A1(n5536), .B0(n5535), .B1(n5534), .Y(
DP_OP_502J223_128_4510_n151) );
OAI22X1TS U7130 ( .A0(n5546), .A1(n5537), .B0(n2303), .B1(n5538), .Y(
DP_OP_502J223_128_4510_n154) );
OAI22X1TS U7131 ( .A0(n5546), .A1(n5538), .B0(n2321), .B1(n5537), .Y(
DP_OP_502J223_128_4510_n155) );
OAI22X1TS U7132 ( .A0(n5548), .A1(n5538), .B0(n2314), .B1(n5537), .Y(
DP_OP_502J223_128_4510_n157) );
OAI22X1TS U7133 ( .A0(n2313), .A1(n5538), .B0(n2377), .B1(n5537), .Y(
DP_OP_502J223_128_4510_n158) );
OAI22X1TS U7134 ( .A0(n5546), .A1(n5539), .B0(n2304), .B1(n5540), .Y(
DP_OP_502J223_128_4510_n162) );
OAI22X1TS U7135 ( .A0(n2321), .A1(n5540), .B0(n2379), .B1(n5539), .Y(
DP_OP_502J223_128_4510_n164) );
OAI22X1TS U7136 ( .A0(n5548), .A1(n5540), .B0(n2314), .B1(n5539), .Y(
DP_OP_502J223_128_4510_n165) );
OAI22X1TS U7137 ( .A0(n2381), .A1(n5541), .B0(n2304), .B1(n5543), .Y(
DP_OP_502J223_128_4510_n170) );
OAI22X1TS U7138 ( .A0(n2381), .A1(n5543), .B0(n2321), .B1(n5541), .Y(
DP_OP_502J223_128_4510_n171) );
OAI22X1TS U7139 ( .A0(n2321), .A1(n5543), .B0(n2379), .B1(n5541), .Y(
DP_OP_502J223_128_4510_n172) );
OAI22X1TS U7140 ( .A0(n2313), .A1(n5543), .B0(n2377), .B1(n5541), .Y(
DP_OP_502J223_128_4510_n174) );
OAI22X1TS U7141 ( .A0(n5546), .A1(n5544), .B0(n2304), .B1(n5545), .Y(
DP_OP_502J223_128_4510_n178) );
OAI22X1TS U7142 ( .A0(n5546), .A1(n5545), .B0(n2320), .B1(n5544), .Y(
DP_OP_502J223_128_4510_n179) );
OAI22X1TS U7143 ( .A0(n5548), .A1(n5545), .B0(n2314), .B1(n5544), .Y(
DP_OP_502J223_128_4510_n181) );
OAI22X1TS U7144 ( .A0(n5546), .A1(n5547), .B0(n2303), .B1(n5549), .Y(
DP_OP_502J223_128_4510_n186) );
OAI22X1TS U7145 ( .A0(n5546), .A1(n5549), .B0(n2321), .B1(n5547), .Y(
DP_OP_502J223_128_4510_n187) );
OAI22X1TS U7146 ( .A0(n2320), .A1(n5549), .B0(n5548), .B1(n5547), .Y(
DP_OP_502J223_128_4510_n188) );
INVX2TS U7147 ( .A(n5550), .Y(n5553) );
INVX2TS U7148 ( .A(n5551), .Y(n5552) );
NAND2X1TS U7149 ( .A(n5555), .B(n5554), .Y(n5556) );
XNOR2X1TS U7150 ( .A(n5557), .B(n5556), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12) );
INVX2TS U7151 ( .A(n5565), .Y(n5571) );
NAND2X1TS U7152 ( .A(n5571), .B(n5567), .Y(n5561) );
INVX2TS U7153 ( .A(n5570), .Y(n5559) );
AOI21X1TS U7154 ( .A0(n5559), .A1(n5567), .B0(n5558), .Y(n5560) );
NAND2X1TS U7155 ( .A(n2487), .B(n5562), .Y(n5563) );
NAND2X1TS U7156 ( .A(n5567), .B(n5566), .Y(n5568) );
XNOR2X1TS U7157 ( .A(n5569), .B(n5568), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10) );
NAND2X1TS U7158 ( .A(n5571), .B(n5570), .Y(n5572) );
INVX2TS U7159 ( .A(n5574), .Y(n5583) );
INVX2TS U7160 ( .A(n5575), .Y(n5577) );
NAND2X1TS U7161 ( .A(n5577), .B(n5576), .Y(n5578) );
XNOR2X1TS U7162 ( .A(n5579), .B(n5578), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8) );
INVX2TS U7163 ( .A(n5580), .Y(n5582) );
NAND2X1TS U7164 ( .A(n5582), .B(n5581), .Y(n5584) );
INVX2TS U7165 ( .A(n5585), .Y(n5587) );
NAND2X1TS U7166 ( .A(n5587), .B(n5586), .Y(n5589) );
NAND2X1TS U7167 ( .A(n5591), .B(n5590), .Y(n5593) );
XNOR2X1TS U7168 ( .A(n5593), .B(n5592), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5) );
INVX2TS U7169 ( .A(n5594), .Y(n5596) );
NAND2X1TS U7170 ( .A(n5596), .B(n5595), .Y(n5598) );
INVX2TS U7171 ( .A(n5599), .Y(n5601) );
NAND2X1TS U7172 ( .A(n5601), .B(n5600), .Y(n5603) );
NAND2X1TS U7173 ( .A(n5605), .B(n5604), .Y(n5607) );
XNOR2X1TS U7174 ( .A(n5607), .B(n5606), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2) );
OAI22X1TS U7175 ( .A0(n5619), .A1(FPMULT_Op_MX[17]), .B0(n2318), .B1(n2405),
.Y(DP_OP_500J223_126_4510_n147) );
OAI22X1TS U7176 ( .A0(n5617), .A1(n2344), .B0(n2376), .B1(n2405), .Y(
DP_OP_500J223_126_4510_n150) );
OAI22X1TS U7177 ( .A0(n2376), .A1(FPMULT_Op_MX[17]), .B0(n5608), .B1(n2405),
.Y(DP_OP_500J223_126_4510_n151) );
OAI22X1TS U7178 ( .A0(n5619), .A1(n5609), .B0(n2305), .B1(n5610), .Y(
DP_OP_500J223_126_4510_n154) );
OAI22X1TS U7179 ( .A0(n5619), .A1(n5610), .B0(n2319), .B1(n5609), .Y(
DP_OP_500J223_126_4510_n155) );
OAI22X1TS U7180 ( .A0(n5621), .A1(n5610), .B0(n5617), .B1(n5609), .Y(
DP_OP_500J223_126_4510_n157) );
OAI22X1TS U7181 ( .A0(n2310), .A1(n5610), .B0(n2376), .B1(n5609), .Y(
DP_OP_500J223_126_4510_n158) );
OAI22X1TS U7182 ( .A0(n5619), .A1(n5611), .B0(n2306), .B1(n5612), .Y(
DP_OP_500J223_126_4510_n162) );
OAI22X1TS U7183 ( .A0(n2319), .A1(n5612), .B0(n2378), .B1(n5611), .Y(
DP_OP_500J223_126_4510_n164) );
OAI22X1TS U7184 ( .A0(n5621), .A1(n5612), .B0(n5617), .B1(n5611), .Y(
DP_OP_500J223_126_4510_n165) );
OAI22X1TS U7185 ( .A0(n2380), .A1(n5613), .B0(n2306), .B1(n5615), .Y(
DP_OP_500J223_126_4510_n170) );
OAI22X1TS U7186 ( .A0(n2380), .A1(n5615), .B0(n2319), .B1(n5613), .Y(
DP_OP_500J223_126_4510_n171) );
OAI22X1TS U7187 ( .A0(n2319), .A1(n5615), .B0(n2378), .B1(n5613), .Y(
DP_OP_500J223_126_4510_n172) );
OAI22X1TS U7188 ( .A0(n2310), .A1(n5615), .B0(n2376), .B1(n5613), .Y(
DP_OP_500J223_126_4510_n174) );
OAI22X1TS U7189 ( .A0(n2380), .A1(n5616), .B0(n2306), .B1(n5618), .Y(
DP_OP_500J223_126_4510_n178) );
OAI22X1TS U7190 ( .A0(n5619), .A1(n5618), .B0(n2319), .B1(n5616), .Y(
DP_OP_500J223_126_4510_n179) );
OAI22X1TS U7191 ( .A0(n2318), .A1(n5618), .B0(n5621), .B1(n5616), .Y(
DP_OP_500J223_126_4510_n180) );
OAI22X1TS U7192 ( .A0(n5621), .A1(n5618), .B0(n2310), .B1(n5616), .Y(
DP_OP_500J223_126_4510_n181) );
OAI22X1TS U7193 ( .A0(n5619), .A1(n5620), .B0(n2306), .B1(n5622), .Y(
DP_OP_500J223_126_4510_n186) );
OAI22X1TS U7194 ( .A0(n5619), .A1(n5622), .B0(n2319), .B1(n5620), .Y(
DP_OP_500J223_126_4510_n187) );
OAI22X1TS U7195 ( .A0(n2319), .A1(n5622), .B0(n2378), .B1(n5620), .Y(
DP_OP_500J223_126_4510_n188) );
NOR3BX1TS U7196 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n5623) );
XOR2X1TS U7197 ( .A(n2382), .B(n5623), .Y(DP_OP_234J223_132_4955_n15) );
OR2X2TS U7198 ( .A(FPMULT_FSM_selector_B[1]), .B(n6781), .Y(n5630) );
OAI2BB1X1TS U7199 ( .A0N(FPMULT_Op_MY[29]), .A1N(n6784), .B0(n5630), .Y(
n5624) );
XOR2X1TS U7200 ( .A(n2382), .B(n5624), .Y(DP_OP_234J223_132_4955_n16) );
OAI2BB1X1TS U7201 ( .A0N(FPMULT_Op_MY[28]), .A1N(n6784), .B0(n5630), .Y(
n5625) );
XOR2X1TS U7202 ( .A(n2382), .B(n5625), .Y(DP_OP_234J223_132_4955_n17) );
OAI2BB1X1TS U7203 ( .A0N(FPMULT_Op_MY[27]), .A1N(n6784), .B0(n5630), .Y(
n5626) );
XOR2X1TS U7204 ( .A(n2382), .B(n5626), .Y(DP_OP_234J223_132_4955_n18) );
OAI2BB1X1TS U7205 ( .A0N(FPMULT_Op_MY[26]), .A1N(n6784), .B0(n5630), .Y(
n5627) );
XOR2X1TS U7206 ( .A(n2382), .B(n5627), .Y(DP_OP_234J223_132_4955_n19) );
OAI2BB1X1TS U7207 ( .A0N(FPMULT_Op_MY[25]), .A1N(n6784), .B0(n5630), .Y(
n5628) );
XOR2X1TS U7208 ( .A(n2382), .B(n5628), .Y(DP_OP_234J223_132_4955_n20) );
OAI2BB1X1TS U7209 ( .A0N(FPMULT_Op_MY[24]), .A1N(n6784), .B0(n5630), .Y(
n5629) );
XOR2X1TS U7210 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n5629), .Y(
DP_OP_234J223_132_4955_n21) );
XOR2X1TS U7211 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n5632), .Y(
DP_OP_234J223_132_4955_n22) );
NOR2BX1TS U7212 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n5633) );
XOR2X1TS U7213 ( .A(n6766), .B(n5633), .Y(DP_OP_26J223_129_1325_n14) );
NOR2BX1TS U7214 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n5634) );
XOR2X1TS U7215 ( .A(n6766), .B(n5634), .Y(DP_OP_26J223_129_1325_n15) );
NOR2BX1TS U7216 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n5635) );
XOR2X1TS U7217 ( .A(n6766), .B(n5635), .Y(DP_OP_26J223_129_1325_n16) );
NOR2BX1TS U7218 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n5636) );
XOR2X1TS U7219 ( .A(n6766), .B(n5636), .Y(DP_OP_26J223_129_1325_n17) );
XOR2X1TS U7220 ( .A(n6766), .B(n2502), .Y(DP_OP_26J223_129_1325_n18) );
XOR2X1TS U7221 ( .A(n5652), .B(n5651), .Y(n5654) );
XNOR2X1TS U7222 ( .A(n5654), .B(n5653), .Y(mult_x_309_n37) );
XNOR2X1TS U7223 ( .A(n5656), .B(n5655), .Y(n5657) );
XNOR2X1TS U7224 ( .A(n5658), .B(n5657), .Y(mult_x_309_n15) );
XOR2X1TS U7225 ( .A(n5660), .B(n5659), .Y(n5662) );
XNOR2X1TS U7226 ( .A(n5662), .B(n5661), .Y(mult_x_309_n18) );
XOR2X1TS U7227 ( .A(n5664), .B(n5663), .Y(n5666) );
XOR2X1TS U7228 ( .A(n5666), .B(n5665), .Y(mult_x_309_n23) );
XOR2X1TS U7229 ( .A(n5668), .B(n5667), .Y(n5670) );
XNOR2X1TS U7230 ( .A(n5670), .B(n5669), .Y(mult_x_309_n30) );
NAND2X1TS U7231 ( .A(FPMULT_Op_MX[18]), .B(n6753), .Y(n5682) );
NOR2BX1TS U7232 ( .AN(n5682), .B(n5671), .Y(n5673) );
XOR2X1TS U7233 ( .A(n5673), .B(n5672), .Y(intadd_515_CI) );
INVX2TS U7234 ( .A(n5674), .Y(n5680) );
AOI21X1TS U7235 ( .A0(n5680), .A1(n2478), .B0(n5675), .Y(n5676) );
NAND2X1TS U7236 ( .A(n2291), .B(FPMULT_Op_MX[19]), .Y(n5681) );
AOI21X1TS U7237 ( .A0(n5682), .A1(n5681), .B0(n5680), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1) );
NOR2BX2TS U7238 ( .AN(n5684), .B(n5683), .Y(n5720) );
INVX2TS U7239 ( .A(n5687), .Y(n5685) );
NAND2X1TS U7240 ( .A(n5685), .B(n5686), .Y(n5689) );
INVX2TS U7241 ( .A(n5686), .Y(n5688) );
XNOR2X1TS U7242 ( .A(n5692), .B(n5691), .Y(n5694) );
XOR2X1TS U7243 ( .A(n5694), .B(n5693), .Y(n5719) );
INVX2TS U7244 ( .A(n5721), .Y(n5696) );
INVX2TS U7245 ( .A(n5720), .Y(n5695) );
OAI22X1TS U7246 ( .A0(n5697), .A1(n5719), .B0(n5696), .B1(n5695), .Y(
intadd_512_A_6_) );
INVX2TS U7247 ( .A(n5699), .Y(n5703) );
INVX2TS U7248 ( .A(n5702), .Y(n5700) );
OAI21X1TS U7249 ( .A0(n5703), .A1(n5702), .B0(n5701), .Y(n5728) );
OAI21X1TS U7250 ( .A0(n5706), .A1(n5705), .B0(n5704), .Y(n5727) );
XNOR2X1TS U7251 ( .A(n5708), .B(n5707), .Y(n5709) );
ACHCINX2TS U7252 ( .CIN(n5728), .A(n5727), .B(n5729), .CO(intadd_512_A_4_)
);
XNOR2X1TS U7253 ( .A(n5711), .B(n5714), .Y(n5713) );
XOR2X1TS U7254 ( .A(n5713), .B(n5712), .Y(intadd_512_A_1_) );
NOR2BX1TS U7255 ( .AN(n5718), .B(n5717), .Y(intadd_512_B_7_) );
XOR2X1TS U7256 ( .A(n5720), .B(n5719), .Y(n5722) );
XNOR2X1TS U7257 ( .A(n5722), .B(n5721), .Y(intadd_512_B_5_) );
XOR2X1TS U7258 ( .A(n5724), .B(n5723), .Y(n5726) );
XNOR2X1TS U7259 ( .A(n5726), .B(n5725), .Y(intadd_512_B_4_) );
XOR2X1TS U7260 ( .A(n5728), .B(n5727), .Y(n5730) );
XNOR2X1TS U7261 ( .A(n5730), .B(n5729), .Y(intadd_512_B_3_) );
XOR2X1TS U7262 ( .A(n5732), .B(n5731), .Y(n5734) );
XOR2X1TS U7263 ( .A(n5734), .B(n5733), .Y(intadd_512_B_2_) );
NAND2X1TS U7264 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MX[12]), .Y(n5737) );
INVX2TS U7265 ( .A(n5737), .Y(n5736) );
NOR2X1TS U7266 ( .A(n5741), .B(n5742), .Y(n5740) );
AOI21X1TS U7267 ( .A0(n5736), .A1(n5738), .B0(n5740), .Y(intadd_512_B_1_) );
OAI21X1TS U7268 ( .A0(n2484), .A1(n2257), .B0(n5739), .Y(n5743) );
XNOR2X1TS U7269 ( .A(n5738), .B(n5737), .Y(n5745) );
NOR2X1TS U7270 ( .A(n5739), .B(n2257), .Y(n5744) );
AOI21X1TS U7271 ( .A0(n5743), .A1(n5745), .B0(n5744), .Y(intadd_512_B_0_) );
XNOR2X1TS U7272 ( .A(n5746), .B(n5745), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2) );
NAND2X1TS U7273 ( .A(FPMULT_Op_MX[8]), .B(n6584), .Y(n5782) );
NOR2X2TS U7274 ( .A(n5783), .B(n5782), .Y(n5781) );
AOI22X1TS U7275 ( .A0(DP_OP_501J223_127_5235_n944), .A1(n6584), .B0(
DP_OP_501J223_127_5235_n903), .B1(n6572), .Y(n5747) );
XNOR2X1TS U7276 ( .A(n5750), .B(n5749), .Y(n5752) );
XOR2X1TS U7277 ( .A(n5752), .B(n5751), .Y(n5756) );
OAI2BB1X1TS U7278 ( .A0N(n5781), .A1N(n5754), .B0(n5753), .Y(mult_x_311_n36)
);
XOR2X1TS U7279 ( .A(n5754), .B(n5781), .Y(n5755) );
XOR2X1TS U7280 ( .A(n5756), .B(n5755), .Y(mult_x_311_n37) );
AOI21X1TS U7281 ( .A0(n5760), .A1(n5759), .B0(n5758), .Y(intadd_513_A_0_) );
XNOR2X1TS U7282 ( .A(n5762), .B(n5761), .Y(n5764) );
XOR2X1TS U7283 ( .A(n5764), .B(n5763), .Y(mult_x_311_n15) );
XOR2X1TS U7284 ( .A(n5766), .B(n5765), .Y(n5768) );
XNOR2X1TS U7285 ( .A(n5768), .B(n5767), .Y(mult_x_311_n18) );
XNOR2X1TS U7286 ( .A(n5770), .B(n5769), .Y(n5772) );
XOR2X1TS U7287 ( .A(n5772), .B(n5771), .Y(mult_x_311_n23) );
XOR2X1TS U7288 ( .A(n5774), .B(n5773), .Y(n5776) );
XOR2X1TS U7289 ( .A(n5776), .B(n5775), .Y(mult_x_311_n30) );
AOI21X1TS U7290 ( .A0(n5779), .A1(n5778), .B0(n5777), .Y(n5786) );
OAI21X1TS U7291 ( .A0(n6765), .A1(n2259), .B0(n5780), .Y(n5784) );
OAI2BB1X1TS U7292 ( .A0N(n5786), .A1N(n5784), .B0(n5785), .Y(intadd_513_B_0_) );
AOI21X1TS U7293 ( .A0(n5783), .A1(n5782), .B0(n5781), .Y(intadd_513_CI) );
NAND2X1TS U7294 ( .A(n5785), .B(n5784), .Y(n5787) );
XNOR2X1TS U7295 ( .A(n5787), .B(n5786), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2) );
NOR2BX2TS U7296 ( .AN(n5789), .B(n5788), .Y(n5823) );
INVX2TS U7297 ( .A(n5792), .Y(n5790) );
NAND2X1TS U7298 ( .A(n5790), .B(n5791), .Y(n5794) );
INVX2TS U7299 ( .A(n5791), .Y(n5793) );
XNOR2X1TS U7300 ( .A(n5797), .B(n5796), .Y(n5799) );
XOR2X1TS U7301 ( .A(n5799), .B(n5798), .Y(n5822) );
INVX2TS U7302 ( .A(n5824), .Y(n5801) );
INVX2TS U7303 ( .A(n5823), .Y(n5800) );
OAI22X1TS U7304 ( .A0(n5802), .A1(n5822), .B0(n5801), .B1(n5800), .Y(
intadd_514_A_6_) );
INVX2TS U7305 ( .A(n5804), .Y(n5808) );
INVX2TS U7306 ( .A(n5807), .Y(n5805) );
OAI21X1TS U7307 ( .A0(n5808), .A1(n5807), .B0(n5806), .Y(n5831) );
OAI21X1TS U7308 ( .A0(n5811), .A1(n5810), .B0(n5809), .Y(n5830) );
XNOR2X1TS U7309 ( .A(n5813), .B(n5812), .Y(n5814) );
ACHCINX2TS U7310 ( .CIN(n5831), .A(n5830), .B(n5832), .CO(intadd_514_A_4_)
);
XNOR2X1TS U7311 ( .A(n5817), .B(n5816), .Y(n5819) );
XOR2X1TS U7312 ( .A(n5819), .B(n5818), .Y(intadd_514_A_1_) );
NOR2BX1TS U7313 ( .AN(n5821), .B(n5820), .Y(intadd_514_B_7_) );
XOR2X1TS U7314 ( .A(n5823), .B(n5822), .Y(n5825) );
XNOR2X1TS U7315 ( .A(n5825), .B(n5824), .Y(intadd_514_B_5_) );
XOR2X1TS U7316 ( .A(n5827), .B(n5826), .Y(n5829) );
XNOR2X1TS U7317 ( .A(n5829), .B(n5828), .Y(intadd_514_B_4_) );
XOR2X1TS U7318 ( .A(n5831), .B(n5830), .Y(n5833) );
XNOR2X1TS U7319 ( .A(n5833), .B(n5832), .Y(intadd_514_B_3_) );
XOR2X1TS U7320 ( .A(n5835), .B(n5834), .Y(n5837) );
XOR2X1TS U7321 ( .A(n5837), .B(n5836), .Y(intadd_514_B_2_) );
NAND2X1TS U7322 ( .A(FPMULT_Op_MY[2]), .B(n6568), .Y(n5840) );
INVX2TS U7323 ( .A(n5840), .Y(n5839) );
NOR2X1TS U7324 ( .A(n5844), .B(n5845), .Y(n5843) );
AOI21X1TS U7325 ( .A0(n5839), .A1(n5841), .B0(n5843), .Y(intadd_514_B_1_) );
OAI21X1TS U7326 ( .A0(n7062), .A1(n2258), .B0(n5842), .Y(n5846) );
XNOR2X1TS U7327 ( .A(n5841), .B(n5840), .Y(n5848) );
NOR2X1TS U7328 ( .A(n5842), .B(n2258), .Y(n5847) );
AOI21X1TS U7329 ( .A0(n5846), .A1(n5848), .B0(n5847), .Y(intadd_514_B_0_) );
XNOR2X1TS U7330 ( .A(n5849), .B(n5848), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2) );
NOR2X1TS U7331 ( .A(n6759), .B(n6789), .Y(n5883) );
NAND2X1TS U7332 ( .A(n5883), .B(FPMULT_Sgf_normalized_result[10]), .Y(n5854)
);
INVX2TS U7333 ( .A(n5876), .Y(n5873) );
AHHCINX2TS U7334 ( .A(FPMULT_Sgf_normalized_result[22]), .CIN(n5856), .S(
n5857), .CO(n5930) );
AHHCONX2TS U7335 ( .A(FPMULT_Sgf_normalized_result[21]), .CI(n5858), .CON(
n5856), .S(n5859) );
AHHCINX2TS U7336 ( .A(FPMULT_Sgf_normalized_result[20]), .CIN(n5860), .S(
n5861), .CO(n5858) );
AHHCONX2TS U7337 ( .A(FPMULT_Sgf_normalized_result[19]), .CI(n5862), .CON(
n5860), .S(n5863) );
AHHCINX2TS U7338 ( .A(FPMULT_Sgf_normalized_result[18]), .CIN(n5864), .S(
n5865), .CO(n5862) );
AHHCONX2TS U7339 ( .A(FPMULT_Sgf_normalized_result[17]), .CI(n5866), .CON(
n5864), .S(n5867) );
AHHCINX2TS U7340 ( .A(FPMULT_Sgf_normalized_result[16]), .CIN(n5868), .S(
n5869), .CO(n5866) );
AHHCONX2TS U7341 ( .A(FPMULT_Sgf_normalized_result[15]), .CI(n5870), .CON(
n5868), .S(n5871) );
AHHCINX2TS U7342 ( .A(FPMULT_Sgf_normalized_result[14]), .CIN(n5872), .S(
n5874), .CO(n5870) );
AHHCONX2TS U7343 ( .A(FPMULT_Sgf_normalized_result[13]), .CI(n5875), .CON(
n5872), .S(n5877) );
AHHCINX2TS U7344 ( .A(FPMULT_Sgf_normalized_result[12]), .CIN(n5878), .S(
n5879), .CO(n5875) );
AHHCONX2TS U7345 ( .A(FPMULT_Sgf_normalized_result[11]), .CI(n5880), .CON(
n5878), .S(n5881) );
INVX2TS U7346 ( .A(n5882), .Y(n5888) );
NAND2X1TS U7347 ( .A(n5888), .B(n5883), .Y(n5884) );
XOR2X1TS U7348 ( .A(n5884), .B(n6865), .Y(n5885) );
NAND2X1TS U7349 ( .A(n5888), .B(FPMULT_Sgf_normalized_result[8]), .Y(n5886)
);
XOR2X1TS U7350 ( .A(n5886), .B(n6789), .Y(n5887) );
XNOR2X1TS U7351 ( .A(n5888), .B(n6759), .Y(n5889) );
INVX2TS U7352 ( .A(n5890), .Y(n5898) );
OAI21X1TS U7353 ( .A0(n5898), .A1(n6792), .B0(n5891), .Y(n5894) );
NAND2X1TS U7354 ( .A(n5894), .B(FPMULT_Sgf_normalized_result[6]), .Y(n5892)
);
XOR2X1TS U7355 ( .A(n5892), .B(n6866), .Y(n5893) );
XNOR2X1TS U7356 ( .A(n5894), .B(n2399), .Y(n5895) );
NAND2X1TS U7357 ( .A(n5898), .B(n2450), .Y(n5896) );
XNOR2X1TS U7358 ( .A(n5896), .B(n6792), .Y(n5897) );
XOR2X1TS U7359 ( .A(n5898), .B(FPMULT_Sgf_normalized_result[4]), .Y(n5900)
);
NAND2X1TS U7360 ( .A(n2485), .B(n5901), .Y(n5902) );
XNOR2X1TS U7361 ( .A(n5903), .B(n5902), .Y(n5904) );
XOR2X1TS U7362 ( .A(n5906), .B(n6788), .Y(n5907) );
INVX2TS U7363 ( .A(n5908), .Y(n5921) );
INVX2TS U7364 ( .A(n5909), .Y(n5911) );
NAND2X1TS U7365 ( .A(n5911), .B(n5910), .Y(n5912) );
XNOR2X1TS U7366 ( .A(n5913), .B(n5912), .Y(n5914) );
XOR2X1TS U7367 ( .A(n5915), .B(FPMULT_Sgf_normalized_result[2]), .Y(n5916)
);
INVX2TS U7368 ( .A(n5917), .Y(n5919) );
NAND2X1TS U7369 ( .A(n5919), .B(n5918), .Y(n5920) );
XOR2X1TS U7370 ( .A(n5921), .B(n5920), .Y(n5922) );
XNOR2X1TS U7371 ( .A(FPMULT_Sgf_normalized_result[0]), .B(
FPMULT_Sgf_normalized_result[1]), .Y(n5923) );
INVX2TS U7372 ( .A(n5924), .Y(n6280) );
AOI21X1TS U7373 ( .A0(n6280), .A1(n2471), .B0(n5925), .Y(n5928) );
NAND2X1TS U7374 ( .A(n2204), .B(n5926), .Y(n5927) );
XOR2X1TS U7375 ( .A(n5928), .B(n5927), .Y(n5929) );
ADDHXLTS U7376 ( .A(FPMULT_Sgf_normalized_result[23]), .B(n5930), .CO(n5932),
.S(n5855) );
NAND2X1TS U7377 ( .A(n6605), .B(n6845), .Y(n1689) );
XNOR2X2TS U7378 ( .A(DP_OP_234J223_132_4955_n1), .B(n5935), .Y(n5936) );
MX2X1TS U7379 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1453) );
BUFX3TS U7380 ( .A(n5937), .Y(n6014) );
AOI211X1TS U7381 ( .A0(FPADDSUB_Data_array_SWR[5]), .A1(n2330), .B0(n5939),
.C0(n5938), .Y(n6004) );
OAI22X1TS U7382 ( .A0(n6004), .A1(n5984), .B0(n6008), .B1(n5954), .Y(n6628)
);
OA22X1TS U7383 ( .A0(n6628), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n1181) );
OAI2BB2XLTS U7384 ( .B0(n5989), .B1(n2263), .A0N(FPADDSUB_Data_array_SWR[10]), .A1N(n2326), .Y(n5940) );
AOI211X1TS U7385 ( .A0(FPADDSUB_Data_array_SWR[6]), .A1(n2329), .B0(n5941),
.C0(n5940), .Y(n6000) );
OAI22X1TS U7386 ( .A0(n6000), .A1(n5984), .B0(n6001), .B1(n5954), .Y(n6639)
);
OA22X1TS U7387 ( .A0(n6639), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n1182) );
AOI211X1TS U7388 ( .A0(FPADDSUB_shift_value_SHT2_EWR[4]), .A1(n5955), .B0(
n5943), .C0(n5942), .Y(n5997) );
OAI22X1TS U7389 ( .A0(n5997), .A1(n5984), .B0(n5996), .B1(n5954), .Y(n6645)
);
OA22X1TS U7390 ( .A0(n6645), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n1183) );
INVX2TS U7391 ( .A(n5944), .Y(n5946) );
NOR2X1TS U7392 ( .A(n2504), .B(n5946), .Y(n5945) );
AOI211X2TS U7393 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n2312), .B0(n5948),
.C0(n5945), .Y(n5994) );
NOR2X1TS U7394 ( .A(n6816), .B(n5946), .Y(n5947) );
OAI2BB2XLTS U7395 ( .B0(n5992), .B1(n2263), .A0N(FPADDSUB_Data_array_SWR[12]), .A1N(n2326), .Y(n5949) );
AOI211X1TS U7396 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n2330), .B0(n5950),
.C0(n5949), .Y(n5995) );
OAI22X1TS U7397 ( .A0(n5994), .A1(n5954), .B0(n5995), .B1(n5984), .Y(n6642)
);
OA22X1TS U7398 ( .A0(n6642), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n1184) );
OAI2BB2XLTS U7399 ( .B0(n5994), .B1(n2263), .A0N(FPADDSUB_Data_array_SWR[13]), .A1N(n2326), .Y(n5952) );
AOI211X1TS U7400 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n2330), .B0(n5953),
.C0(n5952), .Y(n5993) );
OAI22X1TS U7401 ( .A0(n5993), .A1(n5984), .B0(n5992), .B1(n5954), .Y(n6636)
);
OA22X1TS U7402 ( .A0(n6636), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n1185) );
OA22X1TS U7403 ( .A0(n6648), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n1186) );
OA22X1TS U7404 ( .A0(n6632), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n1188) );
OA22X1TS U7405 ( .A0(n6663), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n1189) );
AOI21X1TS U7406 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n2343), .B0(n5979),
.Y(n5965) );
AOI22X1TS U7407 ( .A0(FPADDSUB_Data_array_SWR[22]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[14]), .B1(n2330), .Y(n5964) );
OAI211X1TS U7408 ( .A0(n6842), .A1(n5966), .B0(n5965), .C0(n5964), .Y(n5985)
);
NOR2BX1TS U7409 ( .AN(n5967), .B(n5979), .Y(n5973) );
AOI22X1TS U7410 ( .A0(FPADDSUB_Data_array_SWR[23]), .A1(n3288), .B0(
FPADDSUB_Data_array_SWR[19]), .B1(n2330), .Y(n5968) );
OAI211X1TS U7411 ( .A0(n2418), .A1(n5969), .B0(n5973), .C0(n5968), .Y(n5986)
);
AOI22X1TS U7412 ( .A0(n2357), .A1(n5985), .B0(n5986), .B1(n2356), .Y(n6651)
);
MXI2X1TS U7413 ( .A(n6651), .B(n6858), .S0(n6003), .Y(n1190) );
AOI21X1TS U7414 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n3288), .B0(n5979),
.Y(n5971) );
AOI22X1TS U7415 ( .A0(FPADDSUB_Data_array_SWR[23]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2343), .Y(n5970) );
OAI211X1TS U7416 ( .A0(n2418), .A1(n5974), .B0(n5971), .C0(n5970), .Y(n5982)
);
AOI22X1TS U7417 ( .A0(FPADDSUB_Data_array_SWR[22]), .A1(n3288), .B0(
FPADDSUB_Data_array_SWR[14]), .B1(n2343), .Y(n5972) );
OAI211X1TS U7418 ( .A0(n6842), .A1(n5974), .B0(n5973), .C0(n5972), .Y(n5983)
);
AOI22X1TS U7419 ( .A0(n2357), .A1(n5982), .B0(n5983), .B1(n2235), .Y(n6667)
);
MXI2X1TS U7420 ( .A(n6667), .B(n6862), .S0(n6003), .Y(n1191) );
AOI22X1TS U7421 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n2343), .B0(
FPADDSUB_Data_array_SWR[24]), .B1(n2328), .Y(n5976) );
AOI22X1TS U7422 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n3288), .B0(
FPADDSUB_Data_array_SWR[16]), .B1(n2330), .Y(n5975) );
AOI22X1TS U7423 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n3288), .B0(
FPADDSUB_Data_array_SWR[25]), .B1(n2328), .Y(n5978) );
AOI22X1TS U7424 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n2330), .B0(
FPADDSUB_Data_array_SWR[13]), .B1(n2343), .Y(n5977) );
AOI221X1TS U7425 ( .A0(n2357), .A1(n5980), .B0(n5984), .B1(n5981), .C0(n5979), .Y(n6661) );
MXI2X1TS U7426 ( .A(n6661), .B(n6859), .S0(n6003), .Y(n1192) );
AOI221X1TS U7427 ( .A0(n6005), .A1(n5981), .B0(n2235), .B1(n5980), .C0(n5979), .Y(n6666) );
MXI2X1TS U7428 ( .A(n6666), .B(n6860), .S0(n6003), .Y(n1193) );
AOI22X1TS U7429 ( .A0(n6005), .A1(n5983), .B0(n5982), .B1(n2235), .Y(n6725)
);
MXI2X1TS U7430 ( .A(n6725), .B(n6863), .S0(n6003), .Y(n1194) );
AOI22X1TS U7431 ( .A0(n6005), .A1(n5986), .B0(n5985), .B1(n2356), .Y(n6658)
);
MXI2X1TS U7432 ( .A(n6658), .B(n6856), .S0(n6003), .Y(n1195) );
OAI22X1TS U7433 ( .A0(n5990), .A1(n2357), .B0(n6007), .B1(n5989), .Y(n6726)
);
OA22X1TS U7434 ( .A0(n6726), .A1(n5998), .B0(n6009), .B1(
FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n1198) );
OAI22X1TS U7435 ( .A0(n5993), .A1(n6005), .B0(n6007), .B1(n5992), .Y(n6718)
);
OA22X1TS U7436 ( .A0(n6718), .A1(n5998), .B0(n6009), .B1(
FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n1200) );
OAI22X1TS U7437 ( .A0(n5995), .A1(n6005), .B0(n5994), .B1(n6007), .Y(n6720)
);
OA22X1TS U7438 ( .A0(n6720), .A1(n5998), .B0(n6009), .B1(
FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n1201) );
OAI22X1TS U7439 ( .A0(n5997), .A1(n2357), .B0(n6007), .B1(n5996), .Y(n6723)
);
OA22X1TS U7440 ( .A0(n6723), .A1(n5998), .B0(n6009), .B1(
FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n1202) );
INVX2TS U7441 ( .A(n5999), .Y(n6727) );
OAI22X1TS U7442 ( .A0(n6001), .A1(n6007), .B0(n2357), .B1(n6000), .Y(n6002)
);
NOR2X1TS U7443 ( .A(n6727), .B(n6002), .Y(n6722) );
MXI2X1TS U7444 ( .A(n6722), .B(n6861), .S0(n6003), .Y(n1203) );
OA22X1TS U7445 ( .A0(n6011), .A1(n6010), .B0(n6009), .B1(
FPADDSUB_DmP_mant_SFG_SWR[1]), .Y(n1204) );
OAI32X4TS U7446 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n6012), .B1(n6826),
.Y(n6353) );
MXI2X1TS U7447 ( .A(n6013), .B(n6232), .S0(n6353), .Y(n2144) );
OAI22X1TS U7448 ( .A0(FPMULT_Exp_module_Data_S[8]), .A1(n6021), .B0(n6020),
.B1(n6864), .Y(n1586) );
OA22X1TS U7449 ( .A0(n6626), .A1(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B0(n6022),
.B1(result_add_subt[29]), .Y(n1467) );
OA22X1TS U7450 ( .A0(n6626), .A1(FPADDSUB_exp_rslt_NRM2_EW1[5]), .B0(n6022),
.B1(result_add_subt[28]), .Y(n1468) );
OA22X1TS U7451 ( .A0(n6626), .A1(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B0(n6022),
.B1(result_add_subt[27]), .Y(n1469) );
OA22X1TS U7452 ( .A0(n6626), .A1(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B0(n6022),
.B1(result_add_subt[26]), .Y(n1470) );
OA22X1TS U7453 ( .A0(n6626), .A1(FPADDSUB_exp_rslt_NRM2_EW1[2]), .B0(n6022),
.B1(result_add_subt[25]), .Y(n1471) );
OR4X2TS U7454 ( .A(n6617), .B(FPMULT_Exp_module_Overflow_flag_A), .C(
FPMULT_exp_oper_result[8]), .D(underflow_flag_mult), .Y(n6608) );
INVX2TS U7455 ( .A(n6613), .Y(n6619) );
BUFX3TS U7456 ( .A(n6024), .Y(n6134) );
INVX2TS U7457 ( .A(n6025), .Y(n6185) );
INVX2TS U7458 ( .A(n6026), .Y(n6029) );
INVX2TS U7459 ( .A(n6027), .Y(n6028) );
NAND2X1TS U7460 ( .A(n6031), .B(n6030), .Y(n6036) );
INVX2TS U7461 ( .A(n6036), .Y(n6032) );
XNOR2X1TS U7462 ( .A(n6033), .B(n6032), .Y(n6040) );
INVX2TS U7463 ( .A(n6034), .Y(n6108) );
XNOR2X1TS U7464 ( .A(n6037), .B(n6036), .Y(n6038) );
AOI22X1TS U7465 ( .A0(n6038), .A1(n4499), .B0(FPADDSUB_Raw_mant_NRM_SWR[11]),
.B1(n6711), .Y(n6039) );
OAI2BB1X1TS U7466 ( .A0N(n6134), .A1N(n6040), .B0(n6039), .Y(n1338) );
NAND2X1TS U7467 ( .A(n6043), .B(n6042), .Y(n6046) );
INVX2TS U7468 ( .A(n6046), .Y(n6044) );
XOR2X1TS U7469 ( .A(n6047), .B(n6046), .Y(n6048) );
AOI22X1TS U7470 ( .A0(n6048), .A1(n4499), .B0(FPADDSUB_Raw_mant_NRM_SWR[13]),
.B1(n6711), .Y(n6049) );
OAI2BB1X1TS U7471 ( .A0N(n6134), .A1N(n6050), .B0(n6049), .Y(n1336) );
NAND2X1TS U7472 ( .A(n6054), .B(n6053), .Y(n6057) );
INVX2TS U7473 ( .A(n6057), .Y(n6055) );
XNOR2X1TS U7474 ( .A(n6056), .B(n6055), .Y(n6060) );
XOR2X1TS U7475 ( .A(n6108), .B(n6057), .Y(n6058) );
AOI22X1TS U7476 ( .A0(n6058), .A1(n4499), .B0(FPADDSUB_Raw_mant_NRM_SWR[10]),
.B1(n6711), .Y(n6059) );
OAI2BB1X1TS U7477 ( .A0N(n6134), .A1N(n6060), .B0(n6059), .Y(n1339) );
NAND2X1TS U7478 ( .A(n6062), .B(n6061), .Y(n6065) );
INVX2TS U7479 ( .A(n6065), .Y(n6063) );
XNOR2X1TS U7480 ( .A(n6064), .B(n6063), .Y(n6069) );
XNOR2X1TS U7481 ( .A(n6066), .B(n6065), .Y(n6067) );
AOI22X1TS U7482 ( .A0(n6067), .A1(n4499), .B0(FPADDSUB_Raw_mant_NRM_SWR[16]),
.B1(n6711), .Y(n6068) );
OAI2BB1X1TS U7483 ( .A0N(n6134), .A1N(n6069), .B0(n6068), .Y(n1333) );
NAND2X1TS U7484 ( .A(n6071), .B(n6070), .Y(n6074) );
INVX2TS U7485 ( .A(n6074), .Y(n6072) );
XNOR2X1TS U7486 ( .A(n6073), .B(n6072), .Y(n6078) );
XNOR2X1TS U7487 ( .A(n6075), .B(n6074), .Y(n6076) );
AOI22X1TS U7488 ( .A0(n6076), .A1(n4499), .B0(FPADDSUB_Raw_mant_NRM_SWR[14]),
.B1(n6711), .Y(n6077) );
OAI2BB1X1TS U7489 ( .A0N(n6134), .A1N(n6078), .B0(n6077), .Y(n1335) );
INVX2TS U7490 ( .A(n6079), .Y(n6081) );
NAND2X1TS U7491 ( .A(n6081), .B(n6080), .Y(n6084) );
INVX2TS U7492 ( .A(n6084), .Y(n6082) );
XOR2X1TS U7493 ( .A(n6085), .B(n6084), .Y(n6086) );
AOI22X1TS U7494 ( .A0(n6086), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[17]),
.B1(n6191), .Y(n6087) );
OAI2BB1X1TS U7495 ( .A0N(n6134), .A1N(n6088), .B0(n6087), .Y(n1332) );
NAND2X1TS U7496 ( .A(n6091), .B(n6090), .Y(n6094) );
INVX2TS U7497 ( .A(n6094), .Y(n6092) );
XOR2X1TS U7498 ( .A(n6095), .B(n6094), .Y(n6096) );
AOI22X1TS U7499 ( .A0(n6096), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[15]),
.B1(n6711), .Y(n6097) );
OAI2BB1X1TS U7500 ( .A0N(n6134), .A1N(n6098), .B0(n6097), .Y(n1334) );
NAND2X1TS U7501 ( .A(n6103), .B(n6102), .Y(n6109) );
INVX2TS U7502 ( .A(n6109), .Y(n6104) );
XNOR2X1TS U7503 ( .A(n6105), .B(n6104), .Y(n6113) );
XNOR2X1TS U7504 ( .A(n6110), .B(n6109), .Y(n6111) );
AOI22X1TS U7505 ( .A0(n6111), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[12]),
.B1(n6711), .Y(n6112) );
OAI2BB1X1TS U7506 ( .A0N(n6134), .A1N(n6113), .B0(n6112), .Y(n1337) );
INVX2TS U7507 ( .A(n6114), .Y(n6116) );
NAND2X1TS U7508 ( .A(n6116), .B(n6115), .Y(n6119) );
INVX2TS U7509 ( .A(n6119), .Y(n6117) );
XOR2X1TS U7510 ( .A(n6120), .B(n6119), .Y(n6121) );
AOI22X1TS U7511 ( .A0(n6121), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B1(n6191), .Y(n6122) );
OAI2BB1X1TS U7512 ( .A0N(n6134), .A1N(n6123), .B0(n6122), .Y(n1321) );
INVX2TS U7513 ( .A(n6124), .Y(n6126) );
NAND2X1TS U7514 ( .A(n6126), .B(n6125), .Y(n6129) );
INVX2TS U7515 ( .A(n6129), .Y(n6127) );
XOR2X1TS U7516 ( .A(n6130), .B(n6129), .Y(n6131) );
AOI22X1TS U7517 ( .A0(n6131), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[21]),
.B1(n6191), .Y(n6132) );
OAI2BB1X1TS U7518 ( .A0N(n6134), .A1N(n6133), .B0(n6132), .Y(n1319) );
NAND2X1TS U7519 ( .A(n6136), .B(n6135), .Y(n6139) );
INVX2TS U7520 ( .A(n6139), .Y(n6137) );
XNOR2X1TS U7521 ( .A(n6138), .B(n6137), .Y(n6143) );
XNOR2X1TS U7522 ( .A(n6140), .B(n6139), .Y(n6141) );
AOI22X1TS U7523 ( .A0(n6141), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[20]),
.B1(n6191), .Y(n6142) );
OAI2BB1X1TS U7524 ( .A0N(n6237), .A1N(n6143), .B0(n6142), .Y(n1320) );
OR2X1TS U7525 ( .A(n6844), .B(FPADDSUB_DMP_SFG[22]), .Y(n6145) );
CLKAND2X2TS U7526 ( .A(n6844), .B(FPADDSUB_DMP_SFG[22]), .Y(n6144) );
AOI21X1TS U7527 ( .A0(n6146), .A1(n6145), .B0(n6144), .Y(n6147) );
XOR2X1TS U7528 ( .A(n6147), .B(n6867), .Y(n6151) );
XOR2X1TS U7529 ( .A(n6148), .B(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n6149) );
AOI22X1TS U7530 ( .A0(n6149), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[25]),
.B1(n6191), .Y(n6150) );
OAI2BB1X1TS U7531 ( .A0N(n6237), .A1N(n6151), .B0(n6150), .Y(n1410) );
NAND2X1TS U7532 ( .A(n6153), .B(n6152), .Y(n6156) );
INVX2TS U7533 ( .A(n6156), .Y(n6154) );
XNOR2X1TS U7534 ( .A(n6155), .B(n6154), .Y(n6161) );
XNOR2X1TS U7535 ( .A(n6157), .B(n6156), .Y(n6159) );
AOI22X1TS U7536 ( .A0(n6159), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[22]),
.B1(n6191), .Y(n6160) );
OAI2BB1X1TS U7537 ( .A0N(n6237), .A1N(n6161), .B0(n6160), .Y(n1317) );
INVX2TS U7538 ( .A(n6162), .Y(n6164) );
NAND2X1TS U7539 ( .A(n6164), .B(n6163), .Y(n6167) );
INVX2TS U7540 ( .A(n6167), .Y(n6165) );
XOR2X1TS U7541 ( .A(n6168), .B(n6167), .Y(n6169) );
AOI22X1TS U7542 ( .A0(n6169), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[23]),
.B1(n6191), .Y(n6170) );
OAI2BB1X1TS U7543 ( .A0N(n6237), .A1N(n6171), .B0(n6170), .Y(n1316) );
NAND2X1TS U7544 ( .A(n6173), .B(n6172), .Y(n6176) );
INVX2TS U7545 ( .A(n6176), .Y(n6174) );
XNOR2X1TS U7546 ( .A(n6175), .B(n6174), .Y(n6180) );
XNOR2X1TS U7547 ( .A(n6177), .B(n6176), .Y(n6178) );
AOI22X1TS U7548 ( .A0(n6178), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[18]),
.B1(n6191), .Y(n6179) );
OAI2BB1X1TS U7549 ( .A0N(n6237), .A1N(n6180), .B0(n6179), .Y(n1331) );
INVX2TS U7550 ( .A(n6181), .Y(n6183) );
NAND2X1TS U7551 ( .A(n6183), .B(n6182), .Y(n6189) );
INVX2TS U7552 ( .A(n6189), .Y(n6184) );
AOI21X1TS U7553 ( .A0(n6231), .A1(n6188), .B0(n6187), .Y(n6205) );
XNOR2X1TS U7554 ( .A(n6190), .B(n6189), .Y(n6192) );
AOI22X1TS U7555 ( .A0(n6192), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[9]),
.B1(n6191), .Y(n6193) );
OAI2BB1X1TS U7556 ( .A0N(n6237), .A1N(n6194), .B0(n6193), .Y(n1340) );
AOI21X1TS U7557 ( .A0(n6225), .A1(n6196), .B0(n6195), .Y(n6213) );
INVX2TS U7558 ( .A(n6199), .Y(n6201) );
NAND2X1TS U7559 ( .A(n6201), .B(n6200), .Y(n6204) );
INVX2TS U7560 ( .A(n6204), .Y(n6202) );
XNOR2X1TS U7561 ( .A(n6203), .B(n6202), .Y(n6208) );
XOR2X1TS U7562 ( .A(n6205), .B(n6204), .Y(n6206) );
AOI22X1TS U7563 ( .A0(n6206), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[8]),
.B1(n6232), .Y(n6207) );
OAI2BB1X1TS U7564 ( .A0N(n6237), .A1N(n6208), .B0(n6207), .Y(n1341) );
INVX2TS U7565 ( .A(n6209), .Y(n6211) );
NAND2X1TS U7566 ( .A(n6211), .B(n6210), .Y(n6216) );
INVX2TS U7567 ( .A(n6216), .Y(n6212) );
INVX2TS U7568 ( .A(n6214), .Y(n6227) );
INVX2TS U7569 ( .A(n6226), .Y(n6215) );
AOI21X1TS U7570 ( .A0(n6231), .A1(n6227), .B0(n6215), .Y(n6217) );
XOR2X1TS U7571 ( .A(n6217), .B(n6216), .Y(n6218) );
AOI22X1TS U7572 ( .A0(n6218), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[7]),
.B1(n6232), .Y(n6219) );
OAI2BB1X1TS U7573 ( .A0N(n6237), .A1N(n6220), .B0(n6219), .Y(n1342) );
INVX2TS U7574 ( .A(n6221), .Y(n6224) );
INVX2TS U7575 ( .A(n6222), .Y(n6223) );
AOI21X1TS U7576 ( .A0(n6225), .A1(n6224), .B0(n6223), .Y(n6229) );
NAND2X1TS U7577 ( .A(n6227), .B(n6226), .Y(n6230) );
INVX2TS U7578 ( .A(n6230), .Y(n6228) );
XNOR2X1TS U7579 ( .A(n6231), .B(n6230), .Y(n6234) );
AOI22X1TS U7580 ( .A0(n6234), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[6]),
.B1(n6232), .Y(n6235) );
OAI2BB1X1TS U7581 ( .A0N(n6237), .A1N(n6236), .B0(n6235), .Y(n1343) );
NAND2X1TS U7582 ( .A(n2462), .B(n6238), .Y(n6240) );
XNOR2X1TS U7583 ( .A(n6240), .B(n6239), .Y(n6241) );
INVX2TS U7584 ( .A(n6242), .Y(n6294) );
INVX2TS U7585 ( .A(n6243), .Y(n6284) );
NAND2X1TS U7586 ( .A(n6284), .B(n6282), .Y(n6244) );
XNOR2X1TS U7587 ( .A(n6294), .B(n6244), .Y(n6245) );
INVX2TS U7588 ( .A(n6246), .Y(n6252) );
INVX2TS U7589 ( .A(n6251), .Y(n6247) );
NAND2X1TS U7590 ( .A(n6247), .B(n6250), .Y(n6248) );
XOR2X1TS U7591 ( .A(n6252), .B(n6248), .Y(n6249) );
INVX2TS U7592 ( .A(n6253), .Y(n6255) );
NAND2X1TS U7593 ( .A(n6255), .B(n6254), .Y(n6256) );
XNOR2X1TS U7594 ( .A(n6257), .B(n6256), .Y(n6258) );
INVX2TS U7595 ( .A(n6263), .Y(n6265) );
NAND2X1TS U7596 ( .A(n6265), .B(n6264), .Y(n6266) );
XOR2X1TS U7597 ( .A(n6267), .B(n6266), .Y(n6268) );
OR2X1TS U7598 ( .A(n6270), .B(n6269), .Y(n6272) );
CLKAND2X2TS U7599 ( .A(n6272), .B(n6271), .Y(n6273) );
NAND2X1TS U7600 ( .A(n6278), .B(n2471), .Y(n6279) );
XNOR2X1TS U7601 ( .A(n6280), .B(n6279), .Y(n6281) );
INVX2TS U7602 ( .A(n6282), .Y(n6283) );
AOI21X1TS U7603 ( .A0(n6294), .A1(n6284), .B0(n6283), .Y(n6289) );
INVX2TS U7604 ( .A(n6285), .Y(n6287) );
NAND2X1TS U7605 ( .A(n6287), .B(n6286), .Y(n6288) );
XOR2X1TS U7606 ( .A(n6289), .B(n6288), .Y(n6291) );
AOI21X1TS U7607 ( .A0(n6294), .A1(n6293), .B0(n6292), .Y(n6297) );
NAND2X1TS U7608 ( .A(n2203), .B(n6295), .Y(n6296) );
XOR2X1TS U7609 ( .A(n6297), .B(n6296), .Y(n6298) );
INVX2TS U7610 ( .A(n6299), .Y(n6305) );
INVX2TS U7611 ( .A(n6304), .Y(n6300) );
NAND2X1TS U7612 ( .A(n6300), .B(n6303), .Y(n6301) );
XOR2X1TS U7613 ( .A(n6305), .B(n6301), .Y(n6302) );
INVX2TS U7614 ( .A(n6306), .Y(n6308) );
NAND2X1TS U7615 ( .A(n6308), .B(n6307), .Y(n6309) );
XNOR2X1TS U7616 ( .A(n6310), .B(n6309), .Y(n6311) );
NOR4X1TS U7617 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n6318) );
NOR4X1TS U7618 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n6317) );
NOR4X1TS U7619 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n6315) );
NOR4X1TS U7620 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n6313) );
NOR4X1TS U7621 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n6312) );
AND4X1TS U7622 ( .A(n6315), .B(n6314), .C(n6313), .D(n6312), .Y(n6316) );
NOR4BX1TS U7623 ( .AN(operation_reg[1]), .B(dataB[28]), .C(operation_reg[0]),
.D(dataB[23]), .Y(n6323) );
NOR4X1TS U7624 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[25]),
.Y(n6322) );
NAND4XLTS U7625 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n6320) );
NAND4XLTS U7626 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n6319) );
OR3X1TS U7627 ( .A(n7068), .B(n6320), .C(n6319), .Y(n6324) );
NOR3X1TS U7628 ( .A(dataB[29]), .B(dataB[31]), .C(n6324), .Y(n6321) );
NOR4X1TS U7629 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n6327) );
NOR4X1TS U7630 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n6326) );
NOR4BX1TS U7631 ( .AN(operation_reg[1]), .B(operation_reg[0]), .C(dataA[31]),
.D(n7068), .Y(n6325) );
NOR2X1TS U7632 ( .A(operation_reg[1]), .B(n6324), .Y(n6332) );
NAND4XLTS U7633 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[25]),
.Y(n6328) );
OAI31X1TS U7634 ( .A0(n6330), .A1(n6329), .A2(n6328), .B0(dataB[27]), .Y(
n6331) );
OAI2BB2XLTS U7635 ( .B0(n6334), .B1(n6333), .A0N(n6332), .A1N(
operation_reg[0]), .Y(NaN_reg) );
INVX2TS U7636 ( .A(n6353), .Y(n6355) );
NOR4X1TS U7637 ( .A(n6450), .B(n2298), .C(n6415), .D(n6336), .Y(n6338) );
OAI2BB1X1TS U7638 ( .A0N(operation[1]), .A1N(ack_operation), .B0(n6337), .Y(
n6348) );
AOI32X1TS U7639 ( .A0(begin_operation), .A1(n6340), .A2(operation[1]), .B0(
n6341), .B1(n6340), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
OR2X1TS U7640 ( .A(n6369), .B(n6371), .Y(n6344) );
OAI22X1TS U7641 ( .A0(n6386), .A1(n6347), .B0(n6346), .B1(n6345), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
OR2X1TS U7642 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .Y(n6349) );
AO22XLTS U7643 ( .A0(operation[2]), .A1(n6349), .B0(n6350), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
AO22XLTS U7644 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n6350),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
AOI22X1TS U7645 ( .A0(n6355), .A1(n6714), .B0(n6741), .B1(n6353), .Y(n2147)
);
AOI22X1TS U7646 ( .A0(n6355), .A1(n6741), .B0(n6740), .B1(n6353), .Y(n2146)
);
OAI2BB2XLTS U7647 ( .B0(n6353), .B1(n6740), .A0N(n6353), .A1N(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2145) );
AOI22X1TS U7648 ( .A0(n6355), .A1(n6711), .B0(n2341), .B1(n6353), .Y(n2143)
);
AOI22X1TS U7649 ( .A0(n6355), .A1(n7059), .B0(n6354), .B1(n6353), .Y(n2142)
);
NAND2X1TS U7650 ( .A(n2299), .B(n6455), .Y(n6356) );
OA21XLTS U7651 ( .A0(n2299), .A1(FPSENCOS_cont_iter_out[0]), .B0(n6356), .Y(
n2141) );
AOI22X1TS U7652 ( .A0(n2299), .A1(n6373), .B0(n6768), .B1(n6356), .Y(n2140)
);
NAND2X1TS U7653 ( .A(n2299), .B(n6373), .Y(n6357) );
AOI32X1TS U7654 ( .A0(n2299), .A1(n6372), .A2(n6373), .B0(intadd_517_B_1_),
.B1(n6357), .Y(n2139) );
AOI21X1TS U7655 ( .A0(n6782), .A1(n6359), .B0(n6358), .Y(n2138) );
BUFX3TS U7656 ( .A(n6380), .Y(n6383) );
OAI2BB2XLTS U7657 ( .B0(n6379), .B1(n6558), .A0N(n6383), .A1N(region_flag[0]), .Y(n2135) );
OAI2BB2XLTS U7658 ( .B0(n6379), .B1(n2266), .A0N(n6383), .A1N(region_flag[1]), .Y(n2134) );
AOI22X1TS U7659 ( .A0(FPSENCOS_d_ff3_LUT_out[0]), .A1(n6456), .B0(
FPSENCOS_cont_iter_out[1]), .B1(n6366), .Y(n6361) );
NAND2X1TS U7660 ( .A(n6361), .B(n6363), .Y(n2133) );
INVX2TS U7661 ( .A(n6448), .Y(n6408) );
OAI2BB1X1TS U7662 ( .A0N(FPSENCOS_d_ff3_LUT_out[8]), .A1N(n6408), .B0(n6362),
.Y(n2125) );
OAI2BB1X1TS U7663 ( .A0N(FPSENCOS_d_ff3_LUT_out[19]), .A1N(n6408), .B0(n6367), .Y(n2119) );
BUFX3TS U7664 ( .A(n6449), .Y(n6464) );
INVX2TS U7665 ( .A(n6448), .Y(n6428) );
AOI22X1TS U7666 ( .A0(n6373), .A1(intadd_517_B_1_), .B0(n6372), .B1(n6371),
.Y(n6374) );
INVX2TS U7667 ( .A(n6382), .Y(n6376) );
INVX2TS U7668 ( .A(n6382), .Y(n6378) );
BUFX3TS U7669 ( .A(n6380), .Y(n6377) );
INVX2TS U7670 ( .A(n6382), .Y(n6381) );
INVX2TS U7671 ( .A(n6386), .Y(n6390) );
INVX2TS U7672 ( .A(n6386), .Y(n6542) );
OAI2BB2XLTS U7673 ( .B0(n6390), .B1(n2367), .A0N(n6542), .A1N(
FPSENCOS_d_ff_Zn[0]), .Y(n2074) );
BUFX3TS U7674 ( .A(n6385), .Y(n6391) );
OAI2BB2XLTS U7675 ( .B0(n6391), .B1(n2367), .A0N(n6387), .A1N(
FPSENCOS_d_ff_Yn[0]), .Y(n2073) );
AND3X2TS U7676 ( .A(n6756), .B(n6802), .C(ready_add_subt), .Y(n6388) );
INVX2TS U7677 ( .A(n6388), .Y(n6523) );
INVX2TS U7678 ( .A(n6388), .Y(n6553) );
OAI2BB2XLTS U7679 ( .B0(n6523), .B1(n2367), .A0N(n6553), .A1N(
FPSENCOS_d_ff_Xn[0]), .Y(n2072) );
INVX2TS U7680 ( .A(n6386), .Y(n6543) );
OAI2BB2XLTS U7681 ( .B0(n6543), .B1(n6835), .A0N(n6542), .A1N(
FPSENCOS_d_ff_Zn[1]), .Y(n2071) );
BUFX3TS U7682 ( .A(n6387), .Y(n6389) );
OAI2BB2XLTS U7683 ( .B0(n6389), .B1(n6835), .A0N(n6387), .A1N(
FPSENCOS_d_ff_Yn[1]), .Y(n2070) );
BUFX3TS U7684 ( .A(n6388), .Y(n6392) );
INVX1TS U7685 ( .A(FPSENCOS_d_ff_Xn[1]), .Y(n6397) );
AOI22X1TS U7686 ( .A0(n6392), .A1(n6835), .B0(n6397), .B1(n6539), .Y(n2069)
);
INVX2TS U7687 ( .A(n6386), .Y(n6531) );
OAI2BB2XLTS U7688 ( .B0(n6390), .B1(n6834), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[2]), .Y(n2068) );
BUFX3TS U7689 ( .A(n6387), .Y(n6534) );
OAI2BB2XLTS U7690 ( .B0(n6391), .B1(n6834), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[2]), .Y(n2067) );
AOI22X1TS U7691 ( .A0(n6392), .A1(n6834), .B0(n2401), .B1(n6539), .Y(n2066)
);
OAI2BB2XLTS U7692 ( .B0(n6390), .B1(n6833), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[3]), .Y(n2065) );
OAI2BB2XLTS U7693 ( .B0(n6389), .B1(n6833), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[3]), .Y(n2064) );
INVX1TS U7694 ( .A(FPSENCOS_d_ff_Xn[3]), .Y(n6400) );
AOI22X1TS U7695 ( .A0(n6392), .A1(n6833), .B0(n6400), .B1(n6539), .Y(n2063)
);
OAI2BB2XLTS U7696 ( .B0(n6543), .B1(n2280), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[4]), .Y(n2062) );
OAI2BB2XLTS U7697 ( .B0(n6389), .B1(n2280), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[4]), .Y(n2061) );
OAI2BB2XLTS U7698 ( .B0(n6523), .B1(n2280), .A0N(n6553), .A1N(
FPSENCOS_d_ff_Xn[4]), .Y(n2060) );
INVX2TS U7699 ( .A(n6386), .Y(n6395) );
OAI2BB2XLTS U7700 ( .B0(n6543), .B1(n6836), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[5]), .Y(n2059) );
BUFX3TS U7701 ( .A(n6387), .Y(n6443) );
OAI2BB2XLTS U7702 ( .B0(n6389), .B1(n6836), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[5]), .Y(n2058) );
INVX1TS U7703 ( .A(FPSENCOS_d_ff_Xn[5]), .Y(n6403) );
AOI22X1TS U7704 ( .A0(n6388), .A1(n6836), .B0(n6403), .B1(n6539), .Y(n2057)
);
OAI2BB2XLTS U7705 ( .B0(n6543), .B1(n6839), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[6]), .Y(n2056) );
OAI2BB2XLTS U7706 ( .B0(n6389), .B1(n6839), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[6]), .Y(n2055) );
AOI22X1TS U7707 ( .A0(n6388), .A1(n6839), .B0(n2440), .B1(n6539), .Y(n2054)
);
OAI2BB2XLTS U7708 ( .B0(n6543), .B1(n6840), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[7]), .Y(n2053) );
OAI2BB2XLTS U7709 ( .B0(n6389), .B1(n6840), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[7]), .Y(n2052) );
INVX1TS U7710 ( .A(FPSENCOS_d_ff_Xn[7]), .Y(n6405) );
AOI22X1TS U7711 ( .A0(n6388), .A1(n6840), .B0(n6405), .B1(n6539), .Y(n2051)
);
OAI2BB2XLTS U7712 ( .B0(n6543), .B1(n6659), .A0N(n6390), .A1N(
FPSENCOS_d_ff_Zn[8]), .Y(n2050) );
OAI2BB2XLTS U7713 ( .B0(n6389), .B1(n6659), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[8]), .Y(n2049) );
INVX2TS U7714 ( .A(n6388), .Y(n6555) );
OAI2BB2XLTS U7715 ( .B0(n6555), .B1(n6659), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[8]), .Y(n2048) );
OAI2BB2XLTS U7716 ( .B0(n6543), .B1(n6837), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[9]), .Y(n2047) );
OAI2BB2XLTS U7717 ( .B0(n6389), .B1(n6837), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[9]), .Y(n2046) );
OAI2BB2XLTS U7718 ( .B0(n6555), .B1(n6837), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[9]), .Y(n2045) );
OAI2BB2XLTS U7719 ( .B0(n6543), .B1(n6831), .A0N(n6390), .A1N(
FPSENCOS_d_ff_Zn[10]), .Y(n2044) );
OAI2BB2XLTS U7720 ( .B0(n6389), .B1(n6831), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[10]), .Y(n2043) );
BUFX3TS U7721 ( .A(n6392), .Y(n6541) );
AOI22X1TS U7722 ( .A0(n6541), .A1(n6831), .B0(n2447), .B1(n6528), .Y(n2042)
);
OAI2BB2XLTS U7723 ( .B0(n6543), .B1(n6662), .A0N(n6390), .A1N(
FPSENCOS_d_ff_Zn[11]), .Y(n2041) );
OAI2BB2XLTS U7724 ( .B0(n6393), .B1(n6662), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[11]), .Y(n2040) );
OAI2BB2XLTS U7725 ( .B0(n6555), .B1(n6662), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[11]), .Y(n2039) );
INVX2TS U7726 ( .A(n6386), .Y(n6394) );
OAI2BB2XLTS U7727 ( .B0(n6394), .B1(n6832), .A0N(n6390), .A1N(
FPSENCOS_d_ff_Zn[12]), .Y(n2038) );
OAI2BB2XLTS U7728 ( .B0(n6393), .B1(n6832), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[12]), .Y(n2037) );
INVX1TS U7729 ( .A(FPSENCOS_d_ff_Xn[12]), .Y(n6411) );
AOI22X1TS U7730 ( .A0(n6541), .A1(n6832), .B0(n6411), .B1(n6528), .Y(n2036)
);
OAI2BB2XLTS U7731 ( .B0(n6394), .B1(n6652), .A0N(n6390), .A1N(
FPSENCOS_d_ff_Zn[13]), .Y(n2035) );
OAI2BB2XLTS U7732 ( .B0(n6393), .B1(n6652), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[13]), .Y(n2034) );
AOI22X1TS U7733 ( .A0(n6392), .A1(n6652), .B0(n2424), .B1(n6528), .Y(n2033)
);
OAI2BB2XLTS U7734 ( .B0(n6394), .B1(n6830), .A0N(n6390), .A1N(
FPSENCOS_d_ff_Zn[14]), .Y(n2032) );
OAI2BB2XLTS U7735 ( .B0(n6393), .B1(n6830), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[14]), .Y(n2031) );
INVX1TS U7736 ( .A(FPSENCOS_d_ff_Xn[14]), .Y(n6416) );
AOI22X1TS U7737 ( .A0(n6541), .A1(n6830), .B0(n6416), .B1(n6528), .Y(n2030)
);
OAI2BB2XLTS U7738 ( .B0(n6394), .B1(n6634), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[15]), .Y(n2029) );
OAI2BB2XLTS U7739 ( .B0(n6389), .B1(n6634), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[15]), .Y(n2028) );
OAI2BB2XLTS U7740 ( .B0(n6555), .B1(n6634), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[15]), .Y(n2027) );
OAI2BB2XLTS U7741 ( .B0(n6394), .B1(n6655), .A0N(n6390), .A1N(
FPSENCOS_d_ff_Zn[16]), .Y(n2026) );
OAI2BB2XLTS U7742 ( .B0(n6393), .B1(n6655), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[16]), .Y(n2025) );
AOI22X1TS U7743 ( .A0(n6392), .A1(n6655), .B0(n2414), .B1(n6539), .Y(n2024)
);
OAI2BB2XLTS U7744 ( .B0(n6394), .B1(n6650), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[17]), .Y(n2023) );
OAI2BB2XLTS U7745 ( .B0(n6393), .B1(n6650), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[17]), .Y(n2022) );
INVX1TS U7746 ( .A(FPSENCOS_d_ff_Xn[17]), .Y(n6419) );
AOI22X1TS U7747 ( .A0(n6392), .A1(n6650), .B0(n6419), .B1(n6539), .Y(n2021)
);
OAI2BB2XLTS U7748 ( .B0(n6394), .B1(n6638), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[18]), .Y(n2020) );
OAI2BB2XLTS U7749 ( .B0(n6393), .B1(n6638), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[18]), .Y(n2019) );
OAI2BB2XLTS U7750 ( .B0(n6555), .B1(n6638), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[18]), .Y(n2018) );
OAI2BB2XLTS U7751 ( .B0(n6394), .B1(n6644), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[19]), .Y(n2017) );
OAI2BB2XLTS U7752 ( .B0(n6393), .B1(n6644), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[19]), .Y(n2016) );
INVX1TS U7753 ( .A(FPSENCOS_d_ff_Xn[19]), .Y(n6422) );
AOI22X1TS U7754 ( .A0(n6392), .A1(n6644), .B0(n6422), .B1(n6539), .Y(n2015)
);
OAI2BB2XLTS U7755 ( .B0(n6394), .B1(n6647), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[20]), .Y(n2014) );
OAI2BB2XLTS U7756 ( .B0(n6393), .B1(n6647), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[20]), .Y(n2013) );
INVX1TS U7757 ( .A(FPSENCOS_d_ff_Xn[20]), .Y(n6424) );
AOI22X1TS U7758 ( .A0(n6541), .A1(n6647), .B0(n6424), .B1(n6539), .Y(n2012)
);
OAI2BB2XLTS U7759 ( .B0(n6394), .B1(n6641), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[21]), .Y(n2011) );
OAI2BB2XLTS U7760 ( .B0(n6535), .B1(n6641), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[21]), .Y(n2010) );
OAI2BB2XLTS U7761 ( .B0(n6555), .B1(n6641), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[21]), .Y(n2009) );
OAI2BB2XLTS U7762 ( .B0(n6538), .B1(n6631), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[22]), .Y(n2008) );
OAI2BB2XLTS U7763 ( .B0(n6535), .B1(n6631), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[22]), .Y(n2007) );
OAI2BB2XLTS U7764 ( .B0(n6555), .B1(n6631), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[22]), .Y(n2006) );
OAI2BB2XLTS U7765 ( .B0(n6396), .B1(n2301), .A0N(FPSENCOS_d_ff_Xn[0]), .A1N(
n6427), .Y(n2005) );
AOI22X1TS U7766 ( .A0(n6414), .A1(n6397), .B0(n6398), .B1(n6413), .Y(n2003)
);
OAI2BB2XLTS U7767 ( .B0(n6442), .B1(n6398), .A0N(n6408), .A1N(
FPSENCOS_d_ff3_sh_x_out[1]), .Y(n2002) );
AOI22X1TS U7768 ( .A0(n6414), .A1(n2401), .B0(n6399), .B1(n6413), .Y(n2001)
);
AOI22X1TS U7769 ( .A0(n6414), .A1(n6400), .B0(n6401), .B1(n6413), .Y(n1999)
);
OAI2BB2XLTS U7770 ( .B0(n6442), .B1(n6401), .A0N(n6408), .A1N(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n1998) );
BUFX3TS U7771 ( .A(n6445), .Y(n6468) );
OAI2BB2XLTS U7772 ( .B0(n6402), .B1(n2301), .A0N(FPSENCOS_d_ff_Xn[4]), .A1N(
n6468), .Y(n1997) );
INVX2TS U7773 ( .A(n6448), .Y(n6429) );
OAI2BB2XLTS U7774 ( .B0(n6429), .B1(n6402), .A0N(n6408), .A1N(
FPSENCOS_d_ff3_sh_x_out[4]), .Y(n1996) );
AOI22X1TS U7775 ( .A0(n6414), .A1(n6403), .B0(n6404), .B1(n6413), .Y(n1995)
);
INVX2TS U7776 ( .A(n6448), .Y(n6440) );
OAI2BB2XLTS U7777 ( .B0(n6429), .B1(n6404), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1994) );
AOI22X1TS U7778 ( .A0(n6414), .A1(n2440), .B0(n2422), .B1(n6413), .Y(n1993)
);
OAI2BB2XLTS U7779 ( .B0(n6429), .B1(n2422), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[6]), .Y(n1992) );
AOI22X1TS U7780 ( .A0(n6414), .A1(n6405), .B0(n6406), .B1(n2302), .Y(n1991)
);
OAI2BB2XLTS U7781 ( .B0(n6429), .B1(n6406), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1990) );
OAI2BB2XLTS U7782 ( .B0(n6407), .B1(n2301), .A0N(FPSENCOS_d_ff_Xn[8]), .A1N(
n6468), .Y(n1989) );
OAI2BB2XLTS U7783 ( .B0(n6429), .B1(n6407), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[8]), .Y(n1988) );
OAI2BB2XLTS U7784 ( .B0(n6409), .B1(n2301), .A0N(FPSENCOS_d_ff_Xn[9]), .A1N(
n6468), .Y(n1987) );
OAI2BB2XLTS U7785 ( .B0(n6429), .B1(n6409), .A0N(n6408), .A1N(
FPSENCOS_d_ff3_sh_x_out[9]), .Y(n1986) );
BUFX3TS U7786 ( .A(n6414), .Y(n6452) );
AOI22X1TS U7787 ( .A0(n6452), .A1(n2447), .B0(n2449), .B1(n6413), .Y(n1985)
);
INVX2TS U7788 ( .A(n6449), .Y(n6470) );
OAI2BB2XLTS U7789 ( .B0(n6470), .B1(n2449), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[10]), .Y(n1984) );
OAI2BB2XLTS U7790 ( .B0(n6410), .B1(n2301), .A0N(FPSENCOS_d_ff_Xn[11]),
.A1N(n6427), .Y(n1983) );
OAI2BB2XLTS U7791 ( .B0(n6470), .B1(n6410), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1982) );
AOI22X1TS U7792 ( .A0(n6452), .A1(n6411), .B0(n6412), .B1(n6413), .Y(n1981)
);
OAI2BB2XLTS U7793 ( .B0(n6442), .B1(n6412), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[12]), .Y(n1980) );
AOI22X1TS U7794 ( .A0(n6452), .A1(n2424), .B0(n2425), .B1(n6413), .Y(n1979)
);
OAI2BB2XLTS U7795 ( .B0(n6470), .B1(n2425), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1978) );
INVX2TS U7796 ( .A(n6415), .Y(n6430) );
AOI22X1TS U7797 ( .A0(n4723), .A1(n6416), .B0(n6417), .B1(n6469), .Y(n1977)
);
OAI2BB2XLTS U7798 ( .B0(n6429), .B1(n6417), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1976) );
OAI2BB2XLTS U7799 ( .B0(n6418), .B1(n2301), .A0N(FPSENCOS_d_ff_Xn[15]),
.A1N(n6468), .Y(n1975) );
OAI2BB2XLTS U7800 ( .B0(n6470), .B1(n6418), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1974) );
AOI22X1TS U7801 ( .A0(n4723), .A1(n2414), .B0(n2417), .B1(n6431), .Y(n1973)
);
OAI2BB2XLTS U7802 ( .B0(n6470), .B1(n2417), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1972) );
AOI22X1TS U7803 ( .A0(n4723), .A1(n6419), .B0(n6420), .B1(n6430), .Y(n1971)
);
OAI2BB2XLTS U7804 ( .B0(n6429), .B1(n6420), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1970) );
OAI2BB2XLTS U7805 ( .B0(n6421), .B1(n6439), .A0N(FPSENCOS_d_ff_Xn[18]),
.A1N(n6427), .Y(n1969) );
OAI2BB2XLTS U7806 ( .B0(n6470), .B1(n6421), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1968) );
AOI22X1TS U7807 ( .A0(n6452), .A1(n6422), .B0(n6423), .B1(n6453), .Y(n1967)
);
OAI2BB2XLTS U7808 ( .B0(n6470), .B1(n6423), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1966) );
AOI22X1TS U7809 ( .A0(n4723), .A1(n6424), .B0(n6425), .B1(n6431), .Y(n1965)
);
OAI2BB2XLTS U7810 ( .B0(n6442), .B1(n6425), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1964) );
OAI2BB2XLTS U7811 ( .B0(n6426), .B1(n6439), .A0N(FPSENCOS_d_ff_Xn[21]),
.A1N(n6427), .Y(n1963) );
OAI2BB2XLTS U7812 ( .B0(n6429), .B1(n6426), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[21]), .Y(n1962) );
OAI2BB2XLTS U7813 ( .B0(n2416), .B1(n2301), .A0N(FPSENCOS_d_ff_Xn[22]),
.A1N(n6427), .Y(n1961) );
OAI2BB2XLTS U7814 ( .B0(n6429), .B1(n2416), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1960) );
INVX1TS U7815 ( .A(FPSENCOS_d_ff_Xn[24]), .Y(n6525) );
AOI22X1TS U7816 ( .A0(n4723), .A1(n6525), .B0(n6873), .B1(n4731), .Y(n1958)
);
AOI22X1TS U7817 ( .A0(n6445), .A1(n2452), .B0(n6874), .B1(n6431), .Y(n1957)
);
INVX1TS U7818 ( .A(FPSENCOS_d_ff_Xn[26]), .Y(n6529) );
AOI22X1TS U7819 ( .A0(n4558), .A1(n6529), .B0(n6875), .B1(n4731), .Y(n1956)
);
INVX1TS U7820 ( .A(FPSENCOS_d_ff_Xn[27]), .Y(n6532) );
AOI22X1TS U7821 ( .A0(n6445), .A1(n6532), .B0(n6872), .B1(n6431), .Y(n1955)
);
INVX1TS U7822 ( .A(FPSENCOS_d_ff_Xn[28]), .Y(n6536) );
AOI22X1TS U7823 ( .A0(n4723), .A1(n6536), .B0(n6838), .B1(n4731), .Y(n1954)
);
AOI22X1TS U7824 ( .A0(n6414), .A1(n2431), .B0(n6871), .B1(n4731), .Y(n1953)
);
AOI21X1TS U7825 ( .A0(intadd_518_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n6433),
.Y(n6432) );
AOI21X1TS U7826 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n6436), .B0(n6435), .Y(
n6437) );
OAI2BB2XLTS U7827 ( .B0(n6441), .B1(n6439), .A0N(n6468), .A1N(
FPSENCOS_d_ff_Xn[31]), .Y(n1943) );
OAI2BB2XLTS U7828 ( .B0(n6442), .B1(n6441), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1942) );
OAI2BB2XLTS U7829 ( .B0(n6538), .B1(n6554), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[31]), .Y(n1909) );
OAI2BB2XLTS U7830 ( .B0(n6535), .B1(n6554), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[31]), .Y(n1908) );
OAI2BB2XLTS U7831 ( .B0(n6450), .B1(n2281), .A0N(n6459), .A1N(
FPSENCOS_d_ff2_Y[0]), .Y(n1906) );
OAI2BB2XLTS U7832 ( .B0(n6450), .B1(n2428), .A0N(n6459), .A1N(
FPSENCOS_d_ff2_Y[1]), .Y(n1904) );
BUFX3TS U7833 ( .A(n6445), .Y(n6447) );
OAI2BB2XLTS U7834 ( .B0(n6450), .B1(n2282), .A0N(n6459), .A1N(
FPSENCOS_d_ff2_Y[2]), .Y(n1902) );
OAI2BB2XLTS U7835 ( .B0(n4554), .B1(n2435), .A0N(n6459), .A1N(
FPSENCOS_d_ff2_Y[4]), .Y(n1898) );
INVX2TS U7836 ( .A(n6439), .Y(n6446) );
OAI2BB2XLTS U7837 ( .B0(n6450), .B1(n2439), .A0N(n6459), .A1N(
FPSENCOS_d_ff2_Y[6]), .Y(n1894) );
INVX2TS U7838 ( .A(n6449), .Y(n6451) );
OAI2BB2XLTS U7839 ( .B0(n6450), .B1(n2419), .A0N(n6444), .A1N(
FPSENCOS_d_ff2_Y[8]), .Y(n1890) );
OAI2BB2XLTS U7840 ( .B0(n4554), .B1(n2436), .A0N(n6459), .A1N(
FPSENCOS_d_ff2_Y[9]), .Y(n1888) );
OAI2BB2XLTS U7841 ( .B0(n6450), .B1(n2446), .A0N(n6459), .A1N(
FPSENCOS_d_ff2_Y[10]), .Y(n1886) );
OAI2BB2XLTS U7842 ( .B0(n4554), .B1(n2453), .A0N(n6444), .A1N(
FPSENCOS_d_ff2_Y[12]), .Y(n1882) );
BUFX3TS U7843 ( .A(n6445), .Y(n6454) );
INVX2TS U7844 ( .A(n6415), .Y(n6453) );
OAI2BB2XLTS U7845 ( .B0(n6450), .B1(n6876), .A0N(n6449), .A1N(
FPSENCOS_d_ff2_Y[21]), .Y(n1864) );
NAND2X1TS U7846 ( .A(FPSENCOS_d_ff2_Y[23]), .B(n2300), .Y(n6458) );
AOI32X1TS U7847 ( .A0(intadd_517_CI), .A1(n6449), .A2(n6458), .B0(n6457),
.B1(n6456), .Y(n1853) );
OAI2BB2XLTS U7848 ( .B0(n4554), .B1(n2445), .A0N(n6459), .A1N(
intadd_517_SUM_2_), .Y(n1850) );
AOI21X1TS U7849 ( .A0(intadd_517_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n6461),
.Y(n6460) );
NAND2X1TS U7850 ( .A(n6461), .B(n6841), .Y(n6463) );
AOI21X1TS U7851 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n6463), .B0(n6466), .Y(
n6465) );
AOI22X1TS U7852 ( .A0(Data_2[3]), .A1(n4996), .B0(FPADDSUB_intDY_EWSW[3]),
.B1(n6479), .Y(n6473) );
AOI22X1TS U7853 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n6485),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n6472) );
NAND2X1TS U7854 ( .A(n6474), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n6491) );
AOI22X1TS U7855 ( .A0(Data_2[5]), .A1(n6518), .B0(FPADDSUB_intDY_EWSW[5]),
.B1(n6479), .Y(n6476) );
AOI22X1TS U7856 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n6485),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n6475) );
NAND2X1TS U7857 ( .A(n6474), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n6486) );
AOI22X1TS U7858 ( .A0(Data_2[7]), .A1(n4996), .B0(FPADDSUB_intDY_EWSW[7]),
.B1(n6479), .Y(n6478) );
AOI22X1TS U7859 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n6477) );
NAND2X1TS U7860 ( .A(n4999), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n6480) );
AOI22X1TS U7861 ( .A0(Data_2[11]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[11]),
.B1(n6479), .Y(n6482) );
AOI22X1TS U7862 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n6485),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n6481) );
AOI22X1TS U7863 ( .A0(Data_2[13]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[13]),
.B1(n6505), .Y(n6484) );
AOI22X1TS U7864 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n6483) );
NAND2X1TS U7865 ( .A(n4999), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n6497) );
AOI22X1TS U7866 ( .A0(Data_2[14]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[14]),
.B1(n6505), .Y(n6488) );
AOI22X1TS U7867 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n6485),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n6487) );
AOI22X1TS U7868 ( .A0(Data_2[15]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[15]),
.B1(n6505), .Y(n6490) );
AOI22X1TS U7869 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n6489) );
NAND2X1TS U7870 ( .A(n4999), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n6502) );
AOI22X1TS U7871 ( .A0(Data_2[16]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[16]),
.B1(n6505), .Y(n6493) );
AOI22X1TS U7872 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n6492) );
AOI22X1TS U7873 ( .A0(Data_2[17]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[17]),
.B1(n6505), .Y(n6496) );
AOI22X1TS U7874 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n6495) );
AOI22X1TS U7875 ( .A0(Data_2[18]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[18]),
.B1(n6505), .Y(n6499) );
AOI22X1TS U7876 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n6498) );
AOI22X1TS U7877 ( .A0(Data_2[19]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[19]),
.B1(n6505), .Y(n6501) );
AOI22X1TS U7878 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n6500) );
NAND2X1TS U7879 ( .A(n4999), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n6506) );
AOI22X1TS U7880 ( .A0(Data_2[20]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[20]),
.B1(n6505), .Y(n6504) );
AOI22X1TS U7881 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n6503) );
AOI22X1TS U7882 ( .A0(Data_2[22]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[22]),
.B1(n6505), .Y(n6508) );
AOI22X1TS U7883 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n6507) );
AOI22X1TS U7884 ( .A0(Data_2[27]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[27]),
.B1(n6548), .Y(n6512) );
AOI22X1TS U7885 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n6511) );
NAND2X1TS U7886 ( .A(n4999), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n6515) );
AOI22X1TS U7887 ( .A0(Data_2[28]), .A1(n6518), .B0(FPADDSUB_intDY_EWSW[28]),
.B1(n6548), .Y(n6514) );
AOI22X1TS U7888 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n6549),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n6513) );
AOI22X1TS U7889 ( .A0(Data_2[29]), .A1(n4996), .B0(FPADDSUB_intDY_EWSW[29]),
.B1(n6548), .Y(n6517) );
AOI22X1TS U7890 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n6549),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n6516) );
AOI22X1TS U7891 ( .A0(Data_2[30]), .A1(n6518), .B0(FPADDSUB_intDY_EWSW[30]),
.B1(n6548), .Y(n6520) );
AOI22X1TS U7892 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[30]), .B0(n6549),
.B1(FPSENCOS_d_ff3_sh_x_out[30]), .Y(n6519) );
NAND2X1TS U7893 ( .A(n6520), .B(n6519), .Y(n1813) );
OAI22X1TS U7894 ( .A0(n6522), .A1(n6521), .B0(n5265), .B1(n2504), .Y(n1812)
);
OAI2BB2XLTS U7895 ( .B0(n6538), .B1(n6524), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[23]), .Y(n1786) );
OAI2BB2XLTS U7896 ( .B0(n6535), .B1(n6524), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[23]), .Y(n1785) );
OAI2BB2XLTS U7897 ( .B0(n6555), .B1(n6524), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[23]), .Y(n1784) );
OAI2BB2XLTS U7898 ( .B0(n6538), .B1(n6526), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[24]), .Y(n1783) );
OAI2BB2XLTS U7899 ( .B0(n6535), .B1(n6526), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[24]), .Y(n1782) );
AOI22X1TS U7900 ( .A0(n6541), .A1(n6526), .B0(n6525), .B1(n6528), .Y(n1781)
);
OAI2BB2XLTS U7901 ( .B0(n6538), .B1(n6527), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[25]), .Y(n1780) );
OAI2BB2XLTS U7902 ( .B0(n6535), .B1(n6527), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[25]), .Y(n1779) );
AOI22X1TS U7903 ( .A0(n6541), .A1(n6527), .B0(n2452), .B1(n6528), .Y(n1778)
);
OAI2BB2XLTS U7904 ( .B0(n6538), .B1(n6530), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[26]), .Y(n1777) );
OAI2BB2XLTS U7905 ( .B0(n6535), .B1(n6530), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[26]), .Y(n1776) );
AOI22X1TS U7906 ( .A0(n6541), .A1(n6530), .B0(n6529), .B1(n6528), .Y(n1775)
);
OAI2BB2XLTS U7907 ( .B0(n6538), .B1(n6533), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[27]), .Y(n1774) );
OAI2BB2XLTS U7908 ( .B0(n6535), .B1(n6533), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[27]), .Y(n1773) );
AOI22X1TS U7909 ( .A0(n6541), .A1(n6533), .B0(n6532), .B1(n6528), .Y(n1772)
);
OAI2BB2XLTS U7910 ( .B0(n6538), .B1(n6537), .A0N(n6542), .A1N(
FPSENCOS_d_ff_Zn[28]), .Y(n1771) );
OAI2BB2XLTS U7911 ( .B0(n6535), .B1(n6537), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[28]), .Y(n1770) );
AOI22X1TS U7912 ( .A0(n6541), .A1(n6537), .B0(n6536), .B1(n6528), .Y(n1769)
);
OAI2BB2XLTS U7913 ( .B0(n6538), .B1(n6540), .A0N(n6542), .A1N(
FPSENCOS_d_ff_Zn[29]), .Y(n1768) );
AOI22X1TS U7914 ( .A0(n6541), .A1(n6540), .B0(n2431), .B1(n6528), .Y(n1766)
);
OAI2BB2XLTS U7915 ( .B0(n6543), .B1(n2451), .A0N(n6542), .A1N(
FPSENCOS_d_ff_Zn[30]), .Y(n1765) );
AOI22X1TS U7916 ( .A0(operation[0]), .A1(n4996), .B0(FPADDSUB_intAS), .B1(
n6548), .Y(n6547) );
OAI21XLTS U7917 ( .A0(FPSENCOS_cont_var_out[0]), .A1(FPSENCOS_d_ff3_sign_out), .B0(n6545), .Y(n6546) );
OAI2BB2XLTS U7918 ( .B0(n6555), .B1(n2451), .A0N(n6553), .A1N(
FPSENCOS_d_ff_Xn[30]), .Y(n1729) );
AOI22X1TS U7919 ( .A0(Data_2[31]), .A1(n4996), .B0(FPADDSUB_intDY_EWSW[31]),
.B1(n6548), .Y(n6552) );
AOI22X1TS U7920 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[31]), .B0(n6549),
.B1(FPSENCOS_d_ff3_sh_x_out[31]), .Y(n6551) );
NAND2X1TS U7921 ( .A(n6552), .B(n6551), .Y(n1728) );
OAI2BB2XLTS U7922 ( .B0(n6555), .B1(n6554), .A0N(n6553), .A1N(
FPSENCOS_d_ff_Xn[31]), .Y(n1727) );
AOI22X1TS U7923 ( .A0(n6557), .A1(FPSENCOS_d_ff_Xn[31]), .B0(
FPSENCOS_d_ff_Yn[31]), .B1(n6556), .Y(n6560) );
XOR2X1TS U7924 ( .A(n6560), .B(n6559), .Y(n6561) );
OAI2BB2XLTS U7925 ( .B0(n6562), .B1(n6561), .A0N(n6562), .A1N(
cordic_result[31]), .Y(n1695) );
NOR2XLTS U7926 ( .A(n6757), .B(n6787), .Y(n6563) );
OAI22X1TS U7927 ( .A0(n6564), .A1(n6563), .B0(n6751), .B1(n6787), .Y(n6565)
);
NOR4X1TS U7928 ( .A(n6567), .B(n2346), .C(FPMULT_Op_MX[7]), .D(
DP_OP_501J223_127_5235_n944), .Y(n6576) );
NOR4X1TS U7929 ( .A(n6569), .B(n2481), .C(n6568), .D(FPMULT_Op_MX[2]), .Y(
n6575) );
NOR4X1TS U7930 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[5]), .C(
FPMULT_Op_MX[18]), .D(n6570), .Y(n6574) );
NOR4X1TS U7931 ( .A(n2292), .B(n6572), .C(n2287), .D(FPMULT_Op_MX[19]), .Y(
n6573) );
NAND4XLTS U7932 ( .A(n6576), .B(n6575), .C(n6574), .D(n6573), .Y(n6603) );
NOR4X1TS U7933 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_Op_MX[27]), .C(
FPMULT_Op_MX[26]), .D(FPMULT_Op_MX[25]), .Y(n6583) );
NOR4X1TS U7934 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[13]), .C(
FPMULT_Op_MX[12]), .D(FPMULT_Op_MX[14]), .Y(n6582) );
NOR4X1TS U7935 ( .A(n2285), .B(FPMULT_Op_MX[17]), .C(FPMULT_Op_MX[30]), .D(
FPMULT_Op_MX[29]), .Y(n6581) );
NAND4XLTS U7936 ( .A(n6583), .B(n6582), .C(n6581), .D(n6580), .Y(n6602) );
NOR4X1TS U7937 ( .A(n2383), .B(n2228), .C(n5642), .D(n6584), .Y(n6592) );
NOR4X1TS U7938 ( .A(DP_OP_501J223_127_5235_n903), .B(n2220), .C(n6955), .D(
n2291), .Y(n6591) );
NOR4X1TS U7939 ( .A(n2289), .B(FPMULT_Op_MY[4]), .C(n6587), .D(
FPMULT_Op_MY[2]), .Y(n6590) );
NOR4X1TS U7940 ( .A(n2201), .B(n5643), .C(FPMULT_Op_MY[8]), .D(n6753), .Y(
n6589) );
NAND4XLTS U7941 ( .A(n6592), .B(n6591), .C(n6590), .D(n6589), .Y(n6601) );
NOR4X1TS U7942 ( .A(FPMULT_Op_MY[28]), .B(FPMULT_Op_MY[27]), .C(
FPMULT_Op_MY[26]), .D(FPMULT_Op_MY[25]), .Y(n6599) );
NOR4X1TS U7943 ( .A(n2290), .B(n6594), .C(FPMULT_Op_MY[14]), .D(
FPMULT_Op_MY[12]), .Y(n6598) );
NOR4X1TS U7944 ( .A(n6595), .B(FPMULT_Op_MY[13]), .C(FPMULT_Op_MY[30]), .D(
FPMULT_Op_MY[29]), .Y(n6597) );
NAND4XLTS U7945 ( .A(n6599), .B(n6598), .C(n6597), .D(n6596), .Y(n6600) );
OA22X1TS U7946 ( .A0(n6603), .A1(n6602), .B0(n6601), .B1(n6600), .Y(n6604)
);
OAI2BB2XLTS U7947 ( .B0(n6605), .B1(n6604), .A0N(n6605), .A1N(
FPMULT_zero_flag), .Y(n1625) );
OA22X1TS U7948 ( .A0(n6615), .A1(mult_result[23]), .B0(
FPMULT_exp_oper_result[0]), .B1(n6613), .Y(n1584) );
OA22X1TS U7949 ( .A0(n6607), .A1(mult_result[24]), .B0(
FPMULT_exp_oper_result[1]), .B1(n6608), .Y(n1583) );
OA22X1TS U7950 ( .A0(n6607), .A1(mult_result[25]), .B0(
FPMULT_exp_oper_result[2]), .B1(n6608), .Y(n1582) );
OA22X1TS U7951 ( .A0(n6607), .A1(mult_result[26]), .B0(
FPMULT_exp_oper_result[3]), .B1(n6608), .Y(n1581) );
OA22X1TS U7952 ( .A0(n6607), .A1(mult_result[27]), .B0(
FPMULT_exp_oper_result[4]), .B1(n6608), .Y(n1580) );
OA22X1TS U7953 ( .A0(n6607), .A1(mult_result[28]), .B0(
FPMULT_exp_oper_result[5]), .B1(n6608), .Y(n1579) );
OA22X1TS U7954 ( .A0(n6615), .A1(mult_result[29]), .B0(
FPMULT_exp_oper_result[6]), .B1(n6608), .Y(n1578) );
OA22X1TS U7955 ( .A0(n6615), .A1(mult_result[30]), .B0(
FPMULT_exp_oper_result[7]), .B1(n6608), .Y(n1577) );
INVX2TS U7956 ( .A(n6615), .Y(n6614) );
OAI2BB1X1TS U7957 ( .A0N(mult_result[31]), .A1N(n6614), .B0(n6611), .Y(n1576) );
INVX2TS U7958 ( .A(n6613), .Y(n6612) );
INVX2TS U7959 ( .A(n6613), .Y(n6616) );
INVX2TS U7960 ( .A(n6615), .Y(n6618) );
INVX2TS U7961 ( .A(n6738), .Y(n6739) );
BUFX3TS U7962 ( .A(n6656), .Y(n6741) );
BUFX3TS U7963 ( .A(n6656), .Y(n6736) );
INVX2TS U7964 ( .A(n6738), .Y(n6635) );
INVX2TS U7965 ( .A(n6741), .Y(n6731) );
OAI2BB2XLTS U7966 ( .B0(n6739), .B1(n6820), .A0N(n6731), .A1N(
intadd_516_SUM_0_), .Y(n1476) );
XNOR2X1TS U7967 ( .A(FPADDSUB_DMP_EXP_EWSW[27]), .B(
FPADDSUB_DmP_EXP_EWSW[27]), .Y(n6621) );
XOR2X1TS U7968 ( .A(intadd_516_n1), .B(n6621), .Y(n6622) );
AO22XLTS U7969 ( .A0(n2317), .A1(FPADDSUB_DMP_SFG[23]), .B0(n2501), .B1(
FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n1454) );
INVX2TS U7970 ( .A(n6624), .Y(n6709) );
AO22XLTS U7971 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[24]), .B0(n2501), .B1(FPADDSUB_DMP_exp_NRM_EW[1]),
.Y(n1449) );
INVX2TS U7972 ( .A(n6738), .Y(n6657) );
OA21XLTS U7973 ( .A0(n7060), .A1(underflow_flag_addsubt), .B0(n6626), .Y(
n1412) );
INVX2TS U7974 ( .A(n6627), .Y(n6664) );
INVX4TS U7975 ( .A(n6629), .Y(n6660) );
OAI22X1TS U7976 ( .A0(n7060), .A1(n6631), .B0(n6630), .B1(n6660), .Y(n1408)
);
OAI22X1TS U7977 ( .A0(n2366), .A1(n6634), .B0(n6633), .B1(n2374), .Y(n1405)
);
OAI22X1TS U7978 ( .A0(n7060), .A1(n6638), .B0(n6637), .B1(n6660), .Y(n1402)
);
OAI22X1TS U7979 ( .A0(n2366), .A1(n6641), .B0(n6640), .B1(n2374), .Y(n1399)
);
OAI22X1TS U7980 ( .A0(n2366), .A1(n6644), .B0(n6643), .B1(n6660), .Y(n1396)
);
OAI22X1TS U7981 ( .A0(n2366), .A1(n6647), .B0(n6646), .B1(n2374), .Y(n1393)
);
OAI2BB2XLTS U7982 ( .B0(n6739), .B1(n6854), .A0N(n6731), .A1N(
FPADDSUB_DmP_EXP_EWSW[20]), .Y(n1391) );
OAI22X1TS U7983 ( .A0(n2366), .A1(n6650), .B0(n6649), .B1(n2374), .Y(n1390)
);
OAI22X1TS U7984 ( .A0(n2366), .A1(n6652), .B0(n6651), .B1(n6660), .Y(n1381)
);
OAI22X1TS U7985 ( .A0(n2366), .A1(n6655), .B0(n6654), .B1(n6660), .Y(n1378)
);
OAI22X1TS U7986 ( .A0(n2366), .A1(n6659), .B0(n6658), .B1(n2374), .Y(n1375)
);
INVX2TS U7987 ( .A(n6738), .Y(n6744) );
BUFX3TS U7988 ( .A(n6738), .Y(n6743) );
OAI22X1TS U7989 ( .A0(n2366), .A1(n6662), .B0(n6661), .B1(n2374), .Y(n1372)
);
OAI22X1TS U7990 ( .A0(n6730), .A1(n6830), .B0(n6665), .B1(n6660), .Y(n1369)
);
OAI22X1TS U7991 ( .A0(n6730), .A1(n6831), .B0(n6666), .B1(n6728), .Y(n1366)
);
OAI22X1TS U7992 ( .A0(n7060), .A1(n6832), .B0(n6667), .B1(n2374), .Y(n1363)
);
CLKXOR2X2TS U7993 ( .A(FPADDSUB_intDY_EWSW[31]), .B(FPADDSUB_intAS), .Y(
n6717) );
NOR2BX1TS U7994 ( .AN(FPADDSUB_intDX_EWSW[31]), .B(n6668), .Y(n6716) );
AOI22X1TS U7995 ( .A0(n2215), .A1(FPADDSUB_intDY_EWSW[27]), .B0(n2279), .B1(
FPADDSUB_intDY_EWSW[15]), .Y(n6669) );
AOI22X1TS U7996 ( .A0(n2413), .A1(FPADDSUB_intDY_EWSW[13]), .B0(n2411), .B1(
FPADDSUB_intDY_EWSW[6]), .Y(n6670) );
AOI22X1TS U7997 ( .A0(n2464), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n6804), .B1(
FPADDSUB_intDY_EWSW[26]), .Y(n6671) );
AOI22X1TS U7998 ( .A0(n2231), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n2275), .B1(
FPADDSUB_intDY_EWSW[0]), .Y(n6672) );
NOR4X1TS U7999 ( .A(n6676), .B(n6675), .C(n6674), .D(n6673), .Y(n6704) );
AOI22X1TS U8000 ( .A0(n2407), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n2269), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n6677) );
AOI22X1TS U8001 ( .A0(n2232), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n2272), .B1(
FPADDSUB_intDY_EWSW[18]), .Y(n6678) );
AOI22X1TS U8002 ( .A0(n6805), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n2434), .B1(
FPADDSUB_intDY_EWSW[1]), .Y(n6679) );
AOI22X1TS U8003 ( .A0(n2277), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n2234), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n6680) );
NOR4X1TS U8004 ( .A(n6684), .B(n6683), .C(n6682), .D(n6681), .Y(n6703) );
AOI22X1TS U8005 ( .A0(n6812), .A1(FPADDSUB_intDY_EWSW[29]), .B0(n2278), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n6685) );
AOI22X1TS U8006 ( .A0(n6811), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n2408), .B1(
FPADDSUB_intDY_EWSW[16]), .Y(n6686) );
OAI22X1TS U8007 ( .A0(n2270), .A1(FPADDSUB_intDY_EWSW[8]), .B0(n6810), .B1(
FPADDSUB_intDY_EWSW[30]), .Y(n6687) );
OAI22X1TS U8008 ( .A0(n2230), .A1(FPADDSUB_intDY_EWSW[11]), .B0(n2271), .B1(
FPADDSUB_intDY_EWSW[19]), .Y(n6689) );
AOI221X1TS U8009 ( .A0(n2230), .A1(FPADDSUB_intDY_EWSW[11]), .B0(
FPADDSUB_intDY_EWSW[19]), .B1(n2271), .C0(n6689), .Y(n6697) );
OAI22X1TS U8010 ( .A0(n2233), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n2274), .B1(
FPADDSUB_intDY_EWSW[20]), .Y(n6690) );
OAI22X1TS U8011 ( .A0(n2273), .A1(FPADDSUB_intDY_EWSW[2]), .B0(n6692), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n6691) );
OAI22X1TS U8012 ( .A0(n2432), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n6803), .B1(
FPADDSUB_intDY_EWSW[24]), .Y(n6693) );
NOR4X1TS U8013 ( .A(n6701), .B(n6700), .C(n6699), .D(n6698), .Y(n6702) );
OAI22X1TS U8014 ( .A0(n6706), .A1(n6717), .B0(n6716), .B1(n6705), .Y(n6707)
);
OAI2BB1X1TS U8015 ( .A0N(FPADDSUB_SIGN_FLAG_EXP), .A1N(n6708), .B0(n6707),
.Y(n1362) );
AOI21X1TS U8016 ( .A0(n6717), .A1(n6716), .B0(n6715), .Y(n1355) );
OAI22X1TS U8017 ( .A0(n6730), .A1(n6833), .B0(n6719), .B1(n2374), .Y(n1329)
);
OAI22X1TS U8018 ( .A0(n6730), .A1(n6834), .B0(n6721), .B1(n6660), .Y(n1313)
);
INVX2TS U8019 ( .A(n6738), .Y(n6734) );
BUFX3TS U8020 ( .A(n6738), .Y(n6732) );
OAI22X1TS U8021 ( .A0(n6730), .A1(n2367), .B0(n6722), .B1(n2374), .Y(n1299)
);
OAI22X1TS U8022 ( .A0(n6730), .A1(n6835), .B0(n6724), .B1(n2374), .Y(n1292)
);
OAI2BB2XLTS U8023 ( .B0(n6739), .B1(n6855), .A0N(n6731), .A1N(
FPADDSUB_DmP_EXP_EWSW[1]), .Y(n1290) );
OAI22X1TS U8024 ( .A0(n6730), .A1(n6837), .B0(n6725), .B1(n6660), .Y(n1285)
);
OAI2BB2XLTS U8025 ( .B0(n6739), .B1(n6814), .A0N(n6731), .A1N(
FPADDSUB_DmP_EXP_EWSW[9]), .Y(n1283) );
OAI22X1TS U8026 ( .A0(n6730), .A1(n6836), .B0(n6729), .B1(n6660), .Y(n1278)
);
OAI2BB2XLTS U8027 ( .B0(n6739), .B1(n6815), .A0N(n6731), .A1N(
FPADDSUB_DmP_EXP_EWSW[12]), .Y(n1270) );
INVX2TS U8028 ( .A(n6738), .Y(n6742) );
INVX2TS U8029 ( .A(n6733), .Y(n6737) );
CMPR42X2TS U8030 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]), .C(n6747),
.D(DP_OP_499J223_125_1651_n299), .ICI(DP_OP_499J223_125_1651_n232),
.S(DP_OP_499J223_125_1651_n231), .ICO(DP_OP_499J223_125_1651_n229),
.CO(DP_OP_499J223_125_1651_n230) );
CMPR42X1TS U8031 ( .A(DP_OP_502J223_128_4510_n172), .B(
DP_OP_502J223_128_4510_n186), .C(DP_OP_502J223_128_4510_n179), .D(
DP_OP_502J223_128_4510_n127), .ICI(DP_OP_502J223_128_4510_n126), .S(
DP_OP_502J223_128_4510_n123), .ICO(DP_OP_502J223_128_4510_n121), .CO(
DP_OP_502J223_128_4510_n122) );
CMPR42X1TS U8032 ( .A(DP_OP_500J223_126_4510_n172), .B(
DP_OP_500J223_126_4510_n186), .C(DP_OP_500J223_126_4510_n179), .D(
DP_OP_500J223_126_4510_n127), .ICI(DP_OP_500J223_126_4510_n126), .S(
DP_OP_500J223_126_4510_n123), .ICO(DP_OP_500J223_126_4510_n121), .CO(
DP_OP_500J223_126_4510_n122) );
endmodule
|
/*=============================================================================
M95XXX Serial SPI EEPROM Driver
=============================================================================*/
`include "M95XXX_Parameters.v"
//This defines the parameter file for M95080-W6, "W" or "G" F6SP36% process
//Any other M95xxx memory should define here the proper M95xxx parameter file
//`define tH_CLK `tC/2
//`define tL_CLK `tC/2
//=====================================
module M95XXX_DRV(
C,
D,
Q,
S,
W,
HOLD,
VCC,
VSS
);
//-------------------------------------
input Q;
output C,D,S,W,HOLD,VCC,VSS;
//-------------------------------------
integer i,j,n;
integer add_bytes,instructionA8;
reg C,D,S,W,HOLD,VCC,VSS;
reg[7:0] sr,read_dat;
reg[7:0] data;
reg[3*8-1:0] d_address;
//-------------------------------------
initial begin
if (`MEM_ADDR_BITS <= 9)
add_bytes = 1;
else if (9 < `MEM_ADDR_BITS && `MEM_ADDR_BITS <= 16)
add_bytes = 2;
else if (16 < `MEM_ADDR_BITS && `MEM_ADDR_BITS <= 24)
add_bytes = 3;
else
add_bytes = 2;
if (`MEM_ADDR_BITS == 9)
instructionA8 = 1;
else
instructionA8 = 0;
VSS = 1'b0;
VCC = 1'b1;
#100;
S = 1'b1;
#100;
S = 1'b0; ///HOLD and /W are not driven before this instruction. Model will warn to user.
#100;
VCC = 1'b0;
#100;
VCC = 1'b1;
#100;
S = 1'b1;
W = 1'b1; ///W is driven high
HOLD = 1'b1; ///HOLD is driven high
#100;
//---------------------------------------
$display("======================================================================");
$display("== TESTING1: READ/WRITE STATUS REGISTER INSTRUCTION VERIFICATION. ==");
$display("======================================================================");
W = 1;
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b1111_1111);
READ_STATUS_REGISTER; //should be "0000_0011"
//bit0(WIP) is "1" during the WRSR cycle. bit1(WEL) is "1". bit 4,5,6 are always "0"
// #(M95XXX_SIM.M95XXX_Macro_mux.tW);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_STATUS_REGISTER; //should be "1000_1100"
//bit0(WIP) is "0" and bit1(WEL) is reset when WRSR cycle is completed.
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0000);
READ_STATUS_REGISTER; //should be "1000_1111"
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_STATUS_REGISTER; //should be "0000_0000"
W = 0;
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b1111_1111);
READ_STATUS_REGISTER; //should be "0000_0011"
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_STATUS_REGISTER; //should be "1000_1100"
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0000);
//W = 0, SRWD = 1, enter "HPM" this "WRSR" instruction is not executed and self-time WRSR cycle is not initiated.
READ_STATUS_REGISTER; //should be "1000_1110"
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_STATUS_REGISTER; //should be "1000_1110"
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0011);
READ_STATUS_REGISTER; //should be "1000_1110"
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_STATUS_REGISTER; //should be "1000_1110"
W = 1;
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0011);
READ_STATUS_REGISTER; //should be "1000_1111"
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_STATUS_REGISTER; //should be "0000_0000"
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//---------------------------------------
$display("=======================================================");
$display("== TESTING2: MEMORY ARRAY READ/WRITE VERIFICATION. ==");
$display("=======================================================");
W = 1;
// READ_DATA_BYTES(2,`MEM_ADDR_BITS'h3ff);
READ_DATA_BYTES(2,{`MEM_ADDR_BITS {1'b1}});
WRITE_ENABLE;
// WRITE_DATA_IN(64,`DATA_BITS'h55,`MEM_ADDR_BITS'h3ff);
WRITE_DATA_IN(`PAGE_SIZE,`DATA_BITS'h55,{`MEM_ADDR_BITS {1'b1}});
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
// READ_DATA_BYTES(34,`MEM_ADDR_BITS'h3df);
READ_DATA_BYTES(`PAGE_SIZE+2,{`MEM_ADDR_BITS {1'b1}}-`PAGE_SIZE);
WRITE_DATA_IN(`PAGE_SIZE,`DATA_BITS'h55,{`MEM_ADDR_BITS {1'b1}}); //This Write Enable Instruction will not be executed.
WRITE_ENABLE;
WRITE_DATA_IN(2,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(`PAGE_SIZE,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//WRITE WITH POLLING (RDSR)
$display("=WRITE WITH POLLING (loop on read status register)");
WRITE_ENABLE;
WRITE_DATA_IN(2,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGE_SIZE-1);
POLLING_WITH_SEL_LOOP_ON_RDSR_DESEL; // replacing TW by polling routine #(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(`PAGE_SIZE,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//WRITE WITH POLLING (RDSR)
$display("=WRITE WITH POLLING (loop on select read status register deselect)");
WRITE_ENABLE;
WRITE_DATA_IN(2,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGE_SIZE-1);
POLLING_WITH_LOOP_ON_SEL_RDSR_DESEL; // replacing TW by polling routine #(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(`PAGE_SIZE,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_DATA_IN(2,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGE_SIZE-1);
READ_STATUS_REGISTER; //should be "0000_0000"
#4.991e6;
READ_STATUS_REGISTER; //should be "0000_0000"
#500
READ_STATUS_REGISTER; //should be "0000_0000"
#10
READ_STATUS_REGISTER; //should be "0000_0000"
READ_STATUS_REGISTER; //should be "0000_0000"
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//---------------------------------------
$display("===================================================================================================");
$display("== TESTING3: ALL INSTRUCTIONS (except RDSR) ARE NOT EXECUTED WHILE WRITE CYCLE IS IN PROGRESS. ==");
$display("===================================================================================================");
W = 1;
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h11,{`MEM_ADDR_BITS {1'b0}});
WRITE_ENABLE;
WRITE_DISABLE;
WRITE_STATUS_REGISTER(8'b1000_0111);
READ_DATA_BYTES(1,{`MEM_ADDR_BITS {1'b0}});
WRITE_DATA_IN(1,`DATA_BITS'h22,{`MEM_ADDR_BITS {1'b0}});
READ_STATUS_REGISTER;
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//---------------------------------------
$display("===================================================================================================");
$display("== TESTING 3A: RANDOM TESTS ==");
$display("===================================================================================================");
W = 1;
//--------------------------------------------------------
//Enable and disable test with write data when disabled(rejected)
WRITE_ENABLE;
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_DISABLE;
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_DATA_IN(1,`DATA_BITS'h11,{`MEM_ADDR_BITS {1'b0}}); //rejected
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h11,{`MEM_ADDR_BITS {1'b0}});
WRITE_STATUS_REGISTER(8'b1000_0111); //rejected
READ_STATUS_REGISTER;
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(4,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//--------------------------------------------------------
//--------------------------------------------------------
//Wrap around Test for write an read
WRITE_ENABLE;
WRITE_DATA_IN(3,`DATA_BITS'h55,{`MEM_ADDR_BITS {1'b1}});
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(4,{`MEM_ADDR_BITS {1'b1}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
READ_DATA_BYTES(4,{`MEM_ADDR_BITS {1'b1}}-`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//--------------------------------------------------------
//--------------------------------------------------------
//Read at the ID boundry and write beyond the boundry
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b0,{`PAGE_OFFSET_BITS {1'b1}}); //read beyond the ID boundry
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'h23,{`PAGE_OFFSET_BITS {1'b1}}); //2 written byte rejected beyond the boundry
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(3,1'b0,{`PAGE_OFFSET_BITS {1'b1}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'h23,{`PAGE_OFFSET_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(3,1'b0,{`PAGE_OFFSET_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//--------------------------------------------------------
//--------------------------------------------------------
//write and read the entire ID page
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK({`PAGE_OFFSET_BITS {1'b1}}+1,1'b0,`DATA_BITS'hAA,{`PAGE_OFFSET_BITS {1'b0}}); //write the entire ID PAGE to 0xAA //{`PAGE_OFFSET_BITS {1'b1}}+1
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS({`PAGE_OFFSET_BITS {1'b1}}+1,1'b0,{`PAGE_OFFSET_BITS {1'b0}}); //read the whole ID PAGE
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//--------------------------------------------------------
//--------------------------------------------------------
//write and read LOCK ID STATUS
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(1,1'b1,`DATA_BITS'h02,`MEM_ADDR_BITS'h400); //write lock ID, accepted cause only 1 byte sent
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b1,`MEM_ADDR_BITS'h400); //read lock status twice
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b1,`DATA_BITS'ha5,{`MEM_ADDR_BITS {1'b1}}); //write lock id when it is already lock, not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'ha5,{`MEM_ADDR_BITS {1'b1}}); //write ID memory when it is lock, not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b1,{`PAGE_OFFSET_BITS {1'b1}});
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b1,`MEM_ADDR_BITS'h400); //read lock status twice
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//--------------------------------------------------------
//--------------------------------------------------------
//write when memory disabled and a write polling the read status
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h22,{`MEM_ADDR_BITS {1'b0}});
READ_STATUS_REGISTER;
#(M95XXX_SIM.M95XXX_Macro_mux.tW/2);
READ_STATUS_REGISTER;
#(M95XXX_SIM.M95XXX_Macro_mux.tW/2);
READ_STATUS_REGISTER;
READ_DATA_BYTES(1,{`MEM_ADDR_BITS {1'b0}});
WRITE_DATA_IN(1,`DATA_BITS'h22,{`MEM_ADDR_BITS {1'b0}}); //rejected, write disabled
READ_STATUS_REGISTER;
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//--------------------------------------------------------
//--------------------------------------------------------
//write when memory disabled and a write polling the read status,alternating clk fininsh on zero or one
WRITE_ENABLE;
WRITE_DATA_INh(1,`DATA_BITS'h22,{`MEM_ADDR_BITS {1'b0}});
READ_STATUS_REGISTER;
#(M95XXX_SIM.M95XXX_Macro_mux.tW/2);
READ_STATUS_REGISTERh;
#(M95XXX_SIM.M95XXX_Macro_mux.tW/2);
READ_STATUS_REGISTER;
READ_DATA_BYTESh(1,{`MEM_ADDR_BITS {1'b0}});
WRITE_DATA_IN(1,`DATA_BITS'h22,{`MEM_ADDR_BITS {1'b0}}); //rejected, write disabled
READ_STATUS_REGISTERh;
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_DATA_INh(`PAGE_SIZE,`DATA_BITS'h55,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTESh(`PAGE_SIZE,{`MEM_ADDR_BITS {1'b0}});
WRITE_ENABLE;
WRITE_DATA_INh(`PAGE_SIZE/4,`DATA_BITS'h33,`PAGE_SIZE/2);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTESh(`PAGE_SIZE,{`MEM_ADDR_BITS {1'b0}});
READ_DATA_BYTES(`PAGE_SIZE,{{`MEM_ADDR_BITS-2 {1'b1}},2'b00});
WRITE_ENABLEh;
WRITE_DATA_INh(1,`DATA_BITS'hAA,{`MEM_ADDR_BITS {1'b1}});
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,{`MEM_ADDR_BITS {1'b1}});
READ_DATA_BYTESh(1,{`MEM_ADDR_BITS {1'b0}});
//--------------------------------------------------------
//write and read LOCK ID STATUS, alternating clk fininsh on zero or one
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCKh(1,1'b1,`DATA_BITS'h02,`MEM_ADDR_BITS'h400); //write lock ID, accepted cause only 1 byte sent
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b1,`MEM_ADDR_BITS'h400); //read lock status twice
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLEh;
WRITE_ID_PAGE_OR_LOCK(2,1'b1,`DATA_BITS'ha5,{`MEM_ADDR_BITS {1'b1}}); //write lock id when it is already lock, not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLEh;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'ha5,{`MEM_ADDR_BITS {1'b1}}); //write ID memory when it is lock, not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b1,{`PAGE_OFFSET_BITS {1'b1}});
READ_ID_PAGE_OR_LOCK_STATUSh(2,1'b1,`MEM_ADDR_BITS'h400); //read lock status twice
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//--------------------------------------------------------
//--------------------------------------------------------
//---------------------------------------
$display("=========================================================================");
$display("== TESTING4: VERIFICATION OF ADDRESS INSIDE A WRITE PROTECTED ARRAY. ==");
$display("=========================================================================");
$display("------------------------------------------");
$display("-- Note: Memory Array is not Protected. --");
$display("------------------------------------------");
W = 1;
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0000); //No block of memory is protected
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h99,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h99,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h99,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h99,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h99,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h99,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h99,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
$display("-------------------------------------------------------");
$display("-- Note: Upper quarter of Memory Array is Protected. --");
$display("-------------------------------------------------------");
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0100); //Upper quarter of memory is protected
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
$display("----------------------------------------------------");
$display("-- Note: Upper half of Memory Array is Protected. --");
$display("----------------------------------------------------");
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_1000); //Upper half of memory is protected
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hbb,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hbb,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hbb,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hbb,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hbb,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hbb,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hbb,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
$display("--------------------------------------------");
$display("-- Note: Whole Memory Array is Protected. --");
$display("--------------------------------------------");
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_1100); //whole memory is protected
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hcc,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hcc,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hcc,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hcc,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hcc,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hcc,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hcc,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//---------------------------------------
if (`IDPAGE)
begin
//---------------------------------------
$display("\n=====================================================");
$display("== TESTING5: MEMORY ID ARRAY READ/WRITE VERIFICATION. ==");
$display("========================================+++==========\n");
#20000;
W = 1;
$display("-------------------------------------------------------------");
$display("-- Note: Whole Memory Array is Protected --");
$display("-------------------------------------------------------------");
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_1100); //whole memory is protected
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(1,1'b1,`DATA_BITS'ha5,`MEM_ADDR_BITS'h7ff); //write lock id when it bp1,bp0 = (1,1), not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'ha5,`MEM_ADDR_BITS'h3ff); //write ID memory when it bp1,bp0 = (1,1), not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0000); //whole memory is protected
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
$display("\n-------------------------------------------------");
$display("-- Note: READ/WRITE MEMORY ID. --");
$display("-------------------------------------------------");
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b0,{`PAGE_OFFSET_BITS {1'b1}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'h23,{`PAGE_OFFSET_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b0,{`PAGE_OFFSET_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(3,1'b0,`DATA_BITS'hAA,{`PAGE_OFFSET_BITS {1'b1}}); //write the entire ID PAGE to 0xAA
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b0,{`PAGE_OFFSET_BITS {1'b1}}); //read the whole ID PAGE
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(`PAGE_SIZE,1'b0,`DATA_BITS'hAA,{`PAGE_OFFSET_BITS {1'b0}}); //write the entire ID PAGE to 0xAA
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ID_PAGE_OR_LOCK(`PAGE_SIZE,1'b0,`DATA_BITS'h55,{`PAGE_OFFSET_BITS {1'b1}}); //This Write Enable Instruction will not be executed.
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'ha5,{`MEM_ADDR_BITS {1'b1}}); //write last byte in page and first byte wrap
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(5,1'b0,`DATA_BITS'h13,`PAGE_OFFSET_BITS'h0A); //write starting at loc 0x13 location for 5 bytes
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(`PAGE_SIZE,1'b0,{`PAGE_OFFSET_BITS {1'b0}}); //read the whole ID PAGE
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
$display("-------------------------------------------------------------------------------");
$display("-- Note: WRITE LOCK ID AND READ/WRITE MEMORY ID --");
$display("-------------------------------------------------------------------------------");
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b1,`MEM_ADDR_BITS'h400); //read lock status twice
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b1,`DATA_BITS'h02,{`MEM_ADDR_BITS {1'b1}}); //write LOCK ID, not accepted cause more than 1 byte
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(1,1'b1,`DATA_BITS'h02,`MEM_ADDR_BITS'h400); //write lock ID, accepted cause only 1 byte sent
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b1,`MEM_ADDR_BITS'h400); //read lock status twice
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b1,`DATA_BITS'ha5,{`MEM_ADDR_BITS {1'b1}}); //write lock id when it is already lock, not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'ha5,{`MEM_ADDR_BITS {1'b1}}); //write ID memory when it is lock, not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
end
//---------------------------------------
$display("==============================================");
if (`IDPAGE)
$display("== TESTING6: HOLD CONDITION VERIFICATION. ==");
else
$display("== TESTING5: HOLD CONDITION VERIFICATION. ==");
$display("==============================================");
W = 1;
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0000);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
//////////////////////////Write Data Instruction
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time - data in setup time
//////////////////////////
//************************
HOLD = 1'b0; //HOLD driven low when CLK=1, Pause right now
D = 1'b0;
//#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data in setup time
#(M95XXX_SIM.M95XXX_Macro_mux.tHLCH); //clock low hold time after "HOLD" active
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK-50);
HOLD = 1'b0;
#25;
HOLD = 1'b1; //HOLD driven high when C=1, Resume next CLK falling edge
#25;
//************************
HOLD = 1'b0; //HOLD driven high same as CLK falling edge, Pause
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
for(i=0;i<add_bytes*8-1;i=i+1)
begin
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
C = 1'b1;
//#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK-40);
HOLD = 1'b1; //HOLD driven high when C=1, no effect
#20;
HOLD = 1'b0; //HOLD driven low when C=1 no effect
#20
HOLD = 1'b1; //HOLD driven high when C=1, and sametime C is driven low, Resume
//------------------------
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCLHL);
HOLD = 1'b0; //HOLD driven low when C=0, hold start
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
for(i=0;i<4;i=i+1)
begin
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
HOLD = 1'b1; //HOLD driven high when C=0, hold end
//#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
#(M95XXX_SIM.M95XXX_Macro_mux.tHHCH);
//------------------------
C = 1'b1; //D0 of instruction code, latched in
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
HOLD = 1'b0; //HOLD driven low when C=1, next C falling edge start
for(i=0;i<4;i=i+1)
begin
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK);
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
HOLD = 1'b1; //HOLD driven high when C=1, next falling edge stop
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//------------------------
//*********************************************************************
// ---Write Memory Instruction code with a changing /HOLD signal ---
//*********************************************************************
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
//D = 1'b0;
//#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
//C = 1'b1;
//#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
//C = 1'b0;
//#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
D = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
//----------------------//indicate destination address
d_address = {`MEM_ADDR_BITS {1'b0}};
for(i=0;i<=add_bytes*8-1;i=i+1)
begin
D = d_address[add_bytes*8-1-i];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------//write data
n = 32; //the number of data bytes
data = 8'h29; //indicate data value
for(i=0;i<=n-1;i=i+1)
begin
for(j=0;j<=7;j=j+1)
begin
D = data[7-j];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
//----------------------//Write Instruction Over
READ_DATA_BYTES_HD(16,1'b0,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
$display("-------------------------------------------------------------------------------");
$display("-- Note: READ MEMORY ID WITH HOLDS --");
$display("-------------------------------------------------------------------------------");
if (`IDPAGE) begin
READ_DATA_BYTES_HD(16,1'b1,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
end
$display("======================================================");
if (`IDPAGE)
$display("== TESTING7: THE VIOLATED AC TIMING VERIFICATION. ==");
else
$display("== TESTING6: THE VIOLATED AC TIMING VERIFICATION. ==");
$display("======================================================");
//Following code executes unmeaning operation. It is only used for checking the AC Timing out of spec.
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL - 1); //violated the /S not active hold time //violated the clock high time
S = 1'b0;
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCL - 1); //violated the /S active setup time //violated the clock low time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCH);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCL);
D = ~D; //change the value on "D" input pin
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH - 1); //violated the Data In Setup Time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHDX - 1); //violated the Data In Hold Time
D = ~D; //change the value on "D" input pin
#(M95XXX_SIM.M95XXX_Macro_mux.tCH);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCL);
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH - 1); //violated the /S Active Hold Time //violated the clock high time
S = 1'b1;
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCL - 1); //violated the /S Active Setup Time //violated the clock low time //violated /S Deselest Time
C = 1'b1;
#1; //violated the /S not active hold time
S = 1'b0;
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCL);
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCH);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCLHL); //Clock Low Set-Up Time before /HOLD Active = 0s
HOLD = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tHLCH - 1); //violated the CLock Low Hold Time after /HOLD Active //violated the clock low time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCH);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCLHH); //Clock Low Set-Up Time before /HOLD Not Active = 0s
HOLD = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tHHCH - 1); //violated the CLock Low Hold Time after /HOLD Not Active //violated the clock low time
C = 1'b1;
#100;
S = 1'b1;
#200;
if (!`VALID_PRT)
begin
$display("\n######################################################################");
$display(" ERROR: Part Choosen is NOT a valid Part ");
$display("######################################################################\n");
end
$display("\n######################################################################");
$display(" TESTS DONE ");
$display("######################################################################\n");
$stop; //testing completed
end
//===============================================
//Stimuli task definition
//===============================================
`define logicbit 1'b0
task WRITE_ENABLEi;
input initclk;
begin
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
for(i=0;i<=7;i=i+1)
begin
if((i==5)||(i==6)) D = 1'b1;
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time, and /S active setup time with #(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH)
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK); //Clock High Time
if (i==7) C = initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task WRITE_ENABLE;
WRITE_ENABLEi(`logicbit);
endtask
task WRITE_ENABLEh;
WRITE_ENABLEi(1'b1);
endtask
//===============================================
task WRITE_DISABLEi;
input initclk;
begin
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if(i==5) D = 1'b1;
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (i==7) C = initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task WRITE_DISABLE;
WRITE_DISABLEi(`logicbit);
endtask
task WRITE_DISABLEh;
WRITE_DISABLEi(1'b1);
endtask
//===============================================
task READ_STATUS_REGISTERi;
input initclk;
begin
//----------------------instruction
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if((i==5)||(i==7)) D = 1'b1;
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------read status register
for(i=0;i<=7;i=i+1)
begin
C = 1'b1;
sr = {sr[6:0],Q};
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (i==7) C = initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK);
end
$display("%t: STATUS_REGISTER = [%b]",$realtime,sr);
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task READ_STATUS_REGISTER;
READ_STATUS_REGISTERi(`logicbit);
endtask
task READ_STATUS_REGISTERh;
READ_STATUS_REGISTERi(1'b1);
endtask
//===============================================
task POLLING_WITH_SEL_LOOP_ON_RDSR_DESEL;
begin
//----------------------instruction
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if((i==5)||(i==7)) D = 1'b1;
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------read status register
sr = 03;
while (sr != 0)
begin
for(i=0;i<=7;i=i+1)
begin
C = 1'b1;
sr = {sr[6:0],Q};
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK);
end
$display("%t: STATUS_REGISTER = [%b]",$realtime,sr);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
//===============================================
task POLLING_WITH_LOOP_ON_SEL_RDSR_DESEL;
begin
//----------------------instruction
if (C==1) C=1'b0;
sr = 03;
while (sr != 0)
begin
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if((i==5)||(i==7)) D = 1'b1;
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------read status register
for(i=0;i<=7;i=i+1)
begin
C = 1'b1;
sr = {sr[6:0],Q};
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK);
end
$display("%t: STATUS_REGISTER = [%b]",$realtime,sr);
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
end
endtask
//===============================================
task WRITE_STATUS_REGISTERi;
input[7:0] sr_data;
input initclk;
begin
//----------------------instruction
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL);
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
for(i=0;i<=7;i=i+1)
begin
if(i==7) D = 1'b1;
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------write status register
for(i=0;i<=7;i=i+1)
begin
D = sr_data[7-i];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (i==7) C = initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task WRITE_STATUS_REGISTER;
input[7:0] sr_data;
begin
WRITE_STATUS_REGISTERi(sr_data,`logicbit);
end
endtask
task WRITE_STATUS_REGISTERh;
input[7:0] sr_data;
begin
WRITE_STATUS_REGISTERi(sr_data,1'b1);
end
endtask
//===============================================
task READ_DATA_BYTESi;
input n;
input[23:0] address;
input initclk;
integer j,n;
begin
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if((i==6)||(i==7)) D = 1'b1;
else if ((instructionA8==1)&&(i==4)) D = address[`MEM_ADDR_BITS-1];
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
if (C==1) C = 1'b0; else C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (C==0) C = 1'b1; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------address
for(i=0;i<=add_bytes*8-1;i=i+1)
begin
D = address[add_bytes*8-1-i];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
if (C==1) C = 1'b0; else C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (C==0) C = 1'b1; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------read data bytes
for(i=1;i<=n;i=i+1)
begin
// address = U_M95XXX.memory_address[`MEM_ADDR_BITS-1:0];
for(j=0;j<=7;j=j+1)
begin
if (C==1) C = 1'b0; else C = 1'b1;
// read_dat = {read_dat[6:0],Q};
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
read_dat = {read_dat[6:0],Q};
address = U_M95XXX.memory_address[`MEM_ADDR_BITS-1:0];
if (i==n&&j==7) C = initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK);
end
$display("%t: READ RESULT: ADDRESS = [%h], DATA = [%h]\n",$realtime,address,read_dat);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task READ_DATA_BYTES;
input n;
input[23:0] address;
integer n;
begin
READ_DATA_BYTESi(n,address,`logicbit);
end
endtask
task READ_DATA_BYTESh;
input n;
input[23:0] address;
integer n;
begin
READ_DATA_BYTESi(n,address,1'b1);
end
endtask
//===============================================
task WRITE_DATA_INi;
input n; //the number of data byte that be written in
input[7:0] data; //the data written in memory
input[23:0] address; //the accessed location's address
input initclk;
integer j,n;
begin
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if(i==6) D = 1'b1;
else if ((instructionA8==1)&&(i==4)) D = address[`MEM_ADDR_BITS-1];
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
if (C==1)
C = 1'b0;
else
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (C==0)
C = 1'b1;
else
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------address
for(i=0;i<=add_bytes*8-1;i=i+1)
begin
D = address[add_bytes*8-1-i];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
if (C==1)
C = 1'b0;
else
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (C==0)
C = 1'b1;
else
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------write data
for(i=0;i<=n-1;i=i+1)
begin
for(j=0;j<=7;j=j+1)
begin
D = data[7-j];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
if (C==1) C = 1'b0; else C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (i==n-1&&j==7) C = initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
end
//----------------------
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task WRITE_DATA_IN;
input n; //the number of data byte that be written in
input[7:0] data; //the data written in memory
input[23:0] address; //the accessed location's address
integer n;
begin
WRITE_DATA_INi(n,data,address,`logicbit);
end
endtask
task WRITE_DATA_INh;
input n; //the number of data byte that be written in
input[7:0] data; //the data written in memory
input[23:0] address; //the accessed location's address
integer n;
begin
WRITE_DATA_INi(n,data,address,1'b1);
end
endtask
//===============================================
task WRITE_ID_PAGE_OR_LOCKi;
input n; //the number of data byte that be written in
input idn_lock;
input[7:0] data; //the data written in memory
input[23:0] address; //the accessed location's address
input initclk;
integer j,n;
begin
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if((i==0||i==6)) D = 1'b1;
// else if ((instructionA8==1)&&(i==4)) D = address[`MEM_ADDR_BITS-1];
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------address
if((address[10])&&(!idn_lock))
begin
$display("%t: ERROR: A10 set for lock on a Write ID Operation!",$realtime);
$display("%t: WARNING: Setting A10 to Zero for Write ID Operation!\n",$realtime);
address[10] = 1'b0;
end
else if((!address[10])&&(idn_lock))
begin
$display("%t: ERROR: A10 set for a Write ID on a Lock ID Operation!",$realtime);
$display("%t: WARNING: Setting A10 to one for Lock ID Operation!\n",$realtime);
address[10] = 1'b1;
end
for(i=0;i<=add_bytes*8-1;i=i+1)
begin
D = address[add_bytes*8-1-i];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------write data
for(i=0;i<=n-1;i=i+1)
begin
for(j=0;j<=7;j=j+1)
begin
D = data[7-j];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (i==n-1&&j==7) C = initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
end
//----------------------
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task WRITE_ID_PAGE_OR_LOCK;
input n; //the number of data byte that be written in
input idn_lock;
input[7:0] data; //the data written in memory
input[23:0] address; //the accessed location's address
integer n;
begin
WRITE_ID_PAGE_OR_LOCKi(n,idn_lock,data,address,`logicbit);
end
endtask
task WRITE_ID_PAGE_OR_LOCKh;
input n; //the number of data byte that be written in
input idn_lock;
input[7:0] data; //the data written in memory
input[23:0] address; //the accessed location's address
integer n;
begin
WRITE_ID_PAGE_OR_LOCKi(n,idn_lock,data,address,1'b1);
end
endtask
//===============================================
task READ_ID_PAGE_OR_LOCK_STATUSi;
input n;
input idn_status;
input[23:0] address;
input initclk;
integer j,n;
begin
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if((i==0)||(i==6)||(i==7)) D = 1'b1;
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------address
if((address[10])&&(!idn_status))
begin
$display("%t: ERROR: A10 set for Read Lock Status on a Read ID Operation!",$realtime);
$display("%t: WARNING: Setting A10 to Zero for Read ID Operation!\n",$realtime);
address[10] = 1'b0;
end
else if((!address[10])&&(idn_status))
begin
$display("%t: ERROR: A10 set for Read ID Operation on a Read Lock Status Operation!",$realtime);
$display("%t: WARNING: Setting A10 to one for Read Lock Status Operation!\n",$realtime);
address[10] = 1'b1;
end
// address[`MEM_ADDR_BITS-1:`MEM_ADDR_BITS-`PAGE_ADDR_BITS] = {`PAGE_ADDR_BITS{1'b0}};
for(i=0;i<=add_bytes*8-1;i=i+1)
begin
D = address[add_bytes*8-1-i];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------read data bytes
for(i=1;i<=n;i=i+1)
begin
address = U_M95XXX.memory_address[`MEM_ADDR_BITS-`PAGE_ADDR_BITS-1:0];
for(j=0;j<=7;j=j+1)
begin
C = 1'b1;
read_dat = {read_dat[6:0],Q};
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (i==n&&j==7) C =initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK);
end
$display("%t: READ RESULT: ADDRESS = [%h], DATA = [%h]\n",$realtime,address,read_dat);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task READ_ID_PAGE_OR_LOCK_STATUS;
input n;
input idn_status;
input[23:0] address;
integer n;
begin
READ_ID_PAGE_OR_LOCK_STATUSi(n,idn_status,address,`logicbit);
end
endtask
task READ_ID_PAGE_OR_LOCK_STATUSh;
input n;
input idn_status;
input[23:0] address;
integer n;
begin
READ_ID_PAGE_OR_LOCK_STATUSi(n,idn_status,address,1'b1);
end
endtask
//===============================================
task READ_DATA_BYTES_HD;
input n;
input id;
input[23:0] address;
integer j,n,k;
reg id;
begin
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if((id==1)&&(i==0)) D = 1'b1;
else if((i==6)||(i==7)) D = 1'b1;
else if ((instructionA8==1)&&(i==4)) D = address[`MEM_ADDR_BITS-1];
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------address
for(i=0;i<=add_bytes*8-1;i=i+1)
begin
D = address[add_bytes*8-1-i];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------read data bytes
for(i=1;i<=n;i=i+1)
begin
address = U_M95XXX.memory_address[`MEM_ADDR_BITS-1:0];
for(j=0;j<=7;j=j+1)
begin
C = 1'b1;
read_dat = {read_dat[6:0],Q};
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
//#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-40);
#(M95XXX_SIM.M95XXX_Macro_mux.tCLHL); //clk low setup time before "HOLD" active
//---------------------------------------------
HOLD = 1'b0; //HOLD Condition start
for(k=0;k<1;k=k+1)
begin
//#60;
#(M95XXX_SIM.M95XXX_Macro_mux.tHLCH); //clk low hold time after "HOLD" active
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tCLHL-M95XXX_SIM.M95XXX_Macro_mux.tHLCH);
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
//#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-40);
#(M95XXX_SIM.M95XXX_Macro_mux.tCLHL); //clk low setup time before "HOLD" active
end
HOLD = 1'b1; //HOLD Condition end
//#60;
#(M95XXX_SIM.M95XXX_Macro_mux.tHLCH); //clk low hold time after "HOLD" active
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tCLHL-M95XXX_SIM.M95XXX_Macro_mux.tHLCH);
//---------------------------------------------
end
$display("%t: READ RESULT: ADDRESS = [%h], DATA = [%h]\n",$realtime,address,read_dat);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
//===============================================
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: altera_primitive_sync_fifo_24in_24out_16depth.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_primitive_sync_fifo_24in_24out_16depth (
aclr,
clock,
data,
rdreq,
sclr,
wrreq,
almost_empty,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [23:0] data;
input rdreq;
input sclr;
input wrreq;
output almost_empty;
output almost_full;
output empty;
output full;
output [23:0] q;
output [3:0] usedw;
wire sub_wire0;
wire [3:0] sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire [23:0] sub_wire4;
wire sub_wire5;
wire almost_full = sub_wire0;
wire [3:0] usedw = sub_wire1[3:0];
wire empty = sub_wire2;
wire almost_empty = sub_wire3;
wire [23:0] q = sub_wire4[23:0];
wire full = sub_wire5;
scfifo scfifo_component (
.rdreq (rdreq),
.sclr (sclr),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.almost_full (sub_wire0),
.usedw (sub_wire1),
.empty (sub_wire2),
.almost_empty (sub_wire3),
.q (sub_wire4),
.full (sub_wire5));
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_empty_value = 2,
scfifo_component.almost_full_value = 14,
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 24,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "2"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "14"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "24"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "24"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "2"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "14"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL data[23..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL q[23..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
// Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL usedw[3..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0
// Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_24in_24out_16depth.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_24in_24out_16depth.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_24in_24out_16depth.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_24in_24out_16depth.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_24in_24out_16depth_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_24in_24out_16depth_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_24in_24out_16depth_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_24in_24out_16depth_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_BLACKBOX_V
`define SKY130_FD_SC_HDLL__XNOR2_BLACKBOX_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__xnor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_BLACKBOX_V
|
// -----------------------------------------------------------------------
//
// Copyright 2004 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
`timescale 1ns/10ps
module regfile(input wire clock,
input wire enable,
input wire [ 4:0] rdaddress_a,
input wire [ 4:0] rdaddress_b,
// Write port
input wire wren,
input wire [ 4:0] wraddress,
input wire [31:0] data,
// Read ports
output reg [31:0] qa, // One clock cycle delayed
output reg [31:0] qb // One clock cycle delayed
);
reg [31:0] regs [31:0];
always @(posedge clock)
if (enable) begin
if (wren)
regs[wraddress] <= data;
qa <= regs[rdaddress_a];
qb <= regs[rdaddress_b];
end
reg [7:0] i;
initial begin
i = 0;
repeat (32) begin
regs[i] = 0 /*{4{i}}*/;
i = i + 1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32AI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O32AI_BEHAVIORAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32AI_BEHAVIORAL_V |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ac_e
//
// Generated
// by: wig
// on: Mon Mar 22 12:42:23 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../io.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ac_e.v,v 1.1 2004/04/06 11:05:04 wig Exp $
// $Date: 2004/04/06 11:05:04 $
// $Log: inst_ac_e.v,v $
// Revision 1.1 2004/04/06 11:05:04 wig
// Adding result/io
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ac_e
//
// No `defines in this module
module inst_ac_e
//
// Generated module inst_ac
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ac_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NAND3B_FUNCTIONAL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand3b (
Y ,
A_N,
B ,
C
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, B, not0_out, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_FUNCTIONAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_int_arb.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// jbi_int_arb -- Internal request collection to create a single, JBus arbiter request..
// _____________________________________________________________________________
//
// Description:
// Flow control
// Gates off individual requests as needed. This prevents them from
// getting grants. It does not prevent in-progress multi-cycle transactions
// from issuing dequeues to complete.
// External request to the JBus Arbiter
// The external request to the JBus Arbiter 'int_req', is asserted when
// there exists any internal requests that is not being flow controlled. To
// correctly assert the external request, it is important to know if there
// is another request in a queue behind the current one that is being process.
// Since a request may be multiple entries in a queue, simply looking for a valid
// top-of-queue is inadaquate.
// Tran_count is decremented on int_granted, not the queues dequeue signal. This is
// because the header and initial data quadword are together on the top-of-queue in some
// queues. Hence the header cannot be dequeued until the data is used on the next cycle.
// So we won't get a dequeue when the header is consumed.
//
// o No transactions can appear on the bus for 40 cycles after reset (JBus spec).
// This will inherently not happen because the instruction fetch is to the separate
// boot prom port.
//
// o Single cycle transactions will not assert 'int_req' if the JBus is parked on us.
//
// _____________________________________________________________________________
`include "sys.h"
`include "jbi.h"
module jbi_int_arb (/*AUTOARG*/
// Outputs
sct0rdq_dec_count, sct1rdq_dec_count, sct2rdq_dec_count, sct3rdq_dec_count,
piorqq_req_adv, pioackq_req_adv, dbg_req_adv, int_req, have_trans_waiting,
int_requestors, int_req_type, jbi_log_arb_myreq, jbi_log_arb_reqtype,
// Inputs
sct0rdq_data1_4, sct0rdq_trans_count, sct0rdq_ue_err, sct0rdq_unmapped_error,
sct1rdq_data1_4, sct1rdq_trans_count, sct1rdq_ue_err, sct1rdq_unmapped_error,
sct2rdq_data1_4, sct2rdq_trans_count, sct2rdq_ue_err, sct2rdq_unmapped_error,
sct3rdq_data1_4, sct3rdq_trans_count, sct3rdq_ue_err, sct3rdq_unmapped_error,
piorqq_req, piorqq_req_rw, piorqq_req_dest, pioackq_req, pioackq_ack_nack,
dbg_req_transparent, dbg_req_arbitrate, dbg_req_priority, int_granted,
parked_on_us, ok_send_address_pkt, ok_send_data_pkt_to_4,
ok_send_data_pkt_to_5, csr_jbi_debug_arb_aggr_arb, clk, rst_l
);
`include "jbi_mout.h"
// SCT0 RDQ.
input sct0rdq_data1_4; // If asserted, RD16 read return, else RD64 read return.
input [3:0] sct0rdq_trans_count; // Number of transactions in the queue.
output sct0rdq_dec_count; // When asserted, decrement the transactions count.
input sct0rdq_ue_err; // When asserted, data at top-of-queue has an Uncorrectable Error.
input sct0rdq_unmapped_error; // State for cache to install the data or unmapped error flag.
// SCT1 RDQ.
input sct1rdq_data1_4; // If asserted, RD16 read return, else RD64 read return.
input [3:0] sct1rdq_trans_count; // Number of transactions in the queue.
output sct1rdq_dec_count; // When asserted, decrement the transactions count.
input sct1rdq_ue_err; // When asserted, data at top-of-queue has an Uncorrectable Error.
input sct1rdq_unmapped_error; // State for cache to install the data or unmapped error flag.
// SCT2 RDQ.
input sct2rdq_data1_4; // If asserted, RD16 read return, else RD64 read return.
input [3:0] sct2rdq_trans_count; // Number of transactions in the queue.
output sct2rdq_dec_count; // When asserted, decrement the transactions count.
input sct2rdq_ue_err; // When asserted, data at top-of-queue has an Uncorrectable Error.
input sct2rdq_unmapped_error; // State for cache to install the data or unmapped error flag.
// SCT3 RDQ.
input sct3rdq_data1_4; // If asserted, RD16 read return, else RD64 read return.
input [3:0] sct3rdq_trans_count; // Number of transactions in the queue.
output sct3rdq_dec_count; // When asserted, decrement the transactions count.
input sct3rdq_ue_err; // When asserted, data at top-of-queue has an Uncorrectable Error.
input sct3rdq_unmapped_error; // State for cache to install the data or unmapped error flag.
// PIO RQQ.
input piorqq_req; // The PIORQQ has a valid request.
input piorqq_req_rw; // If asserted, next request is read request, else it is a write request.
input [1:0] piorqq_req_dest; // If request is a write, this signal tell to which device (0 AID0, 1 AID4, 2 AID5, 3 AID Other).
output piorqq_req_adv; // When asserted, pop the transaction header from the PIORQQ_REQ queue.
// PIO ACKQ.
input pioackq_req; // The PIOACKQ has a valid request.
input pioackq_ack_nack; // If asserted, top-of-queue has an INT ACK request, else it is an INT NACK request.
output pioackq_req_adv; // When asserted, pop the transaction header from the PIOACKQ queue.
// DEBUG ACKQ.
input dbg_req_transparent; // The Debug Info queue has valid request and wants it sent without impacting the JBus flow.
input dbg_req_arbitrate; // The Debug Info queue has valid request and wants fair round robin arbitration.
input dbg_req_priority; // The Debug Info queue has valid request and needs it sent right away.
output dbg_req_adv; // When asserted, pop the transaction header from the Debug Info queue.
// JBus Arbiter.
output int_req;
// Arb Timeout support.
output have_trans_waiting; // There is at least one transaction that needs to go to JBus (not AOK/DOK flow controlled).
// JBus Packet Controller.
output [6:0] int_requestors; // Current internal requestor (At most one bit of int_requestors[] is asserted at a time).
output [3:0] int_req_type;
input int_granted;
input parked_on_us;
// Flow Control.
input ok_send_address_pkt;
input ok_send_data_pkt_to_4;
input ok_send_data_pkt_to_5;
// CSRs and errors.
input csr_jbi_debug_arb_aggr_arb; // AGGR_ARB bit of JBI_DEBUG_ARB register.
output [2:0] jbi_log_arb_myreq; // "Arbitration Timeout Error" data log, MYREQ
output [2:0] jbi_log_arb_reqtype; // "Arbitration Timeout Error" data log, REQTYPE.
// Clock and reset.
input clk;
input rst_l;
// Wires and Regs.
wire [6:0] last_granted;
reg [3:0] int_req_type;
// Forming the requests.
wire [6:0] req_in;
assign req_in[LRQ_SCT0RDQ_BIT] = (sct0rdq_trans_count != 1'b0);
assign req_in[LRQ_SCT1RDQ_BIT] = (sct1rdq_trans_count != 1'b0);
assign req_in[LRQ_SCT2RDQ_BIT] = (sct2rdq_trans_count != 1'b0);
assign req_in[LRQ_SCT3RDQ_BIT] = (sct3rdq_trans_count != 1'b0);
assign req_in[LRQ_PIORQQ_BIT] = piorqq_req;
assign req_in[LRQ_PIOACKQ_BIT] = pioackq_req;
assign req_in[LRQ_DBGQ_BIT] = (dbg_req_transparent && parked_on_us &&
(!req_in[LRQ_SCT0RDQ_BIT] && !req_in[LRQ_SCT1RDQ_BIT] && !req_in[LRQ_SCT2RDQ_BIT] &&
!req_in[LRQ_SCT3RDQ_BIT] && !req_in[LRQ_PIORQQ_BIT] && !req_in[LRQ_PIOACKQ_BIT])) ||
dbg_req_arbitrate || dbg_req_priority;
// Conditioning requests with AOK/DOK.
wire [6:0] req_cond;
assign req_cond[LRQ_SCT0RDQ_BIT] = req_in[LRQ_SCT0RDQ_BIT];
assign req_cond[LRQ_SCT1RDQ_BIT] = req_in[LRQ_SCT1RDQ_BIT];
assign req_cond[LRQ_SCT2RDQ_BIT] = req_in[LRQ_SCT2RDQ_BIT];
assign req_cond[LRQ_SCT3RDQ_BIT] = req_in[LRQ_SCT3RDQ_BIT];
assign req_cond[LRQ_PIORQQ_BIT] = req_in[LRQ_PIORQQ_BIT] && (
(piorqq_req_rw && ok_send_address_pkt) || // NCRD requires AOK_ON.
(!piorqq_req_rw && ok_send_address_pkt && (piorqq_req_dest == `JBI_PRQQ_DEST_4) && ok_send_data_pkt_to_4) || // NCWR to AID 4 requires AOK_ON and DOK_ON(4).
(!piorqq_req_rw && ok_send_address_pkt && (piorqq_req_dest == `JBI_PRQQ_DEST_5) && ok_send_data_pkt_to_5) || // NCWR to AID 5 requires AOK_ON and DOK_ON(5).
(!piorqq_req_rw && ok_send_address_pkt && (piorqq_req_dest == `JBI_PRQQ_DEST_0)) || // NCWR to AID 0 requires AOK_ON.
(!piorqq_req_rw && ok_send_address_pkt && (piorqq_req_dest == `JBI_PRQQ_DEST_OTH)) // NCWR to AIDs 1,2,3,6, and 7 require AOK_ON.
);
assign req_cond[LRQ_PIOACKQ_BIT] = req_in[LRQ_PIOACKQ_BIT];
assign req_cond[LRQ_DBGQ_BIT] = req_in[LRQ_DBGQ_BIT];
// Create the internal request signal to the JBus Arbiter.
wire single_cycle_req = (int_req_type == T_RD16) ||
(int_req_type == T_NCRD) ||
(int_req_type == T_INTACK) ||
(int_req_type == T_INTNACK);
wire no_req_needed = single_cycle_req && parked_on_us;
assign int_req = ((| req_cond) && !no_req_needed) || csr_jbi_debug_arb_aggr_arb;
// Internal Arbiter.
//
// Two level arbiter. First level is round-robin, no hold. Second level
// is priority to dbg queue when 'dbg_req_priority' asserted.
//
// First level arbiter (round-robin, no hold).
// (Note: At most one bit of int_requestors[] is asserted at a time).
wire [6:0] int_requestors_l1;
assign int_requestors_l1[6] = req_cond[6] && (
(last_granted[0] ) ||
(last_granted[1] && !( { req_cond[ 0] })) ||
(last_granted[2] && !(| { req_cond[1:0] })) ||
(last_granted[3] && !(| { req_cond[2:0] })) ||
(last_granted[4] && !(| { req_cond[3:0] })) ||
(last_granted[5] && !(| { req_cond[4:0] })) ||
(last_granted[6] && !(| { req_cond[5:0] })));
assign int_requestors_l1[5] = req_cond[5] && (
(last_granted[6] ) ||
(last_granted[0] && !( { req_cond[6] })) ||
(last_granted[1] && !(| { req_cond[ 0], req_cond[6] })) ||
(last_granted[2] && !(| { req_cond[1:0], req_cond[6] })) ||
(last_granted[3] && !(| { req_cond[2:0], req_cond[6] })) ||
(last_granted[4] && !(| { req_cond[3:0], req_cond[6] })) ||
(last_granted[5] && !(| { req_cond[4:0], req_cond[6] })));
assign int_requestors_l1[4] = req_cond[4] && (
(last_granted[5] ) ||
(last_granted[6] && !( { req_cond[ 5] })) ||
(last_granted[0] && !(| { req_cond[6:5] })) ||
(last_granted[1] && !(| { req_cond[ 0], req_cond[6:5] })) ||
(last_granted[2] && !(| { req_cond[1:0], req_cond[6:5] })) ||
(last_granted[3] && !(| { req_cond[2:0], req_cond[6:5] })) ||
(last_granted[4] && !(| { req_cond[3:0], req_cond[6:5] })));
assign int_requestors_l1[3] = req_cond[3] && (
(last_granted[4] ) ||
(last_granted[5] && !( { req_cond[ 4] })) ||
(last_granted[6] && !(| { req_cond[5:4] })) ||
(last_granted[0] && !(| { req_cond[6:4] })) ||
(last_granted[1] && !(| { req_cond[ 0], req_cond[6:4] })) ||
(last_granted[2] && !(| { req_cond[1:0], req_cond[6:4] })) ||
(last_granted[3] && !(| { req_cond[2:0], req_cond[6:4] })));
assign int_requestors_l1[2] = req_cond[2] && (
(last_granted[3] ) ||
(last_granted[4] && !( { req_cond[ 3] })) ||
(last_granted[5] && !(| { req_cond[4:3] })) ||
(last_granted[6] && !(| { req_cond[5:3] })) ||
(last_granted[0] && !(| { req_cond[6:3] })) ||
(last_granted[1] && !(| { req_cond[ 0], req_cond[6:3] })) ||
(last_granted[2] && !(| { req_cond[1:0], req_cond[6:3] })));
assign int_requestors_l1[1] = req_cond[1] && (
(last_granted[2] ) ||
(last_granted[3] && !( { req_cond[ 2] })) ||
(last_granted[4] && !(| { req_cond[3:2] })) ||
(last_granted[5] && !(| { req_cond[4:2] })) ||
(last_granted[6] && !(| { req_cond[5:2] })) ||
(last_granted[0] && !(| { req_cond[6:2] })) ||
(last_granted[1] && !(| { req_cond[ 0], req_cond[6:2] })));
assign int_requestors_l1[0] = req_cond[0] && (
(last_granted[1] ) ||
(last_granted[2] && !( { req_cond[ 1] })) ||
(last_granted[3] && !(| { req_cond[2:1] })) ||
(last_granted[4] && !(| { req_cond[3:1] })) ||
(last_granted[5] && !(| { req_cond[4:1] })) ||
(last_granted[6] && !(| { req_cond[5:1] })) ||
(last_granted[0] && !(| { req_cond[6:1] })));
//
// Second level arbitration (priority to dbg queue when 'dbg_req_priority' asserted).
assign int_requestors = dbg_req_priority? (7'b000_0001 << LRQ_DBGQ_BIT): int_requestors_l1;
// Track the last granted request 'last_granted' to aid the round-robin algorithm.
wire [6:0] next_last_granted = int_requestors;
wire last_granted_en = int_granted;
dffrle_ns #(6) last_granted_reg (.din(next_last_granted[6:1]), .en(last_granted_en), .q(last_granted[6:1]), .rst_l(rst_l), .clk(clk));
dffsle_ns last_granted_reg0 (.din(next_last_granted[0]), .en(last_granted_en), .q(last_granted[0]), .set_l(rst_l), .clk(clk));
// Determine the transaction type of the 'int_requestors'.
// (Note: At most one bit of int_requestors[] is asserted at a time).
always @(/*AS*/int_requestors or pioackq_ack_nack or piorqq_req_dest
or piorqq_req_rw or sct0rdq_data1_4 or sct0rdq_ue_err
or sct0rdq_unmapped_error or sct1rdq_data1_4 or sct1rdq_ue_err
or sct1rdq_unmapped_error or sct2rdq_data1_4 or sct2rdq_ue_err
or sct2rdq_unmapped_error or sct3rdq_data1_4 or sct3rdq_ue_err
or sct3rdq_unmapped_error) begin
case (1'b1)
int_requestors[LRQ_SCT0RDQ_BIT]: int_req_type = (!sct0rdq_data1_4)? T_RD64: (sct0rdq_ue_err || sct0rdq_unmapped_error)? T_RDER: T_RD16; // SCT0 RDQ.
int_requestors[LRQ_SCT1RDQ_BIT]: int_req_type = (!sct1rdq_data1_4)? T_RD64: (sct1rdq_ue_err || sct1rdq_unmapped_error)? T_RDER: T_RD16; // SCT1 RDQ.
int_requestors[LRQ_SCT2RDQ_BIT]: int_req_type = (!sct2rdq_data1_4)? T_RD64: (sct2rdq_ue_err || sct2rdq_unmapped_error)? T_RDER: T_RD16; // SCT2 RDQ.
int_requestors[LRQ_SCT3RDQ_BIT]: int_req_type = (!sct3rdq_data1_4)? T_RD64: (sct3rdq_ue_err || sct3rdq_unmapped_error)? T_RDER: T_RD16; // SCT3 RDQ.
int_requestors[LRQ_PIORQQ_BIT]: int_req_type = (piorqq_req_rw)? T_NCRD: (piorqq_req_dest == `JBI_PRQQ_DEST_0)? T_NCWR0: // PIO RQQ.
(piorqq_req_dest == `JBI_PRQQ_DEST_4)? T_NCWR4:
(piorqq_req_dest == `JBI_PRQQ_DEST_5)? T_NCWR5:
T_NCWR_OTHER;
int_requestors[LRQ_PIOACKQ_BIT]: int_req_type = (pioackq_ack_nack)? T_INTACK: T_INTNACK; // PIO ACKQ.
int_requestors[LRQ_DBGQ_BIT]: int_req_type = T_RD16; // DEBUG INFO.
default: int_req_type = T_NONE;
endcase
end
// Decrement transaction counters.
assign sct0rdq_dec_count = int_requestors[LRQ_SCT0RDQ_BIT] && int_granted;
assign sct1rdq_dec_count = int_requestors[LRQ_SCT1RDQ_BIT] && int_granted;
assign sct2rdq_dec_count = int_requestors[LRQ_SCT2RDQ_BIT] && int_granted;
assign sct3rdq_dec_count = int_requestors[LRQ_SCT3RDQ_BIT] && int_granted;
assign piorqq_req_adv = int_requestors[LRQ_PIORQQ_BIT] && int_granted;
assign pioackq_req_adv = int_requestors[LRQ_PIOACKQ_BIT] && int_granted;
assign dbg_req_adv = int_requestors[LRQ_DBGQ_BIT] && int_granted;
// "Arbitration Timeout Error" data to log.
//
// Encode the 'int_requestors' into 'jbi_log_arb_myreq'.
reg [2:0] jbi_log_arb_myreq_m1;
always @(/*AS*/int_requestors) begin
case (1'b1)
int_requestors[LRQ_PIORQQ_BIT]: jbi_log_arb_myreq_m1 = 3'b001; // PioReqQ
int_requestors[LRQ_PIOACKQ_BIT]: jbi_log_arb_myreq_m1 = 3'b010; // PioAckQ
int_requestors[LRQ_SCT0RDQ_BIT]: jbi_log_arb_myreq_m1 = 3'b011; // SCT0RdQ
int_requestors[LRQ_SCT1RDQ_BIT]: jbi_log_arb_myreq_m1 = 3'b100; // SCT1RdQ
int_requestors[LRQ_SCT2RDQ_BIT]: jbi_log_arb_myreq_m1 = 3'b101; // SCT2RdQ
int_requestors[LRQ_SCT3RDQ_BIT]: jbi_log_arb_myreq_m1 = 3'b110; // SCT3RdQ
int_requestors[LRQ_DBGQ_BIT]: jbi_log_arb_myreq_m1 = 3'b111; // DbgQ
default: jbi_log_arb_myreq_m1 = 3'b000; // None or PioReqQ held by AOK/DOK flow control.
endcase
end
wire [2:0] next_jbi_log_arb_myreq = jbi_log_arb_myreq_m1;
dff_ns #(3) jbi_log_arb_myreq_reg (.din(next_jbi_log_arb_myreq), .q(jbi_log_arb_myreq), .clk(clk));
//
// Encode the 'int_requestors' into 'jbi_log_arb_reqtype'.
reg [2:0] jbi_log_arb_reqtype_m1;
always @(/*AS*/int_requestors or piorqq_req_dest or piorqq_req_rw) begin
case (1'b1)
int_requestors[LRQ_PIORQQ_BIT]: jbi_log_arb_reqtype_m1 = (piorqq_req_rw)? 3'b001: // NCRD
(piorqq_req_dest == `JBI_PRQQ_DEST_0)? 3'b100: // NCWR to aid0
(piorqq_req_dest == `JBI_PRQQ_DEST_4)? 3'b101: // NCWR to aid4
(piorqq_req_dest == `JBI_PRQQ_DEST_5)? 3'b110: // NCWR to aid5
3'b111; // NCWR to aid-other
default: jbi_log_arb_reqtype_m1 = 3'b000; // Empty
endcase
end
wire [2:0] next_jbi_log_arb_reqtype = jbi_log_arb_reqtype_m1;
dff_ns #(3) jbi_log_arb_reqtype_reg (.din(next_jbi_log_arb_reqtype), .q(jbi_log_arb_reqtype), .clk(clk));
// "Arbitration Timeout Error" counter support.
assign have_trans_waiting = req_in[LRQ_SCT0RDQ_BIT] || req_in[LRQ_SCT1RDQ_BIT] || req_in[LRQ_SCT2RDQ_BIT] || req_in[LRQ_SCT3RDQ_BIT] ||
req_in[LRQ_PIORQQ_BIT] || req_in[LRQ_PIOACKQ_BIT] || (req_in[LRQ_DBGQ_BIT] && !dbg_req_transparent);
// Monitors.
// simtech modcovoff -bpen
// synopsys translate_off
// Check: Exactly 1 bit is set in 'last_granted[]'.
always @(posedge clk) begin
if (rst_l && !(last_granted == 7'b000_0001 || last_granted == 7'b000_0010 || last_granted == 7'b000_0100 ||
last_granted == 7'b000_1000 || last_granted == 7'b001_0000 || last_granted == 7'b010_0000 ||
last_granted == 7'b100_0000)) begin
$dispmon ("jbi_mout_jbi_int_arb", 49, "%d %m: ERROR - Exactly one bit must be set in 'last_granted[]' (%b).", $time, last_granted);
end
end
// Check: At most one bit can be set in 'int_requestors[]'.
always @(posedge clk) begin
if (rst_l && !(int_requestors == 7'b000_0000 ||
int_requestors == 7'b000_0001 || int_requestors == 7'b000_0010 || int_requestors == 7'b000_0100 ||
int_requestors == 7'b000_1000 || int_requestors == 7'b001_0000 || int_requestors == 7'b010_0000 ||
int_requestors == 7'b100_0000)) begin
$dispmon ("jbi_mout_jbi_int_arb", 49, "%d %m: ERROR - At most one bit can be set in 'int_requestors[]' (%b).", $time, int_requestors);
end
end
// synopsys translate_on
// simtech modcovon -bpen
endmodule
// Local Variables:
// verilog-library-directories:("." "../../include" "../../../include")
// verilog-library-files:("../../../common/rtl/swrvr_clib.v")
// verilog-auto-read-includes:t
// verilog-module-parents:("jbi_mout")
// End:
|
// megafunction wizard: %ROM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rominout2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module rominout2 (
address_a,
address_b,
clock,
q_a,
q_b);
input [8:0] address_a;
input [8:0] address_b;
input clock;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./MIF/rominit.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "./MIF/rominit.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 GND 0 0 32 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 GND 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rominout2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rominout2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rominout2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rominout2.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rominout2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rominout2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_TB_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_TB_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_isobufsrc.v"
module top();
// Inputs are registered
reg SLEEP;
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__lpflow_isobufsrc dut (.SLEEP(SLEEP), .A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSRECEIVER_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__BUSRECEIVER_FUNCTIONAL_PP_V
/**
* busreceiver: Bus signal receiver.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__busreceiver (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSRECEIVER_FUNCTIONAL_PP_V |
(* * Hoare: Hoare Logic, Part I *)
(** * Hoare_J: ホーア論理 Part I *)
Require Import Coq.Bool.Bool.
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import Coq.omega.Omega.
Require Import SfLib.
Require Import Imp.
Require Import Maps.
(* In the past couple of chapters, we've begun applying the
mathematical tools developed in the first part of the course to
studying the theory of a small programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than of particular programs in the language. These
included:
- determinism of evaluation
- equivalence of some different ways of writing down the
definitions (e.g., functional and relational definitions of
arithmetic expression evaluation)
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the [Equiv] chapter).
If we stopped here, we would already have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties. All of
these properties are things that language designers, compiler
writers, and users might care about knowing. Indeed, many of them
are so fundamental to our understanding of the programming
languages we deal with that we might not consciously recognize
them as "theorems." But properties that seem intuitively obvious
can sometimes be quite subtle (sometimes also subtly wrong!).
We'll return to the theme of metatheoretic properties of whole
languages later in the book when we discuss _types_ and _type
soundness_. In this chapter, though, we turn to a different set
of issues.
Our goal is to carry out some simple examples of _program
verification_ -- i.e., to use the precise definition of Imp to
prove formally that particular programs satisfy particular
specifications of their behavior. We'll develop a reasoning
system called _Floyd-Hoare Logic_ -- often shortened to just
_Hoare Logic_ -- in which each of the syntactic constructs of Imp
is equipped with a generic "proof rule" that can be used to reason
compositionally about the correctness of programs involving this
construct.
Hoare Logic originated in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a multitude of tools that are being used in
academia and industry to specify and verify real software
systems.
Hoare Logic combines two beautiful ideas: a natural way of
writing down _specifications_ of programs, and a _compositional
proof technique_ for proving that programs are correct with
respect to such specifications -- where by "compositional" we mean
that the structure of proofs directly mirrors the structure of the
programs that they are about. *)
(** このところの数章で、コースの最初のパートで用意した数学的道具立てを、
小さなプログラミング言語 Imp の理論の学習に適用し始めています。
- Imp の抽象構文木(_abstract syntax trees_)の型を定義しました。
また、操作的意味論(_operational semantics_)を与える評価関係
(_evaluation relation_、状態間の部分関数)も定義しました。
定義した言語は小さいですが、
C, C++, Java などの本格的な言語の主要な機能を持っています。
その中には変更可能な状態や、いくつかのよく知られた制御構造も含まれます。
- いくつものメタ理論的性質(_metatheoretic properties_)を証明しました。
"メタ"というのは、言語で書かれた特定のプログラムの性質ではなく言語自体の性質という意味です。
証明したものには、以下のものが含まれます:
- 評価の決定性
- 異なった書き方をした定義の同値性(例えば、関数によるものと関係による演算式の評価定義)
- プログラムのあるクラスの、停止性の保証
- プログラムの動作の同値性([Equiv_J.v]の章において)
もしここで止めたとしても、すでに有用なものを持っていることになります。
それは、プログラミング言語とその特性を定義し議論する、数学的に正確で、
柔軟で、使いやすい、主要な性質に適合した道具立てです。
これらの性質は、言語を設計する人、コンパイラを書く人、
そしてユーザも知っておくべきものです。
実際、その多くは我々が扱うプログラミング言語を理解する上で本当に基本的なことですので、
"定理"と意識することはなかったかもしれません。
しかし、直観的に明らかだと思っている性質はしばしばとても曖昧です。(
時には微妙に間違っていることもあります!)
言語全体のメタ理論的性質の問題については、 後に型(_types_)とその健全性(_type soundness_)を議論する際に再度出てきます。
この章では、別の話題について向き合います。
我々の目的は、シンプルなプログラムの検証(_program verification_)
-- Imp を厳密に定義し、ある特定のプログラム(つまり階乗計算と遅い引き算)が
その動作についての特定の仕様を満たすことを、形式的に証明すること--
を行うことです。
一般にフロイド-ホーア論理(_Floyd-Hoare Logic_)、しばしば、 ホーア論理(_Hoare Logic_)と
呼ばれている推論システムを作ります。
この推論システムの中では、Imp の各構文要素に対して1つの一般的な"証明規則" (proof rule)が与えられ、
これによってその構文要素を含むプログラムの正当性の推論が構成的にできるようになっています。
ホーア論理の起源は1960年代です。そして今現在まで継続してさかんに研究がされています。
実際のソフトウェアシステムの仕様を定め検証するために学術的、工業的に使われている
多くのツールは、 ホーア論理を核としているのです。
ホーア論理は2つの美しい考えから構成されています。プログラムの仕様(_specification_)
を自然に記述する方法と、プログラムがその仕様を遵守していることを証明する合成的証明法(_compositional
proof technique_)です。ここでの"合成的"(compositional)という意味は、
証明の構造が証明対象となるプログラムの構造を直接的に反映しているということです。*)
(* ####################################################### *)
(* * Assertions *)
(** ** 表明 *)
(* If we're going to talk about specifications of programs, the first
thing we'll want is a way of making _assertions_ about properties
that hold at particular points in time -- i.e., properties that
may or may not be true of a given state of the memory. *)
(** プログラムの仕様について話そうとするとき、最初に欲しくなるのは、
ある特定の時点で成立している性質 -- つまり、与えられたメモリ状態で真になり得るか、
なり得ないかの性質 -- についての表明(_assertions_)を作る方法です。*)
Definition Assertion := state -> Prop.
(* **** Exercise: 1 star (assertions) *)
(** **** 練習問題: ★ (assertions) *)
(* Paraphrase the following assertions in English.
[[
fun st => asnat (st X) = 3
fun st => asnat (st X) = x
fun st => asnat (st X) <= asnat (st Y)
fun st => asnat (st X) = 3 \/ asnat (st X) <= asnat (st Y)
fun st => (asnat (st Z)) * (asnat (st Z)) <= x
/\ ~ (((S (asnat (st Z))) * (S (asnat (st Z)))) <= x)
fun st => True
fun st => False
]]
[] *)
(** 以下の表明を日本語に直しなさい。
[[
fun st => asnat (st X) = 3
fun st => asnat (st X) = x
fun st => asnat (st X) <= asnat (st Y)
fun st => asnat (st X) = 3 \/ asnat (st X) <= asnat (st Y)
fun st => (asnat (st Z)) * (asnat (st Z)) <= x
/\ ~ (((S (asnat (st Z))) * (S (asnat (st Z)))) <= x)
fun st => True
fun st => False
]]
[] *)
(* This way of writing assertions is formally correct -- it
precisely captures what we mean, and it is exactly what we will
use in Coq proofs -- but it is a bit heavy to look at, for several
reasons. First, every single assertion that we ever write is
going to begin with [fun st => ]; (2) this state [st] is the only
one that we ever use to look up variables (we never need to talk
about two different states at the same time); and (3) all the
variable lookups in assertions are cluttered with [asnat] or
[aslist] coercions. When we are writing down assertions
informally, we can make some simplifications: drop the initial
[fun st =>], write just [X] instead of [st X], and elide [asnat]
and [aslist]. *)
(** この方法で表明を書くことは、形式的に正しいのです。
-- この方法は意図することを正確におさえています。
そしてこれがまさに Coq の証明で使う方法なのです。
しかしこれはいくつかの理由から、若干ヘビーに見えます。
(1)すべての個々の表明は、[fun st=> ]から始まっています。
(2)状態[st]は変数を参照するために使うただ1つのものです
(2つの別々の状態を同時に考える必要はありません)。
(3)表明で参照するすべての変数は[asnat]または[aslist]の強制型変換により、
取り散らかっています。
表明を非形式的に書くときには、いくらか簡単にします。
最初の[fun st =>]は書かず、[st X]のかわりに単に[X]と書きます。
また[asnat]と[aslist]は略します。*)
(* Informally, instead of writing
[[
fun st => (asnat (st Z)) * (asnat (st Z)) <= x
/\ ~ ((S (asnat (st Z))) * (S (asnat (st Z))) <= x)
]]
we'll write just
[[
Z * Z <= x
/\ ~((S Z) * (S Z) <= x).
]]
*)
(** 非形式的には、次のように書くかわりに
[[
fun st => (asnat (st Z)) * (asnat (st Z)) <= x
/\ ~ ((S (asnat (st Z))) * (S (asnat (st Z))) <= x)
]]
次のように書きます。
[[
Z * Z <= x
/\ ~((S Z) * (S Z) <= x).
]]
*)
(* ####################################################### *)
(* ** Hoare Triples *)
(** ** ホーアの三つ組 *)
(* Next, we need a way of specifying -- making claims about -- the
behavior of commands. *)
(** 次に、コマンドの振舞いの仕様を定める、
つまりコマンドの振舞いについての表明を作る方法が必要です。*)
(* Since we've defined assertions as a way of making claims about the
properties of states, and since the behavior of a command is to
transform one state to another, a claim about a command takes the
following form:
- "If [c] is started in a state satisfying assertion [P], and if
[c] eventually terminates, then the final state is guaranteed
to satisfy the assertion [Q]."
Such a claim is called a _Hoare Triple_. The property [P] is
called the _precondition_ of [c]; [Q] is the _postcondition_ of
[c]. *)
(** 表明を、状態の性質について表明するものとして定義してきました。
そして、コマンドの振舞いは、状態を別の状態に変換するものです。
これから、コマンドについての表明は次の形をとります:
- "もし [c] が表明 [P] を満たす状態から開始され、また、
[c]がいつかは停止するならば、最終状態では、表明[Q]が成立することを保証する。"
この表明は ホーアの三つ組(_Hoare Triple_)と呼ばれます。
性質[P]は[c]の事前条件(_precondition_)と呼ばれます。
[Q]は[c]の事後条件(_postcondition_)と呼ばれます。*)
(* (Traditionally, Hoare triples are written [{P} c {Q}], but single
braces are already used for other things in Coq.) *)
(** (伝統的に、ホーアの三つ組は [{P} c {Q}]と書かれます。
しかし Coq では一重の中カッコは別の意味で既に使われています。) *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
(* Since we'll be working a lot with Hoare triples, it's useful to
have a compact notation:
[[
{{P}} c {{Q}}.
]]
*)
(** ホーアの三つ組を今後多用するので、簡潔な記法を用意すると便利です:
[[
{{P}} c {{Q}}.
]]
*)
Notation "{{ P }} c" := (hoare_triple P c (fun st => True)) (at level 90)
: hoare_spec_scope.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q) (at level 90, c at next level)
: hoare_spec_scope.
Open Scope hoare_spec_scope.
(* (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context. The first notation -- with missing postcondition -- will
not actually be used here; it's just a placeholder for a notation
that we'll want to define later, when we discuss decorated
programs.) *)
(** この[hoare_spec_scope]アノテーションは、Coqに、
この記法はグローバルではなく特定のコンテキストで使うものであることを伝えるものです。
[Open Scope]は、このファイルがそのコンテキストであることを Coq に伝えます。
最初の、事後条件を持たない記法は、ここで実際に使うことはありません。
これは単に後に定義する記法のための場所を用意したものです。
後に修飾付きプログラムについて議論する際に使います。*)
(* **** Exercise: 1 star (triples) *)
(** **** 練習問題: ★ (triples) *)
(* Paraphrase the following Hoare triples in English.
[[
{{True}} c {{X = 5}}
{{X = x}} c {{X = x + 5)}}
{{X <= Y}} c {{Y <= X}}
{{True}} c {{False}}
{{X = x}}
c
{{Y = real_fact x}}.
{{True}}
c
{{(Z * Z) <= x /\ ~ (((S Z) * (S Z)) <= x)}}
]]
*)
(** 以下のホーアの三つ組を日本語に直しなさい。
[[
{{True}} c {{X = 5}}
{{X = x}} c {{X = x + 5)}}
{{X <= Y}} c {{Y <= X}}
{{True}} c {{False}}
{{X = x}}
c
{{Y = real_fact x}}.
{{True}}
c
{{(Z * Z) <= x /\ ~ (((S Z) * (S Z)) <= x)}}
]]
*)
(** [] *)
(* **** Exercise: 1 star (valid_triples) *)
(** **** 練習問題: ★ (valid_triples) *)
(* Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
[[
{{True}} X ::= 5 {{X = 5}}
{{X = 2}} X ::= X + 1 {{X = 3}}
{{True}} X ::= 5; Y ::= 0 {{X = 5}}
{{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
{{True}} SKIP {{False}}
{{False}} SKIP {{True}}
{{True}} WHILE True DO SKIP END {{False}}
{{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
{{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
]]
*)
(** 以下のホーアの三つ組のうち、正しい(_valid_)ものを選択しなさい。
-- 正しいとは、[P],[c],[Q]の関係が真であるということです。
[[
{{True}} X ::= 5 {{X = 5}}
{{X = 2}} X ::= X + 1 {{X = 3}}
{{True}} X ::= 5; Y ::= 0 {{X = 5}}
{{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
{{True}} SKIP {{False}}
{{False}} SKIP {{True}}
{{True}} WHILE True DO SKIP END {{False}}
{{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
{{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
]]
*)
(* (Note that we're using informal mathematical notations for
expressions inside of commands, for readability. We'll continue
doing so throughout the chapter.) *)
(** (読みやすくするため、コマンド内の式について、
非形式的な数学記法を使います。この章の最後までその方針をとります。) *)
(** [] *)
(* To get us warmed up, here are two simple facts about Hoare
triples. *)
(** ウォーミングアップとして、ホーアの三つ組についての2つの事実を見てみます。*)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ####################################################### *)
(* ** Weakest Preconditions *)
(** ** 最弱事前条件 *)
(* Some Hoare triples are more interesting than others. For example,
[[
{{ False }} X ::= Y + 1 {{ X <= 5 }}
]]
is _not_ very interesting: it is perfectly valid, but it tells us
nothing useful. Since the precondition isn't satisfied by any
state, it doesn't describe any situations where we can use the
command [X ::= Y + 1] to achieve the postcondition [X <= 5].
By contrast,
[[
{{ Y <= 4 /\ Z = 0 }} X ::= Y + 1 {{ X <= 5 }}
]]
is useful: it tells us that, if we can somehow create a situation
in which we know that [Y <= 4 /\ Z = 0], then running this command
will produce a state satisfying the postcondition. However, this
triple is still not as useful as it could be, because the [Z = 0]
clause in the precondition actually has nothing to do with the
postcondition [X <= 5]. The _most_ useful triple (with the same
command and postcondition) is this one:
[[
{{ Y <= 4 }} X ::= Y + 1 {{ X <= 5 }}
]]
In other words, [Y <= 4] is the _weakest_ valid precondition of
the command [X ::= Y + 1] for the postcondition [X <= 5]. *)
(** いくつかの ホーアの三つ組は、他のものより興味深いものです。例えば:
[[
{{ False }} X ::= Y + 1 {{ X <= 5 }}
]]
はあまり興味深いものではありません。これは完全に正しいものですが、
何も有用なことを伝えてくれません。事前条件がどのような状態でも満たされないことから、
コマンド [X ::= Y + 1] によって事後条件 [X <= 5]
に至るどのような状況も記述していません。
一方、
[[
{{ Y <= 4 /\ Z = 0 }} X ::= Y + 1 {{ X <= 5 }}
]]
は有用です。これは、何らかの方法で[Y <= 4 /\ Z = 0]であるという状況を作りあげた後、
このコマンドを実行すると事後条件を満たす状態になる、ということを伝えています。
しかしながら、この三つ組はもう少し改良できます。なぜなら、
事前条件の[Z = 0]という節は、実際には事後条件[X <= 5]に何の影響も与えないからです。
(このコマンドと事後条件のもとで)最も有効な三つ組は次のものです:
[[
{{ Y <= 4 }} X ::= Y + 1 {{ X <= 5 }}
]]
言いかえると、[Y <= 4] は事後条件[X <= 5]に対してコマンド[X ::= Y + 1]
の最弱の(_weakest_)正しい事前条件です。*)
(* In general, we say that "[P] is the weakest precondition of
[c] for [Q]" if
- [{{P}} c {{Q}}], and
- whenever [P'] is an assertion such that [{{P'}} c {{Q}}], we
have [P' st] implies [P st] for all states [st]. *)
(** 一般に、次が成立するとき"[P]は[Q]に対する[c]の最弱事前条件である"と言います:
- [{{P}} c {{Q}}], かつ
- [P'] が [{{P'}} c {{Q}}] を満たす表明ならば,
すべての状態 [st] について、[P' st] ならば [P st] となる。 *)
(* That is, [P] is the weakest precondition of [c] for [Q]
if (a) [P] _is_ a precondition for [Q] and [c], and (b) [P] is the
_weakest_ (easiest to satisfy) assertion that guarantees [Q] after
[c]. *)
(** つまり、[P]が[Q]に対する[c]の最弱事前条件であるとは、
(a) [P] は [Q] と [c] の事前条件で、かつ、
(b) [P]は[c]の後で[Q]を保証する最弱の(_weakest_)(もっとも簡単に充足できる)
表明である、ということです。*)
(* **** Exercise: 1 star (wp) *)
(** **** 練習問題: ★ (wp) *)
(* What are the weakest preconditions of the following commands
for the following postconditions?
[[
{{ ? }} SKIP {{ X = 5 }}
{{ ? }} X ::= Y + Z {{ X = 5 }}
{{ ? }} X ::= Y {{ X = Y }}
{{ ? }}
IFB X == 0 THEN Y ::= Z + 1 ELSE Y ::= W + 2 FI
{{ Y = 5 }}
{{ ? }}
X ::= 5
{{ X = 0 }}
{{ ? }}
WHILE True DO X ::= 0 END
{{ X = 0 }}
]]
*)
(** 以下のコマンドの以下の事後条件に対する最弱事前条件を示しなさい。
[[
{{ ? }} SKIP {{ X = 5 }}
{{ ? }} X ::= Y + Z {{ X = 5 }}
{{ ? }} X ::= Y {{ X = Y }}
{{ ? }}
IFB X == 0 THEN Y ::= Z + 1 ELSE Y ::= W + 2 FI
{{ Y = 5 }}
{{ ? }}
X ::= 5
{{ X = 0 }}
{{ ? }}
WHILE True DO X ::= 0 END
{{ X = 0 }}
]]
*)
(** [] *)
(* ####################################################### *)
(* ** Proof Rules *)
(** ** 証明規則 *)
(* The goal of Hoare logic is to provide a _compositional_
method for proving the validity of Hoare triples. That is, the
structure of a program's correctness proof should mirror the
structure of the program itself. To this end, in the sections
below, we'll introduce one rule for reasoning about each of the
different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules that are useful for gluing things
together. *)
(** ホーア論理のゴールは、ホーアの三つ組の正しさを証明する"合成的"手法を提供することです。
つまり、プログラムの正しさの証明の構造は、
プログラムの構造をそのまま反映したものになるということです。
このゴールのために、以降の節では、Impのコマンドのいろいろな構文要素のそれぞれ対して、
その構文要素について推論するための規則を1つずつ導入します。代入に1つ、
コマンド合成に1つ、条件分岐に1つ、等です。それに加えて、
複数のものを結合するために有用な2つの"構造的"規則を導入します。*)
(* ####################################################### *)
(* *** Assignment *)
(** *** 代入 *)
(* The rule for assignment is the most fundamental of the Hoare logic
proof rules. Here's how it works.
Consider this (valid) Hoare triple:
[[
{{ Y = 1 }} X ::= Y {{ X = 1 }}
]]
In English: if we start out in a state where the value of [Y]
is [1] and we assign [Y] to [X], then we'll finish in a
state where [X] is [1]. That is, the property of being equal
to [1] gets transferred from [Y] to [X].
Similarly, in
[[
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
]]
the same property (being equal to one) gets transferred to
[X] from the expression [Y + Z] on the right-hand side of
the assignment.
More generally, if [a] is _any_ arithmetic expression, then
[[
{{ a = 1 }} X ::= a {{ X = 1 }}
]]
is a valid Hoare triple.
Even more generally, [a] is _any_ arithmetic expression and [Q] is
_any_ property of numbers, then
[[
{{ Q(a) }} X ::= a {{ Q(X) }}
]]
is a valid Hoare triple.
Rephrasing this a bit gives us the general Hoare rule for
assignment:
[[
{{ Q where a is substituted for X }} X ::= a {{ Q }}
]]
For example, these are valid applications of the assignment
rule:
[[
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 3 = 3 }} X ::= 3 {{ X = 3 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
]]
*)
(** 代入の規則は、ホーア論理の証明規則の中で最も基本的なものです。
この規則は次のように働きます。
次の(正しい)ホーアの三つ組を考えます。
[[
{{ Y = 1 }} X ::= Y {{ X = 1 }}
]]
日本語で言うと、[Y]の値が[1]である状態から始めて、[X]を[Y]に代入するならば、
[X]が[1]である状態になる、ということです。
つまり、[1]である、という性質が[X]から[Y]に移された、ということです。
同様に、
[[
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
]]
においては、同じ性質(1であること)が代入の右辺の[Y+Z]から[X]に移動されています。
より一般に、[a]が「任意の」算術式のとき、
[[
{{ a = 1 }} X ::= a {{ X = 1 }}
]]
は正しいホーアの三つ組になります。
さらに一般化して、[a]が「任意の」算術式、[Q]が数についての「任意の」性質のとき、
[[
{{ Q(a) }} X ::= a {{ Q(X) }}
]]
は正しいホーアの三つ組です。
これを若干言い換えると、代入に対する一般ホーア規則になります:
[[
{{ Q において X を a で置換したもの }} X ::= a {{ Q }}
]]
例えば、以下は、代入規則の正しい適用です:
[[
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 3 = 3 }} X ::= 3 {{ X = 3 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
]]
*)
(* We could try to formalize the assignment rule directly in Coq by
treating [Q] as a family of assertions indexed by arithmetic
expressions -- something like this:
[[
Theorem hoare_asgn_firsttry :
forall (Q : aexp -> Assertion) V a,
{{fun st => Q a st}} (V ::= a) {{fun st => Q (AId V) st}}.
]]
But this formulation is not very nice, for two reasons.
First, it is not quite true! (As a counterexample, consider
a [Q] that inspects the _syntax_ of its argument, such as
[[
Definition Q (a:aexp) : Prop :=
match a with
| AID (Id 0) => fun st => False
| _ => fun st => True
end.
]]
together with any [V = Id 0] because a precondition that reduces
to [True] leads to a postcondition that is [False].) And second,
even if we could prove something similar to this, it would be
awkward to use. *)
(** [Q]を、算術式をインデックスとする表明の族として扱うことで、
代入規則を Coq で直接形式化してみることもできます。例えば次のようになります。
[[
Theorem hoare_asgn_firsttry :
forall (Q : aexp -> Assertion) V a,
{{fun st => Q a st}} (V ::= a) {{fun st => Q (AId V) st}}.
]]
しかし、この形式化は2つの理由であまり良くないのです。
第一に、この式は本当に正しいとは言えないのです!
(反例として、[Q]として自分の引数の「構文」を調べるものを考えてみましょう。
次のようなものです:
[[
Definition Q (a:aexp) : Prop :=
match a with
| AID (Id 0) => fun st => False
| _ => fun st => True
end.
]]
このとき、代入として、[V = Id 0] を考えると、事前条件は[True]となりますが、
事後条件は[False]になります。)第二の理由は、たとえ同様のことが証明できたとしても、
これは使いにくいのです。*)
(* A much smoother way of formalizing the rule arises from the
following observation:
- "[Q] where a is substituted for [X]" holds in a state [st] iff
[Q] holds in the state [update st X (aeval st a)]. *)
(** 規則を形式化するはるかにスムーズな方法は、以下の洞察から得られます:
- "[Q]において[X]を a で置換したもの"が状態[st]で成立する必要十分条件は、
[Q]が状態 [update st X (aeval st a)] で成立することである。*)
(* That is, asserting that a substituted variant of [Q] holds in
some state is the same as asserting that [Q] itself holds in
a substituted variant of the state. *)
(** つまり、ある状態で、[Q]を置換してできるものを表明することは、
その状態を置換してできる状態で、[Q]を表明することと同じだということです。*)
(* Here is the definition of substitution in a state: *)
(** 状態の置換を次のように定義します: *)
Definition assn_sub V a Q : Assertion :=
fun (st : state) =>
Q (update st V (aeval st a)).
(* This gives us the formal proof rule for assignment:
[[[
------------------------------ (hoare_asgn)
{{assn_sub V a Q}} V::=a {{Q}}
]]]
*)
(** これを使って、代入の証明規則を形式的に与えます:
[[
------------------------------ (hoare_asgn)
{{assn_sub V a Q}} V::=a {{Q}}
]]
*)
Theorem hoare_asgn : forall Q V a,
{{assn_sub V a Q}} (V ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q V a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(* Here's a first formal proof using this rule. *)
(** この規則を使った最初の形式的証明が次のものです。*)
Example assn_sub_example :
{{fun st => 3 = 3}}
(X ::= (ANum 3))
{{fun st => asnat (st X) = 3}}.
Proof.
assert ((fun st => 3 = 3) =
(assn_sub X (ANum 3) (fun st => asnat (st X) = 3))).
Case "Proof of assertion".
unfold assn_sub. reflexivity.
rewrite -> H. apply hoare_asgn. Qed.
(* This proof is a little clunky because the [hoare_asgn] rule
doesn't literally apply to the initial goal: it only works with
triples whose precondition has precisely the form [assn_sub Q V a]
for some [Q], [V], and [a]. So we have to start with asserting a
little lemma to get the goal into this form.
Doing this kind of fiddling with the goal state every time we
want to use [hoare_asgn] would get tiresome pretty quickly.
Fortunately, there are easier alternatives. One simple one is
to state a slightly more general theorem that introduces an
explicit equality hypothesis: *)
(** この証明はあまり綺麗ではありません。なぜなら、
[hoare_asgn]規則が最初のゴールに直接適用されてはいないからです。
この規則は、事前条件が、
何らかの[Q]、[V]、[a]について[assn_sub Q V a]という形をしているときのみに適用できます。
このため、ゴールをこの形にするためのちょっとした補題から始めなければならないのです。
[hoare_asgn]を使おうとするときに、
毎回ゴール状態に対してこのような小細工をするのは面倒です。
幸い、より簡単な方法があります。
その一つは、明示的な等式の形の仮定を導く、いくらか一般性の高い定理を示すことです: *)
Theorem hoare_asgn_eq : forall Q Q' V a,
Q' = assn_sub V a Q ->
{{Q'}} (V ::= a) {{Q}}.
Proof.
intros Q Q' V a H. rewrite H. apply hoare_asgn. Qed.
(* With this version of [hoare_asgn], we can do the proof much
more smoothly. *)
(** [hoare_asgn]のこのバージョンを使うことで、証明をよりスムーズに行うことができます。*)
Example assn_sub_example' :
{{fun st => 3 = 3}}
(X ::= (ANum 3))
{{fun st => asnat (st X) = 3}}.
Proof.
apply hoare_asgn_eq. reflexivity. Qed.
(* **** Exercise: 2 stars (hoare_asgn_examples) *)
(** **** 練習問題: ★★ (hoare_asgn_examples) *)
(* Translate these informal Hoare triples...
[[
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
]]
...into formal statements and use [hoare_asgn_eq] to prove
them. *)
(** 次の非形式的なホーアの三つ組...
[[
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
]]
...を、形式的記述に直し、[hoare_asgn_eq]を使って証明しなさい。*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 3 stars (hoarestate2) *)
(** **** 練習問題: ★★★ (hoarestate2) *)
(* The assignment rule looks backward to almost everyone the first
time they see it. If it still seems backward to you, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
[[
{{ True }} X ::= a {{ X = a }}
]]
Explain what is wrong with this rule.
(* FILL IN HERE *)
*)
(** 代入規則は、最初に見たとき、ほとんどの人が後向きの規則であるように感じます。
もし今でも後向きに見えるならば、前向きバージョンの規則を考えてみるのも良いかもしれません。
次のものは自然に見えます:
[[
{{ True }} X ::= a {{ X = a }}
]]
この規則の問題点を指摘しなさい。
(* FILL IN HERE *)
*)
(** [] *)
(* **** Exercise: 3 stars, optional (hoare_asgn_weakest) *)
(** **** 練習問題: ★★★, optional (hoare_asgn_weakest) *)
(* Show that the precondition in the rule [hoare_asgn] is in fact the
weakest precondition. *)
(** [hoare_asgn]規則の事前条件が、本当に最弱事前条件であることを示しなさい。*)
Theorem hoare_asgn_weakest : forall P V a Q,
{{P}} (V ::= a) {{Q}} ->
forall st, P st -> assn_sub V a Q st.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(* *** Consequence *)
(** *** 帰結 *)
(* The discussion above about the awkwardness of applying the
assignment rule illustrates a more general point: sometimes the
preconditions and postconditions we get from the Hoare rules won't
quite be the ones we want -- they may (as in the above example) be
logically equivalent but have a different syntactic form that
fails to unify with the goal we are trying to prove, or they
actually may be logically weaker (for preconditions) or
stronger (for postconditions) than what we need.
For instance, while
[[
{{3 = 3}} X ::= 3 {{X = 3}},
]]
follows directly from the assignment rule, the more natural triple
[[
{{True}} X ::= 3 {{X = 3}}.
]]
does not. This triple is also valid, but it is not an instance of
[hoare_asgn] (or [hoare_asgn_eq]) because [True] and [3 = 3] are
not syntactically equal assertions.
In general, if we can derive [{{P}} c {{Q}}], it is valid to
change [P] to [P'] as long as [P'] is strong enough to imply [P],
and change [Q] to [Q'] as long as [Q] implies [Q'].
This observation is captured by the following _Rule of
Consequence_.
[[[
{{P'}} c {{Q'}}
P implies P' (in every state)
Q' implies Q (in every state)
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
]]]
For convenience, we can state two more consequence rules -- one for
situations where we want to just strengthen the precondition, and
one for when we want to just weaken the postcondition.
[[[
{{P'}} c {{Q}}
P implies P' (in every state)
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' implies Q (in every state)
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
]]]
*)
(** 代入規則の適用のぎこちなさに関する上記の議論は、より一般的なポイントを示しています。
ホーア規則から得られる事前条件と事後条件は欲しいものではないことがしばしばあるのです。
(上の例のように)それらは論理的に同値ですが、構文的に違う形をしているために、
証明しようと思うゴールと単一化することができないのです。あるいは、(事前条件について)
必要なものより論理的に弱かったり、(事後条件について)論理的に強かったりするのです。
例えば、
[[
{{3 = 3}} X ::= 3 {{X = 3}},
]]
が代入規則に直接従うのに対して、より自然な三つ組
[[
{{True}} X ::= 3 {{X = 3}}.
]]
はそうではないのです。この三つ組も正しいのですが、[hoare_asgn]
(または [hoare_asgn_eq]) のインスタンスではないのです。
なぜなら、[True] と [3 = 3] は、構文的に等しい表明ではないからです。
一般に、[{{P}} c {{Q}}] が導出できるとき、
[P']ならば[P]が言えるだけ[P']が十分強ければ、[P]を[P']に置き換えることは正しく、
また[Q]ならば[Q']が言えるときには、[Q]を[Q']に置き換えることは正しいのです。
この洞察をまとめたものが、次の帰結規則(_Rule of Consequence_)です。
[[
{{P'}} c {{Q'}}
P implies P' (in every state)
Q' implies Q (in every state)
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
]]
便宜上、さらに2つの帰結規則を用意します。1つは事前条件を強めるだけのもの、
もう1つは事後条件を弱めるだけのものです。
[[
{{P'}} c {{Q}}
P implies P' (in every state)
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' implies Q (in every state)
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
]]
*)
(* Here are the formal versions: *)
(** 以下が形式化版です: *)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
(forall st, P st -> P' st) ->
(forall st, Q' st -> Q st) ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
intros st st' Hc HP.
apply HQ'Q. apply (Hht st st'). assumption.
apply HPP'. assumption. Qed.
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
(forall st, P st -> P' st) ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
apply hoare_consequence with (P' := P') (Q' := Q);
try assumption.
intros st H. apply H. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
(forall st, Q' st -> Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
apply hoare_consequence with (P' := P) (Q' := Q');
try assumption.
intros st H. apply H. Qed.
(* For example, we might use (the "[_pre]" version of) the
consequence rule like this:
[[
{{ True }} =>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
]]
Or, formally...
*)
(** (例えば、("[_pre]"版の)帰結規則を次のように使うことができます:
[[
{{ True }} =>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
]]
あるいは、形式化すると...
*)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => asnat (st X) = 1}}.
Proof.
apply hoare_consequence_pre with (P' := (fun st => 1 = 1)).
apply hoare_asgn_eq. reflexivity.
intros st H. reflexivity. Qed.
(* ####################################################### *)
(* *** Digression: The [eapply] Tactic *)
(** *** 余談: [eapply] タクティック *)
(* This is a good moment to introduce another convenient feature
of Coq. Having to write [P'] explicitly in the example above
is a bit annoying because the very next thing we are going to
do -- applying the [hoare_asgn] rule -- is going to determine
exactly what it should be. We can use [eapply] instead of
[apply] to tell Coq, essentially, "The missing part is going
to be filled in later." *)
(** ここで、良い機会ですので、Coq の別の便利な機能を紹介しておきましょう。
上述の例で明示的に[P']を書かなければならないことは、少々やっかいです。
なぜなら、すぐ次にやること、つまり[hoare_asgn]規則を適用すること、が、
まさに、それがどうでなければならないかを決定することだからです。
こういう場合、[apply]の代わりに[eapply]を使うことができます。
そうすることは、本質的に、「抜けている部分は後で埋めます」と
Coq に伝えることになります。*)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => asnat (st X) = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn_eq. reflexivity. (* or just [apply hoare_asgn.] *)
intros st H. reflexivity. Qed.
(* In general, [eapply H] tactic works just like [apply H]
except that, instead of failing if unifying the goal with the
conclusion of [H] does not determine how to instantiate all
of the variables appearing in the premises of [H], [eapply H]
will replace these variables with _existential variables_
(written [?nnn]) as placeholders for expressions that will be
determined (by further unification) later in the proof.
There is also an [eassumption] tactic that works similarly. *)
(** 一般に、[eapply H]タクティックは[apply H]とほぼ同様にはたらきますが、
次の点が違います。
[H]の結論部とゴールとの単一化では[H]の前提部に現れる変数のすべてが具体化されなかった場合、
[apply H]は失敗しますが、[eapply H]は残った変数を存在変数
(_existential variables_、[?nnn]と記述される)に置換します。
存在変数は、証明の以降の部分で(さらなる単一化により)決定される式が入る場所を示すものです。
他に同様のはたらきをするものには、[eassumption]タクティックがあります。*)
(* ####################################################### *)
(* *** Skip *)
(** *** Skip *)
(* Since [SKIP] doesn't change the state, it preserves any
property P:
[[[
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
]]]
*)
(** [SKIP]は状態を変えないことから、任意の性質 P を保存します:
[[
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
]]
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ####################################################### *)
(* *** Sequencing *)
(** *** コマンド合成 *)
(* More interestingly, if the command [c1] takes any state where
[P] holds to a state where [Q] holds, and if [c2] takes any
state where [Q] holds to one where [R] holds, then doing [c1]
followed by [c2] will take any state where [P] holds to one
where [R] holds:
[[[
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;c2 {{ R }}
]]]
*)
(** より興味深いことに、コマンド[c1]が、[P]が成立する任意の状態を[Q]が成立する状態にし、
[c2]が、[Q]が成立する任意の状態を[R]が成立する状態にするとき、
[c1]に続いて[c2]を行うことは、[P]が成立する任意の状態を[R]が成立する状態にします:
[[
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;c2 {{ R }}
]]
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); try assumption. Qed.
(* Note that, in the formal rule [hoare_seq], the premises are
given in "backwards" order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule. *)
(** 形式的規則[hoare_seq]においては、
前提部分が「逆順」である([c1]の前に[c2]が来る)ことに注意してください。
この順は、規則を使用する多くの場面で情報の自然な流れにマッチするのです。*)
(* Informally, a nice way of recording a proof using this rule
is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
[[
{{ a = n }}
X ::= a;
{{ X = n }} <---- decoration for Q
SKIP
{{ X = n }}
]]
*)
(** 非形式的には、この規則を利用した証明を記録する良い方法は、
[c1]と[c2]の間に中間表明[Q]を記述する"修飾付きプログラム"の様にすることです:
[[
{{ a = n }}
X ::= a;
{{ X = n }} <---- 修飾 Q
SKIP
{{ X = n }}
]]
*)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
Case "right part of seq".
apply hoare_skip.
Case "left part of seq".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity. Qed.
(* **** Exercise: 2 stars (hoare_asgn_example4) *)
(** **** 練習問題: ★★ (hoare_asgn_example4) *)
(* Translate this decorated program into a formal proof:
[[
{{ True }} =>
{{ 1 = 1 }}
X ::= 1;
{{ X = 1 }} =>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
]]
*)
(** 次の修飾付きプログラムを形式的証明に直しなさい:
[[
{{ True }} =>
{{ 1 = 1 }}
X ::= 1;
{{ X = 1 }} =>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
]]
*)
Example hoare_asgn_example4 :
{{fun st => True}} (X ::= (ANum 1); Y ::= (ANum 2))
{{fun st => asnat (st X) = 1 /\ asnat (st Y) = 2}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 3 stars, optional (swap_exercise) *)
(** **** 練習問題: ★★★, optional (swap_exercise) *)
(* Write an Imp program [c] that swaps the values of [X] and [Y]
and show (in Coq) that it satisfies the following
specification:
[[
{{X <= Y}} c {{Y <= X}}
]]
*)
(** [X]と[Y]の値を交換するImpプログラム[c]を書き、
それが次の仕様を満たすことを(Coq で)示しなさい:
[[
{{X <= Y}} c {{Y <= X}}
]]
*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 3 stars, optional (hoarestate1) *)
(** **** 練習問題: ★★★, optional (hoarestate1) *)
(* Explain why the following proposition can't be proven:
[[
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}} (X ::= (ANum 3); Y ::= a)
{{fun st => asnat (st Y) = n}}.
]]
*)
(** 次の命題が証明できない理由を説明しなさい:
[[
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}} (X ::= (ANum 3); Y ::= a)
{{fun st => asnat (st Y) = n}}.
]]
*)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(* *** Conditionals *)
(** *** 条件分岐 *)
(* What sort of rule do we want for reasoning about conditional
commands? Certainly, if the same assertion [Q] holds after
executing either branch, then it holds after the whole
conditional. So we might be tempted to write:
[[[
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
]]]
However, this is rather weak. For example, using this rule,
we cannot show that:
[[
{{True}}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
]]
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches.
But, actually, we can say something more precise. In the "then"
branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the lemma
gives us more information to work with when reasoning about the
behavior of [c1] and [c2] (i.e., the reasons why they establish the
postcondtion [Q]).
[[[
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
]]]
*)
(** 条件分岐コマンドについて推論するために、どのような規則が必要でしょうか？
確かに、分岐のどちらの枝を実行した後でも表明[Q]が成立するならば、
条件分岐全体でも[Q]が成立するでしょう。
これから次のように書くべきかもしれません:
[[
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
]]
しかし、これはかなり弱いのです。例えば、この規則を使っても次のことを示すことができません:
[[
{{True}}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
]]
なぜなら、この規則では、"then"部と"else"部のどちらの代入が起こる状態なのかについて、
何も言っていないからです。
しかし、実際には、より詳しいことを言うことができます。
"then"の枝では、ブール式[b]の評価結果が[true]になることがわかっています。
また"else"の枝では、それが[false]になることがわかっています。
この情報を補題の前提部分で利用できるようにすることで、
[c1]と[c2]の振舞いについて(つまり事後条件[Q]が成立する理由について)推論するときに、
より多くの情報を使うことができるようになります。
[[
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
]]
*)
(* To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression, which
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
(** この規則を形式的に解釈するために、もう少しやることがあります。
厳密には、上述の表明において、表明とブール式の連言[P /\ b]は、型チェックを通りません。
これを修正するために、ブール式[b]を形式的に「持ち上げ」て、表明にしなければなりません。
このために[bassn b]と書きます。
これは"ブール式[b]の評価結果が(任意の状態で)[true]になる"という表明です。*)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(* A couple of useful facts about [bassn]: *)
(** [bassn]についての2つの便利な事実です: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(* Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
(** いよいよ条件分岐についてのホーア証明規則を形式化し、正しいことを証明できます。*)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
Case "b is true".
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
Case "b is false".
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(* Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
(** 以下が、最初に挙げたプログラムが与えられた条件を満たすことの証明です。*)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => asnat (st X) <= asnat (st Y)}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update. simpl. intros.
inversion H.
symmetry in H1; apply beq_nat_eq in H1.
rewrite H1. omega.
Case "Else".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, update; simpl; intros. omega.
Qed.
(* ####################################################### *)
(* *** Loops *)
(** *** ループ *)
(* Finally, we need a rule for reasoning about while loops. Suppose
we have a loop
[[
WHILE b DO c END
]]
and we want to find a pre-condition [P] and a post-condition
[Q] such that
[[
{{P}} WHILE b DO c END {{Q}}
]]
is a valid triple.
First of all, let's think about the case where [b] is false
at the beginning, so that the loop body never executes at
all. In this case, the loop behaves like [SKIP], so we might
be tempted to write
[[
{{P}} WHILE b DO c END {{P}}.
]]
But, as we remarked above for the conditional, we know a
little more at the end -- not just [P], but also the fact
that [b] is false in the current state. So we can enrich the
postcondition a little:
[[
{{P}} WHILE b DO c END {{P /\ ~b}}
]]
What about the case where the loop body _does_ get executed?
In order to ensure that [P] holds when the loop finally
exits, we certainly need to make sure that the command [c]
guarantees that [P] holds whenever [c] is finished.
Moreover, since [P] holds at the beginning of the first
execution of [c], and since each execution of [c]
re-establishes [P] when it finishes, we can always assume
that [P] holds at the beginning of [c]. This leads us to the
following rule:
[[[
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
]]]
The proposition [P] is called an _invariant_.
This is almost the rule we want, but again it can be improved
a little: at the beginning of the loop body, we know not only
that [P] holds, but also that the guard [b] is true in the
current state. This gives us a little more information to
use in reasoning about [c]. Here is the final version of the
rule:
[[[
{{P /\ b}} c {{P}}
----------------------------------- [hoare_while]
{{P}} WHILE b DO c END {{P /\ ~b}}
]]]
*)
(** 最後に、ループについての推論規則が必要です。
次のループを考えます:
[[
WHILE b DO c END
]]
そして、次の三つ組が正しくなる事前条件[P]と事後条件[Q]を探します:
[[
{{P}} WHILE b DO c END {{Q}}
]]
まず、[b]が最初から偽であるときを考えましょう。
このときループの本体はまったく実行されません。
この場合は、ループは[SKIP]と同様の振舞いをしますので、
次のように書いても良いかもしれません。
[[
{{P}} WHILE b DO c END {{P}}.
]]
しかし、条件分岐について議論したのと同様に、最後でわかっていることはもう少し多いのです。
最終状態では[P]であるだけではなく[b]が偽になっているのです。
そこで、事後条件にちょっと付け足すことができます:
[[
{{P}} WHILE b DO c END {{P /\ ~b}}
]]
それでは、ループの本体が実行されるときはどうなるでしょう？
ループを最後に抜けるときには[P]が成立することを確実にするために、
コマンド[c]の終了時点で常に[P]が成立することを確認する必要があるのは確かでしょう。
さらに、[P]が[c]の最初の実行の前に成立しており、[c]を実行するたびに、
終了時点で[P]の成立が再度確立されることから、
[P]が[c]の実行前に常に成立していると仮定することができます。
このことから次の規則が得られます:
[[
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
]]
命題[P]は不変条件(_invariant_)と呼ばれます。
これで求める規則にかなり近付いたのですが、もうちょっとだけ改良できます。
ループ本体の開始時点で、[P]が成立しているだけでなく、
ガード[b]が現在の状態で真であるということも言えます。
このことは、[c]についての推論の際にいくらかの情報を与えてくれます。
結局、規則の最終バージョンはこうなります:
[[
{{P /\ b}} c {{P}}
----------------------------------- [hoare_while]
{{P}} WHILE b DO c END {{P /\ ~b}}
]]
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Like we've seen before, we need to reason by induction
on He, because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just c *)
(* 先に見たように、Heについての帰納法を使う必要がある。
なぜなら、ループを抜けない場合には、
仮定は[c]だけでなくループ全体について言及しているからである。*)
remember (WHILE b DO c END) as wcom.
ceval_cases (induction He) Case; try (inversion Heqwcom); subst.
Case "E_WhileEnd".
split. assumption. apply bexp_eval_false. assumption.
Case "E_WhileLoop".
apply IHHe2. reflexivity.
apply (Hhoare st st'); try assumption.
split. assumption. apply bexp_eval_true. assumption. Qed.
Example while_example :
{{fun st => asnat (st X) <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => asnat (st X) = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub. intros. rewrite update_eq. simpl.
inversion H as [_ H0]. simpl in H0. apply ble_nat_true in H0.
omega.
unfold bassn. intros. inversion H as [Hle Hb]. simpl in Hb.
remember (ble_nat (asnat (st X)) 2) as le. destruct le.
apply ex_falso_quodlibet. apply Hb; reflexivity.
symmetry in Heqle. apply ble_nat_false in Heqle. omega.
Qed.
(* We can also use the while rule to prove the following Hoare
triple, which may seem surprising at first... *)
(** while規則を使うと、次のホーアの三つ組も証明できます。
これは最初は驚くでしょう...*)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
apply hoare_post_true. intros st. apply I.
Case "Loop invariant and negated guard imply postcondition".
simpl. intros st [Hinv Hguard].
apply ex_falso_quodlibet. apply Hguard. reflexivity.
Case "Precondition implies invariant".
intros st H. constructor. Qed.
(* Actually, this result shouldn't be surprising. If we look back at
the definition of [hoare_triple], we can see that it asserts
something meaningful _only_ when the command terminates. *)
(** 実際は、この結果は驚くことはないのです。
ふり返って[hoare_triple]の定義を見てみると、
コマンドが停止した場合「のみ」に意味がある表明をしているのです。*)
Print hoare_triple.
(* If the command doesn't terminate, we can prove anything we like
about the post-condition. Here's a more direct proof of the same
fact: *)
(** もしコマンドが停止しなければ、事後条件で何でも好きなことが証明できます。
以下は、同じことのより直接的な証明です: *)
Theorem always_loop_hoare' : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
unfold hoare_triple. intros P Q st st' contra.
apply loop_never_stops in contra. inversion contra.
Qed.
(* Hoare rules that only talk about terminating commands are often
said to describe a logic of "partial" correctness. It is also
possible to give Hoare rules for "total" correctness, which build
in the fact that the commands terminate. *)
(** 停止するコマンドについてだけを議論するホーア規則は、「部分」正当性("partial" correctness)
を記述していると言われます。
「完全」正当性("total" correctness)についてのホーア規則を与えることも可能です。
それは、コマンドが停止するという事実を組み込んだものです。*)
(* ####################################################### *)
(* *** Exercise: Hoare Rules for [REPEAT] *)
(** *** 練習問題: [REPEAT]のホーア規則 *)
Module RepeatExercise.
(* **** Exercise: 4 stars (hoare_repeat) *)
(** **** 練習問題: ★★★★ (hoare_repeat) *)
(* In this exercise, we'll add a new constructor to our language of
commands: [CRepeat]. You will write the evaluation rule for
[repeat] and add a new hoare logic theorem to the language for
programs involving it.
We recommend that you do this exercise before the ones that
follow, as it should help solidify your understanding of the
material. *)
(** この練習問題では、コマンド言語に新たなコンストラクタ[CRepeat]を追加します。
[repeat]の評価規則を記述し、
このコマンドを含むプログラムについての新たなホーア論理の定理を、言語に追加しなさい。
以降の問題に進む前にこの練習問題をやっておくことをお勧めします。
この問題は、素材の理解を確固としたものにする助けになるからです。*)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(* [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
(** [REPEAT]は[WHILE]と同じように振舞います。ただし、
ループのガードが本体の実行の「後で」評価され、
それが「偽」である間はループがくりかえされるという点が違います。
このことにより、本体は常に少なくとも1回は実行されることになります。*)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(* Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [WHILE] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. Then update the [ceval_cases] tactic to
handle these added cases. *)
(** 以下の[ceval]に[REPEAT]の新たな規則を追加しなさい。
[WHILE]の規則を参考にして構いません。ただ、
[REPEAT]の本体は1度は実行されることと、
ループの終了はガードが真になったときであることは忘れないで下さい。
そして、この場合を扱えるように、[ceval_cases]タクティックを更新しなさい。*)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n V,
aeval st a1 = n ->
ceval st (V ::= a1) (update st V n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
(* FILL IN HERE *)
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(* A couple of definitions from above, copied here so they use the
new [ceval]. *)
(** 上記から2つの定義のコピーし、新しい[ceval]を使うようにしました。*)
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st || st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q) (at level 90, c at next level).
(* Now state and prove a theorem, [hoare_repeat], that expresses an
appropriate proof rule for [repeat] commands. Use [hoare_while]
as a model. *)
(** [repeat]コマンドの適切な証明規則を表現する定理[hoare_repeat]を述べ、証明しなさい。
このときに[hoare_while]をモデルとして利用しなさい。*)
(* FILL IN HERE *)
End RepeatExercise.
(** [] *)
(* ####################################################### *)
(* ** Decorated Programs *)
(** ** 修飾付きプログラム *)
(* The whole point of Hoare Logic is that it is compositional -- the
structure of proofs exactly follows the structure of programs.
This fact suggests that we we could record the essential ideas of
a proof informally (leaving out some low-level calculational
details) by decorating programs with appropriate assertions around
each statement. Such a _decorated program_ carries with it
an (informal) proof of its own correctness.
For example, here is a complete decorated program:
[[
{{ True }} =>
{{ x = x }}
X ::= x;
{{ X = x }} =>
{{ X = x /\ z = z }}
Z ::= z;
{{ X = x /\ Z = z }} =>
{{ Z - X = z - x }}
WHILE X <> 0 DO
{{ Z - X = z - x /\ X <> 0 }} =>
{{ (Z - 1) - (X - 1) = z - x }}
Z ::= Z - 1;
{{ Z - (X - 1) = z - x }}
X ::= X - 1
{{ Z - X = z - x }}
END;
{{ Z - X = z - x /\ ~ (X <> 0) }} =>
{{ Z = z - x }} =>
{{ Z + 1 = z - x + 1 }}
Z ::= Z + 1
{{ Z = z - x + 1 }}
]]
*)
(** ホーア論理の一番のポイントは、合成的ということです。証明の構造は常にプログラムの構造に従います。
このことから、それぞれの文の周辺を適切な表明で修飾することで
(低レベルの計算の詳細を省いた)証明の本質的アイデアを非形式的に記録できるのではないか、
と考えられます。そういった修飾付きプログラム(_decorated program_)は、
自身の正しさの(非形式的)証明を伴っています。
例えば、次は完全な修飾付きプログラムです:
[[
{{ True }} =>
{{ x = x }}
X ::= x;
{{ X = x }} =>
{{ X = x /\ z = z }}
Z ::= z;
{{ X = x /\ Z = z }} =>
{{ Z - X = z - x }}
WHILE X <> 0 DO
{{ Z - X = z - x /\ X <> 0 }} =>
{{ (Z - 1) - (X - 1) = z - x }}
Z ::= Z - 1;
{{ Z - (X - 1) = z - x }}
X ::= X - 1
{{ Z - X = z - x }}
END;
{{ Z - X = z - x /\ ~ (X <> 0) }} =>
{{ Z = z - x }} =>
{{ Z + 1 = z - x + 1 }}
Z ::= Z + 1
{{ Z = z - x + 1 }}
]]
*)
(* Concretely, a decorated program consists of the program text
interleaved with assertions. To check that a decorated program
represents a valid proof, we check that each individual command is
_locally_ consistent with its accompanying assertions in the
following sense:
- [SKIP] is locally consistent if its precondition and
postcondition are the same
[[
{{ P }}
SKIP
{{ P }}
]]
- The sequential composition of commands [c1] and [c2] is locally
consistent (with respect to assertions [P] and [R]) if [c1]
is (with respect to [P] and [Q]) and [c2] is (with respect to
[Q] and [R]):
[[
{{ P }}
c1;
{{ Q }}
c2
{{ R }}
]]
- An assignment is locally consistent if its precondition is
the appropriate substitution of its postcondition:
[[
{{ P where a is substituted for X }}
X ::= a
{{ P }}
]]
- A conditional is locally consistent (with respect to assertions
[P] and [Q]) if the assertions at the top of its "then" and
"else" branches are exactly [P/\b] and [P/\~b] and if its "then"
branch is locally consistent (with respect to [P/\b] and [Q])
and its "else" branch is locally consistent (with respect to
[P/\~b] and [Q]):
[[
{{ P }}
IFB b THEN
{{ P /\ b }}
c1
{{ Q }}
ELSE
{{ P /\ ~b }}
c2
{{ Q }}
FI
]]
- A while loop is locally consistent if its postcondition is
[P/\~b] (where [P] is its precondition) and if the pre- and
postconditions of its body are exactly [P/\b] and [P]:
[[
{{ P }}
WHILE b DO
{{ P /\ b }}
c1
{{ P }}
END
{{ P /\ ~b }}
]]
- A pair of assertions separated by [=>] is locally consistent if
the first implies the second (in all states):
[[
{{ P }} =>
{{ P' }}
]]
*)
(** 具体的には、修飾付きプログラムはプログラムテキストと表明が交互に記述されたものです。
修飾付きプログラムが正しい証明を表現していることをチェックするには、
個々のコマンドが前後の表明と整合していることを「ローカルに」チェックします。
このローカルな整合性チェックは次のようになります:
- [SKIP]は事前条件と事後条件が同じときに、整合しています。
[[
{{ P }}
SKIP
{{ P }}
]]
- [c1]と[c2]のコマンド合成が(表明[P]と[R]に関して)ローカルに整合的であるとは、
[c1]が([P]と[Q]に関して)整合的であり、[c2]が([Q]と[R]に関して)整合的であることです:
[[
{{ P }}
c1;
{{ Q }}
c2
{{ R }}
]]
- 代入がローカルに整合的であるとは、事後条件を適切に置換したものが事前条件であることです:
[[
{{ P where a is substituted for X }}
X ::= a
{{ P }}
]]
- 条件分岐が(表明[P]と[Q]に関して)ローカルに整合的であるとは、
"then"と"else"の枝の最初の表明がそれぞれ[P/\b]と[P/\~b]であり、
"then"枝が([P/\b]と[Q]に関して)ローカルに整合的で、
"else"枝が([P/\~b]と[Q]に関して)ローカルに整合的であることです:
[[
{{ P }}
IFB b THEN
{{ P /\ b }}
c1
{{ Q }}
ELSE
{{ P /\ ~b }}
c2
{{ Q }}
FI
]]
- While ループがローカルに整合的であるとは、(事前条件を[P]とするとき)
事後条件が[P/\~b]であって、
ループ本体の事前条件と事後条件がそれぞれ[P/\b]と[P]であることです:
[[
{{ P }}
WHILE b DO
{{ P /\ b }}
c1
{{ P }}
END
{{ P /\ ~b }}
]]
- [=>]の前後に1つずつの表明が並べられたものがローカルに整合的であるとは、
[=>]の前の表明が成立するならば[=>]の後の表明が成立するということが(すべての状態で)
言えることです:
[[
{{ P }} =>
{{ P' }}
]]
*)
(* ####################################################### *)
(* * Reasoning About Programs with Hoare Logic *)
(** * ホーア論理によるプログラムについての推論 *)
(* ####################################################### *)
(* ** Example: Slow Subtraction *)
(** ** 例: 遅い引き算 *)
(* Informally:
[[
{{ X = x /\ Z = z }} =>
{{ Z - X = z - x }}
WHILE X <> 0 DO
{{ Z - X = z - x /\ X <> 0 }} =>
{{ (Z - 1) - (X - 1) = z - x }}
Z ::= Z - 1;
{{ Z - (X - 1) = z - x }}
X ::= X - 1
{{ Z - X = z - x }}
END
{{ Z - X = z - x /\ ~ (X <> 0) }} =>
{{ Z = z - x }}
]]
*)
(** 非形式的には:
[[
{{ X = x /\ Z = z }} =>
{{ Z - X = z - x }}
WHILE X <> 0 DO
{{ Z - X = z - x /\ X <> 0 }} =>
{{ (Z - 1) - (X - 1) = z - x }}
Z ::= Z - 1;
{{ Z - (X - 1) = z - x }}
X ::= X - 1
{{ Z - X = z - x }}
END
{{ Z - X = z - x /\ ~ (X <> 0) }} =>
{{ Z = z - x }}
]]
*)
(* Formally: *)
(** 形式的には: *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
Z ::= AMinus (AId Z) (ANum 1);
X ::= AMinus (AId X) (ANum 1)
END.
Definition subtract_slowly_invariant x z :=
fun st => minus (asnat (st Z)) (asnat (st X)) = minus z x.
Theorem subtract_slowly_correct : forall x z,
{{fun st => asnat (st X) = x /\ asnat (st Z) = z}}
subtract_slowly
{{fun st => asnat (st Z) = minus z x}}.
Proof.
(* Note that we do NOT unfold the definition of hoare_triple
anywhere in this proof! The goal is to use only the hoare
rules. Your proofs should do the same. *)
(* 証明内でhoare_tripleの定義のunfoldは使っていないことに注意してください!
ホーア規則だけを使うことが目的です。
読者の証明も同様にしてください。*)
intros x z. unfold subtract_slowly.
(* First we need to transform the pre and postconditions so
that hoare_while will apply. In particular, the
precondition should be the loop invariant. *)
(* 最初に、事前条件、事後条件を変換して、
hoare_while に合うようにしなければなりません。
特に、事前条件はループ不変条件にしなければなりません。 *)
eapply hoare_consequence with (P' := subtract_slowly_invariant x z).
apply hoare_while.
Case "Loop body preserves invariant".
(* Split up the two assignments with hoare_seq - using eapply
lets us solve the second one immediately with hoare_asgn *)
(* 2つの代入をhoare_seqで分離します。
そしてすぐに、hoare_asgnのeapplyで2つ目の代入を解決します。*)
eapply hoare_seq. apply hoare_asgn.
(* Now for the first assignment, transform the precondition
so we can use hoare_asgn *)
(* 続いて最初の代入にとりかかります。
hoare_asgnを使うため、事前条件を変換します。*)
eapply hoare_consequence_pre. apply hoare_asgn.
(* Finally, we need to justify the implication generated by
hoare_consequence_pre (this bit of reasoning is elided in the
informal proof) *)
(* 最後に、hoare_consequence_preで生成された含意の正しさを確認しなければいけません。
(この部分のちょっとした推論は、非形式的証明では省かれています。) *)
unfold subtract_slowly_invariant, assn_sub, update, bassn. simpl.
intros st [Inv GuardTrue].
(* There are several ways to do the case analysis here...this
one is fairly general: *)
(* 場合分け分析を行う方法はいろいろありますが、この方法はかなり一般的です: *)
remember (beq_nat (asnat (st X)) 0) as Q; destruct Q.
inversion GuardTrue.
symmetry in HeqQ. apply beq_nat_false in HeqQ.
omega. (* slow but effective! *)(* 遅いですが、効果的です! *)
Case "Initial state satisfies invariant".
(* This is the subgoal generated by the precondition part of our
first use of hoare_consequence. It's the first implication
written in the decorated program (though we elided the actual
proof there). *)
(* 次は、hoare_consequence の初めての使用の事前条件部分から作られたサブゴールです。
修飾付きプログラムで記述された最初の含意です。
(ただ、ここでは実際の証明は省略します。) *)
unfold subtract_slowly_invariant.
intros st [HX HZ]. omega.
Case "Invariant and negated guard imply postcondition".
(* This is the subgoal generated by the postcondition part of
out first use of hoare_consequence. This implication is
the one written after the while loop in the informal proof. *)
(* 次は、hoare_consequence の初めての使用の事前条件部分から生成されたサブゴールです。
非形式証明で while ループの後に記述された含意にあたるものです。*)
intros st [Inv GuardFalse].
unfold subtract_slowly_invariant in Inv.
unfold bassn in GuardFalse. simpl in GuardFalse.
(* Here's a slightly different alternative for the case analysis that
works out well here (but is less general)... *)
(* 場合分け分析のちょっと違うバージョンです。ここではこれがうまくはたらきます
(ただし、一般性は下がっています)... *)
destruct (asnat (st X)).
omega.
apply ex_falso_quodlibet. apply GuardFalse. reflexivity.
Qed.
(* ####################################################### *)
(* ** Exercise: Reduce to Zero *)
(** ** 練習問題: ゼロへの簡約 *)
(* Here is a while loop that is so simple it needs no invariant:
[[
{{ True }}
WHILE X <> 0 DO
{{ True /\ X <> 0 }} =>
{{ True }}
X ::= X - 1
{{ True }}
END
{{ True /\ X = 0 }} =>
{{ X = 0 }}
]]
Your job is to translate this proof to Coq. It may help to look
at the [slow_subtraction] proof for ideas.
*)
(** 次の while ループは、非常にシンプルなため、不変条件が必要ありません:
[[
{{ True }}
WHILE X <> 0 DO
{{ True /\ X <> 0 }} =>
{{ True }}
X ::= X - 1
{{ True }}
END
{{ True /\ X = 0 }} =>
{{ X = 0 }}
]]
この証明を Coq に変換しなさい。[slow_subtraction]の証明がアイデアの参考になるでしょう。
*)
(* **** Exercise: 2 stars (reduce_to_zero_correct) *)
(** **** 練習問題: ★★ (reduce_to_zero_correct) *)
Definition reduce_to_zero : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= AMinus (AId X) (ANum 1)
END.
Theorem reduce_to_zero_correct :
{{fun st => True}}
reduce_to_zero
{{fun st => asnat (st X) = 0}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(* ** Exercise: Slow Addition *)
(** ** 練習問題: 遅い足し算 *)
(* The following program adds the variable X into the variable Z
by repeatedly decrementing X and incrementing Z. *)
(** 次のプログラムは変数Xを変数Zに足します。
そのために、Xを減らしてZを増やすということを繰り返します。*)
Definition add_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
Z ::= APlus (AId Z) (ANum 1);
X ::= AMinus (AId X) (ANum 1)
END.
(* **** Exercise: 3 stars (add_slowly_decoration) *)
(** **** 練習問題: ★★★ (add_slowly_decoration) *)
(* Following the pattern of the [subtract_slowly] example above, pick
a precondition and postcondition that give an appropriate
specification of [add_slowly]; then (informally) decorate the
program accordingly. *)
(** 上記の例[subtract_slowly]のパターンに従って、
[add_slowly]の適切な事前条件と事後条件を与えなさい。
次に(非形式的に)そのプログラムを前例にならって修飾しなさい。*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 3 stars (add_slowly_formal) *)
(** **** 練習問題: ★★★ (add_slowly_formal) *)
(* Now write down your specification of [add_slowly] formally, as a
Coq [Hoare_triple], and prove it valid. *)
(** Coq の [Hoare_triple]のように、[add_slowly]の仕様を形式的に記述しなさい。
そして正しさを証明しなさい。*)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(* ** Example: Parity *)
(** ** 例: パリティ *)
(* Here's another, slightly trickier example. Make sure you
understand the decorated program completely. Understanding
all the details of the Coq proof is not required, though it
is not actually very hard -- all the required ideas are
already in the informal version. *)
(** 次は、よりトリッキーな例です。
修飾付きプログラムを完全に理解していることを確認してください。
Coqの証明の詳細のすべてを理解することが必要なわけではありません
(それは、それほど大変ではないですが)。
すべての必要なアイデアは非形式的なバージョンの中に含まれています。*)
(* 訳注： 次はもとのまま *)
(**
[[
{{ X = x }} =>
{{ X = x /\ 0 = 0 }}
Y ::= 0;
{{ X = x /\ Y = 0 }} =>
{{ (Y=0 <-> ev (x-X)) /\ X<=x }}
WHILE X <> 0 DO
{{ (Y=0 <-> ev (x-X)) /\ X<=x /\ X<>0 }} =>
{{ (1-Y)=0 <-> ev (x-(X-1)) /\ X-1<=x }}
Y ::= 1 - Y;
{{ Y=0 <-> ev (x-(X-1)) /\ X-1<=x }}
X ::= X - 1
{{ Y=0 <-> ev (x-X) /\ X<=x }}
END
{{ (Y=0 <-> ev (x-X)) /\ X<=x /\ ~(X<>0) }} =>
{{ Y=0 <-> ev x }}
]]
*)
Definition find_parity : com :=
Y ::= (ANum 0);
WHILE (BNot (BEq (AId X) (ANum 0))) DO
Y ::= AMinus (ANum 1) (AId Y);
X ::= AMinus (AId X) (ANum 1)
END.
Definition find_parity_invariant x :=
fun st =>
asnat (st X) <= x
/\ (asnat (st Y) = 0 /\ ev (x - asnat (st X)) \/ asnat (st Y) = 1 /\ ~ev (x - asnat (st X))).
(* It turns out that we'll need the following lemma... *)
(* 次の補題が必要になることがわかった... *)
Lemma not_ev_ev_S_gen: forall n,
(~ ev n -> ev (S n)) /\
(~ ev (S n) -> ev (S (S n))).
Proof.
induction n as [| n'].
Case "n = 0".
split; intros H.
SCase "->".
apply ex_falso_quodlibet. apply H. apply ev_0.
SCase "<-".
apply ev_SS. apply ev_0.
Case "n = S n'".
inversion IHn' as [Hn HSn]. split; intros H.
SCase "->".
apply HSn. apply H.
SCase "<-".
apply ev_SS. apply Hn. intros contra.
apply H. apply ev_SS. apply contra. Qed.
Lemma not_ev_ev_S : forall n,
~ ev n -> ev (S n).
Proof.
intros n.
destruct (not_ev_ev_S_gen n) as [H _].
apply H.
Qed.
Theorem find_parity_correct : forall x,
{{fun st => asnat (st X) = x}}
find_parity
{{fun st => asnat (st Y) = 0 <-> ev x}}.
Proof.
intros x. unfold find_parity.
apply hoare_seq with (Q := find_parity_invariant x).
eapply hoare_consequence.
apply hoare_while with (P := find_parity_invariant x).
Case "Loop body preserves invariant".
eapply hoare_seq.
apply hoare_asgn.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st [[Inv1 Inv2] GuardTrue].
unfold find_parity_invariant, bassn, assn_sub, aeval in *.
rewrite update_eq.
rewrite (update_neq Y X); auto.
rewrite (update_neq X Y); auto.
rewrite update_eq.
simpl in GuardTrue. destruct (asnat (st X)).
inversion GuardTrue. simpl.
split. omega.
inversion Inv2 as [[H1 H2] | [H1 H2]]; rewrite H1;
[right|left]; (split; simpl; [omega |]).
apply ev_not_ev_S in H2.
replace (S (x - S n)) with (x-n) in H2 by omega.
rewrite <- minus_n_O. assumption.
apply not_ev_ev_S in H2.
replace (S (x - S n)) with (x - n) in H2 by omega.
rewrite <- minus_n_O. assumption.
Case "Precondition implies invariant".
intros st H. assumption.
Case "Invariant implies postcondition".
unfold bassn, find_parity_invariant. simpl.
intros st [[Inv1 Inv2] GuardFalse].
destruct (asnat (st X)).
split; intro.
inversion Inv2.
inversion H0 as [_ H1]. replace (x-0) with x in H1 by omega.
assumption.
inversion H0 as [H0' _]. rewrite H in H0'. inversion H0'.
inversion Inv2.
inversion H0. assumption.
inversion H0 as [_ H1]. replace (x-0) with x in H1 by omega.
apply ex_falso_quodlibet. apply H1. assumption.
apply ex_falso_quodlibet. apply GuardFalse. reflexivity.
Case "invariant established before loop".
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H.
unfold assn_sub, find_parity_invariant, update. simpl.
subst.
split.
omega.
replace (asnat (st X) - asnat (st X)) with 0 by omega.
left. split. reflexivity.
apply ev_0. Qed.
(* **** Exercise: 3 stars (wrong_find_parity_invariant) *)
(** **** 練習問題: ★★★ (wrong_find_parity_invariant) *)
(* A plausible first attempt at stating an invariant for [find_parity]
is the following. *)
(** [find_parity]の不変条件の主張として次のものはもっともらしく見えます。*)
Definition find_parity_invariant' x :=
fun st =>
(asnat (st Y)) = 0 <-> ev (x - asnat (st X)).
(* Why doesn't this work? (Hint: Don't waste time trying to answer
this exercise by attempting a formal proof and seeing where it
goes wrong. Just think about whether the loop body actually
preserves the property.) *)
(** これがなぜうまくはたらかないかを説明しなさい。
(ヒント: 形式的証明を考え、その問題を探そうとするのは時間の無駄です。
ループの本体が実際に性質を保存するかどうかだけを考えなさい。) *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(* ** Example: Finding Square Roots *)
(** ** 例: 平方根の探索 *)
Definition sqrt_loop : com :=
WHILE BLe (AMult (APlus (ANum 1) (AId Z))
(APlus (ANum 1) (AId Z)))
(AId X) DO
Z ::= APlus (ANum 1) (AId Z)
END.
Definition sqrt_com : com :=
Z ::= ANum 0;
sqrt_loop.
Definition sqrt_spec (x : nat) : Assertion :=
fun st =>
((asnat (st Z)) * (asnat (st Z))) <= x
/\ ~ (((S (asnat (st Z))) * (S (asnat (st Z)))) <= x).
Definition sqrt_inv (x : nat) : Assertion :=
fun st =>
asnat (st X) = x
/\ ((asnat (st Z)) * (asnat (st Z))) <= x.
Theorem random_fact_1 : forall st,
(S (asnat (st Z))) * (S (asnat (st Z))) <= asnat (st X) ->
bassn (BLe (AMult (APlus (ANum 1) (AId Z))
(APlus (ANum 1) (AId Z)))
(AId X)) st.
Proof.
intros st Hle. unfold bassn. simpl.
destruct (asnat (st X)) as [|x'].
Case "asnat (st X) = 0".
inversion Hle.
Case "asnat (st X) = S x'".
simpl in Hle. apply le_S_n in Hle.
remember (ble_nat (plus (asnat (st Z))
((asnat (st Z)) * (S (asnat (st Z))))) x')
as ble.
destruct ble. reflexivity.
symmetry in Heqble. apply ble_nat_false in Heqble.
unfold not in Heqble. apply Heqble in Hle. inversion Hle.
Qed.
Theorem random_fact_2 : forall st,
bassn (BLe (AMult (APlus (ANum 1) (AId Z))
(APlus (ANum 1) (AId Z)))
(AId X)) st ->
asnat (aeval st (APlus (ANum 1) (AId Z)))
* asnat (aeval st (APlus (ANum 1) (AId Z)))
<= asnat (st X).
Proof.
intros st Hble. unfold bassn in Hble. simpl in *.
destruct (asnat (st X)) as [| x'].
Case "asnat (st X) = 0".
inversion Hble.
Case "asnat (st X) = S x'".
apply ble_nat_true in Hble. omega. Qed.
Theorem sqrt_com_correct : forall x,
{{fun st => True}} (X ::= ANum x; sqrt_com) {{sqrt_spec x}}.
Proof.
intros x.
apply hoare_seq with (Q := fun st => asnat (st X) = x).
Case "sqrt_com".
unfold sqrt_com.
apply hoare_seq with (Q := fun st => asnat (st X) = x
/\ asnat (st Z) = 0).
SCase "sqrt_loop".
unfold sqrt_loop.
eapply hoare_consequence.
apply hoare_while with (P := sqrt_inv x).
SSCase "loop preserves invariant".
eapply hoare_consequence_pre.
apply hoare_asgn. intros st H.
unfold assn_sub. unfold sqrt_inv in *.
inversion H as [[HX HZ] HP]. split.
SSSCase "X is preserved".
rewrite update_neq; auto.
SSSCase "Z is updated correctly".
rewrite (update_eq (aeval st (APlus (ANum 1) (AId Z))) Z st).
subst. apply random_fact_2. assumption.
SSCase "invariant is true initially".
intros st H. inversion H as [HX HZ].
unfold sqrt_inv. split. assumption.
rewrite HZ. simpl. omega.
SSCase "after loop, spec is satisfied".
intros st H. unfold sqrt_spec.
inversion H as [HX HP].
unfold sqrt_inv in HX. inversion HX as [HX' Harith].
split. assumption.
intros contra. apply HP. clear HP.
simpl. simpl in contra.
apply random_fact_1. subst x. assumption.
SCase "Z set to 0".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st HX.
unfold assn_sub. split.
rewrite update_neq; auto.
rewrite update_eq; auto.
Case "assignment of X".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H.
unfold assn_sub. rewrite update_eq; auto. Qed.
(* **** Exercise: 3 stars, optional (sqrt_informal) *)
(** **** 練習問題: ★★★, optional (sqrt_informal) *)
(* Write a decorated program corresponding to the above
correctness proof. *)
(** 上記の正しさの証明に対応する修飾付きプログラムを記述しなさい。*)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(* ** Exercise: Factorial *)
(** ** 練習問題: 階乗 *)
Module Factorial.
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
(* Recall the factorial Imp program: *)
(** 階乗を計算する Imp プログラムを思い出してください: *)
Definition fact_body : com :=
Y ::= AMult (AId Y) (AId Z);
Z ::= AMinus (AId Z) (ANum 1).
Definition fact_loop : com :=
WHILE BNot (BEq (AId Z) (ANum 0)) DO
fact_body
END.
Definition fact_com : com :=
Z ::= (AId X);
Y ::= ANum 1;
fact_loop.
(* **** Exercise: 3 stars, optional (fact_informal) *)
(** **** 練習問題: ★★★, optional (fact_informal) *)
(* Decorate the [fact_com] program to show that it satisfies the
specification given by the pre and postconditions below. Just as
we have done above, you may elide the algebraic reasoning about
arithmetic, the less-than relation, etc., that is (formally)
required by the rule of consequence:
(* FILL IN HERE *)
[[
{{ X = x }}
Z ::= X;
Y ::= 1;
WHILE Z <> 0 DO
Y ::= Y * Z;
Z ::= Z - 1
END
{{ Y = real_fact x }}
]]
*)
(** [fact_com]を修飾して、以下の事前条件、事後条件として与えられる仕様を満たすことを示しなさい。
帰結規則のために(形式的には)算術式や不等号などについての推論が必要になりますが、
ここまでと同様、それらは省略して構いません。
(* FILL IN HERE *)
[[
{{ X = x }}
Z ::= X;
Y ::= 1;
WHILE Z <> 0 DO
Y ::= Y * Z;
Z ::= Z - 1
END
{{ Y = real_fact x }}
]]
*)
(** [] *)
(* **** Exercise: 4 stars, optional (fact_formal) *)
(** **** 練習問題: ★★★★, optional (fact_formal) *)
(* Prove formally that fact_com satisfies this specification,
using your informal proof as a guide. You may want to state
the loop invariant separately (as we did in the examples). *)
(** fact_com がこの仕様を満たすことを、形式的に証明しなさい。
その際、自分の非形式的な証明をガイドとして使いなさい。
(例で行ったように)ループ不変条件を分離して主張しても構いません。*)
Theorem fact_com_correct : forall x,
{{fun st => asnat (st X) = x}} fact_com
{{fun st => asnat (st Y) = real_fact x}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Factorial.
(* ####################################################### *)
(* ** Reasoning About Programs with Lists *)
(** ** リストを扱うプログラムについての推論 *)
(* **** Exercise: 3 stars (list_sum) *)
(** **** 練習問題: ★★★ (list_sum) *)
(* Here is a direct definition of the sum of the elements of a list,
and an Imp program that computes the sum. *)
(** 以下は、リストの要素の合計の直接的定義と、その合計を計算するImpプログラムです *)
Definition sum l := fold_right plus 0 l.
Definition sum_program :=
Y ::= ANum 0;
WHILE (BIsCons (AId X)) DO
Y ::= APlus (AId Y) (AHead (AId X)) ;
X ::= ATail (AId X)
END.
(* Provide an _informal_ proof of the following specification of
[sum_program] in the form of a decorated version of the
program. *)
(** [sum_program]の以下の仕様の「非形式的な」証明を、
修飾を付けたバージョンのプログラムの形で与えなさい。*)
Definition sum_program_spec := forall l,
{{ fun st => aslist (st X) = l }}
sum_program
{{ fun st => asnat (st Y) = sum l }}.
(* FILL IN HERE *)
(** [] **)
(* Next, let's look at a _formal_ Hoare Logic proof for a program
that deals with lists. We will verify the following program,
which checks if the number [Y] occurs in the list [X], and if so sets
[Z] to [1].
*)
(** 次に、リストを扱うあるプログラムの「形式的な」
ホーア論理の証明を見てみましょう。
次のプログラムは、数値[Y]がリスト[X]の中に含まれるかどうかをチェックし、
もし含まれたならば[Z]を[1]にします。
このプログラムを検証します。
*)
Definition list_member :=
WHILE BIsCons (AId X) DO
IFB (BEq (AId Y) (AHead (AId X))) THEN
Z ::= (ANum 1)
ELSE
SKIP
FI;
X ::= ATail (AId X)
END.
Definition list_member_spec := forall l n,
{{ fun st => st X = VList l /\ st Y = VNat n /\ st Z = VNat 0 }}
list_member
{{ fun st => st Z = VNat 1 <-> appears_in n l }}.
(* The proof we will use, written informally, looks as follows:
[[
{{ X = l /\ Y = n /\ Z = 0 }} =>
{{ Y = n /\ exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p) }}
WHILE (BIsCons X)
DO
{{ Y = n /\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p))
/\ (BIsCons X) }}
IFB (Y == head X) THEN
{{ Y = n
/\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p))
/\ (BIsCons X)
/\ Y == AHead X }} =>
{{ Y = n /\ (exists p, p ++ tail X = l
/\ (1 = 1 <-> appears_in n p)) }}
Z ::= 1
{{ Y = n /\ (exists p, p ++ tail X = l
/\ (Z = 1 <-> appears_in n p)) }}
ELSE
{{ Y = n
/\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p))
/\ (BIsCons X)
/\ ~ (Y == head X) }} =>
{{ Y = n
/\ (exists p, p ++ tail X = l /\ (Z = 1 <-> appears_in n p)) }}
SKIP
{{ Y = n
/\ (exists p, p ++ tail X = l /\ (Z = 1 <-> appears_in n p)) }}
FI;
X ::= ATail X
{{ Y = n
/\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p)) }}
END
{{ Y = n
/\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p))
/\ ~ (BIsCons X) }} =>
{{ Z = 1 <-> appears_in n l }}
]]
The only interesting part of the proof is the choice of loop invariant:
[[
exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p)
]]
This states that at each iteration of the loop, the original list
[l] is equal to the append of the current value of [X] and some
other list [p] which is not the value of any variable in the
program, but keeps track of enough information from the original
state to make the proof go through. (Such a [p] is sometimes called
a "ghost variable").
In order to show that such a list [p] exists, in each iteration we
add the head of [X] to the _end_ of [p]. This needs the function
[snoc], from Poly.v. *)
(** 証明は非形式的に書くと次のようになるものを使います:
[[
{{ X = l /\ Y = n /\ Z = 0 }} =>
{{ Y = n /\ exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p) }}
WHILE (BIsCons X)
DO
{{ Y = n /\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p))
/\ (BIsCons X) }}
IFB (Y == head X) THEN
{{ Y = n
/\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p))
/\ (BIsCons X)
/\ Y == AHead X }} =>
{{ Y = n /\ (exists p, p ++ tail X = l
/\ (1 = 1 <-> appears_in n p)) }}
Z ::= 1
{{ Y = n /\ (exists p, p ++ tail X = l
/\ (Z = 1 <-> appears_in n p)) }}
ELSE
{{ Y = n
/\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p))
/\ (BIsCons X)
/\ ~ (Y == head X) }} =>
{{ Y = n
/\ (exists p, p ++ tail X = l /\ (Z = 1 <-> appears_in n p)) }}
SKIP
{{ Y = n
/\ (exists p, p ++ tail X = l /\ (Z = 1 <-> appears_in n p)) }}
FI;
X ::= ATail X
{{ Y = n
/\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p)) }}
END
{{ Y = n
/\ (exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p))
/\ ~ (BIsCons X) }} =>
{{ Z = 1 <-> appears_in n l }}
]]
証明で興味深い点はただ1つ、ループ不変条件の選び方です:
[[
exists p, p ++ X = l /\ (Z = 1 <-> appears_in n p)
]]
これは、ループの繰り返しのたびに、
もとのリスト[l]が[X]の現在値と別のリスト[p]とを結合したものと同一であることを言っています。
この[p]はプログラム内の変数の値ではないですが、最初から証明が進んでいく間、保持されていきます。
(このような[p]は、よく"幽霊変数"(ghost variable)と呼ばれます。)
このようなリスト[p]が存在することを示すために、繰り返しの毎回、
[X]の先頭に[p]の「最後」を加えています。このために Poly_J.vの[snoc]を使っています。*)
Fixpoint snoc {X:Type} (l:list X) (v:X) : (list X) :=
match l with
| nil => [ v ]
| cons h t => h :: (snoc t v)
end.
Lemma snoc_equation : forall (A : Type) (h:A) (x y : list A),
snoc x h ++ y = x ++ h :: y.
Proof.
intros A h x y.
induction x.
Case "x = []". reflexivity.
Case "x = cons". simpl. rewrite IHx. reflexivity.
Qed.
(* The main proof uses various lemmas. *)
(** メインの証明はたくさんの補題を使います。 *)
Lemma appears_in_snoc1 : forall a l,
appears_in a (snoc l a).
Proof.
induction l.
Case "l = []". apply ai_here.
Case "l = cons". simpl. apply ai_later. apply IHl.
Qed.
Lemma appears_in_snoc2 : forall a b l,
appears_in a l ->
appears_in a (snoc l b).
Proof.
induction l; intros H; inversion H; subst; simpl.
Case "l = []". apply ai_here.
Case "l = cons". apply ai_later. apply IHl. assumption.
Qed.
Lemma appears_in_snoc3 : forall a b l,
appears_in a (snoc l b) ->
(appears_in a l \/ a = b).
Proof.
induction l; intros H.
Case "l = []". inversion H.
SCase "ai_here". right. reflexivity.
SCase "ai_later". left. assumption.
Case "l = cons". inversion H; subst.
SCase "ai_here". left. apply ai_here.
SCase "ai_later". destruct (IHl H1).
left. apply ai_later. assumption.
right. assumption.
Qed.
Lemma append_singleton_equation : forall (x : nat) l l',
(l ++ [x]) ++ l' = l ++ x :: l'.
Proof.
intros x l l'.
induction l.
reflexivity.
simpl. rewrite IHl. reflexivity.
Qed.
Lemma append_nil : forall (A : Type) (l : list A),
l ++ [] = l.
Proof.
induction l.
reflexivity.
simpl. rewrite IHl. reflexivity.
Qed.
Lemma beq_true__eq : forall n n',
beq_nat n n' = true ->
n = n'.
Proof.
induction n; destruct n'.
Case "n = 0, n' = 0". reflexivity.
Case "n = 0, n' = S _". simpl. intros H. inversion H.
Case "n = S, n' = 0". simpl. intros H. inversion H.
Case "n = S, n' = S". simpl. intros H.
rewrite (IHn n' H). reflexivity.
Qed.
Lemma beq_nat_refl : forall n,
beq_nat n n = true.
Proof.
induction n.
reflexivity.
simpl. assumption.
Qed.
Theorem list_member_correct : forall l n,
{{ fun st => st X = VList l /\ st Y = VNat n /\ st Z = VNat 0 }}
list_member
{{ fun st => st Z = VNat 1 <-> appears_in n l }}.
Proof.
intros l n.
eapply hoare_consequence.
apply hoare_while with (P := fun st =>
st Y = VNat n
/\ exists p, p ++ aslist (st X) = l
/\ (st Z = VNat 1 <-> appears_in n p)).
(* The loop body preserves the invariant: *)
eapply hoare_seq.
apply hoare_asgn.
apply hoare_if.
Case "If taken".
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st [[[H1 [p [H2 H3]]] H9] H10].
unfold assn_sub. split.
(* (st Y) is still n *)
rewrite update_neq; try reflexivity.
rewrite update_neq; try reflexivity.
assumption.
(* and the interesting part of the invariant is preserved: *)
(* X has to be a cons *)
remember (aslist (st X)) as x.
destruct x as [|h x'].
unfold bassn in H9. unfold beval in H9. unfold aeval in H9.
rewrite <- Heqx in H9. inversion H9.
exists (snoc p h).
rewrite update_eq.
unfold aeval. rewrite update_neq; try reflexivity.
rewrite <- Heqx.
split.
rewrite snoc_equation. assumption.
rewrite update_neq; try reflexivity.
rewrite update_eq.
split.
simpl.
unfold bassn in H10. unfold beval in H10.
unfold aeval in H10. rewrite H1 in H10.
rewrite <- Heqx in H10. simpl in H10.
rewrite (beq_true__eq _ _ H10).
intros. apply appears_in_snoc1.
intros. reflexivity.
Case "If not taken".
eapply hoare_consequence_pre. apply hoare_skip.
unfold assn_sub.
intros st [[[H1 [p [H2 H3]]] H9] H10].
split.
(* (st Y) is still n *)
rewrite update_neq; try reflexivity.
assumption.
(* and the interesting part of the invariant is preserved: *)
(* X has to be a cons *)
remember (aslist (st X)) as x.
destruct x as [|h x'].
unfold bassn in H9. unfold beval in H9. unfold aeval in H9.
rewrite <- Heqx in H9. inversion H9.
exists (snoc p h).
split.
rewrite update_eq.
unfold aeval. rewrite <- Heqx.
rewrite snoc_equation. assumption.
rewrite update_neq; try reflexivity.
split.
intros. apply appears_in_snoc2. apply H3. assumption.
intros. destruct (appears_in_snoc3 _ _ _ H).
SCase "later".
inversion H3 as [_ H3'].
apply H3'. assumption.
SCase "here (absurd)".
subst.
unfold bassn in H10. unfold beval in H10. unfold aeval in H10.
rewrite <- Heqx in H10. rewrite H1 in H10.
simpl in H10. rewrite beq_nat_refl in H10.
apply ex_falso_quodlibet. apply H10. reflexivity.
(* The invariant holds at the start of the loop: *)
intros st [H1 [H2 H3]].
rewrite H1. rewrite H2. rewrite H3.
split.
reflexivity.
exists []. split.
reflexivity.
split; intros H; inversion H.
(* At the end of the loop the invariant implies the right thing. *)
simpl. intros st [[H1 [p [H2 H3]]] H5].
(* x must be [] *)
unfold bassn in H5. unfold beval in H5. unfold aeval in H5.
destruct (aslist (st X)) as [|h x'].
rewrite append_nil in H2.
rewrite <- H2.
assumption.
apply ex_falso_quodlibet. apply H5. reflexivity.
Qed.
(* **** Exercise: 4 stars, optional (list_reverse) *)
(** **** 練習問題: ★★★★, optional (list_reverse) *)
(* Recall the function [rev] from Poly.v, for reversing lists. *)
(** Poly_J.vの[rev]を思い出してください。リストを逆順にするものです。*)
Fixpoint rev {X:Type} (l:list X) : list X :=
match l with
| nil => []
| cons h t => snoc (rev t) h
end.
(* Write an Imp program [list_reverse_program] that reverses
lists. Formally prove that it satisfies the following
specification:
[[
forall l : list nat,
{{ X = l /\ Y = nil }}
list_reverse_program
{{ Y = rev l }}.
]]
You may find the lemmas [append_nil] and [rev_equation] useful.
*)
(** リストを逆順にする Imp プログラム[list_reverse_program]を記述しなさい。
次の仕様を満たすことを形式的に証明しなさい:
[[
forall l : list nat,
{{ X = l /\ Y = nil }}
list_reverse_program
{{ Y = rev l }}.
]]
補題[append_nil]と[rev_equation]を使うのが良いでしょう。
*)
Lemma rev_equation : forall (A : Type) (h : A) (x y : list A),
rev (h :: x) ++ y = rev x ++ h :: y.
Proof.
intros. simpl. apply snoc_equation.
Qed.
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(* * Formalizing Decorated Programs *)
(** * 修飾付きプログラムの形式化 *)
(* The informal conventions for decorated programs amount to a way of
displaying Hoare triples in which commands are annotated with
enough embedded assertions that checking the validity of the
triple is reduced to simple algebraic calculations showing that
some assertions were stronger than others.
In this section, we show that this informal presentation style can
actually be made completely formal. *)
(** ホーアの三つ組を、非形式的な修飾付きプログラムで記述することは結局、
コマンドに十分な表明を付加することで、三つ組の正しさをチェックすることを、
ある表明が別のものより強いことを示す簡単な代数的計算に簡約化することになります。
この節では、この非形式的なスタイルを、実際は完全に形式的に表現できることを示します。*)
(* ** Syntax *)
(** ** 構文 *)
(* The first thing we need to do is to formalize a variant of the
syntax of commands that includes embedded assertions. We call the
new commands _decorated commands_, or [dcom]s. *)
(** 最初にしなければならないことは、表明を埋め込んだコマンド構文を形式化することです。
この形のコマンドを修飾付きコマンド(_decorated commands_)または[dcom]と呼びます。*)
Inductive dcom : Type :=
| DCSkip : Assertion -> dcom
| DCSeq : dcom -> dcom -> dcom
| DCAsgn : id -> aexp -> Assertion -> dcom
| DCIf : bexp -> Assertion -> dcom -> Assertion -> dcom -> dcom
| DCWhile : bexp -> Assertion -> dcom -> Assertion -> dcom
| DCPre : Assertion -> dcom -> dcom
| DCPost : dcom -> Assertion -> dcom.
Tactic Notation "dcom_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Skip" | Case_aux c "Seq" | Case_aux c "Asgn"
| Case_aux c "If" | Case_aux c "While"
| Case_aux c "Pre" | Case_aux c "Post" ].
Notation "'SKIP' {{ P }}"
:= (DCSkip P)
(at level 10) : dcom_scope.
Notation "l '::=' a {{ P }}"
:= (DCAsgn l a P)
(at level 60, a at next level) : dcom_scope.
Notation "'WHILE' b 'DO' {{ Pbody }} d 'END' {{ Ppost }}"
:= (DCWhile b Pbody d Ppost)
(at level 80, right associativity) : dcom_scope.
Notation "'IFB' b 'THEN' {{ P }} d 'ELSE' {{ P' }} d' 'FI'"
:= (DCIf b P d P' d')
(at level 80, right associativity) : dcom_scope.
Notation "'=>' {{ P }} d"
:= (DCPre P d)
(at level 90, right associativity) : dcom_scope.
Notation "{{ P }} d"
:= (DCPre P d)
(at level 90) : dcom_scope.
Notation "d '=>' {{ P }}"
:= (DCPost d P)
(at level 91, right associativity) : dcom_scope.
Notation " d ; d' "
:= (DCSeq d d')
(at level 80, right associativity) : dcom_scope.
Delimit Scope dcom_scope with dcom.
(* To avoid clashing with the existing [Notation] definitions
for ordinary [com]mands, we introduce these notations in a special
scope called [dcom_scope], and we wrap examples with the
declaration [% dcom] to signal that we want the notations to be
interpreted in this scope.
Careful readers will note that we've defined two notations for the
[DCPre] constructor, one with and one without a [=>]. The
"without" version is intended to be used to supply the initial
precondition at the very top of the program. *)
(** 既に定義されているコマンド[com]の記法[Notation]との衝突を避けるため、
[dcom_scope]という特別なスコープを導入します。
そして、例を宣言[% dcom]で包み、記法をこのスコープ内で解釈したいことを表します。
注意深い読者は、[DCPre]コンストラクタに対して2つの記法を定義していることに気付くでしょう。
[=>]を使うものと使わないものです。[=>]を使わないものは、
プログラムの一番最初の事前条件を与える意図で用意したものです。*)
Example dec_while : dcom := (
{{ fun st => True }}
WHILE (BNot (BEq (AId X) (ANum 0)))
DO
{{ fun st => ~(asnat (st X) = 0) }}
X ::= (AMinus (AId X) (ANum 1))
{{ fun _ => True }}
END
{{ fun st => asnat (st X) = 0 }}
) % dcom.
(* It is easy to go from a [dcom] to a [com] by erasing all
annotations. *)
(** [dcom]から[com]に変換するのは簡単です。アノテーションをすべて消せば良いのです。*)
Fixpoint extract (d:dcom) : com :=
match d with
| DCSkip _ => SKIP
| DCSeq d1 d2 => (extract d1 ; extract d2)
| DCAsgn V a _ => V ::= a
| DCIf b _ d1 _ d2 => IFB b THEN extract d1 ELSE extract d2 FI
| DCWhile b _ d _ => WHILE b DO extract d END
| DCPre _ d => extract d
| DCPost d _ => extract d
end.
(* The choice of exactly where to put assertions in the definition of
[dcom] is a bit subtle. The simplest thing to do would be to
annotate every [dcom] with a precondition and postcondition. But
this would result in very verbose programs with a lot of repeated
annotations: for example, a program like [SKIP;SKIP] would have to
be annotated as
[[
{{P}} ({{P}} SKIP {{P}}) ; ({{P}} SKIP {{P}}) {{P}},
]]
with pre- and post-conditions on each [SKIP], plus identical pre-
and post-conditions on the semicolon!
Instead, the rule we've followed is this:
- The _post_-condition expected by each [dcom] [d] is embedded in [d]
- The _pre_-condition is supplied by the context. *)
(** [dcom]の定義のどこに表明を置くかの選択は、ちょっと微妙です。
一番簡単な方法は、すべての[dcom]に事前条件と事後条件の表明を付けてしまうことかもしれません。
しかしそうすると、同じアノテーションが繰替えされて、とてもうるさいプログラムになってしまうでしょう。
例えば、[SKIP;SKIP]は次のように表明が付加されることになります。
[[
{{P}} ({{P}} SKIP {{P}}) ; ({{P}} SKIP {{P}}) {{P}},
]]
それぞれの[SKIP]の事前条件、事後条件と、さらにセミコロンの事前条件、
事後条件として同じものが付加されています!
この代わりに、次の規則に従うことにします:
- [dcom] [d]に対する事後条件は[d]に埋め込む
- 事前条件はコンテキストから与えられるようにする。 *)
(* In other words, the invariant of the representation is that a
[dcom] [d] together with a precondition [P] determines a Hoare
triple [{{P}} (extract d) {{post d}}], where [post] is defined as
follows: *)
(** 言い換えると、この表現での不変条件は、
[dcom] [d] と事前条件 [P] がホーアの三つ組[{{P}} (extract d) {{post d}}]
を決定するということです。ここで [post] は次のように定義されます: *)
Fixpoint post (d:dcom) : Assertion :=
match d with
| DCSkip P => P
| DCSeq d1 d2 => post d2
| DCAsgn V a Q => Q
| DCIf _ _ d1 _ d2 => post d1
| DCWhile b Pbody c Ppost => Ppost
| DCPre _ d => post d
| DCPost c Q => Q
end.
(* We can define a similar function that extracts the "initial
precondition" from a decorated program. *)
(** 修飾付きプログラムから「最初の事前条件」を抽出する同様の関数が定義できます。*)
Fixpoint pre (d:dcom) : Assertion :=
match d with
| DCSkip P => fun st => True
| DCSeq c1 c2 => pre c1
| DCAsgn V a Q => fun st => True
| DCIf _ _ t _ e => fun st => True
| DCWhile b Pbody c Ppost => fun st => True
| DCPre P c => P
| DCPost c Q => pre c
end.
(* This function is not doing anything sophisticated like calculating
a weakest precondition; it just recursively searches for an
explicit annotation at the very beginning of the program,
returning default answers for programs that lack an explicit
precondition (like a bare assignment or [SKIP]).
Using [pre] and [post], and assuming that we adopt the convention
of always supplying an explicit precondition annotation at the
very beginning of our decorated programs, we can express what it
means for a decorated program to be correct as follows: *)
(** この関数は、最弱事前条件を計算する、というような洗練されたことは何もしません。
単に、プログラムの一番最初から明示的に付加されたアノテーションを再帰的に探します。
もし(代入だけのものや[SKIP]のように)明示的事前条件を持たない場合には、
デフォルトの答えを返します。
[pre]と[post]を使い、
修飾付きプログラムの一番最初には常に明示的な事前条件のアノテーションを付ける慣習を守ることを仮定すると、
修飾付きプログラムが正しいとはどういうことかを以下のように表現できます: *)
Definition dec_correct (d:dcom) :=
{{pre d}} (extract d) {{post d}}.
(* To check whether this Hoare triple is _valid_, we need a way to
extract the "proof obligations" from a decorated program. These
obligations are often called _verification conditions_, because
they are the facts that must be verified (by some process looking
at the decorated program) to see that the decorations are
logically consistent and thus add up to a proof of correctness. *)
(** このホーアの三つ組が正しい(_valid_)かどうかをチェックするには、
修飾付きプログラムから「証明課題」("proof obligations")を抽出することが必要となります。
この課題は、しばしば検証条件(_verification conditions_)と呼ばれます。
なぜなら、修飾が論理的に整合していて、
全体として正しさの証明になることを確認するために
(修飾付きプログラムを調べるプロセスによって)検証されるべき事実だからです。*)
(* ** Extracting Verification Conditions *)
(** ** 検証条件の抽出 *)
(* First, a bit of notation: *)
(** 最初に、記法について少々: *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
(* We will write [P ~~> Q] (in ASCII, [P ~][~> Q]) for [assert_implies
P Q]. *)
(** [assert_implies P Q]を[P ~~> Q] (ASCIIでは, [P ~][~> Q])と書きます。*)
Notation "P ~~> Q" := (assert_implies P Q) (at level 80).
Notation "P <~~> Q" := (P ~~> Q /\ Q ~~> P) (at level 80).
(* Next, the key definition. The function [verification_conditions]
takes a [dcom] [d] together with a precondition [P] and returns a
_proposition_ that, if it can be proved, implies that the triple
[{{P}} (extract d) {{post d}}] is valid. It does this by walking
over [d] and generating a big conjunction including all the "local
checks" that we listed when we described the informal rules for
decorated programs. (Strictly speaking, we need to massage the
informal rules a little bit to add some uses of the rule of
consequence, but the correspondence should be clear.) *)
(** 次に、主要な定義です。
関数[verification_conditions]は[dcom] [d]と事前条件[P]をとり、
命題(_proposition_)を返します。
その命題は、もし証明できたならば、
三つ組[{{P}} (extract d) {{post d}}]が正しいことになります。
この関数はその命題を作るために、[d]を調べまわって、
すべてのローカルチェックの /\ (and)をとります。
ローカルチェックとは、
前に修飾付きプログラムについての非形式的規則のところでリストアップしたもののことです。
(厳密に言うと、帰結規則の使用法を拡げるために非形式的規則をちょっと揉んでやる必要があります。
ただ、対応関係は明確でしょう。) *)
Fixpoint verification_conditions (P : Assertion) (d:dcom) : Prop :=
match d with
| DCSkip Q =>
(P ~~> Q)
| DCSeq d1 d2 =>
verification_conditions P d1
/\ verification_conditions (post d1) d2
| DCAsgn V a Q =>
(P ~~> assn_sub V a Q)
| DCIf b P1 t P2 e =>
((fun st => P st /\ bassn b st) ~~> P1)
/\ ((fun st => P st /\ ~ (bassn b st)) ~~> P2)
/\ (post t = post e)
/\ verification_conditions P1 t
/\ verification_conditions P2 e
| DCWhile b Pbody d Ppost =>
(* post d is the loop invariant and the initial precondition *)
(P ~~> post d)
/\ ((fun st => post d st /\ bassn b st) <~~> Pbody)
/\ ((fun st => post d st /\ ~(bassn b st)) <~~> Ppost)
/\ verification_conditions (fun st => post d st /\ bassn b st) d
| DCPre P' d =>
(P ~~> P') /\ verification_conditions P' d
| DCPost d Q =>
verification_conditions P d /\ (post d ~~> Q)
end.
(* And now, the key theorem, which captures the claim that the
[verification_conditions] function does its job correctly. Not
surprisingly, we need all of the Hoare Logic rules in the
proof. *)
(** そしてついに、主定理です。この定理は、
[verification_conditions]関数が正しくはたらくことを主張します。
当然ながら、その証明にはホーア論理のすべての規則が必要となります。*)
(* We have used _in_ variants of several tactics before to
apply them to values in the context rather than the goal. An
extension of this idea is the syntax [tactic in *], which applies
[tactic] in the goal and every hypothesis in the context. We most
commonly use this facility in conjunction with the [simpl] tactic,
as below. *)
(** これまで、いろいろなタクティックについて、
ゴールではなくコンテキストの値に適用する別形を使ってきました。
このアイデアの拡張が構文[tactic in *]です。
この構文では、[tactic]をゴールとコンテキストのすべての仮定とに適用します。
このしくみは、下記のように[simpl]タクティックと組み合わせて使うのが普通です。*)
Theorem verification_correct : forall d P,
verification_conditions P d -> {{P}} (extract d) {{post d}}.
Proof.
dcom_cases (induction d) Case; intros P H; simpl in *.
Case "Skip".
eapply hoare_consequence_pre.
apply hoare_skip.
assumption.
Case "Seq".
inversion H as [H1 H2]. clear H.
eapply hoare_seq.
apply IHd2. apply H2.
apply IHd1. apply H1.
Case "Asgn".
eapply hoare_consequence_pre.
apply hoare_asgn.
assumption.
Case "If".
inversion H as [HPre1 [HPre2 [HQeq [HThen HElse]]]]; clear H.
apply hoare_if.
eapply hoare_consequence_pre. apply IHd1. apply HThen. assumption.
simpl. rewrite HQeq.
eapply hoare_consequence_pre. apply IHd2. apply HElse. assumption.
Case "While".
rename a into Pbody. rename a0 into Ppost.
inversion H as [Hpre [Hbody [Hpost Hd]]]; clear H.
eapply hoare_consequence.
apply hoare_while with (P := post d).
apply IHd. apply Hd.
assumption. apply Hpost.
Case "Pre".
inversion H as [HP Hd]; clear H.
eapply hoare_consequence_pre. apply IHd. apply Hd. assumption.
Case "Post".
inversion H as [Hd HQ]; clear H.
eapply hoare_consequence_post. apply IHd. apply Hd. assumption.
Qed.
(* ** Examples *)
(** ** 例 *)
(* The propositions generated by [verification_conditions] are fairly
big, and they contain many conjuncts that are essentially trivial. *)
(** [verification_conditions]が生成する命題はかなり大きく、
/\ でつながれた命題の中には本質的に自明なものも多く含まれます。*)
Eval simpl in (verification_conditions (fun st => True) dec_while).
(* ====>
((fun _ : state => True) ~~> (fun _ : state => True)) /\
((fun _ : state => True) ~~> (fun _ : state => True)) /\
((fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st)
<~~> (fun st : state => asnat (st X) <> 0)) /\
((fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st)
<~~> (fun st : state => asnat (st X) = 0)) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st)
~~> assn_sub X (AMinus (AId X) (ANum 1)) (fun _ : state => True) *)
(* We can certainly work with them using just the tactics we have so
far, but we can make things much smoother with a bit of
automation. We first define a custom [verify] tactic that applies
splitting repeatedly to turn all the conjunctions into separate
subgoals and then uses [omega] and [eauto] (a handy
general-purpose automation tactic that we'll discuss in detail
later) to deal with as many of them as possible. *)
(** ここまで見てきたタクティックだけを使うことでこれらの命題の証明を進めることは確かにできるのですが、
いくらか自動化を入れることで、よりスムーズに進められるようにできます。
最初に自前のタクティック[verify]を定義します。
このタクティックは、split を繰り返し適用して/\でつながれた命題を個々のサブゴールに分割し、
その後[omega]と[eauto](便利な一般用途のタクティック。後に詳しく議論します)
を適用可能な限り使います。*)
Tactic Notation "verify" :=
try apply verification_correct;
repeat split;
simpl; unfold assert_implies;
unfold bassn in *; unfold beval in *; unfold aeval in *;
unfold assn_sub; simpl in *;
intros;
repeat match goal with [H : _ /\ _ |- _] => destruct H end;
try eauto; try omega.
(* What's left after [verify] does its thing is "just the interesting
parts" of checking that the decorations are correct. For example: *)
(** [verify]適用後残るのは、修飾の正しさをチェックするのに「興味深い部分だけ」です。
例えば: *)
Theorem dec_while_correct :
dec_correct dec_while.
Proof.
verify; destruct (asnat (st X)).
inversion H0.
unfold not. intros. inversion H1.
apply ex_falso_quodlibet. apply H. reflexivity.
reflexivity.
reflexivity.
apply ex_falso_quodlibet. apply H0. reflexivity.
unfold not. intros. inversion H0.
inversion H.
Qed.
(* Another example (formalizing a decorated program we've seen
before): *)
(** 別の例(前に見た修飾付きプログラムを形式化したもの)です: *)
Example subtract_slowly_dec (x:nat) (z:nat) : dcom := (
{{ fun st => asnat (st X) = x /\ asnat (st Z) = z }}
WHILE BNot (BEq (AId X) (ANum 0))
DO {{ fun st => asnat (st Z) - asnat (st X) = z - x
/\ bassn (BNot (BEq (AId X) (ANum 0))) st }}
Z ::= AMinus (AId Z) (ANum 1)
{{ fun st => asnat (st Z) - (asnat (st X) - 1) = z - x }} ;
X ::= AMinus (AId X) (ANum 1)
{{ fun st => asnat (st Z) - asnat (st X) = z - x }}
END
{{ fun st => asnat (st Z)
- asnat (st X)
= z - x
/\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st }}
=>
{{ fun st => asnat (st Z) = z - x }}
) % dcom.
Theorem subtract_slowly_dec_correct : forall x z,
dec_correct (subtract_slowly_dec x z).
Proof.
intros. verify.
rewrite <- H.
assert (H1: update st Z (VNat (asnat (st Z) - 1)) X = st X).
apply update_neq. reflexivity.
rewrite -> H1. destruct (asnat (st X)) as [| X'].
inversion H0. simpl. rewrite <- minus_n_O. omega.
destruct (asnat (st X)).
omega.
apply ex_falso_quodlibet. apply H0. reflexivity.
Qed.
(* **** Exercise: 3 stars (slow_assignment_dec) *)
(** **** 練習問題: ★★★ (slow_assignment_dec) *)
(* A roundabout way of assigning a number currently stored in [X] to
the variable [Y] is to start [Y] at [0], then decrement [X] until it
hits [0], incrementing [Y] at each step.
Here is an informal decorated program that implements this idea
given a parameter [x]: *)
(** [X]に現在設定されている値を変数[Y]に代入する遠回りの方法は、
[Y]を[0]から始め、
[X]を[0]になるまで減らしていきながら、その各ステップで[Y]を増やしていくことです。
次が、
このアイデアを[x]をパラメータとする非形式的な修飾付きプログラムで表したものです: *)
(**
[[
{{ True }}
X ::= x
{{ X = x }} ;
Y ::= 0
{{ X = x /\ Y = 0 }} ;
WHILE X <> 0 DO
{{ X + Y = x /\ X > 0 }}
X ::= X - 1
{{ Y + X + 1 = x }} ;
Y ::= Y + 1
{{ Y + X = x }}
END
{{ Y = x /\ X = 0 }}
]]
*)
(* Write a corresponding function that returns a value of type [dcom]
and prove it correct. *)
(** 対応する[dcom]型の値を返す関数を記述し、その正しさを証明しなさい。*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 4 stars, optional (factorial_dec) *)
(** **** 練習問題: ★★★★, optional (factorial_dec) *)
(* Remember the factorial function we worked with before: *)
(** 以前に扱った階乗関数を思い出してください: *)
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
(* Following the pattern of [subtract_slowly_dec], write a decorated
Imp program that implements the factorial function, and prove it
correct. *)
(** [subtract_slowly_dec]のパターンに倣って、
階乗計算の修飾付きImpプログラムを記述し、その正しさを証明しなさい。*)
(* FILL IN HERE *)
(** [] *)
(* Finally, for a bigger example, let's redo the proof of
[list_member_correct] from above using our new tools.
Notice that the [verify] tactic leaves subgoals for each use of
[hoare_consequence] -- that is, for each [=>] that occurs in the
decorated program. Each of these implications relies on a fact
about lists, for example that [l ++ [] = l]. In other words, the
Hoare logic infrastructure has taken care of the boilerplate
reasoning about the execution of imperative programs, while the
user has to prove lemmas that are specific to the problem
domain (e.g. lists or numbers). *)
(** 最後に、より大きな例として、
新しい道具立てを使って[list_member_correct]の証明を再度行ってみましょう。
[verify]タクティックは[hoare_consequence]を利用するたびに
(つまり修飾付きプログラムに[=>]が現れるたびに)サブゴールを作ることに注意します。
これらの含意は、リストについての事実(例えば[l ++ [] = l]など)に依存しています。
言い換えると、ホーア論理のインフラは命令型プログラムの実行についての一般的な部分を扱い、
一方ユーザは(例えば数値のリストという)問題領域特有の補題を証明しなければなりません。*)
Definition list_member_dec (n : nat) (l : list nat) : dcom := (
{{ fun st => st X = VList l /\ st Y = VNat n /\ st Z = VNat 0 }}
WHILE BIsCons (AId X)
DO {{ fun st => st Y = VNat n
/\ (exists p, p ++ aslist (st X) = l
/\ (st Z = VNat 1 <-> appears_in n p))
/\ bassn (BIsCons (AId X)) st }}
IFB (BEq (AId Y) (AHead (AId X))) THEN
{{ fun st =>
((st Y = VNat n
/\ (exists p, p ++ aslist (st X) = l
/\ (st Z = VNat 1 <-> appears_in n p)))
/\ bassn (BIsCons (AId X)) st)
/\ bassn (BEq (AId Y) (AHead (AId X))) st }}
=>
{{ fun st =>
st Y = VNat n
/\ (exists p, p ++ tail (aslist (st X)) = l
/\ (VNat 1 = VNat 1 <-> appears_in n p)) }}
Z ::= ANum 1
{{ fun st => st Y = VNat n
/\ (exists p, p ++ tail (aslist (st X)) = l
/\ (st Z = VNat 1 <-> appears_in n p)) }}
ELSE
{{ fun st =>
((st Y = VNat n
/\ (exists p, p ++ aslist (st X) = l
/\ (st Z = VNat 1 <-> appears_in n p)))
/\ bassn (BIsCons (AId X)) st)
/\ ~bassn (BEq (AId Y) (AHead (AId X))) st }}
=>
{{ fun st =>
st Y = VNat n
/\ (exists p, p ++ tail (aslist (st X)) = l
/\ (st Z = VNat 1 <-> appears_in n p)) }}
SKIP
{{ fun st => st Y = VNat n
/\ (exists p, p ++ tail (aslist (st X)) = l
/\ (st Z = VNat 1 <-> appears_in n p)) }}
FI ;
X ::= (ATail (AId X))
{{ fun st =>
st Y = VNat n /\
(exists p : list nat, p ++ aslist (st X) = l
/\ (st Z = VNat 1 <-> appears_in n p)) }}
END
{{ fun st =>
(st Y = VNat n
/\ (exists p, p ++ aslist (st X) = l
/\ (st Z = VNat 1 <-> appears_in n p)))
/\ ~bassn (BIsCons (AId X)) st }}
=>
{{ fun st => st Z = VNat 1 <-> appears_in n l }}
) %dcom.
Theorem list_member_correct' : forall n l,
dec_correct (list_member_dec n l).
Proof.
intros n l.
verify.
Case "The loop precondition holds.".
exists []. simpl. split.
rewrite H. reflexivity.
rewrite H1. split; inversion 1.
Case "IF taken".
destruct H2 as [p [H3 H4]].
(* We know X is non-nil. *)
remember (aslist (st X)) as x.
destruct x as [|h x'].
inversion H1.
exists (snoc p h).
simpl. split.
rewrite snoc_equation. assumption.
split.
rewrite H in H0.
simpl in H0.
rewrite (beq_true__eq _ _ H0).
intros. apply appears_in_snoc1.
intros. reflexivity.
Case "If not taken".
destruct H2 as [p [H3 H4]].
(* We know X is non-nil. *)
remember (aslist (st X)) as x.
destruct x as [|h x'].
inversion H1.
exists (snoc p h).
split.
rewrite snoc_equation. assumption.
split.
intros. apply appears_in_snoc2. apply H4. assumption.
intros Hai. destruct (appears_in_snoc3 _ _ _ Hai).
SCase "later". apply H4. assumption.
SCase "here (absurd)".
subst.
simpl in H0. rewrite H in H0. rewrite beq_nat_refl in H0.
apply ex_falso_quodlibet. apply H0. reflexivity.
Case "Loop postcondition implies desired conclusion (->)".
destruct H2 as [p [H3 H4]].
unfold bassn in H1. simpl in H1.
destruct (aslist (st X)) as [|h x'].
rewrite append_nil in H3. subst. apply H4. assumption.
apply ex_falso_quodlibet. apply H1. reflexivity.
Case "loop postcondition implies desired conclusion (<-)".
destruct H2 as [p [H3 H4]].
unfold bassn in H1. simpl in H1.
destruct (aslist (st X)) as [|h x'].
rewrite append_nil in H3. subst. apply H4. assumption.
apply ex_falso_quodlibet. apply H1. reflexivity.
Qed.
|
////////////////////////////////////////////////////////////////////-
// Design unit: testbench (Module)
// :
// File name : testbench.v
// :
// Description: Test Bench for RTL Vending Machine
// :
// Limitations: None
// :
// System : Verilog
// :
// Author : 1. Wan Ahmad Zainie bin Wan Mohamad (ME131135)
// : [email protected]
// : 2. Azfar 'Aizat bin Mohd Isa (ME131032)
// : [email protected]
//
// Revision : Version 0.1 2014-06-01
// : Version 1.0 2014-06-09 Ready for submission
// : Version 2.0 2014-06-10 Change to behavioral - more simulation
////////////////////////////////////////////////////////////////////-
`timescale 100ns / 1ns
module testbench();
// inputs
reg clk, rst;
reg [9:0] deposit, price;
reg [4:0] select;
reg deposited, selected, cancel, maintenance;
// outputs
wire refund, refundall, depositall;
wire [4:0] product;
wire [9:0] change;
wire [2:0] state;
// instantiation
vm myVM(
.clk(clk),
.rst(rst),
.deposit(deposit),
.deposited(deposited),
.select(select),
.selected(selected),
.price(price),
.cancel(cancel),
.maintenance(maintenance),
.refund(refund),
.refundall(refundall),
.depositall(depositall),
.product(product),
.change(change),
.state(state)
);
// for future use
// initial begin
// $display("time: rst, clk");
// $monitor(" %0d: %b, %b", $time, rst, clk);
// end
initial begin
clk= 0;
#5;
forever #5 clk = ~clk;
end
initial begin
rst= 0;
deposited= 0; deposit= 0; selected= 0; select= 'bx; price= 0;
cancel= 0; maintenance= 0;
#10;
#10 rst= 1;
// simulate overflow, insert payment more than threshold value
#20 deposited= 1; deposit= 100;
#20 deposited= 1; deposit= 200;
#20 deposited= 1; deposit= 200;
#20 deposited= 1; deposit= 1;
#20 deposited= 0;
#20;
// simulate cancel
#20 cancel= 1;
#20 cancel= 0;
#20;
// simulate purchase
#20 deposited= 1; deposit= 10;
#20 deposited= 1; deposit= 100;
#20 deposited= 1; deposit= 20;
#10 deposited= 0;
#20 selected= 1; select= 10;
#20 selected= 0; select= 'bx;
#20;
// simulate maintenance changing price
#20 maintenance= 1;
#20 selected= 1; select = 0; price= 10;
#20 selected= 1; select = 31; price= 10;
#20 selected= 1; select = 1; price= 15;
#20 selected= 1; select = 2; price= 10;
#20 selected= 1; select = 3; price= 20;
#20 selected= 1; select = 4; price= 10;
#20 selected= 1; select = 5; price= 15;
#20 selected= 1; select = 6; price= 15;
#20 selected= 1; select = 7; price= 15;
#20 selected= 1; select = 8; price= 10;
#20 selected= 1; select = 9; price= 10;
#20 selected= 1; select = 10; price= 10;
#20 selected= 1; select = 11; price= 10;
#20 selected= 1; select = 12; price= 10;
#20 selected= 1; select = 13; price= 10;
#20 selected= 1; select = 14; price= 10;
#20 selected= 1; select = 15; price= 10;
#20 selected= 1; select = 16; price= 10;
#20 selected= 1; select = 17; price= 10;
#20 selected= 1; select = 18; price= 10;
#20 selected= 1; select = 19; price= 10;
#20 selected= 1; select = 20; price= 10;
#20 selected= 1; select = 21; price= 10;
#20 selected= 1; select = 22; price= 10;
#20 selected= 1; select = 23; price= 10;
#20 selected= 1; select = 24; price= 10;
#20 selected= 1; select = 25; price= 10;
#20 selected= 1; select = 26; price= 10;
#20 selected= 1; select = 27; price= 10;
#20 selected= 1; select = 28; price= 20;
#20 selected= 1; select = 29; price= 20;
#20 selected= 1; select = 30; price= 20;
#20 selected= 1; select = 31; price= 99;
#20 selected= 0; select= 'bx; maintenance = 0;
#20;
// simulate purchase after changing price, item 30, from RM10 to RM2 (balance RM28)
#20 deposited= 1; deposit= 200;
#20 deposited= 1; deposit= 500;
#20 deposited= 1; deposit= 100;
#20 deposited= 0;
#20 selected= 1; select= 30;
#20 selected= 0; select= 'bx;
#20 selected= 1; select= 3;
#20 selected= 0; select= 'bx;
#200 $stop;
end
endmodule
|
//======================================================================
//
// tb_blake2.v
// -----------
// Testbench for the Blake2 top level wrapper.
//
//
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/10ps
module tb_blake2();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter CLK_HALF_PERIOD = 2;
// API for the dut.
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_write_read;
reg [7 : 0] tb_address;
reg [31 : 0] tb_data_in;
wire [31 : 0] tb_data_out;
wire tb_error;
reg [63 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg error_found;
reg [31 : 0] read_data;
reg [511 : 0] extracted_data;
reg display_cycle_ctr;
reg display_read_write;
//----------------------------------------------------------------
// Blake2 device under test.
//----------------------------------------------------------------
blake2 dut(
// Clock and reset.
.clk(tb_clk),
.reset_n(tb_reset_n),
// Control.
.cs(tb_cs),
.we(tb_write_read),
// Data ports.
.address(tb_address),
.write_data(tb_data_in),
.read_data(tb_data_out),
.error(tb_error)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
//
// Monitor displaying information every cycle.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (display_cycle_ctr)
begin
$display("cycle = %016x:", cycle_ctr);
end
end // dut_monitor
//----------------------------------------------------------------
// reset_dut
//----------------------------------------------------------------
task reset_dut();
begin
tb_reset_n = 0;
#(4 * CLK_HALF_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// dump_dut_state
//
// Dump the internal state of the dut to std out.
//----------------------------------------------------------------
task dump_dut_state();
begin
$display("");
$display("DUT internal state");
$display("------------------");
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result();
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// init_dut()
//
// Set the input to the DUT to defined values.
//----------------------------------------------------------------
task init_dut();
begin
// Set clock, reset and DUT input signals to
// defined values at simulation start.
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 0;
tb_cs = 0;
tb_write_read = 0;
tb_address = 8'h00;
tb_data_in = 32'h00000000;
end
endtask // init_dut
//----------------------------------------------------------------
// blake2_test
// The main test functionality.
//----------------------------------------------------------------
initial
begin : blake2_test
$display(" -- Testbench for blake2 started --");
init_dut();
reset_dut();
$display("State at init after reset:");
dump_dut_state();
display_test_result();
$display("*** blake2 simulation done.");
$finish;
end // blake2_test
endmodule // tb_blake2
//======================================================================
// EOF tb_blake2.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_PP_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_PP_SYMBOL_V
/**
* lpflow_inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputiso0p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21OI_4_V
`define SKY130_FD_SC_LS__A21OI_4_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21oi_4 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21OI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__SDFSBP_FUNCTIONAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_s_pg/sky130_fd_sc_hs__u_df_p_s_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfsbp (
VPWR ,
VGND ,
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_s_pg `UNIT_DELAY u_df_p_s_pg0 (buf_Q , mux_out, CLK, SET, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSBP_FUNCTIONAL_V |
/*******************************************************************
*****串口发送模块
*****
*****
*******************************************************************/
module Uart_tx(
input clk,
input rst_n,
input [3:0] num, //一帧数据有几位由num来决定
input sel_data, //波特率技计数中心点（采集数据的使能信号）
input [7:0] rx_data,
output reg rs232_tx
);
always @(posedge clk or negedge rst_n)
if(!rst_n)
rs232_tx <= 1'b1;
else
if(sel_data) //检测波特率采样中心点（使能信号）
case(num) //检测要发送的一帧数据有几位？
0: rs232_tx <= 1'b0; //开始位为低电平
1: rs232_tx <= rx_data[0];
2: rs232_tx <= rx_data[1];
3: rs232_tx <= rx_data[2];
4: rs232_tx <= rx_data[3];
5: rs232_tx <= rx_data[4];
6: rs232_tx <= rx_data[5];
7: rs232_tx <= rx_data[6];
8: rs232_tx <= rx_data[7];
9: rs232_tx <= 1'b1; //结束位为高电平
default: rs232_tx <= 1'b1; //在其他情况下一直处于拉高电平状态
endcase
endmodule |
`include "../src/oserdes_test.v"
`include "../src/lfsr.v"
`include "../src/comparator.v"
`default_nettype none
`timescale 1ns / 1ps
// ============================================================================
module tb;
// ============================================================================
reg CLK;
initial CLK <= 1'b0;
always #0.5 CLK <= !CLK;
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge CLK) rst_sr <= rst_sr >> 1;
wire RST;
assign RST = rst_sr[0];
// ============================================================================
initial begin
$dumpfile("waveforms.vcd");
$dumpvars;
end
integer cycle_cnt;
initial cycle_cnt <= 0;
always @(posedge CLK)
if (!RST) cycle_cnt <= cycle_cnt + 1;
always @(posedge CLK)
if (!RST && cycle_cnt >= 10000)
$finish;
// ============================================================================
reg clk_r;
always @(posedge CLK)
if (RST) clk_r <= 1'b0;
else clk_r <= !clk_r;
wire CLK1 = CLK;
wire CLK2 = clk_r;
// ============================================================================
wire s_dat;
oserdes_test #
(
.DATA_WIDTH (8),
.DATA_RATE ("SDR"),
.ERROR_HOLD (4)
)
trx_path
(
.CLK (CLK),
.CLK1 (CLK1),
.CLK2 (CLK2),
.RST (RST),
.IO_DAT (s_dat)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4B_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR4B_BLACKBOX_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4B_BLACKBOX_V
|
`include "fifo/fifo.v"
module BusArbiter
#(
parameter bus_width=32,
parameter bus_max_devices=16 // -1, since device #0 can't be used
)
(
input clk,
inout [bus_width-1:0] data_lines,
inout [bus_max_devices-1:0] receiver_device, // one-hot
inout [bus_max_devices-1:0] buffer_full, // hold your horses (raised by receiving device)
input [bus_max_devices-1:0] write_request, // priority queue: LSBs first, 0 is invalid
output reg [bus_max_devices-1:0] voice // one-hot signalling
);
// device can hold the bus as long as it has to, and we need this
// register to know when we can assign voice to another device
reg [bus_max_devices-1:0] operating_device=0;
generate
genvar device;
for (device=1; device<bus_max_devices; device=device+1) begin: voice_gen
always @(negedge clk)
// update voice when device has ended its transaction
if (!operating_device || operating_device&&(~write_request[operating_device])) begin
voice[device]=write_request[device] && !write_request[device-1:0];
operating_device=voice; // TODO Will it synthesize?
end
end
endgenerate
always @(clk) begin
if (clk)
$display("BusArbiter: + posedge clk on bus");
else
$display("BusArbiter: - negedge clk on bus");
$display("BusArbiter: bus_data_lines: %b",data_lines);
$display("BusArbiter: bus_receiver_device: %b",receiver_device);
$display("BusArbiter: bus_buffer_full: %b",buffer_full);
$display("BusArbiter: bus_write_request: %b",write_request);
$display("BusArbiter: bus_voice: %b",voice);
$display("BusArbiter: operating_device: %b",operating_device);
end
endmodule
module BusWriter
#(
parameter bus_width=32, // compatible with default bus width
parameter device_id=1 // bit position in bus_voice or bus_receiver, ie. device_id 6 -> sixth bit
)
(
// bus side
input clk,
output [bus_width-1:0] bus_data,
output [bus_max_devices-1:0] bus_receiver,
input [bus_max_devices-1:0] bus_buffer_full,
output [bus_max_devices-1:0] bus_write_request,
input [bus_max_devices-1:0] bus_voice,
// device side
input [bus_width-1:0] client_data,
input [bus_max_devices-1:0] client_target_addr,
input client_enqueue, // save client_data and client_target_addr in FIFOs
output client_buffer_empty, // true, if FIFO empty (all data sent)
output client_buffer_full // true, if FIFO full
);
wire voice=bus_voice[device_id];
wire receiver_buffer_full=bus_buffer_full[bus_receiver];
// negedge copies of FIFO data
wire [bus_width-1:0] buffer_out_net;
reg [bus_width-1:0] buffer_out_reg;
wire [bus_max_devices-1:0] receiver_addr_net;
reg [bus_max_devices-1:0] receiver_addr_reg;
wire client_buffer_full_net;
reg client_buffer_full_reg;
wire client_buffer_empty_net;
reg client_buffer_empty_reg=1;
always @(negedge clk) begin
buffer_out_reg<=buffer_out_net;
receiver_addr_reg<=receiver_addr_net;
client_buffer_full_reg<=client_buffer_full_net;
client_buffer_empty_reg<=client_buffer_empty_net;
end
assign bus_receiver=voice ? receiver_addr_reg : 'bz;
assign bus_data=voice ? buffer_out_reg : 'bz;
assign client_buffer_empty=client_buffer_empty_reg;
assign client_buffer_full=client_buffer_full_reg;
wire wreq=~client_buffer_empty && ~receiver_buffer_full;
generate
genvar id;
for (id=0; id<bus_max_devices; id=id+1) begin: wreq_highz
assign bus_write_request[id]=id==device_id ? wreq : 'bz;
end
endgenerate
wire buffer_next=voice && ~receiver_buffer_full && ~client_buffer_empty;
wire clear=0;
FIFO
#(
.data_width(bus_width),
.size(bus_buffer_size),
.device_id(device_id)
) buffer
(
.data_in(client_data),
.data_out(buffer_out_net),
.clk(clk),
.next(buffer_next),
.insert(client_enqueue),
.clear(clear),
.full(client_buffer_full_net),
.empty(client_buffer_empty_net)
);
wire recv_addresses_buffer_full;
wire recv_addresses_buffer_empty;
FIFO
#(
.data_width(bus_max_devices),
.size(bus_buffer_size),
.device_id(device_id<<1)
) recv_addresses
(
.data_in(client_target_addr),
.data_out(receiver_addr_net),
.clk(clk),
.next(buffer_next),
.insert(client_enqueue),
.clear(clear),
.full(recv_addresses_buffer_full),
.empty(recv_addresses_buffer_empty)
);
always @(clk) begin
if (clk) begin
$display("BusWriter %d: buffer.next=%b",device_id,buffer_next);
$display("BusWriter %d: buffer.insert=%b",device_id,client_enqueue);
$display("BusWriter %d: buffer.full=%b",device_id,client_buffer_full);
$display("BusWriter %d: buffer.client_buffer_empty=%b",device_id,client_buffer_empty);
$display("BusWriter %d: buffer.data_in=%b",device_id,client_data);
$display("BusWriter %d: recv_addresses.data_in=%b",device_id,client_target_addr);
end
else begin
for (int i=0; i<4; i=i+1) begin
$display("BusWriter %d: mem[%d]=%b",device_id,i,buffer.mem[i]);
end
if (receiver_addr_reg==0 && voice)
$display("BusWriter %d: --MAJOR SCREWUP-- Sending to address 0",device_id);
end
end
endmodule
module BusReader
#(
parameter bus_width=32, // compatible with default bus width
parameter bus_max_devices=16,
parameter bus_buffer_size=32,
parameter device_id=1 // bit position in bus_voice or bus_receiver, ie. device_id 6 -> sixth bit
)
(
// bus side
input clk,
input [bus_width-1:0] bus_data,
input [bus_max_devices-1:0] bus_receiver,
output [bus_max_devices-1:0] bus_buffer_full,
input [bus_max_devices-1:0] bus_voice,
// device side
output [bus_width-1:0] client_data,
output [bus_max_devices-1:0] client_source_addr,
input client_next, // save client_data and client_source_addr in FIFOs
output client_buffer_empty, // true, if FIFO empty (all data read)
output client_buffer_full // true, if FIFO full
);
wire data_on_bus=bus_receiver[device_id] && bus_voice;
assign bus_buffer_full[device_id]=client_buffer_full;
wire clear=0;
FIFO
#(
.data_width(bus_width),
.size(bus_buffer_size),
.device_id(device_id)
) buffer
(
.data_in(bus_data),
.data_out(client_data),
.clk(clk),
.next(client_next),
.insert(data_on_bus),
.clear(clear),
.full(client_buffer_full),
.empty(client_buffer_empty)
);
wire sender_addresses_buffer_full;
wire sender_addresses_buffer_empty;
FIFO
#(
.data_width(bus_max_devices),
.size(bus_buffer_size),
.device_id(device_id<<1)
) sender_addresses
(
.data_in(bus_voice),
.data_out(client_source_addr),
.clk(clk),
.next(client_next),
.insert(data_on_bus),
.clear(clear),
.full(sender_addresses_buffer_full),
.empty(sender_addresses_buffer_empty)
);
always @(posedge clk) begin
if (data_on_bus && client_source_addr==0)
$display("BusReader %d: --MAJOR SCREWUP-- Received data from address 0",device_id);
end
endmodule
module BusClient
#(
parameter bus_width=32, // compatible with default bus width
parameter bus_max_devices=16,
parameter bus_buffer_size=32,
parameter device_id=1 // bit position in bus_voice or bus_receiver, ie. device_id 6 -> sixth bit
)
(
// bus side
input clk,
inout [bus_width-1:0] bus_data,
inout [bus_max_devices-1:0] bus_receiver,
inout [bus_max_devices-1:0] bus_write_request,
inout [bus_max_devices-1:0] bus_buffer_full,
input [bus_max_devices-1:0] bus_voice,
// device side
output [bus_width-1:0] client_data_in,
output [bus_max_devices-1:0] client_source_addr,
input [bus_width-1:0] client_data_out,
input [bus_max_devices-1:0] client_destination_addr,
input client_read_next,
input client_send_next,
output client_input_buffer_empty,
output client_input_buffer_full,
output client_output_buffer_empty,
output client_output_buffer_full
);
BusReader
#(
.bus_width(bus_width),
.bus_max_devices(bus_max_devices),
.bus_buffer_size(bus_buffer_size),
.device_id(device_id)
) reader
(
clk,
bus_data,
bus_receiver,
bus_buffer_full,
bus_voice,
client_data_in,
client_source_addr,
client_read_next,
client_input_buffer_empty,
client_input_buffer_full
);
BusWriter
#(
.bus_width(bus_width),
.bus_max_devices(bus_max_devices),
.bus_buffer_size(bus_buffer_size),
.device_id(device_id)
) writer
(
clk,
bus_data,
bus_receiver,
bus_buffer_full,
bus_write_request,
bus_voice,
client_data_out,
client_destination_addr,
client_send_next,
client_output_buffer_empty,
client_output_buffer_full
);
always @(negedge clk) begin
$display("BusClient %d: words in in_buffer: %d",device_id,reader.buffer.words_inside);
$display("BusClient %d: words in out_buffer: %d",device_id,writer.buffer.words_inside);
end
endmodule
module BusTester
#(
// bus-related
parameter bus_width=32,
parameter bus_max_devices=16,
parameter bus_buffer_size=32,
parameter device_id=1,
parameter send_to=2
)
(
// bus side
input clk,
inout [bus_width-1:0] bus_data,
inout [bus_max_devices-1:0] bus_receiver,
inout [bus_max_devices-1:0] bus_write_request,
inout [bus_max_devices-1:0] bus_buffer_full,
input [bus_max_devices-1:0] bus_voice
);
wire [bus_width-1:0] bus_in;
wire [bus_max_devices-1:0] bus_source;
wire [bus_width-1:0] bus_out;
reg [bus_max_devices-1:0] bus_target;
wire bus_next; // read next from FIFO
wire bus_send;
wire bus_input_empty;
wire bus_input_full;
wire bus_output_empty;
wire bus_output_full;
BusClient
#(
.bus_width(bus_width),
.bus_max_devices(bus_max_devices),
.bus_buffer_size(bus_buffer_size),
.device_id(device_id)
) bus_client
(
clk,
bus_data,
bus_receiver,
bus_write_request,
bus_buffer_full,
bus_voice,
bus_in,
bus_source,
bus_out,
bus_target,
bus_next,
bus_send,
bus_input_empty,
bus_input_full,
bus_output_empty,
bus_output_full
);
reg [31:0] counter;
assign bus_out=counter;
assign bus_target=1<<send_to;
always @(negedge clk) begin
if (device_id==2) begin
bus_send<=1;
bus_next<=0;
counter<=counter+1;
$display("BusTester %d: sending %d to %d",device_id,bus_out,bus_target);
end
else if (device_id==8) begin
bus_send<=0;
if (~bus_input_empty) begin
bus_next<=1;
$display("BusTester %d: received %d from %d",device_id,bus_in,bus_source);
end
else begin
bus_next<=0;
$display("BusTester %d: input buffer empty",device_id);
end
end
else
$display("BusTester: id==%d",device_id);
end
endmodule
module BusTestRig
#(
parameter bus_width=32,
parameter bus_max_devices=16 // -1, since device #0 can't be used
)
(
input clk
);
// bus
tri [bus_width-1:0] bus_data_lines;
tri [bus_max_devices-1:0] bus_receiver_device;
tri [bus_max_devices-1:0] bus_buffer_full;
wire [bus_max_devices-1:0] bus_write_request;
wire [bus_max_devices-1:0] bus_voice;
BusArbiter bus_arbiter
(
clk,
bus_data_lines,
bus_receiver_device,
bus_buffer_full,
bus_write_request,
bus_voice
);
BusTester
#(
.bus_width(32),
.bus_max_devices(16),
.device_id(2),
.send_to(8)
) test_module_1
(
clk,
bus_data_lines,
bus_receiver_device,
bus_write_request,
bus_buffer_full,
bus_voice
);
BusTester
#(
.bus_width(32),
.bus_max_devices(16),
.device_id(8),
.send_to(2)
) test_module_2
(
clk,
bus_data_lines,
bus_receiver_device,
bus_write_request,
bus_buffer_full,
bus_voice
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fcud
#(parameter
ID = 1,
NUM_STAGE = 5,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fmul_3_max_dsp_32 convolve_kernel_ap_fmul_3_max_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
// Copyright (c) 2015 CERN
// @author Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// boolean values test.
module vhdl_boolean_test;
vhdl_boolean dut();
initial begin
if(dut.true_val != \true ) begin
$display("FAILED true 1");
$finish();
end
if(!dut.true_val) begin
$display("FAILED true 2");
$finish();
end
if(dut.false_val != \false ) begin
$display("FAILED false 1");
$finish();
end
if(dut.false_val) begin
$display("FAILED false 2");
$finish();
end
if(!dut.and1) begin
$display("FAILED and1");
$finish();
end
if(dut.and2) begin
$display("FAILED and2");
$finish();
end
if(dut.and3) begin
$display("FAILED and3");
$finish();
end
if(!dut.or1) begin
$display("FAILED or1");
$finish();
end
if(dut.or2) begin
$display("FAILED or2");
$finish();
end
if(dut.or3) begin
$display("FAILED or3");
$finish();
end
if(!dut.not1) begin
$display("FAILED not1");
$finish();
end
if(dut.not2) begin
$display("FAILED not2");
$finish();
end
$display("PASSED");
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_PP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire buf0_out_Q ;
wire not1_out_qn;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_PP_V |
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
*
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
* -------------------------------------------------------------------------------
*
* Logic to determine if the physical-channel held by a particular packet
* (buffered in an input PL FIFO) is blocked or ready?
*
* Looks at currently allocated PL or the next free PL that would be allocated
* at this port (as PL allocation may be taking place concurrently).
*
*/
module LAG_pl_status (output_port,
allocated_pl,
allocated_pl_valid,
pl_status,
pl_blocked);
parameter np = 5;
parameter integer links[np][2] = '{'{2,2}, '{2,2}, '{2,2}, '{2,2}, '{2,2} };
parameter ln_num = 2; //ln_num = maximum number of links per trunk
input output_port_t output_port [np-1:0][ln_num-1:0];
input [np-1:0][ln_num-1:0][ln_num-1:0] allocated_pl; // allocated PL ID
input [np-1:0][ln_num-1:0] allocated_pl_valid; // holding allocated PL?
input [np-1:0][ln_num-1:0] pl_status; // blocked/ready status for each output PL
output [np-1:0][ln_num-1:0] pl_blocked;
logic [np-1:0][ln_num-1:0] b, current_pl_blocked;
genvar ip,pl,op;
generate
for (ip=0; ip<np; ip++) begin:il
for (pl=0; pl<links[ip][IN]; pl++) begin:vl
//assign current_pl[ip][pl] = (allocated_pl_valid[ip][pl]) ? allocated_pl[ip][pl] : pl_requested[ip][pl];
unary_select_pair #(.input_port(ip), .WA(np), .WB(ln_num), .links(links)) blocked_mux
(output_port[ip][pl],
allocated_pl[ip][pl],
pl_status,
current_pl_blocked[ip][pl]);
assign b[ip][pl] = current_pl_blocked[ip][pl];
assign pl_blocked[ip][pl] = (LAG_route_valid_input_pl (ip,pl)) ? b[ip][pl] : 1'b0;
end
end
endgenerate
endmodule // LAG_pl_status
|
//////////////////////////////////////////////////////////////////////
//// ////
//// i2cSlaveTop.v ////
//// ////
//// This file is part of the i2cSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Modified by Nathan Larson for the Cloud Car project
//// 10/21/2016
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "i2cSlave_define.v"
module i2cSlaveTop (
clk,
rst,
sda,
scl,
myReg0
);
input clk;
input rst;
inout sda;
input scl;
output [7:0] myReg0;
i2cSlave u_i2cSlave(
.clk(clk),
.rst(rst),
.sda(sda),
.scl(scl),
.myReg0(myReg0),
.myReg1(),
.myReg2(),
.myReg3(),
.myReg4(8'h12),
.myReg5(8'h34),
.myReg6(8'h56),
.myReg7(8'h78)
);
endmodule
|
// testbench for chan_ctrl.v
`timescale 10ns/1ns
`define HALF_CLK (5.0)
class channel_data;
bit [13:0] base;
bit [19:0] size;
bit [19:0] loop; // actually loop-size
bit [ 5:0] add_int;
bit [11:0] add_frac;
bit [19:0] offset_int;
bit [11:0] offset_frac;
bit surround;
bit loopena;
bit [ 5:0] vol_left;
bit [ 5:0] vol_right;
function void init();
base = $random()>>(32-14);
add_int = $random()>>(32-6);
add_frac = $random()>>(32-12);
offset_int = $random()>>(32-20);
offset_frac = $random()>>(32-12);
size = $random()>>(32-10); // TODO: greater sizes
loop = {20{1'b1}};
while(loop>=size)
loop = $random()>>(32-10); // TODO: greater sizes
surround = $random()>>(32-1);
loopena = $random()>>(32-1);
vol_left = $random()>>(32-6);
vol_right = $random()>>(32-6);
endfunction
function void update();
bit cy;
int new_off;
bit [21:0] addr;
{cy,offset_frac} = {1'b0, offset_frac} + {1'b0, add_frac};
new_off = {31'd0, cy} + {26'd0,add_int} + {12'd0,offset_int};
if( new_off >= size )
begin
new_off = new_off - size + loop;
end
offset_int = new_off[19:0];
endfunction
function int get_word(input int wnum);
// return words suitable for channels state
if( wnum==0 )
get_word = {offset_int,offset_frac};
else if( wnum==1 )
get_word = {add_int, add_frac, loopena, surround, vol_left, vol_right};
else if( wnum==2 )
get_word = { (4'd0|$random()), size, base[7:0] };
else if( wnum==3 )
get_word = { (4'd0|$random()), loop-size, 2'b0, base[13:8] };
else
$stop;
endfunction
function bit [21:0] get_addr();
get_addr = base*256 + offset_int;
endfunction
function bit [6:0] get_vol_left();
get_vol_left = {1'b0, vol_left};
endfunction
function bit [6:0] get_vol_right();
if( surround )
get_vol_right = 7'h7F - {1'b0, vol_right};
else
get_vol_right = {1'b0, vol_right};
endfunction
function bit [7:0] get_frac();
get_frac = offset_frac[11:4];
endfunction
endclass
module tb;
reg clk;
reg rst_n;
// sync counter
integer sync_cnt;
bit pre_sync;
// DUT connections
wire [ 6:0] rd_addr;
tri0 [31:0] rd_data;
wire [ 6:0] wr_addr;
wire [31:0] wr_data;
wire wr_stb;
reg sync_stb;
reg [31:0] ch_enas;
wire [ 7:0] out_data;
wire out_stb_addr;
wire out_stb_mix;
// channels memory
reg [31:0] channels_mem [0:127];
// test data
channel_data chans[0:31];
// generation fifos
reg [7:0] mix_fifo[$];
reg [7:0] addr_fifo[$];
// init tb data structures
initial
begin : chans_create
int i;
for(i=0;i<32;i++) chans[i] = new;
mix_fifo.delete();
addr_fifo.delete();
end
// clock and reset gen
initial
begin
rst_n = 1'b0;
clk = 1'b1;
forever #(`HALF_CLK) clk = ~clk;
end
//
initial
begin
#(1);
repeat (3) @(posedge clk);
rst_n <= 1'b1;
end
// sync generator
initial
begin
sync_cnt = 0;
pre_sync = 1'b0;
sync_stb = 1'b0;
end
//
always @(posedge clk)
if( !rst_n )
begin
sync_cnt <= 637;
pre_sync <= 1'b0;
sync_stb <= 1'b0;
end
else
begin
if( sync_cnt<(640-1) )
sync_cnt <= sync_cnt + 1;
else
sync_cnt <= 0;
pre_sync <= !sync_cnt;
sync_stb <= pre_sync;
end
// channels memory emulator
reg [31:0] rd_data_reg;
assign rd_data = rd_data_reg;
//
always @(posedge clk)
rd_data_reg <= channels_mem[rd_addr];
//
always @(posedge clk)
if( wr_stb )
channels_mem[wr_addr] <= wr_data;
// fill queues off the output data
always @(posedge clk)
if( out_stb_mix ) mix_fifo.push_back(out_data);
//
always @(posedge clk)
if( out_stb_addr ) addr_fifo.push_back(out_data);
// channel generator/checker
always @(posedge clk)
if( sync_stb )
begin : chans
int i;
// if there was previous iteration, check it
// init channels for new iteration
for(i=0;i<32;i++)
begin
chans[i].init();
channels_mem[i*4+0] = chans[i].get_word(0);
channels_mem[i*4+1] = chans[i].get_word(1);
channels_mem[i*4+2] = chans[i].get_word(2);
channels_mem[i*4+3] = chans[i].get_word(3);
chans[i].update();
end
end
always @(posedge clk)
ch_enas = 32'hFFFF_FFFF;
// DUT
chan_ctrl chan_ctrl
(
.clk (clk ),
.rst_n(rst_n),
.rd_addr(rd_addr),
.rd_data(rd_data),
.wr_addr(wr_addr),
.wr_data(wr_data),
.wr_stb (wr_stb ),
.sync_stb(sync_stb),
.ch_enas(ch_enas),
.out_data (out_data ),
.out_stb_addr(out_stb_addr),
.out_stb_mix (out_stb_mix )
);
endmodule
|
// Double buffering with dual-port RAM
// Uses single-port RAM to write switches to a section while reading from the same section to control LEDs,
// so each switch acts as if connected directly to the corresponding LED.
// Flip SW0 to change sections.
module top (
input clk,
input [15:0] sw,
output [15:0] led,
// not used
input rx,
output tx
);
assign tx = rx; // TODO(#658): Remove this work-around
wire [5:0] addr;
wire ram_out;
wire ram_in;
RAM_SHIFTER #(
.IO_WIDTH(16),
.ADDR_WIDTH(7)
) shifter (
.clk(clk),
.in(sw),
.out(led),
.addr(addr),
.ram_out(ram_out),
.ram_in(ram_in)
);
RAM256X1S #(
.INIT(256'h96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5)
) ram0 (
.WCLK(clk),
.A({sw[0], addr}),
.O(ram_out),
.D(ram_in),
.WE(1'b1)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCIN_PP_SYMBOL_V
`define SKY130_FD_SC_LP__FAHCIN_PP_SYMBOL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fahcin (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCIN_PP_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:29:18 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_ov7670_controller_1_0 -prefix
// system_ov7670_controller_1_0_ system_ov7670_controller_1_0_stub.v
// Design : system_ov7670_controller_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_controller,Vivado 2016.4" *)
module system_ov7670_controller_1_0(clk, resend, config_finished, sioc, siod, reset,
pwdn, xclk)
/* synthesis syn_black_box black_box_pad_pin="clk,resend,config_finished,sioc,siod,reset,pwdn,xclk" */;
input clk;
input resend;
output config_finished;
output sioc;
inout siod;
output reset;
output pwdn;
output xclk;
endmodule
|
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Mon Nov 5 13:20:16 EST 2012
//
//
// Ports:
// Name I/O size props
// RDY_server_request_put O 1 reg
// server_response_get O 40
// RDY_server_response_get O 1 reg
// client_request_get O 59 reg
// RDY_client_request_get O 1 reg
// RDY_client_response_put O 1 reg
// RDY_macAddr O 1 const
// ecpRx O 1 reg
// RDY_ecpRx O 1 const
// ecpTx O 1 reg
// RDY_ecpTx O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// server_request_put I 40
// client_response_put I 40 reg
// macAddr_u I 48 reg
// EN_server_request_put I 1
// EN_client_response_put I 1
// EN_macAddr I 1
// EN_server_response_get I 1
// EN_client_request_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkEDCPAdapter(CLK,
RST_N,
server_request_put,
EN_server_request_put,
RDY_server_request_put,
EN_server_response_get,
server_response_get,
RDY_server_response_get,
EN_client_request_get,
client_request_get,
RDY_client_request_get,
client_response_put,
EN_client_response_put,
RDY_client_response_put,
macAddr_u,
EN_macAddr,
RDY_macAddr,
ecpRx,
RDY_ecpRx,
ecpTx,
RDY_ecpTx);
input CLK;
input RST_N;
// action method server_request_put
input [39 : 0] server_request_put;
input EN_server_request_put;
output RDY_server_request_put;
// actionvalue method server_response_get
input EN_server_response_get;
output [39 : 0] server_response_get;
output RDY_server_response_get;
// actionvalue method client_request_get
input EN_client_request_get;
output [58 : 0] client_request_get;
output RDY_client_request_get;
// action method client_response_put
input [39 : 0] client_response_put;
input EN_client_response_put;
output RDY_client_response_put;
// action method macAddr
input [47 : 0] macAddr_u;
input EN_macAddr;
output RDY_macAddr;
// value method ecpRx
output ecpRx;
output RDY_ecpRx;
// value method ecpTx
output ecpTx;
output RDY_ecpTx;
// signals for module outputs
wire [58 : 0] client_request_get;
wire [39 : 0] server_response_get;
wire RDY_client_request_get,
RDY_client_response_put,
RDY_ecpRx,
RDY_ecpTx,
RDY_macAddr,
RDY_server_request_put,
RDY_server_response_get,
ecpRx,
ecpTx;
// inlined wires
wire eDoReq_1$wget,
eDoReq_1$whas,
ecpEgress_1$wget,
ecpEgress_1$whas,
ecpIngress_1$wget,
ecpIngress_1$whas,
edpFsm_abort$wget,
edpFsm_abort$whas,
edpFsm_start_reg_1_1$wget,
edpFsm_start_reg_1_1$whas,
edpFsm_start_wire$wget,
edpFsm_start_wire$whas,
edpFsm_state_fired_1$wget,
edpFsm_state_fired_1$whas,
edpFsm_state_overlap_pw$whas,
edpFsm_state_set_pw$whas;
// register doInFlight
reg doInFlight;
wire doInFlight$D_IN, doInFlight$EN;
// register eAddr
reg [31 : 0] eAddr;
wire [31 : 0] eAddr$D_IN;
wire eAddr$EN;
// register eDAddr
reg [47 : 0] eDAddr;
wire [47 : 0] eDAddr$D_IN;
wire eDAddr$EN;
// register eDMH
reg [31 : 0] eDMH;
wire [31 : 0] eDMH$D_IN;
wire eDMH$EN;
// register eData
reg [31 : 0] eData;
wire [31 : 0] eData$D_IN;
wire eData$EN;
// register eDoReq
reg eDoReq;
wire eDoReq$D_IN, eDoReq$EN;
// register eMAddr
reg [47 : 0] eMAddr;
wire [47 : 0] eMAddr$D_IN;
wire eMAddr$EN;
// register ePli
reg [15 : 0] ePli;
wire [15 : 0] ePli$D_IN;
wire ePli$EN;
// register eTyp
reg [15 : 0] eTyp;
wire [15 : 0] eTyp$D_IN;
wire eTyp$EN;
// register ecpEgress
reg ecpEgress;
wire ecpEgress$D_IN, ecpEgress$EN;
// register ecpIngress
reg ecpIngress;
wire ecpIngress$D_IN, ecpIngress$EN;
// register edpFsm_start_reg
reg edpFsm_start_reg;
wire edpFsm_start_reg$D_IN, edpFsm_start_reg$EN;
// register edpFsm_start_reg_1
reg edpFsm_start_reg_1;
wire edpFsm_start_reg_1$D_IN, edpFsm_start_reg_1$EN;
// register edpFsm_state_can_overlap
reg edpFsm_state_can_overlap;
wire edpFsm_state_can_overlap$D_IN, edpFsm_state_can_overlap$EN;
// register edpFsm_state_fired
reg edpFsm_state_fired;
wire edpFsm_state_fired$D_IN, edpFsm_state_fired$EN;
// register edpFsm_state_mkFSMstate
reg [3 : 0] edpFsm_state_mkFSMstate;
reg [3 : 0] edpFsm_state_mkFSMstate$D_IN;
wire edpFsm_state_mkFSMstate$EN;
// register eeDat
reg [31 : 0] eeDat;
wire [31 : 0] eeDat$D_IN;
wire eeDat$EN;
// register eeDmh
reg [31 : 0] eeDmh;
wire [31 : 0] eeDmh$D_IN;
wire eeDmh$EN;
// register eeMDst
reg [47 : 0] eeMDst;
wire [47 : 0] eeMDst$D_IN;
wire eeMDst$EN;
// register eePli
reg [15 : 0] eePli;
reg [15 : 0] eePli$D_IN;
wire eePli$EN;
// register isWrtResp
reg isWrtResp;
wire isWrtResp$D_IN, isWrtResp$EN;
// register lastResp
reg [44 : 0] lastResp;
wire [44 : 0] lastResp$D_IN;
wire lastResp$EN;
// register lastTag
reg [8 : 0] lastTag;
wire [8 : 0] lastTag$D_IN;
wire lastTag$EN;
// register ptr
reg [3 : 0] ptr;
wire [3 : 0] ptr$D_IN;
wire ptr$EN;
// register uMAddr
reg [47 : 0] uMAddr;
wire [47 : 0] uMAddr$D_IN;
wire uMAddr$EN;
// ports of submodule cpReqF
wire [58 : 0] cpReqF$D_IN, cpReqF$D_OUT;
wire cpReqF$CLR, cpReqF$DEQ, cpReqF$EMPTY_N, cpReqF$ENQ, cpReqF$FULL_N;
// ports of submodule cpRespF
wire [39 : 0] cpRespF$D_IN, cpRespF$D_OUT;
wire cpRespF$CLR, cpRespF$DEQ, cpRespF$EMPTY_N, cpRespF$ENQ, cpRespF$FULL_N;
// ports of submodule dcpReqF
reg [78 : 0] dcpReqF$D_IN;
wire [78 : 0] dcpReqF$D_OUT;
wire dcpReqF$CLR, dcpReqF$DEQ, dcpReqF$EMPTY_N, dcpReqF$ENQ, dcpReqF$FULL_N;
// ports of submodule dcpRespF
wire [44 : 0] dcpRespF$D_IN, dcpRespF$D_OUT;
wire dcpRespF$CLR,
dcpRespF$DEQ,
dcpRespF$EMPTY_N,
dcpRespF$ENQ,
dcpRespF$FULL_N;
// ports of submodule eMAddrF
wire [47 : 0] eMAddrF$D_IN, eMAddrF$D_OUT;
wire eMAddrF$CLR, eMAddrF$DEQ, eMAddrF$EMPTY_N, eMAddrF$ENQ, eMAddrF$FULL_N;
// ports of submodule ecpReqF
wire [39 : 0] ecpReqF$D_IN, ecpReqF$D_OUT;
wire ecpReqF$CLR, ecpReqF$DEQ, ecpReqF$EMPTY_N, ecpReqF$ENQ, ecpReqF$FULL_N;
// ports of submodule ecpRespF
reg [39 : 0] ecpRespF$D_IN;
wire [39 : 0] ecpRespF$D_OUT;
wire ecpRespF$CLR,
ecpRespF$DEQ,
ecpRespF$EMPTY_N,
ecpRespF$ENQ,
ecpRespF$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_cp_to_dcp_response,
WILL_FIRE_RL_dcp_to_cp_request,
WILL_FIRE_RL_ecp_ingress,
WILL_FIRE_RL_edpFsm_action_l243c16,
WILL_FIRE_RL_edpFsm_action_l244c16,
WILL_FIRE_RL_edpFsm_fsm_start,
WILL_FIRE_RL_edpFsm_idle_l235c3,
WILL_FIRE_RL_edpFsm_idle_l235c3_1;
// inputs to muxes for submodule ports
reg [44 : 0] MUX_dcpRespF$enq_1__VAL_1;
wire [44 : 0] MUX_dcpRespF$enq_1__VAL_2;
wire [39 : 0] MUX_ecpRespF$enq_1__VAL_1,
MUX_ecpRespF$enq_1__VAL_2,
MUX_ecpRespF$enq_1__VAL_3,
MUX_ecpRespF$enq_1__VAL_4,
MUX_ecpRespF$enq_1__VAL_5,
MUX_ecpRespF$enq_1__VAL_6,
MUX_ecpRespF$enq_1__VAL_7;
wire MUX_dcpRespF$enq_1__SEL_1,
MUX_doInFlight$write_1__SEL_1,
MUX_edpFsm_start_reg$write_1__SEL_2,
MUX_edpFsm_state_mkFSMstate$write_1__SEL_1,
MUX_edpFsm_state_mkFSMstate$write_1__SEL_2,
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3,
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4,
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5,
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6;
// remaining internal signals
reg [7 : 0] CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10;
reg [1 : 0] CASE_ecpRespFD_OUT_BITS_19_TO_18_3_0_ecpRespF_ETC__q3,
CASE_ecpRespFD_OUT_BITS_29_TO_28_3_0_ecpRespF_ETC__q2,
CASE_ecpRespFD_OUT_BITS_39_TO_38_3_0_ecpRespF_ETC__q1,
CASE_ecpRespFD_OUT_BITS_9_TO_8_3_0_ecpRespFD_ETC__q4,
CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q8,
CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q7,
CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q6,
CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q9;
reg CASE_eDMH_BITS_13_TO_12_NOT_eDMH_BITS_13_TO_12_ETC__q5;
wire [47 : 0] x__h3828, x__h5559, x__h5600, x__h5655, y__h5621, y__h5666;
wire [31 : 0] bedw__h2322;
wire [15 : 0] x__h5688, x__h5756;
wire [7 : 0] IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465;
wire [3 : 0] x__h2347;
wire IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21__ETC___d152,
IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23__ETC___d150,
dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463,
dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464,
dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21_OR__ETC___d155,
dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23_AND_ETC___d196,
eMAddrF_i_notFull__9_AND_IF_eDMH_0_BITS_13_TO__ETC___d100,
edpFsm_abort_whas__19_AND_edpFsm_abort_wget__2_ETC___d253;
// action method server_request_put
assign RDY_server_request_put = ecpReqF$FULL_N ;
// actionvalue method server_response_get
assign server_response_get =
{ CASE_ecpRespFD_OUT_BITS_39_TO_38_3_0_ecpRespF_ETC__q1,
ecpRespF$D_OUT[37:30],
CASE_ecpRespFD_OUT_BITS_29_TO_28_3_0_ecpRespF_ETC__q2,
ecpRespF$D_OUT[27:20],
CASE_ecpRespFD_OUT_BITS_19_TO_18_3_0_ecpRespF_ETC__q3,
ecpRespF$D_OUT[17:10],
CASE_ecpRespFD_OUT_BITS_9_TO_8_3_0_ecpRespFD_ETC__q4,
ecpRespF$D_OUT[7:0] } ;
assign RDY_server_response_get = ecpRespF$EMPTY_N ;
// actionvalue method client_request_get
assign client_request_get = cpReqF$D_OUT ;
assign RDY_client_request_get = cpReqF$EMPTY_N ;
// action method client_response_put
assign RDY_client_response_put = cpRespF$FULL_N ;
// action method macAddr
assign RDY_macAddr = 1'd1 ;
// value method ecpRx
assign ecpRx = ecpIngress ;
assign RDY_ecpRx = 1'd1 ;
// value method ecpTx
assign ecpTx = ecpEgress ;
assign RDY_ecpTx = 1'd1 ;
// submodule cpReqF
FIFO2 #(.width(32'd59), .guarded(32'd1)) cpReqF(.RST(RST_N),
.CLK(CLK),
.D_IN(cpReqF$D_IN),
.ENQ(cpReqF$ENQ),
.DEQ(cpReqF$DEQ),
.CLR(cpReqF$CLR),
.D_OUT(cpReqF$D_OUT),
.FULL_N(cpReqF$FULL_N),
.EMPTY_N(cpReqF$EMPTY_N));
// submodule cpRespF
FIFO2 #(.width(32'd40), .guarded(32'd1)) cpRespF(.RST(RST_N),
.CLK(CLK),
.D_IN(cpRespF$D_IN),
.ENQ(cpRespF$ENQ),
.DEQ(cpRespF$DEQ),
.CLR(cpRespF$CLR),
.D_OUT(cpRespF$D_OUT),
.FULL_N(cpRespF$FULL_N),
.EMPTY_N(cpRespF$EMPTY_N));
// submodule dcpReqF
FIFO2 #(.width(32'd79), .guarded(32'd1)) dcpReqF(.RST(RST_N),
.CLK(CLK),
.D_IN(dcpReqF$D_IN),
.ENQ(dcpReqF$ENQ),
.DEQ(dcpReqF$DEQ),
.CLR(dcpReqF$CLR),
.D_OUT(dcpReqF$D_OUT),
.FULL_N(dcpReqF$FULL_N),
.EMPTY_N(dcpReqF$EMPTY_N));
// submodule dcpRespF
FIFO2 #(.width(32'd45), .guarded(32'd1)) dcpRespF(.RST(RST_N),
.CLK(CLK),
.D_IN(dcpRespF$D_IN),
.ENQ(dcpRespF$ENQ),
.DEQ(dcpRespF$DEQ),
.CLR(dcpRespF$CLR),
.D_OUT(dcpRespF$D_OUT),
.FULL_N(dcpRespF$FULL_N),
.EMPTY_N(dcpRespF$EMPTY_N));
// submodule eMAddrF
FIFO2 #(.width(32'd48), .guarded(32'd1)) eMAddrF(.RST(RST_N),
.CLK(CLK),
.D_IN(eMAddrF$D_IN),
.ENQ(eMAddrF$ENQ),
.DEQ(eMAddrF$DEQ),
.CLR(eMAddrF$CLR),
.D_OUT(eMAddrF$D_OUT),
.FULL_N(eMAddrF$FULL_N),
.EMPTY_N(eMAddrF$EMPTY_N));
// submodule ecpReqF
FIFO2 #(.width(32'd40), .guarded(32'd1)) ecpReqF(.RST(RST_N),
.CLK(CLK),
.D_IN(ecpReqF$D_IN),
.ENQ(ecpReqF$ENQ),
.DEQ(ecpReqF$DEQ),
.CLR(ecpReqF$CLR),
.D_OUT(ecpReqF$D_OUT),
.FULL_N(ecpReqF$FULL_N),
.EMPTY_N(ecpReqF$EMPTY_N));
// submodule ecpRespF
FIFO2 #(.width(32'd40), .guarded(32'd1)) ecpRespF(.RST(RST_N),
.CLK(CLK),
.D_IN(ecpRespF$D_IN),
.ENQ(ecpRespF$ENQ),
.DEQ(ecpRespF$DEQ),
.CLR(ecpRespF$CLR),
.D_OUT(ecpRespF$D_OUT),
.FULL_N(ecpRespF$FULL_N),
.EMPTY_N(ecpRespF$EMPTY_N));
// rule RL_ecp_ingress
assign WILL_FIRE_RL_ecp_ingress = ecpReqF$EMPTY_N && !eDoReq ;
// rule RL_dcp_to_cp_request
assign WILL_FIRE_RL_dcp_to_cp_request =
dcpReqF$EMPTY_N &&
IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21__ETC___d152 ;
// rule RL_cp_to_dcp_response
assign WILL_FIRE_RL_cp_to_dcp_response =
dcpRespF$FULL_N && cpRespF$EMPTY_N &&
!WILL_FIRE_RL_dcp_to_cp_request ;
// rule RL_edpFsm_action_l243c16
assign WILL_FIRE_RL_edpFsm_action_l243c16 =
ecpRespF$FULL_N && !isWrtResp &&
edpFsm_state_mkFSMstate == 4'd4 ;
// rule RL_edpFsm_action_l244c16
assign WILL_FIRE_RL_edpFsm_action_l244c16 =
ecpRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd6 ;
// rule RL_edpFsm_fsm_start
assign WILL_FIRE_RL_edpFsm_fsm_start =
edpFsm_abort_whas__19_AND_edpFsm_abort_wget__2_ETC___d253 &&
(!edpFsm_start_reg_1 || edpFsm_state_fired) &&
edpFsm_start_reg ;
// rule RL_edpFsm_idle_l235c3
assign WILL_FIRE_RL_edpFsm_idle_l235c3 =
!edpFsm_start_wire$whas && edpFsm_state_mkFSMstate == 4'd5 ;
// rule RL_edpFsm_idle_l235c3_1
assign WILL_FIRE_RL_edpFsm_idle_l235c3_1 =
!edpFsm_start_wire$whas && edpFsm_state_mkFSMstate == 4'd7 ;
// inputs to muxes for submodule ports
assign MUX_dcpRespF$enq_1__SEL_1 =
WILL_FIRE_RL_dcp_to_cp_request &&
dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21_OR__ETC___d155 ;
assign MUX_doInFlight$write_1__SEL_1 =
WILL_FIRE_RL_dcp_to_cp_request &&
(dcpReqF$D_OUT[78:77] == 2'd0 && dcpReqF$D_OUT[40] ||
dcpReqF$D_OUT[78:77] != 2'd0 &&
(dcpReqF$D_OUT[78:77] == 2'd1 && dcpReqF$D_OUT[76] ||
dcpReqF$D_OUT[78:77] != 2'd1 && dcpReqF$D_OUT[44])) ;
assign MUX_edpFsm_start_reg$write_1__SEL_2 =
edpFsm_abort_whas__19_AND_edpFsm_abort_wget__2_ETC___d253 &&
(!edpFsm_start_reg_1 || edpFsm_state_fired) &&
!edpFsm_start_reg &&
eMAddrF$EMPTY_N &&
dcpRespF$EMPTY_N ;
assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_1 =
WILL_FIRE_RL_edpFsm_idle_l235c3_1 ||
WILL_FIRE_RL_edpFsm_idle_l235c3 ;
assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 =
ecpRespF$FULL_N && edpFsm_start_wire$whas &&
edpFsm_abort_whas__19_AND_edpFsm_abort_wget__2_ETC___d253 ;
assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 =
ecpRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd1 ;
assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 =
ecpRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd2 ;
assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 =
ecpRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd3 ;
assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 =
ecpRespF$FULL_N && isWrtResp && edpFsm_state_mkFSMstate == 4'd4 ;
always@(dcpReqF$D_OUT or lastResp)
begin
case (dcpReqF$D_OUT[78:77])
2'd0:
MUX_dcpRespF$enq_1__VAL_1 =
{ 2'd0,
dcpReqF$D_OUT[40],
32'h40000001,
dcpReqF$D_OUT[39:32],
2'd0 };
2'd1:
MUX_dcpRespF$enq_1__VAL_1 =
{ dcpReqF$D_OUT[78:77],
32'hAAAAAAAA,
dcpReqF$D_OUT[76],
dcpReqF$D_OUT[71:64],
2'd0 };
default: MUX_dcpRespF$enq_1__VAL_1 =
{ (lastResp[44:43] == 2'd0 || lastResp[44:43] == 2'd1) ?
lastResp[44:43] :
2'd2,
lastResp[42:0] };
endcase
end
assign MUX_dcpRespF$enq_1__VAL_2 =
{ 2'd2,
doInFlight,
cpRespF$D_OUT[31:0],
cpRespF$D_OUT[39:32],
2'd0 } ;
assign MUX_ecpRespF$enq_1__VAL_1 =
{ 2'd0,
eeMDst[23:16],
2'd0,
eeMDst[31:24],
2'd0,
eeMDst[39:32],
2'd0,
eeMDst[47:40] } ;
assign MUX_ecpRespF$enq_1__VAL_2 =
{ 2'd0,
uMAddr[39:32],
2'd0,
uMAddr[47:40],
2'd0,
eeMDst[7:0],
2'd0,
eeMDst[15:8] } ;
assign MUX_ecpRespF$enq_1__VAL_3 =
{ 2'd0,
uMAddr[7:0],
2'd0,
uMAddr[15:8],
2'd0,
uMAddr[23:16],
2'd0,
uMAddr[31:24] } ;
assign MUX_ecpRespF$enq_1__VAL_4 =
{ 2'd0, eePli[7:0], 2'd0, eePli[15:8], 20'd65776 } ;
assign MUX_ecpRespF$enq_1__VAL_5 =
{ 2'd1,
eeDmh[31:24],
2'd0,
eeDmh[23:16],
2'd0,
eeDmh[15:8],
2'd0,
eeDmh[7:0] } ;
assign MUX_ecpRespF$enq_1__VAL_6 =
{ 2'd0,
eeDmh[31:24],
2'd0,
eeDmh[23:16],
2'd0,
eeDmh[15:8],
2'd0,
eeDmh[7:0] } ;
assign MUX_ecpRespF$enq_1__VAL_7 =
{ 2'd1,
eeDat[7:0],
2'd0,
eeDat[15:8],
2'd0,
eeDat[23:16],
2'd0,
eeDat[31:24] } ;
// inlined wires
assign eDoReq_1$wget =
(eDAddr == 48'hFFFFFFFFFFFF || eDAddr == uMAddr) &&
eTyp == 16'hF040 &&
(ePli == 16'd10 && ptr == 4'd5 ||
ePli == 16'd14 && ptr == 4'd6) ;
assign eDoReq_1$whas = WILL_FIRE_RL_ecp_ingress ;
assign ecpIngress_1$wget = 1'd1 ;
assign ecpIngress_1$whas = WILL_FIRE_RL_ecp_ingress ;
assign ecpEgress_1$wget =
edpFsm_state_mkFSMstate != 4'd0 &&
edpFsm_state_mkFSMstate != 4'd5 &&
edpFsm_state_mkFSMstate != 4'd7 ||
edpFsm_start_reg_1 && !edpFsm_state_fired ||
edpFsm_start_reg ;
assign ecpEgress_1$whas = 1'd1 ;
assign edpFsm_start_wire$wget = 1'd1 ;
assign edpFsm_start_wire$whas =
WILL_FIRE_RL_edpFsm_fsm_start ||
edpFsm_start_reg_1 && !edpFsm_state_fired ;
assign edpFsm_start_reg_1_1$wget = 1'd1 ;
assign edpFsm_start_reg_1_1$whas = edpFsm_start_wire$whas ;
assign edpFsm_abort$wget = 1'b0 ;
assign edpFsm_abort$whas = 1'b0 ;
assign edpFsm_state_fired_1$wget = 1'd1 ;
assign edpFsm_state_fired_1$whas = edpFsm_state_set_pw$whas ;
assign edpFsm_state_set_pw$whas =
WILL_FIRE_RL_edpFsm_idle_l235c3_1 ||
WILL_FIRE_RL_edpFsm_idle_l235c3 ||
WILL_FIRE_RL_edpFsm_action_l244c16 ||
WILL_FIRE_RL_edpFsm_action_l243c16 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 ;
assign edpFsm_state_overlap_pw$whas = 1'b0 ;
// register doInFlight
assign doInFlight$D_IN = MUX_doInFlight$write_1__SEL_1 ;
assign doInFlight$EN =
WILL_FIRE_RL_dcp_to_cp_request &&
(dcpReqF$D_OUT[78:77] == 2'd0 && dcpReqF$D_OUT[40] ||
dcpReqF$D_OUT[78:77] != 2'd0 &&
(dcpReqF$D_OUT[78:77] == 2'd1 && dcpReqF$D_OUT[76] ||
dcpReqF$D_OUT[78:77] != 2'd1 && dcpReqF$D_OUT[44])) ||
WILL_FIRE_RL_cp_to_dcp_response ;
// register eAddr
assign eAddr$D_IN = bedw__h2322 ;
assign eAddr$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd5 ;
// register eDAddr
assign eDAddr$D_IN = (ptr == 4'd0) ? x__h3828 : x__h5600 ;
assign eDAddr$EN =
WILL_FIRE_RL_ecp_ingress && (ptr == 4'd0 || ptr == 4'd1) ;
// register eDMH
assign eDMH$D_IN = bedw__h2322 ;
assign eDMH$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd4 ;
// register eData
assign eData$D_IN = bedw__h2322 ;
assign eData$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd6 ;
// register eDoReq
assign eDoReq$D_IN = WILL_FIRE_RL_ecp_ingress && eDoReq_1$wget ;
assign eDoReq$EN = 1'd1 ;
// register eMAddr
assign eMAddr$D_IN = (ptr == 4'd1) ? x__h5559 : x__h5655 ;
assign eMAddr$EN =
WILL_FIRE_RL_ecp_ingress && (ptr == 4'd1 || ptr == 4'd2) ;
// register ePli
assign ePli$D_IN = x__h5756 ;
assign ePli$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd3 ;
// register eTyp
assign eTyp$D_IN = x__h5688 ;
assign eTyp$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd3 ;
// register ecpEgress
assign ecpEgress$D_IN = ecpEgress_1$wget ;
assign ecpEgress$EN = 1'd1 ;
// register ecpIngress
assign ecpIngress$D_IN = WILL_FIRE_RL_ecp_ingress ;
assign ecpIngress$EN = 1'd1 ;
// register edpFsm_start_reg
assign edpFsm_start_reg$D_IN = !WILL_FIRE_RL_edpFsm_fsm_start ;
assign edpFsm_start_reg$EN =
WILL_FIRE_RL_edpFsm_fsm_start ||
MUX_edpFsm_start_reg$write_1__SEL_2 ;
// register edpFsm_start_reg_1
assign edpFsm_start_reg_1$D_IN = edpFsm_start_wire$whas ;
assign edpFsm_start_reg_1$EN = 1'd1 ;
// register edpFsm_state_can_overlap
assign edpFsm_state_can_overlap$D_IN =
edpFsm_state_set_pw$whas || edpFsm_state_can_overlap ;
assign edpFsm_state_can_overlap$EN = 1'd1 ;
// register edpFsm_state_fired
assign edpFsm_state_fired$D_IN = edpFsm_state_set_pw$whas ;
assign edpFsm_state_fired$EN = 1'd1 ;
// register edpFsm_state_mkFSMstate
always@(MUX_edpFsm_state_mkFSMstate$write_1__SEL_1 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 or
WILL_FIRE_RL_edpFsm_action_l243c16 or
WILL_FIRE_RL_edpFsm_action_l244c16)
begin
case (1'b1) // synopsys parallel_case
MUX_edpFsm_state_mkFSMstate$write_1__SEL_1:
edpFsm_state_mkFSMstate$D_IN = 4'd0;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_2:
edpFsm_state_mkFSMstate$D_IN = 4'd1;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3:
edpFsm_state_mkFSMstate$D_IN = 4'd2;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4:
edpFsm_state_mkFSMstate$D_IN = 4'd3;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5:
edpFsm_state_mkFSMstate$D_IN = 4'd4;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6:
edpFsm_state_mkFSMstate$D_IN = 4'd5;
WILL_FIRE_RL_edpFsm_action_l243c16: edpFsm_state_mkFSMstate$D_IN = 4'd6;
WILL_FIRE_RL_edpFsm_action_l244c16: edpFsm_state_mkFSMstate$D_IN = 4'd7;
default: edpFsm_state_mkFSMstate$D_IN =
4'b1010 /* unspecified value */ ;
endcase
end
assign edpFsm_state_mkFSMstate$EN =
WILL_FIRE_RL_edpFsm_idle_l235c3_1 ||
WILL_FIRE_RL_edpFsm_idle_l235c3 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 ||
WILL_FIRE_RL_edpFsm_action_l243c16 ||
WILL_FIRE_RL_edpFsm_action_l244c16 ;
// register eeDat
assign eeDat$D_IN = dcpRespF$D_OUT[41:10] ;
assign eeDat$EN =
MUX_edpFsm_start_reg$write_1__SEL_2 &&
dcpRespF$D_OUT[44:43] != 2'd1 ;
// register eeDmh
assign eeDmh$D_IN =
{ dcpRespF$D_OUT[9:2],
CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10,
16'h0 } ;
assign eeDmh$EN = MUX_edpFsm_start_reg$write_1__SEL_2 ;
// register eeMDst
assign eeMDst$D_IN = eMAddrF$D_OUT ;
assign eeMDst$EN = MUX_edpFsm_start_reg$write_1__SEL_2 ;
// register eePli
always@(dcpRespF$D_OUT)
begin
case (dcpRespF$D_OUT[44:43])
2'd0: eePli$D_IN = 16'd10;
2'd1: eePli$D_IN = 16'd6;
default: eePli$D_IN = 16'd10;
endcase
end
assign eePli$EN = MUX_edpFsm_start_reg$write_1__SEL_2 ;
// register isWrtResp
assign isWrtResp$D_IN = dcpRespF$D_OUT[44:43] == 2'd1 ;
assign isWrtResp$EN = MUX_edpFsm_start_reg$write_1__SEL_2 ;
// register lastResp
assign lastResp$D_IN = MUX_dcpRespF$enq_1__VAL_2 ;
assign lastResp$EN = WILL_FIRE_RL_cp_to_dcp_response && !doInFlight ;
// register lastTag
assign lastTag$D_IN =
{ dcpReqF$D_OUT[78:77] != 2'd0,
(dcpReqF$D_OUT[78:77] == 2'd1) ?
dcpReqF$D_OUT[71:64] :
dcpReqF$D_OUT[39:32] } ;
assign lastTag$EN =
WILL_FIRE_RL_dcp_to_cp_request &&
(dcpReqF$D_OUT[78:77] == 2'd0 && !dcpReqF$D_OUT[40] ||
dcpReqF$D_OUT[78:77] != 2'd0 &&
(dcpReqF$D_OUT[78:77] == 2'd1 &&
(!dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464 ||
!lastTag[8]) &&
!dcpReqF$D_OUT[76] ||
dcpReqF$D_OUT[78:77] != 2'd1 &&
(!dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 ||
!lastTag[8]) &&
!dcpReqF$D_OUT[44])) ;
// register ptr
assign ptr$D_IN =
(x__h2347 == 4'd0) ? ((ptr == 4'd15) ? ptr : ptr + 4'd1) : 4'd0 ;
assign ptr$EN = WILL_FIRE_RL_ecp_ingress ;
// register uMAddr
assign uMAddr$D_IN = macAddr_u ;
assign uMAddr$EN = EN_macAddr ;
// submodule cpReqF
assign cpReqF$D_IN =
{ dcpReqF$D_OUT[78:77] != 2'd1,
(dcpReqF$D_OUT[78:77] == 2'd1) ?
{ dcpReqF$D_OUT[23:2],
dcpReqF$D_OUT[75:72],
dcpReqF$D_OUT[63:32] } :
{ 24'hAAAAAA,
dcpReqF$D_OUT[39:32],
dcpReqF$D_OUT[23:2],
dcpReqF$D_OUT[43:40] } } ;
assign cpReqF$ENQ =
WILL_FIRE_RL_dcp_to_cp_request && dcpReqF$D_OUT[78:77] != 2'd0 &&
dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23_AND_ETC___d196 ;
assign cpReqF$DEQ = EN_client_request_get ;
assign cpReqF$CLR = 1'b0 ;
// submodule cpRespF
assign cpRespF$D_IN = client_response_put ;
assign cpRespF$ENQ = EN_client_response_put ;
assign cpRespF$DEQ = WILL_FIRE_RL_cp_to_dcp_response ;
assign cpRespF$CLR = 1'b0 ;
// submodule dcpReqF
always@(eDMH or eAddr or eData)
begin
case (eDMH[13:12])
2'd0: dcpReqF$D_IN = { 38'h0AAAAAAAAA, eDMH[14], eDMH[7:0], eAddr };
2'd1:
dcpReqF$D_IN = { eDMH[13:12], eDMH[14], eDMH[11:0], eData, eAddr };
default: dcpReqF$D_IN = { 34'h2AAAAAAAA, eDMH[14], eDMH[11:0], eAddr };
endcase
end
assign dcpReqF$ENQ =
eMAddrF_i_notFull__9_AND_IF_eDMH_0_BITS_13_TO__ETC___d100 &&
eDoReq &&
(eDMH[13:12] == 2'd0 || eDMH[13:12] == 2'd1 ||
eDMH[13:12] == 2'd2) ;
assign dcpReqF$DEQ = WILL_FIRE_RL_dcp_to_cp_request ;
assign dcpReqF$CLR = 1'b0 ;
// submodule dcpRespF
assign dcpRespF$D_IN =
MUX_dcpRespF$enq_1__SEL_1 ?
MUX_dcpRespF$enq_1__VAL_1 :
MUX_dcpRespF$enq_1__VAL_2 ;
assign dcpRespF$ENQ =
WILL_FIRE_RL_dcp_to_cp_request &&
dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21_OR__ETC___d155 ||
WILL_FIRE_RL_cp_to_dcp_response ;
assign dcpRespF$DEQ = MUX_edpFsm_start_reg$write_1__SEL_2 ;
assign dcpRespF$CLR = 1'b0 ;
// submodule eMAddrF
assign eMAddrF$D_IN = eMAddr ;
assign eMAddrF$ENQ =
eMAddrF_i_notFull__9_AND_IF_eDMH_0_BITS_13_TO__ETC___d100 &&
eDoReq ;
assign eMAddrF$DEQ = MUX_edpFsm_start_reg$write_1__SEL_2 ;
assign eMAddrF$CLR = 1'b0 ;
// submodule ecpReqF
assign ecpReqF$D_IN =
{ CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q6,
server_request_put[37:30],
CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q7,
server_request_put[27:20],
CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q8,
server_request_put[17:10],
CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q9,
server_request_put[7:0] } ;
assign ecpReqF$ENQ = EN_server_request_put ;
assign ecpReqF$DEQ = WILL_FIRE_RL_ecp_ingress ;
assign ecpReqF$CLR = 1'b0 ;
// submodule ecpRespF
always@(MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 or
MUX_ecpRespF$enq_1__VAL_1 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 or
MUX_ecpRespF$enq_1__VAL_2 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 or
MUX_ecpRespF$enq_1__VAL_3 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 or
MUX_ecpRespF$enq_1__VAL_4 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 or
MUX_ecpRespF$enq_1__VAL_5 or
WILL_FIRE_RL_edpFsm_action_l243c16 or
MUX_ecpRespF$enq_1__VAL_6 or
WILL_FIRE_RL_edpFsm_action_l244c16 or MUX_ecpRespF$enq_1__VAL_7)
begin
case (1'b1) // synopsys parallel_case
MUX_edpFsm_state_mkFSMstate$write_1__SEL_2:
ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_1;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3:
ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_2;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4:
ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_3;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5:
ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_4;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6:
ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_5;
WILL_FIRE_RL_edpFsm_action_l243c16:
ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_6;
WILL_FIRE_RL_edpFsm_action_l244c16:
ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_7;
default: ecpRespF$D_IN = 40'hAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign ecpRespF$ENQ =
MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 ||
WILL_FIRE_RL_edpFsm_action_l243c16 ||
WILL_FIRE_RL_edpFsm_action_l244c16 ;
assign ecpRespF$DEQ = EN_server_response_get ;
assign ecpRespF$CLR = 1'b0 ;
// remaining internal signals
assign IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21__ETC___d152 =
(dcpReqF$D_OUT[78:77] == 2'd0) ?
dcpRespF$FULL_N :
(dcpReqF$D_OUT[78:77] == 2'd1 ||
!dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 ||
!lastTag[8] ||
dcpReqF$D_OUT[44] ||
dcpRespF$FULL_N) &&
IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23__ETC___d150 ;
assign IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23__ETC___d150 =
(dcpReqF$D_OUT[78:77] == 2'd1) ?
dcpRespF$FULL_N &&
(dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464 &&
lastTag[8] &&
!dcpReqF$D_OUT[76] ||
cpReqF$FULL_N) :
dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 &&
lastTag[8] &&
!dcpReqF$D_OUT[44] ||
cpReqF$FULL_N ;
assign IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465 =
dcpRespF$D_OUT[42] ? 8'h70 : 8'h30 ;
assign bedw__h2322 =
{ x__h5688, ecpReqF$D_OUT[27:20], ecpReqF$D_OUT[37:30] } ;
assign dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 =
dcpReqF$D_OUT[39:32] == lastTag[7:0] ;
assign dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464 =
dcpReqF$D_OUT[71:64] == lastTag[7:0] ;
assign dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21_OR__ETC___d155 =
dcpReqF$D_OUT[78:77] == 2'd0 || dcpReqF$D_OUT[78:77] == 2'd1 ||
dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 &&
lastTag[8] &&
!dcpReqF$D_OUT[44] ;
assign dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23_AND_ETC___d196 =
dcpReqF$D_OUT[78:77] == 2'd1 &&
(!dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464 ||
!lastTag[8] ||
dcpReqF$D_OUT[76]) ||
dcpReqF$D_OUT[78:77] != 2'd1 &&
(!dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 ||
!lastTag[8] ||
dcpReqF$D_OUT[44]) ;
assign eMAddrF_i_notFull__9_AND_IF_eDMH_0_BITS_13_TO__ETC___d100 =
eMAddrF$FULL_N &&
CASE_eDMH_BITS_13_TO_12_NOT_eDMH_BITS_13_TO_12_ETC__q5 ;
assign edpFsm_abort_whas__19_AND_edpFsm_abort_wget__2_ETC___d253 =
edpFsm_state_mkFSMstate == 4'd0 ||
edpFsm_state_mkFSMstate == 4'd5 ||
edpFsm_state_mkFSMstate == 4'd7 ;
assign x__h2347 =
{ ecpReqF$D_OUT[39:38] != 2'd0,
ecpReqF$D_OUT[29:28] != 2'd0,
ecpReqF$D_OUT[19:18] != 2'd0,
ecpReqF$D_OUT[9:8] != 2'd0 } ;
assign x__h3828 = { bedw__h2322, 16'h0 } ;
assign x__h5559 = { x__h5756, 32'h0 } ;
assign x__h5600 = eDAddr | y__h5621 ;
assign x__h5655 = eMAddr | y__h5666 ;
assign x__h5688 = { ecpReqF$D_OUT[7:0], ecpReqF$D_OUT[17:10] } ;
assign x__h5756 = { ecpReqF$D_OUT[27:20], ecpReqF$D_OUT[37:30] } ;
assign y__h5621 = { 32'h0, x__h5688 } ;
assign y__h5666 = { 16'd0, bedw__h2322 } ;
always@(ecpRespF$D_OUT)
begin
case (ecpRespF$D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_ecpRespFD_OUT_BITS_39_TO_38_3_0_ecpRespF_ETC__q1 =
ecpRespF$D_OUT[39:38];
2'd3: CASE_ecpRespFD_OUT_BITS_39_TO_38_3_0_ecpRespF_ETC__q1 = 2'd3;
endcase
end
always@(ecpRespF$D_OUT)
begin
case (ecpRespF$D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_ecpRespFD_OUT_BITS_29_TO_28_3_0_ecpRespF_ETC__q2 =
ecpRespF$D_OUT[29:28];
2'd3: CASE_ecpRespFD_OUT_BITS_29_TO_28_3_0_ecpRespF_ETC__q2 = 2'd3;
endcase
end
always@(ecpRespF$D_OUT)
begin
case (ecpRespF$D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_ecpRespFD_OUT_BITS_19_TO_18_3_0_ecpRespF_ETC__q3 =
ecpRespF$D_OUT[19:18];
2'd3: CASE_ecpRespFD_OUT_BITS_19_TO_18_3_0_ecpRespF_ETC__q3 = 2'd3;
endcase
end
always@(ecpRespF$D_OUT)
begin
case (ecpRespF$D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_ecpRespFD_OUT_BITS_9_TO_8_3_0_ecpRespFD_ETC__q4 =
ecpRespF$D_OUT[9:8];
2'd3: CASE_ecpRespFD_OUT_BITS_9_TO_8_3_0_ecpRespFD_ETC__q4 = 2'd3;
endcase
end
always@(eDMH or dcpReqF$FULL_N)
begin
case (eDMH[13:12])
2'd0, 2'd1:
CASE_eDMH_BITS_13_TO_12_NOT_eDMH_BITS_13_TO_12_ETC__q5 =
dcpReqF$FULL_N;
default: CASE_eDMH_BITS_13_TO_12_NOT_eDMH_BITS_13_TO_12_ETC__q5 =
eDMH[13:12] != 2'd2 || dcpReqF$FULL_N;
endcase
end
always@(server_request_put)
begin
case (server_request_put[39:38])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q6 =
server_request_put[39:38];
2'd3: CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q6 = 2'd3;
endcase
end
always@(server_request_put)
begin
case (server_request_put[29:28])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q7 =
server_request_put[29:28];
2'd3: CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q7 = 2'd3;
endcase
end
always@(server_request_put)
begin
case (server_request_put[19:18])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q8 =
server_request_put[19:18];
2'd3: CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q8 = 2'd3;
endcase
end
always@(server_request_put)
begin
case (server_request_put[9:8])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q9 =
server_request_put[9:8];
2'd3: CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q9 = 2'd3;
endcase
end
always@(dcpRespF$D_OUT or
IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465)
begin
case (dcpRespF$D_OUT[44:43])
2'd0:
CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10 =
IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465;
2'd1:
CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10 =
dcpRespF$D_OUT[10] ? 8'h70 : 8'h30;
default: CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10 =
IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
doInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
eDoReq <= `BSV_ASSIGNMENT_DELAY 1'd0;
ecpEgress <= `BSV_ASSIGNMENT_DELAY 1'd0;
ecpIngress <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY 1'd1;
edpFsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 4'd0;
lastTag <= `BSV_ASSIGNMENT_DELAY 9'd170;
ptr <= `BSV_ASSIGNMENT_DELAY 4'd0;
end
else
begin
if (doInFlight$EN)
doInFlight <= `BSV_ASSIGNMENT_DELAY doInFlight$D_IN;
if (eDoReq$EN) eDoReq <= `BSV_ASSIGNMENT_DELAY eDoReq$D_IN;
if (ecpEgress$EN) ecpEgress <= `BSV_ASSIGNMENT_DELAY ecpEgress$D_IN;
if (ecpIngress$EN)
ecpIngress <= `BSV_ASSIGNMENT_DELAY ecpIngress$D_IN;
if (edpFsm_start_reg$EN)
edpFsm_start_reg <= `BSV_ASSIGNMENT_DELAY edpFsm_start_reg$D_IN;
if (edpFsm_start_reg_1$EN)
edpFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY edpFsm_start_reg_1$D_IN;
if (edpFsm_state_can_overlap$EN)
edpFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY
edpFsm_state_can_overlap$D_IN;
if (edpFsm_state_fired$EN)
edpFsm_state_fired <= `BSV_ASSIGNMENT_DELAY edpFsm_state_fired$D_IN;
if (edpFsm_state_mkFSMstate$EN)
edpFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
edpFsm_state_mkFSMstate$D_IN;
if (lastTag$EN) lastTag <= `BSV_ASSIGNMENT_DELAY lastTag$D_IN;
if (ptr$EN) ptr <= `BSV_ASSIGNMENT_DELAY ptr$D_IN;
end
if (eAddr$EN) eAddr <= `BSV_ASSIGNMENT_DELAY eAddr$D_IN;
if (eDAddr$EN) eDAddr <= `BSV_ASSIGNMENT_DELAY eDAddr$D_IN;
if (eDMH$EN) eDMH <= `BSV_ASSIGNMENT_DELAY eDMH$D_IN;
if (eData$EN) eData <= `BSV_ASSIGNMENT_DELAY eData$D_IN;
if (eMAddr$EN) eMAddr <= `BSV_ASSIGNMENT_DELAY eMAddr$D_IN;
if (ePli$EN) ePli <= `BSV_ASSIGNMENT_DELAY ePli$D_IN;
if (eTyp$EN) eTyp <= `BSV_ASSIGNMENT_DELAY eTyp$D_IN;
if (eeDat$EN) eeDat <= `BSV_ASSIGNMENT_DELAY eeDat$D_IN;
if (eeDmh$EN) eeDmh <= `BSV_ASSIGNMENT_DELAY eeDmh$D_IN;
if (eeMDst$EN) eeMDst <= `BSV_ASSIGNMENT_DELAY eeMDst$D_IN;
if (eePli$EN) eePli <= `BSV_ASSIGNMENT_DELAY eePli$D_IN;
if (isWrtResp$EN) isWrtResp <= `BSV_ASSIGNMENT_DELAY isWrtResp$D_IN;
if (lastResp$EN) lastResp <= `BSV_ASSIGNMENT_DELAY lastResp$D_IN;
if (uMAddr$EN) uMAddr <= `BSV_ASSIGNMENT_DELAY uMAddr$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
doInFlight = 1'h0;
eAddr = 32'hAAAAAAAA;
eDAddr = 48'hAAAAAAAAAAAA;
eDMH = 32'hAAAAAAAA;
eData = 32'hAAAAAAAA;
eDoReq = 1'h0;
eMAddr = 48'hAAAAAAAAAAAA;
ePli = 16'hAAAA;
eTyp = 16'hAAAA;
ecpEgress = 1'h0;
ecpIngress = 1'h0;
edpFsm_start_reg = 1'h0;
edpFsm_start_reg_1 = 1'h0;
edpFsm_state_can_overlap = 1'h0;
edpFsm_state_fired = 1'h0;
edpFsm_state_mkFSMstate = 4'hA;
eeDat = 32'hAAAAAAAA;
eeDmh = 32'hAAAAAAAA;
eeMDst = 48'hAAAAAAAAAAAA;
eePli = 16'hAAAA;
isWrtResp = 1'h0;
lastResp = 45'h0AAAAAAAAAAA;
lastTag = 9'h0AA;
ptr = 4'hA;
uMAddr = 48'hAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 &&
(MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 ||
WILL_FIRE_RL_edpFsm_action_l243c16 ||
WILL_FIRE_RL_edpFsm_action_l244c16))
$display("Error: \"bsv/eth/EDCP.bsv\", line 237, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l237c14] and\n [RL_edpFsm_action_l238c14, RL_edpFsm_action_l239c14,\n RL_edpFsm_action_l241c16, RL_edpFsm_action_l243c16,\n RL_edpFsm_action_l244c16] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 &&
(MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 ||
WILL_FIRE_RL_edpFsm_action_l243c16 ||
WILL_FIRE_RL_edpFsm_action_l244c16))
$display("Error: \"bsv/eth/EDCP.bsv\", line 238, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l238c14] and\n [RL_edpFsm_action_l239c14, RL_edpFsm_action_l241c16,\n RL_edpFsm_action_l243c16, RL_edpFsm_action_l244c16] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 &&
(MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 ||
WILL_FIRE_RL_edpFsm_action_l243c16 ||
WILL_FIRE_RL_edpFsm_action_l244c16))
$display("Error: \"bsv/eth/EDCP.bsv\", line 239, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l239c14] and\n [RL_edpFsm_action_l241c16, RL_edpFsm_action_l243c16,\n RL_edpFsm_action_l244c16] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 &&
(WILL_FIRE_RL_edpFsm_action_l243c16 ||
WILL_FIRE_RL_edpFsm_action_l244c16))
$display("Error: \"bsv/eth/EDCP.bsv\", line 241, column 16: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l241c16] and\n [RL_edpFsm_action_l243c16, RL_edpFsm_action_l244c16] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l243c16 &&
WILL_FIRE_RL_edpFsm_action_l244c16)
$display("Error: \"bsv/eth/EDCP.bsv\", line 243, column 16: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l243c16] and\n [RL_edpFsm_action_l244c16] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 &&
(MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 ||
WILL_FIRE_RL_edpFsm_action_l243c16 ||
WILL_FIRE_RL_edpFsm_action_l244c16))
$display("Error: \"bsv/eth/EDCP.bsv\", line 236, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l236c14] and\n [RL_edpFsm_action_l237c14, RL_edpFsm_action_l238c14,\n RL_edpFsm_action_l239c14, RL_edpFsm_action_l241c16,\n RL_edpFsm_action_l243c16, RL_edpFsm_action_l244c16] ) fired in the same\n clock cycle.\n");
end
// synopsys translate_on
endmodule // mkEDCPAdapter
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_2_V
`define SKY130_FD_SC_HS__FILL_2_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fill_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hs__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fill_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hs__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_2_V
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: [email protected]
* Description: PPFIFO -> BRAM and BRM -> PPFIFO
* Attaches two PPFIFO to a block RAM.
*
* How to use:
*
* PPFIFO (Read to the BRAM) Interface Attached to read_*
* PPFIFO (Write from the BRAM) Interface Attached to write_*
*
* Changes:
*/
`define MEM_WAIT 2
module adapter_dpb_ppfifo #(
parameter MEM_DEPTH = 9,
parameter DATA_WIDTH = 32
)(
input clk,
input rst,
input i_ppfifo_2_mem_en,
input i_mem_2_ppfifo_stb,
input i_cancel_write_stb,
output reg [31:0] o_num_reads,
output o_idle,
//User Memory Interface
input i_bram_we,
input [MEM_DEPTH - 1: 0] i_bram_addr,
input [DATA_WIDTH - 1: 0] i_bram_din,
output [DATA_WIDTH - 1: 0] o_bram_dout,
output o_bram_valid,
//Ping Pong FIFO Interface
input ppfifo_clk,
input [1:0] i_write_ready,
output reg [1:0] o_write_activate,
input [23:0] i_write_size,
output reg o_write_stb,
output [DATA_WIDTH - 1:0] o_write_data,
input i_read_ready,
output reg o_read_activate,
input [23:0] i_read_size,
input [DATA_WIDTH - 1:0] i_read_data,
output reg o_read_stb
);
//local parameters
localparam MEM_SIZE = (2 ** MEM_DEPTH);
//States
localparam IDLE = 0;
localparam WRITE_SETUP = 1;
localparam WRITE = 2;
localparam READ = 3;
//registes/wires
wire w_pf_rd_en;
wire w_pf_wr_stb;
wire w_pf_cancel_stb;
reg [3:0] state;
reg [23:0] count;
reg r_we;
reg [MEM_DEPTH - 1: 0] r_addr;
reg [3:0] mem_wait_count;
reg [23:0] prev_mem_addr;
//submodules
cross_clock_enable p_en_r (
.rst (rst ),
.in_en (i_ppfifo_2_mem_en ),
.out_clk (ppfifo_clk ),
.out_en (w_pf_rd_en )
);
cross_clock_strobe p_stb_w (
.rst (rst ),
.in_clk (clk ),
.in_stb (i_mem_2_ppfifo_stb ),
.out_clk (ppfifo_clk ),
.out_stb (w_pf_wr_stb )
);
cross_clock_strobe p_stb_cncl_w (
.rst (rst ),
.in_clk (clk ),
.in_stb (i_cancel_write_stb ),
.out_clk (ppfifo_clk ),
.out_stb (w_pf_cancel_stb )
);
//Read/Write Data to a local buffer
dpb #(
.DATA_WIDTH (DATA_WIDTH ),
.ADDR_WIDTH (MEM_DEPTH )
) local_buffer (
.clka (clk ),
.wea (i_bram_we ),
.addra (i_bram_addr ),
.douta (o_bram_dout ),
.dina (i_bram_din ),
.clkb (ppfifo_clk ),
.web (r_we ),
.addrb (r_addr ),
.dinb (i_read_data ),
.doutb (o_write_data )
);
//assign o_write_data = 32'h01234567;
//asynchronous logic
assign o_idle = (state == IDLE);
//synchronous logic
assign o_bram_valid = ((prev_mem_addr == i_bram_addr) && (mem_wait_count == `MEM_WAIT));
always @ (posedge clk) begin
if (rst) begin
mem_wait_count <= `MEM_WAIT;
prev_mem_addr <= 0;
end
else begin
if (prev_mem_addr != i_bram_addr) begin
mem_wait_count <= 0;
prev_mem_addr <= i_bram_addr;
end
else begin
if (mem_wait_count < `MEM_WAIT) begin
mem_wait_count <= mem_wait_count + 1;
end
end
end
end
always @ (posedge ppfifo_clk) begin
o_read_stb <= 0;
o_write_stb <= 0;
r_we <= 0;
if (rst || w_pf_cancel_stb) begin
o_write_activate <= 0;
o_read_activate <= 0;
o_num_reads <= 0;
count <= 0;
r_addr <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
o_read_activate <= 0;
o_write_activate <= 0;
r_addr <= 0;
count <= 0;
if (w_pf_wr_stb) begin
//Load the memory data into the PPFIFO
state <= WRITE_SETUP;
end
else if (w_pf_rd_en) begin
if (i_read_ready) begin
o_read_activate <= 1;
state <= READ;
end
end
end
WRITE_SETUP: begin
if ((i_write_ready > 0) && (o_write_activate == 0)) begin
if (i_write_ready[0]) begin
o_write_activate[0] <= 1;
end
else begin
o_write_activate[1] <= 1;
end
state <= WRITE;
end
end
WRITE: begin
if (count < i_write_size) begin
r_addr <= r_addr + 1;
o_write_stb <= 1;
count <= count + 1;
end
else begin
o_write_activate <= 0;
state <= IDLE;
end
end
READ: begin
//Memory Interface
r_we <= 1;
if (r_we) begin
if (count < i_read_size) begin
o_read_stb <= 1;
count <= count + 1;
o_num_reads <= o_num_reads + 1;
end
else begin
//Done Reading
o_read_activate <= 0;
state <= IDLE;
r_we <= 0;
end
end
if (o_read_stb) begin
//Delay incrementing the address
r_addr <= r_addr + 1;
end
end
default: begin
//Shouldn't get here
state <= IDLE;
end
endcase
end
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module e203_soc_top(
// This clock should comes from the crystal pad generated high speed clock (16MHz)
input hfextclk,
output hfxoscen,// The signal to enable the crystal pad generated clock
// This clock should comes from the crystal pad generated low speed clock (32.768KHz)
input lfextclk,
output lfxoscen,// The signal to enable the crystal pad generated clock
// The JTAG TCK is input, need to be pull-up
input io_pads_jtag_TCK_i_ival,
// The JTAG TMS is input, need to be pull-up
input io_pads_jtag_TMS_i_ival,
// The JTAG TDI is input, need to be pull-up
input io_pads_jtag_TDI_i_ival,
// The JTAG TDO is output have enable
output io_pads_jtag_TDO_o_oval,
output io_pads_jtag_TDO_o_oe,
// The GPIO are all bidir pad have enables
input io_pads_gpio_0_i_ival,
output io_pads_gpio_0_o_oval,
output io_pads_gpio_0_o_oe,
output io_pads_gpio_0_o_ie,
output io_pads_gpio_0_o_pue,
output io_pads_gpio_0_o_ds,
input io_pads_gpio_1_i_ival,
output io_pads_gpio_1_o_oval,
output io_pads_gpio_1_o_oe,
output io_pads_gpio_1_o_ie,
output io_pads_gpio_1_o_pue,
output io_pads_gpio_1_o_ds,
input io_pads_gpio_2_i_ival,
output io_pads_gpio_2_o_oval,
output io_pads_gpio_2_o_oe,
output io_pads_gpio_2_o_ie,
output io_pads_gpio_2_o_pue,
output io_pads_gpio_2_o_ds,
input io_pads_gpio_3_i_ival,
output io_pads_gpio_3_o_oval,
output io_pads_gpio_3_o_oe,
output io_pads_gpio_3_o_ie,
output io_pads_gpio_3_o_pue,
output io_pads_gpio_3_o_ds,
input io_pads_gpio_4_i_ival,
output io_pads_gpio_4_o_oval,
output io_pads_gpio_4_o_oe,
output io_pads_gpio_4_o_ie,
output io_pads_gpio_4_o_pue,
output io_pads_gpio_4_o_ds,
input io_pads_gpio_5_i_ival,
output io_pads_gpio_5_o_oval,
output io_pads_gpio_5_o_oe,
output io_pads_gpio_5_o_ie,
output io_pads_gpio_5_o_pue,
output io_pads_gpio_5_o_ds,
input io_pads_gpio_6_i_ival,
output io_pads_gpio_6_o_oval,
output io_pads_gpio_6_o_oe,
output io_pads_gpio_6_o_ie,
output io_pads_gpio_6_o_pue,
output io_pads_gpio_6_o_ds,
input io_pads_gpio_7_i_ival,
output io_pads_gpio_7_o_oval,
output io_pads_gpio_7_o_oe,
output io_pads_gpio_7_o_ie,
output io_pads_gpio_7_o_pue,
output io_pads_gpio_7_o_ds,
input io_pads_gpio_8_i_ival,
output io_pads_gpio_8_o_oval,
output io_pads_gpio_8_o_oe,
output io_pads_gpio_8_o_ie,
output io_pads_gpio_8_o_pue,
output io_pads_gpio_8_o_ds,
input io_pads_gpio_9_i_ival,
output io_pads_gpio_9_o_oval,
output io_pads_gpio_9_o_oe,
output io_pads_gpio_9_o_ie,
output io_pads_gpio_9_o_pue,
output io_pads_gpio_9_o_ds,
input io_pads_gpio_10_i_ival,
output io_pads_gpio_10_o_oval,
output io_pads_gpio_10_o_oe,
output io_pads_gpio_10_o_ie,
output io_pads_gpio_10_o_pue,
output io_pads_gpio_10_o_ds,
input io_pads_gpio_11_i_ival,
output io_pads_gpio_11_o_oval,
output io_pads_gpio_11_o_oe,
output io_pads_gpio_11_o_ie,
output io_pads_gpio_11_o_pue,
output io_pads_gpio_11_o_ds,
input io_pads_gpio_12_i_ival,
output io_pads_gpio_12_o_oval,
output io_pads_gpio_12_o_oe,
output io_pads_gpio_12_o_ie,
output io_pads_gpio_12_o_pue,
output io_pads_gpio_12_o_ds,
input io_pads_gpio_13_i_ival,
output io_pads_gpio_13_o_oval,
output io_pads_gpio_13_o_oe,
output io_pads_gpio_13_o_ie,
output io_pads_gpio_13_o_pue,
output io_pads_gpio_13_o_ds,
input io_pads_gpio_14_i_ival,
output io_pads_gpio_14_o_oval,
output io_pads_gpio_14_o_oe,
output io_pads_gpio_14_o_ie,
output io_pads_gpio_14_o_pue,
output io_pads_gpio_14_o_ds,
input io_pads_gpio_15_i_ival,
output io_pads_gpio_15_o_oval,
output io_pads_gpio_15_o_oe,
output io_pads_gpio_15_o_ie,
output io_pads_gpio_15_o_pue,
output io_pads_gpio_15_o_ds,
input io_pads_gpio_16_i_ival,
output io_pads_gpio_16_o_oval,
output io_pads_gpio_16_o_oe,
output io_pads_gpio_16_o_ie,
output io_pads_gpio_16_o_pue,
output io_pads_gpio_16_o_ds,
input io_pads_gpio_17_i_ival,
output io_pads_gpio_17_o_oval,
output io_pads_gpio_17_o_oe,
output io_pads_gpio_17_o_ie,
output io_pads_gpio_17_o_pue,
output io_pads_gpio_17_o_ds,
input io_pads_gpio_18_i_ival,
output io_pads_gpio_18_o_oval,
output io_pads_gpio_18_o_oe,
output io_pads_gpio_18_o_ie,
output io_pads_gpio_18_o_pue,
output io_pads_gpio_18_o_ds,
input io_pads_gpio_19_i_ival,
output io_pads_gpio_19_o_oval,
output io_pads_gpio_19_o_oe,
output io_pads_gpio_19_o_ie,
output io_pads_gpio_19_o_pue,
output io_pads_gpio_19_o_ds,
input io_pads_gpio_20_i_ival,
output io_pads_gpio_20_o_oval,
output io_pads_gpio_20_o_oe,
output io_pads_gpio_20_o_ie,
output io_pads_gpio_20_o_pue,
output io_pads_gpio_20_o_ds,
input io_pads_gpio_21_i_ival,
output io_pads_gpio_21_o_oval,
output io_pads_gpio_21_o_oe,
output io_pads_gpio_21_o_ie,
output io_pads_gpio_21_o_pue,
output io_pads_gpio_21_o_ds,
input io_pads_gpio_22_i_ival,
output io_pads_gpio_22_o_oval,
output io_pads_gpio_22_o_oe,
output io_pads_gpio_22_o_ie,
output io_pads_gpio_22_o_pue,
output io_pads_gpio_22_o_ds,
input io_pads_gpio_23_i_ival,
output io_pads_gpio_23_o_oval,
output io_pads_gpio_23_o_oe,
output io_pads_gpio_23_o_ie,
output io_pads_gpio_23_o_pue,
output io_pads_gpio_23_o_ds,
input io_pads_gpio_24_i_ival,
output io_pads_gpio_24_o_oval,
output io_pads_gpio_24_o_oe,
output io_pads_gpio_24_o_ie,
output io_pads_gpio_24_o_pue,
output io_pads_gpio_24_o_ds,
input io_pads_gpio_25_i_ival,
output io_pads_gpio_25_o_oval,
output io_pads_gpio_25_o_oe,
output io_pads_gpio_25_o_ie,
output io_pads_gpio_25_o_pue,
output io_pads_gpio_25_o_ds,
input io_pads_gpio_26_i_ival,
output io_pads_gpio_26_o_oval,
output io_pads_gpio_26_o_oe,
output io_pads_gpio_26_o_ie,
output io_pads_gpio_26_o_pue,
output io_pads_gpio_26_o_ds,
input io_pads_gpio_27_i_ival,
output io_pads_gpio_27_o_oval,
output io_pads_gpio_27_o_oe,
output io_pads_gpio_27_o_ie,
output io_pads_gpio_27_o_pue,
output io_pads_gpio_27_o_ds,
input io_pads_gpio_28_i_ival,
output io_pads_gpio_28_o_oval,
output io_pads_gpio_28_o_oe,
output io_pads_gpio_28_o_ie,
output io_pads_gpio_28_o_pue,
output io_pads_gpio_28_o_ds,
input io_pads_gpio_29_i_ival,
output io_pads_gpio_29_o_oval,
output io_pads_gpio_29_o_oe,
output io_pads_gpio_29_o_ie,
output io_pads_gpio_29_o_pue,
output io_pads_gpio_29_o_ds,
input io_pads_gpio_30_i_ival,
output io_pads_gpio_30_o_oval,
output io_pads_gpio_30_o_oe,
output io_pads_gpio_30_o_ie,
output io_pads_gpio_30_o_pue,
output io_pads_gpio_30_o_ds,
input io_pads_gpio_31_i_ival,
output io_pads_gpio_31_o_oval,
output io_pads_gpio_31_o_oe,
output io_pads_gpio_31_o_ie,
output io_pads_gpio_31_o_pue,
output io_pads_gpio_31_o_ds,
//QSPI SCK and CS is output without enable
output io_pads_qspi_sck_o_oval,
output io_pads_qspi_cs_0_o_oval,
//QSPI DQ is bidir I/O with enable, and need pull-up enable
input io_pads_qspi_dq_0_i_ival,
output io_pads_qspi_dq_0_o_oval,
output io_pads_qspi_dq_0_o_oe,
output io_pads_qspi_dq_0_o_ie,
output io_pads_qspi_dq_0_o_pue,
output io_pads_qspi_dq_0_o_ds,
input io_pads_qspi_dq_1_i_ival,
output io_pads_qspi_dq_1_o_oval,
output io_pads_qspi_dq_1_o_oe,
output io_pads_qspi_dq_1_o_ie,
output io_pads_qspi_dq_1_o_pue,
output io_pads_qspi_dq_1_o_ds,
input io_pads_qspi_dq_2_i_ival,
output io_pads_qspi_dq_2_o_oval,
output io_pads_qspi_dq_2_o_oe,
output io_pads_qspi_dq_2_o_ie,
output io_pads_qspi_dq_2_o_pue,
output io_pads_qspi_dq_2_o_ds,
input io_pads_qspi_dq_3_i_ival,
output io_pads_qspi_dq_3_o_oval,
output io_pads_qspi_dq_3_o_oe,
output io_pads_qspi_dq_3_o_ie,
output io_pads_qspi_dq_3_o_pue,
output io_pads_qspi_dq_3_o_ds,
// Erst is input need to be pull-up by default
input io_pads_aon_erst_n_i_ival,
// dbgmode are inputs need to be pull-up by default
input io_pads_dbgmode0_n_i_ival,
input io_pads_dbgmode1_n_i_ival,
input io_pads_dbgmode2_n_i_ival,
// BootRom is input need to be pull-up by default
input io_pads_bootrom_n_i_ival,
// dwakeup is input need to be pull-up by default
input io_pads_aon_pmu_dwakeup_n_i_ival,
// PMU output is just output without enable
output io_pads_aon_pmu_padrst_o_oval,
output io_pads_aon_pmu_vddpaden_o_oval
);
wire sysper_icb_cmd_valid;
wire sysper_icb_cmd_ready;
wire sysfio_icb_cmd_valid;
wire sysfio_icb_cmd_ready;
wire sysmem_icb_cmd_valid;
wire sysmem_icb_cmd_ready;
e203_subsys_top u_e203_subsys_top(
.core_mhartid (1'b0),
`ifdef E203_HAS_ITCM_EXTITF //{
.ext2itcm_icb_cmd_valid (1'b0),
.ext2itcm_icb_cmd_ready (),
.ext2itcm_icb_cmd_addr (`E203_ITCM_ADDR_WIDTH'b0 ),
.ext2itcm_icb_cmd_read (1'b0 ),
.ext2itcm_icb_cmd_wdata (32'b0),
.ext2itcm_icb_cmd_wmask (4'b0),
.ext2itcm_icb_rsp_valid (),
.ext2itcm_icb_rsp_ready (1'b0),
.ext2itcm_icb_rsp_err (),
.ext2itcm_icb_rsp_rdata (),
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
.ext2dtcm_icb_cmd_valid (1'b0),
.ext2dtcm_icb_cmd_ready (),
.ext2dtcm_icb_cmd_addr (`E203_DTCM_ADDR_WIDTH'b0 ),
.ext2dtcm_icb_cmd_read (1'b0 ),
.ext2dtcm_icb_cmd_wdata (32'b0),
.ext2dtcm_icb_cmd_wmask (4'b0),
.ext2dtcm_icb_rsp_valid (),
.ext2dtcm_icb_rsp_ready (1'b0),
.ext2dtcm_icb_rsp_err (),
.ext2dtcm_icb_rsp_rdata (),
`endif//}
.sysper_icb_cmd_valid (sysper_icb_cmd_valid),
.sysper_icb_cmd_ready (sysper_icb_cmd_ready),
.sysper_icb_cmd_read (),
.sysper_icb_cmd_addr (),
.sysper_icb_cmd_wdata (),
.sysper_icb_cmd_wmask (),
.sysper_icb_rsp_valid (sysper_icb_cmd_valid),
.sysper_icb_rsp_ready (sysper_icb_cmd_ready),
.sysper_icb_rsp_err (1'b0 ),
.sysper_icb_rsp_rdata (32'b0),
.sysfio_icb_cmd_valid(sysfio_icb_cmd_valid),
.sysfio_icb_cmd_ready(sysfio_icb_cmd_ready),
.sysfio_icb_cmd_read (),
.sysfio_icb_cmd_addr (),
.sysfio_icb_cmd_wdata(),
.sysfio_icb_cmd_wmask(),
.sysfio_icb_rsp_valid(sysfio_icb_cmd_valid),
.sysfio_icb_rsp_ready(sysfio_icb_cmd_ready),
.sysfio_icb_rsp_err (1'b0 ),
.sysfio_icb_rsp_rdata(32'b0),
.sysmem_icb_cmd_valid(sysmem_icb_cmd_valid),
.sysmem_icb_cmd_ready(sysmem_icb_cmd_ready),
.sysmem_icb_cmd_read (),
.sysmem_icb_cmd_addr (),
.sysmem_icb_cmd_wdata(),
.sysmem_icb_cmd_wmask(),
.sysmem_icb_rsp_valid(sysmem_icb_cmd_valid),
.sysmem_icb_rsp_ready(sysmem_icb_cmd_ready),
.sysmem_icb_rsp_err (1'b0 ),
.sysmem_icb_rsp_rdata(32'b0),
.io_pads_jtag_TCK_i_ival (io_pads_jtag_TCK_i_ival ),
.io_pads_jtag_TCK_o_oval (),
.io_pads_jtag_TCK_o_oe (),
.io_pads_jtag_TCK_o_ie (),
.io_pads_jtag_TCK_o_pue (),
.io_pads_jtag_TCK_o_ds (),
.io_pads_jtag_TMS_i_ival (io_pads_jtag_TMS_i_ival ),
.io_pads_jtag_TMS_o_oval (),
.io_pads_jtag_TMS_o_oe (),
.io_pads_jtag_TMS_o_ie (),
.io_pads_jtag_TMS_o_pue (),
.io_pads_jtag_TMS_o_ds (),
.io_pads_jtag_TDI_i_ival (io_pads_jtag_TDI_i_ival ),
.io_pads_jtag_TDI_o_oval (),
.io_pads_jtag_TDI_o_oe (),
.io_pads_jtag_TDI_o_ie (),
.io_pads_jtag_TDI_o_pue (),
.io_pads_jtag_TDI_o_ds (),
.io_pads_jtag_TDO_i_ival (1'b1 ),
.io_pads_jtag_TDO_o_oval (io_pads_jtag_TDO_o_oval ),
.io_pads_jtag_TDO_o_oe (io_pads_jtag_TDO_o_oe ),
.io_pads_jtag_TDO_o_ie (),
.io_pads_jtag_TDO_o_pue (),
.io_pads_jtag_TDO_o_ds (),
.io_pads_jtag_TRST_n_i_ival (1'b1 ),
.io_pads_jtag_TRST_n_o_oval (),
.io_pads_jtag_TRST_n_o_oe (),
.io_pads_jtag_TRST_n_o_ie (),
.io_pads_jtag_TRST_n_o_pue (),
.io_pads_jtag_TRST_n_o_ds (),
.test_mode(1'b0),
.test_iso_override(1'b0),
.io_pads_gpio_0_i_ival (io_pads_gpio_0_i_ival & io_pads_gpio_0_o_ie),
.io_pads_gpio_0_o_oval (io_pads_gpio_0_o_oval),
.io_pads_gpio_0_o_oe (io_pads_gpio_0_o_oe),
.io_pads_gpio_0_o_ie (io_pads_gpio_0_o_ie),
.io_pads_gpio_0_o_pue (io_pads_gpio_0_o_pue),
.io_pads_gpio_0_o_ds (io_pads_gpio_0_o_ds),
.io_pads_gpio_1_i_ival (io_pads_gpio_1_i_ival & io_pads_gpio_1_o_ie),
.io_pads_gpio_1_o_oval (io_pads_gpio_1_o_oval),
.io_pads_gpio_1_o_oe (io_pads_gpio_1_o_oe),
.io_pads_gpio_1_o_ie (io_pads_gpio_1_o_ie),
.io_pads_gpio_1_o_pue (io_pads_gpio_1_o_pue),
.io_pads_gpio_1_o_ds (io_pads_gpio_1_o_ds),
.io_pads_gpio_2_i_ival (io_pads_gpio_2_i_ival & io_pads_gpio_2_o_ie),
.io_pads_gpio_2_o_oval (io_pads_gpio_2_o_oval),
.io_pads_gpio_2_o_oe (io_pads_gpio_2_o_oe),
.io_pads_gpio_2_o_ie (io_pads_gpio_2_o_ie),
.io_pads_gpio_2_o_pue (io_pads_gpio_2_o_pue),
.io_pads_gpio_2_o_ds (io_pads_gpio_2_o_ds),
.io_pads_gpio_3_i_ival (io_pads_gpio_3_i_ival & io_pads_gpio_3_o_ie),
.io_pads_gpio_3_o_oval (io_pads_gpio_3_o_oval),
.io_pads_gpio_3_o_oe (io_pads_gpio_3_o_oe),
.io_pads_gpio_3_o_ie (io_pads_gpio_3_o_ie),
.io_pads_gpio_3_o_pue (io_pads_gpio_3_o_pue),
.io_pads_gpio_3_o_ds (io_pads_gpio_3_o_ds),
.io_pads_gpio_4_i_ival (io_pads_gpio_4_i_ival & io_pads_gpio_4_o_ie),
.io_pads_gpio_4_o_oval (io_pads_gpio_4_o_oval),
.io_pads_gpio_4_o_oe (io_pads_gpio_4_o_oe),
.io_pads_gpio_4_o_ie (io_pads_gpio_4_o_ie),
.io_pads_gpio_4_o_pue (io_pads_gpio_4_o_pue),
.io_pads_gpio_4_o_ds (io_pads_gpio_4_o_ds),
.io_pads_gpio_5_i_ival (io_pads_gpio_5_i_ival & io_pads_gpio_5_o_ie),
.io_pads_gpio_5_o_oval (io_pads_gpio_5_o_oval),
.io_pads_gpio_5_o_oe (io_pads_gpio_5_o_oe),
.io_pads_gpio_5_o_ie (io_pads_gpio_5_o_ie),
.io_pads_gpio_5_o_pue (io_pads_gpio_5_o_pue),
.io_pads_gpio_5_o_ds (io_pads_gpio_5_o_ds),
.io_pads_gpio_6_i_ival (io_pads_gpio_6_i_ival & io_pads_gpio_6_o_ie),
.io_pads_gpio_6_o_oval (io_pads_gpio_6_o_oval),
.io_pads_gpio_6_o_oe (io_pads_gpio_6_o_oe),
.io_pads_gpio_6_o_ie (io_pads_gpio_6_o_ie),
.io_pads_gpio_6_o_pue (io_pads_gpio_6_o_pue),
.io_pads_gpio_6_o_ds (io_pads_gpio_6_o_ds),
.io_pads_gpio_7_i_ival (io_pads_gpio_7_i_ival & io_pads_gpio_7_o_ie),
.io_pads_gpio_7_o_oval (io_pads_gpio_7_o_oval),
.io_pads_gpio_7_o_oe (io_pads_gpio_7_o_oe),
.io_pads_gpio_7_o_ie (io_pads_gpio_7_o_ie),
.io_pads_gpio_7_o_pue (io_pads_gpio_7_o_pue),
.io_pads_gpio_7_o_ds (io_pads_gpio_7_o_ds),
.io_pads_gpio_8_i_ival (io_pads_gpio_8_i_ival & io_pads_gpio_8_o_ie),
.io_pads_gpio_8_o_oval (io_pads_gpio_8_o_oval),
.io_pads_gpio_8_o_oe (io_pads_gpio_8_o_oe),
.io_pads_gpio_8_o_ie (io_pads_gpio_8_o_ie),
.io_pads_gpio_8_o_pue (io_pads_gpio_8_o_pue),
.io_pads_gpio_8_o_ds (io_pads_gpio_8_o_ds),
.io_pads_gpio_9_i_ival (io_pads_gpio_9_i_ival & io_pads_gpio_9_o_ie),
.io_pads_gpio_9_o_oval (io_pads_gpio_9_o_oval),
.io_pads_gpio_9_o_oe (io_pads_gpio_9_o_oe),
.io_pads_gpio_9_o_ie (io_pads_gpio_9_o_ie),
.io_pads_gpio_9_o_pue (io_pads_gpio_9_o_pue),
.io_pads_gpio_9_o_ds (io_pads_gpio_9_o_ds),
.io_pads_gpio_10_i_ival (io_pads_gpio_10_i_ival & io_pads_gpio_10_o_ie),
.io_pads_gpio_10_o_oval (io_pads_gpio_10_o_oval),
.io_pads_gpio_10_o_oe (io_pads_gpio_10_o_oe),
.io_pads_gpio_10_o_ie (io_pads_gpio_10_o_ie),
.io_pads_gpio_10_o_pue (io_pads_gpio_10_o_pue),
.io_pads_gpio_10_o_ds (io_pads_gpio_10_o_ds),
.io_pads_gpio_11_i_ival (io_pads_gpio_11_i_ival & io_pads_gpio_11_o_ie),
.io_pads_gpio_11_o_oval (io_pads_gpio_11_o_oval),
.io_pads_gpio_11_o_oe (io_pads_gpio_11_o_oe),
.io_pads_gpio_11_o_ie (io_pads_gpio_11_o_ie),
.io_pads_gpio_11_o_pue (io_pads_gpio_11_o_pue),
.io_pads_gpio_11_o_ds (io_pads_gpio_11_o_ds),
.io_pads_gpio_12_i_ival (io_pads_gpio_12_i_ival & io_pads_gpio_12_o_ie),
.io_pads_gpio_12_o_oval (io_pads_gpio_12_o_oval),
.io_pads_gpio_12_o_oe (io_pads_gpio_12_o_oe),
.io_pads_gpio_12_o_ie (io_pads_gpio_12_o_ie),
.io_pads_gpio_12_o_pue (io_pads_gpio_12_o_pue),
.io_pads_gpio_12_o_ds (io_pads_gpio_12_o_ds),
.io_pads_gpio_13_i_ival (io_pads_gpio_13_i_ival & io_pads_gpio_13_o_ie),
.io_pads_gpio_13_o_oval (io_pads_gpio_13_o_oval),
.io_pads_gpio_13_o_oe (io_pads_gpio_13_o_oe),
.io_pads_gpio_13_o_ie (io_pads_gpio_13_o_ie),
.io_pads_gpio_13_o_pue (io_pads_gpio_13_o_pue),
.io_pads_gpio_13_o_ds (io_pads_gpio_13_o_ds),
.io_pads_gpio_14_i_ival (io_pads_gpio_14_i_ival & io_pads_gpio_14_o_ie),
.io_pads_gpio_14_o_oval (io_pads_gpio_14_o_oval),
.io_pads_gpio_14_o_oe (io_pads_gpio_14_o_oe),
.io_pads_gpio_14_o_ie (io_pads_gpio_14_o_ie),
.io_pads_gpio_14_o_pue (io_pads_gpio_14_o_pue),
.io_pads_gpio_14_o_ds (io_pads_gpio_14_o_ds),
.io_pads_gpio_15_i_ival (io_pads_gpio_15_i_ival & io_pads_gpio_15_o_ie),
.io_pads_gpio_15_o_oval (io_pads_gpio_15_o_oval),
.io_pads_gpio_15_o_oe (io_pads_gpio_15_o_oe),
.io_pads_gpio_15_o_ie (io_pads_gpio_15_o_ie),
.io_pads_gpio_15_o_pue (io_pads_gpio_15_o_pue),
.io_pads_gpio_15_o_ds (io_pads_gpio_15_o_ds),
.io_pads_gpio_16_i_ival (io_pads_gpio_16_i_ival & io_pads_gpio_16_o_ie),
.io_pads_gpio_16_o_oval (io_pads_gpio_16_o_oval),
.io_pads_gpio_16_o_oe (io_pads_gpio_16_o_oe),
.io_pads_gpio_16_o_ie (io_pads_gpio_16_o_ie),
.io_pads_gpio_16_o_pue (io_pads_gpio_16_o_pue),
.io_pads_gpio_16_o_ds (io_pads_gpio_16_o_ds),
.io_pads_gpio_17_i_ival (io_pads_gpio_17_i_ival & io_pads_gpio_17_o_ie),
.io_pads_gpio_17_o_oval (io_pads_gpio_17_o_oval),
.io_pads_gpio_17_o_oe (io_pads_gpio_17_o_oe),
.io_pads_gpio_17_o_ie (io_pads_gpio_17_o_ie),
.io_pads_gpio_17_o_pue (io_pads_gpio_17_o_pue),
.io_pads_gpio_17_o_ds (io_pads_gpio_17_o_ds),
.io_pads_gpio_18_i_ival (io_pads_gpio_18_i_ival & io_pads_gpio_18_o_ie),
.io_pads_gpio_18_o_oval (io_pads_gpio_18_o_oval),
.io_pads_gpio_18_o_oe (io_pads_gpio_18_o_oe),
.io_pads_gpio_18_o_ie (io_pads_gpio_18_o_ie),
.io_pads_gpio_18_o_pue (io_pads_gpio_18_o_pue),
.io_pads_gpio_18_o_ds (io_pads_gpio_18_o_ds),
.io_pads_gpio_19_i_ival (io_pads_gpio_19_i_ival & io_pads_gpio_19_o_ie),
.io_pads_gpio_19_o_oval (io_pads_gpio_19_o_oval),
.io_pads_gpio_19_o_oe (io_pads_gpio_19_o_oe),
.io_pads_gpio_19_o_ie (io_pads_gpio_19_o_ie),
.io_pads_gpio_19_o_pue (io_pads_gpio_19_o_pue),
.io_pads_gpio_19_o_ds (io_pads_gpio_19_o_ds),
.io_pads_gpio_20_i_ival (io_pads_gpio_20_i_ival & io_pads_gpio_20_o_ie),
.io_pads_gpio_20_o_oval (io_pads_gpio_20_o_oval),
.io_pads_gpio_20_o_oe (io_pads_gpio_20_o_oe),
.io_pads_gpio_20_o_ie (io_pads_gpio_20_o_ie),
.io_pads_gpio_20_o_pue (io_pads_gpio_20_o_pue),
.io_pads_gpio_20_o_ds (io_pads_gpio_20_o_ds),
.io_pads_gpio_21_i_ival (io_pads_gpio_21_i_ival & io_pads_gpio_21_o_ie),
.io_pads_gpio_21_o_oval (io_pads_gpio_21_o_oval),
.io_pads_gpio_21_o_oe (io_pads_gpio_21_o_oe),
.io_pads_gpio_21_o_ie (io_pads_gpio_21_o_ie),
.io_pads_gpio_21_o_pue (io_pads_gpio_21_o_pue),
.io_pads_gpio_21_o_ds (io_pads_gpio_21_o_ds),
.io_pads_gpio_22_i_ival (io_pads_gpio_22_i_ival & io_pads_gpio_22_o_ie),
.io_pads_gpio_22_o_oval (io_pads_gpio_22_o_oval),
.io_pads_gpio_22_o_oe (io_pads_gpio_22_o_oe),
.io_pads_gpio_22_o_ie (io_pads_gpio_22_o_ie),
.io_pads_gpio_22_o_pue (io_pads_gpio_22_o_pue),
.io_pads_gpio_22_o_ds (io_pads_gpio_22_o_ds),
.io_pads_gpio_23_i_ival (io_pads_gpio_23_i_ival & io_pads_gpio_23_o_ie),
.io_pads_gpio_23_o_oval (io_pads_gpio_23_o_oval),
.io_pads_gpio_23_o_oe (io_pads_gpio_23_o_oe),
.io_pads_gpio_23_o_ie (io_pads_gpio_23_o_ie),
.io_pads_gpio_23_o_pue (io_pads_gpio_23_o_pue),
.io_pads_gpio_23_o_ds (io_pads_gpio_23_o_ds),
.io_pads_gpio_24_i_ival (io_pads_gpio_24_i_ival & io_pads_gpio_24_o_ie),
.io_pads_gpio_24_o_oval (io_pads_gpio_24_o_oval),
.io_pads_gpio_24_o_oe (io_pads_gpio_24_o_oe),
.io_pads_gpio_24_o_ie (io_pads_gpio_24_o_ie),
.io_pads_gpio_24_o_pue (io_pads_gpio_24_o_pue),
.io_pads_gpio_24_o_ds (io_pads_gpio_24_o_ds),
.io_pads_gpio_25_i_ival (io_pads_gpio_25_i_ival & io_pads_gpio_25_o_ie),
.io_pads_gpio_25_o_oval (io_pads_gpio_25_o_oval),
.io_pads_gpio_25_o_oe (io_pads_gpio_25_o_oe),
.io_pads_gpio_25_o_ie (io_pads_gpio_25_o_ie),
.io_pads_gpio_25_o_pue (io_pads_gpio_25_o_pue),
.io_pads_gpio_25_o_ds (io_pads_gpio_25_o_ds),
.io_pads_gpio_26_i_ival (io_pads_gpio_26_i_ival & io_pads_gpio_26_o_ie),
.io_pads_gpio_26_o_oval (io_pads_gpio_26_o_oval),
.io_pads_gpio_26_o_oe (io_pads_gpio_26_o_oe),
.io_pads_gpio_26_o_ie (io_pads_gpio_26_o_ie),
.io_pads_gpio_26_o_pue (io_pads_gpio_26_o_pue),
.io_pads_gpio_26_o_ds (io_pads_gpio_26_o_ds),
.io_pads_gpio_27_i_ival (io_pads_gpio_27_i_ival & io_pads_gpio_27_o_ie),
.io_pads_gpio_27_o_oval (io_pads_gpio_27_o_oval),
.io_pads_gpio_27_o_oe (io_pads_gpio_27_o_oe),
.io_pads_gpio_27_o_ie (io_pads_gpio_27_o_ie),
.io_pads_gpio_27_o_pue (io_pads_gpio_27_o_pue),
.io_pads_gpio_27_o_ds (io_pads_gpio_27_o_ds),
.io_pads_gpio_28_i_ival (io_pads_gpio_28_i_ival & io_pads_gpio_28_o_ie),
.io_pads_gpio_28_o_oval (io_pads_gpio_28_o_oval),
.io_pads_gpio_28_o_oe (io_pads_gpio_28_o_oe),
.io_pads_gpio_28_o_ie (io_pads_gpio_28_o_ie),
.io_pads_gpio_28_o_pue (io_pads_gpio_28_o_pue),
.io_pads_gpio_28_o_ds (io_pads_gpio_28_o_ds),
.io_pads_gpio_29_i_ival (io_pads_gpio_29_i_ival & io_pads_gpio_29_o_ie),
.io_pads_gpio_29_o_oval (io_pads_gpio_29_o_oval),
.io_pads_gpio_29_o_oe (io_pads_gpio_29_o_oe),
.io_pads_gpio_29_o_ie (io_pads_gpio_29_o_ie),
.io_pads_gpio_29_o_pue (io_pads_gpio_29_o_pue),
.io_pads_gpio_29_o_ds (io_pads_gpio_29_o_ds),
.io_pads_gpio_30_i_ival (io_pads_gpio_30_i_ival & io_pads_gpio_30_o_ie),
.io_pads_gpio_30_o_oval (io_pads_gpio_30_o_oval),
.io_pads_gpio_30_o_oe (io_pads_gpio_30_o_oe),
.io_pads_gpio_30_o_ie (io_pads_gpio_30_o_ie),
.io_pads_gpio_30_o_pue (io_pads_gpio_30_o_pue),
.io_pads_gpio_30_o_ds (io_pads_gpio_30_o_ds),
.io_pads_gpio_31_i_ival (io_pads_gpio_31_i_ival & io_pads_gpio_31_o_ie),
.io_pads_gpio_31_o_oval (io_pads_gpio_31_o_oval),
.io_pads_gpio_31_o_oe (io_pads_gpio_31_o_oe),
.io_pads_gpio_31_o_ie (io_pads_gpio_31_o_ie),
.io_pads_gpio_31_o_pue (io_pads_gpio_31_o_pue),
.io_pads_gpio_31_o_ds (io_pads_gpio_31_o_ds),
.io_pads_qspi_sck_i_ival (1'b1 ),
.io_pads_qspi_sck_o_oval (io_pads_qspi_sck_o_oval ),
.io_pads_qspi_sck_o_oe (),
.io_pads_qspi_sck_o_ie (),
.io_pads_qspi_sck_o_pue (),
.io_pads_qspi_sck_o_ds (),
.io_pads_qspi_dq_0_i_ival (io_pads_qspi_dq_0_i_ival & io_pads_qspi_dq_0_o_ie),
.io_pads_qspi_dq_0_o_oval (io_pads_qspi_dq_0_o_oval),
.io_pads_qspi_dq_0_o_oe (io_pads_qspi_dq_0_o_oe ),
.io_pads_qspi_dq_0_o_ie (io_pads_qspi_dq_0_o_ie ),
.io_pads_qspi_dq_0_o_pue (io_pads_qspi_dq_0_o_pue ),
.io_pads_qspi_dq_0_o_ds (io_pads_qspi_dq_0_o_ds ),
.io_pads_qspi_dq_1_i_ival (io_pads_qspi_dq_1_i_ival & io_pads_qspi_dq_1_o_ie),
.io_pads_qspi_dq_1_o_oval (io_pads_qspi_dq_1_o_oval),
.io_pads_qspi_dq_1_o_oe (io_pads_qspi_dq_1_o_oe ),
.io_pads_qspi_dq_1_o_ie (io_pads_qspi_dq_1_o_ie ),
.io_pads_qspi_dq_1_o_pue (io_pads_qspi_dq_1_o_pue ),
.io_pads_qspi_dq_1_o_ds (io_pads_qspi_dq_1_o_ds ),
.io_pads_qspi_dq_2_i_ival (io_pads_qspi_dq_2_i_ival & io_pads_qspi_dq_2_o_ie),
.io_pads_qspi_dq_2_o_oval (io_pads_qspi_dq_2_o_oval),
.io_pads_qspi_dq_2_o_oe (io_pads_qspi_dq_2_o_oe ),
.io_pads_qspi_dq_2_o_ie (io_pads_qspi_dq_2_o_ie ),
.io_pads_qspi_dq_2_o_pue (io_pads_qspi_dq_2_o_pue ),
.io_pads_qspi_dq_2_o_ds (io_pads_qspi_dq_2_o_ds ),
.io_pads_qspi_dq_3_i_ival (io_pads_qspi_dq_3_i_ival & io_pads_qspi_dq_3_o_ie),
.io_pads_qspi_dq_3_o_oval (io_pads_qspi_dq_3_o_oval),
.io_pads_qspi_dq_3_o_oe (io_pads_qspi_dq_3_o_oe ),
.io_pads_qspi_dq_3_o_ie (io_pads_qspi_dq_3_o_ie ),
.io_pads_qspi_dq_3_o_pue (io_pads_qspi_dq_3_o_pue ),
.io_pads_qspi_dq_3_o_ds (io_pads_qspi_dq_3_o_ds ),
.io_pads_qspi_cs_0_i_ival (1'b1),
.io_pads_qspi_cs_0_o_oval (io_pads_qspi_cs_0_o_oval),
.io_pads_qspi_cs_0_o_oe (),
.io_pads_qspi_cs_0_o_ie (),
.io_pads_qspi_cs_0_o_pue (),
.io_pads_qspi_cs_0_o_ds (),
.hfextclk (hfextclk),
.hfxoscen (hfxoscen),
.lfextclk (lfextclk),
.lfxoscen (lfxoscen),
.io_pads_aon_erst_n_i_ival (io_pads_aon_erst_n_i_ival ),
.io_pads_aon_erst_n_o_oval (),
.io_pads_aon_erst_n_o_oe (),
.io_pads_aon_erst_n_o_ie (),
.io_pads_aon_erst_n_o_pue (),
.io_pads_aon_erst_n_o_ds (),
.io_pads_aon_pmu_dwakeup_n_i_ival (io_pads_aon_pmu_dwakeup_n_i_ival),
.io_pads_aon_pmu_dwakeup_n_o_oval (),
.io_pads_aon_pmu_dwakeup_n_o_oe (),
.io_pads_aon_pmu_dwakeup_n_o_ie (),
.io_pads_aon_pmu_dwakeup_n_o_pue (),
.io_pads_aon_pmu_dwakeup_n_o_ds (),
.io_pads_aon_pmu_vddpaden_i_ival (1'b1 ),
.io_pads_aon_pmu_vddpaden_o_oval (io_pads_aon_pmu_vddpaden_o_oval ),
.io_pads_aon_pmu_vddpaden_o_oe (),
.io_pads_aon_pmu_vddpaden_o_ie (),
.io_pads_aon_pmu_vddpaden_o_pue (),
.io_pads_aon_pmu_vddpaden_o_ds (),
.io_pads_aon_pmu_padrst_i_ival (1'b1 ),
.io_pads_aon_pmu_padrst_o_oval (io_pads_aon_pmu_padrst_o_oval ),
.io_pads_aon_pmu_padrst_o_oe (),
.io_pads_aon_pmu_padrst_o_ie (),
.io_pads_aon_pmu_padrst_o_pue (),
.io_pads_aon_pmu_padrst_o_ds (),
.io_pads_bootrom_n_i_ival (io_pads_bootrom_n_i_ival),
.io_pads_bootrom_n_o_oval (),
.io_pads_bootrom_n_o_oe (),
.io_pads_bootrom_n_o_ie (),
.io_pads_bootrom_n_o_pue (),
.io_pads_bootrom_n_o_ds (),
.io_pads_dbgmode0_n_i_ival (io_pads_dbgmode0_n_i_ival),
.io_pads_dbgmode1_n_i_ival (io_pads_dbgmode1_n_i_ival),
.io_pads_dbgmode2_n_i_ival (io_pads_dbgmode2_n_i_ival)
);
endmodule
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